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#include <bits/stdc++.h> using namespace std; bool debug = 0; int n, m, k; int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; string direc = RDLU ; long long ln, lk, lm; void etp(bool f = 0) { puts(f ? Yes : No ); exit(0); } void addmod(int &x, int y, int mod = 1000000007) { assert(y >= 0); x += y; if (x >= mod) x -= mod; assert(x >= 0 && x < mod); } void et() { puts( -1 ); exit(0); } long long fastPow(long long x, long long y, int mod = 1000000007) { long long ans = 1; while (y > 0) { if (y & 1) ans = (x * ans) % mod; x = x * x % mod; y >>= 1; } return ans; } long long gcd1(long long x, long long y) { long long z = y; while (x % y != 0) { z = x % y; x = y; y = z; } return z; } int fac[105], inv[105]; void initfac(int n) { fac[0] = inv[0] = 1; for (int(i) = 1; (i) <= (int)(n); (i)++) { fac[i] = (long long)fac[i - 1] * i % 1000000007; inv[i] = fastPow(fac[i], 1000000007 - 2); } } int C(int n, int m) { if (n < m) return 0; return (long long)fac[n] * inv[m] % 1000000007 * inv[n - m] % 1000000007; } int d[105]; long long dp[55][55][55], ways[55][55][55]; long long wk(int a, int b, int c) { if (a < 0 || b < 0) return 0; if (dp[a][b][c] != -1) return dp[a][b][c]; int ans = 0; if (c) { ans = (wk(a - 1, b, c - 1) * a + wk(a + 1, b - 1, c - 1) * b) % 1000000007; } else if (a) { ans = (wk(a - 2, b, 0) * (a - 1) + wk(a, b - 1, 0) * b) % 1000000007; } else if (b > 2) { for (long long z = 3, x = (b - 1) * (b - 2) / 2; z <= b; x = x * (b - z++) % 1000000007) { ans += x * wk(0, b - z, 0) % 1000000007; ans %= 1000000007; } } else ans = (b == 0); return dp[a][b][c] = ans; ; } int mdp[55][55]; int cal(int l, int r) { if (mdp[l][r] != -1) return mdp[l][r]; if (r > n) return 0; int ans = 0, c2 = 0, c3 = 0; for (int i = l; i <= r; i++) if (d[i] == 2) c2++; else c3++; if (r == n) ans = wk(c2, c3, 0) % 1000000007; else { for (int x = 1; x <= n - r; x++) { addmod(ans, wk(c2, c3, x) * cal(r + 1, r + x) % 1000000007); } } return mdp[l][r] = ans; } void fmain(int tid) { scanf( %d , &n); for (int(i) = 1; (i) <= (int)(n); (i)++) scanf( %d , d + i); initfac(55); ways[0][0][0] = 1; memset(dp, -1, sizeof dp); memset(mdp, -1, sizeof mdp); int ans = d[1] == 2 ? cal(2, 3) : cal(2, 4); printf( %d n , ans); } int main() { int t = 1; for (int(i) = 1; (i) <= (int)(t); (i)++) { fmain(i); } return 0; } |
#include <bits/stdc++.h> using namespace std; bool major, minor; map<string, int> P; string x, y, z; int k1, k2; void go(string x, string y, string z) { if (P[x] <= P[y]) k1 = P[y] - P[x]; else k1 = 12 - P[x] + P[y]; if (P[y] <= P[z]) k2 = P[z] - P[y]; else k2 = 12 - P[y] + P[z]; if (k1 == 4 && k2 == 3) major = true; else if (k1 == 3 && k2 == 4) minor = true; } int main(int argc, char *argv[]) { P[ C ] = 1; P[ C# ] = 2; P[ D ] = 3; P[ D# ] = 4; P[ E ] = 5; P[ F ] = 6; P[ F# ] = 7; P[ G ] = 8; P[ G# ] = 9; P[ A ] = 10; P[ B ] = 11; P[ H ] = 12; major = false; minor = false; cin >> x >> y >> z; go(x, y, z); go(x, z, y); go(y, x, z); go(y, z, x); go(z, x, y); go(z, y, x); if (major) cout << major << endl; else if (minor) cout << minor << endl; else cout << strange << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; #define me(a, b) memset(a, b, sizeof(a)) #define IOS() ios::sync_with_stdio(false), cin.tie(0) #define endl n typedef long long ll; typedef pair<ll, ll> pll; typedef pair<int, int> pii; const int INF = 0x3f3f3f3f; const int maxn = 2e5 + 5; const ll mod = 1e9 + 7; int cnt[26]; int n, k; vector<pii> ans; int check() { ans.clear(); int sum = 0; for(int i = 0; i < 26; ++i) { int r = cnt[i] % k; if(r){ ans.push_back(pii(i, k - r)); sum += k - r; } } return sum; } void solve() { me(cnt, 0); string s; cin >> n >> k >> s; for(char &c : s) ++cnt[c - a ]; if(check() == 0) { cout << s << endl; return ; } for(int i = s.size()-1; i >= 0; --i) { char &c = s[i]; --cnt[c - a ]; for(int j = s[i] - a + 1; j < 26; ++j) { c = j + a ; ++cnt[j]; int sum = s.size()-i-1 - check(); --cnt[j]; if(sum >= 0 && sum % k == 0) { string t; for(int p = 0; p <= i; ++p) t.push_back(s[p]); t.append(sum, a ); for(pii p : ans) { t.append(p.second, p.first+ a ); } cout << t << endl; return ; } } } cout << -1 n ; } int main() { IOS(); int T; cin >> T; while(T--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int e[100010]; int main() { int n, u, i, j = 3; double ans = 0; scanf( %d%d , &n, &u); for (i = 1; i <= n; i++) scanf( %d , &e[i]); for (i = 1; i <= n; i++) { while (j <= n && e[j] - e[i] <= u) j++; j--; if (j > i + 1) ans = max(ans, (e[j] - e[i + 1] + 0.0) / (e[j] - e[i])); } if (ans == 0) cout << -1 << endl; else { cout.precision(19); cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ifstream fin( input.txt ); double a, b, c = 1.000000011, d; cin >> a >> b; d = a * pow(c, b); cout.precision(30); cout << d << endl; return 0; } |
#include <bits/stdc++.h> int main(void) { int t; long long int a, b, k, p, s; scanf( %d , &t); for (int i = 0; i < t; i++) { scanf( %lld , &a); scanf( %lld , &b); scanf( %lld , &k); s = k / 2; if ((k % 2) == 0) { p = (a - b) * (s); } if ((k % 2) == 1) { p = ((a - b) * (s) + a); } printf( %lld n , p); } return 0; } |
module Average_Filter(
input [11:0] in,
input clk,
input reset_n,
output reg out_ready,
output reg [11:0] out1,
output reg [11:0] out2
);
localparam s0 = 3'b000;
localparam s1 = 3'b001;
localparam s2 = 3'b010;
localparam s3 = 3'b011;
localparam s4 = 3'b100;
localparam s5 = 3'b101;
localparam s6 = 3'b110;
localparam s7 = 3'b111;
reg [2:0] nextState, state;
reg [11:0] sample_array1 [7:0];
reg [11:0] sample_array2 [7:0];
reg [7:0] counter1, counter2;
reg inc_count1, inc_count2, reset_count1, reset_count2, compute_avg,
update_array1, update_array2;
reg [14:0] temp;
initial begin
counter1 = 0;
counter2 = 0;
state = 0;
end
always @ (posedge clk) begin
if(!reset_n) begin
state <= s0;
end
else begin
state <= nextState;
end
end
always @ (posedge clk) begin
if(inc_count1) begin
counter1 <= counter1 + 1;
end
if(inc_count2) begin
counter2 <= counter2 + 1;
end
if(reset_count1) begin
counter1 <= 0;
end
if(reset_count2) begin
counter2 <= 0;
end
if(compute_avg) begin
temp = sample_array1[0] + sample_array1[1] + sample_array1[2] + sample_array1[3] + sample_array1[4] +
sample_array1[5] + sample_array1[6] + sample_array1[7];
out1 = temp >> 3;
temp = sample_array2[0] + sample_array2[1] + sample_array2[2] + sample_array2[3] + sample_array2[4] +
sample_array2[5] + sample_array2[6] + sample_array2[7];
out2 = temp >> 3;
end
if(update_array1) begin
sample_array1[counter1[2:0]] <= in;
end
if(update_array2) begin
sample_array2[counter2[2:0]] <= in;
end
end
always @ * begin
inc_count1 = 0; inc_count2 = 0; reset_count1 = 0; reset_count2 = 0; out_ready = 0; compute_avg = 0;
update_array1 = 0; update_array2 = 0;
case(state)
s0: begin
update_array1 = 1;
nextState = s1;
end
s1: begin
if(counter1 == 7) begin
reset_count1 = 1;
nextState = s2;
end else begin
inc_count1 = 1;
nextState = s0;
end
end
s2: begin
update_array2 = 1;
nextState = s3;
end
s3: begin
if(counter2 == 7) begin
reset_count2 = 1;
nextState = s4;
end else begin
inc_count2 = 1;
nextState = s2;
end
end
s4: begin
update_array1 = 1;
compute_avg = 1;
nextState = s5;
end
s5: begin
inc_count1 = 1;
out_ready = 1;
nextState = s0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int list[n]; int i; for (i = 0; i < n; i++) cin >> list[i]; int total = accumulate(list, list + n, 0); n++; int count = 0; for (i = 1; i <= 5; i++) { if ((total + i) % n != 1) { count++; } } cout << count; } |
#include <bits/stdc++.h> using namespace std; int a[123], p[123]; signed main() { int t; scanf( %d , &t); while (t--) { int n, m; scanf( %d %d , &n, &m); memset(p, 0, sizeof(p)); for (int i = 1; i <= n; ++i) scanf( %d , a + i); for (int i = 1, x; i <= m; ++i) scanf( %d , &x), p[x] = 1; bool ok = 1; for (int i = 1; i <= n; ++i) for (int j = i + 1; j <= n; ++j) { if (!ok) break; if (a[i] > a[j]) for (int k = i; k < j; ++k) if (!p[k]) { ok = 0; break; } } ok ? puts( YES ) : puts( NO ); } return 0; } |
//
// Copyright (c) 1999 Peter Monta ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
wire [3:0] b;
reg [1:0] a;
reg c;
assign b = c<<a;
initial begin
#1 ;
c = 1'b1;
a = 2'd2;
#1;
if (b===4'b0100)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:167772160 ) using namespace std; const int inf = 1000000000; long long k[1001], p[1001], f[1001], c[1001]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) cin >> k[i] >> c[i]; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) if (c[i] > c[j]) { swap(c[i], c[j]); swap(k[i], k[j]); } int t; cin >> t; for (int i = 1; i <= t; i++) cin >> p[i]; p[0] = 0; for (int i = 1; i <= t; i++) f[i] = p[i] - p[i - 1]; f[t + 1] = 1000000000000LL; int j = 1; long long num = 0; long long ans = 0; for (int i = 1; i <= t + 1; i++) { while (j <= n) { long long mn = min(k[j] - num, f[i]); ans += (long long)c[j] * mn * (long long)i; if (mn == k[j] - num && mn == f[i]) { ++j; num = 0; break; } else if (mn == k[j] - num) { ++j; f[i] -= mn; num = 0; } else { num += mn; break; } } } cout << ans << endl; } |
//
// Author: Pawel Szostek ()
// Date: 01.08.2011
`timescale 1ns/1ps
module match_bits_v(input [7:0] a,b, output reg [7:0] match);
integer i;
wire ab_xor;
always @(a or b) begin
for (i=7; i>=0; i=i-1) begin
match[i] = ~(a[i]^b[i]);
end
end
endmodule
module check(input [7:0] a,b,o_vhdl, o_verilog);
always @(a or b) begin
#1 if (o_vhdl !== o_verilog) begin
$display("ERROR!");
$display("VERILOG: ", o_verilog);
$display("VHDL: ", o_vhdl);
$finish;
end
end
endmodule
module stimulus (output reg [7:0] a,b);
parameter S = 20000;
int unsigned i,j,k,l;
initial begin //stimulate data
for (i=0; i<S; i=i+1) begin
#5;
for(k=0; k<8; k=k+1) begin
a[k] <= inject();
end
end
end
initial begin //stimulate data
for (i=0; i<S; i=i+1) begin
#4;
for(l=0; l<8; l=l+1) begin
b[l] <= inject();
end
end
#100 $display("PASSED");
$finish;
end
function inject();
reg [3:0] temp;
begin
temp = $random % 16;
if(temp >= 10)
inject = 1'b1;
else
inject = 1'b0;
end
endfunction
endmodule
module main;
wire [7:0] a,b,o_vhdl, o_verilog;
match_bits match_vhdl(a,b,o_vhdl);
match_bits_v match_verilog(a,b,o_verilog);
stimulus stim(a,b);
check c(a,b,o_vhdl, o_verilog);
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 16469 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4,
w5,
w16384,
w16389,
w80,
w16469;
assign w1 = i_data0;
assign w16384 = w1 << 14;
assign w16389 = w5 + w16384;
assign w16469 = w16389 + w80;
assign w4 = w1 << 2;
assign w5 = w1 + w4;
assign w80 = w5 << 4;
assign o_data0 = w16469;
//multiplier_block area estimate = 5189.18412875588;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[105], z, x; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , a + i); if (a[i] % 2) x++; z += a[i]; } if (z % 2) printf( %d , x); else printf( %d , n - x); } |
#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cout << [ << *it << : << a << ] t ; err(++it, args...); } const long long nax = 1e3 + 5; long long n; long long a[nax], dp[nax][nax]; long long fw(long long i, long long j) { if (i == n) return 0; if (j == n) return a[i]; if (j == n - 1) return max(a[i], a[j]); if (dp[i][j] != -1) return dp[i][j]; long long& first = dp[i][j]; first = (long long)(1e18); first = min(first, fw(j + 1, j + 2) + max(a[i], a[j])); first = min(first, fw(i, j + 2) + max(a[j], a[j + 1])); first = min(first, fw(j, j + 2) + max(a[i], a[j + 1])); return first; } void bw(long long i, long long j) { if (i == n) return; if (j == n) { cout << i + 1; return; } if (j == n - 1) { cout << i + 1 << << j + 1 << n ; return; } long long first = dp[i][j]; if (first == max(a[i], a[j]) + fw(j + 1, j + 2)) { cout << i + 1 << << j + 1 << n ; bw(j + 1, j + 2); return; } if (first == max(a[j], a[j + 1]) + fw(i, j + 2)) { cout << j + 1 << << j + 2 << n ; bw(i, j + 2); return; } if (first == max(a[i], a[j + 1]) + fw(j, j + 2)) { cout << i + 1 << << j + 2 << n ; bw(j, j + 2); return; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; memset(dp, -1, sizeof(dp)); for (long long i = 0; i < n; i++) { cin >> a[i]; } cout << fw(0, 1) << n ; bw(0, 1); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, d[40005], v[4005], p[4005], cur, val, use[4005], cnt; int main() { cin >> n; for (int i = 1; i <= n; ++i) cin >> v[i] >> d[i] >> p[i]; for (int i = 1; i <= n; ++i) if (!use[i]) { cur = v[i]; for (int j = i + 1; j <= n; ++j) if (!use[j]) { if (cur == 0) break; p[j] -= cur; cur--; } for (int j = i + 1; j <= n; ++j) if (p[j] < 0 && !use[j]) { use[j] = 1; val = d[j]; for (int k = j + 1; k <= n; ++k) if (!use[k]) { p[k] -= val; if (p[k] < 0) { use[k] = 1; val += d[k]; } } break; } } for (int i = 1; i <= n; ++i) if (p[i] >= 0) cnt++; cout << cnt << endl; for (int i = 1; i <= n; ++i) if (p[i] >= 0) cout << i << ; } |
`define MEMORY_CONTROLLER_TAGS 1
`define MEMORY_CONTROLLER_TAG_SIZE 1
`define TAG__str 1'b0
`define MEMORY_CONTROLLER_ADDR_SIZE 32
`define MEMORY_CONTROLLER_DATA_SIZE 32
module memory_controller
(
clk,
memory_controller_address,
memory_controller_write_enable,
memory_controller_in,
memory_controller_out
);
input clk;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
input memory_controller_write_enable;
input [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [4:0] str_address;
reg str_write_enable;
reg [7:0] str_in;
wire [7:0] str_out;
single_port_ram _str (
.clk( clk ),
.addr( str_address ),
.we( str_write_enable ),
.data( str_in ),
.out( str_out )
);
wire tag;
//must use all wires inside module.....
assign tag = |memory_controller_address & |memory_controller_address & | memory_controller_in;
reg [`MEMORY_CONTROLLER_TAG_SIZE-1:0] prevTag;
always @(posedge clk)
prevTag <= tag;
always @( tag or memory_controller_address or memory_controller_write_enable or memory_controller_in)
begin
case(tag)
1'b0:
begin
str_address = memory_controller_address[5-1+0:0];
str_write_enable = memory_controller_write_enable;
str_in[8-1:0] = memory_controller_in[8-1:0];
end
endcase
case(prevTag)
1'b0:
memory_controller_out = str_out;
endcase
end
endmodule
module memset
(
clk,
reset,
start,
finish,
return_val,
m,
c,
n,
memory_controller_write_enable,
memory_controller_address,
memory_controller_in,
memory_controller_out
);
output[`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] return_val;
input clk;
input reset;
input start;
output finish;
reg finish;
input [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] m;
input [31:0] c;
input [31:0] n;
output [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] memory_controller_address;
output memory_controller_write_enable;
reg memory_controller_write_enable;
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
reg [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_in;
output [`MEMORY_CONTROLLER_DATA_SIZE-1:0] memory_controller_out;
reg [3:0] cur_state;
/*
parameter Wait = 4'd0;
parameter entry = 4'd1;
parameter entry_1 = 4'd2;
parameter entry_2 = 4'd3;
parameter bb = 4'd4;
parameter bb_1 = 4'd5;
parameter bb1 = 4'd6;
parameter bb1_1 = 4'd7;
parameter bb_nph = 4'd8;
parameter bb2 = 4'd9;
parameter bb2_1 = 4'd10;
parameter bb2_2 = 4'd11;
parameter bb2_3 = 4'd12;
parameter bb2_4 = 4'd13;
parameter bb4 = 4'd14;
*/
memory_controller memtroll (clk,memory_controller_address, memory_controller_write_enable, memory_controller_in, memory_controller_out);
reg [31:0] indvar;
reg var1;
reg [31:0] tmp;
reg [31:0] tmp8;
reg var2;
reg [31:0] var0;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] scevgep;
reg [`MEMORY_CONTROLLER_ADDR_SIZE-1:0] s_07;
reg [31:0] indvar_next;
reg exitcond;
always @(posedge clk)
if (reset)
cur_state <= 4'b0000;
else
case(cur_state)
4'b0000:
begin
finish <= 1'b0;
if (start == 1'b1)
cur_state <= 4'b0001;
else
cur_state <= 4'b0000;
end
4'b0001:
begin
var0 <= n & 32'b00000000000000000000000000000011;
cur_state <= 4'b0010;
end
4'b0010:
begin
var1 <= 1'b0;
var0 <= 32'b00000000000000000000000000000000;
cur_state <= 4'b0011;
end
4'b0011:
begin
if (|var1) begin
cur_state <= 4'b0110;
end
else
begin
cur_state <= 4'b0100;
end
end
4'b0100:
begin
cur_state <= 4'b0101;
end
4'b0101:
begin
cur_state <= 4'b0110;
end
4'b0110:
begin
var2 <= | (n [31:4]);
cur_state <= 4'b0111;
end
4'b0111:
begin
if (|var2)
begin
cur_state <= 4'b1110;
end
else
begin
cur_state <= 4'b1000;
end
end
4'b1000:
begin
tmp <= n ;
indvar <= 32'b00000000000000000000000000000000;
cur_state <= 4'b1001;
end
4'b1001:
begin
cur_state <= 4'b1010;
end
4'b1010:
begin
tmp8 <= indvar;
indvar_next <= indvar;
cur_state <= 4'b1011;
end
4'b1011:
begin
scevgep <= (m & tmp8);
exitcond <= (indvar_next == tmp);
cur_state <= 4'b1100;
end
4'b1100:
begin
s_07 <= scevgep;
cur_state <= 4'b1101;
end
4'b1101:
begin
if (exitcond)
begin
cur_state <= 4'b1110;
end
else
begin
indvar <= indvar_next;
cur_state <= 4'b1001;
end
end
4'b1110:
begin
return_val <= m;
finish <= 1'b1;
cur_state <= 4'b0000;
end
endcase
always @(cur_state)
begin
case(cur_state)
4'b1101:
begin
memory_controller_address = s_07;
memory_controller_write_enable = 1'b1;
memory_controller_in = c;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTN_FUNCTIONAL_V
`define SKY130_FD_SC_HS__SDFRTN_FUNCTIONAL_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_r_pg/sky130_fd_sc_hs__u_df_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfrtn (
VPWR ,
VGND ,
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk , CLK_N );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_df_p_r_pg `UNIT_DELAY u_df_p_r_pg0 (buf_Q , mux_out, intclk, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTN_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 35000, K = 50; struct seg_node { seg_node *lc, *rc; int l, r, f, m; seg_node(seg_node *lc, seg_node *rc, int l, int r) : lc(lc), rc(rc), l(l), r(r), f(), m() {} static seg_node *build(int l, int r) { if (l == r - 1) return new seg_node(nullptr, nullptr, l, r); int mid = (l + r) / 2; return new seg_node(build(l, mid), build(mid, r), l, r); } void add(int val) { f += val; m += val; } void push_down() { if (f > 0) { lc->add(f); rc->add(f); f = 0; } } void maintain() { m = max({m, lc->m, rc->m}); } void add(int ql, int qr, int val) { if (ql == l && qr == r) add(val); else { push_down(); int mid = (l + r) / 2; if (qr <= mid) lc->add(ql, qr, val); else if (ql >= mid) rc->add(ql, qr, val); else { lc->add(ql, mid, val); rc->add(mid, qr, val); } maintain(); } } int query(int ql, int qr) { if (ql == l && qr == r) return m; else { push_down(); int mid = (l + r) / 2; if (qr <= mid) return lc->query(ql, qr); else if (ql >= mid) return rc->query(ql, qr); else return max(lc->query(ql, mid), rc->query(mid, qr)); } } } * t[K + 1]; int a[N], last[N]; int main() { ios::sync_with_stdio(false); int n, k; cin >> n >> k; int cnt = 0; t[1] = seg_node::build(0, n); memset(last, 0xff, sizeof last); for (int i = 0; i < n; i++) { cin >> a[i]; a[i]--; if (last[a[i]] == -1) { cnt++; last[a[i]] = i; } t[1]->add(i, i + 1, cnt); } for (int i = 2; i <= k; i++) { t[i] = seg_node::build(0, n); memset(last, 0xff, sizeof last); for (int j = i - 1; j < n; j++) { t[i - 1]->add(last[a[j]] == -1 ? i - 2 : last[a[j]], j, 1); t[i]->add(j, j + 1, t[i - 1]->query(i - 2, j)); last[a[j]] = j; } } cout << t[k]->query(n - 1, n); } |
#include <bits/stdc++.h> using namespace std; string v[12] = { x^y^z , x^z^y , (x^y)^z , (x^z)^y , y^x^z , y^z^x , (y^x)^z , (y^z)^x , z^x^y , z^y^x , (z^x)^y , (z^y)^x }; pair<long double, long double> sol[12]; const long double EPS = 1e-12; long double cmp(pair<long double, long double> a, pair<long double, long double> b) { long double res1, res2; res1 = a.second * log(a.first); res2 = b.second * log(b.first); if (abs(res1 - res2) < EPS) return 0; return res1 - res2; } int main() { int i, pos; long double x, y, z; cin >> x >> y >> z; sol[0] = {x, pow(y, z)}; sol[1] = {x, pow(z, y)}; sol[2] = {x, y * z}; sol[3] = {x, z * y}; sol[4] = {y, pow(x, z)}; sol[5] = {y, pow(z, x)}; sol[6] = {y, x * z}; sol[6] = {y, z * x}; sol[8] = {z, pow(x, y)}; sol[9] = {z, pow(y, x)}; sol[10] = {z, x * y}; sol[11] = {z, y * x}; pos = 0; for (i = 1; i < 12; ++i) { if (cmp(sol[pos], sol[i]) < 0) pos = i; } cout << v[pos]; return 0; } |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 12.4
// \ \ Application : xaw2verilog
// / / Filename : master_clk.v
// /___/ /\ Timestamp : 05/02/2013 05:55:56
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -intstyle C:/Users/rodriguj/Documents/proyectos_xilinx/ula_replacement_tests/test3/ipcore_dir/master_clk.xaw -st master_clk.v
//Design Name: master_clk
//Device: xc3s100e-4vq100
//
// Module master_clk
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
// Period Jitter (unit interval) for block DCM_SP_INST = 0.04 UI
// Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 3.20 ns
`timescale 1ns / 1ps
module master_clk(CLKIN_IN,
CLKDV_OUT,
CLKFX_OUT,
CLKIN_IBUFG_OUT,
CLK0_OUT);
input CLKIN_IN;
output CLKDV_OUT;
output CLKFX_OUT;
output CLKIN_IBUFG_OUT;
output CLK0_OUT;
wire CLKDV_BUF;
wire CLKFB_IN;
wire CLKFX_BUF;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire GND_BIT;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG CLKFX_BUFG_INST (.I(CLKFX_BUF),
.O(CLKFX_OUT));
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(5.0), .CLKFX_DIVIDE(20),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(),
.PSDONE(),
.STATUS());
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: tb_openMSP430_fpga.v
//
// *Module Description:
// openMSP430 FPGA testbench
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`include "timescale.v"
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module tb_openMSP430_fpga;
//
// Wire & Register definition
//------------------------------
// Clock & Reset
reg CLK_50MHz;
reg RESET;
// Slide Switches
reg SW7;
reg SW6;
reg SW5;
reg SW4;
reg SW3;
reg SW2;
reg SW1;
reg SW0;
// Push Button Switches
reg BTN2;
reg BTN1;
reg BTN0;
// LEDs
wire LED7;
wire LED6;
wire LED5;
wire LED4;
wire LED3;
wire LED2;
wire LED1;
wire LED0;
// Four-Sigit, Seven-Segment LED Display
wire SEG_A;
wire SEG_B;
wire SEG_C;
wire SEG_D;
wire SEG_E;
wire SEG_F;
wire SEG_G;
wire SEG_DP;
wire SEG_AN0;
wire SEG_AN1;
wire SEG_AN2;
wire SEG_AN3;
// UART
reg UART_RXD;
wire UART_TXD;
// Core debug signals
wire [8*32-1:0] i_state;
wire [8*32-1:0] e_state;
wire [31:0] inst_cycle;
wire [8*32-1:0] inst_full;
wire [31:0] inst_number;
wire [15:0] inst_pc;
wire [8*32-1:0] inst_short;
// Testbench variables
integer i;
integer error;
reg stimulus_done;
//
// Include files
//------------------------------
// CPU & Memory registers
`include "registers.v"
// Verilog stimulus
`include "stimulus.v"
//
// Initialize Program Memory
//------------------------------
initial
begin
// Read memory file
#10 $readmemh("./pmem.mem", pmem);
// Update Xilinx memory banks
for (i=0; i<2048; i=i+1)
begin
dut.rom_8x2k_hi_0.inst.mem[i] = pmem[i][15:8];
dut.rom_8x2k_lo_0.inst.mem[i] = pmem[i][7:0];
end
end
//
// Generate Clock & Reset
//------------------------------
initial
begin
CLK_50MHz = 1'b0;
forever #10 CLK_50MHz <= ~CLK_50MHz; // 50 MHz
end
initial
begin
RESET = 1'b0;
#100 RESET = 1'b1;
#600 RESET = 1'b0;
end
//
// Global initialization
//------------------------------
initial
begin
error = 0;
stimulus_done = 1;
SW7 = 1'b0; // Slide Switches
SW6 = 1'b0;
SW5 = 1'b0;
SW4 = 1'b0;
SW3 = 1'b0;
SW2 = 1'b0;
SW1 = 1'b0;
SW0 = 1'b0;
BTN2 = 1'b0; // Push Button Switches
BTN1 = 1'b0;
BTN0 = 1'b0;
UART_RXD = 1'b0; // UART
end
//
// openMSP430 FPGA Instance
//----------------------------------
openMSP430_fpga dut (
// Clock Sources
.CLK_50MHz (CLK_50MHz),
.CLK_SOCKET (1'b0),
// Slide Switches
.SW7 (SW7),
.SW6 (SW6),
.SW5 (SW5),
.SW4 (SW4),
.SW3 (SW3),
.SW2 (SW2),
.SW1 (SW1),
.SW0 (SW0),
// Push Button Switches
.BTN3 (RESET),
.BTN2 (BTN2),
.BTN1 (BTN1),
.BTN0 (BTN0),
// LEDs
.LED7 (LED7),
.LED6 (LED6),
.LED5 (LED5),
.LED4 (LED4),
.LED3 (LED3),
.LED2 (LED2),
.LED1 (LED1),
.LED0 (LED0),
// Four-Sigit, Seven-Segment LED Display
.SEG_A (SEG_A),
.SEG_B (SEG_B),
.SEG_C (SEG_C),
.SEG_D (SEG_D),
.SEG_E (SEG_E),
.SEG_F (SEG_F),
.SEG_G (SEG_G),
.SEG_DP (SEG_DP),
.SEG_AN0 (SEG_AN0),
.SEG_AN1 (SEG_AN1),
.SEG_AN2 (SEG_AN2),
.SEG_AN3 (SEG_AN3),
// RS-232 Port
.UART_RXD (UART_RXD),
.UART_TXD (UART_TXD),
.UART_RXD_A (1'b0),
.UART_TXD_A (UART_TXD_A),
// PS/2 Mouse/Keyboard Port
.PS2_D (PS2_D),
.PS2_C (PS2_C),
// Fast, Asynchronous SRAM
.SRAM_A17 (SRAM_A17), // Address Bus Connections
.SRAM_A16 (SRAM_A16),
.SRAM_A15 (SRAM_A15),
.SRAM_A14 (SRAM_A14),
.SRAM_A13 (SRAM_A13),
.SRAM_A12 (SRAM_A12),
.SRAM_A11 (SRAM_A11),
.SRAM_A10 (SRAM_A10),
.SRAM_A9 (SRAM_A9),
.SRAM_A8 (SRAM_A8),
.SRAM_A7 (SRAM_A7),
.SRAM_A6 (SRAM_A6),
.SRAM_A5 (SRAM_A5),
.SRAM_A4 (SRAM_A4),
.SRAM_A3 (SRAM_A3),
.SRAM_A2 (SRAM_A2),
.SRAM_A1 (SRAM_A1),
.SRAM_A0 (SRAM_A0),
.SRAM_OE (SRAM_OE), // Write enable and output enable control signals
.SRAM_WE (SRAM_WE),
.SRAM0_IO15 (SRAM0_IO15), // SRAM Data signals, chip enables, and byte enables
.SRAM0_IO14 (SRAM0_IO14),
.SRAM0_IO13 (SRAM0_IO13),
.SRAM0_IO12 (SRAM0_IO12),
.SRAM0_IO11 (SRAM0_IO11),
.SRAM0_IO10 (SRAM0_IO10),
.SRAM0_IO9 (SRAM0_IO9),
.SRAM0_IO8 (SRAM0_IO8),
.SRAM0_IO7 (SRAM0_IO7),
.SRAM0_IO6 (SRAM0_IO6),
.SRAM0_IO5 (SRAM0_IO5),
.SRAM0_IO4 (SRAM0_IO4),
.SRAM0_IO3 (SRAM0_IO3),
.SRAM0_IO2 (SRAM0_IO2),
.SRAM0_IO1 (SRAM0_IO1),
.SRAM0_IO0 (SRAM0_IO0),
.SRAM0_CE1 (SRAM0_CE1),
.SRAM0_UB1 (SRAM0_UB1),
.SRAM0_LB1 (SRAM0_LB1),
.SRAM1_IO15 (SRAM1_IO15),
.SRAM1_IO14 (SRAM1_IO14),
.SRAM1_IO13 (SRAM1_IO13),
.SRAM1_IO12 (SRAM1_IO12),
.SRAM1_IO11 (SRAM1_IO11),
.SRAM1_IO10 (SRAM1_IO10),
.SRAM1_IO9 (SRAM1_IO9),
.SRAM1_IO8 (SRAM1_IO8),
.SRAM1_IO7 (SRAM1_IO7),
.SRAM1_IO6 (SRAM1_IO6),
.SRAM1_IO5 (SRAM1_IO5),
.SRAM1_IO4 (SRAM1_IO4),
.SRAM1_IO3 (SRAM1_IO3),
.SRAM1_IO2 (SRAM1_IO2),
.SRAM1_IO1 (SRAM1_IO1),
.SRAM1_IO0 (SRAM1_IO0),
.SRAM1_CE2 (SRAM1_CE2),
.SRAM1_UB2 (SRAM1_UB2),
.SRAM1_LB2 (SRAM1_LB2),
// VGA Port
.VGA_R (VGA_R),
.VGA_G (VGA_G),
.VGA_B (VGA_B),
.VGA_HS (VGA_HS),
.VGA_VS (VGA_VS)
);
//
// Debug utility signals
//----------------------------------------
msp_debug msp_debug_0 (
// OUTPUTs
.e_state (e_state), // Execution state
.i_state (i_state), // Instruction fetch state
.inst_cycle (inst_cycle), // Cycle number within current instruction
.inst_full (inst_full), // Currently executed instruction (full version)
.inst_number (inst_number), // Instruction number since last system reset
.inst_pc (inst_pc), // Instruction Program counter
.inst_short (inst_short), // Currently executed instruction (short version)
// INPUTs
.mclk (mclk), // Main system clock
.puc_rst (puc_rst) // Main system reset
);
//
// Generate Waveform
//----------------------------------------
initial
begin
`ifdef VPD_FILE
$vcdplusfile("tb_openMSP430_fpga.vpd");
$vcdpluson();
`else
`ifdef TRN_FILE
$recordfile ("tb_openMSP430_fpga.trn");
$recordvars;
`else
$dumpfile("tb_openMSP430_fpga.vcd");
$dumpvars(0, tb_openMSP430_fpga);
`endif
`endif
end
//
// End of simulation
//----------------------------------------
initial // Timeout
begin
`ifdef NO_TIMEOUT
`else
`ifdef VERY_LONG_TIMEOUT
#500000000;
`else
`ifdef LONG_TIMEOUT
#;
`else
#500000;
`endif
`endif
$display(" ===============================================");
$display("| SIMULATION FAILED |");
$display("| (simulation Timeout) |");
$display(" ===============================================");
$finish;
`endif
end
initial // Normal end of test
begin
@(inst_pc===16'hffff)
$display(" ===============================================");
if (error!=0)
begin
$display("| SIMULATION FAILED |");
$display("| (some verilog stimulus checks failed) |");
end
else if (~stimulus_done)
begin
$display("| SIMULATION FAILED |");
$display("| (the verilog stimulus didn't complete) |");
end
else
begin
$display("| SIMULATION PASSED |");
end
$display(" ===============================================");
$finish;
end
//
// Tasks Definition
//------------------------------
task tb_error;
input [65*8:0] error_string;
begin
$display("ERROR: %s %t", error_string, $time);
error = error+1;
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.14159265358979323846; const double eps = (1e-10); int isGreater(long double x, long double y) { if (abs(x - y) < eps) return 0; if (x > y) return 1; return -1; } const int MOD = 998244353; int mult(int x, int y) { return (1LL * x * y) % MOD; } int add(int x, int y) { x += y; while (x >= MOD) x -= MOD; while (x < 0) x += MOD; return x; } int add(vector<int> v) { int ret = 0; for (int i = 0; i < (int)((v).size()); ++i) ret = add(ret, v[i]); return ret; } const int MAX_N = 3e5 + 5; vector<int> adj[MAX_N]; int dp[MAX_N][3][2]; int n; void calc(int u, int p) { for (int v : adj[u]) { if (v != p) calc(v, u); } dp[u][0][1] = 0; dp[u][0][0] = 1; for (int v : adj[u]) { if (v != p) dp[u][0][0] = mult(dp[u][0][0], add({dp[v][0][0], dp[v][2][0], dp[v][2][1]})); } dp[u][2][0] = dp[u][2][1] = 1; for (int v : adj[u]) { if (v != p) { dp[u][2][0] = mult(dp[u][2][0], add({dp[v][1][0], dp[v][1][1], dp[v][2][0], dp[v][2][1], dp[v][0][0]})); dp[u][2][1] = mult(dp[u][2][1], add({dp[v][1][0], dp[v][2][0], dp[v][2][1], dp[v][0][0]})); } } dp[u][2][0] = add(dp[u][2][0], -dp[u][0][0]); dp[u][2][1] = add(dp[u][2][1], -dp[u][0][0]); if (u == 0) return; dp[u][1][0] = dp[u][1][1] = 1; for (int v : adj[u]) { if (v != p) { dp[u][1][0] = mult(dp[u][1][0], add({dp[v][0][0], dp[v][2][0], dp[v][2][1], dp[v][1][0], dp[v][1][1]})); dp[u][1][1] = mult(dp[u][1][1], add({dp[v][0][0], dp[v][2][0], dp[v][2][1], dp[v][1][0]})); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n - 1; ++i) { int u, v; cin >> u >> v; --u; --v; adj[u].push_back(v); adj[v].push_back(u); } calc(0, n); cout << add({dp[0][0][0], dp[0][2][0], dp[0][2][1], -1}); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 2147483647; const long long LLINF = 9223372036854775807LL; const int ST = 100010; const int ST1 = 1000010; const long long MOD = 1000000007; long long ABS(long long a) { if (a < 0) return a * (-1); else return a; } int mas[30]; bool ans = true; void bad() { cout << NO ; exit(0); } vector<vector<int> > ppp; int sz = 0; void per(vector<int> &t) { if ((int)((t).size()) == sz) { ppp.push_back(t); } else { t.push_back(0); per(t); t.pop_back(); t.push_back(1); per(t); t.pop_back(); } } void per(vector<int> val, int ed, vector<int> zap) { if ((int)((val).size()) == 0) { if (ed == 0) { cout << YES ; exit(0); } else return; } vector<vector<int> > pp; vector<int> em; sz = (int)((zap).size()); ppp.clear(); per(em); pp = ppp; int tek = val[(int)((val).size()) - 1] - 1; val.pop_back(); int ost = 0; for (int i = 0; i < (int)((pp).size()); i++) { vector<int> next; next.push_back(tek + 1); ost = 0; int kk = 0; for (int j = 0; j < (int)((pp[i]).size()); j++) { if (pp[i][j] == 1) { ost += zap[j]; kk++; } else next.push_back(zap[j]); } if (ost <= tek) { int s = tek - ost; if (s > ed) continue; kk += s; if (kk == 1) continue; per(val, ed - s, next); } } } int main() { int n; cin >> n; if (n == 1) { cout << YES ; return 0; } int kk = 0; for (int i = 0; i < n; i++) { cin >> mas[i]; if (mas[i] == 2) bad(); if (mas[i] == 1) kk++; } sort(mas, mas + n); int mn = n / 2; if (kk < mn) bad(); vector<int> t; int nol = 0; for (int i = 0; i < n; i++) if (mas[i] != 1) t.push_back(mas[i]); else nol++; vector<int> em; reverse(t.begin(), t.end()); per(t, nol, em); cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, a; set<int> st; int main() { ios::sync_with_stdio(false), cin.tie(0); cin >> n; while (n--) cin >> a, st.insert(a); st.erase(0); cout << st.size(); return 0; } |
// megafunction wizard: %ALTGX_RECONFIG%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt2gxb_reconfig
// ============================================================
// File Name: altgx_reconfig.v
// Megafunction Name(s):
// alt2gxb_reconfig
//
// Simulation Library Files(s):
// altera_mf;lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module altgx_reconfig (
reconfig_clk,
reconfig_fromgxb,
busy,
error,
reconfig_togxb)/* synthesis synthesis_clearbox = 1 */;
input reconfig_clk;
input [16:0] reconfig_fromgxb;
output busy;
output error;
output [3:0] reconfig_togxb;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADCE NUMERIC "0"
// Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
// Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: PMA NUMERIC "1"
// Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: CONSTANT: BASE_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
// Retrieval info: CONSTANT: ENABLE_CHL_ADDR_FOR_ANALOG_CTRL STRING "TRUE"
// Retrieval info: CONSTANT: ENABLE_SELF_RECOVERY STRING "TRUE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "1"
// Retrieval info: CONSTANT: READ_BASE_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: enable_buf_cal STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "17"
// Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
// Retrieval info: USED_PORT: error 0 0 0 0 OUTPUT NODEFVAL "error"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 INPUT NODEFVAL "reconfig_fromgxb[16..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_fromgxb 0 0 17 0 reconfig_fromgxb 0 0 17 0
// Retrieval info: CONNECT: @reconfig_mode_sel 0 0 3 0 GND 0 0 3 0
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: CONNECT: error 0 0 0 0 @error 0 0 0 0
// Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altgx_reconfig.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altgx_reconfig.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altgx_reconfig.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altgx_reconfig.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altgx_reconfig_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altgx_reconfig_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: LIB_FILE: lpm
|
//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
//Date : Tue Sep 17 19:42:16 2019
//Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
//Command : generate_target gcd_zynq_snick_wrapper.bd
//Design : gcd_zynq_snick_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module gcd_zynq_snick_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
gcd_zynq_snick gcd_zynq_snick_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
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#include <bits/stdc++.h> using namespace std; const int N = 1e3 + 3; const int inf = 1e8; int n, m; char str[N][N]; int sx, sy; int tx, ty; struct data { int up; int down; int rgt; int lft; data() { up = 0; down = 0; rgt = 0; lft = 0; } void rotate() { int _up = lft; int _rgt = up; int _down = rgt; int _lft = down; up = _up; rgt = _rgt; down = _down; lft = _lft; } }; data mat[N][N]; queue<int> qx; queue<int> qy; queue<int> qr; int dist[N][N][4]; inline void relax(int nx, int ny, int nr, int ndist) { if (dist[nx][ny][nr] > ndist) { dist[nx][ny][nr] = ndist; qx.push(nx); qy.push(ny); qr.push(nr); } } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; ++i) { scanf( %s , str[i] + 1); } for (int i = 0; i <= m + 1; ++i) { str[0][i] = * ; str[n + 1][i] = * ; } for (int i = 0; i <= n + 1; ++i) { str[i][0] = * ; str[i][m + 1] = * ; } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { if (str[i][j] == + ) { mat[i][j].up = 1; mat[i][j].lft = 1; mat[i][j].rgt = 1; mat[i][j].down = 1; } if (str[i][j] == - ) { mat[i][j].up = 0; mat[i][j].lft = 1; mat[i][j].rgt = 1; mat[i][j].down = 0; } if (str[i][j] == | ) { mat[i][j].up = 1; mat[i][j].lft = 0; mat[i][j].rgt = 0; mat[i][j].down = 1; } if (str[i][j] == ^ ) { mat[i][j].up = 1; mat[i][j].lft = 0; mat[i][j].rgt = 0; mat[i][j].down = 0; } if (str[i][j] == > ) { mat[i][j].up = 0; mat[i][j].lft = 0; mat[i][j].rgt = 1; mat[i][j].down = 0; } if (str[i][j] == < ) { mat[i][j].up = 0; mat[i][j].lft = 1; mat[i][j].rgt = 0; mat[i][j].down = 0; } if (str[i][j] == v ) { mat[i][j].up = 0; mat[i][j].lft = 0; mat[i][j].rgt = 0; mat[i][j].down = 1; } if (str[i][j] == L ) { mat[i][j].up = 1; mat[i][j].lft = 0; mat[i][j].rgt = 1; mat[i][j].down = 1; } if (str[i][j] == R ) { mat[i][j].up = 1; mat[i][j].lft = 1; mat[i][j].rgt = 0; mat[i][j].down = 1; } if (str[i][j] == U ) { mat[i][j].up = 0; mat[i][j].lft = 1; mat[i][j].rgt = 1; mat[i][j].down = 1; } if (str[i][j] == D ) { mat[i][j].up = 1; mat[i][j].lft = 1; mat[i][j].rgt = 1; mat[i][j].down = 0; } if (str[i][j] == * ) { mat[i][j].up = 0; mat[i][j].lft = 0; mat[i][j].rgt = 0; mat[i][j].down = 0; } } } scanf( %d %d , &sx, &sy); scanf( %d %d , &tx, &ty); for (int i = 0; i <= n + 1; ++i) { for (int j = 0; j <= m + 1; ++j) { for (int k = 0; k < 4; ++k) { dist[i][j][k] = inf; } } } relax(sx, sy, 0, 0); while (!qx.empty()) { int x = qx.front(); int y = qy.front(); int r = qr.front(); int d = dist[x][y][r]; qx.pop(); qy.pop(); qr.pop(); relax(x, y, (r + 1) % 4, d + 1); data tmp = mat[x][y]; data tmprgt = mat[x][y + 1]; data tmpdown = mat[x + 1][y]; data tmplft = mat[x][y - 1]; data tmpup = mat[x - 1][y]; for (int i = 0; i < r; ++i) { tmp.rotate(); tmprgt.rotate(); tmpdown.rotate(); tmplft.rotate(); tmpup.rotate(); } if (tmp.rgt && tmprgt.lft) { relax(x, y + 1, r, d + 1); } if (tmp.lft && tmplft.rgt) { relax(x, y - 1, r, d + 1); } if (tmp.up && tmpup.down) { relax(x - 1, y, r, d + 1); } if (tmp.down && tmpdown.up) { relax(x + 1, y, r, d + 1); } } int ans = inf; for (int i = 0; i < 4; ++i) { ans = min(ans, dist[tx][ty][i]); } if (ans >= inf) { ans = -1; } printf( %d n , ans); } |
module station_management_tb ();
reg reset;
reg clock;
wire mdc;
reg mdi;
wire mdo;
reg mode;
reg begin_transaction;
reg [4:0] phy_address;
reg [4:0] reg_address;
reg [15:0] data_in;
wire [15:0] data_out;
station_management U_station_management
(
.reset(reset),
.clock(clock),
.mdc(mdc),
.mdi(mdi),
.mdo(mdo),
.mode(mode),
.begin_transaction(begin_transaction),
.phy_address(phy_address),
.reg_address(reg_address),
.data_in(data_in),
.data_out(data_out)
);
integer i;
initial
begin
$dumpfile("test.vcd");
$dumpvars(0,station_management_tb);
end
initial
begin
mdi = 0;
reset = 1;
clock = 1;
mode = 0;
begin_transaction = 0;
phy_address = 5'b00001;
reg_address = 5'b00010;
data_in = 16'hFEDC;
#20 reset = 0;
#20 begin_transaction = 1;
#10 begin_transaction = 0;
#490
for (i=0; i<16; i = i + 1)
begin
reading_bit((i%2)? 1'b1 : 1'b0);
end
mdi = 0;
#50
$finish();
end
always
#5 clock = ~clock;
task reading_bit;
input bit;
begin
mdi = bit;
@(posedge mdc);
end
endtask
task writing_bit;
begin
@(posedge mdc);
end
endtask
endmodule
|
// fpgaTop_xupv5.v - ssiegel 2009-03-17
module fpgaTop(
input wire sys0_clkp, // sys0 Clock +
input wire sys0_clkn, // sys0 Clock -
input wire pci0_clkp, // PCIe Clock +
input wire pci0_clkn, // PCIe Clock -
input wire pci0_rstn, // PCIe Reset
output wire [7:0] pci_exp_txp, // PCIe lanes...
output wire [7:0] pci_exp_txn,
input wire [7:0] pci_exp_rxp,
input wire [7:0] pci_exp_rxn,
output wire [2:0] led, // LEDs ml555
input wire ppsExtIn, // PPS in
output wire ppsOut // PPS out
);
// Instance and connect mkFTop...
mkFTop_xupv5 ftop(
.sys0_clkp (sys0_clkp),
.sys0_clkn (sys0_clkn),
.pci0_clkp (pci0_clkp),
.pci0_clkn (pci0_clkn),
.pci0_rstn (pci0_rstn),
.pcie_rxp_i (pci_exp_rxp),
.pcie_rxn_i (pci_exp_rxn),
.pcie_txp (pci_exp_txp),
.pcie_txn (pci_exp_txn),
.led (led),
.gps_ppsSyncIn_x (ppsExtIn),
.gps_ppsSyncOut (ppsOut)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; void solve() { int n, m, k, x, y; cin >> n >> m >> k; for (int i = 0; i < 2 * k; i++) cin >> x >> y; string ans = ; ans += (string(n - 1, U ) + string(m - 1, L )); for (int i = 0; i < n; i++) { if (i & 1) ans += string(m - 1, L ); else ans += string(m - 1, R ); if (i != n - 1) ans += D ; } cout << ans.size() << n ; cout << ans << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); int t = 1; while (t--) { solve(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_PG_TB_V
`define SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_PG_TB_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 UDP_IN = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 UDP_IN = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 UDP_IN = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 UDP_IN = 1'bx;
end
sky130_fd_sc_hvl__udp_pwrgood_pp$PG dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_PG_TB_V
|
#include<iostream> #include<cstring> #include<cstdio> #include<climits> #include<algorithm> #include<queue> #include<vector> #define int long long #define pii pair<int,int> #define mp make_pair #define pb push_back #define fi first #define se second using namespace std; inline int read(){ int f=1,ans=0; char c=getchar(); while(c< 0 ||c> 9 ){if(c== - )f=-1;c=getchar();} while(c>= 0 &&c<= 9 ){ans=ans*10+c- 0 ;c=getchar();} return f*ans; } const int MAXN=15; const int MAXM=101; struct node{int x,y,w;}tp[MAXM]; bool cmp(node x1,node x2){return x1.w<x2.w;} int X[MAXN],Y[MAXN],N,M,f[1<<MAXN][MAXM],INF,g[1<<MAXN][MAXM],Dis[1<<MAXN][MAXN],DIS[1<<MAXN][MAXM],Maxn; signed main(){ //freopen( 1.in , r ,stdin); N=read(),M=read(); for(int i=0;i<N;i++) X[i]=read(),Y[i]=read(); for(int i=1;i<=M;i++) tp[i].x=read(),tp[i].y=read(),tp[i].w=read(); sort(tp+1,tp+M+1,cmp); memset(f,127/3,sizeof(f)); memset(g,-127/3,sizeof(g)); memset(Dis,127/3,sizeof(Dis)); memset(DIS,127/3,sizeof(DIS)); INF=f[0][0]; for(int S=1;S<(1<<N);S++) for(int u=0;u<N;u++){int Minn=INF; for(int v=0;v<N;v++) if(S&(1<<v)) Minn=min(Minn,abs(X[u]-X[v])+abs(Y[u]-Y[v])); Dis[S][u]=Minn;} for(int S=1;S<(1<<N);S++) for(int u=1;u<=M;u++){int Minn=INF; for(int v=0;v<N;v++) if(S&(1<<v)) Minn=min(Minn,abs(X[v]-tp[u].x)+abs(Y[v]-tp[u].y)); DIS[S][u]=Minn;} for(int i=0;i<N;i++) f[1<<i][0]=0; for(int i=1;i<=M;i++) g[0][i]=1; for(int S=0;S<(1<<N);S++){ // f update f for(int i=0;i<=M;i++) if(f[S][i]!=INF) for(int j=0;j<N;j++) if(!(S&(1<<j))) f[S|(1<<j)][i]=min(f[S|(1<<j)][i],f[S][i]+Dis[S][j]); // f update g for(int i=0;i<=M;i++) if(f[S][i]!=INF) for(int j=1;j<=M;j++) if(f[S][i]+DIS[S][j]<=tp[j].w) g[S][j]=max(g[S][j],i+1); //g update g for(int i=1;i<=M;i++) if(g[S][i]>=0){ for(int j=i+1;j<=M;j++) if(tp[i].w+min(abs(tp[i].x-tp[j].x)+abs(tp[i].y-tp[j].y),DIS[S][j])<=tp[j].w) g[S][j]=max(g[S][j],g[S][i]+1); Maxn=max(Maxn,g[S][i]); } //g update f for(int i=1;i<=M;i++) if(g[S][i]>=0) for(int j=0;j<N;j++) if(!(S&(1<<j))) f[S|(1<<j)][g[S][i]]=min(f[S|(1<<j)][g[S][i]],tp[i].w+(min(abs(tp[i].x-X[j])+abs(tp[i].y-Y[j]),Dis[S][j]))); } printf( %lld n ,Maxn); return 0; }/* 3 4 1 1 2 3 5 2 2 2 12 5 1 4 6 2 11 3 5 10 */ |
#include <bits/stdc++.h> using namespace std; int INP() { int n, flag; char c; n = 0; flag = 1; c = getchar(); while (c < 33) { c = getchar(); } if (c == - ) { flag = -1; c = getchar(); } while (c > 32) { n = n * 10 + c - 0 ; c = getchar(); } n = n * flag; return n; } int GCD(int a, int b) { return (a % b == 0 ? b : GCD(b, a % b)); } int main() { int n, i, idx, ans, stop; string s, s1, mx; vector<string> v; cin >> s; n = s.size(); mx = 0 ; for (i = 0; i < n; i++) { s1.push_back(s[i]); if (s[i + 1] != 0 ) { v.push_back(s1); if (s1.size() > mx.size()) { mx = s1; idx = v.size(); } else if (s1.size() == mx.size() && s1 > mx) { mx = s1; idx = v.size(); } s1.clear(); } } s1.clear(); for (i = 0; i < idx; i++) { if (s1.size() > v[i].size()) { stop = min(stop, i - 1); } else if (s1.size() == v[i].size() && s1 >= v[i]) { stop = min(stop, i - 1); } if (s1.size() < v[i].size()) { stop = INT_MAX; } else if (s1.size() == v[i].size() && v[i] > s1) { stop = INT_MAX; } s1 += v[i]; if (s1.size() > mx.size()) { ans = v.size() - min(i, stop); break; } else if (s1.size() == mx.size() && s1 >= mx) { ans = v.size() - min(i, stop); break; } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int T; cin >> T; while (T--) { int N; cin >> N; for (int i = 0; i < N; i++) cout << 1 ; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long k, d; double t; cin >> k >> d >> t; long long time1 = k; long long time2 = 0; if (k % d > 0) { time2 = (k / d + 1) * d - k; } double each_sum = k + (double)time2 / 2; double res = 0; res += (long long)(t / each_sum) * (time1 + time2); t = t - (long long)(t / each_sum) * each_sum; if (t == 0) { printf( %.1f n , res); } else { res += min(t, (double)k); t -= min(t, (double)k); res += t * 2; printf( %.1f n , res); } } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; int p; string s[100]; string s1, s2, s3 = , s4 = , s5 = , s6, s7, s8, s9; for (int i = 0; i < a; i++) { int p = 0; cin >> s[i]; s6 = s[i]; reverse(s6.begin(), s6.end()); if (s[i] == s6) { s7 = s[i]; } } for (int i = 0; i < a - 1; i++) { s2 = s[i]; reverse(s[i].begin(), s[i].end()); for (int j = i + 1; j < a; j++) { if (s[i] == s[j]) { s3 = s3 + s2; s8 = s[j]; s4 = s8 + s4; } } } s9 = s3 + s7 + s4; cout << s9.size() << endl; int l = s9.size(); if (l != 0) { cout << s3 + s7 + s4 << endl; } } |
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const int N = 2e6 + 1; const long long mod = 998244353; long long fact[N]; long long power(long long x, long long n) { long long res = 1; x %= mod; while (n) { if (n & 1) res = (res * x) % mod; x = (x * x) % mod; n >>= 1; } return res; } long long modInv(long long n) { return power(n, mod - 2); } long long ncr(long long n, long long r) { if (n < 0 || r < 0 || r > n) return 0; long long num = fact[n]; long long denom = (fact[n - r] * fact[r]) % mod; return (num * modInv(denom)) % mod; } void pre() { fact[0] = 1; for (int i = 1; i < N; i++) { fact[i] = (fact[i - 1] * i) % mod; } } void solve() { long long n, k; cin >> n >> k; long long y = n - k; if (y < 0) { cout << 0 << n ; return; } long long ans = ncr(n, y); long long sum = 0; for (int i = 0; i <= y; i++) { long long temp = (ncr(y, y - i) * power(y - i, n)) % mod; if (i % 2) { sum = (sum + mod - temp) % mod; } else { sum = (sum + temp) % mod; } } ans = (ans * sum) % mod; if (y != n) { ans = (ans * 2) % mod; } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; std::cout << std::fixed << std::setprecision(20); ; int t = 1; pre(); while (t--) { solve(); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTN_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLXTN_PP_BLACKBOX_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxtn (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTN_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(); cout.tie(0); long long n, p = 0, q = 0, l = 0, i, flag = 0, k, m, t, j, r = 0, curr = 0, d; cin >> n >> m; long long a[n], b[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < n; i++) { cin >> b[i]; } if (a[0] == 0) { cout << NO ; return 0; } if (a[0] != 0) { if (a[m - 1] != 0) { cout << YES ; return 0; } } if (a[m - 1] == 0) { for (long long i = m; i < n; i++) { if (a[i] == 1 && b[i] == 1) { if (b[m - 1] == 1) { flag = 1; break; } } } } if (flag == 1) { cout << YES ; return 0; } cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; pair<int, int> tree[4 * 100005 + 10]; int a[100005]; int dp[100005]; int n, s, l; int f[4 * 100005 + 10]; void init(int node, int b, int e) { if (b == e) { tree[node].first = tree[node].second = a[b]; return; } int mid = (b + e) / 2; int lft = node * 2; int rght = lft + 1; init(lft, b, mid); init(rght, mid + 1, e); tree[node].first = min(tree[lft].first, tree[rght].first); tree[node].second = max(tree[lft].second, tree[rght].second); return; } pair<int, int> query(int node, int b, int e, int i, int j) { if (i <= b && j >= e) return tree[node]; int mid = (b + e) / 2; int lft = node * 2; int rght = lft + 1; if (j <= mid) return query(lft, b, mid, i, j); else if (mid < i) return query(rght, mid + 1, e, i, j); else { pair<int, int> c, d, ans; c = query(lft, b, mid, i, j); d = query(rght, mid + 1, e, i, j); ans.first = min(c.first, d.first); ans.second = max(c.second, d.second); return ans; } } void update_(int node, int b, int e, int indx) { if (b == e) { f[node] = dp[indx]; return; } int mid = (b + e) / 2; if (indx <= mid) update_(node * 2, b, mid, indx); else update_(node * 2 + 1, mid + 1, e, indx); f[node] = min(f[node * 2], f[node * 2 + 1]); } int get(int node, int b, int e, int i, int j) { if (b >= i && j >= e) return f[node]; int mid = (b + e) / 2; int c, d; if (j <= mid) return get(node * 2, b, mid, i, j); else if (mid < i) return get(node * 2 + 1, mid + 1, e, i, j); else { c = get(node * 2, b, mid, i, j); d = get(node * 2 + 1, mid + 1, e, i, j); return min(c, d); } } int solve() { pair<int, int> tmp; if (l > n) return 20000000; tmp = query(1, 1, n, 1, l); if (tmp.second - tmp.first <= s) dp[l] = 1; else return 20000000; int j = 1; update_(1, 1, n, l); for (int i = l + 1; i <= n; i++) { while (j <= i) { tmp = query(1, 1, n, j, i); if (tmp.second - tmp.first <= s) break; j++; } if (i - j + 1 >= l) { if (j == 1) dp[i] = 1; else dp[i] = get(1, 1, n, j - 1, i - l) + 1; } else dp[i] = 20000000; update_(1, 1, n, i); } return dp[n]; } int main() { cin >> n >> s >> l; for (int i = 1; i <= n; i++) scanf( %d , &a[i]); init(1, 1, n); for (int i = 0; i <= 4 * n; i++) f[i] = 20000000; int res = solve(); if (res >= 20000000) cout << -1; else cout << res << endl; return 0; } |
module bram1_tb #(
parameter ABITS = 8, DBITS = 8, TRANSP = 0
);
reg clk;
reg [ABITS-1:0] WR_ADDR;
reg [DBITS-1:0] WR_DATA;
reg WR_EN;
reg [ABITS-1:0] RD_ADDR;
wire [DBITS-1:0] RD_DATA;
localparam [ABITS-1:0] INIT_ADDR_0 = 1234;
localparam [ABITS-1:0] INIT_ADDR_1 = 4321;
localparam [ABITS-1:0] INIT_ADDR_2 = 2**ABITS-1;
localparam [ABITS-1:0] INIT_ADDR_3 = (2**ABITS-1) / 2;
localparam [DBITS-1:0] INIT_DATA_0 = 128'h 51e152a7300e309ccb8cd06d34558f49;
localparam [DBITS-1:0] INIT_DATA_1 = 128'h 07b1fe94a530ddf3027520f9d23ab43e;
localparam [DBITS-1:0] INIT_DATA_2 = 128'h 3cedc6de43ef3f607af3193658d0eb0b;
localparam [DBITS-1:0] INIT_DATA_3 = 128'h f6bc5514a8abf1e2810df966bcc13b46;
bram1 #(
// .ABITS(ABITS),
// .DBITS(DBITS),
// .TRANSP(TRANSP)
) uut (
.clk (clk ),
.WR_ADDR(WR_ADDR),
.WR_DATA(WR_DATA),
.WR_EN (WR_EN ),
.RD_ADDR(RD_ADDR),
.RD_DATA(RD_DATA)
);
reg [63:0] xorshift64_state = 64'd88172645463325252 ^ (ABITS << 24) ^ (DBITS << 16) ^ (TRANSP << 8);
task xorshift64_next;
begin
// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
end
endtask
reg [ABITS-1:0] randaddr1;
reg [ABITS-1:0] randaddr2;
reg [ABITS-1:0] randaddr3;
function [31:0] getaddr(input [3:0] n);
begin
case (n)
0: getaddr = 0;
1: getaddr = 2**ABITS-1;
2: getaddr = 'b101 << (ABITS / 3);
3: getaddr = 'b101 << (2*ABITS / 3);
4: getaddr = 'b11011 << (ABITS / 4);
5: getaddr = 'b11011 << (2*ABITS / 4);
6: getaddr = 'b11011 << (3*ABITS / 4);
7: getaddr = randaddr1;
8: getaddr = randaddr2;
9: getaddr = randaddr3;
default: begin
getaddr = 1 << (2*n-16);
if (!getaddr) getaddr = xorshift64_state;
end
endcase
end
endfunction
reg [DBITS-1:0] memory [0:2**ABITS-1];
reg [DBITS-1:0] expected_rd, expected_rd_masked;
event error;
reg error_ind = 0;
integer i, j;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, bram1_tb);
memory[INIT_ADDR_0] = INIT_DATA_0;
memory[INIT_ADDR_1] = INIT_DATA_1;
memory[INIT_ADDR_2] = INIT_DATA_2;
memory[INIT_ADDR_3] = INIT_DATA_3;
xorshift64_next;
xorshift64_next;
xorshift64_next;
xorshift64_next;
randaddr1 = xorshift64_state;
xorshift64_next;
randaddr2 = xorshift64_state;
xorshift64_next;
randaddr3 = xorshift64_state;
xorshift64_next;
clk <= 0;
for (i = 0; i < 512; i = i+1) begin
if (i == 0) begin
WR_EN <= 0;
RD_ADDR <= INIT_ADDR_0;
end else
if (i == 1) begin
WR_EN <= 0;
RD_ADDR <= INIT_ADDR_1;
end else
if (i == 2) begin
WR_EN <= 0;
RD_ADDR <= INIT_ADDR_2;
end else
if (i == 3) begin
WR_EN <= 0;
RD_ADDR <= INIT_ADDR_3;
end else begin
if (DBITS > 64)
WR_DATA <= (xorshift64_state << (DBITS-64)) ^ xorshift64_state;
else
WR_DATA <= xorshift64_state;
xorshift64_next;
WR_ADDR <= getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
xorshift64_next;
RD_ADDR <= getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
WR_EN <= xorshift64_state[55];
xorshift64_next;
end
#1; clk <= 1;
#1; clk <= 0;
if (TRANSP) begin
if (WR_EN) memory[WR_ADDR] = WR_DATA;
expected_rd = memory[RD_ADDR];
end else begin
expected_rd = memory[RD_ADDR];
if (WR_EN) memory[WR_ADDR] = WR_DATA;
end
for (j = 0; j < DBITS; j = j+1)
expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j];
$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd, expected_rd_masked === RD_DATA ? "ok" : "ERROR");
if (expected_rd_masked !== RD_DATA) begin -> error; error_ind = ~error_ind; end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, s; scanf( %d%d%d , &a, &b, &s); int req = abs(a) + abs(b); if (req > s) { printf( No n ); } else { int cur = s - req; if (cur & 1) { printf( No n ); } else { printf( Yes n ); } } return 0; } |
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module altera_mem_if_ddr3_phy_0001_read_valid_selector(
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2**MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latency_shifter;
input [MAX_LATENCY_COUNT_WIDTH-1:0] latency_counter;
output read_enable;
output read_valid;
wire [LATENCY_NUM-1:0] selector;
reg [LATENCY_NUM-1:0] selector_reg;
reg read_enable;
reg reading_data;
reg read_valid;
wire [LATENCY_NUM-1:0] valid_select;
lpm_decode uvalid_select(
.data (latency_counter),
.eq (selector)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock (),
.enable ()
// synopsys translate_on
);
defparam uvalid_select.lpm_decodes = LATENCY_NUM;
defparam uvalid_select.lpm_type = "LPM_DECODE";
defparam uvalid_select.lpm_width = MAX_LATENCY_COUNT_WIDTH;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
selector_reg <= {LATENCY_NUM{1'b0}};
else
selector_reg <= selector;
end
assign valid_select = selector_reg & latency_shifter;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
begin
read_enable <= 1'b0;
read_valid <= 1'b0;
end
else
begin
read_enable <= |valid_select;
read_valid <= |valid_select;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND2_1_V
`define SKY130_FD_SC_HDLL__TAPVGND2_1_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog wrapper for tapvgnd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__tapvgnd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__tapvgnd2_1 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__tapvgnd2 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__tapvgnd2_1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__tapvgnd2 base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND2_1_V
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, d; cin >> n >> d; int a[n]; int count = 0; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (j == i) continue; if (abs(a[i] - a[j]) <= d) count++; } } cout << count << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e3 + 5; struct node { int l, r; } num[MAXN]; int cmp(node x, node y) { return x.r < y.r; } int main() { int N; vector<int> v; v.clear(); scanf( %d , &N); for (int i = 0; i < N; i++) { scanf( %d%d , &num[i].l, &num[i].r); if (num[i].r < num[i].l) { int temp = num[i].l; num[i].l = num[i].r; num[i].r = temp; } } sort(num, num + N, cmp); v.push_back(num[0].r); for (int i = 1; i < N; i++) { if (num[i].l > v.back()) { v.push_back(num[i].r); } } printf( %d n , v.size()); for (int i = 0; i < v.size(); i++) printf( %d , v[i]); printf( n ); return 0; } |
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module videosync(
input CLK_24MB,
input LSPC_3M,
input LSPC_1_5M,
input Q53_CO,
input RESETP,
input VMODE,
output [8:0] PIXELC,
output [8:0] RASTERC,
output SYNC,
output BNK,
output BNKB,
output CHBL,
output R15_QD,
output FLIP,
output nFLIP,
output P50_CO
);
wire [3:0] S122_REG;
wire [3:0] R15_REG;
wire [3:0] T116_REG;
assign R15_QD = R15_REG[3];
FDPCell H287(J22_OUT, H287_nQ, 1'b1, RESETP, H287_Q, H287_nQ);
assign nFLIP = ~H287_Q;
assign FLIP = ~H287_nQ;
// Pixel counter
// Used for test mode
assign P40A_OUT = P50_CO | 1'b0;
assign PIXELC = {P15_QC, P15_QB, P15_QA, P50_QD, P50_QC, P50_QB, P50_QA, LSPC_1_5M, LSPC_3M};
C43 P50(CLK_24MB, 4'b1110, RESETP, Q53_CO, 1'b1, 1'b1, {P50_QD, P50_QC, P50_QB, P50_QA}, P50_CO);
C43 P15(CLK_24MB, {3'b101, ~RESETP}, P13B_OUT, Q53_CO, P40A_OUT, 1'b1, {P15_QD, P15_QC, P15_QB, P15_QA}, P15_CO);
assign P39B_OUT = P15_CO & Q53_CO;
assign P13B_OUT = ~|{P39B_OUT, ~RESETP};
// Raster counter
// Used for test mode
assign J22_OUT = P15_QC ^ 1'b0;
assign H284A_OUT = I269_CO | 1'b0;
C43 I269(J22_OUT, {~VMODE, 3'b100}, ~J268_CO, FLIP, FLIP, RESETP, RASTERC[4:1], I269_CO);
C43 J268(J22_OUT, {3'b011, ~VMODE}, ~J268_CO, H284A_OUT, H284A_OUT, RESETP, RASTERC[8:5], J268_CO);
assign RASTERC[0] = FLIP;
// H277B H269B H275A
assign MATCH_PAL = ~&{RASTERC[4:3]} | RASTERC[5] | RASTERC[8];
FDM H272(RASTERC[2], MATCH_PAL, H272_Q, );
FDM I238(FLIP, H272_Q, BLANK_PAL, );
// J259A
assign MATCH_NTSC = ~&{RASTERC[7:5]};
// J251
FD4 J251(~RASTERC[4], MATCH_NTSC, 1'b1, RESETP, BLANK_NTSC, );
// J240A: T2E
assign VSYNC = VMODE ? BLANK_PAL : RASTERC[8];
assign BNK = ~(VMODE ? RASTERC[8] : BLANK_NTSC);
// K15B
assign BNKB = ~BNK;
assign #1 S136A_OUT = ~LSPC_1_5M;
// P13A
assign #1 nPIXEL_H256 = ~P15_QC;
assign P13A_OUT = P15_QA & nPIXEL_H256;
FS1 R15(S136A_OUT, P13A_OUT, R15_REG);
BD3 S51(R15_REG[3], S51_OUT);
FS1 T116(S136A_OUT, ~S51_OUT, T116_REG);
BD3 U127(T116_REG[3], U127_OUT);
FS1 S122(S136A_OUT, ~U127_OUT, S122_REG);
BD3 S119A(S122_REG[3], S119_OUT);
FD2 S116(S136A_OUT, S119_OUT, S116_Q, );
// S131A
assign HSYNC = ~&{S116_Q, ~T116_REG[1]};
// M149
assign SYNC = ~^{HSYNC, VSYNC};
// L40A
assign CHBL = ~&{BNKB, R15_REG[3]};
endmodule
|
//-------------------------------------------------------------------------
// COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//-------------------------------------------------------------------------
// Title : adc_frontend
// Author : Caleb Fangmeier
// Description : Frontend for reading adc data.
//
// $Id$
//-------------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module adc_frontend (
input wire clk, // 133 MHz
input wire reset,
output wire adc_clk, // 13.3 MHz
//--------------------------------------------------------------------------
//------------------------CONTROL INTERFACE---------------------------------
//--------------------------------------------------------------------------
input wire write_req,
input wire read_req,
input wire [31:0] data_write,
output reg [31:0] data_read,
input wire [25:0] addr,
output wire busy,
//--------------------------------------------------------------------------
//---------------------------HW INTERFACE-----------------------------------
//--------------------------------------------------------------------------
input wire [7:0] adc_fco,
input wire [7:0] adc_dco,
input wire [7:0] adc_dat_a,
input wire [7:0] adc_dat_b,
input wire [7:0] adc_dat_c,
input wire [7:0] adc_dat_d
);
//----------------------------------------------------------------------------
// Parameters
//----------------------------------------------------------------------------
localparam IDLE = 2'd0,
READ_0 = 2'd1,
READ_1 = 2'd2;
//----------------------------------------------------------------------------
// Registers
//----------------------------------------------------------------------------
reg [7:0] read_enable;
reg [7:0] buffer_rdreq;
reg busy_int;
reg [25:0] addr_int;
reg [1:0] state;
//----------------------------------------------------------------------------
// Wires
//----------------------------------------------------------------------------
wire [7:0] deser_busy;
wire [7:0] buffer_empty;
wire [9:0] buffer_data_a[7:0];
wire [9:0] buffer_data_b[7:0];
wire [9:0] buffer_data_c[7:0];
wire [9:0] buffer_data_d[7:0];
//----------------------------------------------------------------------------
// Assignments
//----------------------------------------------------------------------------
assign busy = reset | busy_int | write_req | read_req;
//----------------------------------------------------------------------------
// Clocked Logic
//----------------------------------------------------------------------------
always @( posedge clk ) begin
if ( reset ) begin
read_enable <= 8'd0;
buffer_rdreq <= 8'd0;
data_read <= 32'd0;
busy_int <= 0;
state <= IDLE;
end
else begin
buffer_rdreq <= 8'd0;
data_read <= 32'd0;
case ( state )
IDLE: begin
if ( read_req ) begin
busy_int <= 1;
state <= READ_0;
addr_int <= addr;
end
else if ( write_req ) begin
read_enable <= {8{data_write[0]}};
end
end
READ_0: begin
if ( ~buffer_empty[addr_int[4:2]] ) begin
state <= READ_1;
buffer_rdreq[addr_int[4:2]] <= 1;
end
end
READ_1: begin
// TODO: Handle all ADC channels w/o dropping data
state <= IDLE;
busy_int <= 0;
case ( addr_int[1:0] )
2'b00: begin
data_read <= {22'd1, buffer_data_a[addr_int[4:2]]};
end
1'b01: begin
data_read <= {22'd1, buffer_data_b[addr_int[4:2]]};
end
2'b10: begin
data_read <= {22'd1, buffer_data_c[addr_int[4:2]]};
end
2'b11: begin
data_read <= {22'd1, buffer_data_d[addr_int[4:2]]};
end
endcase
end
endcase
end
end
generate
genvar i;
for ( i=0; i<8; i=i+1 ) begin: my_loop
adc_deser adc_deser_inst (
.clk ( clk ),
.reset ( reset ),
.read_enable ( read_enable[i] ),
.buffer_rdreq ( buffer_rdreq[i] ),
.buffer_empty ( buffer_empty[i] ),
.buffer_data_a ( buffer_data_a[i] ),
.buffer_data_b ( buffer_data_b[i] ),
.buffer_data_c ( buffer_data_c[i] ),
.buffer_data_d ( buffer_data_d[i] ),
.adc_fco ( adc_fco[i] ),
.adc_dco ( adc_dco[i] ),
.adc_dat_a ( adc_dat_a[i] ),
.adc_dat_b ( adc_dat_b[i] ),
.adc_dat_c ( adc_dat_c[i] ),
.adc_dat_d ( adc_dat_d[i] )
);
end
endgenerate
adc_pll adc_pll_inst (
.areset ( 1'b0 ),
.inclk0 ( clk ),
.c0 ( adc_clk ),
.locked ( )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; map<long long int, long long int> m; int main() { long long int t; cin >> t; while (t--) { long long int n; cin >> n; long long int a[n]; for (long long int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); long long int x = 0, y = n - 1, iff = 1; vector<long long int> v; for (long long int i = 0; i < n; i++) { if (iff) { v.push_back(a[y]); y--; iff = 0; } else { v.push_back(a[x]); x++; iff = 1; } } for (long long int i = n - 1; i >= 0; i--) cout << v[i] << ; cout << endl; } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// A test case for parameterized module.
//
// When a module is instantiatied with parameter, there will be two modules in
// the tree and eventually one will be removed after param and deadifyModules.
//
// This test is to check that the removal of dead module will not cause
// compilation error. Possible error was/is seen as:
//
// pure virtual method called
// terminate called without an active exception
// %Error: Verilator aborted. Consider trying --debug --gdbbt
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jie Xu.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [71:0] ctrl;
wire [7:0] cl; // this line is added
memory #(.words(72)) i_memory (.clk (clk));
assign ctrl = i_memory.mem[0];
assign cl = i_memory.mem[0][7:0]; // and this line
endmodule
// memory module, which is used with parameter
module memory (clk);
input clk;
parameter words = 16384, bits = 72;
reg [bits-1 :0] mem[words-1 : 0];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long A[10][10] = {}; void rec(long long x, long long y, long long n) { if ((n % 2) == 0) { A[x][y] = n + 1; } if (n == 0) return; else { long long arrx[] = {-2, 2}; long long arry[] = {-1, 1}; for (auto i : arrx) { for (auto j : arry) { long long newx = x + i, newy = y + j; if (newx >= 0 && newx < 10 && newy >= 0 && newy < 10) { { cerr << > << newx << : << newx << , << newy << : << newy << endl; }; if (A[newx][newy] < n) rec(newx, newy, n - 1); } } } for (auto j : arrx) { for (auto i : arry) { long long newx = x + i, newy = y + j; if (newx >= 0 && newx < 10 && newy >= 0 && newy < 10) { { cerr << > << newx << : << newx << , << newy << : << newy << endl; }; if (A[newx][newy] < n) rec(newx, newy, n - 1); } } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { double n, h; cin >> n >> h; double f = h / sqrt(n); cout << setprecision(9); for (long long i = 0; i < n - 1; i++) { cout << f * sqrt(i + 1) << ; } } } |
#include <bits/stdc++.h> using namespace std; pair<int, int> seg[2100000], lazy[2100000]; pair<int, int> Merge(pair<int, int> l, pair<int, int> r) { if (l < r) return l; else return r; } void Propagate(int n, int l, int r) { if (lazy[n] != make_pair(0x3f3f3f3f, 0)) { if (l != r) { lazy[n << 1] = Merge(lazy[n << 1], lazy[n]); lazy[n << 1 | 1] = Merge(lazy[n << 1 | 1], lazy[n]); } seg[n] = Merge(seg[n], lazy[n]); lazy[n] = make_pair(0x3f3f3f3f, 0); } } pair<int, int> Update(int L, int R, pair<int, int> val, int n, int l, int r) { Propagate(n, l, r); if (r < L || R < l) return seg[n]; if (L <= l && r <= R) { lazy[n] = Merge(lazy[n], val); Propagate(n, l, r); return seg[n]; } int mid = l + r >> 1; return seg[n] = Merge(Update(L, R, val, n << 1, l, mid), Update(L, R, val, n << 1 | 1, mid + 1, r)); } pair<int, int> Query(int L, int R, int n, int l, int r) { Propagate(n, l, r); if (r < L || R < l) return make_pair(0x3f3f3f3f, 0); if (L <= l && r <= R) return seg[n]; int mid = l + r >> 1; return Merge(Query(L, R, n << 1, l, mid), Query(L, R, n << 1 | 1, mid + 1, r)); } int N, M; vector<pair<int, int> > v[300001]; pair<int, int> dp[300001]; int main() { for (int i = 0; i < 2100000; i++) seg[i] = lazy[i] = make_pair(0x3f3f3f3f, 0); ios::sync_with_stdio(0); cin.tie(0); cin.exceptions(ios::badbit | ios::failbit); cin >> N >> M; vector<int> com; for (int i = 1; i <= M; i++) { int n, l, r; cin >> n >> l >> r; r++; v[n].push_back({l, r}); com.push_back(l); com.push_back(r); } sort(com.begin(), com.end()); com.erase(unique(com.begin(), com.end()), com.end()); for (int i = 1; i <= N; i++) for (auto &[l, r] : v[i]) { l = lower_bound(com.begin(), com.end(), l) - com.begin(); r = lower_bound(com.begin(), com.end(), r) - com.begin(); } for (int i = 1; i <= N; i++) { dp[i] = {i - 1, 0}; for (auto [l, r] : v[i]) { auto it = Query(l, r - 1, 1, 0, (int)com.size() - 1); dp[i] = min(dp[i], make_pair(it.first + i, it.second)); } for (auto [l, r] : v[i]) { Update(l, r - 1, make_pair(dp[i].first - i - 1, i), 1, 0, (int)com.size() - 1); } } int res = 0x3f3f3f3f, n = 0; for (int i = 1; i <= N; i++) { int val = dp[i].first + (N - i); if (res > val) res = val, n = i; } set<int> s; for (int i = 1; i <= N; i++) s.insert(i); while (n) { s.erase(n); n = dp[n].second; } cout << res << n ; if (res) { for (int i : s) cout << i << ; cout << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311AI_BLACKBOX_V
`define SKY130_FD_SC_HD__O311AI_BLACKBOX_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o311ai (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311AI_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__OR2_FUNCTIONAL_PP_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4BB_TB_V
`define SKY130_FD_SC_LP__AND4BB_TB_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_lp__and4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4BB_TB_V
|
#include <bits/stdc++.h> int a[100], i, j, maxim, h, l, n, b; int main() { scanf( %d , &n); scanf( %d , &l); for (i = 0; i < n; i++) { scanf( %d , &a[i]); } i = 0; j = 0; b = 0; h = l; maxim = l; while (i < n) { if (l % a[i] == 0) { h = l / a[i]; } if (h < maxim) maxim = h; i++; } printf( %d , maxim); } |
#include <bits/stdc++.h> using namespace std; const int inf = 2e9; const long long INF = 4e17; const int mod = 1e9 + 7; const double eps = 1e-9; const int N = 2e5 + 10; long long n, arr[N], tree[N << 2], lazy[N << 2]; void build(int node = 1, int L = 1, int R = n) { if (L == R) { tree[node] = arr[L]; lazy[node] = 0; return; } int mid = (L + R) >> 1, lc = node << 1, rc = lc | 1; build(lc, L, mid), build(rc, mid + 1, R); tree[node] = tree[lc] + tree[rc]; } void set0(int l, int r, int node = 1, int L = 1, int R = n) { if (r < L || R < l || r < l) return; if (l <= L && R <= r) { tree[node] = 0; lazy[node] = 1; return; } int mid = (L + R) >> 1, lc = node << 1, rc = lc | 1; if (lazy[node]) return; set0(l, r, lc, L, mid), set0(l, r, rc, mid + 1, R); tree[node] = tree[lc] + tree[rc]; } void upd(int pos, int v, int node = 1, int L = 1, int R = n) { if (L == R) { tree[node] += v; return; } int mid = (L + R) >> 1, lc = node << 1, rc = lc | 1; if (pos <= mid) upd(pos, v, lc, L, mid); else upd(pos, v, rc, mid + 1, R); tree[node] = tree[lc] + tree[rc]; } long long getsum(int l, int r, int node = 1, int L = 1, int R = n) { if (r < L || R < l) return 0; if (l <= L && R <= r) return tree[node]; if (lazy[node]) return 0; int mid = (L + R) >> 1, lc = node << 1, rc = lc | 1; return getsum(l, r, lc, L, mid) + getsum(l, r, rc, mid + 1, R); } long long getcap(int pos, int node = 1, int L = 1, int R = n) { if (L == R) return tree[node]; if (lazy[node]) return 0; int mid = (L + R) >> 1, lc = node << 1, rc = lc | 1; if (pos <= mid) return getcap(pos, lc, L, mid); return getcap(pos, rc, mid + 1, R); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &arr[i]); int m; scanf( %d , &m); build(); while (m--) { long long t, x, p, k; scanf( %lld , &t); if (t == 1) { scanf( %lld %lld , &p, &x); long long cap = getcap(p); if (cap > x) { if (!1) cout << no overflow decrease << x << from cap n ; upd(p, -x); if (!1) cout << at << p << now << getcap(p) << n ; } else { long long got = 0; int lo = p, hi = n, pos = n + 1; while (lo <= hi) { int mid = (lo + hi) >> 1; got = getsum(p, mid); if (!1) cout << from << p << -> << mid << sum << got << n ; if (got >= x) hi = mid - 1, pos = mid; else lo = mid + 1; } long long usedup = getsum(p, pos - 1); if (!1) cout << overflow ends at << pos << and used up << usedup << out of << x << n ; upd(pos, usedup - x); if (!1) cout << set 0 to all in << p << -> << pos - 1 << n ; set0(p, pos - 1); } } else { scanf( %lld , &k); if (!1) cout << found << getcap(k) << amount left n ; printf( %lld n , arr[k] - getcap(k)); } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int sieve[1000003 + 5]; long long int num_primes[1000005] = {0}; void calc_sieve() { for (long long int i = 0; i <= 1000003; i++) sieve[i] = 0; sieve[0] = sieve[1] = 1; for (long long int i = 2; i <= 1000003; i++) { num_primes[i] = num_primes[i - 1]; if (sieve[i] == 0) { num_primes[i]++; for (long long int j = i + i; j <= 1000003; j = j + i) sieve[j]++; } } } long long int ans = -1; bool check(long long int a, long long int b, long long int l, long long int k) { for (long long int i = a; i <= b - l + 1; i++) { if (num_primes[i + l - 1] - num_primes[i - 1] < k) return false; } ans = l; return true; } void binary_search_primes(long long int a, long long int b, long long int k, long long int start, long long int end) { if (end - start <= 1) { if (!check(a, b, start, k)) check(a, b, end, k); return; } long long int mid = (start + end) / 2; if (check(a, b, mid, k)) { binary_search_primes(a, b, k, start, mid - 1); } else { binary_search_primes(a, b, k, mid + 1, end); } } int main() { calc_sieve(); long long int a, b, k; cin >> a >> b >> k; binary_search_primes(a, b, k, 1, b - a + 1); cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, arr[100003], pre[100003], suf[100003]; int bitidx; bool cmp(long long a, long long b) { return ((a >> bitidx) & 1) < ((b >> bitidx) & 1); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; pre[0] = 0; for (int i = 0; i < n; i++) { cin >> arr[i]; pre[i + 1] = pre[i] ^ arr[i]; } suf[0] = 0; for (int i = 0; i < n; i++) suf[i + 1] = suf[i] ^ arr[n - i - 1]; sort(suf, suf + n + 1); long long mx = 0; for (int k = 0; k <= n; k += 1) { int st = 0, en = n; for (int i = 40; i >= 0; i -= 1) { int bit = (pre[k] >> i) & 1; bitidx = i; int pos = lower_bound(suf + st, suf + en + 1, (1LL << i), cmp) - suf; if (pos > en) continue; if (!bit) st = pos; else en = pos - 1; } mx = max(mx, pre[k] ^ suf[st]); } cout << mx; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, i, g, a[100001], p[100001], maxi; vector<long long> v; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; p[a[i]] = i + 1; } g = 1; for (i = 1; i < n; i++) { if (p[i] <= p[i + 1]) { g++; } else { v.push_back(g); g = 1; } } v.push_back(g); maxi = 0; for (i = 0; i < v.size(); i++) { maxi = max(maxi, v[i]); } cout << n - maxi; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_denorm_3to1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Reduce three fpu_denorm_3b results to one set of results.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_denorm_3to1 (
din2_din1_nz_hi,
din2_din1_denorm_hi,
din2_din1_nz_mid,
din2_din1_denorm_mid,
din2_din1_nz_lo,
din2_din1_denorm_lo,
din2_din1_nz,
din2_din1_denorm
);
input din2_din1_nz_hi; // input 1 and input 2 != 0- high 3 bits
input din2_din1_denorm_hi; // input 1 == denorm- high 3 bits
input din2_din1_nz_mid; // input 1 and input 2 != 0- mid 3 bits
input din2_din1_denorm_mid; // input 1 == denorm- mid 3 bits
input din2_din1_nz_lo; // input 1 and input 2 != 0- low 3 bits
input din2_din1_denorm_lo; // input 1 == denorm- low 3 bits
output din2_din1_nz; // input 1 and input 2 != 0
output din2_din1_denorm; // input 1 == denorm
wire din2_din1_nz;
wire din2_din1_denorm;
assign din2_din1_nz= din2_din1_nz_hi || din2_din1_nz_mid
|| din2_din1_nz_lo;
assign din2_din1_denorm= (din2_din1_nz_hi && din2_din1_denorm_hi)
|| ((!din2_din1_nz_hi) && din2_din1_nz_mid
&& din2_din1_denorm_mid)
|| ((!din2_din1_nz_hi) && (!din2_din1_nz_mid)
&& din2_din1_denorm_lo);
endmodule
|
// megafunction wizard: %Shift register (RAM-based)%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTSHIFT_TAPS
// ============================================================
// File Name: delay_5.v
// Megafunction Name(s):
// ALTSHIFT_TAPS
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module delay_5 (
clken,
clock,
shiftin,
shiftout,
taps);
input clken;
input clock;
input [7:0] shiftin;
output [7:0] shiftout;
output [39:0] taps;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [39:0] sub_wire1;
wire [7:0] shiftout = sub_wire0[7:0];
wire [39:0] taps = sub_wire1[39:0];
altshift_taps ALTSHIFT_TAPS_component (
.clock (clock),
.clken (clken),
.shiftin (shiftin),
.shiftout (sub_wire0),
.taps (sub_wire1)
// synopsys translate_off
,
.aclr ()
// synopsys translate_on
);
defparam
ALTSHIFT_TAPS_component.intended_device_family = "Cyclone II",
ALTSHIFT_TAPS_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
ALTSHIFT_TAPS_component.lpm_type = "altshift_taps",
ALTSHIFT_TAPS_component.number_of_taps = 5,
ALTSHIFT_TAPS_component.tap_distance = 640,
ALTSHIFT_TAPS_component.width = 8;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "5"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "640"
// Retrieval info: PRIVATE: WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "5"
// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "640"
// Retrieval info: CONSTANT: WIDTH NUMERIC "8"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: shiftin 0 0 8 0 INPUT NODEFVAL "shiftin[7..0]"
// Retrieval info: USED_PORT: shiftout 0 0 8 0 OUTPUT NODEFVAL "shiftout[7..0]"
// Retrieval info: USED_PORT: taps 0 0 40 0 OUTPUT NODEFVAL "taps[39..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @shiftin 0 0 8 0 shiftin 0 0 8 0
// Retrieval info: CONNECT: shiftout 0 0 8 0 @shiftout 0 0 8 0
// Retrieval info: CONNECT: taps 0 0 40 0 @taps 0 0 40 0
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_5.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_5.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_5.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_5.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_5_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_5_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const long double pi = acos(-1); const int n_ = 1e5 + 5; int n; long long a[n_], b[n_], dp[n_]; vector<int> st; vector<long double> p; long double getIntersect(int i, int j) { return (dp[j] - dp[i]) / (long double)(b[i] - b[j]); } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lld , a + i); for (int i = 0; i < n; i++) scanf( %lld , b + i); dp[0] = b[0]; st.push_back(0); p.push_back(2e9); int id; for (int i = 1; i < n; i++) { id = lower_bound(p.begin(), p.end(), (long double)a[i] - 1) - p.begin(); dp[i] = dp[st[id]] + b[st[id]] * (a[i] - 1) + b[i]; while (st.size() > 1 && getIntersect(st[st.size() - 2], st.back()) > getIntersect(st.back(), i)) { st.pop_back(); p.pop_back(); } p.back() = getIntersect(st.back(), i); p.push_back(2e9); st.push_back(i); } printf( %lld , dp[n - 1]); return 0; } |
#include <bits/stdc++.h> using namespace std; int r, h; int main() { scanf( %d%d , &r, &h); double tt = h + r * 1.0 / 2; double re = tt / r - (int)(tt / r); int ans; if (fabs(re) < 0.00001) { ans = (int)(tt / r) * 2; } else { ans = (int)(tt / r) * 2; re = h + r - (int)(tt / r) * r; double mm = re - sqrt(3.0) / 2 * r; if (mm > 0.00001) ans++; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p, q, r, s, t, u, v, w, x, y, z, ans, maxi, mini, res; string s1, s2; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> x; if (x == 2) cout << 2; else cout << 1; return 0; } |
`timescale 1ns/10ps
module rs232(input wire clk,
input wire rst,
// Master connections
input wire `REQ rs232_req,
output wire `RES rs232_res,
input wire rs232in_attention,
input wire [7:0] rs232in_data,
input wire rs232out_busy,
output wire rs232out_w,
output wire [7:0] rs232out_d);
parameter debug = 1;
`ifdef __ICARUS__
parameter inputtext = "input.txt";
integer file, ch = 32, rs232in_pending = 0;
`endif
reg [31:0] tsc = 0; // A free running counter....
reg [ 7:0] rs232in_cnt = 0;
wire [31:0] addr = rs232_req`A;
reg [31:0] rd_data = 0;
assign rs232_res`RD = rd_data;
assign rs232_res`HOLD = 0;
always @(posedge clk)
if (rst) begin
rd_data <= 0;
tsc <= 0;
rs232in_cnt <= 0;
end else begin
`ifdef __ICARUS__
if (rs232out_w)
$display("*** serial output '%c' ***", rs232out_d);
`endif
rd_data <= 0;
tsc <= tsc + 1;
`ifndef __ICARUS__
if (rs232in_attention)
rs232in_cnt <= rs232in_cnt + 1'h1;
`endif
if (rs232_req`R) begin
`ifdef __ICARUS__
case (addr[3:2])
0: rd_data <= 0;
1: begin
$display("*** serial input '%c' ***", ch);
rd_data <= {24'h0,ch}; // 4
rs232in_pending = 0;
end
2: begin
if (rs232in_pending > 1) begin
rs232in_pending = rs232in_pending - 1;
if (rs232in_pending == 1) begin
rs232in_cnt = rs232in_cnt + 1;
end
end
rd_data <= {24'h0,rs232in_cnt}; // 8
end
3: rd_data <= tsc; // 12
endcase
if (!rs232in_pending) begin
ch = $fgetc(file);
if (ch != -1)
rs232in_pending = 3; // Minimum 2
end
`else
case (addr[3:2])
0: rd_data <= {31'h0,rs232out_busy};// 0
1: rd_data <= {24'h0,rs232in_data}; // 4
2: rd_data <= {24'h0,rs232in_cnt}; // 8
3: rd_data <= tsc; // 12
endcase
`endif
end
end
// wire rs232en = (peri_ctrl_req`A & 'hFFF0) == 'h0000;
wire [31:0] rs232_writedata = rs232_req`WD;
assign rs232out_d = rs232_writedata[7:0];
assign rs232out_w = rs232_req`W & addr[3:0] == 0;
`ifdef __ICARUS__
initial begin
file = $fopen(inputtext, "r");
$display("Opening of %s resulted in %d", inputtext, file);
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 102; char a[N][N][N]; int main() { int n, m, p; int i, j, k, l; scanf( %d%d%d , &n, &m, &p); for (i = 0; i < n; i++) { for (j = 0; j < m; j++) scanf( n%s , &a[i][j][0]); for (j = 0; j < m; j++) for (k = 0; k < p; k++) if (a[i][j][k] == 0 ) a[i][j][k] = 0; if (i != n - 1) scanf( n ); } int s = 0; for (i = 0; i < n; i++) for (j = 0; j < m; j++) for (k = 0; k < p; k++) if (a[i][j][k]) { if (k - 1 >= 0 && k + 1 < p && a[i][j][k - 1] && a[i][j][k + 1]) s++; else if (j - 1 >= 0 && j + 1 < m && a[i][j - 1][k] && a[i][j + 1][k]) s++; else if (i - 1 >= 0 && i + 1 < n && a[i - 1][j][k] && a[i + 1][j][k]) s++; else if (i - 1 >= 0 && j + 1 < m && a[i - 1][j][k] && a[i][j + 1][k] && !a[i - 1][j + 1][k]) s++; else if (i - 1 >= 0 && k + 1 < p && a[i - 1][j][k] && a[i][j][k + 1] && !a[i - 1][j][k + 1]) s++; else if (j - 1 >= 0 && i + 1 < n && a[i][j - 1][k] && a[i + 1][j][k] && !a[i + 1][j - 1][k]) s++; else if (j - 1 >= 0 && k + 1 < p && a[i][j - 1][k] && a[i][j][k + 1] && !a[i][j - 1][k + 1]) s++; else if (k - 1 >= 0 && i + 1 < n && a[i][j][k - 1] && a[i + 1][j][k] && !a[i + 1][j][k - 1]) s++; else if (k - 1 >= 0 && j + 1 < m && a[i][j][k - 1] && a[i][j + 1][k] && !a[i][j + 1][k - 1]) s++; {} } printf( %d , s); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_4_V
`define SKY130_FD_SC_LS__A32O_4_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a32o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a32o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a32o_4 (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a32o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_4_V
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Generic source synchronous SDR input
*/
module ssio_sdr_in #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire input_clk,
input wire [WIDTH-1:0] input_d,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
wire clk_int;
wire clk_io;
generate
if (TARGET == "XILINX") begin
// use Xilinx clocking primitives
if (CLOCK_INPUT_STYLE == "BUFG") begin
// buffer RX clock
BUFG
clk_bufg (
.I(input_clk),
.O(clk_int)
);
// pass through RX clock to logic and input buffers
assign clk_io = clk_int;
assign output_clk = clk_int;
end else if (CLOCK_INPUT_STYLE == "BUFR") begin
assign clk_int = input_clk;
// pass through RX clock to input buffers
BUFIO
clk_bufio (
.I(clk_int),
.O(clk_io)
);
// pass through RX clock to logic
BUFR #(
.BUFR_DIVIDE("BYPASS")
)
clk_bufr (
.I(clk_int),
.O(output_clk),
.CE(1'b1),
.CLR(1'b0)
);
end else if (CLOCK_INPUT_STYLE == "BUFIO") begin
assign clk_int = input_clk;
// pass through RX clock to input buffers
BUFIO
clk_bufio (
.I(clk_int),
.O(clk_io)
);
// pass through RX clock to MAC
BUFG
clk_bufg (
.I(clk_int),
.O(output_clk)
);
end else if (CLOCK_INPUT_STYLE == "BUFIO2") begin
// pass through RX clock to input buffers
BUFIO2 #(
.DIVIDE(1),
.DIVIDE_BYPASS("TRUE"),
.I_INVERT("FALSE"),
.USE_DOUBLER("FALSE")
)
clk_bufio (
.I(input_clk),
.DIVCLK(clk_int),
.IOCLK(clk_io),
.SERDESSTROBE()
);
// pass through RX clock to MAC
BUFG
clk_bufg (
.I(clk_int),
.O(output_clk)
);
end
end else begin
// pass through RX clock to input buffers
assign clk_io = input_clk;
// pass through RX clock to logic
assign clk_int = input_clk;
assign output_clk = clk_int;
end
endgenerate
(* IOB = "TRUE" *)
reg [WIDTH-1:0] output_q_reg = {WIDTH{1'b0}};
assign output_q = output_q_reg;
always @(posedge clk_io) begin
output_q_reg <= input_d;
end
endmodule
|
#include <bits/stdc++.h> int main() { long double val = 0.0; unsigned transistors = 0, seconds = 0; std::cin >> transistors >> seconds; std::cout.precision(25); std::cout << (long double)transistors * powl(1.000000011, (long double)seconds) << std::endl; return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long getnum() { char c = getchar(); long long num, sign = 1; for (; c < 0 || c > 9 ; c = getchar()) if (c == - ) sign = -1; for (num = 0; c >= 0 && c <= 9 ;) { c -= 0 ; num = num * 10 + c; c = getchar(); } return num * sign; } long long A[3004], C[3004], B[1004]; vector<long long> V[3004], W[3004]; priority_queue<int, vector<int>, greater<int>> PQ; int main() { int n = getnum(), m = getnum(); for (int i = 1; i <= n; i++) { A[i] = getnum(); B[A[i]]++; C[i] = getnum(); V[A[i]].push_back(C[i]); W[A[i]].push_back(C[i]); } for (int i = 1; i <= m; i++) { sort(V[i].begin(), V[i].end()); sort(W[i].begin(), W[i].end()); for (int j = 1; j < V[i].size(); j++) V[i][j] += V[i][j - 1]; } long long ans = LLONG_MAX; int l = 1, r = n; for (int mid = 1; mid <= n; mid++) { int can = B[1]; long long sum = 0; for (int i = 2; i <= m; i++) { for (int j = 0, rem = W[i].size(); j < W[i].size(); j++) { if (rem >= mid) sum += W[i][j], can++, rem--; else PQ.push(W[i][j]); } } while (can < mid) { if (PQ.size() == 0) break; int x = PQ.top(); PQ.pop(); can++; sum += x; } while (PQ.size()) PQ.pop(); if (can >= mid) { ans = min(ans, sum); } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; double d, h, v, e; int main() { ios_base::sync_with_stdio(false); cin >> d >> h >> v >> e; v = v / (acos(-1) * d * d / 4); double t = h / (v - e); if (t < 0 || fabs(v - e) < 1e-8) { printf( NO n ); return 0; } printf( YES n%.12lf n , t); return 0; } |
#include <bits/stdc++.h> using namespace std; long long EPS = 1000000007; const int INF = 1000000000; double PI = 3.14159265358979323846; const int MAXN = 1000040; long long abss(long long h) { return max(h, -h); } double fabss(double h) { return max(h, -h); } long long ceill(long long x, long long y) { if (x % y != 0) return (x / y) + 1; return x / y; } string itos(long long num) { string str = ; if (num == 0) return 0 ; while (num != 0) { str += ((num % 10) + 0 ); num /= 10; } reverse(str.begin(), str.end()); return str; } long long sstoi(string num) { long long count = 1; for (int i = 0; i < (int)num.size() - 1; i++) { count *= 10; } long long ans = 0; for (int i = 0; i < (int)num.size(); i++) { ans += (num[i] - 0 ) * count; count /= 10; } return ans; } long long n, m, k, h; pair<char, int> a[MAXN]; int b[MAXN]; int c[MAXN]; pair<char, int> t[MAXN]; void build(int v, int tl, int tr) { if (tl == tr) { t[v].first = a[tl].first; t[v].second = a[tl].second; } else { int tm = (tl + tr) / 2; build(v * 2, tl, tm); build(v * 2 + 1, tm + 1, tr); if (t[v * 2].first > t[v * 2 + 1].first) { t[v] = t[v * 2 + 1]; } else if (t[v * 2].first < t[v * 2 + 1].first) { t[v] = t[v * 2]; } else if (t[v * 2].first == t[v * 2 + 1].first && t[v * 2].second > t[v * 2 + 1].second) { t[v] = t[v * 2]; } else { t[v] = t[v * 2 + 1]; } } } pair<char, int> sum(int v, int tl, int tr, int l, int r) { if (l > r) return make_pair( z , -1); if (l == tl && r == tr) return t[v]; int tm = (tl + tr) / 2; pair<char, int> q1 = sum(v * 2, tl, tm, l, min(r, tm)); pair<char, int> q2 = sum(v * 2 + 1, tm + 1, tr, max(l, tm + 1), r); if (q1.first > q2.first) { return q2; } else if (q1.first < q2.first) { return q1; } else if (q1.first == q2.first && q1.second > q2.second) { return q1; } else { return q2; } } int counter[30]; int main() { int m; cin >> m; string str; cin >> str; int n = str.size(); for (int i = 0; i < n; i++) { a[i].first = str[i]; a[i].second = i; counter[str[i] - a ]++; } build(1, 0, n - 1); int index = 0; vector<char> answer; char maxChar = a ; while (true) { pair<char, int> w = sum(1, 0, n - 1, index, index + m - 1); answer.push_back(w.first); maxChar = max(maxChar, w.first); index = w.second; if (index + m - 1 >= n - 1) { break; } index++; } sort(answer.begin(), answer.end()); for (char i = a ; i <= z ; i++) { if (i != maxChar) { for (int j = 0; j < counter[i - a ]; j++) { cout << i; } } else { for (int j = 0; j < answer.size(); j++) { if (answer[j] == maxChar) { cout << maxChar; } } break; } } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:10:47 08/17/2015
// Design Name:
// Module Name: Register
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RegisterAdd
# (parameter W = 16)
(
input wire clk, //system clock
input wire rst, //system reset
input wire load, //load signal
input wire [W-1:0] D, //input signal
output reg [W-1:0] Q //output signal
);
always @(posedge clk, posedge rst)
if(rst)
Q <= 0;
else if(load)
Q <= D;
else
Q <= Q;
endmodule
module FFD_NoCE
# (parameter W = 16)
(
input wire clk, //system clock
input wire rst, //system reset
input wire [W-1:0] D, //input signal
output reg [W-1:0] Q //output signal
);
always @(posedge clk, posedge rst)
if(rst)
Q <= 0;
else
Q <= D;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 100; long long int v[N]; inline void outv(vector<long long int> v) { for (long long int i = 0; i < v.size(); i++) { cout << v[i] << ; } cout << n ; } inline long long int pow(long long int x, long long int n) { long long int ans = 1; while (n > 0) { if (n & 1) ans *= x; x *= x; n >>= 1; } return ans; } int solve() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; string n; cin >> n; int even = 0; int s = 0; int z = 0; for (auto c : n) { if ((c) % 2 == 0) even++; s += c - 0 ; if (c == 0 ) z++; } if (s % 3 == 0 && even > 1 && z > 0) return cout << red << n , 0; ; return cout << cyan << n , 0; ; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; int t = 1; cin >> t; while (t--) solve(); return 0; } |
module main;
reg passed = 1'b1;
wire out1;
reg local_out;
reg mode;
assign out1 = mode ? 1'bz : local_out;
pullup(out1);
initial begin
mode = 1'b1;
local_out = 1'bx;
// The pull up device sets the level.
#1 if (out1 !== 1'b1) begin
$display("FAILED test 1, expected 1'b1, got %b", out1);
passed = 1'b0;
end
mode = 1'b0;
local_out = 1'b0;
// Set by local out.
#1 if (out1 !== local_out) begin
$display("FAILED test 1, expected %b, got %b", local_out, out1);
passed = 1'b0;
end
local_out = 1'b1;
// Set by local out.
#1 if (out1 !== local_out) begin
$display("FAILED test 1, expected %b, got %b", local_out, out1);
passed = 1'b0;
end
local_out = 1'bx;
// Set by local out.
#1 if (out1 !== local_out) begin
$display("FAILED test 1, expected %b, got %b", local_out, out1);
passed = 1'b0;
end
local_out = 1'bz;
// The pull up device sets the level.
#1 if (out1 !== 1'b1) begin
$display("FAILED test 1, expected 1'b1, got %b", out1);
passed = 1'b0;
end
if (passed) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int main() { cin >> n >> m; int bagi = (n / m); if (bagi * m == n) { for (int i = 0; i < m; i++) { printf( %d , bagi); } } else { int sisa = (n - (m * bagi)); for (int i = 0; i < m; i++) { int now = 0; if (sisa > 0) { now = bagi + 1; sisa--; } else { now = bagi; } printf( %d , now); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long a[1005], b[1005], n, i, j, k, temp, sum; cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; cin >> b[i]; } for (i = 0; i < n - 1; i++) { for (j = 0; j < n - i - 1; j++) { if (b[j] > b[j + 1]) { temp = b[j]; b[j] = b[j + 1]; b[j + 1] = temp; temp = a[j]; a[j] = a[j + 1]; a[j + 1] = temp; } else if (b[j] == b[j + 1]) { if (a[j] > a[j + 1]) { temp = a[j]; a[j] = a[j + 1]; a[j + 1] = temp; } } } } sum = 0; k = 1; for (i = n - 1; i >= 0; i--) { if (k > 0) { sum += a[i]; k -= 1; } k += b[i]; if (k == 0) break; } cout << sum << endl; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// verilator lint_off MULTIDRIVEN
wire [31:0] outb0c0;
wire [31:0] outb0c1;
wire [31:0] outb1c0;
wire [31:0] outb1c1;
reg [7:0] lclmem [7:0];
ma ma0 (.outb0c0(outb0c0), .outb0c1(outb0c1),
.outb1c0(outb1c0), .outb1c1(outb1c1)
);
global_mod #(32'hf00d) global_cell ();
global_mod #(32'hf22d) global_cell2 ();
input clk;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
//$write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1);
if (cyc==2) begin
if (global_cell.globali != 32'hf00d) $stop;
if (global_cell2.globali != 32'hf22d) $stop;
if (outb0c0 != 32'h00) $stop;
if (outb0c1 != 32'h01) $stop;
if (outb1c0 != 32'h10) $stop;
if (outb1c1 != 32'h11) $stop;
end
if (cyc==3) begin
// Can we scope down and read and write vars?
ma0.mb0.mc0.out <= ma0.mb0.mc0.out + 32'h100;
ma0.mb0.mc1.out <= ma0.mb0.mc1.out + 32'h100;
ma0.mb1.mc0.out <= ma0.mb1.mc0.out + 32'h100;
ma0.mb1.mc1.out <= ma0.mb1.mc1.out + 32'h100;
end
if (cyc==4) begin
// Can we do dotted's inside array sels?
ma0.rmtmem[ma0.mb0.mc0.out[2:0]] = 8'h12;
lclmem[ma0.mb0.mc0.out[2:0]] = 8'h24;
if (outb0c0 != 32'h100) $stop;
if (outb0c1 != 32'h101) $stop;
if (outb1c0 != 32'h110) $stop;
if (outb1c1 != 32'h111) $stop;
end
if (cyc==5) begin
if (ma0.rmtmem[ma0.mb0.mc0.out[2:0]] != 8'h12) $stop;
if (lclmem[ma0.mb0.mc0.out[2:0]] != 8'h24) $stop;
if (outb0c0 != 32'h1100) $stop;
if (outb0c1 != 32'h2101) $stop;
if (outb1c0 != 32'h2110) $stop;
if (outb1c1 != 32'h3111) $stop;
end
if (cyc==6) begin
if (outb0c0 != 32'h31100) $stop;
if (outb0c1 != 32'h02101) $stop;
if (outb1c0 != 32'h42110) $stop;
if (outb1c1 != 32'h03111) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef USE_INLINE_MID
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator no_inline_module*/
`else
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`define INLINE_MID_MODULE /*verilator public_module*/
`endif
`endif
module global_mod;
`INLINE_MODULE
parameter INITVAL = 0;
integer globali;
initial globali = INITVAL;
endmodule
module ma (
output wire [31:0] outb0c0,
output wire [31:0] outb0c1,
output wire [31:0] outb1c0,
output wire [31:0] outb1c1
);
`INLINE_MODULE
reg [7:0] rmtmem [7:0];
mb #(0) mb0 (.outc0(outb0c0), .outc1(outb0c1));
mb #(1) mb1 (.outc0(outb1c0), .outc1(outb1c1));
endmodule
module mb (
output wire [31:0] outc0,
output wire [31:0] outc1
);
`INLINE_MID_MODULE
parameter P2 = 0;
mc #(P2,0) mc0 (.out(outc0));
mc #(P2,1) mc1 (.out(outc1));
global_mod #(32'hf33d) global_cell2 ();
wire reach_up_clk = t.clk;
always @(reach_up_clk) begin
if (P2==0) begin // Only for mb0
if (outc0 !== t.ma0.mb0.mc0.out) $stop; // Top module name and lower instances
if (outc0 !== ma0.mb0.mc0.out) $stop; // Upper module name and lower instances
if (outc0 !== ma .mb0.mc0.out) $stop; // Upper module name and lower instances
if (outc0 !== mb.mc0.out) $stop; // This module name and lower instances
if (outc0 !== mb0.mc0.out) $stop; // Upper instance name and lower instances
if (outc0 !== mc0.out) $stop; // Lower instances
if (outc1 !== t.ma0.mb0.mc1.out) $stop; // Top module name and lower instances
if (outc1 !== ma0.mb0.mc1.out) $stop; // Upper module name and lower instances
if (outc1 !== ma .mb0.mc1.out) $stop; // Upper module name and lower instances
if (outc1 !== mb.mc1.out) $stop; // This module name and lower instances
if (outc1 !== mb0.mc1.out) $stop; // Upper instance name and lower instances
if (outc1 !== mc1.out) $stop; // Lower instances
end
end
endmodule
module mc (output reg [31:0] out);
`INLINE_MODULE
parameter P2 = 0;
parameter P3 = 0;
initial begin
out = {24'h0,P2[3:0],P3[3:0]};
//$write("%m P2=%0x p3=%0x out=%x\n",P2, P3, out);
end
// Can we look from the top module name down?
wire [31:0] reach_up_cyc = t.cyc;
always @ (posedge t.clk) begin
//$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc);
if (reach_up_cyc==2) begin
if (global_cell.globali != 32'hf00d) $stop;
if (global_cell2.globali != 32'hf33d) $stop;
end
if (reach_up_cyc==4) begin
out[15:12] <= {P2[3:0]+P3[3:0]+4'd1};
end
if (reach_up_cyc==5) begin
// Can we set another instance?
if (P3==1) begin // Without this, there are two possible correct answers...
mc0.out[19:16] <= {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2};
$display("%m Set %x->%x %x %x %x %x",mc0.out, {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}, mc0.out[19:16],P2[3:0],P3[3:0],4'd2);
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long qpow(long long a, long long b) { long long ans = 1; while (b) { if (b % 2) ans = ans * a; a = a * a; b = b / 2; } return ans; } vector<int> pos; stack<long long> num; stack<char> ch; long long cal(string s) { while (!num.empty()) num.pop(); while (!ch.empty()) ch.pop(); for (int i = 0; i < s.length(); i++) { char c = s[i]; if (c >= 0 && c <= 9 ) num.push(c - 0 ); else if (c == ( ) { ch.push(c); } else if (c == ) ) { while (ch.top() != ( ) { char x = ch.top(); ch.pop(); long long a = num.top(); num.pop(); long long b = num.top(); num.pop(); if (x == * ) num.push(a * b); else num.push(a + b); } ch.pop(); } else { if (c == + ) { while (!ch.empty() && ch.top() == * ) { char x = ch.top(); ch.pop(); long long a = num.top(); num.pop(); long long b = num.top(); num.pop(); if (x == * ) num.push(a * b); else num.push(a + b); } ch.push(c); } else ch.push(c); } } while (!ch.empty()) { char x = ch.top(); ch.pop(); long long a = num.top(); num.pop(); long long b = num.top(); num.pop(); if (x == * ) num.push(a * b); else num.push(a + b); } return num.top(); } int main() { ios::sync_with_stdio(false); string str; while (cin >> str) { int n = str.size(); pos.clear(); pos.push_back(-1); for (int i = 1; i < n; i += 2) { if (str[i] == * ) { pos.push_back(i); } } pos.push_back(n); int len = pos.size(); long long ans = 0; for (int i = 0; i < len - 1; i++) { for (int j = i + 1; j < len; j++) { string s = str; s.insert(pos[i] + 1, 1, ( ); s.insert(pos[j] + 1, 1, ) ); ans = max(ans, cal(s)); } } cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; const int N = 1000010; long long s1[N], s2[N]; int p, q, n, b[N], d[N]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %I64d , &s1[i]), s1[i] += s1[i - 1]; for (int i = 1; i <= n; i++) scanf( %I64d , &s2[i]), s2[i] += s2[i - 1]; for (int i = 0; i <= n; i++) { while (s1[i] > s2[p] && p <= n) p++; if (s1[i] <= s2[p] && b[s2[p] - s1[i]]) { q = b[s2[p] - s1[i]] - 1; printf( %d n , i - q); for (int j = q + 1; j <= i; j++) printf( %d , j); q = d[s2[p] - s1[i]]; putchar( n ); printf( %d n , p - q); for (int j = q + 1; j <= p; j++) printf( %d , j); return 0; } else b[s2[p] - s1[i]] = i + 1, d[s2[p] - s1[i]] = p; } return 0; } |
#include <bits/stdc++.h> int ct, n, m, tct, cnt[540010], mp[540010], t[540010], a[50010][4], lmax = 27 * 27 * 27 * 27, B, pool[200010], *pt(pool), *v[540010], ans[70010][402]; char s[50010], x[10], y[10]; int nd(const char* st, const char* ed) { int res = 0; while (st != ed) res = res * 27 + (*st++ - a + 1); return res; } int leng(int i) { if (i < 27) return 1; if (i < 27 * 27) return 2; if (i < 27 * 27 * 27) return 3; return 4; } int main() { scanf( %s%d , s, &m); n = strlen(s); B = 500; for (int i = 0; i < n; i++) { if (i <= n - 4) ++cnt[a[i][3] = nd(s + i, s + i + 4)]; if (i <= n - 3) ++cnt[a[i][2] = nd(s + i, s + i + 3)]; if (i <= n - 2) ++cnt[a[i][1] = nd(s + i, s + i + 2)]; ++cnt[a[i][0] = nd(s + i, s + i + 1)]; } for (int i = 1; i < lmax; i++) if (cnt[i]) { mp[i] = ++ct; v[mp[i]] = pt, pt += cnt[i]; cnt[i] = 0; } for (int k = 0; k <= 3; k++) for (int j = 0; j < n - k; j++) { int p = mp[a[j][k]]; v[p][cnt[p]++] = j; } for (int i = 1; i <= lmax; i++) if (cnt[mp[i]] >= B) { t[mp[i]] = ++tct; int q = t[mp[i]], d = leng(i); for (int j = 1; j <= ct; j++) ans[j][q] = 0x3f3f3f3f; int rl = -5, ll = -5; for (int k = 0; k <= 3; k++) { rl = -5; for (int j = 0; j < n - k; j++) { int p = mp[a[j][k]]; if (a[j][d - 1] == i) ll = j - 1, rl = j + d - 1; if (rl != -5) ans[p][q] = std::min(ans[p][q], std::max(j + k, rl) - ll); } } for (int k = 0; k <= 3; k++) { rl = -5; for (int j = n - k - 1; ~j; j--) { int p = mp[a[j][k]]; if (a[j][d - 1] == i) ll = j, rl = j + d; if (rl != -5) ans[p][q] = std::min(ans[p][q], std::max(rl, j + k + 1) - std::min(ll, j)); } } ans[mp[i]][q] = d; } while (m--) { scanf( %s%s , x, y); int xw = strlen(x), yw = strlen(y); int x1 = nd(x, x + xw), y1 = nd(y, y + yw); if (!mp[x1] || !mp[y1]) { puts( -1 ); } else { x1 = mp[x1], y1 = mp[y1]; if (cnt[x1] > cnt[y1]) x1 ^= y1 ^= x1 ^= y1, xw ^= yw ^= xw ^= yw; if (cnt[y1] >= B) { printf( %d n , ans[x1][t[y1]]); } else { int i = 0, j = 0, ans = 0x3f3f3f3f; while (i < cnt[x1] && j < cnt[y1]) { if (v[x1][i] < v[y1][j]) ans = std::min(ans, std::max(v[x1][i] + xw, v[y1][j] + yw) - v[x1][i]), ++i; else ans = std::min(ans, std::max(v[x1][i] + xw, v[y1][j] + yw) - v[y1][j]), ++j; } printf( %d n , ans); } } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211OI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A211OI_FUNCTIONAL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a211oi (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; struct w { int c, mi; } tr[1010 * 1010 * 8]; struct ww { int h, b, l, r, x, y; } c[1010 * 1010]; int i, j, k, n, m, s, vx, vy, t, ans; int a[1010][1010], b[1010][1010]; double d[1010 * 1010]; long long an; inline bool cc1(const ww &a, const ww &b) { return a.b > b.b; } inline void update(int x) { tr[x].mi = min(tr[x * 2].mi, tr[x * 2 + 1].mi); } inline void Cover(int x, int y) { tr[x].c = max(tr[x].c, y); tr[x].mi = max(tr[x].mi, y); } inline void renew(int x) { if (tr[x].c) Cover(x * 2, tr[x].c), Cover(x * 2 + 1, tr[x].c); tr[x].c = 0; } void cover(int q, int x, int y, int l, int r, int h) { if (l <= x && y <= r) { Cover(q, h); return; } renew(q); int mid = (x + y) / 2; if (l <= mid) cover(q * 2, x, mid, l, r, h); if (mid < r) cover(q * 2 + 1, mid + 1, y, l, r, h); update(q); } void cal(int q, int x, int y, int l, int r) { if (l <= x && y <= r) { ans = min(ans, tr[q].mi); return; } renew(q); int mid = (x + y) / 2; if (l <= mid) cal(q * 2, x, mid, l, r); if (mid < r) cal(q * 2 + 1, mid + 1, y, l, r); } int main() { scanf( %d%d%d , &n, &vx, &vy); for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) scanf( %d , &a[i][j]); vx = -vx, vy = -vy; if (vx < 0) { vx = -vx; for (j = 1; j <= n; j++) for (i = 1; i <= n / 2; i++) swap(a[i][j], a[n - i + 1][j]); } if (vy < 0) { vy = -vy; for (i = 1; i <= n; i++) for (j = 1; j <= n / 2; j++) swap(a[i][j], a[i][n - j + 1]); } if (!vx) { swap(vx, vy); for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) b[i][j] = a[i][j]; for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) a[j][n - i + 1] = b[i][j]; } sort(d + 1, d + t + 1); for (i = 1; i <= t; i++) if (!m || d[m] < d[i]) d[++m] = d[i]; double ay = 1. * vy / vx; for (i = 0; i <= n; i++) for (j = 0; j <= n; j++) d[++m] = j - i * ay; sort(d + 1, d + m + 1); for (i = 1; i <= m; i++) if (!t || d[t] + (1e-9) < d[i]) d[++t] = d[i]; for (i = 1; i <= n; i++) for (j = 0; j <= n - 1; j++) { int l = lower_bound(d + 1, d + t + 1, j - i * ay - (1e-9)) - d; int r = lower_bound(d + 1, d + t + 1, j + 1 - (i - 1) * ay - (1e-9)) - d; c[++s] = (ww){a[i][j + 1], i + j, l * 2, r * 2}; } m = t * 2; sort(c + 1, c + s + 1, cc1); for (i = 1; i <= s; i++) { ans = 2000000000; cal(1, 1, m, c[i].l, c[i].r); if (ans < c[i].h) an += c[i].h - ans; cover(1, 1, m, c[i].l, c[i].r, c[i].h); } printf( %I64d n , an); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 08:27:08 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_stub.v
// Design : system_vga_color_test_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_color_test,Vivado 2016.4" *)
module system_vga_color_test_0_0(clk_25, xaddr, yaddr, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk_25,xaddr[9:0],yaddr[9:0],rgb[23:0]" */;
input clk_25;
input [9:0]xaddr;
input [9:0]yaddr;
output [23:0]rgb;
endmodule
|
/**************************************
* Module: priority_vc_perInput
* Date:2016-01-31
* Author: armin
*
* Description:
***************************************/
`include "util.v"
`include "constants.v"
`include "mux1024to1.v"
// for one vc, and one input
module priority_vc_perInput(
output [0:`IN_OUTPORT_CNT-1] selected_inputs_out,
output [0:`IN_OUTPORT_CNT-1] selected_outputs_out,
output [1:`FLIT_SIZE * `IN_OUTPORT_CNT] outputs_out,
output credit_for_input,
output [0:`OCCUPIEDS_SIZE*`IN_OUTPORT_CNT-1] occupieds_out,
input is_new_flit,
input [0:`LOG_PORTS_CNT-1] port_num,
input [0:`IN_OUTPORT_CNT-1] selected_inputs_in,
input [0:`IN_OUTPORT_CNT-1] selected_outputs_in,
input [0:`IN_OUTPORT_CNT-1] nxt_routers_credit,
input [1:`FLIT_SIZE] flit_in,
input [1:`FLIT_SIZE * `IN_OUTPORT_CNT] outputs_in,
input [0:`OCCUPIEDS_SIZE*`IN_OUTPORT_CNT-1] occupieds_in,
input [0:`TABLE_SIZE-1]TABLE
);
parameter VC_NUM = 4;
genvar util_genvar;
`MAKE_ARRAY(occupieds_in_array, occupieds_in, `IN_OUTPORT_CNT, `OCCUPIEDS_SIZE, GEN_OCCUPIEDS_IN)
`MAKE_ARRAY(occupieds_out_array, occupieds_out, `IN_OUTPORT_CNT, `OCCUPIEDS_SIZE, GEN_OCCUPIEDS_OUT)
wire [0:`LOG_PORTS_CNT-1] dst_port_num;
mux1024to1 m(.OUT(dst_port_num),
.select(flit_in `FLIT_DST),
.TABLE(TABLE)
);
genvar i;
generate
for(i=0;i<`IN_OUTPORT_CNT;i=i+1)
begin : GEN_PRIORITY_VC_PERINPUT
assign selected_inputs_out[i] = (i == port_num && is_new_flit ? ((selected_inputs_in[i]==1'b0 && selected_outputs_in[dst_port_num]==1'b0 &&
nxt_routers_credit[dst_port_num]==1'b1 &&
(occupieds_in_array[dst_port_num] `OCCUPIED_IS_FULL==1'b0 ||
(occupieds_in_array[dst_port_num] `OCCUPIED_IS_FULL==1'b1 && occupieds_in_array[dst_port_num] `OCCUPIED_PORT_NO == i)) ) ? 1'b1
: selected_inputs_in[i])
: selected_inputs_in[i]);
assign outputs_out[i*`FLIT_SIZE+1 : (i+1)*`FLIT_SIZE] = (i == port_num && is_new_flit ? ((selected_inputs_in[i]==1'b0 && selected_outputs_in[dst_port_num]==1'b0 &&
nxt_routers_credit[dst_port_num]==1'b1 &&
(occupieds_in_array[dst_port_num] `OCCUPIED_IS_FULL==1'b0 ||
(occupieds_in_array[dst_port_num] `OCCUPIED_IS_FULL && occupieds_in_array[dst_port_num] `OCCUPIED_PORT_NO == i)) ) ? flit_in
: outputs_in[i*`FLIT_SIZE+1 : (i+1)*`FLIT_SIZE])
: outputs_in[i*`FLIT_SIZE+1 : (i+1)*`FLIT_SIZE]);
assign selected_outputs_out[i] = (i == dst_port_num && is_new_flit ? ((selected_inputs_in[port_num]==1'b0 && selected_outputs_in[dst_port_num]==1'b0 &&
nxt_routers_credit[dst_port_num]==1'b1 &&
(occupieds_in_array[dst_port_num] `OCCUPIED_IS_FULL==1'b0 ||
(occupieds_in_array[dst_port_num] `OCCUPIED_IS_FULL==1'b1 && occupieds_in_array[dst_port_num] `OCCUPIED_PORT_NO == port_num)) ) ? 1'b1
:selected_outputs_in[i])
:selected_outputs_in[i]);
assign occupieds_out_array[i] = (i == dst_port_num && is_new_flit ? ((selected_inputs_in[port_num]==1'b0 && selected_outputs_in[dst_port_num]==1'b0 &&
nxt_routers_credit[dst_port_num]==1'b1 &&
(occupieds_in_array[dst_port_num] `OCCUPIED_IS_FULL==1'b0 ||
(occupieds_in_array[dst_port_num] `OCCUPIED_IS_FULL==1'b1 && occupieds_in_array[dst_port_num] `OCCUPIED_PORT_NO == port_num)) ) ? (flit_in `FLIT_TAIL ? {`OCCUPIEDS_SIZE{1'b0}} : {1'b1,port_num[0:`LOG_PORTS_CNT-1]})
:occupieds_in_array[i])
:occupieds_in_array[i]);
end
assign credit_for_input = ((selected_inputs_in[port_num]==1'b0 && selected_outputs_in[dst_port_num]==1'b0 &&
nxt_routers_credit[dst_port_num]==1'b1 &&
(occupieds_in_array[dst_port_num] `OCCUPIED_IS_FULL==1'b0 ||
(occupieds_in_array[dst_port_num] `OCCUPIED_IS_FULL && occupieds_in_array[dst_port_num] `OCCUPIED_PORT_NO == port_num)) ) ? 1'b1 : 1'b0);
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; int a[12000], dp[1100][1100], f[1100]; int ans; void work() { int i, j, l, o, last; scanf( %d%d , &n, &k); dp[0][0] = 1; f[0] = 1; for (i = 1; i <= n; i++) { scanf( %d , &a[i]); for (j = k; j >= a[i]; j--) { if (f[j - a[i]]) { f[j] = 1; dp[j][j] = 1; for (l = 0; l <= k; l++) dp[j][l] = max(dp[j][l], dp[j - a[i]][l]), dp[j][l + a[i]] = max(dp[j][l + a[i]], dp[j - a[i]][l]); } } } for (i = 0; i <= k; i++) if (dp[k][i]) ans++, last = i; printf( %d n , ans); for (i = 0; i <= k; i++) if (dp[k][i]) { printf( %d , i); if (i != last) printf( ); } } int main() { work(); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long double PI = 3.141592653589793238462643383279502884197; priority_queue<int, vector<int>, greater<int> > pq; vector<int> v; int al[256]; char s[200001], t[200001]; int visit[200001]; int n, m; int main() { scanf( %s %s , s, t); n = strlen(s); m = strlen(t); memset(al, -1, sizeof(al)); int l = 0; for (int i = 0; i < n; i++) { if (l < m && s[i] == t[l]) { al[s[i]] = l; l++; } if (al[s[i]] == -1) return !printf( No ); visit[i] = al[s[i]]; } if (l != m) return !printf( No ); l = m - 1; memset(al, -1, sizeof(al)); for (int i = n - 1; i >= 0; i--) { if (l >= 0 && s[i] == t[l]) { al[s[i]] = l; l--; } if (al[s[i]] == -1) return !printf( No ); if (visit[i] < al[s[i]]) return !printf( No ); } if (l != -1) return !printf( No ); printf( Yes ); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4_BEHAVIORAL_V
`define SKY130_FD_SC_HD__OR4_BEHAVIORAL_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 100010; int n, a[N], b[N], c[N]; multiset<int> S; multiset<int>::iterator it; int main() { std::ios::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) cin >> a[i], c[a[i]] = i; for (int i = 0; i < n; i++) cin >> b[i]; for (int i = 0; i < n; i++) { int t = i - c[b[i]]; S.insert(t); } vector<int> r; for (int i = 0; i < n; i++) { int t = 1000000; it = S.lower_bound(i); if (it != S.end()) t = min(t, *(it)-i); if (it != S.begin()) t = min(t, i - *(--it)); r.push_back(t); S.erase(S.find(i - c[b[i]])); S.insert(n - c[b[i]] + i); } for (int i = 0; i < r.size(); i++) cout << r[i] << endl; return 0; } |
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/11.0sp1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2011/04/07 $
// $Author: max $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1ns / 1ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s, ans; cin >> s; ans = ; for (int i = 0; i < s.size(); i++) { ans = ans + s[i]; if (s[i] == a || s[i] == e || s[i] == i || s[i] == o || s[i] == u || s[i] == y ) { for (int j = i; j < s.size(); j++) { if (s[j] == a || s[j] == e || s[j] == i || s[j] == o || s[j] == u || s[j] == y ) { i = j; } else { break; } } } } cout << ans << endl; } |
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module async_fifo
#(
parameter DSIZE = 8,
parameter ASIZE = 4,
parameter FALLTHROUGH = "TRUE" // First word fall-through
)(
input wire wclk,
input wire wrst_n,
input wire winc,
input wire [DSIZE-1:0] wdata,
output wire wfull,
output wire awfull,
input wire rclk,
input wire rrst_n,
input wire rinc,
output wire [DSIZE-1:0] rdata,
output wire rempty,
output wire arempty
);
wire [ASIZE-1:0] waddr, raddr;
wire [ ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
// The module synchronizing the read point
// from read to write domain
sync_r2w
#(ASIZE)
sync_r2w (
.wq2_rptr (wq2_rptr),
.rptr (rptr),
.wclk (wclk),
.wrst_n (wrst_n)
);
// The module synchronizing the write point
// from write to read domain
sync_w2r
#(ASIZE)
sync_w2r (
.rq2_wptr (rq2_wptr),
.wptr (wptr),
.rclk (rclk),
.rrst_n (rrst_n)
);
// The module handling the write requests
wptr_full
#(ASIZE)
wptr_full (
.awfull (awfull),
.wfull (wfull),
.waddr (waddr),
.wptr (wptr),
.wq2_rptr (wq2_rptr),
.winc (winc),
.wclk (wclk),
.wrst_n (wrst_n)
);
// The DC-RAM
fifomem
#(DSIZE, ASIZE, FALLTHROUGH)
fifomem (
.rclken (rinc),
.rclk (rclk),
.rdata (rdata),
.wdata (wdata),
.waddr (waddr),
.raddr (raddr),
.wclken (winc),
.wfull (wfull),
.wclk (wclk)
);
// The module handling read requests
rptr_empty
#(ASIZE)
rptr_empty (
.arempty (arempty),
.rempty (rempty),
.raddr (raddr),
.rptr (rptr),
.rq2_wptr (rq2_wptr),
.rinc (rinc),
.rclk (rclk),
.rrst_n (rrst_n)
);
endmodule
`resetall
|
//
// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module time_64bit
#(
parameter BASE = 0)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input pps,
output reg [63:0] vita_time,
output reg [63:0] vita_time_pps,
output pps_int,
input exp_time_in, output exp_time_out,
output reg good_sync,
output [31:0] debug
);
localparam NEXT_TICKS_HI = 0;
localparam NEXT_TICKS_LO = 1;
localparam PPS_POLSRC = 2;
localparam PPS_IMM = 3;
localparam MIMO_SYNC = 5;
reg [63:0] ticks;
always @(posedge clk)
vita_time <= ticks;
wire [63:0] vita_time_rcvd;
wire [63:0] next_ticks_preset;
wire set_on_pps_trig;
reg set_on_next_pps;
wire pps_polarity, pps_source, set_imm;
reg [1:0] pps_del;
reg pps_reg_p, pps_reg_n, pps_reg;
wire pps_edge;
reg [15:0] sync_counter;
wire sync_rcvd;
wire [63:0] mimo_ticks;
wire mimo_sync_now;
wire mimo_sync;
wire [7:0] sync_delay;
setting_reg #(.my_addr(BASE+NEXT_TICKS_LO)) sr_next_ticks_lo
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(next_ticks_preset[31:0]),.changed());
setting_reg #(.my_addr(BASE+NEXT_TICKS_HI)) sr_next_ticks_hi
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(next_ticks_preset[63:32]),.changed(set_on_pps_trig));
setting_reg #(.my_addr(BASE+PPS_POLSRC), .width(2)) sr_pps_polsrc
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({pps_source,pps_polarity}),.changed());
setting_reg #(.my_addr(BASE+PPS_IMM), .width(1)) sr_pps_imm
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(set_imm),.changed());
setting_reg #(.my_addr(BASE+MIMO_SYNC), .at_reset(0), .width(9)) sr_mimosync
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out({mimo_sync,sync_delay}),.changed());
always @(posedge clk) pps_reg_p <= pps;
always @(negedge clk) pps_reg_n <= pps;
always @* pps_reg <= pps_polarity ? pps_reg_p : pps_reg_n;
always @(posedge clk)
if(rst)
pps_del <= 2'b00;
else
pps_del <= {pps_del[0],pps_reg};
assign pps_edge = pps_del[0] & ~pps_del[1];
always @(posedge clk)
if(pps_edge)
vita_time_pps <= vita_time;
always @(posedge clk)
if(rst)
set_on_next_pps <= 0;
else if(set_on_pps_trig)
set_on_next_pps <= 1;
else if(set_imm | pps_edge)
set_on_next_pps <= 0;
wire [63:0] ticks_plus_one = ticks + 1;
always @(posedge clk)
if(rst)
begin
ticks <= 64'd0;
end
else if((set_imm | pps_edge) & set_on_next_pps)
begin
ticks <= next_ticks_preset;
end
else if(mimo_sync_now)
begin
ticks <= mimo_ticks;
end
else
ticks <= ticks_plus_one;
assign pps_int = pps_edge;
// MIMO Connector Time Sync
wire send_sync = (sync_counter == 59999); // X % 10 = 9
always @(posedge clk)
if(rst)
sync_counter <= 0;
else
if(send_sync)
sync_counter <= 0;
else
sync_counter <= sync_counter + 1;
time_sender time_sender
(.clk(clk),.rst(rst),
.vita_time(vita_time),
.send_sync(send_sync),
.exp_time_out(exp_time_out) );
time_receiver time_receiver
(.clk(clk),.rst(rst),
.vita_time(vita_time_rcvd),
.sync_rcvd(sync_rcvd),
.exp_time_in(exp_time_in) );
assign mimo_ticks = vita_time_rcvd[63:0] + {48'd0,sync_delay};
assign mimo_sync_now = mimo_sync & sync_rcvd;
assign debug = { { 24'b0} ,
{ 2'b0, exp_time_in, exp_time_out, mimo_sync, mimo_sync_now, sync_rcvd, send_sync} };
always @(posedge clk)
if(rst)
good_sync <= 0;
else if(sync_rcvd)
good_sync <= 1;
endmodule // time_64bit
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O221AI_FUNCTIONAL_PP_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int N = 1e5 + 5, M = 100 + 5, OO = 0x3f3f3f3f, mod = 1e9 + 7, base = 131, MOD2 = 1000136437; const double EPS = 1e-9; long double w, h, theta; complex<double> rotate(complex<double> &p, double a) { return p * polar(1.0, a); } int doubleComp(const double &a, const double &b) { return fabs(a - b) < EPS ? 0 : a < b ? -1 : 1; } bool lineInter(const complex<double> &A, const complex<double> &B, const complex<double> &P, const complex<double> &Q, complex<double> &R, bool isSegA = false, bool isSegB = false) { double d1 = ((conj(P - A) * (B - A)).imag()); double d2 = ((conj(Q - A) * (B - A)).imag()); if (fabs(d1 - d2) < EPS) return false; R = (d1 * Q - d2 * P) / (d1 - d2); if (isSegA && doubleComp(hypot(A.real() - B.real(), A.imag() - B.imag()), hypot(A.real() - R.real(), A.imag() - R.imag()) + hypot(B.real() - R.real(), B.imag() - R.imag())) != 0) return false; if (isSegB && doubleComp(hypot(P.real() - Q.real(), P.imag() - Q.imag()), hypot(P.real() - R.real(), P.imag() - R.imag()) + hypot(Q.real() - R.real(), Q.imag() - R.imag())) != 0) return false; return true; } void polygonCut(const complex<double> &a, const complex<double> &b, const vector<complex<double> > &v, vector<complex<double> > &ret) { ret.clear(); for (int i = 0; i < (int)(v).size(); i++) { int j = (i + 1) % (int)(v).size(); if (((conj(((b) - (a))) * (((v[i]) - (a)))).imag()) >= 0) ret.push_back(v[i]); complex<double> r; if (lineInter(a, b, v[i], v[j], r, 0, 1)) ret.push_back(r); } } void polygonIntersection(const vector<complex<double> > &poly1, const vector<complex<double> > &poly2, vector<complex<double> > &ret) { vector<complex<double> > r2; ret = poly1; for (int i = 0; i < (int)(poly2).size(); i++) { int j = (i + 1) % (int)(poly2).size(); polygonCut(poly2[i], poly2[j], ret, r2); ret = r2; } } double areaPolygon(vector<complex<double> > p) { double area = 0.0; for (int i = 0, n = (int)(p).size(); i < n; i++) area += ((conj(p[i]) * (p[(i + 1) % n])).imag()); return abs(area) / 2.0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> w >> h >> theta; vector<complex<double> > p, p2, ans; w /= 2; h /= 2; p.push_back(complex<double>(w, h)); p.push_back(complex<double>(-w, h)); p.push_back(complex<double>(-w, -h)); p.push_back(complex<double>(w, -h)); p2 = p; theta = (theta / 180.0) * (2 * acos(0)); for (auto &i : p2) i = rotate(i, theta); polygonIntersection(p, p2, ans); cout << fixed << setprecision(6) << areaPolygon(ans); return 0; } |
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/blanc/AUTOBUF.v,v 1.2 2008/09/04 22:14:49 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : AUTOBUF.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 04/08/08 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module AUTOBUF (O, I);
parameter BUFFER_TYPE = "AUTO";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
initial begin
case (BUFFER_TYPE)
"AUTO" : ;
"BUF" : ;
"BUFG" : ;
"BUFGP" : ;
"BUFH" : ;
"BUFIO" : ;
"BUFIO2" : ;
"BUFIO2FB" : ;
"BUFR" : ;
"IBUF" : ;
"IBUFG" : ;
"NONE" : ;
"OBUF" : ;
default : begin
$display("Attribute Syntax Error : The Attribute BUFFER_TYPE on AUTOBUF instance %m is set to %s. Legal values for this attribute are AUTO, BUF, BUFG, BUFGP, BUFH, BUFIO, BUFIO2, BUFIO2FB, BUFR, IBUF, IBUFG, NONE, and OBUF.", BUFFER_TYPE);
end
endcase
end
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
//--------------------------------------------------------------------------------
// eia232.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// EIA232 aka RS232 interface.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis - mygizmos.org
//
`timescale 1ns/100ps
module eia232(
clock, reset, speed, send, wrdata, rx,
// outputs
tx, cmd, execute, busy);
parameter [31:0] FREQ = 100000000;
parameter [31:0] SCALE = 28;
parameter [31:0] RATE = 115200;
input clock;
input reset;
input [1:0] speed; // UART speed
input send; // Send data output serial tx
input [31:0] wrdata; // Data to be sent
input rx; // Serial RX
output tx; // Serial TX
output [39:0] cmd;
output execute; // Cmd is valid
output busy; // Indicates transmitter busy
wire clock;
wire reset;
wire [1:0] speed;
wire rx;
wire tx;
wire [39:0] cmd;
wire execute;
wire [31:0] wrdata;
wire send;
wire busy;
parameter TRXFREQ = FREQ / SCALE; // reduced rx & tx clock for receiver and transmitter
wire trxClock;
reg id, next_id;
reg xon, next_xon;
reg xoff, next_xoff;
reg wrFlags, next_wrFlags;
reg dly_execute, next_dly_execute;
reg [3:0] disabledGroupsReg, next_disabledGroupsReg;
wire [7:0] opcode;
wire [31:0] opdata;
assign cmd = {opdata,opcode};
//
// Process special uart commands that do not belong in core decoder...
//
always @(posedge clock)
begin
id = next_id;
xon = next_xon;
xoff = next_xoff;
wrFlags = next_wrFlags;
dly_execute = next_dly_execute;
disabledGroupsReg = next_disabledGroupsReg;
end
always #1
begin
next_id = 1'b0;
next_xon = 1'b0;
next_xoff = 1'b0;
next_wrFlags = 1'b0;
next_dly_execute = execute;
if (!dly_execute && execute)
case(opcode)
8'h02 : next_id = 1'b1;
8'h11 : next_xon = 1'b1;
8'h13 : next_xoff = 1'b1;
8'h82 : next_wrFlags = 1'b1;
endcase
next_disabledGroupsReg = disabledGroupsReg;
if (wrFlags) next_disabledGroupsReg = opdata[5:2];
end
//
// Instantiate prescaler that generates clock matching UART reference (ie: 115200 baud)...
//
prescaler #(.SCALE(SCALE)) prescaler(
.clock(clock), .reset(reset), .div(speed), .scaled(trxClock));
//
// Instantiate serial-to-parallel receiver.
// Asserts "execute" whenever valid 8-bit value received.
//
receiver #(.FREQ(TRXFREQ), .RATE(RATE)) receiver(
.clock(clock), .reset(reset), .rx(rx), .trxClock(trxClock),
.op(opcode), .data(opdata), .execute(execute));
//
// Instantiate parallel-to-serial transmitter.
// Genereate serial data whenever "send" or "id" asserted.
// Obeys xon/xoff commands.
//
transmitter #(.FREQ(TRXFREQ), .RATE(RATE)) transmitter(
.clock(clock), .trxClock(trxClock), .reset(reset),
.disabledGroups(disabledGroupsReg),
.write(send), .wrdata(wrdata),
.id(id), .xon(xon), .xoff(xoff),
.tx(tx), .busy(busy));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__OR3_BEHAVIORAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_BEHAVIORAL_PP_V |
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