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#include <bits/stdc++.h> using namespace std; int main() { int t, n; scanf( %d , &t); while (t--) { scanf( %d , &n); printf( %d n , n - 1); for (int i = 2; i <= n; ++i) printf( %d , i); printf( n ); } } |
#include <bits/stdc++.h> using namespace std; const int p = 1e9 + 7; struct Matrix { int n, m; long long a[105][105]; Matrix(int x, int y) { n = x, m = y; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) a[i][j] = 0; } } void init() { for (int i = 1; i <= min(n, m); i++) a[i][i] = 1; } void print() { for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) cout << a[i][j] << ; cout << endl; } cout << endl; } }; Matrix operator*(Matrix a, Matrix b) { Matrix c = Matrix(a.n, b.m); for (int i = 1; i <= a.n; i++) { for (int j = 1; j <= b.m; j++) { for (int k = 1; k <= a.m; k++) { c.a[i][j] = (c.a[i][j] + a.a[i][k] * b.a[k][j] % p) % p; } } } return c; } Matrix qpow(Matrix a, long long b) { Matrix res = Matrix(a.n, a.m); res.init(); while (b) { if (b & 1) res = res * a; a = a * a; b >>= 1; } return res; } long long n, m, k; int main() { cin >> n >> m >> k; Matrix f = Matrix(m, m); for (int i = 1; i <= m; i++) { for (int j = 1; j <= m; j++) f.a[i][j] = 1; } string s; int x, y, z; while (k--) { cin >> s; if (s[0] <= Z && s[0] >= A ) x = s[0] - A + 27; else x = s[0] - a + 1; if (s[1] <= Z && s[1] >= A ) y = s[1] - A + 27; else y = s[1] - a + 1; f.a[x][y] &= 0; } Matrix ans = Matrix(1, m); for (int i = 1; i <= m; i++) ans.a[1][i] = 1; f = qpow(f, n - 1); ans = ans * f; long long res = 0; for (int i = 1; i <= m; i++) res += ans.a[1][i], res %= p; cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 998244353, inv2 = mod + 1 >> 1; inline void add(int &a, int b) { (a += b) >= mod && (a -= mod); } inline int Add(int a, int b) { return add(a, b), a; } inline void sub(int &a, int b) { (a -= b) < 0 && (a += mod); } inline int Sub(int a, int b) { return sub(a, b), a; } inline void mul(int &a, int b) { a = 1ll * a * b % mod; } inline int Mul(int a, int b) { return 1ll * a * b % mod; } const int N = 40, M = 1 << 20; int m, n, S, f[N][M], g[M], siz[M], x[M], y[M], res[M], ans[N]; long long b[M]; inline void XOR(int *a, int n, bool rev) { for (int k = 2, m = 1; k <= n; k <<= 1, m <<= 1) { for (int j = 0; j < n; j += k) for (int i = 0; i < m; ++i) { int x = a[j + i], y = a[j + i + m]; if (!rev) { a[j + i] = Add(x, y); a[j + i + m] = Sub(x, y); } else { a[j + i] = Mul(Add(x, y), inv2); a[j + i + m] = Mul(Sub(x, y), inv2); } } } } inline void FWT(int *a, int *b, int n) { memcpy(x, a, sizeof(x)), memcpy(y, b, sizeof(y)); XOR(x, n, 0), XOR(y, n, 0); for (int i = 0; i < n; ++i) res[i] = Mul(x[i], y[i]); XOR(res, n, 1); } void dfs1(long long x, int y) { if (y == m) return ++g[x], void(); dfs1(x, y + 1); if (b[y]) dfs1(x ^ b[y], y + 1); } void dfs2(long long x, int y) { if (y == n) return ++f[siz[x >> m]][x & (S - 1)], void(); dfs2(x, y + 1); if (b[y]) dfs2(x ^ b[y], y + 1); } int main() { scanf( %d%d , &m, &n); int tot = 1; for (int i = 1; i <= m; ++i) { long long x; scanf( %lld , &x), mul(tot, 2); for (int k = n - 1; ~k; --k) if (x >> k & 1) { if (!b[k]) { b[k] = x; mul(tot, inv2); break; } x ^= b[k]; } } m = n + 1 >> 1, S = 1 << m; for (int i = 0; i < S; ++i) siz[i] = siz[i >> 1] + (i & 1); dfs1(0, 0), dfs2(0, m); for (int i = 0; i <= n - m; ++i) { FWT(f[i], g, S); for (int s = 0; s < S; ++s) add(ans[i + siz[s]], res[s]); } for (int i = 0; i <= n; ++i) printf( %d , Mul(ans[i], tot)); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SDFRTP_PP_BLACKBOX_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_PP_BLACKBOX_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module delay_line
#(parameter WIDTH=32)
(input clk,
input [3:0] delay,
input [WIDTH-1:0] din,
output [WIDTH-1:0] dout);
genvar i;
generate
for (i=0;i<WIDTH;i=i+1)
begin : gen_delay
SRL16E
srl16e(.Q(dout[i]),
.A0(delay[0]),.A1(delay[1]),.A2(delay[2]),.A3(delay[3]),
.CE(1),.CLK(clk),.D(din[i]));
end
endgenerate
endmodule // delay_line
|
// megafunction wizard: %Virtual JTAG%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: sld_virtual_jtag
// ============================================================
// File Name: vjtag.v
// Megafunction Name(s):
// sld_virtual_jtag
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module vjtag (
ir_out,
tdo,
ir_in,
tck,
tdi,
virtual_state_cdr,
virtual_state_cir,
virtual_state_e1dr,
virtual_state_e2dr,
virtual_state_pdr,
virtual_state_sdr,
virtual_state_udr,
virtual_state_uir);
input [1:0] ir_out;
input tdo;
output [1:0] ir_in;
output tck;
output tdi;
output virtual_state_cdr;
output virtual_state_cir;
output virtual_state_e1dr;
output virtual_state_e2dr;
output virtual_state_pdr;
output virtual_state_sdr;
output virtual_state_udr;
output virtual_state_uir;
wire sub_wire0;
wire sub_wire1;
wire [1:0] sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire sub_wire6;
wire sub_wire7;
wire sub_wire8;
wire sub_wire9;
wire sub_wire10;
wire virtual_state_cir = sub_wire0;
wire virtual_state_pdr = sub_wire1;
wire [1:0] ir_in = sub_wire2[1:0];
wire tdi = sub_wire3;
wire virtual_state_udr = sub_wire4;
wire tck = sub_wire5;
wire virtual_state_e1dr = sub_wire6;
wire virtual_state_uir = sub_wire7;
wire virtual_state_cdr = sub_wire8;
wire virtual_state_e2dr = sub_wire9;
wire virtual_state_sdr = sub_wire10;
sld_virtual_jtag sld_virtual_jtag_component (
.ir_out (ir_out),
.tdo (tdo),
.virtual_state_cir (sub_wire0),
.virtual_state_pdr (sub_wire1),
.ir_in (sub_wire2),
.tdi (sub_wire3),
.virtual_state_udr (sub_wire4),
.tck (sub_wire5),
.virtual_state_e1dr (sub_wire6),
.virtual_state_uir (sub_wire7),
.virtual_state_cdr (sub_wire8),
.virtual_state_e2dr (sub_wire9),
.virtual_state_sdr (sub_wire10)
// synopsys translate_off
,
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_e1ir (),
.jtag_state_e2dr (),
.jtag_state_e2ir (),
.jtag_state_pdr (),
.jtag_state_pir (),
.jtag_state_rti (),
.jtag_state_sdr (),
.jtag_state_sdrs (),
.jtag_state_sir (),
.jtag_state_sirs (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.tms ()
// synopsys translate_on
);
defparam
sld_virtual_jtag_component.sld_auto_instance_index = "NO",
sld_virtual_jtag_component.sld_instance_index = 0,
sld_virtual_jtag_component.sld_ir_width = 2,
sld_virtual_jtag_component.sld_sim_action = "((0,2,0,4),(0,1,1,2),(0,2,12,8),(0,2,34,8),(0,2,56,8),(0,1,0,2),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8))",
sld_virtual_jtag_component.sld_sim_n_scan = 41,
sld_virtual_jtag_component.sld_sim_total_length = 312;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: show_jtag_state STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "NO"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
// Retrieval info: CONSTANT: SLD_IR_WIDTH NUMERIC "2"
// Retrieval info: CONSTANT: SLD_SIM_ACTION STRING "((0,2,0,4),(0,1,1,2),(0,2,12,8),(0,2,34,8),(0,2,56,8),(0,1,0,2),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8),(0,2,0,8))"
// Retrieval info: CONSTANT: SLD_SIM_N_SCAN NUMERIC "41"
// Retrieval info: CONSTANT: SLD_SIM_TOTAL_LENGTH NUMERIC "312"
// Retrieval info: USED_PORT: ir_in 0 0 2 0 OUTPUT NODEFVAL "ir_in[1..0]"
// Retrieval info: USED_PORT: ir_out 0 0 2 0 INPUT NODEFVAL "ir_out[1..0]"
// Retrieval info: USED_PORT: tck 0 0 0 0 OUTPUT NODEFVAL "tck"
// Retrieval info: USED_PORT: tdi 0 0 0 0 OUTPUT NODEFVAL "tdi"
// Retrieval info: USED_PORT: tdo 0 0 0 0 INPUT NODEFVAL "tdo"
// Retrieval info: USED_PORT: virtual_state_cdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cdr"
// Retrieval info: USED_PORT: virtual_state_cir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_cir"
// Retrieval info: USED_PORT: virtual_state_e1dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e1dr"
// Retrieval info: USED_PORT: virtual_state_e2dr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_e2dr"
// Retrieval info: USED_PORT: virtual_state_pdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_pdr"
// Retrieval info: USED_PORT: virtual_state_sdr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_sdr"
// Retrieval info: USED_PORT: virtual_state_udr 0 0 0 0 OUTPUT NODEFVAL "virtual_state_udr"
// Retrieval info: USED_PORT: virtual_state_uir 0 0 0 0 OUTPUT NODEFVAL "virtual_state_uir"
// Retrieval info: CONNECT: @ir_out 0 0 2 0 ir_out 0 0 2 0
// Retrieval info: CONNECT: @tdo 0 0 0 0 tdo 0 0 0 0
// Retrieval info: CONNECT: ir_in 0 0 2 0 @ir_in 0 0 2 0
// Retrieval info: CONNECT: tck 0 0 0 0 @tck 0 0 0 0
// Retrieval info: CONNECT: tdi 0 0 0 0 @tdi 0 0 0 0
// Retrieval info: CONNECT: virtual_state_cdr 0 0 0 0 @virtual_state_cdr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_cir 0 0 0 0 @virtual_state_cir 0 0 0 0
// Retrieval info: CONNECT: virtual_state_e1dr 0 0 0 0 @virtual_state_e1dr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_e2dr 0 0 0 0 @virtual_state_e2dr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_pdr 0 0 0 0 @virtual_state_pdr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_sdr 0 0 0 0 @virtual_state_sdr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_udr 0 0 0 0 @virtual_state_udr 0 0 0 0
// Retrieval info: CONNECT: virtual_state_uir 0 0 0 0 @virtual_state_uir 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vjtag_bb.v TRUE
|
// ____________________________________________________________________
// Copyright(C) 2010: Altera Corporation
// Altera corporation Confidential
// IP to be used with altera devices only
// ____________________________________________________________________
module avalon_st_prtmux
(
// first avalon-st port input to this module
input wire avl_st_iport_0_eop,
input wire[5:0] avl_st_iport_0_error,
input wire avl_st_iport_0_sop,
input wire avl_st_iport_0_val,
input wire[63:0] avl_st_iport_0_data,
input wire[2:0] avl_st_iport_0_empty,
output reg avl_st_lpmx_iport_0_ready,
// second avalon-st port input to this module
input wire avl_st_iport_1_eop,
input wire[5:0] avl_st_iport_1_error,
input wire avl_st_iport_1_sop,
input wire avl_st_iport_1_val,
input wire[63:0] avl_st_iport_1_data,
input wire[2:0] avl_st_iport_1_empty,
output reg avl_st_lpmx_iport_1_ready,
input wire avl_st_default_iport_1_ready, // one from mactx
// output port connected to one of the two
// input ports as listed in lines above
output reg avl_st_oport_eop,
output reg[5:0] avl_st_oport_error,
output reg avl_st_oport_sop,
output reg avl_st_oport_val,
output reg[63:0] avl_st_oport_data,
output reg[2:0] avl_st_oport_empty,
input wire avl_st_oport_ready, // avl_st_snk_lpmx_ready
input wire cfg_lpmx_sel_iport_1
);
// ____________________________________________________________________
// iport0: macrx outputs, iport1: avl st tx outputs
// and oport is the avl st rx inputs. Please note that
// the direction of ready is opposite to rest of signals
//
always@(*)
begin
if (cfg_lpmx_sel_iport_1)
begin
// when loopback is enabled, the avl st rx bus
// is connected to avl st tx bus (iport_1)
// the ready signal for avl st tx will be connected
// to the oport ready signal
avl_st_oport_eop = avl_st_iport_1_eop;
avl_st_oport_error= avl_st_iport_1_error;
avl_st_oport_sop = avl_st_iport_1_sop;
avl_st_oport_val = avl_st_iport_1_val;
avl_st_oport_data = avl_st_iport_1_data;
avl_st_oport_empty = avl_st_iport_1_empty;
avl_st_lpmx_iport_1_ready = avl_st_oport_ready; // avl_st_snk_lpmx_ready;
// we are not considering port0 (default) to outport
// connection here, so it is dont care, we can leave
// the default connection for iport-0 ready as such
avl_st_lpmx_iport_0_ready = avl_st_oport_ready; // avl_st_snk_lpmx_ready;
end
else
begin
avl_st_oport_eop = avl_st_iport_0_eop;
avl_st_oport_error= avl_st_iport_0_error;
avl_st_oport_sop = avl_st_iport_0_sop;
avl_st_oport_val = avl_st_iport_0_val;
avl_st_oport_data = avl_st_iport_0_data;
avl_st_oport_empty = avl_st_iport_0_empty;
avl_st_lpmx_iport_0_ready = avl_st_oport_ready; // avl_st_snk_lpmx_ready;
avl_st_lpmx_iport_1_ready = avl_st_default_iport_1_ready;
end
end
// ____________________________________________________________________
//
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 4e5 + 123; long long n, m, k; int num[maxn]; int dp[maxn][5]; int presum[maxn]; int tmp[maxn]; int main(int argc, char const *argv[]) { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); std::cin >> n; for (int i = 1; i <= n; i++) { long long u; std::cin >> u; int one = 0; while (u) { if (u % 2 == 1) { one++; } u /= 2; } num[i] = one; } long long ans = 0; for (int i = 1; i <= n; i++) { dp[i][1] = dp[i - 1][1]; dp[i][0] = dp[i - 1][0]; presum[i] = presum[i - 1] + num[i]; if (presum[i] % 2 == 1) { dp[i][1] += 1; } else { dp[i][0] += 1; } } int cur = n + 1; for (int i = n; i >= 0; --i) { tmp[i] = cur; if (num[i] != 0) { cur = i; } } for (int i = 1; i <= n; i++) { int k = presum[i - 1] % 2; int cur = i; int sum = num[i]; int maxx = num[i]; for (int j = 1; j < 71; j++) { int kk = tmp[cur]; if (maxx <= sum / 2) { ans += dp[kk - 1][k] - dp[cur - 1][k]; } maxx = max(maxx, num[kk]); sum += num[kk]; cur = kk; if (cur > n) { break; } } ans += dp[n][k] - dp[cur - 1][k]; } std::cout << ans << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_TB_V
`define SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_TB_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_pwrgood_pp_pg_s.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VPWR;
reg VGND;
reg SLEEP;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
SLEEP = 1'bX;
UDP_IN = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 SLEEP = 1'b0;
#40 UDP_IN = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 SLEEP = 1'b1;
#120 UDP_IN = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 SLEEP = 1'b0;
#200 UDP_IN = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 UDP_IN = 1'b1;
#320 SLEEP = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 UDP_IN = 1'bx;
#400 SLEEP = 1'bx;
end
sky130_fd_sc_lp__udp_pwrgood_pp$PG$S dut (.UDP_IN(UDP_IN), .VPWR(VPWR), .VGND(VGND), .SLEEP(SLEEP), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_TB_V
|
#include <bits/stdc++.h> using namespace std; vector<int> myvec; long long int dp[100003]; int main() { int t1, t2, x, index1, index2, time, n; vector<int>::iterator it, it2; cin >> n; myvec.push_back(0); dp[0] = 0; for (int i = 0; i < n; i++) cin >> x, myvec.push_back(x); for (int i = 1; i <= n; i++) { time = myvec[i]; t1 = max(0, myvec[i] - 90); t2 = max(0, myvec[i] - 1440); it = upper_bound(myvec.begin(), myvec.end(), t1); it2 = upper_bound(myvec.begin(), myvec.end(), t2); index1 = it - myvec.begin(); index2 = it2 - myvec.begin(); if (myvec[i] - 90 < 0) { dp[i] = min(dp[0] + 50, dp[0] + 120); dp[i] = min(dp[i], dp[i - 1] + 20); } else { if (myvec[i] - 1440 < 0) dp[i] = min(dp[index1 - 1] + 50, dp[0] + 120); else dp[i] = min(dp[index1 - 1] + 50, dp[index2 - 1] + 120); dp[i] = min(dp[i], dp[i - 1] + 20); } } for (int i = 1; i <= n; i++) cout << dp[i] - dp[i - 1] << endl; return 0; } |
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: tg_status.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module.
// Error signal will be asserted if the comparsion is not equal.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_tg_status #(
parameter TCQ = 100,
parameter DWIDTH = 32
)
(
input clk_i ,
input rst_i ,
input manual_clear_error,
input data_error_i ,
input [DWIDTH-1:0] cmp_data_i,
input [DWIDTH-1:0] rd_data_i ,
input [31:0] cmp_addr_i ,
input [5:0] cmp_bl_i ,
input mcb_cmd_full_i ,
input mcb_wr_full_i,
input mcb_rd_empty_i,
output reg [64 + (2*DWIDTH - 1):0] error_status,
output error
);
reg data_error_r;
reg error_set;
assign error = error_set;
always @ (posedge clk_i)
data_error_r <= #TCQ data_error_i;
always @ (posedge clk_i)
begin
if (rst_i || manual_clear_error) begin
error_status <= #TCQ 'b0;
error_set <= #TCQ 1'b0;
end
else begin
// latch the first error only
if (data_error_i && ~data_error_r && ~error_set ) begin
error_status[31:0] <= #TCQ cmp_addr_i;
error_status[37:32] <= #TCQ cmp_bl_i;
error_status[40] <= #TCQ mcb_cmd_full_i;
error_status[41] <= #TCQ mcb_wr_full_i;
error_status[42] <= #TCQ mcb_rd_empty_i;
error_set <= #TCQ 1'b1;
error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i;
error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i;
end
error_status[39:38] <= #TCQ 'b0; // reserved
error_status[63:43] <= #TCQ 'b0; // reserved
end end
endmodule
|
`timescale 1ns / 1ps
module LED7Seg(clk, seg, segsel, data);
// seg bits and led segment:
// 77
// 2 6
// 11
// 3 5
// 44 0
output [7:0] seg;
output [3:0] segsel;
input clk;
input [15:0] data;
reg [18:0] counter;
wire [3:0] v0, v1, v2, v3;
assign v0 = data[3:0];
assign v1 = data[7:4];
assign v2 = data[11:8];
assign v3 = data[15:12];
wire [1:0] dsel = counter[18:17];
assign segsel = ~(1 << dsel);
assign seg = decodev(dsel, v0, v1, v2, v3);
always @ (posedge clk) begin
counter = counter + 1;
end
function [7:0] decodev (
input [1:0] vsel,
input [4:0] v0,
input [4:0] v1,
input [4:0] v2,
input [4:0] v3);
case (vsel)
2'b00: decodev = decode(v0);
2'b01: decodev = decode(v1);
2'b10: decodev = decode(v2);
2'b11: decodev = decode(v3);
endcase
endfunction
function [7:0] decode (input [3:0] n);
case (n)
4'h0: decode = 8'b00000011;
4'h1: decode = 8'b10011111;
4'h2: decode = 8'b00100101;
4'h3: decode = 8'b00001101;
4'h4: decode = 8'b10011001;
4'h5: decode = 8'b01001001;
4'h6: decode = 8'b01000001;
4'h7: decode = 8'b00011111;
4'h8: decode = 8'b00000001;
4'h9: decode = 8'b00001001;
4'hA: decode = 8'b00010001;
4'hb: decode = 8'b11000001;
4'hC: decode = 8'b01100011;
4'hd: decode = 8'b10000101;
4'hE: decode = 8'b01100001;
4'hF: decode = 8'b01110001;
endcase
endfunction
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBN_1_V
`define SKY130_FD_SC_MS__DFBBN_1_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog wrapper for dfbbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfbbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfbbn_1 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfbbn_1 (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfbbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK_N(CLK_N),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBN_1_V
|
// megafunction wizard: %In-System Sources and Probes%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsource_probe
// ============================================================
// File Name: hps_reset.v
// Megafunction Name(s):
// altsource_probe
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Internal Build 108 07/09/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module hps_reset (
probe,
source_clk,
source);
input probe;
input source_clk;
output [2:0] source;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES"
// Retrieval info: CONSTANT: INSTANCE_ID STRING "RST"
// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0"
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0"
// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3"
// Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe"
// Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]"
// Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk"
// Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0
// Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0
// Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; inline int gi() { int data = 0, fu = 1; char ch = 0; while (ch != - && (ch < 0 || ch > 9 )) ch = getchar(); if (ch == - ) fu = -1, ch = getchar(); while ( 0 <= ch && ch <= 9 ) data = (data << 1) + (data << 3) + (ch ^ 48), ch = getchar(); return data * fu; } int f[100005][205][2]; int n, A[100005]; inline void Merge(int i) { for (int j = 1; j <= 200; ++j) { f[i][j][0] = (f[i][j - 1][0] + f[i][j][0]) % 998244353; f[i][j][1] = (f[i][j - 1][1] + f[i][j][1]) % 998244353; } return; } int main() { n = gi(); for (int i = 1; i <= n; ++i) A[i] = gi(); if (A[1] != -1) f[1][A[1]][0] = 1; else for (int i = 1; i <= 200; ++i) f[1][i][0] = 1; Merge(1); for (int i = 2; i <= n; ++i) { for (int j = 1; j <= 200; ++j) if (A[i] == -1 || A[i] == j) { f[i][j][1] = (f[i - 1][j][0] - f[i - 1][j - 1][0] + 998244353) % 998244353; f[i][j][1] = (f[i][j][1] + (f[i - 1][200][1] - f[i - 1][j - 1][1] + 998244353) % 998244353) % 998244353; f[i][j][0] = (f[i - 1][j - 1][0] + f[i - 1][j - 1][1]) % 998244353; } Merge(i); } cout << f[n][200][1] << endl; return 0; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 29044 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w256,
w257,
w8224,
w8225,
w16,
w241,
w964,
w7261,
w29044;
assign w1 = i_data0;
assign w16 = w1 << 4;
assign w241 = w257 - w16;
assign w256 = w1 << 8;
assign w257 = w1 + w256;
assign w29044 = w7261 << 2;
assign w7261 = w8225 - w964;
assign w8224 = w257 << 5;
assign w8225 = w1 + w8224;
assign w964 = w241 << 2;
assign o_data0 = w29044;
//multiplier_block area estimate = 6752.59195394118;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/*
* Copyright (c) 2000 Guy Hutchison ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module pullupdown;
// declare several bussed wires
wire pull_up_1, pull_down_1;
wire [7:0] pull_up_8, pull_down_8;
reg error;
// assign pullups to each wire
pullup (pull_up_1);
pulldown (pull_down_1);
pullup u8 [7:0] (pull_up_8);
pulldown d8 [7:0] (pull_down_8);
// create tristate drivers for each wire
reg driver_1;
reg [7:0] driver_8;
reg driver_1_en, driver_8_en;
assign pull_up_1 = (driver_1_en) ? driver_1 : 1'bz;
assign pull_down_1 = (driver_1_en) ? driver_1 : 1'bz;
assign pull_up_8 = (driver_8_en) ? driver_8 : 8'bz;
assign pull_down_8 = (driver_8_en) ? driver_8 : 8'bz;
initial
begin : test_block
integer i;
// turn off all drivers
driver_1_en = 0;
driver_8_en = 0;
error = 0;
#1;
// check default values
if ((pull_up_1 !== 1'b1) || (pull_down_1 !== 1'b0) ||
(pull_up_8 !== 8'hFF) || (pull_down_8 !== 8'h00))
error = 1;
// turn on drivers
driver_1_en = 1;
driver_8_en = 1;
for (i=0; i<256; i=i+1)
begin
driver_1 = ~driver_1;
driver_8 = i;
$display ("Testing drivers with value %h", driver_8);
#1;
check_drivers;
#10;
end
if (error)
$display ("FAILED - pullupdown ");
else $display ("PASSED");
end // block: test_block
task check_drivers;
begin
if ((pull_up_1 !== driver_1) || (pull_down_1 !== driver_1) ||
(pull_up_8 !== driver_8) || (pull_down_8 !== driver_8))
error = 1;
end
endtask // check_drivers
endmodule // pullupdown
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__TAP_PP_BLACKBOX_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tap (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5; const int M = N + 7; const int MOD = 1e9 + 7; const long long INF = 1e16 + 17; const int K = 5; void ex() { printf( -1 n ); exit(0); } int a[M]; int l[M], r[M], len[M]; int an[M]; bool dp[M][K + 3]; pair<int, int> par[M][K + 3]; bool cmp(int i, int j) { return l[i] < l[j]; } void fillLR(int tl, int tr, int cnt, int st) { if (tl > tr) return; int d = tr - tl + 1; int cur = d / cnt; for (int i = st; i < st + cnt; ++i) { int x = cur + (d % cnt > i - st); while (x-- && tl <= tr) an[tl++] = i; } } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); l[a[i]] = l[a[i]] ? l[a[i]] : i; r[a[i]] = i; } vector<int> ord; for (int i = 1; i <= N; ++i) { if (l[i]) { len[i] = r[i] - l[i] + 1; ord.push_back(i); } if (len[i] > 5) ex(); } l[0] = -4; r[0] = 0; len[0] = K; ord.push_back(0); sort(ord.begin(), ord.end(), cmp); for (int t = 1; t < (int)ord.size(); ++t) { if (l[ord[t]] <= r[ord[t - 1]]) ex(); } dp[0][0] = true; int m = (int)ord.size() - 1; for (int t = 1; t <= m; ++t) { int i = ord[t]; int j = ord[t - 1]; for (int rr = 0; rr + len[j] <= K; ++rr) { if (!dp[t - 1][rr]) continue; for (int tr = 0; tr + len[i] <= K; ++tr) { for (int tl = 0; tl + tr + len[i] <= K; ++tl) { if (tr + tl + len[i] < 2) continue; int dist = (l[i] - tl) - (r[j] + rr) - 1; int cnt = i - j - 1; if (cnt * 2 <= dist && dist <= cnt * 5) { dp[t][tr] = true; par[t][tr] = make_pair(tl, rr); } } } } } int ans = 0, k = 0; for (int tr = 0; tr + len[ord[m]] <= K && r[ord[m]] + tr <= n; ++tr) { if (dp[m][tr]) { int len = n - r[ord[m]] - tr; if (len != 1) { fillLR(r[ord[m]] + tr + 1, n, len / 2, ord[m] + 1); k = tr; ans = ord[m] + len / 2; break; } } } if (!ans) ex(); while (m) { int cnt = ord[m] - ord[m - 1] - 1; pair<int, int> cur = par[m][k]; fillLR(l[ord[m]] - cur.first, r[ord[m]] + k, 1, ord[m]); fillLR(r[ord[m - 1]] + cur.second + 1, l[ord[m]] - cur.first - 1, cnt, ord[m - 1] + 1); m--; k = cur.second; } printf( %d n , ans); for (int i = 1; i <= n; ++i) printf( %d , an[i]); printf( n ); return 0; } |
// megafunction wizard: %In-System Sources and Probes%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsource_probe
// ============================================================
// File Name: JTAG_Probe1.v
// Megafunction Name(s):
// altsource_probe
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module JTAG_Probe1 (
probe,
source);
input [0:0] probe;
output source;
wire sub_wire0;
wire source = sub_wire0;
altsource_probe altsource_probe_component (
.probe (probe),
.source (sub_wire0)
// synopsys translate_off
,
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_clk (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
altsource_probe_component.enable_metastability = "NO",
altsource_probe_component.instance_id = "NONE",
altsource_probe_component.probe_width = 1,
altsource_probe_component.sld_auto_instance_index = "YES",
altsource_probe_component.sld_instance_index = 1,
altsource_probe_component.source_initial_value = " 0",
altsource_probe_component.source_width = 0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "NO"
// Retrieval info: CONSTANT: INSTANCE_ID STRING "NONE"
// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "1"
// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0"
// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "0"
// Retrieval info: USED_PORT: probe 0 0 1 0 INPUT NODEFVAL "probe[0..0]"
// Retrieval info: USED_PORT: source 0 0 0 0 OUTPUT NODEFVAL "source"
// Retrieval info: CONNECT: @probe 0 0 1 0 probe 0 0 1 0
// Retrieval info: CONNECT: source 0 0 0 0 @source 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL JTAG_Probe1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL JTAG_Probe1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL JTAG_Probe1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL JTAG_Probe1.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL JTAG_Probe1_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL JTAG_Probe1_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; char s[1000010]; int n; bool check(int len) { int now = 0, lft = 0; bool flag = 1; for (int i = 0; i < n; i++) { if (s[i] == R ) { flag = 0; if (now + 1 != len) now++; } else now--; if (now < lft) { lft = now; flag = 1; } } return flag; } int main() { scanf( %s , s); n = strlen(s); if (s[n - 1] == R ) { for (int i = 0; i < n; i++) { if (s[i] == R ) s[i] = L ; else s[i] = R ; } } if (check(n + 5)) { puts( 1 ); return 0; } int l = 0, r = n + 5, ret = 0; while (l <= r) { int mid = (l + r) >> 1; if (check(mid)) ret = mid, l = mid + 1; else r = mid - 1; } printf( %d n , ret); return 0; } |
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for xfcp_mod_axil
*/
module test_xfcp_mod_axil_32;
// Parameters
parameter XFCP_ID_TYPE = 16'h0001;
parameter XFCP_ID_STR = "AXIL Master";
parameter XFCP_EXT_ID = 0;
parameter XFCP_EXT_ID_STR = "";
parameter COUNT_SIZE = 16;
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 32;
parameter STRB_WIDTH = (DATA_WIDTH/8);
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] up_xfcp_in_tdata = 0;
reg up_xfcp_in_tvalid = 0;
reg up_xfcp_in_tlast = 0;
reg up_xfcp_in_tuser = 0;
reg up_xfcp_out_tready = 0;
reg m_axil_awready = 0;
reg m_axil_wready = 0;
reg [1:0] m_axil_bresp = 0;
reg m_axil_bvalid = 0;
reg m_axil_arready = 0;
reg [DATA_WIDTH-1:0] m_axil_rdata = 0;
reg [1:0] m_axil_rresp = 0;
reg m_axil_rvalid = 0;
// Outputs
wire up_xfcp_in_tready;
wire [7:0] up_xfcp_out_tdata;
wire up_xfcp_out_tvalid;
wire up_xfcp_out_tlast;
wire up_xfcp_out_tuser;
wire [ADDR_WIDTH-1:0] m_axil_awaddr;
wire [2:0] m_axil_awprot;
wire m_axil_awvalid;
wire [DATA_WIDTH-1:0] m_axil_wdata;
wire [STRB_WIDTH-1:0] m_axil_wstrb;
wire m_axil_wvalid;
wire m_axil_bready;
wire [ADDR_WIDTH-1:0] m_axil_araddr;
wire [2:0] m_axil_arprot;
wire m_axil_arvalid;
wire m_axil_rready;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
up_xfcp_in_tdata,
up_xfcp_in_tvalid,
up_xfcp_in_tlast,
up_xfcp_in_tuser,
up_xfcp_out_tready,
m_axil_awready,
m_axil_wready,
m_axil_bresp,
m_axil_bvalid,
m_axil_arready,
m_axil_rdata,
m_axil_rresp,
m_axil_rvalid
);
$to_myhdl(
up_xfcp_in_tready,
up_xfcp_out_tdata,
up_xfcp_out_tvalid,
up_xfcp_out_tlast,
up_xfcp_out_tuser,
m_axil_awaddr,
m_axil_awprot,
m_axil_awvalid,
m_axil_wdata,
m_axil_wstrb,
m_axil_wvalid,
m_axil_bready,
m_axil_araddr,
m_axil_arprot,
m_axil_arvalid,
m_axil_rready
);
// dump file
$dumpfile("test_xfcp_mod_axil_32.lxt");
$dumpvars(0, test_xfcp_mod_axil_32);
end
xfcp_mod_axil #(
.XFCP_ID_TYPE(XFCP_ID_TYPE),
.XFCP_ID_STR(XFCP_ID_STR),
.XFCP_EXT_ID(XFCP_EXT_ID),
.XFCP_EXT_ID_STR(XFCP_EXT_ID_STR),
.COUNT_SIZE(COUNT_SIZE),
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.STRB_WIDTH(STRB_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(up_xfcp_in_tdata),
.up_xfcp_in_tvalid(up_xfcp_in_tvalid),
.up_xfcp_in_tready(up_xfcp_in_tready),
.up_xfcp_in_tlast(up_xfcp_in_tlast),
.up_xfcp_in_tuser(up_xfcp_in_tuser),
.up_xfcp_out_tdata(up_xfcp_out_tdata),
.up_xfcp_out_tvalid(up_xfcp_out_tvalid),
.up_xfcp_out_tready(up_xfcp_out_tready),
.up_xfcp_out_tlast(up_xfcp_out_tlast),
.up_xfcp_out_tuser(up_xfcp_out_tuser),
.m_axil_awaddr(m_axil_awaddr),
.m_axil_awprot(m_axil_awprot),
.m_axil_awvalid(m_axil_awvalid),
.m_axil_awready(m_axil_awready),
.m_axil_wdata(m_axil_wdata),
.m_axil_wstrb(m_axil_wstrb),
.m_axil_wvalid(m_axil_wvalid),
.m_axil_wready(m_axil_wready),
.m_axil_bresp(m_axil_bresp),
.m_axil_bvalid(m_axil_bvalid),
.m_axil_bready(m_axil_bready),
.m_axil_araddr(m_axil_araddr),
.m_axil_arprot(m_axil_arprot),
.m_axil_arvalid(m_axil_arvalid),
.m_axil_arready(m_axil_arready),
.m_axil_rdata(m_axil_rdata),
.m_axil_rresp(m_axil_rresp),
.m_axil_rvalid(m_axil_rvalid),
.m_axil_rready(m_axil_rready)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> l[100010], r[100010], chosenl[100010], chosenr[100010]; vector<bool> badl[100010], badr[100010]; bool monst[100010]; int ans[100010]; vector<pair<int, int> > edges[100010]; int cnt[100010], toFather[100010], fromFather[100010]; void longPathChild(int v, int f) { if (monst[v]) ans[v] = 0; else ans[v] = -1000000000; for (int i = 0; i < edges[v].size(); i++) { if (edges[v][i].first != f) { longPathChild(edges[v][i].first, v); ans[v] = max(ans[v], ans[edges[v][i].first] + edges[v][i].second); } } } int longPathFather(int v, int f, int u) { for (int i = 0; i <= edges[v].size(); i++) { l[v].push_back(0); badl[v].push_back(true); chosenl[v].push_back(-1); r[v].push_back(0); badr[v].push_back(true); chosenr[v].push_back(-1); } l[v][0] = r[v][edges[v].size()] = -1000000000; if (monst[v]) l[v][0] = 0; for (int i = 0; i < edges[v].size(); i++) { int t; if (edges[v][i].first != f) t = ans[edges[v][i].first] + edges[v][i].second; else t = u; if (t > l[v][i]) { l[v][i + 1] = t; badl[v][i + 1] = false; chosenl[v][i + 1] = edges[v][i].first; } else if (t == l[v][i]) { l[v][i + 1] = l[v][i]; badl[v][i + 1] = true; chosenl[v][i + 1] = edges[v][i].first; } else { l[v][i + 1] = l[v][i]; badl[v][i + 1] = badl[v][i]; chosenl[v][i + 1] = chosenl[v][i]; } } for (int i = edges[v].size() - 1; i >= 0; i--) { int t; if (edges[v][i].first != f) t = ans[edges[v][i].first] + edges[v][i].second; else t = u; if (t > r[v][i + 1]) { r[v][i] = t; badr[v][i] = false; chosenr[v][i] = edges[v][i].first; } else if (t == r[v][i + 1]) { r[v][i] = r[v][i + 1]; badr[v][i] = true; chosenr[v][i] = edges[v][i].first; } else { r[v][i] = r[v][i + 1]; badr[v][i] = badr[v][i + 1]; chosenr[v][i] = chosenr[v][i + 1]; } } int ret = 0; for (int i = 0; i < edges[v].size(); i++) if (edges[v][i].first != f) { int t = longPathFather(edges[v][i].first, v, max(l[v][i], r[v][i + 1]) + edges[v][i].second); if (l[v][i] > r[v][i + 1] && l[v][i] == u && !badl[v][i]) ret += t; if (r[v][i + 1] > l[v][i] && r[v][i + 1] == u && !badr[v][i + 1]) ret += t; cnt[v] += t; } if (monst[v] && l[v][edges[v].size()] == u && !badl[v][edges[v].size()]) ret++; return (toFather[v] = ret); } void fillFromFather(int v, int f) { cnt[v] += fromFather[v]; for (int i = 0; i < edges[v].size(); i++) { if (max(l[v][i], r[v][i + 1]) < 0) continue; if (edges[v][i].first != f) { if (l[v][i] > r[v][i + 1] && !badl[v][i] && chosenl[v][i] != f) fromFather[chosenl[v][i]] += toFather[edges[v][i].first]; if (r[v][i + 1] > l[v][i] && !badr[v][i + 1] && chosenr[v][i + 1] != f) fromFather[chosenr[v][i + 1]] += toFather[edges[v][i].first]; } else { if (l[v][i] > r[v][i + 1] && !badl[v][i] && chosenl[v][i] != f) fromFather[chosenl[v][i]] += fromFather[v]; if (r[v][i + 1] > l[v][i] && !badr[v][i + 1] && chosenr[v][i + 1] != f) fromFather[chosenr[v][i + 1]] += fromFather[v]; } } if (monst[v] && !badl[v][edges[v].size()] && chosenl[v][edges[v].size()] != f) fromFather[chosenl[v][edges[v].size()]]++; for (int i = 0; i < edges[v].size(); i++) if (edges[v][i].first != f) fillFromFather(edges[v][i].first, v); } int main() { int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int a; cin >> a; monst[a] = true; } for (int i = 0; i < n - 1; i++) { int a, b, c; cin >> a >> b >> c; edges[a].push_back(pair<int, int>(b, c)); edges[b].push_back(pair<int, int>(a, c)); } longPathChild(1, -1); longPathFather(1, -1, -1000000000); fillFromFather(1, -1); int best = 0, bestcnt = 0; for (int i = 1; i <= n; i++) { if (monst[i]) continue; if (cnt[i] > best) { best = cnt[i]; bestcnt = 1; } else if (cnt[i] == best) bestcnt++; } cout << best << << bestcnt << endl; } |
#include <bits/stdc++.h> using namespace std; const int IINF = INT_MAX; const long long LLINF = LLONG_MAX; inline bool LT(double a, double b) { return !(fabs((a) - (b)) < (1e-8)) && a < b; } inline bool LTE(double a, double b) { return (fabs((a) - (b)) < (1e-8)) || a < b; } void compute() {} int main() { string s; cin >> s; deque<char> deq; int cnt = 0; int n = s.size(); for (int i = 0; i < n; ++i) { if (deq.empty()) { deq.push_back(s[i]); } else { if (deq.back() == s[i]) { deq.pop_back(); ++cnt; } else { deq.push_back(s[i]); } } } if (cnt % 2 == 0) puts( No ); else puts( Yes ); compute(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, i, j, ans, tmp, t, curr, x, r, sm, k, l; long long arr[1000005], res[1000005], par1[1000005], par2[1000005]; string s; vector<long long> vec[1000005]; void dfs(long long idx, long long par, long long col) { if (col != arr[idx]) { ans++; col = arr[idx]; } for (long long i = 0; i < vec[idx].size(); i++) { if (vec[idx][i] == par) continue; dfs(vec[idx][i], idx, col); } } int main() { ios_base::sync_with_stdio(false); cin >> n; for (i = 2; i <= n; i++) { cin >> x; vec[x].push_back(i); } for (i = 1; i <= n; i++) cin >> arr[i]; dfs(1, -1, 0); cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int in() { int x; scanf( %d , &x); return x; } template <typename T> istream &operator>>(istream &in, vector<T> &vec) { for (int i = 0; i < vec.size(); ++i) in >> vec[i]; return in; } template <typename T> ostream &operator<<(ostream &out, const vector<T> &vec) { for (int i = 0; i < vec.size(); ++i) out << vec[i] << ; return out; } const int INT = 1e6 + 1; long long eds = 0; int main() { long long a = in(), b = in(), c, n = 0, jac = 1; vector<int> x(a); vector<int> y(a); vector<bool> f(a); priority_queue<pair<long long, int>> qu; for (int i = 0; i < a; ++i) { x[i] = in(); } for (int i = 0; i < a; ++i) { y[i] = in(); } for (int i = 0; i < a; ++i) { if (x[i] % 100) { qu.push(make_pair(-(100 - x[i] % 100) * y[i], i)); b -= x[i] % 100; if (b < 0) { n += -(qu.top().first); f[qu.top().second] = true; qu.pop(); b += 100; } } } cout << n << endl; for (int i = 0; i < a; ++i) { cout << f[i] + x[i] / 100 << << (f[i] ? 0 : x[i] % 100) << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A32OI_BEHAVIORAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int t; long long a, b, c, d; long long solve(long long x) { long long times = x / d + 1; long long sum = (x / d + 1) * a; long long finished; if (x < c) { finished = 0; } else { finished = (x - c) / d + 1; } long long left = times - finished; long long a1 = x - (x / d) * d; sum -= left * a1 * b + left * (left - 1) / 2 * d * b; sum -= finished * b * c; return sum; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> t; while (t--) { cin >> a >> b >> c >> d; if (d >= c) { if (a > b * c) { cout << -1 << endl; } else { cout << a << endl; } } else { if (a > b * c) { cout << -1 << endl; } else { long long l = 0, r = 1e6 / d; while (l < r - 5) { long long ml = (l + r) / 2; long long mr = (ml + r) / 2; if (solve(ml * d) <= solve(mr * d)) { l = ml; } else { r = mr; } } long long mx = 0; for (long long i = l; i <= r; i++) { mx = max(mx, solve(i * d)); } cout << mx << endl; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxi = 3e6; vector<int> ans; int a[maxi]; int cnt[maxi]; int c[maxi]; void solve() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { c[i] = 0; cnt[i] = 0; } for (int i = 1; i <= n; i++) { int x; scanf( %d , &x); c[x]++; } for (int i = 1; i <= n; i++) if (c[i]) cnt[c[i]]++; for (int i = 1; i <= n; i++) cnt[i] += cnt[i - 1]; int ans = n; for (int i = 2; i <= n; i++) { int rez = 0; int ima = 0; for (int j = 1; j <= n / i + 1; j++) { int first = max((j - 1) * i + 1, (i - 1) * j); int sc = min(n, i * j); if (first > sc) continue; rez += j * (cnt[sc] - cnt[first - 1]); ima += cnt[sc] - cnt[first - 1]; } if (ima == cnt[n]) ans = min(ans, rez); } printf( %d n , ans); } int main() { int t; cin >> t; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; vector<string> names; char *cnames[] = { Anka , Chapay , Cleo , Troll , Dracul , Snowy , Hexadecimal }; int n = 7; int id(const string &s) { for (int i = 0; i < (int(names.size())); ++i) if (s == names[i]) return i; } vector<pair<int, int> > s; const int INF = 2000000100; int bdif = INF, bs = 0; int cp[7]; int pts[3]; void solve(int k = 0) { if (k == 7) { int ex[7]; int ngr[3] = {}; for (int i = 0; i < 7; ++i) ngr[cp[i]]++; for (int i = 0; i < 3; ++i) if (ngr[i] == 0) return; for (int i = 0; i < 7; ++i) ex[i] = pts[cp[i]] / ngr[cp[i]]; int maxex = -1, minex = INF; for (int i = 0; i < 7; ++i) { if (maxex < ex[i]) maxex = ex[i]; if (minex > ex[i]) minex = ex[i]; } double cdif = maxex - minex; int cs = 0; for (int i = 0; i < (int(s.size())); ++i) if (cp[s[i].first] == cp[s[i].second]) ++cs; if (cdif < bdif || (cdif == bdif && cs > bs)) bdif = cdif, bs = cs; } else { for (int i = 0; i < 3; ++i) { cp[k] = i; solve(k + 1); } } } int main() { for (int i = 0; i < n; ++i) names.push_back(string(cnames[i])); int k; cin >> k; while (k--) { string n1, n2; cin >> n1 >> n2 >> n2; s.push_back(make_pair(id(n1), id(n2))); } cin >> pts[0] >> pts[1] >> pts[2]; solve(); cout << bdif << << bs << endl; return 0; } |
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : ;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( -O2 ) using namespace std; string doSum(string a, string b) { if (a.size() < b.size()) swap(a, b); int j = a.size() - 1; for (int i = b.size() - 1; i >= 0; i--, j--) a[j] += (b[i] - 0 ); for (int i = a.size() - 1; i > 0; i--) { if (a[i] > 9 ) { int d = a[i] - 0 ; a[i - 1] = ((a[i - 1] - 0 ) + d / 10) + 0 ; a[i] = (d % 10) + 0 ; } } if (a[0] > 9 ) { string k; k += a[0]; a[0] = ((a[0] - 0 ) % 10) + 0 ; k[0] = ((k[0] - 0 ) / 10) + 0 ; a = k + a; } return a; } const int LIM = 1e5 + 5, MOD = 1e9 + 7; const long double EPS = 1e-9; string minofstrings(string a, string b) { if (a.size() == 0) return b; if (b.size() == 0) return a; if (a.size() > b.size()) return b; if (a.size() < b.size()) return a; if (a >= b) return b; return a; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long l; cin >> l; string s; cin >> s; vector<int> v; string ans1, ans2, ans3; int n = s.length(); if (s[n / 2] != 0 ) { ans1 = doSum(s.substr(0, n / 2), s.substr(n / 2, n - n / 2)); } else { int g = n / 2; int f = -1; for (int i = n / 2; i >= 0; --i) { if (s[i] != 0 ) { f = i; break; } } if (f != -1) ans1 = doSum(s.substr(0, f), s.substr(f, n - f)); } if (s[(n - 1) / 2] != 0 ) { ans2 = doSum(s.substr(0, (n - 1) / 2), s.substr((n - 1) / 2, n - (n - 1) / 2)); } else { int g = (n - 1) / 2; int f = -1; for (int i = (n - 1) / 2; i < n; ++i) { if (s[i] != 0 ) { f = i; break; } } if (f != -1) ans2 = doSum(s.substr(0, f), s.substr(f, n - f)); } if (s[(n + 1) / 2] != 0 ) { ans3 = doSum(s.substr(0, (n + 1) / 2), s.substr((n + 1) / 2, n - (n + 1) / 2)); } else { int g = (n + 1) / 2; int f = -1; for (int i = (n + 1) / 2; i < n; ++i) { if (s[i] != 0 ) { f = i; break; } } if (f != -1) ans3 = doSum(s.substr(0, f), s.substr(f, n - f)); } ans1 = minofstrings(ans1, ans2); ans1 = minofstrings(ans1, ans3); cout << ans1 << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SEDFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__SEDFXBP_PP_SYMBOL_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sedfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input DE ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SEDFXBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long double PI = 3.14159265359; long double DEL = 1e-10; int mod = 1000000007; long long fpow(long long x, long long n) { long long res = 1; while (n) { if (n & 1) res = res * x % mod; x = x * x % mod; n >>= 1; } return res; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } void sieve(long long n) { bool prime[1000006]; memset(prime, true, sizeof(prime)); long long rootn = (long long)sqrt(n); for (long long p = 2; p <= rootn; p++) if (prime[p] == true) for (long long i = p * p; i <= n; i += p) prime[i] = false; prime[1] = 0; } const long long N = 300050; long long cnt, sum, mid, mx, mn, ans, a[N], b[N]; long long n, m, d, i, j, k, l, p, q, r, t, w, x, y, z; bool f, f1, f2; string s; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; cout << (n / k + 1) * k; } |
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.2
//
// Date: $Date: 2004/11/08 16:19:26 $
// Tag: $Name: i+H-38+78751 $
// File: $RCSfile: global_logic.ejava,v $
// Rev: $Revision: 1.1.6.2 $
//
// Company: Xilinx
// Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// GLOBAL_LOGIC
//
// Author: Nigel Gulstone
// Xilinx - Embedded Networking System Engineering Group
//
// Description: The GLOBAL_LOGIC module handles channel bonding, channel
// verification, channel error manangement and idle generation.
//
// This module supports 1 4-byte lane designs
//
`timescale 1 ns / 10 ps
module GLOBAL_LOGIC
(
// MGT Interface
CH_BOND_DONE,
EN_CHAN_SYNC,
// Aurora Lane Interface
LANE_UP,
SOFT_ERROR,
HARD_ERROR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
GEN_A,
GEN_K,
GEN_R,
GEN_V,
RESET_LANES,
// System Interface
USER_CLK,
RESET,
POWER_DOWN,
CHANNEL_UP,
START_RX,
CHANNEL_SOFT_ERROR,
CHANNEL_HARD_ERROR
);
`define DLY #1
//***********************************Port Declarations*******************************
// MGT Interface
input CH_BOND_DONE;
output EN_CHAN_SYNC;
// Aurora Lane Interface
input [0:1] SOFT_ERROR;
input LANE_UP;
input HARD_ERROR;
input CHANNEL_BOND_LOAD;
input [0:3] GOT_A;
input GOT_V;
output GEN_A;
output [0:3] GEN_K;
output [0:3] GEN_R;
output [0:3] GEN_V;
output RESET_LANES;
// System Interface
input USER_CLK;
input RESET;
input POWER_DOWN;
output CHANNEL_UP;
output START_RX;
output CHANNEL_SOFT_ERROR;
output CHANNEL_HARD_ERROR;
//*********************************Wire Declarations**********************************
wire gen_ver_i;
wire reset_channel_i;
wire did_ver_i;
//*********************************Main Body of Code**********************************
// State Machine for channel bonding and verification.
CHANNEL_INIT_SM channel_init_sm_i
(
// MGT Interface
.CH_BOND_DONE(CH_BOND_DONE),
.EN_CHAN_SYNC(EN_CHAN_SYNC),
// Aurora Lane Interface
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.GOT_A(GOT_A),
.GOT_V(GOT_V),
.RESET_LANES(RESET_LANES),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET),
.START_RX(START_RX),
.CHANNEL_UP(CHANNEL_UP),
// Idle and Verification Sequence Generator Interface
.DID_VER(did_ver_i),
.GEN_VER(gen_ver_i),
// Channel Error Management Module Interface
.RESET_CHANNEL(reset_channel_i)
);
// Idle and verification sequence generator module.
IDLE_AND_VER_GEN idle_and_ver_gen_i
(
// Channel Init SM Interface
.GEN_VER(gen_ver_i),
.DID_VER(did_ver_i),
// Aurora Lane Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// System Interface
.RESET(RESET),
.USER_CLK(USER_CLK)
);
// Channel Error Management module.
CHANNEL_ERROR_DETECT channel_error_detect_i
(
// Aurora Lane Interface
.SOFT_ERROR(SOFT_ERROR),
.HARD_ERROR(HARD_ERROR),
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.POWER_DOWN(POWER_DOWN),
.CHANNEL_SOFT_ERROR(CHANNEL_SOFT_ERROR),
.CHANNEL_HARD_ERROR(CHANNEL_HARD_ERROR),
// Channel Init State Machine Interface
.RESET_CHANNEL(reset_channel_i)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int max(int &a, int &b) { return (a > b ? a : b); } unsigned long long max(unsigned long long &a, unsigned long long &b) { return (a > b ? a : b); } int min(int &a, int &b) { return (a < b ? a : b); } long long int bits_needed(long long int val) { long long int count = 0; while (val) count++, val >>= 1; return count; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 0, n = 0, i = 0; long long int val = 0, prev = 0, ans = 0; cin >> t; while (t-- > 0) { ans = 0; cin >> n; cin >> prev; for (i = 1; i < n; i++) { cin >> val; if (val < prev) { ans = max(ans, bits_needed(prev - val)); } else prev = val; } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long t[100005], T[100005], x[100005], c[100005]; long long n, m; int main() { while (scanf( %lld%lld , &n, &m) != EOF) { int i; int a, b; long long sum = 0; for (i = 1; i <= n; i++) scanf( %lld%lld%lld%lld , &t[i], &T[i], &x[i], &c[i]); for (i = 1; i <= n; i++) { if (t[i] >= T[i]) { sum += (c[i] + x[i] * m); } else { if (t[i] + m <= T[i]) sum += c[i]; else { long long a, b; long long cha = T[i] - t[i]; long long d = m % (T[i] - t[i]); long long w = m / (T[i] - t[i]); if (d) a = (w + 1) * c[i]; else a = (w * c[i]); b = x[i] * m + c[i]; sum += min(a, b); } } } printf( %I64d n , sum); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1N_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__INPUTISO1N_PP_BLACKBOX_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__inputiso1n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1N_PP_BLACKBOX_V
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_led_pio (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 9: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 9: 0] data_out;
wire [ 9: 0] out_port;
wire [ 9: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {10 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 15;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[9 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, sum = 0; int num[1000]; int x, y; cin >> n; for (int i = 1; i <= n; i++) { cin >> num[i]; sum += num[i]; } cin >> x >> y; int cur = 0; for (int i = 1; i <= n; i++) { if (cur >= x && cur <= y && (sum - cur) >= x && (sum - cur) <= y) { cout << i << endl; return 0; } cur += num[i]; } cout << 0 << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 3e3 + 5; int dw[N], up[N], E[N][2], Mn; vector<pair<int, int> > g[N]; void dfs_down(int v, int p) { dw[v] = 0; for (pair<int, int> u : g[v]) if (u.first != p) dfs_down(u.first, v), dw[v] += dw[u.first] + u.second; } void dfs_up(int v, int p, int f = -1) { if (f != -1) { up[v] = up[p] + dw[p] - dw[v] + f - (f == 0); } else up[v] = 0; Mn = min(Mn, dw[v] + up[v]); for (pair<int, int> u : g[v]) if (u.first != p) dfs_up(u.first, v, u.second ^ 1); } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n; cin >> n; if (n == 1) return cout << 0 n , 0; for (int i = 0; i < n - 1; i++) { cin >> E[i][0] >> E[i][1]; g[E[i][0]].push_back({E[i][1], 0}); g[E[i][1]].push_back({E[i][0], 1}); } int ans = n; for (int i = 0; i < n - 1; i++) { Mn = n, dfs_down(E[i][0], E[i][1]), dfs_up(E[i][0], E[i][1]); int cur = Mn; Mn = n, dfs_down(E[i][1], E[i][0]), dfs_up(E[i][1], E[i][0]); cur += Mn; ans = min(ans, cur); } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, q; char c; vector<int> a(10); cin >> n; for (int i = 0; i < n; i++) { cin >> c; if (c == L ) { q = 0; while (a[q] == 1) { q++; } a[q] = 1; } else if (c == R ) { q = 9; while (a[q] == 1) { q--; } a[q] = 1; } else { q = (int)c - 48; a[q] = 0; } } for (int i = 0; i < 10; i++) { cout << a[i]; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; string s; struct str { int len; bool vis; string pre, suf; void push_front(char ch) { if (!len) vis = 0; else if (ch ^ pre[0]) vis = ch < pre[0]; pre = ch + pre; if (len < 2) suf = ch + suf; else if (pre.length() > 10) pre.pop_back(); len++; } } ans[100005]; int main() { int i; cin >> s; n = s.length(); ans[n].len = ans[n].vis = 0; ans[n].pre = ans[n].suf = ; s += # ; for (i = n - 1; i >= 0; i--) if (s[i] ^ s[i + 1]) ans[i] = ans[i + 1], ans[i].push_front(s[i]); else { ans[i] = ans[i + 2]; if (s[i] < ans[i].pre[0] || s[i] == ans[i].pre[0] && ans[i].vis) { ans[i].push_front(s[i]); ans[i].push_front(s[i]); } } for (i = 0; i < n; i++) { cout << ans[i].len << ; if (ans[i].len <= 10) cout << ans[i].pre << endl; else cout << ans[i].pre.substr(0, 5) << ... << ans[i].suf << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int as[10001]; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, k; cin >> n >> k; for (int i = 1; i <= n; ++i) as[i] = 1; as[n] = 0; for (int j = 0; j < k; ++j) { for (int i = 1; i <= n - (1 << (j + 1)); ++i) { if (as[i] != n - i) { cout << n - (1 << j) << ; as[i] += as[n - (1 << j)]; } else { cout << n << ; } } int x = 1; if (n - (1 << (j + 1)) + 1 > 0) { for (int i = n - (1 << (j + 1)) + 1; i <= n; ++i) { if (as[i] != n - i) { cout << n - (1 << j) + x << ; as[i] += as[n - (1 << j) + x]; ++x; } else { cout << n << ; } } } else { for (int i = 1; i <= n; ++i) { if (as[i] != n - i) { cout << i + as[i] << ; as[i] += as[i + as[i]]; } else { cout << n << ; } } } cout << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFBUF_TB_V
`define SKY130_FD_SC_LS__BUFBUF_TB_V
/**
* bufbuf: Double buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__bufbuf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__bufbuf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFBUF_TB_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Clk_ctrl.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:13 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
module Clk_ctrl(
Reset ,
Clk_125M ,
//host interface,
Speed ,
//Phy interface ,
Gtx_clk ,
Rx_clk ,
Tx_clk ,
//interface clk ,
MAC_tx_clk ,
MAC_rx_clk ,
MAC_tx_clk_div ,
MAC_rx_clk_div
);
input Reset ;
input Clk_125M ;
//host interface
input [2:0] Speed ;
//Phy interface
output Gtx_clk ;//used only in GMII mode
input Rx_clk ;
input Tx_clk ;//used only in MII mode
//interface clk signals
output MAC_tx_clk ;
output MAC_rx_clk ;
output MAC_tx_clk_div ;
output MAC_rx_clk_div ;
//******************************************************************************
//internal signals
//******************************************************************************
wire Rx_clk_div2 ;
wire Tx_clk_div2 ;
//******************************************************************************
//
//******************************************************************************
assign Gtx_clk =Clk_125M ;
assign MAC_rx_clk =Rx_clk ;
CLK_DIV2 U_0_CLK_DIV2(
.Reset (Reset ),
.IN (Rx_clk ),
.OUT (Rx_clk_div2 )
);
CLK_DIV2 U_1_CLK_DIV2(
.Reset (Reset ),
.IN (Tx_clk ),
.OUT (Tx_clk_div2 )
);
CLK_SWITCH U_0_CLK_SWITCH(
.IN_0 (Rx_clk_div2 ),
.IN_1 (Rx_clk ),
.SW (Speed[2] ),
.OUT (MAC_rx_clk_div )
);
CLK_SWITCH U_1_CLK_SWITCH(
.IN_0 (Tx_clk ),
.IN_1 (Clk_125M ),
.SW (Speed[2] ),
.OUT (MAC_tx_clk )
);
CLK_SWITCH U_2_CLK_SWITCH(
.IN_0 (Tx_clk_div2 ),
.IN_1 (Clk_125M ),
.SW (Speed[2] ),
.OUT (MAC_tx_clk_div )
);
endmodule |
#include <bits/stdc++.h> using namespace std; int w[1501000], cnt[1501000]; int main() { int N, i; int po, ans; scanf( %d , &N); for (int i = (0); i < (N); i++) scanf( %d , w + i); sort(w, w + N); memset(cnt, 0, sizeof(cnt)); for (int i = (0); i < (N); i++) cnt[w[i]]++; po = 0; ans = 0; for (int po = (0); po < (1501000); po++) { if (cnt[po] == 0) continue; cnt[po + 1] += cnt[po] / 2; if (cnt[po] % 2) ans++; } printf( %d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTN_TB_V
`define SKY130_FD_SC_LS__SDFRTN_TB_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfrtn.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ls__sdfrtn dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTN_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_G_TB_V
`define SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_G_TB_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_pwrgood_pp_g.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 UDP_IN = 1'b1;
#80 VGND = 1'b1;
#100 UDP_IN = 1'b0;
#120 VGND = 1'b0;
#140 VGND = 1'b1;
#160 UDP_IN = 1'b1;
#180 VGND = 1'bx;
#200 UDP_IN = 1'bx;
end
sky130_fd_sc_hdll__udp_pwrgood_pp$G dut (.UDP_IN(UDP_IN), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_G_TB_V
|
// =======================================================================
// Filename: simple_alu.v
// Created by: Tareque Ahmad
// Date: Feb 20, 2015
// ECE 510: Pre-Silicon Validation
// Lab 0
// This is a simple FSM based ALU that supports 4 basic operations
// based on two operands and an opcode
//
// =======================================================================
// Let's define some defines
`define DATA_WIDTH 8
`define RESET 9'b000000001
`define IDLE 9'b000000010
`define DATA_A 9'b000000100
`define DATA_B 9'b000001000
`define ADD 9'b000010000
`define SUB 9'b000100000
`define PAR 9'b001000000
`define COMP 9'b010000000
`define DONE 9'b100000000
// Define the module
module simple_alu
(
// Global inputs
input clk,
input reset_n,
// Control inputs
input opcode_valid,
input opcode,
// Data input
input [`DATA_WIDTH-1:0] data,
// Outputs
output done,
output overflow,
output [`DATA_WIDTH-1:0] result
);
// Define some parameters
parameter OPCODE_ADD = 2'b00;
parameter OPCODE_SUB = 2'b01;
parameter OPCODE_PAR = 2'b10;
parameter OPCODE_COMP = 2'b11;
// Define registers for FSM
reg [8:0] current_state;
reg [8:0] next_state;
// Define internal registers for data
reg [`DATA_WIDTH-1:0] int_data_a;
reg [`DATA_WIDTH-1:0] int_data_b;
reg [1:0] int_opcode;
// Define internal registers for outputs
reg int_done;
reg int_overflow;
reg [`DATA_WIDTH:0] int_result;
// Define internal registers for outputs from full adder
wire [`DATA_WIDTH-1:0] adder_sum;
wire adder_cout;
// Define internal registers for outputs from full subtractor
wire [`DATA_WIDTH-1:0] sub_diff;
wire sub_borrowout;
// Define internal registers for outputs from parity generator
wire [`DATA_WIDTH-1:0] parity_out;
// Define internal registers for outputs from comparator
wire [`DATA_WIDTH-1:0] comp_out;
// Instantiate full adder
full_adder_generic #(.WIDTH(`DATA_WIDTH)) FA_ALU (.Ain(int_data_a),
.Bin(int_data_b),
.Cin(1'b0),
.Sum(adder_sum),
.Cout(adder_cout));
// Instantiate full subtractor
full_sub_generic #(.WIDTH(`DATA_WIDTH)) SUB_ALU (.Xin(int_data_a),
.Yin(int_data_b),
.BorrowIn(1'b0),
.Diff(sub_diff),
.BorrowOut(sub_borrowout));
// Instantiate parity generator
parity_gen_generic #(.WIDTH(`DATA_WIDTH)) PAR_ALU (.Ain(int_data_a),
.Bin(int_data_b),
.ParityOut(parity_out));
// Instantiate comparator
comparator_generic #(.WIDTH(`DATA_WIDTH)) COMP_ALU (.Ain(int_data_a),
.Bin(int_data_b),
.CompOut(comp_out));
// always block to drive FSM
always @(posedge clk or negedge reset_n or current_state)
if (!reset_n) current_state = `RESET;
else current_state = next_state;
// Always block to define next state and calculate outputs
always @(posedge clk) begin
//$display("SIMPLE_ALU - opcode: %h \t opcode_valid: %h \t data: %h \t result: %h \t overflow: %h \t done: %h \t current_state: %h",opcode,opcode_valid,data,result,overflow,done,current_state);
//$display("int_data_a: %h \t int_data_b: %h", int_data_a, int_data_b);
case (current_state)
// This is the dafault state when the FSM is in reset
// The FSM stays in this state as long as reset_n is asserted
// otherwise, it jumps to IDLE state
// Outputs are cleared in this state
//
`RESET: begin
// Clear the outputs
int_opcode = 2'b00;
int_done = 0;
int_overflow = 0;
int_data_a = {`DATA_WIDTH{1'b0}};
int_data_b = {`DATA_WIDTH{1'b0}};
int_result = {`DATA_WIDTH{1'b0}};
if (!reset_n) begin
next_state = `RESET;
end else begin
next_state = `IDLE;
end
end
// This is the dafault state when there is no valid opcode in the machine.
// The FSM stays in this state as long as opcode_valid is de-asserted,
// otherwise it jumps to DATA_A state
// Outputs are cleared in this state
//
`IDLE: begin
// Clear the outputs
int_opcode = 2'b00;
int_done = 0;
int_overflow = 0;
int_data_a = {`DATA_WIDTH{1'b0}};
int_data_b = {`DATA_WIDTH{1'b0}};
int_result = {`DATA_WIDTH{1'b0}};
if (opcode_valid) begin
next_state = `DATA_A;
end else begin
next_state = `IDLE;
end
end
// First operand (data) and bit[0] of opcode is latched in this state
// The FSM does not stay in this state for more than one clock
// It makes an unconditional jump to DATA_B state from here
// Outputs are not valid at this state (yet)
//
`DATA_A: begin
// Clear the outputs
int_done = 0;
int_overflow = 0;
int_result = {`DATA_WIDTH{1'b0}};
if (!opcode_valid) begin
next_state = `IDLE;
end else begin
// Latch the data
int_data_a = data;
int_opcode[0] = opcode;
next_state = `DATA_B;
end
end
// Second operand (data) and bit[1] of opcode is latched in this state
// The FSM does not stay in this state for more than one clock
// It makes an conditional jump to one of the operational states from
// here
// Outputs are still not valid at this state
//
`DATA_B: begin
// Clear the outputs
int_done = 0;
int_overflow = 0;
int_result = {`DATA_WIDTH{1'b0}};
if (!opcode_valid) begin
next_state = `IDLE;
end else begin
// Latch the data
int_data_b = data;
int_opcode[1] = opcode;
if (int_opcode == OPCODE_ADD)
next_state = `ADD;
else if (int_opcode == OPCODE_SUB)
next_state = `SUB;
else if (int_opcode == OPCODE_PAR)
next_state = `PAR;
else if (int_opcode == OPCODE_COMP)
next_state = `COMP;
else
next_state = `IDLE;
end
end
// This is an individual operation state
// Outputs are derived from full adder
// The FSM does not stay in this state for more than one clock
// It makes an unconditional jump to DONE state from here
//
`ADD: begin
int_result = adder_sum;
int_overflow = adder_cout;
next_state = `DONE;
end
// This is an individual operation state
// Outputs are derived from full subtractor
// The FSM does not stay in this state for more than one clock
// It makes an unconditional jump to DONE state from here
//
`SUB: begin
int_result = sub_diff;
int_overflow = sub_borrowout;
next_state = `DONE;
end
// This is an individual operation state
// Outputs are derived from parity generator
// The FSM does not stay in this state for more than one clock
// It makes an unconditional jump to DONE state from here
//
`PAR: begin
int_result = parity_out;
int_overflow = ^parity_out;
next_state = `DONE;
end
// This is an individual operation state
// Outputs are derived from comparator
// The FSM does not stay in this state for more than one clock
// It makes an unconditional jump to DONE state from here
//
`COMP: begin
int_result = comp_out;
int_overflow = 0;
next_state = `DONE;
end
// This is final state for an individual operation
// Outputs are still valid here
// The FSM WILL stay in this state as long as opcode_valid is asserted.
// It will jump to IDLE state if opcode_valid is de-asserted
//
`DONE: begin
// done output is assrted here
int_done = 1;
if (opcode_valid) begin
next_state = `DONE;
end else begin
next_state = `IDLE;
end
end
endcase
end
// Continuous assignment for the outputs
assign done = int_done;
assign overflow = int_overflow;
assign result = int_result[`DATA_WIDTH-1:0];
endmodule // simple_alu
|
#include <bits/stdc++.h> using namespace std; int main() { int t, a, b, c, d, ans1, ans2, ans3; cin >> t; while (t--) { ans1 = 0; ans2 = 0; ans3 = 0; cin >> a >> b >> c >> d; ans1 = a / b; ans2 = (c - 1) / b; ans3 = d / b; ans1 -= ans3; ans1 += ans2; cout << ans1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n; cin >> n; long long out = n * (n + 1) * (n + 2) / 6; out *= n * (n + 1) * (n + 2) * (n + 3) * (n + 4) / 120; cout << out << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; void upd(int& a, int b) { a = max(a, b); } int main() { int n, m; cin >> n >> m; vector<int> a(n), b(m); for (int i = 0; i < (int)n; ++i) cin >> a[i]; for (int i = 0; i < (int)m; ++i) cin >> b[i]; sort(a.begin(), a.end()); sort(b.begin(), b.end()); vector<int> to_seg(n); int seg = 0; vector<int> start, end; for (int i = 0; i < (int)a.size(); ++i) { if (i == 0 || a[i] != a[i - 1] + 1) { seg++; if (i != 0) end.push_back(i - 1); start.push_back(i); } to_seg[i] = seg - 1; } end.push_back(n - 1); vector<int> z(start.size()), d(start.size()); for (int segment = 0; segment < (int)start.size(); ++segment) { int first = -1; int cnt = 0; for (int i = 0; i < (int)m; ++i) { if (b[i] < a[start[segment]]) first = i; else if (b[i] <= a[end[segment]]) cnt++; } int cnt_orig = cnt; upd(d[segment], cnt); if (segment) upd(d[segment], cnt + z[segment - 1]); if (first != -1) { for (int i = first; i >= 0; --i) { ++cnt; int r = a[start[segment]]; int l = b[i]; if (start[segment] - (r - l) >= 0) { int Q = 0; int X = to_seg[start[segment] - (r - l)] - 1; if (X >= 0) Q = z[X]; upd(d[segment], cnt + Q); } } } cnt = 0; for (int i = first + cnt_orig + 1; i < m; ++i) { ++cnt; int l = a[end[segment]]; int r = b[i]; if (end[segment] + (r - l) < n) { upd(z[to_seg[end[segment] + (r - l)]], d[segment] + cnt); } } upd(z[segment], d[segment]); } cout << *max_element(z.begin(), z.end()) << endl; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void amin(T &x, const T &y) { if (y < x) x = y; } template <class T> inline void amax(T &x, const T &y) { if (x < y) x = y; } template <class Iter> void rprintf(const char *fmt, Iter begin, Iter end) { for (bool sp = 0; begin != end; ++begin) { if (sp) putchar( ); else sp = true; printf(fmt, *begin); } putchar( n ); } int N; int A[200011]; int B[200011]; using Tuple = tuple<int, int, int>; Tuple X[100011]; void MAIN() { scanf( %d , &N); for (int i = 0, i_len = (N); i < i_len; ++i) scanf( %d , A + i); int Q; scanf( %d , &Q); vector<Tuple> sortedX; sortedX.reserve(Q); for (int i = 0, i_len = (Q); i < i_len; ++i) { int s, t, u; scanf( %d%d%d , &s, &t, &u); s--; u--; X[i] = Tuple(s, t, u); sortedX.emplace_back(s, t, -1); } sort(sortedX.begin(), sortedX.end()); sortedX.erase(unique(sortedX.begin(), sortedX.end()), sortedX.end()); long long sum = 0; for (int i = 0, i_len = (N); i < i_len; ++i) sum += A[i]; for (int i = 0, i_len = (Q); i < i_len; ++i) { int s, t, u; tie(s, t, u) = X[i]; auto it = lower_bound(sortedX.begin(), sortedX.end(), Tuple(s, t, -1)); int s0, t0, u0; tie(s0, t0, u0) = *it; if (0 <= u0) { sum -= max(0, A[u0] - B[u0]); B[u0]--; sum += max(0, A[u0] - B[u0]); } if (0 <= u) { sum -= max(0, A[u] - B[u]); B[u]++; sum += max(0, A[u] - B[u]); } *it = Tuple(s, t, u); printf( %lld n , sum); } } int main() { int TC = 1; for (int tc = 0, tc_len = (TC); tc < tc_len; ++tc) MAIN(); return 0; } |
#include <bits/stdc++.h> using namespace std; inline int toInt(string s) { int v; istringstream sin(s); sin >> v; return v; } template <class T> inline string toString(T x) { ostringstream sout; sout << x; return sout.str(); } const double EPS = 1e-10; const double PI = acos(-1.0); vector<int> x, y; int xo, yo; int n, d; int dp[1000][1000]; int sqr(int a) { return a * a; } int dfs(int x1, int y1) { if (sqr(x1) + sqr(y1) > sqr(d)) return dp[x1 + 500][y1 + 500] = 1; if (dp[x1 + 500][y1 + 500] != -1) return dp[x1 + 500][y1 + 500]; for (int i = (0); i < (int((x).size())); ++i) if (!dfs(x1 + x[i], y1 + y[i])) return dp[x1 + 500][y1 + 500] = 1; return dp[x1 + 500][y1 + 500] = 0; } int main(int argc, char *argv[]) { ios::sync_with_stdio(false); memset(dp, -1, sizeof dp); cin >> xo >> yo >> n >> d; for (int i = (0); i < (n); ++i) { int xi, yi; cin >> xi >> yi; x.push_back(xi); y.push_back(yi); } if (dfs(xo, yo)) cout << Anton << endl; else cout << Dasha << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void per() { cerr << endl; } template <typename Head, typename... Tail> void per(Head H, Tail... T) { cerr << H << ; per(T...); } template <class T> bool uin(T& a, T b) { return a > b ? (a = b, true) : false; } template <class T> bool uax(T& a, T b) { return a < b ? (a = b, true) : false; } template <class U, class V> ostream& operator<<(ostream& out, const pair<U, V>& a) { return out << ( << a.first << , << a.second << ) ; } template <class U, class V> istream& operator>>(istream& in, pair<U, V>& a) { return in >> a.first >> a.second; } template <typename W, typename T = typename enable_if<!is_same<W, string>::value, typename W::value_type>::type> ostream& operator<<(ostream& out, const W& v) { out << { ; for (const auto& first : v) out << first << , ; return out << } ; } template <class T> void readArr(T from, T to) { for (auto i = from; i != to; ++i) cin >> *i; } mt19937 mrand(1337); unsigned int myRand32() { return mrand() & (unsigned int)(-1); } unsigned long long myRand64() { return ((unsigned long long)myRand32() << 32) ^ myRand32(); } const int mod = 1000000007; void add(int& a, int b) { a += b; if (a >= mod) a -= mod; } void dec(int& a, int b) { a -= b; if (a < 0) a += mod; } int mult(int a, int b) { return a * (long long)b % mod; } int bp(int a, int b) { int res = 1; while (b > 0) { if (b & 1) res = mult(res, a); a = mult(a, a); b >>= 1; } return res; } int main() { int vl = 1, vr = 1000000000; cout << ? 1 1 << endl; int base1; cin >> base1; while (vl + 1 < vr) { int vm = (vl + vr) >> 1; cout << ? 1 << vm << endl; int first; cin >> first; if (first == base1 - (vm - 1)) vl = vm; else vr = vm; } int y1 = vl; int x1 = base1 - (y1 - 1) + 1; cout << ? 1000000000 1 << endl; int base2; cin >> base2; int x2 = 1000000000 - (base2 - (y1 - 1)); cout << ? 1 1000000000 << endl; int base3; cin >> base3; int y2 = 1000000000 - (base3 - (x1 - 1)); cout << ! << x1 << << y1 << << x2 << << y2 << endl; } |
`include "constants.vh"
`default_nettype none
module reorderbuf
(
input wire clk,
input wire reset,
//Write Signal
input wire dp1,
input wire [`RRF_SEL-1:0] dp1_addr,
input wire [`INSN_LEN-1:0] pc_dp1,
input wire storebit_dp1,
input wire dstvalid_dp1,
input wire [`REG_SEL-1:0] dst_dp1,
input wire [`GSH_BHR_LEN-1:0] bhr_dp1,
input wire isbranch_dp1,
input wire dp2,
input wire [`RRF_SEL-1:0] dp2_addr,
input wire [`INSN_LEN-1:0] pc_dp2,
input wire storebit_dp2,
input wire dstvalid_dp2,
input wire [`REG_SEL-1:0] dst_dp2,
input wire [`GSH_BHR_LEN-1:0] bhr_dp2,
input wire isbranch_dp2,
input wire exfin_alu1,
input wire [`RRF_SEL-1:0] exfin_alu1_addr,
input wire exfin_alu2,
input wire [`RRF_SEL-1:0] exfin_alu2_addr,
input wire exfin_mul,
input wire [`RRF_SEL-1:0] exfin_mul_addr,
input wire exfin_ldst,
input wire [`RRF_SEL-1:0] exfin_ldst_addr,
input wire exfin_branch,
input wire [`RRF_SEL-1:0] exfin_branch_addr,
input wire exfin_branch_brcond,
input wire [`ADDR_LEN-1:0] exfin_branch_jmpaddr,
output reg [`RRF_SEL-1:0] comptr,
output wire [`RRF_SEL-1:0] comptr2,
output wire [1:0] comnum,
output wire stcommit,
output wire arfwe1,
output wire arfwe2,
output wire [`REG_SEL-1:0] dstarf1,
output wire [`REG_SEL-1:0] dstarf2,
output wire [`ADDR_LEN-1:0] pc_combranch,
output wire [`GSH_BHR_LEN-1:0] bhr_combranch,
output wire brcond_combranch,
output wire [`ADDR_LEN-1:0] jmpaddr_combranch,
output wire combranch,
input wire [`RRF_SEL-1:0] dispatchptr,
input wire [`RRF_SEL:0] rrf_freenum,
input wire prmiss
);
reg [`RRF_NUM-1:0] finish;
reg [`RRF_NUM-1:0] storebit;
reg [`RRF_NUM-1:0] dstvalid;
reg [`RRF_NUM-1:0] brcond;
reg [`RRF_NUM-1:0] isbranch;
reg [`ADDR_LEN-1:0] inst_pc [0:`RRF_NUM-1];
reg [`ADDR_LEN-1:0] jmpaddr [0:`RRF_NUM-1];
reg [`REG_SEL-1:0] dst [0:`RRF_NUM-1];
reg [`GSH_BHR_LEN-1:0] bhr [0:`RRF_NUM-1];
assign comptr2 = comptr+1;
wire hidp = (comptr > dispatchptr) || (rrf_freenum == 0) ?
1'b1 : 1'b0;
wire com_en1 = ({hidp, dispatchptr} - {1'b0, comptr}) > 0 ? 1'b1 : 1'b0;
wire com_en2 = ({hidp, dispatchptr} - {1'b0, comptr}) > 1 ? 1'b1 : 1'b0;
wire commit1 = com_en1 & finish[comptr];
// wire commit2 = commit1 & com_en2 & finish[comptr2];
wire commit2 =
~(~prmiss & commit1 & isbranch[comptr]) &
~(commit1 & storebit[comptr] & ~prmiss) &
commit1 & com_en2 & finish[comptr2];
assign comnum = {1'b0, commit1} + {1'b0, commit2};
assign stcommit = (commit1 & storebit[comptr] & ~prmiss) |
(commit2 & storebit[comptr2] & ~prmiss);
assign arfwe1 = ~prmiss & commit1 & dstvalid[comptr];
assign arfwe2 = ~prmiss & commit2 & dstvalid[comptr2];
assign dstarf1 = dst[comptr];
assign dstarf2 = dst[comptr2];
assign combranch = (~prmiss & commit1 & isbranch[comptr]) |
(~prmiss & commit2 & isbranch[comptr2]);
assign pc_combranch = (~prmiss & commit1 & isbranch[comptr]) ?
inst_pc[comptr] : inst_pc[comptr2];
assign bhr_combranch = (~prmiss & commit1 & isbranch[comptr]) ?
bhr[comptr] : bhr[comptr2];
assign brcond_combranch = (~prmiss & commit1 & isbranch[comptr]) ?
brcond[comptr] : brcond[comptr2];
assign jmpaddr_combranch = (~prmiss & commit1 & isbranch[comptr]) ?
jmpaddr[comptr] : jmpaddr[comptr2];
always @ (posedge clk) begin
if (reset) begin
comptr <= 0;
end else if (~prmiss) begin
comptr <= comptr + commit1 + commit2;
end
end
always @ (posedge clk) begin
if (reset) begin
finish <= 0;
brcond <= 0;
end else begin
if (dp1)
finish[dp1_addr] <= 1'b0;
if (dp2)
finish[dp2_addr] <= 1'b0;
if (exfin_alu1)
finish[exfin_alu1_addr] <= 1'b1;
if (exfin_alu2)
finish[exfin_alu2_addr] <= 1'b1;
if (exfin_mul)
finish[exfin_mul_addr] <= 1'b1;
if (exfin_ldst)
finish[exfin_ldst_addr] <= 1'b1;
if (exfin_branch) begin
finish[exfin_branch_addr] <= 1'b1;
brcond[exfin_branch_addr] <= exfin_branch_brcond;
jmpaddr[exfin_branch_addr] <= exfin_branch_jmpaddr;
end
end
end // always @ (posedge clk)
always @ (posedge clk) begin
if (dp1) begin
isbranch[dp1_addr] <= isbranch_dp1;
storebit[dp1_addr] <= storebit_dp1;
dstvalid[dp1_addr] <= dstvalid_dp1;
dst[dp1_addr] <= dst_dp1;
bhr[dp1_addr] <= bhr_dp1;
inst_pc[dp1_addr] <= pc_dp1;
end
if (dp2) begin
isbranch[dp2_addr] <= isbranch_dp2;
storebit[dp2_addr] <= storebit_dp2;
dstvalid[dp2_addr] <= dstvalid_dp2;
dst[dp2_addr] <= dst_dp2;
bhr[dp2_addr] <= bhr_dp2;
inst_pc[dp2_addr] <= pc_dp2;
end
end
endmodule // reorderbuf
`default_nettype wire
|
//====================================================================
// bsg_dff_chain.v
// 04/01/2018,
//====================================================================
//
// Pass the input singal to a chainded DFF registers
`include "bsg_defines.v"
module bsg_dff_chain #(
//the width of the input signal
parameter `BSG_INV_PARAM( width_p )
//the stages of the chained DFF register
//can be 0
,parameter num_stages_p = 1
)
(
input clk_i
,input [width_p-1:0] data_i
,output[width_p-1:0] data_o
);
if( num_stages_p == 0) begin:pass_through
assign data_o = data_i;
end:pass_through
else begin:chained
// data_i -- delayed[0]
//
// data_o -- delayed[num_stages_p]
logic [num_stages_p:0][width_p-1:0] data_delayed;
assign data_delayed[0] = data_i ;
assign data_o = data_delayed[num_stages_p] ;
genvar i;
for(i=1; i<= num_stages_p; i++) begin
bsg_dff #( .width_p ( width_p ) )
ch_reg (
.clk_i ( clk_i )
,.data_i ( data_delayed[ i-1 ] )
,.data_o ( data_delayed[ i ] )
);
end
end:chained
endmodule
`BSG_ABSTRACT_MODULE(bsg_dff_chain)
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b; cin >> a >> b; int k = 0; string star = * ; for (int i = 0; i < 12; i++) star = star + star; a = star + a + star; int res = 3000; for (int i = 0; i < a.size(); i++) { int u = 0; for (int j = 0; j < b.size(); j++) if (a[i + j] != b[j]) u++; res = min(res, u); } cout << res << endl; return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_pipe_misc.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_pipe_misc.v //
// Description : Implements the PIPE interface PIPELINE for all per link //
// interface signals //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_pipe_mics.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_pipe_misc #
(
parameter TCQ = 100,
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
) (
input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect
input wire pipe_tx_reset_i , // PIPE Tx Reset
input wire [1:0] pipe_tx_rate_i , // PIPE Tx Rate
input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis
input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin
input wire pipe_tx_swing_i , // PIPE Tx Swing
input wire [5:0] pipe_tx_eqfs_i , // PIPE Tx
input wire [5:0] pipe_tx_eqlf_i , // PIPE Tx
output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect
output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset
output wire [1:0] pipe_tx_rate_o , // Pipelined PIPE Tx Rate
output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis
output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin
output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing
output wire [5:0] pipe_tx_eqfs_o , // PIPE Tx
output wire [5:0] pipe_tx_eqlf_o , // PIPE Tx
input wire pipe_clk , // PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg [1:0] pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_eqfs_q ;
reg pipe_tx_eqlf_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg [1:0] pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
reg pipe_tx_eqfs_qq ;
reg pipe_tx_eqlf_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
assign pipe_tx_eqfs_o = pipe_tx_eqfs_i;
assign pipe_tx_eqlf_o = pipe_tx_eqlf_i;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
always @(posedge pipe_clk) begin
if (!rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 1'b0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 2'b0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 3'b0;
pipe_tx_swing_q <= #TCQ 1'b0;
pipe_tx_eqfs_q <= #TCQ 5'b0;
pipe_tx_eqlf_q <= #TCQ 5'b0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_eqfs_q <= #TCQ pipe_tx_eqfs_i;
pipe_tx_eqlf_q <= #TCQ pipe_tx_eqlf_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
assign pipe_tx_eqfs_o = pipe_tx_eqfs_q;
assign pipe_tx_eqlf_o = pipe_tx_eqlf_q;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
always @(posedge pipe_clk) begin
if (!rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 1'b0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 2'b0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 1'b0;
pipe_tx_swing_q <= #TCQ 1'b0;
pipe_tx_eqfs_q <= #TCQ 5'b0;
pipe_tx_eqlf_q <= #TCQ 5'b0;
pipe_tx_rcvr_det_qq <= #TCQ 1'b0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 2'b0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 1'b0;
pipe_tx_swing_qq <= #TCQ 1'b0;
pipe_tx_eqfs_qq <= #TCQ 5'b0;
pipe_tx_eqlf_qq <= #TCQ 5'b0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_eqfs_q <= #TCQ pipe_tx_eqfs_i;
pipe_tx_eqlf_q <= #TCQ pipe_tx_eqlf_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
pipe_tx_eqfs_qq <= #TCQ pipe_tx_eqfs_q;
pipe_tx_eqlf_qq <= #TCQ pipe_tx_eqlf_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
assign pipe_tx_eqfs_o = pipe_tx_eqfs_qq;
assign pipe_tx_eqlf_o = pipe_tx_eqlf_qq;
end // if (PIPE_PIPELINE_STAGES == 2)
// Default to zero pipeline stages if PIPE_PIPELINE_STAGES != 0,1,2
else begin
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
assign pipe_tx_eqfs_o = pipe_tx_eqfs_i;
assign pipe_tx_eqlf_o = pipe_tx_eqlf_i;
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jorge Sequeira
//
// Create Date: 08/31/2016 03:34:58 PM
// Design Name:
// Module Name: KOA_c
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Recursive Karasuba Parameterized Algorithm
//
// Dependencies:
//
// Revision:
// Revision 0.03 - File Created
// Additional Comments: La primera version de este modulo se puede encontrar en la misma carpeta madre.
// The reason for a second version is the way the numbers with lenght lower than 8 are treated. Here, we change that
// by using an at the start before the case, so a multiplier below l = 7 is never instatiated.
//
// Revision 0.03
//
// 1. Width of KOA multipliers in the even case was fixed from the original version
// 2. Zero padding in the adders was fixed.
//////////////////////////////////////////////////////////////////////////////////
module KOA_c
//#(parameter SW = 24, parameter precision = 0, parameter depth = 4)
#(parameter SW = 54, parameter precision = 1, parameter depth = 3)
(
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
wire [SW/2+1:0] result_A_adder;
wire [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
wire [2*SW-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
assign leftside1 = (SW/2-2) *1'b0; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = (SW/2-3)*1'b0;
localparam half = SW/2;
localparam next_level = depth - 1;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
if (depth == 1) begin : Booth_Mult
assign sgf_result_o = Data_A_i * Data_B_i;
end else begin : K3
case (SW%2)
0:begin : Even_RKOA
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
KOA_c #(.SW(SW/2), .precision(precision), .depth(next_level) /*,.level(level1)*/) left(
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_c #(.SW(SW/2), .precision(precision), .depth(next_level)/*,.level(level1)*/) right(
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.sgf_result_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+1)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder[SW/2:0]),
.Q(Q_result_A_adder[SW/2:0])
);//
RegisterAdd #(.W(SW/2+1)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder[SW/2:0]),
.Q(Q_result_B_adder[SW/2:0])
);//*/
//multiplication for middle
KOA_c #(.SW(SW/2+1), .precision(precision), .depth(next_level)/*,.level(level1)*/) middle (
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.sgf_result_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({leftside1,S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
1:begin : Odd_RKOA
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
KOA_c #(.SW(SW/2), .precision(precision), .depth(next_level)/*,.level(level2)*/) left_high(
.Data_A_i(Data_A_i[SW-1:SW/2+1]),
.Data_B_i(Data_B_i[SW-1:SW/2+1]),
.sgf_result_o(/*result_left_mult*/Q_left)
);
KOA_c #(.SW((SW/2)+1), .precision(precision), .depth(next_level)/*,.level(level2)*/) right_lower(
/// Modificacion: Tamaño de puerto cambia de SW/2+1 a SW/2+2. El compilador lo pide por alguna razon.
.Data_A_i(Data_A_i[SW/2:0]),
.Data_B_i(Data_B_i[SW/2:0]),
.sgf_result_o(/*result_right_mult*/Q_right)
);
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+2)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder),
.Q(Q_result_A_adder)
);//
RegisterAdd #(.W(SW/2+2)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder),
.Q(Q_result_B_adder)
);//*/
//multiplication for middle
KOA_c #(.SW(SW/2+2), .precision(precision), .depth(next_level)/*,.level(level2)*/) middle (
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.sgf_result_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({leftside2,S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final assignation
assign sgf_result_o = Result[2*SW-1:0];
end
endcase
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Friend { string name; int x, y, z; } f[123]; bool Isde(char *a) { if (a[0] <= a[1]) return false; if (a[1] <= a[3]) return false; if (a[3] <= a[4]) return false; if (a[4] <= a[6]) return false; if (a[6] <= a[7]) return false; return true; } bool Isiden(char *a) { if (a[0] != a[1]) return false; if (a[1] != a[3]) return false; if (a[3] != a[4]) return false; if (a[4] != a[6]) return false; if (a[6] != a[7]) return false; return true; } int main() { int n; while (cin >> n) { int mx = 0, my = 0, mz = 0; for (int i = 0; i < n; ++i) { int m; cin >> m >> f[i].name; f[i].x = f[i].y = f[i].z; char str[100]; for (int j = 0; j < m; ++j) { cin >> str; if (Isiden(str)) f[i].x++; else if (Isde(str)) f[i].y++; else f[i].z++; } mx = max(f[i].x, mx); my = max(f[i].y, my); mz = max(f[i].z, mz); } bool flag = false; cout << If you want to call a taxi, you should call: ; for (int i = 0; i < n; ++i) { if (f[i].x == mx) { if (flag) cout << , ; cout << f[i].name; flag = true; } } cout << . << endl; flag = false; cout << If you want to order a pizza, you should call: ; for (int i = 0; i < n; ++i) { if (f[i].y == my) { if (flag) cout << , ; cout << f[i].name; flag = true; } } cout << . << endl; flag = false; cout << If you want to go to a cafe with a wonderful girl, you should call: ; for (int i = 0; i < n; ++i) { if (f[i].z == mz) { if (flag) cout << , ; cout << f[i].name; flag = true; } } cout << . << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int nCases; cin >> nCases; for (int i = 0; i < nCases; i++) { long long nCandy = 0; cin >> nCandy; if (nCandy == 1 || nCandy == 2) { cout << 0 << endl; } else if (nCandy % 2 == 0) { cout << (nCandy / 2) - 1 << endl; } else { cout << nCandy / 2 << endl; } } return 0; } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import Morphisms BinInt ZDivEucl.
Local Open Scope Z_scope.
(** * Definitions of division for binary integers, Euclid convention. *)
(** In this convention, the remainder is always positive.
For other conventions, see [Z.div] and [Z.quot] in file [BinIntDef].
To avoid collision with the other divisions, we place this one
under a module.
*)
Module ZEuclid.
Definition modulo a b := Z.modulo a (Z.abs b).
Definition div a b := (Z.sgn b) * (Z.div a (Z.abs b)).
Instance mod_wd : Proper (eq==>eq==>eq) modulo.
Proof. congruence. Qed.
Instance div_wd : Proper (eq==>eq==>eq) div.
Proof. congruence. Qed.
Theorem div_mod a b : b<>0 -> a = b*(div a b) + modulo a b.
Proof.
intros Hb. unfold div, modulo.
rewrite Z.mul_assoc. rewrite Z.sgn_abs. apply Z.div_mod.
now destruct b.
Qed.
Lemma mod_always_pos a b : b<>0 -> 0 <= modulo a b < Z.abs b.
Proof.
intros Hb. unfold modulo.
apply Z.mod_pos_bound.
destruct b; compute; trivial. now destruct Hb.
Qed.
Lemma mod_bound_pos a b : 0<=a -> 0<b -> 0 <= modulo a b < b.
Proof.
intros _ Hb. rewrite <- (Z.abs_eq b) at 3 by Z.order.
apply mod_always_pos. Z.order.
Qed.
Include ZEuclidProp Z Z Z.
End ZEuclid.
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n & 1) { cout << (n + 1) / 2; } else { cout << n / 2 + 1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> T gcd(T a, T b) { if (!b) return a; while (b ^= a ^= b ^= a %= b) ; return a; } template <class T> T max(const T& t1, const T& t2, const T& t3) { return max(max(t1, t2), t3); } template <class T> T max(const T& t1, const T& t2, const T& t3, const T& t4) { return max(max(t1, t2), max(t3, t4)); } long long fpow(long long x, long long y, long long mod = 0x7fffffffffffffffll) { long long ret = 1; while (y) { if (y & 1) ret *= x, ret %= mod; x *= x; x %= mod; y >>= 1; } return ret; } void ex_gcd(long long a, long long b, long long& x, long long& y) { if (b == 0) { x = a; y = 0; return; } ex_gcd(b, a % b, y, x); y = y - a / b * x; } long long modrev(long long x, long long mod) { long long x1, x2; ex_gcd(x, mod, x1, x2); return x1; } unsigned long long T_rand() { return (unsigned long long)(rand()); } unsigned long long Rand() { return (T_rand() << 48) | (T_rand() << 32) | (T_rand() << 16) | T_rand(); } template <class T> bool PRE_INPUT_INTENGER(T& ret) { ; ret = 0; char c = getchar(); if (c == -1) return 0; bool f = 0; while ((c < 0 || c > 9 ) && (c != -1) && (c != - )) c = getchar(); if (c == - ) { f = 1; c = getchar(); } while (c >= 0 && c <= 9 ) ret *= 10, ret += c - 0 , c = getchar(); if (f) ret = -ret; if (c == -1) return 0; return 1; } bool input(int& ret) { return PRE_INPUT_INTENGER(ret); } bool input(long long& ret) { return PRE_INPUT_INTENGER(ret); } bool input(unsigned long long& ret) { return PRE_INPUT_INTENGER(ret); } bool input(unsigned int& ret) { return PRE_INPUT_INTENGER(ret); } template <class T> bool PRE_INPUT_DOUBLE(T& ret) { ; ret = 0; char c = getchar(); if (c == -1) return 0; bool f = 0; while ((c < 0 || c > 9 ) && (c != -1) && (c != . ) && (c != - )) c = getchar(); bool isright = 0; if (c == - ) { f = 1; c = getchar(); } T t = 1; while ((c >= 0 && c <= 9 ) || (c == . )) { if (c == . ) isright = 1; else { ret *= 10, ret += c - 0 ; if (isright) t *= 10; } c = getchar(); } ret /= t; if (f) ret = -ret; if (c == -1) return 0; return 1; } bool input(double& ret) { return PRE_INPUT_DOUBLE(ret); } bool input(float& ret) { return PRE_INPUT_DOUBLE(ret); } bool IS_SPECIAL_CHAR(const char& ret) { return (ret == || ret == n || ret == t || ret == r || ret == v ); } bool input(char& ret) { ; ret = getchar(); if (ret == -1) return 0; while (IS_SPECIAL_CHAR(ret)) ret = getchar(); return ~ret; } bool input(char* ret) { ; char c; if (!input(c)) return 0; *ret++ = c; while (!IS_SPECIAL_CHAR(*(ret - 1))) *ret++ = getchar(); *(ret - 1) = 0; return 1; } template <class T1, class T2> bool input(T1& t1, T2& t2) { return input(t1) && input(t2); } template <class T1, class T2, class T3> bool input(T1& t1, T2& t2, T3& t3) { return input(t1) && input(t2) && input(t3); } template <class T1, class T2, class T3, class T4> bool input(T1& t1, T2& t2, T3& t3, T4& t4) { return input(t1) && input(t2) && input(t3) && input(t4); } template <class T1, class T2, class T3, class T4, class T5> bool input(T1& t1, T2& t2, T3& t3, T4& t4, T5& t5) { return input(t1) && input(t2) && input(t3) && input(t4) && input(t5); } template <class T> void input(T* a, int n) { for (int i = 0; i <= n - 1; i++) input(a[i]); } template <class T> void PRE_OUTPUT_INTENGER(const T& t) { ; if (!t) { putchar( 0 ); return; } T key = t; int tt[25]; if (key < 0) { putchar( - ); key = -key; } int cnt = 0; while (key) tt[cnt++] = key % 10, key /= 10; while (cnt) putchar(tt[--cnt] + 0 ); ; } void output(const int& t) { PRE_OUTPUT_INTENGER(t); } void output(const long long& t) { PRE_OUTPUT_INTENGER(t); } void output(const unsigned long long& t) { PRE_OUTPUT_INTENGER(t); } void output(const unsigned int& t) { PRE_OUTPUT_INTENGER(t); } template <class T> void PRE_OUTPUT_DOUBLE(const T& key) { ; printf( %.*f , 6, key); ; } void output(const double& t) { PRE_OUTPUT_DOUBLE(t); } void output(const float& t) { PRE_OUTPUT_DOUBLE(t); } void output(const char* ch) { ; int cnt = 0; while (ch[cnt]) putchar(ch[cnt++]); ; } void output(const char& c) { ; putchar(c); ; } void output(const string& s) { output(s.c_str()); } template <class T1, class T2> void output(const T1& t1, const T2& t2) { output(t1); output(t2); } template <class T1, class T2, class T3> void output(const T1& t1, const T2& t2, const T3& t3) { output(t1); output(t2); output(t3); } template <class T1, class T2, class T3, class T4> void output(const T1& t1, const T2& t2, const T3& t3, const T4& t4) { output(t1); output(t2); output(t3); output(t4); } template <class T1, class T2, class T3, class T4, class T5> void output(const T1& t1, const T2& t2, const T3& t3, const T4& t4, const T5& t5) { output(t1); output(t2); output(t3); output(t4); output(t5); } template <class T1, class T2, class T3, class T4, class T5, class T6> void output(const T1& t1, const T2& t2, const T3& t3, const T4& t4, const T5& t5, const T6& t6) { output(t1); output(t2); output(t3); output(t4); output(t5); output(t6); } template <class T1, class T2, class T3, class T4, class T5, class T6, class T7> void output(const T1& t1, const T2& t2, const T3& t3, const T4& t4, const T5& t5, const T6& t6, const T7& t7) { output(t1); output(t2); output(t3); output(t4); output(t5); output(t6); output(t7); } template <class T> void printal(T* a, int n) { for (int i = 0; i < n - 1; i++) output(a[i], ); output(a[n - 1], n ); } template <class T> void printel(T* a, int n) { for (int i = 0; i < n; i++) output(a[i], n ); } template <class T> void inputal(T* a, int n) { for (int i = 0; i <= n - 1; i++) input(a[i]); } const int maxn = 1e5 + 10; struct Node { string s; int cnt; char last; bool operator<(const Node& t) const { if (cnt < t.cnt) return true; if (last < t.last) return true; return false; } bool operator==(const Node& t) const { return cnt == t.cnt && last == t.last; } }; Node node[maxn]; const char* vowel = aeiou ; bool is_vowel(char c) { switch (c) { case a : case e : case i : case o : case u : return true; default: return false; } } map<int, map<char, vector<int>>> mp; int ans[4 * maxn]; int main() { int n; input(n); for (int i = 0; i <= n - 1; i++) { cin >> node[i].s; node[i].cnt = 0; for (const char& c : node[i].s) { if (is_vowel(c)) { ++node[i].cnt; node[i].last = c; } } if (mp.count(node[i].cnt) == 0) { mp[node[i].cnt] = map<char, vector<int>>(); } if (mp[node[i].cnt].count(node[i].last) == 0) { mp[node[i].cnt][node[i].last] = vector<int>(); } mp[node[i].cnt][node[i].last].push_back(i); } vector<pair<int, int>> has_same; map<int, vector<int>> single; for (const pair<int, map<char, vector<int>>>& t : mp) { for (const pair<char, vector<int>>& t2 : t.second) { for (int i = 0; i < t2.second.size(); i += 2) { if (i == t2.second.size() - 1) { if (single.count(t.first) == 0) { single[t.first] = vector<int>(); } single[t.first].push_back(t2.second[i]); } else { has_same.push_back(make_pair(t2.second[i], t2.second[i + 1])); } } } } int cnt = 0; int last_double_idx = 0; for (const pair<int, vector<int>>& t : single) { int last_single_idx = 0; if (last_double_idx == has_same.size()) break; while (t.second.size() - last_single_idx > 1) { if (last_double_idx == has_same.size()) break; pair<int, int>& cur = has_same[last_double_idx++]; ans[cnt++] = t.second[last_single_idx++]; ans[cnt++] = cur.first; ans[cnt++] = t.second[last_single_idx++]; ans[cnt++] = cur.second; } } while (last_double_idx + 1 < has_same.size()) { ans[cnt++] = has_same[last_double_idx].first; ans[cnt++] = has_same[last_double_idx + 1].first; ans[cnt++] = has_same[last_double_idx].second; ans[cnt++] = has_same[last_double_idx + 1].second; last_double_idx += 2; } output(cnt / 4); putchar( n ); for (int i = 0; i < cnt; i += 2) { output(node[ans[i]].s, , node[ans[i + 1]].s); putchar( n ); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NOR3_BEHAVIORAL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , C, A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; string func(pair<int, int> a, pair<int, int> b) { return to_string(a.first) + + to_string(a.second) + + to_string(b.first) + + to_string(b.second); } int nSmallFactor(int n, vector<int>& primes) { for (int prime : primes) { if (n % prime == 0) { return prime; } } return -1; } void DFS(vector<int>& ve, vector<int>& visited, int n, int start) { int ans = 0; for (int i = start + start; i <= n; i += start) { if (visited[i] == -1) { DFS(ve, visited, n, i); } if (ve[i] > ve[start]) { ans = max(ans, visited[i]); } } visited[start] = ans + 1; } long long sum(long long a) { if (a % 2 == 0) { return (a / 2) * (a + 1); } return ((a + 1) / 2) * a; } long long sum(long long a, long long b) { return sum(b) - sum(a - 1); } vector<int> getPrimes(int n) { vector<int> primes; primes.push_back(2); bool isPrime; for (int i = 3; i * i <= n; i++) { isPrime = true; for (int p = 0; p < primes.size() && primes[p] * primes[p] <= i; p++) { if (i % primes[p] == 0) { isPrime = false; break; } } if (isPrime) { primes.push_back(i); } } return primes; } int findMaxPrime(vector<int> primes, int n, int k) { int ans = INT_MAX; bool findAns = true; int ncpy = n; for (int i = 0; primes[i] <= k && primes[i] * primes[i] <= n; i++) { if (findAns && n % primes[i] == 0) { ans = primes[i]; } while (n % primes[i] == 0) { n /= primes[i]; } } if (n <= k) { ans = min(ans, ncpy / n); } ans = min(ans, ncpy); return ans; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int ttt = 1; cin >> ttt; string s; int temp; int n, k; int p, q, a, b, c, d; bool ans; vector<int> primes = getPrimes(1000000005); int row, col; while (ttt--) { cin >> n; bool a[n][n]; string s; for (int i = (int)0; i < (int)n; i++) { cin >> s; for (int j = (int)0; j < (int)n; j++) { if (s[j] == 1 ) { a[i][j] = true; } else { a[i][j] = false; } } } bool possible = true; for (int i = 1; possible && i < n; i++) { row = n - i - 1; p = row; for (p; p >= 0; p--) { if (a[row][p]) { if (!a[row][p + 1] && !a[row + 1][p]) { possible = false; break; } } } col = row; p = col; for (p; p >= 0; p--) { if (a[p][col]) { if (!a[p][col + 1] && !a[p + 1][col]) { possible = false; break; } } } } if (possible) { cout << YES n ; } else { cout << NO n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { char a[3][3]; for (int i = 0; i < 3; i++) for (int j = 0; j < 3; j++) cin >> a[i][j]; for (int i = 0; i < 3; i++) for (int j = 0; j < 3; j++) if (a[i][j] != a[2 - i][2 - j]) { cout << NO ; return 0; } cout << YES ; return 0; } |
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
module intr_capturer #(
parameter NUM_INTR = 32
// active high level interrupt is expected for the input of this capturer module
)(
input clk,
input rst_n,
input [NUM_INTR-1:0] interrupt_in,
//input [31:0] wrdata,
input addr,
input read,
output [31:0] rddata
);
reg [NUM_INTR-1:0] interrupt_reg;
reg [31:0] readdata_with_waitstate;
wire [31:0] act_readdata;
wire [31:0] readdata_lower_intr;
wire [31:0] readdata_higher_intr;
wire access_lower_32;
wire access_higher_32;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) interrupt_reg <= 'b0;
else interrupt_reg <= interrupt_in;
end
generate
if (NUM_INTR>32) begin : two_intr_reg_needed
assign access_higher_32 = read & (addr == 1);
assign readdata_lower_intr = interrupt_reg[31:0] & {(32){access_lower_32}};
assign readdata_higher_intr = interrupt_reg[NUM_INTR-1:32] & {(NUM_INTR-32){access_higher_32}};
end
else begin : only_1_reg
assign readdata_lower_intr = interrupt_reg & {(NUM_INTR){access_lower_32}};
assign readdata_higher_intr = {32{1'b0}};
end
endgenerate
assign access_lower_32 = read & (addr == 0);
assign act_readdata = readdata_lower_intr | readdata_higher_intr;
assign rddata = readdata_with_waitstate;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) readdata_with_waitstate <= 32'b0;
else readdata_with_waitstate <= act_readdata;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> g[1000010]; int n, k; bool r[1000010]; int s[1000010]; int m[1000010]; int main() { scanf( %d %d , &n, &k); for (int i = 0; i < k; i++) { int x, y; scanf( %d %d , &x, &y); g[x].push_back(y); } int v = 0; for (int i = 1; i <= n; i++) { if (r[i]) continue; s[v++] = i; r[i] = true; for (int j = 0; j < (int)g[i].size(); j++) r[g[i][j]] = true; } int sz = 0; for (int i = 1; i <= n; i++) r[i] = false; for (int i = v - 1; i >= 0; i--) { if (!r[s[i]]) { m[sz++] = s[i]; for (int j = 0; j < (int)g[s[i]].size(); j++) r[g[s[i]][j]] = true; } } printf( %d n , sz); for (int i = 0; i < sz; i++) printf( %d , m[i]); printf( n ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BAI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O21BAI_PP_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BAI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, x, y, z, ans = 0; cin >> n >> x >> y >> z; for (long long i = 0; i <= x / 2; i++) { for (long long j = 0; j <= y; j++) { if ((n - (i + j)) % 2 == 0 && (n - (i + j)) / 2 <= z && (n - (i + j)) / 2 >= 0) ans++; } } cout << ans; } int main() { int t = 1; while (t--) { solve(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
/**
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer, vpb/vnb
* taps, double-row-height cell.
*
* Verilog wrapper for lpflow_lsbuf_lh_isowell_tap with
* size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB
);
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A),
.LOWLVPWR(LOWLVPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22OI_SYMBOL_V
`define SKY130_FD_SC_HDLL__A22OI_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a22oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22OI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINVLP_2_V
`define SKY130_FD_SC_LP__CLKINVLP_2_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog wrapper for clkinvlp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinvlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinvlp_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinvlp_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINVLP_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int a[n][m], b[n][m]; vector<int> aa[1000]; vector<int> bb[1000]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; aa[i + j].push_back(a[i][j]); } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> b[i][j]; bb[i + j].push_back(b[i][j]); } } int flag = 1; for (int i = 0; i < 1000; i++) { sort(aa[i].begin(), aa[i].end()); sort(bb[i].begin(), bb[i].end()); if (aa[i] != bb[i]) { flag = -1; break; } } if (flag == 1) cout << YES << endl; else cout << NO << endl; } |
#include <bits/stdc++.h> using namespace std; int n, m, k; bool debug = false; int dp[1005][1005]; char a[1005], b[1005]; int main() { scanf( %s%s , a + 1, b + 1); int n = strlen(a + 1); int m = strlen(b + 1); for (int i = 1; i <= n; i++) dp[i][0] = i; for (int i = 1; i <= m; i++) dp[0][i] = i; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { dp[i][j] = min(min(dp[i][j - 1], dp[i - 1][j]) + 1, dp[i - 1][j - 1] + (a[i] != b[j])); } } printf( %d n , dp[n][m]); while (n != 0 || m != 0) { if (m != 0 && dp[n][m] == dp[n][m - 1] + 1) { printf( INSERT %d %c n , n + 1, b[m]); m--; } else if (n != 0 && dp[n][m] == dp[n - 1][m] + 1) { printf( DELETE %d n , n); n--; } else if (a[n--] != b[m--]) { printf( REPLACE %d %c n , n + 1, b[m + 1]); } } return 0; } |
/* verilator lint_off WIDTH */
module FIFO
#(
parameter data_width=32,
parameter size=32,
parameter device_id=1
)
(
input [data_width-1:0] data_in /*verilator public*/,
output [data_width-1:0] data_out /*verilator public*/,
input clk /*verilator public*/,
input next /*verilator public*/,
input insert /*verilator public*/,
input clear /*verilator public*/,
output full /*verilator public*/,
output empty /*verilator public*/
);
reg [data_width-1:0] mem[size];
reg [9:0] words_inside=0;
assign data_out=mem[0];
assign full=words_inside==size;
assign empty=words_inside==0;
always @(posedge clk) begin
if (!(insert&&next)) begin
if (clear)
words_inside<=0;
else if (insert && ~full)
words_inside<=words_inside+1;
else if (next && ~empty)
words_inside<=words_inside-1;
end
end
generate
genvar pos;
for (pos=0; pos<size; pos=pos+1) begin: registers
always @(posedge clk) begin
mem[pos]<=
insert^next?
insert && words_inside==pos?
data_in
:
next?
pos+1!=size?
mem[pos+1]
:
0
:
mem[pos]
:
insert&&next?
// -1 : location of
// the last word
pos<words_inside-1?
mem[pos+1]
:
data_in
:
mem[pos];
// I'm so sorry... This evil language
// made me do it.
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; ifstream in; ofstream out; const long long kk = 1000; const long long ml = kk * kk; const long long mod = ml * kk + 7; const long long inf = ml * ml * ml + 7; long long n, i, j; vector<long long> m; vector<long long> bef[10 * kk]; bool viv = false; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (i = 0; i < n - 1; i++) { long long a, b; cin >> a >> b; a--; b--; if (a != n - 1 && b != n - 1 || (a == b)) { cout << NO ; return 0; } if (a > b) swap(a, b); m.push_back(a); } sort(m.begin(), m.end()); vector<long long> kol(n, 0); for (auto i : m) kol[i]++; for (i = 0; i < n; i++) if (kol[i] > i + 1) { cout << NO ; return 0; } vector<long long> st; vector<pair<long long, long long> > re; for (i = 0; i < n - 1; i++) { if (kol[i] == 0) st.push_back(i); if (kol[i] - 1 > st.size()) { cout << NO ; return 0; } if (kol[i] > 0) { long long j = kol[i] - 1; bef[i].push_back(n - 1); while (j) { bef[i].push_back(st.back()); st.pop_back(); j--; } } } for (i = 0; i < n; i++) if (!bef[i].empty()) { for (j = 1; j < bef[i].size(); j++) re.push_back({bef[i][j - 1], bef[i][j]}); re.push_back({i, bef[i].back()}); } cout << YES << endl; for (auto i : re) cout << i.second + 1 << << i.first + 1 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e3 + 7; const int MOD = 1e9 + 7; const int D = 4e3 + 7; int n, m, A[MAXN], cnt, L, R; vector<int> G[MAXN]; void add(int &x, int y) { x += y; if (x >= MOD) x -= MOD; } bool vis[MAXN]; int dfs(int u) { vis[u] = true; for (int v : G[u]) if (!vis[v]) return dfs(v) + 1; return 1; } int f[MAXN][D << 1], g[MAXN][D << 1]; int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= m; i++) { int u, v; scanf( %d %d , &u, &v); G[u].push_back(v); G[v].push_back(u); } vis[1] = true; for (int u : G[1]) if (!vis[u]) A[++cnt] = dfs(u) + 1; L = D - m, R = D + m; f[0][D] = g[cnt + 1][D] = 1; for (int i = 1; i <= cnt; i++) for (int j = L; j <= R; j++) { f[i][j] = f[i - 1][j]; if (j + A[i] <= R) add(f[i][j], f[i - 1][j + A[i]]); if (j - A[i] >= L) add(f[i][j], f[i - 1][j - A[i]]); } for (int i = cnt; ~i; i--) for (int j = L; j <= R; j++) { g[i][j] = g[i + 1][j]; if (j + A[i] <= R) add(g[i][j], g[i + 1][j + A[i]]); if (j - A[i] >= L) add(g[i][j], g[i + 1][j - A[i]]); } int ret = 0; for (int i = 1; i <= cnt; i++) { for (int j = -(A[i] - 2); j <= A[i] - 2; j++) { for (int k = L; k <= R; k++) { int d = j - (k - D) + D; if (L <= d and d <= R) add(ret, 1ll * f[i - 1][k] * g[i + 1][d] % MOD); } } } memset(f, 0, sizeof(f)); memset(g, 0, sizeof(g)); f[0][D] = g[cnt + 1][D] = 1; for (int i = 1; i <= cnt; i++) for (int j = L; j <= R; j++) { if (j + A[i] <= R) add(f[i][j], f[i - 1][j + A[i]]); if (j - A[i] >= L) add(f[i][j], f[i - 1][j - A[i]]); } for (int i = cnt; ~i; i--) for (int j = L; j <= R; j++) { if (j + A[i] <= R) add(g[i][j], g[i + 1][j + A[i]]); if (j - A[i] >= L) add(g[i][j], g[i + 1][j - A[i]]); } for (int i = 1; i <= cnt; i++) { int j = A[i] - 1; for (int k = L; k <= R; k++) { int d = j - (k - D) + D; if (L <= d and d <= R) add(ret, 1ll * f[i - 1][k] * g[i + 1][d] % MOD); } j = -j; for (int k = L; k <= R; k++) { int d = j - (k - D) + D; if (L <= d and d <= R) add(ret, 1ll * f[i - 1][k] * g[i + 1][d] % MOD); } } add(ret, ret); add(ret, f[cnt][D]); cout << ret << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; string str; int main() { cin >> str; bool chk = false; for (int i = 0; i <= str.length(); i++) { for (char ch = a ; ch <= z ; ch++) { string temp1 = str.substr(0, i) + ch + str.substr(i); string temp2 = temp1; reverse(temp2.begin(), temp2.end()); if (temp1.compare(temp2) == 0) { cout << temp1 << endl; chk = true; break; } } if (chk == true) { break; } } if (chk == false) { cout << NA n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, lst[3], mx[2]; long long ans, pos[300005]; char color; inline char get() { char in = getchar(); while (in != R && in != G && in != B ) { in = getchar(); } return in; } inline void did(int opt, int nowpos) { if (lst[opt] != 0) { ans += pos[nowpos] - pos[lst[opt]]; mx[opt] = (mx[opt] > pos[nowpos] - pos[lst[opt]] ? mx[opt] : pos[nowpos] - pos[lst[opt]]); } lst[opt] = nowpos; } inline void did2(int nowpos) { if (lst[2] != 0) { ans += (0 < pos[nowpos] - pos[lst[2]] - mx[0] - mx[1] ? 0 : pos[nowpos] - pos[lst[2]] - mx[0] - mx[1]); } lst[2] = nowpos; mx[0] = 0; mx[1] = 0; } int main() { scanf( %d , &n); for (register int i = 1; i <= n; i++) { scanf( %d , &pos[i]); color = get(); switch (color) { case R : did(0, i); break; case B : did(1, i); break; case G : did(0, i); did(1, i); did2(i); break; } } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1e18; const long double eps = 1e-6; const long long maxn = 1e6 + 100; vector<long long> g[maxn]; long long szc1[maxn], szc2[maxn]; vector<long long> used; void dfsc(long long v, long long col) { used[v] = 1; szc1[col]++; szc2[col]++; for (long long u : g[v]) { if (used[u]) continue; dfsc(u, col); } } bitset<maxn> dp; signed main() { ios_base::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr); long long n, k; cin >> n >> k; vector<long long> p(n); for (long long i = 0; i < n; ++i) { cin >> p[i], --p[i]; g[i].push_back(p[i]); g[p[i]].push_back(i); } long long idxc = 0; used.assign(n, 0); for (long long i = 0; i < n; ++i) { if (!used[i]) { dfsc(i, idxc); ++idxc; } } long long ansl = 0, ansr = 0; long long kl = k, kr = k; for (long long i = 0; i < idxc; ++i) { if (szc1[i] >= 2 && kr) { --kr; ansr += 2; } } long long add = 0; for (long long i = 0; i < idxc && kr; ++i) { long long t = szc1[i]; long long x = t / 2 - 1; if (t >= 3 && t % 2) { ++add; } x = min(x, kr); if (x >= 1) { ansr += 2 * x; kr -= x; } } add = min(add, kr); ansr += add; kr -= add; vector<pair<long long, long long>> gg; vector<long long> cnt(n + 1, 0), us(n + 1, 0); for (long long i = 0; i < idxc; ++i) { cnt[szc2[i]]++; } for (long long i = 0; i < idxc; ++i) { if (us[szc2[i]]) continue; gg.push_back({szc2[i], cnt[szc2[i]]}); us[szc2[i]] = 1; } dp[0] = 1; for (long long i = 0; i < (long long)gg.size(); ++i) { for (long long t = 1; t <= gg[i].second; t *= 2) { long long x = t * gg[i].first; auto bb = dp; bb <<= x; dp |= bb; gg[i].second -= t; } long long x = gg[i].second * gg[i].first; auto bb = dp; bb <<= x; dp |= bb; } if (dp[kl]) ansl = kl; else ansl = kl + 1; cout << ansl << << ansr; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR4_PP_SYMBOL_V
/**
* or4: 4-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1e9; const long long base = 1e9 + 7; const int N = 5e3 + 2; int n, m, k; int a[N][N]; pair<int, int> h[N], c[N]; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m >> k; long long x, y, z; for (int i = (1), b_ = (k); i <= b_; ++i) { cin >> x >> y >> z; if (x == 1) { h[y].first = z; h[y].second = i; } else { c[y].first = z; c[y].second = i; } } for (int i = (1), b_ = (n); i <= b_; ++i) { for (int j = (1), b_ = (m); j <= b_; ++j) { if (h[i].second == 0 && c[j].second == 0) cout << 0 << ; else if (h[i].second > c[j].second) cout << h[i].first << ; else cout << c[j].first << ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int f = 1, mod; void calc(int sum, int t) { for (int i = 1; i <= sum; i++) { if (i % 2 or !t) f = (f * i) % mod; else f = (f * (i / 2)) % mod, t--; } } int main() { int n, p, count = 0, a[200001] = {0}; cin >> n; vector<pair<int, int> > v; for (int i = 1; i <= n; i++) cin >> p, v.push_back(make_pair(p, i)); for (int i = 1; i <= n; i++) cin >> p, v.push_back(make_pair(p, i)); sort(v.begin(), v.end()); int i = 0; cin >> mod; while (i < v.size()) { int t = 0, sum = 0; count++; a[v[i].second] = count; i++; while (i < 2 * n and v[i].first == v[i - 1].first) { if (a[v[i].second] == count) t++; a[v[i].second] = count; sum++; i++; } calc(sum + 1, t); } cout << f; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; int n, k; vector<int> g[N]; int fa[N]; int dep[N]; bool vis[N]; int anc[N][35]; void dfs(int u, int f) { fa[u] = f; anc[u][0] = fa[u]; for (int i = 0; i < g[u].size(); i++) { int v = g[u][i]; if (v != f) { dep[v] = dep[u] + 1; dfs(v, u); } } } void rdfs(int u, int f) { vis[u] = 1; if (u == f) return; rdfs(fa[u], f); } void preprocess() { for (int j = 1; (1 << j) < n; j++) { for (int i = 0; i < n; i++) { if (anc[i][j - 1] != -1) { int a = anc[i][j - 1]; anc[i][j] = anc[a][j - 1]; } } } } int main() { memset(anc, -1, sizeof(anc)); scanf( %d%d , &n, &k); k = n - k; for (int i = 1; i < n; i++) { int x, y; scanf( %d%d , &x, &y); x--, y--; g[x].push_back(y); g[y].push_back(x); } dfs(n - 1, -1); preprocess(); int num = 1; vis[n - 1] = 1; for (int i = n - 2; i >= 0; i--) { if (vis[i]) continue; int t = i; for (int j = 20; j >= 0; j--) { if (anc[t][j] == -1) continue; else { if (!vis[anc[t][j]]) { t = anc[t][j]; } } } if (dep[i] - dep[t] + 1 + num <= k) { num += dep[i] - dep[t] + 1; rdfs(i, t); } } for (int i = 0; i < n; i++) { if (!vis[i]) printf( %d , i + 1); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 19:34:38
// Design Name:
// Module Name: gated_SR_latch_dataflow_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module gated_SR_latch_dataflow_tb(
);
reg R, S, Enable;
wire Q, Qbar;
gated_SR_latch_dataflow DUT (.R(R), .S(S), .Enable(Enable), .Q(Q), .Qbar(Qbar));
initial begin
#120 $finish;
end
initial begin
R = 0; S = 0; Enable = 0;
#10 S = 1;
#10 Enable = 1;
#10 S = 0;
#10 R = 1;
#10 Enable = 0;
#10 R = 0; S = 1;
#10 R = 1; S = 0;
#10 R = 0; S = 1;
#10 Enable = 1;
#10 R = 1; S = 0;
#20;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:08:40 11/19/2015
// Design Name:
// Module Name: EX_MEM
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module EX_MEM(
input clock,
input reset,
input debugEnable,
input debugReset,
input[4:0] writeRegister,
input[31:0] writeData,
input[31:0] aluOut,
input regWrite,
input memToReg,
input [3:0]memWrite,
input [1:0] memReadWidth,
input eop,
output reg[4:0] writeRegisterOut,
output reg[31:0] writeDataOut,
output reg[31:0] aluOutOut,
output reg regWriteOut,
output reg memToRegOut,
output reg [3:0]memWriteOut,
output reg [1:0] memReadWidthOut,
output reg eopOut
);
always @(negedge clock,posedge reset)begin
if(reset)begin
writeRegisterOut<=0;
writeDataOut<=0;
aluOutOut<=0;
regWriteOut<=0;
memToRegOut<=0;
memWriteOut<=0;
memReadWidthOut<=0;
eopOut<=0;
end
else if(debugReset)begin
writeRegisterOut<=0;
writeDataOut<=0;
aluOutOut<=0;
regWriteOut<=0;
memToRegOut<=0;
memWriteOut<=0;
memReadWidthOut<=0;
eopOut<=0;
end
else if(debugEnable) begin
writeRegisterOut<=writeRegister;
writeDataOut<=writeData;
aluOutOut<=aluOut;
regWriteOut<=regWrite;
memToRegOut<=memToReg;
memWriteOut<=memWrite;
memReadWidthOut<=memReadWidth;
eopOut<=eop;
end
end
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : ram_2p.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Dual Port Ram Model
//
// $Id$
//-------------------------------------------------------------------
module ram_lcu_column_32x64 (
clka ,
cena_i ,
oena_i ,
wena_i ,
addra_i ,
dataa_o ,
dataa_i ,
clkb ,
cenb_i ,
oenb_i ,
wenb_i ,
addrb_i ,
datab_o ,
datab_i
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width=32;
parameter Addr_Width=6;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
// A port
input clka; // clock input
input cena_i; // chip enable, low active
input oena_i; // data output enable, low active
input wena_i; // write enable, low active
input [Addr_Width-1:0] addra_i; // address input
input [Word_Width-1:0] dataa_i; // data input
output [Word_Width-1:0] dataa_o; // data output
// B Port
input clkb; // clock input
input cenb_i; // chip enable, low active
input oenb_i; // data output enable, low active
input wenb_i; // write enable, low active
input [Addr_Width-1:0] addrb_i; // address input
input [Word_Width-1:0] datab_i; // data input
output [Word_Width-1:0] datab_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] dataa_r;
reg [Word_Width-1:0] datab_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// -- A Port --//
always @(posedge clka) begin
if(!cena_i && !wena_i)
mem_array[addra_i] <= dataa_i;
end
always @(posedge clka) begin
if (!cena_i && wena_i)
dataa_r <= mem_array[addra_i];
else
dataa_r <= 'bx;
end
assign dataa_o = oena_i ? 'bz : dataa_r;
// -- B Port --//
always @(posedge clkb) begin
if(!cenb_i && !wenb_i)
mem_array[addrb_i] <= datab_i;
end
always @(posedge clkb) begin
if (!cenb_i && wenb_i)
datab_r <= mem_array[addrb_i];
else
datab_r <= 'bx;
end
assign datab_o = oenb_i ? 'bz : datab_r;
endmodule |
#include <bits/stdc++.h> using namespace std; int N, M, M2, B; const int MAXN = 100015; const int MAXM = 20; const int MAXM2 = (1 << 20); char S[MAXN]; int bitc[MAXM2]; int bitl[MAXM2]; int dp[MAXM2]; int cnt[MAXM][MAXM]; int mcnt[MAXM2][MAXM]; int last; int main() { cin >> N >> M >> S; M2 = (1 << M); B = M2 - 1; for (int i = 0; i < M; ++i) for (int j = 0; j < M; ++j) cnt[i][j] = 0; bitc[0] = 0; bitl[0] = 0; dp[0] = 0; for (int j = 0; j < M; ++j) mcnt[0][j] = 0; for (int i = 1; i < M2; ++i) { int b = i & (i - 1); bitc[i] = bitc[b] + 1; for (int j = 0; j < M; ++j) if ((1 << j) & i) { bitl[i] = j; break; } for (int j = 0; j < M; ++j) mcnt[i][j] = 0; dp[i] = 1e9; } for (int i = 0; i < N - 1; ++i) { if (S[i] == S[i + 1]) continue; ++cnt[S[i] - a ][S[i + 1] - a ]; ++cnt[S[i + 1] - a ][S[i] - a ]; } for (int i = 1; i < M2; ++i) for (int j = 0; j < M; ++j) mcnt[i][j] = mcnt[i & (i - 1)][j] + cnt[bitl[i]][j]; for (int i = 0; i < M2; ++i) for (int j = 0; j < M; ++j) { if (((1 << j) & i) == 0) dp[i | (1 << j)] = min(dp[i | (1 << j)], dp[i] + bitc[i] * (mcnt[i][j] - mcnt[B ^ i][j])); } cout << dp[B] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; vector<long long> arr(n); for (long long i = 0; i < n; ++i) { cin >> arr[i]; } sort(arr.begin(), arr.end()); long long grp = 0; long long ptr = 0; unordered_map<long long, long long> mp; long long last = 0; for (long long i = 0; i < n; ++i) { if (arr[i] == 1) { grp++; continue; } else if (ptr > 0) { ptr--; if (ptr == 0 && arr[i] == arr[i - 1]) { grp++; } else { ptr = arr[i] - (i - last + 1); } } else { ptr = arr[i] - 1; last = i; } } cout << grp << n ; } int32_t main() { long long t; cin >> t; while (t--) { solve(); } } |
module bcd_to_7seg_dec (bcd_in, segments_out, invert);
output reg [6:0] segments_out;
input [3:0] bcd_in;
input invert;
// 7-segment encoding
// 0
// ---
// 5 | | 1
// --- <--6
// 4 | | 2
// ---
// 3
reg [6:0] seg_reg;
always @*
case (bcd_in)
// this is the decoding for common anode displays:
4'b0001 : seg_reg = 7'b1111001; // 1
4'b0010 : seg_reg = 7'b0100100; // 2
4'b0011 : seg_reg = 7'b0110000; // 3
4'b0100 : seg_reg = 7'b0011001; // 4
4'b0101 : seg_reg = 7'b0010010; // 5
4'b0110 : seg_reg = 7'b0000010; // 6
4'b0111 : seg_reg = 7'b1111000; // 7
4'b1000 : seg_reg = 7'b0000000; // 8 -> all on
4'b1001 : seg_reg = 7'b0010000; // 9
4'b1010 : seg_reg = 7'b0001000; // A
4'b1011 : seg_reg = 7'b0000011; // b
4'b1100 : seg_reg = 7'b1000110; // C
4'b1101 : seg_reg = 7'b0100001; // d
4'b1110 : seg_reg = 7'b0000110; // E
4'b1111 : seg_reg = 7'b0001110; // F
default : seg_reg = 7'b1000000; // 0
endcase
always @*
case (invert)
1'b1 : segments_out = seg_reg; // do not invert segments for common anode display
1'b0 : segments_out = ~seg_reg; // invert segments for common cathode display
endcase
endmodule
|
`timescale 1ns/1ps
module flushMUX(flushIDEX,RegDstin,RegWrin,ALUSrc1in,ALUSrc2in,ALUFunin,Signin,MemWrin,MemRdin,MemtoRegin,
RegDstout,RegWrout,ALUSrc1out,ALUSrc2out,ALUFunout,Signout,MemWrout,MemRdout,MemtoRegout);
input flushIDEX;
input [1:0] RegDstin;
input RegWrin;
input ALUSrc1in;
input ALUSrc2in;
input [5:0] ALUFunin;
input Signin;
input MemWrin;
input MemRdin;
input [1:0] MemtoRegin;
output [1:0] RegDstout;
reg [1:0] RegDstout;
output RegWrout;
reg RegWrout;
output ALUSrc1out;
reg ALUSrc1out;
output ALUSrc2out;
reg ALUSrc2out;
output [5:0] ALUFunout;
reg [5:0] ALUFunout;
output Signout;
reg Signout;
output MemWrout;
reg MemWrout;
output MemRdout;
reg MemRdout;
output [1:0] MemtoRegout;
reg [1:0] MemtoRegout;
always @(*)
begin
if(~flushIDEX)
begin
RegDstout <= RegDstin;
RegWrout <= RegWrin;
ALUSrc1out <= ALUSrc1in;
ALUSrc2out <= ALUSrc2in;
ALUFunout <= ALUFunin;
Signout <= Signin;
MemWrout <= MemWrin;
MemRdout <= MemRdin;
MemtoRegout <= MemtoRegin;
end
else
begin
RegDstout <= 2'b00;
RegWrout <= 0;
ALUSrc1out <= 0;
ALUSrc2out <= 0;
ALUFunout <= 6'h0;
Signout <= 0;
MemWrout <= 0;
MemRdout <= 0;
MemtoRegout <= 2'b00;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { if (a == 0) return b; return gcd(b % a, a); } template <typename T> T pow(T a, T b, long long m) { T ans = 1; while (b > 0) { if (b % 2 == 1) ans = (ans * a) % m; b /= 2; a = (a * a) % m; } return ans % m; } long long grundy(long long k) { long long i = 1; long long sum = 1; while (sum <= k) { i++; sum += i; } return i - 1; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; long long stxor = 0; for (long long i = 0; i < n; i++) { long long num; cin >> num; stxor ^= grundy(num); } if (stxor == 0) { cout << YES ; } else { cout << NO ; } return 0; } |
`timescale 1ns / 1ns
`define MOD_OSRAM
module tb_ArtyA7;
reg sim_end;
reg RST_N;
reg CLK;
wire uart_txd_in;
wire uart_rxd_out;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1'b0;
/*
`ifdef MOD_OSRAM
force u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.i_base = 32'h2000_0000;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.d_base = 32'h2000_0000;
`endif
*/
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1'b1;
/*
`ifdef MOD_OSRAM
release u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.i_base;
release u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.u_fmrv32im_cache.d_base;
`endif
*/
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
// Clock
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
/*
always @(posedge CLK) begin
if((u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_wstb == 4'hF))
begin
rslt <= u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_wdata;
end
end
*/
// Sinario
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
/*
wait((u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.dbus_wstb == 4'hF));
*/
#();
u_task_uart.write("e");
u_task_uart.write("c");
u_task_uart.write("h");
u_task_uart.write("o");
u_task_uart.write("b");
u_task_uart.write("a");
u_task_uart.write("c");
u_task_uart.write("k");
u_task_uart.write("\r");
u_task_uart.write("\n");
wait(led==4'hF);
repeat(10) @(posedge CLK);
sim_end = 1;
end
integer iena_count;
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x", rslt);
$display("Inst Count: %d", iena_count);
$finish();
end
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.imem);
// initial $readmemh("../../../../src/imem.hex", u_fmrv32im_core.u_fmrv32im_cache.dmem);
ArtyA7
#(
.MEM_FILE ("../../../../src/imem.hex")
)
u_ArtyA7
(
.CLK100MHZ (CLK),
.uart_txd_in (uart_txd_in),
.uart_rxd_out (uart_rxd_out),
.led (led)
);
/*
always @(posedge CLK) begin
if(!RST_N) begin
iena_count <= 0;
end else begin
if(u_ArtyA7.u_fmrv32im_artya7_wrapper.u_fmrv32im_core.ibus_ena) begin
iena_count <= iena_count +1;
end
end
end
*/
task_uart u_task_uart(
.tx(uart_txd_in),
.rx(uart_rxd_out)
);
endmodule // tb_fmrv32im_core
`timescale 1ns / 1ps
module task_uart(
tx,
rx
);
output tx;
input rx;
reg tx;
reg clk, clk2;
reg [7:0] rdata;
reg rx_valid;
wire [7:0] rx_char;
initial begin
clk <= 1'b0;
clk2 <= 1'b0;
tx <= 1'b1;
end
always begin
#(/115200/2) clk <= ~clk;
end
always begin
#(/115200/2/2) clk2 <= ~clk2;
end
task write;
input [7:0] data;
begin
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b0;
@(posedge clk);
tx <= data[0];
@(posedge clk);
tx <= data[1];
@(posedge clk);
tx <= data[2];
@(posedge clk);
tx <= data[3];
@(posedge clk);
tx <= data[4];
@(posedge clk);
tx <= data[5];
@(posedge clk);
tx <= data[6];
@(posedge clk);
tx <= data[7];
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
end
endtask
// Receive
always begin
rx_valid <= 0;
@(posedge clk2);
if(rx == 1'b0) begin
repeat (2) @(posedge clk2);
rdata[0] <= rx;
repeat (2) @(posedge clk2);
rdata[1] <= rx;
repeat (2) @(posedge clk2);
rdata[2] <= rx;
repeat (2) @(posedge clk2);
rdata[3] <= rx;
repeat (2) @(posedge clk2);
rdata[4] <= rx;
repeat (2) @(posedge clk2);
rdata[5] <= rx;
repeat (2) @(posedge clk2);
rdata[6] <= rx;
repeat (2) @(posedge clk2);
rdata[7] <= rx;
repeat (2) @(posedge clk2);
if(rx == 1'b1) begin
// $display("%s", rdata[7:0]);
rx_valid <= 1;
$write("%s", rdata[7:0]);
end
repeat (2) @(posedge clk2);
end
end
assign rx_char = (rx_valid)?rdata:8'd0;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct _d { int r1, c1, r2, c2; }; int n, m; char arr[500][501]; bool ans[600000]; _d queries[600000]; bitset<500> DPU[500][500], DPD[500][500]; void dnc(int l, int r, vector<int> &qid) { if (l > r) return; int mid = (l + r) / 2; vector<int> ql, qr; for (int i = 0; i < qid.size(); i++) { if (queries[qid[i]].r2 < mid) { ql.push_back(qid[i]); qid[i] = qid.back(), qid.pop_back(), --i; } else if (queries[qid[i]].r1 > mid) { qr.push_back(qid[i]); qid[i] = qid.back(), qid.pop_back(), --i; } } if (!qid.empty()) { for (int i = m - 1; i >= 0; i--) { DPU[mid][i] = i != m - 1 && arr[mid][i + 1] == . ? DPU[mid][i + 1] : bitset<500>(); DPU[mid][i][i] = 1; } for (int i = 0; i < m; i++) { DPD[mid][i] = i && arr[mid][i - 1] == . ? DPD[mid][i - 1] : bitset<500>(); DPD[mid][i][i] = 1; } for (int i = mid - 1; i >= l; i--) { for (int j = m - 1; j >= 0; j--) { DPU[i][j] = arr[i + 1][j] == . ? DPU[i + 1][j] : bitset<500>(); if (j != m - 1 && arr[i][j + 1] == . ) DPU[i][j] |= DPU[i][j + 1]; } } for (int i = mid + 1; i <= r; i++) { for (int j = 0; j < m; j++) { DPD[i][j] = arr[i - 1][j] == . ? DPD[i - 1][j] : bitset<500>(); if (j && arr[i][j - 1] == . ) DPD[i][j] |= DPD[i][j - 1]; } } for (int i : qid) { auto cq = queries[i]; ans[i] = (DPU[cq.r1][cq.c1] & DPD[cq.r2][cq.c2]).any(); } } if (!ql.empty()) dnc(l, mid - 1, ql); if (!qr.empty()) dnc(mid + 1, r, qr); } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %s , arr[i]); int q; scanf( %d , &q); vector<int> qid(q); for (int i = 0; i < q; i++) { int r1, c1, r2, c2; scanf( %d%d%d%d , &r1, &c1, &r2, &c2); queries[i] = {r1 - 1, c1 - 1, r2 - 1, c2 - 1}; qid[i] = i; } dnc(0, n - 1, qid); for (int i = 0; i < q; i++) printf(ans[i] ? Yes n : No n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int segtree[400001]; int val[100001]; int inf = (1 << 30) - 1; void build(int l, int r, int pos) { if (l == r) { segtree[pos] = val[r]; return; } int mid = (l + r) / 2; build(l, mid, 2 * pos + 1); build(mid + 1, r, 2 * pos + 2); segtree[pos] = (segtree[2 * pos + 1] & segtree[2 * pos + 2]); } int query(int lq, int rq, int l, int r, int pos) { if (rq < l || lq > r) return inf; if (lq <= l && r <= rq) return segtree[pos]; int mid = (l + r) / 2; return query(lq, rq, l, mid, 2 * pos + 1) & query(lq, rq, mid + 1, r, 2 * pos + 2); } int main() { int n; cin >> n; int m; cin >> m; int flag[n + 1][30]; memset(flag, 0, sizeof flag); int l[m], r[m], v[m]; for (int i = 0; i < m; i++) { cin >> l[i] >> r[i] >> v[i]; l[i]--; r[i]--; for (int j = 0; j < 30; j++) { if (v[i] & (1 << j)) { flag[l[i]][j] += 1; flag[r[i] + 1][j] -= 1; } } } for (int j = 0; j < 30; j++) { for (int i = 1; i < n; i++) { flag[i][j] += flag[i - 1][j]; } } for (int i = 0; i < n; i++) { val[i] = 0; for (int j = 0; j < 30; j++) { if (flag[i][j]) val[i] += (1 << j); } } build(0, n - 1, 0); for (int i = 0; i < m; i++) { if (query(l[i], r[i], 0, n - 1, 0) != v[i]) { cout << NO ; return 0; } } cout << YES n ; for (int j = 0; j < n; j++) cout << val[j] << ; } |
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