text stringlengths 59 71.4k |
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#include <bits/stdc++.h> long long num_div(long long x, long long limit) { long long ans(0); for (long long i = 1; i <= sqrt(x); ++i) { if (!(x % i)) { if (i > limit && i * i == x) ans++; else { if (i > limit) ans++; if (x / i > limit) ans++; } } } return ans; } int main() { long long n, m; scanf( %lld %lld , &n, &m); if (n == m) printf( infinity ); else printf( %lld , n < m ? 0 : num_div(n - m, m)); } |
#include <bits/stdc++.h> using namespace std; int main() { int t, n, p; cin >> t; while (t--) { cin >> n; string s; cin >> s; int c = 0; for (int i = 0; i < n; i++) { if (s[i] == s[i + 1]) c++; } if (c == 1) cout << c << endl; else if (c % 2 != 0) { c /= 2; ++c; cout << c << endl; } else { c /= 2; cout << c << endl; } } } |
`timescale 1ns / 1ps
/*
* File : MEMWB_Stage.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers ()
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 9-Jun-2011 GEA Initial design.
* 2.0 26-Jul-2012 GEA Many updates have been made.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* The Pipeline Register to bridge the Memory and Writeback stages.
*/
module MEMWB_Stage(
input clock,
input reset,
input M_Flush,
input M_Stall,
input WB_Stall,
// Control Signals
input M_RegWrite,
input M_MemtoReg,
// Data Signals
input [31:0] M_ReadData,
input [31:0] M_ALU_Result,
input [4:0] M_RtRd,
// Voter Signals for Registers
input WB_RegWrite,
input WB_MemtoReg,
input [31:0] WB_ReadData,
input [31:0] WB_ALU_Result,
input [4:0] WB_RtRd,
output reg vote_WB_RegWrite,
output reg vote_WB_MemtoReg,
output reg [31:0] vote_WB_ReadData,
output reg [31:0] vote_WB_ALU_Result,
output reg [4:0] vote_WB_RtRd
);
/***
The purpose of a pipeline register is to capture data from one pipeline stage
and provide it to the next pipeline stage. This creates at least one clock cycle
of delay, but reduces the combinatorial path length of signals which allows for
higher clock speeds.
All pipeline registers update unless the forward stage is stalled. When this occurs
or when the current stage is being flushed, the forward stage will receive data that
is effectively a NOP and causes nothing to happen throughout the remaining pipeline
traversal. In other words:
A stall masks all control signals to forward stages. A flush permanently clears
control signals to forward stages (but not certain data for exception purposes).
Since WB is the final stage in the pipeline, it would normally never stall.
However, because the MEM stage may be using data forwarded from WB, WB must stall
when MEM is stalled. If it didn't, the forward data would not be preserved. If
the processor didn't forward any data, a stall would not be needed.
In practice, the only time WB stalls is when forwarding for a Lw->Sw sequence, since
MEM doesn't need the data until its stage, but it does not latch the forwarded data.
This means WB_Stall is probably identical to M_Stall. There is no speed difference by
allowing WB to stall.
***/
always @(posedge clock) begin
vote_WB_RegWrite <= (reset) ? 1'b0 : ((WB_Stall) ? WB_RegWrite : ((M_Stall | M_Flush) ? 1'b0 : M_RegWrite));
vote_WB_MemtoReg <= (reset) ? 1'b0 : ((WB_Stall) ? WB_MemtoReg : M_MemtoReg);
vote_WB_ReadData <= (reset) ? 32'b0 : ((WB_Stall) ? WB_ReadData : M_ReadData);
vote_WB_ALU_Result <= (reset) ? 32'b0 : ((WB_Stall) ? WB_ALU_Result : M_ALU_Result);
vote_WB_RtRd <= (reset) ? 5'b0 : ((WB_Stall) ? WB_RtRd : M_RtRd);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int l[200010], r[200010]; int main() { string s, t; cin >> s >> t; int n = s.size(), k = t.size(); if (s[0] == t[0]) l[0] = 1; if (s[n - 1] == t[k - 1]) r[n - 1] = 1; for (int i = 1; i < n; i++) { if (l[i - 1] < k && s[i] == t[l[i - 1]]) l[i] = l[i - 1] + 1; else l[i] = l[i - 1]; if (r[n - i] < k && s[n - i - 1] == t[k - r[n - i] - 1]) r[n - i - 1] = r[n - i] + 1; else r[n - i - 1] = r[n - i]; } int res = 0; for (int i = 0; i < n; i++) { if (l[i] == k) { res = max(res, n - i - 1); } if (r[i] == k) { res = max(res, i); } } int li = 0, ri = 0; while (li < n) { while (ri < n && r[ri] + l[li] >= k) ri++; ri--; res = max(ri - li - 1, res); li++; } cout << res << endl; } |
// Copyright (c) 2016 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for basic loops in VHDL.
module vhdl_loop_test;
logic start;
int counter;
vhdl_loop dut(start, counter);
initial begin
for(int i = 0; i < 5; ++i) begin
if(counter !== i) begin
$display("FAILED");
$finish();
end
#10;
end
$display("PASSED");
$finish();
end
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : cabac_ctx_state_2p_7x64.v
// Author : guo yong
// Created : 2013-07
// Description : cabac memory for modules
//
//-------------------------------------------------------------------
module cabac_ctx_state_2p_7x64(
//input
clk ,
r_en ,
r_addr ,
w_en ,
w_addr ,
w_data ,
//output
r_data
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk ; //clock signal
input r_en ; //read enable signal
input [5:0] r_addr ; //read address of memory
input w_en ; //write enable signal
input [5:0] w_addr ; //write address of memory
input [6:0] w_data ; //write data of memory
output [6:0] r_data ; //read data from memory
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
rf_2p #(.Addr_Width(6), .Word_Width(7))
rf_2p_ctx_state_7x64 (
.clka ( clk ),
.cena_i ( ~r_en ),
.addra_i ( r_addr ),
.dataa_o ( r_data ),
.clkb ( clk ),
.cenb_i ( ~w_en ),
.wenb_i ( ~w_en ),
.addrb_i ( w_addr ),
.datab_i ( w_data )
);
endmodule
|
module gost89_ecb(
input clk,
input reset,
input mode,
input load_data,
input [511:0] sbox,
input [255:0] key,
input [63:0] in,
output reg [63:0] out,
output reg busy
);
reg [5:0] round_num;
reg [31:0] n1, n2, round_key;
wire [31:0] out1, out2;
gost89_round
rnd(clk, sbox, round_key, n1, n2, out1, out2);
always @(posedge clk) begin
if (load_data) begin
n1 <= in[63:32];
n2 <= in[31:0];
busy <= 1;
round_num <= 0;
end
if (reset && !load_data) begin
busy <= 0;
round_num <= 32;
end
if (!reset && !load_data) begin
if (round_num < 32)
round_num <= round_num + 1;
if (round_num > 0 && round_num < 32) begin
n1 <= out1;
n2 <= out2;
end
if (round_num == 32) begin
out[63:32] <= out2;
out[31:0] <= out1;
busy <= 0;
end
end
end
always @(posedge clk) begin
if (mode)
case (round_num)
0: round_key <= key[255:224];
1: round_key <= key[223:192];
2: round_key <= key[191:160];
3: round_key <= key[159:128];
4: round_key <= key[127:96];
5: round_key <= key[95:64];
6: round_key <= key[63:32];
7: round_key <= key[31:0];
8: round_key <= key[31:0];
9: round_key <= key[63:32];
10: round_key <= key[95:64];
11: round_key <= key[127:96];
12: round_key <= key[159:128];
13: round_key <= key[191:160];
14: round_key <= key[223:192];
15: round_key <= key[255:224];
16: round_key <= key[31:0];
17: round_key <= key[63:32];
18: round_key <= key[95:64];
19: round_key <= key[127:96];
20: round_key <= key[159:128];
21: round_key <= key[191:160];
22: round_key <= key[223:192];
23: round_key <= key[255:224];
24: round_key <= key[31:0];
25: round_key <= key[63:32];
26: round_key <= key[95:64];
27: round_key <= key[127:96];
28: round_key <= key[159:128];
29: round_key <= key[191:160];
30: round_key <= key[223:192];
31: round_key <= key[255:224];
endcase
else
case (round_num)
0: round_key <= key[255:224];
1: round_key <= key[223:192];
2: round_key <= key[191:160];
3: round_key <= key[159:128];
4: round_key <= key[127:96];
5: round_key <= key[95:64];
6: round_key <= key[63:32];
7: round_key <= key[31:0];
8: round_key <= key[255:224];
9: round_key <= key[223:192];
10: round_key <= key[191:160];
11: round_key <= key[159:128];
12: round_key <= key[127:96];
13: round_key <= key[95:64];
14: round_key <= key[63:32];
15: round_key <= key[31:0];
16: round_key <= key[255:224];
17: round_key <= key[223:192];
18: round_key <= key[191:160];
19: round_key <= key[159:128];
20: round_key <= key[127:96];
21: round_key <= key[95:64];
22: round_key <= key[63:32];
23: round_key <= key[31:0];
24: round_key <= key[31:0];
25: round_key <= key[63:32];
26: round_key <= key[95:64];
27: round_key <= key[127:96];
28: round_key <= key[159:128];
29: round_key <= key[191:160];
30: round_key <= key[223:192];
31: round_key <= key[255:224];
endcase
end
endmodule
module gost89_ecb_encrypt(
input clk,
input reset,
input load_data,
input [511:0] sbox,
input [255:0] key,
input [63:0] in,
output reg [63:0] out,
output reg busy
);
reg [5:0] round_num;
reg [31:0] n1, n2, round_key;
wire [31:0] out1, out2;
gost89_round
rnd(clk, sbox, round_key, n1, n2, out1, out2);
always @(posedge clk) begin
if (load_data) begin
n1 <= in[63:32];
n2 <= in[31:0];
busy <= 1;
round_num <= 0;
end
if (reset && !load_data) begin
busy <= 0;
round_num <= 32;
end
if (!reset && !load_data) begin
if (round_num < 32)
round_num <= round_num + 1;
if (round_num > 0 && round_num < 32) begin
n1 <= out1;
n2 <= out2;
end
if (round_num == 32) begin
out[63:32] <= out2;
out[31:0] <= out1;
busy <= 0;
end
end
end
always @(posedge clk)
case (round_num)
0: round_key <= key[255:224];
1: round_key <= key[223:192];
2: round_key <= key[191:160];
3: round_key <= key[159:128];
4: round_key <= key[127:96];
5: round_key <= key[95:64];
6: round_key <= key[63:32];
7: round_key <= key[31:0];
8: round_key <= key[255:224];
9: round_key <= key[223:192];
10: round_key <= key[191:160];
11: round_key <= key[159:128];
12: round_key <= key[127:96];
13: round_key <= key[95:64];
14: round_key <= key[63:32];
15: round_key <= key[31:0];
16: round_key <= key[255:224];
17: round_key <= key[223:192];
18: round_key <= key[191:160];
19: round_key <= key[159:128];
20: round_key <= key[127:96];
21: round_key <= key[95:64];
22: round_key <= key[63:32];
23: round_key <= key[31:0];
24: round_key <= key[31:0];
25: round_key <= key[63:32];
26: round_key <= key[95:64];
27: round_key <= key[127:96];
28: round_key <= key[159:128];
29: round_key <= key[191:160];
30: round_key <= key[223:192];
31: round_key <= key[255:224];
endcase
endmodule
module gost89_ecb_decrypt(
input clk,
input reset,
input load_data,
input [511:0] sbox,
input [255:0] key,
input [63:0] in,
output reg [63:0] out,
output reg busy
);
reg [5:0] round_num;
reg [31:0] n1, n2, round_key;
wire [31:0] out1, out2;
gost89_round
rnd(clk, sbox, round_key, n1, n2, out1, out2);
initial begin
busy = 0;
round_num = 32;
end
always @(posedge clk) begin
if (load_data) begin
n1 <= in[63:32];
n2 <= in[31:0];
busy <= 1;
round_num <= 0;
end
if (reset && !load_data) begin
busy <= 0;
round_num <= 32;
end
if (!reset && !load_data) begin
if (round_num < 32)
round_num <= round_num + 1;
if (round_num > 0 && round_num < 32) begin
n1 <= out1;
n2 <= out2;
end
if (round_num == 32) begin
out[63:32] = out2;
out[31:0] = out1;
busy <= 0;
end
end
end
always @(posedge clk)
case (round_num)
0: round_key <= key[255:224];
1: round_key <= key[223:192];
2: round_key <= key[191:160];
3: round_key <= key[159:128];
4: round_key <= key[127:96];
5: round_key <= key[95:64];
6: round_key <= key[63:32];
7: round_key <= key[31:0];
8: round_key <= key[31:0];
9: round_key <= key[63:32];
10: round_key <= key[95:64];
11: round_key <= key[127:96];
12: round_key <= key[159:128];
13: round_key <= key[191:160];
14: round_key <= key[223:192];
15: round_key <= key[255:224];
16: round_key <= key[31:0];
17: round_key <= key[63:32];
18: round_key <= key[95:64];
19: round_key <= key[127:96];
20: round_key <= key[159:128];
21: round_key <= key[191:160];
22: round_key <= key[223:192];
23: round_key <= key[255:224];
24: round_key <= key[31:0];
25: round_key <= key[63:32];
26: round_key <= key[95:64];
27: round_key <= key[127:96];
28: round_key <= key[159:128];
29: round_key <= key[191:160];
30: round_key <= key[223:192];
31: round_key <= key[255:224];
endcase
endmodule
|
/* This module implements the VGA controller. It assumes a 25MHz clock is supplied as input.
*
* General approach:
* Go through each line of the screen and read the colour each pixel on that line should have from
* the Video memory. To do that for each (x,y) pixel on the screen convert (x,y) coordinate to
* a memory_address at which the pixel colour is stored in Video memory. Once the pixel colour is
* read from video memory its brightness is first increased before it is forwarded to the VGA DAC.
*/
module vga_controller( vga_clock, resetn, pixel_colour, memory_address,
VGA_R, VGA_G, VGA_B,
VGA_HS, VGA_VS, VGA_BLANK,
VGA_SYNC, VGA_CLK);
/* Screen resolution and colour depth parameters. */
parameter BITS_PER_COLOUR_CHANNEL = 1;
/* The number of bits per colour channel used to represent the colour of each pixel. A value
* of 1 means that Red, Green and Blue colour channels will use 1 bit each to represent the intensity
* of the respective colour channel. For BITS_PER_COLOUR_CHANNEL=1, the adapter can display 8 colours.
* In general, the adapter is able to use 2^(3*BITS_PER_COLOUR_CHANNEL) colours. The number of colours is
* limited by the screen resolution and the amount of on-chip memory available on the target device.
*/
parameter MONOCHROME = "FALSE";
/* Set this parameter to "TRUE" if you only wish to use black and white colours. Doing so will reduce
* the amount of memory you will use by a factor of 3. */
parameter RESOLUTION = "320x240";
/* Set this parameter to "160x120" or "320x240". It will cause the VGA adapter to draw each dot on
* the screen by using a block of 4x4 pixels ("160x120" resolution) or 2x2 pixels ("320x240" resolution).
* It effectively reduces the screen resolution to an integer fraction of 640x480. It was necessary
* to reduce the resolution for the Video Memory to fit within the on-chip memory limits.
*/
parameter USING_DE1 = "TRUE";
/* If set to "TRUE" it adjust the offset of the drawing mechanism to account for the differences
* between the DE2 and DE1 VGA digital to analogue converters. Set to "TRUE" if and only if
* you are running your circuit on a DE1 board. */
//--- Timing parameters.
/* Recall that the VGA specification requires a few more rows and columns are drawn
* when refreshing the screen than are actually present on the screen. This is necessary to
* generate the vertical and the horizontal syncronization signals. If you wish to use a
* display mode other than 640x480 you will need to modify the parameters below as well
* as change the frequency of the clock driving the monitor (VGA_CLK).
*/
parameter C_VERT_NUM_PIXELS = 11'd480;
parameter C_VERT_SYNC_START = 11'd493;
parameter C_VERT_SYNC_END = 11'd494; //(C_VERT_SYNC_START + 2 - 1);
parameter C_VERT_TOTAL_COUNT = 11'd525;
parameter C_HORZ_NUM_PIXELS = 11'd640;
parameter C_HORZ_SYNC_START = 11'd659;
parameter C_HORZ_SYNC_END = 11'd754; //(C_HORZ_SYNC_START + 96 - 1);
parameter C_HORZ_TOTAL_COUNT = 11'd800;
/*****************************************************************************/
/* Declare inputs and outputs. */
/*****************************************************************************/
input vga_clock, resetn;
input [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] pixel_colour;
output [((RESOLUTION == "320x240") ? (16) : (14)):0] memory_address;
output reg [9:0] VGA_R;
output reg [9:0] VGA_G;
output reg [9:0] VGA_B;
output reg VGA_HS;
output reg VGA_VS;
output reg VGA_BLANK;
output VGA_SYNC, VGA_CLK;
/*****************************************************************************/
/* Local Signals. */
/*****************************************************************************/
reg VGA_HS1;
reg VGA_VS1;
reg VGA_BLANK1;
reg [9:0] xCounter, yCounter;
wire xCounter_clear;
wire yCounter_clear;
wire vcc;
reg [((RESOLUTION == "320x240") ? (8) : (7)):0] x;
reg [((RESOLUTION == "320x240") ? (7) : (6)):0] y;
/* Inputs to the converter. */
/*****************************************************************************/
/* Controller implementation. */
/*****************************************************************************/
assign vcc =1'b1;
/* A counter to scan through a horizontal line. */
always @(posedge vga_clock or negedge resetn)
begin
if (!resetn)
xCounter <= 10'd0;
else if (xCounter_clear)
xCounter <= 10'd0;
else
begin
xCounter <= xCounter + 1'b1;
end
end
assign xCounter_clear = (xCounter == (C_HORZ_TOTAL_COUNT-1));
/* A counter to scan vertically, indicating the row currently being drawn. */
always @(posedge vga_clock or negedge resetn)
begin
if (!resetn)
yCounter <= 10'd0;
else if (xCounter_clear && yCounter_clear)
yCounter <= 10'd0;
else if (xCounter_clear) //Increment when x counter resets
yCounter <= yCounter + 1'b1;
end
assign yCounter_clear = (yCounter == (C_VERT_TOTAL_COUNT-1));
/* Convert the xCounter/yCounter location from screen pixels (640x480) to our
* local dots (320x240 or 160x120). Here we effectively divide x/y coordinate by 2 or 4,
* depending on the resolution. */
always @(*)
begin
if (RESOLUTION == "320x240")
begin
x = xCounter[9:1];
y = yCounter[8:1];
end
else
begin
x = xCounter[9:2];
y = yCounter[8:2];
end
end
/* Change the (x,y) coordinate into a memory address. */
vga_address_translator controller_translator(
.x(x), .y(y), .mem_address(memory_address) );
defparam controller_translator.RESOLUTION = RESOLUTION;
/* Generate the vertical and horizontal synchronization pulses. */
always @(posedge vga_clock)
begin
//- Sync Generator (ACTIVE LOW)
if (USING_DE1 == "TRUE")
VGA_HS1 <= ~((xCounter >= C_HORZ_SYNC_START-2) && (xCounter <= C_HORZ_SYNC_END-2));
else
VGA_HS1 <= ~((xCounter >= C_HORZ_SYNC_START) && (xCounter <= C_HORZ_SYNC_END));
VGA_VS1 <= ~((yCounter >= C_VERT_SYNC_START) && (yCounter <= C_VERT_SYNC_END));
//- Current X and Y is valid pixel range
VGA_BLANK1 <= ((xCounter < C_HORZ_NUM_PIXELS) && (yCounter < C_VERT_NUM_PIXELS));
//- Add 1 cycle delay
VGA_HS <= VGA_HS1;
VGA_VS <= VGA_VS1;
VGA_BLANK <= VGA_BLANK1;
end
/* VGA sync should be 1 at all times. */
assign VGA_SYNC = vcc;
/* Generate the VGA clock signal. */
assign VGA_CLK = vga_clock;
/* Brighten the colour output. */
// The colour input is first processed to brighten the image a little. Setting the top
// bits to correspond to the R,G,B colour makes the image a bit dull. To brighten the image,
// each bit of the colour is replicated through the 10 DAC colour input bits. For example,
// when BITS_PER_COLOUR_CHANNEL is 2 and the red component is set to 2'b10, then the
// VGA_R input to the DAC will be set to 10'b1010101010.
integer index;
integer sub_index;
wire on_screen;
assign on_screen = (USING_DE1 == "TRUE") ?
(({1'b0, xCounter} >= 2) & ({1'b0, xCounter} < C_HORZ_NUM_PIXELS+2) & ({1'b0, yCounter} < C_VERT_NUM_PIXELS)) :
(({1'b0, xCounter} >= 0) & ({1'b0, xCounter} < C_HORZ_NUM_PIXELS+2) & ({1'b0, yCounter} < C_VERT_NUM_PIXELS));
always @(pixel_colour or on_screen)
begin
VGA_R <= 'b0;
VGA_G <= 'b0;
VGA_B <= 'b0;
if (MONOCHROME == "FALSE")
begin
for (index = 10-BITS_PER_COLOUR_CHANNEL; index >= 0; index = index - BITS_PER_COLOUR_CHANNEL)
begin
for (sub_index = BITS_PER_COLOUR_CHANNEL - 1; sub_index >= 0; sub_index = sub_index - 1)
begin
VGA_R[sub_index+index] <= on_screen & pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL*2];
VGA_G[sub_index+index] <= on_screen & pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL];
VGA_B[sub_index+index] <= on_screen & pixel_colour[sub_index];
end
end
end
else
begin
for (index = 0; index < 10; index = index + 1)
begin
VGA_R[index] <= on_screen & pixel_colour[0:0];
VGA_G[index] <= on_screen & pixel_colour[0:0];
VGA_B[index] <= on_screen & pixel_colour[0:0];
end
end
end
endmodule
|
//------------------------------------------------------------------------------
// Copyright (c) 2007 Xilinx, Inc.
// All Rights Reserved
// $Revision: $ $Date: $
//-----------------------------------------------------------------------------
// (c) Copyright 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------
// This module infers a RAM that is 2^RAM_ADRESS_SIZE x RAM_WIDTH.
// It uses this RAM in an asynchronous FIFO.
// Since this FIFO is asynchronous, pointers
// are passed between clock domains using sample and
// a sample and handshaking for glitch-free operation. However,
// this synchronization requires latency, so updating of the
// flags and levels is not instantaneous and is pessimistic.
// Level is not valid if any of the flags are active.
//
//-----------------------------------------------------------------------------
`timescale 1 ps / 1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module v_axi4s_vid_out_v3_0_bridge_async_fifo_2
#(
// Parmeter for RAM Depth is in GUI
// Paraemeter for RAM width allows for future expanded component widths
// Initial width is fixed at 8/8/8
parameter RAM_WIDTH =26,
parameter RAM_ADDR_BITS = 10 // default depth = 1024
)
(
input wire wr_clk, // write clock
input wire rd_clk, // read clock
input wire rst, // async_reset
input wire wr_ce, // write clock enable
input wire rd_ce, // read clock enable
input wire wr_en, // write enable
input wire rd_en, // read enable
input wire [RAM_WIDTH-1:0] din, // data_in
output reg [RAM_WIDTH-1:0] dout, // output data
output reg empty, // empty flag in read clock domain
output reg rd_error, // read error (read when empty)
output reg full, // full flag in write clock domain
output reg wr_error, // write error (write when full)
output [RAM_ADDR_BITS-1:0] level_rd, // level in read domain
output [RAM_ADDR_BITS-1:0] level_wr // level in write domain
);
reg [RAM_WIDTH-1:0] fifo_ram [(2**RAM_ADDR_BITS)-1:0]; // RAM storage
wire [RAM_WIDTH-1:0] ram_out; // RAM output
(*ASYNC_REG = "TRUE"*) reg rst_wr_1; // reset synchronizing registers
(*ASYNC_REG = "TRUE"*) reg rst_wr_2;
(*ASYNC_REG = "TRUE"*) reg rst_rd_1;
(*ASYNC_REG = "TRUE"*) reg rst_rd_2;
reg [RAM_ADDR_BITS+1:0] rd_ptr =0; // FIFO read pointer
reg [RAM_ADDR_BITS+1:0] wr_ptr =1; // FIFO write pointer
wire [RAM_ADDR_BITS-1:0] rd_addr; // ram_addresses
wire [RAM_ADDR_BITS-1:0] wr_addr; // ram_addresses
reg [RAM_ADDR_BITS+1:0] rd_ptr_sample; // pointer sample regs
reg [RAM_ADDR_BITS+1:0] rd_ptr_wr_dom;
reg [RAM_ADDR_BITS+1:0] wr_ptr_sample;
reg [RAM_ADDR_BITS+1:0] wr_ptr_rd_dom;
wire ce_rd_ptr_sample; // clock enables for ptr samp regs
wire ce_rd_ptr_wr_dom;
wire ce_wr_ptr_sample;
wire ce_wr_ptr_rd_dom;
wire rd_to_wr_req; // pointer sync handshaking
wire rd_to_wr_ack;
wire wr_to_rd_req;
wire wr_to_rd_ack;
(*ASYNC_REG = "TRUE"*) reg req_wr_dom_1; // sycnronizer registers rd to wr
(*ASYNC_REG = "TRUE"*) reg req_wr_dom_2;
(*ASYNC_REG = "TRUE"*) reg req_wr_dom_3;
(*ASYNC_REG = "TRUE"*) reg ack_rd_dom_1;
(*ASYNC_REG = "TRUE"*) reg ack_rd_dom_2;
(*ASYNC_REG = "TRUE"*) reg ack_rd_dom_3;
(*ASYNC_REG = "TRUE"*) reg req_rd_dom_1; // sycnronizer registers wr to rd
(*ASYNC_REG = "TRUE"*) reg req_rd_dom_2;
(*ASYNC_REG = "TRUE"*) reg req_rd_dom_3;
(*ASYNC_REG = "TRUE"*) reg ack_wr_dom_1;
(*ASYNC_REG = "TRUE"*) reg ack_wr_dom_2;
(*ASYNC_REG = "TRUE"*) reg ack_wr_dom_3;
wire [RAM_ADDR_BITS+1:0] ptr_diff_rd_dom_comb;//Pointer difference comb.
reg [RAM_ADDR_BITS+1:0] ptr_diff_rd_dom; //Pointer difference values
reg [RAM_ADDR_BITS+1:0] ptr_diff_wr_dom;
wire empty_comb; // combinatorial empty flag
wire full_comb; // combinatorial full flag
wire[RAM_ADDR_BITS+1:0] ptr_diff_wr_dom_comb; //combinatorial pointer diff
// read error tracking regs
reg ram_out_rd_error;
//
// pointers and flags
//
// parse pointers into addresses and revolutuion numbers
assign wr_addr = wr_ptr[RAM_ADDR_BITS-1:0];
assign rd_addr = rd_ptr[RAM_ADDR_BITS-1:0];
assign ptr_diff_wr_dom_comb = wr_ptr - rd_ptr_wr_dom;
// Define levels
assign level_rd = ptr_diff_rd_dom[RAM_ADDR_BITS-1:0];
assign level_wr = ptr_diff_wr_dom[RAM_ADDR_BITS-1:0];
assign ptr_diff_rd_dom_comb = wr_ptr_rd_dom- rd_ptr;
// Define requests and acknowledge bits for clock-crossing handshaking
assign rd_to_wr_req = !ack_rd_dom_3;
assign rd_to_wr_ack = req_wr_dom_3;
assign wr_to_rd_req = !ack_wr_dom_3;
assign wr_to_rd_ack = req_rd_dom_3;
// Define enables for clock-crossing sample registers.
assign ce_rd_ptr_sample = ack_rd_dom_2 ^ ack_rd_dom_3;
assign ce_rd_ptr_wr_dom = req_wr_dom_2 ^ req_wr_dom_3;
assign ce_wr_ptr_sample = ack_wr_dom_2 ^ ack_wr_dom_3;
assign ce_wr_ptr_rd_dom = req_rd_dom_2 ^ req_rd_dom_3;
// Define combinatorial flags
assign empty_comb = ptr_diff_rd_dom_comb <= 1;
assign full_comb = ptr_diff_wr_dom_comb[RAM_ADDR_BITS];
//
// infer RAM
//
always @(posedge wr_clk)
if (wr_en & wr_ce)
fifo_ram[wr_addr] <= din;
assign ram_out = fifo_ram[rd_addr];
//
// Move pointers
//
// Write-clock domain
always @ (posedge wr_clk) begin
rst_wr_1 <= rst;
rst_wr_2 <= rst_wr_1;
if (rst_wr_2) begin
wr_ptr <= 1;
wr_ptr_sample <= 0;
rd_ptr_wr_dom <= 0;
req_wr_dom_1 <= 0;
req_wr_dom_2 <= 0;
req_wr_dom_3 <= 0;
ack_wr_dom_1 <= 0;
ack_wr_dom_2 <= 0;
ack_wr_dom_3 <= 0;
ptr_diff_wr_dom <= 0;
full <= 0;
wr_error <= 0;
end
else begin
if (wr_ce) begin
if (wr_en) begin
if (full_comb) begin
wr_error <= 1;
end
else begin
wr_ptr <= wr_ptr+1; // increment write pointer
wr_error <= 0;
end
end
else begin
wr_error <= 0;
end
end // if (wr_ce)
// sample write pointer
if (ce_wr_ptr_sample)
wr_ptr_sample <= wr_ptr;
// synchronize read pointer into write domain
if (ce_rd_ptr_wr_dom)
rd_ptr_wr_dom <= rd_ptr_sample;
// delay registers for wr to rd handshaking
ack_wr_dom_1 <= wr_to_rd_ack;
ack_wr_dom_2 <= ack_wr_dom_1;
ack_wr_dom_3 <= ack_wr_dom_2;
// delay registers for rd to wr handshaking
req_wr_dom_1 <= rd_to_wr_req;
req_wr_dom_2 <= req_wr_dom_1;
req_wr_dom_3 <= req_wr_dom_2;
ptr_diff_wr_dom <= ptr_diff_wr_dom_comb;
full <= full_comb;
end
end
// Read-clock domain
always @ (posedge rd_clk ) begin
rst_rd_1 <= rst;
rst_rd_2 <= rst_rd_1;
if (rst_rd_2) begin
rd_ptr <= 0;
rd_ptr_sample <= 0;
wr_ptr_rd_dom <= 0;
req_rd_dom_1 <= 0;
req_rd_dom_2 <= 0;
req_rd_dom_3 <= 0;
ack_rd_dom_1 <= 0;
ack_rd_dom_2 <= 0;
ack_rd_dom_3 <= 0;
ptr_diff_rd_dom <= 0;
empty <= 1;
rd_error <= 0;
dout <= 0;
ram_out_rd_error <= 0;
end
else begin
if (rd_ce) begin
if (rd_en) begin
dout <= ram_out;
rd_error <= ram_out_rd_error;
if (empty_comb) begin
ram_out_rd_error <= 1;
end
else if (!empty_comb) begin
rd_ptr <= rd_ptr + 1;
ram_out_rd_error <= 0;
end
end // if (rd_en)
end
// sample read pointer
if (ce_rd_ptr_sample)
rd_ptr_sample <= rd_ptr;
// delay registers for rd to wr handshaking
ack_rd_dom_1 <= rd_to_wr_ack;
ack_rd_dom_2 <= ack_rd_dom_1;
ack_rd_dom_3 <= ack_rd_dom_2;
// delay registers for wr to rd handshaking
req_rd_dom_1 <= wr_to_rd_req;
req_rd_dom_2 <= req_rd_dom_1;
req_rd_dom_3 <= req_rd_dom_2;
// synchonize write pointer into read clock domain
if (ce_wr_ptr_rd_dom)
wr_ptr_rd_dom <= wr_ptr_sample;
empty <= ptr_diff_rd_dom_comb <= 1;
ptr_diff_rd_dom <= ptr_diff_rd_dom_comb;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222O_2_V
`define SKY130_FD_SC_HS__A222O_2_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog wrapper for a222o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a222o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a222o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a222o_2 (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222O_2_V
|
#include <bits/stdc++.h> long long n, md; void rid(int n, int m) { int i; long long sol = 1, p = 1; for (i = 0, p = n; i <= 30; i++) { if ((m & (1 << i)) == (1 << i)) { sol = (long long)sol * p; sol = (long long)sol % md; } p = (long long)p * p; p = (long long)p % md; } if (sol == 0) sol = md - 1; else sol--; printf( %I64d , sol); } int main() { scanf( %I64d%I64d , &n, &md); rid(3, n); } |
#include <bits/stdc++.h> using namespace std; int n, m, a, b, ms[111][111], d[111], w[111], dd[111]; double f[111], ff[111], ans; int main() { cin >> n >> m; memset(ms, 63, sizeof(ms)); for (int i = 0; i < m; i++) { cin >> a >> b; a--; b--; ms[a][b] = ms[b][a] = 1; } memset(d, 63, sizeof(d)); d[0] = 0; f[0] = 1; memset(w, 0, sizeof(w)); for (int i = 0; i < n; i++) { int o = 1e9, l; for (int i = 0; i < n; i++) if (!w[i] && d[i] < o) o = d[i], l = i; w[l] = 1; for (int i = 0; i < n; i++) if (o + ms[l][i] < d[i]) { d[i] = o + ms[l][i]; f[i] = f[l]; } else if (o + ms[l][i] == d[i]) f[i] += f[l]; } memset(dd, 63, sizeof(dd)); dd[n - 1] = 0; ff[n - 1] = 1; memset(w, 0, sizeof(w)); for (int i = 0; i < n; i++) { int o = 1e9, l; for (int i = 0; i < n; i++) if (!w[i] && dd[i] < o) o = dd[i], l = i; w[l] = 1; for (int i = 0; i < n; i++) if (o + ms[l][i] < dd[i]) { dd[i] = o + ms[l][i]; ff[i] = ff[l]; } else if (o + ms[l][i] == dd[i]) ff[i] += ff[l]; } for (int i = 0; i < n; i++) { double o = 0; for (int j = 0; j < n; j++) if (ms[i][j] == 1) { if (d[i] + 1 + dd[j] == d[n - 1]) o += f[i] * ff[j]; if (dd[i] + 1 + d[j] == d[n - 1]) o += ff[i] * f[j]; } ans = max(ans, o); } printf( %.10lf n , ans / f[n - 1]); return 0; } |
#include <bits/stdc++.h> int n, a[105], ans; int comp(const void* elem1, const void* elem2) { int f = *((int*)elem1); int s = *((int*)elem2); if (f > s) return 1; if (f < s) return -1; return 0; } int main(int argc, char* argv[]) { scanf( %d , &n); int i; for (i = 0; i < n; ++i) { int HH, MM; scanf( %d:%d , &HH, &MM); a[i] = HH * 60 + MM; } qsort(a, n, sizeof(a[0]), comp); ans = 0; for (i = 0; i < n - 1; ++i) { if (a[i + 1] - a[i] > ans) { ans = a[i + 1] - a[i]; } } if (a[0] + 24 * 60 - a[n - 1] > ans) { ans = a[0] + 24 * 60 - a[n - 1]; } ans--; int d1, d2; d1 = ans / 60; d2 = ans % 60; if (d1 < 10) { if (d2 < 10) { printf( 0%d:0%d n , d1, d2); } else { printf( 0%d:%d n , d1, d2); } } else { if (d2 < 10) { printf( %d:0%d n , d1, d2); } else { printf( %d:%d n , d1, d2); } } return 0; } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module chipselects reads and writes to the sram, with 2-cycle *
* read latency and one cycle write latency. *
* *
******************************************************************************/
module video_sys_Pixel_Buffer (
// Inputs
clk,
reset,
address,
byteenable,
read,
write,
writedata,
// Bi-Directional
SRAM_DQ,
// Outputs
readdata,
readdatavalid,
SRAM_ADDR,
SRAM_LB_N,
SRAM_UB_N,
SRAM_CE_N,
SRAM_OE_N,
SRAM_WE_N
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [17: 0] address;
input [ 1: 0] byteenable;
input read;
input write;
input [15: 0] writedata;
// Bi-Directional
inout [15: 0] SRAM_DQ; // SRAM Data bus 16 Bits
// Outputs
output reg [15: 0] readdata;
output reg readdatavalid;
output reg [17: 0] SRAM_ADDR; // SRAM Address bus 18 Bits
output reg SRAM_LB_N; // SRAM Low-byte Data Mask
output reg SRAM_UB_N; // SRAM High-byte Data Mask
output reg SRAM_CE_N; // SRAM Chip chipselect
output reg SRAM_OE_N; // SRAM Output chipselect
output reg SRAM_WE_N; // SRAM Write chipselect
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg is_read;
reg is_write;
reg [15: 0] writedata_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
readdata <= SRAM_DQ;
readdatavalid <= is_read;
SRAM_ADDR <= address;
SRAM_LB_N <= ~(byteenable[0] & (read | write));
SRAM_UB_N <= ~(byteenable[1] & (read | write));
SRAM_CE_N <= ~(read | write);
SRAM_OE_N <= ~read;
SRAM_WE_N <= ~write;
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
is_read <= 1'b0;
else
is_read <= read;
end
always @(posedge clk)
begin
if (reset)
is_write <= 1'b0;
else
is_write <= write;
end
always @(posedge clk)
begin
writedata_reg <= writedata;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign SRAM_DQ = (is_write) ? writedata_reg : 16'hzzzz;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3B_LP_V
`define SKY130_FD_SC_LP__AND3B_LP_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3b_lp (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3b_lp (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3B_LP_V
|
#include <bits/stdc++.h> using namespace std; int n, V, offset; int d[1005]; int u[1000005], v[1000005], cnt = 0; inline void print(int u, int v) { ::u[++cnt] = u + offset; ::v[cnt] = v + offset; } int main() { int i, j; scanf( %d , &n); for (i = 1; i <= n; ++i) scanf( %d , d + i); V = d[n] + 1; for (offset = 1;; ++offset) { if (!d[1]) { offset = V - d[n]; for (i = 1; i < n; ++i) d[i] = d[i + 1]; d[n--] = 0; } if (n <= 1) { for (i = 0; i < d[1]; ++i) for (j = i + 1; j <= d[1]; ++j) print(i, j); break; } for (i = 1; i <= d[n]; ++i) print(0, i); for (i = 1; i <= n; ++i) --d[i]; if (!d[1]) { d[n--] = 0; if (n <= 1) break; } } printf( %d n , cnt); for (i = 1; i <= cnt; ++i) printf( %d %d n , u[i], v[i]); return 0; } |
#include <bits/stdc++.h> const int N = 1e5 + 1e4; struct edg { int now, to, val; } ed[N]; struct edge { int to, next; } e[N]; int ehead[N], ecnt; inline void add_edge(int now, int to) { ecnt++; e[ecnt].to = to; e[ecnt].next = ehead[now]; ehead[now] = ecnt; } int n, m, left, rig, mid; int pos[N], ans[N], acnt, pcnt; void dfs(int now) { pos[now] = 1; for (int i = ehead[now]; i; i = e[i].next) if (pos[e[i].to] == 0) dfs(e[i].to); pos[now] = ++pcnt; } inline bool check(int lim) { ecnt = acnt = 0; memset(ehead, 0, sizeof(ehead)); memset(pos, 0, sizeof(pos)); for (int i = 1; i <= m; i++) if (ed[i].val > lim) add_edge(ed[i].now, ed[i].to); for (int i = 1; i <= n; i++) if (!pos[i]) dfs(i); for (int i = 1; i <= m; i++) if (pos[ed[i].now] < pos[ed[i].to]) if (ed[i].val > lim) return false; else ans[++acnt] = i; return true; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) scanf( %d%d%d , &ed[i].now, &ed[i].to, &ed[i].val); rig = 1e9; while (left != rig) { mid = (left + rig) >> 1; if (check(mid)) rig = mid; else left = mid + 1; } check(left); printf( %d %d n , left, acnt); for (int i = 1; i <= acnt; i++) printf( %d , ans[i]); } |
#include <bits/stdc++.h> using namespace std; void FAST_IO(string filein = , string fileout = , string fileerr = ) { if (fopen(filein.c_str(), r )) { freopen(filein.c_str(), r , stdin); freopen(fileout.c_str(), w , stdout); } cin.tie(0), cout.tie(0)->sync_with_stdio(0); } void Hollwo_Pelw(); signed main() { FAST_IO( hollwo_pelw.inp , hollwo_pelw.out ); int testcases = 1; for (int test = 1; test <= testcases; test++) { Hollwo_Pelw(); } return 0; } const int N = 14, inf = 2e9; inline bool smin(int &a, int b) { return a > b ? a = b, 1 : 0; } int n, m, adj[N][N]; int path[N][N][1 << N], dp[1 << N]; int tr[1 << N], ps[1 << N], pe[1 << N]; void Hollwo_Pelw() { cin >> n >> m; for (int i = 0, u, v; i < m; i++) cin >> u >> v, --u, --v, adj[u][v] = adj[v][u] = 1; memset(path, -1, sizeof path); for (int mask = 0; mask < 1 << n; mask++) { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (mask >> i & 1) continue; if (mask >> j & 1) continue; if (__builtin_popcount(mask) == 1 && i == j) continue; if ((i == j || adj[i][j]) && !mask) { path[i][j][mask] = i; } else { for (int k = 0; k < n; k++) { if ((mask >> k & 1) && path[i][k][mask ^ (1 << k)] >= 0 && adj[k][j]) { path[i][j][mask] = k; break; } } } } } } for (int mask = 1; mask < (1 << n); mask++) { if (__builtin_popcount(mask) == 1) { dp[mask] = 0; } else { dp[mask] = inf; for (int sub = mask; sub; sub = (sub - 1) & mask) { int nmask = mask ^ sub; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if ((nmask >> i & 1) && (nmask >> j & 1) && path[i][j][sub] >= 0) { if (smin(dp[mask], dp[nmask] + __builtin_popcount(sub) + 1)) tr[mask] = sub, ps[mask] = i, pe[mask] = j; } } } } } } cout << dp[(1 << n) - 1] << n ; int cur = (1 << n) - 1; while (__builtin_popcount(cur) > 1) { int nxt = tr[cur], i = ps[cur], j = pe[cur]; cur ^= tr[cur]; do { int k = path[i][j][nxt]; cout << k + 1 << << j + 1 << n ; nxt ^= 1 << k, j = k; } while (i != j); } } |
#include <bits/stdc++.h> using namespace std; char A[2005][2005], B[2005][2005]; int last_valid; pair<int, int> lb[26], ub[26]; bool ans; void _clear(int n, int m) { for (int i = 0; i < 26; ++i) { lb[i] = make_pair(INT_MAX, INT_MAX); ub[i] = make_pair(INT_MIN, INT_MIN); } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { B[i][j] = . ; } } ans = true; last_valid = -1; } void _populate(int n, int m) { for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (A[i][j] == . ) continue; char c = A[i][j] - a ; lb[c].first = min(lb[c].first, i); lb[c].second = min(lb[c].second, j); ub[c].first = max(ub[c].first, i); ub[c].second = max(ub[c].second, j); } } } void _regenerate() { for (int i = 0; i < 26; ++i) { if (lb[i].first != INT_MAX) { last_valid = i; if (lb[i].first == ub[i].first) { int x = lb[i].first; for (int j = lb[i].second; j <= ub[i].second; ++j) B[x][j] = i + a ; } else if (lb[i].second == ub[i].second) { int x = lb[i].second; for (int j = lb[i].first; j <= ub[i].first; ++j) B[j][x] = i + a ; } else ans = false; } } } void _compare(int n, int m) { for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (A[i][j] != B[i][j]) ans = false; } } } void _print() { if (!ans) { cout << NO << endl; return; } cout << YES << endl; cout << last_valid + 1 << endl; for (int i = 0; i <= last_valid; ++i) { if (lb[i].first != INT_MAX) { cout << lb[i].first + 1 << << lb[i].second + 1 << << ub[i].first + 1 << << ub[i].second + 1 << endl; } else { int x = last_valid; cout << lb[x].first + 1 << << lb[x].second + 1 << << ub[x].first + 1 << << ub[x].second + 1 << endl; } } } void _debug(int n, int m) { for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) cout << A[i][j] << ; cout << endl; } cout << endl; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) cout << B[i][j] << ; cout << endl; } cout << endl; } int main() { ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(0); int t, n, m, i, j, k, x, y, z, a, b, c; cin >> t; while (t--) { cin >> n >> m; for (i = 0; i < n; ++i) cin >> A[i]; _clear(n, m); _populate(n, m); _regenerate(); _compare(n, m); _print(); } return 0; } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module generates the clocks needed for the I/O devices on *
* Altera's DE-series boards. *
* *
******************************************************************************/
module Video_System_Clock_Signals (
// Inputs
CLOCK_50,
reset,
// Bidirectional
// Outputs
VGA_CLK,
sys_clk,
sys_reset_n
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input reset;
// Bidirectionals
// Outputs
output VGA_CLK;
output sys_clk;
output sys_reset_n;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
localparam SYS_CLK_MULT = 1;
localparam SYS_CLK_DIV = 1;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 2: 0] sys_mem_clks;
wire clk_locked;
wire video_in_clk;
wire SDRAM_CLK;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign sys_reset_n = clk_locked;
assign sys_clk = sys_mem_clks[0];
assign SDRAM_CLK = sys_mem_clks[1];
assign VGA_CLK = sys_mem_clks[2];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altpll DE_Clock_Generator_System (
// Inputs
.inclk ({1'b0, CLOCK_50}),
// Outputs
.clk (sys_mem_clks),
.locked (clk_locked),
// Unused
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 ()
);
defparam
DE_Clock_Generator_System.clk0_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk0_duty_cycle = 50,
DE_Clock_Generator_System.clk0_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk0_phase_shift = "0",
DE_Clock_Generator_System.clk1_divide_by = SYS_CLK_DIV,
DE_Clock_Generator_System.clk1_duty_cycle = 50,
DE_Clock_Generator_System.clk1_multiply_by = SYS_CLK_MULT,
DE_Clock_Generator_System.clk1_phase_shift = "-3000",
DE_Clock_Generator_System.clk2_divide_by = 2,
DE_Clock_Generator_System.clk2_duty_cycle = 50,
DE_Clock_Generator_System.clk2_multiply_by = 1,
DE_Clock_Generator_System.clk2_phase_shift = "20000",
DE_Clock_Generator_System.compensate_clock = "CLK0",
DE_Clock_Generator_System.gate_lock_signal = "NO",
DE_Clock_Generator_System.inclk0_input_frequency = 20000,
DE_Clock_Generator_System.intended_device_family = "Cyclone II",
DE_Clock_Generator_System.invalid_lock_multiplier = 5,
DE_Clock_Generator_System.lpm_type = "altpll",
DE_Clock_Generator_System.operation_mode = "NORMAL",
DE_Clock_Generator_System.pll_type = "FAST",
DE_Clock_Generator_System.port_activeclock = "PORT_UNUSED",
DE_Clock_Generator_System.port_areset = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkbad1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkloss = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkswitch = "PORT_UNUSED",
DE_Clock_Generator_System.port_fbin = "PORT_UNUSED",
DE_Clock_Generator_System.port_inclk0 = "PORT_USED",
DE_Clock_Generator_System.port_inclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_locked = "PORT_USED",
DE_Clock_Generator_System.port_pfdena = "PORT_UNUSED",
DE_Clock_Generator_System.port_pllena = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanaclr = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanclk = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandata = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandataout = "PORT_UNUSED",
DE_Clock_Generator_System.port_scandone = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanread = "PORT_UNUSED",
DE_Clock_Generator_System.port_scanwrite = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk0 = "PORT_USED",
DE_Clock_Generator_System.port_clk1 = "PORT_USED",
DE_Clock_Generator_System.port_clk2 = "PORT_USED",
DE_Clock_Generator_System.port_clk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clk5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena4 = "PORT_UNUSED",
DE_Clock_Generator_System.port_clkena5 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_enable1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclk3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena1 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena2 = "PORT_UNUSED",
DE_Clock_Generator_System.port_extclkena3 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout0 = "PORT_UNUSED",
DE_Clock_Generator_System.port_sclkout1 = "PORT_UNUSED",
DE_Clock_Generator_System.valid_lock_multiplier = 1;
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* Testbench for creating a string of random numbers and storing
* them into a file named "testfile.bit"
*/
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_acs();
// Declare integers
// Counter for the FOR loop enumeration
integer count;
// Multichannel descriptor for associated file that is opened
integer md_fopen;
// Randomly generated input data bit for the transmitter
reg [0:24] data;
// Declare constants
// Maximum number of data bits in the stream
parameter max_amt_of_data = 9'd255;
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
/**
* $display automatically adds a newline character to
* the end of its output, whereas the $write task does not.
*
* Any null parameter produces a single space character
* in the display. (A null parameter is characterized by
* two adjacent commas in the parameter list.)
*
*
*/
// Open a file channel descriptor for writing
md_fopen=$fopen("rf.fill");
/**
* Assert that the file can be opened for read/write
* operations; else, end the simulation/execution
*/
if (md_fopen == 0) $finish;
// Write a stream of 256 bits to the output file
for(count=0; count<max_amt_of_data; count=count+1)
begin
/**
* Assign the input data bit to a randomly
* generated number
*/
data = $random;
//$fwrite(md_fopen,data);
$fdisplay(md_fopen,data);
end
/**
* Assign the last input data bit to a randomly
* generated number
*/
data = $random;
$fdisplay(md_fopen,data);
// Close a file channel descriptor for writing
$fclose(md_fopen);
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, s; cin >> n >> s; long long int min = INT_MAX; unsigned long long int sum = 0; long long int i; long long int arr[n]; for (i = 0; i < n; i++) { cin >> arr[i]; sum += arr[i]; if (arr[i] < min) min = arr[i]; } if (sum < s) { cout << -1 ; return 0; } if (sum == s) { cout << 0 ; return 0; } long long int count = 0; for (i = 0; i < n; i++) { if (arr[i] > min) count++; } for (i = 0; i < n; i++) { if (count <= 0) break; if (arr[i] > min) { count -= 1; if (s - (arr[i] - min) <= 0) { cout << min; return 0; } s = s - (arr[i] - min); arr[i] = min; } } while (s != 0 && min >= 0) { if (s - (n) <= 0) { cout << (min - 1); return 0; } else { min--; s = s - n; } } cout << -1 ; return 0; } |
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 18220 $
// $Date: 2009-10-27 15:19:11 +0000 (Tue, 27 Oct 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Single-Ported BRAM
module BRAM1(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [ADDR_WIDTH-1:0] ADDR_R;
reg [DATA_WIDTH-1:0] DO_R;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
ADDR_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } };
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLK) begin
if (EN) begin
if (WE)
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DI;
ADDR_R <= `BSV_ASSIGNMENT_DELAY ADDR;
end
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR_R];
end
assign DO = (PIPELINED) ? DO_R : RAM[ADDR_R];
endmodule // BRAM1
|
#include <bits/stdc++.h> using namespace std; int ans[110000], add[110000]; int n, m, a, cnt, me; char temp[3]; int main() { while (~scanf( %d%d , &n, &m)) { for (int i = 1; i <= n; i++) ans[i] = 1, add[i] = 0; ; cnt = 0; me = 0; for (int i = 1; i <= m; i++) { scanf( %s%d , temp, &a); if (*temp == + ) { if (!me || (me == a)) me = a; else ans[a] = 0; add[a] = 1; if (a != me && !add[me]) ans[me] = 0; cnt++; } else { if (!me) me = a; if (a != me && add[a] == 0) { ans[me] = 0; me = a; } if (add[a]) { add[a] = 0; cnt--; } if (cnt) ans[a] = 0; } } int tt = 0; bool fi = true; for (int i = 1; i <= n; i++) if (ans[i]) tt++; printf( %d n , tt); for (int i = 1; i <= n; i++) { if (ans[i]) { if (!fi) printf( ); printf( %d , i); if (fi) fi = false; } } printf( n ); } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:67108864 ) const int MOD = 1000000007; const long long INF = 3000000000000000001; const double EPS = 1e-6; const int HASH_POW = 29; const double PI = acos(-1.0); using namespace std; double workTime() { return double(clock()) / CLOCKS_PER_SEC; } void my_return(int code) { exit(code); } int cnt[1000000]; void add(string s) { reverse(s.begin(), s.end()); int len = s.length(); int ptr = 0; for (int i = 0; i < 18; ++i) { int bit; if (i < len) bit = (s[i] - 0 ) % 2; else bit = 0; ptr += bit * (1 << i); } ++cnt[ptr]; } void destroy(string s) { reverse(s.begin(), s.end()); int len = s.length(); int ptr = 0; for (int i = 0; i < 18; ++i) { int bit; if (i < len) bit = (s[i] - 0 ) % 2; else bit = 0; ptr += bit * (1 << i); } --cnt[ptr]; } int count(string s) { reverse(s.begin(), s.end()); int len = s.length(); int ptr = 0; for (int i = 0; i < 18; ++i) { int bit; if (i < len) bit = (s[i] - 0 ) % 2; else bit = 0; ptr += bit * (1 << i); } return cnt[ptr]; } int main() { cin.sync_with_stdio(0); cin.tie(0); mt19937 mt_rand(time(0)); int q; cin >> q; while (q--) { char c; string v; cin >> c >> v; if (c == + ) add(v); else if (c == - ) destroy(v); else if (c == ? ) cout << count(v) << endl; else return 1; } my_return(0); } |
#include <bits/stdc++.h> using namespace std; int arr[500010]; int d1[500010]; int d2[500010]; int main() { int n; cin >> n; for (int i = (0); i < (int)(n); i++) cin >> arr[i]; int last2left = 0; for (int i = (1); i < (int)(n - 1); i++) { if (arr[i] == arr[i - 1]) { last2left = i; d1[i] = i; } else { d1[i] = last2left; } } last2left = n - 1; for (int i = (n - 1 - 1); i >= (int)(1); i--) { if (arr[i] == arr[i + 1]) { last2left = i; d2[i] = i; } else { d2[i] = last2left; } } int res = 0; for (int i = (1); i < (int)(n - 1); i++) res = max(res, min(i - d1[i], d2[i] - i)); cout << res << endl; cout << arr[0] << ; for (int i = (1); i < (int)(n - 1); i++) cout << ((i - d1[i] < d2[i] - i) ? arr[d1[i]] : arr[d2[i]]) << ; cout << arr[n - 1] << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 151; int m, n; char gd[N][N]; inline int fab(int x) { return x > 0 ? x : -x; } int main() { while (scanf( %d%d , &m, &n) != -1) { for (int i = 0; i < m; i++) scanf( %s , gd[i]); int ans = 0, x = 0, y = 0; for (int i = 0; i < m; i++) for (int j = (i & 1 ? n - 1 : 0); 0 <= j && j < n; j += (i & 1 ? -1 : 1)) if (gd[i][j] == W ) { ans += fab(i - x) + fab(j - y); x = i; y = j; } printf( %d n , ans); } return 0; } |
`default_nettype none
`timescale 1ns / 1ps
module sia_rxq_tb();
reg [15:0] story;
reg clk_i = 0, reset_i = 0;
reg rxd_i = 1, rxc_i = 0;
reg rxq_pop_i = 0;
reg rxq_oe_i = 0;
wire [11:0] rxq_dat_o;
wire rxq_full_o, rxq_not_empty_o;
sia_rxq #(
.SHIFT_REG_WIDTH(12),
.BAUD_RATE_WIDTH(32),
.DEPTH_BITS(2),
.DATA_BITS(12)
) x(
.clk_i(clk_i),
.reset_i(reset_i),
.bits_i(5'd10), // 8N1
.baud_i(32'd49), // 1Mbps when clocked at 50MHz.
.eedd_i(1'b1),
.eedc_i(1'b1),
.rxcpol_i(1'b0),
.rxd_i(rxd_i),
.rxc_i(rxc_i),
.rxq_pop_i(rxq_pop_i),
.rxq_oe_i(rxq_oe_i),
.rxq_dat_o(rxq_dat_o),
.rxq_full_o(rxq_full_o),
.rxq_not_empty_o(rxq_not_empty_o)
);
always begin
#10 clk_i <= ~clk_i;
end
task assert_queue_not_empty;
input expected;
begin
if (expected !== rxq_not_empty_o) begin
$display("@E %d rxq_not_empty_o Expected %d; got %d", story, expected, rxq_not_empty_o);
$stop;
end
end
endtask
task assert_queue_full;
input expected;
begin
if (expected !== rxq_full_o) begin
$display("@E %d rxq_full_o Expected %d; got %d", story, expected, rxq_full_o);
$stop;
end
end
endtask
task assert_dat;
input [11:0] expected;
begin
if (expected !== rxq_dat_o) begin
$display("@E %d rxq_dat_o Expected %012B; got %012B", story, expected, rxq_dat_o);
$stop;
end
end
endtask
initial begin
$dumpfile("sia_rxq.vcd");
$dumpvars;
story <= 1;
reset_i <= 1;
wait(clk_i); wait(~clk_i);
reset_i <= 0;
rxq_pop_i <= 1;
wait(clk_i); wait(~clk_i);
wait(clk_i); wait(~clk_i);
wait(clk_i); wait(~clk_i);
wait(clk_i); wait(~clk_i);
rxq_pop_i <= 0;
assert_dat(12'h000);
assert_queue_not_empty(0);
assert_queue_full(0);
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
assert_queue_not_empty(1);
assert_queue_full(0);
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
assert_queue_not_empty(1);
assert_queue_full(0);
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
assert_queue_not_empty(1);
assert_queue_full(0);
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
assert_queue_not_empty(1);
assert_queue_full(1);
story <= 2;
rxq_oe_i <= 1;
wait(clk_i); wait(~clk_i);
assert_dat(12'b1_10000101_0_11);
assert_queue_not_empty(1);
assert_queue_full(1);
wait(clk_i); wait(~clk_i);
assert_dat(12'b1_10000101_0_11);
assert_queue_not_empty(1);
assert_queue_full(1);
rxq_pop_i <= 1;
wait(clk_i); wait(~clk_i);
assert_dat(12'b1_10100001_0_11);
assert_queue_not_empty(1);
assert_queue_full(0);
wait(clk_i); wait(~clk_i);
assert_dat(12'b1_10000101_0_11);
assert_queue_not_empty(1);
assert_queue_full(0);
wait(clk_i); wait(~clk_i);
assert_dat(12'b1_10100001_0_11);
assert_queue_not_empty(1);
assert_queue_full(0);
wait(clk_i); wait(~clk_i);
assert_dat(12'b1_10000101_0_11); // Data read ptr wraps around to beginning
assert_queue_not_empty(0);
assert_queue_full(0);
wait(clk_i); wait(~clk_i);
assert_dat(12'b1_10000101_0_11); // ... and stays there when empty.
assert_queue_not_empty(0);
assert_queue_full(0);
$display("@I Done.");
$stop;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O22AI_FUNCTIONAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22AI_FUNCTIONAL_PP_V |
/*
Filename : IF.v
Compiler : Quartus II
Description : PC to PC register
INPUT : clk, rst, EN : all active high
PCIn : 32bits Register
OUTPUT : PCIn : 32bits Register
Author : Yeoman Zhuang
Release : *
*/
module IF(
input clk, rst, flush,
input [31:0] PC_In,
input [2:0] PCSrc,
input PCWrite,
Branch,
input [31:0] ConBA,
DataBusA,
input [25:0] JT,
output reg [31:0] PC_Out
);
always @(posedge clk or posedge rst) begin
if (rst) begin
PC_Out <= 0;
end else if(flush)
PC_Out <= {PC_Out[31], {31{1'b0}}};
else if (PCWrite) begin
if(Branch) begin
PC_Out <= ConBA;
end else case (PCSrc) //谁的PCSrc？
3'h0: PC_Out <= PC_In+32'h4; //PC_In = PC
3'h1: PC_Out <= PC_In+32'h4;
3'h2: PC_Out <= {PC_In[31:28], JT, 2'b0};
3'h3: PC_Out <= DataBusA; // jr jalr $Ra
3'h4: PC_Out <= 32'h8000_0004; // ILLOP
3'h5: PC_Out <= 32'h8000_0008; // XADR
default: PC_Out <= 32'h8000_0008;
endcase
end else
PC_Out <= PC_Out;
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module mult_16x16 (
input wire [15:0] A,
input wire [15:0] B,
output wire [31:0] Z
);
assign Z = A * B;
endmodule
module mult_20x18 (
input wire [19:0] A,
input wire [17:0] B,
output wire [37:0] Z
);
assign Z = A * B;
endmodule
module mult_8x8 (
input wire [ 7:0] A,
input wire [ 7:0] B,
output wire [15:0] Z
);
assign Z = A * B;
endmodule
module mult_10x9 (
input wire [ 9:0] A,
input wire [ 8:0] B,
output wire [18:0] Z
);
assign Z = A * B;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long int> a[100004]; int p[100004]; int v[100004]; long long int c[100004]; struct sajal { long long int add, sub, d; }; sajal d[100004]; int main() { long n; cin >> n; long x, y; for (long i = 1; i < n; i++) { cin >> x >> y; a[x].push_back(y); a[y].push_back(x); } queue<long> q; q.push(1); p[1] = 1; while (!q.empty()) { long f = q.front(); q.pop(); v[f] = 1; for (long i = 0; i < a[f].size(); i++) { if (v[a[f][i]] == 0) { v[a[f][i]] = 1; q.push(a[f][i]); p[a[f][i]] = f; } } } for (long i = 1; i <= n; i++) { cin >> c[i]; d[i].add = 0; d[i].sub = 0; d[i].d = a[i].size(); if (a[i].size() == 1 && i != 1) { q.push(i); } } long long int add = 0; long long int sub = 0; long cur = 1; while (!q.empty()) { long f = q.front(); q.pop(); long long int e = d[f].add - d[f].sub; long long int h = -c[f] - e; long long int w = p[f]; if (h >= 0) { d[f].add = d[f].add + h; } else { h = -h; d[f].sub = h + d[f].sub; } if (d[f].sub > sub) sub = d[f].sub; if (d[f].add > add) add = d[f].add; if (d[w].sub < d[f].sub) d[w].sub = d[f].sub; if (d[w].add < d[f].add) d[w].add = d[f].add; d[w].d--; if (d[w].d == 1 && w != 1) { q.push(w); } } c[1] = c[1] + d[1].add - d[1].sub; c[1] = -c[1]; if (c[1] >= 0) { d[1].add = d[1].add + c[1]; } else { c[1] = -c[1]; d[1].sub = d[1].sub + c[1]; } if (add < d[1].add) add = d[1].add; if (sub < d[1].sub) sub = d[1].sub; cout << add + sub << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__EDFXBP_FUNCTIONAL_PP_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXBP_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long mul(long long a, long long b) { return (a * b) % 1000000007; } long long add(long long a, long long b) { a += b; if (a >= 1000000007) a -= 1000000007; return a; } long long binary_expo(long long base, long long expo) { long long res = 1; while (expo) { if (expo % 2) { res = mul(res, base); } expo /= 2; base = mul(base, base); } return res; } void solve() { long long n; cin >> n; cout << n << n ; for (long long i = 1; i <= n; i++) { cout << 1 ; } cout << n ; } signed main() { long long t; ios_base::sync_with_stdio(false); t = 1; while (t--) { solve(); } } |
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_0_clk_wiz
(// Clock in ports
input clk_in1,
// Clock out ports
output clk_out1,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (clk_in1_clk_wiz_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.125),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (9.375),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clk_wiz_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_clk_wiz_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clk_wiz_0),
.CLKIN1 (clk_in1_clk_wiz_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clk_wiz_0),
.I (clkfbout_clk_wiz_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_clk_wiz_0));
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:100000000 ) using namespace std; long long x[3], y[3]; int main() { for (int i = 0; i < 3; i++) cin >> x[i] >> y[i]; if (x[0] == x[1] && x[0] == x[2] || y[0] == y[1] && y[0] == y[2]) { printf( 1 n ); return 0; } int perm[3] = {0, 1, 2}; long long minx = min(x[0], min(x[1], x[2])); long long maxx = max(x[0], max(x[1], x[2])); long long miny = min(y[0], min(y[1], y[2])); long long maxy = max(y[0], max(y[1], y[2])); do { long long x1 = x[perm[0]], y1 = y[perm[0]]; long long x2 = x[perm[1]], y2 = y[perm[1]]; long long x3 = x[perm[2]], y3 = y[perm[2]]; bool gr1 = false; bool gr2 = false; bool gr3 = false; if ((x1 == minx || x1 == maxx) && (y1 == miny || y1 == maxy)) gr1 = true; if ((x2 == minx || x2 == maxx) && (y2 == miny || y2 == maxy)) gr2 = true; if ((x3 == minx || x3 == maxx) && (y3 == miny || y3 == maxy)) gr3 = true; if (gr1 && gr2 && gr3) { printf( 2 ); return 0; } if ((x1 == x2 || y1 == y2) && gr1 && gr3 && !gr2) { printf( 2 ); return 0; } } while (next_permutation(perm, perm + 3)); printf( 3 ); return 0; } |
module npu_core
(
input CLK,
input RESET_X,
input SOFT_RESET,
input [1:0] OP,
input INV_ASEL,
input INV_BSEL,
input INPUT_EN,
input [7:0] A_IN,
input [7:0] B_IN,
output reg OUTPUT_EN,
output reg [7:0] C_OUT,
//ADD
input [31:0] AD_GAIN,
input [31:0] AD_QPARAM,
//MULL CORE
input [31:0] MLC_GAGB,
input [31:0] MLC_GAOB,
input [31:0] MLC_GBOA,
// MULL ADD1
input [31:0] ML1_GAIN,
input [31:0] ML1_QPARAM,
input [31:0] ML2_GAIN,
input [31:0] ML2_QPARAM,
input [7:0] REQ_MID,
input [31:0] REQ_GAIN,
output reg [15:0] RMAX,
output reg [15:0] RMIN
);
wire rst_x;
assign rst_x = RESET_X & ~SOFT_RESET;
wire op_add_sel, op_mul_sel, op_rqt_sel;
wire input_en_add, input_en_mul, input_en_rqt;
wire output_en_add, output_en_mul, output_en_rqt;
wire [7:0] c_out_add, c_out_mul, c_out_rqt;
wire [15:0] rmax_add, rmax_mul, rmax_rqt;
wire [15:0] rmin_add, rmin_mul, rmin_rqt;
reg input_en_1t;
// for add
reg [7:0] a_in_r;
reg [7:0] b_in_r;
wire [7:0] a_in_inv;
wire [7:0] b_in_inv;
// for mul
reg [7:0] a_in_mul;
reg [7:0] b_in_mul;
reg [7:0] a_in_mul_inv;
reg [7:0] b_in_mul_inv;
assign op_add_sel = (OP == 2'b00);
assign op_mul_sel = (OP == 2'b01);
assign op_rqt_sel = (OP == 2'b10);
assign input_en_add = input_en_1t & op_add_sel;
assign input_en_mul = input_en_1t & op_mul_sel;
assign input_en_rqt = input_en_1t & op_rqt_sel;
// invert input
q_inv8 inv_a(.A(A_IN), .B(a_in_inv));
q_inv8 inv_b(.A(B_IN), .B(b_in_inv));
// for add
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0) begin
a_in_r <= 8'h00;
end else begin
if (INV_ASEL == 1) begin
a_in_r <= a_in_inv;
end else begin
a_in_r <= A_IN;
end
end
end // always @ (posedge CLK or negedge rst_x)
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0) begin
b_in_r <= 8'h00;
end else begin
if (INV_BSEL == 1) begin
b_in_r <= b_in_inv;
end else begin
b_in_r <= B_IN;
end
end
end // always @ (posedge CLK or negedge rst_x)
// for mul
always @ (posedge CLK or negedge rst_x)begin
if (rst_x == 0) begin
a_in_mul <= 8'h00;
b_in_mul <= 8'h00;
a_in_mul_inv <= 8'h00;
b_in_mul_inv <= 8'h00;
end else begin
a_in_mul <= A_IN;
b_in_mul <= B_IN;
a_in_mul_inv <= a_in_inv;
b_in_mul_inv <= b_in_inv;
end
end
q_add8 q_add8
(
.CLK(CLK),
.RESET_X(rst_x),
.INPUT_EN(input_en_1t),
.A_IN(a_in_r),
.B_IN(b_in_r),
.OUTPUT_EN(output_en_add),
.C_OUT(c_out_add),
.GAIN(AD_GAIN),
.Q_PARAM(AD_QPARAM),
.MIN(rmax_add),
.MAX(rmin_add)
);
q_mul8 q_mul8
(
.CLK(CLK),
.RESET_X(RESET_X),
.INPUT_EN(input_en_1t),
.A_IN(a_in_mul),
.B_IN(b_in_mul),
.A_IN_INV(a_in_mul_inv),
.B_IN_INV(b_in_mul_inv),
.A_SEL_INV(INV_ASEL),
.B_SEL_INV(INV_BSEL),
.OUTPUT_EN(output_en_mul),
.C_OUT(c_out_mul),
.MLC_GAGB(MLC_GAGB),
.ML1_GAIN(ML1_GAIN),
.ML1_QPARAM(ML1_QPARAM),
.ML2_GAIN(ML2_GAIN),
.ML2_QPARAM(ML2_QPARAM),
.MIN(rmin_mul),
.MAX(rmax_mul)
);
//outut sel
always @ (posedge CLK or negedge rst_x) begin
if (rst_x == 0) begin
OUTPUT_EN <= 0;
C_OUT <= 8'h00;
RMAX <= 16'h0000;
RMIN <= 16'h0000;
end else begin
if (op_add_sel == 1) begin
OUTPUT_EN <= output_en_add;
C_OUT <= c_out_add;
RMAX <= rmax_add;
RMIN <= rmin_add;
end else if(op_mul_sel == 1) begin
OUTPUT_EN <= output_en_mul;
C_OUT <= c_out_mul;
RMAX <= rmax_mul;
RMIN <= rmin_mul;
end else if (op_rqt_sel == 1) begin
OUTPUT_EN <= output_en_rqt;
C_OUT <= c_out_rqt;
RMAX <= rmax_rqt;
RMIN <= rmin_rqt;
end else begin
OUTPUT_EN <= 0;
C_OUT <= 8'h00;
end
end // else: !if(rst_x == 0)
end // always @ (posedge CLK or negedge rst_x)
//delay
always @ (posedge CLK or negedge rst_x) begin
if (rst_x == 0) begin
input_en_1t <= 0;
end else begin
input_en_1t <= INPUT_EN;
end
end
//dummy
assign output_en_rqt = 0;
assign c_out_rqt = 0;
assign rmax_rqt = 0;
assign rmin_rqt = 0;
endmodule // npu_core
|
#include <bits/stdc++.h> using namespace std; const int maxN = 1e5; int n; char ans[maxN + 1]; string s; int main() { ios_base::sync_with_stdio(false); cin >> n; cin.ignore(); for (int i = 0; i < n; i++) { getline(cin, s); for (int j = 0; j < s.length(); j++) { if (ans[j] == 0) ans[j] = ? ; if (s[j] == ? || ans[j] == X ) continue; if (ans[j] == ? && s[j] != ? ) ans[j] = s[j]; else if (ans[j] != ? && s[j] != ? && ans[j] != s[j]) ans[j] = X ; } } for (int i = 0; i < s.length(); i++) { if (ans[i] == X ) ans[i] = ? ; else if (ans[i] == ? ) ans[i] = a ; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int a[] = {0, 4, 22, 27, 58, 85, 94, 121, 166, 202, 265, 274, 319, 346, 355, 378, 382, 391, 438, 454, 483, 517, 526, 535, 562, 576, 588, 627, 634, 636, 645, 648, 654, 663, 666, 690}; int main() { int n; cin >> n; cout << a[n] << n ; return 0; } |
module multiplier_test();
reg clk, sign, enable;
reg [31:0] multi_1, multi_2;
wire [63:0] product;
wire multready;
// instantiate device to be tested
multiplier DUT(clk, sign, enable, multi_1, multi_2, product, multready);
// generate clock to sequence tests
always begin
clk <= 1;
#5;
clk <= 0;
# 5;
end
// check results
initial begin
// Initialize
multi_1 <= 32'b0;
multi_2 <= 32'b0;
enable <= 1'b0;
sign <= 1'b0;
clk <= 1'b0;
// Test Cases
enable <= 1'b0;
#10;
enable <= 1'b1;
multi_1 <= 32'd3;
multi_2 <= 32'd2;
sign <= 1'b0;
#320;
// pos * zero
enable <= 1'b0;
#10;
enable <= 1'b1;
multi_1 <= 32'd0;
multi_2 <= 32'd80;
sign <= 1'b1;
#320;
// neg * zero
enable <= 1'b0;
#10;
enable <= 1'b1;
multi_1 <= 32'hffffffff;
multi_2 <= 32'd0;
sign <= 1'b1;
#320;
// neg * pos
enable <= 1'b0;
#10;
enable <= 1'b1;
multi_1 <= 32'hfffffff8;
multi_2 <= 32'd2;
sign <= 1'b1;
#320;
// pos * neg
enable <= 1'b0;
#10;
enable <= 1'b1;
multi_2 <= 32'hfffffff8;
multi_1 <= 32'd2;
sign <= 1'b1;
#320;
// neg * neg
enable <= 1'b0;
#10;
enable <= 1'b1;
multi_2 <= 32'hfffffff8;
multi_1 <= 32'hfffffff2;
sign <= 1'b1;
#320;
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file ROM01.v when simulating
// the core, ROM01. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module ROM01(
clka,
ena,
addra,
douta
);
input clka;
input ena;
input [7 : 0] addra;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("ROM01.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// $Id: vcr_ovc_ctrl.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// output port controller (tracks state of buffers in downstream router)
//==============================================================================
module vcr_ovc_ctrl
(clk, reset, vc_active, vc_gnt, vc_sel_ip, vc_sel_ivc, sw_active, sw_gnt,
sw_sel_ip, sw_sel_ivc, flit_valid, flit_tail, flit_sel, elig, full,
full_prev, empty);
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
// number of VCs
parameter num_vcs = 4;
// number of input and output ports on router
parameter num_ports = 5;
// enable speculative switch allocation
parameter sw_alloc_spec = 1;
// select whether to exclude full or non-empty VCs from VC allocation
parameter elig_mask = `ELIG_MASK_NONE;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// activity indicator for VC allocation
input vc_active;
// output VC was granted to an input VC
input vc_gnt;
// input port that the output VC was granted to
input [0:num_ports-1] vc_sel_ip;
// input VC that the output VC was granted to
input [0:num_vcs-1] vc_sel_ivc;
// activity indicator for switch allocation
input sw_active;
// switch allocator grant
input sw_gnt;
// which input port does the incoming flit come from?
input [0:num_ports-1] sw_sel_ip;
// which input VC does the incoming flit belong to?
input [0:num_vcs-1] sw_sel_ivc;
// incoming flit is valid
input flit_valid;
// incoming flit is a tail flit
input flit_tail;
// output VC is the owner of the incoming flit
output flit_sel;
wire flit_sel;
// output VC is eligible for allocation (i.e., not currently allocated)
output elig;
wire elig;
// VC has no credits left
input full;
// ignoring the current flit, VC has no credits left
input full_prev;
// VC is empty
input empty;
//---------------------------------------------------------------------------
// track whether this output VC is currently assigend to an input VC
//---------------------------------------------------------------------------
wire alloc_active;
assign alloc_active = vc_active | flit_valid;
wire allocated;
wire allocated_s, allocated_q;
assign allocated_s = vc_gnt | allocated;
c_dff
#(.width(1),
.reset_type(reset_type))
allocatedq
(.clk(clk),
.reset(reset),
.active(alloc_active),
.d(allocated_s),
.q(allocated_q));
assign allocated = allocated_q & ~(flit_valid & flit_sel & flit_tail);
wire [0:num_ports-1] allocated_ip_s, allocated_ip_q;
assign allocated_ip_s = allocated ? allocated_ip_q : vc_sel_ip;
c_dff
#(.width(num_ports),
.reset_type(reset_type))
allocated_ipq
(.clk(clk),
.reset(1'b0),
.active(vc_active),
.d(allocated_ip_s),
.q(allocated_ip_q));
wire port_match;
wire vc_match;
generate
if(sw_alloc_spec)
assign port_match = |(sw_sel_ip & allocated_ip_s);
else
assign port_match = |(sw_sel_ip & allocated_ip_q);
if(num_vcs == 1)
assign vc_match = 1'b1;
else if(num_vcs > 1)
begin
wire [0:num_vcs-1] allocated_ivc_s, allocated_ivc_q;
assign allocated_ivc_s = allocated ? allocated_ivc_q : vc_sel_ivc;
c_dff
#(.width(num_vcs),
.reset_type(reset_type))
allocated_ivcq
(.clk(clk),
.reset(1'b0),
.active(vc_active),
.d(allocated_ivc_s),
.q(allocated_ivc_q));
if(sw_alloc_spec)
assign vc_match = |(sw_sel_ivc & allocated_ivc_s);
else
assign vc_match = |(sw_sel_ivc & allocated_ivc_q);
end
endgenerate
wire match_s, match_q;
assign match_s = sw_gnt ? (port_match & vc_match) : match_q;
c_dff
#(.width(1),
.reset_type(reset_type))
matchq
(.clk(clk),
.reset(reset),
.active(sw_active),
.d(match_s),
.q(match_q));
generate
if(sw_alloc_spec && (elig_mask == `ELIG_MASK_NONE))
assign flit_sel = allocated_q & match_q & ~full_prev;
else
assign flit_sel = allocated_q & match_q;
endgenerate
//---------------------------------------------------------------------------
// keep track of whether current VC is available for allocation
//---------------------------------------------------------------------------
generate
case(elig_mask)
`ELIG_MASK_NONE:
begin
assign elig = ~allocated;
end
`ELIG_MASK_FULL:
begin
assign elig = ~allocated & ~full;
end
`ELIG_MASK_USED:
begin
assign elig = ~allocated & empty;
end
endcase
endgenerate
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_jbi_sc1_2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ff_jbi_sc1_2(/*AUTOARG*/
// Outputs
jbi_sctag_req_d1, scbuf_jbi_data_d1, jbi_scbuf_ecc_d1,
jbi_sctag_req_vld_d1, scbuf_jbi_ctag_vld_d1, scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1, sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1, so,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req, rclk, si, se
);
output [31:0] jbi_sctag_req_d1;
output [31:0] scbuf_jbi_data_d1;
output [6:0] jbi_scbuf_ecc_d1;
output jbi_sctag_req_vld_d1;
output scbuf_jbi_ctag_vld_d1;
output scbuf_jbi_ue_err_d1;
output sctag_jbi_iq_dequeue_d1;
output sctag_jbi_wib_dequeue_d1;
output sctag_jbi_por_req_d1;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
input rclk;
input si, se;
output so;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
dff_s #(32) ff_flop_row0 (.q(jbi_sctag_req_d1[31:0]),
.din(jbi_sctag_req[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_flop_row1 (.q(scbuf_jbi_data_d1[31:0]),
.din(scbuf_jbi_data[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(13) ff_flop_row2 (.q({ jbi_scbuf_ecc_d1[6:0],
jbi_sctag_req_vld_d1,
scbuf_jbi_ctag_vld_d1,
scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1,
sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1}),
.din({ jbi_scbuf_ecc[6:0],
jbi_sctag_req_vld,
scbuf_jbi_ctag_vld,
scbuf_jbi_ue_err,
sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue,
sctag_jbi_por_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
#include <bits/stdc++.h> using namespace std; long n, ps[1000], tp, q, ar[1000], ans, x, y, a, b; int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> ar[i]; ps[ar[i]] = i; } cin >> q; for (; q; --q) { cin >> tp; if (tp == 2) { cin >> a >> b; swap(ar[a], ar[b]); ps[ar[a]] = a; ps[ar[b]] = b; } else { cin >> x >> y; ans = 1; while (x < y) { if (ps[x + 1] < ps[x]) ++ans; ++x; } cout << ans << endl; } } cin.get(); cin.get(); return 0; } |
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : cabac_mvd_neigh_2p_18x8.v
// Author : guo yong
// Created : 2013-07
// Description : cabac memory for left macroblock mvd
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module cabac_mvd_left_2p_18x4(
//input
clk ,
r_en ,
r_addr ,
w_en ,
w_addr ,
w_data ,
//output
r_data
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk ; //clock signal
input r_en ; //read enable signal
input [1:0] r_addr ; //read address of memory
input w_en ; //write enable signal
input [1:0] w_addr ; //write address of memory
input [2*(`FMV_WIDTH+1)-1:0] w_data ; //write data of memory, {mb_type_top, chroma_mode_top, cbp_top} = {4, 4, 9}
output [2*(`FMV_WIDTH+1)-1:0] r_data ; //read data from memory
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
rf_2p #(.Addr_Width(2), .Word_Width(18))
rf_2p_mvd_left_18x4 (
.clka ( clk ),
.cena_i ( ~r_en ),
.addra_i ( r_addr ),
.dataa_o ( r_data ),
.clkb ( clk ),
.cenb_i ( ~w_en ),
.wenb_i ( ~w_en ),
.addrb_i ( w_addr ),
.datab_i ( w_data )
);
endmodule
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG
`define TEST_PROG "firmware.hex"
`include "top.v"
module top_test;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 12;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
reg [WIDTH-1 : 0] expected_output [OUTPUT_CNT-1 : 0];
wire uart_tx;
reg [WIDTH-1 : 0] i, j, k, l;
initial begin
j = 1;
k = 1;
l = 0;
for (i = 0; i < OUTPUT_CNT; i = i + 1) begin
expected_output[i] = k;
l = k;
k = k + j;
j = l;
end
i = 0;
end
always #2 clk = !clk;
always #8 uart_clk = !uart_clk; //For sim. UART TX clock gets divided by 4
top t(
.clk(clk),
.uart_tx_line(uart_tx));
initial begin
$dumpfile("top_test.vcd");
$dumpvars;
end
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1 ) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (i >= OUTPUT_CNT) begin
$display("Fibonacci test passed, computed results match the expected output!\n");
$finish;
end
if (serial_data != expected_output[i]) begin
$display("Fibonacci test failed!\n");
$display("Serial output:%d doesn't match expected_output[%d]:%d\n",
serial_data, i, expected_output[i]);
$finish;
end
i <= i + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222OI_1_V
`define SKY130_FD_SC_HS__A222OI_1_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog wrapper for a222oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a222oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a222oi_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a222oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a222oi_1 (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a222oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222OI_1_V
|
// psi2c.v
module psi2c
(
// avalon clock interface
input csi_clock_clk,
input csi_clock_reset,
// avalon mm slave
input [2:0]avs_ctrl_address,
input avs_ctrl_read,
output [31:0]avs_ctrl_readdata,
input avs_ctrl_write,
input [31:0]avs_ctrl_writedata,
// conduit
input sync,
input phase,
output send,
output sda,
input rda
);
wire go;
wire empty;
wire [11:0] dout;
wire [11:0] din;
wire full;
wire [31:0]rda_data;
wire wr;
psi2c_bitsend bitsend(
.clk(csi_clock_clk),
.reset(csi_clock_reset),
.sync(sync),
.go(go),
.empty(empty),
.phase(phase),
.d(dout),
.rd(rd),
.busy(send),
.sda(sda)
);
psi2c_readback readback
(
.go(tbm & go),
.clk(csi_clock_clk),
.reset(csi_clock_reset),
.sync(sync),
.sync2(phase),
.rda(rda),
.i2c_send(send),
.d(rda_data)
);
i2c_control control
(
.clk(csi_clock_clk),
.reset(csi_clock_reset),
.busy(send),
.write(avs_ctrl_write),
.read(avs_ctrl_read),
.full(full),
.address(avs_ctrl_address),
.rda(rda_data),
.writedata(avs_ctrl_writedata),
.memw(wr),
.go(go),
.tbm(tbm),
.memd(din),
.readdata(avs_ctrl_readdata)
);
psi2c_fifo fifo
(
.clock (csi_clock_clk),
.aclr (csi_clock_reset),
.data (din),
.rdreq (rd),
.wrreq (wr),
.empty (empty),
.full (full),
.q (dout)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/25 23:12:16
// Design Name:
// Module Name: decoder_74138_dataflow_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decoder_74138_dataflow_tb(
);
reg [2:0] x;
reg g1, g2a_n, g2b_n;
wire [7:0] y;
integer k;
decoder_74138_dataflow DUT (.g1(g1), .g2a_n(g2a_n), .g2b_n(g2b_n), .x(x), .y(y));
initial
begin
x = 0; g1 = 0; g2a_n = 1; g2b_n = 1;
for (k=0; k < 8; k=k+1)
#5 x=k;
#10;
x = 0; g1 = 1; g2a_n = 0; g2b_n = 1;
for (k=0; k < 8; k=k+1)
#5 x=k;
#10;
x = 0; g1 = 0; g2a_n = 1; g2b_n = 0;
for (k=0; k < 8; k=k+1)
#5 x=k;
#10;
x = 0; g1 = 1; g2a_n = 0; g2b_n = 0;
for (k=0; k < 8; k=k+1)
#5 x=k;
#10;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : qdr_rld_phy_cntrl_init.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:36:29 $
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7 Series
//Design : QDRII+ SRAM / RLDRAM II SDRAM
//Purpose : write to phy_control block and handle write_enable
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_qdr_rld_phy_cntrl_init #
(
parameter PRE_FIFO = "TRUE",
parameter MEM_TYPE = "QDR2",
parameter TCQ = 100 //Register Delay
)
(
input clk,
input rst,
input phy_ctl_ready,
input phy_ctl_full,
input phy_ctl_a_full,
input of_ctl_full,
input of_data_full,
input [5:0] phy_ctl_data_offset,
input [2:0] phy_ctl_cmd,
output wire [31:0] phy_ctl_wd,
output reg phy_ctl_wr,
output wire io_fifo_rden_cal_done,
(* KEEP = "TRUE" *) output reg of_cmd_wr_en /* synthesis syn_keep = 1 */,
(* KEEP = "TRUE" *) output reg of_data_wr_en /* synthesis syn_keep = 1 */
);
localparam [4:0] IDLE = 5'b00000;
localparam [4:0] STALL_CMD = 5'b00001;
localparam [4:0] CONT_CMD = 5'b00010;
localparam [4:0] CMD_WAIT1 = 5'b00100;
localparam [4:0] CMD_WAIT2 = 5'b01000;
localparam [4:0] CONT_CMD2 = 5'b10000;
reg [4:0] pc_cntr_cmd;
reg [4:0] pc_command_offset;
reg [5:0] pc_data_offset;
reg [1:0] pc_seq;
reg [2:0] pc_cmd;
reg [4:0] pc_ctl_ns;
reg io_fifo_rden_cal_done_r;
wire early_io_fifo_rden_cal_done;
assign io_fifo_rden_cal_done = (PRE_FIFO == "TRUE")? io_fifo_rden_cal_done_r : 1'b1;
assign phy_ctl_wd = {1'b0, 1'b1, pc_cntr_cmd[4:0], pc_seq[1:0],
pc_data_offset[5:0], 2'b00, 3'b000,
4'b0000, pc_command_offset[4:0], pc_cmd[2:0]};
always @ (posedge clk) begin
if (rst)
pc_seq <= #TCQ 'b0;
else if (phy_ctl_wr)
pc_seq <= #TCQ pc_seq + 1;
end
always @ (posedge clk) begin
if (rst) begin
phy_ctl_wr <= #TCQ 1'b0;
pc_cntr_cmd <= #TCQ 5'b11111;
pc_data_offset <= #TCQ 6'b000000;
pc_command_offset <= #TCQ 5'b00000;
pc_cmd <= #TCQ 3'b100;
pc_ctl_ns <= #TCQ IDLE;
io_fifo_rden_cal_done_r <= #TCQ 1'b0;
end else begin
case (pc_ctl_ns)
IDLE : begin
if (phy_ctl_ready) begin
phy_ctl_wr <= #TCQ 1'b1;
pc_cntr_cmd <= #TCQ 5'b11111;
pc_data_offset <= #TCQ 6'b000000;
pc_command_offset <= #TCQ 5'b00000;
pc_cmd <= #TCQ 3'b100;
pc_ctl_ns <= #TCQ STALL_CMD;
end else begin
pc_ctl_ns <= #TCQ IDLE;
end
end
STALL_CMD : begin
// issue stall command. The command offset delays the
// read from the phy control fifo
if (~phy_ctl_a_full) begin
phy_ctl_wr <= #TCQ 1'b1;
pc_cntr_cmd <= #TCQ 5'b00000; // pc_cntr_cmd of 5'b000xx - refers to a stall command
pc_data_offset <= #TCQ 6'b000001;
pc_command_offset <= #TCQ 5'b11111; // max delay possible
pc_cmd <= #TCQ 3'b100; // Non data command
pc_ctl_ns <= #TCQ CONT_CMD;
end else begin
pc_ctl_ns <= #TCQ STALL_CMD;
end
end
CONT_CMD : begin //0x02
// continue to write into the phy control fifo until the fifo is full
if (~phy_ctl_a_full) begin
phy_ctl_wr <= #TCQ 1'b1;
pc_cntr_cmd <= #TCQ 5'b11111;
pc_data_offset <= #TCQ 6'b100010; // was 0
pc_command_offset <= #TCQ 5'b00000;
pc_cmd <= #TCQ 3'b001;
pc_ctl_ns <= #TCQ CONT_CMD;
end else begin
// phy_ctl_wr cannot be asserted when full flag is high
phy_ctl_wr <= #TCQ 1'b0;
pc_cntr_cmd <= #TCQ 5'b11111;
pc_data_offset <= #TCQ 6'b000000;
pc_command_offset <= #TCQ 5'b00000;
pc_cmd <= #TCQ 3'b001;
pc_ctl_ns <= #TCQ CONT_CMD2;
end
//io_fifo_rden_cal_done <= #TCQ 1'b1;
end
// wait for the full flag to deassert. Then start writing into the phy command fifo.
CMD_WAIT1 : begin
if (~ phy_ctl_a_full) begin
phy_ctl_wr <= #TCQ 1'b0;
pc_cntr_cmd <= #TCQ 5'b11111;
pc_data_offset <= #TCQ 6'b000000;
pc_command_offset <= #TCQ 5'b00000;
pc_cmd <= #TCQ 3'b001;
pc_ctl_ns <= #TCQ CONT_CMD2;
end
end
// // potential additional stage, probably not required.. will need to remove
// CMD_WAIT2 : begin
//
// phy_ctl_wr <= #TCQ 1'b0;
// pc_cntr_cmd <= #TCQ 5'b11111;
// pc_data_offset <= #TCQ 6'b000000;
// pc_command_offset <= #TCQ 5'b00000;
// pc_cmd <= #TCQ 3'b001;
// pc_ctl_ns <= #TCQ CONT_CMD2;
//
// end
CONT_CMD2 : begin
// continue to write NOP commands to the control fifo as long as
// the fifo is not full.
// The fifo will not be full as by now the read enable will be
// asserted and will be held high.
// Now the WRITE data and COMMAND fifos can be filled with
// data by the controller.
if (~phy_ctl_a_full) begin
phy_ctl_wr <= #TCQ 1'b1;
pc_cntr_cmd <= #TCQ (MEM_TYPE == "RLD3") ? 5'b0 : 5'b11111;
pc_data_offset <= #TCQ phy_ctl_data_offset; //6'b000000
pc_command_offset <= #TCQ 5'b00000;
pc_cmd <= #TCQ phy_ctl_cmd; //3'b001
pc_ctl_ns <= #TCQ CONT_CMD2;
io_fifo_rden_cal_done_r <= #TCQ 1'b1;
end
end // case: CONT_CMD2
default : begin
phy_ctl_wr <= #TCQ 1'b0;
pc_cntr_cmd <= #TCQ 5'b11111;
pc_data_offset <= #TCQ 6'b000000;
pc_command_offset <= #TCQ 5'b00000;
pc_cmd <= #TCQ 3'b100;
pc_ctl_ns <= #TCQ IDLE;
end
endcase
end
end
assign early_io_fifo_rden_cal_done = (pc_ctl_ns == CONT_CMD2 && !phy_ctl_a_full) ? 1'b1 : 1'b0;
//Generate write enable for the out FIFOs
//always write while the FIFOs are not FULL
always @ (posedge clk) begin
if (rst) begin
of_cmd_wr_en <= #TCQ 1'b0;
of_data_wr_en <= #TCQ 1'b0;
end else if ((PRE_FIFO == "TRUE") && (~phy_ctl_ready)) begin
of_cmd_wr_en <= #TCQ 1'b0;
of_data_wr_en <= #TCQ 1'b0;
end else if (MEM_TYPE == "RLD3") begin
if ((PRE_FIFO == "TRUE") && (!early_io_fifo_rden_cal_done)) begin
of_cmd_wr_en <= #TCQ phy_ctl_wr;
of_data_wr_en <= #TCQ phy_ctl_wr;
end else begin
of_cmd_wr_en <= #TCQ ~of_ctl_full;
of_data_wr_en <= #TCQ ~of_data_full;
end
end else if ((PRE_FIFO == "TRUE") && (~io_fifo_rden_cal_done_r)) begin
of_cmd_wr_en <= #TCQ phy_ctl_wr;
of_data_wr_en <= #TCQ phy_ctl_wr;
//end else begin //can possibly change this to be always high if Pre-fifo is used.
end else if ( ~ (of_ctl_full | of_data_full)) begin //can possibly change this to be always high if Pre-fifo is used.
of_cmd_wr_en <= #TCQ 1'b1;//~(of_ctl_full | of_data_full);
of_data_wr_en <= #TCQ 1'b1; //~(of_ctl_full | of_data_full);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e7; int gcd(int a, int b) { if (a == 0) return b; return gcd(b % a, a); } int main() { int n, ans = INT_MAX, count = 0; cin >> n; vector<int> v(n); for (int i = 0; i < n; i++) { cin >> v[i]; count += (v[i] == 1); } if (count > 0) { cout << n - count << endl; } else { vector<vector<int>> dp(n, vector<int>(n)); for (int i = 0; i < n; i++) dp[i][i] = v[i]; for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) dp[i][j] = gcd(v[j], dp[i][j - 1]); for (int i = 0; i < n; i++) for (int j = i; j < n; j++) if (dp[i][j] == 1) ans = min(ans, j - i); if (ans == INT_MAX) cout << -1 << endl; else cout << ans + n - 1 << endl; } return 0; } |
`include "bsg_defines.v"
module bsg_mul_booth_4_block_rep #(parameter [31:0] blocks_p=1
,parameter S_above_vec_p=0
,parameter dot_bar_vec_p=0
,parameter B_vec_p=0
,parameter one_vec_p=0
)
( input [4:0][2:0] SDN_i
, input cr_i
, input [blocks_p-1:0][3:0][1:0] y_vec_i
, output cl_o
, output [blocks_p-1:0] c_o
, output [blocks_p-1:0] s_o
);
wire [blocks_p:0] ci_local;
genvar i;
for (i = 0; i < blocks_p; i=i+1)
begin: rof
localparam S_above_vec_tmp = (S_above_vec_p >> (i << 2)) & 4'hf;
localparam S_dot_bar_vec_tmp = (dot_bar_vec_p >> (i << 2)) & 4'hf;
localparam B_vec_tmp = (B_vec_p >> (i << 2)) & 4'hf;
localparam one_vec_tmp = (one_vec_p >> (i << 2)) & 4'hf;
bsg_mul_booth_4_block #(
.S_above_vec_p(S_above_vec_tmp)
,.dot_bar_vec_p(S_dot_bar_vec_tmp)
,.B_vec_p(B_vec_tmp)
,.one_vec_p(one_vec_tmp)
)
b4b (.SDN_i(SDN_i), .y_i (y_vec_i[i])
, .cr_i(ci_local[i]), .cl_o(ci_local[i+1]), .c_o (c_o[i]), .s_o (s_o[i]));
end // block: rof
assign ci_local[0] = cr_i;
assign cl_o = ci_local[blocks_p];
endmodule // bsg_mul_booth_4_block_rep
|
// wrapper for alt_vipvfr131_common_pulling_width_adapter (CusP FU)
module alt_vipvfr131_common_unpack_data
( clock,
reset,
// read interface (memory side)
data_in,
read,
stall_in,
// write interface (user side)
data_out,
write,
stall_out,
// clear buffer
clear);
// DATA_WIDTH_IN must not be smaller than DATA_WIDTH_OUT!
parameter DATA_WIDTH_IN = 128;
parameter DATA_WIDTH_OUT = 24;
input clock;
input reset;
// read interface
input [DATA_WIDTH_IN - 1 : 0] data_in;
//output reg read;
output read;
input stall_in;
// write interface
input stall_out;
output reg write;
output [DATA_WIDTH_OUT - 1:0] data_out;
input clear;
wire need_input;
wire ena;
assign ena = ~stall_in;
/*always @(posedge clock or posedge reset)
if (reset)
read <= 1'b0;
else
read <= need_input;
*/
assign read = need_input;
// Cusp FU instantiation
alt_vipvfr131_common_pulling_width_adapter
#(.IN_WIDTH (DATA_WIDTH_IN),
.OUT_WIDTH (DATA_WIDTH_OUT)
)
fu_inst
( .clock (clock),
.reset (reset),
.input_data (data_in),
.need_input (need_input),
.output_data (data_out),
.pull (1'b1), // not explicitely needed
.pull_en (~stall_out),
.discard (1'b1), // not explicitely needed
.discard_en (clear),
.ena (ena)
);
always @(posedge clock or posedge reset)
if (reset) begin
write <= 1'b0;
end
else if (~stall_out) begin
write <= ena;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int const N = 1e6 + 2; int a[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 0; i < (int)(n); ++i) cin >> a[i]; for (int i = 0; i < (int)((1 << n)); ++i) { long long sum = 0; for (int j = 0; j < (int)(n); ++j) if (i & (1 << j)) sum += a[j]; else sum -= a[j]; sum %= 360; if (!sum) return cout << YES , 0; } cout << NO << endl; } |
//Legal Notice: (C)2021 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_tester_pio_1 (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 31: 0] out_port;
output [ 31: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input [ 31: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
wire [ 31: 0] data_in;
reg [ 31: 0] data_out;
wire [ 31: 0] out_port;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
wire wr_strobe;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign wr_strobe = chipselect && ~write_n;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (clk_en)
if (wr_strobe)
data_out <= (address == 5)? data_out & ~writedata[31 : 0]: (address == 4)? data_out | writedata[31 : 0]: (address == 0)? writedata[31 : 0]: data_out;
end
assign out_port = data_out;
assign data_in = in_port;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:23:39 04/29/2015
// Design Name: control_unit
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_control_unit.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: control_unit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_control_unit;
// Inputs
reg [15:0] IR;
// Outputs
wire [2:0] reg_read_adr1_d;
wire [2:0] reg_read_adr2_d;
wire [2:0] reg_write_adr_d;
wire reg_write_d;
wire ALU_source2_d;
wire [7:0] ALU_con_d;
wire [15:0] offset_register_d;
wire mem_write_d;
wire mem_to_reg_d;
wire branch_d;
wire [3:0] branch_condition_d;
wire IEN_d;
wire IOF_d;
wire RTI_d;
// Instantiate the Unit Under Test (UUT)
control_unit uut (
.IR(IR),
.reg_read_adr1_d(reg_read_adr1_d),
.reg_read_adr2_d(reg_read_adr2_d),
.reg_write_adr_d(reg_write_adr_d),
.reg_write_d(reg_write_d),
.ALU_source2_d(ALU_source2_d),
.ALU_con_d(ALU_con_d),
.offset_register_d(offset_register_d),
.mem_write_d(mem_write_d),
.mem_to_reg_d(mem_to_reg_d),
.branch_d(branch_d),
.branch_condition_d(branch_condition_d),
.IEN_d(IEN_d),
.IOF_d(IOF_d),
.RTI_d(RTI_d)
);
initial begin
// Initialize Inputs
IR = 0;
// Wait 100 ns for global reset to finish
//#100;
IR = 16'h1000;
#1;
IR = 16'h2000;
#1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve(int x, int y, int n) { vector<int> ans(n + 1); ans[x] = 1; ans[y] = 2; for (int i = 1, j = 3; i <= n; i++) { if (ans[i] == 0) { ans[i] = j++; } } for (int i = 1; i <= n; i++) { cout << ans[i] << ; } cout << n ; ans[y] = 1; for (int i = 1; i <= n; i++) { cout << ans[i] << ; } cout << n ; exit(0); } signed main() { ios::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; if (n == 0 || n * (n - 1) / 2 == m) { cout << NO n ; } else { cout << YES n ; set<pair<int, int>> st; for (int i = 0; i < m; i++) { int x, y; cin >> x >> y; if (x > y) swap(x, y); st.insert({x, y}); } for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { if (st.find({i, j}) == st.end()) { solve(i, j, n); } } } } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> bool umin(T& a, T b) { if (a > b) { a = b; return 1; } return 0; } template <class T> bool umax(T& a, T b) { if (a < b) { a = b; return 1; } return 0; } long long dp[200009][2], a, par[200009]; priority_queue<long long> bg; priority_queue<long long, vector<long long>, greater<long long> > sm; void upd(long long type, long long x) { if (!type) sm.push(x); else bg.push(x); } long long tap(long long type) { if (!type) return sm.top(); return bg.top(); } int main() { memset(dp, -1, sizeof dp); scanf( %lld , &a); for (long long i = 1; i <= a; i++) { long long x; scanf( %lld , &x); par[i] = par[i - 1] + x; } long long ans = -100000000924052357; upd(0, -par[a]); upd(1, par[a]); for (long long i = a; i >= 3; i--) { dp[i][0] = tap(1); dp[i][1] = tap(0); upd(0, dp[i][0] - par[i - 1]); upd(1, dp[i][1] + par[i - 1]); umax(ans, dp[i][1] + par[i - 1]); } printf( %lld n , max(ans, par[a])); return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_e_e
//
// Generated
// by: wig
// on: Thu Jul 6 05:51:58 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../autoopen.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_e_e.v,v 1.4 2006/07/10 07:30:09 wig Exp $
// $Date: 2006/07/10 07:30:09 $
// $Log: inst_e_e.v,v $
// Revision 1.4 2006/07/10 07:30:09 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_e_e
//
// No user `defines in this module
module inst_e_e
//
// Generated Module inst_e
//
(
p_mix_s_eo3_go,
s_eo1,
s_eo2,
s_eo4,
s_eo5,
s_outname
);
// Generated Module Inputs:
input s_outname;
// Generated Module Outputs:
output p_mix_s_eo3_go;
output s_eo1;
output s_eo2;
output s_eo4;
output s_eo5;
// Generated Wires:
wire p_mix_s_eo3_go;
wire s_eo1;
wire s_eo2;
wire s_eo4;
wire s_eo5;
wire s_outname;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire s_eo3; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_s_eo3_go = s_eo3; // __I_O_BIT_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_ea
inst_ea_e inst_ea (
.s_eo1(s_eo1),
.s_eo2(s_eo2),
.s_eo3(s_eo3),
.s_eo4(s_eo4),
.s_eo5(s_eo5)
);
// End of Generated Instance Port Map for inst_ea
// Generated Instance Port Map for inst_eb
inst_eb_e inst_eb (
.s_eo2(s_eo2)
);
// End of Generated Instance Port Map for inst_eb
endmodule
//
// End of Generated Module rtl of inst_e_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-8; const int inf = 0x3f3f3f3f; const int mod = 1000000007; const int maxn = 100000 + 10; string s, str[maxn]; int n; long long bit[10], len[10]; bool used[10]; long long Qpow(int x, long long b) { long long tmp = x, ret = 1; while (b) { if (b & 1) { ret *= tmp; ret %= mod; } tmp *= tmp; tmp %= mod; b >>= 1; } return ret; } void cal(string ss) { int sz = ss.length(), x = ss[0] - 0 ; long long tmp = 1, ans = 0; for (int i = sz - 1; i > 2; i--) { int now = ss[i] - 0 ; ans += tmp * bit[now]; ans %= mod; tmp *= len[now]; tmp %= mod; } bit[x] = ans; len[x] = tmp; used[x] = true; } int main() { cin >> s >> n; for (int i = 0; i < n; i++) cin >> str[i]; for (int i = 0; i < 10; i++) bit[i] = i, len[i] = 10, used[i] = false; for (int i = n - 1; i >= 0; i--) cal(str[i]); int sz = s.length(); long long ans = 0, tmp = 1; for (int i = sz - 1; i >= 0; i--) { int now = s[i] - 0 ; ans += bit[now] * tmp % mod; ans %= mod; tmp *= len[now]; tmp %= mod; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> a >> b; cout << (a * b) / 2; return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This is almost an exact copy of the lsu_burst_master, but has special support
// for placing items into a a block ram rather than a fifo. I'd rather leave them
// as separate files rather than complicating the already existing lsu's which are
// are known to work.
//
// Helper module to handle bursting large sequential blocks of memory to or
// from global memory.
//
/*****************************************************************************/
// Burst read master:
// Keeps a local buffer populated with data from a sequential block of
// global memory. The block of global memory is specified by a base address
// and size.
/*****************************************************************************/
module lsu_prefetch_block (
clk,
reset,
o_active, //Debugging signal
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_go,
cache_line_to_write_to,
control_done,
control_early_done,
// user logic inputs and outputs
cache_line_to_read_from,
user_buffer_address,
user_buffer_data,
user_data_available,
read_reg_enable,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_burstcount,
master_waitrequest
);
/*************
* Parameters *
*************/
parameter DATAWIDTH = 32;
parameter MWIDTH = DATAWIDTH;
parameter MAXBURSTCOUNT = 4;
parameter BURSTCOUNTWIDTH = 3;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
parameter N=8;
parameter LOG2N=3;
/********
* Ports *
********/
input clk;
input reset;
output o_active;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
input [LOG2N-1:0] cache_line_to_write_to;
output wire control_done;
output wire control_early_done; // don't use this unless you know what you are doing, it's going to fire when the last read is posted, not when the last data returns!
// user logic inputs and outputs
input [LOG2N-1:0] cache_line_to_read_from;
input [FIFODEPTH_LOG2-1:0] user_buffer_address;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
input read_reg_enable;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
/***************
* Architecture *
***************/
// internal control signals
reg control_fixed_location_d1;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
wire increment_address;
wire [BURSTCOUNTWIDTH-1:0] burst_count;
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire first_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire final_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
wire too_many_reads_pending;
reg [FIFODEPTH_LOG2:0] w_user_buffer_address;
// Pipelining
reg r_avm_readdatavalid;
reg [MWIDTH-1:0] r_avm_readdata /* synthesis dont_merge */;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, increment by the burst count presented
end
end
end
// user buffer address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
w_user_buffer_address <= 0;
end
else
begin
if(control_go == 1)
begin
w_user_buffer_address <= 0;
end
else
begin
w_user_buffer_address <= w_user_buffer_address + r_avm_readdatavalid;
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
length <= length - (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, decrement by the burst count presented
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign master_burstcount = burst_count;
assign control_done = 1'b0;
assign control_early_done = 1'b0;
assign master_read = (too_many_reads_pending == 0) & (length != 0);
assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
assign first_short_burst_enable = (burst_boundary_word_address != 0);
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
assign final_short_burst_count = (length / BYTEENABLEWIDTH);
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // this will get the transfer back on a burst boundary,
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address = (too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
assign too_many_reads_pending = 0;
/* --- Pipeline Return Path --- */
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_avm_readdata <= 'x;
r_avm_readdatavalid <= 1'b0;
end
else
begin
r_avm_readdata <= master_readdata;
r_avm_readdatavalid <= master_readdatavalid;
end
end
assign user_data_available = w_user_buffer_address[FIFODEPTH_LOG2];
altsyncram altsyncram_component (
.clock0 (clk),
.address_a ({cache_line_to_write_to,w_user_buffer_address[FIFODEPTH_LOG2-1:0]}),
.wren_a (r_avm_readdatavalid),
.data_a (r_avm_readdata),
.address_b ({cache_line_to_read_from,user_buffer_address}),
.q_b (user_buffer_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (~read_reg_enable),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATAWIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Stratix IV",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = N*FIFODEPTH,
altsyncram_component.numwords_b = N*FIFODEPTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = FIFODEPTH_LOG2+LOG2N,
altsyncram_component.widthad_b = FIFODEPTH_LOG2+LOG2N,
altsyncram_component.width_a = DATAWIDTH,
altsyncram_component.width_b = DATAWIDTH,
altsyncram_component.width_byteena_a = 1;
assign o_active = |length;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 5e5 + 3; const long long MOD = 998244353; int board[4][52]; int n; vector<pair<int, pair<int, int> > > moves; bool flag; void make_move(int a, int b, int x, int y) { if (board[a][b] == 0 && board[x][y] == 0) return; moves.push_back( pair<int, pair<int, int> >(board[a][b], pair<int, int>(x, y))); board[x][y] = board[a][b]; board[a][b] = 0; flag = true; } void enter() { for (int i = 0; i < n; i++) { if (board[0][i] == board[1][i]) { make_move(1, i, 0, i); } if (board[3][i] == board[2][i]) { make_move(2, i, 3, i); } } } const int dx[] = {0, 1, 0, -1}; const int dy[] = {-1, 0, 1, 0}; void print() { for (int i = 0; i < 4; i++) { for (int j = 0; j < n; j++) { printf( %2d , board[i][j]); } puts( ); } puts( ); } void move() { int f = -1, c = -1; for (int i = 0; i < n; i++) { if (board[1][i] == 0) { f = 1; c = i; break; } if (board[2][i] == 0) { f = 2; c = i; break; } } if (f == -1) return; int d; if (f == 1) d = 0; else d = 2; for (int t = 0; t < 2 * n - 1; t++) { int nf = f + dx[d]; int nc = c + dy[d]; if (nf >= 1 && nf <= 2 && nc >= 0 && nc < n) { make_move(nf, nc, f, c); f = nf; c = nc; } else { t--; d = (d + 1) % 4; } } } int main() { ios::sync_with_stdio(0); cin.tie(0); int k; cin >> n >> k; for (int i = 0; i < 4; i++) { for (int j = 0; j < n; j++) { cin >> board[i][j]; } } flag = true; while (flag) { flag = false; enter(); move(); } if (moves.size()) { cout << moves.size() << n ; for (auto x : moves) { cout << x.first << << x.second.first + 1 << << x.second.second + 1 << n ; } } else { cout << -1 << n ; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Wojtek Gumua
//
// Create Date: 19:16:36 05/19/2015
// Design Name:
// Module Name: mean_filter3x3
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mean_filter3x3 #(
parameter [9:0] H_SIZE = 83 // domylny rozmiar obrazu to szeroko = 64 piksele
)(
input clk,
input ce,
input rst,
input [7:0] in_Y,
input [7:0] in_Cb,
input [7:0] in_Cr,
input in_de,
input in_vsync,
input in_hsync,
output [7:0] out_Y,
output [7:0] out_Cb,
output [7:0] out_Cr,
output out_de,
output out_vsync,
output out_hsync
);
wire [10:0] delay_line11;
reg [10:0] delay_line12 [2:0];
wire [10:0] delay_line21;
reg [10:0] delay_line22 [2:0];
wire [10:0] delay_line31;
reg [10:0] delay_line32 [2:0];
reg [11:0] sum_lines[2:0];
reg [11:0] sum_final;
assign delay_line11 = {in_Y, in_de, in_hsync, in_vsync};
//pojedyncze opoznienia dla piksela
genvar i;
generate
always @(posedge clk)
begin
delay_line12[0] <= delay_line11;
delay_line22[0] <= delay_line21;
delay_line32[0] <= delay_line31;
delay_line12[1] <= delay_line12[0];
delay_line22[1] <= delay_line22[0];
delay_line32[1] <= delay_line32[0];
delay_line12[2] <= delay_line12[1];
delay_line22[2] <= delay_line22[1];
delay_line32[2] <= delay_line32[1];
end
endgenerate;
wire [9:0] dummy;//zbdne dane
delayLinieBRAM_WP long_delay1
(
.clk(clk),
.rst(1'b0),
.ce(1'b1),
.din({5'b0, delay_line12[2]}),
.dout({dummy[4:0], delay_line21}),
.h_size(H_SIZE - 3)
);
delayLinieBRAM_WP long_delay2
(
.clk(clk),
.rst(1'b0),
.ce(1'b1),
.din({5'b0, delay_line22[2]}),
.dout({dummy[9:5], delay_line31}),
.h_size(H_SIZE - 3)
);
always @(posedge clk)
begin
//wyznaczanie sum
if(context_valid) begin
//A + 2B + C
sum_lines[0] <= {4'b0, delay_line12[0][10:3]} + {3'b0, delay_line12[1][10:3], 1'b0} + {4'b0,delay_line12[2][10:3]};
//2A + 4B + 2B
sum_lines[1] <= {3'b0, delay_line22[0][10:3], 1'b0} + {2'b0, delay_line22[1][10:3], 2'b0} + {3'b0, delay_line22[2][10:3], 1'b0};
//A + 2B + C
sum_lines[2] <= {4'b0, delay_line32[0][10:3]} + {3'b0, delay_line32[1][10:3], 1'b0} + {4'b0,delay_line32[2][10:3]};
sum_final <= sum_lines[0] + sum_lines[1] + sum_lines[2];
end
end
wire context_valid;
assign context_valid = delay_line12[0][1] & delay_line12[1][1] & delay_line12[2][1] &
delay_line22[0][1] & delay_line22[1][1] & delay_line22[2][1] &
delay_line32[0][1] & delay_line32[1][1] & delay_line32[2][1];
wire [2:0] d_dhv;
delay #
(
.N(3),
.DELAY(2)
)
dhv
(
.d(delay_line22[2][2:0]),
.ce(1'b1),
.clk(clk),
.q({d_dhv})
);
assign out_de = d_dhv[2];
assign out_hsync = d_dhv[1];
assign out_vsync = d_dhv[0];
reg [7:0] mean_latch = 0;
always @(posedge clk)
begin
if(context_valid) mean_latch <= sum_final[11:4];
end;
assign out_Y = mean_latch;
//opoznienie sygnalow Cb, Cr
delay #
(
.N(8),
.DELAY(2 + H_SIZE + 1)
)
delay_cb
(
.d(in_Cb),
.ce(1'b1),
.clk(clk),
.q(out_Cb)
);
delay #
(
.N(8),
.DELAY(2 + H_SIZE + 1)
)
delay_cr
(
.d(in_Cr),
.ce(1'b1),
.clk(clk),
.q(out_Cr)
);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module implements frexp function specified in the OpenCL 1.0 specification.
// It takes as input a floating point number (x), single or double precision, and returns
// a single or double precision number that represents the fraction (r) of the supplied floating point number
// in the range of [0.5, 1) or 0 and an integer (n) that represents the exponent of the input value.
//
// The result of the operation must be such that x = r*2^n.
// Notes:
// - Denormalized numbers are flushed to 0.
// - if the number is infinity or a nan, the returned fraction is the original input and the exponent is 32'd0.
module acl_fp_frexp( clock, resetn, enable, valid_in, valid_out, stall_in, stall_out, dataa, result_fr, result_exp);
parameter WIDTH = 32;
parameter HIGH_CAPACITY = 1;
input clock, resetn;
input enable, valid_in, stall_in;
output valid_out, stall_out;
input [WIDTH-1:0] dataa;
output [WIDTH-1:0] result_fr;
output [31:0] result_exp;
// Simply extract the mantissa and at the most shift it to the right by one position.
reg c1_valid;
wire c1_stall;
wire c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
reg [WIDTH-1:0] c1_fraction;
reg [31:0] c1_exponent;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
end
else if (c1_enable)
begin
c1_valid <= valid_in;
if (WIDTH==32)
begin
if (~(|dataa[WIDTH-2:WIDTH-9]))
begin
c1_fraction <= 32'd0;
c1_exponent <= 32'd0;
end
else if (&dataa[WIDTH-2:WIDTH-9])
begin
c1_fraction <= dataa;
c1_exponent <= 32'd0;
end
else
begin
c1_fraction <= {dataa[WIDTH-1], 8'h7e, dataa[WIDTH-10:0]};
c1_exponent <= {1'b0, dataa[WIDTH-2:WIDTH-9]} - 9'd126;
end
end
else
begin
if (~(|dataa[WIDTH-2:WIDTH-12]))
begin
c1_fraction <= 64'd0;
c1_exponent <= 32'd0;
end
else
if (&dataa[WIDTH-2:WIDTH-12])
begin
c1_fraction <= dataa;
c1_exponent <= 32'd0;
end
else
begin
c1_fraction <= {dataa[WIDTH-1], 11'h3fe, dataa[WIDTH-13:0]};
c1_exponent <= {1'b0, dataa[WIDTH-2:WIDTH-12]} - 12'd1022;
end
end
end
end
assign c1_stall = stall_in;
assign valid_out = c1_valid;
assign result_fr = c1_fraction;
assign result_exp = c1_exponent;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0n, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDLCLKP_BEHAVIORAL_PP_V |
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_chipscope.v
// /___/ /\ Date Last Modified: $Data$
// \ \ / \ Date Created: 9/14/06
// \___\/\___\
//
//Device: Virtex-5
//Purpose:
// Skeleton Chipscope module declarations - for simulation only
//Reference:
//Revision History:
//
//*****************************************************************************
`timescale 1ns/1ps
module icon4
(
control0,
control1,
control2,
control3
)
/* synthesis syn_black_box syn_noprune = 1 */;
output [35:0] control0;
output [35:0] control1;
output [35:0] control2;
output [35:0] control3;
endmodule
module vio_async_in192
(
control,
async_in
)
/* synthesis syn_black_box syn_noprune = 1 */;
input [35:0] control;
input [191:0] async_in;
endmodule
module vio_async_in96
(
control,
async_in
)
/* synthesis syn_black_box syn_noprune = 1 */;
input [35:0] control;
input [95:0] async_in;
endmodule
module vio_async_in100
(
control,
async_in
)
/* synthesis syn_black_box syn_noprune = 1 */;
input [35:0] control;
input [99:0] async_in;
endmodule
module vio_sync_out32
(
control,
clk,
sync_out
)
/* synthesis syn_black_box syn_noprune = 1 */;
input [35:0] control;
input clk;
output [31:0] sync_out;
endmodule |
#include <bits/stdc++.h> using namespace std; template <typename T, size_t N> void PRINT_ARRAY(const T (&a)[N], int n = -1) { if (!n) n = N; for (int i = 0; i < n; i++) cout << a[i] << ; cout << n ; } template <typename T, size_t N, size_t M> void PRINT_ARRAY(const T (&a)[N][M], int n, int m) { for (int i = 0; i < n; i++) PRINT_ARRAY(a[i], m); cout << n ; } long long arr[3005], cost[3005], lessc, more, ans; int n; void solve() { cin >> n; for (int i = 0; i < n; i++) cin >> arr[i]; for (int i = 0; i < n; i++) cin >> cost[i]; ans = (int)(1e9 + 7); for (int i = 1; i < n - 1; i++) { lessc = (int)(1e9 + 7); more = (int)(1e9 + 7); for (int j = 0; j < i; j++) if (arr[i] > arr[j]) lessc = min(lessc, cost[j]); for (int j = i + 1; j < n; j++) if (arr[j] > arr[i]) more = min(more, cost[j]); ans = min(ans, cost[i] + lessc + more); } cout << (ans == (int)(1e9 + 7) ? -1 : ans); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; solve(); } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using ii = pair<ll, ll>; using vi = vector<ll>; using vb = vector<bool>; using vvi = vector<vi>; using vii = vector<ii>; using vvii = vector<vii>; const int INF = 2000000000; const ll LLINF = 9000000000000000000; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int N; ll M, T; cin >> N >> M >> T; vi S(N, 0LL); vi D(N, 0LL); vii Si(N, {0LL, 0LL}); bool lf = false, rf = false; int dsum = 0; for (int i = 0; i < N; ++i) { char c; cin >> S[i] >> c; D[i] = (c == L ? -1 : 1); if (D[i] == -1) lf = true; else rf = true; dsum += D[i]; Si[i] = {S[i], i}; } vi pos(N, 0LL); for (int i = 0; i < N; ++i) { pos[i] = (S[i] + D[i] * (T % M)) + M; pos[i] %= M; if (pos[i] == 0) pos[i] = M; } if (!lf || !rf) { for (int i = 0; i < N; ++i) cout << pos[i] << n [i + 1 == N]; return 0; } vii crossdir; for (int i = 0; i < N; ++i) { ll k = -D[i] * (D[i] == 1 ? (S[i] - 1) : S[i]); while (k <= 0) k += M; k %= M; if (k == 0) k += M; crossdir.push_back({k, D[i]}); } sort(crossdir.begin(), crossdir.end()); ll shift = -(T / M) * dsum; for (size_t j = 0; j < crossdir.size() && crossdir[j].first <= (T % M); ++j) { shift -= crossdir[j].second; } shift = ((shift % N) + N) % N; sort(pos.begin(), pos.end()); sort(Si.begin(), Si.end()); vi ans(N, 0); for (int i = 0; i < N; ++i) { ans[Si[i].second] = pos[(i + N - shift) % N]; } for (int i = 0; i < N; ++i) cout << ans[i] << n [i + 1 == N]; return 0; } |
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//-------------------------------------------------------------------
// Filename : db_sao_cal_offset.v
// Author : Chewein
// Created : 2015-03-19
// Description : calculation the offset dependent on the band
// number and state
//-------------------------------------------------------------------
module db_sao_cal_offset(
b_state_i ,
b_num_i ,
data_valid_i ,
b_offset_o ,
b_distortion_o
);
//---------------------------------------------------------------------------
//
// INPUT/OUTPUT DECLARATION
//
//----------------------------------------------------------------------------
parameter DATA_WIDTH = 128 ;
parameter PIXEL_WIDTH = 8 ;
parameter DIFF_WIDTH = 20 ;
parameter DIS_WIDTH = 25 ;
input signed [DIFF_WIDTH-1:0] b_state_i ;
input [ 12 :0] b_num_i ;
input data_valid_i ;
output signed [ 2 :0] b_offset_o ;
output signed [ DIS_WIDTH-1:0] b_distortion_o ;
reg signed [DIFF_WIDTH-1:0] b_state_r ;
reg [ 12 :0] b_num_r ;
reg [DIFF_WIDTH-1:0] b_state_unsigned_r ;
wire [ 14 :0] b_num_m2_w ;
wire [ 14 :0] b_num_m3_w ;
reg [ 1 :0] b_offset_unsigned_r;
reg signed [ 2 :0] b_offset_r ;
always @* begin
case(data_valid_i)
1'b0 :begin b_state_r = 'd0 ; b_num_r = 13'd0 ;end
1'b1 :begin b_state_r = b_state_i; b_num_r = b_num_i;end
endcase
end
always @* begin
case(b_state_r[DIFF_WIDTH-1])
1'b0 : b_state_unsigned_r = {1'b0,b_state_r} ;
1'b1 : b_state_unsigned_r = (~b_state_r)+1'b1 ;
endcase
end
assign b_num_m2_w = {b_num_r,1'b0} ;
assign b_num_m3_w = {b_num_r,1'b0} + b_num_r ;
always @* begin
if(!b_num_r)
b_offset_unsigned_r = 2'd0 ;
else if(b_state_unsigned_r<b_num_r)
b_offset_unsigned_r = 2'd0 ;
else if(b_state_unsigned_r<b_num_m2_w)
b_offset_unsigned_r = 2'd1 ;
else if(b_state_unsigned_r<b_num_m3_w)
b_offset_unsigned_r = 2'd2 ;
else
b_offset_unsigned_r = 2'd3 ;
end
always @* begin
case(b_state_r[DIFF_WIDTH-1])
1'b0 : b_offset_r = {1'b0,b_offset_unsigned_r} ;
1'b1 : b_offset_r = ~(b_offset_unsigned_r)+1'b1 ;
endcase
end
wire signed [ 5:0] temp1= b_offset_r * b_offset_r;
wire signed [18:0] temp2= b_num_r * temp1 ;
wire signed [DIS_WIDTH-1:0] temp3= b_state_r*b_offset_r ;
assign b_offset_o = b_offset_r ;
assign b_distortion_o = temp2 - {temp3,1'b0} ;
endmodule
|
`timescale 1ns / 1ps
`include "../src/axis_reshaper.v"
module testreshaper(
);
localparam RANDOMOUTPUT = 1;
localparam RANDOMINPUT = 1;
localparam DATA_WIDTH = 12;
wire[DATA_WIDTH-1:0] mdata;
wire mlast;
reg mready;
wire muser;
wire mvalid;
wire[DATA_WIDTH-1:0] sdata;
wire slast;
wire sready;
wire suser;
reg svalid;
reg[11:0] ori_height = 10;
reg[11:0] ori_width = 10;
reg resetn;
reg clk;
axis_reshaper #(
.C_PIXEL_WIDTH(DATA_WIDTH),
.C_LOCK_FRAMES(2),
.C_WIDTH_BITS(12),
.C_HEIGHT_BITS(12)
)uut(
.m_axis_tdata(mdata),
.m_axis_tlast(mlast),
.m_axis_tready(mready),
.m_axis_tuser(muser),
.m_axis_tvalid(mvalid),
.s_axis_tdata(sdata),
.s_axis_tlast(slast),
.s_axis_tready(sready),
.s_axis_tuser(suser),
.s_axis_tvalid(svalid),
.clk(clk),
.resetn(resetn));
initial begin
clk <= 1'b1;
forever #1 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #2 resetn <= 1'b0;
forever #2 resetn <= 1'b1;
end
reg[11:0] in_frm;
reg[11:0] in_row;
reg[11:0] in_col;
assign sdata = (in_frm * 256 + in_row * 16 + in_col);
reg[11:0] out_row;
reg[11:0] out_col;
reg[7:0] out_data;
reg out_last;
assign suser = (in_row == 0 && in_col == 0);
assign slast = (in_col == ori_height - 1);
reg randominput;
reg randomoutput;
always @(posedge clk) begin
if (resetn == 1'b0)
randominput <= 1'b0;
else
randominput <= (RANDOMINPUT ? {$random}%2 : 1);
if (resetn == 1'b0)
randomoutput <= 1'b0;
else
randomoutput <= (RANDOMOUTPUT ? {$random}%2 : 1);
if (resetn == 1'b0) begin
in_frm <= 0;
in_row <= 0;
in_col <= 0;
end
else if (svalid && sready) begin
if (in_col != ori_width - 1) begin
in_col <= in_col + 1;
in_row <= in_row;
end
else if (in_row != ori_height - 1) begin
in_col <= 0;
in_row <= in_row + 1;
end
else begin
in_frm <= in_frm + 1;
in_row <= 0;
in_col <= 0;
end
end
if (resetn == 1'b0)
svalid <= 1'b0;
else if (~svalid) begin
if (randominput) begin
svalid <= 1'b1;
end
end
else if (svalid && sready) begin
if (randominput) begin
svalid <= 1'b1;
end
else begin
svalid <= 1'b0;
end
end
if (resetn == 1'b0)
mready <= 1'b0;
else if (randomoutput)
mready <= 1'b1;
else
mready <= 1'b0;
if (resetn == 1'b0) begin
out_data <= 0;
out_last <= 0;
end
else if (mready && mvalid) begin
out_data <= mdata;
out_last <= mlast;
end
if (resetn == 1'b0) begin
out_col = 0;
out_row = 0;
end
else if (mready && mvalid) begin
if (muser) begin
out_col = 0;
out_row = 0;
end
else if (out_last) begin
out_col = 0;
out_row = out_row + 1;
end
else begin
out_col = out_col + 1;
out_row = out_row;
end
if (muser)
$write("start new frame: \n");
$write("%h ", mdata);
if (mdata[7:0] != (out_row * 16 + out_col))
$write("err!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!\n");
if (mlast)
$write("\n");
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long t; cin >> t; while (t--) { long long n; cin >> n; vector<int> ans; for (int i = 0; i <= 400; i++) { for (int j = 0; j <= 200; j++) { long long x = 3 * i, y = 5 * j; long long z = n - x - y; if (z >= 0) { if (z % 7 == 0) { z = z / 7; ans.push_back(x), ans.push_back(y), ans.push_back(7 * z); break; } } } if (ans.size() == 3) break; } if (ans.size() != 3) cout << -1 << n ; else cout << ans[0] / 3 << << ans[1] / 5 << << ans[2] / 7 << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRBP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 5; const int dir[8][2] = {{0, 1}, {1, 1}, {1, 0}, {1, -1}, {0, -1}, {-1, -1}, {-1, 0}, {-1, 1}}; const int dir8x[8] = {-1, -1, -1, 0, 0, 1, 1, 1}; const int dir8y[8] = {-1, 0, 1, 1, -1, -1, 0, 1}; const long long mod = 1e9 + 7; const double PI = acos(-1.0); long long po(long long a, long long b, long long mod) { long long res = 1; a %= mod; for (; b; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long gcd(long long a, long long b) { if (a == 0) { return b; } else { return gcd(b % a, a); } } int n; long long val[maxn], dp[maxn]; void solve() { scanf( %d , &(n)); for (int i = 1; i <= n; i++) { scanf( %lld , &val[i]); } int last = 1; for (int i = 2; i <= n; i++) { dp[i] = max(dp[last - 1] + labs(val[i] - val[last]), dp[last] + labs(val[i] - val[last + 1])); if (val[i] <= val[i + 1] && val[i] <= val[i - 1]) { last = i; } if (val[i] >= val[i + 1] && val[i] >= val[i - 1]) { last = i; } } long long res = dp[n]; printf( %lld , res); } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; #define fast_io ios::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); #define lli long long #define loop(i, l, r) for (lli i = l; l < r ? i < r : i > r; l < r ? i += 1 : i -= 1) #define itr(it, a) for (auto it = a.begin(); it != a.end(); it++) #define it(i, a) for (auto i : a) #define endl n #define inputarray(arr, start, size) loop(i, start, size) { cin >> arr[i]; } #define printarray(arr, start, size) loop(i, start, size) { cout << arr[i] << ; } cout << endl; #define mod 1000000007 #define inf 1e18 #define sp(x, y) fixed << setprecision(y) << x << endl; #define pii pair<lli, lli> #define mp make_pair #define pb push_back #define fi first #define se second #define all(x) x.begin(), x.end() #define clr(x) memset(x, 0, sizeof(x)) #define sortall(x) sort(all(x)) #define debug(x) cout << #x << = << x << endl int main() { #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif fast_io lli t = 1; cin >> t; while (t--) { lli n; cin >> n; vector<lli> v(n); inputarray(v, 0, n); bool flag = 0; lli diff = INT_MAX, md = INT_MIN; loop(i, 0, n) { if (v[i] < 0) { flag = 1; break; } } if (flag) { cout << NO << endl; continue; } cout << YES << endl; cout << 101 << endl; vector<lli> b; loop(i, 0, 101) { b.push_back(i); } printarray(b, 0, b.size()); } return 0; } |
#include <bits/stdc++.h> using namespace std; int delta[1000000], cnt[1000000]; int main() { int n, m, dx, dy; cin >> n >> m >> dx >> dy; int x = 0, y = 0; delta[0] = 0; for (int i = 1; i < n; ++i) { x = (x + dx) % n; y = (y + dy) % n; delta[x] = y; } for (int i = 0; i < n; ++i) cnt[i] = 0; for (int i = 0; i < m; ++i) { cin >> x >> y; ++cnt[(y + n - delta[x]) % n]; } int ans = 0; for (int i = 0; i < n; ++i) if (cnt[ans] < cnt[i]) ans = i; cout << 0 << << ans << endl; } |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module hps_sdram_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
hps_sdram_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
hps_sdram_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
hps_sdram_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
defparam ureset_seq_clk.RESET_SYNC_STAGES = 15;
defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
defparam ureset_scc_clk.RESET_SYNC_STAGES = 15;
defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
defparam ureset_avl_clk.RESET_SYNC_STAGES = 2;
defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
hps_sdram_p0_reset_sync #(
.RESET_SYNC_STAGES(15),
.NUM_RESET_OUTPUT(1)
)
ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDLCLKP_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__SDLCLKP_BEHAVIORAL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_hdll__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
// Module ports
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire m0n ;
wire clkn ;
wire CLK_delayed ;
wire SCE_delayed ;
wire GATE_delayed ;
wire SCE_gate_delayed;
reg notifier ;
wire awake ;
wire SCE_awake ;
wire GATE_awake ;
// Name Output Other arguments
not not0 (m0n , m0 );
not not1 (clkn , CLK_delayed );
nor nor0 (SCE_gate_delayed, GATE_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dlatch$P_pp$PG$N dlatch0 (m0 , SCE_gate_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0n, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
assign SCE_awake = ( awake & ( GATE_delayed === 1'b0 ) );
assign GATE_awake = ( awake & ( SCE_delayed === 1'b0 ) );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDLCLKP_BEHAVIORAL_V |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module softusb_tx(
input usb_clk,
input usb_rst,
input [7:0] tx_data,
input tx_valid,
output reg tx_ready,
output reg txp,
output reg txm,
output reg txoe,
input low_speed,
input generate_eop
);
/* Register outputs */
reg txp_r;
reg txm_r;
reg txoe_r;
always @(posedge usb_clk) begin
txp <= txp_r;
txm <= txm_r;
txoe <= txoe_r;
end
/* Clock 'divider' */
reg gce; /* global clock enable */
reg [4:0] gce_counter;
always @(posedge usb_clk) begin
if(usb_rst) begin
gce <= 1'b0;
gce_counter <= 5'd0;
end else begin
gce <= low_speed ? (gce_counter == 5'd31) : (gce_counter[1:0] == 2'd3);
gce_counter <= gce_counter + 5'd1;
end
end
/* Shift register w/bit stuffing */
reg sr_rst;
reg sr_load;
reg sr_done;
reg sr_out;
reg [2:0] bitcount;
reg [2:0] onecount;
reg [6:0] sr;
always @(posedge usb_clk) begin
if(sr_rst) begin
sr_done <= 1'b1;
onecount <= 3'd0;
end else if(gce) begin
if(sr_load) begin
sr_done <= 1'b0;
sr_out <= tx_data[0];
bitcount <= 3'd0;
if(tx_data[0])
onecount <= onecount + 3'd1;
else
onecount <= 3'd0;
sr <= tx_data[7:1];
end else if(~sr_done) begin
if(onecount == 3'd6) begin
onecount <= 3'd0;
sr_out <= 1'b0;
if(bitcount == 3'd7)
sr_done <= 1'b1;
end else begin
sr_out <= sr[0];
if(sr[0])
onecount <= onecount + 3'd1;
else
onecount <= 3'd0;
bitcount <= bitcount + 3'd1;
if((bitcount == 3'd6) & (~sr[0] | (onecount != 3'd5)))
sr_done <= 1'b1;
sr <= {1'b0, sr[6:1]};
end
end
end
end
/* Output generation */
reg txoe_ctl;
reg generate_se0;
reg generate_j;
always @(posedge usb_clk) begin
if(usb_rst) begin
txoe_r <= 1'b0;
txp_r <= ~low_speed;
txm_r <= low_speed;
end else if(gce) begin
if(~txoe_ctl) begin
txp_r <= ~low_speed; /* return to J */
txm_r <= low_speed;
end else begin
case({generate_se0, generate_j})
2'b00: begin
if(~sr_out) begin
txp_r <= ~txp_r;
txm_r <= ~txm_r;
end
end
2'b10: begin
txp_r <= 1'b0;
txm_r <= 1'b0;
end
2'b01: begin
txp_r <= ~low_speed;
txm_r <= low_speed;
end
default: begin
txp_r <= 1'bx;
txm_r <= 1'bx;
end
endcase
end
txoe_r <= txoe_ctl;
end
end
/* Sequencer */
parameter IDLE = 3'd0;
parameter DATA = 3'd1;
parameter EOP1 = 3'd2;
parameter EOP2 = 3'd3;
parameter J = 3'd4;
parameter GEOP1 = 3'd5;
parameter GEOP2 = 3'd6;
parameter GJ = 3'd7;
reg [2:0] state;
reg [2:0] next_state;
always @(posedge usb_clk) begin
if(usb_rst)
state <= IDLE;
else if(gce)
state <= next_state;
end
reg tx_ready0;
always @(posedge usb_clk)
tx_ready <= tx_ready0 & gce;
reg tx_valid_r;
reg transmission_continue;
reg transmission_end_ack;
always @(posedge usb_clk) begin
if(usb_rst) begin
tx_valid_r <= 1'b0;
transmission_continue <= 1'b1;
end else begin
tx_valid_r <= tx_valid;
if(tx_valid_r & ~tx_valid)
transmission_continue <= 1'b0;
if(transmission_end_ack)
transmission_continue <= 1'b1;
end
end
reg generate_eop_pending;
reg generate_eop_clear;
always @(posedge usb_clk) begin
if(usb_rst)
generate_eop_pending <= 1'b0;
else begin
if(generate_eop)
generate_eop_pending <= 1'b1;
if(generate_eop_clear)
generate_eop_pending <= 1'b0;
end
end
always @(*) begin
txoe_ctl = 1'b0;
sr_rst = 1'b0;
sr_load = 1'b0;
generate_se0 = 1'b0;
generate_j = 1'b0;
tx_ready0 = 1'b0;
transmission_end_ack = 1'b0;
generate_eop_clear = 1'b0;
next_state = state;
case(state)
IDLE: begin
txoe_ctl = 1'b0;
if(generate_eop_pending)
next_state = GEOP1;
else begin
if(tx_valid) begin
sr_load = 1'b1;
next_state = DATA;
end else
sr_rst = 1'b1;
tx_ready0 = 1'b1;
end
end
DATA: begin
txoe_ctl = 1'b1;
if(sr_done) begin
if(transmission_continue) begin
sr_load = 1'b1;
tx_ready0 = 1'b1;
end else
next_state = EOP1;
end
end
EOP1: begin
transmission_end_ack = 1'b1;
sr_rst = 1'b1;
txoe_ctl = 1'b1;
generate_se0 = 1'b1;
next_state = EOP2;
end
EOP2: begin
sr_rst = 1'b1;
txoe_ctl = 1'b1;
generate_se0 = 1'b1;
next_state = J;
end
J: begin
sr_rst = 1'b1;
txoe_ctl = 1'b1;
generate_j = 1'b1;
next_state = IDLE;
end
GEOP1: begin
sr_rst = 1'b1;
txoe_ctl = 1'b1;
generate_se0 = 1'b1;
next_state = GEOP2;
end
GEOP2: begin
sr_rst = 1'b1;
txoe_ctl = 1'b1;
generate_se0 = 1'b1;
next_state = GJ;
end
GJ: begin
generate_eop_clear = 1'b1;
sr_rst = 1'b1;
txoe_ctl = 1'b1;
generate_j = 1'b1;
next_state = IDLE;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { long long int m, a[1000], b, sum = 0; cin >> m >> b; for (int j = 0; j < m; j++) { cin >> a[j]; } for (int j = 0; j < m; j++) { sum = sum + a[j]; } if (sum == b) { cout << YES << endl; } else { cout << NO << endl; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_PWRGOOD_PP_G_TB_V
`define SKY130_FD_SC_MS__UDP_PWRGOOD_PP_G_TB_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_pwrgood_pp_g.v"
module top();
// Inputs are registered
reg UDP_IN;
reg VGND;
// Outputs are wires
wire UDP_OUT;
initial
begin
// Initial state is x for all inputs.
UDP_IN = 1'bX;
VGND = 1'bX;
#20 UDP_IN = 1'b0;
#40 VGND = 1'b0;
#60 UDP_IN = 1'b1;
#80 VGND = 1'b1;
#100 UDP_IN = 1'b0;
#120 VGND = 1'b0;
#140 VGND = 1'b1;
#160 UDP_IN = 1'b1;
#180 VGND = 1'bx;
#200 UDP_IN = 1'bx;
end
sky130_fd_sc_ms__udp_pwrgood_pp$G dut (.UDP_IN(UDP_IN), .VGND(VGND), .UDP_OUT(UDP_OUT));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_PWRGOOD_PP_G_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; if (s[1] == 1 ) { if (s[0] == a || s[0] == h ) { cout << 3 << endl; } else { cout << 5 << endl; } } else if (s[1] == 8 ) { if (s[0] == a || s[0] == h ) { cout << 3 << endl; } else { cout << 5 << endl; } } else { if (s[0] == a || s[0] == h ) { cout << 5 << endl; } else { cout << 8 << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cout << 2000 << endl; for (int i = 1; i <= 1000; ++i) cout << i << << 1 << << i << 2 n ; for (int i = 1000; i >= 1; --i) cout << i << << 1 << << i << 2 n ; } |
// #pragma GCC optimize( Ofast ) #pragma GCC target ( sse4 ) #include <iostream> #include <cstring> #include <algorithm> #include <cmath> #include <map> #include <queue> using namespace std; const int N = 2e5 + 10, M = N * 2, INT = 0x3f3f3f3f, mod = 1e9 + 7; //#define int long long #define pi 3.1415926 #define x first #define y second typedef long long ll; typedef pair<int,int> pii; //ios::sync_with_stdio(false); ll gcd(ll a,ll b) {return b ? gcd(b, a % b) : a;} // int gcd(int a,int b) {return b ? gcd(b, a % b) : a;} ll qmi(ll a,ll b) {ll res = 1 % mod;while (b){if (b & 1) res = (res * a) % mod;a = a * a % mod;b >>= 1;}return res;} int t, n, m, k; int x; deque<int> q1, q2, s1, s2; int s[M]; int get(deque<int> &a,deque<int> &b) { if (a.size() == 0 || b.size() == 0) return 0; s[b.size()] = 0; // for (auto x : a) printf( %d , x); // puts( ); // for (auto x : b) printf( %d , x); // puts( ); for (int i = b.size() - 1, j = a.size() - 1; i >= 0; i -- ) { while (a[j] > b[i] && j > 0) j --; if (a[j] == b[i]) s[i] = 1; else s[i] = 0; s[i] += s[i + 1]; } // for (int i = 0; i < b.size(); i ++ ) printf( %d , s[i]); // puts( ); int ans = 0; for (int i = 0; i < b.size(); i ++ ) { int p = upper_bound(a.begin(), a.end(), b[i]) - a.begin(); int l = lower_bound(b.begin(), b.end(), b[i] - p + 1) - b.begin(); ans = max(ans, s[i + 1] + i - l + 1); // printf( b_i=%d p = %d b_i-p=%d l = %d n , b[i], p, b[i] - p + 1, l); } // cout << ans << ------------------------- ; return ans; } void solve() { q1.clear(), q2.clear(), s1.clear(), s2.clear(); cin >> n >> m; for (int i = 1; i <= n; i ++ ) { scanf( %d , &x); if (x > 0) { q1.push_back(x); } else q2.push_front(-x); } for (int i = 1; i <= m; i ++ ) { scanf( %d , &x); if (x > 0) { s1.push_back(x); } else s2.push_front(-x); } int ans = get(q1, s1) + get(q2, s2); // puts( ); printf( %d n , ans); } signed main() { cin >> t;while (t -- ) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { int N; cin >> N; string s; cin >> s; int current = N; int count = 0; while (true) { if (current >= s.size()) break; set<char> vs; vs.insert(s[current - 1]); vs.insert(s[current - 2]); vs.insert(s[current - 3]); if (vs.size() == 1) count++; current += N; } cout << count; } |
#include <bits/stdc++.h> using namespace std; int a[10]; bool cmp(int a, int b) { if (a > b) return true; else false; } int main(void) { int i, n = 6, h; for (i = 0; i < n; i++) { scanf( %d , &h); a[h]++; } sort(a, a + 10, greater<int>()); int x = a[0]; if (x == 4) { if (a[1] == 2) printf( Elephant n ); else printf( Bear n ); } else if (x == 5) printf( Bear n ); else if (x == 6) printf( Elephant n ); else printf( Alien n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s, t; cin >> s >> t; int n = s.size(); int m = t.size(); if (n == m && s == t) cout << -1; else cout << max(n, m); } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast , unroll-loops , no-stack-protector ) using namespace std; using ll = long long; using ld = double; using pii = pair<int, int>; using uint = unsigned int; using ull = unsigned long long; mt19937 rnd(chrono::steady_clock::now().time_since_epoch().count()); default_random_engine generator; void solve(); int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout << setprecision(16) << fixed; cerr << setprecision(16) << fixed; int tests = 1; for (int test = 1; test <= tests; ++test) { solve(); } } const int INF = 1e9; struct Point { int x, y; }; void solve() { int n; cin >> n; vector<Point> p(n); for (int i = 0; i < n; ++i) { string s; cin >> s; int a = 0, b = 0; for (char c : s) { a += c == B ; b += c == N ; } p[i] = {a, b}; } int minx = INF, maxx = -INF; int miny = INF, maxy = -INF; int l = INF, r = -INF; for (auto [x, y] : p) { minx = min(minx, x); maxx = max(maxx, x); miny = min(miny, y); maxy = max(maxy, y); l = min(l, x - y); r = max(r, x - y); } int res = 0; res = max(res, (maxx - minx + 1) / 2); res = max(res, (maxy - miny + 1) / 2); res = max(res, (minx - miny) - l); res = max(res, r - (minx - miny)); Point best = {minx + res, miny + res}; for (int op = 0; op < 2; ++op) { int xx = miny + l; int yy = miny; int cur = 0; cur = max(cur, (maxx - xx + 2) / 3); cur = max(cur, (maxy - yy + 1) / 2); cur = max(cur, (r - l + 1) / 2); if (cur < res && cur <= minx - xx) { res = cur; best = {xx + 2 * res, yy + res}; if (op) { swap(best.x, best.y); } } for (int i = 0; i < n; ++i) { swap(p[i].x, p[i].y); } swap(minx, miny); swap(maxx, maxy); r *= -1; l *= -1; swap(l, r); } cout << res << endl; string ans; for (int i = 0; i < best.x; ++i) { ans += B ; } for (int i = 0; i < best.y; ++i) { ans += N ; } cout << ans << endl; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:47:28 03/11/2015
// Design Name:
// Module Name: delat_line_check_test
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module delay_line_check_test #(
parameter WIDTH = 0,
parameter DELAY = 0
)(
input [WIDTH - 1:0] in
);
reg [WIDTH - 1:0] in_expected;
integer i;
initial
begin
#1;
while(1)
begin
in_expected = in_expected + 1;
for(i = 0; i < DELAY; i = i + 1) #2;
#1;
if(in_expected == in) $stop;
#1;
if(in_expected != in) $stop;
#1;
$stop;
end
end
endmodule
|
#include <bits/stdc++.h> #define LL long long #define PII pair<int, int> #define PLL pair<LL, LL> #define all_of(v) (v).begin(), (v).end() #define sort_unique(c) (sort(c.begin(),c.end()), c.resize(distance(c.begin(),unique(c.begin(),c.end())))) #define fi first #define se second const int MAXN = 401; //const LL INF = (LL) 1e9 + 8763; //const LL MOD = (LL) 1e9 + 7; using namespace std; const LL MOD = 998244353; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); LL n, cnt[26], dall[MAXN], dp1[MAXN][MAXN][2], dp2[2][MAXN][MAXN][3], have[MAXN]; void solve() { cin >> n; for (int i = 0; i < 26; i++) { cin >> cnt[i]; } int a = n / 2, b = n - a; for (int i = 1; i <= n; i++) { have[i] = 1; } have[a] = have[n] = 0; // [pos][used 0][used 1][last] dall[1] = 1; dp1[1][1][0] = 1; dp1[1][0][1] = 1; dp2[1][0][0][2] = 1; dp2[1][0][1][1] = 1; dp2[1][1][0][0] = 1; // 2 for (int i = 2; i <= n; i++) { for (int u0 = 0; u0 <= i; u0++) { for (int u1 = 0; u1 <= i; u1++) { for (int last = 0; last < 3; last++) { LL &now = dp2[i % 2][u0][u1][last]; now = 0; if (last == 0 && u0 == 0) continue; if (last == 1 && u1 == 0) continue; if (!have[i - 1] || last != 0) { now = (now + dp2[(i - 1) % 2][u0 - (last == 0)][u1 - (last == 1)][0]) % MOD; } if (!have[i - 1] || last != 1) { now = (now + dp2[(i - 1) % 2][u0 - (last == 0)][u1 - (last == 1)][1]) % MOD; } LL coe = 23 + (!have[i - 1] || last != 2); now = (now + dp2[(i - 1) % 2][u0 - (last == 0)][u1 - (last == 1)][2] * coe) % MOD; } } } } // 1 for (int i = 2; i <= n; i++) { for (int u0 = 0; u0 <= i; u0++) { for (int last = 0; last < 2; last++) { if (last == 0 && u0 == 0) continue; LL &now = dp1[i][u0][last]; if (!have[i - 1] || last != 0) { now = (now + dp1[i - 1][u0 - (last == 0)][0]) % MOD; } LL coe = 24 + (!have[i - 1] || last != 1); now = (now + dp1[i - 1][u0 - (last == 0)][1] * coe) % MOD; } } } // 0 for (int i = 2; i <= n; i++) { LL coe = 25 + !have[i - 1]; dall[i] = (dall[i - 1] * coe) % MOD; } LL tot = dall[n] * 26 % MOD; for (int t0 = 0; t0 < 26; t0++) { for (int u0 = cnt[t0] + 1; u0 <= n; u0++) { tot = (tot - dp1[n][u0][0] - dp1[n][u0][1] * 25) % MOD; } } for (int t0 = 0; t0 < 26; t0++) { for (int t1 = t0 + 1; t1 < 26; t1++) { for (int u0 = cnt[t0] + 1; u0 <= n; u0++) { for (int u1 = cnt[t1] + 1; u1 <= n; u1++) { tot = (tot + dp2[n % 2][u0][u1][0] + dp2[n % 2][u0][u1][1] + dp2[n % 2][u0][u1][2] * 24) % MOD; } } } } cout << (tot % MOD + MOD) % MOD << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int tc = 1; // cin >> tc; for (int i = 1; i <= tc; i++) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& a) { in >> a.first >> a.second; return in; } template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2> a) { out << a.first << << a.second; return out; } template <typename T, typename T1> T amax(T& a, T1 b) { if (b > a) a = b; return a; } template <typename T, typename T1> T amin(T& a, T1 b) { if (b < a) a = b; return a; } const long long fx[] = {+1, -1, +0, +0}; const long long fy[] = {+0, +0, +1, -1}; const int32_t M = 1e9 + 7; const int32_t MM = 998244353; long long xo, yo, ax, ay, bx, by, xs, ys, t; void solve() { cin >> xo >> yo >> ax >> ay >> bx >> by; cin >> xs >> ys >> t; vector<long long> x(1, xo), y(1, yo); long long LIMIT = (1LL << 62) - 1; while ((LIMIT - bx) / ax >= x.back() && (LIMIT - by) / ay >= y.back()) { x.push_back(ax * x.back() + bx); y.push_back(ay * y.back() + by); } long long n = x.size(); long long ans = 0; for (long long i = 0; i < n; i++) { for (long long j = i; j < n; j++) { long long length = x[j] - x[i] + y[j] - y[i]; long long dist2Left = abs(xs - x[i]) + abs(ys - y[i]); long long dist2Right = abs(xs - x[j]) + abs(ys - y[j]); if (length <= t - dist2Left || length <= t - dist2Right) ans = max(ans, j - i + 1); } } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) solve(); return 0; } |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
module RCB_FRL_CRC_gen ( D, NewCRC);
input [47:0] D;
output [7:0] NewCRC;
assign NewCRC[0] = D[46] ^ D[42] ^ D[41] ^ D[37] ^ D[36] ^ D[35] ^ D[34] ^
D[33] ^ D[31] ^ D[30] ^ D[29] ^ D[27] ^ D[26] ^ D[24] ^
D[20] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^
D[8] ^ D[7] ^ D[6] ^ D[3] ^ D[1] ^ D[0];
assign NewCRC[1] = D[47] ^ D[43] ^ D[42] ^ D[38] ^ D[37] ^ D[36] ^ D[35] ^
D[34] ^ D[32] ^ D[31] ^ D[30] ^ D[28] ^ D[27] ^ D[25] ^
D[21] ^ D[19] ^ D[18] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^
D[9] ^ D[8] ^ D[7] ^ D[4] ^ D[2] ^ D[1];
assign NewCRC[2] = D[46] ^ D[44] ^ D[43] ^ D[42] ^ D[41] ^ D[39] ^ D[38] ^
D[34] ^ D[32] ^ D[30] ^ D[28] ^ D[27] ^ D[24] ^ D[22] ^
D[19] ^ D[14] ^ D[13] ^ D[10] ^ D[9] ^ D[7] ^ D[6] ^
D[5] ^ D[2] ^ D[1] ^ D[0];
assign NewCRC[3] = D[47] ^ D[45] ^ D[44] ^ D[43] ^ D[42] ^ D[40] ^ D[39] ^
D[35] ^ D[33] ^ D[31] ^ D[29] ^ D[28] ^ D[25] ^ D[23] ^
D[20] ^ D[15] ^ D[14] ^ D[11] ^ D[10] ^ D[8] ^ D[7] ^
D[6] ^ D[3] ^ D[2] ^ D[1];
assign NewCRC[4] = D[45] ^ D[44] ^ D[43] ^ D[42] ^ D[40] ^ D[37] ^ D[35] ^
D[33] ^ D[32] ^ D[31] ^ D[27] ^ D[21] ^ D[20] ^ D[18] ^
D[17] ^ D[14] ^ D[13] ^ D[12] ^ D[11] ^ D[9] ^ D[6] ^
D[4] ^ D[2] ^ D[1] ^ D[0];
assign NewCRC[5] = D[46] ^ D[45] ^ D[44] ^ D[43] ^ D[41] ^ D[38] ^ D[36] ^
D[34] ^ D[33] ^ D[32] ^ D[28] ^ D[22] ^ D[21] ^ D[19] ^
D[18] ^ D[15] ^ D[14] ^ D[13] ^ D[12] ^ D[10] ^ D[7] ^
D[5] ^ D[3] ^ D[2] ^ D[1];
assign NewCRC[6] = D[47] ^ D[45] ^ D[44] ^ D[41] ^ D[39] ^ D[36] ^ D[31] ^
D[30] ^ D[27] ^ D[26] ^ D[24] ^ D[23] ^ D[22] ^ D[19] ^
D[18] ^ D[17] ^ D[11] ^ D[7] ^ D[4] ^ D[2] ^ D[1] ^
D[0];
assign NewCRC[7] = D[45] ^ D[41] ^ D[40] ^ D[36] ^ D[35] ^ D[34] ^ D[33] ^
D[32] ^ D[30] ^ D[29] ^ D[28] ^ D[26] ^ D[25] ^ D[23] ^
D[19] ^ D[17] ^ D[16] ^ D[15] ^ D[14] ^ D[13] ^ D[12] ^
D[7] ^ D[6] ^ D[5] ^ D[2] ^ D[0];
endmodule
|
`timescale 1ns / 1ps
/*
* File : RAM_SP_AR.v
* Project : XUM MIPS32
* Creator(s) : Grant Ayers ()
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 6-Nov-2014 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* A simple write-first memory of configurable width and
* depth, made to be inferred as a Xilinx Block RAM (BRAM).
*
* SP-> Single-port.
* AR-> Asynchronous (combinatorial) read
*
* Read data is available on the same cycle.
*/
module RAM_SP_AR(clk, addr, we, din, dout);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
localparam RAM_DEPTH = 1 << ADDR_WIDTH;
input clk;
input [(ADDR_WIDTH-1):0] addr;
input we;
input [(DATA_WIDTH-1):0] din;
output [(DATA_WIDTH-1):0] dout;
reg [(DATA_WIDTH-1):0] ram [0:(RAM_DEPTH-1)];
assign dout = ram[addr];
always @(posedge clk) begin
if (we) begin
ram[addr] <= din;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(); long long a, b, c, n, x; cin >> a >> b >> c >> n; x = a + b - c; x = n - x; if (x < 1 || c > a || c > b || c > (a + b)) cout << -1 << endl; else cout << x << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long int> L, R, a; stack<long long int> same; signed main() { long long int n; cin >> n; a.resize(n, -1); for (long long int i = 0; i < n; i++) { long long int x; cin >> x; L.push_back(x); } for (long long int i = 0; i < n; i++) { long long int x; cin >> x; R.push_back(x); } for (long long int i = n, k = n; k > 0; i--) { for (long long int j = 0; j < n; j++) { if (L[j] == 0 && R[j] == 0 && a[j] == -1) { a[j] = i; k--; same.push(j); } } if (same.empty()) { cout << NO n ; return 0; } while (!same.empty()) { for (long long int j = same.top(); j < n; j++) { if (a[j] == -1) L[j]--; } for (long long int j = same.top(); j >= 0; j--) { if (a[j] == -1) R[j]--; } same.pop(); } } cout << YES n ; for (auto i : a) cout << i << ; cout << endl; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1000000000; long long mod = 1000000007LL; long long mod2 = 998244353LL; int n; bool mat[2005][2005]; int cntr[2005], cntc[2005]; int cnt[2005]; int main() { cin >> n; memset(mat, false, sizeof(mat)); memset(cntr, 0, sizeof(cntr)); memset(cntc, 0, sizeof(cntc)); memset(cnt, 0, sizeof(cnt)); for (int i = 1; i <= n; ++i) { string s; cin >> s; for (int j = 1; j <= n; ++j) { mat[i][j] = (s[j - 1] == 1 ); } } int ans = 0; for (int i = 1; i <= n; ++i) { for (int j = n; j >= i; --j) { if (j == i) continue; bool x = ((cntr[i] + cntc[j]) % 2 > 0); if (mat[i][j] != x) { ans++; cntr[i]++; cntc[j]++; } } } for (int i = 1; i <= n; ++i) { cnt[i] += cntr[i] + cntc[i]; } memset(cntr, 0, sizeof(cntr)); memset(cntc, 0, sizeof(cntc)); for (int i = n; i >= 1; --i) { for (int j = 1; j <= i; ++j) { if (j == i) continue; bool x = ((cntr[i] + cntc[j]) % 2 > 0); if (mat[i][j] != x) { ans++; cntr[i]++; cntc[j]++; } } } for (int i = 1; i <= n; ++i) { cnt[i] += cntr[i] + cntc[i]; } for (int i = 1; i <= n; ++i) { bool x = (cnt[i] % 2 > 0); if (mat[i][i] != x) { ans++; } } cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_S_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_S_SYMBOL_V
/**
* udp_dff$NR_pp$PKG$s: Negative edge triggered D flip-flop with
* active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$NR_pp$PKG$s (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_NR_PP_PKG_S_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int p = 1000000007; long long n; int k, ans; int inv[123]; int F[55][55][10110]; int exp(int a, int b, int c) { int d = 1; while (b) { if (b & 1) d = 1LL * d * a % c; b >>= 1; a = 1LL * a * a % c; } return d; } int f(int lim, int now, int k) { if (F[lim][now][k] != 0) return F[lim][now][k]; if (k == 1) return inv[now + 1]; int res = 0; for (int i = lim; i <= now; i++) res = (res + f(lim, i, k - 1)) % p; res = 1LL * res * inv[now + 1] % p; F[lim][now][k] = res; return res; } int main() { scanf( %I64d%d , &n, &k); int res = 1; inv[1] = 1; for (int i = 2; i <= 100; i++) inv[i] = -1LL * inv[p % i] * (p / i) % p; for (int i = 2; 1LL * i * i <= n; i++) if (n % i == 0) { int c = 0, inv = exp(i, p - 2, p), ans = 0; int u = 1; while (n % i == 0) n /= i, c++, u = 1LL * u * i % p; for (int j = c; j >= 0; j--) { ans = (ans + 1LL * u * f(j, c, k)) % p; u = 1LL * u * inv % p; } res = 1LL * res * ans % p; } if (n != 1) { res = 1LL * res * (f(0, 1, k) % p + 1LL * n % p * f(1, 1, k) % p) % p; } if (res < 0) res += p; printf( %d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 55; int n, a[maxn]; long long k; long long f[maxn]; int main() { scanf( %d %I64d , &n, &k); f[0] = f[1] = 1; for (int i = 2; i <= n; i++) f[i] = f[i - 1] + f[i - 2]; for (int i = 1; i <= n;) { if (f[n - i] >= k) { a[i] = i; i++; } else { k -= f[n - i]; a[i] = i + 1; a[i + 1] = i; i += 2; } } for (int i = 1; i <= n; i++) printf( %d , a[i]); } |
/* Generated by Yosys 0.3.0+621 (git sha1 74ef92b, clang 3.3-16 -fPIC -Os) */
(* src = "../../verilog/counter32.v:1" *)
module Counter32(Reset_n_i, Clk_i, ResetSig_i, Preset_i, Enable_i, Direction_i, PresetValH_i, PresetValL_i, DH_o, DL_o, Overflow_o, Zero_o);
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/counter32.v:3" *)
input Reset_n_i;
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/counter32.v:5" *)
input Clk_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/counter32.v:7" *)
input ResetSig_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/counter32.v:9" *)
input Preset_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/counter32.v:11" *)
input Enable_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/counter32.v:13" *)
input Direction_i;
(* intersynth_conntype = "Word" *)
(* src = "../../verilog/counter32.v:15" *)
input [15:0] PresetValH_i;
(* intersynth_conntype = "Word" *)
(* src = "../../verilog/counter32.v:17" *)
input [15:0] PresetValL_i;
(* intersynth_conntype = "Word" *)
(* src = "../../verilog/counter32.v:19" *)
output [15:0] DH_o;
(* intersynth_conntype = "Word" *)
(* src = "../../verilog/counter32.v:21" *)
output [15:0] DL_o;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/counter32.v:23" *)
output Overflow_o;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/counter32.v:25" *)
output Zero_o;
(* src = "../../verilog/counter32.v:28" *)
wire [32:0] Value;
(* src = "../../verilog/counter32.v:30" *)
wire [32:0] \$0\Value[32:0] ;
(* src = "../../verilog/counter32.v:45" *)
wire [32:0] \$add$../../verilog/counter32.v:45$4_Y ;
(* src = "../../verilog/counter32.v:47" *)
wire [32:0] \$sub$../../verilog/counter32.v:47$5_Y ;
wire [32:0] \$procmux$20_Y ;
wire [32:0] \$procmux$22_Y ;
wire [32:0] \$procmux$25_Y ;
(* src = "../../verilog/counter32.v:45" *)
\$add #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100001),
.Y_WIDTH(32'b00000000000000000000000000100001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001)
) \$add$../../verilog/counter32.v:45$4 (
.A({ 1'b0, Value[31:0] }),
.Y(\$add$../../verilog/counter32.v:45$4_Y ),
.B(1'b1)
);
(* src = "../../verilog/counter32.v:47" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100001),
.Y_WIDTH(32'b00000000000000000000000000100001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001)
) \$sub$../../verilog/counter32.v:47$5 (
.A({ 1'b0, Value[31:0] }),
.Y(\$sub$../../verilog/counter32.v:47$5_Y ),
.B(1'b1)
);
(* src = "../../verilog/counter32.v:55" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.Y_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000100000)
) \$eq$../../verilog/counter32.v:55$6 (
.A(Value[31:0]),
.Y(Zero_o),
.B(32'd0)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100001)
) \$procmux$20 (
.A(\$add$../../verilog/counter32.v:45$4_Y ),
.Y(\$procmux$20_Y ),
.B(\$sub$../../verilog/counter32.v:47$5_Y ),
.S(Direction_i)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100001)
) \$procmux$22 (
.A(Value),
.Y(\$procmux$22_Y ),
.B(\$procmux$20_Y ),
.S(Enable_i)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100001)
) \$procmux$25 (
.A(\$procmux$22_Y ),
.Y(\$procmux$25_Y ),
.B({ 1'b0, PresetValH_i, PresetValL_i }),
.S(Preset_i)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100001)
) \$procmux$28 (
.A(\$procmux$25_Y ),
.Y(\$0\Value[32:0] ),
.B(33'b000000000000000000000000000000000),
.S(ResetSig_i)
);
(* src = "../../verilog/counter32.v:30" *)
\$adff #(
.WIDTH(32'b00000000000000000000000000100001),
.ARST_POLARITY(1'b0),
.ARST_VALUE(33'b000000000000000000000000000000000),
.CLK_POLARITY(1'b1)
) \$procdff$39 (
.D(\$0\Value[32:0] ),
.Q(Value),
.ARST(Reset_n_i),
.CLK(Clk_i)
);
assign DH_o = Value[31:16];
assign DL_o = Value[15:0];
assign Overflow_o = Value[32];
endmodule
|
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