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import bsg_vscale_pkg::*;
`include "bsg_defines.v"
module bsg_vscale_hasti_converter
( input clk_i
,input reset_i
// proc
,input [1:0][haddr_width_p-1:0] haddr_i
,input [1:0] hwrite_i
,input [1:0][hsize_width_p-1:0] hsize_i
,input [1:0][hburst_width_p-1:0] hburst_i
,input [1:0] hmastlock_i
,input [1:0][hprot_width_p-1:0] hprot_i
,input [1:0][htrans_width_p-1:0] htrans_i
,input [1:0][hdata_width_p-1:0] hwdata_i
,output [1:0][hdata_width_p-1:0] hrdata_o
,output [1:0] hready_o
,output [1:0] hresp_o
// memory
,output [1:0] m_v_o
,output [1:0] m_w_o
,output [1:0] [haddr_width_p-1:0] m_addr_o
,output [1:0] [hdata_width_p-1:0] m_data_o
,output [1:0] [(hdata_width_p>>3)-1:0] m_mask_o
,input [1:0] m_yumi_i
,input [1:0] m_v_i
,input [1:0] [hdata_width_p-1:0] m_data_i
);
logic [1:0][hsize_width_p-1:0] wsize_r;
logic [1:0][haddr_width_p-1:0] addr_r;
logic [1:0] w_r;
logic [1:0] rvalid_r;
logic [1:0] trans_r;
logic [1:0][hdata_nbytes_p-1:0] wmask;
genvar i;
for(i=0; i<2; i=i+1)
begin
assign wmask[i] = ((wsize_r[i] == 0) ?
hdata_nbytes_p'(1)
: ((wsize_r[i] == 1) ?
hdata_nbytes_p'(3)
: hdata_nbytes_p'(15)
)
) << addr_r[i][1:0];
always_ff @(posedge clk_i)
begin
if(reset_i)
begin
addr_r[i] <= 0;
wsize_r[i] <= 0;
w_r[i] <= 0;
rvalid_r[i] <= 1'b0;
trans_r[i] <= 1'b0;
end
else
begin
rvalid_r[i] <= ~w_r[i] & ~m_yumi_i[i];
if(~trans_r[i] | (w_r[i] & m_yumi_i[i]) | (~w_r[i] & m_v_i[i]))
begin
addr_r[i] <= haddr_i[i];
wsize_r[i] <= hsize_i[i];
w_r[i] <= hwrite_i[i];
rvalid_r[i] <= ~hwrite_i[i];
trans_r[i] <= (htrans_i[i] == htrans_nonseq_p) & ~(m_v_o[i] & ~m_w_o[i] & m_yumi_i[i]);
end
end
end
assign m_v_o[i] = (~reset_i) & ((trans_r[i] & (w_r[i] | rvalid_r[i]))
| (~trans_r[i] & ~hwrite_i[i] & (htrans_i[i] == htrans_nonseq_p))
);
assign m_w_o[i] = w_r[i];
assign m_addr_o[i] = trans_r[i] ? addr_r[i] : haddr_i[i];
assign m_data_o[i] = hwdata_i[i];
assign m_mask_o[i] = ~wmask[i];
assign hrdata_o[i] = m_data_i[i];
assign hready_o[i] = (w_r[i] & m_yumi_i[i]) | (~w_r[i] & m_v_i[i]);
assign hresp_o[i] = hresp_okay_p;
end
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet MAC
*/
module eth_mac_10g #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter ENABLE_PADDING = 1,
parameter ENABLE_DIC = 1,
parameter MIN_FRAME_LENGTH = 64,
parameter PTP_PERIOD_NS = 4'h6,
parameter PTP_PERIOD_FNS = 16'h6666,
parameter TX_PTP_TS_ENABLE = 0,
parameter TX_PTP_TS_WIDTH = 96,
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE,
parameter TX_PTP_TAG_WIDTH = 16,
parameter RX_PTP_TS_ENABLE = 0,
parameter RX_PTP_TS_WIDTH = 96,
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1,
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] tx_axis_tdata,
input wire [KEEP_WIDTH-1:0] tx_axis_tkeep,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire [TX_USER_WIDTH-1:0] tx_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] rx_axis_tdata,
output wire [KEEP_WIDTH-1:0] rx_axis_tkeep,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire [RX_USER_WIDTH-1:0] rx_axis_tuser,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_rxd,
input wire [CTRL_WIDTH-1:0] xgmii_rxc,
output wire [DATA_WIDTH-1:0] xgmii_txd,
output wire [CTRL_WIDTH-1:0] xgmii_txc,
/*
* PTP
*/
input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts,
input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts,
output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,
output wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag,
output wire tx_axis_ptp_ts_valid,
/*
* Status
*/
output wire [1:0] tx_start_packet,
output wire tx_error_underflow,
output wire [1:0] rx_start_packet,
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
// bus width assertions
initial begin
if (DATA_WIDTH != 32 && DATA_WIDTH != 64) begin
$error("Error: Interface width must be 32 or 64");
$finish;
end
if (KEEP_WIDTH * 8 != DATA_WIDTH || CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
end
generate
if (DATA_WIDTH == 64) begin
axis_xgmii_rx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_xgmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.start_packet(rx_start_packet),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
axis_xgmii_tx_64 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_xgmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet),
.error_underflow(tx_error_underflow)
);
end else begin
axis_xgmii_rx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.USER_WIDTH(RX_USER_WIDTH)
)
axis_xgmii_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.m_axis_tdata(rx_axis_tdata),
.m_axis_tkeep(rx_axis_tkeep),
.m_axis_tvalid(rx_axis_tvalid),
.m_axis_tlast(rx_axis_tlast),
.m_axis_tuser(rx_axis_tuser),
.ptp_ts(rx_ptp_ts),
.start_packet(rx_start_packet[0]),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
assign rx_start_packet[1] = 1'b0;
axis_xgmii_tx_32 #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.USER_WIDTH(TX_USER_WIDTH)
)
axis_xgmii_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.s_axis_tdata(tx_axis_tdata),
.s_axis_tkeep(tx_axis_tkeep),
.s_axis_tvalid(tx_axis_tvalid),
.s_axis_tready(tx_axis_tready),
.s_axis_tlast(tx_axis_tlast),
.s_axis_tuser(tx_axis_tuser),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.ptp_ts(tx_ptp_ts),
.m_axis_ptp_ts(tx_axis_ptp_ts),
.m_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.m_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.ifg_delay(ifg_delay),
.start_packet(tx_start_packet[0])
);
assign tx_start_packet[1] = 1'b0;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); long long n, k; cin >> n >> k; if (k < (n * n + n) / 2) return cout << -1, 0; long long t = k; k -= (n * n + n) / 2; long long a[n + 1]; for (long long i = 1; i <= n; i++) a[i] = i; for (long long i = 1; i <= n / 2; i++) { if (k - (n + 1 - 2 * i) > 0) { swap(a[i], a[n - i + 1]); k -= (n + 1 - 2 * i); } else { swap(a[i], a[i + k]); cout << t << endl; for (long long i = 1; i <= n; i++) cout << i << ; cout << endl; for (long long i = 1; i <= n; i++) cout << a[i] << ; return 0; } } cout << t - k << endl; for (long long i = 1; i <= n; i++) cout << i << ; cout << endl; for (long long i = 1; i <= n; i++) cout << a[i] << ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O41AI_BEHAVIORAL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_BEHAVIORAL_V |
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg_hwbrk.v
//
// *Module Description:
// Hardware Breakpoint / Watchpoint module
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 175 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2013-01-30 22:21:42 +0100 (Mit, 30. Jän 2013) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_dbg_hwbrk (
// OUTPUTs
brk_halt, // Hardware breakpoint command
brk_pnd, // Hardware break/watch-point pending
brk_dout, // Hardware break/watch-point register data input
// INPUTs
brk_reg_rd, // Hardware break/watch-point register read select
brk_reg_wr, // Hardware break/watch-point register write select
dbg_clk, // Debug unit clock
dbg_din, // Debug register data input
dbg_rst, // Debug unit reset
decode_noirq, // Frontend decode instruction
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
pc // Program counter
);
// OUTPUTs
//=========
output brk_halt; // Hardware breakpoint command
output brk_pnd; // Hardware break/watch-point pending
output [15:0] brk_dout; // Hardware break/watch-point register data input
// INPUTs
//=========
input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
input dbg_clk; // Debug unit clock
input [15:0] dbg_din; // Debug register data input
input dbg_rst; // Debug unit reset
input decode_noirq; // Frontend decode instruction
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] pc; // Program counter
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
wire range_wr_set;
wire range_rd_set;
wire addr1_wr_set;
wire addr1_rd_set;
wire addr0_wr_set;
wire addr0_rd_set;
parameter BRK_CTL = 0,
BRK_STAT = 1,
BRK_ADDR0 = 2,
BRK_ADDR1 = 3;
//=============================================================================
// 2) CONFIGURATION REGISTERS
//=============================================================================
// BRK_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE
//
// ACCESS_MODE: - 00 : Disabled
// - 01 : Detect read access
// - 10 : Detect write access
// - 11 : Detect read/write access
// NOTE: '10' & '11' modes are not supported on the instruction flow
//
// BREAK_EN: - 0 : Watchmode enable
// - 1 : Break enable
//
// INST_EN: - 0 : Checks are done on the execution unit (data flow)
// - 1 : Checks are done on the frontend (instruction flow)
//
// RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1
// - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range
//
//-----------------------------------------------------------------------------
reg [4:0] brk_ctl;
wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_ctl <= 5'h00;
else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
// BRK_STAT Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD
//-----------------------------------------------------------------------------
reg [5:0] brk_stat;
wire brk_stat_wr = brk_reg_wr[BRK_STAT];
wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE,
range_rd_set & `HWBRK_RANGE,
addr1_wr_set, addr1_rd_set,
addr0_wr_set, addr0_rd_set};
wire [5:0] brk_stat_clr = ~dbg_din[5:0];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_stat <= 6'h00;
else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
else brk_stat <= (brk_stat | brk_stat_set);
wire [7:0] brk_stat_full = {2'b00, brk_stat};
wire brk_pnd = |brk_stat;
// BRK_ADDR0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr0;
wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr0 <= 16'h0000;
else if (brk_addr0_wr) brk_addr0 <= dbg_din;
// BRK_ADDR1/DATA0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr1;
wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr1 <= 16'h0000;
else if (brk_addr1_wr) brk_addr1 <= dbg_din;
//============================================================================
// 3) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] brk_ctl_rd = {8'h00, brk_ctl_full} & {16{brk_reg_rd[BRK_CTL]}};
wire [15:0] brk_stat_rd = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}};
wire [15:0] brk_addr0_rd = brk_addr0 & {16{brk_reg_rd[BRK_ADDR0]}};
wire [15:0] brk_addr1_rd = brk_addr1 & {16{brk_reg_rd[BRK_ADDR1]}};
wire [15:0] brk_dout = brk_ctl_rd |
brk_stat_rd |
brk_addr0_rd |
brk_addr1_rd;
//============================================================================
// 4) BREAKPOINT / WATCHPOINT GENERATION
//============================================================================
// Comparators
//---------------------------
// Note: here the comparison logic is instanciated several times in order
// to improve the timings, at the cost of a bit more area.
wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
wire equ_i_addr0 = decode_noirq & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_i_addr1 = decode_noirq & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_i_range = decode_noirq & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
// Detect accesses
//---------------------------
// Detect Instruction read access
wire i_addr0_rd = equ_i_addr0 & brk_ctl[`BRK_I_EN];
wire i_addr1_rd = equ_i_addr1 & brk_ctl[`BRK_I_EN];
wire i_range_rd = equ_i_range & brk_ctl[`BRK_I_EN];
// Detect Execution-Unit write access
wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
// Detect DATA read access
wire d_addr0_rd = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
wire d_addr1_rd = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
wire d_range_rd = equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
// Set flags
assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd);
assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr;
assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd);
assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr1_wr;
assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd | i_range_rd);
assign range_wr_set = brk_ctl[`BRK_MODE_WR] & d_range_wr;
// Break CPU
assign brk_halt = brk_ctl[`BRK_EN] & |brk_stat_set;
endmodule // omsp_dbg_hwbrk
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
#include <bits/stdc++.h> using namespace std; void setIO() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } const long long N = 3e2 + 0; const long long M = 5e5 + 5; const long long L = 2e1 + 1; const long long inf = 9e17; const long long mod = 1e9 + 7; long long xyz = 1; long long n, k; long long dp[N][N]; long long fac[N]; long long inv[N]; long long chs[N][N]; long long pwr[2][N]; long long bin(long long b, long long e) { return b == k ? pwr[0][e] : pwr[1][e]; } long long cal(long long b, long long e) { if (e == 0) return 1; if (e == 1) return b; if (e == 2) return b * b % mod; return cal(cal(b, e / 2), 2) * cal(b, e % 2) % mod; } void prc(long long n, long long k) { chs[n][k] = fac[n] * inv[k] % mod * inv[n - k] % mod; } void cmp(long long b, long long e) { if (b == k - 0) { pwr[0][e] = cal(b, e); } if (b == k - 1) { pwr[1][e] = cal(b, e); } } long long ncr(long long n, long long k) { return chs[n][k]; } void run() { cin >> n >> k; fac[0] = 1; inv[0] = 1; for (long long i = 1; i <= n; i++) { fac[i] = fac[i - 1] * i % mod; inv[i] = inv[i - 1] * cal(i, mod - 2) % mod; } for (long long i = 0; i <= n; i++) for (long long j = 0; j <= i; j++) prc(i, j); for (long long i = 0; i <= n; i++) cmp(k, i), cmp(k - 1, i); for (long long i = 1; i <= n; i++) dp[1][i] = ncr(n, i) * bin(k - 1, n - i) % mod; for (long long i = 2; i <= n; i++) { for (long long j = 1; j <= n; j++) { dp[i][j] = (bin(k, j) - bin(k - 1, j) + mod) * bin(k - 1, n - j) % mod * dp[i - 1][j] % mod; for (long long x = 1; x < j; x++) { dp[i][j] += bin(k - 1, n - j) * bin(k, x) % mod * ncr(n - x, j - x) % mod * dp[i - 1][x] % mod; dp[i][j] %= mod; } } } cout << dp[n][n] << endl; } signed main() { setIO(); while (xyz--) run(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXTP_1_V
`define SKY130_FD_SC_HD__SEDFXTP_1_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog wrapper for sedfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sedfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sedfxtp_1 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sedfxtp_1 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXTP_1_V
|
#include <bits/stdc++.h> using namespace std; bool gt(long double a, long double b) { return a > b + 1e-12; } long long a, b, x; int main() { int n; cin >> n; while (n--) { string s; cin >> s; if (s == UR || s == DL ) a++; else if (s == UL || s == DR ) b++; else x++; } cout << (x + 1 + a) * (x + 1 + b) << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NOR3_BLACKBOX_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int a[10][10], b[5010], c[51]; string s[110][110]; int main() { int maxx = 0; int summ = 0; for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { cin >> a[i][j]; summ = summ + a[i][j]; } } a[1][1] = summ / 6; int x = a[1][1] + a[1][0] + a[1][2]; a[2][2] = abs(x - a[0][2] - a[1][2]); a[0][0] = abs(x - a[2][2] - a[1][1]); cout << endl; for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { cout << a[i][j] << ; } cout << endl; } return 0; } |
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_tb_test_addr_gen.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// The address for the memory and the various user commands can be given
// through this module. It instantiates the block RAM which stores all the
// information in particular sequence. The data stored should be in a
// sequence starting from LSB:
// column address, row address, bank address, commands.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_tb_test_addr_gen #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter BANK_WIDTH = 2,
parameter COL_WIDTH = 10,
parameter ROW_WIDTH = 14
)
(
input clk,
input rst,
input wr_addr_en,
output reg [2:0] app_af_cmd,
output reg [30:0] app_af_addr,
output reg app_af_wren
);
// RAM initialization patterns
// NOTE: Not all bits in each range may be used (e.g. in an application
// using only 10 column bits, bits[11:10] of ROM output will be unused
// COLUMN = [11:0]
// ROW = [27:12]
// BANK = [30:28]
// CHIP = [31]
// COMMAND = [35:32]
localparam RAM_INIT_00 = {128'h800020C0_800020C8_000020D0_000020D8,
128'h000010E0_000010E8_800010F0_800010F8};
localparam RAM_INIT_01 = {128'h800020C0_800020C8_000020D0_000020D8,
128'h000010E0_000010E8_800010F0_800010F8};
localparam RAM_INIT_02 = {128'h100040C0_100040C8_900040D0_900040D8,
128'h900030E0_900030E8_100030F0_100030F8};
localparam RAM_INIT_03 = {128'h100040C0_100040C8_900040D0_900040D8,
128'h900030E0_900030E8_100030F0_100030F8};
localparam RAM_INIT_04 = {128'hA00060C0_200060C8_200060D0_A00060D8,
128'h200050E0_A00050E8_A00050F0_200050F8};
localparam RAM_INIT_05 = {128'hA00060C0_200060C8_200060D0_A00060D8,
128'h200050E0_A00050E8_A00050F0_200050F8};
localparam RAM_INIT_06 = {128'h300080C0_B00080C8_B00080D0_300080D8,
128'hB00070E0_300070E8_300070F0_B00070F8};
localparam RAM_INIT_07 = {128'h300080C0_B00080C8_B00080D0_300080D8,
128'hB00070E0_300070E8_300070F0_B00070F8};
localparam RAM_INITP_00 = {128'h11111111_00000000_11111111_00000000,
128'h11111111_00000000_11111111_00000000};
reg wr_addr_en_r1;
reg [2:0] af_cmd_r;
reg [30:0] af_addr_r;
reg af_wren_r;
wire [15:0] ramb_addr;
wire [35:0] ramb_dout;
reg rst_r
/* synthesis syn_preserve = 1 */;
reg rst_r1
/* synthesis syn_maxfan = 10 */;
reg [5:0] wr_addr_cnt;
reg wr_addr_en_r0;
// XST attributes for local reset "tree"
// synthesis attribute shreg_extract of rst_r is "no";
// synthesis attribute shreg_extract of rst_r1 is "no";
// synthesis attribute equivalent_register_removal of rst_r is "no"
//*****************************************************************
// local reset "tree" for controller logic only. Create this to ease timing
// on reset path. Prohibit equivalent register removal on RST_R to prevent
// "sharing" with other local reset trees (caution: make sure global fanout
// limit is set to larger than fanout on RST_R, otherwise SLICES will be
// used for fanout control on RST_R.
always @(posedge clk) begin
rst_r <= rst;
rst_r1 <= rst_r;
end
//***************************************************************************
// ADDRESS generation for Write and Read Address FIFOs:
// ROM with address patterns
// 512x36 mode is used with addresses 0-127 for storing write addresses and
// addresses (128-511) for storing read addresses
// INIP_OO: read 1
// INIP_OO: write 0
//***************************************************************************
assign ramb_addr = {5'b00000, wr_addr_cnt, 5'b00000};
RAMB36 #
(
.READ_WIDTH_A (36),
.READ_WIDTH_B (36),
.DOA_REG (1), // register to help timing
.INIT_00 (RAM_INIT_00),
.INIT_01 (RAM_INIT_01),
.INIT_02 (RAM_INIT_02),
.INIT_03 (RAM_INIT_03),
.INIT_04 (RAM_INIT_04),
.INIT_05 (RAM_INIT_05),
.INIT_06 (RAM_INIT_06),
.INIT_07 (RAM_INIT_07),
.INITP_00 (RAM_INITP_00)
)
u_wr_rd_addr_lookup
(
.CASCADEOUTLATA (),
.CASCADEOUTLATB (),
.CASCADEOUTREGA (),
.CASCADEOUTREGB (),
.DOA (ramb_dout[31:0]),
.DOB (),
.DOPA (ramb_dout[35:32]),
.DOPB (),
.ADDRA (ramb_addr),
.ADDRB (16'h0000),
.CASCADEINLATA (),
.CASCADEINLATB (),
.CASCADEINREGA (),
.CASCADEINREGB (),
.CLKA (clk),
.CLKB (clk),
.DIA (32'b0),
.DIB (32'b0),
.DIPA (4'b0),
.DIPB (4'b0),
.ENA (1'b1),
.ENB (1'b1),
.REGCEA (1'b1),
.REGCEB (1'b1),
.SSRA (1'b0),
.SSRB (1'b0),
.WEA (4'b0000),
.WEB (4'b0000)
);
// register backend enables / FIFO enables
// write enable for Command/Address FIFO is generated 2 CC after WR_ADDR_EN
// (takes 2 CC to come out of test RAM)
always @(posedge clk)
if (rst_r1) begin
app_af_wren <= 1'b0;
wr_addr_en_r0 <= 1'b0;
wr_addr_en_r1 <= 1'b0;
af_wren_r <= 1'b0;
end else begin
wr_addr_en_r0 <= wr_addr_en;
wr_addr_en_r1 <= wr_addr_en_r0;
af_wren_r <= wr_addr_en_r1;
app_af_wren <= af_wren_r;
end
// FIFO addresses
always @(posedge clk) begin
af_addr_r <= {30{1'b0}};
af_addr_r[COL_WIDTH-1:0] <= ramb_dout[COL_WIDTH-1:0];
af_addr_r[ROW_WIDTH+COL_WIDTH-1:COL_WIDTH]
<= ramb_dout[ROW_WIDTH+11:12];
af_addr_r[BANK_WIDTH+ROW_WIDTH+COL_WIDTH-1:ROW_WIDTH+COL_WIDTH]
<= ramb_dout[BANK_WIDTH+27:28];
af_addr_r[BANK_WIDTH+ROW_WIDTH+COL_WIDTH]
<= ramb_dout[31];
// only reads and writes are supported for now
af_cmd_r <= {1'b0, ramb_dout[33:32]};
app_af_cmd <= af_cmd_r;
app_af_addr <= af_addr_r;
end
// address input for RAM
always @ (posedge clk)
if (rst_r1)
wr_addr_cnt <= 6'b000000;
else if (wr_addr_en)
wr_addr_cnt <= wr_addr_cnt + 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int binpow(long long int a, long long int b) { long long int res = 1; while (b > 0) { if (b & 1) res = res * a; a = a * a; b >>= 1; } return res; } void solve() { long long int n, k; cin >> n >> k; vector<long long int> a(n); for (long long int i = 0; i < a.size(); i++) { cin >> a[i]; } sort((a).begin(), (a).end()); long long int ans = a[n - 1]; for (long long int i = n - 2; i >= 0; i--) { if (a[i] == 0) continue; if (k > 0) { ans += a[i]; k--; } else { break; } } cout << ans << n ; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long int t = 1; cin >> t; while (t--) { solve(); } return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module rssi (input clock, input reset, input enable,
input [11:0] adc, output [15:0] rssi, output [15:0] over_count);
wire over_hi = (adc == 12'h7FF);
wire over_lo = (adc == 12'h800);
wire over = over_hi | over_lo;
reg [25:0] over_count_int;
always @(posedge clock)
if(reset | ~enable)
over_count_int <= #1 26'd0;
else
over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10];
assign over_count = over_count_int[25:10];
wire [11:0] abs_adc = adc[11] ? ~adc : adc;
reg [25:0] rssi_int;
always @(posedge clock)
if(reset | ~enable)
rssi_int <= #1 26'd0;
else
rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
assign rssi = rssi_int[25:10];
endmodule // rssi
|
#include <bits/stdc++.h> using namespace std; const int N = 510; const long long INF = 1e18; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, m, now; bitset<N> f[2][70][N], g, tmp; long long ans, fac[N]; int main() { n = read(); m = read(); for (int i = 1, u, v, w; i <= m; i++) { u = read(); v = read(); w = read(); f[w][0][u][v] = 1; } for (int i = 1; i <= 60; i++) for (int u = 1; u <= n; u++) for (int v = 1; v <= n; v++) { if (f[0][i - 1][u][v] != 0) f[0][i][u] |= f[1][i - 1][v]; if (f[1][i - 1][u][v] != 0) f[1][i][u] |= f[0][i - 1][v]; } if (f[0][60][1].count()) { puts( -1 ); return 0; } fac[0] = 1; for (int i = 1; i <= 60; i++) fac[i] = fac[i - 1] * 2; now = 0; tmp[1] = 1; for (int i = 60; i >= 0; i--) { g.reset(); for (int j = 1; j <= n; j++) if (tmp[j]) g |= f[now][i][j]; if (g.count() != 0) { now ^= 1; tmp = g; ans += fac[i]; } } if (ans > INF) puts( -1 ); else printf( %lld n , ans); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BA_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O21BA_BEHAVIORAL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BA_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int Get() { char c; while (c = getchar(), c < 0 || c > 9 ) ; int X = c - 48; while (c = getchar(), c >= 0 && c <= 9 ) X = X * 10 + c - 48; return X; } int Pow(int A, int B, int Mod) { if (!B) return 1; int T = Pow((long long)A * A % Mod, B / 2, Mod); if (B & 1) T = (long long)T * A % Mod; return T; } int main() { int N = Get(), M = Get(), Mod = Get(); static int G[600][600], In[600], Out[600]; memset(G, 0, sizeof(G)); memset(In, 0, sizeof(In)); memset(Out, 0, sizeof(Out)); for (int i = 0; i < M; i++) { int X = Get() - 1, Y = Get() - 1; G[X][Y]++; In[Y]++; Out[X]++; } static vector<int> List[600]; for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) if (G[i][j]) List[i].push_back(j); static int Temp[600], Stack[600]; int Top = 0; for (int i = 0; i < N; i++) { Temp[i] = In[i]; if (!Temp[i]) Stack[Top++] = i; } static int Queue[600]; int Count = 0; while (Top--) { int V = Stack[Top]; Queue[Count++] = V; for (int i = 0; i < N; i++) if (G[V][i]) { Temp[i] -= G[V][i]; if (!Temp[i]) Stack[Top++] = i; } } static int P[600][600]; memset(P, 0, sizeof(P)); for (int i = 0; i < N; i++) { int V = Queue[i]; P[V][V] = 1; for (int j = i; j < N; j++) { int U = Queue[j]; if (!P[V][U]) continue; for (int k = 0; k < List[U].size(); k++) { int _U = List[U][k]; P[V][_U] = ((long long)P[V][U] * G[U][_U] + P[V][_U]) % Mod; } } } int K0 = 0, K1 = 0; static int X[600], Y[600]; for (int i = 0; i < N; i++) { if (!In[i] && Out[i]) X[K0++] = i; if (!Out[i] && In[i]) Y[K1++] = i; } int K = K0; static long long A[600][600]; for (int i = 0; i < K; i++) for (int j = 0; j < K; j++) A[i][j] = P[X[i]][Y[j]]; int Ans = 1; for (int i = 0; i < N; i++) if (!In[i] && !Out[i]) X[K0++] = Y[K1++] = i; for (int i = 0; i < K0; i++) for (int j = 0; j < K0; j++) if (X[i] < X[j] && Y[i] > Y[j]) Ans = -Ans; for (int i = 0; i < K; i++) { int P = i; while (P < K && !A[P][i]) P++; if (P == K) { printf( 0 n ); return 0; } if (P != i) { Ans = -Ans; for (int j = i; j < K; j++) swap(A[i][j], A[P][j]); } int Q = Pow(A[i][i], Mod - 2, Mod); for (int j = i + 1; j < K; j++) { int T = (long long)A[j][i] * Q % Mod; if (!T) continue; for (int k = i; k < K; k++) { A[j][k] = (A[j][k] - (long long)T * A[i][k]) % Mod; if (A[j][k] < 0) A[j][k] += Mod; } } } for (int i = 0; i < K; i++) Ans = (long long)Ans * A[i][i] % Mod; if (Ans < 0) Ans += Mod; printf( %d n , Ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int M = 1e9 + 7; long long int n, k; string s, s1; void hi() { for (int i = k; i < s.length(); i++) { s[i] = s[i - k]; } } int main() { cout.precision(10); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k >> s; s1 = s; hi(); if (s >= s1) { cout << n << endl; cout << s; } else { bool ok = true; int i = k - 1; if (s[i] != 9 ) { s[i] = s[i] + 1; hi(); cout << n << endl; cout << s; } else { s[i] = 0 ; for (int j = i - 1; j >= 0; j--) { if (s[j] != 9 ) { s[j]++; ok = false; hi(); cout << n << endl; cout << s; break; } else { s[j] = 0 ; } } if (ok) { cout << n + 1 << endl; cout << s1[0] + 1; for (int i = 0; i < n; i++) { cout << 0 ; } } } } return 0; } long long int nChooseR(long long int n, long long int k) { if (k > n) return 0; if (k * 2 > n) k = n - k; if (k == 0) return 1; long long int result = n; for (int i = 2; i <= k; ++i) { result *= (n - i + 1); result /= i; } return result; } long long int power(long long int a, long long int b) { if (b == 1) { return a % M; } else { if (b % 2 == 0) return (power(a, b / 2) % M * power(a, b / 2) % M) % M; else return (((power(a, b / 2) % M * power(a, b / 2) % M) % M) * a % M) % M; } } |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Transmit_Delay_ROM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module Transmit_Delay_ROM (
address,
clock,
q);
input [2:0] address;
input clock;
output [127:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "Transmit_Delay.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "3"
// Retrieval info: PRIVATE: WidthData NUMERIC "128"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "Transmit_Delay.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL address[2..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
// Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0
// Retrieval info: CONNECT: q 0 0 128 0 @q_a 0 0 128 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Transmit_Delay_ROM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Transmit_Delay_ROM.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Transmit_Delay_ROM.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Transmit_Delay_ROM.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Transmit_Delay_ROM_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Transmit_Delay_ROM_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Transmit_Delay_ROM_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Transmit_Delay_ROM_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int INF = (1 << 30) - 1; const long long lINF = (1LL << 62) - 1; const double dINF = 1e40; const int MAXT = 1 << 22, MAXN = 1001000; struct seg_tree { int sum[MAXT], len; void build(int n) { for (len = 1; len < n; len <<= 1) ; } template <int val> void update(int pos) { for (int x = pos + len; x > 0; x >>= 1) sum[x] += val; } int find(int k) { int x; for (x = 1; x < len;) { x <<= 1; if (sum[x] < k) { k -= sum[x]; x ^= 1; } } return x - len; } } ds; int pos[MAXT], val[MAXN]; bool app[MAXN]; int main() { int n, m; scanf( %d%d , &n, &m); ds.build(n + m); for (int i = 0; i < n; i++) { pos[m + i] = i; ds.update<1>(m + i); } memset(val, -1, sizeof(val)); bool flag = true; for (int i = m - 1; i >= 0; i--) { int k, mark; scanf( %d%d , &mark, &k); int p = ds.find(k), op = pos[p]; ds.update<-1>(p); pos[i] = op; ds.update<1>(i); if (val[op] == -1) val[op] = mark; else if (val[op] != mark) { flag = false; break; } } memset(app, false, sizeof(app)); for (int i = 0; i < n; i++) if (val[i] != -1) { if (app[val[i]]) { flag = false; break; } app[val[i]] = true; } if (flag) { for (int i = 0, v = 1; i < n; i++) { if (val[i] == -1) { for (; app[v]; ++v) ; app[v] = true; val[i] = v; } if (i == n - 1) printf( %d n , val[i]); else printf( %d , val[i]); } } else puts( -1 ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a; cin >> a; if (a <= 4) cout << a % 3 + 1 << endl; else if (a == 5) cout << a - 4 << endl; return 0; } |
//
// Copyright (c) 1999 Peter Monta ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module main;
parameter PARM = 2;
reg [3:0] b;
wire [1:0] a;
assign a = b[3:(3-PARM+1)] + 1;
initial begin
b = 4'b1011;
#1;
if (a===2'b11)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef USE_VPI_NOT_DPI
//We call it via $c so we can verify DPI isn't required - see bug572
`else
import "DPI-C" context function integer mon_check();
`endif
`ifdef VERILATOR_COMMENTS
`define PUBLIC_FLAT_RD /*verilator public_flat_rd*/
`define PUBLIC_FLAT_RW /*verilator public_flat_rw @(posedge clk)*/
`else
`define PUBLIC_FLAT_RD
`define PUBLIC_FLAT_RW
`endif
module t (/*AUTOARG*/
// Inputs
input clk `PUBLIC_FLAT_RD,
// test ports
input [15:0] testin `PUBLIC_FLAT_RD,
output [23:0] testout `PUBLIC_FLAT_RW
);
`ifdef VERILATOR
`systemc_header
extern "C" int mon_check();
`verilog
`endif
reg onebit `PUBLIC_FLAT_RW;
reg [2:1] twoone `PUBLIC_FLAT_RW;
reg onetwo [1:2] `PUBLIC_FLAT_RW;
reg [2:1] fourthreetwoone[4:3] `PUBLIC_FLAT_RW;
integer status;
`ifdef iverilog
// stop icarus optimizing signals away
wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3];
`endif
wire subin `PUBLIC_FLAT_RD;
wire subout `PUBLIC_FLAT_RD;
sub sub(.*);
// Test loop
initial begin
`ifdef VERILATOR
status = $c32("mon_check()");
`endif
`ifdef iverilog
status = $mon_check();
`endif
`ifndef USE_VPI_NOT_DPI
status = mon_check();
`endif
if (status!=0) begin
$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : t
module sub (
input subin `PUBLIC_FLAT_RD,
output subout `PUBLIC_FLAT_RD
);
endmodule : sub
|
#include <bits/stdc++.h> using namespace std; inline int getc() { char ch = getchar(); while (ch != 0 && ch != 1 ) { ch = getchar(); } return ch - 0 ; } int main() { int n; scanf( %d , &n); int cnt1 = 0, cnt2 = 0; for (int i = 0; i < n; ++i) { if (getc() == i % 2) cnt1++; else cnt2++; } printf( %d n , min(cnt1, cnt2)); ; ; ; } |
#include <bits/stdc++.h> using namespace std; int num(string s) { if (s == 00 ) return 0; if (s == 10 ) return 2; if (s == 11 ) return 3; return 1; } void solve(int x) { vector<int> v[4], vv[4]; int n; cin >> n; int ans = 0; for (int i = 0; i < n; i++) { string s; int x; cin >> s >> x; v[num(s)].push_back(x); vv[num(s)].push_back(x); } for (int i = 0; i < 4; i++) { sort(vv[i].begin(), vv[i].end(), greater<int>()); sort(v[i].begin(), v[i].end(), greater<int>()); for (int j = 1; j < v[i].size(); j++) v[i][j] += v[i][j - 1]; } int t1, t2; int sz = v[3].size(); if (sz) ans += v[3][sz - 1]; t1 = sz; t2 = sz; int tot = sz; sz = min(v[1].size(), v[2].size()); if (sz > 0) ans += v[1][sz - 1] + v[2][sz - 1]; int i = sz, j = sz, k = 0; t1 += sz; t2 += sz; tot += sz + sz; int mx = 2 * t1 - tot; vector<int> fin; while (i < v[1].size()) fin.push_back(vv[1][i++]); while (j < v[2].size()) fin.push_back(vv[2][j++]); while (k < v[0].size()) fin.push_back(vv[0][k++]); sort(fin.begin(), fin.end(), greater<int>()); i = 0; while (mx && i < fin.size()) { mx--; ans += fin[i++]; } cout << ans; } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; int T = t; while (t--) { solve(T - t); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
interface intf ();
integer index;
endinterface
module t
(
clk
);
input clk;
intf ifa1_intf[4:1]();
intf ifa2_intf[4:1]();
intf ifb1_intf[1:4]();
intf ifb2_intf[1:4]();
int cyc;
sub sub0
(
.n(0),
.clk,
.cyc,
.alh(ifa1_intf[2:1]),
.ahl(ifa2_intf[2:1]),
.blh(ifb1_intf[1:2]),
.bhl(ifb2_intf[1:2])
);
sub sub1
(
.n(1),
.clk,
.cyc,
.alh(ifa1_intf[4:3]),
.ahl(ifa2_intf[4:3]),
.blh(ifb1_intf[3:4]),
.bhl(ifb2_intf[3:4])
);
`ifndef verilator // Backwards slicing not supported
sub sub2
(
.n(2),
.clk,
.cyc,
.alh(ifa1_intf[1:2]), // backwards vs decl
.ahl(ifa2_intf[1:2]), // backwards vs decl
.blh(ifb1_intf[2:1]), // backwards vs decl
.bhl(ifb2_intf[2:1]) // backwards vs decl
);
sub sub3
(
.n(3),
.clk,
.cyc,
.alh(ifa1_intf[3:4]), // backwards vs decl
.ahl(ifa2_intf[3:4]), // backwards vs decl
.blh(ifb1_intf[4:3]), // backwards vs decl
.bhl(ifb2_intf[4:3]) // backwards vs decl
);
`endif
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 1) begin
ifa1_intf[1].index = 'h101;
ifa1_intf[2].index = 'h102;
ifa1_intf[3].index = 'h103;
ifa1_intf[4].index = 'h104;
ifa2_intf[1].index = 'h201;
ifa2_intf[2].index = 'h202;
ifa2_intf[3].index = 'h203;
ifa2_intf[4].index = 'h204;
ifb1_intf[1].index = 'h301;
ifb1_intf[2].index = 'h302;
ifb1_intf[3].index = 'h303;
ifb1_intf[4].index = 'h304;
ifb2_intf[1].index = 'h401;
ifb2_intf[2].index = 'h402;
ifb2_intf[3].index = 'h403;
ifb2_intf[4].index = 'h404;
end
end
endmodule
module sub
(
input logic clk,
input int cyc,
input int n,
intf alh[1:2],
intf ahl[2:1],
intf blh[1:2],
intf bhl[2:1]
);
always @(posedge clk) begin
if (cyc == 5) begin
if (n == 0) begin
`checkh(alh[1].index, 'h102);
`checkh(alh[2].index, 'h101);
`checkh(ahl[1].index, 'h201);
`checkh(ahl[2].index, 'h202);
`checkh(blh[1].index, 'h301);
`checkh(blh[2].index, 'h302);
`checkh(bhl[1].index, 'h402);
`checkh(bhl[2].index, 'h401);
end
else if (n == 1) begin
`checkh(alh[1].index, 'h104);
`checkh(alh[2].index, 'h103);
`checkh(ahl[1].index, 'h203);
`checkh(ahl[2].index, 'h204);
`checkh(blh[1].index, 'h303);
`checkh(blh[2].index, 'h304);
`checkh(bhl[1].index, 'h404);
`checkh(bhl[2].index, 'h403);
end
else if (n == 2) begin
`checkh(alh[1].index, 'h101);
`checkh(alh[2].index, 'h102);
`checkh(ahl[1].index, 'h202);
`checkh(ahl[2].index, 'h201);
`checkh(blh[1].index, 'h302);
`checkh(blh[2].index, 'h301);
`checkh(bhl[1].index, 'h401);
`checkh(bhl[2].index, 'h402);
end
else if (n == 3) begin
`checkh(alh[1].index, 'h103);
`checkh(alh[2].index, 'h104);
`checkh(ahl[1].index, 'h204);
`checkh(ahl[2].index, 'h203);
`checkh(blh[1].index, 'h304);
`checkh(blh[2].index, 'h303);
`checkh(bhl[1].index, 'h403);
`checkh(bhl[2].index, 'h404);
end
end
if (cyc == 9 && n == 0) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> long long p; int k; namespace solver1 { void main() { std::vector<int> ans; int i; for (i = 0; p; i++) { if (i & 1) ans.push_back(((p - 1) / k + 1) * k - p), p = (p - 1) / k + 1; else ans.push_back(p % k), p /= k; } printf( %d n , (int)ans.size()); for (auto i : ans) { printf( %d , i); } printf( n ); } } // namespace solver1 int main() { std::cin >> p >> k; solver1::main(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32OI_TB_V
`define SKY130_FD_SC_LP__A32OI_TB_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a32oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__a32oi dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32OI_TB_V
|
#include <bits/stdc++.h> using namespace std; struct Hill { int Lid, Mid, Rid; long long Lv, Mv, Rv; bool valid; Hill() : valid(false) {} Hill(int Lid, int Mid, int Rid, long long Lv, long long Mv, long long Rv) : Lid(Lid), Mid(Mid), Rid(Rid), Lv(Lv), Mv(Mv), Rv(Rv), valid(true) {} int Len() const { return valid ? Rid - Lid + 1 : 0; } Hill operator+(const Hill B) const { Hill Ans; if (Rv == B.Lv) return Ans; if (Rv < B.Lv) { if (Mid == Rid) return Hill(Lid, B.Mid, B.Rid, Lv, B.Mv, B.Rv); else return Hill(Rid, B.Mid, B.Rid, Rv, B.Mv, B.Rv); } else { if (B.Mid == B.Lid) return Hill(Lid, Mid, B.Rid, Lv, Mv, B.Rv); else return Hill(Lid, Mid, B.Lid, Lv, Mv, B.Lv); } } bool operator<(const Hill B) const { return Len() < B.Len(); } void show() { if (valid) printf( A[%d]=%d A[%d]=%d A[%d]=%d n , Lid, int(Lv), Mid, int(Mv), Rid, int(Rv)); else printf( ERROR! n ); } }; Hill CLeft(const Hill A, const Hill B) { if (!B.valid || B.Lv == A.Rv) return A; if (A.Mid == A.Rid) { if (B.Lv > A.Rv) return Hill(A.Lid, B.Mid, B.Rid, A.Lv, B.Mv, B.Rv); else if (B.Lid == B.Mid) return Hill(A.Lid, A.Mid, B.Rid, A.Lv, A.Mv, B.Rv); else return Hill(A.Lid, A.Mid, B.Lid, A.Lv, A.Mv, B.Lv); } else { if (B.Lv < A.Rv) { if (B.Lid == B.Mid) return Hill(A.Lid, A.Mid, B.Rid, A.Lv, A.Mv, B.Rv); else return Hill(A.Lid, A.Mid, B.Lid, A.Lv, A.Mv, B.Lv); } else return A; } } Hill CRight(const Hill A, const Hill B) { if (!A.valid || A.Rv == B.Lv) return B; if (B.Mid == B.Lid) { if (A.Rv > B.Lv) return Hill(A.Lid, A.Mid, B.Rid, A.Lv, A.Mv, B.Rv); else if (A.Rid == A.Mid) return Hill(A.Lid, B.Mid, B.Rid, A.Lv, B.Mv, B.Rv); else return Hill(A.Rid, B.Mid, B.Rid, A.Rv, B.Mv, B.Rv); } else { if (A.Rv < B.Lv) { if (A.Rid == A.Mid) return Hill(A.Lid, B.Mid, B.Rid, A.Lv, B.Mv, B.Rv); else return Hill(A.Rid, B.Mid, B.Rid, A.Rv, B.Mv, B.Rv); } else return B; } } struct Segment { Hill L, M, R; bool pure; Segment() {} Segment(Hill L, Hill M, Hill R, bool pure) : L(L), M(M), R(R), pure(pure) {} Segment operator+(const Segment B) const { Segment Ans; Ans.L = pure ? CLeft(L, B.L) : L; Ans.R = B.pure ? CRight(R, B.R) : B.R; Hill CM = M < B.M ? B.M : M; Ans.M = R + B.L; if (Ans.M < CM) Ans.M = CM; Ans.pure = Ans.M.Len() == Ans.R.Rid - Ans.L.Lid + 1; return Ans; } void Add(const long long D) { L.Lv += D; L.Mv += D; L.Rv += D; M.Lv += D; M.Mv += D; M.Rv += D; R.Lv += D; R.Mv += D; R.Rv += D; } void show() { L.show(); M.show(); R.show(); } }; Segment S[300001 << 2]; long long Add[300001 << 2]; int mm[300001 << 2]; void PushUp(int rt) { S[rt] = S[rt << 1] + S[rt << 1 | 1]; } void PushDown(int rt) { int ls = rt << 1, rs = ls | 1; if (Add[rt]) { Add[ls] += Add[rt]; Add[rs] += Add[rt]; S[ls].Add(Add[rt]); S[rs].Add(Add[rt]); Add[rt] = 0; } } void Build(int l, int r, int rt) { if (l == r) { int v; scanf( %d , &v); Hill tempH(l, l, l, v, v, v); S[rt] = Segment(tempH, tempH, tempH, true); return; } int m = mm[rt] = (l + r) >> 1; Build(l, m, rt << 1); Build(m + 1, r, rt << 1 | 1); PushUp(rt); Add[rt] = 0; } void Update(const int L, const int R, const long long D, const int l, const int r, const int rt) { if (L <= l && r <= R) { Add[rt] += D; S[rt].Add(D); return; } const int m = mm[rt]; PushDown(rt); if (L <= m) Update(L, R, D, l, m, rt << 1); if (R > m) Update(L, R, D, m + 1, r, rt << 1 | 1); PushUp(rt); } void Search(int l, int r, int rt) { if (l == r) { printf( %d , int(S[rt].L.Lv)); return; } PushDown(rt); int m = (l + r) >> 1; Search(l, m, rt << 1); Search(m + 1, r, rt << 1 | 1); } int main() { int n, m; while (~scanf( %d , &n)) { Build(1, n, 1); scanf( %d , &m); for (int i = 0; i < m; ++i) { static int l, r, d; scanf( %d%d%d , &l, &r, &d); Update(l, r, d, 1, n, 1); printf( %d n , S[1].M.Len()); } } return 0; } |
// file: system_clk_wiz_1_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1___200.000______0.000______50.0______114.829_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "system_clk_wiz_1_0,clk_wiz_v5_3_3_0,{component_name=system_clk_wiz_1_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module system_clk_wiz_1_0
(
// Clock out ports
output clk_out1,
// Clock in ports
input clk_in1
);
system_clk_wiz_1_0_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NOR4BB_BEHAVIORAL_PP_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nor4bb (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4BB_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; int tas[101], cal[101]; int dp1[10001], dp2[10001]; int w1[101][3], w2[101][3]; while ((cin >> n >> k)) { int s = 0, t = 0; int sum1 = 0, sum2 = 0, sum = 0; for (int i = 1; i <= n; ++i) cin >> tas[i]; for (int j = 1; j <= n; ++j) cin >> cal[j]; for (int i = 1; i <= n; ++i) { int data; data = tas[i] - k * cal[i]; if (data > 0) { w1[++s][1] = data; w1[s][2] = tas[i]; sum1 += data; } else if (data < 0) { data = -data; w2[++t][1] = data; w2[t][2] = tas[i]; sum2 += data; } else sum += tas[i]; } int max = sum1 <= sum2 ? sum1 : sum2; int temp = 0; for (int i = 1; i <= max; ++i) { memset(dp1, -10000000, sizeof(dp1)); memset(dp2, -10000000, sizeof(dp2)); dp1[0] = dp2[0] = 0; for (int j = 1; j <= s; ++j) { for (int v = i; v >= w1[j][1]; --v) { if (dp1[v] < dp1[v - w1[j][1]] + w1[j][2]) dp1[v] = dp1[v - w1[j][1]] + w1[j][2]; } } for (int j = 1; j <= t; ++j) { for (int v = i; v >= w2[j][1]; --v) { if (dp2[v] < dp2[v - w2[j][1]] + w2[j][2]) dp2[v] = dp2[v - w2[j][1]] + w2[j][2]; } } if (dp1[i] > 0 && dp2[i] > 0) { if (dp1[i] + dp2[i] > temp) temp = dp1[i] + dp2[i]; } } sum += temp; if (sum == 0) cout << -1 << endl; else cout << sum << endl; } return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ae
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ae.v,v 1.6 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_ae.v,v $
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ae
//
// No user `defines in this module
module ent_ae
//
// Generated Module inst_ae
//
(
port_ae_2, // Use internally test2, no port generated
port_ae_5, // Bus, single bits go to outside
port_ae_6, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_i_ae, // Input Bus
sig_o_ae // Output Bus
);
// Generated Module Inputs:
input [4:0] port_ae_2;
input [3:0] port_ae_5;
input [3:0] port_ae_6;
input [5:0] sig_07;
input [8:2] sig_08;
input [6:0] sig_i_ae;
// Generated Module Outputs:
output [7:0] sig_o_ae;
// Generated Wires:
wire [4:0] port_ae_2;
wire [3:0] port_ae_5;
wire [3:0] port_ae_6;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [6:0] sig_i_ae;
wire [7:0] sig_o_ae;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ae
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int dp[N]; int pdp[2 * N]; signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int c, n; cin >> c >> n; ++n; pair<pair<int, int>, int> a[n]; a[0] = {{1, 1}, 0}; for (int i = 1; i < n; i++) cin >> a[i].second >> a[i].first.first >> a[i].first.second; memset(dp, 0, sizeof dp); memset(pdp, 0, sizeof pdp); dp[n - 1] = 1; pdp[n - 1] = 1; for (int i = n - 2; i >= 0; i--) { dp[i] = i != 0; for (int j = i + 1; j < min(n, i + 1005); j++) { int taken = abs(a[i].first.first - a[j].first.first) + abs(a[i].first.second - a[j].first.second); int can = a[j].second - a[i].second; if (taken <= can) { dp[i] = max(dp[i], dp[j] + (i != 0)); } } dp[i] = max(dp[i], pdp[i + 1004] + (i != 0)); pdp[i] = max(dp[i], pdp[i + 1]); } cout << dp[0] << endl; } |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_nios2_qsys_0_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
NIOS_Sys_nios2_qsys_0_jtag_debug_module_tck the_NIOS_Sys_nios2_qsys_0_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
NIOS_Sys_nios2_qsys_0_jtag_debug_module_sysclk the_NIOS_Sys_nios2_qsys_0_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic NIOS_Sys_nios2_qsys_0_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam NIOS_Sys_nios2_qsys_0_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// NIOS_Sys_nios2_qsys_0_jtag_debug_module_phy.sld_instance_index = 0,
// NIOS_Sys_nios2_qsys_0_jtag_debug_module_phy.sld_ir_width = 2,
// NIOS_Sys_nios2_qsys_0_jtag_debug_module_phy.sld_mfg_id = 70,
// NIOS_Sys_nios2_qsys_0_jtag_debug_module_phy.sld_sim_action = "",
// NIOS_Sys_nios2_qsys_0_jtag_debug_module_phy.sld_sim_n_scan = 0,
// NIOS_Sys_nios2_qsys_0_jtag_debug_module_phy.sld_sim_total_length = 0,
// NIOS_Sys_nios2_qsys_0_jtag_debug_module_phy.sld_type_id = 34,
// NIOS_Sys_nios2_qsys_0_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
`define bsg_mem_1rw_sync_macro(words,bits) \
if (els_p == words && width_p == bits) \
begin: macro \
hard_mem_1rw_d``words``_w``bits``_wrapper \
mem \
(.clk_i (clk_i) \
,.reset_i(reset_i) \
,.data_i (data_i) \
,.addr_i (addr_i) \
,.v_i (v_i) \
,.w_i (w_i) \
,.data_o (data_o) \
); \
end: macro
module bsg_mem_1rw_sync #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
// whether to substitute a 1r1w
, parameter substitute_1r1w_p = 1
)
( input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_lp-1:0] addr_i
, input v_i
, input w_i
, output logic [width_p-1:0] data_o
);
wire unused = reset_i;
// TODO: Define more hardened macro configs here
`bsg_mem_1rw_sync_macro(512,64) else
`bsg_mem_1rw_sync_macro(256,95) else
`bsg_mem_1rw_sync_macro(256,96) else
// no hardened version found
begin : z
// we substitute a 1r1w macro
// fixme: theoretically there may be
// a more efficient way to generate a 1rw synthesized ram
if (substitute_1r1w_p)
begin: s1r1w
logic [width_p-1:0] data_lo;
bsg_mem_1r1w #( .width_p(width_p)
, .els_p(els_p)
, .read_write_same_addr_p(0)
)
mem
(.w_clk_i (clk_i)
,.w_reset_i(reset_i)
,.w_v_i (v_i & w_i)
,.w_addr_i (addr_i)
,.w_data_i (data_i)
,.r_addr_i (addr_i)
,.r_v_i (v_i & ~w_i)
,.r_data_o (data_lo)
);
// register output data to convert sync to async
always_ff @(posedge clk_i) begin
data_o <= data_lo;
end
end // block: s1r1w
else
begin: notmacro
bsg_mem_1rw_sync_synth # (.width_p(width_p), .els_p(els_p))
synth
(.*);
end // block: notmacro
end // block: z
// synopsys translate_off
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, substitute_1r1w_p=%d (%m)",width_p,els_p,substitute_1r1w_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync)
|
#include <bits/stdc++.h> using namespace std; int dp[1003][1003][12][3]; string s, t; int solve(int i, int j, int k, int cont) { if (i < 0 || j < 0) return 0; if (dp[i][j][k][cont] != -1) return dp[i][j][k][cont]; int ret = -9; if (s[i] == t[j]) { if (cont) { ret = max(ret, 1 + solve(i - 1, j - 1, k, 1)); } if (k > 0) ret = max(ret, 1 + solve(i - 1, j - 1, k - 1, 1)); } ret = max(ret, solve(i - 1, j, k, 0)); ret = max(ret, solve(i, j - 1, k, 0)); dp[i][j][k][cont] = ret; return ret; } int main() { int n, m, k; cin >> n >> m >> k; cin >> s >> t; for (int i = 0; i < 1003; ++i) { for (int j = 0; j < 1003; ++j) { for (int k = 0; k < 12; ++k) { for (int l = 0; l < 3; ++l) { dp[i][j][k][l] = -1; } } } } int ans = solve(n - 1, m - 1, k, 0); cout << ans << n ; } |
`timescale 1ns/1ps
module memcpy_statemachine(
input clk ,
input rst_n ,
input memcpy_start ,
input [63:0] memcpy_len ,
input [63:0] memcpy_addr ,
input burst_busy ,
output reg burst_start ,
output reg [07:0] burst_len ,
output reg [63:0] burst_addr ,
output burst_on ,
input burst_done ,
output reg memcpy_done
);
reg [06:0] cstate,nstate;
reg [63:0] end_addr;
reg [63:0] current_addr;
reg [07:0] current_len;
reg [63:0] next_boundary;
reg [63:0] end_boundary;
reg [63:0] end_aligned;
reg [00:0] last_burst;
parameter IDLE = 7'h01,
INIT = 7'h02,
N4KB = 7'h04,
CLEN = 7'h08,
START = 7'h10,
INPROC = 7'h20,
DONE = 7'h40;
//---- memcpy state machine ----
always@(posedge clk or negedge rst_n)
if (~rst_n)
cstate <= IDLE;
else
cstate <= nstate;
always@*
case(cstate)
IDLE :
if (memcpy_start)
nstate = INIT;
else
nstate = IDLE;
INIT :
if (memcpy_len == 64'd0)
nstate = IDLE;
else
nstate = N4KB;
N4KB :
nstate = CLEN;
CLEN :
if (~burst_busy)
nstate = START;
else
nstate = CLEN;
START :
nstate = INPROC;
INPROC :
if (burst_done)
nstate = DONE;
else
nstate = INPROC;
DONE :
if (last_burst)
nstate = IDLE;
else
nstate = N4KB;
default :
nstate = IDLE;
endcase
//---- end address of transfer ----
always@(posedge clk or negedge rst_n)
if (~rst_n)
end_addr <= 64'd0;
else
case (cstate)
INIT : end_addr <= memcpy_addr + memcpy_len;
endcase
//---- current starting address ----
always@(posedge clk or negedge rst_n)
if (~rst_n)
current_addr <= 64'd0;
else
case (cstate)
INIT : current_addr <= {memcpy_addr[63:6],6'd0}; // previous 64B boundary
DONE : current_addr <= next_boundary;
endcase
//---- current burst length ----
always@(posedge clk or negedge rst_n)
if (~rst_n)
current_len <= 8'd0;
else
case (cstate)
CLEN :
if (next_boundary[63:12]~^end_boundary[63:12])
current_len <= 8'd64 - current_addr[11:6]; // 64*64=4KB, 64B=512b
else
current_len <= end_aligned[13:6] - current_addr[13:6]; // at least do a burst_len=1
endcase
//---- next 4KB boundary ----
always@(posedge clk or negedge rst_n)
if (~rst_n)
begin
next_boundary <= 64'd0;
end_boundary <= 64'd0;
end_aligned <= 64'd0;
end
else
case (cstate)
N4KB :
begin
next_boundary <= {current_addr[63:12] + 52'd1, 12'd0};
end_boundary <= (~|end_addr[11:0])? end_addr : {end_addr[63:12] + 52'd1, 12'd0}; // next immediate 4KB
end_aligned <= (~|end_addr[5:0])? end_addr : {end_addr[63:6] + 58'd1, 6'd0}; // next immediate 64B
end
endcase
//---- determine if current burst is the last one ----
always@(posedge clk or negedge rst_n)
if (~rst_n)
last_burst <= 1'b0;
else
case (cstate)
CLEN :
if (&(next_boundary[63:12]~^end_boundary[63:12]))
last_burst <= 1'b1;
else
last_burst <= 1'b0;
DONE :
last_burst <= 1'b0;
endcase
//---- burst start configuration ----
always@(posedge clk or negedge rst_n)
if (~rst_n)
begin
burst_start <= 1'b0;
burst_addr <= 64'd0;
burst_len <= 8'd0;
end
else
case (cstate)
START :
begin
burst_start <= 1'b1;
burst_addr <= current_addr;
burst_len <= current_len;
end
default :
begin
burst_start <= 1'b0;
end
endcase
//---- burst in progress ----
assign burst_on = (cstate == INPROC);
//---- whole memory read or write is completed ----
always@(posedge clk or negedge rst_n)
if (~rst_n)
memcpy_done <= 1'b1;
else
case (cstate)
START : memcpy_done <= 1'b0;
DONE : if (last_burst)
memcpy_done <= 1'b1;
default:;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; ostream &operator<<(ostream &out, string str) { for (char c : str) out << c; return out; } template <class L, class R> ostream &operator<<(ostream &out, pair<L, R> p) { return out << ( << p.first << , << p.second << ) ; } template <class T> auto operator<<(ostream &out, T a) -> decltype(a.begin(), out) { out << { ; for (auto it = a.begin(); it != a.end(); it = next(it)) out << (it != a.begin() ? , : ) << *it; return out << } ; } void dump() { cerr << n ; } template <class T, class... Ts> void dump(T a, Ts... x) { cerr << a << , ; dump(x...); } template <class T> int size(T &&a) { return a.size(); } using LL = long long; using PII = pair<int, int>; mt19937 _gen(chrono::system_clock::now().time_since_epoch().count()); int rd(int a, int b) { return uniform_int_distribution<int>(a, b)(_gen); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; for (int _t = 0; _t < t; _t++) { int n, m; cin >> n >> m; vector<vector<int>> v(n, vector<int>(m)); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> v[i][j]; vector<int> ord(m); vector<int> mx(m); for (int j = 0; j < m; j++) { ord[j] = j; for (int i = 0; i < n; i++) mx[j] = max(mx[j], v[i][j]); } sort(ord.begin(), ord.end(), [&](int a, int b) { return mx[a] > mx[b]; }); vector<int> rev; for (int i = 0; i < min(n, m); i++) rev.emplace_back(ord[i]); vector<vector<int>> t(n, vector<int>(size(rev))); for (int i = 0; i < n; i++) for (int j = 0; j < size(rev); j++) t[i][j] = v[i][rev[j]]; m = size(rev); int p = (1 << n); vector<vector<int>> dp(m, vector<int>(p)); vector<vector<int>> sum(m, vector<int>(p)); auto mymod = [&](int val) { if (val >= n) return val - n; return val; }; for (int j = 0; j < m; j++) { for (int k = 0; k < p; k++) { for (int r = 0; r < n; r++) { int sumka = 0; for (int i = 0; i < n; i++) { if (k & (1 << mymod(i + r))) sumka += t[i][j]; } sum[j][k] = max(sum[j][k], sumka); } false; } } for (int j = 0; j < m; j++) { if (j != 0) dp[j] = dp[j - 1]; for (int k = 0; k < p; k++) { if (j == 0) dp[j][k] = sum[j][k]; else { for (int l = k; l > 0; l = (l - 1) & k) { dp[j][k] = max(dp[j][k], dp[j - 1][k ^ l] + sum[j][l]); } } } false; } cout << dp[m - 1][p - 1] << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_2_V
`define SKY130_FD_SC_HVL__BUF_2_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_2_V
|
#include <bits/stdc++.h> using namespace std; const int dx[4] = {0, 1, 0, -1}, dy[4] = {-1, 0, 1, 0}; const int ddx[8] = {0, 1, 1, 1, 0, -1, -1, -1}, ddy[8] = {-1, -1, 0, 1, 1, 1, 0, -1}; const int nx[8] = {1, 2, 2, 1, -1, -2, -2, -1}, ny[8] = {-2, -1, 1, 2, 2, 1, -1, -2}; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int t = 1; cin >> t; while (t--) { int n, k; string s; cin >> n >> k >> s; bool ans = true; for (int i = 0; i < k; i++) { bool ze = true, on = true; for (int j = i; j < n; j += k) { if (s[j] == 0 ) on = false; if (s[j] == 1 ) ze = false; } if (ze && !on) { for (int j = i; j < n; j += k) s[j] = 0 ; } if (!ze && on) { for (int j = i; j < n; j += k) s[j] = 1 ; } if (!ze && !on) { ans = false; } } int ze = 0, on = 0, qu = 0; for (int i = 0; i < k; i++) { if (s[i] == 0 ) ze += 1; if (s[i] == 1 ) on += 1; if (s[i] == ? ) qu += 1; } if (ze > k / 2 || on > k / 2) ans = false; cout << (ans ? YES : NO ); done:; cout << n ; } } |
module cmd_gen_submodule (
//input
input clk ,
input reset_n ,
//output
output [7:0] Line_Num,
output [1:0] Focus_Num,
output Pr_Gate ,
output RX_Gate ,
output Sample_Gate,
output Envelop ,
output End_Gate
);
//wire
wire [7:0] Line_Num_buf ;
wire [1:0] Focus_Num_buf ;
wire Pr_Gate_buf ;
wire RX_Gate_buf ;
wire Sample_Gate_buf ;
wire End_Gate_buf ;
wire Envelop_buf ;
//reg
//combination
//seq
//initiation
transmit_test_model transmit_test_rev (
//input
.clk_100M (clk),
.reset_n (reset_n) ,
//output
.Line_Num (Line_Num_buf),
.Focus_Num (Focus_Num_buf),
.Pr_Gate (Pr_Gate_buf) ,
.RX_Gate (RX_Gate_buf) ,
.End_Gate (End_Gate_buf),
.Envelop (Envelop_buf)
);
Transmit Transmit_rev (
//input
.Transmit_CLK (clk), //100MHz
.Line_Num (Line_Num_buf), //Line Num,256 Lines totally,0~255
.Focus_Num (Focus_Num_buf), //Focus_num ,3 totally
.Pr_Gate (Pr_Gate_buf), //prepare for everythings
.RX_Gate (RX_Gate_buf), // Start Transmit
//output
.Sample_Gate (Sample_Gate_buf), //
.P (),
.N (),
.HV_SW_CLR (),
.HV_SW_LE (),
.HV_SW_CLK (),
.HV_SW_DOUT (),
.AX (),
.AY (),
.MT_CS (),
.MT_Strobe (),
.MT_Data ()
);
assign Line_Num = Line_Num_buf ;
assign Focus_Num = Focus_Num_buf ;
assign Pr_Gate = Pr_Gate_buf ;
assign RX_Gate = RX_Gate_buf ;
assign End_Gate = End_Gate_buf ;
assign Sample_Gate = Sample_Gate_buf;
assign Envelop = Envelop_buf ;
endmodule
|
`timescale 1 ns / 100 ps
`include "design/mips_regFile.v"
module reg_file_tb();
parameter ClockDelay = 2;
reg [4:0] rdAddr0, rdAddr1, wrAddr;
reg [31:0] wrData;
reg we, clk, rst_n, halted;
wire [31:0] rdData0, rdData1;
integer i;
mips_regFile regFile(clk, rst_n, rdAddr0, rdAddr1, we, wrAddr, wrData, halted, rdData0, rdData1);
initial begin
clk = 0;
rst_n = 1;
end
always #(ClockDelay/2) clk = ~clk;
initial
begin
$dumpfile("reg_file_tb.vcd");
$dumpvars;
#(ClockDelay);
rst_n = 0;
halted = 0;
#(ClockDelay);
rst_n = 1;
// for (i = 0; i < 32; i = i + 1) begin
// rdAddr0 = i;
// rdAddr1 = i;
// #(ClockDelay);
// end
we = 0;
rdAddr0 = 0;
rdAddr1 = 0;
wrAddr = 0;
wrData = 32'hA0;
#(ClockDelay);
we = 1;
#(ClockDelay);
we = 0;
#(ClockDelay);
for (i = 1; i < 32; i = i + 1) begin
we = 0;
rdAddr0 = i - 1;
rdAddr1 = i;
wrAddr = i;
wrData = i * 32'h01020408;
#(ClockDelay);
we = 1;
#(ClockDelay);
end
for (i = 1; i < 32; i = i + 1) begin
we = 1;
rdAddr0 = 0;
rdAddr1 = 0;
wrAddr = i;
wrData = 0;
#(ClockDelay);
end
for (i = 0; i < 32; i = i + 1) begin
we = 1;
rdAddr0 = i;
rdAddr1 = i;
wrAddr = i;
wrData = i * 32'h100 + i;
#(ClockDelay);
end
#(ClockDelay);
halted = 1;
#(ClockDelay);
rst_n = 1;
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A31OI_BLACKBOX_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a31oi (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int mxn = 5e5 + 123; const int inf = 1e9; const int mod = 1e9 + 7; int a[mxn], n; vector<int> v; int main() { long long s; cin >> s; for (long long i = 1; i <= s; i++) { long long n; cin >> n; long long sum = 0; while (n > 0) { if (n % 2 == 1) sum++; n /= 2; } cout << (1ll << sum) << endl; } return 0; } |
/* SRAM FIFO
*
* A "wrapper" around the SRAM, converting it to a FIFO. Note that this is a
* "dump" FIFO that does not CHECK if it is full or empty before reading, to
* reduce logic on the data path. This means that one can read old data if one
* falls off or writes over previous data if landing on there.
*
* Created By David Tran
* Version 0.1.0.0
* Last Modified:05-01-2014
*/
`include "sram.v"
module SRAM_fifo(
readMode, // Specifies if we want to read from the FIFO
writeMode, // Specifies if we want to write form the FIFO
inputPacket, // The input bit to write to the shift-register (8bits)
outputPacket, // The output bit to read from the shift-register (8bits)
clk, // Clock input
rst // Reset input
);
parameter bits = 8;
parameter depth = 3;
parameter ad_length = 1<<depth;
input readMode, writeMode, clk, rst;
reg readModeQ, writeModeQ;
input [bits-1:0] inputPacket;
wire [bits-1:0] inputPacket;
reg [bits-1:0] inputPacketQ;
output [bits-1:0] outputPacket;
wire [bits-1:0] outputPacket;
reg [2:0] readPtr; // This is the current read pointer of the queue.
reg [2:0] writePtr; // This is the current write pointer of the queue.
reg [2:0] address; // This will be the address used to access the SRAM
reg [2:0] nextReadPtr, nextWritePtr; // Sets the next pointer, to be used in the address.
SRAM sram (.read(readModeQ),
.write(writeModeQ),
.address(address),
.dataIn(inputPacketQ),
.dataOut(outputPacket),
.clk(clk)
);
always @(posedge clk or posedge rst)
if (rst) begin
readPtr <= 3'h0;
writePtr <= 3'h0;
address <= 3'h0;
inputPacketQ <= {bits{1'b0}};
nextReadPtr <= 3'h0;
nextWritePtr <= 3'h0;
end else begin
// Stores the next value as current for the next iteration.
readPtr = nextReadPtr;
writePtr = nextWritePtr;
if (readModeQ) begin
address <= nextReadPtr;
end else if (writeModeQ) begin
address <= nextWritePtr;
end
// Updates the values in the queue.
readModeQ = readMode;
writeModeQ = writeMode;
inputPacketQ = inputPacket;
end
// Moves the increment operation one cycle ahead.
always @(readPtr or writePtr or readMode or writeMode) begin
nextReadPtr <= readMode ? readPtr + 1: readPtr;
nextWritePtr <= writeMode ? writePtr + 1: writePtr;
end
endmodule
|
#include <bits/stdc++.h> int w[505]; int book[505]; int v[1005]; int used[505]; int main(void) { int n, m; int k; int r = 0; scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { used[i] = 0; scanf( %d , &w[i]); } for (int i = 1; i <= m; i++) { scanf( %d , &v[i]); } k = 1; for (int i = 1; i <= m; i++) { if (!used[v[i]]) { used[v[i]] = 1; book[k++] = v[i]; } } for (int i = 1; i <= m; i++) { for (int j = 1; j < k; j++) { if (book[j] == v[i]) { for (int p = j - 1; p >= 1; p--) { r += w[book[p]]; book[p + 1] = book[p]; } book[1] = v[i]; break; } } } printf( %d n , r); return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { char ch; int val; int idx; node(char ch = a , int val = -1, int idx = 0) : ch(ch), val(val), idx(idx) {} }; void swap(node& a, node& b) { node temp(a.ch, a.val, a.idx); a = b; b = temp; } void disp(vector<node>& arr) { for (auto e : arr) cout << e.ch << t ; cout << n ; for (auto e : arr) cout << e.val << t ; cout << n ; for (auto e : arr) cout << e.idx << t ; cout << n ; } int main() { { ios_base::sync_with_stdio(false); cin.tie(NULL); }; long long n; cin >> n; string str; cin >> str; vector<long long> res(n, -1); vector<node> arr(n); for (int i = 0; i < n; i++) { arr[i].ch = str[i]; arr[i].idx = i; } for (int i = 0; i < n; i++) { bool isZero = 0, isOne = 0; char smallestChar = arr[i].ch; int idx = i; for (int j = i; j < n; j++) { if (int(smallestChar) > int(arr[j].ch)) { smallestChar = arr[j].ch; idx = j; } } for (int j = i; j < idx; j++) { if (arr[j].val == 0) isZero = 1; else if (arr[j].val == 1) isOne = 1; } if (isZero and isOne) { cout << NO n ; return 0; } else if (isZero) { if (arr[idx].val == 0) { cout << NO n ; return 0; } else { arr[idx].val = 1; for (int j = i; j < idx; j++) arr[j].val = 0; for (int j = idx; j > i; j--) swap(arr[j], arr[j - 1]); } } else if (isOne) { if (arr[idx].val == 1) { cout << NO n ; return 0; } else { arr[idx].val = 0; for (int j = i; j < idx; j++) arr[j].val = 1; for (int j = idx; j > i; j--) swap(arr[j], arr[j - 1]); } } else { if (arr[idx].val == 1) { for (int j = i; j < idx; j++) arr[j].val = 0; for (int j = idx; j > i; j--) swap(arr[j], arr[j - 1]); } else if (arr[idx].val == 0) { for (int j = i; j < idx; j++) arr[j].val = 1; for (int j = idx; j > i; j--) swap(arr[j], arr[j - 1]); } else { arr[idx].val = 1; for (int j = i; j < idx; j++) arr[j].val = 0; for (int j = idx; j > i; j--) swap(arr[j], arr[j - 1]); } } } cout << YES n ; for (auto e : arr) res[e.idx] = e.val; for (auto e : res) cout << e; cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[10000000]; int main() { long long n, i, j, m, l, r, cnt = 0; string s, s2, s3 = , s4 = , s5 = ; cin >> s >> s2; n = s.size(); for (i = 0; i < n - 1; i++) { if (s[i] == s2[i]) s3 += s[i]; else break; } for (i = n - 1; i > 0; i--) { if (s[i] == s2[i - 1]) s4 += s[i]; else break; } l = s3.size(); r = s4.size(); if (l + 1 < n - r) cout << 0 << endl; else { s5 = s5 + s[l]; cnt = 0; for (i = l; i >= 0; i--) { if (s5[0] == s[i]) { a[cnt] = i + 1; ++cnt; } else break; } for (i = l + 1; i < n; i++) { if (s5[0] == s[i]) { a[cnt] = i + 1; ++cnt; } else break; } sort(a, a + cnt); cout << cnt << endl; for (i = 0; i < cnt; i++) { cout << a[i] << ; } } } |
// ====================================================================
// MAH PONK
//
// Copyright (C) 2007, Viacheslav Slavinsky
// This design and core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
// An open table tennis game for VGA displays.
//
// Author: Viacheslav Slavinsky, http://sensi.org/~svo
//
// Design File: ballscan.v, instantiated by tehgame.v
// Generates ball scan signal.
//
// Pins description:
// clk input master clock
// screenx input x-scan coordinate
// screeny input y-scan coordinate
// ball_x input ball position
// ball_y input ball position
// ball_scan output ball scan signal
//
module ballscan(clk, screenx, screeny, ball_x, ball_y, ball_scan);
parameter BALLSIZE=8;
input clk;
input [9:0] screenx;
input [9:0] screeny;
input [9:0] ball_x;
input [9:0] ball_y;
output ball_scan;
reg [3:0] ballscanX;
reg ballscanY;
always @(posedge clk) begin
if (screenx == ball_x-BALLSIZE/2)
ballscanX = 12;
if (ballscanX > 0)
ballscanX = ballscanX - 1'b1;
end
always @(posedge clk) begin
if (screeny == ball_y-BALLSIZE/2)
ballscanY = 1;
if (screeny == ball_y+BALLSIZE/2)
ballscanY = 0;
end
assign ball_scan = ballscanX != 0 && ballscanY;
endmodule
// $Id: ballscan.v,v 1.4 2007/08/27 22:14:47 svo Exp $
|
#include <bits/stdc++.h> const int N = 100005; int solve(int n, int k, int cnt[]) { if (k == n || cnt[0] == 0 || cnt[1] == 0) { return 1 - cnt[1] % 2; } if ((n - k) / 2 < cnt[0] && (n - k) / 2 < cnt[1]) { if ((n - k) % 2 == 0) return 1; else return 0; } if ((n - k) / 2 >= cnt[0]) { return 1 - k % 2; } return 1; } int main() { int n, k; scanf( %d%d , &n, &k); int cnt[2]; cnt[0] = cnt[1] = 0; for (int i = 0; i < n; i++) { int tmp; scanf( %d , &tmp); cnt[tmp % 2]++; } printf( %s , solve(n, k, cnt) ? Daenerys : Stannis ); return 0; } |
module ghrd_10as066n2_avlmm_pr_freeze_bridge_1 (
input wire clock, // clock.clk
input wire freeze_conduit_freeze, // freeze_conduit.freeze
output wire freeze_conduit_illegal_request, // .illegal_request
input wire mst_bridge_to_pr_read, // mst_bridge_to_pr.read
output wire mst_bridge_to_pr_waitrequest, // .waitrequest
input wire mst_bridge_to_pr_write, // .write
input wire [31:0] mst_bridge_to_pr_address, // .address
input wire [3:0] mst_bridge_to_pr_byteenable, // .byteenable
input wire [31:0] mst_bridge_to_pr_writedata, // .writedata
output wire [31:0] mst_bridge_to_pr_readdata, // .readdata
input wire [2:0] mst_bridge_to_pr_burstcount, // .burstcount
output wire mst_bridge_to_pr_readdatavalid, // .readdatavalid
input wire mst_bridge_to_pr_beginbursttransfer, // .beginbursttransfer
input wire mst_bridge_to_pr_debugaccess, // .debugaccess
output wire [1:0] mst_bridge_to_pr_response, // .response
input wire mst_bridge_to_pr_lock, // .lock
output wire mst_bridge_to_pr_writeresponsevalid, // .writeresponsevalid
output wire mst_bridge_to_sr_read, // mst_bridge_to_sr.read
input wire mst_bridge_to_sr_waitrequest, // .waitrequest
output wire mst_bridge_to_sr_write, // .write
output wire [31:0] mst_bridge_to_sr_address, // .address
output wire [3:0] mst_bridge_to_sr_byteenable, // .byteenable
output wire [31:0] mst_bridge_to_sr_writedata, // .writedata
input wire [31:0] mst_bridge_to_sr_readdata, // .readdata
output wire [2:0] mst_bridge_to_sr_burstcount, // .burstcount
input wire mst_bridge_to_sr_readdatavalid, // .readdatavalid
output wire mst_bridge_to_sr_beginbursttransfer, // .beginbursttransfer
output wire mst_bridge_to_sr_debugaccess, // .debugaccess
input wire [1:0] mst_bridge_to_sr_response, // .response
output wire mst_bridge_to_sr_lock, // .lock
input wire mst_bridge_to_sr_writeresponsevalid, // .writeresponsevalid
input wire reset_n // reset_n.reset_n
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, ans, Max, an, x; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &x); if (Max < x) { Max = x; ans = 0; an = 0; } if (x == Max) an++; else an = 0; ans = max(ans, an); } printf( %d , ans); } |
#include <bits/stdc++.h> using namespace std; long long max(long long a, long long b) { return (a > b ? a : b); } long long min(long long a, long long b) { return (a < b ? a : b); } void algo() { string s1, s2; char c; cin >> s1 >> s2; long long j = 0, len = s1.size(); for (long long i = 0; i < len; i++) { c = s1[i]; long long k = j; if (s1[i + 1] == c && i != len - 1) { if (c == s2[j]) j++; else { cout << NO ; return; } } else { while (c == s2[j]) { j++; } } if (k == j) { cout << NO ; return; } } if (j != s2.size()) cout << NO ; else cout << YES ; } int main() { ios::sync_with_stdio(0); cin.tie(0); long long t; cin >> t; while (t--) { algo(); cout << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_NSR_TB_V
`define SKY130_FD_SC_LP__UDP_DFF_NSR_TB_V
/**
* udp_dff$NSR: Negative edge triggered D flip-flop (Q output UDP)
* with both active high reset and set (set dominate).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dff_nsr.v"
module top();
// Inputs are registered
reg SET;
reg RESET;
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 RESET = 1'b0;
#60 SET = 1'b0;
#80 D = 1'b1;
#100 RESET = 1'b1;
#120 SET = 1'b1;
#140 D = 1'b0;
#160 RESET = 1'b0;
#180 SET = 1'b0;
#200 SET = 1'b1;
#220 RESET = 1'b1;
#240 D = 1'b1;
#260 SET = 1'bx;
#280 RESET = 1'bx;
#300 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_lp__udp_dff$NSR dut (.SET(SET), .RESET(RESET), .D(D), .Q(Q), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_NSR_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; using namespace std; const long long INF = 1LL << 60; const double PI = acos(-1); using ll = long long; using P = array<ll, 2>; template <typename T> istream& operator>>(istream& i, vector<T>& v) { for (ll j = (0); j < (ll)(v.size()); ++j) i >> v[j]; return i; } template <typename T> string join(vector<T>& v) { stringstream s; for (ll i = (0); i < (ll)(v.size()); ++i) s << << v[i]; return s.str().substr(1); } template <typename T> ostream& operator<<(ostream& o, vector<T>& v) { if (v.size()) o << join(v); return o; } template <typename T> string join(vector<vector<T>>& vv) { string s = n ; for (ll i = (0); i < (ll)(vv.size()); ++i) s += join(vv[i]) + n ; return s; } template <typename T> ostream& operator<<(ostream& o, vector<vector<T>>& vv) { if (vv.size()) o << join(vv); return o; } template <typename T1, typename T2> istream& operator>>(istream& i, pair<T1, T2>& v) { return i >> v.first >> v.second; } template <typename T1, typename T2> ostream& operator<<(ostream& o, pair<T1, T2>& v) { return o << ( << v.first << , << v.second << ) ; } template <typename T> istream& operator>>(istream& i, array<T, 2>& v) { i >> v[0] >> v[1]; return i; } template <typename T> ostream& operator<<(ostream& o, array<T, 2>& v) { return o << ( << v[0] << , << v[1] << ) ; return o; } int dx[4]{0, 1, 0, -1}; int dy[4]{1, 0, -1, 0}; void init_init_init() { ios_base::sync_with_stdio(false); cin.tie(NULL); std::cout << fixed << setprecision(10); } template <class T> T up(T a, T b) { assert(b); return (a + b - 1) / b; } template <typename... A> bool eq(A const&... a) { auto t = {a...}; assert(t.size()); auto tar = *t.begin(); for (const auto& e : t) if (tar != e) return false; return true; } template <class T> bool chmin(T& a, T b) { if (a > b) { a = b; return true; } return false; } template <class T> bool chmax(T& a, T b) { if (a < b) { a = b; return true; } return false; } template <class T> bool chmax(T& a, initializer_list<T> l) { return chmax(a, max(l)); } template <class T> bool chmin(T& a, initializer_list<T> l) { return chmin(a, min(l)); } int main(int argc, char** argv) { init_init_init(); ll x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; ll x3, y3, x4, y4; cin >> x3 >> y3 >> x4 >> y4; ll x5, y5, x6, y6; cin >> x5 >> y5 >> x6 >> y6; x1 *= 2, x2 *= 2, x3 *= 2, x4 *= 2, x5 *= 2, x6 *= 2; y1 *= 2, y2 *= 2, y3 *= 2, y4 *= 2, y5 *= 2, y6 *= 2; bool is{false}; for (ll x = x1; x <= x2; x++) { ll y = y1; if (!((x3 <= x and x <= x4 and y3 <= y and y <= y4) or (x5 <= x and x <= x6 and y5 <= y and y <= y6))) { is = true; } y = y2; if (!((x3 <= x and x <= x4 and y3 <= y and y <= y4) or (x5 <= x and x <= x6 and y5 <= y and y <= y6))) { is = true; } } for (ll y = y1; y <= y2; ++y) { ll x = x1; if (!((x3 <= x and x <= x4 and y3 <= y and y <= y4) or (x5 <= x and x <= x6 and y5 <= y and y <= y6))) { is = true; } x = x2; if (!((x3 <= x and x <= x4 and y3 <= y and y <= y4) or (x5 <= x and x <= x6 and y5 <= y and y <= y6))) { is = true; } } auto ok = is; std::cout << (ok ? YES : NO ) << std::endl; } |
#include <bits/stdc++.h> using namespace std; int n, m, z = 1, k; int main() { cin >> n >> m; if (n > m + 1 || n * 2 + 2 < m) return cout << -1, 0; while (n || m) { if ((m > n && k < 2) || z == 0) m--, z = 1, k++; else n--, z = 0, k = 0; cout << z; } } |
#include <bits/stdc++.h> using namespace std; long long jc[100005], fac[12], vp[12], P[12], s, v[100005][12], r[100005][12]; long long n, L, R, p; long long fpower(long long x, long long k) { long long ans = 1; while (k) { if (k & 1) ans = ans * x % p; x = x * x % p; k >>= 1; } if (!ans) return p; return ans; } long long c(long long x, long long y) { long long m[12] = {}, ans = 0; for (long long i = 1; i <= s; ++i) { long long o = v[x][i] - v[y][i] - v[x - y][i]; if (o >= vp[i]) continue; long long q = fpower(fac[i], vp[i] - o); m[i] = fpower(fac[i], o) * (r[x][i] * fpower(r[y][i] * r[x - y][i] % q, q / fac[i] * (fac[i] - 1) - 1) % q) % P[i]; ans += m[i] * fpower(p / P[i], P[i] / fac[i] * (fac[i] - 1)) % p; } return ans % p; } int main() { scanf( %I64d%I64d%I64d%I64d , &n, &p, &L, &R); jc[0] = 1; for (long long i = 1; i <= n; ++i) jc[i] = jc[i - 1] * i % p; long long t = p; for (long long i = 2; i * i <= t; ++i) { if (t % i) continue; fac[++s] = i; while (t % i == 0) vp[s]++, t /= i; P[s] = fpower(fac[s], vp[s]); } if (t > 1) fac[++s] = t, vp[s] = 1, P[s] = t; for (long long i = 1; i <= s; ++i) { r[0][i] = 1; for (long long j = 1; j <= n; ++j) { long long t = j, sum = 0; while (t % fac[i] == 0) t /= fac[i], sum++; v[j][i] = v[j - 1][i] + sum, r[j][i] = r[j - 1][i] * t % P[i]; } } long long ans = 0; for (long long i = 0; i <= n; ++i) { long long o = 0; if (i - L >= 0) o += c(i, (i - L) / 2); if (i - R - 1 >= 0) o -= c(i, (i - R - 1) / 2); ans = (ans + c(n, i) * o) % p; } printf( %I64d n , (p + ans % p) % p); return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:25:48 10/15/2013
// Design Name: VGA_Display
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab4/lab_pong/test_vga_display.v
// Project Name: lab_pong
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: VGA_Display
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_vga_display;
// Inputs
reg [9:0] actual_x;
reg [8:0] actual_y;
reg [8:0] barra_y;
reg [9:0] ball_x;
reg [8:0] ball_y;
// Outputs
wire r_out;
wire g_out;
wire b_out;
// Instantiate the Unit Under Test (UUT)
VGA_Display uut (
.actual_x(actual_x),
.actual_y(actual_y),
.barra_y(barra_y),
.ball_x(ball_x),
.ball_y(ball_y),
.r_out(r_out),
.g_out(g_out),
.b_out(b_out)
);
initial begin
// Initialize Inputs
actual_x = 0;
actual_y = 0;
barra_y = 0;
ball_x = 0;
ball_y = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
/* Verilog for cell 'PPR{sch}' from library 'wordlib8' */
/* Created on Sun Nov 03, 2013 19:07:25 */
/* Last revised on Sun Nov 03, 2013 21:35:17 */
/* Written on Sun Nov 03, 2013 21:35:28 by Electric VLSI Design System, version 8.06 */
module muddlib07__fulladder(a, b, c, cout, s);
input a;
input b;
input c;
output cout;
output s;
supply1 vdd;
supply0 gnd;
wire coutb, net_1, net_11, net_111, net_23, net_32, net_33, net_90, net_92;
wire net_94, net_95, sb;
tranif1 nmos_0(gnd, net_1, a);
tranif1 nmos_1(gnd, net_1, b);
tranif1 nmos_2(net_1, coutb, c);
tranif1 nmos_3(gnd, net_11, a);
tranif1 nmos_4(net_11, coutb, b);
tranif1 nmos_5(gnd, net_23, a);
tranif1 nmos_6(gnd, net_23, b);
tranif1 nmos_7(gnd, net_23, c);
tranif1 nmos_8(net_23, sb, coutb);
tranif1 nmos_9(gnd, net_33, a);
tranif1 nmos_10(net_33, net_32, b);
tranif1 nmos_11(net_32, sb, c);
tranif1 nmos_12(gnd, cout, coutb);
tranif1 nmos_13(gnd, s, sb);
tranif0 pmos_1(sb, net_92, c);
tranif0 pmos_2(net_92, net_90, b);
tranif0 pmos_3(net_90, vdd, a);
tranif0 pmos_4(sb, net_94, coutb);
tranif0 pmos_5(net_94, vdd, b);
tranif0 pmos_6(net_94, vdd, c);
tranif0 pmos_7(net_94, vdd, a);
tranif0 pmos_8(cout, vdd, coutb);
tranif0 pmos_9(net_95, vdd, a);
tranif0 pmos_10(coutb, net_95, b);
tranif0 pmos_11(net_111, vdd, a);
tranif0 pmos_12(net_111, vdd, b);
tranif0 pmos_13(coutb, net_111, c);
tranif0 pmos_14(s, vdd, sb);
endmodule /* muddlib07__fulladder */
module muddlib07__inv_1x(a, y);
input a;
output y;
supply1 vdd;
supply0 gnd;
tranif1 nmos_0(gnd, y, a);
tranif0 pmos_0(y, vdd, a);
endmodule /* muddlib07__inv_1x */
module muddlib07__nand2_1x(a, b, y);
input a;
input b;
output y;
supply1 vdd;
supply0 gnd;
wire net_5;
tranif1 nmos_0(net_5, y, b);
tranif1 nmos_1(gnd, net_5, a);
tranif0 pmos_0(y, vdd, b);
tranif0 pmos_1(y, vdd, a);
endmodule /* muddlib07__nand2_1x */
module muddlib07__xnor_ds(A, B, Y);
input A;
input B;
output Y;
supply1 vdd;
supply0 gnd;
wire net_0, net_1, net_11, net_28;
tranif1 nmos_0(net_0, net_1, A);
tranif1 nmos_1(gnd, net_0, B);
tranif1 nmos_4(net_11, Y, A);
tranif1 nmos_5(net_11, Y, B);
tranif1 nmos_6(gnd, net_11, net_1);
tranif0 pmos_0(net_1, vdd, A);
tranif0 pmos_1(net_1, vdd, B);
tranif0 pmos_2(Y, vdd, net_1);
tranif0 pmos_3(net_28, vdd, B);
tranif0 pmos_4(Y, net_28, A);
endmodule /* muddlib07__xnor_ds */
module wordlib8__FTC(Cin, I1, I2, I3, I4, C, Cout, S);
input Cin;
input I1;
input I2;
input I3;
input I4;
output C;
output Cout;
output S;
supply1 vdd;
supply0 gnd;
wire net_10, net_13, net_2, net_5, net_9;
muddlib07__fulladder fulladde_0(.a(I2), .b(I1), .c(I3), .cout(Cout),
.s(net_2));
muddlib07__inv_1x inv_1x_0(.a(net_5), .y(net_9));
muddlib07__nand2_1x nand2_1x_0(.a(Cin), .b(I4), .y(net_13));
muddlib07__nand2_1x nand2_1x_2(.a(net_2), .b(net_9), .y(net_10));
muddlib07__nand2_1x nand2_1x_3(.a(net_10), .b(net_13), .y(C));
muddlib07__xnor_ds xnor_ds_0(.A(Cin), .B(I4), .Y(net_5));
muddlib07__xnor_ds xnor_ds_1(.A(net_5), .B(net_2), .Y(S));
endmodule /* wordlib8__FTC */
module PPR(PP0, PP1, PP2, PP3, Sign0, Sign1, Sign2, C0, C1, C10, C11, C12, C2,
C3, C4, C5, C6, C7, C8, C9, S0, S1, S10, S11, S12, S2, S3, S4, S5, S6,
S7, S8, S9);
input [8:0] PP0;
input [8:0] PP1;
input [8:0] PP2;
input [8:0] PP3;
input Sign0;
input Sign1;
input Sign2;
output C0;
output C1;
output C10;
output C11;
output C12;
output C2;
output C3;
output C4;
output C5;
output C6;
output C7;
output C8;
output C9;
output S0;
output S1;
output S10;
output S11;
output S12;
output S2;
output S3;
output S4;
output S5;
output S6;
output S7;
output S8;
output S9;
supply1 vdd;
supply0 gnd;
wire FTC_19_Cout, net_202, net_214, net_221, net_226, net_239, net_244;
wire net_253, net_262, net_271, net_284, net_364, net_366;
wordlib8__FTC FTC_3(.Cin(gnd), .I1(PP0[2]), .I2(PP1[0]), .I3(gnd), .I4(gnd),
.C(C0), .Cout(net_364), .S(S0));
wordlib8__FTC FTC_6(.Cin(net_364), .I1(PP0[3]), .I2(PP1[1]), .I3(gnd),
.I4(gnd), .C(C1), .Cout(net_366), .S(S1));
wordlib8__FTC FTC_8(.Cin(net_366), .I1(PP0[4]), .I2(PP1[2]), .I3(PP2[0]),
.I4(gnd), .C(C2), .Cout(net_202), .S(S2));
wordlib8__FTC FTC_9(.Cin(net_202), .I1(PP0[5]), .I2(PP1[3]), .I3(PP2[1]),
.I4(gnd), .C(C3), .Cout(net_214), .S(S3));
wordlib8__FTC FTC_10(.Cin(net_214), .I1(PP0[6]), .I2(PP1[4]), .I3(PP2[2]),
.I4(PP3[0]), .C(C4), .Cout(net_221), .S(S4));
wordlib8__FTC FTC_11(.Cin(net_221), .I1(PP0[7]), .I2(PP1[5]), .I3(PP2[3]),
.I4(PP3[1]), .C(C5), .Cout(net_226), .S(S5));
wordlib8__FTC FTC_12(.Cin(net_226), .I1(PP0[8]), .I2(PP1[6]), .I3(PP2[4]),
.I4(PP3[2]), .C(C6), .Cout(net_239), .S(S6));
wordlib8__FTC FTC_13(.Cin(net_239), .I1(Sign0), .I2(PP1[7]), .I3(PP2[5]),
.I4(PP3[3]), .C(C7), .Cout(net_244), .S(S7));
wordlib8__FTC FTC_14(.Cin(net_244), .I1(Sign0), .I2(PP1[8]), .I3(PP2[6]),
.I4(PP3[4]), .C(C8), .Cout(net_253), .S(S8));
wordlib8__FTC FTC_15(.Cin(net_253), .I1(Sign0), .I2(Sign1), .I3(PP2[7]),
.I4(PP3[5]), .C(C9), .Cout(net_262), .S(S9));
wordlib8__FTC FTC_17(.Cin(net_262), .I1(Sign0), .I2(Sign1), .I3(PP2[8]),
.I4(PP3[6]), .C(C10), .Cout(net_271), .S(S10));
wordlib8__FTC FTC_18(.Cin(net_271), .I1(Sign0), .I2(Sign1), .I3(Sign2),
.I4(PP3[7]), .C(C11), .Cout(net_284), .S(S11));
wordlib8__FTC FTC_19(.Cin(net_284), .I1(Sign0), .I2(Sign1), .I3(Sign2),
.I4(PP3[8]), .C(C12), .Cout(FTC_19_Cout), .S(S12));
endmodule /* PPR */
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the tx_engine and buffers the input
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
input TXN_DONE_ACK, // Write transaction actual transfer length read
input [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather data
input SG_DATA_EMPTY, // Scatter gather buffer empty
output SG_DATA_REN, // Scatter gather data read enable
output SG_RST, // Scatter gather reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire wGateRen;
wire wGateEmpty;
wire [C_DATA_WIDTH:0] wGateData;
wire wBufWen;
wire [C_FIFO_DEPTH_WIDTH-1:0] wBufCount;
wire [C_DATA_WIDTH-1:0] wBufData;
wire wTxn;
wire wTxnAck;
wire wTxnLast;
wire [31:0] wTxnLen;
wire [30:0] wTxnOff;
wire [31:0] wTxnWordsRecvd;
wire wTxnDone;
wire wTxnErr;
wire wSgElemRen;
wire wSgElemRdy;
wire wSgElemEmpty;
wire [31:0] wSgElemLen;
wire [63:0] wSgElemAddr;
reg [4:0] rWideRst=0;
reg rRst=0;
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Capture channel transaction open/close events as well as channel data.
tx_port_channel_gate_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.RD_CLK(CLK),
.RD_DATA(wGateData),
.RD_EMPTY(wGateEmpty),
.RD_EN(wGateRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
// Filter transaction events from channel data. Use the events to put only
// the requested amount of data into the port buffer.
tx_port_monitor_32 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
.RST(rRst),
.CLK(CLK),
.EVT_DATA(wGateData),
.EVT_DATA_EMPTY(wGateEmpty),
.EVT_DATA_RD_EN(wGateRen),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount),
.TXN(wTxn),
.ACK(wTxnAck),
.LAST(wTxnLast),
.LEN(wTxnLen),
.OFF(wTxnOff),
.WORDS_RECVD(wTxnWordsRecvd),
.DONE(wTxnDone),
.TX_ERR(SG_ERR)
);
// Buffer the incoming channel data.
tx_port_buffer_32 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
.CLK(CLK),
.RST(rRst | (TXN_DONE & wTxnErr)),
.RD_DATA(TX_DATA),
.RD_EN(TX_DATA_REN),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | SG_RST),
.BUF_DATA(SG_DATA),
.BUF_DATA_EMPTY(SG_DATA_EMPTY),
.BUF_DATA_REN(SG_DATA_REN),
.VALID(wSgElemRdy),
.EMPTY(wSgElemEmpty),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Controls the flow of request to the tx engine for transfers in a transaction.
tx_port_writer writer (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN),
.TXN_ACK(TXN_ACK),
.TXN_LEN(TXN_LEN),
.TXN_OFF_LAST(TXN_OFF_LAST),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.NEW_TXN(wTxn),
.NEW_TXN_ACK(wTxnAck),
.NEW_TXN_LAST(wTxnLast),
.NEW_TXN_LEN(wTxnLen),
.NEW_TXN_OFF(wTxnOff),
.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
.NEW_TXN_DONE(wTxnDone),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_EMPTY(wSgElemEmpty),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(SG_RST),
.SG_ERR(SG_ERR),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_LAST(),
.TX_SENT(TX_SENT)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLCLKP_BLACKBOX_V
`define SKY130_FD_SC_HVL__SDLCLKP_BLACKBOX_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__sdlclkp (
GCLK,
SCE ,
GATE,
CLK
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLCLKP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100010, M = 100010, SIZE = 26, LEN = 1000010; int n, m, dfk = 0; namespace BIT { int c[LEN]; void Add(int x, int k) { for (; x <= dfk; x += x & -x) c[x] += k; return; } int Sum(int x) { int sum = 0; for (; x; x -= x & -x) sum += c[x]; return sum; } } // namespace BIT struct Trie_Node; struct Edge; struct Trie_Node { Trie_Node() { dfn = size = 0; head = NULL; fail = NULL; for (int i = 0; i < SIZE; ++i) link[i] = NULL; return; } Trie_Node *fail, *link[SIZE]; Edge *head; int dfn, size; } * node[M]; struct Edge { Edge() { p = NULL; nxt = NULL; return; } Trie_Node *p; Edge *nxt; }; inline void Add_Edge(Trie_Node *u, Trie_Node *v) { Edge *w = new Edge(); w->p = v; w->nxt = u->head; u->head = w; return; } bool exist[M]; char buff[LEN]; queue<Trie_Node *> que; void BFS(Trie_Node *root) { root->fail = root; for (int i = 0; i < SIZE; ++i) if (root->link[i]) { Add_Edge(root->link[i]->fail = root, root->link[i]); que.push(root->link[i]); } else root->link[i] = root; while (!que.empty()) { Trie_Node *u = que.front(); que.pop(); for (int i = 0; i < SIZE; ++i) if (u->link[i]) { Add_Edge(u->link[i]->fail = u->fail->link[i], u->link[i]); que.push(u->link[i]); } else u->link[i] = u->fail->link[i]; } return; } void DFS(Trie_Node *u) { u->dfn = ++dfk; u->size = 1; for (Edge *i = u->head; i; i = i->nxt) { Trie_Node *v = i->p; DFS(v); u->size += v->size; } return; } long long Query(Trie_Node *root, char *s) { long long res = 0; int j = 1, m = strlen(s + 1); for (Trie_Node *i = root; j <= m; ++j) { i = i->link[s[j] - 97]; res += BIT::Sum(i->dfn); } return res; } int main() { scanf( %d%d , &n, &m); Trie_Node *root = new Trie_Node(); for (int i = 1; i <= m; ++i) { scanf( %s , buff + 1); int k = strlen(buff + 1); node[i] = root; for (int j = 1; j <= k; node[i] = node[i]->link[buff[j] - 97], ++j) if (!node[i]->link[buff[j] - 97]) node[i]->link[buff[j] - 97] = new Trie_Node(); } BFS(root); DFS(root); using namespace BIT; for (int i = 1; i <= m; ++i) { Add(node[i]->dfn, 1); Add(node[i]->dfn + node[i]->size, -1); } memset(exist, 1, sizeof(exist)); for (int i = 1; i <= n; ++i) { char t; cin >> t; if (t != ? ) { int x; scanf( %d , &x); if (t != - ) { if (!exist[x]) { exist[x] = 1; Add(node[x]->dfn, 1); Add(node[x]->dfn + node[x]->size, -1); } } else if (exist[x]) { exist[x] = 0; Add(node[x]->dfn, -1); Add(node[x]->dfn + node[x]->size, 1); } } else { scanf( %s , buff + 1); printf( %lld n , Query(root, buff)); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int b[100]; for (int i = 0; i < 100; i++) b[i] = 0; int x; for (int i = 0; i < n; i++) { cin >> x; b[x - 1] += 1; } x = b[0]; for (int i = 0; i < 100; i++) { if (b[i] > x) { x = b[i]; } } if (x % k == 0) x = x / k; else x = x / k + 1; x = x * k; k = 0; for (int i = 0; i < 100; i++) if (b[i]) { k += x - b[i]; } cout << k; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, arr[1000], dp[1000][10]; int solve(int i, int flag) { if (i >= n) return 0; if (dp[i][flag] != -1) return dp[i][flag]; if (arr[i] == 0) dp[i][flag] = 1 + solve(i + 1, 0); else if (arr[i] == 1) { if (flag == 0 || flag == 1) { dp[i][flag] = min(solve(i + 1, 2), 1 + solve(i + 1, 0)); } else dp[i][flag] = 1 + solve(i + 1, 0); } else if (arr[i] == 2) { if (flag == 0 || flag == 2) { dp[i][flag] = min(1 + solve(i + 1, 0), solve(i + 1, 1)); } else dp[i][flag] = 1 + solve(i + 1, 0); } else { if (flag == 0) { dp[i][flag] = min(solve(i + 1, 2), min(1 + solve(i + 1, 0), solve(i + 1, 1))); } else if (flag == 1) { dp[i][flag] = min(solve(i + 1, 2), 1 + solve(i + 1, 0)); } else { dp[i][flag] = min(solve(i + 1, 1), 1 + solve(i + 1, 0)); } } return dp[i][flag]; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> arr[i]; memset(dp, -1, sizeof(dp)); cout << solve(0, 0) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long k, n, w; cin >> k >> n >> w; long long req = ((w * (w + 1)) / 2) * k; req = req - n; if (req > 0) cout << req; else cout << 0 ; } |
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_mulAddRecFN_add#(parameter expWidth = 3, parameter sigWidth = 3);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
parameter maxNumErrors = 20;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam formatWidth = expWidth + sigWidth;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg [(`floatControlWidth - 1):0] control;
reg [2:0] roundingMode;
reg [(formatWidth - 1):0] a, b, expectOut;
reg [4:0] expectExceptionFlags;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recA, recB, recExpectOut;
fNToRecFN#(expWidth, sigWidth) fNToRecFN_a(a, recA);
fNToRecFN#(expWidth, sigWidth) fNToRecFN_b(b, recB);
fNToRecFN#(expWidth, sigWidth)
fNToRecFN_expectOut(expectOut, recExpectOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recOut;
wire [4:0] exceptionFlags;
mulAddRecFN#(expWidth, sigWidth)
mulAddRecFN_add(
control,
2'b0,
recA,
{2'b01, {(expWidth + sigWidth - 1){1'b0}}},
recB,
roundingMode,
recOut,
exceptionFlags
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire sameOut;
sameRecFN#(expWidth, sigWidth) sameRecFN(recOut, recExpectOut, sameOut);
wire isQuietNaNOut =
(recOut[(expWidth + sigWidth - 1):(expWidth + sigWidth - 3)] == 'b111)
&& recOut[sigWidth - 2];
wire isQuietNaNExpectOut =
(recExpectOut[(expWidth + sigWidth - 1):(expWidth + sigWidth - 3)]
== 'b111)
&& recExpectOut[sigWidth - 2];
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
integer errorCount, count, partialCount;
initial begin
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$fwrite('h80000002, "Testing 'mulAddRecF%0d_add'", formatWidth);
if ($fscanf('h80000000, "%h %h", control, roundingMode) < 2) begin
$fdisplay('h80000002, ".\n--> Invalid test-cases input.");
`finish_fail;
end
$fdisplay(
'h80000002,
", control %H, rounding mode %0d:",
control,
roundingMode
);
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
errorCount = 0;
count = 0;
partialCount = 0;
begin :TestLoop
while (
$fscanf(
'h80000000,
"%h %h %h %h",
a,
b,
expectOut,
expectExceptionFlags
) == 4
) begin
#1;
partialCount = partialCount + 1;
if (partialCount == 10000) begin
count = count + 10000;
$fdisplay('h80000002, "%0d...", count);
partialCount = 0;
end
/*------------------------------------------------------------
| When a fused multiply-add is used for addition, quiet NaN
| results may not be as expect for an addition operation.
*------------------------------------------------------------*/
if (
!(sameOut || (isQuietNaNOut && isQuietNaNExpectOut))
|| (exceptionFlags !== expectExceptionFlags)
) begin
if (errorCount == 0) begin
$display(
"Errors found in 'mulAddRecF%0d_add', control %H, rounding mode %0d:",
formatWidth,
control,
roundingMode
);
end
$write("%H %H", recA, recB);
if (formatWidth > 64) begin
$write("\n\t");
end else begin
$write(" ");
end
$write("=> %H %H", recOut, exceptionFlags);
if (formatWidth > 32) begin
$write("\n\t");
end else begin
$write(" ");
end
$display(
"expected %H %H", recExpectOut, expectExceptionFlags);
errorCount = errorCount + 1;
if (errorCount == maxNumErrors) disable TestLoop;
end
#1;
end
end
count = count + partialCount;
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
if (errorCount) begin
$fdisplay(
'h80000002,
"--> In %0d tests, %0d errors found.",
count,
errorCount
);
`finish_fail;
end else if (count == 0) begin
$fdisplay('h80000002, "--> Invalid test-cases input.");
`finish_fail;
end else begin
$display(
"In %0d tests, no errors found in 'mulAddRecF%0d_add', control %H, rounding mode %0d.",
count,
formatWidth,
control,
roundingMode
);
end
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$finish;
end
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_mulAddRecF16_add;
test_mulAddRecFN_add#(5, 11) test_mulAddRecF16_add();
endmodule
module test_mulAddRecF32_add;
test_mulAddRecFN_add#(8, 24) test_mulAddRecF32_add();
endmodule
module test_mulAddRecF64_add;
test_mulAddRecFN_add#(11, 53) test_mulAddRecF64_add();
endmodule
module test_mulAddRecF128_add;
test_mulAddRecFN_add#(15, 113) test_mulAddRecF128_add();
endmodule
|
`default_nettype none
`timescale 1ns / 1ps
// The RAMCON core exposes an asynchronous, static RAM as a
// synchronous, Wishbone B4 compatible peripheral.
//
// NOTE: This module does not use the chip-enable input of the
// static RAM chip. It statically hardwires the _CE signal in
// an asserted state.
//
// NOTE: This module does not bind to inout pins. You must do this
// at the top-level, as how this is done will be FPGA-dependent.
//
// NOTE: This module exposes a STALL_O signal. However, this
// module currently never stalls the master. RAMCON will always
// acknowledge a transfer one cycle after it's registered.
module ramcon(
input clk_i,
input reset_i,
input cyc_i,
input stb_i,
input we_i,
input [1:0] sel_i,
input [19:1] adr_i,
input [15:0] dat_i,
output ack_o,
output [15:0] dat_o,
output stall_o,
output _sram_ce,
output _sram_we,
output _sram_oe,
output _sram_ub,
output _sram_lb,
output [19:1] sram_a,
output [15:0] sram_d_out,
input [15:0] sram_d_in
);
reg transfer;
reg [1:0] selects;
reg write;
reg [15:0] data_in;
reg [19:1] address;
assign ack_o = transfer;
wire sram_we = transfer & write & ~clk_i;
wire sram_oe = transfer & ~write & ~clk_i;
assign _sram_ce = 0;
assign _sram_we = ~sram_we;
assign _sram_oe = ~sram_oe;
assign _sram_ub = ~selects[1];
assign _sram_lb = ~selects[0];
assign dat_o = sram_oe ? sram_d_in : 0;
assign sram_a = address;
assign sram_d_out = data_in;
assign stall_o = 0;
always @(posedge clk_i) begin
transfer <= cyc_i & stb_i;
selects <= sel_i;
write <= we_i;
address <= adr_i;
data_in <= dat_i;
end
endmodule
`ifndef SYNTHESIS
module ramcon_tb();
reg clk_i, reset_i, cyc_i, stb_i, we_i;
reg [1:0] sel_i;
reg [19:1] adr_i;
reg [15:0] dat_i;
wire ack_o;
wire _sram_we, _sram_oe, _sram_ub, _sram_lb;
wire [15:0] dat_o, sram_d_out;
wire [19:1] sram_a;
ramcon rc(
.clk_i(clk_i),
.reset_i(reset_i),
.cyc_i(cyc_i),
.stb_i(stb_i),
.we_i(we_i),
.sel_i(sel_i),
.adr_i(adr_i),
.ack_o(ack_o),
.dat_o(dat_o),
.dat_i(dat_i),
._sram_we(_sram_we),
._sram_oe(_sram_oe),
._sram_ub(_sram_ub),
._sram_lb(_sram_lb),
.sram_a(sram_a),
.sram_d_in(16'hF00D),
.sram_d_out(sram_d_out)
);
always begin
#5 clk_i <= ~clk_i;
end
initial begin
$dumpfile("ramcon.vcd");
$dumpvars;
{clk_i, reset_i, cyc_i, stb_i, we_i, sel_i, adr_i, dat_i} = 0;
wait(~clk_i); wait(clk_i);
reset_i <= 1;
wait(~clk_i); wait(clk_i);
adr_i <= 0;
reset_i <= 0;
wait(~clk_i); wait(clk_i);
cyc_i <= 1;
stb_i <= 1;
wait(~clk_i); wait(clk_i);
stb_i <= 0;
wait(~clk_i); wait(clk_i);
stb_i <= 1;
wait(~clk_i); wait(clk_i);
sel_i <= 2'b01;
wait(~clk_i); wait(clk_i);
sel_i <= 2'b10;
wait(~clk_i); wait(clk_i);
sel_i <= 2'b11;
stb_i <= 0;
wait(~clk_i); wait(clk_i);
cyc_i <= 0;
sel_i <= 0;
wait(~clk_i); wait(clk_i);
wait(~clk_i); wait(clk_i);
cyc_i <= 1;
stb_i <= 1;
adr_i <= 20'h00000;
we_i <= 0;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00001;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00002;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00003;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00000;
we_i <= 1;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00001;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00002;
wait(~clk_i); wait(clk_i);
adr_i <= 20'h00003;
wait(~clk_i); wait(clk_i);
cyc_i <= 0;
stb_i <= 0;
#100;
$stop;
end
endmodule
`endif
|
module idec(aluf,readAddrA,readAddrB, writeAddress,selA,selB,clrR,
clrIr0, gate, rw, sel_addr_reg, dojump, wrAddr,
ir0q,ir1q,flags,reset);
output [3:0] aluf,readAddrA,readAddrB, writeAddress;
output [1:0] selA,selB;
output clrR, clrIr0, gate, rw, sel_addr_reg, dojump,wrAddr ;
input [15:0] ir0q,ir1q;
input [3:0] flags;
input reset;
/* instruction format
ffff dddd ssss m ccc
ffff <- Four bit alu function ir[15:12]
dddd <- four bit destination register adderss and second operand
ssss <- four bit source register address
0 - immidiate data
1 - pc
2 - addressing register for load/store
3 to 15 general registers in reg file
m <- memory indirection bit 1 uses the address from r2
ccc <- condition codes for jump
ccc <-- encoded condition ir[2:0]
unc 000 pos 001
neg 010 zero 011
parodd 100 carry 101
ncarry 110 nzero 111
*/
wire m0 = ir0q[3],
m1 = ir1q[3];
/* jump condition codes in ir[2:0] */
`define unc 3'b000
`define pos 3'b001
`define neg 3'b010
`define zero 3'b011
`define parodd 3'b100
`define carry 3'b101
`define ncarry 3'b110
`define nzero 3'b111
function jmpchk;
input [2:0] condition;
input [3:0] flags;
reg sign,carry,parity,zero;
begin
{sign,carry,parity,zero} = flags;
case (condition)
`unc: jmpchk = 1;
`pos: jmpchk = ~ sign;
`neg: jmpchk = sign;
`zero: jmpchk = zero;
`parodd: jmpchk = parity;
`carry: jmpchk = carry;
`ncarry: jmpchk = ~carry;
`nzero: jmpchk = ~zero;
endcase
end
endfunction
assign #1
// Alu function comes from ir1 always
aluf = ir1q[15:12],
// the sources for the alu come from ir0
readAddrA = ir0q[11:8],
readAddrB = ir0q[ 7:4],
// the destination for the data from the alu is comes from Ir1
writeAddress = ir1q[11:8],
// The Mux selects can be derived from read Addresses
selA = readAddrA[3:2] ? 2'b11 : readAddrA[1:0],
selB = readAddrB[3:2] ? 2'b11 : readAddrB[1:0],
// Data goes to/from memory if the m bit is set when
// ssss == 0000 in ir0 or dddd == 0000 in ir1
sel_addr_reg = (m0 & (ir0q[ 7:4] == 4'b0))
| (m1 & (ir1q[11:8] == 4'b0)) ,
// the read/write signal is low for a memory write which can only occur
// when the instruction in ir1 had a desination or memory
rw = ~(m1 & (ir1q[11:8] == 4'b0)) ,
// When the destination is the PC(1) check the condition flags
dojump = jmpchk(ir1q[2:0],flags) & (ir1q[11:8] == 3'h1),
// If the desitation is the address regster (2) gernate a write for it
wrAddr = (ir1q[11:8] == 3'h2),
// The flag registers are clocked every alu cycle except on move operartions
gate = | ir1q[15:12] ,
// reset and clear signals
clrR = reset,
// Clear the pipeline if we are jumping or if data is coming from memory
// or if writing to memory
clrIr0 = reset | dojump
| ((ir0q[ 7:4] == 4'b0) & (ir0q[ 11:8] != 4'b0))
| ~rw ;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_port_requester.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Issues read requests to the tx_engine for the rx_port
// and sg_list_requester modules in the rx_port. Expects those modules to update
// their address and length values after every request issued. Also expects them
// to update their space available values within 6 cycles of a change to the
// RX_LEN.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_RXPORTREQ_RX_TX 2'b00
`define S_RXPORTREQ_TX_RX 2'b01
`define S_RXPORTREQ_ISSUE 2'b10
`timescale 1ns/1ns
module rx_port_requester_mux (
input RST,
input CLK,
input SG_RX_REQ, // Scatter gather RX read request
input [9:0] SG_RX_LEN, // Scatter gather RX read request length
input [63:0] SG_RX_ADDR, // Scatter gather RX read request address
output SG_RX_REQ_PROC, // Scatter gather RX read request processing
input SG_TX_REQ, // Scatter gather TX read request
input [9:0] SG_TX_LEN, // Scatter gather TX read request length
input [63:0] SG_TX_ADDR, // Scatter gather TX read request address
output SG_TX_REQ_PROC, // Scatter gather TX read request processing
input MAIN_REQ, // Main read request
input [9:0] MAIN_LEN, // Main read request length
input [63:0] MAIN_ADDR, // Main read request address
output MAIN_REQ_PROC, // Main read request processing
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output REQ_ACK // Request accepted
);
reg rRxReqAck=0, _rRxReqAck=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_RXPORTREQ_RX_TX, _rState=`S_RXPORTREQ_RX_TX;
reg [9:0] rLen=0, _rLen=0;
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg rSgRxAck=0, _rSgRxAck=0;
reg rSgTxAck=0, _rSgTxAck=0;
reg rMainAck=0, _rMainAck=0;
reg rAck=0, _rAck=0;
assign SG_RX_REQ_PROC = rSgRxAck;
assign SG_TX_REQ_PROC = rSgTxAck;
assign MAIN_REQ_PROC = rMainAck;
assign RX_REQ = rState[1]; // S_RXPORTREQ_ISSUE
assign RX_REQ_TAG = {rSgTxAck, rSgRxAck};
assign RX_REQ_ADDR = rAddr;
assign RX_REQ_LEN = rLen;
assign REQ_ACK = rAck;
// Buffer signals that come from outside the rx_port.
always @ (posedge CLK) begin
rRxReqAck <= #1 (RST ? 1'd0 : _rRxReqAck);
end
always @ (*) begin
_rRxReqAck = RX_REQ_ACK;
end
// Handle issuing read requests. Scatter gather requests are processed
// with higher priority than the main channel.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_RXPORTREQ_RX_TX : _rState);
rLen <= #1 _rLen;
rAddr <= #1 _rAddr;
rSgRxAck <= #1 _rSgRxAck;
rSgTxAck <= #1 _rSgTxAck;
rMainAck <= #1 _rMainAck;
rAck <= #1 _rAck;
end
always @ (*) begin
_rState = rState;
_rLen = rLen;
_rAddr = rAddr;
_rSgRxAck = rSgRxAck;
_rSgTxAck = rSgTxAck;
_rMainAck = rMainAck;
_rAck = rAck;
case (rState)
`S_RXPORTREQ_RX_TX: begin // Wait for a new read request
if (SG_RX_REQ) begin
_rLen = SG_RX_LEN;
_rAddr = SG_RX_ADDR;
_rSgRxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (SG_TX_REQ) begin
_rLen = SG_TX_LEN;
_rAddr = SG_TX_ADDR;
_rSgTxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (MAIN_REQ) begin
_rLen = MAIN_LEN;
_rAddr = MAIN_ADDR;
_rMainAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else begin
_rState = `S_RXPORTREQ_TX_RX;
end
end
`S_RXPORTREQ_TX_RX: begin // Wait for a new read request
if (SG_TX_REQ) begin
_rLen = SG_TX_LEN;
_rAddr = SG_TX_ADDR;
_rSgTxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (SG_RX_REQ) begin
_rLen = SG_RX_LEN;
_rAddr = SG_RX_ADDR;
_rSgRxAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else if (MAIN_REQ) begin
_rLen = MAIN_LEN;
_rAddr = MAIN_ADDR;
_rMainAck = 1;
_rAck = 1;
_rState = `S_RXPORTREQ_ISSUE;
end
else begin
_rState = `S_RXPORTREQ_RX_TX;
end
end
`S_RXPORTREQ_ISSUE: begin // Issue the request
_rAck = 0;
if (rRxReqAck) begin
_rSgRxAck = 0;
_rSgTxAck = 0;
_rMainAck = 0;
if (rSgRxAck)
_rState = `S_RXPORTREQ_TX_RX;
else
_rState = `S_RXPORTREQ_RX_TX;
end
end
default: begin
_rState = `S_RXPORTREQ_RX_TX;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { vector<stack<int> > vs; int maxi = -1, maximum = 0, nbVertices, n, type[100009], destination[100009], source[100009]; cin >> n; vs = vector<stack<int> >(n); for (int i = 0; i < n; ++i) { source[i] = 0; } for (int i = 0; i < n; ++i) { cin >> type[i]; } for (int i = 0; i < n; ++i) { cin >> destination[i]; destination[i] -= 1; if (destination[i] != -1) source[destination[i]]++; } for (int i = 0; i < n; ++i) { if (type[i]) { int j = i; nbVertices = 1; while (source[destination[j]] == 1 && destination[j] != -1) { ++nbVertices; vs[i].push(j + 1); j = destination[j]; } vs[i].push(j + 1); if (maximum < nbVertices) { maximum = nbVertices; maxi = i; } } } cout << maximum << endl; while (vs[maxi].size()) { int top = vs[maxi].top(); cout << top << ; vs[maxi].pop(); } cout << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_4_V
`define SKY130_FD_SC_LS__O41AI_4_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41ai_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_4_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: driver_7segment.v
//
// *Module Description:
// Driver for the four-digit, seven-segment LED display.
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 111 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $
//----------------------------------------------------------------------------
module driver_7segment (
// OUTPUTs
per_dout, // Peripheral data output
seg_a, // Segment A control
seg_b, // Segment B control
seg_c, // Segment C control
seg_d, // Segment D control
seg_e, // Segment E control
seg_f, // Segment F control
seg_g, // Segment G control
seg_dp, // Segment DP control
seg_an0, // Anode 0 control
seg_an1, // Anode 1 control
seg_an2, // Anode 2 control
seg_an3, // Anode 3 control
// INPUTs
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
puc_rst // Main system reset
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
output seg_a; // Segment A control
output seg_b; // Segment B control
output seg_c; // Segment C control
output seg_d; // Segment D control
output seg_e; // Segment E control
output seg_f; // Segment F control
output seg_g; // Segment G control
output seg_dp; // Segment DP control
output seg_an0; // Anode 0 control
output seg_an1; // Anode 1 control
output seg_an2; // Anode 2 control
output seg_an3; // Anode 3 control
// INPUTs
//=========
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input puc_rst; // Main system reset
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15'h0090;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 2;
// Register addresses offset
parameter [DEC_WD-1:0] DIGIT0 = 'h0,
DIGIT1 = 'h1,
DIGIT2 = 'h2,
DIGIT3 = 'h3;
// Register one-hot decoder utilities
parameter DEC_SZ = 2**DEC_WD;
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] DIGIT0_D = (BASE_REG << DIGIT0),
DIGIT1_D = (BASE_REG << DIGIT1),
DIGIT2_D = (BASE_REG << DIGIT2),
DIGIT3_D = (BASE_REG << DIGIT3);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {1'b0, per_addr[DEC_WD-2:0]};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (DIGIT0_D & {DEC_SZ{(reg_addr==(DIGIT0 >>1))}}) |
(DIGIT1_D & {DEC_SZ{(reg_addr==(DIGIT1 >>1))}}) |
(DIGIT2_D & {DEC_SZ{(reg_addr==(DIGIT2 >>1))}}) |
(DIGIT3_D & {DEC_SZ{(reg_addr==(DIGIT3 >>1))}});
// Read/Write probes
wire reg_lo_write = per_we[0] & reg_sel;
wire reg_hi_write = per_we[1] & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_hi_wr = reg_dec & {DEC_SZ{reg_hi_write}};
wire [DEC_SZ-1:0] reg_lo_wr = reg_dec & {DEC_SZ{reg_lo_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// DIGIT0 Register
//-----------------
reg [7:0] digit0;
wire digit0_wr = DIGIT0[0] ? reg_hi_wr[DIGIT0] : reg_lo_wr[DIGIT0];
wire [7:0] digit0_nxt = DIGIT0[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit0 <= 8'h00;
else if (digit0_wr) digit0 <= digit0_nxt;
// DIGIT1 Register
//-----------------
reg [7:0] digit1;
wire digit1_wr = DIGIT1[0] ? reg_hi_wr[DIGIT1] : reg_lo_wr[DIGIT1];
wire [7:0] digit1_nxt = DIGIT1[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit1 <= 8'h00;
else if (digit1_wr) digit1 <= digit1_nxt;
// DIGIT2 Register
//-----------------
reg [7:0] digit2;
wire digit2_wr = DIGIT2[0] ? reg_hi_wr[DIGIT2] : reg_lo_wr[DIGIT2];
wire [7:0] digit2_nxt = DIGIT2[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit2 <= 8'h00;
else if (digit2_wr) digit2 <= digit2_nxt;
// DIGIT3 Register
//-----------------
reg [7:0] digit3;
wire digit3_wr = DIGIT3[0] ? reg_hi_wr[DIGIT3] : reg_lo_wr[DIGIT3];
wire [7:0] digit3_nxt = DIGIT3[0] ? per_din[15:8] : per_din[7:0];
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) digit3 <= 8'h00;
else if (digit3_wr) digit3 <= digit3_nxt;
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
// Data output mux
wire [15:0] digit0_rd = (digit0 & {8{reg_rd[DIGIT0]}}) << (8 & {4{DIGIT0[0]}});
wire [15:0] digit1_rd = (digit1 & {8{reg_rd[DIGIT1]}}) << (8 & {4{DIGIT1[0]}});
wire [15:0] digit2_rd = (digit2 & {8{reg_rd[DIGIT2]}}) << (8 & {4{DIGIT2[0]}});
wire [15:0] digit3_rd = (digit3 & {8{reg_rd[DIGIT3]}}) << (8 & {4{DIGIT3[0]}});
wire [15:0] per_dout = digit0_rd |
digit1_rd |
digit2_rd |
digit3_rd;
//============================================================================
// 5) FOUR-DIGIT, SEVEN-SEGMENT LED DISPLAY DRIVER
//============================================================================
// Anode selection
//------------------
// Free running counter
reg [23:0] anode_cnt;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) anode_cnt <= 24'h00_0000;
else anode_cnt <= anode_cnt+24'h00_0001;
// Anode selection
wire [3:0] seg_an = (4'h1 << anode_cnt[17:16]);
wire seg_an0 = ~seg_an[0];
wire seg_an1 = ~seg_an[1];
wire seg_an2 = ~seg_an[2];
wire seg_an3 = ~seg_an[3];
// Segment selection
//----------------------------
wire [7:0] digit = seg_an[0] ? digit0 :
seg_an[1] ? digit1 :
seg_an[2] ? digit2 :
digit3;
wire seg_a = ~digit[7];
wire seg_b = ~digit[6];
wire seg_c = ~digit[5];
wire seg_d = ~digit[4];
wire seg_e = ~digit[3];
wire seg_f = ~digit[2];
wire seg_g = ~digit[1];
wire seg_dp = ~digit[0];
endmodule // driver_7segment
|
#include <bits/stdc++.h> using namespace std; vector<char> line; bool isPossible(int gLoc, int k); int main() { int n, k; cin >> n; cin >> k; char curr; int grasshopperLocation; for (int i = 0; i < n; i++) { cin >> curr; line.push_back(curr); if (curr == G ) grasshopperLocation = i; } if (isPossible(grasshopperLocation, k)) cout << YES ; else cout << NO ; return 0; } bool isPossible(int gLoc, int k) { for (int j = gLoc; j < line.size(); j += k) { if (line[j] == T ) return true; else if (line[j] == # ) break; } for (int j = gLoc; j >= 0; j -= k) { if (line[j] == T ) return true; else if (line[j] == # ) break; } return false; } |
#include <bits/stdc++.h> using namespace std; void solve() { string s; cin >> s; int n = s.length(); int r = 0; vector<int> fin(3, -1); fin[0] = 0; vector<int> z(n + 1); for (int i = 1; i <= n; i++) { r = (r + s[i - 1] - 0 ) % 3; z[i] = z[i - 1]; if (fin[r] != -1) z[i] = max(z[i], z[fin[r]] + 1); fin[r] = i; } cout << z[n] << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tst = 1; while (tst--) solve(); return 0; } |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) input clk,
output [3:0] led,
inout out_a,
output [1:0] out_b,
output signal_p,
output signal_n
);
wire LD6, LD7, LD8, LD9;
wire inter_wire, inter_wire_2;
localparam BITS = 1;
localparam LOG2DELAY = 25;
reg [BITS+LOG2DELAY-1:0] counter = 0;
always @(posedge clk) begin
counter <= counter + 1;
end
assign led[1] = inter_wire;
assign inter_wire = inter_wire_2;
assign {LD9, LD8, LD7, LD6} = counter >> LOG2DELAY;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *)
OBUFTDS OBUFTDS_2 (
.I (LD6),
.O (signal_p),
.OB(signal_n),
.T (1'b1)
);
(* async_reg = "false", mr_ff = "false", dont_touch = "true" *)
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_6 (
.I(LD6),
.O(led[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_7 (
.I(LD7),
.O(inter_wire_2)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_OUT (
.I(LD7),
.O(out_a)
);
bottom bottom_inst (
.I (LD8),
.O (led[2]),
.OB(out_b)
);
bottom_intermediate bottom_intermediate_inst (
.I(LD9),
.O(led[3])
);
endmodule
module bottom_intermediate (
input I,
output O
);
wire bottom_intermediate_wire;
assign O = bottom_intermediate_wire;
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_8 (
.I(I),
.O(bottom_intermediate_wire)
);
endmodule
module bottom (
input I,
output [1:0] OB,
output O
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_9 (
.I(I),
.O(O)
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_10 (
.I(I),
.O(OB[0])
);
OBUF #(
.IOSTANDARD("LVCMOS33"),
.SLEW("SLOW")
) OBUF_11 (
.I(I),
.O(OB[1])
);
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) using namespace std; const int dx[8] = {1, 1, 1, 0, 0, -1, -1, -1}; const int dy[8] = {1, -1, 0, 1, -1, -1, 1, 0}; template <class T> T gcd(T a, T b) { return ((b == 0) ? a : gcd(b, a % b)); } int n, m; vector<string> s; vector<string> g; vector<vector<int> > dist, dist1; bool valid(int i, int j) { return (min(i, j) >= 0 && i < n && j < m); } bool check(int t) { queue<pair<int, int> > q; for (int i = 0; i < (int)(n); i++) for (int j = 0; j < (int)(m); j++) { g[i][j] = . ; dist1[i][j] = 0; if (dist[i][j] > t) { g[i][j] = X ; dist1[i][j] = t + 1; q.push(make_pair(i, j)); } } while (!q.empty()) { pair<int, int> cur = q.front(); q.pop(); for (int i = 0; i < (int)(8); i++) { int x = cur.first + dx[i], y = cur.second + dy[i]; if (valid(x, y) && dist1[x][y] < (dist1[cur.first][cur.second] - 1)) { dist1[x][y] = dist1[cur.first][cur.second] - 1; q.push(make_pair(x, y)); } } } for (int i = 0; i < (int)(n); i++) for (int j = 0; j < (int)(m); j++) { if (s[i][j] == . ) { if (dist1[i][j] > 0) return 0; } else if (dist1[i][j] <= 0) return 0; } return 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> m; s.resize(n); for (int i = 0; i < (int)(n); i++) cin >> s[i]; string a = ; for (int j = 0; j < (int)(m); j++) a += . ; g.resize(n); for (int i = 0; i < (int)(n); i++) g[i] = a; dist.resize(n); dist1.resize(n); vector<int> b(m, 0); for (int i = 0; i < (int)(n); i++) dist[i] = dist1[i] = b; queue<pair<int, int> > q; for (int i = 0; i < (int)(n); i++) for (int j = 0; j < (int)(m); j++) { if (s[i][j] == . ) { dist[i][j] = 0; q.push(make_pair(i, j)); } else dist[i][j] = 1e9; } while (!q.empty()) { pair<int, int> cur = q.front(); q.pop(); for (int i = 0; i < (int)(8); i++) { int x = cur.first + dx[i], y = cur.second + dy[i]; if (valid(x, y) && dist[x][y] == 1e9) { dist[x][y] = dist[cur.first][cur.second] + 1; q.push(make_pair(x, y)); } } } for (int i = 0; i < (int)(n); i++) for (int j = 0; j < (int)(m); j++) { dist[i][j] = min({dist[i][j], i + 1, j + 1, (n - i), (m - j)}); } int l = 0, r = min(n, m) + 1; while (l < r) { int mid = (l + r + 1) / 2; if (check(mid)) l = mid; else r = mid - 1; } cout << l << endl; assert(check(l)); for (int i = 0; i < (int)(n); i++) cout << g[i] << n ; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Mauricio Carvajal Delgado
//
// Create Date: 03.17.2013 10:36:22
// Design Name:
// Module Name: Uart
// Project Name:
// Target Devices:
// Tool versions:
// Description: Interfaz UART
//
//////////////////////////////////////////////////////////////////////////////////
module Uart(
//INPUTS
input wire RST,CLK,RX,TX_START,
input wire [7:0] TX_DATA,
//OUTPUTS
output wire [7:0] RX_DATA,
output wire RX_DONE,TX,TX_DONE
);
//WIRES
wire Tclk; //salida del contador
//Contador
Coun_Baud ICONT(.clk(CLK), .reset(RST), .max_tick(Tclk));
//Receptor RX
ReceptorRX IRECEPTOR (.MCLK(CLK), .RST(RST), .tick_clk(Tclk), .RX(RX), .DATAOUT(RX_DATA), .RX_Done(RX_DONE));
//Transmisor TX
Transmisor_TX ITRANSMISOR(.RST(RST), .CLK(CLK), .TX_Start(TX_START), .DATAIN(TX_DATA), .s_tick(Tclk), .TX(TX), .TX_Done(TX_DONE));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int maxn = 100005; int a[maxn], b[maxn]; int main() { long long d, k, a, b, t; scanf( %I64d%I64d%I64d%I64d%I64d , &d, &k, &a, &b, &t); if (d < k) { printf( %I64d n , d * a); return 0; } d -= k; long long ans = k * a; long long k1 = k * a + t, k2 = k * b; if (k1 >= k2) { ans += d * b; } else { ans += d / k * k1; d %= k; ans += min(t + d * a, d * b); } printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; long long int gcd(long long int A, long long int B) { if (!B) return A; return gcd(B, A % B); } int main() { int n; string s; cin >> n >> s; vector<int> pbal(n + 2), sbal(n + 2); vector<bool> pref(n + 1, 1), suff(n + 1, 1); for (int i = 1; i <= n; i++) { if (s[i - 1] == ( ) pbal[i]++; else pbal[i]--; pbal[i] += pbal[i - 1]; if (pref[i - 1] && pbal[i] >= 0) pref[i] = 1; else pref[i] = 0; } for (int i = n; i > 0; i--) { if (s[i - 1] == ) ) sbal[i]--; else sbal[i]++; sbal[i] += sbal[i + 1]; if (suff[i + 1] && sbal[i] <= 0) suff[i] = 1; else suff[i] = 0; } int ans = 0; for (int i = 1; i <= n; i++) { if (!pref[i - 1] || !suff[i + 1]) continue; else { if (s[i - 1] == ( ) { if (pbal[i - 1] > 0 && pbal[i - 1] - 1 + sbal[i + 1] == 0) ans++; } else { if (sbal[i + 1] < 0 && pbal[i - 1] + 1 + sbal[i + 1] == 0) ans++; } } } cout << ans; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2018 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam string SVEC [0:7] = '{"zero", "one", "two", "three", "four", "five", "six", "seven"};
initial begin
$display("%s", SVEC[3'd1]);
$write("*-* All Finished *-*\n");
$finish;
end
localparam string REGX [0:31] = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
"a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"};
function string regx (logic [5-1:0] r, bit abi=1'b0);
regx = abi ? REGX[r] : $sformatf("x%0d", r);
endfunction: regx
function string dis32 (logic [32-1:0] op);
casez (op)
32'b0000_0000_0000_0000_0000_0000_0001_0011: dis32 = $sformatf("nop");
32'b0000_0000_0000_0000_0100_0000_0011_0011: dis32 = $sformatf("-");
32'b????_????_????_????_?000_????_?110_0111: dis32 = $sformatf("jalr %s, 0x%03x (%s)",
regx(op[5-1:0]), op[16-1:0], regx(op[5-1:0]));
default: dis32 = "illegal";
endcase
endfunction: dis32
always @(posedge clk) begin
for (int unsigned i=0; i<32; i++)
$display("REGX: %s", regx(i[4:0]));
$display("OP: %s", dis32(32'h00000000));
$finish();
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); void Fast() { std::ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } long long gcd(long long a, long long b) { return a ? gcd(b % a, a) : b; } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } long long fact(long long n) { long long f = 1; for (int i = 2; i <= n; i++) { f *= i; } return f; } long long ncr(long long n, long long r) { return fact(n) / (fact(r) * fact(n - r)); } long long npr(long long n, long long r) { return fact(n) / fact(n - r); } bool prime(long long n) { for (long long i = 2; i * i <= n; i++) { if (n % i == 0) { return 0; break; } } return 1; } char arr[55][55]; void solve() { int n, m; cin >> n >> m; int r1 = INT_MIN, r2 = INT_MAX, c1 = INT_MIN, c2 = INT_MAX; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> arr[i][j]; if (arr[i][j] == * ) { r1 = max(r1, i); r2 = min(r2, i); c1 = max(c1, j); c2 = min(c2, j); } } } for (int i = r2; i <= r1; i++) { for (int j = c2; j <= c1; j++) { cout << arr[i][j]; } cout << n ; } } int main() { Fast(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int test_case; cin >> test_case; while (test_case--) { int a, b, x, y; vector<int> akash; cin >> a >> b >> x >> y; int temp1 = 0, temp2 = 0, temp3 = 0, temp4 = 0; temp1 = ((b - y) - 1) * a; temp2 = ((a - x) - 1) * b; temp3 = (y - 0) * a; temp4 = (x - 0) * b; akash.push_back(temp1); akash.push_back(temp2); akash.push_back(temp3); akash.push_back(temp4); int max = akash[0]; for (int i = 1; i < 4; i++) { if (max < akash[i]) { max = akash[i]; } } cout << max << endl; akash.clear(); } return 0; } |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "niosii_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 13: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 12000,
the_altsyncram.numwords_a = 12000,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 14;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21AI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O21AI_PP_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int mod = 1e9 + 7, N = 2e5; int mul(int a, int b) { return (a * 1LL * b) % mod; } int mul2(int a, int b) { return (a * 1LL * b) % (mod - 1); } int Pow(int v, long long p) { int ans = 1; while (p) { if (p & 1) { ans = mul(ans, v); } p /= 2; v = mul(v, v); } return ans; } long long F(int n) { return n * 1LL * (n + 1) / 2; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; map<int, int> p; while (n--) { int x; cin >> x; ++p[x]; } int mult = 1, sum = 1, last = 1; for (auto e : p) { last = Pow(last, e.second + 1); mult = Pow(Pow(e.first, F(e.second)), sum); sum = mul2(sum, e.second + 1); last = mul(mult, last); } cout << last; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; long int mod = 1e9 + 7; long int i, j, n, t, m, k; vector<pair<long int, long int> > a, b; set<long int> c; bool cmp(const pair<long int, long int> &l, const pair<long int, long int> &r) { return l.first < r.first; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (long int i = 0; i < m; i++) { cin >> j; a.push_back(make_pair(j, i)); c.insert(j); } sort(a.begin(), a.end()); for (long int i = 0; i < a.size(); i++) { if ((i + 1) < a.size()) { long int rag = a[i].second, bha = a[i].second; j = i + 1; while (a[i].first == a[j].first) { rag = max(rag, a[j].second); bha = min(bha, a[j].second); j++; if (j >= a.size()) break; } i = j - 1; b.push_back(make_pair(a[i].first, bha)); b.push_back(make_pair(a[i].first, rag)); } else { b.push_back(make_pair(a[i].first, a[i].second)); b.push_back(make_pair(a[i].first, a[i].second)); } } for (long int i = 1; i < n + 1; i++) { long int l, rag = -1, bha = -1, rag1 = -1, bha1 = -1; l = lower_bound(b.begin(), b.end(), pair<long int, long int>(i, 0), cmp) - b.begin(); if (l >= b.size()) l--; if (b[l].first == i) { bha = b[l].second; rag = b[l + 1].second; } l = lower_bound(b.begin(), b.end(), pair<long int, long int>(i + 1, 0), cmp) - b.begin(); if (l >= b.size()) l--; if (b[l].first == i + 1) { bha1 = b[l].second; rag1 = b[l + 1].second; } if ((rag == -1 && bha == -1) && (rag1 == -1 && bha1 == -1)) continue; else if ((rag != -1 && bha != -1) && (rag1 != -1 && bha1 != -1)) { if (bha < rag1) t++; if (bha1 < rag) t++; } } t += c.size(); t = ((3 * n) - 2) - t; cout << t; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; ll modinv(ll a, ll m) { assert(m > 0); if (m == 1) return 0; a %= m; if (a < 0) a += m; assert(a != 0); if (a == 1) return 1; return m - modinv(m, a) * m / a; } template <int MOD_> struct modnum { private: int v; public: static const int MOD = MOD_; modnum() : v(0) {} modnum(ll v_) : v(int(v_ % MOD)) { if (v < 0) v += MOD; } explicit operator int() const { return v; } friend bool operator==(const modnum& a, const modnum& b) { return a.v == b.v; } friend bool operator!=(const modnum& a, const modnum& b) { return a.v != b.v; } modnum operator~() const { modnum res; res.v = modinv(v, MOD); return res; } modnum& operator+=(const modnum& o) { v += o.v; if (v >= MOD) v -= MOD; return *this; } modnum& operator-=(const modnum& o) { v -= o.v; if (v < 0) v += MOD; return *this; } modnum& operator*=(const modnum& o) { v = int(ll(v) * ll(o.v) % MOD); return *this; } modnum& operator/=(const modnum& o) { return *this *= (~o); } friend modnum operator+(const modnum& a, const modnum& b) { return modnum(a) += b; } friend modnum operator-(const modnum& a, const modnum& b) { return modnum(a) -= b; } friend modnum operator*(const modnum& a, const modnum& b) { return modnum(a) *= b; } friend modnum operator/(const modnum& a, const modnum& b) { return modnum(a) /= b; } }; using num = modnum<998244353>; template <typename T> T pow(T a, long long b) { assert(b >= 0); T r = 1; while (b) { if (b & 1) r *= a; b >>= 1; a *= a; } return r; } vector<num> fact; vector<num> ifact; void init() { int N = 1100000; fact = {1}; for (int i = 1; i < N; i++) fact.push_back(i * fact[i - 1]); ifact.resize(N); ifact.back() = 1 / fact.back(); for (int i = N - 1; i > 0; i--) ifact[i - 1] = i * ifact[i]; } num ncr(int n, int k) { if (k < 0 || k > n) return 0; return fact[n] * ifact[k] * ifact[n - k]; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); init(); int n, k; cin >> n >> k; vector<int> A(n); for (int i = 0; i < n; i++) cin >> A[i]; int same = 0; for (int i = 0; i < n; i++) if (A[i] == A[(i + 1) % n]) same++; int diff = n - same; num ans = 0; for (int a = 0; a * 2 <= diff; a++) { ans += ncr(diff, a) * ncr(diff - a, a) * pow(num(k - 2), diff - a - a); } ans = (pow(num(k), diff) - ans) / 2; ans = ans * pow(num(k), same); cout << (int)ans << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O21AI_BEHAVIORAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21AI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int count_inversions(vector<int> v) { int t = 0; for (int i = 0; i < (int)v.size(); ++i) for (int j = i + 1; j < (int)v.size(); ++j) if (v[i] > v[j]) t++; return t; } int main() { int n; scanf( %d , &n); vector<int> v(n); for (int i = 0; i < n; ++i) scanf( %d , &v[i]); int inversions = count_inversions(v); cout << (inversions / 2) * 4 + (inversions % 2) << endl; } |
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int inf = 1e9; const int NINF = 0xc0c0c0c0; const int maxn = 1e5 + 7; const int bas = maxn / 2; const int Maxn = 1e7 + 7; const double eps = 1e-6; const int mod = (1 << 31) - 1; template <typename T> void read(T &x) { x = 0; char c = getchar(); T flag = 1; while (c < 0 || c > 9 ) { if (c == - ) flag = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } x = x * flag; } struct edge { int v, next; } e[maxn << 1]; int head[maxn], cnt; void add(int a, int b) { e[++cnt] = edge{b, head[a]}; head[a] = cnt; } int f[maxn][21], dep[maxn], tot, dp[maxn], treez = 0, root; void dfs(int u, int fa) { dep[u] = dep[fa] + 1; f[u][0] = fa; for (int i = 1; i <= 20; i++) { f[u][i] = f[f[u][i - 1]][i - 1]; } for (int i = head[u]; i; i = e[i].next) { int v = e[i].v; if (v == fa) continue; dfs(v, u); treez = max(treez, dp[u] + dp[v] + 1); dp[u] = max(dp[u], dp[v] + 1); } } int getlca(int a, int b) { if (dep[a] < dep[b]) swap(a, b); for (int i = 20; ~i; i--) { int x = f[a][i]; if (dep[x] >= dep[b]) a = x; } if (a == b) return a; for (int i = 20; ~i; i--) { if (f[a][i] != f[b][i]) { a = f[a][i]; b = f[b][i]; } } return f[a][0]; } int k; int work(int a, int lca) { for (int i = 20; ~i; i--) { if ((1 << i) <= k && dep[f[a][i]] >= dep[lca]) { a = f[a][i]; k -= (1 << i); } } return a; } void solve() { int n, a, b, da, db; cin >> n >> a >> b >> da >> db; for (int i = 1; i <= n; i++) head[i] = 0, dp[i] = 0, dep[i] = 0; cnt = 0; treez = 0; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; add(u, v); add(v, u); } if (da * 2 >= db) { puts( Alice ); return; } dfs(1, 0); int lca = getlca(a, b); if (treez <= da * 2) { puts( Alice ); return; } if (dep[a] + dep[b] - dep[lca] * 2 <= da) { puts( Alice ); return; } puts( Bob ); } signed main() { int T = 1; scanf( %d , &T); while (T--) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a, b; cin >> n >> m >> a >> b; int x = m - n, r = 0, t = 14; if (b >= a && a * 8 < x) { cout << -1; return 0; } while (x > 0) { if (10 <= t && t < 22) x -= a; else x += b; t++; if (t == 24) r++, t = 0; } cout << r; } |
#include <bits/stdc++.h> using namespace std; string s; int x[100009], y[100009], z[100009], m, l, r; int main() { cin >> s; cin >> m; for (int i = 1; i <= s.size(); i++) { x[i] = x[i - 1]; y[i] = y[i - 1]; z[i] = z[i - 1]; if (s[i - 1] == x ) x[i]++; if (s[i - 1] == y ) y[i]++; if (s[i - 1] == z ) z[i]++; } for (int i = 1; i <= m; i++) { cin >> l >> r; if (min(x[r] - x[l - 1], min(y[r] - y[l - 1], z[r] - z[l - 1])) + 1 >= max(x[r] - x[l - 1], max(y[r] - y[l - 1], z[r] - z[l - 1]))) { cout << YES n ; continue; } if (r - l + 1 <= 2) { cout << YES n ; continue; } cout << NO n ; } } |
`timescale 1ns/100ps
module assign_test;
reg clk;
reg cat1;
reg cat2;
reg cat3;
reg cat4;
reg foo1;
reg foo2;
reg foo3;
reg foo4;
reg bar1;
reg bar2;
reg bar3;
reg bar4;
initial begin
clk = 0;
#100 $finish(0);
end
always begin
clk = 0;
#50;
clk = 1;
#50;
end
always @(posedge clk) begin
cat1 = #1 1;
cat2 = #1 1;
cat3 = #1 1;
cat4 = #1 1;
foo1 = #1 1;
foo2 = #1 1;
foo3 = #1 1;
foo4 = #1 1;
bar1 <= #1 1;
bar2 <= #1 1;
bar3 <= #1 1;
bar4 <= #1 1;
end
always @(cat1)
$write("time=%0t, cat1=%0h\n", $time, cat1);
always @(cat2) $write("time=%04d, cat2=%0h\n", $time, cat2);
always @(cat3) $write("time=%04d, cat3=%0h\n", $time, cat3);
always @(cat4) $write("time=%04d, cat4=%0h\n", $time, cat4);
always @(foo1) $write("time=%04d, foo1=%0h\n", $time, foo1);
always @(foo2) $write("time=%04d, foo2=%0h\n", $time, foo2);
always @(foo3) $write("time=%04d, foo3=%0h\n", $time, foo3);
always @(foo4) $write("time=%04d, foo4=%0h\n", $time, foo4);
always @(bar1) $write("time=%04d, bar1=%0h\n", $time, bar1);
always @(bar2) $write("time=%04d, bar2=%0h\n", $time, bar2);
always @(bar3) $write("time=%04d, bar3=%0h\n", $time, bar3);
always @(bar4) $write("time=%04d, bar4=%0h\n", $time, bar4);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: ram_1clk_1w_1r.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: An inferrable RAM module. Single clock, 1 write port, 1
// read port. In Xilinx designs, specify RAM_STYLE="BLOCK"
// to use BRAM memory or RAM_STYLE="DISTRIBUTED" to use
// LUT memory.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module ram_1clk_1w_1r
#(
parameter C_RAM_WIDTH = 32,
parameter C_RAM_DEPTH = 1024
)
(
input CLK,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRA,
input WEA,
input [clog2s(C_RAM_DEPTH)-1:0] ADDRB,
input [C_RAM_WIDTH-1:0] DINA,
output [C_RAM_WIDTH-1:0] DOUTB
);
localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH);
reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0];
reg [C_RAM_WIDTH-1:0] rDout;
assign DOUTB = rDout;
always @(posedge CLK) begin
if (WEA)
rRAM[ADDRA] <= #1 DINA;
rDout <= #1 rRAM[ADDRB];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200005; int N, M, K; int A[MAXN]; int B[MAXN]; set<int> adj[MAXN]; int deg[MAXN]; set<pair<int, int> > st; bool inGraph[MAXN]; int ans[MAXN]; void update(int x) { if (!inGraph[x]) return; set<pair<int, int> >::iterator it = st.find(make_pair(deg[x], x)); st.erase(it); deg[x]--; st.insert(make_pair(deg[x], x)); } void fix() { while (!st.empty() && st.begin()->first < K) { int cur = st.begin()->second; st.erase(st.begin()); inGraph[cur] = false; for (auto nxt : adj[cur]) { adj[nxt].erase(cur); update(nxt); } adj[cur].clear(); } } int main() { scanf( %d %d %d , &N, &M, &K); for (int i = 0; i < M; i++) { scanf( %d %d , &A[i], &B[i]); deg[A[i]]++; deg[B[i]]++; adj[A[i]].insert(B[i]); adj[B[i]].insert(A[i]); } for (int i = 1; i <= N; i++) { st.insert(make_pair(deg[i], i)); inGraph[i] = true; } for (int i = M - 1; i >= 0; i--) { fix(); ans[i] = st.size(); adj[A[i]].erase(B[i]); adj[B[i]].erase(A[i]); if (inGraph[B[i]]) update(A[i]); if (inGraph[A[i]]) update(B[i]); } for (int i = 0; i < M; i++) printf( %d n , ans[i]); return 0; } |
//
// Prof. Taylor 7/24/2014
// <>
//
// Updated by Paul Gao 02/2019
//
//
// this implements:
// - outgoing source-synchronous launch flops
// - outgoing token channel to go from core domain deque to out of chip
// - outgoing source-synchronous launch flops for token
// - center-aligned DDR source sync output clock
//
// General reset procedures:
//
// Step 1: Assert io_link_reset_i and core_link_reset_i.
// Step 2: async_token_reset_i must be posedge/negedge toggled (0->1->0)
// at least once. token_clk_i cannot toggle during this step.
// Step 3: io_clk_i posedge toggled at least four times after that.
// Step 4: Deassert io_link_reset_i.
// Step 5: Deassert core_link_reset_i.
//
// *************************************************************************
// async_token_reset_i io_link_reset_i core_link_reset_i
// Step 1 0 1 1
// Step 2 1 1 1
// Step 3 0 1 1
// Step 4 0 0 1
// Step 5 0 0 0
// *************************************************************************
//
//
`include "bsg_defines.v"
module bsg_link_source_sync_upstream
#( parameter channel_width_p = 16
, parameter lg_fifo_depth_p = 6
, parameter lg_credit_to_token_decimation_p = 3
, parameter bypass_twofer_fifo_p = 0
// we explicit set the "inactive pattern"
// on data lines when valid bit is not set
// to (10)+ = 0xA*
//
// the inactive pattern should balance the current
// across I/O V33 and VZZ pads, reducing
// electromigration for the common case of not
// sending.
//
// for example, in TSMC 250, the EM limit is 41 mA
// and the ratio of signal to I/O V33 and VZZ is
// 4:1:1.
//
// fixme: an alternative might be to tri-state
// the output, but further analysis is required
// as to whether this is a good idea.
// this default is only safe because we assume that only data bits are
// being specified in the channel and no control bits, and that these data bits
// are otherwise ignored by the receiver control logic if the output of this module
// is indicated as invalid.
, parameter inactive_pattern_p = {channel_width_p { 2'b10 } }
)
(// control signals
input core_clk_i
, input core_link_reset_i
, input io_clk_i
, input io_link_reset_i
, input async_token_reset_i
// Input from chip core
, input [channel_width_p-1:0] core_data_i
, input core_valid_i
, output core_ready_o
// output channel to ODDR_PHY
, output logic [channel_width_p-1:0] io_data_o // output data
, output logic io_valid_o // output valid
, input io_ready_i // output PHY is ready
, input token_clk_i // input token clock
);
logic core_fifo_valid, core_fifo_yumi;
logic [channel_width_p-1:0] core_fifo_data;
logic core_async_fifo_full;
assign core_fifo_yumi = core_fifo_valid & ~core_async_fifo_full;
// MBT: we insert a two-element fifo here to
// decouple the async fifo logic which can be on the critical
// path in some cases. possibly this is being overly conservative
// and may introduce too much latency. but certainly in the
// case of the bsg_comm_link code, it is necessary.
// fixme: possibly make it a parameter as to whether we instantiate
// this fifo
if (bypass_twofer_fifo_p == 0)
begin: twofer
bsg_two_fifo
#(.width_p(channel_width_p)
) fifo
(.clk_i (core_clk_i)
,.reset_i(core_link_reset_i)
,.ready_o(core_ready_o)
,.data_i (core_data_i)
,.v_i (core_valid_i)
,.v_o (core_fifo_valid)
,.data_o (core_fifo_data)
,.yumi_i (core_fifo_yumi)
);
end
else
begin: no_twofer
// keep async_fifo isolated when reset is asserted
assign core_fifo_valid = core_valid_i;
assign core_fifo_data = core_data_i;
assign core_ready_o = (core_link_reset_i)? 1'b1 : ~core_async_fifo_full;
end
logic io_async_fifo_valid, io_async_fifo_yumi;
logic [channel_width_p-1:0] io_async_fifo_data;
// ******************************************
// clock-crossing async fifo
// this is just an output fifo and does not
// need to cover the round trip latency
// of the channel; just the clock domain crossing
//
// Assuming (A and B are registers with the corresponding clocks)
// this is the structure of the roundtrip path:
//
// /-- B <-- B <-- A <--\
// | |
// \--> B --> A --> A ---/
//
// Suppose we have cycleTimeA and cycleTimeB, with cycleTimeA > cycleTimeB
// the bandwidth*delay product of the roundtrip is:
//
// 3 * (cycleTimeA + cycleTimeB) * min(1/cycleTimeA, 1/cycleTimeB)
// = 3 + 3 * cycleTimeB / cycleTimeA
//
// w.c. is cycleTimeB == cycleTimeA
//
// --> 6 elements
//
// however, for the path from A to B and B to A
// we need to clear not only the cycle time of A/B
// but the two setup times, which are guaranteed to
// be less than a cycle each. So we get 8 elements total.
//
// TODO: if we use 3-cycle synchronizers, then the async fifo would have to be larger.
bsg_async_fifo
#(.lg_size_p(3)
,.width_p(channel_width_p)
) async_fifo
(.w_clk_i (core_clk_i)
,.w_reset_i(core_link_reset_i)
,.w_enq_i (core_fifo_yumi)
,.w_data_i (core_fifo_data)
,.w_full_o (core_async_fifo_full)
,.r_clk_i (io_clk_i)
,.r_reset_i(io_link_reset_i)
,.r_deq_i (io_async_fifo_yumi)
,.r_data_o (io_async_fifo_data)
,.r_valid_o(io_async_fifo_valid)
);
// ******************************************
// Output valid and data signals
// when fifo has valid data and token credit is available
logic io_valid_n;
always_comb
begin
// By default, data output is inactive pattern
io_data_o = inactive_pattern_p[0+:channel_width_p];
if (io_link_reset_i)
begin
io_valid_o = 1'b0;
end
else
begin
// subtle: we assert the real data rather than the inactive_pattern when we have
// valid data and enough credit, even if the serdes is not ready to send, since
// the data is ignored and it will reduce spurious switching.
io_valid_o = io_valid_n;
if (io_valid_n)
io_data_o = io_async_fifo_data;
end
end
// we need to track whether the credits are coming from
// posedge or negedge tokens.
// high bit indicates which counter we are grabbing from
logic [lg_credit_to_token_decimation_p+1-1:0] io_token_alternator_r;
// Increase token alternator when dequeue from async fifo
bsg_counter_clear_up
#(.max_val_p({(lg_credit_to_token_decimation_p+1){1'b1}})
,.init_val_p(0) // this will start us on the posedge token
,.disable_overflow_warning_p(1) // Allow overflow for this counter
)
token_alt
(.clk_i (io_clk_i)
,.reset_i(io_link_reset_i)
,.clear_i(1'b0)
,.up_i (io_async_fifo_yumi)
,.count_o(io_token_alternator_r)
);
// high bit set means we have exceeded number of posedge credits
// and are doing negedge credits
wire io_on_negedge_token = io_token_alternator_r[lg_credit_to_token_decimation_p];
logic io_negedge_credits_avail, io_posedge_credits_avail;
wire io_credit_avail = io_on_negedge_token
? io_negedge_credits_avail
: io_posedge_credits_avail;
// we send if we have both data to send and credits to send with
assign io_valid_n = io_credit_avail & io_async_fifo_valid;
// dequeue from fifo when io_ready
assign io_async_fifo_yumi = io_valid_n & io_ready_i;
wire io_negedge_credits_deque = io_async_fifo_yumi & io_on_negedge_token;
wire io_posedge_credits_deque = io_async_fifo_yumi & ~io_on_negedge_token;
// **********************************************
// token channel
//
// these are tokens coming from off chip that need to
// cross into the io clock domain.
//
// note that we are a little unconventional here; we use the token
// itself as a clock. this because we don't know the phase of the
// token signal coming in.
//
// we count both edges of the token separately, and assume that they
// will alternate in lock-step. we use two separate counters to do this.
//
// an alternative would be to use
// dual-edged flops, but they are not available in most ASIC libraries
// and although you can synthesize these out of XOR'd flops, they
// violate the async maxim that all signals crossing clock boundaries
// must come from a launch flop.
bsg_async_credit_counter
#(// half the credits will be positive edge tokens
.max_tokens_p(2**(lg_fifo_depth_p-1-lg_credit_to_token_decimation_p))
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.count_negedge_p(1'b0)
// we enable extra margin in case downstream module wants more tokens
,.extra_margin_p(2)
,.start_full_p(1)
,.use_async_w_reset_p(1'b1)
) pos_credit_ctr
(
.w_clk_i (token_clk_i)
,.w_inc_token_i(1'b1)
,.w_reset_i(async_token_reset_i)
// the I/O clock domain is responsible for tabulating tokens
,.r_clk_i (io_clk_i )
,.r_reset_i (io_link_reset_i )
,.r_dec_credit_i (io_posedge_credits_deque)
,.r_infinite_credits_i(1'b0 )
,.r_credits_avail_o (io_posedge_credits_avail)
);
bsg_async_credit_counter
#(// half the credits will be negative edge tokens
.max_tokens_p(2**(lg_fifo_depth_p-1-lg_credit_to_token_decimation_p))
,.lg_credit_to_token_decimation_p(lg_credit_to_token_decimation_p)
,.count_negedge_p(1'b1)
// we enable extra margin in case downstream module wants more tokens
,.extra_margin_p(2)
,.start_full_p(1)
,.use_async_w_reset_p(1'b1)
) neg_credit_ctr
(
.w_clk_i (token_clk_i)
,.w_inc_token_i(1'b1)
,.w_reset_i(async_token_reset_i)
// the I/O clock domain is responsible for tabulating tokens
,.r_clk_i (io_clk_i )
,.r_reset_i (io_link_reset_i )
,.r_dec_credit_i (io_negedge_credits_deque)
,.r_infinite_credits_i(1'b0 )
,.r_credits_avail_o (io_negedge_credits_avail)
);
endmodule |
#include <bits/stdc++.h> unsigned long long tmp[131073], invn; int a_[131072]; inline int ksm(unsigned long long a, int b) { int ans = 1; while (b) (b & 1) && (ans = a * ans % 998244353), a = a * a % 998244353, b >>= 1; return ans; } void init(int n) { for (int i = 1; i < n; i++) a_[i] = i & 1 ? a_[i ^ 1] | n >> 1 : a_[i >> 1] >> 1; for (int i = tmp[0] = 1, j = ksm(3, (998244353 - 1) / n); i <= n; i++) tmp[i] = tmp[i - 1] * j % 998244353; invn = ksm(n, 998244353 - 2); } void ntt(int a[], int n, bool typ) { int p; for (int i = 1; i < n; i++) if (a_[i] < i) p = a[i], a[i] = a[a_[i]], a[a_[i]] = p; if (typ) for (int i = 1, d = n >> 1; d; i <<= 1, d >>= 1) for (int j = 0; j < n; j += i << 1) for (int k = 0; k < i; k++) p = tmp[n - d * k] * a[i + j + k] % 998244353, (a[i + j + k] = a[j + k] + 998244353 - p) >= 998244353 && (a[i + j + k] -= 998244353), (a[j + k] += p) >= 998244353 && (a[j + k] -= 998244353); else for (int i = 1, d = n >> 1; d; i <<= 1, d >>= 1) for (int j = 0; j < n; j += i << 1) for (int k = 0; k < i; k++) p = tmp[d * k] * a[i + j + k] % 998244353, (a[i + j + k] = a[j + k] + 998244353 - p) >= 998244353 && (a[i + j + k] -= 998244353), (a[j + k] += p) >= 998244353 && (a[j + k] -= 998244353); if (typ) for (int i = 0; i < n; i++) a[i] = invn * a[i] % 998244353; } void getinv(int n, int a[], int b[]) { static int tmp[131072]; memset(b, 0, sizeof(int) * (n << 1)); b[0] = ksm(a[0], 998244353 - 2); for (int i = 1; i < n; i <<= 1) { init(i << 2); memset(tmp, 0, sizeof(int) * (i << 2)); memcpy(tmp, a, sizeof(int) * (i << 1)); ntt(tmp, i << 2, 0); ntt(b, i << 2, 0); for (int j = 0; j < i << 2; j++) b[j] = (1ull * (998244353 - tmp[j]) * b[j] % 998244353 + 2) * b[j] % 998244353; ntt(b, i << 2, 1); memset(b + (i << 1), 0, sizeof(int) * (i << 1)); } } int n, m, a[131072], b[131072], d0[131072], d1[131072], len, ans; void work(int v) { if (v == 1) { for (int i = 0; i < len; i++) a[i] = 1; ans = 1; return; } work(v >> 1); memset(d0, 0, sizeof(int) * (len << 1)); memset(d1, 0, sizeof(int) * (len << 1)); for (int i = 0; i < len; i++) (i & 1 ? d1 : d0)[i] = a[i]; if (v & 1) ++d1[1] == 998244353 && (d1[1] = 0); memset(a, 0, sizeof(int) * (len << 1)); for (int i = 0; i < len; i++) a[i] = d1[i] ? 998244353 - d1[i] : 0; ++a[0] == 998244353 && (a[0] = 0); getinv(len, a, b); if (v == m || !(n & 1)) { int Ans = 0; for (int i = 1; i <= n; i += 2) Ans = (1ull * d1[i] * b[n - i] % 998244353 * i + Ans) % 998244353; if (!(n & 1)) ans = (2ull * ans + Ans) % 998244353; else ans = Ans; if (v == m) return; } init(len << 1); ntt(d0, len << 1, 0); for (int i = 0; i < len << 1; i++) d0[i] = 1ull * d0[i] * d0[i] % 998244353; ntt(d0, len << 1, 1); memset(d0 + len, 0, sizeof(int) * len); ntt(d0, len << 1, 0); ntt(b, len << 1, 0); for (int i = 0; i < len << 1; i++) a[i] = 1ull * d0[i] * b[i] % 998244353; ntt(a, len << 1, 1); for (int i = 1; i < len; i += 2) (a[i] += d1[i]) >= 998244353 && (a[i] -= 998244353); if (v & 1) a[1] ? a[1]-- : a[1] = 998244353 - 1; } int main() { scanf( %d%d , &n, &m); len = n << 1; while (len ^ len & -len) len ^= len & -len; work(m); printf( %d n , ans); } |
#include <bits/stdc++.h> using namespace std; int a[1 << 18]; long long sum[1 << 18]; int p[1 << 18]; int n, T, m; double c; void Calc() { double mean = 0.0; for (int i = 0, j = 0; i < n && j < m; i++) { mean = (mean + (a[i] + .0) / T) / c; if (i == p[j] - 1) { double real = (.0 + sum[i + 1] - sum[i - T + 1]) / T; printf( %.9lf , real); printf( %.9lf , mean); printf( %.9lf n , fabs(real - mean) / real); j++; } } } int main() { scanf( %d%d%lf , &n, &T, &c); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); sum[i + 1] = sum[i] + a[i]; } scanf( %d , &m); for (int i = 0; i < m; i++) scanf( %d , &p[i]); Calc(); return 0; } |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module my_dff (
input d,
clk,
output reg q
);
always @(posedge clk) q <= d;
endmodule
module my_dffe (
input d,
clk,
en,
output reg q
);
initial begin
q = 0;
end
always @(posedge clk) if (en) q <= d;
endmodule
module my_dffr_p (
input d,
clk,
clr,
output reg q
);
always @(posedge clk or posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffr_p_2 (
input d1,
input d2,
clk,
clr,
output reg q1,
output reg q2
);
always @(posedge clk or posedge clr)
if (clr) begin
q1 <= 1'b0;
q2 <= 1'b0;
end else begin
q1 <= d1;
q2 <= d2;
end
endmodule
module my_dffr_n (
input d,
clk,
clr,
output reg q
);
always @(posedge clk or negedge clr)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffre_p (
input d,
clk,
clr,
en,
output reg q
);
always @(posedge clk or posedge clr)
if (clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffre_n (
input d,
clk,
clr,
en,
output reg q
);
always @(posedge clk or negedge clr)
if (!clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffs_p (
input d,
clk,
pre,
output reg q
);
always @(posedge clk or posedge pre)
if (pre) q <= 1'b1;
else q <= d;
endmodule
module my_dffs_n (
input d,
clk,
pre,
output reg q
);
always @(posedge clk or negedge pre)
if (!pre) q <= 1'b1;
else q <= d;
endmodule
module my_dffse_p (
input d,
clk,
pre,
en,
output reg q
);
always @(posedge clk or posedge pre)
if (pre) q <= 1'b1;
else if (en) q <= d;
endmodule
module my_dffse_n (
input d,
clk,
pre,
en,
output reg q
);
always @(posedge clk or negedge pre)
if (!pre) q <= 1'b1;
else if (en) q <= d;
endmodule
module my_dffn (
input d,
clk,
output reg q
);
initial q <= 1'b0;
always @(negedge clk) q <= d;
endmodule
module my_dffnr_p (
input d,
clk,
clr,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or posedge clr)
if (clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffnr_n (
input d,
clk,
clr,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or negedge clr)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffns_p (
input d,
clk,
pre,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or posedge pre)
if (pre) q <= 1'b1;
else q <= d;
endmodule
module my_dffns_n (
input d,
clk,
pre,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or negedge pre)
if (!pre) q <= 1'b1;
else q <= d;
endmodule
module my_dffsr_ppp (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or posedge pre or posedge clr)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_pnp (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or negedge pre or posedge clr)
if (!pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_ppn (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or posedge pre or negedge clr)
if (pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_pnn (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or negedge pre or negedge clr)
if (!pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_npp (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or posedge pre or posedge clr)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_nnp (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or negedge pre or posedge clr)
if (!pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_npn (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or posedge pre or negedge clr)
if (pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsr_nnn (
input d,
clk,
pre,
clr,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or negedge pre or negedge clr)
if (!pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else q <= d;
endmodule
module my_dffsre_ppp (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or posedge pre or posedge clr)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_pnp (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or negedge pre or posedge clr)
if (!pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_ppn (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or posedge pre or negedge clr)
if (pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_pnn (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(posedge clk or negedge pre or negedge clr)
if (!pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_npp (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or posedge pre or posedge clr)
if (pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_nnp (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or negedge pre or posedge clr)
if (!pre) q <= 1'b1;
else if (clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_npn (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or posedge pre or negedge clr)
if (pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffsre_nnn (
input d,
clk,
pre,
clr,
en,
output reg q
);
initial q <= 1'b0;
always @(negedge clk or negedge pre or negedge clr)
if (!pre) q <= 1'b1;
else if (!clr) q <= 1'b0;
else if (en) q <= d;
endmodule
module my_dffs_clk_p (
input d,
clk,
pre,
output reg q
);
initial q <= 0;
always @(posedge clk)
if (pre) q <= 1'b1;
else q <= d;
endmodule
module my_dffs_clk_n (
input d,
clk,
clr,
output reg q
);
initial q <= 0;
always @(negedge clk)
if (!clr) q <= 1'b0;
else q <= d;
endmodule
|
#include <bits/stdc++.h> long long int a, b; int main() { scanf( %lld %lld , &a, &b); if (a % 2 == 0) { if (2 * b - 1 < a) { printf( %lld , 2 * b - 1); } else { printf( %lld , (b - a / 2) * 2); } } else { if (2 * b - 1 <= a) { printf( %lld , 2 * b - 1); } else { printf( %lld , ((b - a / 2) - 1) * 2); } } return 0; } |
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