text stringlengths 59 71.4k |
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#include <bits/stdc++.h> using namespace std; template <class T, class U> inline void chmin(T &t, U f) { if (t > f) t = f; } template <class T, class U> inline void chmax(T &t, U f) { if (t < f) t = f; } long long N; char S[11111]; long long ex[27 * 26 * 26]; long long dp[11111][2]; long long get(long long l, long long r) { if (r > N) return -1; long long x = 0; for (long long i = l; i < r; i++) { x = x * 26 + (S[i] - a ); } if (r - l == 2) x += 26 * 26 * 26; return x; } signed main() { scanf( %s , S); N = strlen(S); if (N <= 6) { puts( 0 ); return 0; } if (N == 7) { puts( 1 ); printf( %s , S + 5); return 0; } ex[get(N - 2, N)] = true; ex[get(N - 3, N)] = true; dp[N - 2][0] = true; dp[N - 3][1] = true; for (long long i = N - 4; i >= 5; i--) { long long t2 = get(i, i + 2); long long t3 = get(i, i + 3); if (t2 == get(i + 2, i + 4)) dp[i][0] = dp[i + 2][1]; else dp[i][0] = dp[i + 2][0] | dp[i + 2][1]; if (t3 == get(i + 3, i + 6)) dp[i][1] = dp[i + 3][0]; else dp[i][1] = dp[i + 3][0] | dp[i + 3][1]; if (dp[i][0]) ex[t2] = true; if (dp[i][1]) ex[t3] = true; } vector<string> vec; for (long long i = 0; i < (26); i++) for (long long j = 0; j < (26); j++) if (ex[26 * 26 * 26 + i * 26 + j]) vec.push_back(string(1, a + i) + string(1, a + j)); for (long long i = 0; i < (26); i++) for (long long j = 0; j < (26); j++) for (long long k = 0; k < (26); k++) if (ex[i * 26 * 26 + j * 26 + k]) vec.push_back(string(1, a + i) + string(1, a + j) + string(1, a + k)); sort((vec).begin(), (vec).end()); printf( %lld n , (long long)vec.size()); for (long long i = 0; i < (vec.size()); i++) printf( %s n , vec[i].c_str()); return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:44:51 04/21/2016
// Design Name: clock
// Module Name: W:/CPE/digital/project/cuckooExten/t_clock.v
// Project Name: cuckooExten
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: clock
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module t_clock;
// Inputs
reg hourClkRate;
reg minClkRate;
reg clk10hz;
reg setM;
reg setH;
reg setButton;
// Outputs
wire [3:0] hourMu;
wire [3:0] hourTens;
wire [3:0] minMu;
wire [3:0] minTens;
wire colon;
// Instantiate the Unit Under Test (UUT)
clock uut (
.hourMu(hourMu),
.hourTens(hourTens),
.minMu(minMu),
.minTens(minTens),
.colon(colon),
.hourClkRate(hourClkRate),
.minClkRate(minClkRate),
.clk10hz(clk10hz),
.setM(setM),
.setH(setH),
.setButton(setButton)
);
initial begin
// Initialize Inputs
hourClkRate = 0;
minClkRate = 0;
clk10hz = 0;
setM = 1;
setH = 1;
setButton = 1;
// Wait 100 ns for global reset to finish
forever #10 clk10hz=~clk10hz;
// Add stimulus here
end
initial #100000 $finish;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; string s; cin >> s; vector<int> stars, pacmans; for (int i = 0; i < n; i++) { if (s[i] == * ) stars.push_back(i); else if (s[i] == P ) pacmans.push_back(i); } stars.push_back(1e9); int l = 1, r = 2 * n, ok = 1; while (l <= r) { int mid = (l + r) / 2; int start = stars[0]; int curr = 0; bool f = true; for (int x : pacmans) { if (start < x - mid) f = false; else if (start < x) { curr = max(x + mid - (x - start) * 2, x + (mid - x + start) / 2); } else { curr = x + mid; } start = *upper_bound(stars.begin(), stars.end(), curr); } if (!f or start != 1e9) { l = mid + 1; } else { ok = mid; r = mid - 1; } } cout << ok << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, s; int even_odd[100005][2]; int visited[100005]; vector<int> ans; vector<int> v[100005]; int dfs(int s, int p) { if (v[s].empty() && p) { ans.push_back(s); return 1; } for (auto it : v[s]) { if (even_odd[it][p ^ 1] == 0) { even_odd[it][p ^ 1] = s; if (dfs(it, p ^ 1) == 1) { ans.push_back(s); return 1; } } } return 0; } bool dfs2(int source) { visited[source] = 1; for (auto it : v[source]) if (visited[it] == 1 || (visited[it] == 0 && dfs2(it))) return true; visited[source] = 2; return false; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) { int k; cin >> k; for (int j = 0; j < k; j++) { int a; cin >> a; v[i + 1].push_back(a); } } cin >> s; if (dfs(s, 0)) { cout << Win n ; for (int i = ans.size() - 1; i >= 0; i--) cout << ans[i] << ; return 0; } if (dfs2(s)) { cout << Draw n ; return 0; } cout << Lose n ; return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int d, f, t; long long c; } a[100005]; int cmp(node a, node b) { return a.d < b.d; } long long INF = 0x3f3f3f3f3f3f; long long cost[100005]; int vis[100005]; int cnt1[1000006]; int cnt2[1000006]; long long sum2[1000006]; long long sum1[1000006]; int main() { int n, m, k; memset(cnt1, 0, sizeof(cnt1)); memset(cnt2, 0, sizeof(cnt2)); memset(vis, 0, sizeof(vis)); memset(cost, INF, sizeof(cost)); memset(sum1, 0, sizeof(sum1)); memset(sum2, 0, sizeof(sum2)); scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= m; i++) { scanf( %d%d%d%I64d , &a[i].d, &a[i].f, &a[i].t, &a[i].c); } sort(a + 1, a + 1 + m, cmp); int pre = 0; for (int i = 1; i <= m; i++) { if (a[i].f == 0) continue; int f = a[i].f; int d = a[i].d; sum1[d] = sum1[pre]; cnt1[d] = cnt1[pre]; if (cost[f] > a[i].c) { if (vis[f] == 1) sum1[d] = sum1[d] - cost[f] + a[i].c; else sum1[d] += a[i].c; cost[f] = a[i].c; if (vis[f] == 0) { cnt1[d]++; vis[f] = 1; } } pre = d; } for (int i = 1; i <= 1000000; i++) { if (cnt1[i] == 0) cnt1[i] = cnt1[i - 1]; if (sum1[i] == 0) sum1[i] = sum1[i - 1]; } memset(vis, 0, sizeof(vis)); pre = 1000000; memset(cost, INF, sizeof(cost)); for (int i = m; i >= 1; i--) { if (a[i].t == 0) continue; int d = a[i].d; int t = a[i].t; sum2[d] = sum2[pre]; cnt2[d] = cnt2[pre]; if (cost[t] > a[i].c) { if (vis[t] == 1) sum2[d] = sum2[d] - cost[t] + a[i].c; else sum2[d] += a[i].c; cost[t] = a[i].c; if (vis[t] == 0) { cnt2[d]++; vis[t] = 1; } } pre = d; } for (int i = 1000000; i >= 0; i--) { if (cnt2[i] == 0) cnt2[i] = cnt2[i + 1]; if (sum2[i] == 0) sum2[i] = sum2[i + 1]; } long long ans = INF; for (int i = 1; i <= 1000000; i++) { if (i + k + 1 > 1000000) break; if (cnt1[i] == n && cnt2[i + k + 1] == n) ans = min(ans, (long long)sum1[i] + sum2[i + k + 1]); } if (ans == INF) { printf( -1 n ); return 0; } printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; vector<int> ans; int row[5], col[20]; vector<int> v[3]; bool vis[20][11][11][11][11][11][1 << 5]; bool solve(int x, int r1, int r2, int r3, int r4, int r5, int mask) { if (x == m) { if (r1 + r2 + r3 + r4 + r5) return false; return true; } bool &ret = vis[x][r1][r2][r3][r4][r5][mask]; if (ret) return false; ret = true; int a[5]; a[0] = r1, a[1] = r2, a[2] = r3, a[3] = r4, a[4] = r5; int h = col[x]; for (int i = 0; i < v[h].size(); i++) { int b[5] = {0}; int now = v[h][i]; for (int j = 0; j < n; j++) b[j] = a[j]; bool flag = true; for (int j = 0; j < n; j++) { if ((mask & (1 << j)) == 0 && now & (1 << j)) b[j]--; if (b[j] < 0) { flag = false; break; } } if (flag) { if (solve(x + 1, b[0], b[1], b[2], b[3], b[4], now)) { ans.push_back(now); return true; } } } return false; } int main() { scanf( %d , &n); ; scanf( %d , &m); ; for (int i = 0; i < n; i++) scanf( %d , &row[i]); ; for (int i = 0; i < m; i++) scanf( %d , &col[i]); ; for (int i = 0; i < 1 << n; i++) { int c = 0, pre = 0; for (int j = 0; j < n; j++) { if (i & (1 << j) && !pre) { pre = 1; c++; } else pre = bool(i & (1 << j)); } v[c].push_back(i); } solve(0, row[0], row[1], row[2], row[3], row[4], 0); reverse(ans.begin(), ans.end()); for (int i = 0; i < n; i++) { for (int j = 0; j < ans.size(); j++) { if (ans[j] & (1 << i)) cout << * ; else cout << . ; } cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; char a[100005]; int main() { int n; scanf( %d , &n); scanf( %s , &a); int x = 0, f = 0, sum = n, y = 0; for (int i = 1; i < n; i++) { if (a[i] != a[i - 1]) { sum -= x; x = 0; if (i - 2 >= 0 && i + 1 < n && a[i - 2] == a[i - 1] && a[i] == a[i + 1]) { if (f < 2) f = 2; } else if (i - 2 >= 0 && i + 1 >= n && a[i - 2] == a[i - 1]) { if (f == 0) f = 1; } else if (i - 2 < 0 && i + 1 < n && a[i] == a[i + 1]) if (f == 0) f = 1; } else { x++; y++; if (i - 1 == 0 || i == n - 1) if (f == 0) f = 1; } if (y > 1) { if (f < 2) f = 2; } else if (y == 1) if (f < 2) f = 1; } sum -= x; sum += f; printf( %d n , sum); } |
#include <bits/stdc++.h> using namespace std; int const xn = 1e4 + 105, xm = 105; int n, m, cnt, hd[xn], ct, to[xn], nxt[xn], w[xn], s1, s2, f; long long dis[2][xn], inf = 1e17; bool vis[xn]; struct E { int u, v, bh, l, r, w; } ed[xm]; struct N { long long d; int id; N(long long d = 0, int i = 0) : d(d), id(i) {} bool operator<(const N &y) const { return d > y.d; } }; priority_queue<N> q; int rd() { int ret = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = 0; ch = getchar(); } while (ch >= 0 && ch <= 9 ) ret = ret * 10 + ch - 0 , ch = getchar(); return f ? ret : -ret; } void add(int x, int y, int z) { to[++ct] = y; nxt[ct] = hd[x]; hd[x] = ct; w[ct] = z; } void dij(int t) { for (int i = 1; i <= n; i++) dis[t][i] = inf; for (int i = 1; i <= n; i++) vis[i] = 0; int st = (t ? s2 : s1); dis[t][st] = 0; q.push(N(0, st)); while (q.size()) { int x = q.top().id; q.pop(); if (vis[x]) continue; vis[x] = 1; for (int i = hd[x], u; i; i = nxt[i]) if (dis[t][u = to[i]] > dis[t][x] + w[i]) { dis[t][u] = dis[t][x] + w[i]; q.push(N(dis[t][u], u)); } } } int main() { n = rd(); m = rd(); cnt = rd(); s1 = rd(); s2 = rd(); f = rd(); for (int i = 1, x, y, z; i <= m; i++) x = rd(), y = rd(), z = rd(), add(x, y, z); for (int i = 1; i <= cnt; i++) ed[i].u = rd(), ed[i].v = rd(), ed[i].l = rd(), ed[i].r = rd(), ed[i].bh = ct + 1, ed[i].w = 1, add(ed[i].u, ed[i].v, ed[i].r); dij(0); dij(1); while (dis[0][f] >= dis[1][f]) { int i; for (i = 1; i <= cnt; i++) if (dis[0][ed[i].u] <= dis[1][ed[i].u] && ed[i].w) break; if (i > cnt) { if (dis[0][f] > dis[1][f]) puts( LOSE ); else { puts( DRAW ); for (int j = 1; j <= cnt; j++) printf( %d , ed[j].w ? ed[j].r : ed[j].l); puts( ); } return 0; } ed[i].w = 0; w[ed[i].bh] = ed[i].l; dij(0); dij(1); } puts( WIN ); for (int j = 1; j <= cnt; j++) printf( %d , ed[j].w ? ed[j].r : ed[j].l); puts( ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_LP_V
`define SKY130_FD_SC_LP__A22OI_LP_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22oi_lp (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22oi_lp (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_LP_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_response_generator #(
parameter ID_WIDTH = 3)(
input clk,
input resetn,
input enable,
output reg enabled,
input [ID_WIDTH-1:0] request_id,
output reg [ID_WIDTH-1:0] response_id,
input eot,
output resp_valid,
input resp_ready,
output resp_eot,
output [1:0] resp_resp
);
`include "inc_id.vh"
`include "resp.vh"
assign resp_resp = RESP_OKAY;
assign resp_eot = eot;
assign resp_valid = request_id != response_id && enabled;
// We have to wait for all responses before we can disable the response handler
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else if (enable == 1'b1) begin
enabled <= 1'b1;
end else if (request_id == response_id) begin
enabled <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
response_id <= 'h0;
end else if (resp_valid == 1'b1 && resp_ready == 1'b1) begin
response_id <= inc_id(response_id);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int test; cin >> test; while (test--) { int bun, beef, chicks, hp, cp, count1 = 0, count2 = 0; cin >> bun >> beef >> chicks >> hp >> cp; bun /= 2; if (hp >= cp) { count1 = min(bun, beef); bun -= count1; if (bun != 0) { count2 = min(bun, chicks); } } else { count2 = min(bun, chicks); bun -= count2; if (bun != 0) { count1 = min(bun, beef); } } cout << count1 * hp + count2 * cp << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4BB_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR4BB_PP_SYMBOL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
input D_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4BB_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pii = pair<int, int>; using pll = pair<ll, ll>; using vi = vector<int>; using vll = vector<ll>; constexpr int MOD = 1e9 + 7; constexpr int INF = INT_MAX; constexpr ll LLINF = LLONG_MAX; template <class T> inline bool setmin(T &a, T b) { if (a > b) return a = b, 1; return 0; } template <class T> inline bool setmax(T &a, T b) { if (a < b) return a = b, 1; return 0; } namespace fastio { template <class T> istream &operator>>(istream &os, vector<T> &container) { for (auto &u : container) os >> u; return os; } template <class T> ostream &operator<<(ostream &os, const vector<T> &container) { for (auto &u : container) os << u << ; return os; } template <class T1, class T2> inline istream &operator>>(istream &os, pair<T1, T2> &p) { return os >> p.first >> p.second; } template <class T1, class T2> ostream &operator<<(ostream &os, const pair<T1, T2> &p) { return os << p.first << << p.second; } template <typename... args> void re(args &...tail) { ((cin >> tail), ...); } template <typename... args> void pr(args... tail) { ((cout << tail << ), ...); } template <typename... args> void prln(args... tail) { ((cout << tail << ), ...); cout << n ; } } // namespace fastio using namespace fastio; namespace debug { template <typename _T> inline void _debug(const char *s, _T x) { cerr << s << = << x << n ; } template <typename _T, typename... args> void _debug(const char *s, _T x, args... a) { while (*s != , ) cerr << *s++; cerr << = << x << , ; _debug(s + 1, a...); } } // namespace debug using namespace debug; const int N = 1e5 + 7; string s; int n, q; int nxt[N][26]; int dp[257][257][257]; string rel[3]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; re(n, q, s); for (int i = (0); i <= (25); i++) nxt[n][i] = nxt[n + 1][i] = n; for (int i = (n - 1); i >= (0); i--) { for (int j = (0); j <= (25); j++) { nxt[i][j] = (s[i] == a + j ? i : nxt[i + 1][j]); } } dp[0][0][0] = -1; for (int _ = (1); _ <= (q); _++) { char t; int x; re(t, x); x--; if (t == + ) { char l; re(l); rel[x] += l; int e0 = (int)(rel[0]).size(), e1 = (int)(rel[1]).size(), e2 = (int)(rel[2]).size(); int b0 = (x == 0 ? e0 : 0); int b1 = (x == 1 ? e1 : 0); int b2 = (x == 2 ? e2 : 0); for (int a = (b0); a <= (e0); a++) { for (int b = (b1); b <= (e1); b++) { for (int c = (b2); c <= (e2); c++) { auto &v = dp[a][b][c]; v = n; if (a) setmin(v, nxt[dp[a - 1][b][c] + 1][rel[0][a - 1] - a ]); if (b) setmin(v, nxt[dp[a][b - 1][c] + 1][rel[1][b - 1] - a ]); if (c) setmin(v, nxt[dp[a][b][c - 1] + 1][rel[2][c - 1] - a ]); } } } } else { rel[x].pop_back(); } prln(dp[(int)(rel[0]).size()][(int)(rel[1]).size()][(int)(rel[2]).size()] < n ? YES : NO ); } exit(0); } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 10086; struct Node { string name; vector<Node *> son; }; char str[MAXN]; int ans; void build(Node *&root, int &pos) { if (str[pos] == 0) { root = NULL; return; } string name = ; for (; str[pos] != . && str[pos] != : ;) { name += str[pos++]; } root = new Node(); root->name = name; if (str[pos] == : ) { do { pos++; Node *son; build(son, pos); if (son != NULL) root->son.push_back(son); } while (str[pos] != . ); } pos++; } void dfs(Node *root, map<string, int> &mp) { if (root == NULL) return; mp[root->name]++; for (vector<Node *>::iterator it = root->son.begin(); it != root->son.end(); it++) { map<string, int> _mp; dfs(*it, _mp); ans += _mp[root->name]; for (map<string, int>::iterator mit = _mp.begin(); mit != _mp.end(); mit++) mp[mit->first] += mit->second; } } int main() { while (~scanf( %s , str)) { Node *root; int pos = 0; build(root, pos); ans = 0; map<string, int> mp; dfs(root, mp); printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { vector<int> v = {1, 3, 9, 27, 81, 243, 729, 2187, 6561, 19683}; vector<int> vis; for (int i = 0; i < (1 << 10); i++) { int sum = 0; for (int j = 0; j < 10; j++) { if (i & (1 << j)) { sum += v[j]; } } vis.push_back(sum); } sort(vis.begin(), vis.end()); int q; cin >> q; while (q--) { int x; cin >> x; cout << *lower_bound(vis.begin(), vis.end(), x) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; void RI() {} template <typename... T> void RI(int& head, T&... tail) { scanf( %d , &head); RI(tail...); } template <typename T> void _dump(const char* s, T&& head) { cerr << s << = << head << endl; } template <typename T, typename... Args> void _dump(const char* s, T&& head, Args&&... tail) { int c = 0; while (*s != , || c != 0) { if (*s == ( || *s == [ || *s == { ) c++; if (*s == ) || *s == ] || *s == } ) c--; cerr << *s++; } cerr << = << head << , ; _dump(s + 1, tail...); } template <typename Iter> ostream& _out(ostream& s, Iter b, Iter e) { s << [ ; for (auto it = b; it != e; it++) s << (it == b ? : ) << *it; s << ] ; return s; } template <typename A, typename B> ostream& operator<<(ostream& s, const pair<A, B>& p) { return s << ( << p.first << , << p.second << ) ; } template <typename T> ostream& operator<<(ostream& s, const vector<T>& c) { return _out(s, begin(c), end(c)); } template <typename T> ostream& operator<<(ostream& s, const set<T>& c) { return _out(s, begin(c), end(c)); } template <typename A, typename B> ostream& operator<<(ostream& s, const map<A, B>& c) { return _out(s, begin(c), end(c)); } vector<int> app[1000010]; int ask(int l, int r, int v) { auto it = lower_bound(begin(app[v]), end(app[v]), l); auto jt = upper_bound(begin(app[v]), end(app[v]), r); return jt - it; } int n, m, a[300010], sa[300010], ord[300010], l[300010], r[300010]; bool vis[300010]; bool cmp(int x, int y) { return a[x] < a[y]; } long long calc(int l1, int r1, int l2, int r2, int mx) { long long ans = 0; mx %= m; if (r1 - l1 <= r2 - l2) { for (int i = (l1 - 1); i <= int(r1 - 1); i++) { int x = sa[i] + mx; if (x >= m) x -= m; int now = ask(l2, r2, x); ans += now; } } else { for (int i = (l2); i <= int(r2); i++) { int x = sa[i] - mx; if (x < 0) x += m; int now = ask(l1 - 1, r1 - 1, x); ans += now; } } return ans; } int main() { RI(n, m); for (int i = (1); i <= int(n); i++) RI(a[i]); for (int i = (1); i <= int(n); i++) l[i] = r[i] = i; for (int i = (1); i <= int(n); i++) ord[i] = i; for (int i = (1); i <= int(n); i++) sa[i] = (sa[i - 1] + a[i]) % m; for (int i = (0); i <= int(n); i++) app[sa[i]].push_back(i); sort(ord + 1, ord + n + 1, cmp); long long ans = 0; for (int ii = (1); ii <= int(n); ii++) { int i = ord[ii]; vis[i] = 1; if (i > 1 && vis[i - 1]) { ans += calc(l[i - 1], i - 1, i, i, a[i]); l[i] = l[i - 1]; r[l[i - 1]] = i; } if (i < n && vis[i + 1]) { ans += calc(l[i], i, i + 1, r[i + 1], a[i]); r[l[i]] = r[i + 1]; l[r[i + 1]] = l[i]; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int judge(int n) { int flag = 0; for (int i = 2; i <= n / 2; i++) { if (n % i == 0) { flag = 1; break; } } if (flag) return 0; else return 1; } int main() { int n; cin >> n; for (int i = 1; i <= 1000; i++) { int sum = i * n + 1; if (judge(sum) == 0) { printf( %d n , i); return 0; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, nq, tr, tg, z, tot, root; int ls[7000010], rs[7000010], s[7000010]; long long mod, ans, x, y; long long b[100010], a[100010]; void push_down(int p) { if (!ls[p]) ls[p] = ++tot; if (!rs[p]) rs[p] = ++tot; if (s[ls[p]] == 0 || s[p] < s[ls[p]]) s[ls[p]] = s[p]; if (s[rs[p]] == 0 || s[p] < s[rs[p]]) s[rs[p]] = s[p]; s[p] = 0; } void change(int &p, long long l, long long r) { if (l > y || r < x) return; if (!p) p = ++tot; if (l >= x && r <= y) { if (s[p] == 0 || z < s[p]) s[p] = z; return; } if (s[p]) push_down(p); change(ls[p], l, (l + r) / 2); change(rs[p], (l + r) / 2 + 1, r); } int query(int &p, long long l, long long r) { if (!p) p = ++tot; if (l == r) return s[p]; if (s[p]) push_down(p); if (x <= (l + r) / 2) return query(ls[p], l, (l + r) / 2); else return query(rs[p], (l + r) / 2 + 1, r); } int main() { int i, j, q; long long tx, ty; scanf( %d%d%d , &n, &tg, &tr); mod = tg + tr; for (i = 1; i <= n + 1; i++) scanf( %I64d , &a[i]); for (i = 1; i <= n + 1; i++) a[i] += a[i - 1]; for (i = n; i >= 1; i--) { x = mod - a[i] % mod; y = query(root, 1, mod); if (!y) b[i] = 0; else b[i] = b[y] + (mod - (a[y] - a[i]) % mod); tx = ((tg - a[i]) % mod + mod - 1) % mod + 1; ty = ((mod - 1 - a[i]) % mod + mod - 1) % mod + 1; z = i; if (tx <= ty) { x = tx; y = ty; change(root, 1, mod); } else { x = 1; y = ty; change(root, 1, mod); x = tx; y = mod; change(root, 1, mod); } } scanf( %d , &nq); for (q = 1; q <= nq; q++) { scanf( %d , &x); ans = x + a[n + 1]; x = (x - 1) % mod + 1; y = query(root, 1, mod); if (y) ans += mod - (a[y] + x) % mod + b[y]; printf( %I64d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int matrix[505][505]; int m, n; int col[505]; int row[505]; int prime[110000]; int pc; bool visit[110000]; void init() { for (int i = 2; i < 110000; i++) { if (visit[i]) continue; for (int j = i * 2; j < 110000; j += i) visit[j] = true; } for (int i = 2; i < 110000; i++) if (!visit[i]) prime[pc++] = i; } int next(int num) { int l, r, mid; l = 0; r = pc - 1; while (l < r) { mid = (l + r) / 2; if (prime[mid] < num) l = mid + 1; else r = mid; } return prime[r] - num; } int main() { int i, j, v, tmp, min; cin >> n >> m; init(); for (i = 0; i < n; i++) for (j = 0; j < m; j++) cin >> matrix[i][j]; for (i = 0; i < n; i++) { v = 0; for (j = 0; j < m; j++) { tmp = next(matrix[i][j]); col[j] += tmp; v += tmp; } row[i] = v; } min = INT_MAX; for (i = 0; i < n; i++) if (min > row[i]) min = row[i]; for (j = 0; j < m; j++) if (min > col[j]) min = col[j]; cout << min << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { int N; cin >> N; long long int dp_D = 1, dp = 0, dp_temp; for (int i = 0; i < N; i++) { dp_temp = dp_D; dp_D = 3 * dp; dp = dp * 2 + dp_temp; dp %= 1000000007; dp_D %= 1000000007; } cout << dp_D << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int T = 1; while (T--) { solve(); } return 0; } |
`timescale 1ns / 1ps
/*
* PicoBlaze_OutReg.v
*
* ___ _ _ _ _ ___ _ _ ___
* | __._ _ _| |_ ___ _| |_| |___ _| | . | \ |_ _|
* | _>| ' ' | . / ._/ . / . / ._/ . | | || |
* |___|_|_|_|___\___\___\___\___\___|_|_|_\_||_|
*
*
* Created on : 20/07/2015
* Author : Ernesto Andres Rincon Cruz
* Web : www.embeddedant.org
* Device : XC3S700AN - 4FGG484
* Board : Spartan-3AN Starter Kit.
*
* Revision History:
* Rev 1.0.0 - (ErnestoARC) First release 19/06/2015.
*/
//////////////////////////////////////////////////////////////////////////////////
module PicoBlaze_OutReg
#(parameter LOCAL_PORT_ID = 8'h00)
(
clk,
reset,
port_id,
write_strobe,
out_port,
new_out_port);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
input wire clk;
input wire reset;
input wire [7:0] port_id;
input wire write_strobe;
input wire [7:0] out_port;
output reg [7:0] new_out_port;
//=======================================================
// REG/WIRE declarations
//=======================================================
reg RegEnable=1;
//=======================================================
// Structural coding
//=======================================================
always @ (*)
begin
if (write_strobe == 1)
begin
case (port_id)
LOCAL_PORT_ID: RegEnable = 1;
default: RegEnable = 0;
endcase
end
else
RegEnable=0;
end
always @ (posedge clk, posedge reset)
begin
if(reset == 1)
new_out_port <= 8'h00;
else
begin
if(RegEnable == 1)
new_out_port <= out_port;
else
new_out_port <= new_out_port;
end
end
//=======================================================
// Connections & assigns
//=======================================================
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 100; const long long INF = 1e12; int solve(long long x) { int res = 0; while (x) { res += (x % 10); x /= 10; } return res; } int main() { ios::sync_with_stdio(false); long long n; while (cin >> n) { long long tmp = 0, b = 0; while (1) { tmp = tmp * 10 + 9; if (tmp > n) break; b = tmp; } cout << solve(b) + solve(n - b) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; int main() { cin >> n >> m; cout << min(n, m) + 1 << endl; for (int i = 0; i <= min(n, m); i++) cout << i << << min(n, m) - i << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO0N_FUNCTIONAL_V
`define SKY130_FD_SC_LP__INPUTISO0N_FUNCTIONAL_V
/**
* inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__inputiso0n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Name Output Other arguments
and and0 (X , A, SLEEP_B );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO0N_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int cnt1[5001] = {0}; int cnt2[5001][5001] = {0}; vector<int> p[5001]; int cnt[5001] = {0}; int solve() { int n, q; cin >> n >> q; vector<pair<int, int>> v; for (int j = 0; j < q; j++) { int l, r; cin >> l >> r; v.push_back({l, r}); } sort(v.begin(), v.end()); for (int j = 0; j < q; j++) { for (int i = v[j].first; i <= v[j].second; i++) { cnt[i]++; if (cnt[i] <= 2) { p[i].push_back(j); } } } int s = 0; for (int j = 1; j <= n; j++) { int k = cnt[j]; if (k) { s++; } if (k == 1) { cnt1[p[j][0]]++; } else if (k == 2) { cnt2[p[j][0]][p[j][1]]++; cnt2[p[j][1]][p[j][0]]++; } } int ans = 0; for (int j = 0; j < q; j++) { for (int i = j + 1; i < q; i++) { ans = max(ans, s - cnt1[j] - cnt1[i] - cnt2[i][j]); } } cout << ans << n ; return 0; } signed main() { ios::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int t; t = 1; while (t--) { solve(); } return 0; } |
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This top level module chooses between the original Altera-ST JTAG Interface
// component in ACDS version 8.1 and before, and the new one with the PLI
// Simulation mode turned on, which adds a wrapper over the original component.
`timescale 1 ns / 1 ns
module altera_avalon_st_jtag_interface #(
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1,
parameter EXPORT_JTAG = 0,
parameter USE_PLI = 0, // set to 1 enable PLI Simulation Mode
parameter PLI_PORT = 50000 // PLI Simulation Port
) (
input wire jtag_tck,
input wire jtag_tms,
input wire jtag_tdi,
output wire jtag_tdo,
input wire jtag_ena,
input wire jtag_usr1,
input wire jtag_clr,
input wire jtag_clrn,
input wire jtag_state_tlr,
input wire jtag_state_rti,
input wire jtag_state_sdrs,
input wire jtag_state_cdr,
input wire jtag_state_sdr,
input wire jtag_state_e1dr,
input wire jtag_state_pdr,
input wire jtag_state_e2dr,
input wire jtag_state_udr,
input wire jtag_state_sirs,
input wire jtag_state_cir,
input wire jtag_state_sir,
input wire jtag_state_e1ir,
input wire jtag_state_pir,
input wire jtag_state_e2ir,
input wire jtag_state_uir,
input wire [2:0] jtag_ir_in,
output wire jtag_irq,
output wire [2:0] jtag_ir_out,
input wire clk,
input wire reset_n,
input wire source_ready,
output wire [7:0] source_data,
output wire source_valid,
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
output wire resetrequest,
output wire debug_reset,
output wire mgmt_valid,
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output wire mgmt_data
);
// Signals in the JTAG clock domain
wire tck;
wire tdi;
wire tdo;
wire [2:0] ir_in;
wire virtual_state_cdr;
wire virtual_state_sdr;
wire virtual_state_udr;
assign jtag_irq = 1'b0;
assign jtag_ir_out = 3'b000;
generate
if (EXPORT_JTAG == 0) begin
// SLD node instantiation
altera_jtag_sld_node node (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_out (1'b0),
.ir_in (ir_in),
.virtual_state_cdr (virtual_state_cdr),
.virtual_state_cir (),
.virtual_state_e1dr (),
.virtual_state_e2dr (),
.virtual_state_pdr (),
.virtual_state_sdr (virtual_state_sdr),
.virtual_state_udr (virtual_state_udr),
.virtual_state_uir ()
);
assign jtag_tdo = 1'b0;
end else begin
assign tck = jtag_tck;
assign tdi = jtag_tdi;
assign jtag_tdo = tdo;
assign ir_in = jtag_ir_in;
assign virtual_state_cdr = jtag_ena && !jtag_usr1 && jtag_state_cdr;
assign virtual_state_sdr = jtag_ena && !jtag_usr1 && jtag_state_sdr;
assign virtual_state_udr = jtag_ena && !jtag_usr1 && jtag_state_udr;
end
endgenerate
generate
if (USE_PLI == 0)
begin : normal
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
end
else
begin : pli_mode
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end
else begin
`ifdef MODEL_TECH
$do_transaction(
PLI_PORT,
pli_out_valid,
source_ready,
pli_out_data,
sink_valid,
pli_in_ready,
sink_data
);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)//,
//.debug_reset(debug_reset),
//.mgmt_valid(mgmt_valid),
//.mgmt_channel(mgmt_channel),
//.mgmt_data(mgmt_data)
);
// synthesis read_comments_as_HDL on
// assign source_valid = jtag_source_valid;
// assign source_data = jtag_source_data;
// assign sink_ready = jtag_sink_ready;
// assign resetrequest = jtag_resetrequest;
// synthesis read_comments_as_HDL off
//synthesis translate_off
assign source_valid = pli_out_valid;
assign source_data = pli_out_data;
assign sink_ready = pli_in_ready;
assign resetrequest = 1'b0;
//synthesis translate_on
assign jtag_tdo = 1'b0;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 0; char ch = getchar(); while (!isdigit(ch)) f |= (ch == - ), ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return f ? -x : x; } inline void write(long long x) { if (x < 0) x = -x, putchar( - ); if (x >= 10) write(x / 10); putchar(x % 10 + 0 ); } long long n, now[4][4] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}; inline long long find(long long x, long long y) { return (x / 4) * (n / 4) + y / 4 + 1; } signed main() { n = read(); for (register long long i = 0; i <= n - 1; i++) { for (register long long j = 0; j <= n - 1; j++) { long long at = find(i, j); cout << (at - 1) * 16 + now[i % 4][j % 4] << ; } puts( ); } return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: mb2cpx_sm.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/***************************************************************************
* mb2cpx_sm.v State machine for the MicroBlaze FSL to SPARC CPX interface
*
* $Id: mb2cpx_sm.v,v 1.1 2007/06/30 00:23:39 tt147840 Exp $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module mb2cpx_sm (
// Outputs
cpx_fsl_s_read,
cpx_shift_out,
cpx_spc_data_rdy_cx2,
// Inputs
rclk,
reset_l,
fsl_cpx_s_exists,
fsl_cpx_s_control,
atomic_txn
);
parameter CPX_GEAR_RATIO = (((`CPX_WIDTH+3-1)/`FSL_D_WIDTH)+1);
parameter CPX_FSL_EXTRA_BITS = (`FSL_D_WIDTH * CPX_GEAR_RATIO) -
(`PCX_WIDTH+3);
parameter [2:0] CPX_FIRST_COUNT = CPX_GEAR_RATIO - 2;
parameter pCPX_IDLE = 0,
pCPX_SHIFT = 1,
pCPX_AT_WAIT = 2;
parameter CPX_IDLE = 3'b001,
CPX_SHIFT = 3'b010,
CPX_AT_WAIT = 3'b100;
// Outputs
output cpx_fsl_s_read;
output cpx_shift_out;
output cpx_spc_data_rdy_cx2;
// Inputs
input rclk;
input reset_l;
input fsl_cpx_s_exists;
input fsl_cpx_s_control;
input atomic_txn;
// Wire definitions for outputs
reg cpx_fsl_s_read;
reg cpx_shift_out;
wire cpx_spc_data_rdy_cx2;
// State machine to control the shifting of data
reg [2:0] curr_state;
reg [2:0] next_state;
reg [2:0] curr_count;
reg [2:0] next_count;
reg atomic_first;
reg atomic_second;
reg next_atomic_first;
reg next_atomic_second;
reg next_shift_out;
reg atomic_second_d1;
reg atomic_second_d2;
reg cpx_shift_out_d1;
always @ (posedge rclk) begin // Start with a synchronous reset
if (!reset_l) begin
curr_state <= CPX_IDLE;
curr_count <= 3'b000;
atomic_first <= 1'b0;
atomic_second <= 1'b0;
cpx_shift_out <= 1'b0;
end
else begin
curr_state <= next_state;
curr_count <= next_count;
atomic_first <= next_atomic_first;
atomic_second <= next_atomic_second;
cpx_shift_out <= next_shift_out;
end
end
always @(posedge rclk) begin
atomic_second_d1 <= atomic_second;
atomic_second_d2 <= atomic_second_d1;
cpx_shift_out_d1 <= cpx_shift_out;
end
always @ (curr_state or fsl_cpx_s_exists or fsl_cpx_s_control or
curr_count or atomic_txn or atomic_first or atomic_second) begin
case (1)
curr_state[pCPX_IDLE] : begin
next_atomic_second = 1'b0;
next_shift_out = 1'b0;
if (fsl_cpx_s_exists && fsl_cpx_s_control) begin
next_state = CPX_SHIFT;
next_count = CPX_FIRST_COUNT;
next_atomic_first = atomic_txn;
cpx_fsl_s_read = 1'b1;
end
// Expect that the control bit will be set for the first
// 32-bit sub-word of each transaction. Just a double-check
// to ensure we are in sync. Drop any initial words without
// a control bit
else if (fsl_cpx_s_exists && !fsl_cpx_s_control) begin
next_state = CPX_IDLE;
next_count = 3'b000;
next_atomic_first = 1'b0;
cpx_fsl_s_read = 1'b1;
end
else begin
next_state = CPX_IDLE;
next_count = 3'b000;
next_atomic_first = 1'b0;
cpx_fsl_s_read = 1'b0;
end
end
curr_state[pCPX_SHIFT] : begin
if (fsl_cpx_s_exists && curr_count == 3'b000) begin
if (atomic_first) begin
next_state = CPX_AT_WAIT;
next_count = curr_count;
next_atomic_first = 1'b0;
next_atomic_second = atomic_first;
cpx_fsl_s_read = 1'b1;
next_shift_out = 1'b1;
end
else begin
next_state = CPX_IDLE;
next_count = CPX_FIRST_COUNT;
next_atomic_first = 1'b0;
next_atomic_second = 1'b0;
cpx_fsl_s_read = 1'b1;
next_shift_out = 1'b1;
end
end
else if (fsl_cpx_s_exists) begin
next_state = CPX_SHIFT;
next_count = curr_count - 3'b001;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
cpx_fsl_s_read = 1'b1;
next_shift_out = 1'b0;
end
else begin
next_state = CPX_SHIFT;
next_count = curr_count;
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
cpx_fsl_s_read = 1'b0;
next_shift_out = 1'b0;
end
end
curr_state[pCPX_AT_WAIT] : begin
next_atomic_first = atomic_first;
next_atomic_second = atomic_second;
next_shift_out = 1'b0;
if (fsl_cpx_s_exists && fsl_cpx_s_control) begin
next_state = CPX_SHIFT;
next_count = CPX_FIRST_COUNT;
cpx_fsl_s_read = 1'b1;
end
// Expect that the control bit will be set for the first
// 32-bit sub-word of each transaction. Just a double-check
// to ensure we are in sync. Drop any initial words without
// a control bit
else if (fsl_cpx_s_exists && !fsl_cpx_s_control) begin
next_state = CPX_AT_WAIT;
next_count = 3'b000;
cpx_fsl_s_read = 1'b1;
end
else begin
next_state = CPX_AT_WAIT;
next_count = 3'b000;
cpx_fsl_s_read = 1'b0;
end
end
default : begin
next_state = CPX_IDLE;
next_count = 3'b000;
next_atomic_first = 1'b0;
next_atomic_second = 1'b0;
cpx_fsl_s_read = 1'b0;
next_shift_out = 1'b0;
end
endcase
end
// Outputs of the state machine
assign cpx_spc_data_rdy_cx2 = (!atomic_second && !atomic_second_d2 &&
cpx_shift_out_d1) ||
(atomic_second_d1 && cpx_shift_out);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[100100], q[1000000], ql, qr, m[100100][2]; bool edge(int i, int j) { return m[i][0] == j || m[i][1] == j; } void add(int i, int j) { if (m[i][0] == -1) m[i][0] = j; else m[i][1] = j; } int main() { int i, j, k, n, l, L, t, x = 1; for (i = 0; i < 100100; m[i][0] = -1, m[i][1] = -1, i++) ; for (scanf( %d%d , &n, &k), l = 0; l < k; scanf( %d%d , &i, &j), i--, j--, add(i, j), add(j, i), l++) ; for (i = 0; i < n; a[i] = i, i++) ; for (L = 0; L < 10000000;) { random_shuffle(a, a + n); L += n; ql = 0; qr = 0; for (i = 0; i < k; i++) if (edge(a[i], a[(i + 1) % n])) q[qr++] = i; for (t = 0; t < n && ql < qr; t++, L++, x = ((long long)x * 123121 + 412412) % 1000000007) { i = q[ql++]; if (!edge(a[i], a[(i + 1) % n])) continue; if (x % 2) i = (i + 2) % n; swap(a[(i + n - 1) % n], a[i % n]); for (j = i - 2; j <= i; j += 2) if (edge(a[(j + 2 * n) % n], a[(j + 1 + 2 * n) % n])) q[qr++] = (j + 2 * n) % n; } if (ql == qr) break; } if (L < 10000000) { for (i = 0; i < k; printf( %d %d n , a[i] + 1, a[(i + 1) % n] + 1), i++) if (edge(a[i], a[(i + 1) % n])) throw; } else printf( -1 n ); return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_8_axi_basic_rx.v
// Version : 1.7
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_8_axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [KEEP_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_8_axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
pcie_7x_v1_8_axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVP_TB_V
`define SKY130_FD_SC_LS__EINVP_TB_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__einvp.v"
module top();
// Inputs are registered
reg A;
reg TE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ls__einvp dut (.A(A), .TE(TE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVP_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; void solve() { long long n; cin >> n; string s; cin >> s; vector<long long> v(n); for (long long i = 0; i <= n - 1; i++) cin >> v[i]; long long ans = mod; for (long long i = 0; i <= n - 2; i++) { if (s[i] == R && s[i + 1] == L ) ans = min(ans, abs(v[i] - v[i + 1])); } if (ans == mod) cout << -1; else cout << ans / 2; } int main() { long long tc = 1; while (tc--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; long long max(long long a, long long b) { if (a > b) { return a; } else { return b; } } long long min(long long a, long long b) { if (a < b) { return a; } else { return b; } } struct P { double x, y; P() {} P(double x, double y) : x(x), y(y) {} P operator+(const P &a) const { return P(x + a.x, y + a.y); } P operator-(const P &a) const { return P(x - a.x, y - a.y); } double operator^(const P &a) const { return x * a.x + y * a.y; } void in() { scanf( %lf%lf , &x, &y); } void out() { printf( REQUIRED %.7f %.7f n , x, y); } double dist(P a, P b) { return sqrt((a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y)); } double sqdist(P a, P b) { return (a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y); } }; int n, k; int a[9999]; int b[9999]; int cc[9999]; int bb[9999]; long long res = -100000000; long long ma[9999]; long long query(long long l, long long r) { int length = r - l + 1; if (length <= k) return ma[length]; int cnt = 0; for (int i = (1); i <= (n); i++) { if ((i < l) || (i > r)) cc[++cnt] = a[i]; } int cnt2 = 0; for (int i = (l); i <= (r); i++) bb[++cnt2] = a[i]; sort(cc + 1, cc + cnt + 1); sort(bb + 1, bb + cnt2 + 1); int go = 0; for (int i = (1); i <= (min(min(cnt, cnt2), k)); i++) { if (cc[cnt - i + 1] > bb[i]) go = i; } for (int i = (1); i <= (go); i++) bb[i] = cc[cnt - i + 1]; long long sum = 0; for (int i = (1); i <= (cnt2); i++) sum += bb[i]; return sum; } int main() { scanf( %d%d , &n, &k); for (int i = (1); i <= (n); i++) scanf( %d , &a[i]); for (int i = (1); i <= (n); i++) b[i] = a[i]; sort(b + 1, b + n + 1); ma[0] = 0; for (int i = (n); i >= (1); i--) { ma[n - i + 1] = ma[n - i] + b[i]; } for (int i = (1); i <= (n); i++) { for (int j = (i); j <= (n); j++) { res = max(res, query(i, j)); } } printf( %I64d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, c, d, e, f; cin >> a >> b >> c >> d >> e >> f; if (d == 0) cout << Hermione << endl; else if (c == 0) cout << Ron << endl; else if (b == 0) cout << Hermione << endl; else if (a == 0) cout << Ron << endl; else if (f == 0) cout << Hermione << endl; else if (e == 0) cout << Ron << endl; else cout << (b * d * f > a * c * e ? Ron : Hermione ) << endl; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; int main() { int cases; scanf( %d , &cases); while (cases--) { char str[1009]; int ret[9]; scanf( %s , str); int num = 0; int i; int cnt = 0; int flag = -1; for (i = 0; str[i]; i++) { if (str[i] >= A && str[i] <= Z ) { str[i] = str[i] - A + a ; } if (str[i] == : ) { if (str[i + 1] == : ) { flag = cnt; i++; } ret[cnt] = num; cnt++; num = 0; } else if (str[i] >= 0 && str[i] <= 9 ) { num = num * 16 + str[i] - 0 ; } else { num = num * 16 + str[i] - a + 10; } } ret[cnt++] = num; int k = 0; for (int j = 0; j < cnt; j++) { printf( %04x , ret[j]); k++; if (k != 8) { putchar( : ); } if (flag == j) { for (i = 0; i < 8 - cnt; i++) { printf( 0000 ); k++; if (k != 8) { putchar( : ); } } } } putchar(10); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////
//// ////
//// ////
//// Sincronizador ////
//// ////
//// ////
//// Este archivo describe el comportamiento ////
//// de un temporizador en Verilog ////
//// ////
//// Description ////
//// Este módulo es un temporizador que cuenta 7 segundos para ////
//// enviar una señal a la maquina de estados y cerrar la puerta ////
//// del ascensor. Tiene 3 entradas: _clk_ el reloj de 1Hz, ////
//// start_i que habilita la cuenta y restart_i que se encarga de////
//// reiniciar la cuenta. La salida es una señal t_expired que se////
//// habilita en un ciclo de reloj cuando la cuenta llega a 7. ////
//// ////
//// ////
//// ////
//// ////
//// Autor : ////
//// - Manuel Zumbado Corrales ////
//// - Arturo Salas Delgado ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
/// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module Temporizador( _clk_, start_i, restart_i, t_expired_o);
input _clk_, start_i, restart_i;
output t_expired_o;
reg[3:0] contador = 4'b0; //registro que almacena Contador
localparam contador_max=7; //Se cuentan 7 segundos
reg t_expired_o=0;
always @(posedge _clk_) begin
t_expired_o<=0;
if(restart_i)
contador <=0;
else begin
if (start_i) begin
if(contador==contador_max-1) begin
t_expired_o<=1'b1;
contador <=0;
end
else begin
contador <= contador+1;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void AWAD() { std::ios::sync_with_stdio(false); cin.tie(0); } bool cmp(long long int a, long long int b) { if (a > b) return true; return false; } int a[1000001], b[1000001]; int main() { AWAD(); string input; long long int c4 = 0, c7 = 0; cin >> input; for (int i = 0; i < input.size(); i++) if (input[i] == 4 ) ++c4; else if (input[i] == 7 ) ++c7; if (!c4 && !c7) cout << -1 n ; else if (c4 >= c7) cout << 4 << endl; else cout << 7 << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O2111A_FUNCTIONAL_PP_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o2111a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , B1, C1, or0_out, D1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111A_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; vector<int> ed[N], leaves; int n, root = -1; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; ed[u].push_back(v); ed[v].push_back(u); } for (int i = 1; i <= n; i++) { if (ed[i].size() > 2) { if (root != -1) { cout << No n ; return 0; } root = i; } if (ed[i].size() == 1) leaves.push_back(i); } if (root == -1) cout << Yes n << 1 n << leaves[0] << << leaves.back() << n ; else { cout << Yes n ; cout << leaves.size() << n ; for (auto i : leaves) cout << root << << i << n ; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/07/04 14:03:17
// Design Name:
// Module Name: clock_50Hz
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clock_50Hz(clk,rst_n,out_50Hz,out_50Hz_pulse);
input clk,rst_n;
output reg out_50Hz,out_50Hz_pulse;
reg [31:0] counter;
always @ (posedge clk or negedge rst_n)
if (!rst_n) begin
out_50Hz_pulse <= 0;
out_50Hz <= 0;
counter <= 0;
end
else begin //clk=100MHz
if (counter >= 32'd1_999_999) begin
counter <= 0;
out_50Hz_pulse <= 1;
out_50Hz <= 1;
end
else begin
if (counter < 32'd1_000_000) out_50Hz <= 1;
else if (counter < 32'd2_000_000) out_50Hz <= 0;
counter <= counter + 1;
out_50Hz_pulse <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve(string s, int n) { if (s.size() <= 3) { cout << s; return; } cout << s.substr(0, 2) << - ; s = s.substr(2, n - 2); solve(s, n); } int main() { int n; cin >> n; string s; cin >> s; solve(s, n); } |
// File: rom.v
// Generated by MyHDL 1.0dev
// Date: Fri Nov 18 06:48:26 2016
`timescale 1ns/10ps
module rom (
dout,
addr
);
output [7:0] dout;
reg [7:0] dout;
input [6:0] addr;
always @(addr) begin: ROM_READ
case (addr)
0: dout = 0;
1: dout = 8;
2: dout = 28;
3: dout = 28;
4: dout = 28;
5: dout = 28;
6: dout = 28;
7: dout = 8;
8: dout = 0;
9: dout = 120;
10: dout = 14;
11: dout = 7;
12: dout = 3;
13: dout = 1;
14: dout = 1;
15: dout = 1;
16: dout = 0;
17: dout = 0;
18: dout = 0;
19: dout = 24;
20: dout = 62;
21: dout = 103;
22: dout = 65;
23: dout = 0;
24: dout = 0;
25: dout = 0;
26: dout = 12;
27: dout = 30;
28: dout = 63;
29: dout = 107;
30: dout = 73;
31: dout = 8;
32: dout = 0;
33: dout = 51;
34: dout = 102;
35: dout = 108;
36: dout = 123;
37: dout = 119;
38: dout = 101;
39: dout = 65;
40: dout = 0;
41: dout = 0;
42: dout = 0;
43: dout = 6;
44: dout = 63;
45: dout = 127;
46: dout = 59;
47: dout = 41;
48: dout = 0;
49: dout = 59;
50: dout = 30;
51: dout = 12;
52: dout = 8;
53: dout = 24;
54: dout = 60;
55: dout = 110;
56: dout = 0;
57: dout = 28;
58: dout = 94;
59: dout = 56;
60: dout = 24;
61: dout = 60;
62: dout = 102;
63: dout = 67;
64: dout = 0;
65: dout = 99;
66: dout = 62;
67: dout = 93;
68: dout = 127;
69: dout = 93;
70: dout = 62;
71: dout = 99;
72: dout = 0;
73: dout = 8;
74: dout = 68;
75: dout = 110;
76: dout = 127;
77: dout = 110;
78: dout = 68;
79: dout = 8;
80: dout = 0;
81: dout = 96;
82: dout = 120;
83: dout = 62;
84: dout = 47;
85: dout = 41;
86: dout = 97;
87: dout = 64;
88: dout = 0;
89: dout = 12;
90: dout = 30;
91: dout = 8;
92: dout = 60;
93: dout = 102;
94: dout = 65;
95: dout = 0;
96: dout = 0;
97: dout = 30;
98: dout = 3;
99: dout = 70;
100: dout = 92;
101: dout = 80;
102: dout = 120;
103: dout = 63;
104: dout = 0;
105: dout = 48;
106: dout = 88;
107: dout = 64;
108: dout = 67;
109: dout = 70;
110: dout = 108;
111: dout = 56;
112: dout = 0;
113: dout = 127;
114: dout = 63;
115: dout = 3;
116: dout = 3;
117: dout = 3;
118: dout = 3;
119: dout = 3;
120: dout = 0;
121: dout = 65;
122: dout = 99;
123: dout = 59;
124: dout = 63;
125: dout = 47;
126: dout = 99;
default: dout = 67;
endcase
end
endmodule
|
#include <bits/stdc++.h> const int MOD = 1E9 + 7; const int N = 150000 + 5; const int dx[] = {-1, 1, 0, 0, -1, -1, 1, 1}; const int dy[] = {0, 0, -1, 1, -1, 1, -1, 1}; using namespace std; struct Edge { int nex, to; int w; Edge() {} Edge(int nex, int to, int w) : nex(nex), to(to), w(w) {} } edge[5151111]; int head[N]; int cnt; void addEdge(int from, int to, int w) { edge[++cnt].nex = head[from]; edge[cnt].to = to; edge[cnt].w = w; head[from] = cnt++; } vector<int> G[N]; vector<int> nex[N]; int dis[N]; bool vis[N]; int Find(int y, int w) { int left = 0, right = G[y].size() - 1; while (left <= right) { int mid = (left + right) / 2; if (G[y][mid] > w) right = mid - 1; else if (G[y][mid] < w) left = mid + 1; else return nex[y][mid]; } return w; } int SPFA(int s, int n) { memset(dis, 0x3f3f3f3f, sizeof(dis)); memset(vis, false, sizeof(vis)); vis[s] = true; dis[s] = Find(1, 0); queue<int> Q; Q.push(s); while (!Q.empty()) { int x = Q.front(); Q.pop(); vis[x] = false; for (int i = head[x]; i != -1; i = edge[i].nex) { int y = edge[i].to; int w = edge[i].w; int times = dis[x] + w; if (y != n) times = Find(y, times); if (dis[y] > times) { dis[y] = times; if (!vis[y]) { vis[y] = true; Q.push(y); } } } } return dis[n]; } int main() { int n, m; scanf( %d%d , &n, &m); memset(head, -1, sizeof(head)); for (int i = 1; i <= m; i++) { int x, y, w; scanf( %d%d%d , &x, &y, &w); addEdge(x, y, w); addEdge(y, x, w); } for (int i = 1; i <= n; i++) { int t; scanf( %d , &t); while (t--) { int x; scanf( %d , &x); G[i].push_back(x); } } for (int i = 1; i <= n; i++) { for (int j = G[i].size() - 1; j >= 0; j--) { int before; if (j == G[i].size() - 1 || G[i][j] != G[i][j + 1] - 1) before = G[i][j] + 1; nex[i].push_back(before); } reverse(nex[i].begin(), nex[i].end()); } int res = SPFA(1, n); if (res == 0x3f3f3f3f) res = -1; printf( %d n , res); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize(3) #pragma GCC optimize(2) using namespace std; const int maxn = 2e5 + 10; char s[maxn]; int N, K; long long T; int A[22][22]; long long DP[1 << 22]; long long t[22]; int mask[22]; int main() { scanf( %d %d %lld , &N, &K, &T); scanf( %s , s + 1); for (int i = 0; i < K; ++i) { scanf( %lld , &t[i]); } for (int i = 0; i < K; ++i) { for (int j = 0; j < K; ++j) { scanf( %d , &A[i][j]); } } for (int i = 0; i < K; ++i) { DP[1 << i] = t[i]; mask[i] = -1; } int S = 0; for (int i = 1; i <= N; ++i) { int x = s[i] - A ; S |= (1 << x); for (int j = 0; j < K; ++j) { if (mask[j] >= 0) { if ((mask[j] & (1 << j)) == 0 && (mask[j] & (1 << x)) == 0) { DP[mask[j]] += A[j][x]; DP[mask[j] | (1 << j)] -= A[j][x]; DP[mask[j] | (1 << x)] -= A[j][x]; DP[mask[j] | (1 << j) | (1 << x)] += A[j][x]; } mask[j] |= (1 << x); } } mask[x] = 0; } for (int i = 0; i < K; ++i) { for (int s = 0; s < (1 << K); ++s) { if (s & (1 << i)) { DP[s] += DP[s ^ (1 << i)]; } } } long long ret = 0; for (int s = 0; s < (1 << K); ++s) { if ((s & S) == s && DP[s] <= T && s != S) { ++ret; } } printf( %lld n , ret); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2_2_V
`define SKY130_FD_SC_LS__AND2_2_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SRSDFRTN_BEHAVIORAL_PP_V
/**
* srsdfrtn: Scan flop with sleep mode, inverted reset, inverted
* clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nr_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_nr_pp_pkg_sn.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__srsdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$NR_pp$PKG$sN `UNIT_DELAY dff0 (buf_Q , mux_out, CLK_N_delayed, RESET, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( ( SLEEP_B === 1'b1 ) && awake );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 && awake );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
bufif1 bufif10 (Q , buf_Q, VPWR );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTN_BEHAVIORAL_PP_V |
// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 16.1.1 Build 200 11/30/2016 SJ Lite Edition"
// DATE "02/14/2017 10:24:10"
//
// Device: Altera EP4CE22F17C6 Package FBGA256
//
//
// This greybox netlist file is for third party Synthesis Tools
// for timing and resource estimation only.
//
module clckctrl (
inclk,
ena,
outclk)/* synthesis synthesis_greybox=0 */;
input inclk;
input ena;
output outclk;
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;
wire \altclkctrl_0|clckctrl_altclkctrl_0_sub_component|wire_clkctrl1_outclk ;
wire \ena~input_o ;
wire \inclk~input_o ;
clckctrl_clckctrl_altclkctrl_0 altclkctrl_0(
.outclk(\altclkctrl_0|clckctrl_altclkctrl_0_sub_component|wire_clkctrl1_outclk ),
.ena(\ena~input_o ),
.inclk(\inclk~input_o ));
assign \ena~input_o = ena;
assign \inclk~input_o = inclk;
assign outclk = \altclkctrl_0|clckctrl_altclkctrl_0_sub_component|wire_clkctrl1_outclk ;
endmodule
module clckctrl_clckctrl_altclkctrl_0 (
outclk,
ena,
inclk)/* synthesis synthesis_greybox=0 */;
output outclk;
input ena;
input inclk;
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;
clckctrl_clckctrl_altclkctrl_0_sub clckctrl_altclkctrl_0_sub_component(
.outclk(outclk),
.ena(ena),
.inclk({gnd,gnd,gnd,inclk}));
endmodule
module clckctrl_clckctrl_altclkctrl_0_sub (
outclk,
ena,
inclk)/* synthesis synthesis_greybox=0 */;
output outclk;
input ena;
input [3:0] inclk;
wire gnd;
wire vcc;
wire unknown;
assign gnd = 1'b0;
assign vcc = 1'b1;
// unknown value (1'bx) is not needed for this tool. Default to 1'b0
assign unknown = 1'b0;
cycloneive_clkctrl clkctrl1(
.ena(ena),
.inclk({gnd,gnd,gnd,inclk[0]}),
.clkselect({gnd,gnd}),
.outclk(outclk));
defparam clkctrl1.clock_type = "global clock";
defparam clkctrl1.ena_register_mode = "falling edge";
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1005; double a[N][N], f[N]; int n, m, sx, sy; inline void solve(int x) { memset(a, 0, sizeof(a)); for (int i = 1; i <= m; ++i) { if (i == 1) { a[1][1] = 2; a[1][2] = -1; a[1][m + 1] = 3 + f[1]; } else if (i == m) { a[m][m] = 2; a[m][m - 1] = -1; a[m][m + 1] = 3 + f[m]; } else { a[i][i] = 3; a[i][i - 1] = a[i][i + 1] = -1; a[i][m + 1] = 4 + f[i]; } } for (int i = 1; i < m; ++i) { double p = a[i + 1][i] / a[i][i]; a[i + 1][i] = 0; a[i + 1][i + 1] -= a[i][i + 1] * p; a[i + 1][m + 1] -= a[i][m + 1] * p; } f[m] = a[m][m + 1] / a[m][m]; for (int i = m - 1; i >= 1; --i) { f[i] = (a[i][m + 1] + f[i + 1]) / a[i][i]; } } int main() { scanf( %d%d , &n, &m); scanf( %d%d , &sx, &sy); if (m == 1) { printf( %.10lf n , 2.0 * (n - sx)); return 0; } for (int i = n - 1; i >= sx; --i) solve(i); printf( %.10lf n , f[sy]); return 0; } |
//Define 32 to 16 multiplexer
module multiplexer32to16(out , in1 , in2 ,control);
// I/O port declaration
output [31:0] out;
input [31:0] in1,in2;
input control;
//internal nets
wire control_not;
wire [31:0] anded_out_1,anded_out_2;
//internal gate circuitry
not (control_not,control);
and (anded_out_1[0] , control_not , in1[0]);
and (anded_out_1[1] , control_not , in1[1]);
and (anded_out_1[2] , control_not , in1[2]);
and (anded_out_1[3] , control_not , in1[3]);
and (anded_out_1[4] , control_not , in1[4]);
and (anded_out_1[5] , control_not , in1[5]);
and (anded_out_1[6] , control_not , in1[6]);
and (anded_out_1[7] , control_not , in1[7]);
and (anded_out_1[8] , control_not , in1[8]);
and (anded_out_1[9] , control_not , in1[9]);
and (anded_out_1[10] , control_not , in1[10]);
and (anded_out_1[11] , control_not , in1[11]);
and (anded_out_1[12] , control_not , in1[12]);
and (anded_out_1[13] , control_not , in1[13]);
and (anded_out_1[14] , control_not , in1[14]);
and (anded_out_1[15] , control_not , in1[15]);
and (anded_out_1[16] , control_not , in1[16]);
and (anded_out_1[17] , control_not , in1[17]);
and (anded_out_1[18] , control_not , in1[18]);
and (anded_out_1[19] , control_not , in1[19]);
and (anded_out_1[20] , control_not , in1[20]);
and (anded_out_1[21] , control_not , in1[21]);
and (anded_out_1[22] , control_not , in1[22]);
and (anded_out_1[23] , control_not , in1[23]);
and (anded_out_1[24] , control_not , in1[24]);
and (anded_out_1[25] , control_not , in1[25]);
and (anded_out_1[26] , control_not , in1[26]);
and (anded_out_1[27] , control_not , in1[27]);
and (anded_out_1[28] , control_not , in1[28]);
and (anded_out_1[29] , control_not , in1[29]);
and (anded_out_1[30] , control_not , in1[30]);
and (anded_out_1[31] , control_not , in1[31]);
and (anded_out_2[0] , control , in2[0]);
and (anded_out_2[1] , control , in2[1]);
and (anded_out_2[2] , control , in2[2]);
and (anded_out_2[3] , control , in2[3]);
and (anded_out_2[4] , control , in2[4]);
and (anded_out_2[5] , control , in2[5]);
and (anded_out_2[6] , control , in2[6]);
and (anded_out_2[7] , control , in2[7]);
and (anded_out_2[8] , control , in2[8]);
and (anded_out_2[9] , control , in2[9]);
and (anded_out_2[10] , control , in2[10]);
and (anded_out_2[11] , control , in2[11]);
and (anded_out_2[12] , control , in2[12]);
and (anded_out_2[13] , control , in2[13]);
and (anded_out_2[14] , control , in2[14]);
and (anded_out_2[15] , control , in2[15]);
and (anded_out_2[16] , control , in2[16]);
and (anded_out_2[17] , control , in2[17]);
and (anded_out_2[18] , control , in2[18]);
and (anded_out_2[19] , control , in2[19]);
and (anded_out_2[20] , control , in2[20]);
and (anded_out_2[21] , control , in2[21]);
and (anded_out_2[22] , control , in2[22]);
and (anded_out_2[23] , control , in2[23]);
and (anded_out_2[24] , control , in2[24]);
and (anded_out_2[25] , control , in2[25]);
and (anded_out_2[26] , control , in2[26]);
and (anded_out_2[27] , control , in2[27]);
and (anded_out_2[28] , control , in2[28]);
and (anded_out_2[29] , control , in2[29]);
and (anded_out_2[30] , control , in2[30]);
and (anded_out_2[31] , control , in2[31]);
or (out[0] , anded_out_1[0] , anded_out_2[0]);
or (out[1] , anded_out_1[1] , anded_out_2[1]);
or (out[2] , anded_out_1[2] , anded_out_2[2]);
or (out[3] , anded_out_1[3] , anded_out_2[3]);
or (out[4] , anded_out_1[4] , anded_out_2[4]);
or (out[5] , anded_out_1[5] , anded_out_2[5]);
or (out[6] , anded_out_1[6] , anded_out_2[6]);
or (out[7] , anded_out_1[7] , anded_out_2[7]);
or (out[8] , anded_out_1[8] , anded_out_2[8]);
or (out[9] , anded_out_1[9] , anded_out_2[9]);
or (out[10] , anded_out_1[10] , anded_out_2[10]);
or (out[11] , anded_out_1[11] , anded_out_2[11]);
or (out[12] , anded_out_1[12] , anded_out_2[12]);
or (out[13] , anded_out_1[13] , anded_out_2[13]);
or (out[14] , anded_out_1[14] , anded_out_2[14]);
or (out[15] , anded_out_1[15] , anded_out_2[15]);
or (out[16] , anded_out_1[16] , anded_out_2[16]);
or (out[17] , anded_out_1[17] , anded_out_2[17]);
or (out[18] , anded_out_1[18] , anded_out_2[18]);
or (out[19] , anded_out_1[19] , anded_out_2[19]);
or (out[20] , anded_out_1[20] , anded_out_2[20]);
or (out[21] , anded_out_1[21] , anded_out_2[21]);
or (out[22] , anded_out_1[22] , anded_out_2[22]);
or (out[23] , anded_out_1[23] , anded_out_2[23]);
or (out[24] , anded_out_1[24] , anded_out_2[24]);
or (out[25] , anded_out_1[25] , anded_out_2[25]);
or (out[26] , anded_out_1[26] , anded_out_2[26]);
or (out[27] , anded_out_1[27] , anded_out_2[27]);
or (out[28] , anded_out_1[28] , anded_out_2[28]);
or (out[29] , anded_out_1[29] , anded_out_2[29]);
or (out[30] , anded_out_1[30] , anded_out_2[30]);
or (out[31] , anded_out_1[31] , anded_out_2[31]);
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize(2) #pragma warning(disable : 4996) using namespace std; const long long INF = 2147483647; const double PI = acos(-1); const int mod = 1e9 + 7; bool vis[3][120000]; int main() { long long n, q; cin >> n >> q; long long obstacles = 0; for (int j = 1; j <= q; j++) { long long x, y; cin >> x >> y; long long increment = vis[x][y] == 1 ? -1 : 1; vis[x][y] = 1 - vis[x][y]; long long dx = x == 2 ? 1 : 2; for (int i = -1; i <= 1; i++) { if (vis[dx][y + i]) obstacles += increment; } if (obstacles) cout << No << endl; else cout << Yes << endl; } return 0; } |
`timescale 1ns/1ps
module SPIFSM #(
parameter SPPRWidth = 4,
parameter SPRWidth = 4,
parameter DataWidth = 8
) (
input Reset_n_i,
input Clk_i,
// FSM control
input Start_i,
output reg Done_o,
output reg [DataWidth-1:0] Byte0_o,
output reg [DataWidth-1:0] Byte1_o,
// to/from SPI_Master
input SPI_Transmission_i,
output reg SPI_Write_o,
output reg SPI_ReadNext_o,
output reg [DataWidth-1:0] SPI_Data_o,
input [DataWidth-1:0] SPI_Data_i,
input SPI_FIFOFull_i,
input SPI_FIFOEmpty_i,
// to ADT7310
output reg ADT7310CS_n_o,
// parameters
input [15:0] ParamCounterPreset_i
);
// SPI FSM
localparam stIdle = 4'b0000;
localparam stWriteValue = 4'b0001;
localparam stWaitSent = 4'b0010;
localparam stConsume1 = 4'b0011;
localparam stWait = 4'b0100;
localparam stWriteDummy1= 4'b0101;
localparam stWriteDummy2= 4'b0110;
localparam stRead1 = 4'b0111;
localparam stRead2 = 4'b1000;
localparam stRead3 = 4'b1001;
localparam stPause = 4'b1010;
reg [3:0] SPI_FSM_State;
reg [3:0] SPI_FSM_NextState;
wire SPI_FSM_TimerOvfl;
reg SPI_FSM_TimerPreset;
reg SPI_FSM_TimerEnable;
reg SPI_FSM_Wr1;
reg SPI_FSM_Wr0;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SPI_FSM_State <= stIdle;
end
else
begin
SPI_FSM_State <= SPI_FSM_NextState;
end
end
always @(SPI_FSM_State, Start_i, SPI_Transmission_i, SPI_FSM_TimerOvfl)
begin // process SPI_FSM_CombProc
SPI_FSM_NextState = SPI_FSM_State;
// control signal default values
ADT7310CS_n_o = 1'b1;
SPI_Data_o = 8'bxxxxxxxx; // most time we don't care which value is set
SPI_Write_o = 1'b0;
SPI_ReadNext_o = 1'b0;
SPI_FSM_TimerPreset = 1'b1;
SPI_FSM_TimerEnable = 1'b0;
SPI_FSM_Wr1 = 1'b0;
SPI_FSM_Wr0 = 1'b0;
Done_o = 1'b1;
// next state and output logic
case (SPI_FSM_State)
stIdle: begin
if (Start_i == 1'b1)
begin
// single-shot measurement mode: write to 8-bit configuration
// register (0x01): send 0x08 0x20 (one shot mode)
SPI_FSM_NextState = stWriteValue;
ADT7310CS_n_o = 1'b0;
SPI_Data_o = 8'h08;
SPI_Write_o = 1'b1;
Done_o = 1'b0;
end
end
stWriteValue: begin
SPI_FSM_NextState = stWaitSent;
ADT7310CS_n_o = 1'b0;
// send 0x20
SPI_Data_o = 8'h20;
SPI_Write_o = 1'b1;
Done_o = 1'b0;
end
stWaitSent: begin
// wait until SPI transmission has finished
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
if (SPI_Transmission_i == 1'b0)
begin
SPI_FSM_NextState = stConsume1;
SPI_ReadNext_o = 1'b1; // consume first received value
end
end
stConsume1: begin
SPI_FSM_NextState = stWait;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_ReadNext_o = 1'b1; // consume second received value
SPI_FSM_TimerPreset = 1'b0;
SPI_FSM_TimerEnable = 1'b1; // start timer
end
stWait: begin
// wait for 240ms
ADT7310CS_n_o = 1'b1;
Done_o = 1'b0;
if (SPI_FSM_TimerOvfl == 1'b0)
begin
SPI_FSM_TimerPreset = 1'b0;
SPI_FSM_TimerEnable = 1'b1; // timer running
end
else
begin
// timer overflow -> continue: send read command and two dummy bytes
ADT7310CS_n_o = 1'b0;
SPI_FSM_NextState = stWriteDummy1;
SPI_Data_o = 8'h50;
SPI_Write_o = 1'b1;
end
end
stWriteDummy1: begin
SPI_FSM_NextState = stWriteDummy2;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_Data_o = 8'hFF;
SPI_Write_o = 1'b1;
end
stWriteDummy2: begin
SPI_FSM_NextState = stRead1;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_Data_o = 8'hFF;
SPI_Write_o = 1'b1;
end
stRead1: begin
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
// wait until SPI transmission has finished
if (SPI_Transmission_i == 1'b0) begin
SPI_FSM_NextState = stRead2;
// consume and ignore first byte
SPI_ReadNext_o = 1'b1;
end
end
stRead2: begin
Done_o = 1'b0;
// consume and store second byte
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr1 = 1'b1;
SPI_FSM_NextState = stRead3;
end
stRead3: begin
Done_o = 1'b0;
// consume and store third byte
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr0 = 1'b1;
SPI_FSM_NextState = stPause;
end
stPause: begin
SPI_FSM_NextState = stIdle;
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Byte-wide Memory /////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Byte0_o <= 8'd0;
Byte1_o <= 8'd0;
end
else
begin
if (SPI_FSM_Wr0)
begin
Byte0_o <= SPI_Data_i;
end
if (SPI_FSM_Wr1)
begin
Byte1_o <= SPI_Data_i;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [15:0] SPI_FSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SPI_FSM_Timer <= 16'd0;
end
else
begin
if (SPI_FSM_TimerPreset)
begin
SPI_FSM_Timer <= ParamCounterPreset_i;
end
else if (SPI_FSM_TimerEnable)
begin
SPI_FSM_Timer <= SPI_FSM_Timer - 1'b1;
end
end
end
assign SPI_FSM_TimerOvfl = (SPI_FSM_Timer == 0) ? 1'b1 : 1'b0;
endmodule // SPIFSM
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \$__QL_MUL20X18 (input [19:0] A, input [17:0] B, output [37:0] Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
wire [19:0] a;
wire [17:0] b;
wire [37:0] z;
assign a = (A_WIDTH == 20) ? A :
(A_SIGNED) ? {{(20 - A_WIDTH){A[A_WIDTH-1]}}, A} :
{{(20 - A_WIDTH){1'b0}}, A};
assign b = (B_WIDTH == 18) ? B :
(B_SIGNED) ? {{(18 - B_WIDTH){B[B_WIDTH-1]}}, B} :
{{(18 - B_WIDTH){1'b0}}, B};
dsp_t1_20x18x64 _TECHMAP_REPLACE_ (
.a_i (a),
.b_i (b),
.acc_fir_i (6'd0),
.z_o (z),
.feedback_i (3'd0),
.load_acc_i (1'b0),
.unsigned_a_i (!A_SIGNED),
.unsigned_b_i (!B_SIGNED),
.output_select_i (3'd0),
.saturate_enable_i (1'b0),
.shift_right_i (6'd0),
.round_i (1'b0),
.subtract_i (1'b0),
.register_inputs_i (1'b0)
);
assign Y = z;
endmodule
module \$__QL_MUL10X9 (input [9:0] A, input [8:0] B, output [18:0] Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
wire [ 9:0] a;
wire [ 8:0] b;
wire [18:0] z;
assign a = (A_WIDTH == 10) ? A :
(A_SIGNED) ? {{(10 - A_WIDTH){A[A_WIDTH-1]}}, A} :
{{(10 - A_WIDTH){1'b0}}, A};
assign b = (B_WIDTH == 9) ? B :
(B_SIGNED) ? {{( 9 - B_WIDTH){B[B_WIDTH-1]}}, B} :
{{( 9 - B_WIDTH){1'b0}}, B};
dsp_t1_10x9x32 _TECHMAP_REPLACE_ (
.a_i (a),
.b_i (b),
.acc_fir_i (6'd0),
.z_o (z),
.feedback_i (3'd0),
.load_acc_i (1'b0),
.unsigned_a_i (!A_SIGNED),
.unsigned_b_i (!B_SIGNED),
.output_select_i (3'd0),
.saturate_enable_i (1'b0),
.shift_right_i (6'd0),
.round_i (1'b0),
.subtract_i (1'b0),
.register_inputs_i (1'b0)
);
assign Y = z;
endmodule
|
#include <bits/stdc++.h> using namespace std; int inf_int = 1e9; long long inf_ll = 1e16; const double pi = 3.1415926535898; const int mod = 1e9 + 9; const int MAXN = 2e5 + 100; bool debug = false; char a[1005][1005]; char used[1005][1005][4][3]; int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; int n, m; inline bool is_ok(int x, int y, int d, int z) { return x >= 1 && x <= n && y >= 1 && y <= m && z <= 2 && a[x][y] != * && !used[x][y][d][z]; } void solve() { cin >> n >> m; int x1, y1; for (int i = 1; i <= n; ++i) { for (int e = 1; e <= m; ++e) { cin >> a[i][e]; if (a[i][e] == S ) { x1 = i; y1 = e; } } } queue<pair<pair<int, int>, pair<int, int> > > q; used[x1][y1][0][0] = 1; used[x1][y1][1][0] = 1; used[x1][y1][2][0] = 1; used[x1][y1][3][0] = 1; q.push({{x1, y1}, {0, 0}}); q.push({{x1, y1}, {1, 0}}); q.push({{x1, y1}, {2, 0}}); q.push({{x1, y1}, {3, 0}}); while (!q.empty()) { int x = q.front().first.first, y = q.front().first.second; int d = q.front().second.first, z = q.front().second.second; q.pop(); if (is_ok(x + dx[d], y + dy[d], d, z)) { q.push({{x + dx[d], y + dy[d]}, {d, z}}); used[x + dx[d]][y + dy[d]][d][z] = 1; } for (int i = 0; i < 4; ++i) { if (is_ok(x + dx[i], y + dy[i], i, z + 1)) { q.push({{x + dx[i], y + dy[i]}, {i, z + 1}}); used[x + dx[i]][y + dy[i]][i][z + 1] = 1; } } } for (int i = 1; i <= n; ++i) { for (int e = 1; e <= m; ++e) { if (a[i][e] == T ) { for (int j = 0; j < 4; ++j) { for (int f = 0; f <= 2; ++f) { if (used[i][e][j][f]) { cout << YES ; return; } } } } } } cout << NO ; } int main() { if (!debug) { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int t = 1; while (t--) solve(); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
`define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0)
module t (/*AUTOARG*/);
bit fail;
localparam signed [3:0] bug737_p1 = 4'b1000;
wire [3:0] bug737_a = 4'b1010;
reg [5:0] bug737_y;
reg signed [3:0] w4_s;
reg signed [4:0] w5_s;
reg [3:0] w4_u;
reg [4:0] w5_u;
reg signed [8:0] w9_s;
real r;
initial begin
// verilator lint_off WIDTH
bug737_y = bug737_a + (bug737_p1 + 4'sb0);
`checkh(bug737_y, 6'b010010); //bug737
// 6u +[6u] 4s +[6s] 6s
bug737_y = 6'b001010 + (4'sb1000 + 6'sb0);
`checkh(bug737_y, 6'b010010); //bug737, getx 000010
// 6u +[6u] 4s +[6s] 6s
bug737_y = 6'b001010 + (4'b1000 + 6'sb0);
`checkh(bug737_y, 6'b010010); //ok
bug737_y = 6'b001010 + (6'sb111000 + 6'sb0);
`checkh(bug737_y, 6'b000010); //ok
// v--- sign extends to 6-bits
bug737_y = 6'sb001010 + (4'sb1000 + 6'sb0);
`checkh(bug737_y, 6'b000010); //ok
// From t_math_signed_3
w4_s = 4'sb1111 - 1'b1;
`checkh(w4_s,33'he);
w4_s = 4'sb1111 - 5'b00001;
`checkh(w4_s,33'he);
w4_s = 4'sb1111 - 1'sb1;
`checkh(w4_s,4'h0);
w5_s = 4'sb1111 - 1'sb1;
`checkh(w5_s,4'h0);
w4_s = 4'sb1111 - 4'sb1111;
`checkh(w4_s,4'h0);
w5_s = 4'sb1111 - 4'sb1111;
`checkh(w5_s,5'h0);
// The assign LHS being signed or unsigned does not matter per IEEE
// The upper add being signed DOES matter propagating to lower
w4_s = 4'sb1111 - (1'sb1 + 4'b0); //1'sb1 not extended as unsigned add
`checkh(w4_s,4'he);
w4_s = 4'sb1111 - (1'sb1 + 4'sb0); //1'sb1 does sign extend
`checkh(w4_s,4'h0);
w4_s = 4'b1111 - (1'sb1 + 4'sb0); //1'sb1 does *NOT* sign extend
`checkh(w4_s,4'he); // BUG, Verilator says 'h0
w5_u = 4'b1111 + 4'b0001; // Extends to 5 bits due to LHS
`checkh(w5_u, 5'b10000);
w4_u = 4'b1111 + 4'b0001; // Normal case
`checkh(w4_u, 4'b0000);
// Another example of promotion, the add is 4 bits wide
w4_u = 3'b111 + 3'b010;
`checkh(w4_u, 4'b1001);
//
w4_u = 3'sb111 * 3'sb001; // Signed output, LHS does not matter
`checkh(w4_u, 4'sb1111);
w4_s = 3'sb111 * 3'sb001; // Signed output
`checkh(w4_s, 4'sb1111);
w4_s = 3'b111 * 3'sb001; // Unsigned output
`checkh(w4_s, 4'b0111);
// Conditionals get width from parent; are assignment-like
w4_u = 1'b0 ? 4'b0 : (2'b01+2'b11);
`checkh(w4_u, 4'b0100);
w4_u = 1'b0 ? 4'b0 : (6'b001000+6'b001000);
`checkh(w4_u, 4'b0000);
// If RHS is larger, that larger size is used
w4_u = 5'b10000 / 5'b00100;
`checkh(w4_u, 4'b0100);
// bug754
w5_u = 4'sb0010 << -2'sd1; // << 3
`ifdef VCS
`checkh(w5_u, 5'b00000); // VCS E-2014.03 bug
`else
`checkh(w5_u, 5'b10000); // VCS E-2014.03 bug
`endif
w5_u = 4'sb1000 << 0; // Sign extends
`checkh(w5_u, 5'b11000);
// Reals do not propagate to children
r = 1.0 + ( 1 + (1 / 2));
`checkf(r, 2.0);
// Self determined sign extension
r = $itor(3'sb111);
`checkf(r, -1.0);
// If any part of case is real, all is real
case (22)
22.0: ;
22.1: $stop;
default: $stop;
endcase
// bug759
w5_u = { -4'sd7 };
`checkh(w5_u, 5'b01001);
w5_u = {2{ -2'sd1 }};
`checkh(w5_u, 5'b01111);
// Don't break concats....
w5_u = {{0{1'b1}}, -4'sd7 };
`checkh(w5_u, 5'b01001);
w9_s = { -4'sd7, -4'sd7 };
`checkh(w9_s, 9'b010011001);
{w5_u, {w4_u}} = 9'b10101_1100;
`checkh(w5_u, 5'b10101);
`checkh(w4_u, 4'b1100);
{w4_u} = 4'b1011;
`checkh(w4_u, 4'b1011);
if (fail) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline string GetString() { char S[1000005]; scanf( %s , S); string ret = S; return ret; } inline char getc() { char c = ; while (c == || c == t || c == r || c == n ) c = getchar(); return c; } template <typename t> t getnum() { t res = 0; char c; int sign = 1; while (1) { c = getchar(); if (c == || c == n ) continue; else break; } if (c == + ) { } else if (c == - ) sign = -1; else res = c - 0 ; while (1) { c = getchar(); if (c >= 0 && c <= 9 ) res = res * 10 + c - 0 ; else break; } return res * sign; } int main(int argc, char** argv) { int n = getnum<int>(); int m = getnum<int>(); int i = getnum<int>(); int j = getnum<int>(); int a = getnum<int>(); int b = getnum<int>(); int satu = 10000000, dua = 10000000, tiga = 10000000, empat = 10000000; if ((i - 1) % a == 0 && (j - 1) % b == 0) { int x = (i - 1) / a, y = (j - 1) / b; if (x % 2 == y % 2) satu = max(x, y); } if ((i - 1) % a == 0 && (m - j) % b == 0) { int x = (i - 1) / a, y = (m - j) / b; if (x % 2 == y % 2) dua = max(x, y); } if ((n - i) % a == 0 && (j - 1) % b == 0) { int x = (n - i) / a, y = (j - 1) / b; if (x % 2 == y % 2) tiga = max(x, y); } if ((n - i) % a == 0 && (m - j) % b == 0) { int x = (n - i) / a, y = (m - j) / b; if (x % 2 == y % 2) empat = max(x, y); } int ans = min(satu, min(dua, min(tiga, empat))); if (ans != 0 && (a > n - 1 || b > m - 1)) ans = 10000000; if (ans == 10000000) puts( Poor Inna and pony! ); else printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; struct people { long long a, b, id; } p[300010]; long long n, s[300010], t; bool v[300010], ans[300010]; bool cmp(people a, people b) { return a.a == b.a ? a.b > b.b : a.a > b.a; } long double check(people a, people b) { return (long double)a.a * b.a * (b.b - a.b) / (b.a - a.a) / b.b / a.b; } int main() { scanf( %lld , &n); for (int i = 1; i <= n; i++) scanf( %lld%lld , &p[i].a, &p[i].b), p[i].id = i; sort(p + 1, p + n + 1, cmp); s[1] = 1, t = 1; long long maxb = p[1].b; for (int i = 2; i <= n; i++) if (p[i].b <= maxb) v[i] = 1; else maxb = p[i].b; for (int i = 2; i <= n; i++) { if (v[i] || check(p[i], p[s[t]]) > 0) continue; while (t > 1 && check(p[i], p[s[t]]) < check(p[s[t - 1]], p[s[t]])) t--; s[++t] = i; } for (int i = 1; i <= t; i++) { ans[p[s[i]].id] = 1; for (int j = s[i] + 1; j <= n && p[s[i]].a == p[j].a && p[s[i]].b == p[j].b; j++) ans[p[j].id] = 1; } for (int i = 1; i <= n; i++) if (ans[i]) printf( %d , i); return 0; } |
`timescale 1ns / 100ps
/* The GPIA bit input mux is used when a processing element reads from I/O
* space. Some bits may be configured to sample actual signals outside the
* GPIA ("inputs"). Some pins will be configured to drive signals outside the
* GPIA ("outputs"). If a particular I/O bit is configured as an output, we
* want to read back the last value we wrote to it. Otherwise, we want to
* read the current state of the external signal attached to it.
*/
module test();
reg out_o;
reg inp_o;
reg ddr_o;
reg stb_o;
wire q_i;
/* We have a clock, but the mux doesn't use it. I use it for test
* synchronization only.
*/
reg clk_o;
/* Scenario tag for knowing which test is running when viewing waveforms. */
reg [7:0] scenario_o;
/* Device Under Test */
GPIA_BIT_IN dut (
.out_i(out_o),
.inp_i(inp_o),
.ddr_i(ddr_o),
.stb_i(stb_o),
.q_o(q_i)
);
always begin
#20 clk_o <= ~clk_o;
end
task waitclk;
begin @(negedge clk_o); @(posedge clk_o);
end
endtask
/* The scenario tests commence here. */
initial begin
scenario_o <= 8'h00;
out_o <= 0;
inp_o <= 0;
ddr_o <= 0;
stb_o <= 0;
clk_o <= 0;
$dumpfile("test.vcd");
$dumpvars;
/* With stb_o low, we expect a zero result, regardless of the state
* of the inputs. This allows an implementation to logically-OR
* buses together.
*/
@(posedge clk_o);
scenario_o <= 8'h10;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h14;
out_o <= 1;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h18;
inp_o <= 1;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h1C;
out_o <= 0;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
/* With stb_o high, we expect actual results, according to the
* current value of ddr_o.
*
* We first exercise the circuit with DDR set to 0 (input).
*/
@(posedge clk_o);
scenario_o <= 8'h20;
stb_o <= 1;
inp_o <= 0;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h24;
out_o <= 1;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h28;
inp_o <= 1;
waitclk;
#2 if(q_i != 1) begin
$display("FAIL %x: Q not 1", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h2C;
out_o <= 0;
waitclk;
#2 if(q_i != 1) begin
$display("FAIL %x: Q not 1", scenario_o); $finish;
end
/* Next, we set the DDR to 1 (output), so Q should track
* out_o instead of inp_o.
*/
@(posedge clk_o);
scenario_o <= 8'h30;
stb_o <= 1;
ddr_o <= 1;
inp_o <= 0;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h34;
out_o <= 1;
waitclk;
#2 if(q_i != 1) begin
$display("FAIL %x: Q not 1", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h38;
inp_o <= 1;
waitclk;
#2 if(q_i != 1) begin
$display("FAIL %x: Q not 1", scenario_o); $finish;
end
@(posedge clk_o);
scenario_o <= 8'h3C;
out_o <= 0;
waitclk;
#2 if(q_i != 0) begin
$display("FAIL %x: Q not 0", scenario_o); $finish;
end
$display("PASS"); $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename _T> inline void read(_T &dig) { int flg; char c; flg = dig = 0; while (c = getchar(), !isdigit(c)) if (c == - ) flg = 1; while (isdigit(c)) dig = dig * 10 + c - 0 , c = getchar(); if (flg) dig = -dig; } template <typename _T, typename... Args> inline void read(_T &x, Args &...args) { read(x); read(args...); } const int N = 505, M = 1e5 + 5; int n, f[N][N], a[N]; int head[M], nxt[M], tot, ver[M], v[N], in[N]; queue<int> q; void add(int u, int v) { nxt[++tot] = head[u], head[u] = tot, ver[tot] = v; } int main() { read(n); for (int i = (1); i <= (n); ++i) read(a[i]), f[i][i] = a[i]; for (int k = 2; k <= n; ++k) for (int i = 1; i + k - 1 <= n; ++i) for (int j = i; j < i + k - 1; ++j) if (f[i][j] && f[i][j] == f[j + 1][i + k - 1]) { f[i][i + k - 1] = f[i][j] + 1; break; } for (int i = 1; i <= n; ++i) for (int j = i; j <= n; ++j) if (f[i][j]) add(i, j + 1); memset(v, 0x3f, sizeof(v)); v[1] = 0, q.push(1); int x, y; while (q.size()) { x = q.front(), q.pop(), in[x] = 0; for (int i = head[x]; i; i = nxt[i]) { if (v[y = ver[i]] > v[x] + 1) { v[y] = v[x] + 1; if (!in[y]) q.push(y), in[y] = 1; } } } printf( %d n , v[n + 1]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 100100; const long long oo = 1e18; int N; long long P[MAX], D[MAX]; int L[MAX], R[MAX]; void init_L() { stack<int> S; for (int i = 0; i <= N + 1; ++i) { while (S.size() >= 2) { int x = S.top(); S.pop(); if (D[x] >= P[i] - P[S.top()]) { S.push(x); break; } } if (!S.empty()) L[i] = S.top(); S.push(i); } } void init_R() { stack<int> S; for (int i = N + 1; i >= 0; --i) { while (S.size() >= 2) { int x = S.top(); S.pop(); if (D[x] >= P[S.top()] - P[i]) { S.push(x); break; } } if (!S.empty()) R[i] = S.top(); S.push(i); } } long long low(int x) { if (x == N + 1) return -1e10; long long ret = P[R[x]] - D[x]; return ret < P[x] ? ret : +oo; } long long high(int x) { if (x == 0) return +1e10; long long ret = P[L[x]] + D[x]; return ret > P[x] ? ret : -oo; } bool check(long long W) { multiset<long long> S; for (int a = 0, b = 0; a <= N; ++a) { for (; b <= N + 1 && P[b] - P[a] <= W; ++b) S.insert(low(b)); S.erase(S.find(low(a))); if (!S.empty() && high(a) >= *S.begin()) return true; } return false; } int main() { scanf( %d , &N); for (int i = 0; i <= N + 1; ++i) scanf( %lld , P + i); for (int i = 1; i <= N; ++i) scanf( %lld , D + i), D[i] *= 2; D[0] = D[N + 1] = oo; init_L(); init_R(); if (R[0] != N + 1) { puts( 0 ); return 0; } long long lo = 1, hi = 1e10; while (lo < hi) { long long mid = (lo + hi) / 2; check(mid) ? hi = mid : lo = mid + 1; } printf( %.1lf n , lo / 2.0); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, ans, x, mn = 100001; vector<int> A, B; map<int, int> Ps1, Ps2, Mn; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> x; Ps1[x] = i; } for (int i = 0; i < n; i++) { cin >> x; Ps2[i] = Ps1[x]; } for (int i = n - 1; i >= 0; i--) { mn = min(mn, Ps2[i]); Mn[i] = mn; } for (int i = 0; i < n; i++) { if (Ps2[i] > Mn[i]) ans++; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; template <typename T> class FenwickTree { private: vector<T> bit; int M; public: FenwickTree(int M) : bit(vector<T>(M + 1, 0)), M(M) {} int sum(int i) { if (!i) return 0; return bit[i] + sum(i - (i & -i)); } void add(int i, T x) { if (i > M) return; bit[i] += x; add(i + (i & -i), x); } }; int main() { ios::sync_with_stdio(false); int N; cin >> N; vector<int> X1(N), X2(N), Y1(N), Y2(N); map<int, int> Yc; set<int> Ys; vector<int> YI; map<int, vector<int>> Ha, He; map<int, vector<pair<int, int>>> V, H; set<int> cand; YI.push_back(-1 << 30); for (int i = 0; i < N; ++i) { int x1, x2, y1, y2; cin >> x1 >> y1 >> x2 >> y2; if (x2 < x1) swap(x1, x2); if (y2 < y1) swap(y1, y2); YI.push_back(y1 - 1); YI.push_back(y1); YI.push_back(y1 + 1); YI.push_back(y2 - 1); YI.push_back(y2); YI.push_back(y2 + 1); X1[i] = x1, X2[i] = x2, Y1[i] = y1, Y2[i] = y2; } sort((YI.begin()), (YI.end())); YI.erase(unique(YI.begin(), YI.end()), YI.end()); for (int i = 0; i < N; ++i) { Y1[i] = lower_bound((YI.begin()), (YI.end()), Y1[i]) - YI.begin(); Y2[i] = lower_bound((YI.begin()), (YI.end()), Y2[i]) - YI.begin(); if (X1[i] == X2[i]) { V[X1[i]].push_back({Y1[i], Y2[i]}); cand.insert(X1[i]); } else { Ha[X1[i]].push_back(Y1[i]); He[X2[i]].push_back(Y1[i]); H[Y1[i]].push_back({X1[i], X2[i]}); cand.insert(X1[i]); cand.insert(X2[i]); } } FenwickTree<signed long long> bt(YI.size()); signed long long ret = 0; for (auto cx : cand) { for (auto y : Ha[cx]) if (Yc[y]++ == 0) bt.add(y, 1); if (V.count(cx)) { vector<pair<int, int>>& T = V[cx]; sort((T.begin()), (T.end())); int ma = -1 << 30; for (auto r : T) { r.first = max(r.first, ma + 1); if (r.first > r.second) continue; ret += YI[r.second] - YI[r.first] + 1; ret -= bt.sum(r.second) - bt.sum(r.first - 1); ma = r.second; } } for (auto y : He[cx]) if (--Yc[y] == 0) bt.add(y, -1); } for (auto hy : H) { vector<pair<int, int>>& T = hy.second; sort((T.begin()), (T.end())); int ma = -1 << 30; for (auto r : T) { r.first = max(r.first, ma + 1); if (r.first > r.second) continue; ret += r.second - r.first + 1; ma = r.second; } } cout << ret << endl; } |
#include <bits/stdc++.h> using namespace std; vector<int> a, k; int fun(int x) { int c = 0; for (auto y : a) if (y <= x) c++; for (auto y : k) { if (y > 0 && y <= x) c++; if (y < 0 && -y <= c) c--; } return c; } int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); srand(time(NULL)); ; int T = 1; cin >> T; while (T--) { int n; cin >> n; cout << setprecision(10) << 1 / (2 * sin(3.141592653589793238 / (4 * n))); cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int f, x; cin >> f; x = f + 1; if (f == 0) { f = 0; } else if (x % 2 == 0) { f = x / 2; } else { f++; } cout << f << endl; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:37:41 08/26/2015
// Design Name: DecoBCDto7seg
// Module Name: /home/manzumbado/Development/HDL/Xilinx/ControladorElevadorTDD/trunk/DecoGreytoBCD.v
// Project Name: ControladorElevadorTDD
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: DecoBCDto7seg
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
//Decodificador que convierte código grey de 3 bits en código binario
module DecoGreytoBCD(
entradas_i, //3 bits de entrada
salidas_o //3 bits de salida
);
input [2:0] entradas_i;
output [2:0] salidas_o;
//wire entradas_i;
//wire salidas_o;
//Aqui se hace la transformación
assign salidas_o[2] = entradas_i[2];
xor xorB(salidas_o[1], entradas_i[2], entradas_i[1]);
xor xorC(salidas_o[0], salidas_o[1], entradas_i[0]);
endmodule
|
// Polyphase filter bank for upsampling from 48000.0kHz to 96000.0kHz
// Depth: 32
module rom_firbank_48_96(
input wire clk,
input wire [4:0] addr,
output wire [23:0] data);
reg [23:0] data_ff;
assign data = data_ff;
always @(posedge clk) begin
case(addr)
0: data_ff <= 24'h164B2D; //
1: data_ff <= 24'hF5BAE8; // -673048
2: data_ff <= 24'h0633AB; // 406443
3: data_ff <= 24'hFC29F9; // -251399
4: data_ff <= 24'h0242A4; // 148132
5: data_ff <= 24'hFEC9C7; // -79417
6: data_ff <= 24'h008EDD; // 36573
7: data_ff <= 24'hFFCE7B; // -12677
8: data_ff <= 24'h0005BB; // 1467
9: data_ff <= 24'h00091C; // 2332
10: data_ff <= 24'hFFF5DC; // -2596
11: data_ff <= 24'h0006AF; // 1711
12: data_ff <= 24'hFFFCC4; // -828
13: data_ff <= 24'h000124; // 292
14: data_ff <= 24'hFFFFC3; // -61
15: data_ff <= 24'h000004; // 4
16: data_ff <= 24'h35A6A3; //
17: data_ff <= 24'hF90C13; // -455661
18: data_ff <= 24'h01922A; // 102954
19: data_ff <= 24'h005211; // 21009
20: data_ff <= 24'hFEFDCB; // -66101
21: data_ff <= 24'h011F4C; // 73548
22: data_ff <= 24'hFF0A15; // -62955
23: data_ff <= 24'h00B389; // 45961
24: data_ff <= 24'hFF8D35; // -29387
25: data_ff <= 24'h00406C; // 16492
26: data_ff <= 24'hFFE0A7; // -8025
27: data_ff <= 24'h000CDE; // 3294
28: data_ff <= 24'hFFFBC5; // -1083
29: data_ff <= 24'h0000FE; // 254
30: data_ff <= 24'hFFFFE3; // -29
31: data_ff <= 24'hFFFFFF; // -1
default: data_ff <= 0;
endcase
end
endmodule
|
#include <cstdio> #include <cassert> #include <utility> #include <functional> #define X first #define Y second const int mod = 998244353; template<int k> struct node{ node <k-1>* chd[2]; int cnt; int lazy; int has[2]; int get_cnt(){ assert(this!=NULL); return cnt; } int get_has(int d){ assert(this!=NULL); push(); assert(has[d]<(1<<(k+1))); return has[d]; } node():chd{NULL, NULL}, has{0, 0}, cnt(0),lazy(0){}; node(node<k-1>* l,node <k-1>* r):chd{l,r},cnt(0),lazy(0),has{0,0}{ if(l){ cnt+=l->get_cnt(); has[0]|=l->get_has(0)|(1<<k); has[1]|=l->get_has(1); } if(r){ cnt+=r->get_cnt(); has[0]|=r->get_has(0); has[1]|=r->get_has(1)|(1<<k); } assert(has[0]<(1<<(k+1))); assert(has[1]<(1<<(k+1))); } void push(){ assert(lazy<(1<<(k+1))); if(!lazy) return; if(lazy&(1<<k)){ std::swap(chd[0],chd[1]); if((has[0]^has[1])&(1<<k)){ has[0]^=(1<<k); has[1]^=(1<<k); } lazy^=(1<<k); } int flip=(has[0]^has[1])&lazy; has[0]^=flip; has[1]^=flip; if(chd[0]) chd[0]->lazy^=lazy; if(chd[1]) chd[1]->lazy^=lazy; lazy=0; assert(has[0]<(1<<(k+1))); assert(has[1]<(1<<(k+1))); } }; template<> struct node<-1>{ int lazy; node():lazy(0){ } int get_cnt(){ assert(this!=NULL); return 1; } int get_has(int d){ assert(this!=NULL); return 0; } }; template<int k> node<k>* create(int x){ if(x&(1<<k)){ return new node<k>(NULL,create<k-1>(x)); }else{ return new node<k>(create<k-1>(x),NULL); } } template<> node<-1>*create(int x) { return new node<-1>(); } template<int k> std::pair <node<k - 1>*, node< k - 1>*> destruct(node <k>*a) { assert(a!=NULL); a -> push(); auto res = std::make_pair(a -> chd[0], a -> chd[1]); delete a; return res; } template <int k> node <k>* join(node<k -1>* l, node <k - 1>* r) { if(l == NULL && r == NULL) { return NULL; } return new node<k>(l, r); } template<int k> node<k>* merge(node<k> *a, node<k> *b) { if(!a) { return b; } if(!b) { return a; } auto aa = destruct(a); auto bb = destruct(b); node <k - 1> *l = merge<k - 1>(aa.X, bb.X); node <k - 1> *r = merge<k - 1>(aa.Y, bb.Y); return join<k>(l, r); } template<>node<-1>* merge(node<-1>*a, node<-1>* b) { if(!a) { return b; } if(!b) { return a; } delete b; return a; } template<int k> std::pair<node<k>*,node<k>*> split(node<k>* a,int thres){ if(a==NULL){ return {NULL,NULL}; } if(thres<=0) return {NULL,a}; if(thres>=(1<<(k+1))) return {a,NULL}; assert(k>=0); auto aa =destruct(a); if(thres<(1<<k)){ node<k-1>* l,*r; std::tie(l,r)=split<k-1>(aa.first,thres); return std::make_pair(join<k>(l,NULL),join<k>(r,aa.second)); }else if(thres>(1<<k)){ node<k-1>* l,*r; std::tie(l,r)=split<k-1>(aa.second, thres-(1<<k)); return std::make_pair(join<k>(aa.first,l),join<k>(NULL,r)); }else{ return std::make_pair(join<k>(aa.first,NULL),join<k>(NULL,aa.second)); } } template<> std::pair<node<-1>*,node<-1>*> split<-1>(node<-1>* a,int thres){ assert(0); } template<int k> node<k>* update(node<k> *a, int val) { if(a == NULL) return NULL; a -> push(); assert(val<(1<<(k+1))); if((val & a -> has[0] & a -> has[1]) == 0) { a -> lazy ^= (val & a ->has[0]); return a; } node<k - 1>*l, *r; std::tie(l, r) = destruct(a); l = update<k - 1>(l, val & ~(1 << k)); r = update<k - 1>(r, val & ~(1 << k)); if(val & (1 << k)) { return join<k>(NULL, merge<k - 1>(l, r)); } else { return join<k>(l, r); } } template<>node<-1>*update(node<-1>*a, int val) { return a; } int main() { // ifstream cin( input1.txt.4c ); // ios_base::sync_with_stdio(0); // cin.tie(0); //cout.tie(0); node<19>* root = NULL; int n, q; //cin >> n >> q; scanf( %d %d , &n, &q); // printf( A n ); for(int i = 0; i< n; i++) { int a; scanf( %d , &a); // root = create<19> (a); root = merge(root, create<19>(a)); } while(q--) { int t, l, r; scanf( %d%d%d , &t, &l, &r); node<19>*left, *right; std::tie(left, root) = split(root, l); std::tie(root, right) = split(root, r + 1); if(t == 4) { if(root) { printf( %d n , root -> cnt); // return 0; } else { printf( 0 n ); //return 0; } } else { int x; scanf( %d , &x); if(root != NULL) { if(t == 1) { root -> lazy ^= ((1 << 20) - 1); root = update(root, x ^ ((1 << 20) - 1)); root -> lazy ^= ((1 << 20) - 1); } else if(t == 2) { root = update(root, x); } else { root -> lazy ^=x; } } } root = merge(root, left); root = merge(root, right); } return 0; } |
// DeBounce_v.v
//////////////////////// Button Debounceer ///////////////////////////////////////
//***********************************************************************
// FileName: DeBounce_v.v
// FPGA: MachXO2 7000HE
// IDE: Diamond 2.0.1
//
// HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
// WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
// PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
// BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
// DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
// PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
// BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
// ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
// DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
// INFRINGEMENT.
//
// Version History
// Version 1.0 04/11/2013 Tony Storey
// Initial Public Release
// Small Footprint Button Debouncer
`timescale 1 ns / 100 ps
module DeBounce
(
input clk, n_reset, button_in, // inputs
output reg DB_out // output
);
//// ---------------- internal constants --------------
parameter N = 11 ; // (2^ (21-1) )/ 38 MHz = 32 ms debounce time
////---------------- internal variables ---------------
reg [N-1 : 0] q_reg; // timing regs
reg [N-1 : 0] q_next;
reg DFF1, DFF2; // input flip-flops
wire q_add; // control flags
wire q_reset;
//// ------------------------------------------------------
////contenious assignment for counter control
assign q_reset = (DFF1 ^ DFF2); // xor input flip flops to look for level chage to reset counter
assign q_add = ~(q_reg[N-1]); // add to counter when q_reg msb is equal to 0
//// combo counter to manage q_next
always @ ( q_reset, q_add, q_reg)
begin
case( {q_reset , q_add})
2'b00 :
q_next <= q_reg;
2'b01 :
q_next <= q_reg + 1;
default :
q_next <= { N {1'b0} };
endcase
end
//// Flip flop inputs and q_reg update
always @ ( posedge clk )
begin
if(n_reset == 1'b0)
begin
DFF1 <= 1'b0;
DFF2 <= 1'b0;
q_reg <= { N {1'b0} };
end
else
begin
DFF1 <= button_in;
DFF2 <= DFF1;
q_reg <= q_next;
end
end
//// counter control
always @ ( posedge clk )
begin
if(q_reg[N-1] == 1'b1)
DB_out <= DFF2;
else
DB_out <= DB_out;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1010; int n, a[N], ans; bool vis[N]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); int now = 1, dir = 0, tot = 0; while (tot < n) { if (dir == 0) { for (int i = now; i <= n; i++) if (!vis[i] && tot >= a[i]) { vis[i] = 1; tot++; } now = n; dir = 1; if (tot < n) ans++; } else { for (int i = now; i >= 1; i--) if (!vis[i] && tot >= a[i]) { vis[i] = 1; tot++; } now = 1; dir = 0; if (tot < n) ans++; } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<vector<int> > graph; vector<int> AL; vector<int> visited; void dfs(int u) { visited[u] = 1; for (auto v : graph[u]) { if (!visited[v]) { dfs(v); } } } int main() { ios::sync_with_stdio(false); cin.tie(NULL); int tc; cin >> tc; while (tc--) { int n; cin >> n; string a, b; cin >> a >> b; AL.assign(20, 0); graph.assign(20, vector<int>()); visited.assign(20, 0); for (int i = 0; i < n; i++) { if (a[i] != b[i]) { AL[a[i] - a ] |= 1 << (b[i] - a ); graph[a[i] - a ].push_back(b[i] - a ); graph[b[i] - a ].push_back(a[i] - a ); } } int numCC = 0; for (int i = 0; i < 20; i++) { if (!visited[i]) { dfs(i); numCC++; } } int ans = 0; vector<bool> c(1 << 20); c[0] = true; for (int mask = 0; mask < (1 << 20); mask++) { if (c[mask]) { ans = max(ans, __builtin_popcount(mask)); for (int i = 0; i < 20; i++) { if (((~mask >> i) & 1) && (AL[i] & mask) == 0) { c[mask | (1 << i)] = true; } } } } cout << 2 * 20 - ans - numCC << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int arr[100000]; int pre[100000]; int leftMax; int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); ; int t; cin >> t; while (t--) { int maxLen = 0; int n, x; cin >> n >> x; for (int i = 0; i < n; i++) cin >> arr[i]; pre[0] = arr[0]; for (int i = 1; i < n; i++) pre[i] = arr[i] + pre[i - 1]; leftMax = -1; for (int i = 0; i < n; i++) { pre[i] = pre[i] % x; if (pre[i] != 0) maxLen = i + 1; if (pre[i] != 0 && leftMax == -1) leftMax = i; } if (maxLen == 0) cout << -1 n ; else { int finalLen = maxLen; for (int i = 0; i < n; i++) { if (pre[i] == 0) finalLen = max(finalLen, max(abs(i - leftMax), abs(i - maxLen))); } cout << finalLen << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MX = (1 << 20); class Disjoint_Set { public: int sz[MX], P[MX]; int find_(int x) { if (x != P[x]) P[x] = find_(P[x]); return P[x]; } int comp; void init(int N) { for (int j = 1; j <= N; j++) sz[j] = 1, P[j] = j; comp = N; } bool same(int x, int y) { return find_(x) == find_(y); } int compsize(int node) { return sz[find_(node)]; } bool merge_(int x, int y) { int px = find_(x), py = find_(y); if (px == py) return false; if (sz[px] < sz[py]) swap(px, py); P[py] = px; comp--; sz[px] += sz[py]; return true; } } G; int n, m; int main() { scanf( %d %d , &n, &m); if (n != m) { puts( NO ); return 0; } G.init(n); int tt = 0; while (m--) { int a, b; scanf( %d %d , &a, &b); if (!G.merge_(a, b)) tt++; } if (tt == 1) puts( FHTAGN! ); else puts( NO ); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// verilator lint_off MULTIDRIVEN
wire [31:0] outb0c0;
wire [31:0] outb0c1;
wire [31:0] outb1c0;
wire [31:0] outb1c1;
reg [7:0] lclmem [7:0];
ma ma0 (.outb0c0(outb0c0), .outb0c1(outb0c1),
.outb1c0(outb1c0), .outb1c1(outb1c1)
);
global_mod #(32'hf00d) global_cell ();
global_mod #(32'hf22d) global_cell2 ();
input clk;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1);
`endif
if (cyc==2) begin
if (global_cell.globali != 32'hf00d) $stop;
if (global_cell2.globali != 32'hf22d) $stop;
if (outb0c0 != 32'h00) $stop;
if (outb0c1 != 32'h01) $stop;
if (outb1c0 != 32'h10) $stop;
if (outb1c1 != 32'h11) $stop;
end
if (cyc==3) begin
// Can we scope down and read and write vars?
ma0.mb0.mc0.out <= ma0.mb0.mc0.out + 32'h100;
ma0.mb0.mc1.out <= ma0.mb0.mc1.out + 32'h100;
ma0.mb1.mc0.out <= ma0.mb1.mc0.out + 32'h100;
ma0.mb1.mc1.out <= ma0.mb1.mc1.out + 32'h100;
end
if (cyc==4) begin
// Can we do dotted's inside array sels?
ma0.rmtmem[ma0.mb0.mc0.out[2:0]] = 8'h12;
lclmem[ma0.mb0.mc0.out[2:0]] = 8'h24;
if (outb0c0 != 32'h100) $stop;
if (outb0c1 != 32'h101) $stop;
if (outb1c0 != 32'h110) $stop;
if (outb1c1 != 32'h111) $stop;
end
if (cyc==5) begin
if (ma0.rmtmem[ma0.mb0.mc0.out[2:0]] != 8'h12) $stop;
if (lclmem[ma0.mb0.mc0.out[2:0]] != 8'h24) $stop;
if (outb0c0 != 32'h1100) $stop;
if (outb0c1 != 32'h2101) $stop;
if (outb1c0 != 32'h2110) $stop;
if (outb1c1 != 32'h3111) $stop;
end
if (cyc==6) begin
if (outb0c0 != 32'h31100) $stop;
if (outb0c1 != 32'h02101) $stop;
if (outb1c0 != 32'h42110) $stop;
if (outb1c1 != 32'h03111) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef USE_INLINE_MID
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator no_inline_module*/
`else
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`define INLINE_MID_MODULE /*verilator public_module*/
`endif
`endif
module global_mod;
`INLINE_MODULE
parameter INITVAL = 0;
integer globali;
initial globali = INITVAL;
endmodule
module ma (
output wire [31:0] outb0c0,
output wire [31:0] outb0c1,
output wire [31:0] outb1c0,
output wire [31:0] outb1c1
);
`INLINE_MODULE
reg [7:0] rmtmem [7:0];
mb #(0) mb0 (.outc0(outb0c0), .outc1(outb0c1));
mb #(1) mb1 (.outc0(outb1c0), .outc1(outb1c1));
endmodule
module mb (
output wire [31:0] outc0,
output wire [31:0] outc1
);
`INLINE_MID_MODULE
parameter P2 = 0;
mc #(P2,0) mc0 (.out(outc0));
mc #(P2,1) mc1 (.out(outc1));
global_mod #(32'hf33d) global_cell2 ();
wire reach_up_clk = t.clk;
always @(reach_up_clk) begin
if (P2==0) begin // Only for mb0
if (outc0 !== t.ma0.mb0.mc0.out) $stop; // Top module name and lower instances
if (outc0 !== ma0.mb0.mc0.out) $stop; // Upper module name and lower instances
if (outc0 !== ma .mb0.mc0.out) $stop; // Upper module name and lower instances
if (outc0 !== mb.mc0.out) $stop; // This module name and lower instances
if (outc0 !== mb0.mc0.out) $stop; // Upper instance name and lower instances
if (outc0 !== mc0.out) $stop; // Lower instances
if (outc1 !== t.ma0.mb0.mc1.out) $stop; // Top module name and lower instances
if (outc1 !== ma0.mb0.mc1.out) $stop; // Upper module name and lower instances
if (outc1 !== ma .mb0.mc1.out) $stop; // Upper module name and lower instances
if (outc1 !== mb.mc1.out) $stop; // This module name and lower instances
if (outc1 !== mb0.mc1.out) $stop; // Upper instance name and lower instances
if (outc1 !== mc1.out) $stop; // Lower instances
end
end
endmodule
module mc (output reg [31:0] out);
`INLINE_MODULE
parameter P2 = 0;
parameter P3 = 0;
initial begin
out = {24'h0,P2[3:0],P3[3:0]};
//$write("%m P2=%0x p3=%0x out=%x\n",P2, P3, out);
end
// Can we look from the top module name down?
wire [31:0] reach_up_cyc = t.cyc;
always @ (posedge t.clk) begin
//$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc);
if (reach_up_cyc==2) begin
if (global_cell.globali != 32'hf00d) $stop;
if (global_cell2.globali != 32'hf33d) $stop;
end
if (reach_up_cyc==4) begin
out[15:12] <= {P2[3:0]+P3[3:0]+4'd1};
end
if (reach_up_cyc==5) begin
// Can we set another instance?
if (P3==1) begin // Without this, there are two possible correct answers...
mc0.out[19:16] <= {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2};
$display("%m Set %x->%x %x %x %x %x",mc0.out, {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}, mc0.out[19:16],P2[3:0],P3[3:0],4'd2);
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; set<int> fang[400001]; map<int, int> cishu[400001]; int n, m, q, to1[400001], Nxt[400001], first1[400001], dfn[400001], low[400001]; int to[500001], nxt[500001], first[500001], cnt, e1, x2, fa[400001]; int sum, tot = 0, ss[400001], heavy[400001], siz[400001], seg[1000001]; int pos[400001], top[400001], deep[400001], h = 0, Stack[400001 * 10]; char ch; void Build(int x, int y) { to1[cnt] = y; Nxt[cnt] = first1[x]; first1[x] = cnt++; } void insert(int x, int y) { to[e1] = y; nxt[e1] = first[x]; first[x] = e1++; } void tarjan(int x) { dfn[x] = low[x] = ++tot; Stack[++h] = x; for (int i = first1[x]; i != -1; i = Nxt[i]) if (!dfn[to1[i]]) { tarjan(to1[i]); low[x] = min(low[x], low[to1[i]]); if (dfn[x] <= low[to1[i]]) { int z; sum++; do { z = Stack[h--]; insert(sum, z); insert(z, sum); } while (z != to1[i]); insert(sum, x); insert(x, sum); } } else low[x] = min(low[x], dfn[to1[i]]); } void dfs(int o, int p) { siz[o] = 1; deep[o] = deep[p] + 1; fa[o] = p; for (int i = first[o]; i != -1; i = nxt[i]) if (to[i] != p) { dfs(to[i], o); siz[o] += siz[to[i]]; if (siz[to[i]] > siz[heavy[o]]) heavy[o] = to[i]; } } void dfs1(int o, int p) { pos[o] = ++x2; if (heavy[o] > 0) { top[heavy[o]] = top[o]; dfs1(heavy[o], o); for (int i = first[o]; i != -1; i = nxt[i]) if ((to[i] != p) && (to[i] != heavy[o])) { top[to[i]] = to[i]; dfs1(to[i], o); } } } void put(int o, int p, int q, int r, int s) { if ((o == q) && (p == q)) { seg[r] = s; return; } int mid = (o + p) / 2; if (q <= mid) { put(o, mid, q, r * 2, s); seg[r] = min(seg[r * 2 + 1], seg[r * 2]); } else { put(mid + 1, p, q, r * 2 + 1, s); seg[r] = min(seg[r * 2], seg[r * 2 + 1]); } } int get(int o, int p, int q, int r, int s) { if ((o == q) && (p == r)) return seg[s]; int mid = (o + p) / 2; if (r <= mid) return get(o, mid, q, r, s * 2); else if (q > mid) return get(mid + 1, p, q, r, s * 2 + 1); else return min(get(o, mid, q, mid, s * 2), get(mid + 1, p, mid + 1, r, s * 2 + 1)); } int gettree(int o, int p) { int yu = INF; while (top[o] != top[p]) { if (deep[top[o]] < deep[top[p]]) { int t = o; o = p; p = t; } yu = min(yu, get(1, sum, pos[top[o]], pos[o], 1)); o = fa[top[o]]; } if (deep[o] > deep[p]) { int t = o; o = p; p = t; } yu = min(yu, get(1, sum, pos[o], pos[p], 1)); if (o > n) yu = min(yu, ss[fa[o]]); return yu; } int main() { memset(first1, -1, sizeof(first1)); memset(first, -1, sizeof(first)); scanf( %d%d%d , &n, &m, &q); sum = n; for (int i = 1; i <= n; i++) scanf( %d , &ss[i]); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); Build(x, y); Build(y, x); } for (int i = 1; i <= n; i++) if (!dfn[i]) tarjan(i); deep[0] = 0; dfs(1, 0); top[1] = 1; dfs1(1, 0); for (int i = 1; i <= n; i++) if (fa[i] > 0) { fang[fa[i]].insert(ss[i]); if (!cishu[fa[i]].count(ss[i])) cishu[fa[i]][ss[i]] = 0; cishu[fa[i]][ss[i]]++; } for (int i = n + 1; i <= sum; i++) ss[i] = *fang[i].begin(); for (int i = 0; i <= 1000000; i++) seg[i] = INF + 1; for (int i = 1; i <= sum; i++) put(1, sum, pos[i], 1, ss[i]); for (int i = 1; i <= q; i++) { int x, y; getchar(); scanf( %c%d%d , &ch, &x, &y); if (ch == C ) { if (fa[x] > 0) { cishu[fa[x]][ss[x]]--; if (cishu[fa[x]][ss[x]] == 0) fang[fa[x]].erase(ss[x]); if (!cishu[fa[x]].count(y)) cishu[fa[x]][y] = 0; cishu[fa[x]][y]++; fang[fa[x]].insert(y); put(1, sum, pos[fa[x]], 1, (*fang[fa[x]].begin())); } put(1, sum, pos[x], 1, y); ss[x] = y; } else cout << gettree(x, y) << endl; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:33:05 12/07/2015
// Design Name:
// Module Name: Peripheral_clk_interruptor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Peripheral_clk_interruptor(
input clk,
input rst,
input [15:0] d_in,
input cs,
input [3:0] addr,
input rd,
input wr,
output reg [15:0] d_out
);
//--------------------------------------
reg [5:0] s; //selector mux_4 and write registers
reg [31:0] limit;
reg [31:0] count;
reg en=0;
wire int_0;
wire done;
//----------------------------------------
always @(*) begin
case (addr)
4'h0:begin s = (cs && wr) ? 6'b000001 : 6'b000000 ;end //limit
4'h2:begin s = (cs && wr) ? 6'b000010 : 6'b000000 ;end //count
4'h4:begin s = (cs && wr) ? 6'b000100 : 6'b000000 ;end //init
4'h6:begin s = (cs && rd) ? 6'b001000 : 6'b000000 ;end //done
4'h8:begin s = (cs && rd) ? 6'b010000 : 6'b000000 ;end //clk_0
default:begin s = 6'b000000 ; end
endcase
end
//----------------------------------------
always @(negedge clk) begin
limit = (s[0]) ? d_in : limit; //Write Registers
count = (s[1]) ? d_in : count; //Write Registers
en = s[2] ; // (s[2]) ? d_in : init; //Write Registers
end
//----------------------------------------
always @(negedge clk) begin
case (s[5:3])
3'b001: d_out[0] = done ;
3'b010: d_out = int_0 ;
default: d_out = 0 ;
endcase
end//-----------------------------------------------mux_4
//----------------------------------------
clk_interruptor c_i ( .clk(clk), .rst(rst), .limit(limit), .count(count), .en(en), .int_0(int_0), .done(done) );
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fll; const mt19937 rng((int)chrono::steady_clock::now().time_since_epoch().count()); const int MOD = 998244353; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { int n, k; cin >> n >> k; vector<int> a(n); for (int &i : a) cin >> i; map<int, int> pos; for (int i = 0; i < n; i++) pos[a[i]] = i; vector<int> b(k); for (int &i : b) cin >> i; long long ans = 1; set<int> sb(b.begin(), b.end()); for (int i : b) { int p = pos[i]; long long nxt = 0; if (p != 0) { int vl = a[p - 1]; if (sb.count(vl) == 0) nxt += ans; } if (p != n - 1) { int vr = a[p + 1]; if (sb.count(vr) == 0) nxt += ans; } sb.erase(i); if (nxt >= MOD) nxt -= MOD; ans = nxt; } cout << ans << n ; } exit(0); } |
#include <bits/stdc++.h> using namespace std; long long dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; long long ddx[8] = {1, 1, 0, -1, -1, -1, 0, 1}, ddy[8] = {0, 1, 1, 1, 0, -1, -1, -1}; long long gcd(long long a, long long b) { if (!a) return b; return gcd(b % a, a); } long long lcm(long long a, long long b) { return (a * b) / gcd(a, b); } unordered_map<char, long long> mp; string s; long long n; bool fun(long long x) { long long cnt = 0; for (auto it : mp) { long long val = it.second; cnt += it.second / x; if (it.second % x != 0) { cnt++; } } if (cnt <= n) return true; else return false; } void test_case() { cin >> s; cin >> n; for (auto it : s) { mp[it]++; } if (mp.size() > n) { cout << -1 << n ; return; } long long l, r; l = 1; r = 1000; long long ans = 1000; while (l <= r) { long long mid = l + (r - l) / 2; if (fun(mid)) { ans = min(ans, mid); r = mid - 1; } else { l = mid + 1; } } cout << ans << n ; string st = ; for (auto it : mp) { long long val = it.second; long long cnt = 0; cnt = it.second / ans; if (it.second % ans != 0) { cnt++; } while (cnt--) { st += it.first; } } while (st.size() != n) { st += a ; } cout << st << n ; } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed << setprecision(20); long long t = 1; while (t--) { test_case(); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAPKAPWR_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DECAPKAPWR_FUNCTIONAL_V
/**
* decapkapwr: Decoupling capacitance filler on keep-alive rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__decapkapwr ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAPKAPWR_FUNCTIONAL_V |
// bsg_nonsynth_mixin_motherboard_comm_link
//
// This module is a mixin module, because it is parameterize by a module name
// and two submodules that need to be predefined.
//
// This file is a generic motherboard testing module; there are two "sockets"
// for chips. These chips have standard electrical interfaces corresponding
// to the bsg comm link. One socket is for the chipset, and the other is for the
// chip.
//
// To use this module, you must set three defines:
//
// BSG_NONSYNTH_MIXIN_MOTHERBOARD_module_name - the name of the motherboard module
//
// BSG_NONSYNTH_MIXIN_MOTHERBOARD_chipset_sig - partial instantiation of chipset module
// BSG_NONSYNTH_MIXIN_MOTHERBOARD_chip_sig - partial instantiation of the chip module
//
//
//
`include "bsg_defines.v"
`ifndef BSG_NONSYNTH_MIXIN_MOTHERBOARD_module_name
ERROR in bsg_nonsynth_mixin_motherboard.v: BSG_NONSYNTH_MIXIN_MOTHERBOARD_module_name must be defined
`endif
`ifndef BSG_NONSYNTH_MIXIN_MOTHERBOARD_chip_sig
ERROR in bsg_nonsynth_mixin_motherboard.v: BSG_NONSYNTH_MIXIN_MOTHERBOARD_chip_sig must be defined
`endif
`ifndef BSG_NONSYNTH_MIXIN_MOTHERBOARD_chip_sig
ERROR in bsg_nonsynth_mixin_motherboard.v: BSG_NONSYNTH_MIXIN_MOTHERBOARD_chip_sig must be defined
`endif
// note: this module is non-synthesizable
module `BSG_NONSYNTH_MOTHERBOARD_MIXIN_module_name
#( parameter `BSG_INV_PARAM(tile_x_max_p )
, parameter `BSG_INV_PARAM(tile_y_max_p )
, parameter asic_core_period_p = 5ns
, parameter chipset_core_period_p = 6ns
, parameter asic_io_master_period_p = 7ns
, parameter chipset_io_master_period_p = 8ns
, parameter tline_delay_p = 5ns // we could change this to have different delays
// defaults; usually do not change
, parameter num_channels_p = 4
, parameter channel_width_p = 8
)
( output logic asic_core_clock_o
, output logic asic_core_reset_o
);
wire asic_core_clk_i;
wire asic_async_reset_i;
wire asic_io_master_clk_i;
wire chipset_core_clk_i;
wire chipset_async_reset_i;
wire chipset_io_master_clk_i;
assign asic_core_clock_o = asic_core_clk_i;
bsg_nonsynth_clock_gen #(.cycle_time_p(asic_core_period_p)) asic_clk (.o(asic_core_clk_i ));
bsg_nonsynth_clock_gen #(.cycle_time_p(chipset_core_period_p)) chipset_clk (.o(chipset_core_clk_i));
initial
$display("%m creating clocks"
,asic_core_period_p , chipset_core_period_p
,asic_io_master_period_p, chipset_io_master_period_p);
bsg_nonsynth_clock_gen #(.cycle_time_p(asic_io_master_period_p)) i0_clk (.o(asic_io_master_clk_i ));
bsg_nonsynth_clock_gen #(.cycle_time_p(chipset_io_master_period_p)) i1_clk (.o(chipset_io_master_clk_i));
localparam core_reset_cycles_hi_lp = 256;
localparam core_reset_cycles_lo_lp = 16;
bsg_nonsynth_reset_gen
#(.num_clocks_p(4)
,.reset_cycles_lo_p(core_reset_cycles_lo_lp)
,.reset_cycles_hi_p(core_reset_cycles_hi_lp)
) reset_gen
(.clk_i({ asic_core_clk_i, asic_io_master_clk_i, chipset_core_clk_i, chipset_io_master_clk_i })
,.async_reset_o(chipset_async_reset_i)
);
wire [num_channels_p-1:0] asic_io_clk_tline_i;
wire [num_channels_p-1:0] asic_io_valid_tline_i;
wire [channel_width_p-1:0] asic_io_data_tline_i [num_channels_p-1:0];
wire [num_channels_p-1:0] asic_io_token_clk_tline_o;
// out to i/o
wire [num_channels_p-1:0] asic_im_clk_tline_o;
wire [num_channels_p-1:0] asic_im_valid_tline_o;
wire [channel_width_p-1:0] asic_im_data_tline_o [num_channels_p-1:0];
wire [num_channels_p-1:0] asic_token_clk_tline_i;
wire [num_channels_p-1:0] chipset_io_clk_tline_i;
wire [num_channels_p-1:0] chipset_io_valid_tline_i;
wire [channel_width_p-1:0] chipset_io_data_tline_i [num_channels_p-1:0];
wire [num_channels_p-1:0] chipset_io_token_clk_tline_o;
// out to i/o
wire [num_channels_p-1:0] chipset_im_clk_tline_o;
wire [num_channels_p-1:0] chipset_im_valid_tline_o;
wire [channel_width_p-1:0] chipset_im_data_tline_o [num_channels_p-1:0];
wire [num_channels_p-1:0] chipset_token_clk_tline_i;
wire chipset_im_slave_reset_tline_r_o;
wire chipset_core_reset_o;
// **************************
// the FPGA
/*
bsg_nonsynth_raw_chipset_vtile_pli #(.tile_x_max_p(tile_x_max_p)
,.tile_y_max_p(tile_y_max_p)
,.channel_width_p(channel_width_p)
,.num_channels_p(num_channels_p)
,.master_bypass_test_p(5'b11111) // speed up simulation
,.enabled_at_start_vec_p( { (tile_x_max_p+1) {1'b1 } })
) */
`BSG_NONSYNTH_MIXIN_MOTHERBOARD_chipset_sig
chipset
(
.core_clk_i(chipset_core_clk_i)
, .async_reset_i(chipset_async_reset_i)
, .io_master_clk_i(chipset_io_master_clk_i)
// input from i/o
, .io_clk_tline_i (chipset_io_clk_tline_i) // clk
, .io_valid_tline_i(chipset_io_valid_tline_i)
, .io_data_tline_i (chipset_io_data_tline_i)
, .io_token_clk_tline_o(chipset_io_token_clk_tline_o) // clk
// out to i/o
, .im_clk_tline_o (chipset_im_clk_tline_o ) // clk
, .im_valid_tline_o (chipset_im_valid_tline_o )
, .im_data_tline_o (chipset_im_data_tline_o )
, .token_clk_tline_i(chipset_token_clk_tline_i) // clk
// note: generate by the master (FPGA) and sent to the slave (ASIC)
// not used by slave (ASIC).
, .im_slave_reset_tline_r_o(chipset_im_slave_reset_tline_r_o)
// this signal is the post-calibration reset signal
// synchronous to the core clock
, .core_reset_o(chipset_core_reset_o)
);
// **************************
// PC board traces
//
// we introduce delays in the transmission lines that
// go between chips; technically we could use different delays
//
bsg_nonsynth_delay_line #(.width_p(num_channels_p), .delay_p(tline_delay_p)) bdl0
(.i(asic_im_clk_tline_o), .o(chipset_io_clk_tline_i));
bsg_nonsynth_delay_line #(.width_p(num_channels_p), .delay_p(tline_delay_p)) bdl1
(.i(chipset_im_clk_tline_o), .o(asic_io_clk_tline_i));
bsg_nonsynth_delay_line #(.width_p(num_channels_p), .delay_p(tline_delay_p)) bdl2
(.i(asic_im_valid_tline_o), .o(chipset_io_valid_tline_i));
bsg_nonsynth_delay_line #(.width_p(num_channels_p), .delay_p(tline_delay_p)) bdl3
(.i(chipset_im_valid_tline_o), .o(asic_io_valid_tline_i));
bsg_nonsynth_delay_line #(.width_p(num_channels_p), .delay_p(tline_delay_p)) bdl4
(.i(asic_io_token_clk_tline_o), .o(chipset_token_clk_tline_i));
bsg_nonsynth_delay_line #(.width_p(num_channels_p), .delay_p(tline_delay_p)) bdl5
(.i(chipset_io_token_clk_tline_o), .o(asic_token_clk_tline_i));
genvar i;
for (i=0; i < num_channels_p; i++)
begin: rof
bsg_nonsynth_delay_line #(.width_p(channel_width_p), .delay_p(tline_delay_p)) bdl6
(.i(asic_im_data_tline_o[i]), .o(chipset_io_data_tline_i[i]));
bsg_nonsynth_delay_line #(.width_p(channel_width_p), .delay_p(tline_delay_p)) bdl7
(.i(chipset_im_data_tline_o[i]), .o(asic_io_data_tline_i[i]));
end
bsg_nonsynth_delay_line #(.width_p(1), .delay_p(tline_delay_p)) bdl8
(.i(chipset_im_slave_reset_tline_r_o), .o(asic_async_reset_i));
// **************************
// the ASIC
/*
bsg_guts_greendroid_node #(.tile_x_max_p(tile_x_max_p)
,.tile_y_max_p(tile_y_max_p)
,.south_side_only_p(1)
)
*/
`BSG_NONSYNTH_MIXIN_MOTHERBOARD_chip_sig
asic
(.core_clk_i(asic_core_clk_i)
, .async_reset_i(asic_async_reset_i)
, .io_master_clk_i(asic_io_master_clk_i)
// input from i/o
, .io_clk_tline_i (asic_io_clk_tline_i ) // clk
, .io_valid_tline_i(asic_io_valid_tline_i)
, .io_data_tline_i (asic_io_data_tline_i )
, .io_token_clk_tline_o(asic_io_token_clk_tline_o) // clk
// out to i/o
, .im_clk_tline_o (asic_im_clk_tline_o ) // clk
, .im_valid_tline_o (asic_im_valid_tline_o )
, .im_data_tline_o (asic_im_data_tline_o )
, .token_clk_tline_i(asic_token_clk_tline_i) // clk
// note: generate by the master (FPGA) and sent to the slave (ASIC)
// not used by slave (ASIC).
, .im_slave_reset_tline_r_o() // unused; fixme remove?
// this signal is the post-calibration reset signal
// synchronous to the core clock
, .core_reset_o(asic_core_reset_o)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_mixin_motherboard)
|
#include <bits/stdc++.h> using namespace std; const int N = 100000 + 5, inf = 1e9 + 7; int n, m, x, y, l, r, f[N]; struct tt { int l, r; } a[100]; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d%d , &x, &y); l = max(1, x - y), r = min(m, x + y); a[i].l = l, a[i].r = r; } for (int i = 1; i <= m; i++) { f[i] = i; for (int j = 1; j <= n; j++) { if (a[j].l <= i && i <= a[j].r) f[i] = min(f[i], f[i - 1]); else if (a[j].r < i) f[i] = min(f[i], i - a[j].r + f[max(0, a[j].l - i + a[j].r - 1)]); } } printf( %d n , f[m]); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[100 + 10]; int main() { int n; while (~scanf( %d , &n)) { int p1, p2, p3, t1, t2; scanf( %d%d%d%d%d , &p1, &p2, &p3, &t1, &t2); int ans = 0; int temp, len = 0; for (int i = 1; i <= n; i++) { int x, y; scanf( %d%d , &x, &y); ans += (y - x) * p1; if (i > 1) { a[len++] = x - temp; } temp = y; } for (int i = 0; i < len; i++) { if (a[i] < t1) { ans += a[i] * p1; } else if (a[i] < t1 + t2) { ans += t1 * p1 + (a[i] - t1) * p2; } else { ans += t1 * p1 + t2 * p2 + (a[i] - t1 - t2) * p3; } } cout << ans << endl; } return 0; } |
`include "gate16.v"
module Mux(input a, b, sel, output out);
Not g1(sel, nsel);
And g2(a, nsel, o1);
And g3(b, sel, o2);
Or g4(o1, o2, out);
endmodule
module DMux(input in, sel, output a, b);
Not g1(sel, nsel);
And g2(nsel, in, a);
And g3(sel, in, b);
endmodule
module Mux16(input[15:0] a, b, input sel, output[15:0] out);
Mux g15(a[15], b[15], sel, out[15]);
Mux g14(a[14], b[14], sel, out[14]);
Mux g13(a[13], b[13], sel, out[13]);
Mux g12(a[12], b[12], sel, out[12]);
Mux g11(a[11], b[11], sel, out[11]);
Mux g10(a[10], b[10], sel, out[10]);
Mux g09(a[9], b[9], sel, out[9]);
Mux g08(a[8], b[8], sel, out[8]);
Mux g07(a[7], b[7], sel, out[7]);
Mux g06(a[6], b[6], sel, out[6]);
Mux g05(a[5], b[5], sel, out[5]);
Mux g04(a[4], b[4], sel, out[4]);
Mux g03(a[3], b[3], sel, out[3]);
Mux g02(a[2], b[2], sel, out[2]);
Mux g01(a[1], b[1], sel, out[1]);
Mux g00(a[0], b[0], sel, out[0]);
endmodule
module Mux4Way16(input[15:0] a,b,c,d, input[1:0] sel, output[15:0] out);
wire [15:0] outab, outcd;
Mux16 g1(a, b, sel[0], outab);
Mux16 g2(c, d, sel[0], outcd);
Mux16 g3(outab, outcd, sel[1], out);
endmodule
module Mux8Way16(input[15:0] a,b,c,d,e,f,g,h, input[2:0] sel, output[15:0] out);
wire [15:0] outad, outeh;
Mux4Way16 g1(a, b, c, d, sel[1:0], outad);
Mux4Way16 g2(e, f, g, h, sel[1:0], outeh);
Mux16 g3(outad, outeh, sel[2], out);
endmodule
module DMux4Way(input in, input[1:0] sel, output a,b,c,d);
Not g1(sel[1], nsel1);
Not g2(sel[0], nsel0);
And g3(nsel1, nsel0, sel00);
And g4(nsel1, sel[0], sel01);
And g5(sel[1], nsel0, sel10);
And g6(sel[1], sel[0], sel11);
DMux g7(in, sel00, d0, a);
DMux g8(in, sel01, d1, b);
DMux g9(in, sel11, d2, d);
DMux g10(in, sel10, d3, c);
endmodule
module DMux8Way(input in, input[2:0] sel, output a,b,c,d,e,f,g,h);
Not g1(sel[2], nsel2);
And g2(in, sel[2], s2h);
And g3(in, nsel2, s2l);
DMux4Way g4(s2h, sel[1:0], e, f, g, h);
DMux4Way g5(s2l, sel[1:0], a, b, c, d);
endmodule
|
#include <bits/stdc++.h> using namespace std; bool prime(int x) { for (int i = 2; i * i <= x; i++) { if (x % i == 0) return 0; } return 1; } int main() { int n; vector<int> ans; cin >> n; for (int i = 2; i <= n; ++i) { if (prime(i)) { for (int j = i; j <= n; j *= i) { ans.push_back(j); } } } cout << ans.size() << endl; for (auto i : ans) { cout << i << ; } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Fri Sep 22 18:26:44 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0]" */;
input clk;
input [63:0]probe0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR3B_2_V
`define SKY130_FD_SC_HD__NOR3B_2_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3b_2 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor3b_2 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR3B_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_TB_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD1_TB_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv3sd1.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__clkdlyinv3sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD1_TB_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Instruction TLB ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of ITLB. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.6 2002/10/28 16:34:32 mohor
// RAMs wrong connected to the BIST scan chain.
//
// Revision 1.5 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.4 2002/08/14 06:23:50 lampret
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
//
// Revision 1.3 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.2 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Insn TLB
//
module or1200_immu_tlb(
// Rst and clk
clk, rst,
// I/F for translation
tlb_en, vaddr, hit, ppn, uxe, sxe, ci,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// I/F for translation
//
input tlb_en;
input [aw-1:0] vaddr;
output hit;
output [31:`OR1200_IMMU_PS] ppn;
output uxe;
output sxe;
output ci;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
wire [`OR1200_ITLB_TAG] vpn;
wire v;
wire [`OR1200_ITLB_INDXW-1:0] tlb_index;
wire tlb_mr_en;
wire tlb_mr_we;
wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_in;
wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out;
wire tlb_tr_en;
wire tlb_tr_we;
wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in;
wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out;
// BIST
`ifdef OR1200_BIST
wire itlb_mr_ram_si;
wire itlb_mr_ram_so;
wire itlb_tr_ram_si;
wire itlb_tr_ram_so;
`endif
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-19 v 0
// itlbwYtrX: ppn 31-13 uxe 7 sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
// 1 bit for cache inhibit
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];
//
// Output to SPRS unit
//
assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
{vpn, tlb_index & {`OR1200_ITLB_INDXW{v}}, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
(!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
32'h00000000;
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out;
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};
//
// Assign outputs from Translate registers
//
assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out;
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
//
// Generate hit
//
assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];
`ifdef OR1200_BIST
assign itlb_mr_ram_si = mbist_si_i;
assign itlb_tr_ram_si = itlb_mr_ram_so;
assign mbist_so_o = itlb_tr_ram_so;
`endif
//
// Instantiation of ITLB Match Registers
//
or1200_spram_64x14 itlb_mr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(itlb_mr_ram_si),
.mbist_so_o(itlb_mr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_mr_ram_in),
.doq(tlb_mr_ram_out)
);
//
// Instantiation of ITLB Translate Registers
//
or1200_spram_64x22 itlb_tr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(itlb_tr_ram_si),
.mbist_so_o(itlb_tr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_tr_ram_in),
.doq(tlb_tr_ram_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > snakeG(int x1, int y1, int x2, int y2) { vector<pair<int, int> > res; int n = y2 - y1 + 1, m = x2 - x1 + 1; for (int i = 0; i < m; ++i) { for (int j = 0; j < n; ++j) { if (i % 2 == 0) { res.push_back(make_pair(x1 + i, y1 + j)); } else { res.push_back(make_pair(x1 + i, y2 - j)); } } } return res; } vector<pair<int, int> > snakeV(int x1, int y1, int x2, int y2) { vector<pair<int, int> > res; int n = y2 - y1 + 1, m = x2 - x1 + 1; for (int j = 0; j < n; ++j) { for (int i = 0; i < m; ++i) { if (j % 2 == 0) { res.push_back(make_pair(x1 + i, y1 + j)); } else { res.push_back(make_pair(x2 - i, y1 + j)); } } } return res; } int main() { int n, m; cin >> n >> m; if (m == 1) { if (n == 2) { cout << 0 << endl; cout << 1 << << 1 << endl; cout << 2 << << 1 << endl; cout << 1 << << 1 << endl; return 0; } else { cout << 1 << endl; cout << n << << m << << 1 << << 1 << endl; for (int i = 1; i < n + 1; ++i) cout << i << << 1 << endl; cout << 1 << << 1 << endl; return 0; } } if (n == 1) { if (m == 2) { cout << 0 << endl; cout << 1 << << 1 << endl; cout << 1 << << 2 << endl; cout << 1 << << 1 << endl; return 0; } else { cout << 1 << endl; cout << n << << m << << 1 << << 1 << endl; for (int i = 1; i < m + 1; ++i) cout << 1 << << i << endl; cout << 1 << << 1 << endl; return 0; } } if (n == m) { if (n % 2 == 0) { cout << 0 << endl; vector<pair<int, int> > res = snakeG(1, 2, n, m); cout << 1 << << 1 << endl; for (int i = 0; i < res.size(); ++i) cout << res[i].first << << res[i].second << endl; for (int i = n; i >= 1; --i) cout << i << << 1 << endl; } else { cout << 1 << endl; cout << n << << m << << 1 << << 1 << endl; vector<pair<int, int> > res = snakeG(1, 1, n, m); for (int i = 0; i < res.size(); ++i) cout << res[i].first << << res[i].second << endl; cout << 1 << << 1 << endl; } } else { if (n > m) { if (m % 2 == 0) { if (n % 2 == 0) { cout << 0 << endl; vector<pair<int, int> > res = snakeG(1, 2, n, m); cout << 1 << << 1 << endl; for (int i = 0; i < res.size(); ++i) cout << res[i].first << << res[i].second << endl; for (int i = n; i >= 1; --i) cout << i << << 1 << endl; } else { cout << 0 << endl; vector<pair<int, int> > res = snakeG(1, 2, n - 2, m); vector<pair<int, int> > res1 = snakeV(n - 1, 1, n, m); reverse(res1.begin(), res1.end()); cout << 1 << << 1 << endl; for (int i = 0; i < res.size(); ++i) cout << res[i].first << << res[i].second << endl; for (int i = 0; i < res1.size(); ++i) cout << res1[i].first << << res1[i].second << endl; for (int i = n - 2; i >= 1; --i) cout << i << << 1 << endl; } } else { if (n % 2 == 0) { cout << 0 << endl; vector<pair<int, int> > res = snakeG(1, 2, n, m); cout << 1 << << 1 << endl; for (int i = 0; i < res.size(); ++i) cout << res[i].first << << res[i].second << endl; for (int i = n; i >= 1; --i) cout << i << << 1 << endl; } else { cout << 1 << endl; cout << n << << m << << 1 << << 1 << endl; vector<pair<int, int> > res = snakeG(1, 1, n, m); for (int i = 0; i < res.size(); ++i) cout << res[i].first << << res[i].second << endl; cout << 1 << << 1 << endl; } } } else { if (n % 2 == 0) { cout << 0 << endl; vector<pair<int, int> > res = snakeG(1, 2, n, m); cout << 1 << << 1 << endl; for (int i = 0; i < res.size(); ++i) cout << res[i].first << << res[i].second << endl; for (int i = n; i >= 1; --i) cout << i << << 1 << endl; } else { if (m % 2 == 0) { cout << 0 << endl; vector<pair<int, int> > res = snakeG(1, 2, n - 2, m); vector<pair<int, int> > res1 = snakeV(n - 1, 1, n, m); reverse(res1.begin(), res1.end()); cout << 1 << << 1 << endl; for (int i = 0; i < res.size(); ++i) cout << res[i].first << << res[i].second << endl; for (int i = 0; i < res1.size(); ++i) cout << res1[i].first << << res1[i].second << endl; for (int i = n - 2; i >= 1; --i) cout << i << << 1 << endl; } else { cout << 1 << endl; cout << n << << m << << 1 << << 1 << endl; vector<pair<int, int> > res = snakeG(1, 1, n, m); for (int i = 0; i < res.size(); ++i) cout << res[i].first << << res[i].second << endl; cout << 1 << << 1 << endl; } } } } return 0; } |
#include <bits/stdc++.h> using namespace std; char ans[1005][1005]; int x[1005][1005], y[1005][1005]; int n; int dx[] = {1, 0, -1, 0}; int dy[] = {0, 1, 0, -1}; bool isvalid(int i, int j) { if (i < 0 || j < 0 || i >= n || j >= n) return 0; return 1; } void color(int i, int j) { if (i < 0 || j < 0 || i >= n || j >= n || ans[i][j] == Z || x[i][j] != -1 || y[i][j] != -1) return; ans[i][j] = Z ; for (int k = 0; k < 4; k++) color(i + dx[k], j + dy[k]); } void DFS(int i, int j, char ch, int ka, int kh) { if (i < 0 || j < 0 || i >= n || j >= n || x[i][j] == -1 || ans[i][j] != K ) return; ans[i][j] = ch; if (isvalid(i + 1, j) && x[i + 1][j] == ka && y[i + 1][j] == kh) { DFS(i + 1, j, U , ka, kh); } if (isvalid(i - 1, j) && x[i - 1][j] == ka && y[i - 1][j] == kh) { DFS(i - 1, j, D , ka, kh); } if (isvalid(i, j + 1) && x[i][j + 1] == ka && y[i][j + 1] == kh) { DFS(i, j + 1, L , ka, kh); } if (isvalid(i, j - 1) && x[i][j - 1] == ka && y[i][j - 1] == kh) { DFS(i, j - 1, R , ka, kh); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> x[i][j] >> y[i][j]; ans[i][j] = K ; } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (x[i][j] == -1 && y[i][j] == -1) color(i, j); else if (x[i][j] == i + 1 && y[i][j] == j + 1) DFS(i, j, X , i + 1, j + 1); } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (ans[i][j] == Z ) { if (isvalid(i + 1, j) && x[i + 1][j] == -1) { ans[i][j] = D ; ans[i + 1][j] = U ; } else if (isvalid(i - 1, j) && x[i - 1][j] == -1) { ans[i][j] = U ; ans[i - 1][j] = D ; } else if (isvalid(i, j + 1) && x[i][j + 1] == -1) { ans[i][j] = R ; ans[i][j + 1] = L ; } else if (isvalid(i, j - 1) && x[i][j - 1] == -1) { ans[i][j] = L ; ans[i][j - 1] = R ; } } } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (ans[i][j] == K || ans[i][j] == Z ) { cout << INVALID ; return 0; } } } cout << VALID n ; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) cout << ans[i][j]; cout << n ; } return 0; } |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: sg_list_reader_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Reads data from the scatter gather list buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_SGR128_RD_0 1'b1
`define S_SGR128_RD_WAIT 1'b0
`define S_SGR128_CAP_0 1'b0
`define S_SGR128_CAP_RDY 1'b1
`timescale 1ns/1ns
module sg_list_reader_128 #(
parameter C_DATA_WIDTH = 9'd128
)
(
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output VALID, // Scatter gather element data is valid
output EMPTY, // Scatter gather elements empty
input REN, // Scatter gather element data read enable
output [63:0] ADDR, // Scatter gather element address
output [31:0] LEN // Scatter gather element length (in words)
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg rRdState=`S_SGR128_RD_0, _rRdState=`S_SGR128_RD_0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg rCapState=`S_SGR128_CAP_0, _rCapState=`S_SGR128_CAP_0;
reg [C_DATA_WIDTH-1:0] rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rLen=0, _rLen=0;
reg rFifoValid=0, _rFifoValid=0;
reg rDataValid=0, _rDataValid=0;
assign BUF_DATA_REN = rRdState; // Not S_SGR128_RD_WAIT
assign VALID = rCapState; // S_SGR128_CAP_RDY
assign EMPTY = (BUF_DATA_EMPTY & rRdState); // Not S_SGR128_RD_WAIT
assign ADDR = rAddr;
assign LEN = rLen;
// Capture address and length as it comes out of the FIFO
always @ (posedge CLK) begin
rRdState <= #1 (RST ? `S_SGR128_RD_0 : _rRdState);
rCapState <= #1 (RST ? `S_SGR128_CAP_0 : _rCapState);
rData <= #1 _rData;
rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
end
always @ (*) begin
_rRdState = rRdState;
_rCapState = rCapState;
_rAddr = rAddr;
_rLen = rLen;
_rData = BUF_DATA;
_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
_rDataValid = rFifoValid;
case (rCapState)
`S_SGR128_CAP_0: begin
if (rDataValid) begin
_rAddr = rData[63:0];
_rLen = rData[95:64];
_rCapState = `S_SGR128_CAP_RDY;
end
end
`S_SGR128_CAP_RDY: begin
if (REN)
_rCapState = `S_SGR128_CAP_0;
end
endcase
case (rRdState)
`S_SGR128_RD_0: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR128_RD_WAIT;
end
`S_SGR128_RD_WAIT: begin // Wait for the data to be consumed
if (REN)
_rRdState = `S_SGR128_RD_0;
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
// OK
reg [15:0] a_split_1, a_split_2;
always @ (/*AS*/m_din) begin
a_split_1 = m_din;
a_split_2 = m_din;
end
// OK
reg [15:0] b_split_1, b_split_2;
always @ (/*AS*/m_din) begin
b_split_1 = m_din;
b_split_2 = b_split_1;
end
// Not OK
reg [15:0] c_split_1, c_split_2;
always @ (/*AS*/m_din) begin
c_split_1 = m_din;
c_split_2 = c_split_1;
c_split_1 = ~m_din;
end
// OK
reg [15:0] d_split_1, d_split_2;
always @ (posedge clk) begin
d_split_1 <= m_din;
d_split_2 <= d_split_1;
d_split_1 <= ~m_din;
end
// Not OK
always @ (posedge clk) begin
$write(" foo %x", m_din);
$write(" bar %x\n", m_din);
end
// Not OK
reg [15:0] e_split_1, e_split_2;
always @ (posedge clk) begin
e_split_1 = m_din;
e_split_2 = e_split_1;
end
// Not OK
reg [15:0] f_split_1, f_split_2;
always @ (posedge clk) begin
f_split_2 = f_split_1;
f_split_1 = m_din;
end
// Not Ok
reg [15:0] l_split_1, l_split_2;
always @ (posedge clk) begin
l_split_2 <= l_split_1;
l_split_1 <= l_split_2 | m_din;
end
// OK
reg [15:0] z_split_1, z_split_2;
always @ (posedge clk) begin
z_split_1 <= 0;
z_split_1 <= ~m_din;
end
always @ (posedge clk) begin
z_split_2 <= 0;
z_split_2 <= z_split_1;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
m_din <= 16'hfeed;
end
if (cyc==3) begin
end
if (cyc==4) begin
m_din <= 16'he11e;
//$write(" A %x %x\n", a_split_1, a_split_2);
if (!(a_split_1==16'hfeed && a_split_2==16'hfeed)) $stop;
if (!(b_split_1==16'hfeed && b_split_2==16'hfeed)) $stop;
if (!(c_split_1==16'h0112 && c_split_2==16'hfeed)) $stop;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop;
if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop;
end
if (cyc==5) begin
m_din <= 16'he22e;
if (!(a_split_1==16'he11e && a_split_2==16'he11e)) $stop;
if (!(b_split_1==16'he11e && b_split_2==16'he11e)) $stop;
if (!(c_split_1==16'h1ee1 && c_split_2==16'he11e)) $stop;
if (!(d_split_1==16'h0112 && d_split_2==16'h0112)) $stop;
if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop;
end
if (cyc==6) begin
m_din <= 16'he33e;
if (!(a_split_1==16'he22e && a_split_2==16'he22e)) $stop;
if (!(b_split_1==16'he22e && b_split_2==16'he22e)) $stop;
if (!(c_split_1==16'h1dd1 && c_split_2==16'he22e)) $stop;
if (!(d_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
if (!(z_split_1==16'h1ee1 && d_split_2==16'h0112)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop;
if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop;
end
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; static int aQWEs = []() -> int { ios::sync_with_stdio(false); cin.tie(NULL); return 0; }(); long long int power(long long int a, long long int p, long long int m = 1000000007) { a %= m; long long int val = 1; while (p > 0) { if (p & 1) { val = (val * a) % m; } a = (a * a) % m; p >>= 1; } return (val); } int dfs(const vector<int>& v, std::vector<bool>& vis, int cur, int depth) { vis[cur] = 1; if (!vis[v[cur]]) return dfs(v, vis, v[cur], depth + 1); return depth; } int main() { long long int i, j; int T = 1; while (T--) { int n; cin >> n; std::vector<int> v(n + 1); std::vector<bool> vis(n + 1); int ans = 0; for (i = 1; i <= n; ++i) { cin >> v[i]; } for (i = 1; i <= n; ++i) { if (!vis[i]) ans += dfs(v, vis, i, 0); } if (!((3 * n - ans) & 1)) { cout << Petr n ; } else cout << Um_nik n ; } } |
#include <bits/stdc++.h> using namespace std; int const sqN = 320; int add(int a, int b); int sub(int a, int b); int arr[100005]; struct query { int index; int l; int r; int ans; }; bool comp(query &a, query &b) { if (a.l / sqN != b.l / sqN) { return a.l / sqN < b.l / sqN; } return a.r < b.r; } bool comp_by_index(query &a, query &b) { return a.index < b.index; } int main() { int n, m, aux, l, r, cnt; cin >> n >> m; vector<int> F; F.push_back(0); for (int i = 0; i < n; i++) { cin >> aux; if (aux > 100000) aux = 0; F.push_back(aux); } vector<query> Q; for (int i = 0; i < m; i++) { cin >> l >> r; query inp; inp.index = i; inp.l = l; inp.r = r; Q.push_back(inp); } sort(Q.begin(), Q.end(), comp); memset(arr, 0, sizeof(arr)); r = 1; l = 0; cnt = (F[1] == 1) ? 1 : 0; arr[F[1]] += 1; for (int i = 0; i < m; i++) { query curq = Q[i]; while (r < Q[i].r) { r++; cnt += sub(arr[F[r]], F[r]); arr[F[r]] += 1; cnt += add(arr[F[r]], F[r]); } while (l < Q[i].l - 1) { l++; cnt += sub(arr[F[l]], F[l]); arr[F[l]] -= 1; cnt += add(arr[F[l]], F[l]); } while (l >= Q[i].l) { cnt += sub(arr[F[l]], F[l]); arr[F[l]] += 1; cnt += add(arr[F[l]], F[l]); l--; } while (r > Q[i].r) { cnt += sub(arr[F[r]], F[r]); arr[F[r]] -= 1; cnt += add(arr[F[r]], F[r]); r--; } Q[i].ans = cnt; } sort(Q.begin(), Q.end(), comp_by_index); for (int i = 0; i < Q.size(); i++) cout << Q[i].ans << endl; } int add(int a, int b) { if (b > 0 and b == a) return 1; return 0; } int sub(int a, int b) { if (b > 0 and b == a) return -1; return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_slave #(
parameter ACCEPTANCE = 3,
parameter MIN_LATENCY = 16,
parameter MAX_LATENCY = 32
) (
input clk,
input reset,
input valid,
output ready,
input [31:0] addr,
input [7:0] len,
input [2:0] size,
input [1:0] burst,
input [2:0] prot,
input [3:0] cache,
output beat_stb,
input beat_ack,
output [31:0] beat_addr,
output beat_last
);
reg [31:0] timestamp = 'h00;
always @(posedge clk) begin
if (reset == 1'b1) begin
timestamp <= 'h00;
end else begin
timestamp <= timestamp + 1'b1;
end
end
reg [32+32+8-1:0] req_fifo[0:15];
reg [3:0] req_fifo_rd = 'h00;
reg [3:0] req_fifo_wr = 'h00;
wire [3:0] req_fifo_level = req_fifo_wr - req_fifo_rd;
assign ready = req_fifo_level < ACCEPTANCE;
always @(posedge clk) begin
if (reset == 1'b1) begin
req_fifo_wr <= 'h00;
end else begin
if (valid == 1'b1 && ready == 1'b1) begin
req_fifo[req_fifo_wr][71:40] <= timestamp + {$random} % (MAX_LATENCY - MIN_LATENCY + 1) + MIN_LATENCY;
req_fifo[req_fifo_wr][39:0] <= {addr,len};
req_fifo_wr <= req_fifo_wr + 1'b1;
end
end
end
reg [7:0] beat_counter = 'h00;
assign beat_stb = req_fifo_level != 0 && timestamp > req_fifo[req_fifo_rd][71:40];
assign beat_last = beat_stb ? beat_counter == req_fifo[req_fifo_rd][0+:8] : 1'b0;
assign beat_addr = req_fifo[req_fifo_rd][8+:32] + beat_counter * 4;
always @(posedge clk) begin
if (reset == 1'b1) begin
beat_counter <= 'h00;
req_fifo_rd <= 'h00;
end else begin
if (beat_ack == 1'b1) begin
if (beat_last == 1'b1) begin
beat_counter <= 'h00;
req_fifo_rd <= req_fifo_rd + 1'b1;
end else begin
beat_counter <= beat_counter + 1'b1;
end
end
end
end
endmodule
|
// file: clk_gen_83M_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module clk_gen_83M_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 40.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [3:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_gen_83M_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2010; struct edge { int to, next, w; } e[200010]; int head[N], ecnt, n, vis[N], val[N], mark[N][N]; long long dp[2][N][N], cover[N][N], sum; inline void adde(int from, int to, int w) { e[++ecnt] = (edge){to, head[from], w}, head[from] = ecnt; e[++ecnt] = (edge){from, head[to], w}, head[to] = ecnt; } inline void Dijkstra(long long d[], int s) { for (int i = 1; i <= n; i++) d[i] = 1e18; memset(vis, 0, sizeof(vis)); priority_queue<pair<long long, int> > q; q.push(pair<long long, int>(0, s)), d[s] = 0; while (!q.empty()) { int u = q.top().second; q.pop(); if (vis[u]) continue; vis[u] = 1; for (int i = head[u]; i; i = e[i].next) if (!vis[e[i].to] && d[u] + e[i].w < d[e[i].to]) d[e[i].to] = d[u] + e[i].w, q.push(pair<long long, int>(-d[e[i].to], e[i].to)); } } inline void work(int s, int t) { static long long S[N], T[N], tmp[N]; Dijkstra(S, s), Dijkstra(T, t); int top = 0; for (int i = 1; i <= n; i++) tmp[++top] = S[i]; sort(tmp + 1, tmp + top + 1), top = unique(tmp + 1, tmp + top + 1) - tmp - 1; for (int i = 1; i <= n; i++) S[i] = lower_bound(tmp + 1, tmp + top + 1, S[i]) - tmp; top = sum = 0; for (int i = 1; i <= n; i++) tmp[++top] = T[i]; sort(tmp + 1, tmp + top + 1), top = unique(tmp + 1, tmp + top + 1) - tmp - 1; for (int i = 1; i <= n; i++) sum += val[i]; for (int i = 1; i <= n; i++) T[i] = lower_bound(tmp + 1, tmp + top + 1, T[i]) - tmp; for (int i = 1; i <= n; i++) cover[S[i] - 1][T[i] - 1] -= val[i], mark[S[i] - 1][T[i] - 1] = -1; for (int i = n; i >= 0; i--) for (int j = n; j >= 0; j--) { cover[i][j] += cover[i + 1][j] + cover[i][j + 1] - cover[i + 1][j + 1]; mark[i][j] += mark[i + 1][j] + mark[i][j + 1] - mark[i + 1][j + 1]; } for (int i = 0; i <= n; i++) for (int j = 0; j <= n; j++) cover[i][j] += sum, mark[i][j] += n; } int nxt[2][N][N]; long long f[N][N], g[N][N]; int main() { int m, s, t; scanf( %d%d%d%d , &n, &m, &s, &t); for (int i = 1; i <= n; i++) scanf( %d , &val[i]); for (int i = 1, a, b, c; i <= m; i++) scanf( %d%d%d , &a, &b, &c), adde(a, b, c); work(s, t); for (int i = 0; i <= n + 1; i++) for (int j = 0; j <= n + 1; j++) f[i][j] = g[i][j] = -1e18; for (int i = n; i >= 0; i--) for (int j = n; j >= 0; j--) { if (mark[i][j] != mark[i + 1][j]) nxt[1][i][j] = i + 1; else nxt[1][i][j] = nxt[1][i + 1][j]; if (mark[i][j] != mark[i][j + 1]) nxt[0][i][j] = j + 1; else nxt[0][i][j] = nxt[0][i][j + 1]; } for (int i = n; i >= 0; i--) for (int j = n; j >= 0; j--) { f[i][j] = f[i + 1][j], g[i][j] = g[i][j + 1]; if (cover[i][j] == sum) dp[0][i][j] = dp[1][i][j] = 0; else dp[1][i][j] = f[nxt[1][i][j]][j] - cover[i][j], dp[0][i][j] = g[i][nxt[0][i][j]] - cover[i][j]; f[i][j] = max(f[i][j], cover[i][j] - dp[0][i][j]), g[i][j] = max(g[i][j], cover[i][j] - dp[1][i][j]); } long long w = dp[1][0][0]; if (w == 0) puts( Flowers ); else puts(w > 0 ? Break a heart : Cry ); return 0; } |
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2012 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Ltac f_equiv' := repeat progress (f_equiv; try intros ? ? ?; auto).
Module NStrongRecProp (Import N : NAxiomsRecSig').
Include NSubProp N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows to define a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0; f_equiv'.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt; f_equiv'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
f_equiv.
rewrite recursion_succ; f_equiv'.
reflexivity.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ; f_equiv'.
rewrite strong_rec0_0. reflexivity.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
f_equiv.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Arguments strong_rec [A] a f n.
End NStrongRecProp.
|
#include <bits/stdc++.h> using namespace std; const int N = 200002; int n, x1, x2, p[N]; pair<int, int> a[N]; int i1, i2; bool solve() { i1 = i2 = -1; for (int i = n; i >= 1; --i) { if (a[i].first * (n - i + 1) >= x1) { i1 = i; break; } } for (int i = i1 - 1; i >= 1; --i) { if (a[i].first * (i1 - i) >= x2) { i2 = i; break; } } return i1 != -1 && i2 != -1; } int main() { ios_base::sync_with_stdio(0); cin >> n >> x1 >> x2; for (int i = 1; i <= n; ++i) { cin >> a[i].first; a[i].second = i; } sort(a + 1, a + 1 + n); if (solve()) { cout << Yes << endl; cout << (n - i1 + 1) << << (i1 - i2) << endl; for (int i = i1; i <= n; ++i) cout << a[i].second << ; cout << endl; for (int i = i2; i < i1; ++i) cout << a[i].second << ; cout << endl; return 0; } swap(x1, x2); if (solve()) { cout << Yes << endl; cout << (i1 - i2) << << (n - i1 + 1) << endl; for (int i = i2; i < i1; ++i) cout << a[i].second << ; cout << endl; for (int i = i1; i <= n; ++i) cout << a[i].second << ; cout << endl; return 0; } cout << No ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DECAP_FUNCTIONAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__decap ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_FUNCTIONAL_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_int.v ////
//// ////
//// This file is part of the "uart16550" project ////
//// http://www.opencores.org/projects/uart16550/ ////
//// ////
//// Author(s): ////
//// - (Tadej Markovic) ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
`include "uart_defines.v"
`include "uart_testbench_defines.v"
`include "timescale.v"
module testcase;
// Testcase INDEPENDENT code - common to all testcases
//#####################################################
// Variables
// Testbench reporting events & signals
event severe_err_event;
event err_event;
event wrn_event;
event msg_event;
event val_event;
event testbench_log_written;
reg [7999: 0] tim;
reg [7999: 0] severe_err_msg;
reg [7999: 0] msg;
integer val;
// Testcase reporting events & signals
event testcase_log_written;
event test_end;
reg [1599: 0] test_name;
reg error_detected;
// Module for writing to log files
uart_log log ();
defparam log.testcase_name = "uart_interrupts";
// Log
initial
fork
begin: init_log
reg ok;
// Delay allows all other blocks in this fork - join block to execute
#1;
log.start_log(ok);
if (ok !== 1'b1)
begin
`SEVERE_ERROR("Failed to open log file(s)!");
disable init_log;
end
testcase_init;
testcase_test;
log.end_log;
# 100;
$finish;
end
begin
forever
begin
@(test_name);
error_detected = 1'b0;
log.report_test_name(test_name);
log.verbose_test_name(test_name);
-> testcase_log_written;
end
end
begin
forever
begin
@(test_end);
if (error_detected)
begin
log.tests_failed = log.tests_failed + 1'b1;
end
else
begin
log.tests_ok = log.tests_ok + 1'b1;
log.report_test_ok;
end
-> testcase_log_written;
end
end
begin
@(severe_err_event);
error_detected = 1'b1;
-> test_end;
@(testcase_log_written);
log.report_test_failed(severe_err_msg);
if (testcase.log.free == 0)
begin
wait (testcase.log.free);
severe_err_msg = "Failed to write to log file(s)!";
end
log.verbose_severe_err(tim, severe_err_msg);
-> testbench_log_written;
# 100; $finish;
end
begin
forever
begin
@(err_event);
error_detected = 1'b1;
-> test_end;
@(testcase_log_written);
log.report_test_failed(msg);
if (testcase.log.free == 0)
begin
`SEVERE_ERROR("Failed to write to log file(s)!");
end
log.verbose_err(tim, msg);
-> testbench_log_written;
`PROMPT;
end
end
begin
forever
begin
@(wrn_event);
if (testcase.log.free == 0)
begin
`SEVERE_ERROR("Failed to write to log file(s)!");
end
log.verbose_wrn(tim, msg);
-> testbench_log_written;
end
end
begin
forever
begin
@(msg_event);
if (testcase.log.free == 0)
begin
`SEVERE_ERROR("Failed to write to log file(s)!");
end
log.verbose_msg(tim, msg);
-> testbench_log_written;
end
end
begin
forever
begin
@(val_event);
if (testcase.log.free == 0)
begin
`SEVERE_ERROR("Failed to write to log file(s)!");
end
log.verbose_val(tim, msg, val);
-> testbench_log_written;
end
end
join
// Testcase (DEPENDENT) code
//###########################
// Initialization
task testcase_init;
begin:init
test_name = "Initialization of UART.";
@(testcase_log_written);
//
testbench_utilities.do_reset;
testbench_utilities.disable_clk_generators(1, 1, 1, 1);
testbench_utilities.set_device_tx_rx_clk_divisor(32'h1000);
testbench_utilities.set_wb_clock_period(100);
testbench_utilities.enable_clk_generators(1, 1, 1, 1);
#100;
testbench_utilities.release_reset;
//
uart_wb_utilities.write_dlr(16'h1000);
uart_wb_utilities.write_ier(8'h07);
uart_wb_utilities.write_fcr(8'hC0);
uart_wb_utilities.write_lcr(8'h03);
//
uart_device_utilities.set_rx_length(8);
uart_device_utilities.disable_rx_parity;
uart_device_utilities.set_rx_second_stop_bit(0);
//
uart_device_utilities.set_tx_length(8);
uart_device_utilities.disable_tx_parity;
uart_device_utilities.correct_tx_parity;
uart_device_utilities.correct_tx_frame;
uart_device_utilities.generate_tx_glitch(0);
-> test_end;
@(testcase_log_written);
end
endtask // testcase_init
// Testcase
task testcase_test;
begin:test
test_name = "Interrupt test.";
@(testcase_log_written);
fork
begin: test
uart_wb_utilities.write_char(8'hAA);
@(testbench.int_aserted);
`TC_MSG("INT ASSERTED!");
uart_wb_utilities.write_char(8'hAA);
@(testbench.int_released);
`TC_MSG("INT RELEASED!");
@(testbench.int_aserted);
`TC_MSG("INT ASSERTED!");
uart_wb_utilities.read_iir;
@(testbench.int_released);
`TC_MSG("INT RELEASED!");
end
begin: wait_end
@(testbench.i_uart_device.device_received_packet);
@(testbench.i_uart_device.device_received_packet);
repeat(2) @(testbench.i_uart_device.rx_clk);
disable test;
disable wait_clk;
end
begin: wait_clk
testbench_utilities.wait_for_num_of_wb_clk(32'h450000);
disable test;
disable wait_end;
end
join
repeat (4) @(posedge testbench.wb_clk);
# 100;
-> test_end;
@(testcase_log_written);
end
endtask // testcase_test
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module fifo_w16_d4_A_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module fifo_w16_d4_A (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd16;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
fifo_w16_d4_A_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_fifo_w16_d4_A_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
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