text stringlengths 59 71.4k |
|---|
`default_nettype none
module div_pipelined_latch #(
parameter N = 4
)(
//System
input wire iCLOCK,
input wire inRESET,
input wire iREMOVE,
//PREVIOUS
input wire iPREVIOUS_VALID,
output wire oPREVIOUS_BUSY,
input wire iPREVIOUS_SIGN,
input wire [31:0] iPREVIOUS_DIVISOR,
input wire [31:0] iPREVIOUS_DIVIDEND,
input wire [N-1:0] iPREVIOUS_Q,
input wire [30:0] iPREVIOUS_R,
//NEXT
output wire oNEXT_VALID,
input wire iNEXT_BUSY,
output wire oNEXT_SIGN,
output wire [31:0] oNEXT_DIVISOR,
output wire [31:0] oNEXT_DIVIDEND,
output wire [N-1:0] oNEXT_Q,
output wire [30:0] oNEXT_R
);
reg b_valid;
reg b_sign;
reg [31:0] b_divisor;
reg [31:0] b_dividend;
reg [N-1:0] b_q;
reg [30:0] b_r;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_valid <= 1'b0;
b_sign <= 1'b0;
b_divisor <= {32{1'b0}};
b_dividend <= {32{1'b0}};
b_q <= {N{1'b0}};
b_r <= {31{1'b0}};
end
else if(iREMOVE)begin
b_valid <= 1'b0;
b_sign <= 1'b0;
b_divisor <= {32{1'b0}};
b_dividend <= {32{1'b0}};
b_q <= {N{1'b0}};
b_r <= {31{1'b0}};
end
else begin
if(!iNEXT_BUSY)begin
b_valid <= iPREVIOUS_VALID;
b_sign <= iPREVIOUS_SIGN;
b_divisor <= iPREVIOUS_DIVISOR;
b_dividend <= iPREVIOUS_DIVIDEND;
b_q <= iPREVIOUS_Q;
b_r <= iPREVIOUS_R;
end
end
end
assign oPREVIOUS_BUSY = iNEXT_BUSY;
assign oNEXT_VALID = b_valid;
assign oNEXT_SIGN = b_sign;
assign oNEXT_DIVISOR = b_divisor;
assign oNEXT_DIVIDEND = b_dividend;
assign oNEXT_Q = b_q;
assign oNEXT_R = b_r;
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; int n, m, c; int ans[1001]; int zero; inline void send(int x, int p) { if (ans[x] == 0) --zero; ans[x] = p; printf( %d n , x); fflush(stdout); } int main() { scanf( %d %d %d , &n, &m, &c); int mid = (c + 1) / 2; zero = n; for (int round = 1; zero && round <= m; ++round) { int p; scanf( %d , &p); if (p <= mid) { int i; for (i = 1; i < n; ++i) if (ans[i] == 0 || ans[i] > p) { break; } send(i, p); } else { int i; for (i = n; i > 1; --i) if (ans[i] == 0 || ans[i] < p) { break; } send(i, p); } } } |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
// Designer : Bob Hu
//
// Description:
// The Write-Back module to arbitrate the write-back request from all
// long pipe modules
//
// ====================================================================
`include "e203_defines.v"
module e203_exu_longpwbck(
//////////////////////////////////////////////////////////////
// The LSU Write-Back Interface
input lsu_wbck_i_valid, // Handshake valid
output lsu_wbck_i_ready, // Handshake ready
input [`E203_XLEN-1:0] lsu_wbck_i_wdat,
input [`E203_ITAG_WIDTH -1:0] lsu_wbck_i_itag,
input lsu_wbck_i_err , // The error exception generated
input lsu_cmt_i_buserr ,
input [`E203_ADDR_SIZE -1:0] lsu_cmt_i_badaddr,
input lsu_cmt_i_ld,
input lsu_cmt_i_st,
//////////////////////////////////////////////////////////////
// The Long pipe instruction Wback interface to final wbck module
output longp_wbck_o_valid, // Handshake valid
input longp_wbck_o_ready, // Handshake ready
output [`E203_FLEN-1:0] longp_wbck_o_wdat,
output [5-1:0] longp_wbck_o_flags,
output [`E203_RFIDX_WIDTH -1:0] longp_wbck_o_rdidx,
output longp_wbck_o_rdfpu,
//
// The Long pipe instruction Exception interface to commit stage
output longp_excp_o_valid,
input longp_excp_o_ready,
output longp_excp_o_insterr,
output longp_excp_o_ld,
output longp_excp_o_st,
output longp_excp_o_buserr , // The load/store bus-error exception generated
output [`E203_ADDR_SIZE-1:0] longp_excp_o_badaddr,
output [`E203_PC_SIZE -1:0] longp_excp_o_pc,
//
//The itag of toppest entry of OITF
input oitf_empty,
input [`E203_ITAG_WIDTH -1:0] oitf_ret_ptr,
input [`E203_RFIDX_WIDTH-1:0] oitf_ret_rdidx,
input [`E203_PC_SIZE-1:0] oitf_ret_pc,
input oitf_ret_rdwen,
input oitf_ret_rdfpu,
output oitf_ret_ena,
input clk,
input rst_n
);
// The Long-pipe instruction can write-back only when it's itag
// is same as the itag of toppest entry of OITF
wire wbck_ready4lsu = (lsu_wbck_i_itag == oitf_ret_ptr) & (~oitf_empty);
wire wbck_sel_lsu = lsu_wbck_i_valid & wbck_ready4lsu;
//assign longp_excp_o_ld = wbck_sel_lsu & lsu_cmt_i_ld;
//assign longp_excp_o_st = wbck_sel_lsu & lsu_cmt_i_st;
//assign longp_excp_o_buserr = wbck_sel_lsu & lsu_cmt_i_buserr;
//assign longp_excp_o_badaddr = wbck_sel_lsu ? lsu_cmt_i_badaddr : `E203_ADDR_SIZE'b0;
assign {
longp_excp_o_insterr
,longp_excp_o_ld
,longp_excp_o_st
,longp_excp_o_buserr
,longp_excp_o_badaddr } =
({`E203_ADDR_SIZE+4{wbck_sel_lsu}} &
{
1'b0,
lsu_cmt_i_ld,
lsu_cmt_i_st,
lsu_cmt_i_buserr,
lsu_cmt_i_badaddr
})
;
//////////////////////////////////////////////////////////////
// The Final arbitrated Write-Back Interface
wire wbck_i_ready;
wire wbck_i_valid;
wire [`E203_FLEN-1:0] wbck_i_wdat;
wire [5-1:0] wbck_i_flags;
wire [`E203_RFIDX_WIDTH-1:0] wbck_i_rdidx;
wire [`E203_PC_SIZE-1:0] wbck_i_pc;
wire wbck_i_rdwen;
wire wbck_i_rdfpu;
wire wbck_i_err ;
assign lsu_wbck_i_ready = wbck_ready4lsu & wbck_i_ready;
assign wbck_i_valid = ({1{wbck_sel_lsu}} & lsu_wbck_i_valid)
;
`ifdef E203_FLEN_IS_32 //{
wire [`E203_FLEN-1:0] lsu_wbck_i_wdat_exd = lsu_wbck_i_wdat;
`else//}{
wire [`E203_FLEN-1:0] lsu_wbck_i_wdat_exd = {{`E203_FLEN-`E203_XLEN{1'b0}},lsu_wbck_i_wdat};
`endif//}
assign wbck_i_wdat = ({`E203_FLEN{wbck_sel_lsu}} & lsu_wbck_i_wdat_exd )
;
assign wbck_i_flags = 5'b0
;
assign wbck_i_err = wbck_sel_lsu & lsu_wbck_i_err
;
assign wbck_i_pc = oitf_ret_pc;
assign wbck_i_rdidx = oitf_ret_rdidx;
assign wbck_i_rdwen = oitf_ret_rdwen;
assign wbck_i_rdfpu = oitf_ret_rdfpu;
// If the instruction have no error and it have the rdwen, then it need to
// write back into regfile, otherwise, it does not need to write regfile
wire need_wbck = wbck_i_rdwen & (~wbck_i_err);
// If the long pipe instruction have error result, then it need to handshake
// with the commit module.
wire need_excp = wbck_i_err;
assign wbck_i_ready =
(need_wbck ? longp_wbck_o_ready : 1'b1)
& (need_excp ? longp_excp_o_ready : 1'b1);
assign longp_wbck_o_valid = need_wbck & wbck_i_valid & (need_excp ? longp_excp_o_ready : 1'b1);
assign longp_excp_o_valid = need_excp & wbck_i_valid & (need_wbck ? longp_wbck_o_ready : 1'b1);
assign longp_wbck_o_wdat = wbck_i_wdat ;
assign longp_wbck_o_flags = wbck_i_flags ;
assign longp_wbck_o_rdfpu = wbck_i_rdfpu ;
assign longp_wbck_o_rdidx = wbck_i_rdidx;
assign longp_excp_o_pc = wbck_i_pc;
assign oitf_ret_ena = wbck_i_valid & wbck_i_ready;
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010, 2011 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Generate ack signal from early ack signal and mask strobe.
* After an early acked write, it should pulse after 2 cycles.
* After an early acked read, it should pulse after CL+3 cycles, that is
* 5 cycles when tim_cas = 0 (assumed here)
* 6 cycles when tim_cas = 1
*/
module fmlarb_dack(
input sys_clk,
input sys_rst,
input stb,
input eack,
input we,
output stbm,
output reg ack
);
wire read = eack & ~we;
wire write = eack & we;
reg ack_read2;
reg ack_read1;
reg ack_read0;
always @(posedge sys_clk) begin
if(sys_rst) begin
ack_read2 <= 1'b0;
ack_read1 <= 1'b0;
ack_read0 <= 1'b0;
end else begin
ack_read2 <= read;
ack_read1 <= ack_read2;
ack_read0 <= ack_read1;
end
end
reg ack0;
always @(posedge sys_clk) begin
if(sys_rst) begin
ack0 <= 1'b0;
ack <= 1'b0;
end else begin
ack0 <= ack_read0|write;
ack <= ack0;
end
end
reg mask;
assign stbm = stb & ~mask;
always @(posedge sys_clk) begin
if(sys_rst)
mask <= 1'b0;
else begin
if(eack)
mask <= 1'b1;
if(ack)
mask <= 1'b0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void umax(T &a, T b) { if (a < b) a = b; } template <class T> inline void umin(T &a, T b) { if (a > b) a = b; } const int N = 2e5; long long X, Y, x[N], y[N]; long long nx, bx; long long ny, by; long long basx, basy; int main() { cin >> nx >> bx; for (int i = 1; i <= nx; i++) cin >> x[i]; cin >> ny >> by; for (int i = 1; i <= ny; i++) cin >> y[i]; basx = basy = 1; for (int i = nx; i >= 1; i--) { X += basx * x[i]; basx *= bx; } for (int i = ny; i >= 1; i--) { Y += basy * y[i]; basy *= by; } if (X < Y) cout << < ; else if (X > Y) cout << > ; else cout << = ; return !1; } |
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module seven_seg(
input wire[31:0] disp_num,
input clk,
input wire clr,
input wire[1:0]SW,
input wire[1:0]Scanning,
input wire [3:0] dpdot,
output wire[7:0]SEGMENT,
output reg[3:0]AN
);
reg[3:0] digit;
reg[7:0] temp_seg,digit_seg;
wire[15:0] disp_current;
assign SEGMENT=SW[0]?digit_seg:temp_seg;
assign disp_current=SW[1]?disp_num[31:16]:disp_num[15:0];
always @(*)begin
case(Scanning)
0:begin
digit = disp_current[3:0];
temp_seg={disp_num[24],disp_num[12],disp_num[5],disp_num[17],
disp_num[25],disp_num[16],disp_num[4],disp_num[0]};
AN = 4'b1110;
end
1:begin
digit = disp_current[7:4];
temp_seg={disp_num[26],disp_num[13],disp_num[7],disp_num[19],
disp_num[27],disp_num[18],disp_num[6],disp_num[1]};
AN = 4'b1101;
end
2:begin
digit = disp_current[11:8];
temp_seg={disp_num[28],disp_num[14],disp_num[9],disp_num[21],
disp_num[29],disp_num[20],disp_num[8],disp_num[2]};
AN = 4'b1011;
end
3:begin
digit = disp_current[15:12];
temp_seg={disp_num[30],disp_num[15],disp_num[11],disp_num[23],
disp_num[31],disp_num[22],disp_num[10],disp_num[3]};
AN = 4'b0111;
end
endcase
end
/*
always @(*)begin
case(Scanning)
0:begin
digit = disp_current[3:0];
temp_seg={disp_num[24],disp_num[0],disp_num[4],disp_num[16],
disp_num[25],disp_num[17],disp_num[5],disp_num[12]};
AN = 4'b1110;
end
1:begin
digit = disp_current[7:4];
temp_seg={disp_num[26],disp_num[1],disp_num[6],disp_num[18],
disp_num[27],disp_num[19],disp_num[7],disp_num[13]};
AN = 4'b1101;
end
2:begin
digit = disp_current[11:8];
temp_seg={disp_num[28],disp_num[2],disp_num[8],disp_num[20],
disp_num[29],disp_num[21],disp_num[9],disp_num[14]};
AN = 4'b1011;
end
3:begin
digit = disp_current[15:12];
temp_seg={disp_num[30],disp_num[3],disp_num[10],disp_num[22],
disp_num[31],disp_num[23],disp_num[11],disp_num[15]};
AN = 4'b0111;
end
endcase
end
*/
always @(*)begin
case(digit)
0: digit_seg = 7'b1000000;
1: digit_seg = 7'b1111001;
2: digit_seg = 7'b0100100;
3: digit_seg = 7'b0110000;
4: digit_seg = 7'b0011001;
5: digit_seg = 7'b0010010;
6: digit_seg = 7'b0000010;
7: digit_seg = 7'b1111000;
8: digit_seg = 7'b0000000;
9: digit_seg = 7'b0010000;
'hA: digit_seg = 7'b0001000;
'hB: digit_seg = 7'b0000011;
'hC: digit_seg = 7'b1000110;
'hD: digit_seg = 7'b0100001;
'hE: digit_seg = 7'b0000110;
'hF: digit_seg = 7'b0001110;
default: digit_seg = 7'b1000000;
endcase
digit_seg[7] = ~dpdot[Scanning];
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.92
// \ \ Application: MIG
// / / Filename: iodelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:00 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// This module instantiates the IDELAYCTRL primitive, which continously
// calibrates the IODELAY elements in the region to account for varying
// environmental conditions. A 200MHz or 300MHz reference clock (depending
// on the desired IODELAY tap resolution) must be supplied
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: iodelay_ctrl.v,v 1.1 2011/06/02 07:18:00 mishra Exp $
**$Date: 2011/06/02 07:18:00 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ip_top/iodelay_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module iodelay_ctrl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter IODELAY_GRP = "IODELAY_MIG", // May be assigned unique name when
// multiple IP cores used in design
parameter INPUT_CLK_TYPE = "DIFFERENTIAL", // input clock type
// "DIFFERENTIAL","SINGLE_ENDED"
parameter RST_ACT_LOW = 1 // Reset input polarity
// (0 = active high, 1 = active low)
)
(
input clk_ref_p,
input clk_ref_n,
input clk_ref,
input sys_rst,
output iodelay_ctrl_rdy
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
wire clk_ref_bufg;
wire clk_ref_ibufg;
wire rst_ref;
reg [RST_SYNC_NUM-1:0] rst_ref_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp_idelay;
wire sys_rst_act_hi;
//***************************************************************************
// Possible inversion of system reset as appropriate
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst;
//***************************************************************************
// Input buffer for IDELAYCTRL reference clock - handle either a
// differential or single-ended input
//***************************************************************************
generate
if (INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref
IBUFGDS #
(
.DIFF_TERM ("TRUE"),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_p),
.IB (clk_ref_n),
.O (clk_ref_ibufg)
);
end else if (INPUT_CLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref),
.O (clk_ref_ibufg)
);
end
endgenerate
//***************************************************************************
// Global clock buffer for IDELAY reference clock
//***************************************************************************
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
//*****************************************************************
// IDELAYCTRL reset
// This assumes an external clock signal driving the IDELAYCTRL
// blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
// lock signal will need to be incorporated in this.
//*****************************************************************
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi;
always @(posedge clk_ref_bufg or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r <= #TCQ rst_ref_sync_r << 1;
assign rst_ref = rst_ref_sync_r[RST_SYNC_NUM-1];
//*****************************************************************
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY (iodelay_ctrl_rdy),
.REFCLK (clk_ref_bufg),
.RST (rst_ref)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using vvi = vector<vi>; using vll = vector<ll>; using vvll = vector<vll>; using vb = vector<bool>; using vd = vector<double>; using vs = vector<string>; using pii = pair<int, int>; using pll = pair<ll, ll>; using pdd = pair<double, double>; using vpii = vector<pii>; using vvpii = vector<vpii>; using vpll = vector<pll>; using vvpll = vector<vpll>; using vpdd = vector<pdd>; using vvpdd = vector<vpdd>; template <typename T> void ckmin(T& a, const T& b) { a = min(a, b); } template <typename T> void ckmax(T& a, const T& b) { a = max(a, b); } mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); namespace __input { template <class T1, class T2> void re(pair<T1, T2>& p); template <class T> void re(vector<T>& a); template <class T, size_t SZ> void re(array<T, SZ>& a); template <class T> void re(T& x) { cin >> x; } void re(double& x) { string t; re(t); x = stod(t); } template <class Arg, class... Args> void re(Arg& first, Args&... rest) { re(first); re(rest...); } template <class T1, class T2> void re(pair<T1, T2>& p) { re(p.first, p.second); } template <class T> void re(vector<T>& a) { for (int i = 0; i < (int((a).size())); i++) re(a[i]); } template <class T, size_t SZ> void re(array<T, SZ>& a) { for (int i = 0; i < (SZ); i++) re(a[i]); } } // namespace __input using namespace __input; namespace __output { template <class T1, class T2> void pr(const pair<T1, T2>& x); template <class T, size_t SZ> void pr(const array<T, SZ>& x); template <class T> void pr(const vector<T>& x); template <class T> void pr(const deque<T>& x); template <class T> void pr(const set<T>& x); template <class T1, class T2> void pr(const map<T1, T2>& x); template <class T> void pr(const T& x) { cout << x; } template <class Arg, class... Args> void pr(const Arg& first, const Args&... rest) { pr(first); pr(rest...); } template <class T1, class T2> void pr(const pair<T1, T2>& x) { pr( { , x.first, , , x.second, } ); } template <class T, bool pretty = true> void prContain(const T& x) { if (pretty) pr( { ); bool fst = 1; for (const auto& a : x) pr(!fst ? pretty ? , : : , a), fst = 0; if (pretty) pr( } ); } template <class T> void pc(const T& x) { prContain<T, false>(x); pr( n ); } template <class T, size_t SZ> void pr(const array<T, SZ>& x) { prContain(x); } template <class T> void pr(const vector<T>& x) { prContain(x); } template <class T> void pr(const deque<T>& x) { prContain(x); } template <class T> void pr(const set<T>& x) { prContain(x); } template <class T1, class T2> void pr(const map<T1, T2>& x) { prContain(x); } void ps() { pr( n ); } template <class Arg> void ps(const Arg& first) { pr(first); ps(); } template <class Arg, class... Args> void ps(const Arg& first, const Args&... rest) { pr(first, ); ps(rest...); } } // namespace __output using namespace __output; namespace __algorithm { template <typename T> void dedup(vector<T>& v) { sort((v).begin(), (v).end()); v.erase(unique((v).begin(), (v).end()), v.end()); } template <typename T> typename vector<T>::iterator find(vector<T>& v, const T& x) { auto it = lower_bound((v).begin(), (v).end(), x); return it != v.end() && *it == x ? it : v.end(); } template <typename T> size_t index(vector<T>& v, const T& x) { auto it = find(v, x); assert(it != v.end() && *it == x); return it - v.begin(); } template <typename C, typename T, typename OP> vector<T> prefixes(const C& v, T id, OP op) { vector<T> r(int((v).size()) + 1, id); for (int i = 0; i < (int((v).size())); i++) r[i + 1] = op(r[i], v[i]); return r; } template <typename C, typename T, typename OP> vector<T> suffixes(const C& v, T id, OP op) { vector<T> r(int((v).size()) + 1, id); for (int i = (int((v).size())) - 1; i >= 0; i--) r[i] = op(v[i], r[i + 1]); return r; } } // namespace __algorithm using namespace __algorithm; struct monostate { friend istream& operator>>(istream& is, const __attribute__((unused)) monostate& ms) { return is; } friend ostream& operator<<(ostream& os, const __attribute__((unused)) monostate& ms) { return os; } } ms; template <typename W = monostate> struct wedge { int u, v, i; W w; wedge<W>(int _u = -1, int _v = -1, int _i = -1) : u(_u), v(_v), i(_i) {} int operator[](int loc) const { return u ^ v ^ loc; } friend void re(wedge& e) { re(e.u, e.v, e.w); --e.u, --e.v; } friend void pr(const wedge& e) { pr(e.u, <- , e.w, -> , e.v); } }; namespace __io { void setIn(string second) { freopen(second.c_str(), r , stdin); } void setOut(string second) { freopen(second.c_str(), w , stdout); } void setIO(string second = ) { ios_base::sync_with_stdio(0); cin.tie(0); cout.precision(15); if (int((second).size())) { setIn(second + .in ), setOut(second + .out ); } } } // namespace __io using namespace __io; struct uf_monostate { uf_monostate(__attribute__((unused)) int id) {} void merge(__attribute__((unused)) uf_monostate& o, __attribute__((unused)) const monostate& e) {} }; template <typename T = uf_monostate, typename E = monostate> struct union_find { struct node { int par, rnk, size; T state; node(int id = 0) : par(id), rnk(0), size(1), state(id) {} void merge(node& o, E& e) { if (rnk == o.rnk) rnk++; if (size < o.size) swap(state, o.state); size += o.size; state.merge(o.state, e); } }; int cc; vector<node> uf; union_find(int N = 0) : uf(N), cc(N) { for (int i = 0; i < N; i++) uf[i] = node(i); } int rep(int i) { if (i != uf[i].par) uf[i].par = rep(uf[i].par); return uf[i].par; } bool unio(int a, int b, E& e = ms) { a = rep(a), b = rep(b); if (a == b) return false; if (uf[a].rnk < uf[b].rnk) swap(a, b); uf[a].merge(uf[b], e); uf[b].par = a; cc--; return true; } T& state(int i) { return uf[rep(i)].state; } }; int main() { setIO(); int N, S; re(N, S); vi a(N); re(a); vi ti(N); vi st = a, did(N); sort((st).begin(), (st).end()); vvi occ(N); for (int i = 0; i < (N); i++) if (a[i] != st[i]) { int w = index(st, a[i]); while (a[w + did[w]] == st[w + did[w]]) did[w]++; ti[i] = w + did[w]++; occ[w].push_back(i); } else ti[i] = i; vb vis(N); union_find<> uf(N); for (int i = 0; i < (N); i++) if (!vis[i]) { vis[i] = true; for (int t = ti[i]; t != i; t = ti[t]) { uf.unio(i, t); vis[t] = true; } } for (int i = 0; i < (N); i++) for (int j = 0; j < (int((occ[i]).size()) - 1); j++) { if (uf.unio(occ[i][j], occ[i][j + 1])) { swap(ti[occ[i][j]], ti[occ[i][j + 1]]); } } int wr = 0; for (int i = 0; i < (N); i++) if (a[i] != st[i]) wr++; if (wr > S) { ps(-1); return 0; } if (a == st) { ps(0); return 0; } vvi cyc; for (int i = 0; i < (N); i++) if (i == uf.rep(i) && i != ti[i]) { cyc.push_back({i + 1}); for (int t = ti[i]; t != i; t = ti[t]) cyc.back().push_back(t + 1); } int merge = min(S - wr, int((cyc).size())); if (merge > 2) { vi loop, fix; for (int c = (int((cyc).size()) - merge); c < (int((cyc).size())); c++) { loop.insert(loop.end(), (cyc[c]).begin(), (cyc[c]).end()); fix.push_back(cyc[c].front()); } reverse((fix).begin(), (fix).end()); cyc.erase(cyc.end() - merge, cyc.end()); cyc.push_back(loop); cyc.push_back(fix); } ps(int((cyc).size())); for (auto& c : cyc) ps(int((c).size())), pc(c); return 0; } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3.1 (lin64) Build Fri Oct 20 14:20:00 MDT 2017
// Date : Fri Mar 9 12:16:02 2018
// Host : hwreg2.conveycomputer.com running 64-bit CentOS release 6.7 (Final)
// Command : write_verilog -force -mode synth_stub
// /netscratch/cbaronne/WX2_UIO_PRBS/DAY9/uvpt_100REF_25G_initclk/ip/aurora_64b66b_25p4G/aurora_64b66b_25p4G_stub.v
// Design : aurora_64b66b_25p4G
// Purpose : Stub declaration of top-level module interface
// Device : xcvu7p-flvb2104-2L-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "aurora_64b66b_v11_2_2, Coregen v14.3_ip3, Number of lanes = 1, Line rate is double25.4Gbps, Reference Clock is double100.0MHz, Interface is Framing, Flow Control is None and is operating in DUPLEX configuration" *)
module aurora_64b66b_25p4G(s_axi_tx_tdata, s_axi_tx_tlast,
s_axi_tx_tkeep, s_axi_tx_tvalid, s_axi_tx_tready, m_axi_rx_tdata, m_axi_rx_tlast,
m_axi_rx_tkeep, m_axi_rx_tvalid, rxp, rxn, txp, txn, refclk1_in, hard_err, soft_err, channel_up,
lane_up, mmcm_not_locked, user_clk, sync_clk, reset_pb, gt_rxcdrovrden_in, power_down,
loopback, pma_init, gt_pll_lock, gt_qpllclk_quad1_in, gt_qpllrefclk_quad1_in,
gt_qplllock_quad1_in, gt_qpllrefclklost_quad1, gt_to_common_qpllreset_out,
s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
s_axi_wready, s_axi_bvalid, s_axi_bresp, s_axi_bready, s_axi_araddr, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rvalid, s_axi_rresp, s_axi_rready, init_clk,
link_reset_out, gt_powergood, sys_reset_out, bufg_gt_clr_out, tx_out_clk)
/* synthesis syn_black_box black_box_pad_pin="s_axi_tx_tdata[0:63],s_axi_tx_tlast,s_axi_tx_tkeep[0:7],s_axi_tx_tvalid,s_axi_tx_tready,m_axi_rx_tdata[0:63],m_axi_rx_tlast,m_axi_rx_tkeep[0:7],m_axi_rx_tvalid,rxp[0:0],rxn[0:0],txp[0:0],txn[0:0],refclk1_in,hard_err,soft_err,channel_up,lane_up[0:0],mmcm_not_locked,user_clk,sync_clk,reset_pb,gt_rxcdrovrden_in,power_down,loopback[2:0],pma_init,gt_pll_lock,gt_qpllclk_quad1_in,gt_qpllrefclk_quad1_in,gt_qplllock_quad1_in,gt_qpllrefclklost_quad1,gt_to_common_qpllreset_out,s_axi_awaddr[31:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bvalid,s_axi_bresp[1:0],s_axi_bready,s_axi_araddr[31:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rvalid,s_axi_rresp[1:0],s_axi_rready,init_clk,link_reset_out,gt_powergood[0:0],sys_reset_out,bufg_gt_clr_out,tx_out_clk" */;
input [0:63]s_axi_tx_tdata;
input s_axi_tx_tlast;
input [0:7]s_axi_tx_tkeep;
input s_axi_tx_tvalid;
output s_axi_tx_tready;
output [0:63]m_axi_rx_tdata;
output m_axi_rx_tlast;
output [0:7]m_axi_rx_tkeep;
output m_axi_rx_tvalid;
input [0:0]rxp;
input [0:0]rxn;
output [0:0]txp;
output [0:0]txn;
input refclk1_in;
output hard_err;
output soft_err;
output channel_up;
output [0:0]lane_up;
input mmcm_not_locked;
input user_clk;
input sync_clk;
input reset_pb;
input gt_rxcdrovrden_in;
input power_down;
input [2:0]loopback;
input pma_init;
output gt_pll_lock;
input gt_qpllclk_quad1_in;
input gt_qpllrefclk_quad1_in;
input gt_qplllock_quad1_in;
input gt_qpllrefclklost_quad1;
output gt_to_common_qpllreset_out;
input [31:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output s_axi_bvalid;
output [1:0]s_axi_bresp;
input s_axi_bready;
input [31:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output s_axi_rvalid;
output [1:0]s_axi_rresp;
input s_axi_rready;
input init_clk;
output link_reset_out;
output [0:0]gt_powergood;
output sys_reset_out;
output bufg_gt_clr_out;
output tx_out_clk;
endmodule
|
// DESCRIPTION: Verilator: Check initialisation of cloned clock variables
//
// This tests issue 1327 (Strange initialisation behaviour with
// "VinpClk" cloned clock variables)
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Rupert Swarbrick (Argon Design).
// SPDX-License-Identifier: CC0-1.0
// bug1327
// This models some device under test with an asynchronous reset pin
// which counts to 15.
module dut (input wire clk,
input wire rst_n,
output wire done);
reg [3:0] counter;
always @(posedge clk or negedge rst_n) begin
if (rst_n & ! clk) begin
$display("[%0t] %%Error: Oh dear! 'always @(posedge clk or negedge rst_n)' block triggered with clk=%0d, rst_n=%0d.",
$time, clk, rst_n);
$stop;
end
if (! rst_n) begin
counter <= 4'd0;
end else begin
counter <= counter < 4'd15 ? counter + 4'd1 : counter;
end
end
assign done = rst_n & (counter == 4'd15);
endmodule
module t(input wire clk,
input wire rst_n);
wire dut_done;
// A small FSM for driving the test
//
// This is just designed to be enough to force Verilator to make a
// "VinpClk" variant of dut_rst_n.
// Possible states:
//
// 0: Device in reset
// 1: Device running
// 2: Device finished
reg [1:0] state;
always @(posedge clk or negedge rst_n) begin
if (! rst_n) begin
state <= 0;
end else begin
if (state == 2'd0) begin
// One clock after resetting the device, we switch to running
// it.
state <= 2'd1;
end
else if (state == 2'd1) begin
// If the device is running, we switch to finished when its
// done signal goes high.
state <= dut_done ? 2'd2 : 2'd1;
end
else begin
// If the dut has finished, the test is done.
$write("*-* All Finished *-*\n");
$finish;
end
end
end
wire dut_rst_n = rst_n & (state != 0);
wire done;
dut dut_i (.clk (clk),
.rst_n (dut_rst_n),
.done (dut_done));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__EDFXBP_FUNCTIONAL_PP_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_lp__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__EDFXBP_FUNCTIONAL_PP_V |
//altclkctrl CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Cyclone IV E" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
//VERSION_BEGIN 16.1 cbx_altclkbuf 2016:11:22:18:30:39:SJ cbx_cycloneii 2016:11:22:18:30:39:SJ cbx_lpm_add_sub 2016:11:22:18:30:39:SJ cbx_lpm_compare 2016:11:22:18:30:39:SJ cbx_lpm_decode 2016:11:22:18:30:39:SJ cbx_lpm_mux 2016:11:22:18:30:39:SJ cbx_mgl 2016:11:22:19:17:36:SJ cbx_nadder 2016:11:22:18:30:39:SJ cbx_stratix 2016:11:22:18:30:39:SJ cbx_stratixii 2016:11:22:18:30:39:SJ cbx_stratixiii 2016:11:22:18:30:39:SJ cbx_stratixv 2016:11:22:18:30:39:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = clkctrl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module clckctrl_altclkctrl_0_sub
(
ena,
inclk,
outclk) /* synthesis synthesis_clearbox=1 */;
input ena;
input [3:0] inclk;
output outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ena;
tri0 [3:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_clkctrl1_outclk;
wire [1:0] clkselect;
wire [1:0] clkselect_wire;
wire [3:0] inclk_wire;
cycloneive_clkctrl clkctrl1
(
.clkselect(clkselect_wire),
.ena(ena),
.inclk(inclk_wire),
.outclk(wire_clkctrl1_outclk)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
clkctrl1.clock_type = "Global Clock",
clkctrl1.ena_register_mode = "falling edge",
clkctrl1.lpm_type = "cycloneive_clkctrl";
assign
clkselect = {2{1'b0}},
clkselect_wire = {clkselect},
inclk_wire = {inclk},
outclk = wire_clkctrl1_outclk;
endmodule //clckctrl_altclkctrl_0_sub
//VALID FILE // (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clckctrl_altclkctrl_0 (
ena,
inclk,
outclk);
input ena;
input inclk;
output outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ena;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire outclk;
wire sub_wire1;
wire [3:0] sub_wire2;
wire [2:0] sub_wire3;
assign outclk = sub_wire0;
assign sub_wire1 = inclk;
assign sub_wire2[3:0] = {sub_wire3, sub_wire1};
assign sub_wire3[2:0] = 3'h0;
clckctrl_altclkctrl_0_sub clckctrl_altclkctrl_0_sub_component (
.ena (ena),
.inclk (sub_wire2),
.outclk (sub_wire0));
endmodule |
#include <bits/stdc++.h> using namespace std; struct node { vector<int> adj; } graf[5 * 10010]; bool mark[5 * 10010]; int last[5 * 10010]; void DFS(int u, int lst) { last[u] = lst; mark[u] = true; for (int i = 0; i < graf[u].adj.size(); i++) if (!mark[graf[u].adj[i]]) DFS(graf[u].adj[i], u); } int main() { int n, r1, r2; scanf( %d%d%d , &n, &r1, &r2); for (int i = 1; i <= n; i++) { if (i == r1) continue; int tmp; scanf( %d , &tmp); graf[i].adj.push_back(tmp); graf[tmp].adj.push_back(i); } DFS(r2, 0); for (int i = 1; i <= n; i++) { if (i == r2) continue; printf( %d , last[i]); } printf( n ); return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of aou
//
// Generated
// by: wig
// on: Mon Jun 26 16:38:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../nreset2.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: aou.v,v 1.3 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: aou.v,v $
// Revision 1.3 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of aou
//
// No user `defines in this module
module aou
//
// Generated Module aou_i1
//
(
reset_i_n // Async. Reset (CGU,PAD)
);
// Generated Module Inputs:
input reset_i_n;
// Generated Wires:
wire reset_i_n;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of aou
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int N = 3E6 + 5; const int M = 3E6 + 5; struct map { int l, r; } Q[M]; int n, m, k, len, tr[N * 4], u, x, P[N], tot; char s[N], ans[N], ch; void add(int p, int l, int r, int x) { if (x < l || x > r) return; tr[p]++; if (l == r) return; int mid = (l + r) / 2; add(p * 2, l, mid, x); add(p * 2 + 1, mid + 1, r, x); } int get(int x) { for (int p = 1, l = 1, r = k;;) { if (l == r) return x == 1 && !tr[p] ? l : k + 1; int mid = (l + r) / 2; if (mid - l + 1 - tr[p * 2] < x) { x -= mid - l + 1 - tr[p * 2]; l = mid + 1; p = p * 2 + 1; } else r = mid, p *= 2; } } int main() { while (ch = getchar(), ch != n && tot < N) s[tot++] = ch; if (ch != n ) while (ch = getchar(), ch != n ) ; scanf( %d%d , &k, &n); for (int i = 1; i <= n; i++) scanf( %d%d , &Q[i].l, &Q[i].r); for (int i = n; i; i--) { len = Q[i].r - Q[i].l + 1; u = 1; for (int j = Q[i].l + 1; j <= Q[i].r && Q[i].r + u <= k; j += 2) { x = get(Q[i].r + 1); if (x > k) break; P[x] = get(j); u++; add(1, 1, k, x); } for (int j = Q[i].l; j <= Q[i].r && Q[i].r + u <= k; j += 2) { x = get(Q[i].r + 1); if (x > k) break; P[x] = get(j); u++; add(1, 1, k, x); } } u = 0; for (int i = 1; i <= k; i++) { if (!P[i]) ans[i] = s[u++]; else ans[i] = ans[P[i]]; putchar(ans[i]); } } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; long long int h1[n + 1], h[n + 1]; for (int i = 1; i <= n; i++) cin >> h[i]; for (int i = 1; i <= n; i++) cin >> h1[i]; long long int dp[n + 1][2]; dp[1][0] = h[1]; dp[1][1] = h1[1]; dp[0][0] = 0; dp[0][1] = 0; for (int i = 2; i <= n; i++) { long long int q = max(dp[i - 1][1], dp[i - 2][0]); q = max(q, dp[i - 2][1]); dp[i][0] = q + h[i]; q = max(dp[i - 1][0], dp[i - 2][0]); q = max(q, dp[i - 2][1]); dp[i][1] = q + h1[i]; } long long int q = max(dp[n][0], dp[n][1]); q = max(q, dp[n - 1][0]); q = max(q, dp[n - 1][1]); cout << q; return 0; } |
#include <bits/stdc++.h> int main() { int n, i, j, cnt = 0, sum = 0, cost; scanf( %d %d , &n, &cost); int ara[n], ara2[100000]; for (i = 0; i < n; i++) { scanf( %d , &ara[i]); } std::sort(ara, ara + n); int x = 0, z = 0; for (i = 1; i <= cost; i++) { sum += i; cnt++; if (i == ara[x] && x < n) { cnt--; sum -= ara[x]; x++; continue; } if (sum > cost) { sum -= i; cnt--; i--; break; } else if (sum == cost) { ara2[z] = i; z++; break; } else { ara2[z] = i; z++; } } printf( %d n , cnt); for (j = 0; j < z; j++) printf( %d , ara2[j]); } |
//////////////////////////////////////////////////////////////////////
//// ////
//// bytefifo.v ////
//// ////
//// ////
//// A simple byte-wide FIFO with byte and free space counts ////
//// ////
//// Author(s): ////
//// Nathan Yawn () ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// This is an 8-entry, byte-wide, single-port FIFO. It can either
// push or pop a byte each clock cycle (but not both). It includes
// outputs indicating the number of bytes in the FIFO, and the number
// of bytes free - if you don't connect BYTES_FREE, the synthesis
// tool should eliminate the hardware to generate it.
//
// This attempts to use few resources. There is only 1 counter,
// and only 1 decoder. The FIFO works like a big shift register:
// bytes are always written to entry '0' of the FIFO, and older
// bytes are shifted toward entry '7' as newer bytes are added.
// The counter determines which entry the output reads.
//
// One caveat is that the DATA_OUT will glitch during a 'push'
// operation. If the output is being sent to another clock
// domain, you should register it first.
//
// Ports:
// CLK: Clock for all synchronous elements
// RST: Zeros the counter and all registers asynchronously
// DATA_IN: Data to be pushed into the FIFO
// DATA_OUT: Always shows the data at the head of the FIFO, 'XX' if empty
// PUSH_POPn: When high (and EN is high), DATA_IN will be pushed onto the
// FIFO and the count will be incremented at the next posedge
// of CLK (assuming the FIFO is not full). When low (and EN
// is high), the count will be decremented and the output changed
// to the next value in the FIFO (assuming FIFO not empty).
// EN: When high at posedege CLK, a push or pop operation will be performed,
// based on the value of PUSH_POPn, assuming sufficient data or space.
// BYTES_AVAIL: Number of bytes in the FIFO. May be in the range 0 to 8.
// BYTES_FREE: Free space in the FIFO. May be in the range 0 to 8.
// Top module
module bytefifo (
CLK,
RST,
DATA_IN,
DATA_OUT,
PUSH_POPn,
EN,
BYTES_AVAIL,
BYTES_FREE
);
input CLK;
input RST;
input [7:0] DATA_IN;
output [7:0] DATA_OUT;
input PUSH_POPn;
input EN;
output [3:0] BYTES_AVAIL;
output [3:0] BYTES_FREE;
reg [7:0] reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
reg [3:0] counter;
reg [7:0] DATA_OUT;
wire [3:0] BYTES_AVAIL;
wire [3:0] BYTES_FREE;
wire push_ok;
wire pop_ok;
///////////////////////////////////
// Combinatorial assignments
assign BYTES_AVAIL = counter;
assign BYTES_FREE = 4'h8 - BYTES_AVAIL;
assign push_ok = !(counter == 4'h8);
assign pop_ok = !(counter == 4'h0);
///////////////////////////////////
// FIFO memory / shift registers
// Reg 0 - takes input from DATA_IN
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg0 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg0 <= DATA_IN;
end
// Reg 1 - takes input from reg0
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg1 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg1 <= reg0;
end
// Reg 2 - takes input from reg1
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg2 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg2 <= reg1;
end
// Reg 3 - takes input from reg2
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg3 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg3 <= reg2;
end
// Reg 4 - takes input from reg3
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg4 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg4 <= reg3;
end
// Reg 5 - takes input from reg4
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg5 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg5 <= reg4;
end
// Reg 6 - takes input from reg5
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg6 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg6 <= reg5;
end
// Reg 7 - takes input from reg6
always @ (posedge CLK or posedge RST)
begin
if(RST)
reg7 <= 8'h0;
else if(EN & PUSH_POPn & push_ok)
reg7 <= reg6;
end
///////////////////////////////////////////////////
// Read counter
// This is a 4-bit saturating up/down counter
// The 'saturating' is done via push_ok and pop_ok
always @ (posedge CLK or posedge RST)
begin
if(RST) counter <= 4'h0;
else if(EN & PUSH_POPn & push_ok) counter <= counter + 4'h1;
else if(EN & (~PUSH_POPn) & pop_ok) counter <= counter - 4'h1;
end
/////////////////////////////////////////////////
// Output decoder
always @ (counter or reg0 or reg1 or reg2 or reg3 or reg4 or reg5
or reg6 or reg7)
begin
case (counter)
4'h1: DATA_OUT <= reg0;
4'h2: DATA_OUT <= reg1;
4'h3: DATA_OUT <= reg2;
4'h4: DATA_OUT <= reg3;
4'h5: DATA_OUT <= reg4;
4'h6: DATA_OUT <= reg5;
4'h7: DATA_OUT <= reg6;
4'h8: DATA_OUT <= reg7;
default: DATA_OUT <= 8'hXX;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_BEHAVIORAL_V |
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Input Buffer
// /___/ /\ Filename : IBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:23 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 07/16/08 - Added IBUF_LOW_PWR attribute.
// 04/22/09 - CR 519127 - Changed IBUF_LOW_PWR default to TRUE.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUF (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
#1 $finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
#1 $finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
#1 $finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE);
#1 $finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
module ButtonCount(input clk, input button, output[7:0] segment, output[7:0] digit,
output TxD);
wire button_state, button_up, button_down;
debounce DB(
.clk (clk),
.button (button),
.button_state (button_state),
.button_up (button_up),
.button_down (button_down));
reg[3:0] d0 = 3'd0;
reg[3:0] d1 = 3'd0;
reg[3:0] d2 = 3'd0;
reg[3:0] d3 = 3'd0;
reg[3:0] d4 = 3'd0;
reg[3:0] d5 = 3'd0;
reg[3:0] d6 = 3'd0;
reg[3:0] d7 = 3'd0;
reg[2:0] sdigit = 0;
reg[3:0] sdigit_val = 3'd0;
wire hztick;
HZGenerator hz(
.clk(clk),
.tick(hztick)
);
always @(posedge clk)
begin
if (hztick)
sdigit <= sdigit + 3'd1;
end
reg[23:0] tx_to_send = 0;
reg send = 0;
always @(*)
begin
case (sdigit)
3'd0: begin sdigit_val = d0; end
3'd1: begin sdigit_val = d1; end
3'd2: begin sdigit_val = d2; end
3'd3: begin sdigit_val = d3; end
3'd4: begin sdigit_val = d4; end
3'd5: begin sdigit_val = d5; end
3'd6: begin sdigit_val = d6; end
3'd7: begin sdigit_val = d7; end
endcase
end
always @(posedge clk)
begin
send = button_up & ~send;
if (button_up)
begin
d0 = d0 + 3'd1;
tx_to_send = tx_to_send + 23'd1;
if (d0 == 10) begin d1 = d1 + 3'd1; d0 = 3'd0; end;
if (d1 == 10) begin d2 = d2 + 3'd1; d1 = 3'd0; end;
if (d2 == 10) begin d3 = d3 + 3'd1; d2 = 3'd0; end;
if (d3 == 10) begin d4 = d4 + 3'd1; d3 = 3'd0; end;
if (d4 == 10) begin d5 = d5 + 3'd1; d4 = 3'd0; end;
if (d5 == 10) begin d6 = d6 + 3'd1; d5 = 3'd0; end;
if (d6 == 10) begin d7 = d7 + 3'd1; d6 = 3'd0; end;
if (d7 == 10) begin d1 = d1 + 3'd1; d7 = 3'd0; end;
end
end
RS232TX rs232tx(
.clk(clk),
.Tx_start(send),
.dbuffer(tx_to_send),
.Tx(TxD)
);
LED led(
.clk(clk),
.enable(hztick),
.val (sdigit_val),
.sidx (sdigit),
.digit(digit),
.segment(segment));
endmodule |
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 11; const long long mod = 1e9 + 7; int n, m, k; long long a[N], ans; int par[N], sz[N]; pair<long long, pair<int, int> > b[N]; vector<pair<int, int> > v; vector<int> cur; bool u[N]; int find_set(int v) { if (v == par[v]) return v; return par[v] = find_set(par[v]); } void union_sets(int a, int b) { a = find_set(a); b = find_set(b); if (a != b) { if (sz[a] < sz[b]) swap(a, b); par[b] = a; sz[a] += sz[b]; } } long long binpow(int n) { long long a = 2, res = 1; while (n) { if (n % 2 == 0) { n /= 2; a = (a * a) % mod; } else { n--; res = (res * a) % mod; } } return res; } int main() { cin >> n >> m >> k; for (int i = 1; i <= n; i++) scanf( %I64d , &a[i]); for (int i = 1; i <= m; i++) { scanf( %d%d , &b[i].second.first, &b[i].second.second); b[i].first = a[b[i].second.first] ^ a[b[i].second.second]; } sort(b + 1, b + m + 1); int l = 0; int uniq = 0, comp; for (int i = 1; i <= m; i++) { if (b[i].first == b[i + 1].first) continue; comp = 0; for (int j = l + 1; j <= i; j++) v.push_back(b[j].second); for (auto i : v) { par[i.first] = i.first; par[i.second] = i.second; sz[i.first] = sz[i.second] = 1; } for (auto i : v) { if (!u[i.first]) cur.push_back(i.first); if (!u[i.second]) cur.push_back(i.second); u[i.first] = u[i.second] = true; } for (auto i : v) union_sets(i.first, i.second); for (auto i : cur) if (find_set(i) == i) comp++; ans = (ans + binpow(n - (int)cur.size() + comp)) % mod; for (auto i : cur) { u[i] = false; } cur.clear(); v.clear(); l = i; uniq++; } long long p = ((1ll << k) - uniq) % mod; p = (p * binpow(n)) % mod; ans = (ans + p) % mod; cout << ans; return 0; } |
//----------------------------------------------------------------------------
//-- rxleds: Uart-rx example 1
//-- The 4-bits less significant of the character received are shown in the
//-- red leds of the icestick board
//----------------------------------------------------------------------------
//-- (C) BQ. December 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//-- Top entity
module rxleds #(
parameter BAUDRATE = `B115200
)(
input wire clk, //-- System clock
input wire rx, //-- Serial input
output reg [3:0] leds //-- Red leds
);
//-- Received character signal
wire rcv;
//-- Received data
wire [7:0] data;
//-- Reset signal
reg rstn = 0;
//-- Initialization
always @(posedge clk)
rstn <= 1;
//-- Receiver unit instantation
uart_rx #(BAUDRATE)
RX0 (.clk(clk), //-- System clock
.rstn(rstn), //-- Reset (Active low)
.rx(rx), //-- Serial input
.rcv(rcv), //-- Character received notification (1)
.data(data) //-- Character received
);
//-- Register the character received and show its 4 less significant leds
//-- in the icestick leds
always @(posedge clk)
if (!rstn)
leds <= 0;
//-- When there is data available, capture it!
else if (rcv == 1'b1)
leds <= data[3:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1005; struct node { int u, v, val; } ans[maxn * 10]; std::vector<int> g[maxn]; int n, tot; int in[maxn]; int x[maxn], y[maxn], val[maxn]; void addedge(int u, int v, int val) { ans[++tot] = (node){u, v, val}; } void find(int u, int fa, int &x3, int &x4) { if (g[u].size() == 1) { if (x3 == 0) x3 = u; else x4 = u; return; } else for (int i = 0; i < g[u].size(); i++) { if (g[u][i] == fa) continue; find(g[u][i], u, x3, x4); } } int main() { scanf( %d , &n); if (n == 2) { printf( YES n1 n ); int x, y, k; scanf( %d%d%d , &x, &y, &k); printf( %d %d %d n , x, y, k); return 0; } for (int i = 1; i < n; i++) { scanf( %d%d%d , &x[i], &y[i], &val[i]); g[x[i]].push_back(y[i]); g[y[i]].push_back(x[i]); in[x[i]]++; in[y[i]]++; } for (int i = 1; i <= n; i++) if (in[i] == 2) return !printf( NO n ); printf( YES n ); for (int k = 1; k < n; k++) { if (in[x[k]] > in[y[k]]) swap(x[k], y[k]); if (in[x[k]] == 1) { int x4 = 0, x1 = 0, x2 = 0, x5 = 0, x3 = 0; x1 = y[k]; x3 = x[k]; find(x1, x3, x4, x5); addedge(x3, x4, val[k] / 2); addedge(x3, x5, val[k] / 2); addedge(x4, x5, -val[k] / 2); } else { int x1 = 0, x2 = 0, x3 = 0, x4 = 0, x5 = 0, x6 = 0; x1 = x[k]; x2 = y[k]; find(x1, x2, x3, x4); find(x2, x1, x5, x6); addedge(x3, x5, val[k] / 2); addedge(x4, x6, val[k] / 2); addedge(x3, x4, -val[k] / 2); addedge(x5, x6, -val[k] / 2); } } printf( %d n , tot); for (int i = 1; i <= tot; i++) { printf( %d %d %d n , ans[i].u, ans[i].v, ans[i].val); } } |
#include <bits/stdc++.h> using namespace std; const int inf = 2e9; const long long Inf = 1e10; const int P = 1e9 + 7; const int N = 100005; const int M = 1000005; inline long long IN() { long long x = 0; int ch = 0, f = 0; for (ch = getchar(); ch != -1 && (ch < 48 || ch > 57); ch = getchar()) f = (ch == - ); for (; ch >= 48 && ch <= 57; ch = getchar()) x = (x << 1) + (x << 3) + ch - 0 ; return f ? (-x) : x; } template <typename T> inline int chkmin(T &a, const T &b) { if (b < a) return a = b, 1; return 0; } template <typename T> inline int chkmax(T &a, const T &b) { if (b > a) return a = b, 1; return 0; } void renew(int &x, const int &y) { x += y; if (x >= P) x -= P; if (x < 0) x += P; } int Pow(int x, int y, int p) { int a = 1; for (; y; y >>= 1, x = (long long)x * x % p) if (y & 1) a = (long long)a * x % p; return a; } vector<pair<int, int> > in[M], ou[M]; int n, m, K; int cov[M << 2], sum[M << 2], len[M << 2]; int ql, qr, qv, qans; void Cov(int x, int y) { cov[x] = y; sum[x] = 1LL * len[x] * y % P; } void sep(int x) { if (cov[x] == -1) return; Cov(x << 1, cov[x]); Cov(x + x + 1, cov[x]); cov[x] = -1; } void A(int x, int L, int R) { if (ql <= L && R <= qr) { Cov(x, qv); return; } sep(x); int md = (L + R) >> 1; if (ql <= md) A(x << 1, L, md); if (md < qr) A(x + x + 1, md + 1, R); sum[x] = sum[x + x + 1]; renew(sum[x], sum[x << 1]); } void Add(int l, int r, int v) { if (l > r) return; ql = l; qr = r; qv = v; A(1, 1, m); } void Q(int x, int L, int R) { if (ql <= L && R <= qr) { renew(qans, sum[x]); return; } sep(x); int md = (L + R) >> 1; if (ql <= md) Q(x << 1, L, md); if (md < qr) Q(x + x + 1, md + 1, R); } int Ask(int l, int r) { if (l > r) return 0; ql = l; qr = r; qans = 0; Q(1, 1, m); return qans; } void B(int x, int L, int R) { len[x] = R - L + 1; if (L == R) return; int md = (L + R) / 2; B(x << 1, L, md); B(x + x + 1, md + 1, R); } set<pair<int, int> > st; int main() { scanf( %d%d%d , &n, &m, &K); for (int i = (int)(1); i <= (int)(K); i++) { int x1, y1, x2, y2; scanf( %d%d%d%d , &x1, &y1, &x2, &y2); in[x1].push_back(make_pair(y1, y2)); ou[x2 + 1].push_back(make_pair(y1, y2)); } B(1, 1, m); Add(1, 1, 1); for (auto v : in[1]) { st.insert(v); Add(v.first, v.second, 0); } for (int i = (int)(2); i <= (int)(n); i++) { static int tot, vx[N], vc[N]; tot = 0; for (auto v : in[i]) { if (v.second + 1 > m) continue; auto w = st.lower_bound(make_pair(v.second + 2, 0)); int Low = 0; if (w != st.begin()) { --w; Low = w->second; } ++tot; vc[tot] = Ask(Low + 1, v.second + 1); vx[tot] = v.second + 1; } for (int j = (int)(1); j <= (int)(tot); j++) Add(vx[j], vx[j], vc[j]); for (auto v : ou[i]) st.erase(v); for (auto v : in[i]) { st.insert(v); Add(v.first, v.second, 0); } } int Low = (st.empty()) ? (0) : ((--st.end())->second); cout << Ask(Low + 1, m) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } bool checkprime(long long n) { long long i = 2; while (i * i <= n) { if (n % i == 0) return 0; i++; } return 1; } long long fact(long long n) { if (n == 0) return 1; return n * fact(n - 1); } bool compare(const pair<long long, long long>& i, const pair<long long, long long>& j) { return i.first < j.first; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, m; cin >> n >> m; long long ans = 0; long long l[m + 1], r[m + 1], t[m + 1], c[m + 1]; for (long long i = 1; i <= m; i++) cin >> l[i] >> r[i] >> t[i] >> c[i]; for (long long i = 1; i <= n; i++) { long long mxc = 0, mx = 100000, mxi = -1; for (long long j = 1; j <= m; j++) { if (i >= l[j] && i <= r[j] && t[j] < mx) { mxi = j; mx = t[j]; mxc = c[j]; } } ans += mxc; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:100000000000 ) bool ascending(int i, int j) { return (i < j); } bool descending(int i, int j) { return (i > j); } using namespace std; const int MOD = 1000 * 1000 * 1000 + 7; unsigned long long powmod(unsigned long long a, unsigned long long b, unsigned long long m) { unsigned long long x = a, p = 1; while (b > 0) { if (b % 2) p = ((p % m) * (x % m)) % m; b /= 2; x = ((x % m) * (x % m)) % m; } return p; } int main() { int mersenne[] = {0, 2, 3, 5, 7, 13, 17, 19, 31, 61, 89, 107, 127, 521, 607, 1279, 2203, 2281, 3217, 4253, 4423, 9689, 9941, 11213, 19937, 21701, 23209, 44497, 86243, 110503, 132049, 216091, 756839, 859433, 1257787, 1398269, 2976221, 3021377, 6972593, 13466917, 20996011}; int n; cin >> n; cout << powmod(2, mersenne[n] - 1, MOD) - 1 << endl; } |
#include <bits/stdc++.h> using namespace std; long long int dp[1000005]; int a[30]; int main() { int t, k, i, j, n, m, x, y, q, c, d; dp[0] = 0; dp[1] = 0; for (i = 2; i < 1000005; i++) dp[i] = dp[i / 2] + dp[i - i / 2] + i / 2 * 1LL * (i - i / 2); cin >> k; if (k == 0) { cout << a ; return 0; } for (i = 0; i < 26 && k; i++) { int low = 0, high = 1000000, mid; while (low < high) { mid = low + (high - low + 1) / 2; if (dp[mid] <= k) low = mid; else high = mid - 1; } a[i] = low; k -= dp[low]; } for (i = 0; i < 26; i++) { char ch = a + i; if (a[i]) while (a[i]--) cout << ch; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, s, f, l, r, t; int stay() { int next = (s < f) ? s + 1 : s - 1; return (s >= l && s <= r) || (next >= l && next <= r); } int di[] = {0, 1}; int dj[] = {1, 0}; void write(vector<string> &res, int x, int y, int dir, string s) { for (int i = 0; i < s.size(); i++) { res[x][y] = s[i]; x += di[dir]; y += dj[dir]; } } void print(vector<string> res) { for (int i = 0; i < res.size(); i++) { for (int j = 0; j < res[i].size(); ++j) { cout << res[i][j]; } cout << endl; } } bool same(string a, string b, int i, int j) { return a[i] == b[j]; } int main() { vector<string> arr(6); vector<bool> vis(6, 0); for (int i = 0; i < 6; ++i) { cin >> arr[i]; } sort(arr.begin(), arr.end()); vector<string> best, res; do { if (!same(arr[0], arr[1], 0, 0) || !same(arr[4], arr[5], arr[4].size() - 1, arr[5].size() - 1)) continue; if (arr[3].size() != arr[0].size() + arr[4].size() - 1 || arr[2].size() != arr[1].size() + arr[5].size() - 1) continue; if (!same(arr[3], arr[2], arr[0].size() - 1, arr[1].size() - 1) || !same(arr[2], arr[0], 0, arr[0].size() - 1) || !same(arr[2], arr[4], arr[2].size() - 1, 0)) continue; if (!same(arr[3], arr[1], 0, arr[1].size() - 1) || !same(arr[3], arr[5], arr[3].size() - 1, 0)) continue; int n = arr[2].size(), m = arr[3].size(); string tmp = string(m, . ); res = vector<string>(n, tmp); write(res, 0, 0, 0, arr[0]); write(res, 0, 0, 1, arr[1]); write(res, 0, arr[0].size() - 1, 1, arr[2]); write(res, arr[1].size() - 1, 0, 0, arr[3]); write(res, n - 1, arr[0].size() - 1, 0, arr[4]); write(res, arr[1].size() - 1, m - 1, 1, arr[5]); if (!best.size() || best > res) best = res; } while (next_permutation(arr.begin(), arr.end())); if (!best.size()) cout << Impossible << endl; else print(best); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:39:29 10/01/2015
// Design Name:
// Module Name: Zero_InfMult_Unit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Zero_InfMult_Unit
//SINGLE PRECISION PARAMETERS
# (parameter W = 32)
//DOUBLE PRECISION PARAMETERS
/* # (parameter W = 64) */
(
input wire clk,
input wire rst,
input wire load,
input wire [W-2:0] Data_A,
input wire [W-2:0] Data_B,
output wire zero_m_flag
);
//Wires/////////////////////
wire or_1, or_2;
wire [W-2:0] zero_comp;
wire zero_reg;
////////////////////////////
Comparator_Equal #(.S(W-1)) Data_A_Comp (
.Data_A(Data_A),
.Data_B(zero_comp),
.equal_sgn(or_1)
);
Comparator_Equal #(.S(W-1)) Data_B_Comp (
.Data_A(zero_comp),
.Data_B(Data_B),
.equal_sgn(or_2)
);
RegisterAdd #(.W(1)) Zero_Info_Mult ( //Data X input register
.clk(clk),
.rst(rst),
.load(load),
.D(zero_reg),
.Q(zero_m_flag)
);
assign zero_reg = or_1 || or_2;
generate
if (W == 32)
assign zero_comp = 31'd0;
else
assign zero_comp = 63'd0;
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22OI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A22OI_FUNCTIONAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 102; pair<int, int> ar[N]; bool used[N]; vector<deque<int>> vc; int main() { int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> ar[i].first >> ar[i].second; for (int i = 1; i <= n; ++i) { if (used[i]) continue; deque<int> q; q.push_back(i); int cur = i; while (ar[cur].first) { used[cur] = true; cur = ar[cur].first; q.push_front(cur); } used[cur] = true; cur = i; while (ar[cur].second) { used[cur] = true; cur = ar[cur].second; q.push_back(cur); } used[cur] = true; vc.push_back(q); } for (int i = 1; i < vc.size(); ++i) { while (!vc[i].empty()) { vc[0].push_back(vc[i].front()); vc[i].pop_front(); } } auto cur = vc[0]; ar[cur.front()].first = ar[cur.back()].second = 0; for (int i = 0; i < (int)cur.size() - 1; ++i) ar[cur[i]].second = cur[i + 1]; for (int i = (int)cur.size() - 1; i > 0; --i) ar[cur[i]].first = cur[i - 1]; for (int i = 1; i <= n; ++i) cout << ar[i].first << << ar[i].second << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, result = 0; { cin >> n; float init = sqrt(n); if (init == floor(init)) cout << init * 4 << endl; else { int init2 = floor(init); n = n - init2 * init2; result = init2 * 4; if (n > init2) { int temp1 = n / 2; result = result + (temp1 + 1) * 2 - temp1 * 2; int temp2 = n - n / 2; result = result + (temp2 + 1) * 2 - temp2 * 2; } else result = result + (n + 1) * 2 - n * 2; cout << result << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { char a[100000]; int len, i, flag = 0, m; cin >> a; len = strlen(a); for (i = 0; i <= (len / 2); i++) { m = int(a[i]); if ((m == 65) || (m == 72) || (m == 73) || (m == 77) || (m == 79) || (m == 84) || (m == 85) || (m == 86) || (m == 87) || (m == 88) || (m == 89)) { if (int(a[len - 1 - i]) != m) { flag = 1; break; } } else { flag = 1; break; } } if (flag == 1) { cout << NO ; } else { cout << YES ; } } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: lsu_tagdp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module lsu_tagdp( /*AUTOARG*/
// Outputs
so, lsu_misc_rdata_w2, lsu_rd_dtag_parity_g,
// Inputs
rclk, si, se, lsu_va_wtchpt_addr, lsu_va_wtchpt_sel_g, dva_vld_m,
dtag_rdata_w0_m, dtag_rdata_w1_m, dtag_rdata_w2_m,
dtag_rdata_w3_m, lsu_dtag_rsel_m, lsu_local_ldxa_data_g,
lsu_local_ldxa_sel_g, lsu_tlb_rd_data, lsu_local_ldxa_tlbrd_sel_g,
lsu_local_diagnstc_tagrd_sel_g
);
input rclk;
input si;
input se;
output so;
input [47:3] lsu_va_wtchpt_addr ;
input lsu_va_wtchpt_sel_g;
input [3:0] dva_vld_m; // valid array read
input [29:0] dtag_rdata_w0_m; // 29b tag; 1b parity from dtag
input [29:0] dtag_rdata_w1_m; // 29b tag; 1b parity from dtag
input [29:0] dtag_rdata_w2_m; // 29b tag; 1b parity from dtag
input [29:0] dtag_rdata_w3_m; // 29b tag; 1b parity from dtag
input [3:0] lsu_dtag_rsel_m; // select one of the above tag from ??
input [47:0] lsu_local_ldxa_data_g; // from dctl
input lsu_local_ldxa_sel_g; //used to mux ldxa data with 1/4 tags. from ??
input [63:0] lsu_tlb_rd_data; // from tlbdp - used in local ldxa mux
input lsu_local_ldxa_tlbrd_sel_g;
input lsu_local_diagnstc_tagrd_sel_g;
output [63:0] lsu_misc_rdata_w2; // to qdp1
output [3:0] lsu_rd_dtag_parity_g; // parity check on 4 tags. to dctl
wire dtag_rdata_w0_parity_g,
dtag_rdata_w1_parity_g,
dtag_rdata_w2_parity_g,
dtag_rdata_w3_parity_g;
wire [29:0] dtag_rdata_sel_m,
dtag_rdata_sel_g;
wire [3:0] dtag_rdata_w0_8b_parity_m,
dtag_rdata_w1_8b_parity_m,
dtag_rdata_w2_8b_parity_m,
dtag_rdata_w3_8b_parity_m;
wire [3:0] dtag_rdata_w0_8b_parity_g,
dtag_rdata_w1_8b_parity_g,
dtag_rdata_w2_8b_parity_g,
dtag_rdata_w3_8b_parity_g;
wire [63:0] lsu_misc_rdata_g;
wire dtag_vld_sel_m, dtag_vld_sel_g;
wire clk;
assign clk = rclk;
//=================================================================================================
// Select Tag Read data / ldxa data
//=================================================================================================
// select 1 out of 4 tags
mux4ds #(31) dtag_rdata_sel (
.in0 ({dtag_rdata_w0_m[29:0],dva_vld_m[0]}),
.in1 ({dtag_rdata_w1_m[29:0],dva_vld_m[1]}),
.in2 ({dtag_rdata_w2_m[29:0],dva_vld_m[2]}),
.in3 ({dtag_rdata_w3_m[29:0],dva_vld_m[3]}),
.sel0 (lsu_dtag_rsel_m[0]),
.sel1 (lsu_dtag_rsel_m[1]),
.sel2 (lsu_dtag_rsel_m[2]),
.sel3 (lsu_dtag_rsel_m[3]),
.dout ({dtag_rdata_sel_m[29:0],dtag_vld_sel_m})
);
dff_s #(31) dtag_rdata_sel_g_ff (
.din ({dtag_rdata_sel_m[29:0],dtag_vld_sel_m}),
.q ({dtag_rdata_sel_g[29:0],dtag_vld_sel_g}),
.clk (clk),
.se (se), .si (), .so ());
mux4ds #(64) lsu_misc_rdata_sel (
.in0 ({16'h0,lsu_local_ldxa_data_g[47:0]}),
.in1 (lsu_tlb_rd_data[63:0]),
.in2 ({16'h0,lsu_va_wtchpt_addr[47:3],3'b000}),
.in3 ({33'h0,dtag_rdata_sel_g[29:0],dtag_vld_sel_g}),
.sel0 (lsu_local_ldxa_sel_g),
.sel1 (lsu_local_ldxa_tlbrd_sel_g),
.sel2 (lsu_va_wtchpt_sel_g),
.sel3 (lsu_local_diagnstc_tagrd_sel_g),
.dout (lsu_misc_rdata_g[63:0])
);
dff_s #(64) lsu_misc_rdata_w2_ff (
.din (lsu_misc_rdata_g[63:0]),
.q (lsu_misc_rdata_w2[63:0]),
.clk (clk),
.se (se), .si (), .so ());
//=================================================================================================
// Tag Parity Calculation
//=================================================================================================
// flop tag parity bits
dff_s #(4) dtag_rdata_parity_g_ff (
.din ({dtag_rdata_w0_m[29],
dtag_rdata_w1_m[29],
dtag_rdata_w2_m[29],
dtag_rdata_w3_m[29]}),
.q ({dtag_rdata_w0_parity_g,
dtag_rdata_w1_parity_g,
dtag_rdata_w2_parity_g,
dtag_rdata_w3_parity_g}),
.clk (clk),
.se (se), .si (), .so ());
// generate 8bit parity for all ways before g-flop
assign dtag_rdata_w0_8b_parity_m[0] = ^dtag_rdata_w0_m[7:0] ;
assign dtag_rdata_w0_8b_parity_m[1] = ^dtag_rdata_w0_m[15:8] ;
assign dtag_rdata_w0_8b_parity_m[2] = ^dtag_rdata_w0_m[23:16] ;
assign dtag_rdata_w0_8b_parity_m[3] = ^dtag_rdata_w0_m[28:24] ;
assign dtag_rdata_w1_8b_parity_m[0] = ^dtag_rdata_w1_m[7:0] ;
assign dtag_rdata_w1_8b_parity_m[1] = ^dtag_rdata_w1_m[15:8] ;
assign dtag_rdata_w1_8b_parity_m[2] = ^dtag_rdata_w1_m[23:16] ;
assign dtag_rdata_w1_8b_parity_m[3] = ^dtag_rdata_w1_m[28:24] ;
assign dtag_rdata_w2_8b_parity_m[0] = ^dtag_rdata_w2_m[7:0] ;
assign dtag_rdata_w2_8b_parity_m[1] = ^dtag_rdata_w2_m[15:8] ;
assign dtag_rdata_w2_8b_parity_m[2] = ^dtag_rdata_w2_m[23:16] ;
assign dtag_rdata_w2_8b_parity_m[3] = ^dtag_rdata_w2_m[28:24] ;
assign dtag_rdata_w3_8b_parity_m[0] = ^dtag_rdata_w3_m[7:0] ;
assign dtag_rdata_w3_8b_parity_m[1] = ^dtag_rdata_w3_m[15:8] ;
assign dtag_rdata_w3_8b_parity_m[2] = ^dtag_rdata_w3_m[23:16] ;
assign dtag_rdata_w3_8b_parity_m[3] = ^dtag_rdata_w3_m[28:24] ;
// g-flop for 8-bit parity for all 4 ways
dff_s #(4) dtag_rdata_w0_8b_parity_g_ff (
.din (dtag_rdata_w0_8b_parity_m[3:0]),
.q (dtag_rdata_w0_8b_parity_g[3:0]),
.clk (clk),
.se (se), .si (), .so ());
dff_s #(4) dtag_rdata_w1_8b_parity_g_ff (
.din (dtag_rdata_w1_8b_parity_m[3:0]),
.q (dtag_rdata_w1_8b_parity_g[3:0]),
.clk (clk),
.se (se), .si (), .so ());
dff_s #(4) dtag_rdata_w2_8b_parity_g_ff (
.din (dtag_rdata_w2_8b_parity_m[3:0]),
.q (dtag_rdata_w2_8b_parity_g[3:0]),
.clk (clk),
.se (se), .si (), .so ());
dff_s #(4) dtag_rdata_w3_8b_parity_g_ff (
.din (dtag_rdata_w3_8b_parity_m[3:0]),
.q (dtag_rdata_w3_8b_parity_g[3:0]),
.clk (clk),
.se (se), .si (), .so ());
assign lsu_rd_dtag_parity_g[0] = ^({dtag_rdata_w0_8b_parity_g[3:0],dtag_rdata_w0_parity_g});
assign lsu_rd_dtag_parity_g[1] = ^({dtag_rdata_w1_8b_parity_g[3:0],dtag_rdata_w1_parity_g});
assign lsu_rd_dtag_parity_g[2] = ^({dtag_rdata_w2_8b_parity_g[3:0],dtag_rdata_w2_parity_g});
assign lsu_rd_dtag_parity_g[3] = ^({dtag_rdata_w3_8b_parity_g[3:0],dtag_rdata_w3_parity_g});
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SDFXTP_BEHAVIORAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXTP_BEHAVIORAL_V |
module top;
reg signed [7:0] neg = -2;
reg signed [7:0] m1 = -1;
reg signed [7:0] zero = 0;
reg signed [7:0] one = 1;
reg signed [7:0] pos = 2;
reg signed [7:0] pose = 2;
reg signed [7:0] poso = 3;
reg signed [7:0] res;
wire signed [7:0] neg_pose = neg**pose;
wire signed [7:0] neg_poso = neg**poso;
wire signed [7:0] m1_pose = m1**pose;
wire signed [7:0] m1_poso = m1**poso;
wire signed [7:0] zero_pos = zero**pos;
wire signed [7:0] one_pos = one**pos;
wire signed [7:0] pos_pos = pos**pos;
wire signed [7:0] neg_zero = neg**zero;
wire signed [7:0] m1_zero = m1**zero;
wire signed [7:0] zero_zero = zero**zero;
wire signed [7:0] one_zero = one**zero;
wire signed [7:0] pos_zero = pos**zero;
wire signed [7:0] neg_neg = neg**m1;
wire signed [7:0] m1_nege = m1**neg;
wire signed [7:0] m1_nego = m1**m1;
wire signed [7:0] zero_neg = zero**m1;
wire signed [7:0] one_neg = one**m1;
wire signed [7:0] pos_neg = pos**m1;
reg pass;
initial begin
pass = 1'b1;
#1;
/* Positive exponent. */
if (neg_pose !== 4) begin
$display("Failed neg**pos even, got %d", neg_pose);
pass = 1'b0;
end
if (neg_poso !== -8) begin
$display("Failed neg**pos odd, got %d", neg_poso);
pass = 1'b0;
end
if (m1_pose !== 1) begin
$display("Failed -1**pos even, got %d", m1_pose);
pass = 1'b0;
end
if (m1_poso !== -1) begin
$display("Failed -1**pos odd, got %d", m1_poso);
pass = 1'b0;
end
if (zero_pos !== 0) begin
$display("Failed 0**pos, got %d", zero_pos);
pass = 1'b0;
end
if (one_pos !== 1) begin
$display("Failed 1**pos, got %d", one_pos);
pass = 1'b0;
end
if (pos_pos !== 4) begin
$display("Failed 1**pos, got %d", pos_pos);
pass = 1'b0;
end
/* Zero exponent. */
if (neg_zero !== 1) begin
$display("Failed neg**0, got %d", neg_zero);
pass = 1'b0;
end
if (m1_zero !== 1) begin
$display("Failed -1**0, got %d", m1_zero);
pass = 1'b0;
end
if (zero_zero !== 1) begin
$display("Failed 0**0, got %d", zero_zero);
pass = 1'b0;
end
if (one_zero !== 1) begin
$display("Failed 1**0, got %d", one_zero);
pass = 1'b0;
end
if (pos_zero !== 1) begin
$display("Failed pos**0, got %d", pos_zero);
pass = 1'b0;
end
/* Negative exponent. */
if (neg_neg !== 0) begin
$display("Failed neg**neg got %d", neg_neg);
pass = 1'b0;
end
if (m1_nege !== 1) begin
$display("Failed -1**neg (even) got %d", m1_nege);
pass = 1'b0;
end
if (m1_nego !== -1) begin
$display("Failed -1**neg (odd) got %d", m1_nego);
pass = 1'b0;
end
if (zero_neg !== 'sbx) begin
$display("Failed 0**neg (odd) got %d", zero_neg);
pass = 1'b0;
end
if (one_neg !== 1) begin
$display("Failed 1**neg got %d", one_neg);
pass = 1'b0;
end
if (pos_neg !== 0) begin
$display("Failed pos**neg got %d", pos_neg);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: pci2net_dma_16x32.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pci2net_dma_16x32 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [31:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [31:0] q;
output [3:0] usedw;
wire [3:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [31:0] sub_wire3;
wire sub_wire4;
wire [3:0] usedw = sub_wire0[3:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [31:0] q = sub_wire3[31:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_full_value = 9,
scfifo_component.intended_device_family = "Stratix IV",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 32,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "9"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "9"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 4 0 OUTPUT NODEFVAL "usedw[3..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: usedw 0 0 4 0 @usedw 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pci2net_dma_16x32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pci2net_dma_16x32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pci2net_dma_16x32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pci2net_dma_16x32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pci2net_dma_16x32_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pci2net_dma_16x32_bb.v TRUE
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9; const int Maxn = 1005; const int dx[] = {-1, 0, 1, 0}; const int dy[] = {0, 1, 0, -1}; struct pos { int first, second, third; }; string s; int n, k; pair<int, int> d[11111]; int main() { scanf( %d%d , &n, &k); cin >> s; int ans = INF; string as = ; string os = s; for (char c = 0 ; c <= 9 ; c++) { s = os; for (int(i) = 0; (i) < (int)(n); i++) d[i] = {abs(s[i] - c), s[i] >= c ? -(n - i) : n - i}; sort(d, d + n); int cur = 0; for (int(i) = 0; (i) < (int)(k); i++) { cur += d[i].first; int x = d[i].second; if (x < 0) x = -x; x = -x + n; s[x] = c; } if (cur < ans || (cur == ans && s < as)) { as = s; ans = cur; } } printf( %d n , ans); puts(as.c_str()); return 0; } |
/*******************************************************************************
* (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. *
* *
* This file contains confidential and proprietary information *
* of Xilinx, Inc. and is protected under U.S. and *
* international copyright and other intellectual property *
* laws. *
* *
* DISCLAIMER *
* This disclaimer is not a license and does not grant any *
* rights to the materials distributed herewith. Except as *
* otherwise provided in a valid license issued to you by *
* Xilinx, and to the maximum extent permitted by applicable *
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
* (2) Xilinx shall not be liable (whether in contract or tort, *
* including negligence, or under any other theory of *
* liability) for any loss or damage of any kind or nature *
* related to, arising under or in connection with these *
* materials, including for any direct, or any indirect, *
* special, incidental, or consequential loss or damage *
* (including loss of data, profits, goodwill, or any type of *
* loss or damage suffered as a result of any action brought *
* by a third party) even if such damage or loss was *
* reasonably foreseeable or Xilinx had been advised of the *
* possibility of the same. *
* *
* CRITICAL APPLICATIONS *
* Xilinx products are not designed or intended to be fail- *
* safe, or for use in any application requiring fail-safe *
* performance, such as life-support or safety devices or *
* systems, Class III medical devices, nuclear facilities, *
* applications related to the deployment of airbags, or any *
* other applications that could lead to death, personal *
* injury, or severe property or environmental damage *
* (individually and collectively, "Critical *
* Applications"). Customer assumes the sole risk and *
* liability of any use of Xilinx products in Critical *
* Applications, subject only to applicable laws and *
* regulations governing limitations on product liability. *
* *
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
* PART OF THIS FILE AT ALL TIMES. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file mem_ins.v when simulating
// the core, mem_ins. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module mem_ins(
a,
spo);
input [5 : 0] a;
output [31 : 0] spo;
// synthesis translate_off
DIST_MEM_GEN_V5_1 #(
.C_ADDR_WIDTH(6),
.C_DEFAULT_DATA("0"),
.C_DEPTH(64),
.C_FAMILY("spartan3"),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_SPRA(0),
.C_HAS_WE(0),
.C_MEM_INIT_FILE("mem_ins.mif"),
.C_MEM_TYPE(0),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(32))
inst (
.A(a),
.SPO(spo),
.D(),
.DPRA(),
.SPRA(),
.CLK(),
.WE(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.DPO(),
.QSPO(),
.QDPO());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of mem_ins is "black_box"
endmodule
|
#include <bits/stdc++.h> const long double EPS = 1e-10; const long long int MOD = 1000000007ll; const long long int mod1 = 1000000009ll; const long long int mod2 = 1100000009ll; int INF = (int)1e9; long long int INFINF = (long long int)1e18; int debug = 0; long double PI = acos(-1.0); using namespace std; long long int bit_count(long long int _x) { long long int _ret = 0; while (_x) { if (_x % 2 == 1) _ret++; _x /= 2; } return _ret; } long long int bit(long long int _mask, long long int _i) { return (_mask & (1 << _i)) == 0 ? 0 : 1; } long long int powermod(long long int _a, long long int _b, long long int _m = MOD) { long long int _r = 1; while (_b) { if (_b % 2 == 1) _r = (_r * _a) % _m; _b /= 2; _a = (_a * _a) % _m; } return _r; } long long int add(long long int a, long long int b, long long int m = MOD) { long long int x = a + b; while (x >= m) x -= m; while (x < 0) x += m; return x; } long long int sub(long long int a, long long int b, long long int m = MOD) { long long int x = a - b; while (x < 0) x += m; while (x >= m) x -= m; return x; } long long int mul(long long int a, long long int b, long long int m = MOD) { long long int x = a * 1ll * b; x %= m; if (x < 0) x += m; return x; } int N, M, K; vector<int> G[1010]; bool spec[1010]; bool vis[1010]; int tot, cnt; vector<int> sizes; void dfs(int u) { tot++; cnt++; vis[u] = true; for (int v : G[u]) { if (!vis[v]) { dfs(v); } } } int main() { if (0) { freopen( input.txt , r , stdin); debug = 1; } srand(time(NULL)); scanf( %d , &N); scanf( %d , &M); scanf( %d , &K); for (int i = 1; i <= K; i++) { int x; scanf( %d , &x); spec[x] = true; } for (int i = 1; i <= M; i++) { int u, v; scanf( %d , &u); scanf( %d , &v); G[u].push_back(v); G[v].push_back(u); } for (int i = 1; i <= N; i++) { if (spec[i]) { cnt = 0; dfs(i); sizes.push_back(cnt); } } sort(sizes.begin(), sizes.end()); reverse(sizes.begin(), sizes.end()); sizes[0] += (N - tot); long long int ans = 0; for (int it : sizes) { ans += (it * (it - 1)) / 2; } cout << ans - M; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[500005]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); int kk = 1; sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) { if (a[i] >= a[kk] * 2) { ++kk; } } --kk; kk = min(n / 2, kk); printf( %d n , n - kk); return 0; } |
#include <bits/stdc++.h> using namespace std; const short int N = 1000; short int n, m, ax[] = {0, 0, 1, -1}, ay[] = {1, -1, 0, 0}, man_dis[N][N]; bool vis[N][N], v[N][N], g[N][N]; void good() { for (short int i = 0; i < n; i++) { for (short int j = 0; j < m; j++) { bool f = 0; if (i and v[i][j] == v[i - 1][j]) f = 1; if (j and v[i][j] == v[i][j - 1]) f = 1; if (i < n - 1 and v[i][j] == v[i + 1][j]) f = 1; if (j < m - 1 and v[i][j] == v[i][j + 1]) f = 1; g[i][j] = f; } } } void man_dist() { queue<pair<short int, short int>> q; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (g[i][j]) man_dis[i][j] = 0, q.push({i, j}), vis[i][j] = true; while (q.size()) { short int y = q.front().first, x = q.front().second; q.pop(); for (int i = 0; i < 4; i++) { int nx = x + ax[i], ny = y + ay[i]; if (nx < 0 || ny < 0 || nx >= m || ny >= n || vis[ny][nx]) continue; man_dis[ny][nx] = man_dis[y][x] + 1; vis[ny][nx] = true; q.push({ny, nx}); } } } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tt, ii = 0; short int k = 0; cin >> n >> m >> tt; for (short int i = 0; i < n; i++) for (short int j = 0; j < m; j++) { char x; cin >> x; v[i][j] = (x == 1 ); } good(); man_dist(); while (ii++ < tt) { short int i, j; long long p; cin >> i >> j >> p; i--, j--; if (n + m == 2) { cout << v[i][j] << endl; continue; } short int f = man_dis[i][j]; if (p <= f || !vis[i][j]) cout << v[i][j] << endl; else cout << (p - f + v[i][j]) % 2 << endl; } cerr << [Execution : << (1.0 * clock()) / CLOCKS_PER_SEC << s] n ; return 0; } |
#include <bits/stdc++.h> inline long long read() { char c = getchar(); while (c != - && (c < 0 || c > 9 )) c = getchar(); long long k = 1, kk = 0; if (c == - ) c = getchar(), k = -1; while (c >= 0 && c <= 9 ) kk = kk * 10 + c - 0 , c = getchar(); return kk * k; } using namespace std; void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x / 10) write(x / 10); putchar(x % 10 + 0 ); } void writeln(long long x) { write(x); puts( ); } long long n, rd[1000010], ans, sum, z[1000010], d, x, y; signed main() { n = read(); if (n == 2) { puts( Yes ); puts( 1 ); puts( 1 2 ); return 0; } for (long long i = 1; i < n; i++) x = read(), y = read(), rd[x]++, rd[y]++; for (long long i = 1; i <= n; i++) { if (rd[i] > 2) ans++; if (rd[i] == 1) z[++d] = i; if (rd[i] > rd[sum]) sum = i; } if (ans > 1) return puts( No ), 0; puts( Yes ); writeln(d); for (long long i = 1; i <= d; i++) write(z[i]), putchar( ), writeln(sum); } |
`define ADDER_WIDTH 019
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
// Elbert V2 Library
// Copyright (c) 2015 J.B. Langston
//
// (subsequently tweaked by MLT)
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//////////////////////////////////////////////////////////////////////////////////
module vga_noise_demo(clkin, dips, segments, anodes, hsync, vsync, red, green, blue, audio_l, audio_r, gpio_P1);
input clkin;
// DIP switch
input [8:1] dips;
// 7-SEG
output [7:0] segments;
output [3:1] anodes;
// VGA
output hsync, vsync;
output [2:0] red, green;
output [1:0] blue;
wire [7:0] color;
wire [9:0] x, y;
//
// AUDIO
output audio_l, audio_r;
// GPIO
output [7:0] gpio_P1;
wire [11:0] bcd;
wire clk;
reg [15:0] cnt;
// Use the DCM to multiply the incoming 12MHz clock to a 192MHz clock
clock_mgr dcm (
.CLKIN_IN(clkin),
.CLKFX_OUT(clk),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT()
);
// Convert binary input from DIP switches into BCD
binary_to_bcd conv (
.binary({4'b0, ~dips}),
.bcd(bcd)
);
// Increment a counter for each clock cycle which can be used to divide the clock as needed
always @(posedge clk) cnt <= cnt + 1;
// route the divided clock to GPIO
// so we can see it on the scope
// /1024 so MHz are now ~= kHz
assign gpio_P1[0] = cnt[9];// main clock / 1024
assign gpio_P1[1] = cnt[3];// pixel clock / 2
assign gpio_P1[2] = dips[1]&vsync; // LFSR reset signal
// assign remaining GPIOs to something
assign gpio_P1[7:3] = 5'b00000;
// Generate sync pulses and x/y coordinates
// pixel clock is 25.5MHz, should be 25.175MHz
vga_driver vga (
.clk(cnt[2]),
.color(color),
.hsync(hsync),
.vsync(vsync),
.red(red),
.green(green),
.blue(blue),
.x(x),
.y(y)
);
// generate VGA output:
//
// DIP switch 1 pauses/unpauses the noise display
// DIP switch 2 switches between colour/monochrome output
// DIP switch 3 switches between noise mode and test mode
vga_noise vga_noise(
.clk(clk),
.color(color),
.pause(dips[1]),
.vsync(vsync),
.hsync(hsync),
.style(dips[2]),
.test(dips[3]),
.audio_l(audio_l),
.audio_r(audio_r)
);
// Multiplex BCD value across seven segment display (no decimal points)
seven_segment_mux mux (
.clk(cnt[15]),
.value({4'b0, bcd}),
.dp(3'b000),
.segments(segments),
.anodes(anodes)
);
endmodule
|
`timescale 1ns / 1ps
module Basys3(
input [1:0] switch,
input mclk,
input btnClk,
input reset,
output wire [7:0] display,
output wire [3:0] an
);
reg [15:0] tmp[0:3];
reg [15:0] num;
wire clk;
wire [31:0] pc, pcNext;
wire [31:0] instruction;
wire [31:26] op;
wire [25:21] rs;
wire [20:16] rt;
wire [15:11] rd;
wire [10:6] sa;
wire [15:0] imm;
wire [25:0] address;
wire [31:0] readData1, readData2, writeData, aluResult, memData;
assign op = instruction[31:26];
assign rs = instruction[25:21];
assign rt = instruction[20:16];
assign rd = instruction[15:11];
assign sa = instruction[10:6];
assign imm = instruction[15:0];
assign address = instruction[25:0];
CPU cpu(
.clk(clk),
.reset(reset),
.pcAddressOutNext(pcNext),
.pcAddressOut(pc),
.imDataOut(instruction),
.rfReadData1(readData1),
.rfReadData2(readData2),
.dbdrDataOut(writeData),
.aluResult(aluResult),
.dmDataOut(memData)
);
Print print(
.mclk(mclk),
.num(num),
.display(display),
.an(an)
);
Button btn(
.mclk(mclk),
.in(btnClk),
.out(clk)
);
always@(switch or pcNext or pc or instruction or readData1 or readData2 or aluResult or writeData) begin
case (switch)
2'B00: num = { pc[7:0], pcNext[7:0] };
2'B01: num = { 3'B0, instruction[25:21], readData1[7:0] };
2'B10: num = { 3'B0, instruction[20:16], readData2[7:0] };
2'B11: num = { aluResult[7:0], writeData[7:0] };
endcase
end
endmodule
|
/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* round constant */
module rconst(i, rc);
input [23:0] i;
output reg [63:0] rc;
always @ (i)
begin
rc = 0;
rc[0] = i[0] | i[4] | i[5] | i[6] | i[7] | i[10] | i[12] | i[13] | i[14] | i[15] | i[20] | i[22];
rc[1] = i[1] | i[2] | i[4] | i[8] | i[11] | i[12] | i[13] | i[15] | i[16] | i[18] | i[19];
rc[3] = i[2] | i[4] | i[7] | i[8] | i[9] | i[10] | i[11] | i[12] | i[13] | i[14] | i[18] | i[19] | i[23];
rc[7] = i[1] | i[2] | i[4] | i[6] | i[8] | i[9] | i[12] | i[13] | i[14] | i[17] | i[20] | i[21];
rc[15] = i[1] | i[2] | i[3] | i[4] | i[6] | i[7] | i[10] | i[12] | i[14] | i[15] | i[16] | i[18] | i[20] | i[21] | i[23];
rc[31] = i[3] | i[5] | i[6] | i[10] | i[11] | i[12] | i[19] | i[20] | i[22] | i[23];
rc[63] = i[2] | i[3] | i[6] | i[7] | i[13] | i[14] | i[15] | i[16] | i[17] | i[19] | i[20] | i[21] | i[23];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 1; int n, h, w, g[N], p[N], t[N], ansx[N], ansy[N]; vector<int> v[3 * N]; int main() { scanf( %d%d%d , &n, &w, &h); for (int i = 0; i < n; i++) { scanf( %d%d%d , g + i, p + i, t + i); v[p[i] - t[i] + N].push_back(i); } fill(ansx, ansx + N, w); fill(ansy, ansy + N, h); for (auto i : v) if (!i.empty()) { vector<int> x, y; for (auto j : i) if (g[j] == 2) y.push_back(p[j]); else x.push_back(p[j]); sort(x.rbegin(), x.rend()); sort(y.begin(), y.end()); sort(i.begin(), i.end(), [](int &a, int &b) { if (g[a] != g[b]) return g[a] == 1; if (g[a] == 1) return p[a] > p[b]; return p[a] < p[b]; }); for (int j = 0; j < y.size(); j++) ansy[i[j]] = y[j]; for (int j = 0; j < x.size(); j++) ansx[i[j + y.size()]] = x[j]; } for (int i = 0; i < n; i++) printf( %d %d n , ansx[i], ansy[i]); } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const int INF = 2e9; vector<string> v; int n, m; int diff(string a, string b) { int i, cc = 0; for (i = 0; i < m; ++i) cc += (a[i] != b[i]); return cc; } string solve() { string s = v[0], t; int i, j, cc; char c; bool f; for (i = 0; i < m; ++i) { t = s; for (c = a ; c <= z ; ++c) { t[i] = c; cc = 0; f = 1; for (j = 0; j < n; ++j) { cc = diff(t, v[j]); if (cc > 1) f = 0; } if (f) return t; } } return -1 ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int tc, ti = 1; cin >> tc; while (tc--) { int i, j; cin >> n >> m; v.resize(n); for (i = 0; i < n; ++i) cin >> v[i]; cout << solve() << n ; } return 0; } |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// bcam_bhv.v: Behavioral description of binary CAM //
// //
// Author: Ameer M. S. Abdelhadi ( ; ) //
// SRAM-based Modular II-2D-BCAM ; The University of British Columbia , Sep. 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module bcam_bhv
#( parameter CDEP = 512, // CAM depth
parameter PWID = 32 , // CAM/pattern width
parameter INOM = 1 ) // binary / Initial CAM with no match (has priority over IFILE)
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(CDEP)-1:0] wAddr , // write address
input [ PWID -1:0] wPatt , // write pattern
input [ PWID -1:0] mPatt , // patern to match
output reg match , // match indicator
output reg [`log2(CDEP)-1:0] mAddr ); // matched address
// assign memory array
reg [PWID-1:0] mem [0:CDEP-1];
// valid bit
reg [CDEP-1:0] vld;
// initialize memory, with zeros if INOM or file if IFILE.
integer i;
initial
if (INOM)
for (i=0; i<CDEP; i=i+1)
{vld[i],mem[i]} = {1'b0,{PWID{1'b0}}};
always @(posedge clk) begin
// write to memory
if (wEnb)
{vld[wAddr],mem[wAddr]} = {1'b1,wPatt};
// search memory
match = 0;
mAddr = 0;
match = (mem[mAddr]==mPatt) && vld[mAddr];
while ((!match) && (mAddr<(CDEP-1))) begin
mAddr=mAddr+1;
match = (mem[mAddr]==mPatt) && vld[mAddr];
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_g/sky130_fd_sc_hd__udp_pwrgood_pp_g.v"
`include "../../models/udp_pwrgood_pp_p/sky130_fd_sc_hd__udp_pwrgood_pp_p.v"
`celldefine
module sky130_fd_sc_hd__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_hd__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_hd__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CONB_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long int mod = 1000 * 1000 * 1000 + 7; const double PI = 3.14159265358979323846264; const pair<long long int, long long int> steps[] = { {1, 0}, {0, 1}, {-1, 0}, {0, -1}, {1, -1}, {1, 1}, {-1, -1}, {-1, 1}}; template <typename... T> void read(T&... args) { ((cin >> args), ...); } template <typename... T> void write(T&&... args) { ((cout << args << ), ...); } void fio() { ios_base::sync_with_stdio(false); cin.tie(NULL); } void setUpLocal() {} const long long int maxN = 2 * 1e3; const long long int gp_size = maxN; vector<long long int> gp[gp_size]; long long int vis[gp_size]; long long int cnt[gp_size]; void dfs(long long int i) { vis[i] = 1; for (long long int child : gp[i]) if (!vis[child]) dfs(child); } long long int modPow(long long int n, long long int k) { long long int ret = 1; while (k) { if (k & 1) ret = ret * n % mod; k >>= 1; n = n * n % mod; } return ret; } void solve() { long long int n, m, k; cin >> n >> m >> k; for (long long int i = 1; i <= n - k + 1; i++) { for (long long int f = i, b = i + k - 1; f <= b; f++, b--) { gp[f].push_back(b); gp[b].push_back(f); } } long long int cc = 0; for (long long int i = 1; i <= n; i++) { if (!vis[i]) { cc++; dfs(i); } } cout << modPow(m, cc); } int32_t main() { fio(); setUpLocal(); return solve(), 0; } |
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: CacheBlockRAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 232 07/05/2012 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module CacheBlockRAM (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [8:0] address_a;
input [8:0] address_b;
input clock;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "9216"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M9K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
// Retrieval info: USED_PORT: address_b 0 0 9 0 INPUT NODEFVAL "address_b[8..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]"
// Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]"
// Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]"
// Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 address_b 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0
// Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0
// Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CacheBlockRAM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: lt24Model.v
//
// *Module Description:
// LT24 Model
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module lt24Model (
// OUTPUTs
lt24_lcd_d_o, // LT24 LCD Data input
lt24_adc_busy_o, // LT24 ADC Busy
lt24_adc_dout_o, // LT24 ADC Data Out
lt24_adc_penirq_n_o, // LT24 ADC Pen Interrupt
// INPUTs
lt24_lcd_cs_n_i, // LT24 LCD Chip select (Active low)
lt24_lcd_rd_n_i, // LT24 LCD Read strobe (Active low)
lt24_lcd_wr_n_i, // LT24 LCD Write strobe (Active low)
lt24_lcd_rs_i, // LT24 LCD Command/Param selection (Cmd=0/Param=1)
lt24_lcd_d_i, // LT24 LCD Data output
lt24_lcd_d_en_i, // LT24 LCD Data output enable
lt24_lcd_reset_n_i, // LT24 LCD Reset (Active Low)
lt24_lcd_on_i, // LT24 LCD on/off
lt24_adc_cs_n_i, // LT24 ADC Chip Select
lt24_adc_dclk_i, // LT24 ADC Clock
lt24_adc_din_i // LT24 ADC Data In
);
// OUTPUTs
//============
output [15:0] lt24_lcd_d_o; // LT24 LCD Data input
output lt24_adc_busy_o; // LT24 ADC Busy
output lt24_adc_dout_o; // LT24 ADC Data Out
output lt24_adc_penirq_n_o; // LT24 ADC Pen Interrupt
// INPUTs
//============
input lt24_lcd_cs_n_i; // LT24 LCD Chip select (Active low)
input lt24_lcd_rd_n_i; // LT24 LCD Read strobe (Active low)
input lt24_lcd_wr_n_i; // LT24 LCD Write strobe (Active low)
input lt24_lcd_rs_i; // LT24 LCD Command/Param selection (Cmd=0/Param=1)
input [15:0] lt24_lcd_d_i; // LT24 LCD Data output
input lt24_lcd_d_en_i; // LT24 LCD Data output enable
input lt24_lcd_reset_n_i; // LT24 LCD Reset (Active Low)
input lt24_lcd_on_i; // LT24 LCD on/off
input lt24_adc_cs_n_i; // LT24 ADC Chip Select
input lt24_adc_dclk_i; // LT24 ADC Clock
input lt24_adc_din_i; // LT24 ADC Data In
//----------------------------------------------------------------------------
// LCD
//----------------------------------------------------------------------------
// PARAMETERs
//============
// Screen
parameter LCD_WIDTH = 320;
parameter LCD_HEIGHT = 240;
parameter LCD_SIZE = LCD_WIDTH * LCD_HEIGHT;
// Command
parameter CMD_LCD_NOP = 16'h0000;
parameter CMD_LCD_SOFTWARE_RESET = 16'h0001;
parameter CMD_LCD_READ_DISPLAY_ID = 16'h0004;
parameter CMD_LCD_READ_DISPLAY_STATUS = 16'h0009;
parameter CMD_LCD_READ_DISPLAY_POWER_MODE = 16'h000A;
parameter CMD_LCD_READ_DISPLAY_MADCTL = 16'h000B;
parameter CMD_LCD_READ_DISPLAY_PIXEL_FORMAT = 16'h000C;
parameter CMD_LCD_READ_DISPLAY_IMAGE_FORMAT = 16'h000D;
parameter CMD_LCD_READ_DISPLAY_SIGNAL_MODE = 16'h000E;
parameter CMD_LCD_READ_DISPLAY_SELF_DIAG = 16'h000F;
parameter CMD_LCD_ENTER_SLEEP_MODE = 16'h0010;
parameter CMD_LCD_SLEEP_OUT = 16'h0011;
parameter CMD_LCD_PARTIAL_MODE_ON = 16'h0012;
parameter CMD_LCD_NORMAL_DISPLAY_MODE_ON = 16'h0013;
parameter CMD_LCD_DISPLAY_INVERSION_OFF = 16'h0020;
parameter CMD_LCD_DISPLAY_INVERSION_ON = 16'h0021;
parameter CMD_LCD_GAMMA_SET = 16'h0026;
parameter CMD_LCD_DISPLAY_OFF = 16'h0028;
parameter CMD_LCD_DISPLAY_ON = 16'h0029;
parameter CMD_LCD_COLUMN_ADDRESS_SET = 16'h002A;
parameter CMD_LCD_PAGE_ADDRESS_SET = 16'h002B;
parameter CMD_LCD_MEMORY_WRITE = 16'h002C;
parameter CMD_LCD_COLOR_SET = 16'h002D;
parameter CMD_LCD_MEMORY_READ = 16'h002E;
parameter CMD_LCD_PARTIAL_AREA = 16'h0030;
parameter CMD_LCD_VERTICAL_SCROLLING_DEF = 16'h0033;
parameter CMD_LCD_TEARING_EFFECT_LINE_OFF = 16'h0034;
parameter CMD_LCD_TEARING_EFFECT_LINE_ON = 16'h0035;
parameter CMD_LCD_MEMORY_ACCESS_CONTROL = 16'h0036;
parameter CMD_LCD_VERTICAL_SCROL_START_ADDR = 16'h0037;
parameter CMD_LCD_IDLE_MODE_OFF = 16'h0038;
parameter CMD_LCD_IDLE_MODE_ON = 16'h0039;
parameter CMD_LCD_PIXEL_FORMAT_SET = 16'h003A;
parameter CMD_LCD_WRITE_MEMORY_CONTINUE = 16'h003C;
parameter CMD_LCD_READ_MEMORY_CONTINUE = 16'h003E;
parameter CMD_LCD_SET_TEAR_SCANLINE = 16'h0044;
parameter CMD_LCD_GET_SCANLINE = 16'h0045;
parameter CMD_LCD_WRITE_DISPLAY_BRIGHTNESS = 16'h0051;
parameter CMD_LCD_READ_DISPLAY_BRIGHTNESS = 16'h0052;
parameter CMD_LCD_WRITE_CTRL_DISPLAY = 16'h0053;
parameter CMD_LCD_READ_CTRL_DISPLAY = 16'h0054;
parameter CMD_LCD_WRITE_CONTENT_ADAPTIVE = 16'h0055;
parameter CMD_LCD_READ_CONTENT_ADAPTIVE = 16'h0056;
parameter CMD_LCD_WRITE_CABC_MIN_BRIGHTNESS = 16'h005E;
parameter CMD_LCD_READ_CABC_MIN_BRIGHTNESS = 16'h005F;
parameter CMD_LCD_READ_ID1 = 16'h00DA;
parameter CMD_LCD_READ_ID2 = 16'h00DB;
parameter CMD_LCD_READ_ID3 = 16'h00DC;
parameter CMD_LCD_IDLE = 16'hFFFF;
// COMMAND DECODER
//=================
reg [15:0] lt24_state;
always @(posedge lt24_lcd_wr_n_i or posedge lt24_lcd_cs_n_i)
if (lt24_lcd_cs_n_i) lt24_state <= CMD_LCD_IDLE;
else if (~lt24_lcd_rs_i) lt24_state <= lt24_lcd_d_i;
reg lt24_state_update;
always @(posedge lt24_lcd_wr_n_i or posedge lt24_lcd_rs_i)
if (lt24_lcd_rs_i) lt24_state_update <= 1'b0;
else lt24_state_update <= 1'b1;
// MEMORY
//============
integer mem_addr;
reg [15:0] mem [0:LCD_SIZE-1];
always @(posedge lt24_lcd_wr_n_i)
if ((lt24_lcd_d_i ==CMD_LCD_MEMORY_WRITE) & ~lt24_lcd_rs_i)
begin
mem_addr <= 0;
end
else if (lt24_state==CMD_LCD_MEMORY_WRITE)
begin
mem[mem_addr] <= lt24_lcd_d_i;
mem_addr <= mem_addr+1;
end
assign lt24_lcd_d_o = 16'h0000;
//----------------------------------------------------------------------------
// ADC
//----------------------------------------------------------------------------
reg lt24_adc_penirq_n_o;
integer coord_x;
integer coord_y;
reg [11:0] adc_coord_x;
reg [11:0] adc_coord_y;
initial
begin
coord_x = 0;
coord_y = 0;
adc_coord_x = 12'h000;
adc_coord_y = 12'h000;
lt24_adc_penirq_n_o = 1'b1; // LT24 ADC Pen Interrupt
end
always @(coord_x)
adc_coord_x = (coord_x*'hfff)/320;
always @(coord_x)
adc_coord_y = (coord_y*'hfff)/240;
integer shift_cnt;
always @(posedge lt24_adc_dclk_i or posedge lt24_adc_cs_n_i)
if (lt24_adc_cs_n_i) shift_cnt <= 0;
else shift_cnt <= shift_cnt+1;
reg [15:0] shift_in;
always @(posedge lt24_adc_dclk_i or posedge lt24_adc_cs_n_i)
if (lt24_adc_cs_n_i) shift_in <= 16'h0000;
else shift_in <= {shift_in[14:0], lt24_adc_din_i};
reg [15:0] shift_out;
always @(negedge lt24_adc_dclk_i or posedge lt24_adc_cs_n_i)
if (lt24_adc_cs_n_i) shift_out <= 16'h0000;
else if ((shift_cnt==8) & (shift_in==16'h0092)) shift_out <= {1'b0, adc_coord_x, 3'b000};
else if ((shift_cnt==32) & (shift_in==16'h00D2)) shift_out <= {1'b0, adc_coord_y, 3'b000};
else shift_out <= {shift_out[14:0], 1'b0};
assign lt24_adc_dout_o = shift_out[15]; // LT24 ADC Data Out
assign lt24_adc_busy_o = 1'b0; // LT24 ADC Busy
endmodule // lt24Model
|
#include <bits/stdc++.h> using namespace std; bool is_prime(long long n) { for (long long i = 2; i * i <= n; ++i) { if (n % i == 0) { return false; } } return true; } long long getPow(long long a, long long b) { long long res = 1ll, tp = a; while (b) { if (b & 1ll) { res *= tp; res %= 1000000007; } tp *= tp; tp %= 1000000007; b >>= 1ll; } return res; } long long vec_mult(long long x1, long long y1, long long x2, long long y2, long long x3, long long y3) { return abs((x2 - x1) * (y3 - y1) - (y2 - y1) * (x3 - x1)); } void ok() { cout << YES << endl; exit(0); } void no() { cout << NO << endl; exit(0); } inline long long nxt() { long long x; cin >> x; return x; } struct Fenwick { int n; vector<int> a; Fenwick(int _n = 0) : n(_n), a(_n) {} void add(int pos, int x) { while (pos < n) { a[pos] += x; pos |= pos + 1; } } int get(int pos) { int res = 0; while (pos >= 0) { res += a[pos]; pos = (pos & (pos + 1)) - 1; } return res; } int get(int l, int r) { return get(r) - get(l - 1); } }; struct Robot { int x, r, iq; Robot() {} Robot(int t1, int t2, int t3) : x(t1), r(t2), iq(t3) {} bool operator<(const Robot& a) const { return r > a.r; } }; const long long N = 2e5 + 5, inf = 1e18; int days[13] = {0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int main() { ios_base::sync_with_stdio(false); cin.tie(0), cout.tie(0); long long n = nxt(), k = nxt(); vector<Robot> mas(n); for (int i = 0; i < n; i++) { long long t1 = nxt(), t2 = nxt(), t3 = nxt(); mas[i] = Robot(t1, t2, t3); } sort(mas.begin(), mas.end()); vector<long long> iqs; for (int i = 0; i < n; i++) { iqs.push_back(mas[i].iq); } sort((iqs).begin(), (iqs).end()); (iqs).resize(unique((iqs).begin(), (iqs).end()) - (iqs).begin()); vector<vector<long long>> positions(iqs.size()); for (int i = 0; i < n; i++) { int ind = lower_bound(iqs.begin(), iqs.end(), mas[i].iq) - iqs.begin(); positions[ind].push_back(mas[i].x); } for (int i = 0; i < positions.size(); i++) { sort((positions[i]).begin(), (positions[i]).end()); (positions[i]) .resize(unique((positions[i]).begin(), (positions[i]).end()) - (positions[i]).begin()); } vector<Fenwick> fenws; for (int i = 0; i < iqs.size(); i++) { fenws.push_back(Fenwick(positions[i].size())); } long long ans = 0; for (auto t : mas) { int l = lower_bound(iqs.begin(), iqs.end(), t.iq - k) - iqs.begin(); while (l < iqs.size() && iqs[l] <= t.iq + k) { long long le = lower_bound(positions[l].begin(), positions[l].end(), t.x - t.r) - positions[l].begin(); long long ri = upper_bound(positions[l].begin(), positions[l].end(), t.x + t.r) - positions[l].begin() - 1; ans += fenws[l].get(le, ri); l++; } int ind = lower_bound(iqs.begin(), iqs.end(), t.iq) - iqs.begin(); int pos = lower_bound(positions[ind].begin(), positions[ind].end(), t.x) - positions[ind].begin(); fenws[ind].add(pos, 1); } cout << ans; return 0; } |
// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Structure:
// axic_srl_fifo
// ndeep_srl
// nto1_mux
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_7_axic_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg M_VALID_i;
reg S_READY_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
assign M_VALID = M_VALID_i;
assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;
assign M_MESG = m_axi_mesg_i;
assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);
assign pop = M_VALID_i & M_READY;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
//---------------------------------------------------------------------------
// When FIFO is empty, reset master valid bit. When not empty set valid bit.
// When FIFO is full, reset slave ready bit. When not full set ready bit.
//---------------------------------------------------------------------------
always @(posedge ACLK) begin
if (ARESET) begin
M_VALID_i <= 1'b0;
end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
M_VALID_i <= 1'b0;
end else if (push) begin
M_VALID_i <= 1'b1;
end
end
always @(posedge ACLK) begin
if (ARESET) begin
S_READY_i <= 1'b0;
end else if (areset_d1) begin
S_READY_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
S_READY_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
S_READY_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_7_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule
`default_nettype wire
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_fdiv(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataout, o_dataout_valid, i_stall);
parameter DATA_WIDTH = 32;
parameter LATENCY = 14;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_stall;
reg [LATENCY-1:0] shift_reg_valid;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
wire is_fifo_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_fifo_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_fifo_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
shift_reg_valid <= {LATENCY{1'b0}};
end
else
begin
if(~is_stalled)
shift_reg_valid <= { is_fifo_a_valid & is_fifo_b_valid, shift_reg_valid[LATENCY-1:1] };
end
end
assign is_stalled = (shift_reg_valid[0] & i_stall);
assign is_fifo_stalled = (shift_reg_valid[0] & i_stall) | !(is_fifo_a_valid & is_fifo_b_valid);
acl_fp_div fdiv_unit(
.enable(~is_stalled), .clock(clock), .dataa(dataa), .datab(datab), .result(o_dataout));
assign o_dataout_valid = shift_reg_valid[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> using vv = vector<vector<T>>; template <class T> ostream &operator<<(ostream &os, const vector<T> &t) { os << { ; for (int(i) = 0; (i) < (t.size()); ++(i)) { os << t[i] << , ; } os << } << endl; return os; } template <class S, class T> ostream &operator<<(ostream &os, const pair<S, T> &t) { return os << ( << t.first << , << t.second << ) ; } const long long MOD = 1e9 + 9; const int N = (1 << 17), r = 11451; struct Seg { long long h, q, r; Seg(int v = 0) { h = v; q = 0; r = (v ? ::r : 1); } void comp(const Seg &ope) { q = ope.q; } void clear() { q = 0; } static Seg Ope(int v = 0) { Seg re; re.q = v; return re; } static Seg e; }; Seg Seg::e = Seg(); ostream &operator<<(ostream &os, const Seg &t) { return os << ( << t.h << , << t.q << , << t.r << ) ; } Seg seg[2 * N + 10]; Seg operator+(const Seg l, const Seg r) { Seg re; re.h = (l.h * r.r % MOD + r.h) % MOD; re.r = l.r * r.r % MOD; return re; } vector<long long> ser(N); inline void lazy_eval(int k, int a, int b) { if (!seg[k].q) return; seg[k].h = seg[k].q * ser[b - a - 1] % MOD; if (2 * k <= 2 * N + 5) { seg[2 * k + 1].comp(seg[k]); seg[2 * k + 2].comp(seg[k]); } seg[k].clear(); } inline void update_node(int k) { seg[k] = seg[2 * k + 1] + seg[2 * k + 2]; } void update(int l, int r, Seg ope, int k = 0, int a = 0, int b = N) { lazy_eval(k, a, b); if (b <= l || r <= a) return; if (l <= a && b <= r) { seg[k].comp(ope); lazy_eval(k, a, b); return; } int m = (a + b) / 2; update(l, r, ope, 2 * k + 1, a, m); update(l, r, ope, 2 * k + 2, m, b); update_node(k); } Seg get(int l, int r, int k = 0, int a = 0, int b = N) { lazy_eval(k, a, b); if (b <= l || r <= a) return Seg::e; if (l <= a && b <= r) { return seg[k]; } int m = (a + b) / 2; Seg vl = get(l, r, 2 * k + 1, a, m); Seg vr = get(l, r, 2 * k + 2, m, b); update_node(k); return vl + vr; } int main() { ios_base::sync_with_stdio(false); cout << fixed << setprecision(0); ser[0] = 1; for (int(i) = 0; (i) < (N - 1); ++(i)) ser[i + 1] = (1 + ser[i] * r % MOD) % MOD; int n, m, t; cin >> n >> m >> t; string str; cin >> str; int a, l, r, x; for (int(i) = 0; (i) < (n); ++(i)) seg[(1 << 17) - 1 + i] = Seg(str[i]); for (int(i) = ((1 << 17) - 1) - 1; (i) >= 0; --(i)) update_node(i); for (int(i) = 0; (i) < (t + m); ++(i)) { cin >> a >> l >> r >> x; --l; if (a == 1) { update(l, r, Seg::Ope(x + 0 )); } else { cout << (get(l, r - x).h == get(l + x, r).h ? YES : NO ) << endl; } } return 0; } |
module nmac_crc_check(
clk,
wr_clk,
reset,
in_pkt_wrreq,
in_pkt,
in_pkt_usedw,
in_valid_wrreq,
in_valid,
port_error,
out_pkt_wrreq,
out_pkt,
out_pkt_usedw,
out_valid_wrreq,
out_valid
);
input clk;
input wr_clk;
input reset;
input in_pkt_wrreq;
input [138:0]in_pkt;
output [7:0]in_pkt_usedw;
input in_valid_wrreq;
input in_valid;
output port_error;
output out_pkt_wrreq;
output [138:0]out_pkt;
input [7:0]out_pkt_usedw;
output out_valid_wrreq;
output out_valid;
reg out_pkt_wrreq;
reg [138:0]out_pkt;
reg out_valid_wrreq;
reg out_valid;
reg port_error;
reg [2:0]current_state;
parameter idle=3'b0,
transmit=3'b001,
wait_crcbad=3'b010,
discard=3'b011;
always@(posedge clk or negedge reset)
if(!reset)
begin
crc_data_valid<=1'b0;
crc_empty<=4'b0;
start_of_pkt<=1'b0;
end_of_pkt<=1'b0;
in_pkt_rdreq<=1'b0;
in_valid_rdreq<=1'b0;
out_pkt_wrreq<=1'b0;
out_valid_wrreq<=1'b0;
port_error <= 1'b0;
current_state<=idle;
end
else
begin
case(current_state)
idle:
begin
out_valid_wrreq<=1'b0;
port_error <= 1'b0;
if(out_pkt_usedw<8'd161)
begin
if(!in_valid_empty)
begin
if(in_valid_q==1'b1)
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b1;
current_state<=transmit;
end
else
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b1;
current_state<=discard;
end
end
else
begin
current_state<=idle;
end
end
else
begin
current_state<=idle;
end
end//end idle;
transmit:
begin
in_valid_rdreq<=1'b0;
if(in_pkt_q[138:136]==3'b101)//header;
begin
in_pkt_rdreq<=1'b1;
crc_data_valid<=1'b1;
crc_data<=in_pkt_q[127:0];
start_of_pkt<=1'b1;
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=transmit;
end
else if(in_pkt_q[138:136]==3'b110)//tail;
begin
in_pkt_rdreq<=1'b0;
crc_data_valid<=1'b1;
crc_data<=in_pkt_q[127:0];
end_of_pkt<=1'b1;
crc_empty<=4'b1111-in_pkt_q[135:132];
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=wait_crcbad;
end
else//middle;
begin
in_pkt_rdreq<=1'b1;
start_of_pkt<=1'b0;
crc_data_valid<=1'b1;
crc_data<=in_pkt_q[127:0];
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=transmit;
end
end//end transmit;
wait_crcbad:
begin
end_of_pkt<=1'b0;
crc_empty<=4'b0;
crc_data_valid<=1'b0;
out_pkt_wrreq<=1'b0;
if(crc_bad_valid==1'b1)
begin
if(crc_bad==1'b1)//error;
begin
out_valid_wrreq<=1'b1;
out_valid<=1'b0;
port_error <= 1'b1;
end
else
begin
out_valid_wrreq<=1'b1;
out_valid<=1'b1;
end
current_state<=idle;
end
else
begin
current_state<=wait_crcbad;
end
end//end wait_crcbad;
discard:
begin
in_valid_rdreq<=1'b0;
in_pkt_rdreq<=1'b1;
if(in_pkt_q[138:136]==3'b110)//tail;
begin
in_pkt_rdreq<=1'b0;
current_state<=idle;
end
else if(in_pkt_q[138:136]==3'b111)//tail;
begin
in_pkt_rdreq<=1'b0;
current_state<=idle;
end
else
begin
current_state<=discard;
end
end//end discard;
default:
begin
current_state<=idle;
end
endcase
end
reg [127:0]crc_data;
reg crc_data_valid;
reg [3:0]crc_empty;
reg start_of_pkt;
reg end_of_pkt;
wire crc_bad_valid;
wire crc_bad;
check_ip check_ip0(
.clk(clk),
.data(crc_data),
.datavalid(crc_data_valid),
.empty(crc_empty),
.endofpacket(end_of_pkt),
.reset_n(reset),
.startofpacket(start_of_pkt),
.crcbad(crc_bad),
.crcvalid(crc_bad_valid)
);
reg in_pkt_rdreq;
wire [138:0]in_pkt_q;
wire [7:0]in_pkt_usedw;
asy_256_139 asy_256_1391(
.aclr(!reset),
.data(in_pkt),
.rdclk(clk),
.rdreq(in_pkt_rdreq),
.wrclk(wr_clk),
.wrreq(in_pkt_wrreq),
.q(in_pkt_q),
.wrusedw(in_pkt_usedw)
);
reg in_valid_rdreq;
wire in_valid_q;
wire in_valid_empty;
asy_64_1 asy_64_11(
.aclr(!reset),
.data(in_valid),
.rdclk(clk),
.rdreq(in_valid_rdreq),
.wrclk(wr_clk),
.wrreq(in_valid_wrreq),
.q(in_valid_q),
.rdempty(in_valid_empty)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int main() { int h; cin >> h; int n = (1 << h) - 1; vector<pair<int, int>> c(n + 1); for (int i = 0; i <= n; i++) c[i] = {0, i}; for (int i = 0; i < 420; i++) { int u = rng() % n + 1, v = rng() % n + 1, w = rng() % n + 1; while (u == v) v = rng() % n + 1; while (w == u || w == v) w = rng() % n + 1; cout << ? << u << << v << << w << n ; int x; cin >> x; c[x].first++; } sort(c.rbegin(), c.rend()); for (int i = 1; i <= n; i++) { if (i == c[0].second || i == c[1].second) continue; cout << ? << c[0].second << << c[1].second << << i << n ; int x; cin >> x; if (x == i) { cout << ! << i << n ; return 0; } } } |
module spi_ctrl(
clk,rst_n,sck,mosi,miso,cs_n,spi_tx_en,spi_rx_en,mode_select_CPHA,mode_select_CPOL,receive_status
);
input clk,rst_n,miso;
input mode_select_CPHA;
input mode_select_CPOL;
output sck,mosi,cs_n;
output receive_status;
input spi_tx_en;
input spi_rx_en;
wire spi_over;
wire receive_status;
reg spi_clk;
reg cs_n;
reg[7:0] clk_count;
reg[7:0] rst_count;
reg rst_flag;
/*
spi baud rate is calculated by clk / 100 / 3
as we count 3 sck change to be a full period
*/
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
clk_count <= 8'h0;
spi_clk <= 1'b0;
end
else begin
if(clk_count < 8'd100)
clk_count <= clk_count + 1'b1;
else begin
clk_count <= 8'h0;
spi_clk <= ~spi_clk;
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cs_n <= 1'b1;
else begin
if(spi_over || ((spi_tx_en == 1'b0) && (spi_rx_en == 1'b0)))
cs_n <= 1'b1;
else
cs_n <= 1'b0;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
rst_flag <= 1'b0;
rst_count <= 'h0;
end
else begin
if(rst_count<8'd20)
rst_count <= rst_count + 1'b1;
else
rst_flag <= 1'b1;
end
end
spi_master spi_master_instance(
.clk(spi_clk),
.rst_n(rst_flag),
.spi_miso(miso),
.spi_mosi(mosi),
.spi_clk(sck),
.spi_tx_en(spi_tx_en),
.spi_over(spi_over),
.spi_rx_en(spi_rx_en),
.mode_select_CPHA(mode_select_CPHA),
.mode_select_CPOL(mode_select_CPOL),
.receive_status(receive_status)
);
endmodule |
// Name: WcaLimeIF.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaLimeIF
(
input clock_dsp, //DSP Sampling Clock, which can be substantially faster than the other clocks.
input clock_rx, //Rx Clock Interface 2x Sample rate
input clock_tx, //Tx Clock Interface 2x Sample rate
input reset, //Resets configuration and clears state.
input aclr, //Clears state but not configuration
//Internal Bus I/O
input wire [23:0] tx_iq, //Transmit I/Q data stream input (12 bits each).
output reg [23:0] rx_iq, //Receive I/Q data stream output (12 bits each).
output wire rx_strobe, //Baseband processing receive sample strobe output.
output wire tx_strobe, //Baseband processing transmit sample strobe output.
// LIME Chip Baseband interface.
output wire rf_rxclk, //Lime receive ADC clock.
input wire rf_rxiqsel,
output wire rf_rxen,
input wire [11:0] rf_rxdata,
output wire rf_txclk, //Lime transmit ADC clock.
output wire rf_txiqsel,
output wire rf_txen,
output wire [11:0] rf_txdata,
//Control Interface.
input wire [11:0] rbusCtrl, // Address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter CTRL_ADDR = 0;
parameter RSSI_ADDR = 0;
parameter RXBIAS_ADDR = 0;
//RF Interface. (WRITE)
// bit# | Description
//-------|----------------------------------------------------------
// 0-1 RX Input Mode
// 0 = tx_iq loopback
// 1 = rf_rxdata input (dc bias removed).
// 2 = rf_rxdata input (raw).
// 3 = Fixed Test Pattern i = 256, q = -256;
// 2-3 TX Ouput Mode
// 0 = rf_rxdata loopback
// 1 = rf_txdata input.
// 2 = Fixed Test Pattern i = 256, q = -256;
// 3 = Fixed Test Pattern i = 0, q = 0;
// 4 "rf_rxen" output line - set to 1 to enable, 0 to disable. Enables disables the
// Lime chip #1 receive ADC function.
//
// 5 "rf_txen" output pin state - set to 1 to enable, 0 to disable Enables / disables the
// Lime chip #1 transmit DAC function.
//
// 6 "rf_rxclk" enable (1) / (0). If enabled the rf_rxclk pin will turn on and provide clock
// signals to the receive functions of the Lime chips.
//
// 7 "rf_txclk" enable (1) / (0). If enabled the tx_rxclk pin will turn on and provide clock
// signals to the transmit functions of Lime chip #1. If disabled, clock output will be low.
wire [7:0] rf_ctrl;
//Control Register
WcaWriteByteReg #(CTRL_ADDR) wr_rf_ctrl
(.reset(reset), .out( rf_ctrl), .rbusCtrl(rbusCtrl), .rbusData(rbusData) );
//------------------------------------------------------------
// Lime chip control.
//------------------------------------------------------------
WcaSynchEdgeDetect synchRxEnable ( .clk(clock_rx), .in(rf_ctrl[4]), .out(rf_rxen));
WcaSynchEdgeDetect synchTxEnable ( .clk(clock_rx), .in(rf_ctrl[4]), .out(rf_txen));
//Buffer the clock output so the internal clock
//fanout is not driving the output pins.
ODDR2 oddr2_rxclk ( .D0(1'b1), .D1(1'b0), .CE(rf_ctrl[6]), .C0(clock_rx), .C1(~clock_rx), .Q(rf_rxclk) );
ODDR2 oddr2_txclk ( .D0(1'b1), .D1(1'b0), .CE(rf_ctrl[7]), .C0(clock_tx), .C1(~clock_tx), .Q(rf_txclk) );
//------------------------------------------------------------
// Receiver Interface Selector.
//------------------------------------------------------------
wire clearState = reset | aclr;
wire [11:0] rx_DciBiasRemoved; //These are provided by the DC Offset calculation
reg [1:0] reg_rxstrobe;
//Shape RX strobe as a 1 clock pulse strobe.
always @(posedge clock_dsp)
begin
if( clearState)
begin
reg_rxstrobe[0] <= 1'b0;
reg_rxstrobe[1] <= 1'b0;
end
else
begin
reg_rxstrobe[0] <= ~rf_rxiqsel & ~reg_rxstrobe[1] &~reg_rxstrobe[0];
reg_rxstrobe[1] <= reg_rxstrobe[0];
//reg_rxstrobe[2] <= reg_rxstrobe[1];
//reg_rxstrobe[3] <= reg_rxstrobe[2];
end
end
assign rx_strobe = reg_rxstrobe[1] & rf_ctrl[6];
//Break out receive data into separate I/Q paths
//so we can process in dsp.
always @(posedge clock_dsp)
begin
case( { rf_ctrl[1:0]} )
2'b00 : // 0 is loop back.tx back on to rx.
begin
rx_iq <= #1 tx_iq;
end
2'b01 : //Rx data with DC Offset Removed.
begin
if( rf_rxiqsel )
rx_iq[11:0] <= #1 rx_DciBiasRemoved;
else
rx_iq[23:12] <= #1 rx_DciBiasRemoved;
end
2'b10 : //2 raw rx data,.
begin
if( rf_rxiqsel )
rx_iq[11:0] <= #1 rf_rxdata;
else
rx_iq[23:12] <= #1 rf_rxdata;
end
default: // 2 is fixed test pattern
begin
rx_iq <= #1 24'hF00100; //256,-256 I & Q.
end
endcase
end
//------------------------------------------------------------
// Transmitter Interface Selector.
//------------------------------------------------------------
reg [1:0] reg_txstrobe;
reg [23:0] txdata;
reg txiqsel;
// Generate TX IQ select clock.
always @(posedge clock_tx)
begin
if( clearState)
txiqsel <= 1'h0;
else
txiqsel <= ~txiqsel;
end
//disable IQ select when no clocking.
assign rf_txiqsel = txiqsel & rf_ctrl[7];
// Generate TX IQ select clock.
always @(posedge clock_dsp)
begin
if( clearState)
begin
reg_txstrobe[0] <= 1'b0;
reg_txstrobe[1] <= 1'b0;
txdata <= 24'h0;
end
else
begin
reg_txstrobe[0] <= ~rf_txiqsel & ~reg_txstrobe[1] &~reg_txstrobe[0];
reg_txstrobe[1] <= reg_txstrobe[0];
txdata <= (reg_txstrobe[0]) ? tx_iq : txdata;
end
end
assign tx_strobe = reg_txstrobe[1] & rf_ctrl[7];
assign rf_txdata = ( rf_ctrl[3:2] == 2'b00) // Loop back tx to rx
? rf_rxdata
: ((rf_ctrl[3:2] == 2'b01) // 1 tx.
? ((txiqsel)? txdata[11:00] : txdata[23:12] ) //When iqsel is 1
: ((rf_ctrl[3:2] == 2'b10) // test pattern
? ((txiqsel) ? 12'h100 : 12'hF00)
: 12'h0));
//------------------------------------------------------------
// RX RSSI Implementation
//------------------------------------------------------------
wire [7:0] rssi_q;
wire [7:0] rssi_i;
//Construct Inphase RSSI function
WcaRssi RssiInphase(
.clock(clock_dsp), .reset(clearState), .strobe(rx_strobe), .adc(rx_iq[11:00]), .rssi(rssi_i) );
//RSSI Quadrature Function
WcaRssi RssiQuadrature(
.clock(clock_dsp), .reset(clearState), .strobe(rx_strobe), .adc(rx_iq[23:12]), .rssi(rssi_q) );
//Place the RSSI values into a register for retrieval.
WcaReadWordReg #(RSSI_ADDR) RxRssiReadReg
( .reset(reset), .clock(clock_dsp), .enableIn(rx_strobe), .in( {rssi_q, rssi_i} ), .rbusCtrl(rbusCtrl), .rbusData(rbusData) );
//------------------------------------------------------------
// RX DC Bias Detection.
//------------------------------------------------------------
wire [11:0] dcOffset;
WcaDcOffset DcOffsetRemove(
.clock(clock_rx), .reset(clearState), .strobe(1'h1), .iqSel(rf_rxiqsel), .sig_in(rf_rxdata), .dcoffset( dcOffset), .sigout(rx_DciBiasRemoved));
//Place the DCOffset values into registers for retrieval.
//WcaReadDwordReg #(RXBIAS_ADDR) RxBiasReadReg
//( .reset(reset), .clock(clock_dsp), .enableIn(rx_strobe), .in( {dcOffset_i, dcOffset_q} ), .rbusCtrl(rbusCtrl), .rbusData(rbusData) );
endmodule // WcaLimeIF |
#include <bits/stdc++.h> using namespace std; int main() { int n, sum = 0; string s; cin >> n >> s; for (int i = 0; i < n; i++) sum += s[i] - 0 ; for (int i = 2; i <= n; i++) { if (sum % i == 0) { int cur = 0; bool flag = 1; for (int j = 0; j < n; j++) { cur += s[j] - 0 ; if (sum / i < cur) { flag = 0; break; } if (sum / i == cur) cur = 0; } if (flag) { cout << YES ; return 0; } } } cout << NO ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111A_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O2111A_BEHAVIORAL_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o2111a (
X ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X, B1, C1, or0_out, D1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111A_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int n, ans = 1, p, m; string s; set<int> buy, sell, extra; int main() { cin >> n; while (n--) { cin >> s >> p; if (s == ACCEPT ) { if (extra.find(p) != extra.end()) { for (auto it : extra) { if (it < p) buy.insert(it); else if (it > p) sell.insert(it); } ans = (ans + ans) % 1000000007; extra.clear(); } else if (buy.find(p) != buy.end()) { auto it = buy.end(); it--; if (*it != p) ans = 0; it = buy.find(p); buy.erase(it); for (auto it : extra) { sell.insert(it); } extra.clear(); } else { auto it = sell.find(p); assert(it != sell.end()); if (it != sell.begin()) ans = 0; sell.erase(it); for (auto it : extra) { buy.insert(it); } extra.clear(); } } else { if (buy.empty()) { if (sell.empty()) { extra.insert(p); } else { auto it = sell.begin(); if (p > *it) sell.insert(p); else extra.insert(p); } } else { auto it = buy.end(); it--; if (sell.empty()) { if (p < *it) buy.insert(p); else extra.insert(p); } else { auto jt = sell.begin(); if (p > *it && p < *jt) extra.insert(p); else if (p < *it) buy.insert(p); else sell.insert(p); } } } } long long int res = ((ans * 1LL) * (extra.size() + 1)) % 1000000007; return cout << res << n , false; } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (b == 0) { return a; } gcd(b, a % b); } int n, m, a, b, t; bool eo = 0; int main() { cin >> n >> m; n++; m++; for (int i = 1; i <= n; i++) { if (i == 1) cin >> a; else cin >> t; } for (int i = 1; i <= m; i++) { if (i == 1) cin >> b; else cin >> t; } if (a * b < 0) eo = 1; if (n > m) { if (eo) cout << - ; cout << Infinity << endl; } if (n < m) { cout << 0/1 ; } if (n == m) { a = abs(a), b = abs(b); int t = gcd(a, b); if (eo) cout << - ; a /= t, b /= t; cout << a << / << b; } } |
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_buttons (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 7: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] d1_data_in;
reg [ 7: 0] d2_data_in;
wire [ 7: 0] data_in;
reg [ 7: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 7: 0] edge_detect;
wire irq;
reg [ 7: 0] irq_mask;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({8 {(address == 0)}} & data_in) |
({8 {(address == 2)}} & irq_mask) |
({8 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[7 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[4] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[4] <= 0;
else if (edge_detect[4])
edge_capture[4] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[5] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[5] <= 0;
else if (edge_detect[5])
edge_capture[5] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[6] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[6] <= 0;
else if (edge_detect[6])
edge_capture[6] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[7] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[7] <= 0;
else if (edge_detect[7])
edge_capture[7] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = ~d1_data_in & d2_data_in;
endmodule
|
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_ff
// ============================================================
// File Name: lpm_ff_v1.v
// Megafunction Name(s):
// lpm_ff
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module lpm_ff_v1 (
clock,
data,
q);
input clock;
input [63:0] data;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
lpm_ff lpm_ff_component (
.clock (clock),
.data (data),
.q (sub_wire0)
// synopsys translate_off
,
.aclr (),
.aload (),
.aset (),
.enable (),
.sclr (),
.sload (),
.sset ()
// synopsys translate_on
);
defparam
lpm_ff_component.lpm_fftype = "DFF",
lpm_ff_component.lpm_type = "LPM_FF",
lpm_ff_component.lpm_width = 64;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: DFF NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "64"
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3_LP_V
`define SKY130_FD_SC_LP__OR3_LP_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3_lp (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or3_lp (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3_LP_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, d; cin >> n >> m >> d; vector<int> v(n * m, 0); for (int i = 0; i < n * m; i++) cin >> v[i]; int ans = INT_MAX; for (int i = 0; i < n * m; i++) { int temp_ans = 0; for (int j = 0; j < n * m; j++) { if (abs(v[j] - v[i]) % d != 0) { temp_ans = -1; break; } else { temp_ans += abs(v[j] - v[i]) / d; } } ans = min(temp_ans, ans); if (ans == -1) break; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 5 * (1e5 + 5); vector<int> e[MAX]; vector<int> ice[MAX]; int n, m; int ans[MAX]; bool vis[MAX]; int cnt; void dfs(int now, int pre) { int len = ice[now].size(); for (int i = 0; i <= len; i++) vis[i] = 0; for (int i = 0; i < len; i++) if (ans[ice[now][i]]) vis[ans[ice[now][i]]] = 1; int f = 1; for (int i = 0; i < len; i++) if (!ans[ice[now][i]]) { int t = ice[now][i]; while (vis[f]) f++; ans[t] = f++; } for (int i = 0; i < e[now].size(); i++) if (e[now][i] != pre) dfs(e[now][i], now); } int main() { cin >> n >> m; int mx = 0; for (int i = 1; i <= n; i++) { int u, g; scanf( %d , &u); mx = max(mx, u); for (int j = 1; j <= u; j++) { scanf( %d , &g); ice[i].push_back(g); } } for (int i = 1; i <= n - 1; i++) { int x, y; scanf( %d%d , &x, &y); e[x].push_back(y); e[y].push_back(x); } dfs(1, -1); if (mx) printf( %d n , mx); else printf( 1 n ); if (ans[1]) printf( %d , ans[1]); else printf( 1 ); for (int i = 2; i <= m; i++) { if (ans[i]) printf( %d , ans[i]); else printf( 1 ); } puts( ); return 0; } |
/*
* Copyright (c) 2014 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
`default_nettype none
module main;
class test_t;
reg [1:0] a;
reg [2:0] b;
function new (int ax, int bx);
begin
a = ax;
b = bx;
end
endfunction // new
endclass // test_t
test_t foo [0:3][0:7], tmp;
bit [3:0] idx1, idx2;
initial begin
for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
foo[idx1][idx2] = new(idx1,idx2);
end
foreach (foo[ia,ib]) begin
if (ia > 3 || ib > 7) begin
$display("FAILED -- index out of range: ia=%0d, ib=%0d", ia, ib);
$finish;
end
tmp = foo[ia][ib];
if (tmp.a !== ia[1:0] || tmp.b !== ib[2:0]) begin
$display("FAILED -- foo[%0d][%0d] == %b", ia, ib, {tmp.a, tmp.b});
$finish;
end
foo[ia][ib] = null;
end
for (idx1 = 0 ; idx1 < 4 ; idx1 = idx1+1) begin
for (idx2 = 0 ; idx2 <= 7 ; idx2 = idx2+1)
if (foo[idx1][idx2] != null) begin
$display("FAILED -- foreach failed to visit foo[%0d][%0d]", idx1,idx2);
$finish;
end
end
$display("PASSED");
end
endmodule // main
|
`timescale 1ns/1ns
/*
* Trial test bench for clock switching between two asynchronous clocks, but where one clock is synchronous to a much
* higher speed clock which is used to control the digital state machine
*
* Enable the `define STOP_IN_PHI1_D to stop the clocks low for the handover, and omit it to stop in PHI2.
*
* ie for Beeb816 there's not much time to detect whether to switch to the low speed clock when running in a
* high speed mode if STOP_ON_PHI1 is selected - this is probably why we defaulted to stopping in PHI2 instead.
*
* In this version
* o hsclk = high speed clock
* o hsclk_by4 = hsclk div 4, alternative for 65816 clock
* o hsclk_by2 = hsclk div 2, expected to be the 65816 CPU clock
* o lsclk = low speed clock
*
* The state machine needs at least a 2x relationship between hsclk and the CPU clock, and assumes that
* the lsclk is much slower. Clock switching with this version is quicker than with the fully async one,
* but there is still the same limitation that when stopping in PHI1 (PHI2) the clock selection signal must only
* change in PHI1 (PHI2).
*
* Sample clock must be >= 6x faster than the async BBC clock due to the length of the retiming chain.
*
* Setting stop on PHI1 requires the state machine to wait with clock low until it sees a falling edge on the other clock
* Setting stop on PHI2 requires the state machine to wait with clock low until it sees a rising edge on the other clock
*
*
*/
//`define STOP_ON_PHI1_D 1
//`define DIVIDE_BY_4_D
`define CHANGEDGE negedge
`define LSCLK_HALF_CYCLE 250 // 2MHz mother board clock
`define HSCLK_HALF_CYCLE 30.5 // 16.384MHZ XTAL
`define HSCLK_DIV 2'b00
`define CPUCLK_DIV 2'b00
module clkctrl2_tb ;
reg reset_b_r;
reg lsclk_r;
reg hsclk_r;
reg hienable_r;
wire clkout;
wire hsclk_selected_w;
initial
begin
$dumpvars();
reset_b_r = 0;
lsclk_r = 0;
hsclk_r = 0;
hienable_r = 0;
#500 reset_b_r = 1;
#2000;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 1;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 0;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 1;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 0;
#2500 @ ( `CHANGEDGE clkout);
#(`HSCLK_HALF_CYCLE-4) hienable_r = 1;
#2000 $finish();
end
always
#`LSCLK_HALF_CYCLE lsclk_r = !lsclk_r ;
always
#`HSCLK_HALF_CYCLE hsclk_r = !hsclk_r ;
`ifdef SYNC_SWITCH_D
clkctrl2 clkctrl2_u(
.hsclk_in(hsclk_r),
.lsclk_in(lsclk_r),
.rst_b(reset_b_r),
.hsclk_sel(hienable_r),
.hsclk_div_sel(`HSCLK_DIV),
.cpuclk_div_sel(`CPUCLK_DIV),
.hsclk_selected(hsclk_selected_w),
.clkout(clkout)
);
`else
clkctrl clkctrl_u(
.hsclk_in(hsclk_r),
.lsclk_in(lsclk_r),
.rst_b(reset_b_r),
.hsclk_sel(hienable_r),
.cpuclk_div_sel(`CPUCLK_DIV),
.hsclk_selected(hsclk_selected_w),
.clkout(clkout)
);
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int x, y, c1 = 0, c2 = 0, i1 = 0, i2 = 0, t, cou = 0; cin >> x >> y; if (y < x) { t = x; x = y; y = t; } while (x != y) { if (c1 <= c2) { if (c1 == 0) c1 = 1; x++; i1++; c1 += i1; cou += i1; } else { if (c2 == 0) c2 = 1; y--; i2++; c2 += i2; cou += i2; } } cout << cou; return 0; } |
#include <bits/stdc++.h> using namespace std; const int Max_L = 100000 + 100, inf = ~0U >> 2; pair<int, int> Ret[1000]; int main() { int L, b, f; cin >> L >> f >> b; int n; cin >> n; set<pair<int, int> > S; S.insert(pair<int, int>(-inf, -inf)); S.insert(pair<int, int>(inf, inf)); for (int i = 0; i < n; i++) { int t, len; cin >> t >> len; if (t == 1) { bool ok = false; for (typeof(S.begin()) it = S.begin(); it != S.end(); it++) { if (it == --S.end()) continue; int l = max(it->second + f, 0); ++it; int r = min(it->first - b, L); --it; if (r - l >= len) { ok = true; cout << l << endl; Ret[i] = pair<int, int>(l, l + len); S.insert(Ret[i]); break; } } if (!ok) cout << -1 << endl; } else { len--; S.erase(Ret[len]); } } } |
// Tests that packed structs can have signed/unsigned modifier and that signed
// packed structs when used as a primary behave correctly.
module test;
// Unsigned by default
struct packed {
logic [15:0] x;
} s1;
// Explicitly unsigned
struct packed unsigned {
logic [15:0] x;
} s2;
// Explicitly signed
struct packed signed {
logic [15:0] x;
} s3;
bit failed = 1'b0;
`define check(x) \
if (!(x)) begin \
$display("FAILED: ", `"x`"); \
failed = 1'b1; \
end
initial begin
s1 = -1;
s2 = -1;
s3 = -1;
`check(!$is_signed(s1));
`check(!$is_signed(s2));
`check($is_signed(s3));
// These evaluate as signed
`check($signed(s1) < 0);
`check($signed(s2) < 0);
`check(s3 < 0);
// These all evaluate as unsigned
`check(s1 > 0);
`check(s2 > 0);
`check(s3.x > 0)
`check(s3[15:0] > 0)
`check({s3} > 0)
`check($unsigned(s3) > 0)
`check(s3 > 16'h0)
if (!failed) begin
$display("PASSED");
end
end
endmodule
|
#include<bits/stdc++.h> using namespace std; typedef long long ll; void solve() { int x,y; cin>>x>>y; string s; cin>>s; int cR=0,cU=0,cL=0,cD=0; for(int i=0;i<s.size();i++) { if(s[i]== R ) cR++; else if(s[i]== U ) cU++; else if(s[i]== L ) cL++; else cD++; } //cout<<cR<< <<cL<< <<cU<< <<cD<< n ; if(x>0&&y>0) { if(cR>=x&&cU>=y) cout<< YES n ; else cout<< NO n ; } else if(x>0&&y<0) { if(cR>=x&&cD>=abs(y)) cout<< YES n ; else cout<< NO n ; } else if(x<0&&y>0) { if(cL>=abs(x)&&cU>=y) cout<< YES n ; else cout<< NO n ; } else if(x<0&&y<0) { if(cL>=abs(x)&&cD>=abs(y)) cout<< YES n ; else cout<< NO n ; } else { if(x>0&&y==0) { if(cR>=x) cout<< YES n ; else cout<< NO n ; } else if(x<0&&y==0) { if(cL>=abs(x)) cout<< YES n ; else cout<< NO n ; } else if(x==0&&y>0) { if(cU>=y) cout<< YES n ; else cout<< NO n ; } else if(x==0&&y<0) { if(cD>=abs(y)) cout<< YES n ; else cout<< NO n ; } else cout<< NO n ; } } int main() { int t; ios::sync_with_stdio(false); cin>>t; cin.tie(0); cout.tie(0); while(t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; if (n == 1) { cout << 1; return 0; } if (n & 1) { if (m <= n / 2) cout << m + 1; else cout << m - 1; } else { if (m <= n / 2) cout << m + 1; else cout << m - 1; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLXBP_PP_BLACKBOX_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxbp (
Q ,
Q_N ,
D ,
GATE,
VPWR,
VGND
);
output Q ;
output Q_N ;
input D ;
input GATE;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBP_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk, fastclk
);
input clk;
input fastclk;
genvar unused;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire o_com; // From b of t_inst_first_b.v
wire o_seq_d1r; // From b of t_inst_first_b.v
// End of automatics
integer _mode; // initial _mode=0
reg na,nb,nc,nd,ne;
wire ma,mb,mc,md,me;
wire da,db,dc,dd,de;
reg [7:0] wa,wb,wc,wd,we;
wire [7:0] qa,qb,qc,qd,qe;
wire [5:0] ra;
wire [4:0] rb;
wire [29:0] rc;
wire [63:0] rd;
reg [5:0] sa;
reg [4:0] sb;
reg [29:0] sc;
reg [63:0] sd;
reg _guard1; initial _guard1=0;
wire [104:0] r_wide = {ra,rb,rc,rd};
reg _guard2; initial _guard2=0;
wire [98:0] r_wide0 = {rb,rc,rd};
reg _guard3; initial _guard3=0;
wire [93:0] r_wide1 = {rc,rd};
reg _guard4; initial _guard4=0;
wire [63:0] r_wide2 = {rd};
reg _guard5; initial _guard5=0;
wire [168:0] r_wide3 = {ra,rb,rc,rd,rd};
reg [127:0] _guard6; initial _guard6=0;
t_inst_first_a a (
.clk (clk),
// Outputs
.o_w5 ({ma,mb,mc,md,me}),
.o_w5_d1r ({da,db,dc,dd,de}),
.o_w40 ({qa,qb,qc,qd,qe}),
.o_w104 ({ra,rb,rc,rd}),
// Inputs
.i_w5 ({na,nb,nc,nd,ne}),
.i_w40 ({wa,wb,wc,wd,we}),
.i_w104 ({sa,sb,sc,sd})
);
reg i_seq;
reg i_com;
wire [15:14] o2_comhigh;
t_inst_first_b b (
.o2_com (o2_comhigh),
.i2_com ({i_com,~i_com}),
.wide_for_trace (128'h1234_5678_aaaa_bbbb_cccc_dddd),
.wide_for_trace_2 (_guard6 + 128'h1234_5678_aaaa_bbbb_cccc_dddd),
/*AUTOINST*/
// Outputs
.o_seq_d1r (o_seq_d1r),
.o_com (o_com),
// Inputs
.clk (clk),
.i_seq (i_seq),
.i_com (i_com));
// surefire lint_off STMINI
initial _mode = 0;
always @ (posedge fastclk) begin
if (_mode==1) begin
if (o_com !== ~i_com) $stop;
if (o2_comhigh !== {~i_com,i_com}) $stop;
end
end
always @ (posedge clk) begin
//$write("[%0t] t_inst: MODE = %0x NA=%x MA=%x DA=%x\n", $time, _mode,
// {na,nb,nc,nd,ne}, {ma,mb,mc,md,me}, {da,db,dc,dd,de});
$write("[%0t] t_inst: MODE = %0x IS=%x OS=%x\n", $time, _mode, i_seq, o_seq_d1r);
if (_mode==0) begin
$write("[%0t] t_inst: Running\n", $time);
_mode<=1;
{na,nb,nc,nd,ne} <= 5'b10110;
{wa,wb,wc,wd,we} <= {8'ha, 8'hb, 8'hc, 8'hd, 8'he};
{sa,sb,sc,sd} <= {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210};
//
i_seq <= 1'b1;
i_com <= 1'b1;
end
else if (_mode==1) begin
_mode<=2;
if ({ma,mb,mc,md,me} !== 5'b10110) $stop;
if ({qa,qb,qc,qd,qe} !== {8'ha,8'hb,8'hc,8'hd,8'he}) $stop;
if ({sa,sb,sc,sd} !== {6'hf, 5'h3, 30'h12345, 32'h0abc_abcd, 32'h7654_3210}) $stop;
end
else if (_mode==2) begin
_mode<=3;
if ({da,db,dc,dd,de} !== 5'b10110) $stop;
if (o_seq_d1r !== ~i_seq) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin
$write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5);
$stop;
end
end
// surefire lint_off UDDSDN
wire _unused_ok = |{1'b1, r_wide0, r_wide1,r_wide2,r_wide3,r_wide};
endmodule
|
#include <bits/stdc++.h> using namespace std; bool SR(int &x) { return scanf( %d , &x) == 1; } bool SR(long long &x) { return scanf( %lld , &x) == 1; } bool SR(double &x) { return scanf( %lf , &x) == 1; } bool SR(char *s) { return scanf( %s , s) == 1; } bool RI() { return true; } template <typename I, typename... T> bool RI(I &x, T &...tail) { return SR(x) && RI(tail...); } void SP(const int x) { printf( %d , x); } void SP(const long long x) { printf( %lld , x); } void SP(const double x) { printf( %.16lf , x); } void SP(const char *s) { printf( %s , s); } void PL() { puts( ); } template <typename I, typename... T> void PL(const I x, const T... tail) { SP(x); if (sizeof...(tail)) putchar( ); PL(tail...); } const int maxn = 1e2 + 2; vector<bool> a[maxn]; int n, m, k; void read() { RI(n, m, k); for (int i = 0; i < int(n); i++) a[i].resize(m); for (int i = 0; i < int(n); i++) for (int j = 0; j < int(m); j++) { int x; RI(x); a[i][j] = (x == 1); } } void build() {} int doo(const vector<bool> &v) { int ans = 0; for (int i = 0; i < int(n); i++) { int c[2] = {0, 0}; for (int j = 0; j < int(m); j++) c[v[j] ^ a[i][j]]++; ans += min(c[0], c[1]); } return ans; } void sol() { int ans = k + 1; if (n > 10) { for (int i = 0; i < int(n); i++) ans = min(ans, doo(a[i])); } else { vector<bool> c[maxn]; for (int i = 0; i < int(m); i++) c[i].resize(n); for (int i = 0; i < int(n); i++) for (int j = 0; j < int(m); j++) c[j][i] = a[i][j]; swap(n, m); for (int i = 0; i < int(n); i++) a[i] = c[i]; vector<bool> v(m); for (int i = 0; i < int((1 << m)); i++) { for (int j = 0; j < int(m); j++) v[j] = ((i >> j) & 1); ans = min(ans, doo(v)); } } if (ans <= k) PL(ans); else PL(-1); } int main() { read(); build(); sol(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main(void) { long long n, k; cin >> n >> k; long long len = (1LL << n) - 1; while (true) { long long mid = len / 2 + 1; if (k == mid) break; if (k > mid) k -= mid; n--; len = (1LL << n) - 1; } cout << n << endl; return 0; } |
`timescale 1ns/100ps
// -----------------------------------------------------------------------------
// One-level up Hierarchical module
// -----------------------------------------------------------------------------
module a_h
// Verilog 2001 style
#(parameter M=5, N=3)
(
// Outputs
output [N-1:0] [M-1:0] a_o1 // From Ia of autoinst_sv_kulkarni_base.v
// End of automatics
// AUTOINPUT*/
);
/*AUTOWIRE*/
autoinst_sv_kulkarni_base
#(/*AUTOINSTPARAM*/
// Parameters
.M (M),
.N (N))
Ia
(/*AUTOINST*/
// Outputs
.a_o1 (a_o1/*[N-1:0][M-1:0]*/),
// Inputs
.a_i1 (a_i1/*[N-1:0][M-1:0]*/)); // <---- BUG?
endmodule
// -----------------------------------------------------------------------------
// Top-level module or Testbench
// -----------------------------------------------------------------------------
module top;
parameter M=4;
parameter N=2;
wire [N-1:0] a_o1;
logic [N-1:0][M-1:0] a_i1;
logic temp;
/*AUTOWIRE*/
// Workaround to fix multi-dimensional port problem
// a) Set "verilog-auto-inst-vector = nil"
// b) ----> a_h AUTO_TEMPLATE ( .\(.*\) (\1), ); */
a_h #(/*AUTOINSTPARAM*/
// Parameters
.M (M),
.N (N))
Ua_h
(/*AUTOINST*/
// Outputs
.a_o1 (a_o1/*[N-1:0][M-1:0]*/)); // <---- BUG?
// Stimulus
initial begin
a_i1 = { 4'h0, 4'h2 };
#5;
$display("Loop Init: a_i1 = { %h, %h } a_o1 = %h\n",
a_i1[1], a_i1[0], a_o1);
#5;
for (int i=0; i<1; i++) begin
for (int j=0; j<N; j++) begin
temp = 1'b0;
for (int k=0; k<M; k++) begin
a_i1[j][k] = temp;
temp = ~temp;
end
end
#5;
$display("Loop %0d: a_i1 = { %h, %h } a_o1 = %h\n",
i, a_i1[1], a_i1[0], a_o1);
#5;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5e5 + 10; int n, m, q, times[maxn]; long long a[maxn]; int main() { scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= n; ++i) { int x; scanf( %d , &x); a[i] = (long long)(times[x]++) * m + x; } sort(a + 1, a + 1 + n); for (int i = 1; i <= n; ++i) a[i] -= i; while (q--) { long long k; scanf( %lld , &k); k += lower_bound(a + 1, a + 1 + n, k - n) - a - 1 - n; printf( %lld n , (k - 1) % m + 1); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BO_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A21BO_PP_BLACKBOX_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BO_PP_BLACKBOX_V
|
#include <bits/stdc++.h> const double EPS = 1e-8; using namespace std; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } template <typename A, size_t N, typename T> void Fill(A (&array)[N], const T &val) { std::fill((T *)array, (T *)(array + N), val); } class Graph { public: int vn; int sumcost = 0; vector<vector<pair<int, int>>> g; Graph(int n) { vn = n; g.resize(n); } virtual void con(int a, int b, int w) = 0; int getWeight(int f, int t) { auto itr = lower_bound((g[f]).begin(), (g[f]).end(), make_pair(t, INT_MIN)); if (itr != g[f].end()) return itr->second; return INT_MIN; } int Costsum() { return sumcost; } void scan(int edcount, bool oindexed, bool w) { for (int i = (0); (edcount) > i; i++) { int a, b, c = 1; scanf( %d %d , &a, &b); if (w) scanf( %d , &c); con(a - oindexed, b - oindexed, c); } } }; class BiDGraph : public Graph { public: BiDGraph(int n) : Graph(n) {} void con(int a, int b, int w = 1) { g[a].push_back({b, w}); g[b].push_back({a, w}); sumcost++; } }; struct RSQ { int n; vector<int> dat; RSQ() {} RSQ(int n_) { n = 1; while (n < n_) n *= 2; dat.resize(2 * n - 1, 0); } void add(int k, int a) { k += n - 1; dat[k] += a; while (k > 0) { k = (k - 1) / 2; dat[k] = dat[2 * k + 1] + dat[2 * k + 2]; } } int query(int a, int b) { return query(a, b, 0, 0, n); } int query(int a, int b, int k, int l, int r) { if (r <= a || b <= l) return 0; if (a <= l && r <= b) return dat[k]; int vl = query(a, b, 2 * k + 1, l, (l + r) / 2); int vr = query(a, b, 2 * k + 2, (l + r) / 2, r); return vl + vr; } }; class Heavy_Light_Decomposition { public: BiDGraph g, compg; vector<int> sz, depth, chain, par; int bn = 0; vector<int> bvn, inbn; vector<vector<int>> bv; Heavy_Light_Decomposition(BiDGraph graph, vector<int> root) : g(graph), compg(graph.vn), sz(graph.vn, 1), depth(graph.vn), chain(graph.vn), par(graph.vn), bvn(graph.vn, -1), inbn(graph.vn) { for (auto itr : root) getsz(itr, itr); bv.push_back(vector<int>()); for (auto itr : root) { if (bv[bv.size() - 1].size()) bv.push_back(vector<int>()), bn++; HLD(itr, -1, itr, bn); } } int getsz(int cur, int p) { par[cur] = p; for (auto itr : g.g[cur]) if (p != itr.first) depth[itr.first] = depth[cur] + 1, sz[cur] += getsz(itr.first, cur); return sz[cur]; } void HLD(int cur, int p, int head, int num) { chain[cur] = head, bvn[cur] = num; inbn[cur] = bv[num].size(), bv[num].push_back(cur); pair<int, int> Maxc = {-1, -1}; for (auto itr : g.g[cur]) if (itr.first != p) Maxc = max(Maxc, {sz[itr.first], itr.first}); for (auto itr : g.g[cur]) if (itr.first != p) { int nb = num; if (itr.first != Maxc.second) { bv.push_back(vector<int>()); nb = ++bn; } HLD(itr.first, cur, itr.first == Maxc.second ? head : itr.first, nb); } } int lca(int a, int b) { if (chain[a] == chain[b]) return depth[a] < depth[b] ? a : b; if (depth[chain[a]] > depth[chain[b]]) return lca(par[chain[a]], b); return lca(a, par[chain[b]]); } void for_each_edge(int a, int b, function<void(int, int)> func) { if (chain[a] == chain[b]) return func(inbn[a] < inbn[b] ? a : b, inbn[a] < inbn[b] ? b : a); if (depth[chain[a]] < depth[chain[b]]) swap(a, b); for_each_edge(a, chain[a], func), for_each_edge(par[chain[a]], b, func); } }; struct UnionFind { vector<int> data; UnionFind(int size) : data(size, -1) {} bool unionSet(int x, int y) { x = root(x); y = root(y); if (x != y) { if (data[y] < data[x]) swap(x, y); data[x] += data[y]; data[y] = x; } return x != y; } bool findSet(int x, int y) { return root(x) == root(y); } int root(int x) { return data[x] < 0 ? x : data[x] = root(data[x]); } bool isroot(int x) { return data[x] < 0; } int size(int x) { return -data[root(x)]; } }; int main() { int n; cin >> n; BiDGraph g(n); vector<int> t(n); vector<int> root; UnionFind uf(n); for (int i = (0); (n) > i; i++) { int p; scanf( %d %d , &p, &t[i]); if (p == -1) root.push_back(i); if (p > 0) uf.unionSet(i, p - 1), g.con(i, p - 1); } Heavy_Light_Decomposition hld(g, root); vector<RSQ> seg; for (int i = (0); (hld.bv.size()) > i; i++) { seg.push_back(RSQ(hld.bv[i].size())); for (int j = (0); (hld.bv[i].size()) > j; j++) seg[i].add(j, t[hld.bv[i][j]]); } int q; cin >> q; for (int i = (0); (q) > i; i++) { int mode, p, c; scanf( %d %d %d , &mode, &p, &c); c--, p--; if (c == p || !uf.findSet(p, c)) { printf( NO n ); continue; } int lca = hld.lca(p, c); if (mode == 1) { bool f = 0; if (lca == p) { int sum = 0; hld.for_each_edge(p, c, [&](int u, int v) { sum += seg[hld.bvn[u]].query(hld.inbn[u], hld.inbn[v] + 1); if (u == lca) { sum -= t[lca]; } else if (v == lca) { sum -= t[lca]; } }); if (sum == 0) f = 1; } printf(f ? YES n : NO n ); } else { if (lca == c) { printf( NO n ); continue; } int sum = 0, sum2 = 0; hld.for_each_edge(p, lca, [&](int u, int v) { sum += seg[hld.bvn[u]].query(hld.inbn[u], hld.inbn[v] + 1); if (u == lca) { sum -= t[lca]; } else if (v == lca) { sum -= t[lca]; } }); hld.for_each_edge(c, lca, [&](int u, int v) { sum2 += seg[hld.bvn[u]].query(hld.inbn[u], hld.inbn[v] + 1); if (u == lca) { sum2 -= t[lca]; } else if (v == lca) { sum2 -= t[lca]; } }); if (sum == 0 && sum2 == (hld.depth[c] - hld.depth[lca])) printf( YES n ); else printf( NO n ); } } return 0; } |
/*
* Copyright 2020-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`include "../../vtr/dff/dff.sim.v"
`include "../dsp_combinational/dsp_combinational.sim.v"
/* DSP Block with register on both the inputs and the output, which use different clocks */
module DSP_INOUT_REGISTERED_DUALCLK (iclk, oclk, a, b, m, out);
localparam DATA_WIDTH = 4;
input wire iclk;
input wire oclk;
input wire [DATA_WIDTH/2-1:0] a;
input wire [DATA_WIDTH/2-1:0] b;
input wire m;
output wire [DATA_WIDTH-1:0] out;
/* Input registers on iclk */
(* pack="DFF-DSP" *)
wire [DATA_WIDTH/2-1:0] q_a;
(* pack="DFF-DSP" *)
wire [DATA_WIDTH/2-1:0] q_b;
(* pack="DFF-DSP" *)
wire q_m;
genvar i;
for (i=0; i<DATA_WIDTH/2; i=i+1) begin: input_dffs_gen
DFF q_a_ff(.D(a[i]), .Q(q_a[i]), .CLK(iclk));
DFF q_b_ff(.D(b[i]), .Q(q_b[i]), .CLK(iclk));
end
DFF m_ff(.D(m), .Q(q_m), .CLK(iclk));
/* Combinational logic */
(* pack="DFF-DSP" *)
wire [DATA_WIDTH-1:0] c_out;
DSP_COMBINATIONAL comb (.a(q_a), .b(q_b), .m(q_m), .out(c_out));
/* Output register on oclk */
wire [DATA_WIDTH-1:0] q_out;
genvar j;
for (j=0; j<DATA_WIDTH; j=j+1) begin: output_dffs_gen
DFF q_out_ff(.D(c_out[j]), .Q(out[j]), .CLK(oclk));
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRBP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DFRBP_FUNCTIONAL_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_lp__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_lp__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, CLK, RESET );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRBP_FUNCTIONAL_V |
#include <bits/stdc++.h> void answer(const std::vector<std::vector<std::string>>& v) { for (const auto& r : v) { const char* separator = ; for (const std::string& x : r) { std::cout << separator << x; separator = ; } std::cout << n ; } } void solve(unsigned k) { const size_t n = k - 1; std::vector<std::vector<std::string>> t(n, std::vector<std::string>(n)); for (size_t i = 0; i < n; ++i) { for (size_t j = 0; j < n; ++j) { unsigned c = (i + 1) * (j + 1); do { t[i][j].push_back( 0 + c % k); c /= k; } while (c != 0); std::reverse(t[i][j].begin(), t[i][j].end()); } } answer(t); } int main() { unsigned k; std::cin >> k; solve(k); return 0; } |
/*
* @Author: tmh
* @Date: 2017-07-20 15:16:05
* @File Name: RegisterFile.v
*/
`include "define.v"
module RegisterFile (
input clk , // Clock
input rst , // Asynchronous reset active low
input [ 2:0] writeCommand,
input [ 4:0] fileAddr ,
input [`DATA_WIDTH-1:0] writeDataIn ,
input [`DATA_WIDTH-1:0] statusIn ,
input [`IO_A_WIDTH-1:0] portAIn ,
input [`IO_B_WIDTH-1:0] portBIn ,
input [`IO_C_WIDTH-1:0] portCIn ,
input [ `PC_WIDTH-1:0] pcIn ,
output [`DATA_WIDTH-1:0] fsrOut , // First Select Register out
output [`DATA_WIDTH-1:0] regfileOut , // regfile out
output [`DATA_WIDTH-1:0] statusOut , //status out
output [`IO_A_WIDTH-1:0] portAOut ,
output [`IO_B_WIDTH-1:0] portBOut ,
output [`IO_C_WIDTH-1:0] portCOut
);
// Reg
reg[`DATA_WIDTH - 1:0] status;
reg[`DATA_WIDTH - 1:0] FSReg;
reg[`IO_A_WIDTH - 1:0] portA;
reg[`IO_B_WIDTH - 1:0] portB;
reg[`IO_C_WIDTH - 1:0] portC;
reg[`DATA_WIDTH - 1:0] indirect; // not real register
reg[`DATA_WIDTH - 1:0] direct; // not real register
// MEM
reg [`DATA_WIDTH - 1:0] GPR [31:8];
//assign
assign fsrOut = FSReg;
assign regfileOut = (fileAddr == `ADDR_INDF) ? indirect : direct;
assign statusOut = status;
assign portAOut = portA;
assign portBOut = portB;
assign portCOut = portC;
// fsr indirect read
always @(*) begin
case (FSReg[4:0])
`ADDR_INDF: begin
indirect = `DATA_WIDTH'b0;
end
`ADDR_TMR0: begin
indirect = `DATA_WIDTH'b0;
end
`ADDR_PCL: begin
indirect = pcIn[7:0];
end
`ADDR_STATUS: begin
indirect = status;
end
`ADDR_FSR: begin
indirect = FSReg;
end
`ADDR_PORTA: begin
indirect = {4'b0000, portAIn};
end
`ADDR_PORTB: begin
indirect = portBIn;
end
`ADDR_PORTC: begin
indirect = portCIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F:begin
indirect = GPR[FSReg[4:0]];
end
default: ;
endcase
end
// fsr direct read
always @(*) begin
case (fileAddr)
`ADDR_INDF: begin
direct = `DATA_WIDTH'bX;
end
`ADDR_TMR0: begin
direct = `DATA_WIDTH'bX;
end
`ADDR_PCL: begin
direct = pcIn[7:0];
end
`ADDR_STATUS: begin
direct = status;
end
`ADDR_FSR: begin
direct = FSReg;
end
`ADDR_PORTA: begin
direct = {4'b0000, portAIn};
end
`ADDR_PORTB: begin
direct = portBIn;
end
`ADDR_PORTC: begin
direct = portCIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F: begin
direct = GPR[fileAddr];
end
default: ;
endcase
end
integer index;
// write block
always@(posedge clk) begin
if(!rst) begin
status <= `DATA_WIDTH'b0001_1xxx;
FSReg <= `DATA_WIDTH'b1xxx_xxxx;
portA <= `IO_A_WIDTH'bxxxx;
portB <= `IO_B_WIDTH'bxxxx_xxxx;
portC <= `IO_C_WIDTH'bxxxx_xxxx;
GPR[8] <= `DATA_WIDTH'b0000_0000;
GPR[9] <= `DATA_WIDTH'b0000_0000;
GPR[10] <= `DATA_WIDTH'b0000_0000;
GPR[11] <= `DATA_WIDTH'b0000_0000;
GPR[12] <= `DATA_WIDTH'b0000_0000;
GPR[13] <= `DATA_WIDTH'b0000_0000;
GPR[14] <= `DATA_WIDTH'b0000_0000;
GPR[15] <= `DATA_WIDTH'b0000_0000;
end
else begin
case (writeCommand)
3'b010,3'b011: begin
if(writeCommand == 3'b011) begin
status <= statusIn;
end
case (fileAddr)
`ADDR_INDF: begin
case(FSReg[4:0])
`ADDR_INDF: begin
end
`ADDR_TMR0: begin
end
`ADDR_PCL: begin
end
`ADDR_STATUS: begin
status <= {writeDataIn[7:5],status[4:3],writeDataIn[2:0]};
end
`ADDR_FSR: begin
FSReg <= writeDataIn;
end
`ADDR_PORTA: begin
portA <= writeDataIn[`IO_A_WIDTH - 1:0];
end
`ADDR_PORTB: begin
portB <= writeDataIn;
end
`ADDR_PORTC: begin
portC <= writeDataIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F: begin
GPR[FSReg[4:0]] <= writeDataIn;
end
default: ;
endcase
end
`ADDR_TMR0: begin
end
`ADDR_PCL: begin
end
`ADDR_STATUS: begin
status <= {writeDataIn[7:5],status[4:3],writeDataIn[2:0]};
end
`ADDR_FSR: begin
FSReg <= writeDataIn;
end
`ADDR_PORTA: begin
portA <= writeDataIn[`IO_A_WIDTH - 1:0];
end
`ADDR_PORTB: begin
portB <= writeDataIn;
end
`ADDR_PORTC: begin
portC <= writeDataIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F: begin
GPR[fileAddr] <= writeDataIn;
end
default : /* default */;
endcase
end
3'b001: begin
status <= statusIn;
end
3'b100: begin
FSReg <= writeDataIn;
end
default : /* default */;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool comprobarNum(vector<int> aux, int num) { for (int i = 0; i < aux.size(); i++) { if (aux[i] == num) { return true; } } return false; } int main() { int n, aux; cin >> n; vector<int> s; vector<int> numR; int contador = 1; while (n--) { cin >> aux; if (comprobarNum(s, aux)) { numR.push_back(aux); } else { s.push_back(aux); } } int max = 1; for (int i = 0; i < numR.size(); i++) { for (int j = 0; j < numR.size(); j++) { if (numR[j] == numR[i]) { contador++; } } if (contador > max) max = contador; contador = 1; } cout << max << << s.size(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 200; int h[maxn]; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } int main() { long long n, m, sx, sy, ex, ey; int q; scanf( %lld%lld%d , &n, &m, &q); long long gc = gcd(n, m); long long stp1 = n / gc, stp2 = m / gc; long long num1, num2; while (q--) { scanf( %lld%lld%lld%lld , &sx, &sy, &ex, &ey); num1 = num2 = 0; if (sx == 1) { num1 = sy / stp1; if (sy % stp1 != 0) num1++; } else { num1 = sy / stp2; if (sy % stp2 != 0) num1++; } if (ex == 1) { num2 = ey / stp1; if (ey % stp1 != 0) num2++; } else { num2 = ey / stp2; if (ey % stp2 != 0) num2++; } if (num1 == num2) printf( YES n ); else printf( NO n ); } return 0; } |
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : iReg.v ** //
// ** Project : ISAAC NEWTON ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 5, 2008 ** //
// ** Description : Internal Register for Newton core ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 5, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 2 ** //
// ** Author : kaylangu ** //
// ** Date : August 19, 2008 ** //
// ** FileName : ** //
// ** Notes : 1. Register 0 functional modification ** //
// ** 2. Bit ReOrdering function change to for loop ** //
// ** 3. Register 1 and Register 2 counter modify to use ** //
// ** Write Enable bits ** //
// ** ** //
// ** File : iReg.v ** //
// ** Revision : 3 ** //
// ** Author : kaylangu ** //
// ** Date : October 23, 2008 ** //
// ** FileName : ** //
// ** Notes : Change interrupt signal to be only one clock long ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module iReg
(/*AUTOARG*/
// Outputs
ESCR, WPTR, ICNT, FREQ, OCNT, FCNT,
// Inputs
clk, arst, idata, iaddr, iwe, FIR_WE, WFIFO_WE
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter r0setclr = 15; // Register 0 set/clr bit
parameter initWM = 8'h60;
// parameter ModuleVersion = 2;
// DATA TYPE - INPUTS AND OUTPUTS
input clk; // 100MHz Clock from BUS
input arst; // Asynchronous Reset (positive logic)
input [15:0] idata;
input [13:0] iaddr;
input iwe;
input FIR_WE;
input WFIFO_WE;
output [15:0] ESCR;
output [15:0] WPTR;
output [15:0] ICNT;
output [15:0] FREQ;
output [15:0] OCNT;
output [15:0] FCNT;
// DATA TYPE - INTERNAL REG
reg OVFL_MSK; // Overflow Mask
reg WMI_MSK; // WMI Mask
reg OVFL; // Overflow for CPTR
reg WMI; // Watermark Interrupt
reg [15:0] ICNT; // Counts the numbers of inputs
reg [7:0] OCNT_WM; // Output counter watermark
reg [7:0] OCNT_int; // Counts the numbers of outputs
reg FIR_WE_dly1;
reg [10:0] CPTR;
reg [15:0] FCNT;
reg SYNC;
// reg iReg_intr_d1;
// reg iReg_intr_1d;
reg [6:0] FREQ_int;
reg NEWFREQ;
reg START;
// DATA TYPE - INTERNAL WIRES
wire setclr;
wire reg0w;
wire reg1w;
wire reg2w;
wire reg3w;
wire reg4w;
//**************************************************************************//
//* REG 1 *//
//**************************************************************************//
assign setclr = reg0w & idata[r0setclr];
assign reg0w = (iaddr[2:0] == 3'h1) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OVFL_MSK <= 1'b0;
else if (reg0w & idata[10])
OVFL_MSK <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
WMI_MSK <= 1'b0;
else if (reg0w & idata[9])
WMI_MSK <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OVFL <= 1'b0;
else if (CPTR[10] == 1'b1) // BRAM pointer overflows
OVFL <= 1'b1;
else if (reg0w & idata[2])
OVFL <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
START <= 1'b0;
else if (reg0w & idata[3])
START <= idata[r0setclr];
else if (WMI | (FCNT[11:0] == 12'b1111_1111_1110))
START <= 1'b0;
else
START <= START;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
FIR_WE_dly1 <= 1'b0;
else
FIR_WE_dly1 <= FIR_WE;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
WMI <= 1'b0;
else if (FIR_WE_dly1 & (OCNT_int[7:0] == OCNT_WM[7:0])) // Output counter overflows
WMI <= 1'b1;
else if (reg0w & idata[1])
WMI <= idata[r0setclr];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
SYNC <= 1'b0;
else if (reg0w & idata[0])
SYNC <= idata[r0setclr];
// Read out
assign ESCR[15:0] = {setclr, 4'd0, OVFL_MSK, WMI_MSK, 5'd0, START,
OVFL, WMI, SYNC};
//**************************************************************************//
//* REG 2 *//
//**************************************************************************//
/*always @ (posedge clk or posedge arst)
if (arst != 1'b0)
SPTR[9:0] <= 10'd0;
else if (Bus2IP_WrCE[1])
SPTR[9:0] <= idata[25:16];*/
assign reg1w = (iaddr[2:0] == 3'h2) & iwe;
always @ (posedge clk or posedge SYNC)
if (SYNC != 1'b0)
CPTR[10:0] <= 11'd0;
else if (OVFL == 1'b1)
CPTR[10] <= 1'b0;
// else if (SYNC)
// CPTR[10:0] <= 11'd0;
else
CPTR[10:0] <= CPTR[10:0] + FIR_WE; //Pointer to BRAM address
// Readout
assign WPTR[15:0] = {6'd0, CPTR[9:0]};
//**************************************************************************//
//* REG 3 *//
//**************************************************************************//
assign reg2w = (iaddr[2:0] == 3'h3) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
ICNT[15:0] <= 16'd0;
else if (reg2w)
ICNT[15:0] <= idata[15:0];
else
ICNT[15:0] <= ICNT[15:0] + WFIFO_WE;
//**************************************************************************//
//* REG 4 *//
//**************************************************************************//
assign reg3w = (iaddr[2:0] == 3'h4) & iwe;
assign setclrf = reg3w & idata[7];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
FREQ_int[6:0] <= 7'h41; //Resets to frequency 65MHz
else if (setclrf)
FREQ_int[6:0] <= idata[6:0];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
NEWFREQ <= 1'b0;
else if (reg3w )
NEWFREQ <= idata[14];
assign FREQ[15:0] = {1'b0, NEWFREQ, 6'd0, setclrf, FREQ_int[6:0]};
//**************************************************************************//
//* REG 5 *//
//**************************************************************************//
assign reg4w = (iaddr[2:0] == 3'h5) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OCNT_WM[7:0] <= initWM;
else if (reg4w)
OCNT_WM[7:0] <= idata[15:8];
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
OCNT_int[7:0] <= 8'd0;
else if (reg4w)
OCNT_int[7:0] <= idata[7:0];
else
OCNT_int[7:0] <= OCNT_int[7:0] + FIR_WE;
// Read out
assign OCNT[15:0] = {OCNT_WM[7:0], OCNT_int[7:0]};
//**************************************************************************//
//* REG 6 *//
//**************************************************************************//
assign reg5w = (iaddr[2:0] == 3'h6) & iwe;
always @ (posedge clk or posedge arst)
if (arst != 1'b0)
FCNT[15:0] <= 16'd0;
else if (reg5w)
FCNT[15:0] <= idata[15:0];
else if (START)
FCNT[15:0] <= FCNT[15:0] + 1;
//**************************************************************************//
//* Read Out *//
//**************************************************************************//
//always @ (/*AS*/Bus2IP_RdCE or ESCR or ICNT or OCNT or WPTR)
/*begin
IP2Bus_Data_int[31:0] = 32'b0;
case (1'b1)
Bus2IP_RdCE[0] : IP2Bus_Data_int[31:0] = ESCR[31:0];
Bus2IP_RdCE[1] : IP2Bus_Data_int[31:0] = WPTR[31:0];
Bus2IP_RdCE[2] : IP2Bus_Data_int[31:0] = ICNT[31:0];
Bus2IP_RdCE[3] : IP2Bus_Data_int[31:0] = OCNT[31:0];
endcase // case (1'b1)
end*/
// assign iReg2IP_RdAck = |Bus2IP_RdCE[0:3];
// assign IP2Bus_WrAck = |Bus2IP_WrCE[0:3];
endmodule // iReg
|
#include <bits/stdc++.h> using namespace std; int q, w, e, W; int a[500000], k, b, c, d, n, m, ip1, ip2, a1, b1, c1, d1, m1[500000], m2[500000], m3[500000], m4[500000]; string old[2000], nov[2000], s1, s2; int main() { cin >> q; for (int i = 1; i <= q; i++) { cin >> s1 >> s2; int ok = 0; for (int j = 1; j <= k; j++) if (nov[j] == s1) { nov[j] = s2; ok = 1; break; } if (ok == 0) old[++k] = s1, nov[k] = s2; } cout << k << endl; for (int j = 1; j <= k; j++) cout << old[j] << << nov[j] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } int power(int a, int b, int p) { int ans = 1 % p; for (; b; b >>= 1) { if (b & 1) ans = (long long)ans * a % p; a = (long long)a * a % p; } return ans; } int a, b, c, d; int main() { scanf( %d%d%d%d , &a, &b, &c, &d); if (a == d && (a != 0 || c == 0)) printf( 1 n ); else printf( 0 n ); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22O_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__A22O_BEHAVIORAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22O_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; scanf( %d , &(n)); scanf( %d , &(k)); int A[101]; for (int(i) = 0; (i) < (n); (i)++) { scanf( %d , &(A[i])); } int x, y, ans = 0; for (int(i) = 0; (i) < (k); (i)++) { x = 0; y = 0; for (int(j) = 0; (j) < (n / k); (j)++) { if (A[j * k + i] == 2) y++; else x++; } ans += min(x, y); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; clock_t __stt; inline void TStart() { __stt = clock(); } inline void TReport() { printf( nTaken Time : %.3lf sec n , (double)(clock() - __stt) / CLOCKS_PER_SEC); } template <typename T> T MIN(T a, T b) { return a < b ? a : b; } template <typename T> T MAX(T a, T b) { return a > b ? a : b; } template <typename T> T ABS(T a) { return a > 0 ? a : (-a); } template <typename T> void UMIN(T &a, T b) { if (b < a) a = b; } template <typename T> void UMAX(T &a, T b) { if (b > a) a = b; } int n, q, fa[100005], deg[100005]; double p[100005], s[100005], ini; vector<int> adj[100005]; void dfs(int ver) { if (!ver) fa[ver] = -1; int i; ini += ((double)deg[ver]) * p[ver]; for (i = 0; i < (int)adj[ver].size(); ++i) { if (adj[ver][i] != fa[ver]) { fa[adj[ver][i]] = ver; s[ver] += p[adj[ver][i]]; dfs(adj[ver][i]); } } } int main() { int i, j, k; scanf( %d , &n); ini = 0; for (i = 0; i < n; ++i) { scanf( %lf , p + i); } memset(deg, -1, sizeof(deg)); for (i = 0; i < n - 1; ++i) { int u, v; scanf( %d%d , &u, &v); ++deg[u]; ++deg[v]; adj[u].push_back(v); adj[v].push_back(u); } dfs(0); for (i = 0; i < n; ++i) { ini -= p[i] * s[i]; } scanf( %d , &q); while (q--) { int u; double d; scanf( %d%lf , &u, &d); ini += (d - p[u]) * (double)deg[u]; if (fa[u] != -1) { ini += p[fa[u]] * s[fa[u]]; s[fa[u]] += d - p[u]; ini -= p[fa[u]] * s[fa[u]]; } ini += p[u] * s[u]; p[u] = d; ini -= p[u] * s[u]; printf( %.5lf n , ini + 1.0); } return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:clk_gen:1.0
// IP Revision: 0
(* X_CORE_INFO = "clk_gen,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_clk_gen_0_0,clk_gen,{}" *)
(* CORE_GENERATION_INFO = "design_1_clk_gen_0_0,clk_gen,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=clk_gen,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,CLOCK_PERIOD=8.0,INITIAL_RESET_CLOCK_CYCLES=100,RESET_POLARITY=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_clk_gen_0_0 (
clk,
sync_rst
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
output wire clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sync_rst RST" *)
output wire sync_rst;
clk_gen #(
.CLOCK_PERIOD(8.0),
.INITIAL_RESET_CLOCK_CYCLES(100),
.RESET_POLARITY(0)
) inst (
.clk(clk),
.clk_n(),
.clk_p(),
.sync_rst(sync_rst)
);
endmodule
|
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