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#include <bits/stdc++.h> using namespace std; int main() { int q; cin >> q; while (q--) { int a, b, c; cin >> a >> b >> c; int temp = min(a, b); if (temp * 3 <= a + b + c) { cout << temp << endl; continue; } else { cout << (a + b + c) / 3 << endl; continue; } } return 0; } |
module opc5wrapper
(
input USER_RESET,
output SPI_SCK,
output [0:0] SPI_CS_n,
inout SPI_IO1,
inout SPI_IO2,
inout SPI_IO3,
inout SPI_IO4,
input USER_CLOCK,
input GPIO_DIP1,
input GPIO_DIP2,
input GPIO_DIP3,
input GPIO_DIP4,
output [3:0] GPIO_LED,
input USB_RS232_RXD,
output USB_RS232_TXD,
inout SCL,
input SDA,
output [12:0] LPDDR_A,
output [1:0] LPDDR_BA,
inout [15:0] LPDDR_DQ,
output LPDDR_LDM,
output LPDDR_UDM,
inout LPDDR_LDQS,
inout LPDDR_UDQS,
output LPDDR_CK_N,
output LPDDR_CK_P,
output LPDDR_CKE,
output LPDDR_CAS_n,
output LPDDR_RAS_n,
output LPDDR_WE_n,
output LPDDR_RZQ,
input ETH_COL,
input ETH_CRS,
input ETH_MDC,
input ETH_MDIO,
output ETH_RESET_n,
input ETH_RX_CLK,
input [3:0] ETH_RX_D,
input ETH_RX_DV,
input ETH_RX_ER,
input ETH_TX_CLK,
output [3:0] ETH_TX_D,
output ETH_TX_EN
);
wire [7:0] led;
assign GPIO_LED = led[3:0];
opc5system #(
.CLKSPEED(40000000),
.BAUD(115200),
.RAMSIZE(14),
.SEVEN_SEG_DUTY_CYCLE(7)
) system (
.clk(USER_CLOCK),
.sw({4'b0, GPIO_DIP4, GPIO_DIP3, GPIO_DIP2, GPIO_DIP1}),
.led(led),
.rxd(USB_RS232_RXD),
.txd(USB_RS232_TXD),
.seg(),
.an(),
.select(!USER_RESET)
);
// Sensible defaults for AVNet On-board peripherals
assign SPI_SCK = 1'b1;
assign SPI_CS_n = 1'b1;
assign SPI_IO1 = 1'bz;
assign SPI_IO2 = 1'bz;
assign SPI_IO3 = 1'bz;
assign SPI_IO4 = 1'bz;
assign SCL = 1'bz;
assign LPDDR_A = 13'b0;
assign LPDDR_BA = 1'b0;
assign LPDDR_DQ = 16'bz;
assign LPDDR_LDM = 1'b0;
assign LPDDR_UDM = 1'b0;
assign LPDDR_LDQS = 1'bz;
assign LPDDR_UDQS = 1'bz;
assign LPDDR_CKE = 1'b0;
assign LPDDR_CAS_n = 1'b1;
assign LPDDR_RAS_n = 1'b1;
assign LPDDR_WE_n = 1'b1;
assign LPDDR_RZQ = 1'bz;
assign ETH_RESET_n = 1'b1;
assign ETH_TX_D = 4'bz;
assign ETH_TX_EN = 1'b0;
OBUFDS LPDDR_CK_inst (
.O(LPDDR_CK_P), // Diff_p output (connect directly to top-level port)
.OB(LPDDR_CK_N), // Diff_n output (connect directly to top-level port)
.I(1'b0)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_1_V
`define SKY130_FD_SC_HS__O221AI_1_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o221ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o221ai_1 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_1_V
|
// +----------------------------------------------------------------------------
// GNU General Public License
// -----------------------------------------------------------------------------
// This file is part of uDLX (micro-DeLuX) soft IP-core.
//
// uDLX is free soft IP-core: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// uDLX soft core is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with uDLX. If not, see <http://www.gnu.org/licenses/>.
// +----------------------------------------------------------------------------
// PROJECT: uDLX core Processor
// ------------------------------------------------------------------------------
// FILE NAME : top_fetch.v
// KEYWORDS : instruction fetch, program counter, pc, dlx
// -----------------------------------------------------------------------------
// PURPOSE:
// -----------------------------------------------------------------------------
module top_fetch
#(
parameter PC_DATA_WIDTH = 20,
parameter INSTRUCTION_WIDTH = 32,
parameter PC_INITIAL_ADDRESS = 20'h0
)(
input clk, // CPU core clock
input rst_n, // CPU core reset active low
input en,
input stall, // Indicates a stall insertion on the datapath
// input flush, // Force flush in pipeline registers
// input [INSTRUCTION_WIDTH-1:0] inst_mem_data_in, // SRAM input data
input select_new_pc_in, // Signal used for branch not taken
input [PC_DATA_WIDTH-1:0] new_pc_in, // New value of Program Counter
// output reg [PC_DATA_WIDTH-1:0] new_pc_out, // Updated value of the Program Counter
output [PC_DATA_WIDTH-1:0] pc_out, // Value of the Program Counter
// output reg [INSTRUCTION_WIDTH-1:0] instruction_reg_out, // CPU core fetched instruction
output [PC_DATA_WIDTH-1:0] inst_mem_addr_out, // Instruction SRAM address bus
input boot_mode
);
reg [PC_DATA_WIDTH-1:0] pc;
reg [PC_DATA_WIDTH-1:0] pc_mux_data;
reg [PC_DATA_WIDTH-1:0] pc_adder_data;
// -------------------------------------------------------------
// Multiplex to select new PC value
// -------------------------------------------------------------
always@(*)
begin
case(select_new_pc_in)
0 : pc_mux_data = pc_adder_data;
1 : pc_mux_data = new_pc_in;
endcase
end
// -------------------------------------------------------------
// Program Counter adder
// -------------------------------------------------------------
always@(*)
begin
pc_adder_data = pc + 20'd4;
end
// -------------------------------------------------------------
// Program Counter regireg [FUNCTION_WIDTH-1:0] inst_function,ster
// -------------------------------------------------------------
assign inst_mem_addr_out = pc;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
pc <= PC_INITIAL_ADDRESS;
end
else if (boot_mode) begin
pc <= PC_INITIAL_ADDRESS;
end
else if((!stall)&en) begin
pc <= pc_mux_data;
end
end
assign pc_out = pc;
// -------------------------------------------------------------
// Pipeline Registers
// The if_id pipe needs only this
// ++TODO: Plance this procedure into a module.
// -------------------------------------------------------------
// always@(posedge clk or negedge rst_n)begin
// if(!rst_n) begin
// new_pc_out <= 0;
// instruction_reg_out <= 0;
// end else if(!stall)begin
// new_pc_out <= pc;
// if(flush)begin
// instruction_reg_out <= 0;
// end
// else begin
// instruction_reg_out <= inst_mem_data_in;
// end
// end
// end
endmodule
|
/********************************************/
/* vga_monitor.v */
/* Generates VGA sync and pixel data */
/* Compatible with Altera DE1 board */
/* */
/* 2011, */
/********************************************/
module vga_monitor #(
parameter VGA = 1, // SVGA or VGA mode
parameter IRW = 4, // input red width
parameter IGW = 4, // input green width
parameter IBW = 4, // input blue width
parameter ODW = 8, // output width
parameter DLY = 3, // delay of output active
parameter COR = "RGB", // color order (RGB or BGR)
parameter FNW = 32, // filename string width
parameter FEX = "hex", // filename extension
parameter FILE = "" // filename (without extension!)
)(
// system
input wire clk, // clock
// status
input wire oa, // vga output active
input wire [ 7-1:0] f_cnt, // frame counter (resets for every second)
input wire f_start, // frame start
// vga data
input wire [IRW-1:0] r_in,
input wire [IGW-1:0] g_in,
input wire [IBW-1:0] b_in
);
////////////////////////////////////////
// internal variables
////////////////////////////////////////
/* filename */
reg [8*FNW-1:0] filename;
/* file pointer */
integer fp = 0;
/* enabled */
reg en;
/* vga oa reg */
reg [DLY-1:0] oa_r;
wire [DLY :0] oa_w;
wire oa_out;
////////////////////////////////////////
// initial values
////////////////////////////////////////
initial begin
en = 0;
end
////////////////////////////////////////
// tasks
////////////////////////////////////////
/* start monitor */
task start;
begin
en = 1;
end
endtask
/* stop monitor */
task stop;
begin
en = 0;
end
endtask
////////////////////////////////////////
// logging
////////////////////////////////////////
/* open and close file */
always @ (posedge clk)
begin
if (en) begin
if (f_start) begin
if (fp) $fclose(fp);
$sformat(filename, "%s_%1d.%s", FILE, f_cnt, FEX);
fp = $fopen(filename, "w");
end
end else begin
if (fp) $fclose(fp);
end
end
/* register vga output active */
always @ (posedge clk) oa_r <= #1 {oa_r[DLY-2:0], oa};
assign oa_w = {oa_r, oa};
assign oa_out = oa_w[DLY];
/* log data to file */
always @ (posedge clk)
begin
if (en) begin
if (oa_out) begin
if (COR == "RGB") $fwrite(fp, "%02x%02x%02x\n", {r_in, {(8-IRW){1'h0}}}, {g_in, {(8-IGW){1'h0}}}, {b_in, {(8-IBW){1'h0}}});
else $fwrite(fp, "%02x%02x%02x\n", {b_in, {(8-IBW){1'h0}}}, {g_in, {(8-IGW){1'h0}}}, {r_in, {(8-IRW){1'h0}}});
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; char a[5005], b[5005]; int la, lb; int memo[5005][5005]; int dp(int x, int y) { if (x == la || y == lb) return 0; else if (memo[x][y] != -1) { return memo[x][y]; } else { int ans1 = dp(x, y + 1) % 1000000007; int ans2 = 0; if (a[x] == b[y]) { ans2 = (dp(x + 1, y + 1) + 1) % 1000000007; } int ret = (ans1 + ans2) % 1000000007; return memo[x][y] = ret; } } int main() { scanf( %s %s , a, b); memset(memo, -1, sizeof(memo)); int i; la = strlen(a); lb = strlen(b); int ans = 0; for (i = 0; i < la; i++) { ans = (ans + dp(i, 0)) % 1000000007; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; void add(int &a, int b) { a += b; if (a >= mod) a -= mod; } int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<int> dp(20002), pre(20002, 0); int zero = 10000; int ans = 0; for (int i = 1; i <= n; ++i) { int x; cin >> x; ++pre[zero]; for (int j = 0; j <= zero << 1; ++j) { if (j >= x) add(dp[j], pre[j - x]); if (j + x <= zero * 2) add(dp[j], pre[j + x]); } add(ans, dp[zero]); if (i == n) continue; pre = dp; memset(&dp[0], 0, sizeof dp[0] * dp.size()); } cout << ans; } |
// Name: WcaUpConverter.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaUpConverter
(
//General functions.
input clock,
input reset,
input enable,
//Lines from DDUC Controller.
input wire [7:0] cfg, //Configuration lines.
input wire [12:0] rate_interp, //Interpolation rate output required by DUC block.
input wire rate_interp_we,//Rate input write enable.
input wire strobe_cic, //CIC interpolation strobe
input wire strobe_bb, //Baseband data strobe
input wire [31:0] phase_cordic, //Generated Cordic phase.
input wire [3:0] log2_rate,
//Data I/O.
input wire strobe_if,
input wire [31:0] iq_bb_in,
output reg [23:0] iq_if_out,
//CPU Interface.
input wire [11:0] rbusCtrl, // Address and control lines(12 total) { addr[7:0], readEnable, writeEnable, dataStrobe, clkbus}
inout wire [7:0] rbusData // Tri-state I/O data.
);
parameter MODE = 4'hF; //Dynamic configuration enabled by default.
//DDC Configuration Mode flags:
`define CORDIC_ENABLED 3'h1
`define CIC_ENABLED 3'h2
`define HBF_ENABLED 3'h4
`define DYNAMIC_CONFIG 4'h8
wire aclr = cfg[1]; // clear all registers
wire [15:0] ihb_in = iq_bb_in[15:0];
wire [15:0] qhb_in = iq_bb_in[31:16];
wire [11:0] icor_in;
wire [11:0] qcor_in;
wire [23:0] cor_out;
wire [15:0] icic_in;
wire [15:0] qcic_in;
wire hb_strobe_out;
wire cic_strobe_out;
//*****************************************************
// Halfband filter
//*****************************************************
generate if( MODE & `HBF_ENABLED )
begin
wire [15:0] ihbout_internal;
wire [15:0] qhbout_internal;
wire [15:0] ihb_out;
wire [15:0] qhb_out;
//Implement strobe that tighens up when data is ready so we don't
//double clock.
/*
wire rdy;
reg hbstrobeout;
always @(posedge clock)
begin
if( reset) hbstrobeout <= 1'b0;
else hbstrobeout <= (rdy & ~hbstrobeout);
end
assign dstrobe_out = hbstrobeout;
*/
// xbh_in --> |halfband interp|--> xhb_out
// where x is 'i' or 'q'
halfband_interp hb_i (
.clk(clock), // input clk
.nd(strobe_bb), // input nd
.rfd(), // output rfd
.rdy(), // output rdy
.din(ihb_in), // input [15 : 0] din
.dout(ihbout_internal)); // output [15 : 0] dout
halfband_interp hb_q(
.clk(clock), // input clk
.nd(strobe_bb), // input nd
.rfd(), // output rfd
.rdy(), // output rdy
.din(qhb_in), // input [15 : 0] din
.dout(qhbout_internal)); // output [15 : 0] dout
//Enable dynamic selection of bypass if DYNAMIC_CONFIG ENABLED, otherwise hardwire.
wire bypassHbf = MODE[3] & cfg[5];
assign icic_in = (bypassHbf) ? ihb_in : ihbout_internal;
assign qcic_in = (bypassHbf) ? qhb_in : qhbout_internal;
end
else
begin
assign icic_in = ihb_in;
assign qcic_in = qhb_in;
end
endgenerate
//*****************************************************
// CIC Interpolator
//*****************************************************
generate if( MODE & `CIC_ENABLED)
begin
wire [15:0] icic_out;
wire [15:0] qcic_out;
reg [15:0] icic_latch;
reg [15:0] qcic_latch;
WcaCicInterp cic_i (
.clock(clock),
.reset(reset | aclr),
.enable(enable),
.strobe_cic(strobe_cic),
.strobe_if(strobe_if),
.log2_rate(log2_rate),
.data_in(icic_in),
.data_out(icic_out)
);
WcaCicInterp cic_q (
.clock(clock),
.reset(reset | aclr),
.enable(enable),
.strobe_cic(strobe_cic),
.strobe_if(strobe_if),
.log2_rate(log2_rate),
.data_in(qcic_in),
.data_out(qcic_out)
);
//Latch up data so timing is consistent.
always @(posedge clock)
begin
if( strobe_if)
begin
icic_latch<= icic_out;
qcic_latch<= qcic_out;
end
end
//Enable dynamic selection of bypass if DYNAMIC_CONFIG ENABLED, otherwise hardwire.
wire bypassCic = MODE[3] & cfg[3];
assign icor_in = (bypassCic) ? icic_in[15:4] : icic_latch[15:4];
assign qcor_in = (bypassCic) ? qcic_in[15:4] : qcic_latch[15:4] ;
end
else
begin
assign icor_in = icic_in[15:4] ;
assign qcor_in = qcic_in[15:4] ;
end
endgenerate
//*****************************************************
// CORDIC Frequency Up/Down Conversion
//*****************************************************
generate if( MODE & `CORDIC_ENABLED)
begin
wire [11:0] icordicout_internal;
wire [11:0] qcordicout_internal;
//Down conversion frequency must be in the 1Qn format (see cordic doc below). 2^n-1 = pi/2 and -2^n-1 = -pi/2
//The Cordic only supports values between this range so the phase accumulator must produce values within this range.
//We rotate quadrants and adjust phase to make work.
reg [11:0] X0;
reg [11:0] Y0;
reg [11:0] A0;
always @(posedge clock)
case({strobe_if, phase_cordic[31:30]})
3'b101 : //pi/2 to pi
begin
X0 <= #1 -qcor_in;
Y0 <= #1 icor_in;
A0 <= #1 phase_cordic[31:20] - 12'h400;
end
3'b110 : //-pi/2 to -pi
begin
X0 <= #1 qcor_in;
Y0 <= #1 -icor_in;
A0 <= #1 phase_cordic[31:20] + 12'h400;
end
3'b100: // 0 to pi/2
begin
X0 <= #1 icor_in;
Y0 <= #1 qcor_in;
A0 <= #1 phase_cordic [31:20];
end
3'b111: // 0 to -pi/2
begin
X0 <= #1 icor_in;
Y0 <= #1 qcor_in;
A0 <= #1 phase_cordic [31:20];
end
endcase
// CORDIC gain is about 1.64 and formulation requires that numbers have the format of 1Qn format
// where there are 1 sign bit plus 1 integer bits and n-1 fractional bits. For a 12 bit 2's complement number
// this means that n = 11: 1 sign bit, 1 integer bit, and 10 fractional. For 1Qn format, the maximum allowable
// range input is between -2^n-1 and 2^n-1; thus with 12 bits, the maximum range is -2^10 to 2^10 (-1024 to 1024).
// In a 12 bit system, -1024 = -1.0 and 1024 = 1.0. Converting between decimal and 1Qn is
//
// 1Qn = int(1024* float_val);
// float_val = 1Qn / 1024f;
//
// 2' Complement numbers need to be scaled to conform to this standard. If value magnitude in X and Y are > 1024 overflow
// can occur. This implementation does not scale the input so need to be careful.
//
WcaCordic12 #(12,12,0) cordic
(
.ngreset(1'b1), .clock(clock),.reset(reset | aclr), .strobeData(strobe_if),
.X0(X0), .Y0(Y0),.A0(A0),
.XN(icordicout_internal), .YN(qcordicout_internal), .AN()
);
//Enable dynamic selection of bypass if DYNAMIC_CONFIG ENABLED, otherwise hardwire.
wire bypassCordic = MODE[3] & cfg[2];
assign cor_out = (bypassCordic) ? {qcor_in, icor_in} : {qcordicout_internal, icordicout_internal};
end
else // bypass
begin
assign cor_out = {qcor_in, icor_in};
end
endgenerate
//*****************************************************
// Output Latch
//*****************************************************
//Latch up data so timing is consistent.
always @(posedge clock)
begin
if( strobe_if) iq_if_out <= cor_out;
end
endmodule // WcaUpConverter |
#include <bits/stdc++.h> inline char getThirdColor(char a, char b) { char ret; if (a == B && b == G || a == G && b == B ) ret = R ; else if (a == B && b == R || a == R && b == B ) ret = G ; else if (a == R && b == G || a == G && b == R ) ret = B ; return ret; } std::unordered_map<std::string, bool> ump; inline bool solve(std::string s, char c) { if (s.size() == 1) { return s[0] == c; } if (ump.find(s) != ump.end()) return ump[s]; bool ret = false; for (int i = 0; i < s.size(); ++i) { for (int j = i + 1; j < s.size(); ++j) { if (s[i] == s[j]) { std::string next_pass{s[i]}; for (int k = 0; k < s.size(); ++k) { if (k != i && k != j) next_pass += s[k]; } ret = solve(next_pass, c); } else { char thirdColor = getThirdColor(s[i], s[j]); std::string next_pass{thirdColor}; for (int k = 0; k < s.size(); ++k) { if (k != i && k != j) next_pass += s[k]; } ret = solve(next_pass, c); } if (ret) break; } if (ret) break; } return ump[s] = ret; } int main() { int n; std::cin >> n; std::string s; std::cin >> s; std::string modified; modified.reserve(n); std::unordered_map<char, int> cnt; for (int i = 0; i < s.size(); ++i) { if (modified.empty()) { modified += s[i]; ++cnt[s[i]]; } else if (modified.back() == s[i] && cnt[s[i]] == 1) { modified += s[i]; ++cnt[s[i]]; } else if (modified.back() != s[i]) { modified += s[i]; ++cnt[s[i]]; } } std::vector<char> possible{ B , G , R }; for (int i = 0; i < possible.size(); ++i) { ump.clear(); if (solve(modified, possible[i])) { std::cout << possible[i]; } } std::cout << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4B_BEHAVIORAL_V
`define SKY130_FD_SC_MS__AND4B_BEHAVIORAL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__and4b (
X ,
A_N,
B ,
C ,
D
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B, C, D);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4B_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NOR4_PP_SYMBOL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_PP_SYMBOL_V
|
// $Id: c_regfile.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic register file
//==============================================================================
module c_regfile
(clk, write_active, write_enable, write_address, write_data, read_address,
read_data);
`include "c_functions.v"
`include "c_constants.v"
// number of entries
parameter depth = 8;
// width of each entry
parameter width = 64;
// number of write ports
parameter num_write_ports = 1;
// number of read ports
parameter num_read_ports = 1;
// select implementation variant
parameter regfile_type = `REGFILE_TYPE_FF_2D;
// width required to swelect an entry
localparam addr_width = clogb(depth);
input clk;
input write_active;
// if high, write to entry selected by write_address
input [0:num_write_ports-1] write_enable;
// entry to be written to
input [0:num_write_ports*addr_width-1] write_address;
// data to be written
input [0:num_write_ports*width-1] write_data;
// entries to read out
input [0:num_read_ports*addr_width-1] read_address;
// contents of entries selected by read_address
output [0:num_read_ports*width-1] read_data;
wire [0:num_read_ports*width-1] read_data;
genvar read_port;
genvar write_port;
generate
case(regfile_type)
`REGFILE_TYPE_FF_2D:
begin
if(num_write_ports == 1)
begin
reg [0:width-1] storage_2d [0:depth-1];
always @(posedge clk)
if(write_active)
if(write_enable)
storage_2d[write_address] <= write_data;
for(read_port = 0; read_port < num_read_ports;
read_port = read_port + 1)
begin:read_ports_2d
wire [0:addr_width-1] port_read_address;
assign port_read_address
= read_address[read_port*addr_width:
(read_port+1)*addr_width-1];
wire [0:width-1] port_read_data;
assign port_read_data = storage_2d[port_read_address];
assign read_data[read_port*width:(read_port+1)*width-1]
= port_read_data;
end
end
else
begin
// synopsys translate_off
initial
begin
$display({"ERROR: Register file %m does not support ",
"2D FF array register file models with %d ",
"write ports."}, num_write_ports);
$stop;
end
// synopsys translate_on
end
end
`REGFILE_TYPE_FF_1D_MUX, `REGFILE_TYPE_FF_1D_SEL:
begin
wire [0:num_write_ports*depth-1] write_sel_by_port;
for(write_port = 0; write_port < num_write_ports;
write_port = write_port + 1)
begin:write_ports_1d
wire [0:addr_width-1] port_write_address;
assign port_write_address
= write_address[write_port*addr_width:
(write_port+1)*addr_width-1];
wire [0:depth-1] port_write_sel;
c_decode
#(.num_ports(depth))
port_write_sel_dec
(.data_in(port_write_address),
.data_out(port_write_sel));
assign write_sel_by_port[write_port*depth:
(write_port+1)*depth-1]
= port_write_sel;
end
wire [0:depth*num_write_ports-1] write_sel_by_level;
c_interleave
#(.width(num_write_ports*depth),
.num_blocks(num_write_ports))
write_sel_by_level_intl
(.data_in(write_sel_by_port),
.data_out(write_sel_by_level));
wire [0:depth*width-1] storage_1d;
genvar level;
for(level = 0; level < depth; level = level + 1)
begin:levels
wire [0:num_write_ports-1] lvl_write_sel;
assign lvl_write_sel
= write_sel_by_level[level*num_write_ports:
(level+1)*num_write_ports-1];
wire [0:num_write_ports-1] lvl_port_write;
assign lvl_port_write = write_enable & lvl_write_sel;
wire lvl_write_enable;
assign lvl_write_enable = |lvl_port_write;
wire [0:width-1] lvl_write_data;
c_select_1ofn
#(.num_ports(num_write_ports),
.width(width))
lvl_write_data_sel
(.select(lvl_port_write),
.data_in(write_data),
.data_out(lvl_write_data));
reg [0:width-1] storage;
always @(posedge clk)
if(write_active)
if(lvl_write_enable)
storage <= lvl_write_data;
assign storage_1d[level*width:(level+1)*width-1] = storage;
end
for(read_port = 0; read_port < num_read_ports;
read_port = read_port + 1)
begin:read_ports_1d
wire [0:addr_width-1] port_read_address;
assign port_read_address
= read_address[read_port*addr_width:
(read_port+1)*addr_width-1];
wire [0:width-1] port_read_data;
case(regfile_type)
`REGFILE_TYPE_FF_1D_SEL:
begin
wire [0:depth-1] port_read_sel;
c_decode
#(.num_ports(depth))
port_read_sel_dec
(.data_in(port_read_address),
.data_out(port_read_sel));
c_select_1ofn
#(.num_ports(depth),
.width(width))
port_read_data_sel
(.select(port_read_sel),
.data_in(storage_1d),
.data_out(port_read_data));
end
`REGFILE_TYPE_FF_1D_MUX:
begin
assign port_read_data
= storage_1d[port_read_address*width +: width];
end
endcase
assign read_data[read_port*width:(read_port+1)*width-1]
= port_read_data;
end
end
endcase
//----------------------------------------------------------------------
// check parameter validity
//----------------------------------------------------------------------
// synopsys translate_off
if(depth < 2)
begin
initial
begin
$display({"ERROR: Register file module %m requires a depth ",
"of two or more entries."});
$stop;
end
end
// synopsys translate_on
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = (long long)1e18; const int N = 1234567; long long a[N], b[N]; int main() { int n, k; scanf( %d %d , &n, &k); n++; for (int i = 0; i < n; i++) { int foo; scanf( %d , &foo); a[i] = foo; } long long z = 0; int up = 0; for (int i = 0; i < n; i++) { z += a[i]; b[i] = z; if (z % 2 != 0) { break; } up++; z /= 2; } long long value = 0; int ans = 0; for (int i = n - 1; i >= 0; i--) { if (i <= up) { long long tmp = value * 2 + b[i]; long long z = a[i] - tmp; if (-k <= z && z <= k && (i != n - 1 || z != 0)) { ans++; } } value = value * 2 + a[i]; if (value < -inf || value > inf) { break; } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; bool deb = false; int i; const int N = 100011; int g[N]; int ans1[N], ans2[N]; int main() { int i, j, n, k; scanf( %d , &n), scanf( %d , &k); int a, b, c, d; scanf( %d , &a), scanf( %d , &b), scanf( %d , &c), scanf( %d , &d); if (k < n + 1 || n == 4) { printf( %d n , -1); return 0; } g[1] = a; g[2] = c; g[n] = b, g[n - 1] = d; j = 3; for (i = 1; i < n + 1; ++i) { if (i == a || i == b || i == c || i == d) continue; if (g[j] == 0) g[j] = i, j++; } for (i = 1; i < n + 1; ++i) printf( %d , g[i]); printf( n ); printf( %d , g[2]), printf( %d , g[1]); for (i = 3; i < n - 1; ++i) { printf( %d , g[i]); } printf( %d , g[n]), printf( %d n , g[n - 1]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DFBBP_PP_SYMBOL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 51123987; int len, n; char s[4000010], tmp[2000010]; long long p[4000010]; long long sum, ans; long long le[4000010], ri[4000010]; int main() { scanf( %d%s , &len, tmp + 1); s[++n] = @ ; for (int i = 1; i <= len; i++) { s[++n] = # ; s[++n] = tmp[i]; } s[++n] = # ; long long id = 0, mx = 0; for (long long i = 1; i <= n; i++) { p[i] = ((mx > i) ? min(p[id * 2 - i], mx - i) : 1); while (s[i + p[i]] == s[i - p[i]]) p[i]++; if (i + p[i] > mx) { mx = i + p[i]; id = i; } sum += 1ll * p[i] / 2; sum %= mod; le[i - p[i]]++; le[i]--; ri[i - 1]++; ri[i + p[i] - 1]--; } sum = sum * (sum - 1) / 2; sum %= mod; for (int i = 1; i <= n; i++) { le[i] += le[i - 1]; ri[i] += ri[i - 1]; if (i % 2 == 0) { sum -= 1ll * ans * le[i] % mod; sum = (sum + mod) % mod; ans = (ans + ri[i]) % mod; } } cout << (sum + mod) % mod; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3f; const int MOD = 1e9 + 7; int dir[8][2] = {-1, 0, 1, 0, 0, -1, 0, 1, -1, -1, -1, 1, 1, -1, 1, 1}; template <typename S, typename T> ostream &operator<<(ostream &os, const pair<S, T> x) { os << ( << x.first << , << x.second << ) ; return os; } template <typename S, typename T> inline bool Min(S &a, const T &b) { return a > b ? a = b, true : false; } template <typename S, typename T> inline bool Max(S &a, const T &b) { return a < b ? a = b, true : false; } template <typename S, typename T> inline void Adm(S &a, const T &b) { a = (a + b) % MOD; if (a < 0) a += MOD; } template <typename T> inline bool IsPri(T x) { if (x < 2) return false; for (T i = 2; i * i <= x; ++i) if (x % i == 0) return false; return true; } template <typename T> inline T _Gcd(T a, T b) { while (b) { T t = b; b = a % b; a = t; } return a; } template <typename T> inline int _BitCnt(T x) { int cnt = 0; while (x) ++cnt, x &= x - 1; return cnt; } inline long long Pow(long long a, long long n) { long long t = 1; a %= MOD; while (n > 0) { if (n & 1) t = t * a % MOD; a = a * a % MOD, n >>= 1; } return t % MOD; } inline int read() { static char buf[1000000], *p1 = buf, *p2 = buf; register int x = false; register char ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; register bool sgn = false; while (ch != - && (ch < 0 || ch > 9 )) ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; if (ch == - ) sgn = true, ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; while (ch >= 0 && ch <= 9 ) x = (x << 1) + (x << 3) + (ch ^ 48), ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; return sgn ? -x : x; } const int N = 1e5 + 100; char s[N]; int main() { scanf( %s , s); int n = strlen(s); string str, ss; vector<int> pos; stack<pair<int, string>> stk; for (int i = n - 1; i >= 0; --i) { char c = s[i]; if (str.empty() || str.back() != c || pos.back() - i > 1) { str.push_back(c), pos.push_back(i); if (ss.empty() || ss.back() != c) ss.push_back(c); } else { if (((int)(ss).size()) == 1 || ss[((int)(ss).size()) - 2] < c) { str.pop_back(), pos.pop_back(); if (str.empty() || str.back() != ss.back()) ss.pop_back(); } else { str.push_back(c), pos.push_back(i); if (ss.empty() || ss.back() != c) ss.push_back(c); } } pair<int, string> now = {((int)(str).size()), }; if (((int)(str).size()) <= 10) now.second = str; else now.second = str.substr(0, 2) + ... + str.substr(((int)(str).size()) - 5, 5); reverse((now.second).begin(), (now.second).end()); stk.push(now); } while (!stk.empty()) printf( %d %s n , stk.top().first, stk.top().second.c_str()), stk.pop(); return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma warning(disable : 4996) #pragma comment(linker, /STACK:20000007 ) #pragma GCC optimize( unroll-loops ) const int N = (int)1e6 + 100; const int maxn = (int)1e3 + 100; const int base = (int)1e9; const int mod = (int)1e9 + 7; const int inf = INT_MAX; const long long ll_inf = LLONG_MAX; const long double PI = acos((long double)-1.0); const long double eps = 1e-8; void solve() { int n, s; scanf( %d%d , &n, &s); vector<int> P(n); for (int i = 0; i < n; ++i) { scanf( %d , &P[i]); } multiset<int> S; for (int i = 0; i < n; ++i) { S.insert(P[i]); } map<int, int> C; for (int i = 0; i < n; ++i) { C[P[i]]++; } int ans = 0; --s; if (P[s]) { C[P[s]]--; S.erase(S.find(P[s])); C[0]++; ++ans; P[s] = 0; } ans += C[0] - 1; int have = C[0] - 1; S.erase(0); int now = 1; while (!S.empty() && now <= *(--S.end())) { if (S.find(now) != S.end()) ; else if (have) --have; else { ++ans; S.erase(--S.end()); } ++now; } printf( %d n , ans); } int main() { int T = 1; for (; T; --T) solve(); return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// both inputs are considered unsigned 16 bits-
// ddata is delay matched generic data
`timescale 1ps/1ps
module ad_mul_u16 (
// data_p = data_a * data_b;
clk,
data_a,
data_b,
data_p,
// delay interface
ddata_in,
ddata_out);
// delayed data bus width
parameter DELAY_DATA_WIDTH = 16;
localparam DW = DELAY_DATA_WIDTH - 1;
// data_p = data_a * data_b;
input clk;
input [15:0] data_a;
input [15:0] data_b;
output [31:0] data_p;
// delay interface
input [DW:0] ddata_in;
output [DW:0] ddata_out;
// internal registers
reg [DW:0] p1_ddata = 'd0;
reg [DW:0] p2_ddata = 'd0;
reg [DW:0] ddata_out = 'd0;
// internal signals
// a/b reg, m-reg, p-reg delay match
always @(posedge clk) begin
p1_ddata <= ddata_in;
p2_ddata <= p1_ddata;
ddata_out <= p2_ddata;
end
lpm_mult i_mult_macro (
.clock (clk),
.dataa (data_a),
.datab (data_b),
.result (data_p),
.aclr (1'b0),
.clken (1'b1),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 16,
lpm_mult_component.lpm_widthb = 16,
lpm_mult_component.lpm_widthp = 32;
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int n, m, i, j; string s[103]; bool ktra1() { if (n % 3 == 0) { static int chk[1000]; fill_n(chk, 1000, 0); for (int i = 1; i <= n / 3; ++i) { for (int j = 1; j <= m; ++j) { chk[s[i][j]]++; } } if (chk[s[1][1]] != m * n / 3) return false; for (int i = n / 3 + 1; i <= 2 * n / 3; ++i) { for (int j = 1; j <= m; ++j) { chk[s[i][j]]++; } } if (chk[s[n / 3 + 1][1]] != m * n / 3) return false; for (int i = 2 * n / 3 + 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { chk[s[i][j]]++; } } if (chk[s[n][1]] != m * n / 3) return false; } else return false; return true; } bool ktra2() { if (m % 3 == 0) { static int chk[1000]; fill_n(chk, 1000, 0); for (int j = 1; j <= m / 3; ++j) { for (int i = 1; i <= n; ++i) { chk[s[i][j]]++; } } if (chk[s[1][1]] != m * n / 3) return false; for (int j = m / 3 + 1; j <= 2 * m / 3; ++j) { for (int i = 1; i <= n; ++i) { chk[s[i][j]]++; } } if (chk[s[1][m / 3 + 1]] != m * n / 3) return false; for (int j = 2 * m / 3 + 1; j <= m; ++j) { for (int i = 1; i <= n; ++i) { chk[s[i][j]]++; } } if (chk[s[1][m]] != m * n / 3) return false; } else return false; return true; } int main() { cin >> n >> m; for (int i = 1; i <= n; ++i) cin >> s[i], s[i] = + s[i]; if (ktra1() || ktra2()) cout << YES ; else cout << NO ; } |
#include <bits/stdc++.h> using namespace std; const int N = 4e5 + 50; int n, m, a[N], b[N]; vector<int> G[N]; int in[N], out[N], tim, dep[N]; int mn[20][N], lg[N], p[N], k; void dfs(int u, int f) { dep[u] = dep[f] + 1; in[u] = ++tim; mn[0][p[u] = ++k] = u; for (int v : G[u]) if (v != f) dfs(v, u), mn[0][++k] = u; out[u] = tim; } int chk(int x, int y) { return dep[x] < dep[y] ? x : y; } int LCA(int x, int y) { x = p[x], y = p[y]; if (x > y) swap(x, y); int z = lg[y - x + 1]; return chk(mn[z][x], mn[z][y - (1 << z) + 1]); } int D(int x, int y) { return dep[x] + dep[y] - 2 * dep[LCA(x, y)]; } struct lll { int x, y, o; lll(int _x = 0, int _y = 0, int _o = 0) { x = _x, y = _y, o = _o; } friend lll operator+(const lll &a, const lll &b) { if (!a.o) return a; if (!b.o) return b; if (!a.x) return b; if (!b.x) return a; lll t = b; int A = D(a.x, t.x), B = D(a.x, t.y), C = D(t.x, t.y); if (A + B == C) t = lll(t.x, t.y, 1); else if (B + C == A) t = lll(a.x, t.x, 1); else if (A + C == B) t = lll(a.x, t.y, 1); else return lll(0, 0, 0); A = D(a.y, t.x), B = D(a.y, t.y), C = D(t.x, t.y); if (A + B == C) t = lll(t.x, t.y, 1); else if (B + C == A) t = lll(a.y, t.x, 1); else if (A + C == B) t = lll(a.y, t.y, 1); else return lll(0, 0, 0); return t; } }; namespace SGT { const int N = ::N << 2; lll t[N]; void up(int x) { t[x] = t[x << 1] + t[x << 1 | 1]; } void build(int x, int l, int r) { if (l == r) return t[x] = lll(b[l], b[l], 1), void(); build(x << 1, l, ((l + r) >> 1)), build(x << 1 | 1, ((l + r) >> 1) + 1, r); up(x); } void mdf(int x, int l, int r, int p, int v) { if (l == r) return t[x] = lll(v, v, 1), void(); if (p <= ((l + r) >> 1)) mdf(x << 1, l, ((l + r) >> 1), p, v); else mdf(x << 1 | 1, ((l + r) >> 1) + 1, r, p, v); up(x); } int ask(int x, int l, int r, lll z) { if (l == r) { lll y = z + t[x]; if (y.o) return l + 1; return l; } lll y = z + t[x << 1]; if (!y.o) return ask(x << 1, l, ((l + r) >> 1), z); return ask(x << 1 | 1, ((l + r) >> 1) + 1, r, y); } } // namespace SGT int main() { cin >> n; for (int i = 1; i <= n; i++) scanf( %d , &a[i]), b[a[i]] = i; for (int i = 2, x; i <= n; i++) scanf( %d , &x), G[x].push_back(i); dfs(1, 0); for (int i = 2; i <= k; i++) lg[i] = lg[i >> 1] + 1; for (int i = 1; (1 << i) <= k; i++) for (int j = 1; j + (1 << i) - 1 <= k; j++) mn[i][j] = chk(mn[i - 1][j], mn[i - 1][j + (1 << i - 1)]); SGT ::build(1, 0, n - 1); cin >> m; while (m--) { int o, x, y; scanf( %d , &o); if (o == 1) { scanf( %d%d , &x, &y); swap(a[x], a[y]); x = a[x], y = a[y]; swap(b[x], b[y]); SGT ::mdf(1, 0, n - 1, x, b[x]); SGT ::mdf(1, 0, n - 1, y, b[y]); } if (o == 2) cout << SGT ::ask(1, 0, n - 1, lll(0, 0, 1)) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int timeTook[50010][10]; int timeSpent[50010]; int main() { int numOfPictures, numOfPainters; scanf( %d %d , &numOfPictures, &numOfPainters); for (int i = 0; i < numOfPictures; i++) { for (int j = 0; j < numOfPainters; j++) { scanf( %d , &timeTook[i][j]); } } for (int i = 0; i < numOfPictures; i++) timeSpent[i] = 0; for (int painter = 0; painter < numOfPainters - 1; painter++) { int curTime = 0; for (int i = 0; i < numOfPictures; i++) { if (curTime >= timeSpent[i]) { timeSpent[i] += (curTime - timeSpent[i]) + timeTook[i][painter]; curTime += timeTook[i][painter]; } else { int waitTime = timeSpent[i] - curTime; timeSpent[i] += timeTook[i][painter]; curTime += waitTime + timeTook[i][painter]; } } } int curTime = 0; for (int i = 0; i < numOfPictures; i++) { if (curTime >= timeSpent[i]) { curTime += timeTook[i][numOfPainters - 1]; } else { int waitTime = timeSpent[i] - curTime; curTime += waitTime + timeTook[i][numOfPainters - 1]; } printf( %d , curTime); } printf( n ); return 0; } |
`include "../network_params.h"
module sub_sample( // Mean pooling
input clock,
input reset,
input [`NH_VECTOR_BITWIDTH:0] nh_vector, // ` indicates a difined macro
output [`POOL_OUT_BITWIDTH:0] pool_out
);
// parameter declarations
// wire declarations
wire [`POOL_OUT_BITWIDTH:0] adder_tree_wire [(`NEIGHBORHOOD_SIZE*2)-1-1:0]; // use n-1:0 notation to appease modelsim
// reg declarations
// assign statments
assign pool_out = adder_tree_wire[0] / `NEIGHBORHOOD_SIZE;
genvar i;
generate
for(i=(`NEIGHBORHOOD_SIZE*2)-2; i >=1; i=i-2) begin : adder_tree
pool_add2 pool_add2_inst(
.clock(clock),
.reset(reset),
.operand_a(adder_tree_wire[i-1]),
.operand_b(adder_tree_wire[i]),
.sum(adder_tree_wire[(i/2)-1])
);
end // for
endgenerate
genvar j;
generate
for(j=0; j < `NEIGHBORHOOD_SIZE; j=j+1) begin : connect_input_to_adder_tree
assign adder_tree_wire[j+`NEIGHBORHOOD_SIZE-1] = {`POOL_TREE_PAD'd0, nh_vector[(`NN_WIDTH*j)+`NN_BITWIDTH:`NN_WIDTH*j] };
end // for
endgenerate
endmodule
module pool_add2(
input clock,
input reset,
input [`POOL_OUT_BITWIDTH:0] operand_a,
input [`POOL_OUT_BITWIDTH:0] operand_b,
output reg[`POOL_OUT_BITWIDTH:0] sum
);
`ifdef POOL_RESET
always@(posedge clock or negedge reset) begin
if(reset == 1'b0)
sum <= `POOL_OUT_BITWIDTH'd0;
else
sum <= operand_a + operand_b;
end // always
`else
always@(posedge clock) begin
sum <= operand_a + operand_b;
end // always
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; unsigned int dp[100010][400]; vector<int> nima[100010]; int a[100010], b[100010]; int n, m, s, e; int solve(int all = s, int c = e) { unsigned int INF = -1; vector<int> vt[100010]; int cur = 0; memset(dp, -1, sizeof(dp)); int cnt = (all + c - 1) / c; for (int i = 0; i < m; ++i) { vt[b[i]].push_back(i + 1); } int ans = 0; for (int i = 0; i < n; ++i) { dp[cur][0] = 0; cur ^= 1; memset(dp[cur], -1, sizeof(dp[cur])); for (int j = 1; j < cnt + 1; ++j) { unsigned int pre = dp[cur ^ 1][j - 1]; unsigned int p = upper_bound(vt[a[i]].begin(), vt[a[i]].end(), pre) - vt[a[i]].begin(); if (p == vt[a[i]].size()) p = INF; else p = vt[a[i]][p]; dp[cur][j] = min(dp[cur ^ 1][j], p); if (dp[cur ^ 1][j] > p && p + i + j * c <= all) ans = max(ans, j); } } return ans; } int main() { while (cin >> n >> m >> s >> e) { memset(dp, -1, sizeof(dp)); for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); } for (int i = 0; i < m; ++i) { scanf( %d , &b[i]); nima[b[i]].push_back(i + 1); } int ans = 0; int cnt = s / e; for (int i = 0; i < n; ++i) { dp[i][0] = 0; if (nima[a[i]].size()) dp[i][1] = nima[a[i]][0]; else dp[i][1] = -1; if (i == 0) continue; for (int j = 1; j <= cnt; ++j) { unsigned int now = -1; int w = a[i]; int last = dp[i - 1][j - 1]; now = upper_bound(nima[w].begin(), nima[w].end(), last) - nima[w].begin(); if (now == nima[w].size() || dp[i - 1][j - 1] == -1) { now = -1; } else { now = nima[w][now]; } dp[i][j] = min(dp[i - 1][j], now); } } for (int i = 0; i < n; ++i) for (int j = 0; j < cnt + 1; ++j) { if (dp[i][j] != -1) { if (i + dp[i][j] + 1 + j * e <= s) ans = max(ans, j); } } cout << ans << endl; return 0; } } |
/********************************************/
/* io.v */
/* A generic implementation of IOs */
/* (buttons, switches, LEDs, ...) */
/* */
/* 2012, */
/********************************************/
module io #(
parameter SW = 1, // signal width
parameter OE = 1'b0, // output enable (direction), 0 = input, 1 = output
parameter DS = 1'b0, // default (off) state
parameter PD = 10, // push delay
parameter DBG = 0 // debug output
)(
inout wire [ SW-1:0] io
);
////////////////////////////////////////
// logic //
////////////////////////////////////////
reg [ SW-1:0] i = {SW{DS}};
reg [ SW-1:0] o = {SW{DS}};
reg [ SW-1:0] oe = {SW{OE}};
assign io = oe ? o : {SW{1'bz}};
////////////////////////////////////////
// input change detect //
////////////////////////////////////////
always @ (io) begin
if ((io & (~oe)) != (i & (~oe))) begin
if (DBG) $display ("BENCH : %M : %t : input changed from [%b] to [%b].", $time, i, ((i & ( oe | io)) | (~oe & io)));
i = i & ( oe | io);
i = i | (~oe & io);
end
end
////////////////////////////////////////
// tasks //
////////////////////////////////////////
//// dir ////
task dir;
input [ SW-1:0] dir;
begin
if (DBG) $display ("BENCH : %M : %t : output enable changed from [%b] to [%b].", $time, oe, dir);
oe = dir;
end
endtask
//// read ////
task read(data);
output [ SW-1:0] data;
begin
data = i;
end
endtask
//// on ////
task on;
input [ SW-1:0] in;
begin
if (DBG) $display ("BENCH : %M : %t : output changed from [%b] to [%b].", $time, o, (DS ? in & o : in | o));
o <= #1 DS ? in & o : in | o;
end
endtask
//// off ////
task off;
input [ SW-1:0] in;
begin
if (DBG) $display ("BENCH : %M : %t : changing state from [%b] to [%b].", $time, o, (DS ? in | o : in & o));
o <= #1 DS ? in | o : in & o;
end
endtask
//// push ////
task push;
input [ SW-1:0] in;
begin
if (DBG) $display ("BENCH : %M : %t : changing state from [%b] to [%b].", $time, o, (in ^ o));
o = #1 in ^ o;
#PD;
if (DBG) $display ("BENCH : %M : %t : changing state from [%b] to [%b].", $time, o, (in ^ o));
o = #1 in ^ o;
end
endtask
//// toggle ////
task toggle;
input [ SW-1:0] in;
begin
if (DBG) $display ("BENCH : %M : %t : changing state from [%b] to [%b].", $time, o, (in ^ o));
o = #1 in ^ o;
end
endtask
endmodule
|
// $Id: c_arbiter.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// generic arbiter
module c_arbiter
(clk, reset, update, req, gnt);
`include "c_functions.v"
`include "c_constants.v"
// number of input ports
parameter num_ports = 32;
// number fo bits required to select a port
localparam port_idx_width = clogb(num_ports);
// select type of arbiter to use
parameter arbiter_type = `ARBITER_TYPE_ROUND_ROBIN;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// update port priorities
input update;
// request vector
input [0:num_ports-1] req;
// grant vector
output [0:num_ports-1] gnt;
wire [0:num_ports-1] gnt;
generate
if(num_ports > 1)
begin
case(arbiter_type)
`ARBITER_TYPE_ROUND_ROBIN:
begin
c_rr_arbiter
#(.num_ports(num_ports),
.reset_type(reset_type))
rr_arb
(.clk(clk),
.reset(reset),
.update(update),
.req(req),
.gnt(gnt));
end
`ARBITER_TYPE_MATRIX:
begin
c_matrix_arbiter
#(.num_ports(num_ports),
.reset_type(reset_type))
m_arb
(.clk(clk),
.reset(reset),
.update(update),
.req(req),
.gnt(gnt));
end
`ARBITER_TYPE_DW_FCFS:
begin
wire rst_n;
if(reset_type == `RESET_TYPE_ASYNC)
assign rst_n = ~reset;
else
assign rst_n = 1'b1;
wire init_n;
if(reset_type == `RESET_TYPE_SYNC)
assign init_n = ~reset;
else
assign init_n = 1'b1;
wire parked;
wire locked;
wire [0:port_idx_width-1] grant_index;
DW_arb_fcfs
#(.n(num_ports),
.park_mode(0),
.output_mode(0))
dw_fcfs_arb
(.clk(clk),
.rst_n(rst_n),
.init_n(init_n),
.enable(update),
.request(req),
.lock({num_ports{1'b0}}),
.mask({num_ports{1'b0}}),
.parked(parked),
.locked(locked),
.grant(gnt),
.grant_index(grant_index));
end
endcase
end
else
assign gnt = req;
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; int main() { cin >> s; s = + s; int dem = 0; for (int i = 1; i <= s.size() - 1; i++) { if (s[i] < 97 && (s[i] - 0 ) % 2 != 0) dem++; else if (s[i] == a || s[i] == e || s[i] == i || s[i] == o || s[i] == u ) dem++; } cout << dem; } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } int calc(int a, int x, int n) { return max(0, min(x - (a + 1) / 2, n - a)); } void solve(istream &in, ostream &out) { int n, m, x, y, a, b; in >> n >> m >> x >> y >> a >> b; int d = gcd(a, b); a /= d; b /= d; int t = min(n / a, m / b); a *= t; b *= t; int x1 = calc(a, x, n); int y1 = calc(b, y, m); int x2 = x1 + a; int y2 = y1 + b; out << x1 << << y1 << << x2 << << y2 << endl; } int main() { solve(cin, cout); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string d[] = { monday , tuesday , wednesday , thursday , friday , saturday , sunday }; string a, b; int e, c, g, f, u; bool o; cin >> a >> b; for (int i = 0; i < 7; i++) { if (a == d[i]) { e = i; } if (b == d[i]) { c = i; } } u = abs(e - c); for (int m = 1; m <= 12; m++) { if (m == 1 || m == 3 || m == 5 || m == 7 || m == 8 || m == 10 || m == 12) { g = 4; f = e - g; if (f < 0) { f = 7 - abs(f); } if (d[f] == d[c]) { o = 1; cout << YES ; break; } else o = 0; } else if (m == 2) { g = 0; f = e - g; if (f < 0) { f = 7 - abs(f); } if (d[f] == d[c]) { o = 1; cout << YES ; break; } else o = 0; } else if (m == 4 || m == 6 || m == 9 || m == 1) { g = 5; f = e - g; if (f < 0) { f = 7 - abs(f); } if (d[f] == d[c]) { o = 1; cout << YES ; break; } else o = 0; } } if (o == 0) { cout << NO ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4BB_2_V
`define SKY130_FD_SC_HDLL__OR4BB_2_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog wrapper for or4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4bb_2 (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or4bb_2 (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4BB_2_V
|
`timescale 1ns/10ps
module top;
reg pass;
reg [60*8-1:0] str, cmp;
reg [7:0] bval;
reg [15:0] oval, hval;
integer dval;
time tval;
real rval;
initial begin
pass = 1'b1;
// Check the %b conversion.
bval = 8'b01101001;
cmp = "";
$sformat(str, "%0b", bval);
if (str != cmp) begin
$display("FAILED: %%0b, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "0000000001101001";
$sformat(str, "%016b", bval);
if (str != cmp) begin
$display("FAILED: %%016b, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = " ";
$sformat(str, "%-016b", bval);
if (str != cmp) begin
$display("FAILED: %%-016b, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
// Check the %o conversion.
oval = 16'o01234;
cmp = "1234";
$sformat(str, "%0o", oval);
if (str != cmp) begin
$display("FAILED: %%0o, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "00001234";
$sformat(str, "%08o", oval);
if (str != cmp) begin
$display("FAILED: %%08o, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "1234 ";
$sformat(str, "%-08o", oval);
if (str != cmp) begin
$display("FAILED: %%-08o, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
// Check the %h conversion.
hval = 16'h0abc;
cmp = "abc";
$sformat(str, "%0h", hval);
if (str != cmp) begin
$display("FAILED: %%0h, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "00000abc";
$sformat(str, "%08h", hval);
if (str != cmp) begin
$display("FAILED: %%08h, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "abc ";
$sformat(str, "%-08h", hval);
if (str != cmp) begin
$display("FAILED: %%-08h, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
// Check the %c conversion.
bval = "c";
cmp = "c";
$sformat(str, "%0c", bval);
if (str != cmp) begin
$display("FAILED: %%0c, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "000c";
$sformat(str, "%04c", bval);
if (str != cmp) begin
$display("FAILED: %%04c, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
// Check the %d conversion.
dval = 123;
cmp = "00000123";
$sformat(str, "%08d", dval);
if (str != cmp) begin
$display("FAILED: %%08d, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "+";
$sformat(str, "%+08d", dval);
if (str != cmp) begin
$display("FAILED: %%+08d, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = " 123";
$sformat(str, "%d", dval);
if (str != cmp) begin
$display("FAILED: %%d, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "123 ";
$sformat(str, "%-08d", dval);
if (str != cmp) begin
$display("FAILED: %%-08d, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "123";
$sformat(str, "%0d", dval);
if (str != cmp) begin
$display("FAILED: %%0d, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
dval = -123;
cmp = "-";
$sformat(str, "%08d", dval);
if (str != cmp) begin
$display("FAILED: %%08d, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
$sformat(str, "%+08d", dval);
if (str != cmp) begin
$display("FAILED: %%+08d, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = " -123";
$sformat(str, "%d", dval);
if (str != cmp) begin
$display("FAILED: %%d, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
// Check the %t conversion.
tval = 100_000;
cmp = "";
$sformat(str, "%010t", tval);
if (str != cmp) begin
$display("FAILED: %%010t, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = " 10000000"; // Default width is 20.
$sformat(str, "%t", tval);
if (str != cmp) begin
$display("FAILED: %%t, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "10000000 ";
$sformat(str, "%-010t", tval);
if (str != cmp) begin
$display("FAILED: %%-010t, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "10000000";
$sformat(str, "%0t", tval);
if (str != cmp) begin
$display("FAILED: %%0t, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
rval=100_000.25;
cmp = "";
$sformat(str, "%010t", rval);
if (str != cmp) begin
$display("FAILED: %%010t (real), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = " 10000025"; // Default width is 20.
$sformat(str, "%t", rval);
if (str != cmp) begin
$display("FAILED: %%t (real), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "10000025 ";
$sformat(str, "%-010t", rval);
if (str != cmp) begin
$display("FAILED: %%-010t (real), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "10000025";
$sformat(str, "%0t", rval);
if (str != cmp) begin
$display("FAILED: %%0t (real), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
// Display in ns with 10ps resolution.
$timeformat(-9, 2, " ns", 15);
cmp = "000100000.00 ns";
$sformat(str, "%015t", tval);
if (str != cmp) begin
$display("FAILED: %%015t (w/$tf), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = " 100000.00 ns";
$sformat(str, "%t", tval);
if (str != cmp) begin
$display("FAILED: %%t (w/$tf), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "100000.00 ns ";
$sformat(str, "%-015t", tval);
if (str != cmp) begin
$display("FAILED: %%-015t (w/$tf), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "100000.00 ns";
$sformat(str, "%-0t", tval);
if (str != cmp) begin
$display("FAILED: %%-0t (w/$tf), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "000100000.25 ns";
$sformat(str, "%015t", rval);
if (str != cmp) begin
$display("FAILED: %%015t (w/$tf, rl), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = " 100000.25 ns";
$sformat(str, "%t", rval);
if (str != cmp) begin
$display("FAILED: %%t (w/$tf, rl), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "100000.25 ns ";
$sformat(str, "%-015t", rval);
if (str != cmp) begin
$display("FAILED: %%-015t (w/$tf, rl), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "100000.25 ns";
$sformat(str, "%-0t", rval);
if (str != cmp) begin
$display("FAILED: %%-0t (w/$tf, rl), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
// Check the real conversions (%e, %f, %g). If one works they all
// they all work (uses system conversion).
rval = 1.25;
cmp = "000000001.250000";
$sformat(str, "%016.6f", rval);
if (str != cmp) begin
$display("FAILED: %%016.6f, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "+00000001.250000";
$sformat(str, "%+016.6f", rval);
if (str != cmp) begin
$display("FAILED: %%+016.6f, expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
rval = -1.25;
cmp = "-00000001.250000";
$sformat(str, "%016.6f", rval);
if (str != cmp) begin
$display("FAILED: %%016.6f (negative), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
cmp = "-00000001.250000";
$sformat(str, "%+016.6f", rval);
if (str != cmp) begin
$display("FAILED: %%+016.6f (negative), expected %0s, got %0s", cmp, str);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`include "../include/tune.v"
module drammem(
input [9:0] ma,
inout [15:0] d,
input ras_n,
input ucas_n,
input lcas_n,
input we_n
);
parameter _verbose_ = 1;
parameter _add_to_addr_ = 0;
parameter _filter_out_ = 32'h91;
parameter _init_ = 1;
reg [15:0] array [0:];
reg [15:0] dout;
reg [19:0] addr;
wire cas_n;
wire idle;
reg was_ras;
reg was_cas;
reg ready;
initial
begin : clear_mem
integer i;
if( _init_ )
begin
for(i=0;i<;i=i+1)
array[i] = 16'hDEAD;
end
end
always @(negedge ras_n)
addr[9:0] <= ma[9:0];
assign cas_n = ucas_n & lcas_n;
always @(negedge cas_n)
begin
addr[19:10] <= ma[9:0];
end
always @(posedge cas_n, negedge cas_n)
ready <= ~cas_n; // to introduce delta-cycle in ready to allow capturing of CAS address before proceeding data
assign idle = ras_n & cas_n;
always @(negedge ras_n, posedge idle)
begin
if( idle )
was_ras <= 1'b0;
else // negedge ras_n
was_ras <= 1'b1;
end
always @(negedge cas_n, posedge idle)
begin
if( idle )
was_cas <= 1'b0;
else
if( was_ras )
was_cas <= 1'b1;
end
assign d = dout;
always @*
begin
if( ready && was_ras && was_cas && we_n && (~idle) ) // idle here is to prevent races at the end of all previous signals, which cause redundant read at the end of write
begin
dout = array[addr];
`ifdef DRAMMEM_VERBOSE
if( _verbose_ == 1 )
begin
if( addr != _filter_out_ )
$display("DRAM read at %t: ($%h)=>$%h",$time,addr*2+_add_to_addr_,dout);
end
`endif
end
else
begin
dout = 16'hZZZZ;
end
end
always @*
if( ready && was_ras && was_cas && (~we_n) && (~idle) )
begin
if( ~ucas_n )
array[addr][15:8] = d[15:8];
if( ~lcas_n )
array[addr][7:0] = d[7:0];
`ifdef DRAMMEM_VERBOSE
if( _verbose_ == 1 )
begin
if( addr != _filter_out_ )
$display("DRAM written at %t: ($%h)<=$%h.$%h",$time,addr*2+_add_to_addr_,ucas_n?8'hXX:d[15:8],lcas_n?8'hXX:d[7:0]);
end
`endif
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32O_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__A32O_BEHAVIORAL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32O_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; vector<int> roda(int f, vector<int> valores) { vector<int> temp(valores); if (f == 0) { temp[17] = valores[5]; temp[18] = valores[6]; temp[21] = valores[17]; temp[22] = valores[18]; temp[13] = valores[21]; temp[14] = valores[22]; temp[5] = valores[13]; temp[6] = valores[14]; } else if (f == 1) { temp[3] = valores[17]; temp[4] = valores[19]; temp[16] = valores[3]; temp[14] = valores[4]; temp[10] = valores[16]; temp[9] = valores[14]; temp[17] = valores[10]; temp[19] = valores[9]; } else if (f == 2) { temp[20] = valores[7]; temp[19] = valores[8]; temp[24] = valores[20]; temp[23] = valores[19]; temp[15] = valores[24]; temp[16] = valores[23]; temp[7] = valores[15]; temp[8] = valores[16]; } else if (f == 3) { temp[1] = valores[24]; temp[3] = valores[22]; temp[5] = valores[1]; temp[7] = valores[3]; temp[9] = valores[5]; temp[11] = valores[7]; temp[24] = valores[9]; temp[22] = valores[11]; } else if (f == 4) { temp[2] = valores[23]; temp[4] = valores[21]; temp[6] = valores[6]; temp[8] = valores[8]; temp[10] = valores[10]; temp[12] = valores[12]; temp[23] = valores[23]; temp[21] = valores[21]; } else if (f == 5) { temp[1] = valores[15]; temp[2] = valores[13]; temp[18] = valores[1]; temp[20] = valores[2]; temp[12] = valores[18]; temp[11] = valores[20]; temp[15] = valores[12]; temp[13] = valores[11]; } return temp; } bool checa(vector<int> valores) { for (int i = 0; i < 6; i++) { int cor = valores[1 + i * 4]; for (int j = 1; j < 4; j++) if (valores[1 + i * 4 + j] != cor) return false; } return true; } int main() { vector<int> valores(25); int i; for (i = 1; i < 25; i++) cin >> valores[i]; int resp = 0; for (i = 0; i < 6; i++) { resp = resp || checa(roda(i, valores)); resp = resp || checa(roda(i, roda(i, roda(i, valores)))); } if (resp) puts( YES ); else puts( NO ); } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( Ofast,no-stack-protector ) using namespace std; function<void(void)> ____ = []() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); }; template <typename T> vector<T> &operator<<(vector<T> &__container, T x) { __container.push_back(x); return __container; } template <typename T> ostream &operator<<(ostream &out, vector<T> &__container) { for (T _ : __container) out << _ << ; return out; } const int MAXN = 1e5 + 7; struct EDGE { int to, cap, rev; EDGE(){}; EDGE(int to, int cap, int rev) : to(to), cap(cap), rev(rev){}; }; vector<EDGE> G[MAXN]; int iter[MAXN], rk[MAXN]; void ADDEDGE(int u, int v, int cap) { G[u].push_back(EDGE(v, cap, (int)G[v].size())); G[v].push_back(EDGE(u, 0, (int)G[u].size() - 1)); } bool bfs() { memset(rk, 0, sizeof(rk)); memset(iter, 0, sizeof(iter)); rk[0] = 1; queue<int> que; que.push(0); while (!que.empty()) { int u = que.front(); que.pop(); for (auto e : G[u]) { if (!e.cap or rk[e.to]) continue; rk[e.to] = rk[u] + 1; que.push(e.to); } } return rk[MAXN - 1] != 0; } int dfs(int u, int flow) { if (u == MAXN - 1) return flow; for (int &i = iter[u]; i < (int)G[u].size(); i++) { auto &e = G[u][i]; if (!e.cap or rk[e.to] != rk[u] + 1) continue; int d = dfs(e.to, min(e.cap, flow)); if (d) { e.cap -= d; G[e.to][e.rev].cap += d; return d; } } return 0; } int Dinic() { int flow = 0; while (bfs()) { int d = dfs(0, 0x3f3f3f3f); while (d) { flow += d; d = dfs(0, 0x3f3f3f3f); } } return flow; } int n, m, idud[222][222], idlr[MAXN][222]; char g[222][222]; void solve() { scanf( %d , &n); scanf( %d , &m); int cur = 1, cnt = 0, tot = 0; for (int i = 1; i <= n; i++) scanf( %s , g[i] + 1); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (g[i][j] == # ) tot++; for (int i = 1; i < n; i++) for (int j = 1; j <= m; j++) idud[i][j] = cur++; for (int i = 1; i <= n; i++) for (int j = 1; j < m; j++) idlr[i][j] = cur++; for (int i = 1; i < n; i++) for (int j = 1; j <= m; j++) if (g[i][j] == # and g[i + 1][j] == # ) ADDEDGE(0, idud[i][j], 1), cnt++; for (int i = 1; i <= n; i++) for (int j = 1; j < m; j++) if (g[i][j] == # and g[i][j + 1] == # ) ADDEDGE(idlr[i][j], MAXN - 1, 1), cnt++; for (int i = 1; i < n; i++) for (int j = 1; j <= m; j++) { if (g[i][j] == # and g[i + 1][j] == # ) { if (g[i][j - 1] == # ) ADDEDGE(idud[i][j], idlr[i][j - 1], 0x3f3f3f3f); if (g[i + 1][j - 1] == # ) ADDEDGE(idud[i][j], idlr[i + 1][j - 1], 0x3f3f3f3f); if (g[i][j + 1] == # ) ADDEDGE(idud[i][j], idlr[i][j], 0x3f3f3f3f); if (g[i + 1][j + 1] == # ) ADDEDGE(idud[i][j], idlr[i + 1][j], 0x3f3f3f3f); } } cout << tot - (cnt - Dinic()) << n ; } int main() { solve(); return 0; } |
//---------------------------------------------------------------------------------------
// uart receive module
//
//---------------------------------------------------------------------------------------
module uart_rx
(
clock, reset,
ce_16, ser_in,
rx_data, new_rx_data
);
//---------------------------------------------------------------------------------------
// modules inputs and outputs
input clock; // global clock input
input reset; // global reset input
input ce_16; // baud rate multiplyed by 16 - generated by baud module
input ser_in; // serial data input
output [7:0] rx_data; // data byte received
output new_rx_data; // signs that a new byte was received
// internal wires
wire ce_1; // clock enable at bit rate
wire ce_1_mid; // clock enable at the middle of each bit - used to sample data
// internal registers
reg [7:0] rx_data;
reg new_rx_data;
reg [1:0] in_sync;
reg rx_busy;
reg [3:0] count16;
reg [3:0] bit_count;
reg [7:0] data_buf;
//---------------------------------------------------------------------------------------
// module implementation
// input async input is sampled twice
always @ (posedge clock or posedge reset)
begin
if (reset)
in_sync <= 2'b11;
else
in_sync <= {in_sync[0], ser_in};
end
// a counter to count 16 pulses of ce_16 to generate the ce_1 and ce_1_mid pulses.
// this counter is used to detect the start bit while the receiver is not receiving and
// signs the sampling cycle during reception.
always @ (posedge clock or posedge reset)
begin
if (reset)
count16 <= 4'b0;
else if (ce_16)
begin
if (rx_busy | (in_sync[1] == 1'b0))
count16 <= count16 + 4'b1;
else
count16 <= 4'b0;
end
end
// ce_1 pulse indicating expected end of current bit
assign ce_1 = (count16 == 4'b1111) & ce_16;
// ce_1_mid pulse indication the sampling clock cycle of the current data bit
assign ce_1_mid = (count16 == 4'b0111) & ce_16;
// receiving busy flag
always @ (posedge clock or posedge reset)
begin
if (reset)
rx_busy <= 1'b0;
else if (~rx_busy & ce_1_mid)
rx_busy <= 1'b1;
else if (rx_busy & (bit_count == 4'h8) & ce_1_mid)
rx_busy <= 1'b0;
end
// bit counter
always @ (posedge clock or posedge reset)
begin
if (reset)
bit_count <= 4'h0;
else if (~rx_busy)
bit_count <= 4'h0;
else if (rx_busy & ce_1_mid)
bit_count <= bit_count + 4'h1;
end
// data buffer shift register
always @ (posedge clock or posedge reset)
begin
if (reset)
data_buf <= 8'h0;
else if (rx_busy & ce_1_mid)
data_buf <= {in_sync[1], data_buf[7:1]};
end
// data output and flag
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
rx_data <= 8'h0;
new_rx_data <= 1'b0;
end
else if (rx_busy & (bit_count == 4'h8) & ce_1)
begin
rx_data <= data_buf;
new_rx_data <= 1'b1;
end
else
new_rx_data <= 1'b0;
end
endmodule
//---------------------------------------------------------------------------------------
// Th.. Th.. Th.. Thats all folks !!!
//---------------------------------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlymetal6s2s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; void _fill_int(int* p, int val, int rep) { int i; for (i = 0; i < rep; i++) p[i] = val; } signed long long GETi() { signed long long i; scanf( %lld , &i); return i; } int N, M; int A[10000], B[10000]; int T[4][10000]; void solve() { int f, i, j, k, l, x, y; cin >> N >> M; for (i = 0; i < N; i++) A[i] = 1 << 29; for (i = 0; i < M; i++) { cin >> T[0][i] >> T[1][i] >> T[2][i] >> T[3][i]; T[1][i]--; T[2][i]--; } for (i = M - 1; i >= 0; i--) { if (T[0][i] == 1) { for (j = T[1][i]; j <= T[2][i]; j++) A[j] -= T[3][i]; } else { for (j = T[1][i]; j <= T[2][i]; j++) A[j] = min(A[j], T[3][i]); } } int ng = 0; memmove(B, A, sizeof(A)); for (i = 0; i < M; i++) { int y = -1 << 29; if (T[0][i] == 1) for (j = T[1][i]; j <= T[2][i]; j++) B[j] += T[3][i]; else { for (j = T[1][i]; j <= T[2][i]; j++) y = max(y, B[j]); if (y != T[3][i]) ng = 1; } } if (ng) (void)printf( NO n ); else { (void)printf( YES n ); for (i = 0; i < N; i++) (void)printf( %d , A[i]); (void)printf( n ); } } int main(int argc, char** argv) { if (argc > 1) freopen(argv[1], r , stdin); solve(); return 0; } |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "TimeHoldOver_Qsys_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 9: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 1024,
the_altsyncram.numwords_a = 1024,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "M9K",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 10;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 510000; int n; int sz[MAXN]; int was[MAXN]; int up[MAXN]; vector<int> eds[MAXN]; int ans[MAXN]; void dfs1(int v) { sz[v] = 1; was[v] = 1; for (int u : eds[v]) { if (!was[u]) { dfs1(u); sz[v] += sz[u]; } } } void dfs2(int v) { was[v] = 1; up[v] = 0; if (sz[v] * 2 <= n) up[v] = sz[v]; for (int u : eds[v]) { if (!was[u]) { dfs2(u); up[v] = max(up[v], up[u]); } } } void dfs3(int v, int now) { ans[v] = 1; was[v] = 1; if ((n - sz[v]) * 2 <= n) now = max(now, n - sz[v]); if ((n - sz[v] - now) * 2 > n) ans[v] = 0; int mx1 = 0; int mx2 = 0; for (int u : eds[v]) { if (!was[u]) { mx2 = max(mx2, up[u]); if (mx2 > mx1) swap(mx1, mx2); } } for (int u : eds[v]) { if (!was[u]) { if ((sz[u] - up[u]) * 2 > n) ans[v] = 0; int go = now; if (up[u] == mx1) go = max(now, mx2); else go = max(now, mx1); dfs3(u, go); } } } int main() { scanf( %d , &n); for (int i = 0; i < n - 1; ++i) { int a, b; scanf( %d%d , &a, &b); --a; --b; eds[a].push_back(b); eds[b].push_back(a); } dfs1(0); memset(was, 0, sizeof(was)); dfs2(0); memset(was, 0, sizeof(was)); dfs3(0, 0); for (int i = 0; i < n; ++i) printf( %d , ans[i]); printf( n ); return 0; } |
module chan_fifo_reader
(reset, tx_clock, tx_strobe, timestamp_clock, samples_format,
fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
input wire reset ;
input wire tx_clock ;
input wire tx_strobe ; //signal to output tx_i and tx_q
input wire [31:0] timestamp_clock ; //current time
input wire [3:0] samples_format ;// not useful at this point
input wire [31:0] fifodata ; //the data input
input wire pkt_waiting ; //signal the next packet is ready
output reg rdreq ; //actually an ack to the current fifodata
output reg skip ; //finish reading current packet
output reg [15:0] tx_q ; //top 16 bit output of fifodata
output reg [15:0] tx_i ; //bottom 16 bit output of fifodata
output reg underrun ;
output reg tx_empty ; //cause 0 to be the output
input wire [31:0] rssi;
input wire [31:0] threshhold;
input wire [31:0] rssi_wait;
output wire [14:0] debug;
assign debug = {7'd0, rdreq, skip, reader_state, pkt_waiting, tx_strobe, tx_clock};
//Samples format
// 16 bits interleaved complex samples
`define QI16 4'b0
// States
parameter IDLE = 3'd0;
parameter HEADER = 3'd1;
parameter TIMESTAMP = 3'd2;
parameter WAIT = 3'd3;
parameter WAITSTROBE = 3'd4;
parameter SEND = 3'd5;
// Header format
`define PAYLOAD 8:2
`define ENDOFBURST 27
`define STARTOFBURST 28
`define RSSI_FLAG 26
/* State registers */
reg [2:0] reader_state;
/* Local registers */
reg [6:0] payload_len;
reg [6:0] read_len;
reg [31:0] timestamp;
reg burst;
reg trash;
reg rssi_flag;
reg [31:0] time_wait;
always @(posedge tx_clock)
begin
if (reset)
begin
reader_state <= IDLE;
rdreq <= 0;
skip <= 0;
underrun <= 0;
burst <= 0;
tx_empty <= 1;
tx_q <= 0;
tx_i <= 0;
trash <= 0;
rssi_flag <= 0;
time_wait <= 0;
end
else
begin
case (reader_state)
IDLE:
begin
/*
* reset all the variables and wait for a tx_strobe
* it is assumed that the ram connected to this fifo_reader
* is a short hand fifo meaning that the header to the next packet
* is already available to this fifo_reader when pkt_waiting is on
*/
skip <=0;
time_wait <= 0;
if (pkt_waiting == 1)
begin
reader_state <= HEADER;
rdreq <= 1;
underrun <= 0;
end
if (burst == 1 && pkt_waiting == 0)
underrun <= 1;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
/* Process header */
HEADER:
begin
if (tx_strobe == 1)
tx_empty <= 1 ;
rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST];
//Check Start/End burst flag
if (fifodata[`STARTOFBURST] == 1
&& fifodata[`ENDOFBURST] == 1)
burst <= 0;
else if (fifodata[`STARTOFBURST] == 1)
burst <= 1;
else if (fifodata[`ENDOFBURST] == 1)
burst <= 0;
if (trash == 1 && fifodata[`STARTOFBURST] == 0)
begin
skip <= 1;
reader_state <= IDLE;
rdreq <= 0;
end
else
begin
payload_len <= fifodata[`PAYLOAD] ;
read_len <= 0;
rdreq <= 1;
reader_state <= TIMESTAMP;
end
end
TIMESTAMP:
begin
timestamp <= fifodata;
reader_state <= WAIT;
if (tx_strobe == 1)
tx_empty <= 1 ;
rdreq <= 0;
end
// Decide if we wait, send or discard samples
WAIT:
begin
if (tx_strobe == 1)
tx_empty <= 1 ;
time_wait <= time_wait + 32'd1;
// Outdated
if ((timestamp < timestamp_clock) ||
(time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
begin
trash <= 1;
reader_state <= IDLE;
skip <= 1;
end
// Let's send it
else if (timestamp == timestamp_clock
|| timestamp == 32'hFFFFFFFF)
begin
if (rssi <= threshhold || rssi_flag == 0)
begin
trash <= 0;
reader_state <= WAITSTROBE;
end
else
reader_state <= WAIT;
end
else
reader_state <= WAIT;
end
// Wait for the transmit chain to be ready
WAITSTROBE:
begin
// If end of payload...
if (read_len == payload_len)
begin
reader_state <= IDLE;
skip <= 1;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
else if (tx_strobe == 1)
begin
reader_state <= SEND;
rdreq <= 1;
end
end
// Send the samples to the tx_chain
SEND:
begin
reader_state <= WAITSTROBE;
read_len <= read_len + 7'd1;
tx_empty <= 0;
rdreq <= 0;
case(samples_format)
`QI16:
begin
tx_i <= fifodata[15:0];
tx_q <= fifodata[31:16];
end
// Assume 16 bits complex samples by default
default:
begin
tx_i <= fifodata[15:0];
tx_q <= fifodata[31:16];
end
endcase
end
default:
begin
//error handling
reader_state <= IDLE;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int A[100], L[100], n, m; cin >> n >> m; for (int i = 0; i < n; ++i) cin >> A[i], A[i]--; for (int i = 0; i < m; ++i) cin >> L[i]; for (int i = 0; i < n; ++i) { for (int j = i + 1; j <= n; ++j) { vector<int> cnt(m + 1, 0); for (int k = i; k < j; ++k) cnt[A[k]]++; bool fl = true; for (int k = 0; k < m; ++k) fl &= (L[k] == cnt[k]); if (fl) { cout << YES n ; return 0; } } } cout << NO n ; } |
#include <bits/stdc++.h> const int MAXN = 1e6 + 5; std::vector<int> G[MAXN]; int f[MAXN][26]; void dfs(int v) { for (register int i = 1; i <= 20; ++i) { f[v][i] = f[f[v][i - 1]][i - 1]; } for (auto x : G[v]) { if (x == f[v][0]) continue; f[x][0] = v; dfs(x); } } int n, k; bool vis[MAXN]; int main() { scanf( %d%d , &n, &k); for (register int i = 1; i <= n - 1; ++i) { int u, v; scanf( %d%d , &u, &v); G[u].push_back(v); G[v].push_back(u); } int res = n - k; f[n][0] = n; dfs(n); vis[n] = true; res--; for (register int i = n - 1; i >= 1; --i) { if (vis[i]) continue; int len = 1, v = i; for (register int j = 20; j >= 0; --j) { if (vis[f[v][j]]) continue; v = f[v][j]; len += (1 << j); } if (len <= res) { res -= len; int x = i; while (true) { if (vis[x]) break; vis[x] = 1; x = f[x][0]; } } } for (register int i = 1; i <= n; ++i) if (!vis[i]) printf( %d , i); puts( ); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; using i64 = long long; using i32 = int; using f64 = long double; template <class Key> using vec = vector<Key>; template <class Key> using heap = priority_queue<Key>; template <class Key> using hash_set = unordered_set<Key>; template <class Key, class Value> using hash_map = unordered_map<Key, Value>; using str = string; template <size_t Size1> using a64 = array<i64, Size1>; template <size_t Size1, size_t Size2> using aa64 = array<a64<Size2>, Size1>; template <size_t Size1, size_t Size2, size_t Size3> using aaa64 = array<aa64<Size2, Size3>, Size1>; using p64 = pair<i64, i64>; using v64 = vec<i64>; using vv64 = vec<v64>; using s64 = set<i64>; using m64 = map<i64, i64>; mt19937 gen(998244353); const i64 inf = numeric_limits<i64>::max() / 2; template <typename T> inline i64 sz(const T& a) { return (i64)(a.size()); } inline void fast() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); } template <typename T> inline bool check_min(T& a, T b) { if (a > b) return a = b, 1; return 0; } template <typename T> inline bool check_max(T& a, T b) { if (a < b) return a = b, 1; return 0; } struct Problem { Problem(bool multitest = 0) { read(); if (!multitest) solve(); } void solve(), read(); }; signed main() { fast(); Problem(); return 0; } i64 n, m; v64 a, b; vv64 c; i64 dist(i64 from, i64 to) { return (to - from + n) % n; } void Problem::solve() { c.resize(n); for (i64 i = 0; i < m; i++) { c[a[i]].push_back(dist(a[i], b[i])); } for (i64 i = 0; i < sz(c); i++) { sort((c[i]).begin(), (c[i]).end()); } for (i64 i = 0; i < n; i++) { i64 ans = 0; for (i64 j = 0; j < n; j++) { if (c[j].empty()) continue; i64 cur = dist(i, j) + (sz(c[j]) - 1) * n + c[j][0]; check_max(ans, cur); } cout << ans << ; } } void Problem::read() { cin >> n >> m; a.resize(m), b.resize(m); for (i64 i = 0; i < m; i++) { cin >> a[i] >> b[i]; --a[i], --b[i]; } } |
#include <bits/stdc++.h> using namespace std; const int INF = (int)1e9 + 34; const int N = (int)1e6 + 34; int p[N], sz[N]; int fnd(int v) { return (p[v] == v ? v : fnd(p[v])); } void uniq(int v1, int v2) { v1 = fnd(v1); v2 = fnd(v2); if (v1 == v2) return; p[v1] = v2; sz[v2] += sz[v1]; } int a[N]; void solve() { int n; cin >> n; map<int, vector<int>> mp; for (int i = 0; i < n; i++) { cin >> a[i]; p[i] = i; sz[i] = 1; mp[a[i]].push_back(i); } int tot = 0, lst = -1; int ansL = 1; int ansK = mp.rbegin()->first; map<int, int> num; for (auto it = mp.begin(); it != mp.end(); it++) { auto v = it->second; for (int ps : v) { tot++; num[1]++; lst = 1; if (ps > 0 && a[ps] >= a[ps - 1]) { int v1 = fnd(ps); int v2 = fnd(ps - 1); if (v1 != v2) { tot--; num[sz[v1]]--; num[sz[v2]]--; uniq(v1, v2); lst = sz[fnd(ps)]; num[lst]++; } } if (ps + 1 < n && a[ps] >= a[ps + 1]) { int v1 = fnd(ps); int v2 = fnd(ps + 1); if (v1 != v2) { tot--; num[sz[v1]]--; num[sz[v2]]--; uniq(v1, v2); lst = sz[fnd(ps)]; num[lst]++; } } } if (tot == num[lst]) { int curK = it->first; int curL = num[lst]; if (curL > ansL || (curL == ansL && curK < ansK)) { ansL = curL; ansK = curK; } } } cout << ansK + 1 << n ; } int main() { solve(); return 0; } |
//-----------------------------------------------------
// Design Name : hw3_t
// File Name : hw3_t.v
// Function : This program will test datapath.v
// Coder : hydai
//-----------------------------------------------------
`timescale 1 ns/1 ps
`define TESTSIZE 44
`define STRINGIFY(x) `"x`"
`define PATTERN pattern1.dat
`define GOLDEN golden1.dat
`define SNAPSHOT dump1.dat
`define CLOCK_CYCLE 10
`define HALF_CYCLE 5
module hw3_t ;
reg [57:0] test_vector [`TESTSIZE-1:0];
reg [291:0] test_response [`TESTSIZE-1:0];
reg [25:0] control;
reg [15:0] constant;
reg [15:0] data;
reg clk, rst_n;
reg V, C, N, Z;
wire [15:0] R0;
wire [15:0] R1;
wire [15:0] R2;
wire [15:0] R3;
wire [15:0] R4;
wire [15:0] R5;
wire [15:0] R6;
wire [15:0] R7;
wire [15:0] R8;
wire [15:0] R9;
wire [15:0] R10;
wire [15:0] R11;
wire [15:0] R12;
wire [15:0] R13;
wire [15:0] R14;
wire [15:0] R15;
wire [15:0] BUSA;
wire [15:0] BUSB;
reg [291:0] snapshot;
integer error, snapshotPT, descPT, i;
reg cmp;
datapath golden(
V, C, N, Z,
R0, R1, R2, R3, R4, R5, R6, R7,
R8, R9, R10, R11, R12, R13, R14, R15,
BUSA, BUSB,
control,
constant,
data,
clk,
rst_n
);
initial begin
`ifdef NETLIST
$sdf_annotate("datapath_syn.sdf", golden);
$fsdbDumpfile("datapath_syn.fsdb");
`else
$fsdbDumpfile("datapath.fsdb");
`endif
$fsdbDumpvars;
end
always begin
#`CLOCK_CYCLE clk = ~clk;
end
task simulation;
input [57:0] instr;
begin
#(`HALF_CYCLE) assign {control, constant, data} = instr;
#(`HALF_CYCLE)
#(`CLOCK_CYCLE)
$display("");
end
endtask
initial begin
$fsdbDumpfile("hw3_t.fsdb");
$fsdbDumpvars;
end
initial begin
#0 clk = 0; rst_n = 0; constant = 0; control = 0; data = 0;
#20 rst_n = 1;
$readmemb(`STRINGIFY(`PATTERN), test_vector);
$readmemb(`STRINGIFY(`GOLDEN), test_response);
snapshotPT = $fopen(`STRINGIFY(`SNAPSHOT));
$display("File dump handle in %h", snapshotPT);
error = 0;
for (i = 0; i < `TESTSIZE; i++) begin
simulation(test_vector[i]);
descPT = snapshotPT;
assign snapshot = {V, C, N, Z, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, BUSA, BUSB};
$fdisplay(descPT, "%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b", V, C, N, Z, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, BUSA, BUSB);
cmp = (snapshot == test_response[i])?1:0;
if (cmp == 0) begin
$display("Error in line %d", i);
error++;
end
end
#10
if (error == 0) begin
$display("PASS");
end else begin
$display("NOT PASS");
end
$fclose(snapshotPT);
$finish;
end
endmodule // End of Module hw3_t
|
#include <bits/stdc++.h> using namespace std; int n, w, m; double a[100]; int kol[100]; vector<pair<int, double> > v[100]; int main() { cin >> n >> w >> m; double q = n * w * 1.0 / m; memset(kol, 0, sizeof(kol)); for (int i = 0; i < 100; ++i) a[i] = w; for (int i = 0; i < m; ++i) { double p = q; int z = 0; for (int j = 0; j < n; ++j) { if (a[j] > 1e-9) { double temp = min(p, a[j]); v[i].push_back(make_pair(j + 1, temp)); p -= temp; a[j] -= temp; ++z; ++kol[j]; if (kol[j] > 2) { cout << NO n ; return 0; } if (p < 1e-9) break; } } if (z == 0 || p > 1e-9) { cout << NO n ; return 0; } } cout << YES n ; for (int i = 0; i < m; ++i) { for (int j = 0; j < v[i].size(); ++j) { if (j) cout << ; cout << v[i][j].first << << fixed << setprecision(10) << v[i][j].second; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int x, y; cin >> x >> y; if (y == 0) { cout << No << endl; return 0; } y = y - 1; if (y >= 1) { x = x - y; if (x >= 0 && x % 2 == 0) { cout << Yes << endl; } else { cout << No << endl; } } else { if (x == 0) { cout << Yes << endl; } else cout << No << endl; } return 0; } |
////////////////////////////////////////////////////////////////////////////////
//
// Filename: speechfifo.v
// {{{
// Project: wbuart32, a full featured UART with simulator
//
// Purpose: To test/demonstrate/prove the wishbone access to the FIFO'd
// UART via sending more information than the FIFO can hold,
// and then verifying that this was the value received.
//
// To do this, we "borrow" a copy of Abraham Lincolns Gettysburg address,
// make that the FIFO isn't large enough to hold it, and then try
// to send this address every couple of minutes.
//
// With some minor modifications (discussed below), this RTL should be
// able to be run as a top-level testing file, requiring only that the
// clock and the transmit UART pins be working.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2015-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
// One issue with the design is how to set the values of the setup register.
// (*This is a comment, not a verilator attribute ... ) Verilator needs to
// know/set those values in order to work. However, this design can also be
// used as a stand-alone top level configuration file. In this latter case,
// the setup register needs to be set internal to the file. Here, we use
// OPT_STANDALONE to distinguish between the two. If set, the file runs under
// (* Another comment still ...) Verilator and we need to get i_setup from the
// external environment. If not, it must be set internally.
//
`ifndef VERILATOR
`define OPT_STANDALONE
`endif
// }}}
module speechfifo #(
// {{{
// Here we set i_setup to something appropriate to create a
// 115200 Baud UART system from a 100MHz clock. This also sets
// us to an 8-bit data word, 1-stop bit, and no parity (for the
// non-LITE UART). This will be overwritten by i_setup (if
// present), but at least it gives us something to start
// with/from.
parameter INITIAL_UART_SETUP = 31'd868,
// Let's set our message length, in case we ever wish to change
// it in the future
localparam MSGLEN=2203
// }}}
) (
// {{{
input wire i_clk,
`ifndef OPT_STANDALONE
input wire [30:0] i_setup,
`endif
output wire o_uart_tx
// }}}
);
// Signal declarations
// {{{
reg restart;
reg wb_stb;
reg [1:0] wb_addr;
reg [31:0] wb_data;
wire uart_stall;
// We aren't using the receive interrupts, or the received data, or the
// ready to send line, so we'll just mark them all here as ignored.
/* verilator lint_off UNUSED */
wire uart_ack, tx_int;
wire [31:0] uart_data;
wire ignored_rx_int, ignored_rxfifo_int;
wire rts_n_ignored;
/* verilator lint_on UNUSED */
reg pwr_reset;
reg [7:0] message [0:4095];
reg [30:0] restart_counter;
reg [11:0] msg_index;
reg end_of_message;
wire cts_n;
wire txfifo_int;
// }}}
// i_setup
// {{{
// The i_setup wires are input when run under Verilator, but need to
// be set internally if this is going to run as a standalone top level
// test configuration.
`ifdef OPT_STANDALONE
wire [30:0] i_setup;
assign i_setup = INITIAL_UART_SETUP;
`endif
// }}}
// pwr_reset
// {{{
// The next four lines create a strobe signal that is true on the first
// clock, but never after. This makes for a decent power-on reset
// signal.
initial pwr_reset = 1'b1;
always @(posedge i_clk)
pwr_reset <= 1'b0;
// }}}
// initializing the memory
// {{{
// The message we wish to transmit is kept in "message". It needs to be
// set initially. Do so here.
//
// Since the message has fewer than 2048 elements in it, we preset every
// element to a space so that if (for some reason) we broadcast past the
// end of our message, we'll at least be sending something useful.
integer i;
initial begin
// xx Verilator needs this file to be in the directory the file
// is run from. For that reason, the project builds, makes,
// and keeps speech.hex in bench/cpp.
//
// Vivado, however, wants speech.hex to be in a project file
// directory, such as bench/verilog. For that reason, the
// build function in bench/cpp also copies speech.hex to the
// bench/verilog directory. You may need to make certain the
// file is both built, and copied into a directory where your
// synthesis tool can find it.
//
$readmemh("speech.hex", message);
for(i=MSGLEN; i<4095; i=i+1)
message[i] = 8'h20;
//
// The problem with the above approach is Xilinx's ISE program.
// It's broken. It can't handle HEX files well (at all?) and
// has more problems with HEX's defining ROM's. For that
// reason, the mkspeech program can be tuned to create an
// include file, speech.inc. We include that program here.
// It is rather ugly, though, and not a very elegant solution,
// since it walks through every value in our speech, byte by
// byte, with an initial line for each byte declaring what it
// is to be.
//
// If you (need to) use this route, comment out both the
// readmemh, the for loop, and the message[i] = 8'h20 lines
// above and uncomment the include line below.
//
// `include "speech.inc"
end
// }}}
// restart_counter
// {{{
// Let's keep track of time, and send our message over and over again.
// To do this, we'll keep track of a restart counter. When this counter
// rolls over, we restart our message.
//
// Since we want to start our message just a couple clocks after power
// up, we'll set the reset counter just a couple clocks shy of a roll
// over.
initial restart_counter = -31'd16;
always @(posedge i_clk)
restart_counter <= restart_counter+1'b1;
// }}}
// restart
// {{{
// Ok, now that we have a counter that tells us when to start over,
// let's build a set of signals that we can use to get things started
// again. This will be the restart signal. On this signal, we just
// restart everything.
initial restart = 0;
always @(posedge i_clk)
restart <= (restart_counter == 0);
// }}}
// msg_index
// {{{
// Our message index. This is the address of the character we wish to
// transmit next. Note, there's a clock delay between setting this
// index and when the wb_data is valid. Hence, we set the index on
// restart[0] to zero.
initial msg_index = 12'h000 - 12'h8;
always @(posedge i_clk)
if (restart)
msg_index <= 0;
else if ((wb_stb)&&(!uart_stall))
// We only advance the index if a port operation on the
// wbuart has taken place. That's what the
// (wb_stb)&&(!uart_stall) is about. (wb_stb) is the
// request for a transaction on the bus, uart_stall
// tells us to wait 'cause the peripheral isn't ready.
// In our case, it's always ready, uart_stall == 0, but
// we keep/maintain this logic for good form.
//
// Note also, we only advance when restart[0] is zero.
// This keeps us from advancing prior to the setup
// word.
msg_index <= msg_index + 1'b1;
// }}}
// wb_data -- What data will we be sending to the port?
// {{{
always @(posedge i_clk)
if (restart)
// The first thing we do is set the baud rate, and
// serial port configuration parameters. Ideally,
// we'd only set this once. But rather than complicate
// the logic, we set it everytime we start over.
wb_data <= { 1'b0, i_setup };
else if ((wb_stb)&&(!uart_stall))
// Then, if the last thing was received over the bus,
// we move to the next data item.
wb_data <= { 24'h00, message[msg_index] };
// }}}
// wb_addr
// {{{
// We send our first value to the SETUP address (all zeros), all other
// values we send to the transmitters address. We should really be
// double checking that stall remains low, but its not required here.
always @(posedge i_clk)
if (restart)
wb_addr <= 2'b00;
else // if (!uart_stall)??
wb_addr <= 2'b11;
// }}}
// end_of_message
// {{{
// Knowing when to stop sending the speech is important, but depends
// upon an 11 bit comparison. Since FPGA logic is best measured by the
// number of inputs to an always block, we pull those 11-bits out of
// the always block for wb_stb, and place them here on the clock prior.
// If end_of_message is true, then we need to stop transmitting, and
// wait for the next (restart) to get us started again. We set that
// flag hee.
initial end_of_message = 1'b1;
always @(posedge i_clk)
if (restart)
end_of_message <= 1'b0;
else
end_of_message <= (msg_index >= MSGLEN);
// }}}
// wb_stb
// {{{
// The wb_stb signal indicates that we wish to write, using the wishbone
// to our peripheral. We have two separate types of writes. First,
// we wish to write our setup. Then we want to drop STB and write
// our data. Once we've filled half of the FIFO, we wait for the FIFO
// to empty before issuing a STB again and then fill up half the FIFO
// again.
initial wb_stb = 1'b0;
always @(posedge i_clk)
if (restart)
// Start sending to the UART on a reset. The first
// thing we'll send will be the configuration, but
// that's done elsewhere. This just starts up the
// writes to the peripheral wbuart.
wb_stb <= 1'b1;
else if (end_of_message)
// Stop transmitting when we get to the end of our
// message.
wb_stb <= 1'b0;
else if (txfifo_int)
// If the FIFO is less than half full, then write to
// it.
wb_stb <= 1'b1;
else
// But once the FIFO gets to half full, stop.
wb_stb <= 1'b0;
// }}}
// cts_n
// {{{
// The WBUART can handle hardware flow control signals. This test,
// however, cannot. The reason? Simply just to keep things simple.
// If you want to add hardware flow control to your design, simply
// make rts an input to this module.
//
// Since this is an output only module demonstrator, what would be the
// cts output is unused.
assign cts_n = 1'b0;
// }}}
// Finally--the unit under test--now that we've set up all the wires
// to run/test it.
wbuart #(INITIAL_UART_SETUP)
wbuarti(i_clk, pwr_reset,
wb_stb, wb_stb, 1'b1, wb_addr, wb_data, 4'hf,
uart_stall, uart_ack, uart_data,
1'b1, o_uart_tx, cts_n, rts_n_ignored,
ignored_rx_int, tx_int,
ignored_rxfifo_int, txfifo_int);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const long long int MOD1 = 1e9 + 7; const long long int MAX5 = 1e5; const long long int MAX6 = 1e6; const long long int MAX7 = 1e7; const long long int MAX8 = 1e8; const long long int MAX9 = 1e9; const long long int MAX10 = 1e10; const long long int MAXX = 1e18; long long int pow(long long int x, long long int y) { long long int res = 1; while (y > 0) { res = res * x; x = x * x; y >>= 1; } return res; } long long int gcd(int a, int b) { if (a < b) swap(a, b); if (b == 0) return a; return gcd(a % b, b); } void solve() { int n, q; cin >> n >> q; set<int> p; for (int ii = 0; ii < n; ii++) { int aa; cin >> aa; p.insert(aa); } auto it = p.begin(); multiset<int> m; m.insert(0); for (int ii = 0; ii < p.size() - 1; ii++) { int x = *it; it++; m.insert(x - *it); } cout << *p.rbegin() - *p.begin() + *m.begin(); cout << n ; ; for (int ii = 0; ii < q; ii++) { int t, x; cin >> t >> x; int y, z; bool Y = false, Z = false; if (t == 0) { it = p.find(x); if (it != p.begin()) { it--; y = *it; Y = true; m.erase(m.find(y - x)); } it = p.find(x); if (it != (--p.end())) { it++; z = *it; Z = true; m.erase(m.find(x - z)); } if (Y && Z) m.insert(y - z); p.erase(x); } if (t == 1) { p.insert(x); it = p.find(x); if (it != p.begin()) { it--; y = *it; Y = true; m.insert(y - x); } it = p.find(x); if (it != (--p.end())) { it++; z = *it; Z = true; m.insert(x - z); } if (Y && Z) m.erase(m.find(y - z)); } if (!p.empty()) cout << *p.rbegin() - *p.begin() + *m.begin(); else cout << 0; cout << n ; ; } } int main() { { solve(); } } |
#include <bits/stdc++.h> int main() { int n, i, j, temp; scanf( %d , &n); char s[n]; scanf( %s , &s); for (i = 0; i < n; i++) { if (s[i] > s[i + 1] && i + 1 < n) { printf( YES n ); printf( %d %d , i + 1, i + 2); return 0; } } printf( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( O3 ) #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* na, Arg1&& arg1, Args&&... args) { const char* c = strchr(na + 1, , ); cerr.write(na, c - na) << : << arg1 << , ; __f(c + 1, args...); } const double pi = acos(-1.0); const double eps = 1e-8; const int inf = 1e9; const long long INF = 1e18; const int mod = 1e9 + 7; const int N = 3e5 + 5; void solve() { int len, q; cin >> len >> q; string s; cin >> s; s = # + s; int ans = 0; for (int i = 1; i <= len;) { if (s[i] == . ) { int j = i; while (j <= len && s[j] == . ) j++; ans += (j - i - 1); i = j; } else { i++; } } while (q--) { int pos; string ch; cin >> pos >> ch; if (s[pos] != . && ch[0] == . ) { if (pos - 1 >= 1 && s[pos - 1] == . ) ans++; if (pos + 1 <= len && s[pos + 1] == . ) ans++; s[pos] = . ; } else if (s[pos] == . && ch[0] != . ) { if (pos - 1 >= 1 && s[pos - 1] == . ) ans--; if (pos + 1 <= len && s[pos + 1] == . ) ans--; s[pos] = ch[0]; } cout << ans << n ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t = 1; for (int tc = 1; tc <= t; tc++) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fll; template <typename T, bool MULTI = false, typename SIZE_T = int> struct sms_mo { static_assert(std::is_integral<T>::value, Not an integral type ); static_assert(std::is_integral<SIZE_T>::value, Not an integral type ); struct node { node* ch[2]; SIZE_T cnt; char d; T v, mi; node(int d_, T v_, SIZE_T cnt_) : cnt(cnt_), d(d_), v(v_), mi(v) { ch[0] = ch[1] = NULL; } node(node* x, bool b = true) : cnt(x->cnt), d(x->d), v(x->v), mi(x->mi) { if (b) ch[0] = x->ch[0], ch[1] = x->ch[1]; else ch[0] = ch[1] = NULL; } void update() { if (!ch[0] ^ !ch[1]) { for (int i = 0; i < 2; i++) if (ch[i]) { node* tmp = ch[i]; ch[0] = tmp->ch[0], ch[1] = tmp->ch[1]; d = tmp->d, v = tmp->v; cnt = tmp->cnt, mi = tmp->mi; delete tmp; return; } } cnt = 0; mi = std::numeric_limits<T>::max(); for (int i = 0; i < 2; i++) if (ch[i]) { cnt += ch[i]->cnt; mi = std::min(mi, ch[i]->mi); } } }; node* root; T N; char n; sms_mo() : root(NULL), N(0), n(0) {} sms_mo(T v) : sms_mo() { while (v >> n) n++, N = 2 * N + 1; } sms_mo(const sms_mo& t) : root(NULL), N(t.N), n(t.n) { if (!t.root) return; root = new node(t.root, false); std::vector<std::pair<node*, node*>> q = {{root, t.root}}; while (q.size()) { auto [x, y] = q.back(); q.pop_back(); for (int i = 0; i < 2; i++) if (y->ch[i]) { x->ch[i] = new node(y->ch[i], false); q.emplace_back(x->ch[i], y->ch[i]); } } } sms_mo(std::initializer_list<T> v) : sms_mo() { for (T i : v) insert(i); } ~sms_mo() { std::vector<node*> q = {root}; while (q.size()) { node* x = q.back(); q.pop_back(); if (!x) continue; q.push_back(x->ch[0]), q.push_back(x->ch[1]); delete x; } } friend void swap(sms_mo& a, sms_mo& b) { std::swap(a.root, b.root), std::swap(a.N, b.N), std::swap(a.n, b.n); } sms_mo& operator=(const sms_mo& v) { sms_mo tmp = v; swap(tmp, *this); return *this; } SIZE_T size() const { return root ? root->cnt : 0; } SIZE_T count(node* x) const { return x ? x->cnt : 0; } void clear() { sms_mo tmp; swap(*this, tmp); } void expand(T v) { while (v >> n) n++, N = 2 * N + 1; } char msb(T v, char l, char r) { for (char i = r; i > l; i--) if (v >> i & 1) return i; return -1; } void cut(node* at, T v, char i, node* prev = NULL) { char d = msb(v ^ at->v, prev ? std::max(at->d, prev->d) : at->d, i); if (d == -1) { if (!prev or prev->d <= at->d) return; d = prev->d, v = ~at->v; } node* nxt = new node(at); at->ch[v >> d & 1] = NULL; at->ch[!(v >> d & 1)] = nxt; at->d = d; } node* insert(node* at, T v, SIZE_T qt, char i) { if (!at) return new node(-1, v, qt); cut(at, v, i); if (at->d == -1) { at->cnt += qt; at->mi = v; if (!MULTI) at->cnt = 1; return at; } bool dir = v >> at->d & 1; at->ch[dir] = insert(at->ch[dir], v, qt, at->d - 1); at->update(); return at; } void insert(T v, SIZE_T qt = 1) { if (qt <= 0) return erase(v, -qt); expand(v); root = insert(root, v, qt, n - 1); } node* erase(node* at, T v, SIZE_T qt, char i) { if (!at) return at; if (at->d == -1) at->cnt = at->cnt < qt ? 0 : at->cnt - qt; else { bool dir = v >> at->d & 1; at->ch[dir] = erase(at->ch[dir], v, qt, i - 1); at->update(); } if (!at->cnt) delete at, at = NULL; return at; } void erase(T v, SIZE_T qt = 1) { if (v < 0 or v > N or !qt) return; if (qt < 0) insert(v, -qt); if (!count(v)) return; root = erase(root, v, qt, n - 1); } void erase_all(T v) { if (v < 0 or v > N or !count(v)) return; root = erase(root, v, std::numeric_limits<SIZE_T>::max(), n - 1); } SIZE_T count(node* at, T a, T b, T l, T r, char i) const { if (!at or b < l or r < a) return 0; if (a <= l and r <= b) return at->cnt; T m = l + (r - l) / 2; if (at->d < i) { if ((at->v >> i & 1) == 0) return count(at, a, b, l, m, i - 1); else return count(at, a, b, m + 1, r, i - 1); } return count(at->ch[0], a, b, l, m, i - 1) + count(at->ch[1], a, b, m + 1, r, i - 1); } SIZE_T count(T v) const { return count(root, v, v, 0, N, n - 1); } SIZE_T order_of_key(T v) { return count(root, 0, v - 1, 0, N, n - 1); } SIZE_T lower_bound(T v) { return order_of_key(v); } const T operator[](SIZE_T k) const { node* at = root; T l = 0, r = N; char i = n - 1; while (l < r) { T m = l + (r - l) / 2; if (at->d < i) { if ((at->v >> i & 1) == 0) r = m; else l = m + 1; i--; continue; } if (count(at->ch[0]) > k) at = at->ch[0], r = m; else { k -= count(at->ch[0]); at = at->ch[1]; l = m + 1; } i--; } return l; } node* merge(node* l, node* r, char i) { if (!l or !r) return l ? l : r; cut(l, r->v, i, r), cut(r, l->v, i, l); if (l->d == -1) { if (MULTI) l->cnt += r->cnt; delete r; return l; } for (int j = 0; j < 2; j++) l->ch[j] = merge(l->ch[j], r->ch[j], l->d - 1); l->update(), delete r; return l; } void merge(sms_mo& s) { if (N > s.N) swap(*this, s); expand(s.N); root = merge(root, s.root, n - 1); s.root = NULL; } node* split(node*& x, SIZE_T k) { if (k <= 0 or !x) return NULL; node* ret = new node(x); ret->ch[0] = ret->ch[1] = NULL; ret->cnt = 0; if (x->d == -1) x->cnt -= k, ret->cnt += k, ret->mi = x->mi; else { if (k <= count(x->ch[0])) ret->ch[0] = split(x->ch[0], k); else { ret->ch[1] = split(x->ch[1], k - count(x->ch[0])); std::swap(x->ch[0], ret->ch[0]); } ret->update(), x->update(); } if (!x->cnt) delete x, x = NULL; return ret; } void split(SIZE_T k, sms_mo& s) { s.clear(); s.root = split(root, std::min(k, size())); s.N = N, s.n = n; } void split_val(T k, sms_mo& s) { split(order_of_key(k), s); } T min() { return root->mi; }; }; std::mt19937 dyn_array_rng( (int)std::chrono::steady_clock::now().time_since_epoch().count()); template <typename T, typename SIZE_T = int, typename SET = sms_mo<T, true, SIZE_T>> struct dyn_array { static_assert(std::is_integral<T>::value, Not an integral type ); static_assert(std::is_integral<SIZE_T>::value, Not an integral type ); struct node { node *l, *r; int p; SIZE_T sz; bool rev, rev_lazy; SET val; T mi; node(SET& v) : l(NULL), r(NULL), p(dyn_array_rng()), sz(1), rev(0), rev_lazy(0) { swap(val, v); mi = val.min(); } node(node* x) : l(NULL), r(NULL), p(x->p), sz(x->sz), rev(x->rev), rev_lazy(x->rev_lazy), val(x->val), mi(x->mi) {} void prop() { if (rev_lazy) { rev ^= 1; std::swap(l, r); if (l) l->rev_lazy ^= 1; if (r) r->rev_lazy ^= 1; } rev_lazy = false; } void update() { sz = val.size(); mi = val.min(); if (l) sz += l->sz, mi = std::min(mi, l->mi); if (r) sz += r->sz, mi = std::min(mi, r->mi); } }; node* root; dyn_array() { root = NULL; } dyn_array(const dyn_array& v) : root(NULL) { if (!v.root) return; root = new node(v.root); std::vector<std::pair<node*, node*>> q = {{root, v.root}}; while (q.size()) { auto [x, y] = q.back(); q.pop_back(); if (y->l) { x->l = new node(y->l); q.emplace_back(x->l, y->l); } if (y->r) { x->r = new node(y->r); q.emplace_back(x->r, y->r); } } } dyn_array(std::initializer_list<T> v) : dyn_array() { for (T i : v) push_back(i); } ~dyn_array() { std::vector<node*> q = {root}; while (q.size()) { node* x = q.back(); q.pop_back(); if (!x) continue; q.push_back(x->l), q.push_back(x->r); delete x; } } friend void swap(dyn_array& a, dyn_array& b) { std::swap(a.root, b.root); } dyn_array& operator=(const dyn_array& v) { dyn_array tmp = v; swap(tmp, *this); return *this; } void clear() { dyn_array tmp; swap(tmp, *this); } SIZE_T size(node* x) const { return x ? x->sz : 0; } SIZE_T size() const { return size(root); } void join(node* l, node* r, node*& i) { if (!l or !r) return void(i = l ? l : r); l->prop(), r->prop(); if (l->p > r->p) join(l->r, r, l->r), i = l; else join(l, r->l, r->l), i = r; i->update(); } void concat(dyn_array& v) { join(root, v.root, root); v.root = NULL; } void split(node* i, node*& l, node*& r, SIZE_T idx) { if (!i) return void(r = l = NULL); i->prop(); if (size(i->l) + i->val.size() <= idx) { split(i->r, i->r, r, idx - size(i->l) - i->val.size()); l = i; } else if (size(i->l) >= idx) { split(i->l, l, i->l, idx); r = i; } else { SET L; if (!i->rev) i->val.split(idx - size(i->l), L); else { i->val.split(i->val.size() - (idx - size(i->l)), L); swap(L, i->val); } node* novo = new node(L); novo->rev = i->rev; novo->l = i->l; i->l = NULL; novo->update(); l = novo, r = i; } i->update(); } void split(SIZE_T k, dyn_array& v) { v.clear(); split(root, v.root, root, std::min(k, size())); } void push_back(T val, SIZE_T qt = 1) { SET v; v.insert(val, qt); node* i = new node(v); join(root, i, root); } T get(node* i, SIZE_T idx) const { i->prop(); if (size(i->l) + i->val.size() <= idx) return get(i->r, idx - size(i->l) - i->val.size()); if (size(i->l) > idx) return get(i->l, idx); if (!i->rev) return i->val[idx - size(i->l)]; return i->val[i->val.size() - 1 - (idx - size(i->l))]; } const T operator[](SIZE_T i) const { return get(root, i); } void update(SIZE_T idx, T val) { dyn_array L, M; split(idx + 1, M); M.split(idx, L); L.push_back(val); L.concat(*this); swap(*this, L); } void merge(node*& i, SET& v) { if (!i) return; i->prop(); merge(i->l, v), merge(i->r, v); v.merge(i->val); delete i; i = NULL; } void sort(bool reverse = false) { if (!root) return; root->prop(); merge(root->l, root->val); merge(root->r, root->val); root->rev = reverse; root->update(); } void sort(SIZE_T l, SIZE_T r, bool reverse = false) { dyn_array L, M; split(r + 1, M); M.split(l, L); M.sort(reverse); L.concat(M); L.concat(*this); swap(*this, L); } void reverse() { if (root) root->rev_lazy ^= 1; } void reverse(SIZE_T l, SIZE_T r) { dyn_array L, M; split(r + 1, M); M.split(l, L); M.reverse(); L.concat(M); L.concat(*this); swap(*this, L); } T min() { return root->mi; } T rmq(SIZE_T l, SIZE_T r) { dyn_array L, M; split(r + 1, M); M.split(l, L); T ans = M.min(); L.concat(M); L.concat(*this); swap(*this, L); return ans; } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, q; cin >> n >> q; map<int, int> ida, volta; vector<int> w(n); for (int& i : w) cin >> i; auto w2 = w; sort(w2.begin(), w2.end()); for (int i = 0; i < n; i++) ida[w2[i]] = i, volta[i] = w2[i]; dyn_array<int> v; for (int i = 0; i < n; i++) v.push_back(ida[w[i]]); while (q--) { int t, r; cin >> t >> r; r--; v.sort(0, r, t - 1); } for (int i = 0; i < n; i++) cout << volta[v[i]] << ; cout << n ; exit(0); } |
#include <bits/stdc++.h> using namespace std; map<pair<int, int>, int> cntmp; int n; struct Point { int x, y; } pt[200005]; bool cpx(const Point &a, const Point &b) { if (a.x != b.x) { return a.x < b.x; } return a.y < b.y; } bool cpy(const Point &a, const Point &b) { if (a.y != b.y) { return a.y < b.y; } return a.x < b.x; } long long dcs(long long sx, long long mx) { return (sx + mx) * (mx - sx + 1) / 2; } int main() { scanf( %d , &n); cntmp.clear(); for (int i = 1; i <= n; i++) { scanf( %d %d , &pt[i].x, &pt[i].y); cntmp[make_pair(pt[i].x, pt[i].y)]++; } sort(pt + 1, pt + 1 + n, cpx); long long res = 0; for (int i = 1; i <= n; i++) { int j = i; long long cnt = 0; while (pt[j].x == pt[i].x && j <= n) { cnt++; j++; } j--; if (cnt > 1) { res += dcs(1, cnt - 1); } i = j; } sort(pt + 1, pt + 1 + n, cpy); for (int i = 1; i <= n; i++) { int j = i; long long cnt = 0; while (pt[j].y == pt[i].y && j <= n) { cnt++; j++; } j--; if (cnt > 1) { res += dcs(1, cnt - 1); } i = j; } for (map<pair<int, int>, int>::iterator it = cntmp.begin(); it != cntmp.end(); it++) { if (it->second > 1) { res -= dcs(1, it->second - 1); } } cout << res << endl; } |
#include <bits/stdc++.h> using namespace std; char func(char c) { if (c >= A && c <= Z ) c = tolower(c); if (c == o ) c = 0 ; else if (c == l || c == i ) c = 1 ; return c; } int main() { string s; int n; cin >> s >> n; for (int i = 0; i < n; i++) { string str; cin >> str; if (str.size() != s.size()) continue; bool ok = true; for (int j = 0; j < s.size(); j++) { if (func(s[j]) != func(str[j])) { ok = false; break; } } if (ok) { cout << No ; return 0; } } cout << Yes ; return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:128000000 ) using namespace std; map<string, int> a; map<string, int>::iterator ii, jj; string s; int main() { int k, i, v, u, j, n, m, d, d2, y, r, p, t1, t2, x, l, t, z, fl, to; cin >> n; for (i = 1; i <= n; i++) { cin >> s >> p; if (a[s] <= p) a[s] = p; } k = 0; for (ii = a.begin(); ii != a.end(); ii++) k++; cout << k << endl; for (ii = a.begin(); ii != a.end(); ii++) { t = 0; p = 0; for (jj = a.begin(); jj != a.end(); jj++) { if ((*ii).second >= (*jj).second) t++; if ((*ii).second < (*jj).second) p++; } if ((double)p / (double)k > 0.5) { cout << (*ii).first << << noob << endl; continue; } if ((double)t / (double)k >= 0.5 && (double)p / (double)k > 0.2) { cout << (*ii).first << << random << endl; continue; } if ((double)t / (double)k >= 0.8 && (double)p / (double)k > 0.1) { cout << (*ii).first << << average << endl; continue; } if ((double)t / (double)k >= 0.9 && (double)p / (double)k > 0.01) { cout << (*ii).first << << hardcore << endl; continue; } if ((double)t / (double)k >= 0.99) { cout << (*ii).first << << pro << endl; continue; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__NAND3_PP_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nand3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int solve(int n, int a[]) { int count = 0; for (int i = 0; i < n; ++i) { if (a[i] == i) { ++count; } } for (int i = 0; i < n; ++i) { if (a[i] != i && a[a[i]] == i) { return count + 2; } } return min(count + 1, n); } int main() { int n; int a[100000]; cin >> n; for (int i = 0; i < n; ++i) { cin >> a[i]; } cout << solve(n, a) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, maxi = 2, ans = 2; int a[100005]; vector<int> num; int main() { cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; if (n < 3) { cout << n; return 0; } for (int i = 2; i < n; i++) { if (a[i] == a[i - 1] + a[i - 2]) { ans++; maxi = max(maxi, ans); } else ans = 2; } cout << maxi; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A211OI_PP_BLACKBOX_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll INF = 4e18; const int MAXN = 1.1e5; ll T[MAXN]; int main() { ios::sync_with_stdio(0), cin.tie(0); ll N, M, A, D; cin >> N >> M >> A >> D; for (ll i = 0; i < M; i++) { cin >> T[i]; } sort(T, T + M); T[M] = INF; auto getEmployee = [&](ll i) -> ll { return i <= N ? i * A : INF; }; ll est = 1; ll cst = 0; ll ans = 0; while (est <= N || cst < M) { ll nxt = D + min(getEmployee(est), T[cst]); ll een = min(N + 1, (nxt / A) + 1); ll cen = ll(upper_bound(T, T + M, nxt) - T); ans++; if (cst == cen) { ll delta = een - est; assert(delta > 0); ll tgt = min(N + 1, T[cst] / A); ll extra = max(tgt - een, ll(0)) / delta; ans += extra; een += extra * delta; } assert(een > est || cen > cst); assert(est <= een && cst <= cen); tie(est, cst) = {een, cen}; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 105; vector<long long> a, b, v; string s; long long n, m, x; long long killAll() { vector<long long> hlp; long long i = 0; for (long long x : b) { while (i < v.size() and v[i] <= x) { hlp.push_back(v[i]); i++; } if (i == v.size()) return 0; else i++; } while (i < v.size()) { hlp.push_back(v[i]); i++; } long long ans = 0; long long j = hlp.size() - 1; for (__typeof(((long long)a.size() - 1)) i = ((long long)a.size() - 1); i >= (0); i--) { long long x = a[i]; if (j < i) return 0; if (hlp[j] >= x) ans += (hlp[j] - x); else return 0; j--; } while (j >= 0) { ans += hlp[j]; j--; } return ans; } long long killExact(long long k) { if (k > a.size()) return 0; long long i = k - 1; long long j = v.size() - 1; long long ans = 0; while (i >= 0 and j >= 0) { if (v[j] >= a[i]) ans += (v[j] - a[i]); else return 0; j--; i--; } return ans; } long long killFew() { long long ans = 0; for (long long i = 1; i <= m; i++) ans = max(ans, killExact(i)); return ans; } long long solve() { cin >> n >> m; for (__typeof((n)) i = (1); i <= (n); i++) { cin >> s >> x; if (s == ATK ) a.push_back(x); else b.push_back(x); } for (__typeof((m)) i = (1); i <= (m); i++) { cin >> x; v.push_back(x); } sort((v).begin(), (v).end()); sort((a).begin(), (a).end()); sort((b).begin(), (b).end()); cout << max(killAll(), killFew()) << n ; return 0; } signed main() { long long t; ios_base::sync_with_stdio(false); t = 1; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> const int N = 2e5 + 10; const int MOD = 1e9 + 7; const int INF = 2e9; using namespace std; vector<int> a; int f[N], d[N]; int c, n; int main() { ios::sync_with_stdio(false); cin >> c >> n; for (int i = 0; i < n; i++) { int x; cin >> x; a.push_back(x); } sort(a.begin(), a.end()); for (int i = 1; i <= N; i++) d[i] = -1; for (int i = 0; i < n; i++) if (d[a[i]] == -1) d[a[i]] = i; vector<int>::iterator it; for (int i = 1; i <= c; i++) { it = lower_bound(a.begin(), a.end(), i); if (*it == i) f[i] = it - a.begin(); else if (it > a.begin()) f[i] = it - a.begin() - 1; else f[i] = -1; } for (int i = 1; i < c; i++) { int tmp = c, prev = n + 1; bool ok = true; while (1) { int y = f[tmp]; if (y >= prev) y = prev - 1; if (y < 0) { cout << i; return 0; } if (y == -1) { cout << i; return 0; } else if (ok && a[y] <= i && i <= tmp) { tmp -= i; ok = false; } else { int x = a[y]; int pos = d[x]; int t1 = y - pos + 1; int t2 = tmp / x; if (t1 > t2) { tmp -= t2 * x; prev = y - t2 + 1; } else { tmp -= t1 * x; prev = pos; } } if (tmp == 0) break; } } cout << Greed is good ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBP_BLACKBOX_V
`define SKY130_FD_SC_HS__SDFBBP_BLACKBOX_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBP_BLACKBOX_V
|
/*
*
* Copyright (c) 2013
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
/*
* This top level module implements Bitcoin vanity address generation.
*/
module fpgaminer_vanitygen_top (
input clk
);
//*****************************************************************************
// Clock Generation
//*****************************************************************************
wire mining_clk;
clk_pll clk_pll_blk (
.rx_clk (clk),
.tx_mining_clk (mining_clk)
);
//*****************************************************************************
// External Input
//*****************************************************************************
wire reset;
wire [255:0] a, b;
wire [159:0] vanity_min, vanity_max;
virtual_wire # (.OUTPUT_WIDTH (256), .INSTANCE_ID ("A")) a_vw (.clk (mining_clk), .rx_input (), .tx_output (a));
virtual_wire # (.OUTPUT_WIDTH (256), .INSTANCE_ID ("B")) b_vw (.clk (mining_clk), .rx_input (), .tx_output (b));
virtual_wire # (.OUTPUT_WIDTH (160), .INSTANCE_ID ("MIN")) min_vw (.clk (mining_clk), .rx_input (), .tx_output (vanity_min));
virtual_wire # (.OUTPUT_WIDTH (160), .INSTANCE_ID ("MAX")) max_vw (.clk (mining_clk), .rx_input (), .tx_output (vanity_max));
virtual_wire # (.OUTPUT_WIDTH (1), .INSTANCE_ID ("RST")) reset_vw (.clk (mining_clk), .rx_input (), .tx_output (reset));
//*****************************************************************************
// Public Key Adder
//*****************************************************************************
reg adder_reset;
reg [255:0] x, y;
reg [63:0] cnt;
wire adder_done;
wire [255:0] adder_x, adder_y;
public_key_adder adder_blk (
.clk (mining_clk),
.reset (adder_reset),
.rx_x (x),
.rx_y (y),
.tx_done (adder_done),
.tx_x (adder_x),
.tx_y (adder_y)
);
//*****************************************************************************
// Hasher
//*****************************************************************************
wire hash_done;
wire [159:0] hash_hash;
address_hash hash_blk (
.clk (mining_clk),
.rx_reset (adder_done),
.rx_x (adder_x),
.rx_y (adder_y),
.tx_done (hash_done),
.tx_hash (hash_hash)
);
//*****************************************************************************
// Compare
//*****************************************************************************
wire vanity_match;
reg old_vanity_match = 1'b0;
reg [63:0] vanity_matched_cnt = 64'd0;
vanity_compare vanity_compare_blk (
.clk (mining_clk),
.rx_reset (hash_done),
.rx_min (vanity_min),
.rx_max (vanity_max),
.rx_hash (hash_hash),
.tx_match (vanity_match)
);
//*****************************************************************************
// External Output
//*****************************************************************************
virtual_wire # (.INPUT_WIDTH (1), .INSTANCE_ID ("DONE")) done_vw (.clk (mining_clk), .rx_input (adder_done), .tx_output ());
virtual_wire # (.INPUT_WIDTH (256), .INSTANCE_ID ("TXX")) adder_x_vw (.clk (mining_clk), .rx_input (adder_x), .tx_output ());
virtual_wire # (.INPUT_WIDTH (256), .INSTANCE_ID ("TXY")) adder_y_vw (.clk (mining_clk), .rx_input (adder_y), .tx_output ());
virtual_wire # (.INPUT_WIDTH (1), .INSTANCE_ID ("HDNE")) hash_done_vw (.clk (mining_clk), .rx_input (hash_done), .tx_output ());
virtual_wire # (.INPUT_WIDTH (160), .INSTANCE_ID ("HASH")) hash_vw (.clk (mining_clk), .rx_input (hash_hash), .tx_output ());
virtual_wire # (.INPUT_WIDTH (64), .INSTANCE_ID ("MTCH")) matched_vw (.clk (mining_clk), .rx_input (vanity_matched_cnt), .tx_output ());
always @ (posedge mining_clk)
begin
old_vanity_match <= vanity_match;
adder_reset <= 1'b0;
if (adder_done && !adder_reset)
begin
cnt <= cnt + 64'd1;
adder_reset <= 1'b1;
x <= adder_x;
y <= adder_y;
end
if (~old_vanity_match && vanity_match)
begin
vanity_matched_cnt <= cnt;
end
if (reset)
begin
cnt <= 64'd0;
x <= a;
y <= b;
adder_reset <= 1'b1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long pw(long long b, long long p) { if (!p) return 1; long long sq = pw(b, p / 2); sq *= sq; if (p % 2) sq *= b; return sq; } long long gcd(long long a, long long b) { return (b == 0 ? a : gcd(b, a % b)); } long long sd(long long x) { return x < 10 ? x : x % 10 + sd(x / 10); } long long lcm(long long a, long long b) { return ((a * b) / gcd(a, b)); } int n, xs, ys, xd, yd, dp[1010][1010]; int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; bool isvalid(int x, int y) { return (((y == 0 || y == n) && x <= n && x >= 0) || ((x == 0 || x == n) && y <= n && y >= 0)); } int dfs(int x, int y) { if (x == xd && y == yd) return 0; if (!isvalid(x, y)) return 1 << 30; int &ret = dp[x][y]; if (ret != -1) return ret; ret = 1 << 30; for (int i = 0; i < 4; ++i) ret = min(ret, dfs(x + dx[i], y + dy[i]) + 1); return ret; } int main() { cin >> n >> xs >> ys >> xd >> yd; memset(dp, -1, sizeof dp); cout << dfs(xs, ys); } |
#include <bits/stdc++.h> using namespace std; void addmod(int &a, long long b) { a = (a + b); if (a >= 1000000007) a -= 1000000007; } void mulmod(int &a, long long b) { a = (a * b) % 1000000007; } template <class T> bool domin(T &a, const T &b) { return a > b ? a = b, 1 : 0; } template <class T> bool domax(T &a, const T &b) { return a < b ? a = b, 1 : 0; } int gi() { int a; scanf( %d , &a); return a; } long long gll() { long long a; scanf( %lld , &a); return a; } int n; namespace treap { struct treap { int val, size, lazy; long long rnd; treap *l, *r; treap() : val(0), size(0), lazy(0), rnd((((long long)rand()) << 32) | rand()), l(NULL), r(NULL) {} treap(int val) : val(val), size(1), lazy(0), rnd((((long long)rand()) << 32) | rand()), l(NULL), r(NULL) {} void push() { if (lazy == 0) return; val += lazy; if (l != NULL) l->lazy += lazy; if (r != NULL) r->lazy += lazy; lazy = 0; } void updateSz() { size = 1; if (l != NULL) size += l->size; if (r != NULL) size += r->size; } }; typedef treap *ptreap; ptreap root = NULL; void split(ptreap tp, int key, ptreap &l, ptreap &r) { if (tp == NULL) { l = NULL, r = NULL; return; } tp->push(); if (tp->val < key) l = tp, split(tp->r, key, tp->r, r); else r = tp, split(tp->l, key, l, tp->l); if (l != NULL) l->updateSz(); if (r != NULL) r->updateSz(); } pair<ptreap, ptreap> split(int v) { ptreap l, r; split(root, v, l, r); return {l, r}; } pair<ptreap, ptreap> split(ptreap tp, int v) { ptreap l, r; split(tp, v, l, r); return {l, r}; } void insert(ptreap &tp, ptreap v) { if (tp == NULL) { tp = v; return; } tp->push(); if (v->rnd < tp->rnd) insert(v->val > tp->val ? tp->r : tp->l, v); else split(tp, v->val, v->l, v->r), tp = v; tp->updateSz(); } void insert(int v) { ptreap tp = new treap(v); insert(root, tp); } void merge(ptreap &t, ptreap l, ptreap r) { if (l != NULL) l->push(); if (r != NULL) r->push(); if (l == NULL || r == NULL) t = (l == NULL ? r : l); else if (l->rnd > r->rnd) t = l, merge(t->r, l->r, r); else t = r, merge(t->l, l, r->l); if (t != NULL) t->updateSz(); } void erase(ptreap &tp, int v) { if (tp == NULL) return; tp->push(); if (v == tp->val) { merge(tp, tp->l, tp->r); } else { erase(v < tp->val ? tp->l : tp->r, v); tp->updateSz(); } } int getmin(ptreap tp) { if (tp == NULL) return 0; tp->push(); return tp->l == NULL ? tp->val : getmin(tp->l); } int getmax(ptreap tp) { if (tp == NULL) return 0; tp->push(); return tp->r == NULL ? tp->val : getmax(tp->r); } void recalc(ptreap tp) { if (tp == NULL) return; tp->push(); recalc(tp->l); recalc(tp->r); tp->updateSz(); } void debug(ptreap &tp) { if (tp == NULL) return; tp->push(); if (tp->l != NULL) debug(tp->l); cout << << tp->val << : << tp->rnd << : << tp->size << endl; if (tp->r != NULL) debug(tp->r); } } // namespace treap int main() { n = gi(); for (int i = 0; i < n; i++) { int l = gi(), r = gi(); auto v = treap::split(l); auto v2 = treap::split(v.second, r); if (v2.first != NULL) v2.first->lazy++; if (v2.second != NULL) { auto v = treap::getmin(v2.second); treap::erase(v2.second, v); } treap::merge(treap::root, v.first, v2.first); treap::merge(treap::root, treap::root, v2.second); treap::insert(l); } cout << treap::root->size << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 4e5 + 5; const int BN = 25; int n, a[N], cnt; vector<int> v[BN]; int main() { ios ::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; } int res = 0; for (int i = 1; i <= n; ++i) { if (a[i] & 1) { int k = (i - 1) - cnt; if (k & 1) { res ^= 1; } } else { int k = cnt; if (k & 1) { res ^= 1; } } int cur_val = (a[i] & 1); for (int bit = 1; bit <= 24; ++bit) { if ((a[i] >> bit) & 1) { cur_val += (1 << bit); } v[bit].push_back(cur_val); } cnt += (a[i] & 1); } for (int bit = 1; bit <= 24; ++bit) sort(v[bit].begin(), v[bit].end()); for (int bit = 1; bit <= 24; ++bit) { while (!v[bit].empty()) { int cur_val = v[bit].back(); v[bit].pop_back(); int k = lower_bound(v[bit].begin(), v[bit].end(), (1 << bit) - cur_val) - v[bit].begin(); k = v[bit].size() - k; int j = lower_bound(v[bit].begin(), v[bit].end(), (1 << (bit + 1)) - cur_val) - v[bit].begin(); j = v[bit].size() - j; int l = lower_bound(v[bit].begin(), v[bit].end(), (1 << (bit + 1)) + (1 << bit) - cur_val) - v[bit].begin(); l = v[bit].size() - l; k += l; k -= j; if (k & 1) { res ^= (1 << bit); } } } cout << res; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS_IBUFDISABLE_INT.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 11/09/11 - Initial -- added due to CR 631983 fix - for timing netlist only
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/10/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS_IBUFDISABLE_INT (O, I, IB, IBUFDISABLE);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter USE_IBUFDISABLE = "TRUE";
localparam MODULE_NAME = "IBUFDS_IBUFDISABLE_INT";
output O;
input I;
input IB;
input IBUFDISABLE;
wire i_in, ib_in, ibufdisable_in;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
reg USE_IBUFDISABLE_BINARY = 1'b0;
assign O = (USE_IBUFDISABLE_BINARY == 1'b0) ? o_out :
((ibufdisable_in === 1'b1) ? 1'b1 : ((ibufdisable_in === 1'b0) ? o_out : 1'bx));
assign i_in = I;
assign ib_in = IB;
assign ibufdisable_in = IBUFDISABLE;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
#1 $finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
#1 $finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
#1 $finish;
end
endcase
case (USE_IBUFDISABLE)
"TRUE" : USE_IBUFDISABLE_BINARY <= #1 1'b1;
"FALSE" : USE_IBUFDISABLE_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute USE_IBUFDISABLE on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, USE_IBUFDISABLE);
#1 $finish;
end
endcase
end
always @(i_in or ib_in or DQS_BIAS_BINARY) begin
if (i_in == 1'b1 && ib_in == 1'b0)
o_out <= 1'b1;
else if (i_in == 1'b0 && ib_in == 1'b1)
o_out <= 1'b0;
else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((i_in === 1'bx) || (ib_in === 1'bx))
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//Register map:
//addr register type
//0 read data r
//1 write data w
//2 status r/w
//3 control r/w
//6 end-of-packet-value r/w
//INPUT_CLOCK: 100000000
//ISMASTER: 0
//DATABITS: 8
//TARGETCLOCK: 128000
//NUMSLAVES: 1
//CPOL: 0
//CPHA: 0
//LSBFIRST: 0
//EXTRADELAY: 0
//TARGETSSDELAY: 0
module TimeHoldOver_Qsys_spi_0 (
// inputs:
MOSI,
SCLK,
SS_n,
clk,
data_from_cpu,
mem_addr,
read_n,
reset_n,
spi_select,
write_n,
// outputs:
MISO,
data_to_cpu,
dataavailable,
endofpacket,
irq,
readyfordata
)
;
output MISO;
output [ 15: 0] data_to_cpu;
output dataavailable;
output endofpacket;
output irq;
output readyfordata;
input MOSI;
input SCLK;
input SS_n;
input clk;
input [ 15: 0] data_from_cpu;
input [ 2: 0] mem_addr;
input read_n;
input reset_n;
input spi_select;
input write_n;
wire E;
reg EOP;
wire MISO;
reg MOSI_reg;
reg ROE;
reg RRDY;
wire TMT;
reg TOE;
reg TRDY;
wire control_wr_strobe;
reg d1_tx_holding_emptied;
reg data_rd_strobe;
reg [ 15: 0] data_to_cpu;
reg data_wr_strobe;
wire dataavailable;
wire ds1_SCLK;
wire ds1_SS_n;
reg ds2_SCLK;
reg ds2_SS_n;
reg ds3_SS_n;
wire ds_MOSI;
wire endofpacket;
reg [ 15: 0] endofpacketvalue_reg;
wire endofpacketvalue_wr_strobe;
wire forced_shift;
reg iEOP_reg;
reg iE_reg;
reg iROE_reg;
reg iRRDY_reg;
reg iTMT_reg;
reg iTOE_reg;
reg iTRDY_reg;
wire irq;
reg irq_reg;
wire p1_data_rd_strobe;
wire [ 15: 0] p1_data_to_cpu;
wire p1_data_wr_strobe;
wire p1_rd_strobe;
wire p1_wr_strobe;
reg rd_strobe;
wire readyfordata;
wire resetShiftSample;
reg [ 7: 0] rx_holding_reg;
wire sample_clock;
reg shiftStateZero;
wire shift_clock;
reg [ 7: 0] shift_reg;
wire [ 10: 0] spi_control;
wire [ 10: 0] spi_status;
reg [ 3: 0] state;
wire status_wr_strobe;
reg transactionEnded;
reg tx_holding_emptied;
reg [ 7: 0] tx_holding_reg;
reg wr_strobe;
//spi_control_port, which is an e_avalon_slave
assign p1_rd_strobe = ~rd_strobe & spi_select & ~read_n;
// Read is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_strobe <= 0;
else
rd_strobe <= p1_rd_strobe;
end
assign p1_data_rd_strobe = p1_rd_strobe & (mem_addr == 0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_rd_strobe <= 0;
else
data_rd_strobe <= p1_data_rd_strobe;
end
assign p1_wr_strobe = ~wr_strobe & spi_select & ~write_n;
// Write is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wr_strobe <= 0;
else
wr_strobe <= p1_wr_strobe;
end
assign p1_data_wr_strobe = p1_wr_strobe & (mem_addr == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_wr_strobe <= 0;
else
data_wr_strobe <= p1_data_wr_strobe;
end
assign control_wr_strobe = wr_strobe & (mem_addr == 3);
assign status_wr_strobe = wr_strobe & (mem_addr == 2);
assign endofpacketvalue_wr_strobe = wr_strobe & (mem_addr == 6);
assign TMT = SS_n & TRDY;
assign E = ROE | TOE;
assign spi_status = {EOP, E, RRDY, TRDY, TMT, TOE, ROE, 3'b0};
// Streaming data ready for pickup.
assign dataavailable = RRDY;
// Ready to accept streaming data.
assign readyfordata = TRDY;
// Endofpacket condition detected.
assign endofpacket = EOP;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
iEOP_reg <= 0;
iE_reg <= 0;
iRRDY_reg <= 0;
iTRDY_reg <= 0;
iTMT_reg <= 0;
iTOE_reg <= 0;
iROE_reg <= 0;
end
else if (control_wr_strobe)
begin
iEOP_reg <= data_from_cpu[9];
iE_reg <= data_from_cpu[8];
iRRDY_reg <= data_from_cpu[7];
iTRDY_reg <= data_from_cpu[6];
iTMT_reg <= data_from_cpu[5];
iTOE_reg <= data_from_cpu[4];
iROE_reg <= data_from_cpu[3];
end
end
assign spi_control = {iEOP_reg, iE_reg, iRRDY_reg, iTRDY_reg, 1'b0, iTOE_reg, iROE_reg, 3'b0};
// IRQ output.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_reg <= 0;
else
irq_reg <= (EOP & iEOP_reg) | ((TOE | ROE) & iE_reg) | (RRDY & iRRDY_reg) | (TRDY & iTRDY_reg) | (TOE & iTOE_reg) | (ROE & iROE_reg);
end
assign irq = irq_reg;
// End-of-packet value register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
endofpacketvalue_reg <= 0;
else if (endofpacketvalue_wr_strobe)
endofpacketvalue_reg <= data_from_cpu;
end
assign p1_data_to_cpu = ((mem_addr == 2))? spi_status :
((mem_addr == 3))? spi_control :
((mem_addr == 6))? endofpacketvalue_reg :
rx_holding_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_to_cpu <= 0;
else
// Data to cpu.
data_to_cpu <= p1_data_to_cpu;
end
assign forced_shift = ds2_SS_n & ~ds3_SS_n;
assign ds1_SS_n = SS_n;
// System clock domain events.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
ds2_SS_n <= 1;
ds3_SS_n <= 1;
transactionEnded <= 0;
EOP <= 0;
RRDY <= 0;
TRDY <= 1;
TOE <= 0;
ROE <= 0;
tx_holding_reg <= 0;
rx_holding_reg <= 0;
d1_tx_holding_emptied <= 0;
end
else
begin
ds2_SS_n <= ds1_SS_n;
ds3_SS_n <= ds2_SS_n;
transactionEnded <= forced_shift;
d1_tx_holding_emptied <= tx_holding_emptied;
if (tx_holding_emptied & ~d1_tx_holding_emptied)
TRDY <= 1;
// EOP must be updated by the last (2nd) cycle of access.
if ((p1_data_rd_strobe && (rx_holding_reg == endofpacketvalue_reg)) || (p1_data_wr_strobe && (data_from_cpu[7 : 0] == endofpacketvalue_reg)))
EOP <= 1;
if (forced_shift)
begin
if (RRDY)
ROE <= 1;
else
rx_holding_reg <= shift_reg;
RRDY <= 1;
end
// On data read, clear the RRDY bit.
if (data_rd_strobe)
RRDY <= 0;
// On status write, clear all status bits (ignore the data).
if (status_wr_strobe)
begin
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
end
// On data write, load the transmit holding register and prepare to execute.
//Safety feature: if tx_holding_reg is already occupied, ignore this write, and generate
//the write-overrun error.
if (data_wr_strobe)
begin
if (TRDY)
tx_holding_reg <= data_from_cpu;
if (~TRDY)
TOE <= 1;
TRDY <= 0;
end
end
end
assign resetShiftSample = ~reset_n | transactionEnded;
assign MISO = ~SS_n & shift_reg[7];
assign ds1_SCLK = SCLK;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
ds2_SCLK <= 0;
else
ds2_SCLK <= ds1_SCLK;
end
assign shift_clock = ((~ds1_SS_n & ~ds1_SCLK)) & ~((~ds2_SS_n & ~ds2_SCLK));
assign sample_clock = (~(~ds1_SS_n & ~ds1_SCLK)) & ~(~(~ds2_SS_n & ~ds2_SCLK));
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
state <= 0;
else
state <= resetShiftSample ? 0 : (sample_clock & (state != 8)) ? (state + 1) : state;
end
assign ds_MOSI = MOSI;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
MOSI_reg <= 0;
else
MOSI_reg <= resetShiftSample ? 0 : sample_clock ? ds_MOSI : MOSI_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
shift_reg <= 0;
else
shift_reg <= resetShiftSample ? 0 : shift_clock ? (shiftStateZero ? tx_holding_reg : {shift_reg[6 : 0], MOSI_reg}) : shift_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
shiftStateZero <= 1;
else
shiftStateZero <= resetShiftSample ? 1 : shift_clock? 0 : shiftStateZero;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_holding_emptied <= 0;
else
tx_holding_emptied <= resetShiftSample ? 0 : shift_clock ? (shiftStateZero ? 1 : 0) : tx_holding_emptied;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int N; int main() { int T; scanf( %d , &T); while (T--) { cin >> N; printf( %d n , (N > 2 ? N - 2 : 0)); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O31A_FUNCTIONAL_PP_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long n, k, A, B; vector<long long> a(100000 + 5); long long rec(int l, int r) { long long m = (l + r) / 2, i, j, col = 0, lng = r - l + 1; i = lower_bound(a.begin(), a.end(), l) - a.begin(); j = upper_bound(a.begin(), a.end(), r) - a.begin(); j--; col = j - i + 1; if (l == r && !col) return A; if (l == r && col) return B * col; if (!col) return A; return min(B * lng * col, rec(l, m) + rec(m + 1, r)); } int main() { long long x; cin >> n >> k >> A >> B; for (int i = 0; i < k; i++) { cin >> x; a.push_back(x); } sort(a.begin(), a.end()); cout << rec(1, pow(2, n)); return 0; } |
#include <bits/stdc++.h> using namespace std; int i; char s[100005]; int main() { scanf( %s , s); int l = strlen(s); for (i = 0; i < l; i++) { if (s[i] == s[l - 1 - i]) continue; return 0 * printf( NO n ); } for (i = 0; i < l; i++) { if (s[i] == A || s[i] == H || s[i] == I || s[i] == M || s[i] == O || s[i] == T || s[i] == U || s[i] == V || s[i] == W || s[i] == X || s[i] == Y ) continue; return 0 * printf( NO n ); } printf( YES n ); } |
module autoconstant_gooch
(/*AUTOARG*/
// Outputs
out1, out2, out3,
// Inputs
in1, in2, in3
);
input [3:0] in1;
input [3:0] in2;
input [3:0] in3;
output [3:0] out1;
reg [3:0] out1;
output [3:0] out2;
reg [3:0] out2;
output [3:0] out3;
reg [3:0] out3;
always @(/*AUTOSENSE*/in1 or in2 or in3)
begin
case (in1)
4'b0001 : begin
out1 = in2;
end
4'b0010 : begin
out1 = in2 + in3;
end
4'b0100 : begin
out1 = in2 - in3;
end
4'b1000 : begin
out1 = in2;
end
default : begin
out1 = {4{1'b0}};
end
endcase
end
always @(/*AUTOSENSE*/in1 or in2 or in3)
begin
case (in1)
4'b0001 : begin
out2 = in2;
end
4'b0010 : begin
out2 = in2 + in3;
end
4'b0100 : begin
out2 = in2 - in3;
end
4'b1000 : begin
out2 = in2;
end
default : begin
out2 = {4{1'b0}};
end
endcase
end
always @(/*AUTOSENSE*/in1 or in2 or in3)
begin
/* AUTO_CONSTANT( temp )*/
/* AxxxUTO_CONSTANT temp */
out3 = in1 + in2;
temp2 = temp;
// ERROR here - above constant definition is not
// correct - no braces - and so parser keeps looking
// for the first variable it finds between a pair of
// braces - in this case, in2. This in2 is now a
// "constant" and is removed from all sensitivity lists.
// ( in2 )
case (in1)
4'b0001 : begin
out3 = in2;
end
4'b0010 : begin
out3 = in2 + in3;
end
4'b0100 : begin
out3 = in2 - in3;
end
4'b1000 : begin
out3 = in2;
end
default : begin
out3 = {4{1'b0}};
end
endcase
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_if0_p0_reset_sync(
reset_n,
clk,
reset_n_sync
);
parameter RESET_SYNC_STAGES = 4;
parameter NUM_RESET_OUTPUT = 1;
input reset_n;
input clk;
output [NUM_RESET_OUTPUT-1:0] reset_n_sync;
// identify the synchronizer chain so that Quartus can analyze metastability.
// Since these resets are localized to the PHY alone, make them routed locally
// to avoid using global networks.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name GLOBAL_SIGNAL OFF"}*) reg [RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:0] reset_reg /*synthesis dont_merge */;
generate
genvar i;
for (i=0; i<RESET_SYNC_STAGES+NUM_RESET_OUTPUT-1; i=i+1)
begin: reset_stage
always @(posedge clk or negedge reset_n)
begin
if (~reset_n)
reset_reg[i] <= 1'b0;
else
begin
if (i==0)
reset_reg[i] <= 1'b1;
else if (i < RESET_SYNC_STAGES)
reset_reg[i] <= reset_reg[i-1];
else
reset_reg[i] <= reset_reg[RESET_SYNC_STAGES-2];
end
end
end
endgenerate
assign reset_n_sync = reset_reg[RESET_SYNC_STAGES+NUM_RESET_OUTPUT-2:RESET_SYNC_STAGES-1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFRTP_TB_V
`define SKY130_FD_SC_LS__SDFRTP_TB_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfrtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 RESET_B = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 RESET_B = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 RESET_B = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 RESET_B = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__sdfrtp dut (.D(D), .SCD(SCD), .SCE(SCE), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFRTP_TB_V
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e6 + 5; const int K = 20; vector<int> P[N]; int s[K]; int t[K]; int L[1 << K]; int R[1 << K]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int n, m, k; cin >> n >> m >> k; char f; int c0 = 0, c1 = 0; for (int i = 0; i < k; i++) { cin >> f; s[i] = f - 0 ; c0 += s[i]; } for (int i = 0; i < k; i++) { cin >> f; t[i] = f - 0 ; c1 += t[i]; } for (int i = 0; i <= n; i++) { for (int j = 0; j < k; j++) P[i].push_back(j); } int l, r; for (int i = 1; i <= n; i++) { cin >> l >> r; l--; r--; P[i][l] = r; P[i][r] = l; vector<int> nw; for (auto x : P[i]) { nw.push_back(P[i - 1][x]); } P[i] = nw; } for (int i = 0; i < (1 << k); i++) { L[i] = (int)1e9; R[i] = -1; } int mask; for (int i = 0; i <= n - 1; i++) { mask = 0; for (int j = 0; j < k; j++) { if (s[j]) mask |= (1 << P[i][j]); } L[mask] = min(L[mask], i); } for (int i = 1; i <= n; i++) { mask = 0; for (int j = 0; j < k; j++) { if (t[j]) mask |= (1 << P[i][j]); } R[mask] = max(R[mask], i); } int nex; for (int i = (1 << k) - 1; i >= 0; i--) { for (int j = 0; j < k; j++) { if ((i & (1 << j))) continue; nex = (i | (1 << j)); L[i] = min(L[i], L[nex]); R[i] = max(R[i], R[nex]); } } int mx = 0; int fl = 0, fr = n; for (int i = 0; i < (1 << k); i++) { if (L[i] == (int)1e9 || R[i] == -1) continue; if (R[i] - L[i] >= m) { if (__builtin_popcount(i) > mx) { mx = __builtin_popcount(i); fl = L[i], fr = R[i]; } } } cout << k + 2 * mx - c0 - c1 << n ; cout << fl + 1 << << fr << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; map<int, int> mp; int main() { int n, m; cin >> n >> m; int now1 = 0; for (int i = 0; i < n; i++) { int c, t; cin >> c >> t; now1 += c * t; mp[now1] = 1; } map<int, int>::iterator it = mp.begin(); int now = 0; for (int i = 0; i < m; i++) { int v; cin >> v; while (v > it->first) { it++; now++; } cout << now + 1 << endl; } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5; struct Node { int value; struct Node *next; } *head = NULL, *tail; struct Query { int index, ans1, ans2; long long round; } queries[maxn]; bool cmp_by_round(const Query &lhs, const Query &rhs) { return lhs.round < rhs.round; } bool cmp_by_index(const Query &lhs, const Query &rhs) { return lhs.index < rhs.index; } int a[maxn], b[maxn]; int main() { int n, q, maxv = 0; scanf( %d%d , &n, &q); struct Node *last = NULL; for (int i = 0; i < n; i++) { scanf( %d , a + i); struct Node *node = (Node *)malloc(sizeof(Node)); node->value = a[i]; node->next = NULL; if (head == NULL) head = node; if (last) last->next = node; last = tail = node; if (a[i] > a[maxv]) maxv = i; } for (int i = 0; i < q; i++) { scanf( %lld , &queries[i].round); queries[i].index = i; } sort(queries, queries + q, cmp_by_round); int index_query = 0; for (int i = 0; i < maxv; i++) { struct Node *node1 = (Node *)malloc(sizeof(Node)); struct Node *node2 = (Node *)malloc(sizeof(Node)); int v1 = head->value, v2 = head->next->value; while (1LL * i == queries[index_query].round - 1) { queries[index_query].ans1 = head->value; queries[index_query].ans2 = head->next->value; index_query++; } if (v1 < v2) swap(v1, v2); node1->value = v1; if (head->next->next) node1->next = head->next->next; else node1->next = node2; node2->value = v2; node2->next = NULL; tail->next = node2; tail = node2; free(head->next); free(head); head = node1; } struct Node *node = head; for (int i = 0; i < n; i++) { b[i] = node->value; node = node->next; } while (index_query < q) { long long temp_round = queries[index_query].round - maxv; queries[index_query].ans1 = b[0]; queries[index_query].ans2 = b[int((temp_round - 1) % (n - 1) + 1)]; index_query++; } sort(queries, queries + q, cmp_by_index); for (int i = 0; i < q; i++) printf( %d %d n , queries[i].ans1, queries[i].ans2); return 0; } |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// IMPORTANT: This requires an input text file named "rf1.fill"
// Include definition of the control signals
`include "control.h"
// Non-synthesizable behavioral RTL model for the instruction memory
module data_mem (data_out,data_in,mem_ctrl_addr,clk,dm_ctrl_sig);
// load instr - take data out
// store - put data into the memory
// ===============================================================
// Output signals...
// Data output read from the data memory
output [0:127] data_out;
// ===============================================================
// Input signals
// Data input stored into the data memory
input [0:127] data_in;
/**
* Enable signal to indicate that the instruction memory shall be
* from an input text file named "rf1.fill"
*/
input [0:31] mem_ctrl_addr;
// Clock signal
input clk;
// Control signals for the data memory
input [0:1] dm_ctrl_sig;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Definitions for the constants the instruction memory
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Declare "reg" signals:
reg [0:127] data_out; // Output signals
/**
* (256 word) depth and (31 bits per word) width
*/
reg [127:0] data_mem [255:0]; // Store the data here
// Store instruction address in the instruction memory
// ===============================================================
initial
begin
/**
* Read the input data for r from an input file named
* "rf1.fill"'
*
* The system task to read data from the file must be placed
* in an INITIAL block
*/
$readmemh("rf1.fill",data_mem);
end
// A change in the instruction address activates this...
always @(posedge clk)
begin
/**
* Check the control signal and implement the appropriate
* function
*/
case(dm_ctrl_sig)
`memwld:
begin
// Read the data from the memory
data_out<=data_mem[mem_ctrl_addr[0:7]];
end
`memwst:
begin
// Write the data to the memory
data_mem[mem_ctrl_addr[0:7]]<=data_in;
$display("Value written to data mem",data_mem[mem_ctrl_addr[0:7]],"#");
end
`memnop:
begin
data_out<=128'd0;
end
default:
begin
data_out<=128'd0;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:58:55 05/17/2016
// Design Name:
// Module Name: escritor_lector_rtc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module escritor_lector_rtc_2
(
input wire clk,reset,
input wire [7:0] in_dato, port_id,
input wire write_strobe, k_write_strobe, read_strobe,
output wire reg_a_d,reg_cs,reg_rd,reg_wr,
output wire[7:0]out_dato,
output reg flag_done,
inout [7:0]dato
);
wire fin_lectura_escritura;
reg en_funcion;
reg [7:0]addr_RAM,dato_escribir;
reg [7:0]reg_addr_RAM, reg_dato_escribir;
reg reg_escribir_leer,escribir_leer;
reg state_reg_flag,state_next_flag;//Para la máquina de estados que controla el flag_done
wire direccion_dato;//conexión interna
/// I/O Datos
Driver_bus_bidireccional instance_driver_bus_bidireccional (
.clk(clk),
.in_flag_escritura(~reg_wr),
.in_flag_lectura(~reg_rd),
.in_direccion_dato(direccion_dato), //bandera para saber si se debe escribir direccion/dato
.in_dato(dato_escribir),
.out_reg_dato(out_dato),
.addr_RAM(addr_RAM),
.dato(dato)
);
//Generador de señales de control
signal_control_rtc_generator instance_signal_control_rtc_generator (
.clk(clk),
.reset(reset),
.in_escribir_leer(escribir_leer),
.en_funcion(en_funcion),
.reg_a_d(reg_a_d),
.reg_cs(reg_cs),
.reg_wr(reg_wr),
.reg_rd(reg_rd),
.out_direccion_dato(direccion_dato),
.flag_done(fin_lectura_escritura)
);
//Para habilitar el generador de señales
always@(posedge clk)
begin
if(port_id == 8'h0E) en_funcion <= 1'b1;
else en_funcion <= 1'b0;
end
// logica secuencial
always@(negedge clk , posedge reset) begin
if (reset)begin
addr_RAM <= 8'h0;
dato_escribir <= 8'h0;
escribir_leer <= 1'b0;
end
else begin
addr_RAM <= reg_addr_RAM;
dato_escribir <= reg_dato_escribir;
escribir_leer <= reg_escribir_leer;
end
end
// logica combinacional para port_id
always@* begin
if (write_strobe == 1'b1 || k_write_strobe == 1'b1) begin
// inicio de secuencia de lectura_escritura rtc
case (port_id)
8'h00: begin //actualiza direccion
reg_addr_RAM = in_dato;
reg_dato_escribir = dato_escribir;
reg_escribir_leer = escribir_leer;
end
8'h01: begin // actualiza dato
reg_dato_escribir = in_dato;
reg_addr_RAM = addr_RAM;
reg_escribir_leer = escribir_leer;
end
8'h0E: begin // inicia secuancia de rtc
reg_addr_RAM = addr_RAM;
reg_dato_escribir = dato_escribir;
reg_escribir_leer = in_dato[0];
end
default: begin
reg_addr_RAM = addr_RAM;
reg_dato_escribir = dato_escribir;
reg_escribir_leer = escribir_leer;
end
endcase
end
else begin
reg_addr_RAM = addr_RAM;
reg_dato_escribir = dato_escribir;
reg_escribir_leer = escribir_leer;
end
end
/// maquina de estados para manipular fin lectura escritura
always @ (negedge clk, posedge reset) begin
if (reset) state_reg_flag <= 1'b0;
else state_reg_flag <= state_next_flag;
end
always@*
begin
state_next_flag = state_reg_flag;
case (state_reg_flag)
1'b0: begin
flag_done = 8'h00;
if (fin_lectura_escritura == 1) state_next_flag = 1'b1;
else state_next_flag = 1'b0;
end
1'b1: begin
flag_done = 8'h01;
if(port_id == 8'h0F && read_strobe == 1) state_next_flag = 1'b0;//Cuando el micro lee el dato se baja la bandera
else state_next_flag = 1'b1;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__OR4BB_BEHAVIORAL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__or4bb (
X ,
A ,
B ,
C_N,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out;
wire or0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out, D_N, C_N );
or or0 (or0_out_X, B, A, nand0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4BB_BEHAVIORAL_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t;
//Several simulators don't support this.
//typedef struct pack2; // Forward declaration
typedef struct packed { // [3:0]
bit b3;
bit b2;
bit b1;
bit b0;
} b4_t;
typedef struct packed { // [3:0]
b4_t x1;
b4_t x0;
} b4x2_t;
typedef union packed { // [3:0]
bit [3:0] quad0;
b4_t quad1;
} q4_t;
typedef struct packed { // [5:0]
bit msb;
q4_t four;
bit lsb;
} pack2_t;
typedef union packed { // [5:0]
pack2_t pack2;
bit [6:1] pvec;
// Vector not allowed in packed structure, per spec:
// bit vec[6];
// bit vec2d[2][3];
} pack3_t;
const b4_t b4_const_a = '{1'b1, 1'b0, 1'b0, 1'b1};
// Cast to a pattern - note bits are tagged out of order
const b4_t b4_const_b = b4_t'{ b1 : 1'b0, b0 : 1'b1, b3 : 1'b1, b2 : 1'b0 };
wire b4_t b4_wire;
assign b4_wire = '{1'b1, 1'b0, 1'b1, 1'b0};
pack2_t arr[2];
initial begin
pack3_t tsu;
tsu = 6'b110110;
// 543210
if (tsu!=6'b110110) $stop;
if (tsu[5:4]!=2'b11) $stop;
if (tsu[5:4] == tsu[1:0]) $stop; // Not a good extraction test if LSB subtraction doesn't matter
if (tsu.pvec!=6'b110110) $stop;
if (tsu.pvec[6:5]!=2'b11) $stop;
if (tsu.pack2[5:1] != 5'b11011) $stop;
if (tsu.pack2.msb != 1'b1) $stop;
if (tsu.pack2.lsb != 1'b0) $stop;
if (tsu.pack2.four.quad0 != 4'b1011) $stop;
if (tsu.pack2.four.quad1.b0 != 1'b1) $stop;
if (tsu.pack2.four.quad1.b1 != 1'b1) $stop;
if (tsu.pack2.four.quad1.b2 != 1'b0) $stop;
if (tsu.pack2.four.quad1.b3 != 1'b1) $stop;
//
tsu = 1'b0 ? '0 : '{pvec: 6'b101011};
if (tsu!=6'b101011) $stop;
//
arr[0] = 6'b101010;
arr[1] = 6'b010101;
if (arr[0].four !== 4'b0101) $stop;
if (arr[1].four !== 4'b1010) $stop;
//
// Initialization
begin
b4_t q = '{1'b1, 1'b1, 1'b0, 1'b0};
if (q != 4'b1100) $stop;
end
begin
b4_t q = '{3{1'b1}, 1'b0};
if (q != 4'b1110) $stop;
end
begin
b4_t q = '{4{1'b1}}; // Repeats the {}
if (q != 4'b1111) $stop;
end
begin
b4x2_t m = '{4'b1001, '{1'b1, 1'b0, 1'b1, 1'b1}};
if (m != 8'b10011011) $stop;
end
begin
b4_t q = '{default:1'b1};
if (q != 4'b1111) $stop;
end
begin
b4_t q = '{b0:1'b1, b2:1'b1, b3:1'b1, b1:1'b0};
if (q != 4'b1101) $stop;
end
begin
b4_t q = '{b2:1'b0, default:1'b1};
if (q != 4'b1011) $stop;
end
if (b4_const_a != 4'b1001) $stop;
if (b4_const_b != 4'b1001) $stop;
if (b4_wire != 4'b1010) $stop;
if (pat(4'b1100, 4'b1100)) $stop;
if (pat('{1'b1, 1'b0, 1'b1, 1'b1}, 4'b1011)) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
function pat(b4_t in, logic [3:0] cmp);
if (in !== cmp) $stop;
pat = 1'b0;
endfunction
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND2_BEHAVIORAL_V
`define SKY130_FD_SC_HS__TAPVGND2_BEHAVIORAL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvgnd2 (
VPWR,
VGND
);
// Module ports
input VPWR;
input VGND;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND2_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; long long n, x, a[200005], b[200005]; int main() { cin >> n; for (int i = 1; i <= n / 2; i++) cin >> b[i]; a[1] = 0; a[n] = b[1]; for (int i = 2; i <= n / 2; i++) { a[i] = a[i - 1]; a[n - i + 1] = b[i] - a[i]; if (a[n - i + 1] > a[n - i + 2]) { a[n - i + 1] = a[n - i + 2]; a[i] = b[i] - a[n - i + 1]; } } for (int i = 1; i <= n; i++) { cout << a[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using u32 = unsigned int; using u64 = unsigned long long; char buf[10]; void NO() { puts( Impossible ); exit(0); } ll update(ll x, ll c) { if (x == LLONG_MAX || x == LLONG_MIN) return x; return x + c; } int main() { int n; scanf( %d , &n); ll max_r = LLONG_MAX; ll min_r = LLONG_MIN; for (int i = (0); i < (n); ++i) { ll c_i, d_i; scanf( %lld%lld , &c_i, &d_i); ; if (d_i == 2) { if (min_r >= 1900) NO(); if (max_r >= 1900) max_r = 1899; } else if (d_i == 1) { if (max_r < 1900) NO(); if (min_r < 1900) min_r = 1900; } max_r = update(max_r, c_i); min_r = update(min_r, c_i); } if (max_r == LLONG_MAX) puts( Infinity ); else printf( %lld , max_r); return 0; } |
#include <bits/stdc++.h> using namespace std; int n; vector<int> sz[1001]; vector<int> s[1001]; vector<int> l; bool v[1001]; int dist[1001][1001]; vector<pair<int, pair<int, int> > > t; void bfs(int a, int f) { for (int i = 0; i < sz[a].size(); i++) { int x = sz[a][i]; if (dist[x][f] == 0) { dist[x][f] = dist[a][f] + 1; bfs(x, f); } } } void solve(int a, int b, int y) { if (y == 0) { return; } if (sz[a].size() == 1) { swap(a, b); } if (sz[a].size() == 1) { t.push_back({a, {b, y}}); return; } int esz, msz, besz = 0, bmsz = 0; for (int i = 0; i < sz[a].size(); i++) { int x = sz[a][i]; if (x != b) { esz = x; swap(esz, msz); } } int c, d, e, f; if (sz[b].size() == 1) { e = b; f = b; } else { for (int i = 0; i < sz[b].size(); i++) { int x = sz[b][i]; if (x != a) { besz = x; swap(besz, bmsz); } } } for (int i = 0; i < l.size(); i++) { int x = l[i]; if (dist[a][x] < dist[b][x]) { if (dist[esz][x] < dist[msz][x]) { c = x; } else { d = x; } } else { if (besz != 0) { if (dist[besz][x] < dist[bmsz][x]) { e = x; } else { f = x; } } else { e = x; swap(e, f); } } } y /= 2; t.push_back({c, {e, y}}); t.push_back({d, {f, y}}); t.push_back({c, {d, -y}}); if (e != f) { t.push_back({e, {f, -y}}); } } int main() { cin >> n; for (int i = 1; i < n; i++) { int a, b, c; cin >> a >> b >> c; sz[a].push_back(b); sz[b].push_back(a); s[a].push_back(c); s[b].push_back(c); } for (int i = 1; i <= n; i++) { if (sz[i].size() == 2) { cout << NO ; return 0; } if (sz[i].size() == 1) { l.push_back(i); } } for (int i = 1; i <= n; i++) { dist[i][i] = 1; bfs(i, i); } cout << YES << n ; for (int i = 1; i <= n; i++) { for (int j = 0; j < sz[i].size(); j++) { int x = sz[i][j]; int y = s[i][j]; if (i < x) { solve(i, x, y); } } } cout << t.size() << n ; for (int i = 0; i < t.size(); i++) { cout << t[i].first << << t[i].second.first << << t[i].second.second << n ; } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9643_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dcfilter_data_out,
adc_dcfilter_data_in,
adc_iqcor_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter IQSEL = 0;
parameter CHID = 0;
parameter DP_DISABLE = 0;
// adc interface
input adc_clk;
input adc_rst;
input [13:0] adc_data;
input adc_or;
// channel interface
output [15:0] adc_dcfilter_data_out;
input [15:0] adc_dcfilter_data_in;
output [15:0] adc_iqcor_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire [15:0] adc_dfmt_data_s;
wire [15:0] adc_dcfilter_data_i_s;
wire [15:0] adc_dcfilter_data_q_s;
wire adc_iqcor_enb_s;
wire adc_dcfilt_enb_s;
wire adc_dfmt_se_s;
wire adc_dfmt_type_s;
wire adc_dfmt_enable_s;
wire [15:0] adc_dcfilt_offset_s;
wire [15:0] adc_dcfilt_coeff_s;
wire [15:0] adc_iqcor_coeff_1_s;
wire [15:0] adc_iqcor_coeff_2_s;
wire [ 3:0] adc_pnseq_sel_s;
wire adc_pn_err_s;
wire adc_pn_oos_s;
// iq correction inputs
assign adc_dcfilter_data_i_s = (IQSEL == 1) ? adc_dcfilter_data_in : adc_dcfilter_data_out;
assign adc_dcfilter_data_q_s = (IQSEL == 1) ? adc_dcfilter_data_out : adc_dcfilter_data_in;
axi_ad9643_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
generate
if (DP_DISABLE == 1) begin
assign adc_dfmt_data_s = {2'd0, adc_data};
end else begin
ad_datafmt #(.DATA_WIDTH(14)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data),
.valid_out (),
.data_out (adc_dfmt_data_s),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign adc_dcfilter_data_out = adc_dfmt_data_s;
end else begin
ad_dcfilter i_ad_dcfilter (
.clk (adc_clk),
.valid (1'b1),
.data (adc_dfmt_data_s),
.valid_out (),
.data_out (adc_dcfilter_data_out),
.dcfilt_enb (adc_dcfilt_enb_s),
.dcfilt_coeff (adc_dcfilt_coeff_s),
.dcfilt_offset (adc_dcfilt_offset_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign adc_iqcor_data = (IQSEL == 1) ? adc_dcfilter_data_q_s : adc_dcfilter_data_i_s;
end else begin
ad_iqcor #(.IQSEL(IQSEL)) i_ad_iqcor (
.clk (adc_clk),
.valid (1'b1),
.data_i (adc_dcfilter_data_i_s),
.data_q (adc_dcfilter_data_q_s),
.valid_out (),
.data_out (adc_iqcor_data),
.iqcor_enable (adc_iqcor_enb_s),
.iqcor_coeff_1 (adc_iqcor_coeff_1_s),
.iqcor_coeff_2 (adc_iqcor_coeff_2_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(CHID)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (adc_iqcor_enb_s),
.adc_dcfilt_enb (adc_dcfilt_enb_s),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (adc_dcfilt_offset_s),
.adc_dcfilt_coeff (adc_dcfilt_coeff_s),
.adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
.adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
module simd(
issue_source_reg1,
issue_source_reg2,
issue_source_reg3,
issue_dest_reg1,
issue_dest_reg2,
issue_imm_value0,
issue_imm_value1,
issue_opcode,
issue_wfid,
issue_alu_select,
vgpr_source1_data,
vgpr_source2_data,
vgpr_source3_data,
sgpr_rd_data,
exec_rd_exec_value,
exec_rd_vcc_value,
exec_rd_m0_value,
exec_rd_scc_value,
issue_instr_pc,
rfa_queue_entry_serviced,
vgpr_source1_rd_en,
vgpr_source2_rd_en,
vgpr_source3_rd_en,
vgpr_source1_addr,
vgpr_source2_addr,
vgpr_source3_addr,
vgpr_dest_addr,
vgpr_dest_data,
vgpr_wr_en,
vgpr_wr_mask,
exec_rd_wfid,
exec_rd_en,
exec_wr_vcc_wfid,
exec_wr_vcc_en,
exec_wr_vcc_value,
sgpr_rd_en,
sgpr_rd_addr,
sgpr_wr_addr,
sgpr_wr_en,
sgpr_wr_data,
sgpr_wr_mask,
issue_alu_ready,
vgpr_instr_done_wfid,
vgpr_instr_done,
rfa_queue_entry_valid,
tracemon_retire_pc,
clk,
rst
);
input clk;
input rst;
input issue_alu_select, exec_rd_scc_value, rfa_queue_entry_serviced;
input[5:0] issue_wfid;
input[11:0] issue_source_reg1, issue_source_reg2, issue_source_reg3,
issue_dest_reg1, issue_dest_reg2;
input[15:0] issue_imm_value0;
input[31:0] issue_imm_value1, issue_opcode, sgpr_rd_data, exec_rd_m0_value,
issue_instr_pc;
input[63:0] exec_rd_exec_value, exec_rd_vcc_value;
input[2047:0] vgpr_source1_data, vgpr_source2_data, vgpr_source3_data;
output vgpr_source1_rd_en, vgpr_source2_rd_en, vgpr_source3_rd_en, vgpr_wr_en,
exec_rd_en, exec_wr_vcc_en, sgpr_rd_en, sgpr_wr_en, issue_alu_ready,
vgpr_instr_done, rfa_queue_entry_valid;
output[5:0] exec_rd_wfid, exec_wr_vcc_wfid, vgpr_instr_done_wfid;
output[8:0] sgpr_rd_addr, sgpr_wr_addr;
output[9:0] vgpr_source1_addr, vgpr_source2_addr, vgpr_source3_addr,
vgpr_dest_addr;
output[31:0] tracemon_retire_pc;
output[63:0] vgpr_wr_mask, exec_wr_vcc_value, sgpr_wr_data, sgpr_wr_mask;
output[2047:0] vgpr_dest_data;
alu #(.MODULE(`MODULE_SIMD))
alu(
.issue_source_reg1(issue_source_reg1),
.issue_source_reg2(issue_source_reg2),
.issue_source_reg3(issue_source_reg3),
.issue_dest_reg1(issue_dest_reg1),
.issue_dest_reg2(issue_dest_reg2),
.issue_imm_value0(issue_imm_value0),
.issue_imm_value1(issue_imm_value1),
.issue_opcode(issue_opcode),
.issue_wfid(issue_wfid),
.issue_alu_select(issue_alu_select),
.vgpr_source1_data(vgpr_source1_data),
.vgpr_source2_data(vgpr_source2_data),
.vgpr_source3_data(vgpr_source3_data),
.sgpr_rd_data(sgpr_rd_data),
.exec_rd_exec_value(exec_rd_exec_value),
.exec_rd_vcc_value(exec_rd_vcc_value),
.exec_rd_m0_value(exec_rd_m0_value),
.exec_rd_scc_value(exec_rd_scc_value),
.issue_instr_pc(issue_instr_pc),
.rfa_queue_entry_serviced(rfa_queue_entry_serviced),
.vgpr_source1_rd_en(vgpr_source1_rd_en),
.vgpr_source2_rd_en(vgpr_source2_rd_en),
.vgpr_source3_rd_en(vgpr_source3_rd_en),
.vgpr_source1_addr(vgpr_source1_addr),
.vgpr_source2_addr(vgpr_source2_addr),
.vgpr_source3_addr(vgpr_source3_addr),
.vgpr_dest_addr(vgpr_dest_addr),
.vgpr_dest_data(vgpr_dest_data),
.vgpr_wr_en(vgpr_wr_en),
.vgpr_wr_mask(vgpr_wr_mask),
.exec_rd_wfid(exec_rd_wfid),
.exec_rd_en(exec_rd_en),
.exec_wr_vcc_wfid(exec_wr_vcc_wfid),
.exec_wr_vcc_en(exec_wr_vcc_en),
.exec_wr_vcc_value(exec_wr_vcc_value),
.sgpr_rd_en(sgpr_rd_en),
.sgpr_rd_addr(sgpr_rd_addr),
.sgpr_wr_addr(sgpr_wr_addr),
.sgpr_wr_en(sgpr_wr_en),
.sgpr_wr_data(sgpr_wr_data),
.sgpr_wr_mask(sgpr_wr_mask),
.issue_alu_ready(issue_alu_ready),
.vgpr_instr_done_wfid(vgpr_instr_done_wfid),
.vgpr_instr_done(vgpr_instr_done),
.rfa_queue_entry_valid(rfa_queue_entry_valid),
.tracemon_retire_pc(tracemon_retire_pc),
.clk(clk),
.rst(rst)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_1_V
`define SKY130_FD_SC_LS__O311A_1_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o311a_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o311a_1 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_1_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 20 13:53:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_0/affine_block_uint_to_ieee754_fp_0_0_stub.v
// Design : affine_block_uint_to_ieee754_fp_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "uint_to_ieee754_fp,Vivado 2016.4" *)
module affine_block_uint_to_ieee754_fp_0_0(x, y)
/* synthesis syn_black_box black_box_pad_pin="x[9:0],y[31:0]" */;
input [9:0]x;
output [31:0]y;
endmodule
|
module mux4_1(output2, w, x, y, z, sel); wire _00_; wire _01_; wire _02_; wire _03_; wire _04_; wire _05_; wire _06_; wire _07_; wire _08_; wire _09_; wire _10_; wire _11_; wire _12_; wire _13_; wire _14_; wire _15_; wire _16_; wire _17_; wire _18_; wire _19_; wire _20_; wire _21_; wire _22_; wire _23_; wire _24_; wire _25_; wire _26_; wire _27_; wire _28_; wire _29_; wire _30_; wire _31_; wire _32_; wire _33_; wire _34_; wire _35_; output [3:0] output2; input [1:0] sel; input [3:0] w; input [3:0] x; input [3:0] y; input [3:0] z; NAND2X1 _36_ ( .A(w[0]), .B(_00_), .Y(_01_) ); INVX1 _37_ ( .A(sel[1]), .Y(_02_) ); INVX1 _38_ ( .A(z[0]), .Y(_03_) ); OAI21X1 _39_ ( .A(sel[0]), .B(_02_), .C(_03_), .Y(_04_) ); INVX1 _40_ ( .A(sel[0]), .Y(_05_) ); INVX1 _41_ ( .A(y[0]), .Y(_06_) ); NAND3X1 _42_ ( .A(sel[1]), .B(_05_), .C(_06_), .Y(_07_) ); AOI22X1 _43_ ( .A(_02_), .B(sel[0]), .C(_07_), .D(_04_), .Y(_08_) ); AOI21X1 _44_ ( .A(sel[0]), .B(x[0]), .C(sel[1]), .Y(_09_) ); OAI21X1 _45_ ( .A(_09_), .B(_08_), .C(_01_), .Y(output2[0]) ); NAND2X1 _46_ ( .A(w[1]), .B(_00_), .Y(_10_) ); INVX1 _47_ ( .A(z[1]), .Y(_11_) ); NAND2X1 _48_ ( .A(sel[0]), .B(_02_), .Y(_12_) ); NAND2X1 _49_ ( .A(sel[1]), .B(_05_), .Y(_13_) ); NAND3X1 _50_ ( .A(_11_), .B(_12_), .C(_13_), .Y(_14_) ); INVX1 _51_ ( .A(y[1]), .Y(_15_) ); NAND3X1 _52_ ( .A(sel[1]), .B(_05_), .C(_15_), .Y(_16_) ); INVX1 _53_ ( .A(x[1]), .Y(_17_) ); OAI21X1 _54_ ( .A(_05_), .B(_17_), .C(_02_), .Y(_18_) ); NAND3X1 _55_ ( .A(_16_), .B(_18_), .C(_14_), .Y(_19_) ); NAND2X1 _56_ ( .A(_10_), .B(_19_), .Y(output2[1]) ); NAND2X1 _57_ ( .A(w[2]), .B(_00_), .Y(_20_) ); INVX1 _58_ ( .A(z[2]), .Y(_21_) ); NAND3X1 _59_ ( .A(_21_), .B(_12_), .C(_13_), .Y(_22_) ); INVX1 _60_ ( .A(y[2]), .Y(_23_) ); NAND3X1 _61_ ( .A(sel[1]), .B(_05_), .C(_23_), .Y(_24_) ); INVX1 _62_ ( .A(x[2]), .Y(_25_) ); OAI21X1 _63_ ( .A(_05_), .B(_25_), .C(_02_), .Y(_26_) ); NAND3X1 _64_ ( .A(_24_), .B(_26_), .C(_22_), .Y(_27_) ); NAND2X1 _65_ ( .A(_20_), .B(_27_), .Y(output2[2]) ); NAND2X1 _66_ ( .A(w[3]), .B(_00_), .Y(_28_) ); INVX1 _67_ ( .A(z[3]), .Y(_29_) ); NAND3X1 _68_ ( .A(_29_), .B(_12_), .C(_13_), .Y(_30_) ); INVX1 _69_ ( .A(y[3]), .Y(_31_) ); NAND3X1 _70_ ( .A(sel[1]), .B(_05_), .C(_31_), .Y(_32_) ); INVX1 _71_ ( .A(x[3]), .Y(_33_) ); OAI21X1 _72_ ( .A(_05_), .B(_33_), .C(_02_), .Y(_34_) ); NAND3X1 _73_ ( .A(_32_), .B(_34_), .C(_30_), .Y(_35_) ); NAND2X1 _74_ ( .A(_28_), .B(_35_), .Y(output2[3]) ); NOR2X1 _75_ ( .A(sel[1]), .B(sel[0]), .Y(_00_) );endmodule
|
#include <bits/stdc++.h> using namespace std; long long inf = 2147483647; const long long ll = 9223372036854775807, ninf = 1000000000; const double eps = 1e-6; const long long nll = 1000000000000000000; class MulticoreProcessingEasy { public: int fastestTime(int jobLength, int corePenalty, vector<int> speed, vector<int> cores) {} }; int main() { int a; while (cin >> a) { int A[100005] = {}; for (int i = 1; i <= a; i++) cin >> A[i]; int no = 0; for (int i = 1; i <= a; i++) { if (A[i] != A[A[i]]) { no = 1; } } if (no) { cout << -1 << n ; continue; } int b[100005] = {}; int c[100005] = {}; int vis[100005] = {}; int now = 0; for (int i = 1; i <= a; i++) { if (!vis[A[i]]) { now++; vis[A[i]] = now; c[now] = A[i]; } b[i] = vis[A[i]]; } cout << now << n ; for (int i = 1; i <= a; i++) cout << b[i] << ; cout << n ; for (int i = 1; i <= now; i++) cout << c[i] << ; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( Ofast,unroll-loops ) const long long int MAXN = 4e3 + 20, md = 1e9 + 7, inf = 5e18; int dp[MAXN][100][100], a[MAXN], ps[MAXN], sp[MAXN]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); memset(dp, -63, sizeof(dp)); long long int n, sq; cin >> n >> a[0]; ps[0] = a[0]; sq = ceil(sqrt(2 * n)); for (int i = 1; i < n; i++) { cin >> a[i]; ps[i] = ps[i - 1] + a[i]; } sp[n - 1] = a[n - 1]; for (int i = n - 2; i >= 0; i--) { sp[i] = sp[i + 1] + a[i]; } if (n == 1) { cout << a[0] << n ; return 0; } if (n == 2) { cout << a[0] + abs(a[1]) << n ; return 0; } if (n == 3) { int h = a[0] + a[1], q; q = -a[2] - abs(a[1]); cout << max(h, q + a[0]) << n ; return 0; } for (int i = n / 2 - 1; i >= 0; i--) { for (int k = 1; k <= sq; k++) { for (int j = 0; j <= k; j++) { int l = i, r = n - l - j - 1, h1, h2; if (r <= l) break; l += k; r -= k; if (r <= l) { r += k; if (l < r) { h1 = ps[l] - sp[r]; } else { l -= k; dp[i][k][j] = ps[l] - sp[r]; continue; } } else { h1 = dp[l][k][j]; r--; if (l < r) { h1 = min(h1, dp[l][k + 1][j + 1]); } } l = i; r = n - l - j - 1; l += k + 1; r -= k + 1; if (r <= l) { r += k + 1; if (l < r) { h2 = ps[l] - sp[r]; } else { dp[i][k][j] = h1; continue; } } else { h2 = dp[l][k + 1][j]; r--; if (l < r) { h2 = min(h2, dp[l][k + 2][j + 1]); } } dp[i][k][j] = max(h1, h2); } } } int h1 = min(dp[1][2][0], (dp[1][3][1] < -1e6 ? 500000000 : dp[1][3][1])), h2 = min(dp[0][1][0], dp[0][2][1]); cout << max(h1, h2) << n ; return 0; } |
module decoder ( cx, d );
input [8:0] cx;
output [2:0] d;
wire n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154,
n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165,
n166, n167, n168, n169, n170;
MUX2X1 U47 ( .B(n133), .A(n134), .S(cx[2]), .Y(d[2]) );
NOR2X1 U48 ( .A(n135), .B(n136), .Y(n134) );
INVX1 U49 ( .A(n137), .Y(n135) );
MUX2X1 U50 ( .B(n137), .A(n138), .S(cx[1]), .Y(d[1]) );
NOR2X1 U51 ( .A(n139), .B(n136), .Y(n138) );
NAND2X1 U52 ( .A(n140), .B(n141), .Y(n136) );
INVX1 U53 ( .A(n142), .Y(n140) );
MUX2X1 U54 ( .B(n141), .A(n143), .S(cx[0]), .Y(d[0]) );
NOR2X1 U55 ( .A(n142), .B(n144), .Y(n143) );
NAND2X1 U56 ( .A(n137), .B(n133), .Y(n144) );
INVX1 U57 ( .A(n139), .Y(n133) );
NOR2X1 U58 ( .A(n145), .B(n146), .Y(n139) );
NAND3X1 U59 ( .A(n147), .B(cx[6]), .C(n148), .Y(n146) );
NAND3X1 U60 ( .A(n149), .B(n150), .C(n151), .Y(n145) );
NAND3X1 U61 ( .A(n147), .B(n152), .C(n153), .Y(n137) );
NOR2X1 U62 ( .A(n149), .B(n154), .Y(n153) );
NAND2X1 U63 ( .A(n150), .B(n155), .Y(n154) );
INVX1 U64 ( .A(n156), .Y(n150) );
NAND3X1 U65 ( .A(n157), .B(n158), .C(n159), .Y(n142) );
INVX1 U66 ( .A(n160), .Y(n159) );
OAI21X1 U67 ( .A(n152), .B(cx[6]), .C(n147), .Y(n160) );
NOR2X1 U68 ( .A(n161), .B(n148), .Y(n152) );
MUX2X1 U69 ( .B(n162), .A(n163), .S(n149), .Y(n158) );
INVX1 U70 ( .A(n164), .Y(n149) );
NOR2X1 U71 ( .A(n156), .B(n155), .Y(n162) );
INVX1 U72 ( .A(cx[6]), .Y(n155) );
MUX2X1 U73 ( .B(n156), .A(n148), .S(n161), .Y(n157) );
OR2X1 U74 ( .A(n165), .B(n166), .Y(n141) );
NAND3X1 U75 ( .A(n147), .B(n156), .C(cx[6]), .Y(n166) );
XNOR2X1 U76 ( .A(cx[0]), .B(n167), .Y(n156) );
XOR2X1 U77 ( .A(cx[4]), .B(cx[1]), .Y(n167) );
XNOR2X1 U78 ( .A(cx[0]), .B(n168), .Y(n147) );
XOR2X1 U79 ( .A(cx[5]), .B(cx[2]), .Y(n168) );
NAND3X1 U80 ( .A(n161), .B(n163), .C(n164), .Y(n165) );
XNOR2X1 U81 ( .A(cx[0]), .B(cx[8]), .Y(n164) );
INVX1 U82 ( .A(n148), .Y(n163) );
XOR2X1 U83 ( .A(n169), .B(n170), .Y(n148) );
XOR2X1 U84 ( .A(cx[7]), .B(cx[2]), .Y(n170) );
INVX1 U85 ( .A(cx[1]), .Y(n169) );
INVX1 U86 ( .A(n151), .Y(n161) );
XNOR2X1 U87 ( .A(cx[2]), .B(cx[3]), .Y(n151) );
endmodule
|
// Automatically generated: write_netlist -wrapapp -verilog -module reconflogic-wrapmax6682mean.v
module MyReconfigLogic (
input Reset_n_i,
input Clk_i,
input AdcConvComplete_i,
output AdcDoConvert_o,
input[9:0] AdcValue_i,
input I2C_Busy_i,
output[7:0] I2C_DataIn_o,
input[7:0] I2C_DataOut_i,
output[15:0] I2C_Divider800_o,
output I2C_ErrAckParam_o,
input I2C_Error_i,
output I2C_F100_400_n_o,
input I2C_FIFOEmpty_i,
input I2C_FIFOFull_i,
output I2C_FIFOReadNext_o,
output I2C_FIFOWrite_o,
output[3:0] I2C_ReadCount_o,
output I2C_ReceiveSend_n_o,
output I2C_StartProcess_o,
input[7:0] Inputs_i,
output[7:0] Outputs_o,
output[4:0] ReconfModuleIRQs_o,
output SPI_CPHA_o,
output SPI_CPOL_o,
output[7:0] SPI_DataIn_o,
input[7:0] SPI_DataOut_i,
input SPI_FIFOEmpty_i,
input SPI_FIFOFull_i,
output SPI_LSBFE_o,
output SPI_ReadNext_o,
output[7:0] SPI_SPPR_SPR_o,
input SPI_Transmission_i,
output SPI_Write_o,
input[7:0] ReconfModuleIn_i,
output[7:0] ReconfModuleOut_o,
input[7:0] I2C_Errors_i,
input[13:0] PerAddr_i,
input[15:0] PerDIn_i,
input[1:0] PerWr_i,
input PerEn_i,
output[15:0] CfgIntfDOut_o,
output[15:0] ParamIntfDOut_o
);
wire [15:0] PauseCounterPreset_s;
wire [15:0] PeriodCounterPresetH_s;
wire [15:0] PeriodCounterPresetL_s;
wire [15:0] SensorValue_s;
wire [15:0] Threshold_s;
wire [0:0] CfgClk_s;
wire CfgMode_s;
wire [0:0] CfgShift_s;
wire CfgDataOut_s;
wire [0:0] CfgDataIn_s;
wire [2:0] ParamWrAddr_s;
wire [15:0] ParamWrData_s;
wire ParamWr_s;
wire [0:0] ParamRdAddr_s;
wire [15:0] ParamRdData_s;
TODO: implement
wire Params_s;
wire [0:0] I2C_ErrAckParam_s;
wire ParamI2C_Divider800Enable_s;
wire ParamI2C_ErrAckParamEnable_s;
wire ParamPauseCounterPresetEnable_s;
wire ParamPeriodCounterPresetHEnable_s;
wire ParamPeriodCounterPresetLEnable_s;
wire ParamThresholdEnable_s;
// Configuration Interface
CfgIntf #(
.BaseAddr('h0180),
.NumCfgs(1)
) CfgIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(CfgIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.CfgClk_o(CfgClk_s),
.CfgMode_o(CfgMode_s),
.CfgShift_o(CfgShift_s),
.CfgDataOut_o(CfgDataOut_s),
.CfgDataIn_i(CfgDataIn_s)
);
// Parameterization Interface: 6 write addresses, 2 read addresses
ParamIntf #(
.BaseAddr('h0188),
.WrAddrWidth(3),
.RdAddrWidth(1)
) ParamIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(ParamIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.ParamWrAddr_o(ParamWrAddr_s),
.ParamWrData_o(ParamWrData_s),
.ParamWr_o(ParamWr_s),
.ParamRdAddr_o(ParamRdAddr_s),
.ParamRdData_i(ParamRdData_s)
);
MAX6682Mean MAX6682Mean_0 (
.MAX6682CS_n_o(Outputs_o[0]),
.CpuIntr_o(ReconfModuleIRQs_o[0]),
.SPI_Data_o(SPI_DataIn_o),
.SPI_Data_i(SPI_DataOut_i),
.SPI_FIFOEmpty_i(SPI_FIFOEmpty_i),
.SPI_FIFOFull_i(SPI_FIFOFull_i),
.SPI_ReadNext_o(SPI_ReadNext_o),
.SPI_Transmission_i(SPI_Transmission_i),
.SPI_Write_o(SPI_Write_o),
.Enable_i(ReconfModuleIn_i[0]),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i),
.PauseCounterPreset_i(PauseCounterPreset_s),
.PeriodCounterPresetH_i(PeriodCounterPresetH_s),
.PeriodCounterPresetL_i(PeriodCounterPresetL_s),
.SensorValue_o(SensorValue_s),
.Threshold_i(Threshold_s)
);
assign AdcDoConvert_o = 1'b0;
assign I2C_DataIn_o = 8'b00000000;
assign I2C_F100_400_n_o = 1'b0;
assign I2C_FIFOReadNext_o = 1'b0;
assign I2C_FIFOWrite_o = 1'b0;
assign I2C_ReadCount_o = 4'b0000;
assign I2C_ReceiveSend_n_o = 1'b0;
assign I2C_StartProcess_o = 1'b0;
assign Outputs_o[1] = 1'b0;
assign Outputs_o[2] = 1'b0;
assign Outputs_o[3] = 1'b0;
assign Outputs_o[4] = 1'b0;
assign Outputs_o[5] = 1'b0;
assign Outputs_o[6] = 1'b0;
assign Outputs_o[7] = 1'b0;
assign ReconfModuleIRQs_o[1] = 1'b0;
assign ReconfModuleIRQs_o[2] = 1'b0;
assign ReconfModuleIRQs_o[3] = 1'b0;
assign ReconfModuleIRQs_o[4] = 1'b0;
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_LSBFE_o = 1'b0;
assign SPI_SPPR_SPR_o = 8'b00000000;
assign ReconfModuleOut_o[0] = 1'b0;
assign ReconfModuleOut_o[1] = 1'b0;
assign ReconfModuleOut_o[2] = 1'b0;
assign ReconfModuleOut_o[3] = 1'b0;
assign ReconfModuleOut_o[4] = 1'b0;
assign ReconfModuleOut_o[5] = 1'b0;
assign ReconfModuleOut_o[6] = 1'b0;
assign ReconfModuleOut_o[7] = 1'b0;
/* just a fixed value for the config interface */
assign CfgDataIn_s = 1'b0;
/* Param read address decoder
Synthesis: Accept undefined behavior if ParamRdAddr_s >= NumParams and
hope that the synthesis optimizes the MUX
Simulation: ModelSim complains "Fatal: (vsim-3421) Value x is out of range
0 to n.", even during param write cycles, because ParamRdAddr has the
source as ParamWrAddr. Use the parameter "-noindexcheck" during
compilation ("vcom"). Simulation works fine then, but ModelSim generates
numerous "INTERNAL ERROR"s to stdout, which seem harmless. */
assign ParamRdData_s = Params_s[to_integer(unsigned(ParamRdAddr_s))];
ParamOutReg #(
.Width(16)
) ParamOutReg_I2C_Divider800 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_Divider800_o),
.Enable_i(ParamI2C_Divider800Enable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(1)
) ParamOutReg_I2C_ErrAckParam (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_ErrAckParam_s),
.Enable_i(ParamI2C_ErrAckParamEnable_s),
.ParamWrData_i(ParamWrData_s[0:0])
);
ParamOutReg #(
.Width(16)
) ParamOutReg_PauseCounterPreset (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(PauseCounterPreset_s),
.Enable_i(ParamPauseCounterPresetEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_PeriodCounterPresetH (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(PeriodCounterPresetH_s),
.Enable_i(ParamPeriodCounterPresetHEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_PeriodCounterPresetL (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(PeriodCounterPresetL_s),
.Enable_i(ParamPeriodCounterPresetLEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_Threshold (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(Threshold_s),
.Enable_i(ParamThresholdEnable_s),
.ParamWrData_i(ParamWrData_s)
);
assign I2C_ErrAckParam_o = I2C_ErrAckParam_s[0];
/* Address $00 */
assign Params_s[0] = { 8'b00000000, I2C_Errors_i };
/* Address $01 */
assign Params_s[1] = SensorValue_s;
/* Address $00 */
assign ParamI2C_Divider800Enable_s = TODO: implement;
/* Address $01 */
assign ParamI2C_ErrAckParamEnable_s = TODO: implement;
/* Address $02 */
assign ParamPauseCounterPresetEnable_s = TODO: implement;
/* Address $03 */
assign ParamPeriodCounterPresetHEnable_s = TODO: implement;
/* Address $04 */
assign ParamPeriodCounterPresetLEnable_s = TODO: implement;
/* Address $05 */
assign ParamThresholdEnable_s = TODO: implement;
endmodule
|
interface automodport_if
( input logic clk,
input logic rst_n
);
//----------------------------------------------------------------------------------------
// Group: Signals
logic req_val;
logic [63:0] req_dat;
logic req_credit;
logic [1:0] rsp_cmd;
logic [63:0] rsp_data;
logic rsp_credit;
logic in_pure;
logic out_pure;
logic manually_listed;
//----------------------------------------------------------------------------------------
// Group: Clocking blocks
clocking req_mon_cb @(posedge clk);
input rst_n;
input req_val;
input req_dat;
input req_credit;
input manually_listed;
endclocking : req_mon_cb
clocking rsp_drv_cb @(posedge clk);
input rst_n;
output rsp_cmd;
output rsp_data;
input rsp_credit;
endclocking : rsp_drv_cb
//----------------------------------------------------------------------------------------
// Group: Modports
modport req_mon_mp(clocking req_mon_cb);
modport rsp_drv_mp(clocking rsp_drv_cb, import rsp_reset);
modport pure_mp(input in_pure, output out_pure);
//----------------------------------------------------------------------------------------
// Group: Methods
function void rsp_reset();
rsp_cmd = 2'b0;
rsp_data = 64'b0;
endfunction : rsp_reset
//----------------------------------------------------------------------------------------
// Group: Assertions
logic [1:0] cmd_m1;
always @(posedge clk) begin
cmd_m1 <= rsp_cmd;
if(rst_n) begin
if($isunknown(req_val)) `cn_err_intf(("Signal req_data_cycle is an X."));
if(req_val==1'b1 & $isunknown(req_data)) `cn_err_intf(("Signal req_data is an X."));
if($isunknown(req_credit)) `cn_err_intf(("Signal req_credit is an X."));
if($isunknown(rsp_cmd)) `cn_err_intf(("Signal rsp_cmd is an X."));
if(cmd_m1!=2'b0 & $isunknown(rsp_data)) `cn_err_intf(("Signal rsp_data is an X."));
if($isunknown(rsp_credit)) `cn_err_intf(("Signal rsp_credit is an X."));
end
end
endinterface
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MX = 6; int n, Arr[6]; int solve(int rem, int mask) { if (mask == ((1 << MX) - 1)) return 0; int Ans = 50; for (int i = 0; i < MX; i++) { if (!(mask & (1 << i))) { if (rem < Arr[i]) Ans = min(Ans, 1 + solve(n - Arr[i], mask | (1 << i))); else Ans = min(Ans, solve(rem - Arr[i], mask | (1 << i))); } } return Ans; } int main() { scanf( %d %d %d , &n, &Arr[0], &Arr[2]); Arr[1] = Arr[3] = Arr[4] = Arr[0]; Arr[5] = Arr[2]; printf( %d n , solve(0, 0)); return 0; } |
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