text stringlengths 59 71.4k |
|---|
// Define an ALU with 16 functions
module alu (A, B, function_sel,
aluout, zero_flag, parity_flag, carry_flag);
// Define I/O for the ALU
output [15:0] aluout;
output zero_flag, parity_flag, carry_flag;
input [15:0] A, B;
input [3:0] function_sel;
reg [15:0] aluout;
reg zero_flag, parity_flag, carry_flag;
// Define text macros for ALU opcodes
`define move 4'b0000 /* aluout = B */
`define comp 4'b0001 /* aluout = bit-wise complement(B) */
`define and 4'b0010 /* aluout = A & B */
`define or 4'b0011 /* aluout = A | B */
`define xor 4'b0100 /* aluout = A ^ B */
`define add 4'b0101 /* aluout = A + B */
`define incr 4'b0110 /* aluout = B + 1 */
`define sub 4'b0111 /* aluout = A - B */
`define rotl 4'b1000 /* aluout = rotate B left one bit */
`define lshl 4'b1001 /* aluout = logical shift B left one bit, zero fill */
`define rotr 4'b1010 /* aluout = rotate B right one bit */
`define lshr 4'b1011 /* aluout = logical shift B right one bit, zero fill */
`define xnor 4'b1100 /* aluout = A ~^ B */
`define nor 4'b1101 /* aluout = ~(A | B) */
`define decr 4'b1110 /* aluout = B - 1 */
`define nand 4'b1111 /* aluout = ~(A & B) */
always @(A or B or function_sel)
begin
case (function_sel)
`move : {carry_flag, aluout} = {1'b0, B};
`comp : {carry_flag, aluout} = {1'b1, ~B};
`and : {carry_flag, aluout} = {1'b0, A & B};
`or : {carry_flag, aluout} = {1'b0, A | B};
`xor : {carry_flag, aluout} = {1'b0, A ^ B};
`add : {carry_flag, aluout} = A + B;
`incr : {carry_flag, aluout} = B + 1;
`sub : {carry_flag, aluout} = {1'b1, A} - B;
`rotl : {carry_flag, aluout} = {B[15:0], B[15]};
`lshl : {carry_flag, aluout} = {B[15:0], 1'b0};
`rotr : {carry_flag, aluout} = {B[0], B[0], B[15:1]};
`lshr : {carry_flag, aluout} = {2'b0, B[15:1]};
`xnor : {carry_flag, aluout} = {1'b1, A ~^ B};
`nor : {carry_flag, aluout} = {1'b1, ~(A | B)};
`decr : {carry_flag, aluout} = B - 1;
`nand : {carry_flag, aluout} = {1'b1, ~(A & B)};
endcase
zero_flag = ~|aluout;
parity_flag = ^aluout;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_P_TB_V
`define SKY130_FD_SC_HDLL__UDP_DFF_P_TB_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__udp_dff_p.v"
module top();
// Inputs are registered
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
#20 D = 1'b0;
#40 D = 1'b1;
#60 D = 1'b0;
#80 D = 1'b1;
#100 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hdll__udp_dff$P dut (.D(D), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_P_TB_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 00:44:28 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_rgb888_to_g8_0_0 -prefix
// system_rgb888_to_g8_0_0_ system_rgb888_to_g8_0_0_stub.v
// Design : system_rgb888_to_g8_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb888_to_g8,Vivado 2016.4" *)
module system_rgb888_to_g8_0_0(clk, rgb888, g8)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb888[23:0],g8[7:0]" */;
input clk;
input [23:0]rgb888;
output [7:0]g8;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; long long n, s, e, x[5001], a[5001], b[5001], c[5001], d[5001]; long long dp[5001][5001], ans = INF; void init() { for (int i = 0; i < 5001; i++) for (int j = 0; j < 5001; j++) dp[i][j] = INF; cin >> n >> s >> e; for (int i = 1; i < n + 1; i++) cin >> x[i]; for (int i = 1; i < n + 1; i++) cin >> a[i]; for (int i = 1; i < n + 1; i++) cin >> b[i]; for (int i = 1; i < n + 1; i++) cin >> c[i]; for (int i = 1; i < n + 1; i++) cin >> d[i]; } long long solve() { for (int i = 0; i < 5001; i++) for (int j = 0; j < 5001; j++) dp[i][j] = INF; dp[0][0] = 0; for (int i = 1; i < n + 1; i++) for (int j = 0; j < 5001; j++) { if (i != n && j == 0) continue; if (i == s) { dp[i][j] = min(dp[i][j], dp[i - 1][j + 1] + x[i] + c[i]); dp[i][j] = min(dp[i][j], dp[i - 1][j - 1] - x[i] + d[i]); } else if (i == e) { dp[i][j] = min(dp[i][j], dp[i - 1][j - 1] + b[i] - x[i]); dp[i][j] = min(dp[i][j], dp[i - 1][j + 1] + a[i] + x[i]); } else { if (j >= 2) dp[i][j] = min(dp[i][j], dp[i - 1][j - 2] + b[i] + d[i] - 2 * x[i]); if (j > 1 || s < e) dp[i][j] = min(dp[i][j], dp[i - 1][j] + a[i] + d[i]); if (j > 1 || s > e) dp[i][j] = min(dp[i][j], dp[i - 1][j] + c[i] + b[i]); if (j + 2 <= 5000) dp[i][j] = min(dp[i][j], dp[i - 1][j + 2] + a[i] + c[i] + 2 * x[i]); } } return dp[n][0]; } int main() { init(); ans = min(ans, solve()); cout << ans; } |
#include <bits/stdc++.h> const int kMaxN = 5000; std::vector<int> way[kMaxN], cost[kMaxN]; int f[kMaxN], c[kMaxN]; short hash[kMaxN][kMaxN], father[kMaxN][2 * kMaxN]; int a[kMaxN], id[kMaxN], t[kMaxN]; inline bool cmp(int x, int y) { return a[x] < a[y]; } void BuildTree(int u, int ff) { f[u] = ff; for (size_t i = 0; i < way[u].size(); ++i) { int v = way[u][i]; if (v == ff) continue; c[v] = cost[u][i]; BuildTree(v, u); } } int Find(short *f, int x) { int y = x, z; while (f[y] != -1) y = f[y]; while (x != y) { z = x; x = f[x]; f[z] = y; } return y; } int Put(int x) { int t = 0; while (x != 0) { ++t; if (f[x] == 0) return t; int ff = f[x]; t = Find(father[ff], t); if (++hash[ff][t] == c[ff]) { father[ff][t] = t + 1; } x = ff; } return 0; } int main() { int n, x, y, cc; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d , a + i); id[i] = i; } std::sort(id, id + n, cmp); for (int j = 1; j < n; ++j) { scanf( %d%d%d , &x, &y, &cc); --x; --y; way[x].push_back(y); way[y].push_back(x); cost[x].push_back(cc); cost[y].push_back(cc); } BuildTree(0, -1); memset(father, -1, sizeof(father)); for (int i = 0; i < n; ++i) { t[id[i]] = Put(id[i]); } for (int i = 0; i < n; ++i) { if (i != 0) printf( ); printf( %d , t[i]); } puts( ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRBP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFRBP_PP_BLACKBOX_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRBP_PP_BLACKBOX_V
|
/*
output: sqrt(x1^2 + x2^2)
*/
/*
sqrt #(16) instance_name(clock_input, first_signed_input, second_signed_input, unsigned_output);
*/
module sqrt
#(parameter DATA_IN_WIDTH = 16)
(
input wire clk,
input wire signed [ DATA_IN_WIDTH-1: 0 ] x1,
input wire signed [ DATA_IN_WIDTH-1: 0 ] x2,
output wire [ DATA_IN_WIDTH-1: 0 ] y
);
localparam DATA_WIDTH_SQUARING = (2*DATA_IN_WIDTH) - 1;
wire [ DATA_WIDTH_SQUARING-1 : 0 ] x1_2 = x1*x1;
wire [ DATA_WIDTH_SQUARING-1 : 0 ] x2_2 = x2*x2;
localparam DATA_WIDTH_SUM = DATA_WIDTH_SQUARING+1;
wire [ DATA_WIDTH_SUM-1 : 0 ] x = x1_2 + x2_2;
assign y[DATA_IN_WIDTH-1] = x[(DATA_WIDTH_SUM-1)-:2] == 2'b00 ? 1'b0 : 1'b1;
genvar k;
generate
for(k = DATA_IN_WIDTH-2; k >= 0; k = k - 1)
begin: gen
assign y[k] = x[(DATA_WIDTH_SUM-1)-:(2*(DATA_IN_WIDTH-k))] <
{y[DATA_IN_WIDTH-1:k+1],1'b1}*{y[DATA_IN_WIDTH-1:k+1],1'b1} ? 1'b0 : 1'b1;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) #pragma GCC optimize( unroll-loops ) using namespace std; const long double eps = 1e-7; const int inf = 1000000010; const long long INF = 10000000000000010LL; const int mod = 1000000007; const int MAXN = 100010, LOG = 20; int n, m, k, q, u, v, x, y, t, a, b, ans; int stt[MAXN], fnt[MAXN], ras[MAXN], timer = 1; int sz[MAXN], par[MAXN], head[MAXN], h[MAXN]; long long fen[MAXN]; pair<long long, int> seg[MAXN << 2]; long long lazy[MAXN << 2]; set<int> st[MAXN]; vector<int> G[MAXN]; void add(int pos, long long val) { for (; pos < MAXN; pos += pos & -pos) fen[pos] += val; } long long get(int pos) { long long res = 0; for (; pos; pos -= pos & -pos) res += fen[pos]; return res; } int dfs1(int node) { h[node] = h[par[node]] + 1; for (int v : G[node]) if (v != par[node]) { par[v] = node; sz[node] += dfs1(v); } return ++sz[node]; } void dfs2(int node, int hd) { head[node] = hd; stt[node] = timer++; ras[stt[node]] = node; int big = 0; for (int v : G[node]) if (v != par[node] && sz[v] > sz[big]) big = v; if (big) dfs2(big, hd); for (int v : G[node]) if (v != par[node] && v != big) dfs2(v, v); fnt[node] = timer; } pair<long long, int> Build(int id, int tl, int tr) { if (tr - tl == 1) return seg[id] = {INF, ras[tl]}; int mid = (tl + tr) >> 1; return seg[id] = min(Build(id << 1, tl, mid), Build(id << 1 | 1, mid, tr)); } void add_lazy(int id, long long val) { seg[id].first += val; lazy[id] += val; } void shift(int id) { if (!lazy[id]) return; add_lazy(id << 1, lazy[id]); add_lazy(id << 1 | 1, lazy[id]); lazy[id] = 0; } void Add(int id, int tl, int tr, int l, int r, long long val) { if (r <= tl || tr <= l) return; if (l <= tl && tr <= r) { add_lazy(id, val); return; } shift(id); int mid = (tl + tr) >> 1; Add(id << 1, tl, mid, l, r, val); Add(id << 1 | 1, mid, tr, l, r, val); seg[id] = min(seg[id << 1], seg[id << 1 | 1]); } pair<long long, int> Get(int id, int tl, int tr, int l, int r) { if (r <= tl || tr <= l) return seg[0]; if (l <= tl && tr <= r) return seg[id]; shift(id); int mid = (tl + tr) >> 1; return min(Get(id << 1, tl, mid, l, r), Get(id << 1 | 1, mid, tr, l, r)); } void Set(int id, int tl, int tr, int pos, long long val) { if (pos < tl || tr <= pos) return; if (tr - tl == 1) { seg[id].first = val; return; } shift(id); int mid = (tl + tr) >> 1; Set(id << 1, tl, mid, pos, val); Set(id << 1 | 1, mid, tr, pos, val); seg[id] = min(seg[id << 1], seg[id << 1 | 1]); } pair<long long, int> GetPath(int u, int v) { pair<long long, int> res = {INF, -1}; while (head[u] != head[v]) { if (h[head[u]] > h[head[v]]) swap(u, v); res = min(res, Get(1, 1, n + 1, stt[head[v]], stt[v] + 1)); v = par[head[v]]; } if (h[u] > h[v]) swap(u, v); res = min(res, Get(1, 1, n + 1, stt[u], stt[v] + 1)); return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m >> q; for (int i = 1; i < n; i++) { cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } for (int i = 1; i <= m; i++) cin >> x, st[x].insert(i); dfs1(1); dfs2(1, 1); Build(1, 1, n + 1); seg[0] = {INF, 0}; for (int i = 1; i <= n; i++) if (st[i].size()) Set(1, 1, n + 1, stt[i], *st[i].begin()); while (q--) { cin >> t; if (t == 2) { cin >> v >> x; Add(1, 1, n + 1, stt[v], fnt[v], x); add(stt[v], +x); add(fnt[v], -x); continue; } vector<int> out; cin >> u >> v >> k; while (k--) { pair<long long, int> p = GetPath(u, v); if (p.first >= INF) break; int v = p.second, id = *st[v].begin(); out.push_back(id); st[v].erase(id); if (st[v].empty()) Set(1, 1, n + 1, stt[v], INF); else Set(1, 1, n + 1, stt[v], *st[v].begin() + get(stt[v])); } cout << out.size() << ; for (int i : out) cout << i << ; cout << n ; } return 0; } |
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
// IP Revision: 8
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module MSPAC_DROM (
a,
spo
);
input wire [13 : 0] a;
output wire [7 : 0] spo;
dist_mem_gen_v8_0 #(
.C_FAMILY("zynq"),
.C_ADDR_WIDTH(14),
.C_DEFAULT_DATA("0"),
.C_DEPTH(16384),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_WE(0),
.C_MEM_INIT_FILE("MSPAC_DROM.mif"),
.C_ELABORATION_DIR("./"),
.C_MEM_TYPE(0),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(8),
.C_PARSER_TYPE(1)
) inst (
.a(a),
.d(8'B0),
.dpra(14'B0),
.clk(1'D0),
.we(1'D0),
.i_ce(1'D1),
.qspo_ce(1'D1),
.qdpo_ce(1'D1),
.qdpo_clk(1'D0),
.qspo_rst(1'D0),
.qdpo_rst(1'D0),
.qspo_srst(1'D0),
.qdpo_srst(1'D0),
.spo(spo),
.dpo(),
.qspo(),
.qdpo()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); struct Point { double x, y; Point(double x = 0, double y = 0) : x(x), y(y) {} }; Point operator+(Point a, Point b) { return Point(a.x + b.x, a.y + b.y); } Point operator-(Point a, Point b) { return Point(a.x - b.x, a.y - b.y); } Point operator*(Point a, double p) { return Point(a.x * p, a.y * p); } Point operator/(Point a, double p) { return a * (1 / p); } bool operator<(const Point& a, const Point& b) { return a.x < b.x || (a.x == b.x && a.y < b.y); } const double EPS = 1e-10; int dcmp(double x) { if (fabs(x) < EPS) return 0; else return x < 0 ? -1 : 1; } bool operator==(const Point& a, const Point& b) { return dcmp(a.x - b.x) == 0 && dcmp(a.y - b.y) == 0; } double ang(Point v) { return atan2(v.y, v.x); } double Dot(Point A, Point B) { return A.x * B.x + A.y * B.y; } double Length(Point A) { return sqrt(Dot(A, A)); } double Angle(Point A, Point B) { return acos(Dot(A, B) / Length(A) / Length(B)); } double Cross(Point A, Point B) { return A.x * B.y - A.y * B.x; } Point CirCenter(Point a, Point b, Point c) { double a1 = b.x - a.x, b1 = b.y - a.y, c1 = (a1 * a1 + b1 * b1) / 2; double a2 = c.x - a.x, b2 = c.y - a.y, c2 = (a2 * a2 + b2 * b2) / 2; double d = a1 * b2 - a2 * b1; return Point(a.x + (c1 * b2 - c2 * b1) / d, a.y + (a1 * c2 - a2 * c1) / d); } vector<Point> ConvexHull(vector<Point> p) { sort(p.begin(), p.end()); p.erase(unique(p.begin(), p.end()), p.end()); int n = p.size(); vector<Point> ch(n + 1); int m = 0; for (int i = 0; i < n; i++) { while (m > 1 && dcmp(Cross(ch[m - 1] - ch[m - 2], p[i] - ch[m - 2])) <= 0) m--; ch[m++] = p[i]; } int k = m; for (int i = n - 2; i >= 0; i--) { while (m > k && dcmp(Cross(ch[m - 1] - ch[m - 2], p[i] - ch[m - 2])) <= 0) m--; ch[m++] = p[i]; } if (n > 1) m--; ch.resize(m); return ch; } bool judge(const vector<Point>& a, const vector<Point>& b, int i, int j) { double minr = -DBL_MAX, maxr = DBL_MAX; int mid = -1; int na = a.size(), nb = b.size(); bool flag = true; for (int k = i + 1; k < j; k++) { if (dcmp(Cross(a[k] - a[i], a[k] - a[j])) == 0) { flag = false; break; } Point center = CirCenter(a[i], a[j], a[k]); double r = Length(center - (a[i] + a[j]) / 2.0); if (dcmp(Cross(center - a[i], a[j] - a[i])) * dcmp(Cross(a[k] - a[i], a[j] - a[i])) < 0) r = -r; if (dcmp(r - minr) > 0) minr = r, mid = k; } if (flag) { for (int k = (j + 1) % na;; k = (k + 1) % na) { if (k == i) break; if (dcmp(Cross(a[k] - a[i], a[k] - a[j])) == 0) { flag = false; break; } Point center = CirCenter(a[i], a[j], a[k]); double r = Length(center - (a[i] + a[j]) / 2.0); if (dcmp(Cross(center - a[i], a[j] - a[i])) * dcmp(Cross(a[k] - a[i], a[j] - a[i])) > 0) r = -r; if (dcmp(r - maxr) < 0) maxr = r; } } bool ok = true; if (flag) { for (int k = 0; k < nb; k++) { if (dcmp(Cross(b[k] - a[i], a[j] - a[i])) == 0 && dcmp(Dot(a[i] - b[k], a[j] - b[k])) <= 0) { ok = false; break; } Point center = CirCenter(a[i], a[j], b[k]); double r = Length(center - (a[i] + a[j]) / 2.0); if (dcmp(Cross(center - a[i], a[j] - a[i])) * dcmp(Cross(b[k] - a[i], a[j] - a[i])) < 0) r = -r; if (dcmp(Cross(b[k] - a[i], a[j] - a[i])) > 0) { if (dcmp(r - maxr) < 0) maxr = r; } else if (dcmp(Cross(b[k] - a[i], a[j] - a[i])) < 0) { r = -r; if (dcmp(minr - r) < 0) minr = r; } if (dcmp(maxr - minr) <= 0) { ok = false; break; } } } else ok = false; return ok || (mid >= 0 && (judge(a, b, i, mid) || judge(a, b, mid, j))); } int n, m; int main() { scanf( %d%d , &n, &m); vector<Point> ina(n), inb(m); int x, y; for (int i = 0; i < n; i++) scanf( %d%d , &x, &y), ina[i].x = (double)x, ina[i].y = (double)y; for (int i = 0; i < m; i++) scanf( %d%d , &x, &y), inb[i].x = (double)x, inb[i].y = (double)y; vector<Point> a = ConvexHull(ina), b = ConvexHull(inb); puts((judge(a, inb, 0, a.size() - 1) || judge(b, ina, 0, b.size() - 1)) ? YES : NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> v; bool super(string s) { int sv = 0, f = 0; for (int i = 0; i < s.length(); ++i) { (s[i] == 7 ? sv += 1 : f += 1); } return (sv == f ? true : false); } long long strtoll(string s) { long long res = 0; for (int i = 0; i < s.length(); ++i) { res = res * 10 + (s[i] - 0 ); } return res; } void gennbrs(string s) { if (s.length() == 11) return; if (s != and super(s)) v.push_back(strtoll(s)); gennbrs(s + 4 ); gennbrs(s + 7 ); } int main() { gennbrs( ); sort(v.begin(), v.end()); int n; scanf( %d , &n); for (int i = 0; i < v.size(); ++i) { if (v[i] >= n) { cout << v[i] << endl; break; } } return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { node *bit[2]; int cnt = 0; int index = -1; }; node *root; void insert(string &s, int id) { node *cur = root; for (char x : s) { int ch = x - 0 ; if (!cur->bit[ch]) cur->bit[ch] = new node(); cur = cur->bit[ch]; cur->cnt++; } cur->index = id; } int already(string &s) { node *cur = root; for (char x : s) { int ch = x - 0 ; if (!cur->bit[ch]) return -1; else if (cur->bit[ch]->cnt < 1) return -1; cur = cur->bit[ch]; } return cur->index; } void remove(string &s) { node *cur = root; for (char x : s) { int ch = x - 0 ; cur = cur->bit[ch]; cur->cnt--; } cur->index = -1; } void test_case() { root = new node(); int n; cin >> n; int a[n]; vector<bool> can(n, true); int both_zero = 0, both_one = 0; for (int i = 0; i < n; i++) { string s; cin >> s; a[i] = (s[0] - 0 ) * 2 + (s.back() - 0 ); if (s[0] != s.back()) { int index = already(s); if (index != -1) { can[index] = false; can[i] = false; remove(s); } else { reverse(s.begin(), s.end()); insert(s, i); } } else { can[i] = false; } } vector<int> possible[2]; vector<int> type(4, 0); for (int i = 0; i < n; i++) { if (can[i] == true) { possible[a[i] - 1].push_back(i + 1); } else { type[a[i]]++; } } vector<int> ans[2]; vector<int> valid(2, true); for (int t = 0; t < 2; t++) { vector<int> cnt = type; vector<int> p[2]; p[0] = possible[0]; p[1] = possible[1]; int last = t; for (int i = 0; i < n; i++) { bool found = false; for (int j = 0; j < 4; j++) { if (last == j / 2 && cnt[j] > 0) { cnt[j]--; found = true; last = j % 2; break; } } if (found) continue; if (!p[last].empty()) { p[last].pop_back(); last = 1 - last; continue; } if (p[1 - last].empty()) { valid[t] = false; break; } ans[t].push_back(p[1 - last].back()); p[1 - last].pop_back(); last = 1 - last; } } if (valid[0] == false && valid[1] == false) { cout << -1 n ; return; } int id = 0; if (valid[0] == true && valid[1] == false) { id = 0; } else if (valid[0] == false && valid[1] == true) { id = 1; } else { if (ans[0].size() < ans[1].size()) id = 0; else id = 1; } cout << (int)ans[id].size() << n ; for (int i : ans[id]) cout << i << ; cout << n ; } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; cin >> t; while (t--) test_case(); } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1234567; const int MOD = 1e9 + 7; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); string s, a, t; cin >> s; vector<string> v; for (int i = 0; i < 10; i++) { cin >> a; v.push_back(a); } for (int i = 0; i < s.size(); i += 10) { t = s.substr(i, 10); for (int j = 0; j < 10; j++) if (v[j].compare(t) == 0) { cout << j; break; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, a[100001], b[100001]; void solve(int first) { vector<int> ans(1, first); for (int i = 1; i < n; i++) { int pre = ans.back(); for (int j = 0; j <= 3; j++) { if ((pre & j) == b[i] && (pre | j) == a[i]) { ans.push_back(j); break; } } } if (ans.size() != n) return; cout << YES n ; for (int x : ans) cout << x << ; exit(0); } int main() { cin >> n; for (int i = 1; i < n; i++) cin >> a[i]; for (int i = 1; i < n; i++) cin >> b[i]; for (int i = 0; i <= 3; i++) solve(i); cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, h, value, width = 0; vector<int> v; cin >> n; cin >> h; for (int i = 0; i < n; i++) { cin >> value; v.push_back(value); } for (int j = 0; j < v.size(); j++) { if (v[j] > h) width = width + 2; else width = width + 1; } cout << width; return 0; } |
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Simple/useful components
*
*/
//
// Register
//
/*module NW_reg (data_in, data_out, clk, rst_n);
parameter type reg_t = byte;
input reg_t data_in;
output reg_t data_out;
input clk, rst_n;
always@(posedge clk) begin
if (!rst_n) begin
data_out<='0;
end else begin
data_out<=data_in;
end
end
endmodule */ // NW_reg
//
// Multiplexer with one-hot encoded select input
//
// - output is '0 if no select input is asserted
//
module NW_mux_oh_select (data_in, select, data_out);
//parameter type dtype_t = byte;
parameter n = 4;
input fifo_elements_t data_in [n-1:0];
input [n-1:0] select;
output fifo_elements_t data_out;
int i;
always_comb
begin
data_out='0;
for (i=0; i<n; i++) begin
if (select[i]) data_out = data_in[i];
end
end
endmodule // NW_mux_oh_select
//
// Crossbar built from multiplexers, one-hot encoded select input
//
module NW_crossbar_oh_select (data_in, select, data_out);
//parameter type dtype_t = byte;
parameter n = 4;
input flit_t data_in [n-1:0];
// select[output][select-input];
input [n-1:0][n-1:0] select; // n one-hot encoded select signals per output
output flit_t data_out [n-1:0];
genvar i;
generate
for (i=0; i<n; i++) begin:outmuxes
NW_mux_oh_select #( .n(n)) xbarmux (data_in, select[i], data_out[i]);
end
endgenerate
endmodule // NW_crossbar_oh_select
|
#include <bits/stdc++.h> using namespace std; long long n, ti[2005], co[2005], dp[2005][2005], i, j; int main() { cin >> n; for (i = 1; i <= n; i++) { cin >> ti[i] >> co[i]; ti[i]++; } for (i = 0; i <= n; i++) { for (j = 1; j <= n; j++) dp[i][j] = 1e16; } for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { dp[i][j] = min(dp[i - 1][j], dp[i - 1][max(0ll, j - ti[i])] + co[i]); } } cout << dp[n][n]; return 0; } |
module m_tera;
// global section
// specify clock LOW and reset HIGH initial values
reg r_clock = 1'b0;
reg r_reset = 1'b1;
wire w_clock, w_reset;
assign w_clock = r_clock;
assign w_reset = r_reset;
// end global section
// program counter section
reg r_pc_demux_channel = 1'b0;
wire [7:0] w_bus_instr_mem_addr, w_bus_alu_out;
wire w_jump_flag;
m_program_counter pc (w_bus_instr_mem_addr, w_bus_alu_out, w_jump_flag, w_clock, w_reset);
// end program counter section
// memory section
wire [7:0] w_bus_instr_mem_word, w_bus_data_mem_word, w_bus_data_mem_addr, w_bus_high_register_value, w_bus_low_register_value;
wire w_data_mem_write_enable;
m_instruction_memory instr_mem (w_bus_instr_mem_word, w_bus_instr_mem_addr);
m_data_memory data_mem (w_bus_data_mem_word, w_bus_high_register_value, w_data_mem_write_enable, w_reset, w_clock);
// end memory section
// register file section
wire [7:0] w_bus_write_back_value;
wire [3:0] w_bus_write_back_reg;
wire w_write_back_flag;
m_register_file regfile (w_bus_high_register_value, w_bus_low_register_value, w_bus_instr_mem_word, w_bus_write_back_value, w_bus_write_back_reg, w_write_back_flag, w_clock, w_reset);
// end register file section
// instruction logic unit section
wire w_store_word_flag, w_store_pc_flag, w_load_word_flag, w_cf; // w_cf is comparison flag
m_instruction_logic_unit ilu (w_jump_flag, w_data_mem_write_enable, w_store_word_flag, w_store_pc_flag, w_load_word_flag, w_write_back_flag, w_bus_write_back_reg, w_bus_instr_mem_word, w_cf, w_clock);
// end instruction logic unit section
// arithmetic logic unit section
m_arithmetic_logic_unit alu (w_bus_alu_out, w_cf, w_bus_instr_mem_word, w_bus_high_register_value, w_bus_low_register_value, w_clock);
// end arithmetic logic unit section
// mux/demux section
wire [7:0] w_bus_demux_inter0, w_bus_mux_inter;
m_1to2_8bit_demux store_demux (w_bus_demux_inter0, w_bus_data_mem_word, w_bus_alu_out, w_store_word_flag);
m_2to1_8bit_mux load_mux (w_bus_mux_inter, w_bus_demux_inter0, w_bus_data_mem_word, w_load_word_flag);
m_2to1_8bit_mux_with_add1 pc_mux (w_bus_write_back_value, w_bus_mux_inter, w_bus_instr_mem_addr, w_store_pc_flag);
// end mux/demux section
initial begin
$dumpfile ("dumpfile.vcd");
$dumpvars (0, m_tera);
$display ("\nStarting program (Program Counter = 0).\n");
#2 r_reset = 1'b0;
end
always #1 begin
r_clock = ~w_clock; // send clock pulses
if (w_bus_instr_mem_addr == 8'b11111111) begin
$display ("\nReached EOF (Program Counter = 255). Closing program.\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; const int mod = 1e9 + 7; const double eps = 1e-8; const double PI = acos(-1.0); int a[N], l[N], r[N], d[N], cha[N]; int m, n, k, t; bool check(int x) { if (!x) return true; for (int i = 0; i <= n + 1; i++) cha[i] = 0; int g = a[x]; for (int i = 1; i <= k; i++) { if (d[i] > g) { cha[l[i]]++, cha[r[i] + 1]--; } } int res = 0; for (int i = 1; i <= n + 1; i++) { cha[i] += cha[i - 1]; if (cha[i] > 0) res++; } return res * 2 + n + 1 <= t; } int main() { std::ios::sync_with_stdio(false); cin >> m >> n >> k >> t; for (int i = 1; i <= m; i++) cin >> a[i]; sort(a + 1, a + 1 + m, greater<int>()); for (int i = 1; i <= k; i++) cin >> l[i] >> r[i] >> d[i]; int L = 0, R = m, M, ans = 0; while (L <= R) { M = (L + R) >> 1; if (check(M)) { ans = M; L = M + 1; } else R = M - 1; } cout << ans << endl; return 0; } |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.7
// \ \ Application: MIG
// / / Filename: iodelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2010/10/05 16:43:09 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// This module instantiates the IDELAYCTRL primitive, which continously
// calibrates the IODELAY elements in the region to account for varying
// environmental conditions. A 200MHz or 300MHz reference clock (depending
// on the desired IODELAY tap resolution) must be supplied
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: iodelay_ctrl.v,v 1.1 2010/10/05 16:43:09 mishra Exp $
**$Date: 2010/10/05 16:43:09 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_7/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ip_top/iodelay_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module iodelay_ctrl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter IODELAY_GRP = "IODELAY_MIG", // May be assigned unique name when
// multiple IP cores used in design
parameter INPUT_CLK_TYPE = "DIFFERENTIAL", // input clock type
// "DIFFERENTIAL","SINGLE_ENDED"
parameter RST_ACT_LOW = 1 // Reset input polarity
// (0 = active high, 1 = active low)
)
(
input clk_ref_p,
input clk_ref_n,
input clk_ref,
input sys_rst,
output iodelay_ctrl_rdy
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
wire clk_ref_bufg;
wire clk_ref_ibufg;
wire rst_ref;
reg [RST_SYNC_NUM-1:0] rst_ref_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp_idelay;
wire sys_rst_act_hi;
//***************************************************************************
// Possible inversion of system reset as appropriate
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst;
//***************************************************************************
// Input buffer for IDELAYCTRL reference clock - handle either a
// differential or single-ended input
//***************************************************************************
generate
if (INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref
IBUFGDS #
(
.DIFF_TERM ("TRUE"),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_p),
.IB (clk_ref_n),
.O (clk_ref_ibufg)
);
end else if (INPUT_CLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref),
.O (clk_ref_ibufg)
);
end
endgenerate
//***************************************************************************
// Global clock buffer for IDELAY reference clock
//***************************************************************************
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
//*****************************************************************
// IDELAYCTRL reset
// This assumes an external clock signal driving the IDELAYCTRL
// blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
// lock signal will need to be incorporated in this.
//*****************************************************************
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi;
always @(posedge clk_ref_bufg or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r <= #TCQ rst_ref_sync_r << 1;
assign rst_ref = rst_ref_sync_r[RST_SYNC_NUM-1];
//*****************************************************************
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY (iodelay_ctrl_rdy),
.REFCLK (clk_ref_bufg),
.RST (rst_ref)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int n; const int MAXN = 2e5; pair<ll, int> arr[MAXN]; ll sum[MAXN]; ll ans = 1e18; void init() { ans = 1e18; } void input() { cin >> n; for (int i = 0; i < n; i++) { cin >> arr[i].first; } for (int j = 0; j < n; j++) { cin >> arr[j].second; } sort(arr, arr + n); } void make_sum() { sum[0] = arr[0].second; for (int i = 1; i < n; i++) { sum[i] = sum[i - 1] + arr[i].second; } ans = sum[n - 1]; } void solve() { for (int i = 0; i < n; i++) { ans = min(ans, max(arr[i].first, sum[n - 1] - sum[i])); if (ans == 3) { } } } void output() { cout << ans << endl; } int main() { int number_of_testcases = 1; cin >> number_of_testcases; while (number_of_testcases--) { init(); input(); make_sum(); solve(); output(); } return 0; } |
//Autogenerated verilog on 2015-05-13 11:01:32.310768
`timescale 1 ns / 1 ps
module rbo_test
(
input clk,
output reg CAL,
output CS,
output reg IS1,
output reg IS2,
output reg LE,
output reg R12,
output reg RBI,
output reg RESET,
output reg RPHI1,
output reg RPHI2,
output reg SBI,
output reg SEB,
output reg SPHI1,
output reg SPHI2,
output reg SR,
output [15:0]Aref,
output [15:0]RG,
output [15:0]Vana,
output [15:0]Vthr,
input reset_gen
);
reg [31:0]counter;
reg [7:0]stage;
reg [15:0]stage_iter;
assign CS=0;
assign Vthr=16'H0025;
assign Aref=16'H0033;
assign Vana=16'H0066;
assign RG=16'H0033;
always @(posedge clk) begin
if(reset_gen == 1) begin
counter <= 0;
stage <= 0;
stage_iter <= 0;
end
else begin
if(stage == 0) begin
if(counter == 0) begin
CAL <= 0;
SBI <= 0;
SPHI1 <= 0;
SPHI2 <= 0;
SEB <= 1;
IS1 <= 1;
IS2 <= 0;
SR <= 1;
RESET <= 1;
R12 <= 1;
RBI <= 0;
RPHI1 <= 1;
RPHI2 <= 1;
LE <= 0;
end
if(counter == 7) begin
RBI <= 1;
end
if(counter == 16) begin
RBI <= 0;
end
if(counter == 22) begin
RPHI1 <= 0;
RPHI2 <= 0;
end
if(counter == 24) begin
RBI <= 1;
end
if(counter == 25) begin
RPHI1 <= 1;
end
if(counter == 26) begin
RPHI1 <= 0;
end
if(counter == 27) begin
RBI <= 0;
end
if(counter == 28) begin
RPHI2 <= 1;
end
if(counter == 29) begin
RPHI2 <= 0;
end
if(counter == 29) begin
if(stage_iter == 0) begin
stage <= (stage + 1) % 2;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(stage == 1) begin
if(counter == 0) begin
CAL <= 0;
SBI <= 0;
SPHI1 <= 0;
SPHI2 <= 0;
SEB <= 1;
IS1 <= 1;
IS2 <= 0;
SR <= 1;
RESET <= 1;
R12 <= 1;
RBI <= 0;
RPHI1 <= 1;
RPHI2 <= 0;
LE <= 0;
end
if(counter == 1) begin
RPHI1 <= 0;
end
if(counter == 2) begin
RPHI2 <= 1;
end
if(counter == 3) begin
RPHI2 <= 0;
end
if(counter == 3) begin
if(stage_iter == 128) begin
stage <= (stage + 1) % 2;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<long long> heros(n); for (auto& x : heros) cin >> x; sort(heros.begin(), heros.end()); long long sum = accumulate(heros.begin(), heros.end(), 0ll); int m; cin >> m; while (m--) { long long atk, dfns; cin >> atk >> dfns; int id = lower_bound(heros.begin(), heros.end(), atk) - heros.begin(); long long ans = 2e18 + 5; if (id > 0) { ans = min(ans, atk - heros[id - 1] + max(0ll, dfns - (sum - heros[id - 1]))); } if (id < n) { ans = min(ans, max(0ll, dfns - (sum - heros[id]))); } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18 + 9; int main() { ios::sync_with_stdio(false); cin.tie(0); long long n, k; cin >> n >> k; vector<long long> a(n); for (long long i = 0; i < n; i++) { cin >> a[i]; } sort(a.begin(), a.end()); vector<long long> pref(n, 0), suf(n, 0); for (long long i = 1, sm = a[0]; i < n; i++) { pref[i] = a[i] * i - sm; sm += a[i]; } for (long long i = n - 2, sm = a[n - 1]; i >= 0; i--) { suf[i] = sm - a[i] * (n - i - 1); sm += a[i]; } long long ans = INF; for (long long i = 0, j = 0; i < n; i = j) { for (; j < n && a[j] == a[i]; j++) ; long long prev = 0, forw = 0; long long base = INF; prev += pref[i]; prev -= i; if (i >= k - j + i) base = min(base, prev); forw += suf[j - 1]; forw -= (n - j); if (n - j >= k - j + i) base = min(base, forw); base = min(base, prev + forw); ans = min(ans, base + k - (j - i)); if (j - i >= k) ans = 0; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int i, j, k, p, q, mx = 0, sm = -1, smc = 0, cnt = 0, n; scanf( %d , &n); int arr[n + 5]; int a[100050]; memset(a, 0, sizeof(a)); for (i = 0; i < n; i++) { scanf( %d , &p); a[p]++; arr[i] = p; } sort(arr, arr + n); for (i = n - 1; i >= 0; i--) { if (a[arr[i]] % 2) { return !printf( Conan n ); } } printf( Agasa n ); return 0; } |
`include "scmem.vh"
//
// Icache (IC for short)
//
// 16 or 32KB cache
// DM or 4 way assoc cache
// Cache coherent with the L2 cache
//
// Banked IL1 cache In a 4inst IC, each bank has 16bytes width with 2 banks.
// In a 16 instruction fetch, we just need one bank (64bytes wide).
//
// 4 or 16 instruction fetch (4 or 8 way core)
module icache(
/* verilator lint_off UNUSED */
/* verilator lint_off UNDRIVEN */
input clk
,input reset
//---------------------------
// core interface
,input coretoic_pc_valid
,output coretoic_pc_retry
,input I_coretoic_pc_type coretoic_pc // Bit 0 is always zero
,output ictocore_valid
,input ictocore_retry
,output I_ictocore_type ictocore
//---------------------------
// TLB interface
,input l1tlbtol1_fwd_valid
,output l1tlbtol1_fwd_retry
,input I_l1tlbtol1_fwd_type l1tlbtol1_fwd
// Notify the L1 that the index of the TLB is gone
,input l1tlbtol1_cmd_valid
,output l1tlbtol1_cmd_retry
,input I_l1tlbtol1_cmd_type l1tlbtol1_cmd
//---------------------------
// core Prefetch interface
,output PF_cache_stats_type cachetopf_stats
//---------------------------
// L2 interface (same as DC, but no disp/dack)
,output l1tol2tlb_req_valid
,input l1tol2tlb_req_retry
,output I_l1tol2tlb_req_type l1tol2tlb_req
,output l1tol2_req_valid
,input l1tol2_req_retry
,output I_l1tol2_req_type l1tol2_req
,input l2tol1_snack_valid
,output l2tol1_snack_retry
,input I_l2tol1_snack_type l2tol1_snack
,output l1tol2_snoop_ack_valid
,input l1tol2_snoop_ack_retry
,output I_l2snoop_ack_type l1tol2_snoop_ack
/* verilator lint_on UNUSED */
/* verilator lint_on UNDRIVEN */
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ii = pair<int, int>; using ll = long long int; using vi = vector<int>; using graph = vector<vi>; const int INF = 0x3f3f3f3f; const ll INFL = 0x3f3f3f3f3f3f3f3f; const int MAXN = 200005; int fq[4]; int main() { int n, m, k; string s; cin >> n; cin >> s; for (auto c : s) { int x = c - 0 ; fq[x]++; } if (n == 1) { cout << s << n ; } else if (n == 2) { if (fq[1] == 2) { cout << 1 << n ; } else { cout << s << n ; } } else { cout << 1; while (fq[0]--) { cout << 0; } } } |
/***************************************************************************************************
* *
* Module: Altera_UP_PS2 *
* Description: *
* This module communicates with the PS2 core. *
* Retrived from: http://www.eecg.toronto.edu/~jayar/ece241_08F/AudioVideoCores/ps2/ps2.html *
***************************************************************************************************/
module PS2_Controller #(parameter INITIALIZE_MOUSE = 0) (
// Inputs
CLOCK_50,
reset,
the_command,
send_command,
// Bidirectionals
PS2_CLK, // PS2 Clock
PS2_DAT, // PS2 Data
// Outputs
command_was_sent,
error_communication_timed_out,
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input reset;
input [7:0] the_command;
input send_command;
// Bidirectionals
inout PS2_CLK;
inout PS2_DAT;
// Outputs
output command_was_sent;
output error_communication_timed_out;
output [7:0] received_data;
output received_data_en;
wire [7:0] the_command_w;
wire send_command_w, command_was_sent_w, error_communication_timed_out_w;
generate
if(INITIALIZE_MOUSE) begin
assign the_command_w = init_done ? the_command : 8'hf4;
assign send_command_w = init_done ? send_command : (!command_was_sent_w && !error_communication_timed_out_w);
assign command_was_sent = init_done ? command_was_sent_w : 0;
assign error_communication_timed_out = init_done ? error_communication_timed_out_w : 1;
reg init_done;
always @(posedge CLOCK_50)
if(reset) init_done <= 0;
else if(command_was_sent_w) init_done <= 1;
end else begin
assign the_command_w = the_command;
assign send_command_w = send_command;
assign command_was_sent = command_was_sent_w;
assign error_communication_timed_out = error_communication_timed_out_w;
end
endgenerate
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire ps2_clk_posedge;
wire ps2_clk_negedge;
wire start_receiving_data;
wire wait_for_incoming_data;
// Internal Registers
reg [7:0] idle_counter;
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
// State Machine Registers
reg [2:0] ns_ps2_transceiver;
reg [2:0] s_ps2_transceiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
s_ps2_transceiver <= PS2_STATE_0_IDLE;
else
s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*)
begin
// Defaults
ns_ps2_transceiver = PS2_STATE_0_IDLE;
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if ((idle_counter == 8'hFF) &&
(send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else
ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
if ((received_data_en == 1'b1)/* && (ps2_clk_posedge == 1'b1)*/)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if ((command_was_sent == 1'b1) ||
(error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if (received_data_en == 1'b1)
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else
begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= PS2_CLK;
ps2_data_reg <= PS2_DAT;
end
end
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
idle_counter <= 6'h00;
else if ((s_ps2_transceiver == PS2_STATE_0_IDLE) &&
(idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign ps2_clk_posedge =
((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge =
((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data =
(s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_PS2_Data_In PS2_Data_In (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
// Bidirectionals
// Outputs
.received_data (received_data),
.received_data_en (received_data_en)
);
Altera_UP_PS2_Command_Out PS2_Command_Out (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.the_command (the_command_w),
.send_command (send_command_w),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
// Bidirectionals
.PS2_CLK (PS2_CLK),
.PS2_DAT (PS2_DAT),
// Outputs
.command_was_sent (command_was_sent_w),
.error_communication_timed_out (error_communication_timed_out_w)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; long long x[2005], y[2005]; long long c[2005]; long long k[2005]; bool vis[2005]; long long dis[2005]; long long tower[2005]; long long diss[2005]; long long way[2005][2005]; long long townum = 0; long long add[2005][2]; long long addnum = 0; long long ans = 0; void pri() { printf( %lld n , ans); printf( %lld n , townum); for (int i = 1; i <= townum; i++) { printf( %lld , tower[i]); } printf( n%lld n , addnum); for (int i = 1; i <= addnum; i++) { printf( %lld %lld n , add[i][0], add[i][1]); } } void init() { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { way[i][j] = (abs(x[i] - x[j]) + abs(y[i] - y[j])) * (k[i] + k[j]); } } for (int i = 1; i <= 2003; i++) dis[i] = 1e18; for (int i = 1; i <= n; i++) way[i][0] = way[0][i] = c[i]; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lld%lld , &x[i], &y[i]); } int minn = 1; for (int i = 1; i <= n; i++) { scanf( %lld , &c[i]); } for (int i = 1; i <= n; i++) { scanf( %lld , &k[i]); } init(); dis[0] = 0; for (int i = 0; i <= n; i++) { long long ma = 1e18 + 10; int id = -1; for (int j = 0; j <= n; j++) { if (!vis[j] && dis[j] < ma) { id = j; ma = dis[j]; } } vis[id] = true; ans += dis[id]; if (id != 0) { if (diss[id] != 0) { add[++addnum][0] = diss[id]; add[addnum][1] = id; } else { tower[++townum] = id; } } for (int j = 0; j <= n; j++) { if (!vis[j]) { if (dis[j] > way[id][j]) { dis[j] = way[id][j]; diss[j] = id; } } } } pri(); } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x7f7f7f7f; const int maxn = 1111; const int mod = 1000000007; const double eps = 1e-8; bool vis[maxn][maxn]; int n, k; vector<pair<int, int> > ans; bool solve() { for (int i = 1; i <= n; i++) { int cnt = 0; for (int j = 1; j <= n; j++) { if (vis[i][j]) continue; if (i == j) continue; vis[i][j] = vis[j][i] = true; cnt++; ans.push_back(make_pair(i, j)); if (cnt == k) break; } if (cnt != k) return false; } return true; } int main() { while (cin >> n >> k) { if (!solve()) puts( -1 ); else { cout << ((int)ans.size()) << endl; for (int i = 0; i < ((int)ans.size()); i++) printf( %d %d n , ans[i].first, ans[i].second); } } } |
#include <bits/stdc++.h> using namespace std; int n, m, l; long long dp[250005]; short big_arr[250005], small_arr[5001]; long long pre[51], sum[51], suf[51], mx[51], maxx = -1e5; long long solve(int indx, long long curSum) { if (indx == m + 1) return -2000; short &i = big_arr[indx]; long long &res = dp[indx]; if (~res) return res; res = pre[i]; if (curSum + sum[i] >= suf[i] && curSum + sum[i] > 0) res = max(res, solve(indx + 1, curSum + sum[i]) + sum[i]); else if (suf[i] > 0) res = max(res, solve(indx + 1, suf[i]) + suf[i] - curSum); else res = max(res, solve(indx + 1, 0) - curSum); return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL), cout.tie(NULL); cin >> n >> m; fill(pre, pre + 51, -1e5); fill(suf, suf + 51, -1e5); fill(mx, mx + 51, -1e5); fill(dp, dp + 250005, -1); for (int i = 0; i < n; i++) { cin >> l; long long tmp = 0; for (int j = 0; j < l; j++) { cin >> small_arr[j]; mx[i] = max((long long)small_arr[j], mx[i]); if (tmp < 0) tmp = 0; tmp += small_arr[j]; mx[i] = max(mx[i], tmp); sum[i] += small_arr[j]; pre[i] = max(pre[i], sum[i]); } tmp = 0; for (int j = l - 1; j >= 0; j--) { tmp += small_arr[j]; suf[i] = max(suf[i], tmp); } } for (int i = 1; i <= m; i++) { cin >> big_arr[i]; big_arr[i]--; maxx = max(mx[big_arr[i]], maxx); } cout << max(solve(1, 0), maxx) << endl; } |
`include "defines.v"
//////////////////////////////////////////////////////////////////////////////////
// Licznik robienia kawki
//////////////////////////////////////////////////////////////////////////////////
module counter(clk, count_in, count_out, count_secs);
input clk;
input [3:0] count_in;
output reg count_out;
output wire [6:0]count_secs; // przekazanie pozosta³ego czasu (w sekundach) do modu³u g³ownego
// potrzebna do wywietlacza - 7 bit = max 127 sek (wystarczy)
reg [22:0] count_to_0 = 0; //rejestr 23 bitowy, przy zegarze 50kHz wystarczy na odliczanie od 167 sekund
// pozostaje przeliczyæ czasy
// 1 s = 1 000 000 000 ns
// 1 s = 1 000 000 us
parameter tick_every = 20; // parametr co ile nastêpuje tick zegara (w us)
integer mc = /tick_every; // mno¿nik dla czasu w sekundach (czêstotliwoæ w Hz)
// wysy³amy pozosta³y czas do modu³u top (w sekundach)
assign count_secs = count_to_0/mc;
always @(count_in)
begin
case (count_in)
`LICZNIK_RESET: // reset licznika
begin
count_out <= `NIC_NIE_ODLICZAM;
count_to_0 <= 0;
end
`ODLICZ_KUBEK: // maszyna podstawia kubek
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KUBEK*mc;
end
`ODLICZ_KAWA_OP1: // maszyna mieli kawê dla opcji 1
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KAWA_OPCJA1*mc;
end
`ODLICZ_KAWA_OP2: // maszyna mieli kawê dla opcji 2
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KAWA_OPCJA2*mc;
end
`ODLICZ_KAWA_OP3: // maszyna mieli kawê dla opcji 3
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_KAWA_OPCJA3*mc;
end
`ODLICZ_WODA_OP1: // maszyna wlewa wrz¹tek dla opcji 1
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_WODA_OPCJA1*mc;
end
`ODLICZ_WODA_OP2: // maszyna wlewa wrz¹tek dla opcji 2
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_WODA_OPCJA2*mc;
end
`ODLICZ_WODA_OP3: // maszyna wlewa wrz¹tek dla opcji 3
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_WODA_OPCJA3*mc;
end
`ODLICZ_MLEKO: // maszyna spienia mleko
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_MLEKO*mc;
end
`ODLICZ_NAPELN: // maszyna wype³nia przewody wod¹
begin
count_out <= `ODLICZAM;
count_to_0 <= `CZAS_NAPELN*mc;
end
`ODLICZ_CZYSC: // maszyna usuwa zu¿yt¹ kawê, czyci instalacjê, usuwa wodê z przewodów
begin
count_out = `ODLICZAM;
count_to_0 = `CZAS_CZYSC*mc;
end
endcase;
end
always @(negedge clk) // odliczanie do 0
begin
if(count_out == `ODLICZAM && count_to_0 > 0)
count_to_0 <= count_to_0 - 1;
else
count_out <= `SKONCZYLEM_ODLICZAC; // skoñczylimy odliczaæ
end
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/25 09:40:43
// Design Name:
// Module Name: counters_8bit_with_TD_ff
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module counters_8bit_with_TD_ff(
input Clk,
input Enable,
input Clear,
output [7:0] Q
);
T_ff_with_D_ff SR0 (.Clk(Clk), .T(Enable), .reset_n(Clear), .Q(Q[0]));
T_ff_with_D_ff SR1 (.Clk(Clk), .T(Enable & Q[0]), .reset_n(Clear), .Q(Q[1]));
T_ff_with_D_ff SR2 (.Clk(Clk), .T(Enable & Q[0] & Q[1]), .reset_n(Clear), .Q(Q[2]));
T_ff_with_D_ff SR3 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2]), .reset_n(Clear), .Q(Q[3]));
T_ff_with_D_ff SR4 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3]), .reset_n(Clear), .Q(Q[4]));
T_ff_with_D_ff SR5 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4]), .reset_n(Clear), .Q(Q[5]));
T_ff_with_D_ff SR6 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4] & Q[5]), .reset_n(Clear), .Q(Q[6]));
T_ff_with_D_ff SR7 (.Clk(Clk), .T(Enable & Q[0] & Q[1] & Q[2] & Q[3] & Q[4] & Q[5] & Q[6]), .reset_n(Clear), .Q(Q[7]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_SYMBOL_V
`define SKY130_FD_SC_LP__O22AI_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o22ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { std::cerr << name << : << arg1 << endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); std::cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } const long long MOD = 998244353; const long long INFLL = 0x3f3f3f3f3f3f3f3f; const int INF = 0x3f3f3f3f; const long long MAXN = 1e+5 + 7; const int m = 998244353; const int nax = 1e6; long long fatorial[nax + 1]; long long binary_pow(long long a, long long b) { a = a % m; long long ans = 1; while (b > 0) { if (b & 1) { ans = (ans * a) % m; } a = (a * a) % m; b = b >> 1; } return ans; } long long modular_inverse(long long a) { return binary_pow(a, m - 2); } void calcula_fatorial() { fatorial[0] = 1; for (int i = 1; i <= nax; i++) { fatorial[i] = (fatorial[i - 1] * i) % m; } } long long binomial_coefficient(int n, int k) { return fatorial[n] * modular_inverse(fatorial[k]) % m * modular_inverse(fatorial[n - k]) % m; } void solve() { long long n, k; cin >> n >> k; set<long long> evento; map<long long, long long> entrada, saida; for (int i = 0; i < n; ++i) { long long a, b; cin >> a >> b; evento.insert(a); evento.insert(b); entrada[a]++; saida[b]++; } long long ans = 0, sz = 0; for (auto e : evento) { sz += entrada[e]; for (int i = 0; i < saida[e]; ++i) { if (sz - 1 < k - 1) { sz--; continue; } ans += binomial_coefficient(sz - 1, k - 1); ans %= m; sz--; } } cout << ans << n ; } int main() { calcula_fatorial(); ios_base::sync_with_stdio(0); cin.tie(0); long long i, j, n; int t = 1; while (t--) solve(); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
logic in1 = 1;
logic [1:0] in2 = 2'b11;
logic [31:0] out;
logic [7:0] ones = 8'b11111111;
logic [9:0] ones10 = 10'b1111111111;
typedef logic [7:0] data_t;
typedef logic [9:0] ten_t;
ten_t out10;
// verilator lint_off WIDTH
initial begin
in1 = 1;
in2 = 0;
out = data_t'(in1 << in2);
if (out != 8'b1) $stop;
in2 = 1;
out = data_t'(in1 << in2);
if (out != 8'b10) $stop;
in2 = 2;
out = data_t'(in1 << in2);
if (out != 8'b100) $stop;
in2 = 3;
out = data_t'(in1 << in2);
if (out != 8'b1000) $stop;
// Check upper bits get cleared when cast
in2 = 3;
out = data_t'(ones << in2);
if (out != 8'b11111000) $stop;
in2 = 3;
out = data_t'(ones10 << in2);
if (out != 8'b11111000) $stop;
// bug2597
out = data_t'(10'h208 >> 2);
if (out != 8'h82) $stop;
out = data_t'(10'h208 >> 2);
if (out != 8'h82) $stop;
out = data_t'('h208 >> 2);
if (out != 8'h82) $stop;
out10 = ten_t'('h404 >> 2);
if (out10 != 10'h101) $stop;
$write("*-* All Finished *-*\n");
$finish();
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: prn5ccc.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module prn5ccc (
address,
clock,
q);
input [9:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "prn5.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1023,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "prn5.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1023"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "prn5.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1023"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL prn5ccc.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL prn5ccc.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL prn5ccc.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL prn5ccc.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL prn5ccc_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL prn5ccc_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { int t = 0; int l, r, n, m, x; cin >> n >> x; int sum; int temp = 0; for (int i = 1; i <= n; i++) { cin >> l >> r; sum = 0; while (1) { t = t + x; if (t >= l) { t = (t - x); sum = sum + (r - t); t = t + sum; break; } } temp = temp + sum; } cout << temp << endl; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:03:37 05/12/2015
// Design Name:
// Module Name: sbox6
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sbox6(
Bin,
BSout
);
input [6:1] Bin;
output reg [4:1] BSout;
wire [6:1] offset;
assign offset = {Bin[6], Bin[1], Bin[5 : 2]};
always @(offset)
begin
case (offset)
6'b000000: BSout <= 4'd12;
6'b000001: BSout <= 4'd1;
6'b000010: BSout <= 4'd10;
6'b000011: BSout <= 4'd15;
6'b000100: BSout <= 4'd9;
6'b000101: BSout <= 4'd2;
6'b000110: BSout <= 4'd6;
6'b000111: BSout <= 4'd8;
6'b001000: BSout <= 4'd0;
6'b001001: BSout <= 4'd13;
6'b001010: BSout <= 4'd3;
6'b001011: BSout <= 4'd4;
6'b001100: BSout <= 4'd14;
6'b001101: BSout <= 4'd7;
6'b001110: BSout <= 4'd5;
6'b001111: BSout <= 4'd11;
6'b010000: BSout <= 4'd10;
6'b010001: BSout <= 4'd15;
6'b010010: BSout <= 4'd4;
6'b010011: BSout <= 4'd2;
6'b010100: BSout <= 4'd7;
6'b010101: BSout <= 4'd12;
6'b010110: BSout <= 4'd9;
6'b010111: BSout <= 4'd5;
6'b011000: BSout <= 4'd6;
6'b011001: BSout <= 4'd1;
6'b011010: BSout <= 4'd13;
6'b011011: BSout <= 4'd14;
6'b011100: BSout <= 4'd0;
6'b011101: BSout <= 4'd11;
6'b011110: BSout <= 4'd3;
6'b011111: BSout <= 4'd8;
6'b100000: BSout <= 4'd9;
6'b100001: BSout <= 4'd14;
6'b100010: BSout <= 4'd15;
6'b100011: BSout <= 4'd5;
6'b100100: BSout <= 4'd2;
6'b100101: BSout <= 4'd8;
6'b100110: BSout <= 4'd12;
6'b100111: BSout <= 4'd3;
6'b101000: BSout <= 4'd7;
6'b101001: BSout <= 4'd0;
6'b101010: BSout <= 4'd4;
6'b101011: BSout <= 4'd10;
6'b101100: BSout <= 4'd1;
6'b101101: BSout <= 4'd13;
6'b101110: BSout <= 4'd11;
6'b101111: BSout <= 4'd6;
6'b110000: BSout <= 4'd4;
6'b110001: BSout <= 4'd3;
6'b110010: BSout <= 4'd2;
6'b110011: BSout <= 4'd12;
6'b110100: BSout <= 4'd9;
6'b110101: BSout <= 4'd5;
6'b110110: BSout <= 4'd15;
6'b110111: BSout <= 4'd10;
6'b111000: BSout <= 4'd11;
6'b111001: BSout <= 4'd14;
6'b111010: BSout <= 4'd1;
6'b111011: BSout <= 4'd7;
6'b111100: BSout <= 4'd6;
6'b111101: BSout <= 4'd0;
6'b111110: BSout <= 4'd8;
6'b111111: BSout <= 4'd13;
default: BSout <= 4'd0;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NAND4_BEHAVIORAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, D, C, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int n; int a[3][11]; int sum[11]; int x, len, i; int main() { scanf( %d , &n); for (i = 0; i < n; i++) for (int j = 0; j < 6; j++) { scanf( %d , &x); a[i][x]++; sum[x]++; } for (i = 1; i < 1000; i++) { if (i < 10) { if (sum[i]) continue; else break; } else if (i < 100) { int flag = 0; for (int j = 0; j < 3; j++) for (int k = 0; k < 3; k++) { if (k == j) continue; if (a[j][i % 10] && a[k][i / 10]) flag = 1; } if (flag == 0) break; } else { int flag = 0; for (int j = 0; j < 3; j++) { for (int k = 0; k < 3; k++) { if (k == j) continue; for (int l = 0; l < 3; l++) { if (l == k || l == j) continue; if (a[j][i % 10] && a[k][i / 10 % 10] && a[l][i / 100]) flag = 1; } } } if (flag == 0) break; } } cout << i - 1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long po(long long x, long long n) { long long res = 1; while (n > 0) { if (n & 1) res = (res * x) % 998244353; n = n / 2; x = (x * x) % 998244353; } return res; } long long fac[500000 + 1] = {0}; long long ifac[500000 + 1] = {0}; void pre() { fac[0] = ifac[0] = 1; for (int i = 1; i <= 500000; i++) { fac[i] = (i * fac[i - 1]) % 998244353; ifac[i] = po(fac[i], 998244353 - 2); } } long long nCr(long long n, long long r) { if (r > n || r < 0 || n < 0) return 0; return (((fac[n] * ifac[r]) % 998244353) * ifac[n - r]) % 998244353; } void func() { long long n, k; cin >> n >> k; long long ans = 0; pre(); for (int i = 1; i <= n; i++) { ans = (ans + nCr(n / i - 1, k - 1)) % 998244353; } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) func(); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; if (m % 2 != 0) { cout << (m + 1) / 2; } else { cout << (n - m + 2) / 2; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector,unroll-loops,fast-math,O3 ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,sse4.2,popcnt,abm,mmx,avx ) using namespace std; template <class T> istream& operator>>(istream& is, vector<T>& v) { for (auto& x : v) { is >> x; } return is; } template <class T> ostream& operator<<(ostream& os, vector<T>& v) { for (auto& x : v) { os << x << ; } return os; } const int N = (1 << 20) + 1; vector<pair<int, int>> eulerWalk(vector<vector<pair<int, int>>>& gr, int nedges, int src = 0) { int n = ((int)(gr.size())); static vector<int> D(N), its(N), eu(N); D.clear(), D.resize(n); its.clear(), its.resize(n); eu.clear(), eu.resize(nedges); static vector<pair<int, int>> s; s = {make_pair(src, -1)}; static vector<pair<int, int>> ret; ret.clear(); D[src]++; while (!s.empty()) { auto x = s.back(); int y, e, &it = its[x.first], end = ((int)(gr[x.first].size())); if (it == end) { ret.push_back(x); s.pop_back(); continue; } tie(y, e) = gr[x.first][it++]; if (!eu[e]) { D[x.first]--, D[y]++; eu[e] = 1; s.emplace_back(y, e); } } for (int x : D) if (x < 0 || ((int)(ret.size())) != nedges + 1) return {}; return {ret.rbegin(), ret.rend()}; } vector<vector<pair<int, int>>> graph(N); vector<pair<int, int>> cycle; bool valid(int k, const vector<pair<int, int>>& pearls) { graph.clear(); graph.resize((1 << k)); int src; for (int i = 0; i < ((int)(pearls.size())); ++i) { int u = (pearls[i].first & ((1 << k) - 1)); int v = (pearls[i].second & ((1 << k) - 1)); graph[u].emplace_back(v, i); graph[v].emplace_back(u, i); src = u; } cycle = eulerWalk(graph, pearls.size(), src); return !cycle.empty() && cycle.back().first == src; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n; cin >> n; vector<pair<int, int>> pearls(n); for (auto& p : pearls) { cin >> p.first >> p.second; } int res = 20; while (!valid(res, pearls)) { --res; } cout << res << n ; for (int i = 0; i < n; ++i) { int u = (pearls[i].first & ((1 << res) - 1)); int v = (pearls[i].second & ((1 << res) - 1)); pearls[i] = make_pair(u, v); } for (int i = 1; i <= n; ++i) { auto curr = cycle[i]; int prev_node = cycle[i - 1].first; int curr_edge = curr.second; if (pearls[curr_edge].first == prev_node && pearls[curr_edge].second == curr.first) { cout << 2 * curr_edge + 1 << << 2 * curr_edge + 2 << ; } else { cout << 2 * curr_edge + 2 << << 2 * curr_edge + 1 << ; } } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 1e6 + 10; const long long INF = 1e18; const long double EPS = 1e-12; long long w[200005]; long long h[200005]; long long c[200005]; long long rgcd[200005]; map<long long, vector<pair<long long, long long> > > ma; long long gcd(long long a, long long b) { if (b == 0) return a; a %= b; return gcd(b, a); } int main() { int n; cin >> n; long long tp = 0; for (int i = 0; i < (int)n; i++) { cin >> w[i] >> h[i] >> c[i]; ma[w[i]].push_back(make_pair(h[i], c[i])); if (i == 0) tp = c[i]; else tp = gcd(tp, c[i]); } map<long long, vector<pair<long long, long long> > >::iterator it, it_; for (it = ma.begin(); it != ma.end(); it++) { sort((it->second).begin(), (it->second).end()); } it_ = ma.begin(); it_++; for (it = ma.begin(); it_ != ma.end(); it++) { int si = (int)(it->second).size(); int si_ = (int)(it_->second).size(); if (si != si_) { cout << 0 << endl; return 0; } for (int i = 0; i < (int)si; i++) { if ((it->second)[i].first != (it_->second)[i].first) { cout << 0 << endl; return 0; } } it_++; } long long net; int fl = 0; for (it = ma.begin(); it != ma.end(); it++) { int si = (int)(it->second).size(); int si_ = (int)(it_->second).size(); long long tmp = (it->second)[0].second; for (int i = (int)1; i < (int)si; i++) { if (tmp == 1) break; tmp = gcd(tmp, (it->second)[i].second); } for (int i = 0; i < (int)si; i++) { ((it->second)[i].second) /= tp; } } net = tp; if (net == 1) { it_ = ma.begin(); it_++; for (it = ma.begin(); it_ != ma.end(); it++) { int si = (int)(it->second).size(); int si_ = (int)(it_->second).size(); long long d1 = 0; long long d2 = 0; for (int i = 0; i < (int)si; i++) { d1 += ((it->second)[i].first) * ((it->second)[i].second); } for (int i = 0; i < (int)si; i++) { d2 += ((it_->second)[i].first) * ((it_->second)[i].second); } if (d1 != d2) { cout << 0 << endl; return 0; } it_++; } } long long ans = 0; for (int i = (int)1; i < (int)1e6 + 5; i++) { long long i_ = (long long)(i); if (i_ * i_ > net) break; if (net % i_ == 0) { ans += 2; } if (i_ * i_ == net) { ans--; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; template <class T, class U> inline void Max(T &a, U b) { if (a < b) a = b; } template <class T, class U> inline void Min(T &a, U b) { if (a > b) a = b; } inline void add(int &a, int b) { a += b; while (a >= 1000003) a -= 1000003; } int pow(int a, int b) { int ans = 1; while (b) { if (b & 1) ans = ans * (long long)a % 1000003; a = (long long)a * a % 1000003; b >>= 1; } return ans; } int f[700005], inv[700005], M; int main() { int T = 100, j, k, i, ca = 0, m, n; scanf( %d%d , &n, &m); M = n + m; f[0] = 1; for (int i = 1; i < M; i++) f[i] = f[i - 1] * (long long)i % 1000003; inv[M - 1] = pow(f[M - 1], 1000003 - 2); for (int i = M - 1 - 1; i >= 0; i--) inv[i] = inv[i + 1] * (long long)(i + 1) % 1000003; long long ans = 0; for (int i = 1; i < n + 1; i++) { ans += 1LL * f[i + m - 1] * inv[i] % 1000003; } ans %= 1000003; printf( %d n , ans * inv[m - 1] % 1000003); return 0; } |
`timescale 1 ps / 1 ps
(* message_disable = "14320" *) module alt_mem_ddrx_fifo
# (
parameter
CTL_FIFO_DATA_WIDTH = 8,
CTL_FIFO_ADDR_WIDTH = 3
)
(
// general
ctl_clk,
ctl_reset_n,
// pop free fifo entry
get_valid,
get_ready,
get_data,
// push free fifo entry
put_valid,
put_ready,
put_data
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_FIFO_DEPTH = (2 ** CTL_FIFO_ADDR_WIDTH);
localparam CTL_FIFO_TYPE = "SCFIFO"; // SCFIFO, CUSTOM
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free fifo entry
input get_ready;
output get_valid;
output [CTL_FIFO_DATA_WIDTH-1:0] get_data;
// push free fifo entry
output put_ready;
input put_valid;
input [CTL_FIFO_DATA_WIDTH-1:0] put_data;
// -----------------------------
// port type declaration
// -----------------------------
wire get_valid;
wire get_ready;
wire [CTL_FIFO_DATA_WIDTH-1:0] get_data;
wire put_valid;
wire put_ready;
wire [CTL_FIFO_DATA_WIDTH-1:0] put_data;
// -----------------------------
// signal declaration
// -----------------------------
reg [CTL_FIFO_DATA_WIDTH-1:0] fifo [CTL_FIFO_DEPTH-1:0];
reg [CTL_FIFO_DEPTH-1:0] fifo_v;
wire fifo_get;
wire fifo_put;
wire fifo_empty;
wire fifo_full;
wire zero;
// -----------------------------
// module definition
// -----------------------------
assign fifo_get = get_valid & get_ready;
assign fifo_put = put_valid & put_ready;
assign zero = 1'b0;
generate
begin : gen_fifo_instance
if (CTL_FIFO_TYPE == "SCFIFO")
begin
assign get_valid = ~fifo_empty;
assign put_ready = ~fifo_full;
scfifo #(
.add_ram_output_register ( "ON" ),
.intended_device_family ( "Stratix IV" ),
.lpm_numwords ( CTL_FIFO_DEPTH ),
.lpm_showahead ( "ON" ),
.lpm_type ( "scfifo" ),
.lpm_width ( CTL_FIFO_DATA_WIDTH ),
.lpm_widthu ( CTL_FIFO_ADDR_WIDTH ),
.overflow_checking ( "OFF" ),
.underflow_checking ( "OFF" ),
.use_eab ( "ON" )
) scfifo_component (
.aclr (~ctl_reset_n),
.clock (ctl_clk),
.data (put_data),
.rdreq (fifo_get),
.wrreq (fifo_put),
.empty (fifo_empty),
.full (fifo_full),
.q (get_data),
.almost_empty (),
.almost_full (),
.sclr (zero),
.usedw (),
.eccstatus ()
);
end
else // CTL_FIFO_TYPE == "CUSTOM"
begin
assign get_valid = fifo_v[0];
assign put_ready = ~fifo_v[CTL_FIFO_DEPTH-1];
assign get_data = fifo[0];
// put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
// initialize every entry
fifo [i] <= 0;
fifo_v [i] <= 1'b0;
end
end
else
begin
// get request code must be above put request code
if (fifo_get)
begin
// on a get request, fifo entry is shifted to move next entry to head
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
fifo_v [i-1] <= fifo_v [i];
fifo [i-1] <= fifo [i];
end
fifo_v [CTL_FIFO_DEPTH-1] <= 0;
end
if (fifo_put)
begin
// on a put request, next empty fifo entry is written
if (~fifo_get)
begin
// put request only
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
if ( fifo_v[i-1] & ~fifo_v[i])
begin
fifo_v [i] <= 1'b1;
fifo [i] <= put_data;
end
end
if (~fifo_v[0])
begin
fifo_v [0] <= 1'b1;
fifo [0] <= put_data;
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
if ( fifo_v[i-1] & ~fifo_v[i])
begin
fifo_v [i-1] <= 1'b1;
fifo [i-1] <= put_data;
end
end
if (~fifo_v[0])
begin
$display("error - fifo underflow");
end
end
end
end
end
end
end
endgenerate
endmodule
//
// ASSERT
//
// fifo underflow
//
|
#include <bits/stdc++.h> using namespace std; long long nChooseR(int n, int k); long long gcd(long long a, long long b); vector<string> split(string target, char c); bool isPrime(long long g); long long n, m, t, a[] = {0, 0, 1, 2, 3, 4, 5}, k, x, y, z; long long ans; map<pair<int, int>, int> mp; vector<vector<int>> grid(7); void solve(int i) { for (auto u : grid[i]) { if (mp[make_pair(a[i], a[u])] == 1) { z++; mp[make_pair(a[i], a[u])] = 0; mp[make_pair(a[u], a[i])] = 0; solve(u); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m; for (int i = 0; i < (int)(m); i++) { cin >> x >> y; x--; y--; grid[x].push_back(y); grid[y].push_back(x); } do { z = 0; for (int i = 0; i < (int)(6); i++) { for (int j = 0; j < (int)(6); j++) mp[make_pair(i, j)] = 1; } for (int i = 0; i < (int)(6); i++) solve(i); ans = max(ans, z); } while (next_permutation(a, a + 7)); cout << ans; return 0; } long long nChooseR(int n, int k) { if (k > n) return 0; if (k * 2 > n) k = n - k; if (k == 0) return 1; long long result = n; for (int i = 2; i <= k; ++i) { result *= (n - i + 1); result /= i; } return result; } long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } vector<string> split(string target, char c) { string d = ; vector<string> arr; for (auto n : target) { if (n != c) d += n; else if (d != ) arr.push_back(d), d = ; } if (d != ) arr.push_back(d), d = ; return arr; } bool isPrime(long long g) { if ((g % 2 == 0 && g > 2) || g == 1) return 0; for (long long i = 3; i * i <= g; i += 2) if (g % i == 0) return 0; return 1; } |
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; long long quickpow(long long a, long long b) { long long ans = 1; a = a % mod; while (b > 0) { if (b % 2) ans = ans * a; b = b / 2; a = a * a; } return ans; } int gcd(int a, int b) { return b == 0 ? a : gcd(b, a % b); } long long a[500005]; long long sum[500005]; long long tot = 0; int main() { ios::sync_with_stdio(false); int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) { sum[i] = sum[i - 1] + a[i]; } tot += sum[n]; for (int i = 1; i <= n - 1; i++) { tot += (sum[n] - sum[i - 1]); } cout << tot << endl; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { for (; b; a %= b, swap(a, b)) ; return a; } int main() { ios::sync_with_stdio(0); cin.tie(0), cout.tie(0); int t; cin >> t; while (t--) { int n, x; cin >> n >> x; int cnt = 0; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; if (u == x || v == x) cnt++; } if (cnt <= 1) { cout << Ayush n ; continue; } if (n % 2) cout << Ashish n ; else cout << Ayush n ; } } |
#include <bits/stdc++.h> using namespace std; const int N = 1005; struct edge { int to, next; } e[N * 2]; int head[N], tot, n; int sz[N], mxv, mxrt; void add(int x, int y) { e[++tot] = (edge){y, head[x]}; head[x] = tot; } void dfs(int x, int fa, int n) { int mx = 0; sz[x] = 1; for (int i = head[x]; i; i = e[i].next) if (e[i].to != fa) { dfs(e[i].to, x, n); sz[x] += sz[e[i].to]; mx = max(mx, sz[e[i].to]); } mx = max(mx, n - sz[x]); if (mx < mxv) mxv = mx, mxrt = x; } pair<int, int> q[N]; int f[N][N]; int top, be[N], mnv, mnid, dif; void insert(int x, int y) { q[++top] = pair<int, int>(x, y); for (int i = (int)(0); i <= (int)(n); i++) f[top][i] = f[top - 1][i]; for (int i = (int)(y); i <= (int)(n); i++) f[top][i] |= f[top - 1][i - y]; } int s1, s2, dep[N]; void getans(int x, int fa, int type) { dep[x] = (type == 1 ? (s1 += 1) : (s2 += dif)); printf( %d %d %d n , x, fa, dep[x] - dep[fa]); for (int i = head[x]; i; i = e[i].next) if (e[i].to != fa) getans(e[i].to, x, type); } int main() { scanf( %d , &n); for (int i = (int)(1); i <= (int)(n - 1); i++) { int x, y; scanf( %d%d , &x, &y); add(x, y); add(y, x); } mxv = 1 << 30; dfs(1, 0, n); f[0][0] = 1; for (int i = head[mxrt]; i; i = e[i].next) insert(e[i].to, sz[e[i].to] > sz[mxrt] ? n - sz[mxrt] : sz[e[i].to]); insert(mxrt, 1); mnv = 1 << 30; for (int i = (int)(0); i <= (int)(n); i++) if (abs(n - 2 * i) < mnv && f[top][i]) mnv = n - 2 * i, mnid = i; dif = mnid; for (int i = (int)(top); i >= (int)(1); i--) { if (mnid >= q[i].second && f[i - 1][mnid - q[i].second]) be[i] = 1, mnid -= q[i].second; else be[i] = 0; } for (int i = (int)(1); i <= (int)(top - 1); i++) getans(q[i].first, mxrt, be[i]); } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; long long m, x, p[22], a[22], b[22], len, res = 1; map<long long, int> Map[22]; inline void init(long long n) { for (register long long i = 2; i * i <= n; i++) if (n % i == 0) { len++; p[len] = i; while (n % i == 0) n /= i, a[len]++; } if (n > 1) len++, p[len] = n, a[len] = 1; } inline void init2(long long n, int tp) { for (register long long i = 2; i * i <= n; i++) { while (n % i == 0) Map[tp][i]++, n /= i; } if (n > 1) Map[tp][n]++; } inline long long mul(long long a, long long n, long long mo) { long long res = 0; n %= mo; a %= mo; if (mo <= 2000000000) return a * n % mo; while (n) { if (n & 1) res = res + a < mo ? res + a : res + a; a = a + a < mo ? a + a : a + a - mo; n >>= 1; } return res % mo; } inline long long power(long long a, long long n, long long mo) { long long res = 1; if (mo == 1) return 0; n %= mo - 1; while (n) { if (n & 1) res = mul(res, a, mo); a = mul(a, a, mo); n >>= 1; } return res; } inline void dfs(int dep, long long d) { if (dep > len) { if (d == 1) return; map<long long, int> fac; for (register int i = 1; i <= (len); i++) if (b[i]) { if (b[i] - 1) fac[p[i]] += b[i] - 1; for (map<long long, int>::iterator it = Map[i].begin(); it != Map[i].end(); it++) fac[(*it).first] += (*it).second; } static long long c[22]; int tot = 0; long long phi = 1; for (map<long long, int>::iterator it = fac.begin(); it != fac.end(); it++) { tot++, c[tot] = (*it).first; for (register int i = 1; i <= ((*it).second); i++) phi *= c[tot]; } long long k = phi; for (register int i = 1; i <= (tot); i++) { while (k % c[i] == 0 && power(x, k / c[i], d) == 1) k /= c[i]; } res += phi / k; return; } for (register int i = 0; i <= (a[dep]); i++) b[dep] = i, dfs(dep + 1, d), d *= p[dep], b[dep] = 0; } int main() { scanf( %lld%lld , &m, &x); init(m); for (register int i = 1; i <= (len); i++) init2(p[i] - 1, i); dfs(1, 1); cout << res; return 0; } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_rate_limit;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 8'd0;
reg input_axis_tvalid = 1'b0;
reg input_axis_tlast = 1'b0;
reg input_axis_tuser = 1'b0;
reg output_axis_tready = 1'b0;
reg [7:0] rate_num = 0;
reg [7:0] rate_denom = 0;
reg rate_by_frame = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready,
rate_num,
rate_denom,
rate_by_frame);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_rate_limit.lxt");
$dumpvars(0, test_axis_rate_limit);
end
axis_rate_limit #(
.DATA_WIDTH(8)
)
UUT (
.clk(clk),
.rst(rst),
// axi input
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// axi output
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
// configuration
.rate_num(rate_num),
.rate_denom(rate_denom),
.rate_by_frame(rate_by_frame)
);
endmodule
|
`timescale 1ns / 1ps
module ProcessorControl
(
// Input
input [5:0] Inst,
input Compare,
input [5:0] Fn,
// Output
output wire [1:0] RegDst,
output wire ALUSrc,
output wire [1:0] MemtoReg,
output wire RegWrite,
output wire MemRead,
output wire MemWrite,
output wire Branch,
output wire [1:0] ALUOp,
output wire Jump,
output wire Jr,
output wire FlushIF
);
// Internal Variables
wire RFormat;
wire lw;
wire sw;
wire beq;
wire j;
wire addi;
wire subi;
wire jr0;
// Assigns
assign RFormat = &(~Inst[5:0]);
assign lw = (&(~Inst[4:2])) & (&(Inst[1:0])) & Inst[5];
assign sw = (&(Inst[1:0])) & Inst[5] & Inst[3] & ~Inst[4] & ~Inst[2];
assign beq = (&(~Inst[5:3])) & (&(~Inst[1:0])) & Inst[2];
assign j = (&(~Inst[5:2])) & Inst[1]; // OP(j) = 000010, OP(jal) = 000011
assign addi = (&(~Inst[5:4])) & Inst[3] & (&(~Inst[2:0])); // OP(addi) = 001000
assign subi = (&(~Inst[5:3])) & Inst[2:0]; // OP(subi) = 000111
assign jr0 = RFormat & (&(~Fn[5:4])) & Fn[3] & (&(~Fn[2:0])); // Fn = 001000, OP = 0x00
// Output Setting
assign RegDst[0] = RFormat ;
assign RegDst[1] = ( j & Inst[0] );
assign ALUSrc = lw | sw | addi | subi;
assign MemtoReg[0] = lw;
assign MemtoReg[1] = ( j & Inst[0] );
assign RegWrite = ( RFormat | lw | ( j & Inst[0] ) | addi | subi ) & (~jr0);
assign MemRead = lw;
assign MemWrite = sw;
assign Branch = beq;
assign Jump = j;
assign Jr = jr0;
assign ALUOp[0] = beq | subi;
assign ALUOp[1] = RFormat;
assign FlushIF = ( (Compare && beq) | j | jr0 ) ? 1'b1 : 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; struct Trie { int trie[6000005][2]; int cnt[6000005]; int root = 0; long long val[6000005]; long long xorsum = 0; long long ans[6000005 / 10]; int C = 0; int newroot() { trie[C][0] = trie[C][1] = -1; cnt[C] = 0; return C++; } void Insert(long long x) { long long p = root; for (int i = 60; i >= 0; i--) { long long id = (x >> i) & 1; if (trie[p][id] == -1) trie[p][id] = newroot(); p = trie[p][id]; cnt[p]++; } val[p] = x; } bool check(long long xorsum, long long &res, int index, bool limit, int dep) { if (index != root && (cnt[index] == 0 || index == -1)) return false; if (dep == -1) { res = val[index]; cnt[index]--; return true; } int id = (xorsum >> dep) & 1; if (id == 0) { bool ret = (check(xorsum, res, trie[index][0], limit, dep - 1)) || (!limit && check(xorsum, res, trie[index][1], limit, dep - 1)); if (ret == 0) return false; cnt[index]--; return true; } else { bool ret = (check(xorsum, res, trie[index][0], limit, dep - 1)) || (check(xorsum, res, trie[index][1], false, dep - 1)); if (ret == 0) return false; cnt[index]--; return true; } } void solve() { for (int i = n - 1; i >= 0; i--) { long long res; bool ret = check(xorsum, res, root, true, 60); if (ret == 0) { puts( No ); return; } ans[i] = res; assert(xorsum > (xorsum ^ res)); xorsum ^= res; } puts( Yes ); for (int i = 0; i < n; i++) { cout << ans[i] << ; } puts( ); } } Tree; int main() { scanf( %d , &n); Tree.root = Tree.newroot(); for (int i = 0; i < n; i++) { long long x; scanf( %I64d , &x); Tree.Insert(x); Tree.xorsum ^= x; } Tree.solve(); } |
`include "../network_params.h"
module window_wrapper(
input clock,
input reset,
// buffer inputs
input [`CAMERA_PIXEL_BITWIDTH:0] pixel_in,
input shift_left,
input shift_up,
// window inputs
input [`X_COORD_BITWIDTH:0] kernel_x, // the bottom right corner of the kernel position
input [`Y_COORD_BITWIDTH:0] kernel_y, // the bottom right corner of the kernel position
// the kernel sized view of the buffer to be fed into the multipliers
output [`WINDOW_VECTOR_BITWIDTH:0] window_out
);
// wire declarations
wire [`BUFFER_OUT_VECTOR_BITWIDTH:0] buffer_vector;
wire [`CAMERA_PIXEL_BITWIDTH:0] window_wire [`KERNEL_SIZE-1:0][`KERNEL_SIZE-1:0];
// reg declarations
// instantiate shifting window
shifting_window shifting_window_inst(
.clock(clock),
.reset(reset),
.shift_up(shift_up), // shift all rows up
.shift_left(shift_left), // to load new pixel into bottom row
.pixel_in(pixel_in),
.buffer_out(buffer_vector)
);
// generate window selectors
genvar i;
genvar j;
generate
for (j=0; j<`KERNEL_SIZE; j=j+1) begin : selector_height_loop
for (i=0; i<`KERNEL_SIZE; i=i+1) begin : selector_width_loop
window_selector selector_inst(
.clock(clock),
.reset(reset),
.buffer_vector(buffer_vector),
.x(kernel_x+i),
.y(kernel_y+j),
.value_out(window_wire[i][j])
);
end // for i
end // for j
endgenerate
genvar n;
genvar m;
generate
for (n=0; n<`KERNEL_SIZE; n=n+1) begin : kernel_h_loop
for (m=0; m<`KERNEL_SIZE; m=m+1) begin : kernel_w_loop
assign window_out[
(`CAMERA_PIXEL_WIDTH*m)+(`KERNEL_SIZE*`CAMERA_PIXEL_WIDTH*n)+`CAMERA_PIXEL_BITWIDTH:
(`CAMERA_PIXEL_WIDTH*m)+(`KERNEL_SIZE*`CAMERA_PIXEL_WIDTH*n)
] = window_wire[m][n];
end // for m
end // for n
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int pp = (1e9) + 7; long long P[1000010]; long long ans, now; int N, K; long long quick(int x, int y) { long long s = 1, t = x; for (; y; y >>= 1) { if (y & 1) s = s * t % pp; t = t * t % pp; } return s; } long long get0() { long long t = 1; for (int i = N - K - 1; i < N; i++) t = t * i % pp; for (int i = 1; i <= K + 1; i++) t = t * quick(pp - i, pp - 2) % pp; return t; } int main() { scanf( %d%d , &N, &K); if (!K) { printf( %d n , N); return 0; } for (int i = 1; i <= K + 2; i++) P[i] = (P[i - 1] + quick(i, K)) % pp; if (N <= K + 2) { printf( %I64d n , P[N]); return 0; } ans = 0; now = get0(); for (int i = 1; i <= K + 1; i++) { now = now * quick(i, pp - 2) % pp * (N - i + 1) % pp * quick(N - i, pp - 2) % pp * (pp - (K - i + 2)) % pp; ans = (ans + P[i] * now) % pp; } printf( %I64d , ans); } |
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Matrix Arbiter
*
* See Dally/Towles (p.359) for implementation details and full description
*
* Multistage Options
* ==================
*
* [multistage=0] Arbiter state is updated whenever a request is granted.
*
* [multistage=1] This arbiter is meant for situations where the initial
* request must progress through multiple stages of arbitration. An
* additional input to the arbiter (success) ensures that the state of
* the arbiter is only updated if the request is finally granted (at the
* last stage of arbitration).
*
* || This assumes 'success' is produced before the end of the current clock
* || cycle.
*
* [multistage=2] Used in situations where multistage=1 would be, but when
* 'success' is not available until the next clock cycle.
*
* Prioritised inputs
* ==================
*
* [priority_support = 0 | 1]
*
* Input requested are prioritized by associated 'req_priority' input,
* may be anything from a single bit to N-bits wide.
*
* e.g. for 16 priority levels:
*
* parameter priority_support = 1;
* parameter type priority_type = bit unsigned [3:0];
*
* Note: The priority input is ignored if the associated request is
* not asserted.
*
*/
//#################################
// NOT IMPLEMENTED YET:
//
// - parameter GRANT_HOLD
// don't update matrix state until request
// assoc. with current grant is released
// - winning request will hold grant for as long as it is asserted
//
// - parameter PRIORITIZE first F inputs -
// inputs 0..F are priority inputs
// input 0 will be granted if requested
// input 1 will be granted (if input 0 is not asserted)
// ..etc to input F
//
// weighted arbiter,....
module comb_matrix_arb_next_state (state, grant, new_state);
parameter size=4;
input [size*size-1:0] state;
input [size-1:0] grant;
output [size*size-1:0] new_state;
genvar i,j;
generate
for (i=0; i<size; i=i+1) begin:ol2
for (j=0; j<size; j=j+1) begin:il2
assign new_state[j*size+i]= (state[j*size+i]&&!grant[j])||(grant[i]);
end
end
endgenerate
endmodule // comb_matrix_arb_next_state
module matrix_arb (request, grant, success, clk, rst_n);
parameter size= 4;
parameter multistage = 0;
parameter grant_hold = 0;
parameter priority_support = 0;
input [size-1:0] request;
output [size-1:0] grant;
input success;
input clk, rst_n;
genvar i,j;
logic [size-1:0] req;
logic [size-1:0] newgrant;
logic [size*size-1:0] next_state, current_state;
logic [size-1:0] pri [size-1:0];
logic [size*size-1:0] new_state;
logic [size*size-1:0] state;
logic update;
genvar r;
integer k;
assign req = request;
// ##########################################
// Generate grants
// ##########################################
generate
for (i=0; i<size; i=i+1) begin:ol1
// generate grant i
for (j=0; j<size; j=j+1) begin:il1
if (j==i)
// request i wins if requesting and....
assign pri[i][j]=req[i];
else
// ....no other request with higher priority
if (j>i)
// j beats i
assign pri[i][j]=!(req[j]&&state[j*size+i]);
else
// !(i beats j)
assign pri[i][j]=!(req[j]&&!state[i*size+j]);
end
assign grant[i]=&pri[i];
end
endgenerate
generate
if (multistage==2) begin
assign state = success ? next_state : current_state;
end else begin
assign state = current_state;
end
endgenerate
//
// calculate next matrix state based on current requests and grants
//
comb_matrix_arb_next_state #(size) calc_next (.*);
always@(posedge clk) begin
if (!rst_n) begin
current_state<='1; //-1;
next_state<='1; //-1;
end else begin
// **************************************************
// Multistage Arbiter with Late Success Notification (multistage==2)
// **************************************************
if (multistage==2) begin
update<=|req;
if (|req) begin
// This 'next_state' will only be used on next clock cycle if
// 'success' is asserted
next_state <= new_state;
end
if (update) begin
current_state <= state;
end
end else begin
// ************************************
// Multistage Arbiter (multistage==1)
// ************************************
// check request was ultimately successful before updating arbiter state
// we know about success before the next clock cycle.
if ((multistage==1)&!success) begin
// request was not ultimately successful, don't update priorities
end else begin
// **********************************
// Basic Arbiter (multistage==0)
// **********************************
// Update state whenever at least one request has been made
if (|req) begin
current_state<=new_state;
end
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t, c, i, a, m, l, r; cin >> t >> i >> m >> a >> l; r = i; c = 1; t = t - r; while (t > 0) { c++; r = r + a; if (r > m) r = m; t = t + l - r; if (t < 0) t = 0; } cout << c; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; const int MAX = 2e5 + 5; const long long MAX2 = 11; const int MOD = 1000000000 + 7; const long long INF = 20000; const int dr[] = {1, 0, -1, 0, 1, 1, -1, -1}; const int dc[] = {0, 1, 0, -1, 1, -1, 1, -1}; const double pi = acos(-1); long long tc, a, b, c, d, x[3]; bool ans; inline bool cek() { sort(x, x + 3); if (x[0] < 0 || 2 * x[2] - x[0] - x[1] > a || (a - 2 * x[2] + x[0] + x[1]) % 3 || x[0] + x[1] + x[2] > b || (x[0] + x[1] + x[2]) % 3 != b % 3) return 0; return 1; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> tc; while (tc--) { cin >> a >> b >> c >> d; if (c > d) c ^= d ^= c ^= d; a -= b; ans = 0; x[0] = 0, x[1] = c, x[2] = d; ans |= cek(); x[0] = 0, x[1] = c, x[2] = c + d; ans |= cek(); x[0] = 0, x[1] = d, x[2] = c + d; ans |= cek(); x[0] = 0, x[1] = c - d, x[2] = c; ans |= cek(); x[0] = 0, x[1] = d - c, x[2] = d; ans |= cek(); if (ans) cout << yes n ; else cout << no n ; } return 0; } |
#include <bits/stdc++.h> inline int sbt(int x) { return __builtin_popcount(x); } using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } int main() { cin.sync_with_stdio(false); cout.sync_with_stdio(false); int t; cin >> t; while (t--) { int n, x, y, d; int res = 1000000007; cin >> n >> x >> y >> d; int dff = abs(x - y); if (!(dff % d)) res = min(res, dff / d); if (!((y - 1) % d)) res = min(res, (y - 1) / d + (x - 1) / d + (((x - 1) % d) > 0)); if (!((n - y) % d)) res = min(res, (n - x) / d + (n - y) / d + (((n - x) % d) > 0)); if (res == 1000000007) cout << -1; else cout << res; cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int T; cin >> T; while (T--) { int result = 0; int a[105]; int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] - result - i > 0) { result += a[i] - result - i; } } cout << result << endl; } return 0; } |
#include <cmath> #include <algorithm> #include <iostream> #include <string> #include <vector> using namespace std; typedef long double ld; typedef vector<int> vi; typedef long long ll; constexpr ld EPS = numeric_limits<ld>::epsilon(); constexpr int INF = numeric_limits<int>::max() - 10; constexpr ll LINF = numeric_limits<ll>::max() - 10; int w; int h; int n; void input() { cin >> w >> h >> n; } void solve() { int alpha = (w & -w); int beta = (h & -h); string ans = NO ; if (alpha * beta >= n) ans = YES ; cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.precision(16); cout << fixed; int _times = 1; #ifdef _DEBUG freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif cin >> _times; while (_times--) { input(); solve(); } } |
#include <bits/stdc++.h> using namespace std; const long long MAX = 9999999999999999; int t, n; vector<long long> ans; vector<long long> graphSize; vector<long long> aToFirst, aToLast, bToFirst, bToLast; void countLength(vector<long long> &toFirst, vector<long long> &toLast, long long v, int n) { if (n == 0) { toFirst[0] = 0; toLast[0] = 0; return; } if (n == 1) { toFirst[1] = v == 2; toLast[1] = v == 1; return; } if (v <= graphSize[n - 1]) { countLength(toFirst, toLast, v, n - 1); toFirst[n] = min(toFirst[n - 1], toLast[n - 1] + 2); toLast[n] = min(toFirst[n - 1], toLast[n - 1]) + (n - 1) / 2 + 1; } else { countLength(toFirst, toLast, v - graphSize[n - 1], n - 2); toFirst[n] = toFirst[n - 2] + 1; toLast[n] = toLast[n - 2]; } } long long findMinLength(long long a, long long b, int n) { if (a == b) return 0; if (n <= 2) return 1; if (a <= graphSize[n - 1]) { if (b >= graphSize[n - 1] + 1) { return min(aToFirst[n - 1], aToLast[n - 1]) + bToFirst[n - 2] + 1; } else { long long d1 = min(aToFirst[n - 1] + bToLast[n - 1] + 2, aToLast[n - 1] + bToFirst[n - 1] + 2); return min(d1, findMinLength(a, b, n - 1)); } } else { return findMinLength(a - graphSize[n - 1], b - graphSize[n - 1], n - 2); } } int main() { cin >> t >> n; graphSize.push_back(1); graphSize.push_back(2); int iMax = 2; for (; graphSize.back() < MAX; ++iMax) { graphSize.push_back(graphSize[iMax - 1] + graphSize[iMax - 2]); } for (int i = 1; i <= t; ++i) { long long a, b; cin >> a >> b; if (a > b) swap(a, b); aToFirst.resize(min(n, iMax) + 1); aToLast.resize(min(n, iMax) + 1); bToFirst.resize(min(n, iMax) + 1); bToLast.resize(min(n, iMax) + 1); countLength(aToFirst, aToLast, a, min(n, iMax)); countLength(bToFirst, bToLast, b, min(n, iMax)); ans.push_back(findMinLength(a, b, min(n, iMax))); } for (int i = 0; i < ans.size(); ++i) { cout << ans[i] << endl; } return 0; } |
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
// $Revision: #8 $
// $Date: 2009/02/18 $
// $Author: pscheidt $
//-----------------------------------------------------------------------------
//
// File: altera_std_synchronizer_nocut.v
//
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
// as altera_std_synchronizer.v, except that the embedded false
// path constraint is removed in this module. If you use this
// module, you will have to apply the appropriate timing
// constraints.
//
// We expect to make this a standard Quartus atom eventually.
//
// Composed of two or more flip flops connected in series.
// Random metastable condition is simulated when the
// __ALTERA_STD__METASTABLE_SIM macro is defined.
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
// on the Verilog simulator compiler command line to
// enable this mode. In addition, define the macro
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
// with every metastable event generated in the synchronizer.
//
// Copyright (C) Altera Corporation 2009, All Rights Reserved
//-----------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_std_synchronizer_nocut (
clk,
reset_n,
din,
dout
);
parameter depth = 3; // This value must be >= 2 !
input clk;
input reset_n;
input din;
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip-flops with synchronizer flip-flops.
// QuartusII TimeQuest directives:
// 1. Identify all flip-flops in this module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= 1'b0;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { for (int t = 0; t < n - 1; t++) { if (a[t] > a[t + 1]) { int j = t + 1; cout << t + 1 << << j + 1 << endl; int q = a[t]; a[t] = a[j]; a[j] = q; } } } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o2111ai (
Y ,
A1,
A2,
B1,
C1,
D1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, B1, D1, or0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; mt19937 rng(std::chrono::duration_cast<std::chrono::nanoseconds>( chrono::high_resolution_clock::now().time_since_epoch()) .count()); const long long int N = 20005; const long long int LG = 22; long long int n, m; long long int power(long long int x, long long int y, long long int m) { if (y == 0) return 1; long long int p = power(x, y / 2, m) % m; p = (p * p) % m; return (y % 2 == 0) ? p : (x * p) % m; } long long int fact[N], ifact[N]; void proecss() { fact[0] = 1; for (long long int i = 1; i < N; i++) fact[i] = (fact[i - 1] * i) % 1000000007; for (long long int i = 0; i < N; i++) ifact[i] = power(fact[i], 1000000007 - 2, 1000000007); } long long int nCr(long long int n, long long int r) { if (r > n) return 0; if (r == n) return 1; long long int ans = (ifact[n - r] * ifact[r]) % 1000000007; ans = (ans * fact[n]) % 1000000007; return ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); proecss(); cin >> n >> m; long long int b[n + 5], a[n + 5]; for (long long int i = 1; i <= n; i++) { long long int nn = n - i + 1; long long int rr = m - 1; b[i] = nCr(nn + rr - 1, rr); a[i] = nCr(i + rr - 1, rr); } for (long long int i = n - 1; i >= 1; i--) b[i] += b[i + 1], b[i] %= 1000000007; long long int ans = 0; for (long long int i = 1; i <= n; i++) { ans = (ans + (a[i] * b[i]) % 1000000007) % 1000000007; } cout << ans << endl; return 0; } |
/*
Map input Virtual Address to output address.
VA's are 48-bit (high 16 bits unused).
Output ("hardware") address space is 40 bits.
80xx_xxxx_xxxx maps exactly from input->output.
Input and Output is 64 bits mostly to facilitate get/set registers.
Page size is 12 bits.
*/
parameter[2:0] TLB_OPMODE_NONE = 3'h00; //do nothing
parameter[2:0] TLB_OPMODE_LOOKUP = 3'h01; //lookup memory address
parameter[2:0] TLB_OPMODE_GETREG = 3'h02; //get MMU register
parameter[2:0] TLB_OPMODE_SETREG = 3'h03; //set MMU register
parameter[2:0] TLB_OPMODE_LDTLB = 3'h04; //load TLB entry
module MemTLB(
/* verilator lint_off UNUSED */
clk,
reset,
opMode,
opReg,
inAddr,
outAddr,
outTlbSr
);
input clk;
input reset;
input[2:0] opMode;
input[2:0] opReg;
input[63:0] inAddr;
output[63:0] outAddr;
output[7:0] outTlbSr;
reg[63:0] tOutAddr;
reg[7:0] tHashIdx0;
reg[5:0] tHashIdx;
reg[35:0] tlbPageSrcA[63:0]; //source addresses
reg[35:0] tlbPageSrcB[63:0];
reg[35:0] tlbPageSrcC[63:0];
reg[35:0] tlbPageSrcD[63:0];
reg[27:0] tlbPageDstA[63:0]; //dest addresses
reg[27:0] tlbPageDstB[63:0];
reg[27:0] tlbPageDstC[63:0];
reg[27:0] tlbPageDstD[63:0];
reg[63:0] regPTEH;
reg[63:0] regPTEL;
reg[63:0] regTTB;
reg[63:0] regTEA;
reg[63:0] regMMUCR;
reg[63:0] regNextPTEH;
reg[63:0] regNextPTEL;
reg[63:0] regNextTTB;
reg[63:0] regNextTEA;
reg[63:0] regNextMMUCR;
reg[7:0] tTlbSr;
reg tlbMiss;
reg[2:0] tlbSwap;
reg[35:0] tlbSwapSrcA; //source addresses
reg[35:0] tlbSwapSrcB;
reg[35:0] tlbSwapSrcC;
reg[35:0] tlbSwapSrcD;
reg[27:0] tlbSwapDstA; //dest addresses
reg[27:0] tlbSwapDstB;
reg[27:0] tlbSwapDstC;
reg[27:0] tlbSwapDstD;
reg[35:0] tlbSwapSrcE;
reg[27:0] tlbSwapDstE;
assign outAddr = tOutAddr;
assign outTlbSr = tTlbSr;
always @ (opMode)
begin
tlbMiss = 0;
tlbSwap = 0;
tTlbSr = 0;
regNextPTEH = regPTEH;
regNextPTEL = regPTEL;
regNextTTB = regTTB;
regNextTEA = regTEA;
regNextMMUCR = regMMUCR;
if(opMode==TLB_OPMODE_NONE)
begin
tlbMiss = 0;
end
else
if(opMode==TLB_OPMODE_LOOKUP)
begin
tHashIdx0=
inAddr[19:12]+inAddr[26:19]+
inAddr[33:26]+inAddr[40:33]+
inAddr[47:40]+3;
tHashIdx=tHashIdx0[7:2];
tlbMiss = 1;
tlbSwapSrcA=tlbPageSrcA[tHashIdx];
tlbSwapDstA=tlbPageDstA[tHashIdx];
tlbSwapSrcB=tlbPageSrcB[tHashIdx];
tlbSwapDstB=tlbPageDstB[tHashIdx];
tlbSwapSrcC=tlbPageSrcC[tHashIdx];
tlbSwapDstC=tlbPageDstC[tHashIdx];
tlbSwapSrcD=tlbPageSrcD[tHashIdx];
tlbSwapDstD=tlbPageDstD[tHashIdx];
if((inAddr[47:40]==8'h80) ||
(regMMUCR[0]==0) ||
(inAddr[61]!=inAddr[63]))
begin
tOutAddr[63:40] = 0;
tOutAddr[39: 0] = inAddr[39:0];
tlbMiss = 0;
end
else
begin
if(inAddr[47:12]==tlbSwapSrcA[35: 0])
begin
tOutAddr[63:40] = 0;
tOutAddr[39:12] = tlbSwapDstA[27: 0];
tOutAddr[11: 0] = inAddr [11: 0];
tlbMiss = 0;
tlbSwap = 0;
end
else if(inAddr[47:12]==tlbSwapSrcB[35: 0])
begin
tOutAddr[63:40] = 0;
tOutAddr[39:12] = tlbSwapDstB[27: 0];
tOutAddr[11: 0] = inAddr [11: 0];
tlbMiss = 0;
tlbSwap = 1;
end
else if(inAddr[47:12]==tlbSwapSrcC[35: 0])
begin
tOutAddr[63:40] = 0;
tOutAddr[39:12] = tlbSwapDstC[27: 0];
tOutAddr[11: 0] = inAddr [11: 0];
tlbMiss = 0;
tlbSwap = 2;
end
else if(inAddr[47:12]==tlbSwapSrcD[35: 0])
begin
tOutAddr[63:40] = 0;
tOutAddr[39:12] = tlbSwapDstD[27: 0];
tOutAddr[11: 0] = inAddr [11: 0];
tlbMiss = 0;
tlbSwap = 3;
end
end
end
else
if(opMode==TLB_OPMODE_GETREG)
begin
case(opReg)
3'h0:
begin
tOutAddr = 0;
tlbMiss = 0;
end
3'h1:
begin
tOutAddr = regPTEH;
tlbMiss = 0;
end
3'h2:
begin
tOutAddr = regPTEL;
tlbMiss = 0;
end
3'h3:
begin
tOutAddr = regTTB;
tlbMiss = 0;
end
3'h4:
begin
tOutAddr = regTEA;
tlbMiss = 0;
end
3'h5:
begin
tOutAddr = regMMUCR;
tlbMiss = 0;
end
default:
begin
tOutAddr = 0;
tlbMiss = 1;
end
endcase
end
else
if(opMode==TLB_OPMODE_SETREG)
begin
case(opReg)
3'h0:
begin
tOutAddr = 0;
tlbMiss = 0;
end
3'h1:
begin
regNextPTEH = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
3'h2:
begin
regNextPTEL = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
3'h3:
begin
regNextTTB = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
3'h4:
begin
regNextTEA = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
3'h5:
begin
regNextMMUCR = inAddr;
tOutAddr = 0;
tlbMiss = 0;
end
default:
begin
tOutAddr = 0;
tlbMiss = 1;
end
endcase
end
else
if(opMode==TLB_OPMODE_LDTLB)
begin
tHashIdx0=
regPTEH[19:12]+regPTEH[26:19]+
regPTEH[33:26]+regPTEH[40:33]+
regPTEH[47:40]+3;
tHashIdx=tHashIdx0[7:2];
tlbSwapSrcE[35:0] = regPTEH[47:12];
tlbSwapDstE[27:0] = regPTEL[39:12];
tlbSwap = 4;
end
tTlbSr[0] = tlbMiss;
end
always @ (posedge clk)
begin
regPTEH <= regNextPTEH;
regPTEL <= regNextPTEL;
regTTB <= regNextTTB;
regTEA <= regNextTEA;
regMMUCR <= regNextMMUCR;
case(tlbSwap)
0: begin end
1: begin
tlbPageSrcA[tHashIdx] <= tlbSwapSrcB;
tlbPageDstA[tHashIdx] <= tlbSwapDstB;
tlbPageSrcB[tHashIdx] <= tlbSwapSrcA;
tlbPageDstB[tHashIdx] <= tlbSwapDstA;
end
2: begin
tlbPageSrcB[tHashIdx] <= tlbSwapSrcC;
tlbPageDstB[tHashIdx] <= tlbSwapDstC;
tlbPageSrcC[tHashIdx] <= tlbSwapSrcB;
tlbPageDstC[tHashIdx] <= tlbSwapDstB;
end
3: begin
tlbPageSrcC[tHashIdx] <= tlbSwapSrcD;
tlbPageDstC[tHashIdx] <= tlbSwapDstD;
tlbPageSrcD[tHashIdx] <= tlbSwapSrcC;
tlbPageDstD[tHashIdx] <= tlbSwapDstC;
end
4: begin
tlbPageSrcD[tHashIdx] <= tlbSwapSrcE;
tlbPageDstD[tHashIdx] <= tlbSwapDstE;
end
default: begin end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T a, T b) { if (a == 0) return b; return gcd(b % a, a); } template <typename T> T pow(T a, T b, long long m) { T ans = 1; while (b > 0) { if (b % 2 == 1) ans = (ans * a) % m; b /= 2; a = (a * a) % m; } return ans % m; } const long long N = 1e6 + 5; long long n, m; long long a[N], b[N], x[N], y[N]; map<long long, long long> ans; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (long long i = 1; i <= n; i++) { cin >> a[i] >> x[i]; ans[a[i]] = x[i]; } cin >> m; for (long long i = 1; i <= m; i++) { cin >> b[i] >> y[i]; ans[b[i]] = max(ans[b[i]], y[i]); } long long answer = 0; for (auto it : ans) answer += it.second; cout << answer; return 0; } |
//////////////////////////////////////////////////////////////////////////////////
// d_BCH_encoder_top.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <>
// Ilyong Jung <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Encoder
// Module Name: d_BCH_encoder_top
// File Name: d_BCH_encoder_top.v
//
// Version: v1.0.1-256B_T14
//
// Description:
// - BCH encoder TOP module
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.1
// - minor modification for releasing
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_BCH_encoder_parameters.vh"
`timescale 1ns / 1ps
module d_BCH_encoder_top
(
input wire i_clk,
input wire i_nRESET,
input wire i_exe_encoding, // execute encoding, encoding start command signal
input wire i_message_valid, // message BUS strobe signal
input wire [`D_BCH_ENC_P_LVL-1:0] i_message, // message block data BUS
output reg o_message_ready,
output wire o_encoding_start, // [indicate] encoding start
output wire o_last_m_block_rcvd, // [indicate] last message block received
output wire o_encoding_cmplt, // [indicate] encoding complete
input wire i_parity_ready,
output wire o_parity_valid, // [indicate] parity BUS strobe signal
output wire o_parity_out_start, // [indicate] parity block out start
output wire o_parity_out_cmplt, // [indicate] last parity block transmitted
output wire [`D_BCH_ENC_P_LVL-1:0] o_parity_out // parity block data BUS
);
parameter D_BCH_ENC_FSM_BIT = 7;
parameter RESET = 7'b0000001; // RESET: encoder sequence reset
parameter ENCD_ST = 7'b0000010; // encoder: start mode, compute parity
parameter ENCD_FB = 7'b0000100;
parameter P_O_STR = 7'b0001000; // encoder: feedback mode, compute parity
parameter P_O_STBY = 7'b0010000; // parity out: first block
parameter P_O_SHF = 7'b0100000; // parity out: shifted block
parameter MSG_T_P = 7'b1000000; // encoder: message transmit paused (message BUS invalid)
// registered input
reg [`D_BCH_ENC_P_LVL-1:0] r_message_b;
// encoder FSM state
reg [D_BCH_ENC_FSM_BIT-1:0] r_cur_state;
reg [D_BCH_ENC_FSM_BIT-1:0] r_nxt_state;
// internal counter
reg [`D_BCH_ENC_I_CNT_BIT-1:0] r_counter;
// registers for parity code
reg [`D_BCH_ENC_PRT_LENGTH-1:0] r_parity_code;
wire [`D_BCH_ENC_PRT_LENGTH-1:0] w_nxt_parity_code;
wire w_valid_execution;
////////////////////////////////////////////////////////////////////////////////
// modified(improved) linear feedback shift XOR matrix
// LFSR = LFSXOR + register
d_parallel_m_lfs_XOR d_mLFSXOR_matrix (
.i_message (r_message_b),
.i_cur_parity(r_parity_code),
.o_nxt_parity(w_nxt_parity_code));
////////////////////////////////////////////////////////////////////////////////
// generate control/indicate signal
assign w_valid_execution = i_exe_encoding & i_message_valid;
assign o_encoding_start = (r_cur_state == ENCD_ST);
assign o_last_m_block_rcvd = (i_message_valid == 1) & (r_counter == `D_BCH_ENC_I_CNT-1);
assign o_encoding_cmplt = (r_counter == `D_BCH_ENC_I_CNT);
assign o_parity_valid = (r_cur_state == P_O_STR) | (r_cur_state == P_O_SHF) | (r_cur_state == P_O_STBY);
assign o_parity_out_start = (r_cur_state == P_O_STR);
assign o_parity_out_cmplt = ((r_cur_state == P_O_SHF) | (r_cur_state == P_O_STBY)) & (r_counter == `D_BCH_ENC_O_CNT-1) & (i_parity_ready & o_parity_valid);
// parity output
assign o_parity_out = (o_parity_valid)? r_parity_code[`D_BCH_ENC_PRT_LENGTH-1 : `D_BCH_ENC_PRT_LENGTH-`D_BCH_ENC_P_LVL]:0;
// update current state to next state
always @ (posedge i_clk, negedge i_nRESET)
begin
if (!i_nRESET) begin
r_cur_state <= RESET;
end else begin
r_cur_state <= r_nxt_state;
end
end
// decide next state
always @ ( * )
begin
case (r_cur_state)
RESET: begin
r_nxt_state <= (w_valid_execution)? (ENCD_ST):(RESET);
end
ENCD_ST: begin
r_nxt_state <= (i_message_valid)? (ENCD_FB):(MSG_T_P);
end
ENCD_FB: begin
r_nxt_state <= (o_encoding_cmplt)? (P_O_STR):
((i_message_valid)? (ENCD_FB):(MSG_T_P));
end
P_O_STR: begin
r_nxt_state <= (!i_parity_ready) ? (P_O_STBY) : (P_O_SHF);
end
P_O_SHF: begin
r_nxt_state <= (!i_parity_ready) ? (P_O_STBY):((o_parity_out_cmplt) ? (RESET) : (P_O_SHF));//((w_valid_execution)? (ENCD_ST):(RESET)):(P_O_SHF));
end
MSG_T_P: begin
r_nxt_state <= (i_message_valid)? (ENCD_FB):(MSG_T_P);
end
P_O_STBY: begin
r_nxt_state <= (i_parity_ready)?((o_parity_out_cmplt) ? /*((w_valid_execution)? (ENCD_ST):(RESET))*/(RESET) : (P_O_SHF)) : (P_O_STBY);
end
default: begin
r_nxt_state <= RESET;
end
endcase
end
always @ (posedge i_clk, negedge i_nRESET)
begin
if (!i_nRESET)
o_message_ready <= 1;
else
case (r_nxt_state)
RESET:
o_message_ready <= 1;
ENCD_FB:
o_message_ready <= (o_last_m_block_rcvd) ? 0 : 1;
endcase
end
// state behaviour
always @ (posedge i_clk, negedge i_nRESET)
begin
if (!i_nRESET) begin
r_counter <= 0;
r_message_b <= 0;
r_parity_code <= 0;
end
else begin
case (r_nxt_state)
RESET: begin
r_counter <= 0;
r_message_b <= 0;
r_parity_code <= 0;
end
ENCD_ST: begin
r_counter <= 1;
r_message_b <= i_message;
r_parity_code <= 0;
end
ENCD_FB: begin
r_counter <= r_counter + 1'b1;
r_message_b <= i_message;
r_parity_code <= w_nxt_parity_code;
end
P_O_STR: begin
r_counter <= 0;
r_message_b <= 0;
r_parity_code <= w_nxt_parity_code;
end
P_O_SHF: begin
r_counter <= r_counter + 1'b1;
r_message_b <= 0;
r_parity_code <= r_parity_code << `D_BCH_ENC_P_LVL;
end
MSG_T_P: begin
r_counter <= r_counter;
r_message_b <= r_message_b;
r_parity_code <= r_parity_code;
end
P_O_STBY: begin
r_counter <= r_counter;
r_message_b <= 0;
r_parity_code <= r_parity_code;
end
default: begin
r_counter <= 0;
r_message_b <= 0;
r_parity_code <= 0;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> double DIS(T va, T vb) { return sqrt((double)(va.x - vb.x) * (va.x - vb.x) + (va.y - vb.y) * (va.y - vb.y)); } template <class T> inline T INT_LEN(T v) { int len = 1; while (v /= 10) ++len; return len; } char ar[100005], br[100005]; bool cmp(char va, char vb) { return va > vb; } void solve(char *s, char *s2) { int n = (int)strlen(s); int m = (int)strlen(s2); sort(s2, s2 + m, cmp); int i, j; for (i = j = 0; i < n && j < m; i++) { if (s[i] < s2[j]) { s[i] = s2[j]; j++; } } puts(s); } int main(void) { while (2 == scanf( %s%s , ar, br)) { solve(ar, br); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [9:0] index;
wire [7:0] index0 = index[7:0] + 8'h0;
wire [7:0] index1 = index[7:0] + 8'h1;
wire [7:0] index2 = index[7:0] + 8'h2;
wire [7:0] index3 = index[7:0] + 8'h3;
wire [7:0] index4 = index[7:0] + 8'h4;
wire [7:0] index5 = index[7:0] + 8'h5;
wire [7:0] index6 = index[7:0] + 8'h6;
wire [7:0] index7 = index[7:0] + 8'h7;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [9:0] outa0; // From s0 of t_case_huge_sub.v
wire [9:0] outa1; // From s1 of t_case_huge_sub.v
wire [9:0] outa2; // From s2 of t_case_huge_sub.v
wire [9:0] outa3; // From s3 of t_case_huge_sub.v
wire [9:0] outa4; // From s4 of t_case_huge_sub.v
wire [9:0] outa5; // From s5 of t_case_huge_sub.v
wire [9:0] outa6; // From s6 of t_case_huge_sub.v
wire [9:0] outa7; // From s7 of t_case_huge_sub.v
wire [1:0] outb0; // From s0 of t_case_huge_sub.v
wire [1:0] outb1; // From s1 of t_case_huge_sub.v
wire [1:0] outb2; // From s2 of t_case_huge_sub.v
wire [1:0] outb3; // From s3 of t_case_huge_sub.v
wire [1:0] outb4; // From s4 of t_case_huge_sub.v
wire [1:0] outb5; // From s5 of t_case_huge_sub.v
wire [1:0] outb6; // From s6 of t_case_huge_sub.v
wire [1:0] outb7; // From s7 of t_case_huge_sub.v
wire outc0; // From s0 of t_case_huge_sub.v
wire outc1; // From s1 of t_case_huge_sub.v
wire outc2; // From s2 of t_case_huge_sub.v
wire outc3; // From s3 of t_case_huge_sub.v
wire outc4; // From s4 of t_case_huge_sub.v
wire outc5; // From s5 of t_case_huge_sub.v
wire outc6; // From s6 of t_case_huge_sub.v
wire outc7; // From s7 of t_case_huge_sub.v
wire [9:0] outq; // From q of t_case_huge_sub4.v
wire [3:0] outr; // From sub3 of t_case_huge_sub3.v
wire [9:0] outsmall; // From sub2 of t_case_huge_sub2.v
// End of automatics
t_case_huge_sub2 sub2 (
// Outputs
.outa (outsmall[9:0]),
/*AUTOINST*/
// Inputs
.index (index[9:0]));
t_case_huge_sub3 sub3 (/*AUTOINST*/
// Outputs
.outr (outr[3:0]),
// Inputs
.clk (clk),
.index (index[9:0]));
/* t_case_huge_sub AUTO_TEMPLATE (
.outa (outa@[]),
.outb (outb@[]),
.outc (outc@[]),
.index (index@[]));
*/
t_case_huge_sub s0 (/*AUTOINST*/
// Outputs
.outa (outa0[9:0]), // Templated
.outb (outb0[1:0]), // Templated
.outc (outc0), // Templated
// Inputs
.index (index0[7:0])); // Templated
t_case_huge_sub s1 (/*AUTOINST*/
// Outputs
.outa (outa1[9:0]), // Templated
.outb (outb1[1:0]), // Templated
.outc (outc1), // Templated
// Inputs
.index (index1[7:0])); // Templated
t_case_huge_sub s2 (/*AUTOINST*/
// Outputs
.outa (outa2[9:0]), // Templated
.outb (outb2[1:0]), // Templated
.outc (outc2), // Templated
// Inputs
.index (index2[7:0])); // Templated
t_case_huge_sub s3 (/*AUTOINST*/
// Outputs
.outa (outa3[9:0]), // Templated
.outb (outb3[1:0]), // Templated
.outc (outc3), // Templated
// Inputs
.index (index3[7:0])); // Templated
t_case_huge_sub s4 (/*AUTOINST*/
// Outputs
.outa (outa4[9:0]), // Templated
.outb (outb4[1:0]), // Templated
.outc (outc4), // Templated
// Inputs
.index (index4[7:0])); // Templated
t_case_huge_sub s5 (/*AUTOINST*/
// Outputs
.outa (outa5[9:0]), // Templated
.outb (outb5[1:0]), // Templated
.outc (outc5), // Templated
// Inputs
.index (index5[7:0])); // Templated
t_case_huge_sub s6 (/*AUTOINST*/
// Outputs
.outa (outa6[9:0]), // Templated
.outb (outb6[1:0]), // Templated
.outc (outc6), // Templated
// Inputs
.index (index6[7:0])); // Templated
t_case_huge_sub s7 (/*AUTOINST*/
// Outputs
.outa (outa7[9:0]), // Templated
.outb (outb7[1:0]), // Templated
.outc (outc7), // Templated
// Inputs
.index (index7[7:0])); // Templated
t_case_huge_sub4 q (/*AUTOINST*/
// Outputs
.outq (outq[9:0]),
// Inputs
.index (index[7:0]));
integer cyc; initial cyc=1;
initial index = 10'h0;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%x: %x\n",cyc,outr);
//$write("%x: %x %x %x %x\n", cyc, outa1,outb1,outc1,index1);
if (cyc==1) begin
index <= 10'h236;
end
if (cyc==2) begin
index <= 10'h022;
if (outsmall != 10'h282) $stop;
if (outr != 4'b0) $stop;
if ({outa0,outb0,outc0}!={10'h282,2'd3,1'b0}) $stop;
if ({outa1,outb1,outc1}!={10'h21c,2'd3,1'b1}) $stop;
if ({outa2,outb2,outc2}!={10'h148,2'd0,1'b1}) $stop;
if ({outa3,outb3,outc3}!={10'h3c0,2'd2,1'b0}) $stop;
if ({outa4,outb4,outc4}!={10'h176,2'd1,1'b1}) $stop;
if ({outa5,outb5,outc5}!={10'h3fc,2'd2,1'b1}) $stop;
if ({outa6,outb6,outc6}!={10'h295,2'd3,1'b1}) $stop;
if ({outa7,outb7,outc7}!={10'h113,2'd2,1'b1}) $stop;
if (outq != 10'h001) $stop;
end
if (cyc==3) begin
index <= 10'h165;
if (outsmall != 10'h191) $stop;
if (outr != 4'h5) $stop;
if ({outa1,outb1,outc1}!={10'h379,2'd1,1'b0}) $stop;
if ({outa2,outb2,outc2}!={10'h073,2'd0,1'b0}) $stop;
if ({outa3,outb3,outc3}!={10'h2fd,2'd3,1'b1}) $stop;
if ({outa4,outb4,outc4}!={10'h2e0,2'd3,1'b1}) $stop;
if ({outa5,outb5,outc5}!={10'h337,2'd1,1'b1}) $stop;
if ({outa6,outb6,outc6}!={10'h2c7,2'd3,1'b1}) $stop;
if ({outa7,outb7,outc7}!={10'h19e,2'd3,1'b0}) $stop;
if (outq != 10'h001) $stop;
end
if (cyc==4) begin
index <= 10'h201;
if (outsmall != 10'h268) $stop;
if (outr != 4'h2) $stop;
if ({outa1,outb1,outc1}!={10'h111,2'd1,1'b0}) $stop;
if ({outa2,outb2,outc2}!={10'h1f9,2'd0,1'b0}) $stop;
if ({outa3,outb3,outc3}!={10'h232,2'd0,1'b1}) $stop;
if ({outa4,outb4,outc4}!={10'h255,2'd3,1'b0}) $stop;
if ({outa5,outb5,outc5}!={10'h34c,2'd1,1'b1}) $stop;
if ({outa6,outb6,outc6}!={10'h049,2'd1,1'b1}) $stop;
if ({outa7,outb7,outc7}!={10'h197,2'd3,1'b0}) $stop;
if (outq != 10'h001) $stop;
end
if (cyc==5) begin
index <= 10'h3ff;
if (outr != 4'hd) $stop;
if (outq != 10'h001) $stop;
end
if (cyc==6) begin
index <= 10'h0;
if (outr != 4'hd) $stop;
if (outq != 10'h114) $stop;
end
if (cyc==7) begin
if (outr != 4'h4) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; int sz; vector<pair<int, string> > e; int v[2][200009]; int c[200009]; int Call(int in, int count) { if (c[in] != -1) { Call(c[in] - 1, count + 1); } else { int i; printf( n%d , count + 1); } } int Pr(int in) { printf( %d , in + 1); if (c[in] != -1) { Pr(c[in] - 1); c[in] = 0; } else { c[in] = 0; } } int main() { int i, j, k = 0, n = 0, m = 0; cin >> s; sz = s.size(); for (i = 0; i < sz; i++) { if (s[i] - 48 == 0) v[0][n++] = i + 1; else v[1][m++] = i + 1; } int u = 0; for (i = 0, j = 0; i < sz; i++) { if (s[i] - 48 == 0) { if (j == m) c[i] = -1; else if (i + 1 > v[1][j]) return 0 * printf( -1 ); else { c[i] = v[1][j]; j++; } } else { while (i + 1 > v[0][u]) { u++; if (u >= n) return 0 * printf( -1 ); } c[i] = v[0][u]; u++; } } string q; for (i = 0; i < sz; i++) if (c[i] == -1) k++; printf( %d , k); for (i = 0; i < sz; i++) { q = i + 1 + 48; if (c[i] == -1) printf( n1 %d , i + 1); else if (c[i] != 0) { Call(i, 0); Pr(i); } } } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Mon Apr 03 17:46:36 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/andrewandre/Documents/GitHub/axiplasma/hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0_stub.v
// Design : mig_wrap_mig_7series_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module mig_wrap_mig_7series_0_0(ddr3_dq, ddr3_dqs_n, ddr3_dqs_p, ddr3_addr,
ddr3_ba, ddr3_ras_n, ddr3_cas_n, ddr3_we_n, ddr3_reset_n, ddr3_ck_p, ddr3_ck_n, ddr3_cke,
ddr3_cs_n, ddr3_dm, ddr3_odt, sys_clk_p, sys_clk_n, ui_clk, ui_clk_sync_rst, ui_addn_clk_0,
ui_addn_clk_1, ui_addn_clk_2, ui_addn_clk_3, ui_addn_clk_4, mmcm_locked, aresetn,
app_sr_active, app_ref_ack, app_zq_ack, s_axi_awid, s_axi_awaddr, s_axi_awlen, s_axi_awsize,
s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awqos, s_axi_awvalid,
s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid, s_axi_wready,
s_axi_bready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_arid, s_axi_araddr, s_axi_arlen,
s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arqos,
s_axi_arvalid, s_axi_arready, s_axi_rready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast,
s_axi_rvalid, init_calib_complete, device_temp, sys_rst)
/* synthesis syn_black_box black_box_pad_pin="ddr3_dq[63:0],ddr3_dqs_n[7:0],ddr3_dqs_p[7:0],ddr3_addr[13:0],ddr3_ba[2:0],ddr3_ras_n,ddr3_cas_n,ddr3_we_n,ddr3_reset_n,ddr3_ck_p[0:0],ddr3_ck_n[0:0],ddr3_cke[0:0],ddr3_cs_n[0:0],ddr3_dm[7:0],ddr3_odt[0:0],sys_clk_p,sys_clk_n,ui_clk,ui_clk_sync_rst,ui_addn_clk_0,ui_addn_clk_1,ui_addn_clk_2,ui_addn_clk_3,ui_addn_clk_4,mmcm_locked,aresetn,app_sr_active,app_ref_ack,app_zq_ack,s_axi_awid[3:0],s_axi_awaddr[29:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[511:0],s_axi_wstrb[63:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bready,s_axi_bid[3:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_arid[3:0],s_axi_araddr[29:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rready,s_axi_rid[3:0],s_axi_rdata[511:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,init_calib_complete,device_temp[11:0],sys_rst" */;
inout [63:0]ddr3_dq;
inout [7:0]ddr3_dqs_n;
inout [7:0]ddr3_dqs_p;
output [13:0]ddr3_addr;
output [2:0]ddr3_ba;
output ddr3_ras_n;
output ddr3_cas_n;
output ddr3_we_n;
output ddr3_reset_n;
output [0:0]ddr3_ck_p;
output [0:0]ddr3_ck_n;
output [0:0]ddr3_cke;
output [0:0]ddr3_cs_n;
output [7:0]ddr3_dm;
output [0:0]ddr3_odt;
input sys_clk_p;
input sys_clk_n;
output ui_clk;
output ui_clk_sync_rst;
output ui_addn_clk_0;
output ui_addn_clk_1;
output ui_addn_clk_2;
output ui_addn_clk_3;
output ui_addn_clk_4;
output mmcm_locked;
input aresetn;
output app_sr_active;
output app_ref_ack;
output app_zq_ack;
input [3:0]s_axi_awid;
input [29:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [511:0]s_axi_wdata;
input [63:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
input s_axi_bready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input [3:0]s_axi_arid;
input [29:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
input s_axi_rready;
output [3:0]s_axi_rid;
output [511:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
output init_calib_complete;
output [11:0]device_temp;
input sys_rst;
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module reads and writes data to the RS232 connector on Altera's *
* DE-series Development and Education Boards. *
* *
******************************************************************************/
module nios_system_rs232_0 (
// Inputs
clk,
reset,
address,
chipselect,
byteenable,
read,
write,
writedata,
UART_RXD,
// Bidirectionals
// Outputs
irq,
readdata,
UART_TXD
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 434;
parameter HALF_BAUD_TICK_COUNT = 217;
parameter TDW = 10; // Total data width
parameter DW = 8; // Data width
parameter ODD_PARITY = 1'b0;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input address;
input chipselect;
input [ 3: 0] byteenable;
input read;
input write;
input [31: 0] writedata;
input UART_RXD;
// Bidirectionals
// Outputs
output reg irq;
output reg [31: 0] readdata;
output UART_TXD;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire read_fifo_read_en;
wire [ 7: 0] read_available;
wire read_data_valid;
wire [(DW-1):0] read_data;
wire parity_error;
wire write_data_parity;
wire [ 7: 0] write_space;
// Internal Registers
reg read_interrupt_en;
reg write_interrupt_en;
reg read_interrupt;
reg write_interrupt;
reg write_fifo_write_en;
reg [(DW-1):0] data_to_uart;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
irq <= 1'b0;
else
irq <= write_interrupt | read_interrupt;
end
always @(posedge clk)
begin
if (reset)
readdata <= 32'h00000000;
else if (chipselect)
begin
if (address == 1'b0)
readdata <=
{8'h00,
read_available,
read_data_valid,
5'h00,
parity_error,
1'b0,
read_data[(DW - 1):0]};
else
readdata <=
{8'h00,
write_space,
6'h00,
write_interrupt,
read_interrupt,
6'h00,
write_interrupt_en,
read_interrupt_en};
end
end
always @(posedge clk)
begin
if (reset)
read_interrupt_en <= 1'b0;
else if ((chipselect) && (write) && (address) && (byteenable[0]))
read_interrupt_en <= writedata[0];
end
always @(posedge clk)
begin
if (reset)
write_interrupt_en <= 1'b0;
else if ((chipselect) && (write) && (address) && (byteenable[0]))
write_interrupt_en <= writedata[1];
end
always @(posedge clk)
begin
if (reset)
read_interrupt <= 1'b0;
else if (read_interrupt_en == 1'b0)
read_interrupt <= 1'b0;
else
read_interrupt <= (&(read_available[6:5]) | read_available[7]);
end
always @(posedge clk)
begin
if (reset)
write_interrupt <= 1'b0;
else if (write_interrupt_en == 1'b0)
write_interrupt <= 1'b0;
else
write_interrupt <= (&(write_space[6:5]) | write_space[7]);
end
always @(posedge clk)
begin
if (reset)
write_fifo_write_en <= 1'b0;
else
write_fifo_write_en <=
chipselect & write & ~address & byteenable[0];
end
always @(posedge clk)
begin
if (reset)
data_to_uart <= 'h0;
else
data_to_uart <= writedata[(DW - 1):0];
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign parity_error = 1'b0;
assign read_fifo_read_en = chipselect & read & ~address & byteenable[0];
assign write_data_parity = (^(data_to_uart)) ^ ODD_PARITY;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_in_deserializer RS232_In_Deserializer (
// Inputs
.clk (clk),
.reset (reset),
.serial_data_in (UART_RXD),
.receive_data_en (read_fifo_read_en),
// Bidirectionals
// Outputs
.fifo_read_available (read_available),
.received_data_valid (read_data_valid),
.received_data (read_data)
);
defparam
RS232_In_Deserializer.CW = CW,
RS232_In_Deserializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_In_Deserializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_In_Deserializer.TDW = TDW,
RS232_In_Deserializer.DW = (DW - 1);
altera_up_rs232_out_serializer RS232_Out_Serializer (
// Inputs
.clk (clk),
.reset (reset),
.transmit_data (data_to_uart),
.transmit_data_en (write_fifo_write_en),
// Bidirectionals
// Outputs
.fifo_write_space (write_space),
.serial_data_out (UART_TXD)
);
defparam
RS232_Out_Serializer.CW = CW,
RS232_Out_Serializer.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Serializer.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Serializer.TDW = TDW,
RS232_Out_Serializer.DW = (DW - 1);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NOR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__NOR3_PP_BLACKBOX_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nor3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NOR3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> a, b; int n, m; cin >> n; for (int i = 0; i < n; i++) { int tmp; cin >> tmp; a.push_back(tmp); } cin >> m; for (int i = 0; i < m; i++) { int tmp; cin >> tmp; b.push_back(tmp); } sort(a.begin(), a.end()); sort(b.begin(), b.end()); int a3 = 0, b3 = 0; for (int i = a.size() - 1; i >= 0; i--) { int l = 0, r = m; while (l < r) { int mid = (l + r) / 2; if (b[mid] >= a[i]) { r = mid; } else l = mid + 1; } if ((n - i) - (m - l) >= (a3 - b3)) { a3 = n - i; b3 = m - l; } } cout << a3 * 3 + (n - a3) * 2 << : << b3 * 3 + (m - b3) * 2 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, p; int tot, head[100010], next1[100010 << 1], to[100010 << 1]; int deep[100010], cnt[100010]; void add(int x, int y) { to[++tot] = y; next1[tot] = head[x]; head[x] = tot; } void dfs(int x, int f) { deep[x] = deep[f] + 1; cnt[deep[x]]++; for (int i = head[x]; i; i = next1[i]) { int y = to[i]; if (y == f) continue; dfs(y, x); } } int main() { scanf( %d%d%d , &n, &k, &p); for (int i = 1; i < n; i++) { int x, y; scanf( %d%d , &x, &y); add(x, y); add(y, x); } dfs(1, 0); sort(deep + 1, deep + n + 1); int l = 2, r = 2, ans = 1, tmp = 0; while (1) { if (l >= n || r >= n) break; r++; if (deep[r] != deep[r - 1]) tmp += (r - l); while (tmp > p || r - l + 1 > k) { tmp -= (deep[r] - deep[l]); l++; } ans = max(ans, (r - l + 1)); } printf( %d , ans); return 0; } |
//*******************************************************************************************
//Author: Yejoong Kim, Ye-sheng Kuo
//Last Modified: Aug 23 2017
//Description: (Testbench) MBus Node Control for Master Layer
//Update History: Apr 08 2013 - Added glitch reset (Ye-sheng Kuo)
// May 25 2015 - Added double latch for DIN (Ye-sheng Kuo, Yejoong Kim)
// May 21 2016 - Updated for MBus r03 (Yejoong Kim)
// Added "BUS_SWITCH_ROLE: DOUT=1" in "case (bus_state_neg)"
// Changed module name:
// lname_mbus_master_ctrl -> lname_mbus_master_node_ctrl
// Added MBus Watchdog Counter
// Dec 16 2016 - Updated for MBus r04 (Yejoong Kim)
// Added MBus Flag (MSG_INTERRUPTED)
// May 24 2017 - Updated for MBus r04p1 (Yejoong Kim)
// Added FORCE_IDLE_WHEN_DONE to fix DIN sync issue between
// master layer and member layer at the end of message
// that requires a reply.
// Changed some variable names to be consistent with lname_mbus_master_node_ctrl.v
// THRESHOLD -> NUM_BITS_THRESHOLD
// threshold_cnt -> num_bits_threshold_cnt
// next_threshold_cnt -> next_num_bits_threshold_cnt
// Aug 23 2017 - Checked for mbus_testbench
//*******************************************************************************************
`include "include/mbus_def_testbench.v"
module mbus_master_node_ctrl_testbench (
//Input
input CLK_EXT,
input RESETn,
input CIN,
input DIN,
input [`MBUSTB_BITS_WD_WIDTH-1:0] NUM_BITS_THRESHOLD,
//Output
output COUT,
output reg DOUT,
// FSM Configuration
input FORCE_IDLE_WHEN_DONE
);
`include "include/mbus_func_testbench.v"
parameter BUS_IDLE = 0;
parameter BUS_WAIT_START = 3;
parameter BUS_START = 4;
parameter BUS_ARBITRATE = 1;
parameter BUS_PRIO = 2;
parameter BUS_ACTIVE = 5;
parameter BUS_INTERRUPT = 7;
parameter BUS_SWITCH_ROLE = 6;
parameter BUS_CONTROL0 = 8;
parameter BUS_CONTROL1 = 9;
parameter BUS_BACK_TO_IDLE = 10;
parameter NUM_OF_BUS_STATE = 11;
parameter START_CYCLES = 10;
parameter GUARD_BAND_NUM_CYCLES = 20;
parameter BUS_INTERRUPT_COUNTER = 6;
reg [log2(START_CYCLES-1)-1:0] start_cycle_cnt, next_start_cycle_cnt;
reg [log2(NUM_OF_BUS_STATE-1)-1:0] bus_state, next_bus_state, bus_state_neg;
reg [log2(BUS_INTERRUPT_COUNTER-1)-1:0] bus_interrupt_cnt, next_bus_interrupt_cnt;
reg clk_en, next_clk_en;
reg clkin_sampled;
reg [2:0] din_sampled_neg, din_sampled_pos;
reg [`MBUSTB_BITS_WD_WIDTH-1:0] num_bits_threshold_cnt, next_num_bits_threshold_cnt;
reg din_dly_1, din_dly_2;
// DIN double-latch
always @(posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
din_dly_1 <= `MBUSTB_SD 1'b1;
din_dly_2 <= `MBUSTB_SD 1'b1;
end
else if (FORCE_IDLE_WHEN_DONE) begin
if ((bus_state == BUS_IDLE) | (bus_state == BUS_WAIT_START)) begin
din_dly_1 <= `MBUSTB_SD DIN;
din_dly_2 <= `MBUSTB_SD din_dly_1;
end
else begin
din_dly_1 <= `MBUSTB_SD 1'b1;
din_dly_2 <= `MBUSTB_SD 1'b1;
end
end
else begin
din_dly_1 <= `MBUSTB_SD DIN;
din_dly_2 <= `MBUSTB_SD din_dly_1;
end
end
wire [1:0] CONTROL_BITS = `MBUSTB_CONTROL_SEQ; // EOM?, ~ACK?
always @ (posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
bus_state <= `MBUSTB_SD BUS_IDLE;
start_cycle_cnt <= `MBUSTB_SD START_CYCLES - 1'b1;
clk_en <= `MBUSTB_SD 0;
bus_interrupt_cnt <= `MBUSTB_SD BUS_INTERRUPT_COUNTER - 1'b1;
num_bits_threshold_cnt <= `MBUSTB_SD 0;
end
else begin
bus_state <= `MBUSTB_SD next_bus_state;
start_cycle_cnt <= `MBUSTB_SD next_start_cycle_cnt;
clk_en <= `MBUSTB_SD next_clk_en;
bus_interrupt_cnt <= `MBUSTB_SD next_bus_interrupt_cnt;
num_bits_threshold_cnt <= `MBUSTB_SD next_num_bits_threshold_cnt;
end
end
always @* begin
next_bus_state = bus_state;
next_start_cycle_cnt = start_cycle_cnt;
next_clk_en = clk_en;
next_bus_interrupt_cnt = bus_interrupt_cnt;
next_num_bits_threshold_cnt = num_bits_threshold_cnt;
case (bus_state)
BUS_IDLE: begin
if (~din_dly_2) next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = START_CYCLES - 1'b1;
end
BUS_WAIT_START: begin
next_num_bits_threshold_cnt = 0;
if (start_cycle_cnt) next_start_cycle_cnt = start_cycle_cnt - 1'b1;
else begin
if (~din_dly_2) begin
next_clk_en = 1;
next_bus_state = BUS_START;
end
else next_bus_state = BUS_IDLE;
end
end
BUS_START: next_bus_state = BUS_ARBITRATE;
BUS_ARBITRATE: begin
next_bus_state = BUS_PRIO;
if (DIN) next_num_bits_threshold_cnt = NUM_BITS_THRESHOLD; // Glitch, reset bus immediately
end
BUS_PRIO: next_bus_state = BUS_ACTIVE;
BUS_ACTIVE: begin
if ((num_bits_threshold_cnt<NUM_BITS_THRESHOLD)&&(~clkin_sampled))
next_num_bits_threshold_cnt = num_bits_threshold_cnt + 1'b1;
else begin
next_clk_en = 0;
next_bus_state = BUS_INTERRUPT;
end
next_bus_interrupt_cnt = BUS_INTERRUPT_COUNTER - 1'b1;
end
BUS_INTERRUPT: begin
if (bus_interrupt_cnt) next_bus_interrupt_cnt = bus_interrupt_cnt - 1'b1;
else begin
if ({din_sampled_neg, din_sampled_pos}==6'b111_000) begin
next_bus_state = BUS_SWITCH_ROLE;
next_clk_en = 1;
end
end
end
BUS_SWITCH_ROLE: next_bus_state = BUS_CONTROL0;
BUS_CONTROL0: next_bus_state = BUS_CONTROL1;
BUS_CONTROL1: next_bus_state = BUS_BACK_TO_IDLE;
BUS_BACK_TO_IDLE: begin
if (FORCE_IDLE_WHEN_DONE) begin
next_bus_state = BUS_IDLE;
next_clk_en = 0;
end
else begin
if (~DIN) begin
next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = 1;
end
else begin
next_bus_state = BUS_IDLE;
end
next_clk_en = 0;
end
end
endcase
end
always @ (negedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
din_sampled_neg <= `MBUSTB_SD 0;
bus_state_neg <= `MBUSTB_SD BUS_IDLE;
end
else begin
if (bus_state==BUS_INTERRUPT) din_sampled_neg <= `MBUSTB_SD {din_sampled_neg[1:0], DIN};
bus_state_neg <= `MBUSTB_SD bus_state;
end
end
always @ (posedge CLK_EXT or negedge RESETn) begin
if (~RESETn) begin
din_sampled_pos <= `MBUSTB_SD 0;
clkin_sampled <= `MBUSTB_SD 0;
end
else begin
if (bus_state==BUS_INTERRUPT) din_sampled_pos <= `MBUSTB_SD {din_sampled_pos[1:0], DIN};
clkin_sampled <= `MBUSTB_SD CIN;
end
end
assign COUT = (clk_en)? CLK_EXT : 1'b1;
always @* begin
DOUT = DIN;
case (bus_state_neg)
BUS_IDLE: DOUT = 1;
BUS_WAIT_START: DOUT = 1;
BUS_START: DOUT = 1;
BUS_INTERRUPT: DOUT = CLK_EXT;
BUS_SWITCH_ROLE: DOUT = 1;
BUS_CONTROL0: if (num_bits_threshold_cnt==NUM_BITS_THRESHOLD) DOUT = (~CONTROL_BITS[1]);
BUS_BACK_TO_IDLE: DOUT = 1;
endcase
end
endmodule // lname_mbus_master_node_ctrl
|
#include <bits/stdc++.h> using namespace std; bool is_Palindrome(string s) { long long int n = s.size(); for (long long int i = 0; i < n / 2; i++) { if (s[i] != s[n - i - 1]) { return 0; } } return 1; } void solve() { string a; cin >> a; long long int n = a.size(); if (is_Palindrome(a)) { cout << 0 << endl; return; } cout << 3 << endl; cout << L << << 2 << endl << R << << 2 << endl << R << << (2 * n - 1); } void testcase() { int t; cin >> t; while (t--) { solve(); } } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); } |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_128x512a.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 176 10/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_128x512a (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw);
input aclr;
input [127:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [127:0] q;
output rdempty;
output wrfull;
output [8:0] wrusedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "128"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 128 0 INPUT NODEFVAL data[127..0]
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0]
// Retrieval info: CONNECT: @data 0 0 128 0 data 0 0 128 0
// Retrieval info: CONNECT: q 0 0 128 0 @q 0 0 128 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_128x512a_wave*.jpg FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD1_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD1_PP_BLACKBOX_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlygate4sd1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD1_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> inline void chmin(A &a, B b) { if (a > b) a = b; } template <typename A, typename B> inline void chmax(A &a, B b) { if (a < b) a = b; } struct Dinic { struct edge { long long to, cap, rev; edge(long long to, long long cap, long long rev) : to(to), cap(cap), rev(rev) {} }; const long long INF = 1001001001; vector<vector<edge>> G; vector<long long> level, iter; Dinic(long long v) : G(v), level(v), iter(v) {} void addEdge(long long from, long long to, long long cap) { G[from].push_back(edge(to, cap, G[to].size())); G[to].push_back(edge(from, 0, G[from].size() - 1)); } void bfs(long long s) { fill(level.begin(), level.end(), -1); queue<long long> que; level[s] = 0; que.push(s); while (que.size()) { long long v = que.front(); que.pop(); for (auto &e : G[v]) { if (e.cap && level[e.to] == -1) { level[e.to] = level[v] + 1; que.push(e.to); } } } } long long dfs(long long v, long long t, long long f) { if (v == t) return f; for (long long &i = iter[v]; i < G[v].size(); i++) { edge &e = G[v][i]; if (e.cap > 0 && level[v] < level[e.to]) { long long d = dfs(e.to, t, min(f, e.cap)); if (d > 0) { e.cap -= d; G[e.to][e.rev].cap += d; return d; } } } return 0; } long long maxFlow(long long s, long long t) { long long flow = 0; while (true) { bfs(s); if (level[t] < 0) return flow; fill(iter.begin(), iter.end(), 0); long long f; while ((f = dfs(s, t, INF)) > 0) flow += f; } } }; long long N, M; long long A[5555], B[5555]; bool check(long long x) { Dinic d(N + 2); long long src = N; long long snk = N + 1; vector<long long> cnt(N); for (long long i = 0; i < (M); i++) { cnt[A[i]]++; d.addEdge(A[i], B[i], 1); } long long f = 0; for (long long i = 0; i < (N); i++) { if (cnt[i] > x) { d.addEdge(src, i, cnt[i] - x); f += cnt[i] - x; } else if (cnt[i] < x) { d.addEdge(i, snk, x - cnt[i]); } } if (d.maxFlow(src, snk) != f) return false; set<pair<long long, long long>> es; for (long long i = 0; i < (N); i++) for (auto &e : d.G[i]) if (e.cap) es.insert({i, e.to}); for (long long i = 0; i < (M); i++) { if (es.find({A[i], B[i]}) == es.end()) swap(A[i], B[i]); } return true; } signed main() { cin >> N >> M; for (long long i = 0; i < (M); i++) cin >> A[i] >> B[i], A[i]--, B[i]--; long long lb = 0, ub = M; while (ub - lb > 1) { long long mid = (ub + lb) / 2; if (check(mid)) ub = mid; else lb = mid; } check(ub); cout << ub << endl; for (long long i = 0; i < (M); i++) cout << A[i] + 1 << << B[i] + 1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; while (scanf( %d%d%d%d , &a, &b, &c, &d) != EOF) { if (d > 2 * c || d >= b || c > 2 * d) { printf( -1 n ); } else { printf( %d n%d n%d n , 2 * a, 2 * b, max(c, d)); } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int spf[100000 + 1]; long long int const MAXN = 100001; long long int modex(long long int x, long long int y, long long int p); void getZarr(string str, long long int Z[]); void sieve(); vector<long long int> getFactorization(long long int x); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int a, b; cin >> a >> b; for (long long int x = 1; x < a; x++) { long long int temp = sqrt(a * a - x * x); if (temp * temp == a * a - x * x) { if ((b * x) % a == 0 && (b * temp) % a == 0) { if (x == -(b * temp) / a || temp == (b * x) / a) continue; cout << YES << n ; cout << 0 << << 0 << n ; cout << x << << temp << n ; cout << -(b * temp) / a << << (b * x) / a << n ; return 0; } } } cout << NO << n ; } void getZarr(string str, long long int Z[]) { Z[0] = 0; long long int n = str.length(); long long int L, R, k; L = R = 0; for (long long int i = 1; i < n; i++) { if (i > R) { L = R = i; while (R < n && str[R - L] == str[R]) R++; Z[i] = R - L; R--; } else { k = i - L; if (Z[k] < R - i + 1) Z[i] = Z[k]; else { L = i; while (R < n && str[R - L] == str[R]) R++; Z[i] = R - L; R--; } } } } long long int modex(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } void sieve() { spf[1] = 1; for (int i = 2; i < MAXN; i++) spf[i] = i; for (int i = 4; i < MAXN; i += 2) spf[i] = 2; for (int i = 3; i * i < MAXN; i++) { if (spf[i] == i) { for (int j = i * i; j < MAXN; j += i) if (spf[j] == j) spf[j] = i; } } } vector<long long int> getFactorization(long long int x) { vector<long long int> ret; while (x != 1) { ret.push_back(spf[x]); x = x / spf[x]; } return ret; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:44:24 03/10/2015
// Design Name:
// Module Name: Immediate_Extend
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
// load :
// 0. 7:0 s
// 1. 3:0 s
// 2. 10:0 s
// 3. 2:0 t
// 4. 7:0 z
// 5. 4:0 s
// 6. 4:2 t
//////////////////////////////////////////////////////////////////////////////////
module Immediate_Extend(
output [15 : 0] data_out,
input [2 : 0] load,
input [15 : 0] data_in
);
assign data_out =
(load == 0) ? {{8{data_in[7]}}, data_in[7 : 0]} :
(load == 1) ? {{12{data_in[3]}}, data_in[3 : 0]} :
(load == 2) ? {{5{data_in[10]}}, data_in[10 : 0]} :
(load == 3) ? {12'b0, data_in[3 : 0]} :
(load == 4) ? {8'b0, data_in[7 : 0]} :
(load == 5) ? {{11{data_in[4]}}, data_in[4 : 0]} :
{13'b0, data_in[4 : 2]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t, i, j, n, a[100000], x, y, index, num, l, r, count, count1, temp; vector<int> vect; cin >> n >> t; for (i = 0; i < n; i++) { cin >> a[i]; } while (t > 0) { count = 0; count1 = 0; cin >> x >> y >> index; index = index - 1; x = x - 1; y = y - 1; if (x <= index && index <= y) { for (i = index - 1; i >= x; i--) { if (a[index] < a[i]) { count++; } } for (i = index + 1; i <= y; i++) { if (a[index] > a[i]) { count1++; } } if (count == count1) { temp = 1; } else { temp = 0; } } else { temp = 1; } if (temp == 1) { cout << Yes << endl; } else { cout << No << endl; } t--; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct re { long long x[300300]; long long up[300300]; bool f[300300]; }; int o; re rmq; void f_read() { int i, n, a[100100]; cin >> n; for (i = 0; i < n; ++i) cin >> a[i]; o = 1; memset(rmq.x, 0, sizeof(rmq.x)); memset(rmq.up, 0, sizeof(rmq.up)); memset(rmq.f, 0, sizeof(rmq.f)); while (o < n) o *= 2; for (i = 0; i < n; ++i) rmq.x[i + o] = a[i]; for (i = o - 1; i > 0; --i) rmq.x[i] = ((rmq.x[i * 2]) < (rmq.x[i * 2 + 1]) ? (rmq.x[i * 2 + 1]) : (rmq.x[i * 2])); } void RPUSH(int v) { if (!rmq.f[v]) return; rmq.f[v * 2] = 1; rmq.up[v * 2] = rmq.up[v]; rmq.f[v * 2 + 1] = 1; rmq.up[v * 2 + 1] = rmq.up[v]; rmq.x[v] = rmq.up[v]; rmq.f[v] = 0; } long long RMAX(int l, int r, int v = 1, int cl = 1, int cr = o) { if (l > r) return 0; if (l == cl && r == cr) { if (rmq.f[v]) return rmq.up[v]; else return rmq.x[v]; } RPUSH(v); int t = (cl + cr) >> 1; long long a = RMAX(l, ((r) > (t) ? (t) : (r)), v * 2, cl, t), b = RMAX(((t + 1) < (l) ? (l) : (t + 1)), r, v * 2 + 1, t + 1, cr); return ((a) < (b) ? (b) : (a)); } long long RADD(int l, int r, long long d, int v = 1, int cl = 1, int cr = o) { if (l > r) if (rmq.f[v]) return rmq.up[v]; else return rmq.x[v]; if (l == cl && r == cr) { rmq.f[v] = 1; rmq.up[v] = d; return d; } RPUSH(v); int t = (cl + cr) >> 1; long long a = RADD(l, ((t) > (r) ? (r) : (t)), d, v * 2, cl, t), b = RADD(((t + 1) < (l) ? (l) : (t + 1)), r, d, v * 2 + 1, t + 1, cr); rmq.x[v] = ((a) < (b) ? (b) : (a)); return rmq.x[v]; } int main() { f_read(); int i, m, w, h; cin >> m; for (i = 0; i < m; ++i) { cin >> w >> h; long long t = RMAX(1, w); cout << t << endl; RADD(1, w, h + t); } return 0; } |
#include <bits/stdc++.h> using namespace std; pair<int, int> a[110]; int n, k; double p[110]; double dp[110][110]; int was[110][110]; double dist(pair<int, int> a, pair<int, int> b) { double x = a.first - b.first; double y = a.second - b.second; return sqrt(x * x + y * y); } double rec(int pos, int kol) { if (pos == n) { if (kol >= k) return 1; return 0; } if (was[pos][kol]) return dp[pos][kol]; was[pos][kol] = 1; double res = p[pos] * rec(pos + 1, kol + 1); res += (1 - p[pos]) * rec(pos + 1, kol); return dp[pos][kol] = res; } int main() { scanf( %d , &n); int x, y, e; scanf( %d%d , &k, &e); scanf( %d%d , &x, &y); e = 1000 - e; for (int i = (0); i < (n); ++i) scanf( %d%d , &a[i].first, &a[i].second); double l = 0, r = 1e40; double best = -1; for (int i = (0); i < (1000); ++i) { double m = (l + r) / 2; for (int i = (0); i < (n); ++i) { double d = dist(make_pair(x, y), a[i]); if (d <= m) p[i] = 1; else { double k = d * d / m / m; p[i] = exp(1.0 - k); } } memset(was, 0, sizeof(was)); double prob = rec(0, 0); if (prob * 1000 >= e) { best = m; r = m; } else l = m; } printf( %.10lf n , best); return 0; } |
//
// kbd.v -- PC keyboard interface
//
module kbd(clk, reset,
en, wr, addr,
data_in, data_out,
wt, irq,
ps2_clk, ps2_data);
// internal interface
input clk;
input reset;
input en;
input wr;
input addr;
input [7:0] data_in;
output [7:0] data_out;
output wt;
output irq;
// external interface
input ps2_clk;
input ps2_data;
wire [7:0] keyboard_data;
wire keyboard_rdy;
reg [7:0] data;
reg rdy;
reg ien;
reg [7:2] other_bits;
keyboard keyboard1(
.ps2_clk(ps2_clk),
.ps2_data(ps2_data),
.clk(clk),
.reset(reset),
.keyboard_data(keyboard_data[7:0]),
.keyboard_rdy(keyboard_rdy)
);
always @(posedge clk) begin
if (reset == 1) begin
data <= 8'h00;
rdy <= 0;
ien <= 0;
other_bits <= 6'b000000;
end else begin
if (keyboard_rdy == 1) begin
data <= keyboard_data;
end
if (keyboard_rdy == 1 ||
(en == 1 && wr == 0 && addr == 1)) begin
rdy <= keyboard_rdy;
end
if (en == 1 && wr == 1 && addr == 0) begin
rdy <= data_in[0];
ien <= data_in[1];
other_bits <= data_in[7:2];
end
end
end
assign data_out =
(addr == 0) ? { other_bits[7:2], ien, rdy } : data[7:0];
assign wt = 1'b0;
assign irq = ien & rdy;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:41:23 11/18/2013
// Design Name:
// Module Name: sound_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sound_module(
input sclk,
input lrck,
input reset,
output reg[15:0] left_data,
output reg[15:0] right_data
);
/** Direccion que se esta leyendo en memoria */
reg[13:0] addr;
/** Para leer los datos de memoria */
wire[31:0] read_data;
initial
begin
addr <= 14'b0;
left_data <= 16'b0;
right_data <= 16'b0;
end
/** Modulo de memoria que contiene los datos del sonido */
memoria data_sonido (
.clka(sclk), // input clka
.addra(addr), // input [13 : 0] addra
.douta(read_data) // output [31 : 0] douta
);
always @ (negedge lrck or posedge reset)
begin
if(reset)
begin
addr = 14'b0;
end
else
begin
if(addr == 14'd11264)
begin
addr = 14'b0;
end
else
begin
addr = addr + 1;
end
end
end
always @ (negedge sclk or posedge reset)
begin
if(reset)
begin
left_data = 16'd0;
right_data = 16'd0;
end
else
begin
left_data = read_data[31:16];
right_data = read_data[15:0];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; bool a = false; cin >> n; for (long long i = 1; i < n; i++) { for (long long j = 1; j < n; j++) { if (((n - i - j) % 3) != 0 && (i % 3) != 0 && (j % 3) != 0) { cout << i << << j << << (n - i - j) << endl; a = true; break; } } if (a) break; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf(1010101010); const long long P(29); long long pp[100005]; long long ch[100005]; inline bool eq(int start1, int start2, int le) { long long h1(ch[start1 + le] - ch[start1]); long long h2(ch[start2 + le] - ch[start2]); return h1 * pp[start2] == h2 * pp[start1]; } int n, a[100005]; map<int, vector<int> > startpos; int shortest[100005]; int cmin[100005]; int main() { cin >> n; for (int i(0); i < (n); i++) cin >> a[i], startpos[a[i]].push_back(i); ch[0] = 0; pp[0] = 1; int i(1); for (; i <= (n); i++) { ch[i] = ch[i - 1] + pp[i - 1] * a[i - 1]; pp[i] = pp[i - 1] * P; } for (int i(0); i < (n); i++) { shortest[i] = inf; int startnum(a[i]); vector<int> const& v(startpos[startnum]); for (__typeof((v).end()) it((v).begin()); it != ((v).end()); ++it) { int j(*it); if (j <= i) continue; int le(j - i); if (j + le <= n && eq(i, j, le)) shortest[i] = min(shortest[i], le); } } cmin[n] = inf; for (int i(n - 1); i >= (0); i--) { cmin[i] = min(cmin[i + 1], shortest[i]); } int pt(0); for (; pt < (n);) { int le(cmin[pt]); if (le == inf) break; int loc(find(shortest + pt, shortest + n, le) - shortest); pt = loc + le; } cout << (n - pt) << endl; for (int i(pt); i < (n); i++) cout << a[i] << ; cout << endl; } |
#include <bits/stdc++.h> using namespace std; const long long inf = 1LL << 60; const long long md = 1e9 + 7; const long double eps = 1e-14; const int mx = 3010; int t[mx]; void upd(int p) { for (++p; p < mx; p += p & -p) ++t[p]; } int que(int p) { int res = 0; for (; p > 0; p -= p & -p) res += t[p]; return res; } char zey[mx][mx]; int le[mx][mx], ri[mx][mx]; int solve(vector<int> &a, vector<int> &b) { int sz = a.size(); if (sz == 0) return 0; int res = 0; fill(t, t + sz + 5, 0); vector<pair<int, int> > bb(sz); for (int i = (0); i < int(sz); ++i) bb[i] = pair<int, int>(i - b[i] + 1, i); sort(bb.begin(), bb.end()); int ix = 0; for (int i = (0); i < int(sz); ++i) { while (ix < sz && bb[ix].first <= i) upd(bb[ix++].second); res += que(min(sz, i + a[i])) - i; } return res; } int main() { memset(t, 0, sizeof(t)); int n, m; cin >> n >> m; for (int i = (0); i < int(n); ++i) scanf( %s , zey[i]); for (int i = (0); i < int(n); ++i) { le[i][0] = zey[i][0] == z ; ri[i][m - 1] = zey[i][m - 1] == z ; } for (int i = (0); i < int(n); ++i) for (int j = (1); j < int(m); ++j) le[i][j] = zey[i][j] == z ? 1 + le[i][j - 1] : 0; for (int i = (0); i < int(n); ++i) for (int j = (m - 1); j-- > int(0);) ri[i][j] = zey[i][j] == z ? 1 + ri[i][j + 1] : 0; long long ans = 0; for (int s = (0); s < int(m + n - 1); ++s) { vector<int> a, b; for (int d = (max(0, s - m + 1)); d < int(min(n, s + 1)); ++d) { if (zey[d][s - d] == z ) { a.push_back(le[d][s - d]); b.push_back(ri[d][s - d]); } else { ans += solve(a, b); a.clear(); b.clear(); } } ans += solve(a, b); } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-9; const long long MOD = 1e9 + 7; pair<int, int> es[200000]; vector<pair<int, int> > g[200000]; int degree[200000]; set<pair<int, int> > st; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m, k; scanf( %d%d%d , &n, &m, &k); for (long long i = 0; i < m; i++) { scanf( %d%d , &es[i].first, &es[i].second); es[i].first--, es[i].second--; g[es[i].first].push_back({es[i].second, i}); g[es[i].second].push_back({es[i].first, i}); degree[es[i].first]++, degree[es[i].second]++; } reverse(es, es + m); for (long long i = 0; i < n; i++) st.insert({degree[i], i}); while (!st.empty() && st.begin()->first < k) { auto v = st.begin(); for (pair<int, int> &i : g[v->second]) { int to = i.first; if (st.find({degree[to], to}) != st.end()) { st.erase({degree[to], to}); degree[to]--; st.insert({degree[to], to}); } } st.erase(v); } vector<int> out; for (long long j = 0; j < m; j++) { out.push_back(st.size()); int u = es[j].first, v = es[j].second; if (st.find({degree[u], u}) != st.end() && st.find({degree[v], v}) != st.end()) { st.erase({degree[u], u}); degree[u]--; st.insert({degree[u], u}); st.erase({degree[v], v}); degree[v]--; st.insert({degree[v], v}); while (!st.empty() && st.begin()->first < k) { auto v = st.begin(); for (pair<int, int> &i : g[v->second]) { if (i.second >= m - j - 1) continue; int to = i.first; if (st.find({degree[to], to}) != st.end()) { st.erase({degree[to], to}); degree[to]--; st.insert({degree[to], to}); } } st.erase(v); } } } reverse(begin(out), end(out)); for (int i : out) printf( %d n , i); } |
`timescale 1ns/1ps
//Reads from accumulate buffer and writes directly to indexed location in DRAM
module data_loader #(
parameter DRAM_BASE_ADDR=31'h40000000,
parameter ADDRESS_WIDTH=31,
parameter DATA_WIDTH=32,
parameter BLOCK_SIZE=64
) (
clk,
reset,
//Accumulator port for external writes
accumulate_fifo_read_slave_readdata,
accumulate_fifo_read_slave_waitrequest,
accumulate_fifo_read_slave_read,
//Accumulator for internal writes
accumulator_local_readdata,
accumulator_local_read,
accumulator_local_waitrequest,
//Write interface to write into DDR memory
control_fixed_location,
control_write_base,
control_write_length,
control_go,
control_done,
//user logic
user_write_buffer,
user_buffer_input_data,
user_buffer_full
);
localparam NUM_STATES=6;
localparam STATE_IDLE=0;
localparam STATE_WAIT_READ=1;
localparam STATE_READ_KEY_VAL=2;
localparam STATE_COMPUTE_ADDRESS=3;
localparam STATE_WRITE_DRAM=4;
localparam STATE_WAIT_DONE=5;
////////////Ports///////////////////
input clk;
input reset;
//Read interface to read from accumulator FIFO
input [63: 0] accumulate_fifo_read_slave_readdata;
input accumulate_fifo_read_slave_waitrequest;
output reg accumulate_fifo_read_slave_read;
//Accumulator for local writes
//Signals for local accumulation
input [63:0] accumulator_local_readdata;
input accumulator_local_waitrequest;
output reg accumulator_local_read;
// control inputs and outputs
output wire control_fixed_location;
output reg [ADDRESS_WIDTH-1:0] control_write_base;
output reg [ADDRESS_WIDTH-1:0] control_write_length;
output reg control_go;
input wire control_done;
// user logic inputs and outputs
output reg user_write_buffer;
output reg [DATA_WIDTH-1:0] user_buffer_input_data;
input wire user_buffer_full;
///////////Registers/////////////////////
reg avalonmm_read_slave_read_next;
reg [ADDRESS_WIDTH-1:0] control_write_base_next;
reg [ADDRESS_WIDTH-1:0] control_write_length_next;
reg control_go_next;
reg user_write_buffer_next;
reg [DATA_WIDTH-1:0] user_buffer_input_data_next;
reg [NUM_STATES-1:0] state, state_next;
reg [DATA_WIDTH-1:0] key, val, key_next, val_next;
reg accumulate_fifo_read_slave_read_next;
reg accum_type, accum_type_next;
reg accumulator_local_read_next;
localparam LOCAL=0; //local update
localparam EXT=1; //external update
assign control_fixed_location=1'b0;
always@(*)
begin
accumulate_fifo_read_slave_read_next = 1'b0;
key_next = key;
val_next = val;
control_write_length_next = control_write_length;
control_write_base_next = control_write_base;
control_go_next = 1'b0;
user_buffer_input_data_next = user_buffer_input_data;
user_write_buffer_next = 1'b0;
state_next = state;
accum_type_next = accum_type;
accumulator_local_read_next = 1'b0;
case(state)
STATE_IDLE: begin
if(!accumulate_fifo_read_slave_waitrequest) begin //if fifo is not empty, start reading first key
state_next = STATE_WAIT_READ;
accumulate_fifo_read_slave_read_next = 1'b1;
accum_type_next = EXT;
end
else if(!accumulator_local_waitrequest) begin
state_next = STATE_WAIT_READ;
accumulator_local_read_next = 1'b1;
accum_type_next = LOCAL;
end
else begin
state_next = STATE_IDLE;
end
end
STATE_WAIT_READ: begin
//Issue a sucessive read to get value (The FIFO must have (key,value) pairs
accumulate_fifo_read_slave_read_next = 1'b0;
accumulator_local_read_next = 1'b0;
state_next = STATE_READ_KEY_VAL;
end
STATE_READ_KEY_VAL: begin
if(accum_type==EXT) begin
key_next = accumulate_fifo_read_slave_readdata[63:32];
val_next = accumulate_fifo_read_slave_readdata[31:0];
end
else begin
key_next = accumulator_local_readdata[63:32];
val_next = accumulator_local_readdata[31:0];
end
state_next = STATE_COMPUTE_ADDRESS;
end
STATE_COMPUTE_ADDRESS: begin
control_write_base_next = (DRAM_BASE_ADDR+(key<<BLOCK_SIZE)); //convert key to an addressable location in DDDR2 DRAM [loc=key*64]
control_write_length_next = 4; //write a 32 bit key
control_go_next = 1'b1;
state_next = STATE_WRITE_DRAM;
end
STATE_WRITE_DRAM: begin
if(!user_buffer_full) begin
user_buffer_input_data_next = val;
user_write_buffer_next = 1'b1;
state_next = STATE_WAIT_DONE;
end
end
STATE_WAIT_DONE: begin
if(control_done)
state_next = STATE_IDLE;
end
endcase
end
always@(posedge clk)
begin
if(reset) begin
state <= STATE_IDLE;
accumulate_fifo_read_slave_read <= 1'b0;
key <= 0;
val <= 0;
control_write_length <= 0;
control_write_base <= 0;
control_go <= 0;
user_buffer_input_data <= 0;
user_write_buffer <= 1'b0;
accum_type <= 0;
accumulator_local_read <= 0;
end
else begin
state <= state_next;
accumulate_fifo_read_slave_read <= accumulate_fifo_read_slave_read_next;
key <= key_next;
val <= val_next;
control_write_length <= control_write_length_next;
control_write_base <= control_write_base_next;
control_go <= control_go_next;
user_buffer_input_data <= user_buffer_input_data_next;
user_write_buffer <= user_write_buffer_next;
accum_type <= accum_type_next;
accumulator_local_read <= accumulator_local_read_next;
end
end
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Cascaded integrator-comb (CIC) Decimator
*/
module cic_decimator #(
parameter WIDTH = 16,
parameter RMAX = 2,
parameter M = 1,
parameter N = 2,
parameter REG_WIDTH = WIDTH+$clog2((RMAX*M)**N)
)
(
input wire clk,
input wire rst,
/*
* AXI stream input
*/
input wire [WIDTH-1:0] input_tdata,
input wire input_tvalid,
output wire input_tready,
/*
* AXI stream output
*/
output wire [REG_WIDTH-1:0] output_tdata,
output wire output_tvalid,
input wire output_tready,
/*
* Configuration
*/
input wire [$clog2(RMAX+1)-1:0] rate
);
/*
* CIC decimator architecture
*
* ,---.
* IN -->(+)--------+--->| V |----+------->(-)--- OUT
* ^ | `---' | ^
* | | | |
* +-- z-1 --+ +-- z-M --+
*
* \___________/ \___________/
* N N
*
* Integrate Decimate Comb
*
*/
reg [$clog2(RMAX+1)-1:0] cycle_reg = 0;
reg [REG_WIDTH-1:0] int_reg[N-1:0];
wire [REG_WIDTH-1:0] int_reg_0 = int_reg[0];
wire [REG_WIDTH-1:0] int_reg_1 = int_reg[1];
reg [REG_WIDTH-1:0] comb_reg[N-1:0];
wire [REG_WIDTH-1:0] comb_reg_0 = comb_reg[0];
wire [REG_WIDTH-1:0] comb_reg_1 = comb_reg[1];
assign input_tready = output_tready | (cycle_reg != 0);
assign output_tdata = comb_reg[N-1];
assign output_tvalid = input_tvalid & cycle_reg == 0;
genvar k;
integer i;
initial begin
for (i = 0; i < N; i = i + 1) begin
int_reg[i] <= 0;
comb_reg[i] <= 0;
end
end
// integrator stages
generate
for (k = 0; k < N; k = k + 1) begin : integrator
always @(posedge clk) begin
if (rst) begin
int_reg[k] <= 0;
end else begin
if (input_tready & input_tvalid) begin
if (k == 0) begin
int_reg[k] <= $signed(int_reg[k]) + $signed(input_tdata);
end else begin
int_reg[k] <= $signed(int_reg[k]) + $signed(int_reg[k-1]);
end
end
end
end
end
endgenerate
// comb stages
generate
for (k = 0; k < N; k = k + 1) begin : comb
reg [REG_WIDTH-1:0] delay_reg[M-1:0];
initial begin
for (i = 0; i < M; i = i + 1) begin
delay_reg[i] <= 0;
end
end
always @(posedge clk) begin
if (rst) begin
for (i = 0; i < M; i = i + 1) begin
delay_reg[i] <= 0;
end
comb_reg[k] <= 0;
end else begin
if (output_tready & output_tvalid) begin
if (k == 0) begin
delay_reg[0] <= $signed(int_reg[N-1]);
comb_reg[k] <= $signed(int_reg[N-1]) - $signed(delay_reg[M-1]);
end else begin
delay_reg[0] <= $signed(comb_reg[k-1]);
comb_reg[k] <= $signed(comb_reg[k-1]) - $signed(delay_reg[M-1]);
end
for (i = 0; i < M-1; i = i + 1) begin
delay_reg[i+1] <= delay_reg[i];
end
end
end
end
end
endgenerate
always @(posedge clk) begin
if (rst) begin
cycle_reg <= 0;
end else begin
if (input_tready & input_tvalid) begin
if (cycle_reg < RMAX - 1 && cycle_reg < rate - 1) begin
cycle_reg <= cycle_reg + 1;
end else begin
cycle_reg <= 0;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int static_init = []() { ios_base::sync_with_stdio(false), cin.tie(0), cout << fixed; return 0; }(); constexpr int N = 2e5; int32_t n, a[N]; bool v[N]; int main() { int64_t t, ans = 0; cin >> n >> t; for (int i = 0; i < n; i++) cin >> a[i]; for (;;) { int64_t s = 0; int m = 0; for (int i = 0; i < n; i++) { if (v[i]) continue; if (s + a[i] > t) v[i] = true; else s += a[i], m++; } if (m == 0) break; ans += t / s * m; t %= s; } cout << ans << endl; return 0; } |
#include<bits/stdc++.h> using namespace std; int main(){ int t; cin>>t; while(t--){ string s; cin>>s; int n = s.length(); int i=0,j = n-1,k = n-1; char z = a ; while(k>=0){ if(s[i] == z+k) i++; else if(s[j] == z+k) j--; else break; k--; } if(k == -1) cout<< YES <<endl; else cout<< NO <<endl; } return 0; } |
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