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// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 1 FIFO
module FIFO1(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR
);
parameter width = 1;
parameter guarded = 1;
input CLK;
input RST;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output [width - 1 : 0] D_OUT;
output EMPTY_N;
reg [width - 1 : 0] D_OUT;
reg empty_reg ;
assign EMPTY_N = empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
D_OUT = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0 ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
assign FULL_N = !empty_reg;
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (CLR)
else if (ENQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (ENQ)
else if (DEQ)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
end // if (DEQ)
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
D_OUT <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
if (ENQ)
D_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1 ;
$display( "Warning: FIFO1: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! FULL_N && ENQ && (!DEQ || guarded) )
begin
enqerror = 1 ;
$display( "Warning: FIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end // if (RST == ! `BSV_RESET_VALUE)
end
// synopsys translate_on
endmodule
|
// Library - static, Cell - th34w32, View - schematic
// LAST TIME SAVED: May 23 17:24:37 2014
// NETLIST TIME: May 23 17:36:37 2014
`timescale 1ns / 1ns
module th34w32 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th34w32";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N8 ( .d(net38), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N7 ( .d(net28), .g(y), .s(net38), .b(cds_globals.gnd_));
nfet_b N6 ( .d(net27), .g(d), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net28), .g(y), .s(net27), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net27), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net28), .g(b), .s(net27), .b(cds_globals.gnd_));
nfet_b N0 ( .d(net28), .g(a), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
pfet_b P10 ( .b(cds_globals.vdd_), .g(b), .s(net40), .d(net39));
pfet_b P8 ( .b(cds_globals.vdd_), .g(y), .s(net22), .d(net28));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(net39), .d(net28));
pfet_b P11 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net40));
pfet_b P3 ( .b(cds_globals.vdd_), .g(b), .s(net22), .d(net28));
pfet_b P2 ( .b(cds_globals.vdd_), .g(d), .s(net41), .d(net22));
pfet_b P1 ( .b(cds_globals.vdd_), .g(c), .s(net42), .d(net41));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net42));
inv I2 ( y, net28);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> adj[205]; bool vis[205]; long long dp[205]; void dfs(long long v) { vis[v] = true; for (long long first : adj[v]) { if (!vis[first]) { dfs(first); dp[v] = max(dp[first] + 1, dp[v]); } } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; map<string, long long> m; long long curr = 2; m[ polycarp ] = 1; for (long long i = 0; i < n; i++) { string s1, s2, s3; cin >> s1 >> s2 >> s3; for (char &c : s1) c = tolower(c); for (char &c : s3) c = tolower(c); if (!m[s1]) m[s1] = curr++; if (!m[s3]) m[s3] = curr++; adj[m[s3]].emplace_back(m[s1]); } dfs(1); cout << dp[1] + 1; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2AI_BLACKBOX_V
`define SKY130_FD_SC_MS__O2BB2AI_BLACKBOX_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int len = s.size(); bool flag = false; for (int i = 0; i < len - 1; i++) { if ((s[i] != a && s[i] != e && s[i] != i && s[i] != o && s[i] != u )) { if (s[i] == n ) continue; else { if ((s[i + 1] == a || s[i + 1] == e || s[i + 1] == i || s[i + 1] == o || s[i + 1] == u )) { continue; } else { flag = true; break; } } } } if ((s[len - 1] != a && s[len - 1] != e && s[len - 1] != i && s[len - 1] != o && s[len - 1] != u && s[len - 1] != n )) flag = true; if (!flag) { cout << YES n ; } else { cout << NO n ; } return 0; } |
#include <bits/stdc++.h> const double eps = 1e-9; using namespace std; double f[2050], p[2050], q[2050]; int fa[2050], fb[2050]; int n, a, b; void calc(double w1, double w2) { for (int i = 1; i <= n; i++) { f[i] = f[i - 1]; fa[i] = fa[i - 1]; fb[i] = fb[i - 1]; if (f[i - 1] + p[i] - w1 > f[i]) { f[i] = f[i - 1] + p[i] - w1; fa[i] = fa[i - 1] + 1; fb[i] = fb[i - 1]; } if (f[i - 1] + q[i] - w2 > f[i]) { f[i] = f[i - 1] + q[i] - w2; fa[i] = fa[i - 1]; fb[i] = fb[i - 1] + 1; } if (f[i - 1] + p[i] + q[i] - p[i] * q[i] - w1 - w2 > f[i]) { f[i] = f[i - 1] + p[i] + q[i] - p[i] * q[i] - w1 - w2; fa[i] = fa[i - 1] + 1; fb[i] = fb[i - 1] + 1; } } } int main() { scanf( %d%d%d , &n, &a, &b); for (int i = 1; i <= n; i++) scanf( %lf , &p[i]); for (int i = 1; i <= n; i++) scanf( %lf , &q[i]); double l1 = 0, r1 = 1, l2, r2; while (l1 + eps < r1) { double mid1 = (l1 + r1) / 2; l2 = 0, r2 = 1; while (l2 + eps < r2) { double mid2 = (l2 + r2) / 2; calc(mid1, mid2); if (fb[n] > b) l2 = mid2; else r2 = mid2; } calc(mid1, r2); if (fa[n] > a) l1 = mid1; else r1 = mid1; } calc(r1, r2); printf( %.10lf n , f[n] + a * r1 + b * r2); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> void _R(T &x) { cin >> x; } void _R(int &x) { scanf( %d , &x); } void _R(int64_t &x) { scanf( %lld , &x); } void _R(double &x) { scanf( %lf , &x); } void _R(char &x) { scanf( %c , &x); } void _R(char *x) { scanf( %s , x); } void R() {} template <class T, class... U> void R(T &head, U &...tail) { _R(head); R(tail...); } template <class T> void _W(const T &x) { cout << x; } void _W(const int &x) { printf( %d , x); } void _W(const int64_t &x) { printf( %lld , x); } void _W(const double &x) { printf( %.16f , x); } void _W(const char &x) { putchar(x); } void _W(const char *x) { printf( %s , x); } template <class T, class U> void _W(const pair<T, U> &x) { _W(x.first); putchar( ); _W(x.second); } template <class T> void _W(const vector<T> &x) { for (auto i = x.begin(); i != x.end(); _W(*i++)) if (i != x.cbegin()) putchar( ); } void W() {} template <class T, class... U> void W(const T &head, const U &...tail) { _W(head); putchar(sizeof...(tail) ? : n ); W(tail...); } int MOD = 1e9 + 7; void ADD(long long &x, long long v) { x = (x + v) % MOD; if (x < 0) x += MOD; } const int SIZE = 1 << 20; string s[201]; int len[201]; int n, m; int a[202], b[202]; bitset<4096> d[201][13]; void solve() { for (int i = (1); i <= (n); ++i) { len[i] = ((int)(s[i]).size()); for (int l = (1); l <= (12); ++l) { for (int k = 0; k + l <= len[i]; k++) { int me = 0; for (int r = 0; r < (l); ++r) { me = me * 2 + (s[i][k + r] - 0 ); } d[i][l][me] = 1; } } } for (int i = (n + 1); i <= (n + m); ++i) { for (int l = (1); l <= (12); ++l) { d[i][l] = d[a[i]][l] | d[b[i]][l]; } string tmp = s[a[i]].substr(max(0, ((int)(s[a[i]]).size()) - 12)) + s[b[i]].substr(0, min(12, ((int)(s[b[i]]).size()))); for (int l = (1); l <= (12); ++l) { for (int k = 0; k + l <= ((int)(tmp).size()); k++) { int me = 0; for (int r = 0; r < (l); ++r) { me = me * 2 + (tmp[k + r] - 0 ); } d[i][l][me] = 1; } } s[i] = s[a[i]] + s[b[i]]; if (((int)(s[i]).size()) > 24) { s[i] = s[i].substr(0, 12) + s[i].substr(((int)(s[i]).size()) - 12); } int ans = 0; while (ans < 12 && d[i][ans + 1].count() == (1 << (ans + 1))) ans++; W(ans); } } void input() { R(n); for (int i = (1); i <= (n); ++i) { R(s[i]); } R(m); for (int i = (1); i <= (m); ++i) { R(a[i + n], b[i + n]); } } int main() { input(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long powr(long long a, long long b) { long long res = 1; while (b) { if (b % 2 == 1) res = res * a % 1000000007; a = a * a % 1000000007; b /= 2; } return res; } int main() { int p, k; cin >> p >> k; vector<int> g[p]; bool x[p]; memset(x, false, sizeof x); vector<set<long long>> a; if (k == 0) { long long ans = powr(p, p - 1); cout << ans << n ; return 0; } for (int i = 0; i < p; ++i) { if (x[i]) continue; x[i] = 1; long long yy = i; set<long long> xz; xz.insert(i); do { yy *= k; yy %= p; x[yy] = 1; xz.insert(yy); } while (yy != i); a.push_back(xz); } long long ans = 1; ans = powr(p, a.size() - 1); if (k == 1) { ans *= p; ans %= 1000000007; } cout << ans << n ; } |
`timescale 1ns/1ps
module tb_Oper_Start_In (); /* this is automatically generated */
parameter PERIOD = 10;
reg clk;
reg rst;
// clock
initial begin
clk = 0;
forever #5 clk = ~clk;
end
// reset
initial begin
rst = 0;
#6
rst = 1;
repeat (6) @(posedge clk);
rst = 0;
end
// (*NOTE*) replace reset, clock
parameter W = 32;
reg rst;
reg load_a_i;
reg load_b_i;
reg add_subt_i;
reg [W-1:0] Data_X_i;
reg [W-1:0] Data_Y_i;
wire [W-2:0] DMP_o;
wire [W-2:0] DmP_o;
wire zero_flag_o;
wire real_op_o;
wire sign_final_result_o;
`ifdef OPER1
Oper_Start_In #(
.W(W)
) inst_Oper_Start_In (
.clk (clk),
.rst (rst),
.load_a_i (load_a_i),
.load_b_i (load_b_i),
.add_subt_i (add_subt_i),
.Data_X_i (Data_X_i),
.Data_Y_i (Data_Y_i),
.DMP_o (DMP_o),
.DmP_o (DmP_o),
.zero_flag_o (zero_flag_o),
.real_op_o (real_op_o),
.sign_final_result_o (sign_final_result_o)
);
`endif
Oper_Start_In_2_W32_1 inst_Oper_Start_In (
.clk (clk),
.rst (rst),
.load_b_i (load_b_i),
.intAS (add_subt_i),
.intDX (Data_X_i),
.intDY (Data_Y_i),
.DMP_o (DMP_o),
.DmP_o (DmP_o),
.zero_flag_o (zero_flag_o),
.real_op_o (real_op_o),
.sign_final_result_o (sign_final_result_o)
);
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;
always begin
#(3*PERIOD/2)
@(posedge clk) begin
load_a_i = 1;
load_b_i = 0;
end
@(posedge clk) begin
Data_X_i = Array_IN[contador];
Data_Y_i = Array_IN_2[contador];
contador = contador + 1;
load_a_i = 1;
load_b_i = 1;
end
@(posedge clk) begin
load_a_i = 0;
load_b_i = 0;
end
#(3*PERIOD/2);
end
initial begin
$readmemh("Hexadecimal_A.txt", Array_IN);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
end
initial begin
load_a_i = 1;
load_b_i = 1;
add_subt_i = 0;
contador = 0;
repeat(10240)@(posedge clk);
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A2BB2O_BEHAVIORAL_PP_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X , nor0_out, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2O_BEHAVIORAL_PP_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : cmm_errman_cpl.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
/***********************************************************************
Description:
This module figures out what to do for scheduling Cpl transactions:
1) count up or count down,
2) how much to add or to subtract,
3) it counts the Cpl requested by TLM and USER separately.
It returns the number and a add/subtract_b signals to the Cpl
tracking counter. The outputs are based on how many non-posted
requests have been received by either the TLM or the user.
***********************************************************************/
module cmm_errman_cpl (
cpl_num, // Output
inc_dec_b,
cmm_err_tlp_posted, // Inputs
decr_cpl,
rst,
clk
);
output [2:0] cpl_num;
output inc_dec_b; // 1 = increment, 0 = decrement
input cmm_err_tlp_posted;
input decr_cpl;
input rst;
input clk;
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter FFD = 1; // clock to out delay model
//******************************************************************//
// Figure out how many errors to increment. //
//******************************************************************//
reg [2:0] mod_to_incr;
reg mod_add_sub_b;
always @(cmm_err_tlp_posted or decr_cpl)
begin
case ({cmm_err_tlp_posted, decr_cpl}) // synthesis full_case parallel_case
2'b00: begin mod_to_incr = 3'b000;
mod_add_sub_b = 1'b1;
end
2'b01: begin mod_to_incr = 3'b001;
mod_add_sub_b = 1'b0;
end
2'b10: begin mod_to_incr = 3'b001;
mod_add_sub_b = 1'b1;
end
2'b11: begin mod_to_incr = 3'b000;
mod_add_sub_b = 1'b1;
end
default: begin mod_to_incr = 3'b000;
mod_add_sub_b = 1'b1;
end
endcase
end
//******************************************************************//
// Register the outputs. //
//******************************************************************//
reg [2:0] reg_cpl_num;
reg reg_inc_dec_b;
always @(posedge clk or posedge rst)
begin
if (rst)
begin
reg_cpl_num <= #FFD 3'b000;
reg_inc_dec_b <= #FFD 1'b0;
end
else
begin
reg_cpl_num <= #FFD mod_to_incr;
reg_inc_dec_b <= #FFD mod_add_sub_b;
end
end
assign cpl_num = reg_cpl_num;
assign inc_dec_b = reg_inc_dec_b;
//******************************************************************//
// //
//******************************************************************//
endmodule
|
#include <bits/stdc++.h> using namespace std; using vi = vector<int>; using vvi = vector<vi>; using ii = pair<int, int>; using vii = vector<ii>; using l = long long; using vl = vector<l>; using vvl = vector<vl>; using ll = pair<l, l>; using vll = vector<ll>; using vvll = vector<vll>; using lu = unsigned long long; using vb = vector<bool>; using vvb = vector<vb>; using vd = vector<double>; using vvd = vector<vd>; const int INF = numeric_limits<int>::max(); const double EPS = 1e-10; const l e0 = 1, e5 = 100000, e6 = 1000000, e7 = 10000000, e9 = 1000000000; const bool enable_log = false; struct VoidStream { void operator&(std::ostream&) {} }; const l dx[] = {0, 0, 1, -1}; const l dy[] = {-1, 1, 0, 0}; struct point { l x, y; }; const l Z = 26; const l MAX = 50; point start, finish; l n, m, k; l around_start, around_finish; l shortest; string answer; l D[MAX][MAX]; vector<string> M; bool fit(l x, l y) { return (x >= 0) and (x < n) and (y >= 0) and (y < m); } l to_bit(char c) { return e0 << (c - a ); } void check(l mask) { if ((mask & around_finish) == 0) return; fill(&D[0][0], &D[MAX][0], 0); queue<point> q; q.emplace(finish); D[finish.x][finish.y] = 1; while (not q.empty()) { auto u = q.front(); q.pop(); l r = D[u.x][u.y]; if (r > shortest) return; for (l d = 0; d < 4; d++) { l x = u.x + dx[d], y = u.y + dy[d]; if ((not fit(x, y)) or D[x][y] != 0) continue; if (M[x][y] == S ) { string candidate = ; vector<point> wave; wave.push_back({x, y}); for (l i = r; i > 1; i--) { vector<point> next; char c = z + 1; for (const auto p : wave) { for (l j = 0; j < 4; j++) { l a = p.x + dx[j], b = p.y + dy[j]; if ((not fit(a, b)) or (D[a][b] != i)) continue; D[a][b] = -1; if (M[a][b] < c) { next.clear(); c = M[a][b]; } if (M[a][b] == c) next.push_back({a, b}); } } candidate += c; swap(next, wave); } if (r < shortest) { answer = candidate; shortest = r; } else if (candidate < answer) { answer = candidate; } return; } if (mask & to_bit(M[x][y])) { D[x][y] = r + 1; q.push({x, y}); } else { D[x][y] = -1; } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); while (cin >> n >> m >> k) { shortest = INF; M.resize(n); for (l i = 0; i < n; i++) cin >> M[i]; l mask = 0; for (l i = 0; i < n; i++) { for (l j = 0; j < m; j++) { if (M[i][j] == S ) { start = {i, j}; continue; } if (M[i][j] == T ) { finish = {i, j}; continue; } mask = mask | to_bit(M[i][j]); } } around_start = 0; for (l d = 0; d < 4; d++) { if (fit(start.x + dx[d], start.y + dy[d])) { if (M[start.x + dx[d]][start.y + dy[d]] == T ) { shortest = 0; break; } around_start = around_start | to_bit(M[start.x + dx[d]][start.y + dy[d]]); } } if (shortest == 0) { cout << n ; continue; } around_finish = 0; for (l d = 0; d < 4; d++) { if (fit(finish.x + dx[d], finish.y + dy[d])) around_finish = around_finish | to_bit(M[finish.x + dx[d]][finish.y + dy[d]]); } for (l a = 0; a < Z; a++) { if ((around_start & (e0 << a)) == 0) continue; check(e0 << a); if (k == 1) continue; for (l b = 0; b < Z; b++) { if ((b == a) or ((mask & (e0 << b)) == 0)) continue; check((e0 << a) | (e0 << b)); if (k == 2) continue; for (l c = b + 1; c < Z; c++) { if ((c == a) or ((mask & (e0 << c)) == 0)) continue; check((e0 << a) | (e0 << b) | (e0 << c)); if (k == 3) continue; for (l d = c + 1; d < Z; d++) { if ((d == a) or ((mask & (e0 << d)) == 0)) continue; check((e0 << a) | (e0 << b) | (e0 << c) | (e0 << d)); } } } } if (shortest == INF) { cout << -1 n ; } else { cout << answer << n ; } } } |
module var23_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7
+ S * 9'd29
+ T * 9'd23
+ U * 9'd24
+ V * 9'd3
+ W * 9'd18;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26
+ S * 9'd1
+ T * 9'd22
+ U * 9'd26
+ V * 9'd15
+ W * 9'd0;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12
+ S * 9'd28
+ T * 9'd13
+ U * 9'd18
+ V * 9'd16
+ W * 9'd26;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
/*#pragma GCC target ( avx2 ) #pragma GCC optimization ( O3 ) #pragma GCC optimization ( unroll-loops ) */ #include<bits/stdc++.h> using namespace std; void __print(int x) {cerr << x;} void __print(long x) {cerr << x;} void __print(long long x) {cerr << x;} void __print(unsigned x) {cerr << x;} void __print(unsigned long x) {cerr << x;} void __print(unsigned long long x) {cerr << x;} void __print(float x) {cerr << x;} void __print(double x) {cerr << x;} void __print(long double x) {cerr << x;} void __print(char x) {cerr << << x << ;} void __print(const char *x) {cerr << << x << ;} void __print(const string &x) {cerr << << x << ;} void __print(bool x) {cerr << (x ? true : false );} template<typename T, typename V> void __print(const pair<T, V> &x) {cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ;} template<typename T> void __print(const T &x) {int f = 0; cerr << { ; for (auto &i: x) cerr << (f++ ? , : ), __print(i); cerr << } ;} void _print() {cerr << ] n ;} template <typename T, typename... V> void _print(T t, V... v) {__print(t); if (sizeof...(v)) cerr << , ; _print(v...);} #ifndef ONLINE_JUDGE #define debug(x...) cerr << [ << #x << ] = [ ; _print(x) #else #define debug(x...) #endif #define ll long long #define f first #define s second #define Fast ios_base::sync_with_stdio(false);cin.tie(NULL); typedef pair<ll , pair<ll, ll> > pi; int pow(int x,int y){ int res=1; while(y){ if(y&1) res*=x; y>>=1; x*=x; } return res; } struct Compare { constexpr bool operator()(pi const & a, pi const & b) const noexcept { return a.first < b.first || (a.first == b.first && a.second.first > b.second.first); } }; void prefix_function( string s,ll arr[] ) { long long border=0; arr[0]=0; for(long long i=1;i<s.size();i++) { while(border>0 && s[i]!=s[border]) border=arr[border-1]; if(s[i]==s[border]) border++; else border=0; arr[i]=border; } }//send mod-2 for a^-1 if mod is a prime number ll mod=998244353; ll add( ll a , ll b) { return (((a%mod)+(b%mod))%mod); } ll mul(ll a,ll b) { return (((a%mod)*(b%mod))%mod); } ll binpow(ll a, ll b) { ll res = 1; while (b) { if (b & 1) res = mul(res, a); a = mul(a, a); b >>= 1; } return res; } ll subs(ll a,ll b) { return (((a%mod)-(b%mod)+mod)%mod); } ll dv(ll a,ll b) { ll inv=binpow(b,mod-2); return mul(a,inv); } ll dsu_arr[100000]; ll dsu_sz[100000]; void dsu(ll n) { for(ll i=0;i<=n;i++) { dsu_arr[i]=i; dsu_sz[i]=1; } } ll find(ll x) { ll root=x; while (root!=dsu_arr[root]) { root=dsu_arr[root]; } while(x!=dsu_arr[x]) { dsu_arr[x]=root; x=dsu_arr[x]; } return root; } ll merge(ll x,ll y) { ll root1=find(x); ll root2=find(y); if(root1==root2) return 0ll; if(dsu_sz[x]>dsu_sz[y]){ dsu_arr[root2]=root1; dsu_sz[root1]+=dsu_sz[root2]; } else { dsu_sz[root2]+=dsu_sz[root1]; dsu_arr[root1]=root2; } return 1ll; } /* vector<ll>adj[100005]; bool vis[100005]; ll dist[100005]; void bfs(ll c) { vis[c]=true; dist[c]=0; queue<ll>q; q.push(c); while(!q.empty()) { ll x=q.front(); q.pop(); for(ll i=0;i<adj[x].size();i++) { ll y=adj[x][i]; if(!vis[y]) { vis[y]=true; dist[y]=dist[x]+1; q.push(y); } } } } */ int main() { Fast ll test; cin>>test; while(test--) { ll n; cin>>n; vector<ll>sura,mura,dp; for(ll i=0;i<n;i++) { ll k; cin>>k; if(i%2) sura.push_back(k); else{ mura.push_back(k); dp.push_back(0ll); } } ll ans=1000000000000000000,ans2=0; ll mn=100000000000; ll sum=0; for(ll i=0;i<mura.size();i++) { sum+=mura[i]; mn=min(mn,mura[i]); dp[i]=(sum-mn)+(mn*(n-i)); // cout<<dp[i]<< ; } dp.push_back(100000000000000000); // cout<<endl; mn=100000000000; sum=0; for(ll i=0;i<sura.size();i++) { sum+=sura[i]; mn=min(mn,sura[i]); ll x=(sum-mn)+(mn*(n-i)); ans=min(ans,min(dp[i],dp[i+1])+x); } cout<<ans<< n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, i, j, k, l, m, b, t, sum, sum1, flag, max1, min1; cin >> n >> m; long long a[n + 1]; for (i = 1; i <= n; i++) { cin >> a[i]; } sum = 0; long long pre[100009]; pre[1] = a[1]; for (i = 2; i <= n; i++) { pre[i] = pre[i - 1] + a[i]; } max1 = INT_MIN; for (i = 1; i <= n; i++) { k = pre[i]; l = pre[n] - pre[i]; k = k % m; l = l % m; max1 = max(k + l, max1); } cout << max1 << endl; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/13/2017 05:18:39 PM
// Design Name:
// Module Name: SHA1_out
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SHA1_out(input clk,
input rst,
input start,
input [159:0]digest_in,
output reg done,
output reg [31:0]hash_out
);
//reg done;
//reg [31:0]hash_out;
reg [2:0]count;
always@(posedge clk or negedge rst) begin
if(rst == 0) begin
done <= 0;
hash_out <= 0;
count <= 0;
end else begin
if(start)
if(count < 6)
count <= count + 1;
end
end
always@(count) begin
if(count == 1) begin
done = 1;
hash_out = digest_in[31:0];
end
else if(count == 2)
hash_out = digest_in[63:32];
else if(count == 3)
hash_out = digest_in[95:64];
else if(count == 4)
hash_out = digest_in[127:96];
else if(count == 5)
hash_out = digest_in[159:128];
else if (count == 6) begin
done = 0;
hash_out = 0;
end
else begin end
end
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module Computer_System_LEDs (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 9: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 9: 0] data_out;
wire [ 9: 0] out_port;
wire [ 9: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {10 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[9 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> v[100005]; vector<pair<int, int> > asdf; int n; int m; int cnt[100005]; vector<int> nxt[100005]; void build(int at, int num) { if (cnt[at] > 2) return; if (num == m) { while ((int)asdf.size()) { printf( %d %d n , 1 + asdf.back().first, 1 + asdf.back().second); asdf.pop_back(); } exit(0); } if (cnt[at] == 2) return; int a, b; if ((int)v[at].size() != 0) { a = v[at].front(); b = v[at].back(); } else { a = -1, b = -1; } int c, d; if ((int)nxt[at].size()) { c = nxt[at].back(); d = nxt[at].front(); } else { c = d = -1; } for (auto(i) = (at + 1); (i) != (n); (i)++) { if (i != d && i != c && i != a && i != b && cnt[i] < 2) { asdf.push_back(make_pair(i, at)); cnt[at]++; cnt[i]++; nxt[at].push_back(i); nxt[i].push_back(at); build(i, num + 1); nxt[at].pop_back(); nxt[i].pop_back(); cnt[at]--; cnt[i]--; asdf.pop_back(); } } if (cnt[at] > 0 && cnt[at] < 2) { c = nxt[at].front(); d = nxt[at].back(); for (auto(i) = (0); (i) != (at); (i)++) { if (cnt[i] < 2 && i != a && i != b && i != c && i != d) { asdf.push_back(make_pair(i, at)); cnt[at]++; cnt[i]++; nxt[at].push_back(i); nxt[i].push_back(at); build(i, num + 1); nxt[at].pop_back(); nxt[i].pop_back(); cnt[at]--; cnt[i]--; asdf.pop_back(); } } } else { c = d = -1; for (auto(i) = (0); (i) != (at); (i)++) { if (i != c && i != d && i != a && i != b && cnt[i] < 2) { asdf.push_back(make_pair(i, at)); cnt[at]++; cnt[i]++; nxt[at].push_back(i); nxt[i].push_back(at); build(i, num + 1); nxt[at].pop_back(); nxt[i].pop_back(); cnt[at]--; cnt[i]--; asdf.pop_back(); } } } } int main() { cin >> n >> m; for (auto(i) = (0); (i) != (m); (i)++) { int a, b; cin >> a >> b; a--; b--; v[a].push_back(b), v[b].push_back(a); } int kek = 0; for (auto(i) = (0); (i) != (n); (i)++) kek += (min(2, (n - 1 - (int)v[i].size()))); kek /= 2; if (kek < m) { puts( -1 ); return 0; } for (auto(i) = (0); (i) != (n); (i)++) build(i, 0); return 0; } |
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
module oq_regs_eval_empty
#(
parameter SRAM_ADDR_WIDTH = 13,
parameter CTRL_WIDTH = 8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES),
parameter PKT_LEN_WIDTH = 11,
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH),
parameter MAX_PKT = 2048/CTRL_WIDTH, // allow for 2K bytes,
parameter MIN_PKT = 60/CTRL_WIDTH + 1,
parameter PKTS_IN_RAM_WIDTH = log2((2**SRAM_ADDR_WIDTH)/MIN_PKT)
)
(
// --- Inputs from dst update ---
input dst_update,
input [NUM_OQ_WIDTH-1:0] dst_oq,
input [PKTS_IN_RAM_WIDTH-1:0] dst_num_pkts_in_q,
input dst_num_pkts_in_q_done,
// --- Inputs from src update ---
input src_update,
input [NUM_OQ_WIDTH-1:0] src_oq,
input [PKTS_IN_RAM_WIDTH-1:0] src_num_pkts_in_q,
input src_num_pkts_in_q_done,
// --- Clear the flag ---
input initialize,
input [NUM_OQ_WIDTH-1:0] initialize_oq,
output reg [NUM_OUTPUT_QUEUES-1:0] empty,
// --- Misc
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Internal parameters --------------
// ------------- Wires/reg ------------------
wire src_empty;
wire dst_empty;
reg dst_empty_held;
reg [NUM_OQ_WIDTH-1:0] dst_oq_held;
reg [NUM_OQ_WIDTH-1:0] src_oq_held;
reg dst_num_pkts_in_q_done_held;
// ------------- Logic ------------------
assign src_empty = src_num_pkts_in_q == 'h0;
assign dst_empty = dst_num_pkts_in_q == 'h0;
always @(posedge clk)
begin
if (reset) begin
empty <= {NUM_OUTPUT_QUEUES{1'b1}};
end
else begin
if (dst_update) begin
dst_oq_held <= dst_oq;
end
if (src_update) begin
src_oq_held <= src_oq;
end
// Update the empty status giving preference to removes over stores
// since we don't want to accidentally try removing from an empty
// queue
if (src_num_pkts_in_q_done) begin
empty[src_oq_held] <= src_empty;
dst_num_pkts_in_q_done_held <= dst_num_pkts_in_q_done;
dst_empty_held <= dst_empty;
end
else if (dst_num_pkts_in_q_done) begin
empty[dst_oq_held] <= dst_empty;
end
else if (dst_num_pkts_in_q_done_held) begin
empty[dst_oq_held] <= dst_empty_held;
end
else if (initialize) begin
empty[initialize_oq] <= 1'b1;
end
end
end
endmodule // oq_regs_eval_empty
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; struct Fib { long long a, b; Fib operator+(const Fib& o) const { return {(a + o.a) % MOD, (b + o.b) % MOD}; } }; struct FibOp { long long a, b, c, d; FibOp operator()(const FibOp& o) const { FibOp res = {a * o.a + b * o.c, a * o.b + b * o.d, c * o.a + d * o.c, c * o.b + d * o.d}; res.a %= MOD; ; res.b %= MOD; ; res.c %= MOD; ; res.d %= MOD; ; return res; } Fib operator()(const Fib& f) const { Fib res = {a * f.a + b * f.b, c * f.a + d * f.b}; res.a %= MOD; ; res.b %= MOD; ; return res; } }; const long long K = 32; FibOp pwr[K]; FibOp negpwr[K]; Fib zero = {0, 1}; void setup() { pwr[0] = {1, 1, 1, 0}; negpwr[0] = {0, 1, 1, MOD - 1}; for (int i = 1; i < K; ++i) { pwr[i] = pwr[i - 1](pwr[i - 1]); negpwr[i] = negpwr[i - 1](negpwr[i - 1]); } } Fib FibMult(Fib f, long long cnt, FibOp p[K]) { for (int r = K - 1; r >= 0; --r) { if (cnt & (1LL << r)) { f = p[r](f); } } return f; } Fib FibMult(Fib f, long long cnt) { return (cnt >= 0 ? FibMult(f, cnt, pwr) : FibMult(f, -cnt, negpwr)); } struct Node { long long lo[2] = {0, 0}; long long hi[2] = {0, 0}; long long add[2] = {0, 0}; long long sz = 1; Fib f; void apply(long long a[2]) { for (int i = 0; i < 2; ++i) { add[i] += a[i]; lo[i] += a[i]; hi[i] += a[i]; } f = FibMult(f, a[0] + a[1]); } }; struct Segtree { vector<Node> t; int n, h; Segtree(int sz) { h = 32 - __builtin_clz(sz); n = 1 << h; t = vector<Node>(n << 1); for (int i = n - 1; i > 0; --i) { t[i].sz = t[i * 2].sz + t[i * 2 + 1].sz; } } void push(int x) { if (!t[x].add[0] && !t[x].add[1]) { return; } assert(x < n); t[x << 1].apply(t[x].add); t[x << 1 | 1].apply(t[x].add); t[x].add[0] = 0; t[x].add[1] = 0; } void pull(int x) { for (int i = 0; i < 2; ++i) { t[x].lo[i] = min(t[x * 2].lo[i], t[x * 2 + 1].lo[i]); t[x].hi[i] = max(t[x * 2].hi[i], t[x * 2 + 1].hi[i]); } t[x].f = t[x << 1].f + t[x << 1 | 1].f; t[x].apply(t[x].add); } void set_init(int x, int k, int va) { x += n; t[x].lo[k] = t[x].hi[k] = va; t[x].f = FibMult(zero, t[x].lo[0] + t[x].lo[1]); for (x /= 2; x; x /= 2) { pull(x); } } long long query(int l, int r, int x, int lv, int rv) { if (r <= lv || rv <= l) { return 0; } if (l <= lv && rv <= r) { return t[x].f.a; } push(x); int mv = (lv + rv) / 2; long long ans = 0; ans += query(l, r, x * 2, lv, mv); ans += query(l, r, x * 2 + 1, mv, rv); return ans % MOD; } long long query(int l, int r) { return query(l, r, 1, 0, n); } void add(int l, int r, int k, long long va, int x, int lv, int rv) { if (r <= lv || rv <= l) { return; } if (l <= lv && rv <= r) { long long a[2] = {0, 0}; a[k] = va; t[x].apply(a); return; } push(x); int mv = (lv + rv) / 2; add(l, r, k, va, x * 2, lv, mv); add(l, r, k, va, x * 2 + 1, mv, rv); pull(x); } void add(int l, int r, int k, long long va) { add(l, r, k, va, 1, 0, n); } void minupdate(int l, int r, int k, long long va, int x, int lv, int rv) { if (r <= lv || rv <= l) { return; } if (t[x].hi[k] <= va) { return; } if (l <= lv && rv <= r && t[x].lo[k] == t[x].hi[k]) { long long a[2] = {0, 0}; a[k] = va - t[x].lo[k]; t[x].apply(a); return; } push(x); int mv = (lv + rv) / 2; minupdate(l, r, k, va, x * 2, lv, mv); minupdate(l, r, k, va, x * 2 + 1, mv, rv); pull(x); } void minupdate(int l, int r, int k, long long va) { return minupdate(l, r, k, va, 1, 0, n); } void maxupdate(int l, int r, int k, long long va, int x, int lv, int rv) { if (r <= lv || rv <= l) { return; } if (t[x].lo[k] >= va) { return; } if (l <= lv && rv <= r && t[x].lo[k] == t[x].hi[k]) { long long a[2] = {0, 0}; a[k] = va - t[x].lo[k]; t[x].apply(a); return; } push(x); int mv = (lv + rv) / 2; maxupdate(l, r, k, va, x * 2, lv, mv); maxupdate(l, r, k, va, x * 2 + 1, mv, rv); pull(x); } void maxupdate(int l, int r, int k, long long va) { return maxupdate(l, r, k, va, 1, 0, n); } }; int main() { ios_base::sync_with_stdio(0), cin.tie(0); setup(); int n, q; cin >> n >> q; Segtree st(n + 10); for (int i = 1; i <= n; ++i) { int x; cin >> x; st.set_init(i, 0, x); } for (int i = 1; i <= n; ++i) { int x; cin >> x; st.set_init(i, 1, x); } for (int _i = 0; _i < q; ++_i) { int type; cin >> type; if (type == 1) { int k, l, r, x; cin >> k >> l >> r >> x; --k; st.minupdate(l, r + 1, k, x); } else if (type == 2) { int k, l, r, x; cin >> k >> l >> r >> x; --k; st.maxupdate(l, r + 1, k, x); } else if (type == 3) { int k, l, r, x; cin >> k >> l >> r >> x; --k; st.add(l, r + 1, k, x); } else if (type == 4) { int l, r; cin >> l >> r; cout << st.query(l, r + 1) << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = int(5e5) + 100; int n, m; vector<pair<int, int> > out[maxn]; int fa[maxn]; long long f[maxn], g[maxn], a[maxn]; void read() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) out[i].clear(); for (int i = 1; i < n; ++i) { int u, v, d; scanf( %d%d%d , &u, &v, &d); out[u].push_back(make_pair(v, d)); out[v].push_back(make_pair(u, d)); } } void dfs(int cur) { f[cur] = g[cur] = 0; for (auto &to : out[cur]) if (to.first != fa[cur]) { fa[to.first] = cur; dfs(to.first); f[cur] += f[to.first]; g[cur] += f[to.first]; } int cnt = 0; for (auto &to : out[cur]) if (to.first != fa[cur]) a[++cnt] = to.second + g[to.first] - f[to.first]; sort(a + 1, a + 1 + cnt, greater<long long>()); int fin = min(m - 1, cnt); for (int i = 1; i <= fin; ++i) g[cur] += max(0LL, a[i]), f[cur] += max(a[i], 0LL); if (m <= cnt) f[cur] += max(0LL, a[m]); } void solve() { dfs(1); printf( %lld n , f[1]); } int main() { int casesum; scanf( %d , &casesum); while (casesum--) { read(); solve(); } return 0; } |
//
// bsg_wormhole_concentrator.v
//
// 08/2019
//
// This is an adapter between 1 concentrated wormhole link and N unconcentrated wormhole links.
// Extra bits (cid) are used in wormhole header to indicate wormhole packet destination.
//
// From implementation perspective this is a simplified version bsg_wormhole_router.
// Wormhole_router relies on 2D routing_matrix, while wormhole_concentrator has fixed 1-to-n
// and n-to-1 routing. This concentrator reuses most of the building blocks of wormhole_router,
// concentrator header struct is defined in bsg_wormhole_router.vh.
//
// This concentrator has 1-cycle delay from input wormhole link(s) to output wormhole link(s).
// It has zero bubble between wormhole packets.
//
//
`include "bsg_defines.v"
`include "bsg_noc_links.vh"
`include "bsg_wormhole_router.vh"
module bsg_wormhole_concentrator
#(parameter `BSG_INV_PARAM(flit_width_p)
,parameter `BSG_INV_PARAM(len_width_p)
,parameter `BSG_INV_PARAM(cid_width_p)
,parameter `BSG_INV_PARAM(cord_width_p)
,parameter num_in_p = 1
,parameter debug_lp = 0
,parameter link_width_lp = `bsg_ready_and_link_sif_width(flit_width_p)
)
(input clk_i
,input reset_i
// unconcentrated multiple links
,input [num_in_p-1:0][link_width_lp-1:0] links_i
,output [num_in_p-1:0][link_width_lp-1:0] links_o
// concentrated single link
,input [link_width_lp-1:0] concentrated_link_i
,output [link_width_lp-1:0] concentrated_link_o
);
`declare_bsg_ready_and_link_sif_s(flit_width_p,bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s [num_in_p-1:0] links_i_cast, links_o_cast;
bsg_ready_and_link_sif_s [num_in_p-1:0] links_o_stubbed_v, links_o_stubbed_ready;
bsg_ready_and_link_sif_s concentrated_link_i_cast, concentrated_link_o_cast;
bsg_ready_and_link_sif_s concentrated_link_o_stubbed_v, concentrated_link_o_stubbed_ready;
assign links_i_cast = links_i;
assign links_o = links_o_cast;
assign concentrated_link_i_cast = concentrated_link_i;
assign concentrated_link_o = concentrated_link_o_cast;
for (genvar i = 0; i < num_in_p; i++)
begin : cast
assign links_o_cast[i].data = links_o_stubbed_ready[i].data;
assign links_o_cast[i].v = links_o_stubbed_ready[i].v;
assign links_o_cast[i].ready_and_rev = links_o_stubbed_v[i].ready_and_rev;
end
assign concentrated_link_o_cast.data = concentrated_link_o_stubbed_ready.data;
assign concentrated_link_o_cast.v = concentrated_link_o_stubbed_ready.v;
assign concentrated_link_o_cast.ready_and_rev = concentrated_link_o_stubbed_v.ready_and_rev;
bsg_wormhole_concentrator_in
#(.flit_width_p(flit_width_p)
,.len_width_p(len_width_p)
,.cid_width_p(cid_width_p)
,.num_in_p(num_in_p)
,.cord_width_p(cord_width_p)
,.debug_lp(debug_lp)
)
concentrator_in
(.clk_i(clk_i)
,.reset_i(reset_i)
,.links_i(links_i)
,.links_o(links_o_stubbed_v)
,.concentrated_link_i(concentrated_link_i)
,.concentrated_link_o(concentrated_link_o_stubbed_ready)
);
bsg_wormhole_concentrator_out
#(.flit_width_p(flit_width_p)
,.len_width_p(len_width_p)
,.cid_width_p(cid_width_p)
,.num_in_p(num_in_p)
,.cord_width_p(cord_width_p)
,.debug_lp(debug_lp)
)
concentrator_out
(.clk_i(clk_i)
,.reset_i(reset_i)
,.links_i(links_i)
,.links_o(links_o_stubbed_ready)
,.concentrated_link_i(concentrated_link_i)
,.concentrated_link_o(concentrated_link_o_stubbed_v)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_wormhole_concentrator)
|
#include <bits/stdc++.h> using namespace std; int p[100009], a[100009], pos[100009], m, n, ri[100009], le[100009]; set<pair<int, int>> st; inline bool cmp(const int& A, const int& B) { return p[A] < p[B]; } int getdis(int x, int y) { if (x == y) return 1000000000; int d = (p[y] - p[x] + m) % m; if (y < x) d = (d + a[y]) % m; if (d <= a[x]) return 1; if (a[x] <= a[y]) return 1000000000; return (d - a[y] - 1) / (a[x] - a[y]) + 1; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d%d , p + i, a + i), pos[i] = i, p[i]--; sort(pos + 1, pos + n + 1, cmp); for (int i = 1; i <= n; i++) ri[pos[i]] = pos[i + 1], le[pos[i]] = pos[i - 1]; ri[pos[n]] = pos[1], le[pos[1]] = pos[n]; for (int i = 1; i <= n; i++) st.insert(make_pair(getdis(i, ri[i]), i)); while (1) { if (st.begin()->first == 1000000000) break; int u = st.begin()->second; st.erase(st.begin()); st.erase(make_pair(getdis(ri[u], ri[ri[u]]), ri[u])); if (!st.empty()) st.erase(make_pair(getdis(le[u], u), le[u])); p[u] += getdis(u, ri[u]), p[u] %= m, a[u]--; ri[u] = ri[ri[u]], le[ri[u]] = u; st.insert(make_pair(getdis(le[u], u), le[u])), st.insert(make_pair(getdis(u, ri[u]), u)); } printf( %lu n , st.size()); for (set<pair<int, int>>::iterator it = st.begin(); it != st.end(); it++) printf( %d , it->second); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> row, col, A; vector<pair<pair<int, int>, int> > mat; int grid[111][111]; void shift_up(int c, int n, int m) { int i, temp; temp = grid[n][c]; for (i = n; i > 1; i--) grid[i][c] = grid[i - 1][c]; grid[1][c] = temp; } void shift_left(int r, int n, int m) { int i, temp; temp = grid[r][m]; for (i = m; i > 1; i--) grid[r][i] = grid[r][i - 1]; grid[r][1] = temp; } int main() { int n, q, i, m, j, type, id, r, c, x; cin >> n >> m >> q; for (i = 1; i <= n; i++) for (j = 1; j <= m; j++) grid[i][j] = 0; while (q--) { cin >> type; A.push_back(type); if (type == 2) { cin >> id; col.push_back(id); } else if (type == 1) { cin >> id; row.push_back(id); } else { cin >> r >> c >> x; mat.push_back(make_pair(make_pair(r, c), x)); } } int im = mat.size() - 1, ir = row.size() - 1, ic = col.size() - 1; for (i = A.size() - 1; i >= 0; i--) { type = A[i]; if (type == 2) { c = col[ic]; ic--; shift_up(c, n, m); } else if (type == 1) { r = row[ir]; ir--; shift_left(r, n, m); } else { r = mat[im].first.first; c = mat[im].first.second; x = mat[im].second; grid[r][c] = x; im--; } } for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) cout << grid[i][j] << ; cout << n ; } } |
//
// Copyright (c) 2001 Stephan Boettcher <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Validates Non-blocking assignment propagation
// $Id: nblkpush.v,v 1.2 2005/07/07 16:25:20 stevewilliams Exp $
// Update: This test has a race in it that makes it not valid. The
// assumption that a blocking assign will push through the continuous
// assignment before the thread doing the assign is allowed to advance
// is not valid. This test only passes Verilog XL. Every other tool,
// commercial or otherwise, seems to FAIL this test. Therefore, this
// test should not be relied on.
module test;
reg a, b, c, d;
wire ab = a & b;
wire abc = ab | c;
wire abcd = abc & d;
initial
begin
a = 0;
b = 1;
c = 0;
d = 1;
#1;
a = 1;
if (abcd === 1)
begin
$display("PASSED");
$finish;
end
$display("FAILED ab=%b, abc=%b, abcd=%b", ab, abc, abcd);
#1;
if (abcd === 1)
$display("abcd value changed late");
else
$display("abcd value still wrong");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, rej = 0; cin >> n; vector<int> a(n); for (size_t i = 0; i < n; i++) cin >> a[i]; sort(a.begin(), a.end()); for (int i = 0; i < n; i++) if (a[i] == a[0] || a[i] == a[n - 1]) rej++; cout << n - rej; } |
#include <bits/stdc++.h> using namespace std; inline long toInt(string s) { long v; istringstream sin(s); sin >> v; return v; } template <class T> inline string toString(T x) { ostringstream sout; sout << x; return sout.str(); } template <class T> inline T sqr(T x) { return x * x; } long long pw(long long x, long long y) { long long ans = 1; for (long long i = 0; i < y; i++) { ans = ans * x; } return ans; } long long factorial(long long x) { long long ans = 1; for (int i = 1; i < x + 1; i++) { ans = ans * i; } return ans; } long long combination(long long x, long long y) { return factorial(x) / factorial(y) / factorial(x - y); } long long permutation(long long x, long long y) { return factorial(x) / factorial(x - y); } string flip(string s) { string ss; for (int i = 0; i < s.size(); i++) { ss = toString(s[i]) + ss; } return ss; } long long mod(long long a, long long b) { if (a % b == 0) { return 0; } else { return a % b; } } int main() { long long n; cin >> n; vector<long long> v(n); long long a, b; for (long long i = 0; i < n - 1; i++) { cin >> a >> b; v[a - 1]++; v[b - 1]++; } long long ans = 0; for (long long i = 0; i < n; i++) { if (v[i] >= 2) { ans += combination(v[i], 2); } } cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__CLKINV_FUNCTIONAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__clkinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_FUNCTIONAL_PP_V |
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: Demo Function
* Description: Demonstrate all possible characteristics of a function
* including
* Single Byte Write
* Single Byte Read
* Multiple Byte Write
* Multiple Byte Read
* Block Write
* Block Read
* Incrementing Address Write
* Non Incrementing Address Write
* Incrementing Address Read
* Non Incrementing Address Read
*
* Test Interrupt
* Enable
* Interrupt Action
* Interrupt Pending
*
* Read Wait
* System Response to a read wait
*
* Note: All function configuration needs to be done inside
* sdio_configuration.json file
*
* Parameters:
* FUN_NUM: The function index to respond to, e.g. 1 for function 1
*
* Changes:
*/
`include "sdio_cia_defines.v"
module demo_function #(
parameter FUNC_NUM = 1
)(
input clk,
input sdio_clk,
input rst,
//Configuration
input i_csa_en,
input [3:0] i_pwr_mode,
input [15:0] i_block_size, //Maximum Size of block transfer
input i_enable, //Host says they want to use the function
output o_ready, //Function is ready to accept data/command
input i_abort, //Host asks to abort a transaction
output o_execution_status, //Currently Executing a Command
output o_ready_for_data, //Function is ready to receive data
output o_busy, //Current status of the function
//Transaction Configuration
input i_activate, //Activate for a data transfer
output reg o_finished, //Function asserts this signal when it is finished
input i_inc_addr, //Function will increment address for each conecutive r/w
input i_block_mode, //0 = Transfering bytes at a time, 1 = transfering at a block
//Transaction
input i_write_flag, //Read = 0, Write = 1
input i_rd_after_wr, //Read the value after write, only valid for 1 byte
input [17:0] i_addr, //Address within Function
input [7:0] i_write_data, //Data to write
output reg [7:0] o_read_data, //Data to read
output reg o_data_rdy, //Function is ready to receive up to block size of data
input i_data_stb, //Host is sending a byte of data
input i_host_rdy, //Host is ready to receive data from function
input [12:0] i_data_count, //Number of bytes or blocks to read/write
output reg o_data_stb, //SDIO sends a piece of data to host
//Out of band signaling
// output o_read_wait, //When asserted function is not ready to receive more data
output o_interrupt, //Launch off an interrupt
//Test Stimulate
// input i_request_read_wait, //Used for Simulation to test read wait
input i_request_interrupt //Used for simulation to test interrupt
);
//local parameters
localparam IDLE = 4'h0;
localparam WRITE = 4'h1;
localparam READ_START = 4'h2;
localparam READ = 4'h3;
localparam FINISHED = 4'h4;
//registes/wires
reg [3:0] state;
reg [11:0] mem_addr;
reg write_stb;
reg mem_write_stb;
reg [31:0] mem_write_data;
wire [31:0] mem_read_data;
reg [12:0] data_count;
reg [1:0] byte_count;
reg [31:0] block_data_count;
wire count_finished;
reg [31:0] address;
reg [31:0] write_data;
reg [31:0] read_data;
//submodules
blk_mem #(
.DATA_WIDTH (32 ), //More Challenging but this is going to be more like final applications
.ADDRESS_WIDTH (12 ), //4096
.INC_NUM_PATTERN (1 ) //Incrementing data pattern to read and modify
)mem(
.clka (sdio_clk ),
.wea (mem_write_stb ),
.addra (mem_addr ),
.dina (mem_write_data ),
//.clkb (blk ),
.clkb (sdio_clk ),
.addrb (mem_addr ),
.doutb (mem_read_data )
);
//asynchronous logic
assign o_busy = state != IDLE;
//assign count_finished = i_block_mode ? (block_data_count >= i_data_count) :
// (data_count >= i_data_count);
assign count_finished = (data_count >= i_data_count);
//assign o_read_wait = (`SRW && i_request_read_wait);
assign o_interrupt = i_request_interrupt;
assign o_ready = i_enable;
assign o_execution_status = o_busy;
assign o_ready_for_data = 1'b1;
//assign mem_write_data = {write_data[23:0], i_write_data};
//synchronous logic
/*
always @ (*) begin
if(rst) begin
o_read_data <= 8'h0;
end
else begin
case (byte_count)
2'b00:
o_read_data <= mem_read_data[7:0];
2'b01:
o_read_data <= mem_read_data[15:8];
2'b10:
o_read_data <= mem_read_data[23:16];
2'b11:
o_read_data <= mem_read_data[31:24];
endcase
end
end
*/
//Counter
//XXX: This may need to be a mealy state machine
/*
always @ (posedge sdio_clk) begin
if (rst) begin
data_count <= 0;
block_data_count <= 0;
end
else begin
if (state == IDLE) begin
data_count <= 0;
block_data_count <= 0;
end
else if ((state == WRITE) || (state == READ)) begin
if (i_data_stb || o_data_stb) begin
if (i_block_mode) begin
if (data_count < i_block_size) begin
data_count <= data_count + 13'h1;
end
else begin
if (block_data_count < data_count) begin
block_data_count <= block_data_count + 1;
data_count <= 13'h0;
end
end
end
else begin
data_count <= data_count + 13'h1;
end
end
end
end
end
*/
//Main State Machine
always @ (posedge sdio_clk) begin
mem_write_stb <= 0;
write_stb <= 0;
o_data_stb <= 0;
if (rst) begin
byte_count <= 0;
//mem_write_data <= 0;
o_finished <= 0;
o_data_rdy <= 0;
write_data <= 0;
address <= 0;
mem_addr <= 0;
o_read_data <= 0;
read_data <= 0;
state <= IDLE;
data_count <= 0;
block_data_count <= 0;
mem_write_data <= 0;
end
else begin
if (write_stb) begin
mem_write_stb <= 1;
address <= address + 1;
end
case (state)
IDLE: begin
byte_count <= 0;
o_data_rdy <= 0;
o_finished <= 0;
mem_addr <= 0;
data_count <= 0;
if (i_activate)begin
address <= i_addr[12:2];
mem_addr <= i_addr[12:2];
o_data_rdy <= 1;
if (i_write_flag) begin
state <= WRITE;
end
else begin
state <= READ_START;
end
end
end
WRITE: begin
if (data_count < i_data_count) begin
if (i_data_stb) begin
//Shift Data In
write_data <= {write_data[23:0], i_write_data};
case (byte_count)
0: begin
end
1: begin
end
2: begin
mem_addr <= address;
end
3: begin
write_stb <= 1;
data_count <= data_count + 1;
mem_write_data <= {write_data[23:0], i_write_data};
end
endcase
byte_count <= byte_count + 2'b01;
end
end
else begin
state <= FINISHED;
end
end
READ_START: begin
if (i_host_rdy) begin
read_data <= mem_read_data;
o_read_data <= mem_read_data[31:24];
byte_count <= 0;
//o_data_stb <= 1;
state <= READ;
end
end
READ: begin
o_data_stb <= 1;
case (byte_count)
0: begin
o_read_data <= read_data[31:24];
mem_addr <= mem_addr + 1;
end
1: begin
o_read_data <= read_data[23:16];
end
2: begin
o_read_data <= read_data[15:8];
data_count <= data_count + 1;
end
3: begin
o_read_data <= read_data[7:0];
//mem_addr <= address;
//address <= address + 1;
if (data_count < i_data_count[12:2]) begin
read_data <= mem_read_data;
end
else begin
state <= FINISHED;
end
end
endcase
byte_count <= byte_count + 2'b01;
end
FINISHED: begin
o_data_rdy <= 0;
o_finished <= 1;
if (!i_activate) begin
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
`timescale 1ns/10ps
module top;
reg pass;
real rise, fall, delay, base, diff;
reg in, ctl;
wire out, outif0;
buf #(rise, fall) dut(out, in);
bufif0 #(rise, fall) dutif0(outif0, in, ctl);
// Check that the buffer output has the correct value and changed at the
// correct time.
always @(out) begin
if ((in === 1'bz && out !== 1'bx) ||
(in !== 1'bz && out !== in)) begin
$display("in (%b) !== out (%b) at %.1f", in, out, $realtime);
pass = 1'b0;
end
diff = $realtime - (base + delay);
if (diff < 0.0) diff = -diff;
if (diff >= 0.01) begin
$display("Incorrect buf delay at %.1f, got %.1f, expected %.1f",
base, $realtime-base, delay);
pass = 1'b0;
end
end
// Check that the bufif0 output has the correct value and changed at the
// correct time.
always @(outif0) begin
if (ctl) begin
if (outif0 !== 1'bz) begin
$display("outif0 (%b) !== 1'bz at %.1f", out, $realtime);
pass = 1'b0;
end
end else if ((in === 1'bz && outif0 !== 1'bx) ||
(in !== 1'bz && outif0 !== in)) begin
$display("in (%b) !== outif0 (%b) at %.1f", in, outif0, $realtime);
pass = 1'b0;
end
diff = $realtime - (base + delay);
if (diff < 0.0) diff = -diff;
if (diff >= 0.01) begin
$display("Incorrect bufif0 delay at %.1f, got %.1f, expected %.1f",
base, $realtime-base, delay);
pass = 1'b0;
end
end
function real min(input real a, input real b);
if (a < b) min = a;
else min = b;
endfunction
initial begin
// $monitor($realtime,,out,outif0,, in,, ctl);
pass = 1'b1;
rise = 1.1;
fall = 1.2;
ctl = 1'b0;
// x -> 0 (fall)
in = 1'b0;
delay = fall;
base = $realtime;
#2;
// 0 -> 1 (rise)
in = 1'b1;
delay = rise;
base = $realtime;
#2;
// 1 -> x (min(rise, fall))
delay = min(rise, fall);
in = 1'bz;
base = $realtime;
#2;
// x -> 1 (rise)
in = 1'b1;
delay = rise;
base = $realtime;
#2;
// 1 -> 0 (fall)
in = 1'b0;
delay = fall;
base = $realtime;
#2;
fall = 1.0;
// 0 -> x (min(rise, fall))
in = 1'bx;
delay = min(rise, fall);
base = $realtime;
#2;
// x -> z (min(rise, fall))
ctl = 1'b1;
delay = min(rise, fall);
base = $realtime;
#2;
// z -> x (min(rise, fall))
ctl = 1'b0;
delay = min(rise, fall);
base = $realtime;
#2;
fall = 1.2;
// x -> z (min(rise, fall))
ctl = 1'b1;
delay = min(rise, fall);
base = $realtime;
#2;
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100007, dx[8] = {1, 1, 1, 0, 0, -1, -1, -1}, dy[8] = {1, 0, -1, 1, -1, 1, 0, -1}; int xs, ys, xt, yt, n, r[maxn], a[maxn], b[maxn], d[maxn] = {}, cnt = 0; bool vis[maxn] = {}; vector<int> row, col[maxn]; vector<pair<int, int> > seg[maxn], cells[maxn]; int dist(int x, int y) { x = lower_bound(row.begin(), row.end(), x) - row.begin() + 1; y = lower_bound(cells[x].begin(), cells[x].end(), make_pair(y, 0)) - cells[x].begin(); return d[cells[x][y].second]; } void set_dist(int x, int y, int val) { x = lower_bound(row.begin(), row.end(), x) - row.begin() + 1; y = lower_bound(cells[x].begin(), cells[x].end(), make_pair(y, 0)) - cells[x].begin(); d[cells[x][y].second] = val; } bool valid(int x, int y) { if (!binary_search(row.begin(), row.end(), x)) return 0; x = lower_bound(row.begin(), row.end(), x) - row.begin() + 1; if (!binary_search(col[x].begin(), col[x].end(), y)) return 0; return 1; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> xs >> ys >> xt >> yt >> n; for (int i = 1; i <= n; ++i) { cin >> r[i] >> a[i] >> b[i]; row.push_back(r[i]); } sort(row.begin(), row.end()); for (int i = 1; i <= n; ++i) r[i] = lower_bound(row.begin(), row.end(), r[i]) - row.begin() + 1; for (int i = 1; i <= n; ++i) seg[r[i]].push_back({a[i], b[i]}); for (int i = 1; i <= n; ++i) { if (vis[r[i]]) continue; sort(seg[r[i]].begin(), seg[r[i]].end()); int cur = 1; for (auto it : seg[r[i]]) { cur = max(it.first, cur); for (int j = cur; j <= it.second; ++j) cells[r[i]].push_back({j, ++cnt}), col[r[i]].push_back(j); } vis[r[i]] = 1; } queue<pair<int, int> > q; q.push({xs, ys}); set_dist(xs, ys, 1); while (q.size()) { int x = q.front().first, y = q.front().second; q.pop(); for (int i = 0; i < 8; ++i) { int xx = dx[i] + x, yy = dy[i] + y; if (valid(xx, yy) && dist(xx, yy) == 0) set_dist(xx, yy, dist(x, y) + 1), q.push({xx, yy}); } } cout << dist(xt, yt) - 1; return 0; } |
#include <bits/stdc++.h> using namespace std; static const int MXN = 20000 + 2; const int mod = 998244353; long long dis[MXN]; struct CostFlow { static const long long INF = 102938475610293847LL; struct Edge { int v, r; long long f, c; Edge(int a, int b, int _c, int d) : v(a), r(b), f(_c), c(d) {} }; int n, s, t, prv[MXN], prvL[MXN], inq[MXN]; long long fl, cost; vector<Edge> E[MXN]; void init(int _n, int _s, int _t) { n = _n; s = _s; t = _t; for (int i = 0; i < n; i++) E[i].clear(); fl = cost = 0; } void add_edge(int u, int v, long long f, long long c) { E[u].push_back(Edge(v, E[v].size(), f, c)); E[v].push_back(Edge(u, E[u].size() - 1, 0, -c)); } static bool cmp(const int &a, const int &b) { return dis[a] > dis[b]; } pair<long long, long long> flow(int k) { while (true) { for (int i = 0; i < n; i++) { dis[i] = INF; inq[i] = 0; } dis[s] = 0; vector<int> que; que.push_back(s); while (!que.empty()) { int u = que.back(); que.pop_back(); inq[u] = 0; for (int i = 0; i < E[u].size(); i++) { int v = E[u][i].v; long long w = E[u][i].c; if (E[u][i].f > 0 && dis[v] > dis[u] + w) { prv[v] = u; prvL[v] = i; dis[v] = dis[u] + w; if (!inq[v]) { inq[v] = 1; que.push_back(v); } } } if (u == s) { sort(que.begin(), que.end(), cmp); } } if (dis[t] == INF) break; long long tf = INF; for (int v = t, u, l; v != s; v = u) { u = prv[v]; l = prvL[v]; tf = min(tf, E[u][l].f); } for (int v = t, u, l; v != s; v = u) { u = prv[v]; l = prvL[v]; E[u][l].f -= tf; E[v][E[u][l].r].f += tf; } if (dis[t] > 0) break; cost += tf * dis[t]; fl += tf; if (fl == k) break; } return {fl, cost}; } } flow; int val[1 << 20]; int Index; void solve() { int n, k; scanf( %d %d , &n, &k); int a[1 << 20]; for (int i = 0; i < (1 << n); i++) scanf( %d , &a[i]); priority_queue<pair<int, pair<int, int>>, vector<pair<int, pair<int, int>>>, greater<pair<int, pair<int, int>>>> pq; for (int i = 0; i < (1 << n); i++) { if (__builtin_popcount(i) & 1) { for (int j = 0; j < n; j++) { pq.push(make_pair(a[i] + a[i ^ (1 << j)], make_pair(i, i ^ (1 << j)))); } while (pq.size() > 2 * n * k) pq.pop(); } } vector<pair<int, pair<int, int>>> v; while (!pq.empty()) { v.push_back(pq.top()); pq.pop(); } for (int i = 0; i < n * k * 2 && i < v.size(); i++) { int a = v[i].second.first, b = v[i].second.second; if (!val[a]) { val[a] = ++Index; } if (!val[b]) { val[b] = ++Index; } } flow.init(Index + 2, 0, Index + 1); for (int i = 0; i < (1 << n); i++) { if (val[i]) { if (__builtin_popcount(i) & 1) flow.add_edge(0, val[i], 1, -a[i]); else flow.add_edge(val[i], Index + 1, 1, -a[i]); } } for (int i = 0; i < n * k * 2 && i < v.size(); i++) { flow.add_edge(val[v[i].second.first], val[v[i].second.second], 1, 0); } printf( %lld n , -flow.flow(k).second); } int main() { int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; char a[N], b[N]; int n, T; int ans[N * 2], ct, rev; int rt, ch[N][2], fa[N], tg[N], col[N], sz[N]; int get(int x) { return ch[fa[x]][1] == x; } void pushdown(int x) { swap(ch[x][0], ch[x][1]), col[ch[x][0]] ^= 1, col[ch[x][1]] ^= 1, tg[ch[x][0]] ^= 1, tg[ch[x][1]] ^= 1; tg[x] = 0; } int s(int x, int k) { if (tg[x]) pushdown(x); if (sz[ch[x][0]] >= k) return s(ch[x][0], k); if (sz[ch[x][0]] + 1 == k) return x; return s(ch[x][1], k - sz[ch[x][0]] - 1); } char sc(int k) { return col[s(rt, k)] + 0 ; } void updata(int x) { sz[x] = sz[ch[x][0]] + sz[ch[x][1]] + 1; } void rotate(int x) { int k = get(x), y = fa[x]; ch[y][k] = ch[x][k ^ 1]; fa[ch[y][k]] = y; if (fa[y]) ch[fa[y]][ch[fa[y]][1] == y] = x; fa[x] = fa[y]; fa[y] = x; ch[x][k ^ 1] = y; updata(y); updata(x); } int q[N], cnt; void splay(int x) { int y; q[cnt = 1] = x; for (int i = x; fa[i]; i = fa[i]) q[++cnt] = fa[i]; for (int i = cnt; i >= 1; i--) if (tg[q[i]]) pushdown(q[i]); while (fa[x]) { y = fa[x]; if (fa[y]) rotate(get(x) == get(y) ? y : x); rotate(x); } } void work(int k) { if (k == n) { col[rt] ^= 1; tg[rt] ^= 1; return; } int y = s(rt, k + 1); splay(y); rt = y; col[ch[y][0]] ^= 1, tg[ch[y][0]] ^= 1; } void clr() { for (int i = 1; i <= n; i++) fa[i] = tg[i] = sz[i] = ch[i][0] = ch[i][1] = 0; } int ins(int l, int r) { if (l > r) return 0; int mid = l + r >> 1; col[mid] = a[mid] - 0 ; ch[mid][0] = ins(l, mid - 1); fa[ch[mid][0]] = mid; ch[mid][1] = ins(mid + 1, r); fa[ch[mid][1]] = mid; sz[mid] = sz[ch[mid][0]] + sz[ch[mid][1]] + 1; return mid; } int main() { scanf( %d , &T); while (T--) { ct = rev = 0; clr(); char c; int aaa = 1; scanf( %d%s%s , &n, a + 1, b + 1); rt = ins(1, n); for (int i = n; i; i--) if ((c = sc(i)) != b[i]) { if (sc(1) != c) ans[++ct] = 1, work(1); ans[++ct] = i; work(i); } sc(1); printf( %d , ct); for (int i = 1; i <= ct; i++) printf( %d , ans[i]); puts( ); } } |
#include <bits/stdc++.h> using namespace std; int SET(int N, int pos) { return N = N | (1 << pos); } int RESET(int N, int pos) { return N = N & ~(1 << pos); } bool CHECK(int N, int pos) { return (bool)(N & (1 << pos)); } template <typename T> inline T __lcm(T a, T b) { return (a * b) / __gcd(a, b); } struct node { long long x, y, cnt; }; int dx[] = {0, 1, 0, -1, -1, 1, -1, 1}; int dy[] = {1, 0, -1, 0, 1, 1, -1, -1}; long long a[1000000]; long long b[1000000]; long long c[1000000]; void solve() { long long n; cin >> n; if (n % 2 == 0) { cout << -1 << endl; return; } for (long long i = 0; i < n; i++) { c[i] = n - i - 1; } for (long long i = 0; i < n; i++) { a[i] = i; } for (long long i = 0; i < n; i++) { b[i] = c[i] - a[i]; if (b[i] < 0) { b[i] += n; } } for (long long i = 0; i < n; i++) { cout << a[i] << ; } cout << endl; for (long long i = 0; i < n; i++) { cout << b[i] << ; } cout << endl; for (long long i = 0; i < n; i++) { cout << c[i] << ; } cout << endl; } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int MOD = 1e9 + 7; const int MAXN = 3e5 + 5; const double PI = acos(-1); long long a[MAXN][2]; long long dp[MAXN][2][2]; int main(void) { int n, x; scanf( %d%d , &n, &x); for (int i = 1; i <= n; i++) { scanf( %lld , &a[i][0]); a[i][1] = a[i][0] * x; } dp[0][0][1] = 0; dp[0][1][1] = 0; dp[0][0][0] = 0; dp[0][1][0] = 0; long long ans = 0; for (int i = 1; i <= n; i++) { dp[i][0][0] = max(1ll * a[i][0], dp[i - 1][0][0] + 1ll * a[i][0]); dp[i][1][1] = max(1ll * a[i][1], dp[i - 1][1][1] + 1ll * a[i][1]); dp[i][1][0] = max(a[i][0], dp[i - 1][1][1] + 1ll * a[i][0]); dp[i][1][0] = max(dp[i][1][0], dp[i - 1][1][0] + 1ll * a[i][0]); dp[i][1][0] = max(dp[i][1][0], dp[i - 1][0][1] + 1ll * a[i][0]); dp[i][0][1] = max(a[i][1], dp[i - 1][0][1] + 1ll * a[i][1]); dp[i][0][1] = max(dp[i][0][1], dp[i - 1][0][0] + a[i][1]); ans = max(ans, dp[i][0][1]); ans = max(ans, dp[i][0][0]); ans = max(ans, dp[i][1][1]); ans = max(ans, dp[i][1][0]); } printf( %lld n , ans); } |
#include <bits/stdc++.h> using namespace std; const int M = 6e5 + 10, P = 490019; const double PI = acos(-1.0); int a[M << 1], b[M << 1], c[M << 1], pw[M], inv[M], C[M << 1], oo, n, m, cc, r[M << 1], N, l; struct cp { double x, y; cp(double _x = 0, double _y = 0) : x(_x), y(_y) {} } p[M << 1], q[M << 1], w[M << 1], x[M << 1], y[M << 1], u[M << 1], v[M << 1]; inline cp operator+(cp a, cp b) { return cp(a.x + b.x, a.y + b.y); } inline cp operator-(cp a, cp b) { return cp(a.x - b.x, a.y - b.y); } inline cp operator*(cp a, cp b) { return cp(a.x * b.x - a.y * b.y, a.x * b.y + a.y * b.x); } inline cp operator!(cp a) { return cp(a.x, -a.y); } void fft(cp *a) { for (int i = (0); i <= (N - 1); ++i) if (i < r[i]) swap(a[i], a[r[i]]); for (int mid = 1; mid < N; mid <<= 1) for (int R = mid << 1, j = 0; j < N; j += R) { cp *l = a + j, *r = a + j + mid, y; for (int k = 0; k < mid; ++k, ++l, ++r) y = (*r) * w[N / 2 / mid * k], *r = *l - y, *l = *l + y; } } void conv(int *a, int *b, int *c, int n, int m) { cp _u(0.5, 0), _v(0, -0.5), I(0, 1); for (N = 1, l = 0; N < n + m; N <<= 1, ++l) ; for (int i = (0); i <= (N - 1); ++i) r[i] = i & 1 ? r[i ^ 1] | (1 << l - 1) : r[i >> 1] >> 1, w[i] = cp(cos(2 * PI * i / N), sin(2 * PI * i / N)), p[i] = cp(a[i] >> 15, a[i] & 0x7fff), q[i] = cp(b[i] >> 15, b[i] & 0x7fff); fft(p); fft(q); for (int i = (0); i <= (N - 1); ++i) { int j = i ? N - i : 0; cp k1 = (p[i] + !p[j]) * _u, k2 = (q[i] + !q[j]) * _u, b1 = (p[i] - !p[j]) * _v, b2 = (q[i] - !q[j]) * _v; x[j] = k1 * k2, y[j] = k1 * b2, u[j] = b1 * k2, v[j] = b1 * b2; } for (int i = (0); i <= (N - 1); ++i) p[i] = x[i] + y[i] * I, q[i] = u[i] + v[i] * I; fft(p); fft(q); for (int i = (0); i <= (N - 1); ++i) { long long x = (long long)(p[i].x / N + 0.5) % P, y = (long long)(p[i].y / N + 0.5) % P, u = (long long)(q[i].x / N + 0.5) % P, v = (long long)(q[i].y / N + 0.5) % P; c[i] = ((x << 30) + (y + u << 15) + v) % P; } } int main() { scanf( %d%d%d , &n, &m, &cc); pw[0] = inv[1] = 1; for (int i = (0); i <= (n - 1); ++i) scanf( %d , &oo), a[1ll * i * i % (P - 1)] += oo; for (int i = (0); i <= (m - 1); ++i) scanf( %d , &oo), b[1ll * i * i * i % (P - 1)] += oo; for (int i = (1); i <= (P - 1); ++i) pw[i] = 1ll * pw[i - 1] * cc % P; for (int i = (0); i <= (2 * P - 4); ++i) C[i] = 1ll * i * (i - 1) / 2 % (P - 1); for (int i = (2); i <= (P - 1); ++i) inv[i] = 1ll * (P - P / i) * inv[P % i] % P; for (int i = (0); i <= (P - 2); ++i) a[i] = 1ll * a[i] * inv[pw[C[i]]] % P, b[i] = 1ll * b[i] * inv[pw[C[i]]] % P; conv(a, b, c, P - 2, P - 2); long long ans = 0; for (int i = (0); i <= (2 * P - 4); ++i) ans += 1ll * c[i] * pw[C[i]] % P; printf( %lld n , ans % P); return 0; } |
`timescale 1ns / 1ps
`include "../src/axis_scaler.v"
module test();
localparam RANDOMOUTPUT = 1;
localparam RANDOMINPUT = 1;
localparam integer C_REALDATA = 1;
localparam integer C_PIXEL_WIDTH = (C_REALDATA ? 8 : 16);
localparam integer C_SH_WIDTH = 12;
localparam integer C_SW_WIDTH = 12;
localparam integer C_MH_WIDTH = 12;
localparam integer C_MW_WIDTH = 12;
localparam integer C_CH0_WIDTH = 8;
localparam integer C_CH1_WIDTH = 0;
localparam integer C_CH2_WIDTH = 0;
/// 10ms / 5ns
localparam integer C_FSYNC_INTERVAL = 10 * 1000 * 1000 / 5;
wire[C_PIXEL_WIDTH-1:0] m_axis_tdata_tb ;
wire m_axis_tlast_tb ;
reg m_axis_tready_tb;
wire m_axis_tuser_tb ;
wire m_axis_tvalid_tb;
wire[C_PIXEL_WIDTH-1:0] s_axis_tdata_tb ;
wire s_axis_tlast_tb ;
wire s_axis_tready_tb;
wire s_axis_tuser_tb ;
reg s_axis_tvalid_tb;
reg[C_SH_WIDTH-1:0] s_height_tb = 10;
reg[C_SW_WIDTH-1:0] s_width_tb = 10;
reg resetn_tb;
reg[C_MH_WIDTH-1:0] m_height_tb = 240;
reg[C_MW_WIDTH-1:0] m_width_tb = 320;
integer fileR, picType, dataPosition, grayDepth;
reg[80*8:0] outputFileName;
reg[11:0] outputFileIdx = 0;
integer fileW = 0;
initial begin
if (C_REALDATA) begin
fileR=$fopen("a.pgm", "r");
$fscanf(fileR, "P%d\n%d %d\n%d\n", picType, s_width_tb, s_height_tb, grayDepth);
dataPosition=$ftell(fileR);
$display("header: %dx%d, %d", s_width_tb, s_height_tb, grayDepth);
m_height_tb = s_height_tb / 2;
m_width_tb = s_width_tb / 2;
$display("header: %dx%d, %d, %0dx%0d", s_width_tb, s_height_tb, grayDepth, m_width_tb, m_height_tb);
end
else begin
s_width_tb = 10;
s_height_tb = 10;
m_height_tb = 60;
m_width_tb = 60;
end
end
reg clk;
reg fsync_tb = 0;
initial begin
clk <= 1'b1;
forever #2.5 clk <= ~clk;
end
initial begin
m_axis_tready_tb <= 1'b0;
#0.2 m_axis_tready_tb <= 1'b1;
forever begin
#5 m_axis_tready_tb <= (RANDOMOUTPUT ? {$random}%2 : 1);
end
end
initial begin
resetn_tb <= 1'b0;
repeat (5) #5 resetn_tb <= 1'b0;
forever #5 resetn_tb <= 1'b1;
end
initial begin
fsync_tb <= 0;
repeat (10) #5 fsync_tb <= 0;
forever begin
repeat (1) #5 fsync_tb <= 1;
repeat (C_FSYNC_INTERVAL - 1) #5 fsync_tb <= 0;
end
end
reg[23:0] outcnt = 0;
reg[11:0] outline = 0;
////////////////////////////////////////////////////////////////////////// input
reg [C_SH_WIDTH-1:0] s_ridx;
reg [C_SW_WIDTH-1:0] s_cidx;
wire s_rlast;
wire s_clast;
assign s_rlast = (s_ridx == s_height_tb - 1);
assign s_clast = (s_cidx == s_width_tb - 1);
assign s_axis_tuser_tb = (s_ridx == 0 && s_cidx == 0);
assign s_axis_tlast_tb = (s_cidx == s_width_tb - 1);
always @ (posedge clk) begin
if (resetn_tb == 1'b0) begin
s_ridx <= 0;
s_cidx <= 0;
end
else if (s_axis_tvalid_tb && s_axis_tready_tb) begin
if (~s_clast) begin
s_cidx <= s_cidx + 1;
s_ridx <= s_ridx;
end
else if (~s_rlast) begin
s_cidx <= 0;
s_ridx <= s_ridx + 1;
end
else begin
s_cidx <= 0;
s_ridx <= 0;
end
end
end
////////////////////////// enable input ////////////////////////////////////////
reg frm_done;
wire en_input;
wire trans_frm_last;
assign trans_frm_last = (s_ridx == (s_height_tb - 1)
&& s_cidx == s_width_tb - 1
&& s_axis_tvalid_tb);
always @ (posedge clk) begin
if (resetn_tb == 0)
frm_done <= 1;
else if (trans_frm_last)
frm_done <= 1;
else if (fsync_tb)
frm_done <= 0;
end
reg randomresult;
always @ (posedge clk) begin
randomresult <= (RANDOMINPUT ? {$random}%2 : 1);
end
assign en_input = (~trans_frm_last && ~frm_done && randomresult);
always @ (posedge clk) begin
if (resetn_tb == 1'b0)
s_axis_tvalid_tb <= 1'b0;
else if (~s_axis_tvalid_tb || s_axis_tready_tb) begin
s_axis_tvalid_tb <= en_input;
end
end
generate
if (C_REALDATA) begin
reg [C_PIXEL_WIDTH-1:0] s_axis_tdata_tb_r ;
assign s_axis_tdata_tb = s_axis_tdata_tb_r;
always @ (posedge clk) begin
if (fsync_tb)
$fseek(fileR, dataPosition, 0);
end
always @ (posedge clk) begin
if (resetn_tb == 1'b0) begin
s_axis_tdata_tb_r <= 0;
end
else if ((~s_axis_tvalid_tb || s_axis_tready_tb)
&& en_input) begin
s_axis_tdata_tb_r <= $fgetc(fileR);
end
end
end
else begin
assign s_axis_tdata_tb = (s_ridx * 256 + s_cidx);
end
endgenerate
///////////////////////////////////////////////////// output
always @(posedge clk) begin
if (resetn_tb == 1'b0 || (outcnt >= m_height_tb * m_width_tb && m_axis_tready_tb)) begin
if (fileW == 0) begin
outputFileIdx <= outputFileIdx + 1;
$sformat(outputFileName, "output%0d.pgm", outputFileIdx);
fileW=$fopen(outputFileName, "w");
$display("outputFileName: %s - %0d", outputFileName, fileW);
$fwrite(fileW, "P%0d\n%0d %0d\n%0d\n", picType, m_width_tb, m_height_tb, grayDepth);
end
if (outcnt > 0) $display ("new output!");
outcnt <= 0;
outline <= 0;
end
else if (m_axis_tready_tb && m_axis_tvalid_tb) begin
//$display("output data to %s", outputFileName);
$fwrite(fileW, "%c", m_axis_tdata_tb);
if (m_axis_tuser_tb != (outcnt == 0)) begin
$display("error sof %t", $time);
end
if (m_axis_tlast_tb != ((outcnt+1) % m_width_tb == 0)) begin
$display("error eol %t", $time);
end
$write("%h ", m_axis_tdata_tb);
if (m_axis_tlast_tb) begin
$write(outline+1, " time: %t\n", $time);
outline <= outline + 1;
end
outcnt <= outcnt + 1;
if (outcnt == m_height_tb * m_width_tb - 1) begin
$fclose(fileW);
fileW = 0;
end
end
end
axis_scaler # (
.C_PIXEL_WIDTH(C_PIXEL_WIDTH),
.C_SH_WIDTH (C_SH_WIDTH ),
.C_SW_WIDTH (C_SW_WIDTH ),
.C_MH_WIDTH (C_MH_WIDTH ),
.C_MW_WIDTH (C_MW_WIDTH ),
.C_CH0_WIDTH (C_CH0_WIDTH ),
.C_CH1_WIDTH (C_CH1_WIDTH ),
.C_CH2_WIDTH (C_CH2_WIDTH )
) uut (
.m_axis_tdata(m_axis_tdata_tb),
.m_axis_tlast(m_axis_tlast_tb),
.m_axis_tready(m_axis_tready_tb),
.m_axis_tuser(m_axis_tuser_tb),
.m_axis_tvalid(m_axis_tvalid_tb),
.s_axis_tdata(s_axis_tdata_tb),
.s_axis_tlast(s_axis_tlast_tb),
.s_axis_tready(s_axis_tready_tb),
.s_axis_tuser(s_axis_tuser_tb),
.s_axis_tvalid(s_axis_tvalid_tb),
.clk(clk),
.resetn(resetn_tb),
.fsync(fsync_tb),
.s_height(s_height_tb),
.s_width(s_width_tb),
.m_height(m_height_tb),
.m_width(m_width_tb)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long OO = 1e8; const double EPS = (1e-7); vector<vector<int> > readAdjList() { int n, e; scanf( %d%d , &n, &e); vector<vector<int> > adjList(n + 1); for (int i = 0; i < (e); i++) { int u, v; scanf( %d%d , &u, &v); adjList[u].push_back(v); adjList[v].push_back(u); } return adjList; } void DFS(int node, vector<vector<int> >& adjList, vector<int>& visited) { visited[node] = true; for (int i = 0; adjList[node][i]; i++) { int child = adjList[node][i]; if (!visited[child]) DFS(child, adjList, visited); } } vector<int> BFS(int s, vector<vector<int> >& adjList) { vector<int> len(((int)(adjList).size()), OO); queue<pair<int, int> > q; q.push(make_pair(s, 0)); len[s] = 0; int cur, dep; while (!q.empty()) { pair<int, int> p = q.front(); q.pop(); cur = p.first; dep = p.second; for (int i = 0; adjList[cur][i]; i++) { int child = adjList[cur][i]; if (len[child] == OO) { q.push(make_pair(child, dep + 1)); len[child] = dep + 1; } } } return len; } int main() { int n; scanf( %d , &n); if (n == 35) { cout << 1 0 ; return 0; } int inch; (((double)(n % 36) / 3 - floor((double)(n % 36) / 3)) >= 0.5) ? inch = ceil((double)(n % 36) / 3) : inch = floor((double)(n % 36) / 3); int feet = n / 36; if (inch == 12) { feet++; inch = 0; } cout << feet << << inch; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DLYGATE4SD2_BEHAVIORAL_PP_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__dlygate4sd2 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD2_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; const int inf = 1000000009; int i, j, k, m, n, l; int ans; int f(int n, int m) { return n < m ? (n + (n % 2) * (m - 1)) / 2 : f(n - m, 2 * m); } int main() { cin >> n; cout << (n < 2 ? 0 : f(n - 2, 2)) << endl; return 0; } |
//Control circuit
`include "verilog/riscv_instr_defines.v"
module control
(
input wire[2:0] instr_funct3_ctl_i,
input wire[6:0] instr_funct7_ctl_i,
input wire[6:0] instr_opcode_ctl_i,
input wire is_r_type_ctl_i,
input wire is_i_type_ctl_i,
input wire is_s_type_ctl_i,
input wire is_b_type_ctl_i,
input wire is_u_type_ctl_i,
input wire is_j_type_ctl_i,
output wire[1:0] pc_sel_ctl_o,
output wire op1sel_ctl_o,
output wire[1:0] op2sel_ctl_o,
output wire[1:0] wb_sel_ctl_o,
output wire pc4_sel_ctl_o,
output wire mem_wr_ctl_o,
output wire cpr_en_ctl_o,
output wire rf_en_ctl_o,
output wire[5:0] alu_fun_ctl_o
);
wire[1:0] pc_sel_ctl;
wire op1sel_ctl;
wire[1:0] op2sel_ctl;
wire[1:0] wb_sel_ctl;
wire pc4_sel_ctl;
wire mem_wr_ctl;
wire cpr_en_ctl;
wire rf_en_ctl;
wire[5:0] alu_fun_ctl;
wire[3:0] instr_funct_ctl;
wire[4:0] instr_opc_ctl;
reg[16:0] controls;
assign pc_sel_ctl_o = pc_sel_ctl;
assign op1sel_ctl_o = op1sel_ctl;
assign op2sel_ctl_o = op2sel_ctl;
assign wb_sel_ctl_o = wb_sel_ctl;
assign pc4_sel_ctl_o = pc4_sel_ctl;
assign mem_wr_ctl_o = mem_wr_ctl;
assign cpr_en_ctl_o = cpr_en_ctl;
assign rf_en_ctl_o = rf_en_ctl;
assign alu_fun_ctl_o = alu_fun_ctl;
assign instr_funct_ctl = {instr_funct7_ctl_i[5], instr_funct3_ctl_i};
assign instr_opc_ctl = {instr_opcode_ctl_i[4], {1'b0, instr_funct3_ctl_i}};
assign {pc_sel_ctl, op1sel_ctl, op2sel_ctl,
wb_sel_ctl, pc4_sel_ctl, mem_wr_ctl,
cpr_en_ctl, rf_en_ctl, alu_fun_ctl} = controls;
always @ *
begin
if (is_r_type_ctl_i)
begin
case (instr_funct_ctl)
//alu_op_ctl:
//6'b000_00_0: ADD
//6'b000_00_1: SUB
//6'b000_01_0: shift left
//6'b000_10_0: logical shift right
//6'b000_11_0: arithmetic shift right
//6'b001_00_0: logical OR
//6'b010_00_0: logical AND
//6'b011_00_0: logical NOR
//6'b100_00_0: logical XOR
//pc_sel_ctl, op1sel_ctl, op2sel_ctl, wb_sel_ctl,
//pc4_sel_ctl,mem_wr_ctl, cpr_en_ctl, rf_en_ctl, alu_fun_ctl
`ADD : controls = 17'b00_0_11_01_0_0_0_1_000000;
`AND : controls = 17'b00_0_11_01_0_0_0_1_010000;
`OR : controls = 17'b00_0_11_01_0_0_0_1_001000;
`SLL : controls = 17'b00_0_11_01_0_0_0_1_000010;
`SLT : controls = 17'b00_0_11_01_0_0_0_1_101001;
`SLTU : controls = 17'b00_0_11_01_0_0_0_1_110001;
`SRA : controls = 17'b00_0_11_01_0_0_0_1_000110;
`SRL : controls = 17'b00_0_11_01_0_0_0_1_000100;
`SUB : controls = 17'b00_0_11_01_0_0_0_1_000001;
`XOR : controls = 17'b00_0_11_01_0_0_0_1_100000;
default : controls = 17'b00_0_00_01_0_0_0_0_100000;
endcase
end
else if (is_i_type_ctl_i)
begin
case (instr_opc_ctl)
//alu_op_ctl:
//6'b000_00_0: ADD
//6'b000_00_1: SUB
//6'b000_01_0: shift left
//6'b000_10_0: logical shift right
//6'b000_11_0: arithmetic shift right
//6'b001_00_0: logical OR
//6'b010_00_0: logical AND
//6'b011_00_0: logical NOR
//6'b100_00_0: logical XOR
//pc_sel_ctl, op1sel_ctl, op2sel_ctl, wb_sel_ctl,
//pc4_sel_ctl,mem_wr_ctl, cpr_en_ctl, rf_en_ctl, alu_fun_ctl
`LB : controls = 17'b00_0_01_00_0_0_0_1_000000;
`LBU : controls = 17'b00_0_01_00_0_0_0_1_000000;
`LH : controls = 17'b00_0_01_00_0_0_0_1_000000;
`LHU : controls = 17'b00_0_01_00_0_0_0_1_000000;
`LW : controls = 17'b00_0_01_00_0_0_0_1_000000;
`ADDI : controls = 17'b00_0_01_01_0_0_0_1_000000;
`ANDI : controls = 17'b00_0_01_01_0_0_0_1_010000;
`ORI : controls = 17'b00_0_01_01_0_0_0_1_001000;
`SLLI : controls = 17'b00_0_01_01_0_0_0_1_000010;
`SRLI : controls = 17'b00_0_01_01_0_0_0_1_000100;
`SLTI : controls = 17'b00_0_01_01_0_0_0_1_101001;
`SLTIU : controls = 17'b00_0_01_01_0_0_0_1_110001;
`SRAI : controls = 17'b00_0_01_01_0_0_0_1_000110;
`XORI : controls = 17'b00_0_01_01_0_0_0_1_100000;
`JALR : controls = 17'b10_0_01_10_1_0_0_1_000000;
default : controls = 17'b00_0_01_01_0_0_0_0_000000;
endcase
end
else if (is_s_type_ctl_i)
begin
case (instr_funct3_ctl_i)
//alu_op_ctl:
//6'b000_00_0: ADD
//6'b000_00_1: SUB
//6'b000_01_0: shift left
//6'b000_10_0: logical shift right
//6'b000_11_0: arithmetic shift right
//6'b001_00_0: logical OR
//6'b010_00_0: logical AND
//6'b011_00_0: logical NOR
//6'b100_00_0: logical XOR
//pc_sel_ctl, op1sel_ctl, op2sel_ctl, wb_sel_ctl,
//pc4_sel_ctl,mem_wr_ctl, cpr_en_ctl, rf_en_ctl, alu_fun_ctl
`SB : controls = 17'b00_0_01_01_0_1_0_0_000000;
`SH : controls = 17'b00_0_01_01_0_1_0_0_000000;
`SW : controls = 17'b00_0_01_01_0_1_0_0_000000;
default : controls = 17'b00_0_01_01_0_0_0_0_000000;
endcase
end
else if (is_b_type_ctl_i)
begin
case (instr_funct3_ctl_i)
//alu_op_ctl:
//6'b000_00_0: ADD
//6'b000_00_1: SUB
//6'b000_01_0: shift left
//6'b000_10_0: logical shift right
//6'b000_11_0: arithmetic shift right
//6'b001_00_0: logical OR
//6'b010_00_0: logical AND
//6'b011_00_0: logical NOR
//6'b100_00_0: logical XOR
//pc_sel_ctl, op1sel_ctl, op2sel_ctl, wb_sel_ctl,
//pc4_sel_ctl,mem_wr_ctl, cpr_en_ctl, rf_en_ctl, alu_fun_ctl
`BEQ : controls = 17'b01_0_11_00_0_0_0_0_000001;
`BNE : controls = 17'b01_0_11_00_0_0_0_0_000001;
`BLT : controls = 17'b01_0_11_00_0_0_0_0_000001;
`BGE : controls = 17'b01_0_11_00_0_0_0_0_000001;
`BLTU : controls = 17'b01_0_11_00_0_0_0_0_110001;
`BGEU : controls = 17'b01_0_11_00_0_0_0_0_010001;
default : controls = 17'b01_0_00_00_0_0_0_0_000001;
endcase
end
else if (is_u_type_ctl_i)
begin
case (instr_opcode_ctl_i)
//alu_op_ctl:
//6'b000_00_0: ADD
//6'b000_00_1: SUB
//6'b000_01_0: shift left
//6'b000_10_0: logical shift right
//6'b000_11_0: arithmetic shift right
//6'b001_00_0: logical OR
//6'b010_00_0: logical AND
//6'b011_00_0: logical NOR
//6'b100_00_0: logical XOR
//pc_sel_ctl, op1sel_ctl, op2sel_ctl, wb_sel_ctl,
//pc4_sel_ctl,mem_wr_ctl, cpr_en_ctl, rf_en_ctl, alu_fun_ctl
`AUIPC : controls = 17'b00_1_10_01_0_0_0_1_000000;
`LUI : controls = 17'b00_1_00_01_0_0_0_1_000000;
default : controls = 17'b01_1_10_00_0_0_0_0_000000;
endcase
end
else if (is_j_type_ctl_i)
begin
controls = 17'b01_1_01_10_0_0_0_1_000000;
end
else
begin
controls = 17'b00_0_00_00_0_0_0_0_000000;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; while (t--) { long long int minu = 1, temp = 0, n, ans = 0; cin >> n; ans = ((n) * (n + 1)) / 2; while (minu <= n) { temp += minu; minu *= 2; } ans -= (2 * temp); cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, d; cin >> n >> d; int in[n]; vector<pair<int, int>> c; in[0] = in[n - 1] = 0; for (int i = 1; i < n - 1; i++) cin >> in[i]; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; c.push_back({x, y}); } long long dis[n][n]; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { dis[i][j] = d * (abs(c[i].first - c[j].first) + abs(c[i].second - c[j].second)); if (i != 0 && i != n - 1 && i != j) dis[i][j] -= in[i]; } } for (int k = 0; k < n; k++) { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (dis[i][k] + dis[k][j] < dis[i][j]) dis[i][j] = dis[i][k] + dis[k][j]; } } } cout << dis[0][n - 1] << endl; } |
#include <bits/stdc++.h> char s[1000010]; int max_pos_by_allowed_and_len[1 << 20][21]; constexpr int full = (1 << 20) - 1; template <typename T> void mx(T& x, T y) { x = (x > y ? x : y); } void update(const int* __restrict__ a, int* __restrict__ b) { for (int i = 0; i < 21; i += 7) { mx(b[i + 0], a[i + 0]); mx(b[i + 1], a[i + 1]); mx(b[i + 2], a[i + 2]); mx(b[i + 3], a[i + 3]); mx(b[i + 4], a[i + 4]); mx(b[i + 5], a[i + 5]); mx(b[i + 6], a[i + 6]); } } int main() { scanf( %s , s); int n = strlen(s); for (int i = 0; i < n; ++i) s[i] -= a ; for (int i = 1; i <= n; ++i) { int used = 0; for (int j = i; j > 0; --j) { if ((used >> s[j - 1]) & 1) break; used |= (1 << s[j - 1]); max_pos_by_allowed_and_len[full ^ used][i - j + 1] = i; } } for (int mask = full; mask > 0; --mask) { for (int bit = 0; bit < 20; ++bit) { int updated = mask ^ (1 << bit); if (updated > mask) continue; update(&max_pos_by_allowed_and_len[mask][0], &max_pos_by_allowed_and_len[updated][0]); } } int ans = 1; for (int i = 1; i <= n; ++i) { int used = 0; for (int j = i; j > 0; --j) { if ((used >> s[j - 1]) & 1) break; used |= (1 << s[j - 1]); for (int other_len = 20; other_len >= 0; --other_len) { if (max_pos_by_allowed_and_len[used][other_len] > i) { mx(ans, i - j + 1 + other_len); break; } } } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int unibit[60] = {0}; long long a[200005]; long long unia[200005] = {0}; int main() { int n, k, x; cin >> n >> k >> x; long long orr = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; orr |= a[i]; long long b = a[i]; for (int j = 0; b > 0; j++) { if (b % 2 == 1) { if (unibit[j] == 0) unibit[j] = i; else unibit[j] = -1; } b /= 2; } } long long pow = 1; for (int i = 0; i < 35; i++) { if (unibit[i] > 0) { int j = unibit[i]; unia[j] += pow; } pow *= 2; } long long ans = 0; long long xx = 1; for (int i = 0; i < k; i++) xx *= (long long)x; for (int i = 1; i <= n; i++) { long long or2 = orr; or2 ^= unia[i]; a[i] *= xx; or2 |= a[i]; if (ans < or2) ans = or2; } cout << ans; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DIODE_BLACKBOX_V
`define SKY130_FD_SC_LS__DIODE_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__diode (
DIODE
);
input DIODE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DIODE_BLACKBOX_V
|
// FP16 Regular/Relaxed version.
// TODO: Implement overflow/underflow.
module FP16RMulS0Of2(
input clk,
input rst,
input [15:0] arg_0,
input [15:0] arg_1,
output ret_0,
output [4:0] ret_1,
output [4:0] ret_2,
output [11:0] ret_3);
wire s0;
wire s1;
wire [4:0] e0;
wire [4:0] e1;
wire [9:0] f0;
wire [9:0] f1;
wire [10:0] ff0;
wire [10:0] ff1;
wire [21:0] z;
wire [11:0] zz;
assign s0 = arg_0[15:15];
assign s1 = arg_1[15:15];
assign e0 = arg_0[14:10];
assign e1 = arg_1[14:10];
assign f0 = arg_0[9:0];
assign f1 = arg_1[9:0];
// sign
assign ret_0 = s0 ^ s1;
// exponent
assign ret_1 = e0;
assign ret_2 = e1;
assign ff0 = {(e0 == 0 ? 1'b0 : 1'b1), f0};
assign ff1 = {(e1 == 0 ? 1'b0 : 1'b1), f1};
assign z = ff0 * ff1;
assign zz = z[21:10];
// fraction
assign ret_3 = zz;
endmodule // FP16RMulS0Of2
module FP16RMulS1Of2(
input clk,
input rst,
input arg_0,
input [4:0] arg_1,
input [4:0] arg_2,
input [11:0] arg_3,
output [15:0] ret_0);
wire s;
wire c;
wire [9:0] fc;
wire [9:0] uc;
wire [6:0] e7;
wire [4:0] e;
wire underflow;
wire overflow;
wire infinput;
assign s = arg_0;
assign c = arg_3[11:11];
assign e7 = arg_1 + arg_2 - 15 + c;
assign fc = c ? arg_3[10:1] : arg_3[9:0];
assign infinput = (arg_1 == 31) || (arg_2 == 31);
// e7[6:6] negative by subtraction.
// e7[5:5] overflow (> 31) by addition.
assign underflow = e7[6:6];
assign overflow = !underflow && (e7[5:5] || e7[4:0] == 31 || infinput);
assign e = underflow ? 0 : (overflow ? 31 : e7[4:0]);
assign uc = (underflow || e7[4:0] == 0) ? 0 : fc;
assign ret_0 = {s, e, uc};
endmodule // FP16RMulS1Of2
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 239; int n, m, k; vector<set<int>> row; vector<set<int>> column; vector<set<int>> row_free; vector<set<int>> column_free; int get_row_left(int i, int to, int from) { auto it = row[i].lower_bound(from); if (it == row[i].begin()) { return to; } it--; if (to <= *(it) && *(it) <= from) { return *(it) + 1; } else { return to; } } int get_row_right(int i, int to, int from) { auto it = row[i].lower_bound(from); if (it == row[i].end()) { return to; } if ((*it) <= to) { return (*it) - 1; } else { return to; } } int get_column_up(int j, int to, int from) { auto it = column[j].lower_bound(from); if (it == column[j].begin()) { return to; } it--; if (to <= *(it) && *(it) <= from) { return *(it) + 1; } else { return to; } } int get_column_down(int j, int to, int from) { auto it = column[j].lower_bound(from); if (it == column[j].end()) { return to; } if ((*it) <= to) { return (*it) - 1; } else { return to; } } vector<pair<int, int>> all_next(int i, int j) { int ff = get_row_left(i, max(0, j - k), j); int ss = get_row_right(i, min(m - 1, j + k), j); int tt = get_column_up(j, max(0, i - k), i); int th = get_column_down(j, min(n - 1, i + k), i); vector<pair<int, int>> ans; if (j > 0) { auto it = row_free[i].lower_bound(ff); while (true) { if (it == row_free[i].end()) { break; } if (*(it) >= j) { break; } ans.push_back({i, *(it)}); it++; } } if (j + 1 < m) { auto it = row_free[i].upper_bound(j); while (true) { if (it == row_free[i].end()) { break; } if (*(it) > ss) { break; } ans.push_back({i, *(it)}); it++; } } if (i > 0) { auto it = column_free[j].lower_bound(tt); while (true) { if (it == column_free[j].end()) { break; } if (*(it) >= i) { break; } ans.push_back({*(it), j}); it++; } } if (i + 1 < n) { auto it = column_free[j].upper_bound(i); while (true) { if (it == column_free[j].end()) { break; } if (*(it) > th) { break; } ans.push_back({*(it), j}); it++; } } return ans; } void bfs(int si, int sj, int ei, int ej) { vector<vector<int>> d(n, vector<int>(m, inf)); d[si][sj] = 0; queue<pair<int, int>> q; q.push({si, sj}); row_free[si].erase(sj); column_free[sj].erase(si); while (!q.empty()) { auto tmp = q.front(); q.pop(); int ci = tmp.first; int cj = tmp.second; auto next = all_next(ci, cj); for (auto [ni, nj] : next) { if (d[ni][nj] > d[ci][cj] + 1) { d[ni][nj] = d[ci][cj] + 1; row_free[ni].erase(nj); column_free[nj].erase(ni); q.push({ni, nj}); } } } int res = d[ei][ej]; if (res == inf) { cout << -1; } else { cout << res; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> m >> k; row.resize(n); column.resize(m); row_free.resize(n); column_free.resize(m); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { char c; cin >> c; if (c == # ) { row[i].insert(j); column[j].insert(i); } else { row_free[i].insert(j); column_free[j].insert(i); } } } int si, sj, ei, ej; cin >> si >> sj >> ei >> ej; si--; sj--; ei--; ej--; bfs(si, sj, ei, ej); } |
/*
* Copyright (c) 2011-2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
module sramcontroller(
input clk,
input [29:0] addr,
input [31:0] indata,
output reg [31:0] outdata,
input re,
input we,
output read_sync,
output write_sync,
// sram port
input memclk,
output reg [17:0] sram_addr,
inout [15:0] sram_data,
output reg sram_ce,
output reg sram_re,
output reg sram_we
);
reg [29:0] latched_addr;
reg[1:0] state;
`define STATE_START 0
`define STATE_READ 1
`define STATE_WRITE 2
initial begin
sram_addr = 18'bzzzzzzzzzzzzzzzzzz;
sram_ce = 1;
sram_re = 1;
sram_we = 1;
state = `STATE_START;
end
assign read_sync = (state == `STATE_READ && memdone);
assign write_sync = (state == `STATE_WRITE && memdone);
reg [2:0] nextstate;
always @(re or we or memdone) begin
if (re)
nextstate = `STATE_READ;
else if (we)
nextstate = `STATE_WRITE;
else
nextstate = `STATE_START;
end
/* slow clock domain */
always @(posedge clk) begin
state <= nextstate;
case (nextstate)
`STATE_READ: begin
latched_addr <= addr;
end
`STATE_WRITE: begin
latched_addr <= addr;
end
endcase
end
/* fast (memclk) domain */
reg memdone;
wire sameaddr = (sram_addr >> 1 == latched_addr);
wire [15:0] writedata = (memstate == 1) ? indata[15:0] : indata[31:16];
assign sram_data = (!sram_we) ? writedata : 16'bzzzzzzzzzzzzzzzz;
reg [2:0] memstate;
`define MEMSTATE_START 0
`define MEMSTATE_READ1 1
`define MEMSTATE_READ2 2
`define MEMSTATE_READ_DONE 3
`define MEMSTATE_WRITE1 4
`define MEMSTATE_WRITE_DONE 5
initial begin
sram_addr <= 18'bzzzzzzzzzzzzzzzzzz;
memdone <= 0;
memstate <= 0;
end
/* read logic */
always @(posedge memclk) begin
case (state)
`STATE_START: begin
memstate <= `MEMSTATE_START;
memdone <= 0;
sram_ce <= 1;
sram_re <= 1;
sram_we <= 1;
end
`STATE_READ: begin
case (memstate)
default: begin
sram_addr <= latched_addr << 1;
memdone <= 0;
sram_ce <= 0;
sram_re <= 0;
sram_we <= 1;
memdone <= 0;
memstate <= `MEMSTATE_READ1;
end
`MEMSTATE_READ1: begin
outdata[15:0] <= sram_data;
memstate <= `MEMSTATE_READ2;
sram_addr <= sram_addr + 1;
end
`MEMSTATE_READ2: begin
outdata[31:16] <= sram_data; // XXX is this a hold time hazard?
sram_ce <= 1;
sram_re <= 1;
memdone <= 1;
if (sameaddr)
memstate <= `MEMSTATE_READ_DONE;
else
memstate <= `MEMSTATE_START;
end
`MEMSTATE_READ_DONE: begin
if (!sameaddr)
memstate <= `MEMSTATE_START;
end
endcase
end
`STATE_WRITE: begin
case (memstate)
default: begin
sram_addr <= addr;
memdone <= 0;
sram_ce <= 0;
sram_we <= 0;
sram_re <= 1;
memstate <= `MEMSTATE_WRITE1;
end
`MEMSTATE_WRITE1: begin
sram_addr <= sram_addr + 1;
memstate <= `MEMSTATE_WRITE_DONE;
end
`MEMSTATE_WRITE_DONE: begin
memdone <= 1;
sram_ce <= 1;
sram_we <= 1;
if (!sameaddr)
memstate <= `MEMSTATE_START;
end
endcase
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 110; const int M = 10010; int n, m; char mat[N][M]; int dir[2] = {-1, 1}; long long solve() { long long ans = 0; int x = 0, y = 0, d = 1; bool isLeft = true, isRight = true; int pos[2] = {0, 0}; while (true) { if (!isLeft && !isRight) return -1; if (x == n - 1) return ans; if (mat[x + 1][y] == . ) { ans++; x++; isLeft = isRight = true; pos[0] = pos[1] = y; } else if (y == pos[d]) { int ty = y + dir[d]; ans++; if (ty < 0 || ty >= m || mat[x][ty] == # ) { if (d == 0) isLeft = false; else isRight = false; d ^= 1; } else { pos[d] += dir[d]; if (mat[x][ty] == . ) y += dir[d]; else d ^= 1; } } else { ans += (long long)abs((long long)pos[d] - (long long)y); y = pos[d]; } } return -1; } int main() { while (scanf( %d%d%*c , &n, &m) != EOF) { for (int i = 0; i < n; i++) gets(mat[i]); long long ans = solve(); if (ans == -1) puts( Never ); else cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 51; const int mod = (int)1e9 + 7; long long dp0[N][N]; long long dp1[N][N]; long long C[N][N]; inline long long modpow(long long x, long long p) { long long res = 1; while (p) { if (p & 1) res = res * x % mod; x = x * x % mod; p >>= 1; } return res; } void solve() { long long i2 = modpow(2, mod - 2); C[0][0] = 1; for (int i = 1; i < N; i++) { C[i][0] = 1; for (int j = 1; j <= i; j++) { C[i][j] = (C[i - 1][j] + C[i - 1][j - 1]) % mod; } } memset(dp0, 0, sizeof(dp0)); memset(dp1, 0, sizeof(dp1)); int n, K; cin >> n >> K; dp1[0][0] = 1; dp0[1][0] = 1; for (int sz = 2; sz <= n; sz++) { for (int k = 0; k <= sz / 2; k++) { for (int szl = 0; szl < sz; szl++) { int szr = sz - 1 - szl; if (szl > szr) break; long long enumerate = sz == n ? 1 : sz; enumerate = enumerate * C[sz - 1][szl] % mod; for (int kl = 0; kl <= k; kl++) { if (szl == szr && kl > k - kl) break; if (szl == szr && kl == k - kl) enumerate = enumerate * i2 % mod; dp0[sz][k] += dp1[szl][kl] * dp1[szr][k - kl] % mod * enumerate; dp0[sz][k] %= mod; dp1[sz][k + 1] += (dp1[szl][kl] * dp0[szr][k - kl] + dp0[szl][kl] * dp1[szr][k - kl] + dp0[szl][kl] * dp0[szr][k - kl]) % mod * enumerate; dp1[sz][k + 1] %= mod; if (szl == szr && kl == k - kl) enumerate = enumerate * 2 % mod; } } } } cout << (dp0[n][K] + dp1[n][K]) % mod << endl; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const bool debugger1 = 0; const bool debugger2 = 0; const bool debugger3 = 0; const bool debugger4 = 0; const bool debugger5 = 0; const long long MOD = 1e9 + 7, P = 1e9 + 7; long long n; long long sca, scb; std::vector<pair<long long, long long> > liczby; int main() { scanf( %lld , &n); liczby.resize(2 * n); for (int i = 0; i < n; i++) scanf( %lld , &liczby[i].first), liczby[i].second = 1; for (int i = 0; i < n; i++) scanf( %lld , &liczby[n + i].first), liczby[n + i].second = 2; for (int i = 0; i < 2 * n; i++) liczby[i].first *= (-1); sort(liczby.begin(), liczby.end()); for (int i = 0; i < liczby.size(); i++) { if (liczby[i].second == 1) { if (i % 2 == 0) sca -= liczby[i].first; } else if (i % 2 == 1) scb -= liczby[i].first; } printf( %lld , sca - scb); return 0; } |
/**
* $Id: red_pitaya_pid_block.v -01-21 11:40:39Z matej.oblak $
*
* @brief Red Pitaya PID controller.
*
* @Author Matej Oblak
*
* (c) Red Pitaya http://www.redpitaya.com
*
* This part of code is written in Verilog hardware description language (HDL).
* Please visit http://en.wikipedia.org/wiki/Verilog
* for more details on the language used herein.
*/
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ()
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_trigger_block #(
//parameters for input pre-filter
parameter FILTERSTAGES = 1,
parameter FILTERSHIFTBITS = 5,
parameter FILTERMINBW = 1
)
(
// data
input clk_i , // clock
input rstn_i , // reset - active low
input [ 14-1: 0] dat_i , // input data
input [ 14-1: 0] phase1_i , // input phase to feed through
output [ 14-1: 0] dat_o , // output data
output [ 14-1: 0] signal_o , // output data
output trig_o , // trigger signal
// communication with PS
input [ 16-1: 0] addr,
input wen,
input ren,
output reg ack,
output reg [ 32-1: 0] rdata,
input [ 32-1: 0] wdata
);
//output states
localparam TTL = 4'd0;
localparam PHASE = 4'd1;
//settings
reg [ 32-1: 0] set_filter; // filter setting
reg [ 2-1: 0] trigger_source ;
reg [ 4-1: 0] output_select;
reg [ 14-1: 0] set_a_thresh ;
reg [ 14-1: 0] set_a_hyst ;
reg rearm;
reg auto_rearm;
reg [ 14-1: 0] phase_offset;
reg phase_abs;
// System bus connection
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
set_filter <= 32'd0;
trigger_source <= 2'b00;
output_select <= 4'b0000;
set_a_thresh <= 14'd0;
set_a_hyst <= 14'd20; // 2.5 mV by default
rearm <= 1'b0;
auto_rearm <= 1'b0;
phase_offset <= 14'd0;
phase_abs <= 1'b0;
end
else begin
if (addr==16'h100 && wen)
rearm <= 1'b1;
else
rearm <= 1'b0;
if (wen) begin
if (addr==16'h104) {phase_abs, auto_rearm} <= wdata[2-1:0];
if (addr==16'h108) trigger_source <= wdata[2-1:0];
if (addr==16'h10C) output_select <= wdata[4-1:0];
if (addr==16'h110) phase_offset <= wdata[14-1:0];
if (addr==16'h118) set_a_thresh <= wdata[14-1:0];
if (addr==16'h11C) set_a_hyst <= wdata[14-1:0];
if (addr==16'h120) set_filter <= wdata;
end
casez (addr)
16'h100 : begin ack <= wen|ren; rdata <= {{32-1{1'b0}},armed}; end
16'h104 : begin ack <= wen|ren; rdata <= {{32-1{2'b0}},phase_abs,auto_rearm}; end
16'h108 : begin ack <= wen|ren; rdata <= {{32-2{1'b0}},trigger_source}; end
16'h10C : begin ack <= wen|ren; rdata <= {{32-4{1'b0}},output_select}; end
16'h110 : begin ack <= wen|ren; rdata <= {{32-14{1'b0}},phase_offset}; end
16'h118 : begin ack <= wen|ren; rdata <= set_a_thresh; end
16'h11C : begin ack <= wen|ren; rdata <= set_a_hyst; end
16'h120 : begin ack <= wen|ren; rdata <= set_filter; end
16'h15C : begin ack <= wen|ren; rdata <= ctr_value[32-1:0]; end
16'h160 : begin ack <= wen|ren; rdata <= ctr_value[64-1:32]; end
16'h164 : begin ack <= wen|ren; rdata <= timestamp_trigger[32-1:0]; end
16'h168 : begin ack <= wen|ren; rdata <= timestamp_trigger[64-1:32]; end
16'h220 : begin ack <= wen|ren; rdata <= FILTERSTAGES; end
16'h224 : begin ack <= wen|ren; rdata <= FILTERSHIFTBITS; end
16'h228 : begin ack <= wen|ren; rdata <= FILTERMINBW; end
default: begin ack <= wen|ren; rdata <= 32'h0; end
endcase
end
end
//-----------------------------
// cascaded set of FILTERSTAGES low- or high-pass filters
wire signed [14-1:0] dat_i_filtered;
red_pitaya_filter_block #(
.STAGES(FILTERSTAGES),
.SHIFTBITS(FILTERSHIFTBITS),
.SIGNALBITS(14),
.MINBW(FILTERMINBW)
)
triggerfilter
(
.clk_i(clk_i),
.rstn_i(rstn_i),
.set_filter(set_filter),
.dat_i(dat_i),
.dat_o(dat_i_filtered)
);
//---------------------------------------------------------------------------------
// Trigger created from input signal - nearly identical with scope
reg [ 2-1: 0] adc_scht_ap ;
reg [ 2-1: 0] adc_scht_an ;
reg [ 14-1: 0] set_a_threshp ;
reg [ 14-1: 0] set_a_threshm ;
reg adc_trig_ap;
reg adc_trig_an;
always @(posedge clk_i) begin
set_a_threshp <= set_a_thresh + set_a_hyst ; // calculate positive
set_a_threshm <= set_a_thresh - set_a_hyst ; // and negative threshold
if (rstn_i == 1'b0) begin
adc_scht_ap <= 2'h0 ;
adc_scht_an <= 2'h0 ;
adc_trig_ap <= 1'b0 ;
adc_trig_an <= 1'b0 ;
end else begin
if ($signed(dat_i_filtered) >= $signed(set_a_thresh )) adc_scht_ap[0] <= 1'b1 ; // threshold reached
else if ($signed(dat_i_filtered) < $signed(set_a_threshm)) adc_scht_ap[0] <= 1'b0 ; // wait until it goes under hysteresis
if ($signed(dat_i_filtered) <= $signed(set_a_thresh )) adc_scht_an[0] <= 1'b1 ; // threshold reached
else if ($signed(dat_i_filtered) > $signed(set_a_threshp)) adc_scht_an[0] <= 1'b0 ; // wait until it goes over hysteresis
adc_scht_ap[1] <= adc_scht_ap[0] ;
adc_scht_an[1] <= adc_scht_an[0] ;
adc_trig_ap <= adc_scht_ap[0] && !adc_scht_ap[1] ; // make 1 cyc pulse
adc_trig_an <= adc_scht_an[0] && !adc_scht_an[1] ;
end
end
// trigger logic
reg trigger_signal;
reg armed;
reg [ 64 - 1:0] ctr_value ;
reg [ 64 - 1:0] timestamp_trigger;
reg [ 14 - 1:0] phase_processed;
reg [ 14 - 1:0] phase;
reg [ 14 - 1:0] output_data;
wire [ 14 - 1:0] phase_i;
wire [ 14 - 1:0] phase_sum;
//multiplexer for input phase (still TODO)
assign phase_i = phase1_i;
//account for offset
assign phase_sum = phase_i + phase_offset;
always @(posedge clk_i)
if (rstn_i == 1'b0) begin
trigger_signal <= 1'b0;
armed <= 1'b0;
ctr_value <= 64'h0;
timestamp_trigger <= 64'h0;
phase <= 14'd0;
output_data <= 14'd0;
phase_processed <= 14'd0;
end else begin
// bit 0 of trigger_source defines positive slope trigger, bit 1 negative_slope trigger
trigger_signal <= ((adc_trig_ap && trigger_source[0]) || (adc_trig_an && trigger_source[1])) && armed;
// disarm after trigger event, rearm when requested or explicitely or by auto_rearm;
armed <= (armed && (!trigger_signal)) || rearm || auto_rearm;
ctr_value <= ctr_value + 1'b1;
if ((phase_abs == 1'b1) && (phase_sum[14-1] == 1'b1))
phase_processed <= (~phase_sum)+14'd1;
else
phase_processed <= phase_sum;
if (trigger_signal==1'b1) begin
timestamp_trigger <= ctr_value; // take a timestamp
phase <= phase_processed;
end
// output_signal multiplexer
if (output_select==TTL)
output_data <= {1'b0,{13{trigger_signal}}};
else if (output_select==PHASE)
output_data <= phase;
end
assign dat_o = output_data;
assign signal_o = output_data;
assign trig_o = trigger_signal;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct info_t { int x, y, i; }; int main() { int n, m; scanf( %d %d , &n, &m); vector<info_t> from(m), to(m); vector<vector<int>> answer_from, answer_to; auto solve = [&](vector<info_t> &info, vector<vector<int>> &answer) { for (int i = 0; i < m; ++i) { scanf( %d %d , &info[i].x, &info[i].y); --info[i].x; --info[i].y; info[i].i = i; } sort(info.begin(), info.end(), [&](const info_t &a, const info_t &b) { return a.x < b.x || (a.x == b.x && a.y < b.y); }); while (true) { bool need = false; for (int i = 0; i < m; ++i) { if (info[i].x > i) { answer.push_back( vector<int>{info[i].x, info[i].y, info[i].x - 1, info[i].y}); --info[i].x; need = true; } } for (int i = m - 1; ~i; --i) { if (info[i].x < i) { answer.push_back( vector<int>{info[i].x, info[i].y, info[i].x + 1, info[i].y}); ++info[i].x; need = true; } } if (!need) { break; } } for (int i = 0; i < m; ++i) { while (info[i].y < info[i].i) { answer.push_back( vector<int>{info[i].x, info[i].y, info[i].x, info[i].y + 1}); ++info[i].y; } while (info[i].y > info[i].i) { answer.push_back( vector<int>{info[i].x, info[i].y, info[i].x, info[i].y - 1}); --info[i].y; } } }; solve(from, answer_from); solve(to, answer_to); sort(from.begin(), from.end(), [&](const info_t &a, const info_t &b) { return a.i < b.i; }); sort(to.begin(), to.end(), [&](const info_t &a, const info_t &b) { return a.i < b.i; }); for (int i = 0; i < m; ++i) { while (from[i].x < to[i].x) { answer_from.push_back( vector<int>{from[i].x, from[i].y, from[i].x + 1, from[i].y}); ++from[i].x; } while (from[i].x > to[i].x) { answer_from.push_back( vector<int>{from[i].x, from[i].y, from[i].x - 1, from[i].y}); --from[i].x; } } printf( %d n , answer_from.size() + answer_to.size()); for (auto v : answer_from) { printf( %d %d %d %d n , v[0] + 1, v[1] + 1, v[2] + 1, v[3] + 1); } reverse(answer_to.begin(), answer_to.end()); for (auto v : answer_to) { printf( %d %d %d %d n , v[2] + 1, v[3] + 1, v[0] + 1, v[1] + 1); } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast , unroll-loops ) using namespace std; const long long inf = 1ll << 60; const long long iinf = 2147483647; const long long mod = 998244353; const long long maxn = 1e3 + 5; long long pw(long long x, long long p) { long long ret = 1; while (p > 0) { if (p & 1) { ret *= x; ret %= mod; } x *= x; x %= mod; p >>= 1; } return ret; } long long inv(long long x) { return pw(x, mod - 2); } long long dp[5005][5005]; signed main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; long long n; cin >> n; vector<long long> vc(n); for (long long i = (0); i < (n); i++) { cin >> vc[i]; } for (long long i = (1); i < (n + 1); i++) { for (long long j = (1); j < (n - i + 1 + 1); j++) { if (i == 1) { dp[i][j] = vc[j - 1]; continue; } dp[i][j] = dp[i - 1][j] ^ dp[i - 1][j + 1]; } } for (long long i = (1); i < (n + 1); i++) { for (long long j = (1); j < (n - i + 1 + 1); j++) { dp[i][j] = max({dp[i][j], dp[i - 1][j], dp[i - 1][j + 1]}); } } long long q; cin >> q; for (long long i = (0); i < (q); i++) { long long l, r; cin >> l >> r; cout << dp[r - l + 1][l] << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { long long x, d; while (~scanf( %lld%lld , &x, &d)) { vector<pair<long long, int> > counts; long long sum = 0; long long num = 1; while (x > 0) { long long two = 1; int count = 0; while (two - 1 <= x) two *= 2, count++; two /= 2, count--; sum += count; counts.emplace_back(num, count); x -= two - 1; num += d; } printf( %lld n , sum); for (int i = 0; i < counts.size(); i++) for (int j = 0; j < counts[i].second; j++) printf( %lld , counts[i].first); printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, temp, sum = 0; cin >> n; int arr[n]; memset(arr, 0, sizeof(arr)); for (int i = 0; i < n; i++) { cin >> arr[i]; sum += arr[i]; if (i == 0) temp = arr[0]; else if (arr[i] > temp) temp = arr[i]; } while (((temp * n) - sum) <= sum) { temp++; } cout << temp; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_BLACKBOX_V
`define SKY130_FD_SC_HD__DLCLKP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlclkp (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long n, m, k, ans, last, d, x, y, a, b; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } void exgcd(long long a, long long b, long long& d, long long& x, long long& y) { if (!b) { x = 1, y = 0, d = a; } else { exgcd(b, a % b, d, y, x); y -= (a / b) * x; } } void check(long long x0, long long y0) { exgcd(a, b, d, x, y); if ((y0 - x0) % d != 0) return; long long tmp = abs(b / d); x *= (y0 - x0) / d; x = (x % tmp + tmp) % tmp; long long xx = x0 + 2 * n * x; if (xx < 0 || xx >= last) return; ans = min(ans, xx); } int main() { cin >> n >> m >> k; a = 2 * n, b = -2 * m; while (k--) { long long xx, yy; cin >> xx >> yy; ans = 1e18; last = n / gcd(n, m) * m; check(xx, yy); check(-xx, yy); check(xx, -yy); check(-xx, -yy); if (ans == 1e18) cout << -1 << endl; else cout << ans << endl; } } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Output Buffer
// /___/ /\ Filename : OBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/22/06 - CR#226003 - Added integer, real parameter type
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
`timescale 1 ps / 1 ps
`celldefine
module OBUF (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
parameter SLEW = "SLOW";
output O;
input I;
tri0 GTS = glbl.GTS;
bufif0 B1 (O, I, GTS);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on OBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
#1 $finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
//////////////////////////////////////////////////////////////////
////
////
//// AES CORE BLOCK
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// aes128_spec IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa,
//// Julio Cesar
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module aes_ip
(
//OUTPUTS
output int_ccf,
output int_err,
output dma_req_wr,
output dma_req_rd,
output PREADY,
output PSLVERR,
output [31:0] PRDATA,
//INPUTS
input [ 3:0] PADDR,
input [31:0] PWDATA,
input PWRITE,
input PENABLE,
input PSEL,
input PCLK,
input PRESETn
);
wire [31:0] col_out;
wire [31:0] key_out;
wire [31:0] iv_out;
wire end_aes;
wire [ 3:0] iv_en;
wire [ 3:0] iv_sel_rd;
wire [ 3:0] key_en;
wire [ 1:0] key_sel_rd;
wire [ 1:0] data_type;
wire [ 1:0] addr;
wire [ 1:0] op_mode;
wire [ 1:0] aes_mode;
wire start;
wire disable_core;
wire write_en;
wire read_en;
wire first_block;
//wire pwdata_host_interface;
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
//assign pwdata_host_interface = PWDATA[12:0];
host_interface HOST_INTERFACE
(
.key_en ( key_en ),
.col_addr ( addr ),
.col_wr_en ( write_en ),
.col_rd_en ( read_en ),
.key_sel ( key_sel_rd ),
.iv_en ( iv_en ),
.iv_sel ( iv_sel_rd ),
.int_ccf ( int_ccf ),
.int_err ( int_err ),
.chmod ( aes_mode ),
.mode ( op_mode ),
.data_type ( data_type ),
.disable_core ( disable_core ),
.first_block ( first_block ),
.dma_req_wr ( dma_req_wr ),
.dma_req_rd ( dma_req_rd ),
.start_core ( start ),
.PRDATA ( PRDATA ),
.PADDR ( PADDR ),
.PWDATA ( PWDATA[12:0] ),
.PWRITE ( PWRITE ),
.PENABLE ( PENABLE ),
.PSEL ( PSEL ),
.PCLK ( PCLK ),
.PRESETn ( PRESETn ),
.key_bus ( key_out ),
.col_bus ( col_out ),
.iv_bus ( iv_out ),
.ccf_set ( end_aes )
);
aes_core AES_CORE
(
.col_out ( col_out ),
.key_out ( key_out ),
.iv_out ( iv_out ),
.end_aes ( end_aes ),
.bus_in ( PWDATA ),
.iv_en ( iv_en ),
.iv_sel_rd ( iv_sel_rd ),
.key_en ( key_en ),
.key_sel_rd ( key_sel_rd ),
.data_type ( data_type ),
.addr ( addr ),
.op_mode ( op_mode ),
.aes_mode ( aes_mode ),
.start ( start ),
.disable_core ( disable_core ),
.write_en ( write_en ),
.read_en ( read_en ),
.first_block ( first_block ),
.rst_n ( PRESETn ),
.clk ( PCLK )
);
endmodule
|
`timescale 1ns/1ns
module udp_outbound_chain
(input clk_50,
input clk_100,
input [7:0] rxd,
input rxdv,
input rxlast,
output [7:0] txd,
output txdv,
output [15:0] hop_count,
output [7:0] submsg_rxd,
output submsg_rxdv,
output submsg_rxlast);
udp_outbound_chain_rx rx_inst
(.clk_50(clk_50), .clk_100(clk_100),
.rxd(rxd), .rxdv(rxdv), .rxlast(rxlast),
.hop_count(hop_count),
.submsg_rxd(submsg_rxd),
.submsg_rxdv(submsg_rxdv),
.submsg_rxlast(submsg_rxlast));
udp_outbound_chain_tx tx_inst
(.c(clk_50), .rxd(rxd), .rxdv(rxdv), .txd(txd), .txdv(txdv));
endmodule
`ifdef test_udp_outbound_chain
module udp_outbound_chain_tb();
wire c;
sim_clk #(125) clk_125(c);
reg [7:0] rxd;
reg rxdv, rxlast;
wire [7:0] submsg_rxd, txd;
wire submsg_rxdv, txdv;
udp_outbound_chain dut(.*);
wire [7:0] node2_txd, node2_submsg_rxd;
wire node2_txdv, node2_submsg_rxdv;
reg node2_rxlast;
udp_outbound_chain dut2
(.c(c),
.rxd(txd), .rxdv(txdv), .rxlast(node2_rxlast),
.txd(node2_txd), .txdv(node2_txdv),
.submsg_rxd(node2_submsg_rxd), .submsg_rxdv(node2_submsg_rxdv));
wire [7:0] node3_txd, node3_submsg_rxd;
wire node3_txdv, node3_submsg_rxdv;
reg node3_rxlast;
udp_outbound_chain dut3
(.c(c),
.rxd(node2_txd), .rxdv(node2_txdv), .rxlast(node3_rxlast),
.txd(node3_txd), .txdv(node3_txdv),
.submsg_rxd(node3_submsg_rxd), .submsg_rxdv(node3_submsg_rxdv));
localparam PKT_LEN = 24;
reg [7:0] pkt [PKT_LEN-1:0];
integer i;
initial begin
$dumpfile("udp_outbound_chain.lxt");
$dumpvars();
pkt[0] = 8'h1; // protocol low
pkt[1] = 8'h0; // protocol high
pkt[2] = 8'h0; // hop count low
pkt[3] = 8'h0; // hop count high
pkt[4] = 8'h0; // submsg addr low
pkt[5] = 8'h0; // submsg addr high
pkt[6] = 8'h2; // submsg len low
pkt[7] = 8'h0; // submsg len high
pkt[8] = 8'h12; // payload byte 0
pkt[9] = 8'h34; // payload byte 1
////
pkt[10] = 8'h1; // submsg addr low
pkt[11] = 8'h0; // submsg addr high
pkt[12] = 8'h2; // submsg len low
pkt[13] = 8'h0; // submsg len high
pkt[14] = 8'h56; // payload byte 0
pkt[15] = 8'h78; // payload byte 1
////
pkt[16] = 8'h2; // submsg addr low
pkt[17] = 8'h0; // submsg addr high
pkt[18] = 8'h4; // submsg len low
pkt[19] = 8'h0; // submsg len high
pkt[20] = 8'hab; // payload byte 0
pkt[21] = 8'hcd; // payload byte 1
pkt[22] = 8'hef; // payload byte 0
pkt[23] = 8'h42; // payload byte 1
////
rxd = 1'b0;
rxdv = 8'h0;
rxlast = 1'b0;
#100;
for (i = 0; i < PKT_LEN; i = i + 1) begin
wait(~c);
wait(c);
rxd <= pkt[i];
rxdv <= 1'b1;
end
wait(~c);
wait(c);
rxdv <= 1'b0;
rxd <= 8'h0;
for (i = 0; i < 20; i = i + 1) begin
wait(~c);
wait(c);
end
rxlast <= 1'b1;
node2_rxlast <= 1'b1;
node3_rxlast <= 1'b1;
wait(~c);
wait(c);
rxlast <= 1'b0;
node2_rxlast <= 1'b0;
node3_rxlast <= 1'b0;
#1000;
$finish();
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; template <class T> T max(T a, T b, T c) { return max(a, max(b, c)); } template <class T> T min(T a, T b, T c) { return min(a, min(b, c)); } const double PI = 2.0 * acos(0.0); const int mx[] = {0, 1, 0, -1}; const int my[] = {-1, 0, 1, 0}; int check(long long s) { int res = 0; while (s > 0) res += s % 10, s /= 10; return res; } int main() { vector<int> ans; int a, b, c; ans.clear(); scanf( %d%d%d , &a, &b, &c); for (int i = 1; i <= 81; i++) { long long tmp = b; for (int j = 1; j <= a; j++) tmp *= i; tmp += c; if (tmp < 1e9 && check(tmp) == i) ans.push_back(tmp); } sort(ans.begin(), ans.end()); printf( %d n , ans.size()); for (int i = 0; i < ans.size(); i++) { if (i > 0) putchar( ); printf( %d , ans[i]); } putchar( n ); return 0; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for arp
*/
module test_arp;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter CACHE_ADDR_WIDTH = 2;
parameter REQUEST_RETRY_COUNT = 4;
parameter REQUEST_RETRY_INTERVAL = 150;
parameter REQUEST_TIMEOUT = 400;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg s_eth_payload_axis_tuser = 0;
reg m_eth_hdr_ready = 0;
reg m_eth_payload_axis_tready = 0;
reg arp_request_valid = 0;
reg [31:0] arp_request_ip = 0;
reg arp_response_ready = 0;
reg [47:0] local_mac = 0;
reg [31:0] local_ip = 0;
reg [31:0] gateway_ip = 0;
reg [31:0] subnet_mask = 0;
reg clear_cache = 0;
// Outputs
wire s_eth_hdr_ready;
wire s_eth_payload_axis_tready;
wire m_eth_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
wire m_eth_payload_axis_tvalid;
wire m_eth_payload_axis_tlast;
wire m_eth_payload_axis_tuser;
wire arp_request_ready;
wire arp_response_valid;
wire arp_response_error;
wire [47:0] arp_response_mac;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tkeep,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tuser,
m_eth_hdr_ready,
m_eth_payload_axis_tready,
arp_request_valid,
arp_request_ip,
arp_response_ready,
local_mac,
local_ip,
gateway_ip,
subnet_mask,
clear_cache
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
m_eth_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_eth_payload_axis_tdata,
m_eth_payload_axis_tkeep,
m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast,
m_eth_payload_axis_tuser,
arp_request_ready,
arp_response_valid,
arp_response_error,
arp_response_mac
);
// dump file
$dumpfile("test_arp.lxt");
$dumpvars(0, test_arp);
end
arp #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.CACHE_ADDR_WIDTH(CACHE_ADDR_WIDTH),
.REQUEST_RETRY_COUNT(REQUEST_RETRY_COUNT),
.REQUEST_RETRY_INTERVAL(REQUEST_RETRY_INTERVAL),
.REQUEST_TIMEOUT(REQUEST_TIMEOUT)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// ARP requests
.arp_request_valid(arp_request_valid),
.arp_request_ready(arp_request_ready),
.arp_request_ip(arp_request_ip),
.arp_response_valid(arp_response_valid),
.arp_response_ready(arp_response_ready),
.arp_response_error(arp_response_error),
.arp_response_mac(arp_response_mac),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_cache(clear_cache)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5010 + 10; const int mod = 1e9 + 7; char s[N]; char t[N]; int d[N][N]; int main() { int n, m; cin >> n >> m; scanf( %s%s , s + 1, t + 1); int ans = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { d[i][j] = max(d[i - 1][j], d[i][j - 1]) - 1; if (s[i] == t[j]) { d[i][j] = d[i - 1][j - 1] + 2; d[i][j] = max(d[i][j], 2); } ans = max(ans, d[i][j]); } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct team { string nam; int pt, diff, get; } T[55]; int n; void gao(string s, int pt, int diff, int get) { for (int i = 0; i < n; i++) { if (s == T[i].nam) { T[i].pt += pt; T[i].diff += diff; T[i].get += get; break; } } } bool cmp(team a, team b) { if (a.pt != b.pt) return a.pt > b.pt; if (a.diff != b.diff) return a.diff > b.diff; return a.get > b.get; } void tostring(string &a, string &b, char *s) { int l = strlen(s); a = ; b = ; for (int i = 0; i < l; i++) { if (s[i] == - ) { for (int j = i + 1; j < l; j++) { b += s[j]; } return; } a += s[i]; } } int main() { while (cin >> n) { for (int i = 0; i < n; i++) cin >> T[i].nam, T[i].pt = 0, T[i].diff = 0, T[i].get = 0; ; for (int i = 0; i < n * (n - 1) / 2; i++) { char str[66]; string a, b; int sa, sb; scanf( %s %d:%d , str, &sa, &sb); tostring(a, b, str); if (sa > sb) { gao(a, 3, sa - sb, sa); gao(b, 0, sb - sa, sb); } else if (sa == sb) { gao(a, 1, sa - sb, sa); gao(b, 1, sb - sa, sb); } else { gao(a, 0, sa - sb, sa); gao(b, 3, sb - sa, sb); } } sort(T, T + n, cmp); vector<string> res; res.clear(); for (int i = 0; i < n / 2; i++) { res.push_back(T[i].nam); } sort(res.begin(), res.end()); for (int i = 0; i < res.size(); i++) { cout << res[i] << endl; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_2_V
`define SKY130_FD_SC_HDLL__NOR4_2_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_2 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor4_2 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_2_V
|
#include <bits/stdc++.h> int a[200010]; int main() { long long ans = 0; int m = 0, n; scanf( %d n , &n); for (int i = 1; i <= n; i++) { int a1, b1, a2, b2; scanf( %d%d%d%d n , &a1, &b1, &a2, &b2); if (a1 + b1 >= a2 + b2) { a[++m] = a1 + b1; a[++m] = a2 + b2; ans = ans + a1 + a2; } else if (a1 > b2) ans += a1 - b2; else if (a2 < b1) ans += a2 - b1; } std::sort(a + 1, a + m + 1); for (int i = 1; i <= m; i++) if (i & 1) ans -= a[i]; printf( %I64d n , ans); } |
// Stupid first CPU.
module SimpleCPU(clk, rst, cur_ins);
// Definitions.
parameter REG_SET_SIZE = 16;
parameter WORD_SIZE = 32;
// Instruction opcodes.
parameter OP_NOP = 32'b00000000000000000000000000000000;
parameter OP_INC = 32'b00000000000000000000000000000001;
parameter OP_DEC = 32'b00000000000000000000000000000010;
// Input ports.
input clk;
input rst;
input [WORD_SIZE-1:0] cur_ins;
// Define the set of registers.
reg [WORD_SIZE-1:0] regs [0:REG_SET_SIZE];
reg [WORD_SIZE-1:0] CPSR;
// Define aliases for the CPU registers.
`define REG_SP regs[13] // Stack pointer.
`define REG_LR regs[14] // Link register.
`define REG_PC regs[15] // Program counter.
// Define aliases for the CPU flags.
`define CPSR_V CPSR[28] // Overflow flag.
`define CPSR_C CPSR[29] // Carry flag.
`define CPSR_Z CPSR[30] // Zero flag.
`define CPSR_N CPSR[31] // Negative/less than flag.
// Local variables.
integer i;
// Advance on each 'clk' tick and reset on each 'rst' tick.
always @(posedge clk or posedge rst) begin
if (rst) begin
$display("Resetting the CPU.");
// Reset the flags register.
CPSR = 0;
// Reset the general purpose registers.
for (i = 0; i < REG_SET_SIZE; i = i + 1)
begin
regs[i] = 0;
end
end
// Increment the program counter.
`REG_PC = `REG_PC + 1;
// Debug: dump the state.
$display("Current state:");
$display(" r0:%8x r1:%8x r2:%8x r3:%8x r4:%8x r5:%8x r6:%8x r7:%8x", regs[0], regs[1], regs[2], regs[3], regs[4], regs[5], regs[6], regs[7]);
$display(" r8:%8x r9:%8x r10:%8x r11:%8x r12:%8x SP:%8x LR:%8x PC:%8x", regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15]);
$display(" cur_ins:%8x", cur_ins);
// Main instruction dispatcher.
case (cur_ins)
// No operation.
OP_NOP:
begin
$display("OP_NOP");
end
// Increment r0.
OP_INC:
begin
$display("OP_INC");
regs[0] = regs[0] + 1;
end
// Decrement r0.
OP_DEC:
begin
$display("OP_DEC");
regs[0] = regs[0] - 1;
end
// Handle unknown opcodes.
default:
begin
$display("Unknown opcode %8x", cur_ins);
end
endcase
end
endmodule
|
// Code your design here
module serializer(
clk, //clock to send serialized data on out line
reset, //reset counter to 0 on high
enable, //serialize while enable on high
in,
complete, //deserialized data
out //serialized data
);
parameter BITS = 32; //size of serializer
parameter BITS_COUNTER = 6; //size of counter, must be at least log2(BITS)
input clk, reset, enable;
input [BITS-1:0] in;
output reg complete;
output reg out;
reg [5:0] counter; //we need to know which array item (in) to read from
// always@(posedge reset) begin
// counter = 0;
// complete = 0;
// end
always@(posedge clk) begin
if (reset==1) begin
counter <= 6'b000000;
complete <=0;
end
else begin
if(enable && ~(counter==BITS)) begin //when counter gets to limit, it'll stop counting until it's reset
out <= in[counter];
//as long we're not resetting the counter
counter <= counter + 6'b000001;
complete <=0; //next item
end
else if (counter==BITS)begin
complete <=1;
counter <=6'b000000;
end
else begin
counter <= 6'b000000;
complete <=0;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:34:30 10/12/2013
// Design Name:
// Module Name: Logica_Barra
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Logica_Barra(
input clock,
input reset,
input actualizar_posicion,
input revisar_bordes,
input up_sync,
input down_sync,
output reg [8:0] barra_y);
/** Limite de la pantalla */
parameter LIMITE_INF_Y = 480 - `ALTO_BARRA;
parameter LIMITE_SUP_Y = `VELOCIDAD_BARRA;
initial
begin
barra_y <= `Y_INICIAL_BARRA;
end
always @ (posedge clock or posedge reset)
begin
if(reset)
begin
barra_y <= `Y_INICIAL_BARRA;
end //Fin reset
else
begin
if(actualizar_posicion)
begin
if(up_sync)
barra_y <= barra_y - `VELOCIDAD_BARRA ;
if(down_sync)
barra_y <= barra_y + `VELOCIDAD_BARRA ;
end
if(revisar_bordes)
begin
if ( barra_y > LIMITE_INF_Y )
barra_y <= LIMITE_INF_Y;
else if(barra_y < LIMITE_SUP_Y)
barra_y <= LIMITE_SUP_Y;
else
barra_y <= barra_y;
end
end //Fin else NO reset
end /** Fin always*/
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[2005][2005] = {0}; long long int n, t, m, h, l, r; int check(int v) { return v >= l && v <= r; } void solve() { cin >> n >> h >> l >> r; vector<int> v; for (int i = 0; i < n; i++) { cin >> t; v.push_back(t); } for (int i = 0; i <= n; i++) { for (int j = 0; j <= h; j++) dp[i][j] = INT32_MIN; } dp[0][0] = 0; for (int i = 1; i <= n; i++) { for (int j = 0; j < h; j++) { dp[i][j] = max(dp[i - 1][(j - v[i - 1] + h) % h], dp[i - 1][(j - v[i - 1] + 1 + h) % h]) + (j >= l && j <= r); } } int mx = 0; for (int i = 0; i < h; i++) { mx = max(mx, dp[n][i]); } cout << mx << n ; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, i; cin >> n; i = 1; while (n % i == 0) { i = i * 3; } cout << n / i + 1; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__CLKBUF_BEHAVIORAL_PP_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_BEHAVIORAL_PP_V |
`default_nettype none
module dsp_system_top;
wire clk;
wire reset;
wire [15:0] io_data_out;
wire io_wr_strb;
wire [15:0] io_data_in;
wire [7:0] io_addr_out;
wire io_rd_strb;
wire [15:0] pm_addr;
wire [31:0] pm_data;
wire [15:0] dm0_addr;
wire [15:0] dm0_datai;
wire [15:0] dm0_datao;
wire dm0_wr_en;
wire [15:0] dm1_addr;
wire [15:0] dm1_datai;
wire [15:0] dm1_datao;
wire dm1_wr_en;
clk_gen clock_generate(
.clk_o (clk)
);
reset_gen reset_generate(
.reset_o (reset)
);
//For debug purposes to keep track of the instructuion in the pipeline
reg [31:0] pm_data_p1;
reg [31:0] pm_data_p2;
reg [31:0] pm_data_p3;
reg [31:0] pm_data_p4;
reg [31:0] pm_data_p5;
reg [31:0] pm_data_p6;
reg [15:0] pc;
//For pipeline display in simulation
always@* begin
pm_data_p2 = dsp_core.pm_inst_bus;
pc = mem.xpm_addr_ff;
pm_data_p1 = mem.xpm_data;
end
//For pipeline display in simulation
always@(posedge clk) begin
pm_data_p3 <= pm_data_p2;
pm_data_p4 <= pm_data_p3;
pm_data_p5 <= pm_data_p4;
pm_data_p6 <= pm_data_p5;
end
dsp_core dsp_core(
.clk_i (clk),
.reset_i (reset),
.io_data_o (io_data_out),
.io_wr_strobe_o (io_wr_strb),
.io_data_i (io_data_in),
.io_rd_strobe_o (io_rd_strb),
.io_addr_o (io_addr_out),
.pm_addr_o (pm_addr),
.pm_data_i (pm_data),
.dm0_addr_o (dm0_addr),
.dm0_data_o (dm0_datao),
.dm0_wr_en_o (dm0_wr_en),
.dm0_data_i (dm0_datai),
.dm1_addr_o (dm1_addr),
.dm1_data_o (dm1_datao),
.dm1_wr_en_o (dm1_wr_en),
.dm1_data_i (dm1_datai)
);
tb_memories mem(
.clk_i (clk),
.reset_i (reset),
// Program memory
.xpm_data_o (pm_data),
.xpm_addr_i (pm_addr),
// DM0
.xdm0_data_o (dm0_datai),
.xdm0_addr_i (dm0_addr),
.xdm0_data_i (dm0_datao),
.xdm0_wr_en_i (dm0_wr_en),
// DM1
.xdm1_addr_i (dm1_addr),
.xdm1_data_i (dm1_datao),
.xdm1_wr_en_i (dm1_wr_en),
.xdm1_data_o (dm1_datai)
);
always @(posedge clk) begin
if(io_wr_strb) begin
case(io_addr_out)
8'b00010001: begin end
8'b00010010: begin
$display("End of program found");
$finish;
end
8'b00010011: $stop;
8'h21: begin end
8'h22: begin end
default: $display("Unknown IO write request");
endcase // case (io_addr_out)
end
end // always @ (posedge clk)
io_write #(.FILENAME("rtloutput.hex"))
write_out_file(
.clk_i (clk),
.reset_i (reset),
.io_wr_data_i (io_data_out),
.id_io_wr_en_i (io_wr_strb && (io_addr_out == 8'b00010001))
);
io_read #(.FILENAME("IOS0010"))
read_in_file(
.clk_i (clk),
.reset_i (reset),
.io_rd_data_o (io_data_in),
.id_io_rd_en_i (io_rd_strb)
);
wire [15:0] refdata;
io_read #(.FILENAME("reffile.hex"))
read_ref_file(
.clk_i (clk),
.reset_i (reset),
.io_rd_data_o (refdata),
.id_io_rd_en_i (io_wr_strb && (io_addr_out == 8'b00010001))
);
//Compare reference data with RTL generated data
always @(posedge clk) begin
if (io_wr_strb && (io_addr_out == 8'h11)) begin
//Comment out the following line for less output
$display("Comparing %x and %x",refdata,io_data_out);
if(refdata !== io_data_out) begin
$display("*** ERROR: reference data does not match output data");
//$finish;
$stop;
end
end
if (io_wr_strb && (io_addr_out == 8'h21)) begin
$display("Port 0x21: %x",io_data_out);
$stop;
end
if (io_wr_strb && (io_addr_out == 8'h22)) begin
$display("Port 0x22: %x",io_data_out);
end
end
endmodule |
//////////////////////////////////////////////////////////////////////////////
/// Copyright (c) 2012, Jahanzeb Ahmad
/// All rights reserved.
///
/// Redistribution and use in source and binary forms, with or without modification,
/// are permitted provided that the following conditions are met:
///
/// * Redistributions of source code must retain the above copyright notice,
/// this list of conditions and the following disclaimer.
/// * Redistributions in binary form must reproduce the above copyright notice,
/// this list of conditions and the following disclaimer in the documentation and/or
/// other materials provided with the distribution.
///
/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
/// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
/// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
/// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
/// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
/// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
/// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
/// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
/// POSSIBILITY OF SUCH DAMAGE.
///
///
/// * http://opensource.org/licenses/MIT
/// * http://copyfree.org/licenses/mit/license.txt
///
//////////////////////////////////////////////////////////////////////////////
/*!
EDID master for reading edid structure from monitor.
the output is in byte format in "sdadata" on the rising edge of out_en
*/
module edidmaster (rst_n,clk,sda,scl,stop_reading,address_w,start,address_r,reg0,sdadata,out_en);
input clk;
input stop_reading;
input rst_n;
output reg scl;
inout sda;
input start;
input [7:0] address_w;
input [7:0] address_r;
input [7:0] reg0;
output reg [7:0] sdadata;
output reg out_en;
wire sdain;
reg sdaout;
assign sda = (sdaout == 1'b0) ? 1'b0 : 1'bz;
assign sdain = sda;
//% state machine states
parameter INI = 0;
parameter WAIT_FOR_START = 1;
parameter GEN_START = 2;
parameter WRITE_BYTE_ADD_W = 3;
parameter FREE_SDA_ADD_W = 4;
parameter WAIT_WRITE_BYTE_ACK_ADD = 5;
parameter WRITE_BYTE_REG = 6;
parameter FREE_SDA_REG = 7;
parameter WAIT_WRITE_BYTE_ACK_REG = 8;
parameter WRITE_BYTE_ADD_R = 9;
parameter FREE_SDA_ADD_R = 10;
parameter WAIT_WRITE_BYTE_ACK_ADD_R = 11;
parameter READ_DATA = 12;
parameter SEND_READ_ACK = 13;
parameter RELESASE_ACK = 14;
parameter GEN_START2 = 15;
parameter SKIP1 = 16;
reg [4:0] state;
reg [8:0] scl_counter;
reg scl_q,middle_scl;
reg [2:0] bitcount;
assign scl_risingedge = (scl_q ^ scl) & scl;
assign scl_fallingedge = (scl_q ^ scl) & (~scl);
always @(posedge clk) begin
if (~rst_n) begin
scl_counter <=0;
scl <= 0;
middle_scl <= 0;
scl_q <= 0;
state <= INI;
bitcount <= 7;
sdadata <=0;
sdaout <= 1;
out_en <=0;
end else begin // clk
out_en <=0;
scl_counter <= scl_counter +1;
if (scl_counter == 499) begin
scl <= ~ scl;
scl_counter <= 0;
end
scl_q <= scl;
middle_scl <= 0;
if ((scl_counter == 256) & scl) begin
middle_scl <= 1;
end
case (state)
INI: begin //ini all signals //0
state <= WAIT_FOR_START;
scl_q <= 0;
bitcount <=7;
sdadata <=0;
sdaout <= 1;
end
WAIT_FOR_START: begin //1
if (start) begin
state <= GEN_START;
end
end
GEN_START : begin //2
if (middle_scl) begin
sdaout <= 0;
scl_counter <= 0;
state <= WRITE_BYTE_ADD_W;
end
end
WRITE_BYTE_ADD_W: begin//3
if (scl_fallingedge) begin
bitcount <= bitcount -1;
sdaout <= address_w[bitcount];
if (bitcount==0) begin
state <= FREE_SDA_ADD_W;
end
end
end
FREE_SDA_ADD_W: begin//4
if (scl_fallingedge) begin
sdaout <= 1;
state <= WAIT_WRITE_BYTE_ACK_ADD;
end
end
WAIT_WRITE_BYTE_ACK_ADD: begin//5
if (scl_risingedge) begin
if (~sdain) begin
state <= WRITE_BYTE_REG;
end else begin
state <= INI;
end
end
end
WRITE_BYTE_REG: begin//6
if (scl_fallingedge) begin
bitcount <= bitcount -1;
sdaout <= reg0[bitcount];
if (bitcount==0) begin
state <= FREE_SDA_REG;
end
end
end
FREE_SDA_REG: begin//7
if (scl_fallingedge) begin
sdaout <= 1;
state <= WAIT_WRITE_BYTE_ACK_REG;
end
end
WAIT_WRITE_BYTE_ACK_REG: begin//8
if (scl_risingedge) begin
if (~sdain) begin
state <= SKIP1;
end else begin
state <= INI;
end
end
end
SKIP1 : begin
if (scl_risingedge) begin
state <= GEN_START2;
end
end
GEN_START2 : begin //15
if (middle_scl) begin
sdaout <= 0;
scl_counter <= 0;
state <= WRITE_BYTE_ADD_R;
end
end
WRITE_BYTE_ADD_R: begin//9
if (scl_fallingedge) begin
bitcount <= bitcount -1;
sdaout <= address_r[bitcount];
if (bitcount==0) begin
state <= FREE_SDA_ADD_R;
end
end
end
FREE_SDA_ADD_R: begin//10
if (scl_fallingedge) begin
sdaout <= 1;
state <= WAIT_WRITE_BYTE_ACK_ADD_R;
end
end
WAIT_WRITE_BYTE_ACK_ADD_R: begin//11
if (scl_risingedge) begin
if (~sdain) begin
state <= READ_DATA;
end else begin
state <= INI;
end
end
end
READ_DATA: begin //12
if (scl_risingedge) begin
bitcount <= bitcount -1;
sdadata[bitcount] <= sdain;
if (bitcount==0) begin
out_en <= 1;
state <= SEND_READ_ACK;
end
end
end
SEND_READ_ACK: begin//13
if (scl_fallingedge) begin
if (stop_reading) begin
state <= INI;
sdaout <= 1; // negeative ack
end else begin
sdaout <= 0;
state <= RELESASE_ACK;
end
end
end
RELESASE_ACK: begin//14
if (scl_fallingedge) begin
sdaout <= 1;
state <= READ_DATA;
end
end
default : begin
state <= INI;
end
endcase
end
end
endmodule
|
module lab5_top(CLK, SW, KEY, RESET_N, LEDR, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0);
input CLK;
input [9:0] SW;
input [3:0] KEY;
input RESET_N;
output [9:0] LEDR;
output [6:0] HEX5;
output [6:0] HEX4;
output [6:0] HEX3;
output [6:0] HEX2;
output [6:0] HEX1;
output [6:0] HEX0;
wire RESET;
wire EN_L;
wire [7:0] IOA;
wire [7:0] IOB;
wire [7:0] IOC;
wire [7:0] IOD;
wire [7:0] IOE;
wire [7:0] IOF;
wire [7:0] IOG;
assign RESET = ~RESET_N;
assign EN_L = KEY[2];
lab5 daCore(
.CLK(CLK),
.RESET(RESET),
.IOA(IOA),
.IOB(IOB),
.IOC(IOC),
.EN_L(EN_L),
.IOD(IOD),
.IOE(IOE),
.IOF(IOF),
.IOG(IOG)
);
dual_reg_in inputs(
.CLK(CLK),
.IN(SW[7:0]),
.SEL(SW[8]),
.WEN_L(KEY[3]),
.OUTA(IOA),
.OUTB(IOB)
);
// PUSHBUTTON INPUT LOGIC
assign IOC[7:2] = 6'b0;
assign IOC[1] = ~KEY[1];
assign IOC[0] = ~KEY[0];
// LED ARRAY LOGIC
assign LEDR[9] = CLK;
assign LEDR[8] = 1'b0;
assign LEDR[7:0] = IOD;
// SEVEN-SEGMENT DISPLAY DRIVERS
hex_to_seven_seg upperIOG(
.B(IOG[7:4]),
.SSEG_L(HEX5)
);
hex_to_seven_seg lowerIOG(
.B(IOG[3:0]),
.SSEG_L(HEX4)
);
hex_to_seven_seg upperIOF(
.B(IOF[7:4]),
.SSEG_L(HEX3)
);
hex_to_seven_seg lowerIOF(
.B(IOF[3:0]),
.SSEG_L(HEX2)
);
hex_to_seven_seg upperIOE(
.B(IOE[7:4]),
.SSEG_L(HEX1)
);
hex_to_seven_seg lowerIOE(
.B(IOE[3:0]),
.SSEG_L(HEX0)
);
endmodule
|
module note2dds_5st_gen(clk, note, adder);
input wire clk;
input wire [6:0] note;
output [31:0] adder;
(* romstyle = "logic" *) reg [31:0] table_values;
reg [4:0] addr_reg;
wire [3:0] diap = (note < 12) ? 4'd00 :
(note < 24) ? 4'd01 :
(note < 36) ? 4'd02 :
(note < 48) ? 4'd03 :
(note < 60) ? 4'd04 :
(note < 72) ? 4'd05 :
(note < 84) ? 4'd06 :
(note < 96) ? 4'd07 :
(note < 108) ? 4'd08 :
(note < 120) ? 4'd09 : 4'd010 ;
wire [6:0] c_addr = note - (diap * 4'd012);
wire [3:0] divider = 4'd010 - diap;
always@(posedge clk) begin
addr_reg <= c_addr[3:0];
case(addr_reg)
4'd00: table_values <= 32'd0359575;
4'd01: table_values <= 32'd0380957;
4'd02: table_values <= 32'd0403610;
4'd03: table_values <= 32'd0427610;
4'd04: table_values <= 32'd0453037;
4'd05: table_values <= 32'd0479976;
4'd06: table_values <= 32'd0508516;
4'd07: table_values <= 32'd0538754;
4'd08: table_values <= 32'd0570790;
4'd09: table_values <= 32'd0604731;
4'd10: table_values <= 32'd0640691;
4'd11: table_values <= 32'd0678788;
4'd12: table_values <= 32'd0;
4'd13: table_values <= 32'd0;
4'd14: table_values <= 32'd0;
4'd15: table_values <= 32'd0;
endcase
end
assign adder = table_values >> divider;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 100005, INF = 1e18; void solve() { long long n, ans = 0, max = 0; cin >> n; ans = n / 2; cout << ans << n ; for (long long i = (long long)0; i < ans - 1; i++) { cout << 2 ; } if (n % 2 == 0) cout << 2 << n ; else cout << 3 << n ; } int32_t main() { std::ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long t = 1; while (t--) solve(); } |
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 5
*/
// Testbench for behavioral model for the circular FIFO
// Import the modules that will be tested for in this testbench
`include "fifo.v"
// IMPORTANT: To run this, try: ncverilog -f fifo.f +gui
module tb_fifo();
/**
* Depth = number of rows for the register file
*
* The construct base**exponent is not synthesizable for our
* tool and technology library set up. It should be with the latest
* version of Verilog, Verilog 2005
*/
parameter DEPTH = 8; // DEPTH = 2^DEPTH_P2 = 2^3
// Width of the register file
parameter WIDTH = 8;
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the FIFO queue
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// data_out & emp & full_cb output signals
wire [7:0] d_out;
wire empty_cb,full_cb;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// push, pop, reset, & clk
reg push_cb,pop_cb,rst,clock;
// data_in
reg [WIDTH-1:0] d_in;
// ============================================================
// Counter for loop to enumerate all the values of r
//integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of SIPO() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
FIFO fifo_cb (
// instance_name(signal name),
// Signal name can be the same as the instance name
d_out,empty_cb,full_cb,d_in,push_cb,pop_cb,rst,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
rst=1'd1; // Reset
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd45;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd231;
// Push 8...
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd230;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd37;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd174;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd179;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd235;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd39;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd201;
// Pop 8...
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
// Try push and pull
/*
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd0;
d_in=8'd18;
*/
// Push 3 in
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd18;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
/*
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd74;
#10
rst=1'd0;
push_cb=1'd1;
pop_cb=1'd0;
d_in=8'd138;
// Pop 3 out
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
#10
rst=1'd0;
push_cb=1'd0;
pop_cb=1'd1;
d_in=8'd12;
*/
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> #pragma optimize( SEX_ON_THE_BEACH ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( O3 ) #pragma GCC optimize( fast-math ) using ll = long long int; using ull = long long int; using dd = double; using ldd = long double; namespace Hashes { const int mod197 = 1e9 + 7; const int mod199 = 1e9 + 9; const int modfft = 998244353; int MOD = mod197; template <typename T = int> struct Hash { T me, mod; Hash() {} Hash(T _me, T _mod = MOD) { me = _me, mod = _mod; if (me >= mod) me %= mod; } Hash operator+(Hash to) { to.me += me; if (to.me >= to.mod) to.me -= to.mod; return to; } Hash operator-(Hash to) { to.me -= me; to.me *= -1; if (to.me < 0) to.me += to.mod; return to; } Hash operator*(Hash to) { to.me *= me; to.me %= to.mod; return to; } Hash& operator+=(Hash to) { me += to.me; if (me >= mod) me -= mod; return *this; } Hash& operator-=(Hash to) { me -= to.me; if (me < 0) me += mod; return *this; } Hash& operator*=(Hash to) { me *= to.me; me %= mod; return *this; } bool operator==(Hash to) { return me == to.me; } T operator*() { return me; } }; } // namespace Hashes namespace someUsefull { template <typename T1, typename T2> inline void checkMin(T1& a, T2 b) { if (a > b) a = b; } template <typename T1, typename T2> inline void checkMax(T1& a, T2 b) { if (a < b) a = b; } const int _popcount_size_ = 16; char _bits_count_[1 << _popcount_size_]; inline void _build_bits_count_() { for (int i = 1, j = 0; i < (1 << _popcount_size_); ++i) { if (i & (1 << (j + 1))) ++j; _bits_count_[i] = _bits_count_[i ^ (1 << j)] + 1; } } template <typename T1 = int, typename T2 = int> inline T1 popcnt(T2 x) { T1 ans = 0; while (x) { ans += _bits_count_[x & (1 << _popcount_size_) - 1]; x >>= _popcount_size_; } return ans; } } // namespace someUsefull using namespace std; using namespace Hashes; using namespace someUsefull; vector<vector<int>> gr; vector<vector<pair<int, ll>>> hr; set<pair<int, int>> br; vector<int> tin, tout, cmp; vector<int> was; vector<ll> pr; vector<ll> dp; vector<ll> ans; vector<int> cntST; vector<int> isMe; int TT; int t = 0; void dfs(int v, int p = -1) { tin[v] = tout[v] = ++t; was[v] = 1; for (int to : gr[v]) { if (to == p) continue; if (was[to] == 1) checkMin(tout[v], tin[to]); else { dfs(to, v); checkMin(tout[v], tout[to]); if (tout[to] > tin[v]) { br.insert({v, to}); br.insert({to, v}); } } } } void dfs2(int v, int c) { cmp[v] = c; for (int to : gr[v]) if (!cmp[to] && br.count({v, to}) == 0) dfs2(to, c); } void dfs3(int v, int p = -1) { cntST[v] = isMe[v]; for (pair<int, int> to : hr[v]) { if (to.first == p) continue; dfs3(to.first, v); cntST[v] += cntST[to.first]; } } void dpC(int v, int p = -1) { dp[v] += pr[v]; for (pair<int, int> to : hr[v]) { if (to.first == p) continue; dpC(to.first, v); if (cntST[to.first] != 0 && cntST[to.first] != TT) dp[v] += max(0ll, dp[to.first] - to.second); else dp[v] += dp[to.first]; } } void dpF(int v, int p = -1) { ans[v] = dp[v]; for (pair<int, int> to : hr[v]) { if (to.first == p) continue; if (cntST[to.first] != 0 && cntST[to.first] != TT) dp[v] -= max(0ll, dp[to.first] - to.second); else dp[v] -= dp[to.first]; cntST[v] -= cntST[to.first]; if (cntST[v] != 0 && cntST[v] != TT) dp[to.first] += max(0ll, dp[v] - to.second); else dp[to.first] += dp[v]; cntST[to.first] += cntST[v]; dpF(to.first, v); if (cntST[v] != 0 && cntST[v] != TT) dp[to.first] -= max(0ll, dp[v] - to.second); else dp[to.first] -= dp[v]; cntST[to.first] -= cntST[v]; if (cntST[to.first] != 0 && cntST[to.first] != TT) dp[v] += max(0ll, dp[to.first] - to.second); else dp[v] += dp[to.first]; cntST[v] += cntST[to.first]; } } void solve(int test) { int n, k, m; cin >> n >> m >> k; vector<int> inter(k); vector<ll> cc(n); vector<ll> w(m); for (int i = 0; i < k; ++i) cin >> inter[i]; for (int i = 0; i < n; ++i) cin >> cc[i]; for (int i = 0; i < m; ++i) cin >> w[i]; vector<pair<int, int>> ed; gr.resize(n); for (int i = 0; i < m; ++i) { int a, b; cin >> a >> b; --a; --b; ed.push_back({a, b}); gr[a].push_back(b); gr[b].push_back(a); } tin.resize(n); tout.resize(n); cmp.resize(n); was.resize(n); dfs(0); int c = 1; for (int i = 0; i < n; ++i) { if (cmp[i] == 0) { dfs2(i, c); c++; } } for (int i = 0; i < n; ++i) --cmp[i]; --c; hr.resize(c); pr.resize(c); dp.resize(c); ans.resize(c); cntST.resize(c); isMe.resize(c); for (int i : inter) isMe[cmp[i - 1]] = 1; for (int i = 0; i < n; ++i) { pr[cmp[i]] += cc[i]; } for (int i = 0; i < m; ++i) { if (br.count(ed[i])) { hr[cmp[ed[i].first]].push_back({cmp[ed[i].second], w[i]}); hr[cmp[ed[i].second]].push_back({cmp[ed[i].first], w[i]}); } } dfs3(0); TT = cntST[0]; dpC(0); 0; ; dpF(0); for (int i = 0; i < n; ++i) { cout << ans[cmp[i]] << ; } } signed main() { ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(0); _build_bits_count_(); int t = 1; for (int i = 0; i < t; ++i) { solve(i + 1); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41AI_1_V
`define SKY130_FD_SC_LS__O41AI_1_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o41ai_1 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41AI_1_V
|
//==================================================================================================
// Filename : musb_hazard_unit.v
// Created On : 2014-09-26 20:26:08
// Last Modified : 2015-05-31 22:58:43
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Hazard detection and pipeline control unit
// No MEM exception stall: using LSU signal to avoid loops
//==================================================================================================
`include "musb_defines.v"
module musb_hazard_unit(
input [4:0] id_rs, // Rs @ ID stage
input [4:0] id_rt, // Rt @ ID stage
input [4:0] ex_rs, // Rs @ EX stage
input [4:0] ex_rt, // Rt @ EX stage
input id_mtc0, // mtc0 instruction
input [4:0] ex_gpr_wa, // Write Address @ EX stage
input [4:0] mem_gpr_wa, // Write Address @ MEM stage
input [4:0] wb_gpr_wa, // Write Address @ WB stage
input id_branch, // Branch signal
input id_jump, // Branch signal
input ex_mem_to_gpr, // Selector: MEM -> GPR @ EX
input mem_mem_to_gpr, // Selector: MEM -> GPR @ MEM
input ex_gpr_we, // GPR write enable @ EX
input mem_gpr_we, // GPR write enable @ MEM
input wb_gpr_we, // GPR write enable @ WB
input ex_request_stall, // Ex unit request a stall
input dmem_request_stall, // LSU: stall for Data access
input imem_request_stall, // LSU: stall for Instruction Fetch
input if_exception_stall, // Stall waiting for possible exception
input id_exception_stall, // Stall waiting for possible exception
input ex_exception_stall, // Stall waiting for possible exception
input mem_exception_stall, //
output [1:0] forward_id_rs, // Forwarding Rs multiplexer: Selector @ ID
output [1:0] forward_id_rt, // Forwarding Rt multiplexer: Selector @ ID
output [1:0] forward_ex_rs, // Forwarding Rs multiplexer: Selector @ EX
output [1:0] forward_ex_rt, // Forwarding Rt multiplexer: Selector @ EX
output if_stall, // Stall pipeline register
output id_stall, // Stall pipeline register
output ex_stall, // Stall pipeline register
output ex_stall_unit, // Stall the EX unit.
output mem_stall, // Stall pipeline register
output wb_stall // Stall pipeline register
);
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
// no forwarding if reading register zero
wire id_rs_is_zero;
wire id_rt_is_zero;
wire ex_rs_is_zero;
wire ex_rt_is_zero;
// verify match: register address and write address (EX, MEM & WB)
wire id_ex_rt_match_mtc0;
wire id_ex_rt_match;
wire id_ex_rs_match;
wire id_mem_rs_match;
wire id_mem_rt_match;
wire id_wb_rs_match;
wire id_wb_rt_match;
wire ex_mem_rs_match;
wire ex_mem_rt_match;
wire ex_wb_rs_match;
wire ex_wb_rt_match;
// stall signals
wire stall_id_rs_mtc0;
wire stall_id_rs_rt_load_ex;
wire stall_id_rs_rt_branch;
wire stall_id_rs_rt_load_mem;
wire stall_ex_rs_rt_load_mem;
// forward signals
wire forward_mem_id_rs;
wire forward_mem_id_rt;
wire forward_wb_id_rs;
wire forward_wb_id_rt;
wire forward_mem_ex_rs;
wire forward_mem_ex_rt;
wire forward_wb_ex_rs;
wire forward_wb_ex_rt;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign id_rs_is_zero = (id_rs == 5'b0);
assign id_rt_is_zero = (id_rt == 5'b0);
assign ex_rs_is_zero = (ex_rs == 5'b0);
assign ex_rt_is_zero = (ex_rt == 5'b0);
assign id_ex_rt_match_mtc0 = (~id_rt_is_zero) & (id_rt == ex_gpr_wa) & id_mtc0; // Match register
assign id_ex_rs_match = (~id_rs_is_zero) & (id_rs == ex_gpr_wa) & ex_gpr_we; // Match registers
assign id_ex_rt_match = (~id_rt_is_zero) & (id_rt == ex_gpr_wa) & ex_gpr_we; // Match registers
assign id_mem_rs_match = (~id_rs_is_zero) & (id_rs == mem_gpr_wa) & mem_gpr_we; // Match registers
assign id_mem_rt_match = (~id_rt_is_zero) & (id_rt == mem_gpr_wa) & mem_gpr_we; // Match registers
assign id_wb_rs_match = (~id_rs_is_zero) & (id_rs == wb_gpr_wa) & wb_gpr_we; // Match registers
assign id_wb_rt_match = (~id_rt_is_zero) & (id_rt == wb_gpr_wa) & wb_gpr_we; // Match registers
assign ex_mem_rs_match = (~ex_rs_is_zero) & (ex_rs == mem_gpr_wa) & mem_gpr_we; // Match registers
assign ex_mem_rt_match = (~ex_rt_is_zero) & (ex_rt == mem_gpr_wa) & mem_gpr_we; // Match registers
assign ex_wb_rs_match = (~ex_rs_is_zero) & (ex_rs == wb_gpr_wa) & wb_gpr_we; // Match registers
assign ex_wb_rt_match = (~ex_rt_is_zero) & (ex_rt == wb_gpr_wa) & wb_gpr_we; // Match registers
assign stall_id_rs_mtc0 = id_ex_rt_match_mtc0;
assign stall_id_rs_rt_load_ex = (id_ex_rs_match | id_ex_rt_match) & ex_mem_to_gpr & id_branch;
assign stall_id_rs_rt_branch = (id_ex_rs_match | id_ex_rt_match) & id_branch;
assign stall_id_rs_rt_load_mem = (id_mem_rs_match | id_mem_rt_match) & mem_mem_to_gpr & id_branch;
assign stall_ex_rs_rt_load_mem = (ex_mem_rs_match | ex_mem_rt_match) & mem_mem_to_gpr;
assign forward_mem_id_rs = id_mem_rs_match & (~mem_mem_to_gpr); // No forward if instruction at MEM stage is a Load instruction
assign forward_mem_id_rt = id_mem_rt_match & (~mem_mem_to_gpr); // No forward if instruction at MEM stage is a Load instruction
assign forward_wb_id_rs = id_wb_rs_match;
assign forward_wb_id_rt = id_wb_rt_match;
assign forward_mem_ex_rs = ex_mem_rs_match & (~mem_mem_to_gpr); // No forward if instruction at MEM stage is a Load instruction
assign forward_mem_ex_rt = ex_mem_rt_match & (~mem_mem_to_gpr); // No forward if instruction at MEM stage is a Load instruction
assign forward_wb_ex_rs = ex_wb_rs_match;
assign forward_wb_ex_rt = ex_wb_rt_match;
//--------------------------------------------------------------------------
// Assign stall signals
//--------------------------------------------------------------------------
assign wb_stall = mem_stall;
assign mem_stall = dmem_request_stall | mem_exception_stall;
assign ex_stall_unit = mem_stall | stall_ex_rs_rt_load_mem | ex_exception_stall;
assign ex_stall = ex_stall_unit | ex_request_stall;
assign id_stall = ex_stall | stall_id_rs_mtc0 | stall_id_rs_rt_load_ex | stall_id_rs_rt_branch | stall_id_rs_rt_load_mem |
id_exception_stall | (if_stall & (id_branch | id_jump));
assign if_stall = imem_request_stall | if_exception_stall; // No id_stall to avoid loops
//--------------------------------------------------------------------------
// forwarding control signals
//--------------------------------------------------------------------------
// sel | ID stage | EX stage
//--------------------------------------------------------------------------
// 00 -> ID (no forwarding) | EX (no forwarding)
// 01 -> MEM | MEM
// 10 -> WB | WB
// 11 -> don't care | don't care
//--------------------------------------------------------------------------
assign forward_id_rs = (forward_mem_id_rs) ? 2'b01 : ((forward_wb_id_rs) ? 2'b10 : 2'b00);
assign forward_id_rt = (forward_mem_id_rt) ? 2'b01 : ((forward_wb_id_rt) ? 2'b10 : 2'b00);
assign forward_ex_rs = (forward_mem_ex_rs) ? 2'b01 : ((forward_wb_ex_rs) ? 2'b10 : 2'b00);
assign forward_ex_rt = (forward_mem_ex_rt) ? 2'b01 : ((forward_wb_ex_rt) ? 2'b10 : 2'b00);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module HLS_accel_dadd_64ns_64ns_64_5_full_dsp
#(parameter
ID = 12,
NUM_STAGE = 5,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
HLS_accel_ap_dadd_3_full_dsp_64 HLS_accel_ap_dadd_3_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(); cout.tie(); int n, m; cin >> n >> m; if (n == m) { cout << n << endl; return 0; } cout << 2 << endl; } |
// DEFINES
`define WIDTH 8 // Bit width
`define DEPTH 4 // Bit depth
module dpram(clock,
wren1,
wren2,
reset_n,
value_out,
value_out2,
value_in,
value_in2
);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input wren1;
input wren2;
input [`WIDTH-1:0] value_in;
input [`WIDTH-1:0] value_in2;
output [`WIDTH-1:0] value_out;
output [`WIDTH-1:0] value_out2;
wire [`WIDTH-1:0] value_out;
wire [`WIDTH-1:0] value_out2;
reg [`DEPTH-1:0] address_counter;
reg [`DEPTH-1:0] address_counter2;
reg [`WIDTH-1:0] temp;
reg [`WIDTH-1:0] temp2;
dual_port_ram inst1(
.we1(wren1),
.we2(wren2),
.clk(clock),
.data1(value_in),
.data2(value_in2),
.out1(value_out),
.out2(value_out2),
.addr1(address_counter),
.addr2(address_counter2));
always @(posedge clock)
begin
if (reset_n == 1'b1) begin
address_counter <= 4'b0000;
address_counter2 <= 4'b1111;
end
else
begin
address_counter <= address_counter + 1;
address_counter2 <= address_counter2 - 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); int a, b, c; cin >> a >> b >> c; int s = 0; int min = a < b ? a : b; int max = a > b ? a : b; s += min; if (c > (max + min)) s += (max + min); else s += c; if ((c + min) < max) s += c + min; else s += max; cout << s << endl; } |
#include <bits/stdc++.h> int ma[100005]; int main() { int n, k; scanf( %d%d , &n, &k); for (int i = 1; i <= k + 1; i++) { if (i & 1) printf( %d , i / 2 + 1); else printf( %d , k + 2 - i / 2); } int s = (k + 1) / 2 + 1; int e = k + 2 - (k + 1) / 2; for (int i = s + 1; i < e - 1; i++) { printf( %d , i); } for (int i = k + 2; i <= n; i++) { printf( %d , i); } if (s + 1 <= e - 1) printf( %d n , e - 1); return 0; } |
#include <bits/stdc++.h> using namespace std; struct P { long long x; long long y; bool operator<(const P &a) const { return y > a.y; } }; vector<long long> v[3]; int a, c, i, b, n, m, k, d; long long o[1333331]; int l[1111111]; int j[1111115]; int e[1111111]; int dx[10] = {0, 1, 0, -1, 1, 1, -1, -1}, dy[10] = {1, 0, -1, 0, 1, -1, 1, -1}, dz[10] = {0, 0, 0, 0, 1, -1}; long long x, y, mod = 1000000007, mod2 = 1000000009, mod3 = 2017; long long z; double pi = 3.14159265; P u[1]; queue<int> q; bool as(P a, P b) { if (a.x != b.x) return a.x < b.x; return a.y < b.y; } long long f(long long a, long long b) { for (; b;) { long long h = a; a = b; b = h % b; } return a; } int main() { scanf( %d , &a); for (int t = 1; t <= a; t++) scanf( %lld , &o[t]); for (int t = 2; t <= a; t++) scanf( %d , &l[t]); for (int t = a; t > 0; t--) o[l[t]] += o[t]; for (int t = a; t > 0; t--) if (o[1] / f(o[1], o[t]) <= a) { j[o[1] / f(o[1], o[t])]++; } for (int t = a; t > 0; t--) { for (int h = t * 2; h <= a; h += t) j[h] += j[t]; } for (int t = 1; t <= a; t++) if (j[t] >= t) e[t] = 1; for (int t = a; t > 0; t--) if (e[t]) { for (int h = t * 2; h <= a; e[t] %= mod, h += t) e[t] += e[h]; } printf( %d , e[1]); } |
#include <bits/stdc++.h> using namespace std; long long a[200005]; set<long long> ns; long long p2[100]; int main() { int n, i, j; int cnt = 0; long long t = 1; while (t < 2000000000) { cnt++; p2[cnt] = t; t *= 2; } cin >> n; for (i = 1; i <= n; i++) { scanf( %lld , &a[i]); ns.insert(a[i]); } sort(a + 1, a + 1 + n); for (i = 2; i < n; i++) { for (j = 1; j <= cnt; j++) { long long t1 = a[i] - p2[j], t2 = a[i] + p2[j]; if (ns.find(t1) != ns.end() && ns.find(t2) != ns.end()) { puts( 3 ); cout << t1 << << a[i] << << t2 << endl; return 0; } } } for (i = 2; i <= n; i++) { for (j = 1; j <= cnt; j++) { long long t1 = a[i] - p2[j]; if (ns.find(t1) != ns.end()) { puts( 2 ); cout << t1 << << a[i] << endl; return 0; } } } puts( 1 ); cout << a[1] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; bool spj(set<int>& s) { vector<int> v{s.begin(), s.end()}; return (v[2] == 3 * v[0] && v[1] == 2 * v[0]); } int main() { int n; scanf( %d , &n); vector<int> result; for (int i = n, factor = 1; i != 0; i /= 2, factor *= 2) { if (i == 3) { { result.push_back(factor); result.push_back(factor); result.push_back(3 * factor); break; } } int k = (i + 1) / 2; for (int j = 0; j < k; ++j) { result.emplace_back(factor); } } for (int x : result) { printf( %d , x); } } |
#include <bits/stdc++.h> using namespace std; int n; char grid[101][101]; bool rw[101], cl[101]; int main() { bool f, r = 0, c = 0; int cnt; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %s , grid[i]); f = 1; for (int j = 0; j < n; ++j) { f &= (grid[i][j] == E ); if (grid[i][j] == . ) rw[i] = cl[j] = 1; } c |= f; } for (int j = 0; j < n; ++j) { f = 1; for (int i = 0; i < n; ++i) { f &= (grid[i][j] == E ); } r |= f; } if (r && c) { printf( -1 n ); } else { cnt = 0; for (int i = 0; i < n; ++i) cnt += rw[i]; if (cnt == n) { for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { if (grid[i][j] == . ) { printf( %d %d n , i + 1, j + 1); break; } } } } else { for (int j = 0; j < n; ++j) { for (int i = 0; i < n; ++i) { if (grid[i][j] == . ) { printf( %d %d n , i + 1, j + 1); break; } } } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5010, inf = 0x7fffffff; bool has[maxn][maxn], flag = 0; int sum[maxn][maxn], n, m, l[10], r[10], req; long long ans; void init() { for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) sum[i][j] = sum[i - 1][j] + sum[i][j - 1] - sum[i - 1][j - 1] + (has[i][j] == 1); } int calculate(int x1, int y1, int x2, int y2) { return sum[x2][y2] - sum[x1][y2] - sum[x2][y1] + sum[x1][y1]; } void work(int up, int down, int left, int right, bool dir) { if (left == right || up == down) return; if (left + 1 == right && up + 1 == down) { ans += calculate(up, left, down, right) == req; return; } if (dir == 0) { int mid = (left + right) >> 1; work(up, down, left, mid, dir ^ 1); work(up, down, mid, right, dir ^ 1); for (int i = up; i < down; i++) { l[0] = r[0] = mid; for (int k = 1; k <= req + 1; k++) l[k] = left, r[k] = right; for (int j = i + 1; j <= down; j++) { for (int k = 1; k <= req + 1; k++) while (calculate(i, l[k], j, mid) >= k) l[k]++; for (int k = 1; k <= req + 1; k++) while (calculate(i, mid, j, r[k]) >= k) r[k]--; for (int k = 0; k <= req; k++) ans += (l[k] - l[k + 1]) * (r[req - k + 1] - r[req - k]); } } } else { int mid = (up + down) >> 1; work(up, mid, left, right, dir ^ 1); work(mid, down, left, right, dir ^ 1); for (int i = left; i < right; i++) { l[0] = r[0] = mid; for (int k = 1; k <= req + 1; k++) l[k] = up, r[k] = down; for (int j = i + 1; j <= right; j++) { for (int k = 1; k <= req + 1; k++) while (calculate(l[k], i, mid, j) >= k) l[k]++; for (int k = 1; k <= req + 1; k++) while (calculate(mid, i, r[k], j) >= k) r[k]--; for (int k = 0; k <= req; k++) ans += (l[k] - l[k + 1]) * (r[req - k + 1] - r[req - k]); } } } } int main() { while (scanf( %d%d%d , &n, &m, &req) == 3) { memset(has, 0, sizeof(has)); ans = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) scanf( %1d , &has[i][j]); init(); work(0, n, 0, m, n < m); printf( %I64d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int max(long long int a, long long int b) { if (a >= b) return a; else return b; } long long int min(long long int a, long long int b) { if (a >= b) return b; else return a; } long long int diff(long long int a, long long int b) { if (a >= b) return a - b; else return b - a; } long long int mod(long long int a) { if (a >= 0) return a; else return -a; } void pairsort(int a[], int b[], int n) { pair<int, int> pairt[n]; for (int i = 0; i < n; i++) { pairt[i].first = a[i]; pairt[i].second = b[i]; } sort(pairt, pairt + n); for (int i = 0; i < n; i++) { a[i] = pairt[i].first; b[i] = pairt[i].second; } } int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); char c; cin >> c; string s1, s2; char s[9] = { 6 , 7 , 8 , 9 , T , J , Q , K , A }; cin >> s1 >> s2; int ind1, ind2; if (s1[1] == s2[1]) { for (int i = 0; i < 9; i++) if (s[i] == s1[0]) ind1 = i; for (int i = 0; i < 9; i++) if (s[i] == s2[0]) ind2 = i; if (ind1 > ind2) cout << YES ; else cout << NO ; } else { if (s1[1] == c) cout << YES ; else cout << NO ; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void remax(T& A, T B) { if (A < B) A = B; } template <class T> inline void remin(T& A, T B) { if (A > B) A = B; } string ToString(long long num) { string ret; do { ret += ((num % 10) + 0 ); num /= 10; } while (num); reverse(ret.begin(), ret.end()); return ret; } long long ToNumber(string s) { long long r = 0, p = 1; for (int i = s.size() - 1; i >= 0; --i) r += (s[i] - 0 ) * p, p *= 10; return r; } long long Gcd(long long a, long long b) { while (a %= b ^= a ^= b ^= a) ; return b; } long long Power(long long base, long long power) { long long ret = 1; while (power) { if (power & 1) ret *= base; power >>= 1; base *= base; } return ret; } long long PowerMod(long long base, long long power, long long mod) { if (!power) return 1; if (power & 1) return (base * PowerMod(base, power - 1, mod)) % mod; return PowerMod((base * base) % mod, power >> 1, mod); } int Log(long long num, long long base) { int ret = 0; while (num) { ++ret; num /= base; } return ret; } int Count(long long mask) { int ret = 0; while (mask) { if (mask & 1) ++ret; mask >>= 1; } return ret; } inline void run() { int arr[2000]; int n, b, ans; scanf( %d%d , &n, &b); for (int i = 0; i < n;) scanf( %d , arr + i++); ans = b; for (int i = 0; i < n; ++i) for (int j = i + 1; j < n; ++j) remax(ans, arr[j] * (b / arr[i]) + b % arr[i]); printf( %d n , ans); } int main() { run(); return 0; } |
/*********************************************************************
* SYNOPSYS CONFIDENTIAL *
* *
* This is an unpublished, proprietary work of Synopsys, Inc., and *
* is fully protected under copyright and trade secret laws. You may *
* not view, use, disclose, copy, or distribute this file or any *
* information contained herein except pursuant to a valid written *
* license from Synopsys. *
*********************************************************************/
// Description: Carry Look-Ahead Adders
// Details:
//
// Four Bit Slice of Carry Look-Ahead Adder
//
// SUM[i] = A[i] xor B[i] xor Carry[i]
// GENERATE[i] = A[i] and B[i]
// PROPAGATE[i] = A[i] or B[i]
// CARRY[i] = GENERATE[i-1] or (PROPAGATE[i-1] and CARRY[i-1])
//
module CLA_4Bits(PP,GP,S,A,B,CI);
output PP,GP; // Carry Propagate & Generate Prime
output [3:0] S; // Sum
input [3:0] A,B; // Adder Inputs
input CI; // Carry In
wire [3:0] P = A | B;
wire [3:0] G = A & B;
wire C1 = G[0] | P[0]&CI;
wire C2 = G[1] | P[1]&C1;
wire C3 = G[2] | P[2]&C2;
wire [3:0] C = { C3, C2, C1, CI };
assign PP = & P[3:0];
assign GP = G[3] | P[3]&G[2] | P[3]&P[2]&G[1] | P[3]&P[2]&P[1]&G[0];
assign S = A ^ B ^ C ;
// always #1 $display ($time,,,"BIT CI=%b, C=%b, A=%b, B=%b, S=%b, P=%b, G=%b", CI, C, A, B, S, P, G);
endmodule
// Four Bit Carry Look-Ahead generator
//
module CLA_Gen_2Bits(PPP,GPP,C4,PP,GP,CI);
output PPP, GPP, C4;
input [1:0] PP, GP;
input CI;
assign C4=GP[0] | PP[0]&CI,
GPP=GP[1] | PP[1]&GP[0],
PPP=PP[1]&PP[0];
endmodule
// Four Bit Carry Look-Ahead generator
//
module CLA_Gen_4Bits(PPP,GPP,C4,C8,C12,PP,GP,CI);
output PPP, GPP, C4, C8, C12;
input [3:0] PP, GP;
input CI;
assign C4=GP[0] | PP[0]&CI,
C8=GP[1] | PP[1]&GP[0] | PP[1]&PP[0]&CI,
C12=GP[2] | PP[2]&GP[1] | PP[2]&PP[1]&GP[0] | PP[2]&PP[1]&PP[0]&CI,
GPP=GP[3] | PP[3]&GP[2] | PP[3]&PP[2]&GP[1] | PP[3]&PP[2]&PP[1]&GP[0],
PPP = & PP[3:0];
endmodule
// SixTeen Bit Slice Carry Look-Ahead Adder
//
module CLA_16Bits(PPP,GPP,S,A,B,CI);
output GPP, PPP;
output [15:0] S;
input [15:0] A,B;
input CI;
wire [3:0] PP, GP;
wire C4, C8, C12;
CLA_4Bits BITS30(PP[0],GP[0],S[3:0],A[3:0],B[3:0],CI),
BITS74(PP[1],GP[1],S[7:4],A[7:4],B[7:4],C4),
BITS118(PP[2],GP[2],S[11:8],A[11:8],B[11:8],C8),
BITS1512(PP[3],GP[3],S[15:12],A[15:12],B[15:12],C12);
CLA_Gen_4Bits GEN150(PPP,GPP,C4,C8,C12,PP[3:0],GP[3:0],CI);
// always #10 $display ($time,,,"G1 GP=%b, PP=%b, C=%b%b%b%b", GP, PP, C12,C8,C4,CI);
// always #10 $display ($time,,,"G1 A=%h, B=%h, S=%h", A, B, S);
endmodule
// Sixteen Bit Carry Look-Ahead Adder
/*
module CLA_16Bit_Adder(CO,S,A,B,CI);
output CO;
output [15:0] S;
input [15:0] A,B;
input CI;
wire PP, GP;
CLA_16Bits BITS15_0(PP,GP,S[15:0],A[15:0],B[15:0],CI);
assign CO = GP | PP&CI;
// always #10 $display ($time,,,"G2 GP=%b, PP=%b, C=%b", GP, PP, CI);
// always #10 $display ($time,,,"G2 A=%h, B=%h, S=%h", A, B, S);
endmodule
*/
// Thirty Two Bit Carry Look-Ahead Adder
//
module CLA_32Bit_Adder(CO,S,A,B,CI);
output CO;
output [31:0] S;
input [31:0] A,B;
input CI;
wire GPP, PPP;
wire [1:0] PP, GP;
wire C16, C32, C48;
CLA_16Bits BITS15_0(PP[0],GP[0],S[15:0],A[15:0],B[15:0],CI),
BITS31_16(PP[1],GP[1],S[31:16],A[31:16],B[31:16],C16);
CLA_Gen_2Bits GEN31_0(PPP,GPP,C16,PP[1:0],GP[1:0],CI);
assign CO = GPP | PPP&CI;
// always #10 $display ($time,,,"G2 GP=%b, PP=%b, C=%b%b", GP, PP, C16,CI);
// always #10 $display ($time,,,"G2 A=%h, B=%h, S=%h", A, B, S);
endmodule
// SixtyFour Bit Carry Look-Ahead Adder
/*
module CLA_64Bit_Adder(CO,S,A,B,CI);
output CO;
output [63:0] S;
input [63:0] A,B;
input CI;
wire GPP, PPP;
wire [3:0] PP, GP;
wire C16, C32, C48;
CLA_16Bits BITS15_0(PP[0],GP[0],S[15:0],A[15:0],B[15:0],CI),
BITS31_16(PP[1],GP[1],S[31:16],A[31:16],B[31:16],C16),
BITS47_32(PP[2],GP[2],S[47:32],A[47:32],B[47:32],C32),
BITS63_48(PP[3],GP[3],S[63:48],A[63:48],B[63:48],C48);
CLA_Gen_4Bits GEN63_0(PPP,GPP,C16,C32,C48,PP[3:0],GP[3:0],CI);
assign CO = GPP | PPP&CI;
// always #10 $display ($time,,,"G2 GP=%b, PP=%b, C=%b%b%b%b", GP, PP, C48,C32,C16,CI);
// always #10 $display ($time,,,"G2 A=%h, B=%h, S=%h", A, B, S);
endmodule
*/
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 5, INF = 0x3f3f3f3f; int a[maxn]; int last[maxn]; int main() { int n; while (cin >> n) { memset(last, INF, sizeof(last)); for (int i = 0; i < n; i++) { cin >> a[i]; last[a[i]] = i; } sort(last, last + maxn); cout << a[last[0]] << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; bool gone[1000000]; int n; int ord[1000000], put[1000000]; int main() { scanf( %i , &n); for (int(a) = 0; (a) < (n); (a)++) scanf( %i , ord + a); for (int(a) = 0; (a) < (n); (a)++) scanf( %i , put + a); int i = 0; for (int(a) = 0; (a) < (n); (a)++) { int res = 0; if (gone[put[a]] || i >= n) { printf( %i , res); continue; } while (ord[i] != put[a]) { gone[ord[i]] = true; i++; res++; } gone[ord[i]] = true; i++; res++; printf( %i , res); } printf( n ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBP_TB_V
`define SKY130_FD_SC_MS__DFBBP_TB_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfbbp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SET_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 RESET_B = 1'b1;
#200 SET_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 RESET_B = 1'b0;
#340 SET_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SET_B = 1'b1;
#540 RESET_B = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SET_B = 1'bx;
#680 RESET_B = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__dfbbp dut (.D(D), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBP_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_BEHAVIORAL_V |
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