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#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int n, tot, u, v; int c[N], head[N], last[N * 2], ver[N * 2]; void add(int x, int y) { ver[++tot] = y; last[tot] = head[x]; head[x] = tot; } void dfs(int x, int fa) { cout << x << ; for (int i = head[x]; i; i = last[i]) { int y = ver[i]; if (y == fa) continue; c[y] *= -1; dfs(y, x); } if (c[x] == -1 && x != 1) { cout << fa << << x << ; c[fa] *= -1; c[x] *= -1; } if (x != 1) { if (fa == 1) { for (int i = 1; i <= n; i++) { if (c[i] == -1) { cout << fa << ; c[fa] *= -1; return; } } } else { cout << fa << ; c[fa] *= -1; } } } int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> c[i]; for (int i = 1; i < n; i++) { cin >> u >> v; add(u, v); add(v, u); } dfs(1, -1); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; cin >> n >> k; pair<int, int> ar[k]; for (long long i = 0; i < k; i++) { cin >> ar[i].first >> ar[i].second; } set<long long> X, Y; long long atk, safe; for (int i = 0; i < k; i++) { X.insert(ar[i].first); Y.insert(ar[i].second); atk = 1ll * X.size() * n + 1ll * Y.size() * n - 1ll * X.size() * 1ll * Y.size(); safe = n * n - atk; cout << safe << ; } return 0; } |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////
//
// Summary:
//
// The RESOURCE_SHARING_CONTROL module allocates the BIT_ALIGN_MACHINE
// module to each of the 16 data channels of the interface. Each channel
// must be aligned one at a time, such that the RESOURCE_SHARING_CONTROL module
// must determine when training on a given channel is complete, and then
// switch the context to the next channel.
//
//----------------------------------------------------------------
module RCB_FRL_RESOURCE_SHARING_CONTROL (
input CLK,
input RST,
input DATA_ALIGNED,
output [3:0] CHAN_SEL,
output reg START_ALIGN,
output ALL_CHANNELS_ALIGNED
);
wire [6:0] COUNT_VALUE;
reg UD_DELAY;
reg COUNT_DELAY;
reg COUNT_CHAN;
reg [2:0] CS;
reg [2:0] NS;
parameter INIT = 3'b000;
parameter INC_CHAN_SEL = 3'b001;
parameter WAIT_8 = 3'b010;
parameter START_NEXT = 3'b011;
parameter LAST_CHAN = 3'b100;
parameter TRAIN_DONE = 3'b101;
parameter IDLE = 3'b110;
parameter START_LAST = 3'b111;
assign ALL_CHANNELS_ALIGNED = CS[2] & ~CS[1] & CS[0];
RCB_FRL_count_to_128 delay_counter(
.clk(CLK),
.rst(RST),
.count(COUNT_DELAY),
.ud(UD_DELAY),
.counter_value(COUNT_VALUE)
);
RCB_FRL_count_to_16x channel_counter(
.clk(CLK),
.rst(RST),
.count(COUNT_CHAN),
.counter_value(CHAN_SEL)
);
//CURRENT STATE LOGIC
always@(posedge CLK) begin
if (RST == 1'b1)
CS <= INIT;
else
CS <= NS;
end
//NEXT_STATE LOGIC
always @(CS or DATA_ALIGNED or COUNT_VALUE or CHAN_SEL) begin
case (CS)
INIT: begin
if (COUNT_VALUE < 7'h08 || DATA_ALIGNED == 1'b0)
NS <= INIT;
else
NS <= IDLE;
end
IDLE: NS <= INC_CHAN_SEL;
INC_CHAN_SEL: NS <= WAIT_8;
WAIT_8: begin
if (COUNT_VALUE < 7'h08)
NS <= WAIT_8;
else if (CHAN_SEL == 4'b0100)
NS <= START_LAST;
else
NS <= START_NEXT;
end
START_NEXT: NS <= INIT;
START_LAST: NS <= LAST_CHAN;
LAST_CHAN: begin
if (COUNT_VALUE < 7'h08 || DATA_ALIGNED == 1'b0)
NS <= LAST_CHAN;
else
NS <= TRAIN_DONE;
end
TRAIN_DONE: NS <= TRAIN_DONE;
default: NS <= INIT;
endcase
end
//OUTPUT LOGIC
always @(CS) begin
case (CS)
INIT: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b1;
UD_DELAY <= 1'b1;
START_ALIGN <= 1'b0;
end
IDLE: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b0;
UD_DELAY <= 1'b0;
START_ALIGN <= 1'b0;
end
INC_CHAN_SEL: begin
COUNT_CHAN <= 1'b1;
COUNT_DELAY <= 1'b0;
UD_DELAY <= 1'b0;
START_ALIGN <= 1'b0;
end
WAIT_8: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b1;
UD_DELAY <= 1'b1;
START_ALIGN <= 1'b0;
end
START_NEXT: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b0;
UD_DELAY <= 1'b0;
START_ALIGN <= 1'b1;
end
START_LAST: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b0;
UD_DELAY <= 1'b0;
START_ALIGN <= 1'b1;
end
LAST_CHAN: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b1;
UD_DELAY <= 1'b1;
START_ALIGN <= 1'b0;
end
TRAIN_DONE: begin
COUNT_CHAN <= 1'b0;
COUNT_DELAY <= 1'b0;
UD_DELAY <= 1'b0;
START_ALIGN <= 1'b0;
end
default: begin
COUNT_CHAN <= 1'b1;
COUNT_DELAY <= 1'b0;
UD_DELAY <= 1'b0;
START_ALIGN <= 1'b0;
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Use this file as a template for submitting bugs, etc.
// This module takes a single clock input, and should either
// $write("*-* All Finished *-*\n");
// $finish;
// on success, or $stop.
//
// The code as shown applies a random vector to the Test
// module, then calculates a CRC on the Test module's outputs.
//
// **If you do not wish for your code to be released to the public
// please note it here, otherwise:**
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by ____YOUR_NAME_HERE____.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] result; // From test of Test.v
// End of automatics
Test test (.*);
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'he58508de5310b541
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test
(
input clk,
input [63:0] crc,
input [31:0] cyc,
output wire [31:0] result);
wire enable = crc[32];
wire [31:0] d = crc[31:0];
logic [31:0] y;
always @(d iff enable == 1) begin
y <= d;
end
wire reset = (cyc < 10);
assert property (@(posedge clk iff enable)
disable iff (reset)
(crc != '0));
// Aggregate outputs into a single result vector
assign result = {32'h0, y};
endmodule
|
#include <bits/stdc++.h> using namespace std; void karem() { ios::sync_with_stdio(0); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } int main() { karem(); int n, s = 0, res = 0; cin >> n; vector<int> v(12); for (int i = int(0); i < 12; i++) cin >> v[i]; sort(v.begin(), v.end()); reverse(v.begin(), v.end()); for (int i = int(0); i < 12; i++) { if (s >= n) break; s += v[i]; res++; } if (s < n) cout << -1; else cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[10]; int main() { int n; while (scanf( %d , &n) != EOF) { memset(a, 0, sizeof(a)); for (int i = 1; i <= n; ++i) a[i % 9]++; long long ans = 0; for (int i = 0; i < 9; ++i) for (int j = 0; j < 9; ++j) ans += a[i] * a[j] * a[(i * j) % 9]; for (int i = 1; i <= n; ++i) ans -= n / i; cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int INF = 2147483647; int inf = -2147483648; const double PI = acos(-1.0); const double pi = 2 * asin(1.0); int vis[1000009]; int vi[1000009]; int main() { ios::sync_with_stdio(false); int a, b, c, d; cin >> a >> b >> c >> d; for (int i = 0; i <= 100; i++) { vis[b + a * i] = 1; } for (int i = 0; i <= 100; i++) { vi[d + c * i] = 1; } for (int i = 0; i < 1000009; i++) { if (vis[i] == 1 && vi[i] == 1) { cout << i << endl; return 0; } } cout << -1 << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFRTP_SYMBOL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; sort(arr, arr + n); int c[1005] = {0}; int u[1005] = {0}, t = 0; for (int i = 0; i < n; i++) { if (c[arr[i]] == 0) { u[t++] = arr[i]; } c[arr[i]]++; } int fans = 0; while (1) { int ans = -1; for (int i = 0; i < t; i++) { if (c[u[i]] > 0) { ans++; c[u[i]]--; } } if (ans <= 0) break; fans += ans; } cout << fans; } |
#include <bits/stdc++.h> int main() { long long k, l, c = 0; scanf( %I64d , &k); scanf( %I64d , &l); while (l % k == 0) { l /= k; c++; } if (c >= 0 && l == 1) printf( YES n%I64d , c - 1); else printf( NO ); } |
module Sec6_Top(
input [7:0] ADCData,
input reset_n,
output [2:0] sel,
output [6:0] segments,
output digit,
output CS_n,
output RD_n,
output WR_n
);
wire clk;
wire clk_slow;
wire [3:0] dispNum;
wire [8:0] voltage;
//This is an instance of a special, built in module that accesses our chip's oscillator
OSCH #("2.08") osc_int ( //"2.03" specifies the operating frequency, 2.03 MHz. Other clock frequencies can be found in the MachX02's documentation
.STDBY(1'b0), //Specifies active state
.OSC(clk), //Outputs clock signal to 'clk' net
.SEDSTDBY()); //Leaves SEDSTDBY pin unconnected
clock_counter counter_1(
.clk_i(clk),
.reset_n(reset_n),
.clk_o(clk_slow)
);
ADCinterface int(
.reset_n(reset_n),
.clk(clk),
.CS_n(CS_n),
.RD_n(RD_n),
.WR_n(WR_n)
);
Sec6_SM FSM_1(
.clk_i(clk_slow),
.reset_n(reset_n),
.sel(sel),
.digit(digit)
);
interpretADC interp(
.ADCData(ADCData),
.voltage(voltage)
);
determineNum det(
.sel(sel),
.ADCData(voltage),
// .reset_n(reset_n),
.dispNum(dispNum)
);
sevenSeg segDecoder(
.data(dispNum),
.segments(segments)
);
endmodule |
module hps_fpga (
clk_clk,
cpu_0_rx_0_external_connection_export,
cpu_0_rx_1_external_connection_export,
cpu_0_rx_2_external_connection_export,
cpu_0_rx_3_external_connection_export,
cpu_0_rx_4_external_connection_export,
cpu_0_rx_5_external_connection_export,
cpu_0_rx_6_external_connection_export,
cpu_0_rx_7_external_connection_export,
cpu_0_tx_0_external_connection_export,
cpu_0_tx_1_external_connection_export,
cpu_0_tx_2_external_connection_export,
cpu_0_tx_3_external_connection_export,
cpu_0_tx_4_external_connection_export,
cpu_0_tx_5_external_connection_export,
cpu_0_tx_6_external_connection_export,
cpu_0_tx_7_external_connection_export,
cpu_1_rx_0_external_connection_export,
cpu_1_rx_1_external_connection_export,
cpu_1_rx_2_external_connection_export,
cpu_1_rx_3_external_connection_export,
cpu_1_rx_4_external_connection_export,
cpu_1_rx_5_external_connection_export,
cpu_1_rx_6_external_connection_export,
cpu_1_rx_7_external_connection_export,
cpu_1_tx_0_external_connection_export,
cpu_1_tx_1_external_connection_export,
cpu_1_tx_2_external_connection_export,
cpu_1_tx_3_external_connection_export,
cpu_1_tx_4_external_connection_export,
cpu_1_tx_5_external_connection_export,
cpu_1_tx_6_external_connection_export,
cpu_1_tx_7_external_connection_export,
hps_0_h2f_reset_reset_n,
hps_io_hps_io_emac1_inst_TX_CLK,
hps_io_hps_io_emac1_inst_TXD0,
hps_io_hps_io_emac1_inst_TXD1,
hps_io_hps_io_emac1_inst_TXD2,
hps_io_hps_io_emac1_inst_TXD3,
hps_io_hps_io_emac1_inst_RXD0,
hps_io_hps_io_emac1_inst_MDIO,
hps_io_hps_io_emac1_inst_MDC,
hps_io_hps_io_emac1_inst_RX_CTL,
hps_io_hps_io_emac1_inst_TX_CTL,
hps_io_hps_io_emac1_inst_RX_CLK,
hps_io_hps_io_emac1_inst_RXD1,
hps_io_hps_io_emac1_inst_RXD2,
hps_io_hps_io_emac1_inst_RXD3,
hps_io_hps_io_sdio_inst_CMD,
hps_io_hps_io_sdio_inst_D0,
hps_io_hps_io_sdio_inst_D1,
hps_io_hps_io_sdio_inst_CLK,
hps_io_hps_io_sdio_inst_D2,
hps_io_hps_io_sdio_inst_D3,
hps_io_hps_io_usb1_inst_D0,
hps_io_hps_io_usb1_inst_D1,
hps_io_hps_io_usb1_inst_D2,
hps_io_hps_io_usb1_inst_D3,
hps_io_hps_io_usb1_inst_D4,
hps_io_hps_io_usb1_inst_D5,
hps_io_hps_io_usb1_inst_D6,
hps_io_hps_io_usb1_inst_D7,
hps_io_hps_io_usb1_inst_CLK,
hps_io_hps_io_usb1_inst_STP,
hps_io_hps_io_usb1_inst_DIR,
hps_io_hps_io_usb1_inst_NXT,
hps_io_hps_io_uart0_inst_RX,
hps_io_hps_io_uart0_inst_TX,
led_external_connection_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
noc_clock_clk,
noc_ctrl_0_external_connection_export,
noc_ctrl_1_external_connection_export,
noc_status_0_external_connection_export,
noc_status_1_external_connection_export,
pll_0_outclk0_clk,
reset_reset_n,
sw_external_connection_export);
input clk_clk;
input [31:0] cpu_0_rx_0_external_connection_export;
input [31:0] cpu_0_rx_1_external_connection_export;
input [31:0] cpu_0_rx_2_external_connection_export;
input [31:0] cpu_0_rx_3_external_connection_export;
input [31:0] cpu_0_rx_4_external_connection_export;
input [31:0] cpu_0_rx_5_external_connection_export;
input [31:0] cpu_0_rx_6_external_connection_export;
input [31:0] cpu_0_rx_7_external_connection_export;
output [31:0] cpu_0_tx_0_external_connection_export;
output [31:0] cpu_0_tx_1_external_connection_export;
output [31:0] cpu_0_tx_2_external_connection_export;
output [31:0] cpu_0_tx_3_external_connection_export;
output [31:0] cpu_0_tx_4_external_connection_export;
output [31:0] cpu_0_tx_5_external_connection_export;
output [31:0] cpu_0_tx_6_external_connection_export;
output [31:0] cpu_0_tx_7_external_connection_export;
input [31:0] cpu_1_rx_0_external_connection_export;
input [31:0] cpu_1_rx_1_external_connection_export;
input [31:0] cpu_1_rx_2_external_connection_export;
input [31:0] cpu_1_rx_3_external_connection_export;
input [31:0] cpu_1_rx_4_external_connection_export;
input [31:0] cpu_1_rx_5_external_connection_export;
input [31:0] cpu_1_rx_6_external_connection_export;
input [31:0] cpu_1_rx_7_external_connection_export;
output [31:0] cpu_1_tx_0_external_connection_export;
output [31:0] cpu_1_tx_1_external_connection_export;
output [31:0] cpu_1_tx_2_external_connection_export;
output [31:0] cpu_1_tx_3_external_connection_export;
output [31:0] cpu_1_tx_4_external_connection_export;
output [31:0] cpu_1_tx_5_external_connection_export;
output [31:0] cpu_1_tx_6_external_connection_export;
output [31:0] cpu_1_tx_7_external_connection_export;
output hps_0_h2f_reset_reset_n;
output hps_io_hps_io_emac1_inst_TX_CLK;
output hps_io_hps_io_emac1_inst_TXD0;
output hps_io_hps_io_emac1_inst_TXD1;
output hps_io_hps_io_emac1_inst_TXD2;
output hps_io_hps_io_emac1_inst_TXD3;
input hps_io_hps_io_emac1_inst_RXD0;
inout hps_io_hps_io_emac1_inst_MDIO;
output hps_io_hps_io_emac1_inst_MDC;
input hps_io_hps_io_emac1_inst_RX_CTL;
output hps_io_hps_io_emac1_inst_TX_CTL;
input hps_io_hps_io_emac1_inst_RX_CLK;
input hps_io_hps_io_emac1_inst_RXD1;
input hps_io_hps_io_emac1_inst_RXD2;
input hps_io_hps_io_emac1_inst_RXD3;
inout hps_io_hps_io_sdio_inst_CMD;
inout hps_io_hps_io_sdio_inst_D0;
inout hps_io_hps_io_sdio_inst_D1;
output hps_io_hps_io_sdio_inst_CLK;
inout hps_io_hps_io_sdio_inst_D2;
inout hps_io_hps_io_sdio_inst_D3;
inout hps_io_hps_io_usb1_inst_D0;
inout hps_io_hps_io_usb1_inst_D1;
inout hps_io_hps_io_usb1_inst_D2;
inout hps_io_hps_io_usb1_inst_D3;
inout hps_io_hps_io_usb1_inst_D4;
inout hps_io_hps_io_usb1_inst_D5;
inout hps_io_hps_io_usb1_inst_D6;
inout hps_io_hps_io_usb1_inst_D7;
input hps_io_hps_io_usb1_inst_CLK;
output hps_io_hps_io_usb1_inst_STP;
input hps_io_hps_io_usb1_inst_DIR;
input hps_io_hps_io_usb1_inst_NXT;
input hps_io_hps_io_uart0_inst_RX;
output hps_io_hps_io_uart0_inst_TX;
output [9:0] led_external_connection_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
output noc_clock_clk;
output [31:0] noc_ctrl_0_external_connection_export;
output [31:0] noc_ctrl_1_external_connection_export;
input [31:0] noc_status_0_external_connection_export;
input [31:0] noc_status_1_external_connection_export;
output pll_0_outclk0_clk;
input reset_reset_n;
input [9:0] sw_external_connection_export;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int n, m, s, vis[100005], cy; long long t; int nex(int x, int y) { if (x < m) return (x + y) % n; else return (x - y + n) % n; } int main() { scanf( %d %d , &n, &m); scanf( %d %lld , &s, &t); --s; while (t % n != 0) { s = nex(s, t % n); --t; } t /= n; while (t && (!vis[s])) { vis[s] = ++cy; for (int y = n - 1; y > 0; --y) s = nex(s, y); --t; } if (!t) { cout << s + 1; return 0; } t %= (cy + 1 - vis[s]); while (t) { for (int y = n - 1; y > 0; --y) s = nex(s, y); --t; } cout << s + 1; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
reg [31:0] r32;
wire [3:0] w4;
wire [4:0] w5;
assign w4 = NUMONES_8 ( r32[7:0] );
assign w5 = NUMONES_16( r32[15:0] );
function [3:0] NUMONES_8;
input [7:0] i8;
reg [7:0] i8;
begin
NUMONES_8 = 4'b1;
end
endfunction // NUMONES_8
function [4:0] NUMONES_16;
input [15:0] i16;
reg [15:0] i16;
begin
NUMONES_16 = ( NUMONES_8( i16[7:0] ) + NUMONES_8( i16[15:8] ));
end
endfunction
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
r32 <= 32'h12345678;
end
if (cyc==2) begin
if (w4 !== 1) $stop;
if (w5 !== 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
`timescale 1ns/1ps
module tb_multiplier (); /* this is automatically generated */
// clock
initial begin
clk = 0;
forever #5 clk = ~clk;
end
// (*NOTE*) replace reset, clock
reg [SW-1:0] a;
reg [SW-1:0] b;
// wire [2*SW-2:0] BinaryRES;
// wire [2*SW-1:0] FKOARES;
// wire [2*SW-1:0] RKOARES;
//wire [2*SW-2:0] SimpleRES;
// wire [2*SW-2:0] HybridRES;
//wire [2*SW-1:0] Simple_KOA;
wire [2*SW-1:0] Recursive_KOA;
reg clk;
parameter SW = 23;
// Bks26 inst_Bks26 (.a(a), .b(b), .d(BinaryRES));
// Sgf_Multiplication #(.SW(SW)) inst_Sgf_Multiplication (.clk(clk),.Data_A_i(a), .Data_B_i(b), .sgf_result_o(FKOARES));
// Sks26 inst_Sks26 (.a(a), .b(b), .d(SimpleRES));
// Hks26 inst_Hks26 (.a(a), .b(b), .d(HybridRES));
// RKOA #(.SW(SW)) inst_RKOA (.Data_A_i(a), .Data_B_i(b), .sgf_result_o(RKOARES));
//Simple_KOA #(.SW(SW)) i_Simple_KOA (.Data_A_i(a), .Data_B_i(b), .sgf_result_o(Simple_KOA));
Recursive_KOA #(.SW(SW)) inst_Recursive_KOA (.Data_A_i(a), .Data_B_i(b), .sgf_result_o(Recursive_KOA));
integer i = 1;
parameter cycles = 1024;
initial begin
$monitor(a,b,Recursive_KOA, a*b);
end
initial begin
b = 1;
a = 1;
#100;
b = 2;
repeat (cycles) begin
a = i;
b = b + 2;
i = i + 1;
#50;
end
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string st, t; vector<string> a; int p; int main() { ios_base ::sync_with_stdio(false); cin >> st; for (auto i : st) { t += i; if (i == > ) { a.push_back(t); t = ; } } for (auto i : a) { if (i[1] == / ) { --p; } for (int j = 0; j < p; ++j) { cout << ; } cout << i << endl; if (i[1] != / ) { ++p; } } } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long t; cin >> t; while (t--) { long long d, m; cin >> d >> m; long long j = 1, ans = 1, sum = 0; while (sum + j <= d) { ans = ans * (j + 1) % m; sum += j; j *= 2; } ans = ans * (d - sum + 1) % m; ans += m - 1; ans %= m; cout << ans << n ; } } |
#include <bits/stdc++.h> using namespace std; const long long MAXN = 1000001; long long n, l[MAXN], r[MAXN], id[MAXN], K; bool cmp(long long i, long long j) { return (l[i] / K == l[j] / K) ? ((l[i] / K & 1) ? (r[i] < r[j]) : (r[i] > r[j])) : (l[i] < l[j]); } int main() { scanf( %lld , &n); K = 1000; for (long long i = 1; i <= n; i++) scanf( %lld%lld , &l[i], &r[i]), id[i] = i; sort(id + 1, id + 1 + n, cmp); for (int i = 1; i <= n; i++) printf( %lld , id[i]); } |
#include <bits/stdc++.h> using namespace std; long long a, b, c; int vis[12]; bool ok(long long mid, int x) { long long m = mid % 7; int day = x; long long res[5]; res[1] = mid / 7; res[2] = mid / 7; res[3] = mid / 7; res[1] *= 3; res[2] *= 2; res[3] *= 2; while (m--) { res[vis[day]]++; day++; day %= 7; } return res[1] <= a && res[2] <= b && res[3] <= c; } long long ans(int x) { long long st = 0, en = 1e12; while (st < en) { long long mid = (st + en) / 2; if (ok(mid, x)) st = mid + 1; else en = mid; } return st; } int main() { ios_base::sync_with_stdio(false); cin >> a >> b >> c; vis[0] = 2; vis[1] = 1; vis[2] = 1; vis[3] = 2; vis[4] = 3; vis[5] = 1; vis[6] = 3; long long mx = 0; for (int i = 0; i < 7; i++) { mx = max(mx, ans(i)); } cout << --mx << n ; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:20:39 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlconstant_0_1/RAT_xlconstant_0_1_stub.v
// Design : RAT_xlconstant_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module RAT_xlconstant_0_1(dout)
/* synthesis syn_black_box black_box_pad_pin="dout[1:0]" */;
output [1:0]dout;
endmodule
|
module fifo # (parameter abits = 3800, dbits = 1)(
input reset, clock,
input rd, wr,
input [dbits-1:0] din,
output [dbits-1:0] dout,
output empty,
output full
//output reg ledres
);
wire db_wr, db_rd;
//reg dffw1, dffw2, dffr1, dffr2;
reg [dbits-1:0] out;
//initial ledres = 0;
//always @ (posedge clock) dffw1 <= wr;
//always @ (posedge clock) dffw2 <= dffw1;
assign db_wr = wr; //monostable multivibrator to detect only one pulse of the button
//always @ (posedge clock) dffr1 <= rd;
//always @ (posedge clock) dffr2 <= dffr1;
assign db_rd = rd; //monostable multivibrator to detect only one pulse of the button
reg [dbits-1:0] regarray[2**abits-1:0]; //number of words in fifo = 2^(number of address bits)
reg [abits-1:0] wr_reg, wr_next, wr_succ; //points to the register that needs to be written to
reg [abits-1:0] rd_reg, rd_next, rd_succ; //points to the register that needs to be read from
reg full_reg, empty_reg, full_next, empty_next;
assign wr_en = db_wr & ~full; //only write if write signal is high and fifo is not full
//always block for write operation
always @ (posedge clock)
begin
if(wr_en)
begin
regarray[wr_reg] <= din; //at wr_reg location of regarray store what is given at din
out <= regarray[rd_reg];
end
end
//always block for read operation
//always @ (posedge clock)
//begin
//if(db_rd)
//out <= regarray[rd_reg];
//end
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
wr_reg <= 0;
rd_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
//ledres=0;
end
else
begin
wr_reg <= wr_next; //created the next registers to avoid the error of mixing blocking and non blocking assignment to the same signal
rd_reg <= rd_next;
full_reg <= full_next;
empty_reg <= empty_next;
//ledres=1;
end
end
always @(*)
begin
wr_succ = wr_reg + 1; //assigned to new value as wr_next cannot be tested for in same always block
rd_succ = rd_reg + 1; //assigned to new value as rd_next cannot be tested for in same always block
wr_next = wr_reg; //defaults state stays the same
rd_next = rd_reg; //defaults state stays the same
full_next = full_reg; //defaults state stays the same
empty_next = empty_reg; //defaults state stays the same
case({db_wr,db_rd})
//2'b00: do nothing LOL..
2'b01: //read
begin
if(~empty) //if fifo is not empty continue
begin
rd_next = rd_succ;
full_next = 1'b0;
if(rd_succ == wr_reg) //all data has been read
empty_next = 1'b1; //its empty again
end
end
2'b10: //write
begin
if(~full) //if fifo is not full continue
begin
wr_next = wr_succ;
empty_next = 1'b0;
if(wr_succ == (2**abits-1)) //all registers have been written to
full_next = 1'b1; //its full now
end
end
2'b11: //read and write
begin
wr_next = wr_succ;
rd_next = rd_succ;
end
//no empty or full flag will be checked for or asserted in this state since data is being written to and read from together it can not get full in this state.
endcase
end
assign full = full_reg;
assign empty = empty_reg;
assign dout = out;
endmodule
|
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// mv_read O 64
// mav_write O 64
// CLK I 1 clock
// RST_N I 1 reset
// mav_write_misa I 28
// mav_write_wordxl I 64
// m_external_interrupt_req_req I 1 reg
// s_external_interrupt_req_req I 1 reg
// software_interrupt_req_req I 1 reg
// timer_interrupt_req_req I 1 reg
// EN_reset I 1
// EN_mav_write I 1
//
// Combinational paths from inputs to outputs:
// (mav_write_misa, mav_write_wordxl) -> mav_write
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCSR_MIP(CLK,
RST_N,
EN_reset,
mv_read,
mav_write_misa,
mav_write_wordxl,
EN_mav_write,
mav_write,
m_external_interrupt_req_req,
s_external_interrupt_req_req,
software_interrupt_req_req,
timer_interrupt_req_req);
input CLK;
input RST_N;
// action method reset
input EN_reset;
// value method mv_read
output [63 : 0] mv_read;
// actionvalue method mav_write
input [27 : 0] mav_write_misa;
input [63 : 0] mav_write_wordxl;
input EN_mav_write;
output [63 : 0] mav_write;
// action method m_external_interrupt_req
input m_external_interrupt_req_req;
// action method s_external_interrupt_req
input s_external_interrupt_req_req;
// action method software_interrupt_req
input software_interrupt_req_req;
// action method timer_interrupt_req
input timer_interrupt_req_req;
// signals for module outputs
wire [63 : 0] mav_write, mv_read;
// register rg_meip
reg rg_meip;
wire rg_meip$D_IN, rg_meip$EN;
// register rg_msip
reg rg_msip;
wire rg_msip$D_IN, rg_msip$EN;
// register rg_mtip
reg rg_mtip;
wire rg_mtip$D_IN, rg_mtip$EN;
// register rg_seip
reg rg_seip;
wire rg_seip$D_IN, rg_seip$EN;
// register rg_ssip
reg rg_ssip;
wire rg_ssip$D_IN, rg_ssip$EN;
// register rg_stip
reg rg_stip;
wire rg_stip$D_IN, rg_stip$EN;
// register rg_ueip
reg rg_ueip;
wire rg_ueip$D_IN, rg_ueip$EN;
// register rg_usip
reg rg_usip;
wire rg_usip$D_IN, rg_usip$EN;
// register rg_utip
reg rg_utip;
wire rg_utip$D_IN, rg_utip$EN;
// rule scheduling signals
wire CAN_FIRE_m_external_interrupt_req,
CAN_FIRE_mav_write,
CAN_FIRE_reset,
CAN_FIRE_s_external_interrupt_req,
CAN_FIRE_software_interrupt_req,
CAN_FIRE_timer_interrupt_req,
WILL_FIRE_m_external_interrupt_req,
WILL_FIRE_mav_write,
WILL_FIRE_reset,
WILL_FIRE_s_external_interrupt_req,
WILL_FIRE_software_interrupt_req,
WILL_FIRE_timer_interrupt_req;
// remaining internal signals
wire [11 : 0] new_mip__h524, new_mip__h942;
wire seip__h558, ssip__h562, stip__h560, ueip__h559, usip__h563, utip__h561;
// action method reset
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// value method mv_read
assign mv_read = { 52'd0, new_mip__h524 } ;
// actionvalue method mav_write
assign mav_write = { 52'd0, new_mip__h942 } ;
assign CAN_FIRE_mav_write = 1'd1 ;
assign WILL_FIRE_mav_write = EN_mav_write ;
// action method m_external_interrupt_req
assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;
// action method s_external_interrupt_req
assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;
// action method software_interrupt_req
assign CAN_FIRE_software_interrupt_req = 1'd1 ;
assign WILL_FIRE_software_interrupt_req = 1'd1 ;
// action method timer_interrupt_req
assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
assign WILL_FIRE_timer_interrupt_req = 1'd1 ;
// register rg_meip
assign rg_meip$D_IN = m_external_interrupt_req_req ;
assign rg_meip$EN = 1'b1 ;
// register rg_msip
assign rg_msip$D_IN = software_interrupt_req_req ;
assign rg_msip$EN = 1'b1 ;
// register rg_mtip
assign rg_mtip$D_IN = timer_interrupt_req_req ;
assign rg_mtip$EN = 1'b1 ;
// register rg_seip
assign rg_seip$D_IN = s_external_interrupt_req_req ;
assign rg_seip$EN = 1'b1 ;
// register rg_ssip
assign rg_ssip$D_IN = !EN_reset && ssip__h562 ;
assign rg_ssip$EN = EN_mav_write || EN_reset ;
// register rg_stip
assign rg_stip$D_IN = !EN_reset && stip__h560 ;
assign rg_stip$EN = EN_mav_write || EN_reset ;
// register rg_ueip
assign rg_ueip$D_IN = !EN_reset && ueip__h559 ;
assign rg_ueip$EN = EN_mav_write || EN_reset ;
// register rg_usip
assign rg_usip$D_IN = !EN_reset && usip__h563 ;
assign rg_usip$EN = EN_mav_write || EN_reset ;
// register rg_utip
assign rg_utip$D_IN = !EN_reset && utip__h561 ;
assign rg_utip$EN = EN_mav_write || EN_reset ;
// remaining internal signals
assign new_mip__h524 =
{ rg_meip,
1'b0,
rg_seip,
rg_ueip,
rg_mtip,
1'b0,
rg_stip,
rg_utip,
rg_msip,
1'b0,
rg_ssip,
rg_usip } ;
assign new_mip__h942 =
{ rg_meip,
1'b0,
seip__h558,
ueip__h559,
rg_mtip,
1'b0,
stip__h560,
utip__h561,
rg_msip,
1'b0,
ssip__h562,
usip__h563 } ;
assign seip__h558 = mav_write_misa[18] && mav_write_wordxl[9] ;
assign ssip__h562 = mav_write_misa[18] && mav_write_wordxl[1] ;
assign stip__h560 = mav_write_misa[18] && mav_write_wordxl[5] ;
assign ueip__h559 = mav_write_misa[13] && mav_write_wordxl[8] ;
assign usip__h563 = mav_write_misa[13] && mav_write_wordxl[0] ;
assign utip__h561 = mav_write_misa[13] && mav_write_wordxl[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_meip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_msip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_seip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_ssip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_stip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_ueip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_usip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_utip <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (rg_meip$EN) rg_meip <= `BSV_ASSIGNMENT_DELAY rg_meip$D_IN;
if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN;
if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN;
if (rg_seip$EN) rg_seip <= `BSV_ASSIGNMENT_DELAY rg_seip$D_IN;
if (rg_ssip$EN) rg_ssip <= `BSV_ASSIGNMENT_DELAY rg_ssip$D_IN;
if (rg_stip$EN) rg_stip <= `BSV_ASSIGNMENT_DELAY rg_stip$D_IN;
if (rg_ueip$EN) rg_ueip <= `BSV_ASSIGNMENT_DELAY rg_ueip$D_IN;
if (rg_usip$EN) rg_usip <= `BSV_ASSIGNMENT_DELAY rg_usip$D_IN;
if (rg_utip$EN) rg_utip <= `BSV_ASSIGNMENT_DELAY rg_utip$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_meip = 1'h0;
rg_msip = 1'h0;
rg_mtip = 1'h0;
rg_seip = 1'h0;
rg_ssip = 1'h0;
rg_stip = 1'h0;
rg_ueip = 1'h0;
rg_usip = 1'h0;
rg_utip = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCSR_MIP
|
// RFID Reader for testing epc class 1 gen 2 tags.
// rigidly assume clock = 7.812mhz. (this makes our divide ratios work out nicely)
// for an 8mhz crystal, we are off by about 2%
`timescale 1ns/1ns
module rfid_reader (
// basic setup connections
reset, clk, tag_backscatter, reader_modulation
);
input reset, clk, tag_backscatter;
output reader_modulation;
// Packets (valid tx_cmd values)
parameter QUERYREP = 0;
parameter ACK = 1;
parameter QUERY = 2;
parameter QUERYADJ = 3;
parameter SELECT = 4;
parameter NACK = 5;
parameter REQRN = 6;
parameter READ = 7;
parameter WRITE = 8;
parameter KILL = 9;
parameter LOCK = 10;
parameter ACCESS = 11;
parameter BLOCKWRITE = 12;
parameter BLOCKERASE = 13;
// Query parameters
parameter DR = 1'd0; // 0 = 8, 1 = 64/3
parameter M = 2'd0; // 0 to 3
parameter TREXT = 1'd0; // 0 or 1
parameter SEL = 2'd0; // 0 or 1
parameter SESSION = 2'd0; // 0 or 1
parameter TARGET = 1'd0; // 0 or 1
parameter Q = 4'd2; // 0 to 15
// TX Timing info
parameter DELIM = 16'd15000; // delimiter = 15us
parameter PW = 16'd1000; //
parameter TARI = 16'd6250; //
parameter RTCAL = 16'd18750; // 2.5*TARI<RTCAL<3*TARI
parameter TRCAL = 16'd25000; // >RTCAL
wire [2:0] miller;
assign miller = M;
wire trext;
assign trext = TREXT;
wire divide_ratio;
assign divide_ratio = DR;
wire [15:0] tari_ns;
assign tari_ns = TARI;
wire [15:0] trcal_ns;
assign trcal_ns = TRCAL;
wire [2:0] q_adj;
assign q_adj = 0;
wire [3:0] slot_q;
assign slot_q = Q;
wire [1:0] session;
assign session = SESSION;
wire [1:0] select;
assign select = SEL;
wire target;
assign target = TARGET;
reg [3:0] send_packet_type;
reg start_tx;
reg [15:0] tx_handle;
wire [15:0] rx_handle;
wire reader_done, rx_timeout, rx_packet_complete, reader_running;
rfid_reader_packet_rxtx UREADER (
// basic setup connections
reset, clk, tag_backscatter, reader_modulation,
// modulation settings
miller, trext, divide_ratio, tari_ns, trcal_ns,
// tag state settings
slot_q, q_adj, session, target, select,
// command to send, posedge send trigger
send_packet_type, start_tx, reader_done, rx_timeout, rx_packet_complete, reader_running,
// tx payload info
tx_handle,
// rx payload info
rx_handle
);
// divide time periods by 128 ns via shift right 7 to get clock cycles
parameter CLK_EXP = 7;
wire [15:0] startup_counts;
assign startup_counts = 16'd50000 >> CLK_EXP;
reg [5:0] reader_state;
parameter STATE_INIT = 0;
parameter STATE_QUERY = 1;
parameter STATE_QUERYREP = 2;
parameter STATE_ACK = 3;
parameter STATE_REQRN = 4;
parameter STATE_READ = 5;
parameter STATE_REQMASK = 6;
parameter STATE_WRITE = 7;
reg started;
reg [15:0] counter;
always @ (posedge clk or posedge reset) begin
if (reset) begin
reader_state <= 0;
started <= 0;
tx_handle <= 0;
start_tx <= 0;
counter <= 0;
send_packet_type <= 0;
end else begin
case(reader_state)
STATE_INIT: begin
if (!started) begin
counter <= 0;
started <= 1;
end else begin
if (counter >= startup_counts) begin
reader_state <= STATE_QUERY;
started <= 0;
end else begin
counter <= counter + 1;
end
end
end
STATE_QUERY: begin
send_packet_type <= QUERY;
if (!started && reader_running) begin
start_tx <= 0;
started <= 1;
end else if (!started && !reader_running) begin
start_tx <= 1;
end else if (started && reader_done && rx_packet_complete) begin
tx_handle <= rx_handle;
reader_state <= STATE_ACK;
started <= 0;
end else if (started && reader_done && !rx_packet_complete) begin
reader_state <= STATE_QUERYREP;
started <= 0;
end
end
STATE_QUERYREP: begin
send_packet_type <= QUERYREP;
if (!started && reader_running) begin
start_tx <= 0;
started <= 1;
end else if (!started && !reader_running) begin
start_tx <= 1;
end else if (started && reader_done && rx_packet_complete) begin
tx_handle <= rx_handle;
reader_state <= STATE_ACK;
started <= 0;
end else if (started && reader_done && !rx_packet_complete) begin
reader_state <= STATE_QUERYREP;
started <= 0;
end
end
STATE_ACK: begin
send_packet_type <= ACK;
if (!started && reader_running) begin
start_tx <= 0;
started <= 1;
end else if (!started && !reader_running) begin
start_tx <= 1;
end else if (started && reader_done && rx_packet_complete) begin
tx_handle <= rx_handle;
reader_state <= STATE_REQRN;
started <= 0;
end else if (started && reader_done && !rx_packet_complete) begin
reader_state <= STATE_QUERY;
started <= 0;
end
end
STATE_REQRN: begin
send_packet_type <= REQRN;
if (!started && reader_running) begin
start_tx <= 0;
started <= 1;
end else if (!started && !reader_running) begin
start_tx <= 1;
end else if (started && reader_done && rx_packet_complete) begin
tx_handle <= rx_handle;
reader_state <= STATE_READ;
started <= 0;
end else if (started && reader_done && !rx_packet_complete) begin
reader_state <= STATE_QUERY;
started <= 0;
end
end
STATE_READ: begin
send_packet_type <= READ;
if (!started && reader_running) begin
start_tx <= 0;
started <= 1;
end else if (!started && !reader_running) begin
start_tx <= 1;
end else if (started && reader_done && rx_packet_complete) begin
tx_handle <= rx_handle;
reader_state <= STATE_QUERY;
started <= 0;
end else if (started && reader_done && !rx_packet_complete) begin
reader_state <= STATE_QUERY;
started <= 0;
end
end
default: begin
reader_state <= 0;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int gcd(int x, int y) { if (y == 0) return x; return gcd(y, x % y); } int lcm(int x, int y) { return x * y / gcd(x, y); } long long int gcd(long long int x, long long int y) { if (y == 0) return x; return gcd(y, x % y); } long long int lcm(long long int x, long long int y) { return x * y / gcd(x, y); } void swap(long long int& x, long long int& y) { long long int temp = x; x = y; y = temp; } long long int binpow(long long int a, long long int b) { long long int res = 1; while (b > 0) { if (b & 1) res = res * a; a = a * a; b >>= 1; } return res; } long long int binpowM(long long int a, long long int b) { a %= 100000007; long long int res = 1; while (b > 0) { if (b & 1) res = res * a % 100000007; a = a * a % 100000007; b >>= 1; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cout << fixed; int n, ans = 0, k; cin >> n; vector<int> a(3); for (int i = 0; i < 3; i++) { cin >> a[i]; } sort(a.begin(), a.end(), greater<int>()); int i = 0, j, l = n / a[1], m = n / a[0]; while (i <= m) { j = 0; while (j <= l) { k = n - i * a[0] - j * a[1]; if (k % a[2] == 0) { ans = max(i + j + k / a[2], ans); } j++; } i++; } cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__NAND2B_FUNCTIONAL_PP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2B_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2111O_2_V
`define SKY130_FD_SC_LS__A2111O_2_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2111o_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a2111o_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2111O_2_V
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 7; int ans[N]; int he[N]; int res[N]; vector<int> g[N]; vector<int> a[N]; vector<int> lul[N]; void dfs(int v, int pr, int h) { he[v] = h; for (auto to : g[v]) { if (to != pr) { dfs(to, v, h + 1); } } } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { ans[i] = 1; res[i] = 1e9; } for (int i = 0; i < n; i++) { int s; scanf( %d , &s); while (s--) { int x; scanf( %d , &x); lul[i].push_back(x); } } for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); g[u].push_back(v); g[v].push_back(u); } dfs(1, 0, 0); vector<int> a(n); for (int i = 0; i < n; i++) { a[i] = i + 1; } for (int i = 0; i < n; i++) { for (auto c : lul[i]) { res[c] = min(res[c], he[i + 1]); } } sort(a.begin(), a.end(), [](int a, int b) { return he[a] < he[b]; }); int lfl = 1; for (int i : a) { vector<int> lel; int cnt = 0; set<int> s; for (auto c : lul[i - 1]) { if (res[c] == he[i]) { lel.push_back(c); } else { s.insert(ans[c]); } } int sz = 1; for (auto c : lel) { while (s.count(sz)) { sz++; } s.insert(sz); ans[c] = sz; lfl = max(lfl, sz); } } printf( %d n , lfl); for (int i = 1; i <= m; i++) { printf( %d , ans[i]); } puts( ); } |
#include <bits/stdc++.h> using namespace std; const int N = 2000500; int P[N]; int D[N]; multiset<int> S[N]; inline bool recalc(int x) { if (x == 1) { D[x] = *S[x].rbegin() + 1; return false; } else { int nd; if (S[x].size() == 1) nd = *S[x].rbegin(); else nd = max(*S[x].rbegin(), *(++S[x].rbegin()) + 1); if (nd != D[x]) { S[P[x]].erase(S[P[x]].find(D[x])); D[x] = nd; S[P[x]].insert(nd); return true; } else return false; } } int main() { int n; scanf( %d , &n); P[1] = -1; D[0] = 1; for (int i = 2; i < n + 2; i++) { scanf( %d , &P[i]); S[P[i]].insert(0); for (int x = P[i]; recalc(x); x = P[x]) ; printf( %d , D[1]); } printf( n ); } |
#include <bits/stdc++.h> using namespace std; inline void rd(int &x) { x = 0; char o, f = 1; while (o = getchar(), o < 48) if (o == 45) f = -f; do x = (x << 3) + (x << 1) + (o ^ 48); while (o = getchar(), o > 47); x *= f; } int head[100005], to[100005 << 1], nxt[100005 << 1], tot; inline void add(int a, int b) { to[++tot] = b; nxt[tot] = head[a]; head[a] = tot; } int n, m, q, a, b, c, tp, ans[100005]; int id[100005], reid[100005], dfsid, sz[100005], son[100005], fa[100005], top[100005], deep[100005]; void dfs(int x, int f) { fa[x] = f; deep[x] = deep[f] + 1; sz[x] = 1; for (int i = head[x]; i; i = nxt[i]) { int y = to[i]; if (y == fa[x]) continue; dfs(y, x); sz[x] += sz[y]; if (sz[y] > sz[son[x]]) son[x] = y; } } void chain(int x, int f) { top[x] = f; reid[id[x] = ++dfsid] = x; if (son[x]) chain(son[x], f); for (int i = head[x]; i; i = nxt[i]) { int y = to[i]; if (y == fa[x] || y == son[x]) continue; chain(y, y); } } vector<int> area[100005]; int st[100005 << 2][22]; void build(int p = 1, int l = 1, int r = n) { if (l == r) { for (int i = 0, tp = 0; i < area[reid[l]].size() && tp < 10; i++, tp++) st[p][++st[p][0]] = area[reid[l]][i]; return; } int mid = l + r >> 1, x = 0, y = 0; build(p << 1, l, mid); build(p << 1 | 1, mid + 1, r); while (st[p][0] < 10 && x < st[p << 1][0] && y < st[p << 1 | 1][0]) { if (st[p << 1][x + 1] < st[p << 1 | 1][y + 1]) st[p][++st[p][0]] = st[p << 1][++x]; else st[p][++st[p][0]] = st[p << 1 | 1][++y]; } while (st[p][0] < 10 && x < st[p << 1][0]) st[p][++st[p][0]] = st[p << 1][++x]; while (st[p][0] < 10 && y < st[p << 1 | 1][0]) st[p][++st[p][0]] = st[p << 1 | 1][++y]; } void query(int a, int b, int p = 1, int l = 1, int r = n) { if (l > b || r < a) return; if (l >= a && r <= b) { for (int i = 1; i <= min(st[p][0], c); i++) ans[++ans[0]] = st[p][i]; return; } int mid = l + r >> 1; query(a, b, p << 1, l, mid); query(a, b, p << 1 | 1, mid + 1, r); } int main() { rd(n), rd(m), rd(q); for (int i = 1; i < n; i++) { rd(a), rd(b); add(a, b); add(b, a); } dfs(1, 0); chain(1, 1); for (int i = 1; i <= m; i++) { rd(a); area[a].push_back(i); } for (int i = 1; i <= n; i++) sort(area[i].begin(), area[i].end()); build(); while (q--) { ans[0] = 0; rd(a), rd(b), rd(c); while (top[a] != top[b]) { if (deep[top[a]] < deep[top[b]]) swap(a, b); query(id[top[a]], id[a]); a = fa[top[a]]; } if (deep[a] > deep[b]) swap(a, b); query(id[a], id[b]); sort(ans + 1, ans + 1 + ans[0]); printf( %d , min(c, ans[0])); for (int i = 1; i <= min(c, ans[0]); i++) printf( %d , ans[i]); puts( ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int binarySearch(long long int arr[], long long int l, long long int r, long long int x) { if (r >= l) { long long int mid = l + (r - l) / 2; if (arr[mid] == x) return mid; if (arr[mid] > x) return binarySearch(arr, l, mid - 1, x); return binarySearch(arr, mid + 1, r, x); } return -1; } int main() { ios_base::sync_with_stdio(false); long long int t; cin >> t; while (t--) { long long int n, x; cin >> n >> x; long long int a[n]; for (long long int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); long long int ans = 0; if (binarySearch(a, 0, n - 1, x) != -1) { ans = 1; } else { if (x % a[n - 1] == 0) { ans = x / a[n - 1]; } else { if (x / a[n - 1] == 0) { ans++; } ans += x / a[n - 1] + 1; } } cout << ans << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MAJ3_2_V
`define SKY130_FD_SC_LP__MAJ3_2_V
/**
* maj3: 3-input majority vote.
*
* Verilog wrapper for maj3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__maj3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__maj3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__maj3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__maj3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MAJ3_2_V
|
// ----------------------------
// This module impelements a linear feedback shift register (lfsr).
//
// Note:
// - Syntax works and compiles with Verilog2LPN compiler
// - async. design follows dual rail encoding that maps
// input to output and output to internal states
//
// author: Tramy Nguyen
// ----------------------------
module lfsr_imp (req, ack, a0, a1, b0, b1, c0, c1);
input req;
output reg ack, a0, a1, b0, b1, c0, c1;
reg feedback, state0, state1;
initial begin
a0 = 1'b0;
b0 = 1'b0;
c0 = 1'b0;
a1 = 1'b0;
b1 = 1'b0;
c1 = 1'b0;
ack = 1'b0;
feedback = 1'b0;
state0 = 1'b0;
state1 = 1'b0;
end
always begin
// input to output
wait(req == 1'b1) #5;
if(state0 != 1'b1 && state1 != 1'b1 && feedback != 1'b1) begin
#5 a0 = 1'b1;
#5 b0 = 1'b1;
#5 c0 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 != 1'b1 && state1 != 1'b1 && feedback == 1'b1) begin
#5 a0 = 1'b1;
#5 b0 = 1'b1;
#5 c1 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 != 1'b1 && state1 == 1'b1 && feedback != 1'b1) begin
#5 a0 = 1'b1;
#5 b1 = 1'b1;
#5 c0 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 != 1'b1 && state1 == 1'b1 && feedback == 1'b1) begin
#5 a0 = 1'b1;
#5 b1 = 1'b1;
#5 c1 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 == 1'b1 && state1 != 1'b1 && feedback != 1'b1) begin
#5 a1 = 1'b1;
#5 b0 = 1'b1;
#5 c0 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 == 1'b1 && state1 != 1'b1 && feedback == 1'b1) begin
#5 a1 = 1'b1;
#5 b0 = 1'b1;
#5 c1 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 == 1'b1 && state1 == 1'b1 && feedback != 1'b1) begin
#5 a1 = 1'b1;
#5 b1 = 1'b1;
#5 c0 = 1'b1;
#5 ack = 1'b1;
end
else if(state0 == 1'b1 && state1 == 1'b1 && feedback == 1'b1) begin
#5 a1 = 1'b1;
#5 b1 = 1'b1;
#5 c1 = 1'b1;
#5 ack = 1'b1;
end
// output to states
if(a0 == 1'b1 && b0 == 1'b1 && c0 == 1'b1) begin
state0 = 1'b0;
state1 = 1'b0;
feedback = 1'b1;
end
else if(a0 == 1'b1 && b1 == 1'b1 && c0 == 1'b1) begin
state0 = 1'b1;
state1 = 1'b0;
feedback = 1'b0;
end
else if(a1 == 1'b1 && b0 == 1'b1 && c0 == 1'b1) begin
state0 = 1'b0;
state1 = 1'b0;
feedback = 1'b0;
end
else if(a1 == 1'b1 && b1 == 1'b1 && c0 == 1'b1) begin
state0 = 1'b1;
state1 = 1'b0;
feedback = 1'b1;
end
else if(a0 == 1'b1 && b0 == 1'b1 && c1 == 1'b1) begin
state0 = 1'b0;
state1 = 1'b1;
feedback = 1'b1;
end
else if(a0 == 1'b1 && b1 == 1'b1 && c1 == 1'b1) begin
state0 = 1'b1;
state1 = 1'b1;
feedback = 1'b0;
end
else if(a1 == 1'b1 && b0 == 1'b1 && c1 == 1'b1) begin
state0 = 1'b0;
state1 = 1'b1;
feedback = 1'b0;
end
else if(a1 == 1'b1 && b1 == 1'b1 && c1 == 1'b1) begin
state0 = 1'b1;
state1 = 1'b1;
feedback = 1'b1;
end
//stabilize signals
wait((a0 == 1'b1 && b0 == 1'b1 && c0 == 1'b1 && state0 != 1'b1 && state1 != 1'b1 && feedback == 1'b1) ||
(a0 == 1'b1 && b1 == 1'b1 && c0 == 1'b1 && state0 == 1'b1 && state1 != 1'b1 && feedback != 1'b1) ||
(a1 == 1'b1 && b0 == 1'b1 && c0 == 1'b1 && state0 != 1'b1 && state1 != 1'b1 && feedback != 1'b1) ||
(a1 == 1'b1 && b1 == 1'b1 && c0 == 1'b1 && state0 == 1'b1 && state1 != 1'b1 && feedback == 1'b1) ||
(a0 == 1'b1 && b0 == 1'b1 && c1 == 1'b1 && state0 != 1'b1 && state1 == 1'b1 && feedback == 1'b1) ||
(a0 == 1'b1 && b1 == 1'b1 && c1 == 1'b1 && state0 == 1'b1 && state1 == 1'b1 && feedback != 1'b1) ||
(a1 == 1'b1 && b0 == 1'b1 && c1 == 1'b1 && state0 != 1'b1 && state1 == 1'b1 && feedback != 1'b1) ||
(a1 == 1'b1 && b1 == 1'b1 && c1 == 1'b1 && state0 == 1'b1 && state1 == 1'b1 && feedback == 1'b1)) #5;
// reset
wait(req != 1'b1) #5;
if(a0 == 1'b1) begin
#5 a0 = 1'b0;
end
if(a1 == 1'b1) begin
#5 a1 = 1'b0;
end
if(b0 == 1'b1) begin
#5 b0 = 1'b0;
end
if(b1 == 1'b1) begin
#5 b1 = 1'b0;
end
if(c0 == 1'b1) begin
#5 c0 = 1'b0;
end
if(c1 == 1'b1) begin
#5 c1 = 1'b0;
end
#5 ack = 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long solve(long long l, long long r, long long x) { long long res = 0; for (int i = 1; i <= 62; i++) { long long p = (1LL << i) - 1; long long val = (x ^ p); if (l <= p && p <= r) { res = max(res, val); } if (l <= val && val <= r) { res = max(res, p); } } return res; } int main() { long long l, r; cin >> l >> r; if (l == r) { cout << 0; } else if (r - l <= 1000) { long long m = 0; for (long long i = l; i <= r; i++) { for (long long j = l; j <= r; j++) { m = max(m, i ^ j); } } cout << m; } else { long long a = solve(l, r, l); long long b = solve(l, r, r); cout << max(a, b); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22AI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O22AI_BEHAVIORAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22AI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FA_TB_V
`define SKY130_FD_SC_LP__FA_TB_V
/**
* fa: Full adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fa.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CIN;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CIN = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CIN = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 CIN = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 CIN = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 CIN = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 CIN = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_lp__fa dut (.A(A), .B(B), .CIN(CIN), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FA_TB_V
|
////////////////////////////////////////////////////////////////////////////////////////////////////
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
// 02111-1307, USA.
//
// ©2013 - Roman Ovseitsev <>
////////////////////////////////////////////////////////////////////////////////////////////////////
//##################################################################################################
//
// Register configuration for OV7670 camera module.
// Initializes RGB565 VGA, with distorted colors... I yet to find the register settings to fix this.
//
//
// Calculating required clock frequency. 30fps RGB565 VGA:
//
// HREF = tLINE = 640*tP + 144*tP = 784*tP
// VSYNC = 510 * tLINE = 510 * 784*tP
// PCLK = VSYNC * FPS * BYTES_PER_PIXEL = 784 * 510 * 30 * 2 = 23990400 ~= 24MHz
//
//##################################################################################################
`timescale 1ns / 1ps
module OV7670Init (index_i, data_o);
input [5:0] index_i; // Register index.
output reg [16:0] data_o; // {Register_address, register_value, rw_flag} :
// Where register_value is the value to write if rw_flag = 1
// otherwise it's not used when rw_flag = 0 (read).
// {16'hffff, 1'b1} - denotes end of the register set.
// {16'hf0f0, 1'b1} - denotes that a delay is needed at this point.
always @* begin
(* parallel_case *) case(index_i)
//6'd0 : data_o = {16'h0A76, 1'b0};
6'd0 : data_o = {16'h1280, 1'b1}; // COM7 Reset.
6'd1 : data_o = {16'hf0f0, 1'b1}; // Denotes delay.
6'd2 : data_o = {16'h1180, 1'b1}; // CLKRC Use external clock?
6'd3 : data_o = {16'h1205, 1'b1}; // COM12 Set RGB
/*
6'd2 : data_o = {16'h1204, 1'b1}; // COM7 Set RGB (06 enables color bar overlay).
6'd3 : data_o = {16'h1100, 1'b1}; // CLKRC Use external clock directly.
6'd4 : data_o = {16'h0C00, 1'b1}; // COM3 Disable DCW & scalling. + RSVD bits.
6'd5 : data_o = {16'h3E00, 1'b1}; // COM14 Normal PCLK.
6'd6 : data_o = {16'h8C00, 1'b1}; // RGB444 Disable RGB444
6'd7 : data_o = {16'h0400, 1'b1}; // COM1 Disable CCIR656. AEC low 2 LSB.
6'd8 : data_o = {16'h40d0, 1'b1}; // COM15 Set RGB565 full value range
6'd9 : data_o = {16'h3a04, 1'b1}; // TSLB Don't set window automatically. + RSVD bits.
6'd10: data_o = {16'h1418, 1'b1}; // COM9 Maximum AGC value x4. Freeze AGC/AEC. + RSVD bits.
6'd11: data_o = {16'h4fb3, 1'b1}; // MTX1 Matrix Coefficient 1
6'd12: data_o = {16'h50b3, 1'b1}; // MTX2 Matrix Coefficient 2
6'd13: data_o = {16'h5100, 1'b1}; // MTX3 Matrix Coefficient 3
6'd14: data_o = {16'h523d, 1'b1}; // MTX4 Matrix Coefficient 4
6'd15: data_o = {16'h53a7, 1'b1}; // MTX5 Matrix Coefficient 5
6'd16: data_o = {16'h54e4, 1'b1}; // MTX6 Matrix Coefficient 6
6'd17: data_o = {16'h589e, 1'b1}; // MTXS Enable auto contrast center. Matrix coefficient sign. + RSVD bits.
6'd18: data_o = {16'h3dc0, 1'b1}; // COM13 Gamma enable. + RSVD bits.
6'd19: data_o = {16'h1100, 1'b1}; // CLKRC Use external clock directly.
6'd20: data_o = {16'h1714, 1'b1}; // HSTART HREF start high 8 bits.
6'd21: data_o = {16'h1802, 1'b1}; // HSTOP HREF stop high 8 bits.
6'd22: data_o = {16'h3280, 1'b1}; // HREF HREF edge offset. HSTART/HSTOP low 3 bits.
6'd23: data_o = {16'h1903, 1'b1}; // VSTART VSYNC start high 8 bits.
6'd24: data_o = {16'h1A7b, 1'b1}; // VSTOP VSYNC stop high 8 bits.
6'd25: data_o = {16'h030a, 1'b1}; // VREF VSYNC edge offset. VSTART/VSTOP low 3 bits.
6'd26: data_o = {16'h0f41, 1'b1}; // COM6 Disable HREF at optical black. Reset timings. + RSVD bits.
6'd27: data_o = {16'h1e03, 1'b1}; // MVFP No mirror/vflip. Black sun disable. + RSVD bits.
6'd28: data_o = {16'h330b, 1'b1}; // CHLF Array Current Control - Reserved
//6'd29: data_o = {16'h373f, 1'b1}; // ADC
//6'd30: data_o = {16'h3871, 1'b1}; // ACOM ADC and Analog Common Mode Control - Reserved
//6'd31: data_o = {16'h392a, 1'b1}; // OFON ADC Offset Control - Reserved
6'd29: data_o = {16'h3c78, 1'b1}; // COM12 No HREF when VSYNC is low. + RSVD bits.
6'd30: data_o = {16'h6900, 1'b1}; // GFIX Fix Gain Control? No.
6'd31: data_o = {16'h6b1a, 1'b1}; // DBLV Bypass PLL. Enable internal regulator. + RSVD bits.
6'd32: data_o = {16'h7400, 1'b1}; // REG74 Digital gain controlled by VREF[7:6]. + RSVD bits.
6'd33: data_o = {16'hb084, 1'b1}; // RSVD ?
6'd34: data_o = {16'hb10c, 1'b1}; // ABLC1 Enable ABLC function. + RSVD bits.
6'd35: data_o = {16'hb20e, 1'b1}; // RSVD ?
6'd36: data_o = {16'hb380, 1'b1}; // THL_ST ABLC Target.
6'd37: data_o = {16'h7a20, 1'b1}; // SLOP Gamma Curve Highest Segment Slope
6'd38: data_o = {16'h7b10, 1'b1}; // GAM1
6'd39: data_o = {16'h7c1e, 1'b1}; // GAM2
6'd40: data_o = {16'h7d35, 1'b1}; // GAM3
6'd41: data_o = {16'h7e5a, 1'b1}; // GAM4
6'd42: data_o = {16'h7f69, 1'b1}; // GAM5
6'd43: data_o = {16'h8076, 1'b1}; // GAM6
6'd44: data_o = {16'h8180, 1'b1}; // GAM7
6'd45: data_o = {16'h8288, 1'b1}; // GAM8
6'd46: data_o = {16'h838f, 1'b1}; // GAM9
6'd47: data_o = {16'h8496, 1'b1}; // GAM10
6'd48: data_o = {16'h85a3, 1'b1}; // GAM11
6'd49: data_o = {16'h86af, 1'b1}; // GAM12
6'd50: data_o = {16'h87c4, 1'b1}; // GAM13
6'd51: data_o = {16'h88d7, 1'b1}; // GAM14
6'd52: data_o = {16'h89e8, 1'b1}; // GAM15
*/
default: data_o = {16'hffff, 1'b1};
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:11:09 08/01/2014
// Design Name:
// Module Name: pwm_controller
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pwm_controller( clk, slow_rate, speaker_out );
input clk; // input clk run at 1MHz
input [12:0] slow_rate;
output speaker_out;
reg [12:0] counter;
reg speaker;
reg [12:0] slow_rate_old;
initial begin
counter = 0;
slow_rate_old = 0;
speaker = 1'b0;
end
always @(posedge clk) begin
if(slow_rate_old != slow_rate) begin
counter <= 0;
speaker <= 1'b0;
slow_rate_old <= slow_rate;
end
if(counter == slow_rate && slow_rate != 0) begin
speaker <= ~speaker;
counter <= 0;
end else if (slow_rate != 0) begin
counter <= counter + 1;
end else begin
counter <= 0;
end
end
assign speaker_out = speaker;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> ans; void solve() { long long int i, a, b, c, d, n; cin >> a >> b >> c >> d; n = a + b + c + d; string s = ; while (a > 0) { s += 0 ; a--; } while (c > 0) { s += 2 ; c--; } i = 0; while (b > 0 && i < s.length()) { if (s[i] == 0 ) { s.insert(i + 1, 1, 1 ); b--; } else { break; } i = i + 2; } while (d > 0 && i < s.length()) { if (s[i] == 2 ) { s.insert(i + 1, 1, 3 ); d--; } i = i + 2; } while (b > 0 && i < s.length()) { if (s[i] == 2 ) { s.insert(i + 1, 1, 1 ); b--; } i = i + 2; } if (d > 0 && s[0] == 2 ) { s.insert(0, 1, 3 ); d--; } if (b > 0 && (s[0] == 0 || s[0] == 2 )) { s.insert(0, 1, 1 ); b--; } if (b > 0 && (s[s.length() - 1] == 0 || s[s.length() - 1] == 2 )) { s.insert(s.length() - 1, 1, 1 ); b--; } while (b > 0) { s += 1 ; b--; } while (d > 0) { s += 3 ; d--; } for (i = 1; i < n; i++) { if (abs(s[i] - s[i - 1]) != 1) { cout << NO ; return; } } cout << YES n ; for (i = 0; i < n; i++) cout << s[i] << ; } int main() { long long int t; t = 1; while (t--) { solve(); cout << n ; } } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file rrrrom.v when simulating
// the core, rrrrom. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module rrrrom(
clka,
addra,
douta
);
input clka;
input [11 : 0] addra;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(1),
.C_DISABLE_WARN_BHV_RANGE(1),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____33.333______0.000______50.0______165.726_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_4_1_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_0
(
// Clock out ports
output clk_out1,
// Clock in ports
input clk_in1
);
clk_wiz_0_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; double areaa(int x1, int x2, int x3, int y1, int y2, int y3); int gcd(int x, int y); int lcm(int x, int y); int egcd(int a, int b, int& x, int& y); vector<int> prime_possible_factors(int n); vector<int> primes_included(int n, int m); map<int, int> factor(int N); bool isPrime(int N); int charType(char c); double areaa(int x1, int x2, int x3, int y1, int y2, int y3) { double area = abs((x1 * (y2 - y3) + x2 * (y3 - y1) + x3 * (y1 - y2)) / 4.0); return area; } int gcd(int x, int y) { return y == 0 ? x : gcd(y, x % y); } int lcm(int x, int y) { return (x * y / gcd(x, y)); } int egcd(int a, int b, int& x, int& y) { if (b == 0) { x = 1; y = 0; return a; } else { int d = egcd(b, a % b, x, y); x -= a / b * y; swap(x, y); return d; } } vector<int> prime_possible_factors(int n) { bool* isPrime = new bool[n]; for (int i = 0; i < n; i++) { isPrime[i] = true; } vector<int> primes; for (int i = 2; i * i <= n; ++i) { if (isPrime[i]) { primes.push_back(i); for (int j = i; j < n; j += i) isPrime[j] = false; } } return primes; } vector<int> primes_included(int n, int m) { bool* isPrime = new bool[m]; for (int i = 0; i < m; i++) { isPrime[i] = true; } vector<int> primes; for (int i = 2; i < m; ++i) { if (isPrime[i]) { if (i >= n) primes.push_back(i); for (int j = i; j < m; j += i) isPrime[j] = false; } } return primes; } map<int, int> factor(int N) { vector<int> primes; primes = primes_included(0, N); map<int, int> factors; for (int i = 0; i < primes.size(); ++i) { int prime = primes[i], power = 0; while (N % prime == 0) { power++; N /= prime; } factors[prime] = power; } return factors; } bool isPrime(int N) { vector<int> check = prime_possible_factors(N); for (int i = 0; i < check.size(); i++) { if (N % check[i] == 0) { return false; } } return true; } int main() { int T; long long int n, s, t; cin >> T; int i = 0; for (i; i < T; i++) { cin >> n >> s >> t; cout << max(n - s, n - t) + 1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 5 + 2e5; int in[MAX], k = 1; long long s[MAX], sorted[MAX], tos[MAX << 1], BIT[MAX << 1]; map<long long, int> mp; void add(int i, int val) { while (i > 0) { BIT[i] += val; i -= (i & (-i)); } } long long at_index(int i) { long long sum = 0; while (i <= k) { sum += BIT[i]; i += (i & (-i)); } return sum; } int main() { ios::sync_with_stdio(0); long long x = 0, t, ans = 0; int n, i; cin >> n >> t; for (i = 0; i < n; ++i) cin >> in[i]; for (i = 0; i < n; ++i) { x += in[i]; s[i] = x; sorted[i] = x; tos[i] = x; } int N = 1 + 2 * n; for (i = 0; i < n; ++i) tos[n + i] = t + tos[i]; tos[n + i] = t; sort(sorted, sorted + n); sort(tos, tos + N); for (i = 0; i < N; ++i) { if (mp.find(tos[i]) == mp.end()) { mp[tos[i]] = k; ++k; } } for (i = 0; i < n; ++i) { x = upper_bound(sorted, sorted + n, t - 1) - sorted; ans += (x - at_index(mp[t])); t += in[i]; add(k, 1); add(mp[s[i]], -1); } cout << ans; } |
#include <bits/stdc++.h> using namespace std; void cal(long long number, long long x, long long s) { long long d = number ^ x; long long temp = 2 * number - (s + d); if (temp % 2 == 0) { cout << 3 << endl; cout << d << << temp / 2 << << temp / 2 << endl; } if (temp % 2 == 1) { number -= 1; d = number ^ x; temp = 2 * number - (s + d); cout << 3 << endl; cout << d << << temp / 2 << << temp / 2 << endl; } } void solve() { long long n; cin >> n; vector<long long> a(n); long long s = 0, x = 0, number = 0; for (long long i = 0; i < 57; i++) { number = number | 1LL << i; } for (long long i = 0; i < n; i++) { cin >> a[i]; s = s + a[i]; x = x ^ a[i]; } cal(number, x, s); } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; cin >> t; while (t--) solve(); return 0; } |
//Copyright 2011 Andreas Lindh
//This file is part of genMem.
//genMem is free software: you can redistribute it and/or modify
//it under the terms of the GNU Lesser General Public License as published by
//the Free Software Foundation, either version 3 of the License, or
//(at your option) any later version.
//
//genMem is distributed in the hope that it will be useful,
//but WITHOUT ANY WARRANTY; without even the implied warranty of
//MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//GNU Lesser General Public License for more details.
//
//You should have received a copy of the GNU Lesser General Public License
//along with genMem. If not, see <http://www.gnu.org/licenses/>.
`timescale 1 ns/1 ps
module twoPortMem (
writeAddress,
writeClk,
writeEnable,
writeData,
readAddress,
readClk,
readEnable,
readData);
//user defined
parameter addresses = 32;
parameter width = 8;
parameter muxFactor = 0;
parameter writeMask = 1;
//Auto-calculated, user dont touch
localparam addressWidth =$clog2(addresses);
input [addressWidth-1:0] writeAddress;
input writeClk;
input [writeMask-1:0] writeEnable;
input [width-1:0] writeData;
input [addressWidth-1:0] readAddress;
input readClk;
input readEnable;
output [width-1:0] readData;
generate
if((addresses==0)&&(width==0))
begin
initial
begin
$display("FAIL!! :%m:Parameters, addresses and width can not be set to 0");
$stop;
end
end
`include "scriptGeneratedListOfVendorTwoPortMems.vh"
else
begin
twoPortMemSim #(.addresses (addresses),
.width (width),
.muxFactor (muxFactor),
.writeMask (writeMask)
) mem (.writeAddress(writeAddress),
.writeClk(writeClk),
.writeEnable(writeEnable),
.writeData(writeData),
.readAddress(readAddress),
.readClk(readClk),
.readEnable(readEnable),
.readData(readData));
end
endgenerate
endmodule // twoPortMem
module twoPortMemSim (
writeAddress,
writeClk,
writeEnable,
writeData,
readAddress,
readClk,
readEnable,
readData);
//user defined
parameter addresses = 32;
parameter width = 8;
parameter muxFactor = 0;
parameter writeMask = 1;
//Auto-calculated, user dont touch
localparam addressWidth =$clog2(addresses);
input [addressWidth-1:0] writeAddress;
input writeClk;
input [writeMask-1:0] writeEnable;
input [width-1:0] writeData;
input [addressWidth-1:0] readAddress;
input readClk;
input readEnable;
output [width-1:0] readData;
reg [width-1:0] mem [addresses-1:0];
reg [width-1:0] readData;
integer i;
initial
begin
$display("%m : simulation model of memory");
end
always @(posedge writeClk)
begin
if (writeEnable!=0)
begin
if(writeMask==1)
begin
mem[writeAddress] <= writeData;
end
else
begin
for(i=0; i<writeMask; i=i+1)
if(writeEnable[i]==1)
mem[writeAddress][i] <= writeData[i];
end
end
end
always @(posedge writeClk)
begin
if(readEnable)
begin
readData <= mem[readAddress];
end
end
endmodule
|
`timescale 1ns / 1ps
// Decodes the bit-pairs received by the rx_DS_SE module
// into N-chars and L-chars.
//
// At present, parity is ignored. However, it will eventually
// be covered by this module as well.
// The only way to recover from a parity error is through
// resetting the module.
module rx_DS_char_tb();
reg rxClk, rxReset, dv;
reg [1:0] d;
wire [7:0] q;
wire nchar, lchar;
wire parityError;
rx_DS_char charDecoder(
.rxClk(rxClk),
.rxReset(rxReset),
.d(d),
.dValid(dv),
.q(q),
.nchar(nchar),
.lchar(lchar),
.parityError(parityError)
);
always begin
#10; rxClk = ~rxClk;
end
task bitPair;
input [1:0] pair;
begin
{dv, d} <= {1'b1, pair};
#20;
{dv, d} <= {1'b0, pair};
#20;
end
endtask
task nch;
input oddp;
input [7:0] chr;
begin
bitPair({1'b0, oddp});
bitPair(chr[1:0]);
bitPair(chr[3:2]);
bitPair(chr[5:4]);
bitPair(chr[7:6]);
end
endtask
task lch;
input oddp;
input [1:0] chr;
begin
bitPair({1'b1, oddp});
bitPair(chr);
end
endtask
task null;
input oddp;
begin
lch(oddp, 2'b11);
lch(0, 0);
end
endtask
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
{rxClk, rxReset, dv, d} <= 0;
#10;
rxReset <= 1;
#20;
rxReset <= 0;
#20;
null(0);
null(0);
nch(1, 8'h41);
lch(0, 2);
null(1);
null(0);
nch(1, 8'h4F);
lch(1, 2);
lch(1, 3); // NULL character with parity error.
lch(1, 0); // This result in parityError being asserted.
null(1);
null(0);
nch(1, 8'h41);
nch(1, 8'h62);
nch(0, 8'h63);
nch(1, 8'h64);
lch(1, 2);
null(1);
null(0);
$display("@I Done.");
$stop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2B_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NAND2B_PP_SYMBOL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand2b (
//# {{data|Data Signals}}
input A_N ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2B_PP_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (clk);
input clk;
// verilator lint_off WIDTH
`define INT_RANGE 31:0
`define INT_RANGE_MAX 31
`define VECTOR_RANGE 63:0
reg [`INT_RANGE] stashb, stasha, stashn, stashm;
function [`VECTOR_RANGE] copy_range;
input [`VECTOR_RANGE] y;
input [`INT_RANGE] b;
input [`INT_RANGE] a;
input [`VECTOR_RANGE] x;
input [`INT_RANGE] n;
input [`INT_RANGE] m;
begin
copy_range = y;
stashb = b;
stasha = a;
stashn = n;
stashm = m;
end
endfunction
parameter DATA_SIZE = 16;
parameter NUM_OF_REGS = 32;
reg [NUM_OF_REGS*DATA_SIZE-1 : 0] memread_rf;
reg [DATA_SIZE-1:0] memread_rf_reg;
always @(memread_rf) begin : memread_convert
memread_rf_reg = copy_range('d0, DATA_SIZE-'d1, DATA_SIZE-'d1, memread_rf,
DATA_SIZE-'d1, DATA_SIZE-'d1);
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
memread_rf = 512'haa;
end
if (cyc==3) begin
if (stashb != 'd15) $stop;
if (stasha != 'd15) $stop;
if (stashn != 'd15) $stop;
if (stashm != 'd15) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; map<int, int> m; bool f = true; vector<int> v; while (n--) { int a; cin >> a; v.push_back(a); m[a] += 1; if (m[a] > 1) f = false; } if (!f || !m[1]) { cout << -1 << endl; continue; } vector<int> o; set<int> s; for (int a : v) { o.push_back(a); s.insert(a); for (int i = a + 1; i < 201; i++) if (!m[i] && s.find(i) == s.end()) { o.push_back(i); s.insert(i); m[i] += 1; break; } } bool r = true; int p; for (int a : s) { if (f) p = a, f = false; if (a - p > 1) { r = false; break; } p = a; } f = false; if (r) for (int a : o) { if (f) cout << ; cout << a; f = true; } else cout << -1; cout << endl; } return 0; } |
/*********************************************************************
* SYNOPSYS CONFIDENTIAL *
* *
* This is an unpublished, proprietary work of Synopsys, Inc., and *
* is fully protected under copyright and trade secret laws. You may *
* not view, use, disclose, copy, or distribute this file or any *
* information contained herein except pursuant to a valid written *
* license from Synopsys. *
*********************************************************************/
// Description: General Purpose Registers
//
module GeneralPurposeRegisters(A,B,C,RdAdrA,RdAdrB,RdAdrC,
WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,clock,reset);
output [31:0] A, B, C; // A-reg, B-reg, & C-reg outputs
input [3:0] RdAdrA, RdAdrB, RdAdrC; // Read Addresses
input [3:0] WrtAdrX, WrtAdrY; // Write Address
input WrtEnbX, WrtEnbY; // Write Enables
input [31:0] X, Y; // Data Input
input clock;
input reset;
wire [31:0] regIn0, regIn1, regIn2, regIn3;
wire [31:0] regIn4, regIn5, regIn6, regIn7;
wire [31:0] regIn8, regIn9, regInA, regInB;
wire [31:0] regInC, regInD, regInE, regInF;
wire [31:0] Data_A, Data_B, Data_C;
reg [31:0] GPR0_reg, GPR1_reg, GPR2_reg, GPR3_reg;
reg [31:0] GPR4_reg, GPR5_reg, GPR6_reg, GPR7_reg;
reg [31:0] GPR8_reg, GPR9_reg, GPRA_reg, GPRB_reg;
reg [31:0] GPRC_reg, GPRD_reg, GPRE_reg, GPRF_reg;
reg [31:0] A_reg, B_reg, C_reg;
// Write GPRs decode
//
assign regIn0 = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPR0_reg,4'h0);
assign regIn1 = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPR1_reg,4'h1);
assign regIn2 = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPR2_reg,4'h2);
assign regIn3 = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPR3_reg,4'h3);
assign regIn4 = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPR4_reg,4'h4);
assign regIn5 = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPR5_reg,4'h5);
assign regIn6 = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPR6_reg,4'h6);
assign regIn7 = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPR7_reg,4'h7);
assign regIn8 = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPR8_reg,4'h8);
assign regIn9 = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPR9_reg,4'h9);
assign regInA = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPRA_reg,4'hA);
assign regInB = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPRB_reg,4'hB);
assign regInC = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPRC_reg,4'hC);
assign regInD = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPRD_reg,4'hD);
assign regInE = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPRE_reg,4'hE);
assign regInF = GPRdecode(WrtAdrX,WrtEnbX,WrtAdrY,WrtEnbY,X,Y,GPRF_reg,4'hF);
// Read GPRs selection
//
assign Data_A=Select16(RdAdrA,GPR0_reg,GPR1_reg,GPR2_reg,GPR3_reg,
GPR4_reg,GPR5_reg,GPR6_reg,GPR7_reg,
GPR8_reg,GPR9_reg,GPRA_reg,GPRB_reg,
GPRC_reg,GPRD_reg,GPRE_reg,GPRF_reg);
assign Data_B=Select16(RdAdrB,GPR0_reg,GPR1_reg,GPR2_reg,GPR3_reg,
GPR4_reg,GPR5_reg,GPR6_reg,GPR7_reg,
GPR8_reg,GPR9_reg,GPRA_reg,GPRB_reg,
GPRC_reg,GPRD_reg,GPRE_reg,GPRF_reg);
assign Data_C=Select16(RdAdrC,GPR0_reg,GPR1_reg,GPR2_reg,GPR3_reg,
GPR4_reg,GPR5_reg,GPR6_reg,GPR7_reg,
GPR8_reg,GPR9_reg,GPRA_reg,GPRB_reg,
GPRC_reg,GPRD_reg,GPRE_reg,GPRF_reg);
// Drive the A, B & C registers to the module outputs
//
assign A = A_reg;
assign B = B_reg;
assign C = C_reg;
// CLOCKED: Load GPR Registers and A, B & C Registers
//
// synopsys sync_set_reset "reset"
always @ (posedge clock)
begin
if (reset)
begin
GPR0_reg = 32'h00000000; GPR1_reg = 32'h00000000;
GPR2_reg = 32'h00000000; GPR3_reg = 32'h00000000;
GPR4_reg = 32'h00000000; GPR5_reg = 32'h00000000;
GPR6_reg = 32'h00000000; GPR7_reg = 32'h00000000;
GPR8_reg = 32'h00000000; GPR9_reg = 32'h00000000;
GPRA_reg = 32'h00000000; GPRB_reg = 32'h00000000;
GPRC_reg = 32'h00000000; GPRD_reg = 32'h00000000;
GPRE_reg = 32'h00000000; GPRF_reg = 32'h00000000;
A_reg = 32'h00000000;
B_reg = 32'h00000000;
C_reg = 32'h00000000;
end
else
begin
GPR0_reg = regIn0; GPR1_reg = regIn1;
GPR2_reg = regIn2; GPR3_reg = regIn3;
GPR4_reg = regIn4; GPR5_reg = regIn5;
GPR6_reg = regIn6; GPR7_reg = regIn7;
GPR8_reg = regIn8; GPR9_reg = regIn9;
GPRA_reg = regInA; GPRB_reg = regInB;
GPRC_reg = regInC; GPRD_reg = regInD;
GPRE_reg = regInE; GPRF_reg = regInF;
A_reg = Data_A;
B_reg = Data_B;
C_reg = Data_C;
end
end
// FUNCTION: Select16 - Generate Data in for GPRs
//
function [31:0] Select16;
input [3:0] sel;
input [31:0] d0,d1,d2,d3,d4,d5,d6,d7;
input [31:0] d8,d9,da,db,dc,dd,de,df;
case(sel)
4'h0: Select16=d0;
4'h1: Select16=d1;
4'h2: Select16=d2;
4'h3: Select16=d3;
4'h4: Select16=d4;
4'h5: Select16=d5;
4'h6: Select16=d6;
4'h7: Select16=d7;
4'h8: Select16=d8;
4'h9: Select16=d9;
4'hA: Select16=da;
4'hB: Select16=db;
4'hC: Select16=dc;
4'hD: Select16=dd;
4'hE: Select16=de;
4'hF: Select16=df;
endcase
endfunction
// FUNCTION: GPR Decode - Generate Data in for GPRs
//
function [31:0] GPRdecode;
input [3:0] xaddr;
input xenb;
input [3:0] yaddr;
input yenb;
input [31:0] x;
input [31:0] y;
input [31:0] hold;
input [3:0] gpr;
if ( (xaddr[3:0] == gpr[3:0]) && (xenb == 1'b1) )
GPRdecode = x;
else if ( (yaddr[3:0] == gpr[3:0]) && (yenb == 1'b1) )
GPRdecode = y;
else
GPRdecode = hold;
endfunction
//always #10 $display ($time,,, " X=%h, Adr=%h, E=%b",X,WrtAdrX,WrtEnbX);
//always #10 $display ($time,,, " Y=%h, Adr=%h, E=%b",Y,WrtAdrY,WrtEnbY);
//always #10 $display ($time,,, " RdA=%h, RdB=%h, RdC=%h",RdAdrA,RdAdrB,RdAdrC);
//always #10 $display ($time,,, " in0=%h GPR0=%h",regIn0,GPR0_reg);
//always #10 $display ($time,,, " in1=%h GPR1=%h",regIn1,GPR1_reg);
//always #10 $display ($time,,, " in2=%h GPR2=%h",regIn2,GPR2_reg);
//always #10 $display ($time,,, " in3=%h GPR3=%h",regIn3,GPR3_reg);
//always #10 $display ($time,,, " da=%h A=%h",Data_A,A_reg);
//always #10 $display ($time,,, " db=%h B=%h",Data_B,B_reg);
//always #10 $display ($time,,, " dc=%h C=%h",Data_C,C_reg);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; string s; cin >> n >> s; for (int i = 0; i < s.length() - 1; i++) { if (s[i] > s[i + 1]) { cout << YES << endl << i + 1 << << i + 2; return 0; } } cout << NO ; return 0; } |
//////////////////////////////////////////////////////////////////////////////////
// AXI4LiteSlaveInterface for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <>
// Yong Ho Song <>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <>
//
// Project Name: Cosmos OpenSSD
// Design Name: AXI4Lite slave interface
// Module Name: AXI4LiteSlaveInterface
// File Name: AXI4LiteSlaveInterface.v
//
// Version: v1.0.0
//
// Description: AXI4-Lite compliant slave interface for AXI-related IPs
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module AXI4LiteSlaveInterface
#
(
parameter AddressWidth = 32,
parameter DataWidth = 32
)
(
ACLK ,
ARESETN ,
AWVALID ,
AWREADY ,
AWADDR ,
AWPROT ,
WVALID ,
WREADY ,
WDATA ,
WSTRB ,
BVALID ,
BREADY ,
BRESP ,
ARVALID ,
ARREADY ,
ARADDR ,
ARPROT ,
RVALID ,
RREADY ,
RDATA ,
RRESP ,
oWriteAddress ,
oReadAddress ,
oWriteData ,
iReadData ,
oWriteValid ,
oReadValid ,
iWriteAck ,
iReadAck
);
// AXI4 Lite Interface
input ACLK ;
input ARESETN ;
input AWVALID ;
output AWREADY ;
input [AddressWidth - 1:0] AWADDR ;
input [2:0] AWPROT ;
input WVALID ;
output WREADY ;
input [DataWidth - 1:0] WDATA ;
input [DataWidth/8 - 1:0] WSTRB ;
output BVALID ;
input BREADY ;
output [1:0] BRESP ;
input ARVALID ;
output ARREADY ;
input [AddressWidth - 1:0] ARADDR ;
input [2:0] ARPROT ;
output RVALID ;
input RREADY ;
output [DataWidth - 1:0] RDATA ;
output [1:0] RRESP ;
// Inner AXI-like Interface
output [AddressWidth - 1:0] oWriteAddress ;
output [AddressWidth - 1:0] oReadAddress ;
output [DataWidth - 1:0] oWriteData ;
input [DataWidth - 1:0] iReadData ;
output oWriteValid ;
output oReadValid ;
input iWriteAck ;
input iReadAck ;
AXI4LiteSlaveInterfaceWriteChannel
#
(
.AddressWidth (AddressWidth ),
.DataWidth (DataWidth )
)
Inst_AXI4LiteSlaveInterfaceWriteChannel
(
.ACLK (ACLK ),
.ARESETN (ARESETN ),
.AWVALID (AWVALID ),
.AWREADY (AWREADY ),
.AWADDR (AWADDR ),
.AWPROT (AWPROT ),
.WVALID (WVALID ),
.WREADY (WREADY ),
.WDATA (WDATA ),
.WSTRB (WSTRB ),
.BVALID (BVALID ),
.BREADY (BREADY ),
.BRESP (BRESP ),
.oWriteAddress (oWriteAddress ),
.oWriteData (oWriteData ),
.oWriteValid (oWriteValid ),
.iWriteAck (iWriteAck )
);
AXI4LiteSlaveInterfaceReadChannel
#
(
.AddressWidth (AddressWidth ),
.DataWidth (DataWidth )
)
Inst_AXI4LiteSlaveInterfaceReadChannel
(
.ACLK (ACLK ),
.ARESETN (ARESETN ),
.ARVALID (ARVALID ),
.ARREADY (ARREADY ),
.ARADDR (ARADDR ),
.ARPROT (ARPROT ),
.RVALID (RVALID ),
.RREADY (RREADY ),
.RDATA (RDATA ),
.RRESP (RRESP ),
.oReadAddress (oReadAddress ),
.iReadData (iReadData ),
.oReadValid (oReadValid ),
.iReadAck (iReadAck )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2B_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR2B_BLACKBOX_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor2b (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2B_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:43:39 06/14/2016
// Design Name:
// Module Name: tausworthe
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tausworthe( urng_seed1, urng_seed2, urng_seed3, clk, reset, out, valid
);
input [31:0]urng_seed1;
input [31:0]urng_seed2;
input [31:0]urng_seed3;
input clk, reset;
output reg [31:0]out;
output reg valid;
reg [31:0]b1,b2,b3,seed1,seed2, seed3, seed4;
initial
begin
out=0;
valid=0;
seed1=0;
seed2=0;
seed3=0;
seed4=0;
b1=0;
b2=0;
b3=0;
end
/* asynchronous reset
always @(posedge reset) // reset works irrespective of clock pulse.
begin
out<=0;
valid<=0;
end
*/
always @(posedge clk, reset, urng_seed1,urng_seed2,urng_seed3)
begin
if(reset) // synchronous reset. Reset works only on positive clock pulse.
begin
out=0;
valid=0;
end
else
begin // tausworthe logic
b1=(((urng_seed1<<13)^urng_seed1)>>19);
seed1= (((urng_seed1&'hFFFFFFFE)<<12)^b1);
b1=(((urng_seed2<<2)^urng_seed2)>>25);
seed2=(((urng_seed2&'hFFFFFFF8)<<4)^b1);
b1=(((urng_seed3<<3)^urng_seed3)>>11);
seed3=(((urng_seed3&'hFFFFFFF0)<<17)^b1);
seed4=seed1^seed2;
out=seed4^seed3;
valid=1;
end
end
endmodule
|
#include <bits/stdc++.h> int read() { int r = 0, t = 1, c = getchar(); while (c < 0 || c > 9 ) { t = c == - ? -1 : 1; c = getchar(); } while (c >= 0 && c <= 9 ) { r = (r << 3) + (r << 1) + (c ^ 48); c = getchar(); } return r * t; } const int N = 200010; int n; int c1, c2; std::vector<int> e[N]; int dfs(int u, int f) { int c = 0; for (auto v : e[u]) if (v != f) c += dfs(v, u); if (c) { c1++; c2 += c; return 0; } else return 1; } int main() { for (int T = (1), end_T = (read()); T <= end_T; T++) { n = read(); c1 = c2 = 0; for (int i = (1), end_i = (n); i <= end_i; i++) e[i].clear(); for (int i = (1), end_i = (n - 1); i <= end_i; i++) { int u = read(), v = read(); e[u].push_back(v); e[v].push_back(u); } dfs(1, 0); printf( %d n , c2 - (c1 - 1)); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { string s; cin >> s; int x; cin >> x; int a[s.length()]; for (int i = 0; i < s.length(); i++) { a[i] = 1; } for (int i = 0; i < s.length(); i++) { if (s[i] == 0 ) { if (i - x >= 0) { a[i - x] = 0; } if (i + x < s.length()) { a[i + x] = 0; } } } int tag = 0; for (int i = 0; i < s.length(); i++) { if (s[i] == 1 ) { int tag1 = 0; if (i - x >= 0) { if (a[i - x] == 1) { a[i - x] = 1; tag1++; } } if (i + x < s.length()) { if (a[i + x] == 1) { tag1++; } } if (tag1 == 0) { tag = 1; break; } } } if (tag == 1) { cout << -1 << endl; } else { for (int i = 0; i < s.length(); i++) { cout << a[i]; } cout << endl; } } } |
#include <bits/stdc++.h> using namespace std; const int Z = (int)3e3 + 228; const int N = (int)1e6 + 228; const int INF = (int)1e9 + 228; const int MOD = (int)1e9 + 7; int n, d; long long a[N], delta[N], k; bool can(long long mid) { fill(delta + 1, delta + 1 + n, 0LL); for (int i = 1; i <= n; i++) { delta[max(1, i - d)] += a[i]; delta[i + d + 1] -= a[i]; } long long cur = 0, res = 0; for (int i = 1; i <= n; i++) { cur += delta[i]; if (cur < mid) { res += mid - cur; if (res > k) return false; delta[i + 2 * d + 1] -= mid - cur; cur = mid; } } return true; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> d >> k; for (int i = 1; i <= n; i++) cin >> a[i]; long long l = 0, r = 2e18 + 5; while (l < r) { long long mid = (l + r + 1) / 2; if (can(mid)) l = mid; else r = mid - 1; } cout << l; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, m, i, cnt = 0, sum = 0, ans = 0, x, j; string s; vector<string> v; cin >> n >> m; int a[m]; for (i = 0; i < n; i++) { cin >> s; v.push_back(s); } for (i = 0; i < m; i++) cin >> a[i]; for (i = 0; i < m; i++) { int arr[5] = {0}; for (j = 0; j < n; j++) { x = v[j][i] - A ; arr[x]++; } sort(arr, arr + 5); ans += arr[4] * a[i]; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; long long n, num; long long a[maxn]; long long vis[maxn]; priority_queue<long long> pq; void fnd(long long x) { if (vis[a[x]] == 0) { vis[a[x]] = 1; num++; fnd(a[x]); } else return; } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } memset(vis, 0, sizeof(vis)); for (int i = 1; i <= n; i++) { num = 1; if (vis[i] == 0) { vis[i] = 1; fnd(i); pq.push(num); } } long long t = pq.top(); pq.pop(); if (!pq.size()) { cout << t * t << endl; } else { t += pq.top(); pq.pop(); long long ans = t * t; while (pq.size()) { t = pq.top(); pq.pop(); ans += t * t; } cout << ans << endl; } return 0; } |
/* _/_/_/_/_/_/ _/_/_/_/_/ _/_/_/_/_/ _/_/_/_/_/ _/_/_/_/_/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/_/_/ _/_/_/ _/_/_/_/_/ _/_/_/_/_/ _/_/ _/ _/ _/ _/ _/ _/ _/ _/ _/ _/_/_/_/_/_/ _/_/_/_/_/ _/_/_/_/_/ _/ _/ _/ _/ _/ */ #include<bits/stdc++.h> #include<math.h> #define IOS ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); #define int long long #define test int t; cin>>t; while(t--) #define vi vector<int> v; #define pb push_back #define input(arr) int n; cin>>n; int arr[n]; for(int i=0; i<n; i++) {cin>>arr[i];} #define f(n) for(int i=0; i<n; i++) #define OK if(ok){cout<< YES <<endl;} else{cout<< NO <<endl;} #define Ok if(ok){cout<< Yes <<endl;} else{cout<< No <<endl;} #define mod 1000000007 #define endl n using namespace std; //----------------------------------------------------------------------------- // to check prime number IN O(sqrt(n)) //bool isPrime(int); // //// to get divisors of a number IN O(sqrt(n)) //vector<int> divisors(int); // //// to find power using mod using Binary Exponential in TC O(logn) //int power(int, int, int); // //// ternary search to find x in sorted array arr //int ts(int, int, int, int); // //// to find frequencies of a substring in a string or to find all positions of all substrings //vector<int> count_freq(string ,string); // ////to check palindrome //bool palindrome(int, int); // #ifndef ONLINE_JUDGE // if (fopen( input.txt , r )) // { // freopen( input.txt , r , stdin); // freopen( output.txt , w , stdout); // } // #endif //************************************************************************************************* vector<int> printDivisors(int n, int temp) { vector<int> vec; // Note that this loop runs till square root for (int i=1; i<=sqrt(n); i++) { if (n%i == 0) { // If divisors are equal, print only one if (n/i == i) { if(i >= temp) vec.pb(i); } else // Otherwise print both { if(i >= temp) vec.pb(i); if((n/i) >= temp) vec.pb(n/i); } } } return vec; } int32_t main() { IOS #ifndef ONLINE_JUDGE if (fopen( input.txt , r )) { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } #endif test { int n; cin >> n; int arr[n]; int temp = 0; int sum = 0; f(n) { cin >> arr[i]; sum += arr[i]; temp = max(temp, arr[i]); } vector<int> v = printDivisors(sum, temp); sort(v.begin(), v.end()); int ans = 0; int j=0, add=0; int t1 = v[j]; for(int i=0; i<n; i++) { if(arr[i] != t1) { add += arr[i]; ans++; if(add > t1) { ans = 0; add = 0; i = -1; ++j; t1 = v[j]; } else if(add == t1) { ans--; add = 0; } } else if(add > 0) { add = 0; ans = 0; i = -1; ++j; t1 = v[j]; } } cout << ans << endl; } return 0; } //****************************************************************************** //getchar() - uses for no extra comments in output section //toupper() - converts a string in uppercase //tolower() //lower_bound((a, a+n, m)-a) - when you have to find total number of small values to m b/w range of a to a+n // or finds the lower position of num. eg 10 20 30 30 30 40 50 num=30, ans = 2; //upper_bound - work as lower_bound but finds the upper position. eg 10 20 30 30 30 40 50 num=30, ans = 5; //shift+f6+enter - to change a word everywhere //stringstream - to find number of words in a string or to find frequency of words //s.substr(1, 3) - geeks - eek //*max_element(v+2, v+4) - to find max element in an array //*min_element //__gcd(2, 10) - to find greatest common devisor, doesn t support float or double //count(a, a+n, k) - to find frequency of k or frequency of a char in string in an array or in vector //s = aaaaa , a[2]++, s = aabaa //compare() - to campare to string s size //__builtin_popcountll(n) - number of bit 1 in n //__builtin_ctzll(n) - number of bit 0 after last 1 //cout<<fixed()<<setprecision(k)<<endl; //log(n) - to find digits in binary repersatation, returns float value //floor(1.3) - 3, floor(-1.2) - -2 //****************************************************************************** //// to check prime number //bool isPrime(int n) //IN O(sqrt(n)) //{ // if(n<=1) return false; // for(int i=2;i*i<=n;i++) // if(n%i==0) // return false; // // return true; //} // //// to get divisors of a number. Recall - it s not i sorted order //// vector<int> v = divisors(n); function call //vector<int> divisors(int n){ //IN O(sqrt(n)) // // vector<int> v; // for(int i=1;i*i<=n;i++) // { // if(n%i==0) // { // v.pb(i); // if((n/i)!=i) // v.pb(n/i); // } // } // return v; //} // //// to find power using mod //int power(int a, int n, int m) // using Binary Exponential in TC O(logn) //{ // int res=1; // while(n) // { // if(n%2) // res=(res*a)%m ,n--; // else // a=(a*a)%m ,n/=2; // } // return res; //} // //// ternary search to find x in sorted array arr //int ts(int arr[],int l,int r,int x) //{ // // while(l<=r) // { // int mid1= l+(r-l)/3; // int mid2= r -(r-l)/3; // if(arr[mid1]==x || arr[mid2]==x) // return 1; // if(x<arr[mid1]) // r=mid1-1; // else if(x>arr[mid2]) // l=mid2+1; // else // { // l=mid1+1; // r=mid2-1; // } // } // return 0; //} // //// to find frequencies of a substring in a string or to find all positions of all substrings //// vector<int> v = count_freq(s1 ,s2); function calling //// position storing is 0 based indexing add 1 if required 1 based indexing. ////This code is used to count the frequency of particular substring in a given string using the found function //vector<int> count_freq(string &str ,string &substr) //{ // vector<int>pos; // size_t found = str.find(substr,0); // while(found!=string::npos) // { // pos.pb(found); // found=str.find(substr,found+1); // } // return pos; //} // // //bool palindrome(int arr[], int n) //{ // int flag = 0; // for (int i = 0; i <= n / 2 && n != 0; i++) { // if (arr[i] != arr[n - i - 1]) { // flag = 1; // break; // } // } // if (flag == 1) // return true; // else // return false; //} |
#include <bits/stdc++.h> using namespace std; void rf() {} void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } void solve() { int k = 0; string s; cin >> s; k = 0; for (int i = 0; i < s.size(); i++) { if (k && s[i] == B ) { k--; } else { k++; } } cout << k << endl; } int main() { fast(); rf(); int t; cin >> t; while (t--) { solve(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_1_V
`define SKY130_FD_SC_LS__A221O_1_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a221o_1 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2B_BLACKBOX_V
`define SKY130_FD_SC_LP__AND2B_BLACKBOX_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2b (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2B_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; ; vector<pair<int, int>> vec; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k, a, b, c; c = 1; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> a >> b; vec.push_back(make_pair(a * -1, b)); } sort(vec.begin(), vec.end()); for (int i = 0; i < n; i++) { if (i == k - 1) { while (vec[i] == vec[i + 1]) { i++; c++; } cout << c << n ; break; } if (vec[i] == vec[i + 1]) c++; else c = 1; } cout.flush(); } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 100; int a[N]; int per[N]; int main() { int n; cin >> n; for (int i = 0; i < n - 1; i++) { scanf( %d , &a[i]); } int ls = a[0]; set<int> st; for (int i = 1; i <= n; i++) { st.insert(i); } for (int i = 0; i < n - 1; i++) { if (per[a[i]]) { ls = *(--st.end()); st.erase(--st.end()); per[ls] = a[i]; } else { st.erase(a[i]); per[a[i]] = per[ls]; per[ls] = a[i]; if (i == 0) i--; } } printf( %d n , a[0]); for (int i = 1; i <= n; i++) { if (per[i] == i) continue; printf( %d %d n , i, per[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int Inf = (1 << 30) - 1; const long long lInf = (1LL << 62) - 1; const int mInf = 0x7f7f7f7f; const int Maxn = 200010; vector<int> a[Maxn]; pair<int, int> S[Maxn << 1]; int f[Maxn]; int t[Maxn]; int n, m, ans; void solve(int k) { map<int, int> M; for (int i = 1; i <= n; i++) M[++f[i]] = i; for (int i = 1; i <= n; i++) t[i] = a[i][k]; int cnt = 0, tot = 0, minn = Inf; for (int i = 1; i <= n; i++) { int tmp = M[t[i]]; if (tmp != 0 && i - tmp != 0) S[++tot] = make_pair(i - tmp > 0 ? i - tmp : i - tmp + n, 1); if (tmp != 0) S[++tot] = make_pair(i - tmp + 1 > 0 ? i - tmp + 1 : i - tmp + n + 1, -1); if (t[i] == f[i]) cnt++; } sort(S + 1, S + tot + 1); minn = min(minn, n - cnt); int p = 1; for (int i = 1; i < n; i++) { while (S[p].first <= i && p <= tot) cnt += S[p++].second; minn = min(minn, i + n - cnt); } ans += minn; } int main() { ios::sync_with_stdio(false); cin >> n >> m; for (int i = 1; i <= n; i++) { a[i].push_back(0); for (int x, j = 1; j <= m; j++) cin >> x, a[i].push_back(x); } for (int i = 1; i <= n; i++) f[i] = (i - 1) * m; for (int i = 1; i <= m; i++) solve(i); cout << ans << endl; return 0; } |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module cic_decim_tb;
cic_decim #(.bitwidth(16),.stages(4))
decim(clock,reset,enable,strobe_in,strobe_out,signal_in,signal_out);
reg clock;
reg reset;
reg enable;
wire strobe;
reg [15:0] signal_in;
wire [15:0] signal_out;
assign strobe_in = 1'b1;
reg strobe_out;
always @(posedge clock)
while(1)
begin
@(posedge clock);
@(posedge clock);
@(posedge clock);
@(posedge clock);
strobe_out <= 1'b1;
@(posedge clock);
@(posedge clock);
@(posedge clock);
@(posedge clock);
strobe_out <= 1'b0;
end
initial clock = 0;
always #50 clock = ~clock;
initial reset = 1;
initial #1000 reset = 0;
initial enable = 0;
initial #2000 enable = 1;
initial signal_in = 16'h1;
initial #500000 signal_in = 16'h7fff;
initial # signal_in = 16'h8000;
initial # signal_in = 16'hffff;
initial $dumpfile("decim.vcd");
initial $dumpvars(0,cic_decim_tb);
initial #10000000 $finish;
endmodule // cic_decim_tb
|
#include <bits/stdc++.h> using namespace std; class Timer { clock_t start; string name; public: Timer() { name = ; start = clock(); } Timer(string s) { name = s; start = clock(); } ~Timer() { fprintf(stderr, %s: %.3gs n , name.c_str(), 1.0 * (clock() - start) / CLOCKS_PER_SEC); } }; const double EPS = 1e-9; const long double PI = acos(-1.0L); template <typename dtype> inline dtype sq(dtype a) { return a * a; } template <typename dtype1, typename dtype2> inline pair<dtype1, dtype2> mp(dtype1 a, dtype2 b) { return make_pair(a, b); } template <typename dtype1, typename dtype2> inline dtype1 safeMod(dtype1 a, dtype2 m) { return (a % m + m) % m; } template <typename dtype1, typename dtype2> inline bool isEq(dtype1 a, dtype2 b) { return abs(a - b) < EPS; } template <typename dtype1, typename dtype2, typename dtype3> inline bool isEq(dtype1 a, dtype2 b, dtype3 eps) { return abs(a - b) < eps; } template <typename dtype> inline dtype toRad(dtype deg) { return deg * PI / 180.0; } template <typename dtype> inline dtype toDeg(dtype rad) { return rad * 180.0 / PI; } template <typename dtype> inline bool isKthBitOn(dtype n, int k) { assert(n <= numeric_limits<dtype>::max()); assert(k <= numeric_limits<dtype>::digits); dtype ONE = 1; return bool((n & (ONE << k))); } template <typename dtype> inline void setKthBit(dtype& n, int k) { assert(n <= numeric_limits<dtype>::max()); assert(k <= numeric_limits<dtype>::digits); dtype ONE = 1; n = (n | (ONE << k)); } const int oo = 0x3f3f3f3f; const int MAX = 200010; const int MOD = 1000000007; const int precision = 10; int main(int argc, char* argv[]) { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, s, sum = 0; long long ara[MAX]; cin >> n >> s; long long mini = INT_MAX; for (int i = 0; i < n; i++) { cin >> ara[i]; sum += ara[i]; mini = min(mini, ara[i]); } if (sum < s) cout << -1; else { sum = 0; for (int i = 0; i < n; i++) { sum += ara[i] - mini; } s -= sum; s = max(s, 0LL); mini -= s / n + (s % n != 0); cout << mini << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = (int)2e3 + 113; long long n, k, cnt = 0; int main() { cin >> k >> n; while (n > k) { if (n % k != 0) { cout << NO ; return 0; } n /= k; cnt++; } if (n == k) { cout << YES << endl << cnt; return 0; } cout << NO ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUF_FUNCTIONAL_V
`define SKY130_FD_SC_LS__BUF_FUNCTIONAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__buf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUF_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 1e5; long long int n; long long int t[2 * N]; int main() { long long int n, k; cin >> n >> k; long long int a[k], ans = 1e18, g = 0; for (int i = 0; i < k; i++) { cin >> a[i]; if (n % a[i] < ans) { ans = n % a[i]; g = i; } } cout << g + 1 << << n / a[g] << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4BB_2_V
`define SKY130_FD_SC_LS__NOR4BB_2_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog wrapper for nor4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4bb_2 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4bb_2 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4BB_2_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_5_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_5_e.v,v 1.3 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_5_e.v,v $
// Revision 1.3 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_5_e
//
// No `defines in this module
module inst_5_e
//
// Generated Module inst_5
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_5_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; set<pair<int, int> > second; int arr[(int)(1e5) + 30]; int main() { int n, m; int u, v; cin >> n >> m; for (int i = 0; i < m; i++) { cin >> u >> v; second.insert(make_pair(u, v)); second.insert(make_pair(v, u)); } for (int i = 0; i < n; i++) arr[i] = i + 1; int limit = 1000; while (limit--) { random_shuffle(arr, arr + n); arr[n] = arr[0]; for (int i = 0; i < m; i++) { if (second.find(make_pair(arr[i], arr[i + 1])) != second.end()) goto re; } for (int i = 0; i < m; i++) cout << arr[i] << << arr[i + 1] << endl; return 0; re:; } puts( -1 ); } |
#include <bits/stdc++.h> using namespace std; double xp, yp, vp; double x, y, v, r; const double pi = acos(-1); double cal(double x0, double y0, double x1, double y1) { double ji = x0 * x1 + y0 * y1; double L0 = sqrt(x0 * x0 + y0 * y0); double L1 = sqrt(x1 * x1 + y1 * y1); double cosA = ji / L0 / L1; double A = acos(cosA); double s = L1 * L0 * sin(A) / (double)2; double l = sqrt((x0 - x1) * (x0 - x1) + (y0 - y1) * (y0 - y1)); double dis = s * (double)2 / l; if (dis >= r || (L0 * L0 + l * l - L1 * L1) < 0 || (L1 * L1 + l * l - L0 * L0) < 0) return l; double a0 = acos(r / L0); double a1 = acos(r / L1); double Lsum = r * (A - a0 - a1) + L0 * sin(a0) + L1 * sin(a1); return Lsum; } bool s(double t) { double R = sqrt(xp * xp + yp * yp); double a = acos(xp / R); if (yp < 0) a = -a + 2 * pi; a = a + t * vp / R; double x0 = R * cos(a); double y0 = R * sin(a); double t0 = cal(x0, y0, x, y) / v; if (t0 <= t) return true; else return false; } int main() { cin >> xp >> yp >> vp; cin >> x >> y >> v >> r; double l = 0, r = 1e4, mid; while (r - l > 1e-9) { mid = (r + l) / (double)2; if (s(mid)) r = mid; else l = mid; } printf( %.10lf , mid); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 9; vector<int> getBorder(const string str) { int n = str.size(); vector<int> border(n, -1); for (int i = 1, j = -1; i < n; i++) { while (j >= 0 && str[i] != str[j + 1]) { j = border[j]; } if (str[i] == str[j + 1]) j++; border[i] = j; } return border; } int matchPattern(string txt, string pat, const vector<int> border) { int freq = 0; for (int i = 0, j = -1; i < (int)txt.size(); i++) { while (j >= 0 && txt[i] != pat[j + 1]) { j = border[j]; } if (txt[i] == pat[j + 1]) { j++; } if (j + 1 == (int)pat.size()) { freq++; j = border[j]; } } return freq; } string cut(string s, int p, bool pref = true) { if (!pref) { reverse(s.begin(), s.end()); } while ((int)s.size() >= p) s.pop_back(); if (!pref) { reverse(s.begin(), s.end()); } return s; } const int ms = 210; string pref[ms], suf[ms]; long long trans[ms]; int bk = 14; long long getFreq(int n, string pat, long long k) { std::vector<long long> f(n + 1, 0); if (pat == 0 ) f[0]++; if (pat == 1 ) f[1]++; auto border = getBorder(pat); for (int i = 2; i <= n; i++) { long long cur = trans[i - 2]; if (i < bk + 4) { string curString = cut(suf[i - 2], (int)pat.size(), false) + cut(pref[i - 1], (int)pat.size()); cur = matchPattern(curString, pat, border); } f[i] = f[i - 1] + f[i - 2] + cur; if (f[i] > k) return k + 1; trans[i] = cur; } return min(f[n], k + 1); } int main() { pref[0] = suf[0] = 0 ; pref[1] = suf[1] = 1 ; for (int i = 2; i < ms; i++) { pref[i] = cut(pref[i - 2] + pref[i - 1], ms); suf[i] = cut(suf[i - 2] + suf[i - 1], ms, false); } int n, m; long long k; cin >> n >> k >> m; if (n == 0) { cout << 0 n ; return 0; } if (n == 1) { cout << 1 n ; return 0; } string ans; k--; while (k >= 0 && (int)ans.size() < m) { if (ans.size() > 0 && suf[n].substr(suf[n].size() - ans.size(), ans.size()) == ans) { k--; } if (k < 0) break; ans += 0 ; long long got = getFreq(n, ans, k); if (got <= k) { ans.back() = 1 ; k -= got; } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; ifstream Cin( input.txt ); ofstream Cout( output.txt ); int main() { long long i, n4 = 0, n7 = 0, n; string a, b; cin >> a >> b; for (i = 0; i < a.length(); i++) if (a[i] != b[i]) { if (a[i] == 4 ) n4++; else n7++; } cout << n4 + n7 - min(n4, n7); } |
#include <bits/stdc++.h> using namespace std; const int N = 1.1e6; int ans; int n, m; vector<int> F; int S[N][7][7]; int s(int i, int a, int b) { if (i == m) return (F[i] - a) / 3; if (i + 1 == m) return (F[i] - a) / 3 + (F[i + 1] - b) / 3; int loc = S[i + 1][b][0]; for (int j = 0; j < 3; j++) if (a + j <= min(6, F[i]) && b + j <= min(6, F[i + 1]) && 0 + j <= min(6, F[i + 2])) loc = max(loc, j + ((F[i] - (a + j)) / 3) + S[i + 1][b + j][j]); return loc; } int main() { scanf( %d%d , &n, &m); F = vector<int>(m + 1); for (int i = 0; i < n; i++) { int a; scanf( %d , &a); F[a]++; } for (int i = m; i + 1; i--) for (int a = 0; a < 7; a++) for (int b = 0; b < 7; b++) S[i][a][b] = s(i, a, b); printf( %d n , ans + S[0][0][0]); } |
`include "gate.v"
module Not16(input[15:0] in, output[15:0] out);
Not g15(in[15], out[15]);
Not g14(in[14], out[14]);
Not g13(in[13], out[13]);
Not g12(in[12], out[12]);
Not g11(in[11], out[11]);
Not g10(in[10], out[10]);
Not g09(in[9], out[9]);
Not g08(in[8], out[8]);
Not g07(in[7], out[7]);
Not g06(in[6], out[6]);
Not g05(in[5], out[5]);
Not g04(in[4], out[4]);
Not g03(in[3], out[3]);
Not g02(in[2], out[2]);
Not g01(in[1], out[1]);
Not g00(in[0], out[0]);
endmodule
module And16(input[15:0] a, b, output[15:0] out);
And g15(a[15], b[15], out[15]);
And g14(a[14], b[14], out[14]);
And g13(a[13], b[13], out[13]);
And g12(a[12], b[12], out[12]);
And g11(a[11], b[11], out[11]);
And g10(a[10], b[10], out[10]);
And g09(a[9], b[9], out[9]);
And g08(a[8], b[8], out[8]);
And g07(a[7], b[7], out[7]);
And g06(a[6], b[6], out[6]);
And g05(a[5], b[5], out[5]);
And g04(a[4], b[4], out[4]);
And g03(a[3], b[3], out[3]);
And g02(a[2], b[2], out[2]);
And g01(a[1], b[1], out[1]);
And g00(a[0], b[0], out[0]);
endmodule
module Or16(input[15:0] a, b, output[15:0] out);
Or g15(a[15], b[15], out[15]);
Or g14(a[14], b[14], out[14]);
Or g13(a[13], b[13], out[13]);
Or g12(a[12], b[12], out[12]);
Or g11(a[11], b[11], out[11]);
Or g10(a[10], b[10], out[10]);
Or g09(a[9], b[9], out[9]);
Or g08(a[8], b[8], out[8]);
Or g07(a[7], b[7], out[7]);
Or g06(a[6], b[6], out[6]);
Or g05(a[5], b[5], out[5]);
Or g04(a[4], b[4], out[4]);
Or g03(a[3], b[3], out[3]);
Or g02(a[2], b[2], out[2]);
Or g01(a[1], b[1], out[1]);
Or g00(a[0], b[0], out[0]);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, a[15]; long long M[5][5]; long long s; long long check() { long long rs[5], cs[5]; memset(rs, 0, sizeof(rs)); memset(cs, 0, sizeof(cs)); long long d1 = 0, d2 = 0; for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= n; j++) { rs[i] += M[i][j]; cs[j] += M[i][j]; if (i == j) d1 += M[i][j]; if (i + j == n + 1) d2 += M[i][j]; } } set<long long> st; for (long long i = 1; i <= n; i++) st.insert(rs[i]), st.insert(cs[i]); st.insert(d1); st.insert(d2); if (st.size() == 1) { s = d1; return 1; } return 0; } int main() { cin >> n; for (long long i = 0; i < n * n; i++) cin >> a[i]; sort(a, a + n * n); do { memset(M, 0, sizeof(M)); long long j = 1, k = 1; for (long long i = 0, cnt = 1; i < n * n; i++, cnt++) { M[j][k] = a[i]; k++; if (cnt % n == 0) j++, k = 1; } if (check()) { cout << s << n ; for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= n; j++) cout << M[i][j] << ; cout << n ; } return 0; } } while (next_permutation(a, a + n * n)); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2OI_TB_V
`define SKY130_FD_SC_HD__A2BB2OI_TB_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a2bb2oi.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_hd__a2bb2oi dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2OI_TB_V
|
// dig
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
`include "cog.v" // cog logic and memory (8 instances)
`include "hub.v" // hub logic and memory
module dig
(
input nres, // reset input (active low)
output [7:0] cfg, // configuration output (set by clkset instruction)
input clk_cog, // cog clock input
input clk_pll, // pll simulator clock input (2x cog clock)
input [31:0] pin_in, // pin state inputs
output [31:0] pin_out, // pin state outputs
output [31:0] pin_dir, // pin direction outputs
output [7:0] cog_led // led outputs to show which cogs are active
);
// cnt
reg [31:0] cnt;
always @(posedge clk_cog)
if (nres)
cnt <= cnt + 1'b1;
// bus enable
reg ena_bus;
always @(posedge clk_cog or negedge nres)
if (!nres)
ena_bus <= 1'b0;
else
ena_bus <= !ena_bus;
// bus select
reg [7:0] bus_sel;
always @(posedge clk_cog or negedge nres)
if (!nres)
bus_sel <= 8'b0;
else if (ena_bus)
bus_sel <= {bus_sel[6:0], ~|bus_sel[6:0]};
// cogs
wire [7:0] bus_r;
wire [7:0] bus_e;
wire [7:0] bus_w;
wire [7:0] [1:0] bus_s;
wire [7:0] [15:0] bus_a;
wire [7:0] [31:0] bus_d;
wire [7:0] pll;
wire [7:0] [31:0] outx;
wire [7:0] [31:0] dirx;
genvar i;
generate
for (i=0; i<8; i++)
begin : coggen
cog cog_( .nres (nres),
.clk_cog (clk_cog),
.clk_pll (clk_pll),
.ena_bus (ena_bus),
.ptr_w (ptr_w[i]),
.ptr_d (ptr_d),
.ena (cog_ena[i]),
.bus_sel (bus_sel[i]),
.bus_r (bus_r[i]),
.bus_e (bus_e[i]),
.bus_w (bus_w[i]),
.bus_s (bus_s[i]),
.bus_a (bus_a[i]),
.bus_d (bus_d[i]),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack[i]),
.cnt (cnt),
.pll_in (pll),
.pll_out (pll[i]),
.pin_in (pin_in),
.pin_out (outx[i]),
.pin_dir (dirx[i]) );
end
endgenerate
// hub
wire hub_bus_r = |bus_r;
wire hub_bus_e = |bus_e;
wire hub_bus_w = |bus_w;
wire [1:0] hub_bus_s = bus_s[7] | bus_s[6] | bus_s[5] | bus_s[4] | bus_s[3] | bus_s[2] | bus_s[1] | bus_s[0];
wire [15:0] hub_bus_a = bus_a[7] | bus_a[6] | bus_a[5] | bus_a[4] | bus_a[3] | bus_a[2] | bus_a[1] | bus_a[0];
wire [31:0] hub_bus_d = bus_d[7] | bus_d[6] | bus_d[5] | bus_d[4] | bus_d[3] | bus_d[2] | bus_d[1] | bus_d[0];
wire [31:0] bus_q;
wire bus_c;
wire [7:0] bus_ack;
wire [7:0] cog_ena;
wire [7:0] ptr_w;
wire [27:0] ptr_d;
hub hub_ ( .clk_cog (clk_cog),
.ena_bus (ena_bus),
.nres (nres),
.bus_sel (bus_sel),
.bus_r (hub_bus_r),
.bus_e (hub_bus_e),
.bus_w (hub_bus_w),
.bus_s (hub_bus_s),
.bus_a (hub_bus_a),
.bus_d (hub_bus_d),
.bus_q (bus_q),
.bus_c (bus_c),
.bus_ack (bus_ack),
.cog_ena (cog_ena),
.ptr_w (ptr_w),
.ptr_d (ptr_d),
.cfg (cfg) );
// pins
assign pin_out = outx[7] | outx[6] | outx[5] | outx[4] | outx[3] | outx[2] | outx[1] | outx[0];
assign pin_dir = dirx[7] | dirx[6] | dirx[5] | dirx[4] | dirx[3] | dirx[2] | dirx[1] | dirx[0];
// cog leds
assign cog_led = cog_ena;
endmodule
|
`timescale 1ns / 1ps
module fake_tone(
input rst,
input clk,
input ym_p1,
output onebit
);
wire [15:0] tone, linear;
wire sh, so;
ramp_a_tone tonegen( .rst(rst), .clk(clk), .tone(tone) );
sh_encode encoder( .rst(rst), .ym_p1(ym_p1), .data(tone), .sh(sh), .so(so) );
ym_linearize linearizer( .rst(rst), .sh(sh), .ym_so(so), .ym_p1(ym_p1), .linear(linear) );
sigma_delta1 sd1( .rst(rst), .clk(clk), .data(linear), .sound(onebit) );
endmodule
module sh_encode(
input rst,
input ym_p1,
input [15:0] data,
output reg sh,
output so
);
reg [12:0] serial_data;
reg [3:0] cnt;
assign so = serial_data[0];
always @(posedge rst or posedge ym_p1) begin
if( rst ) begin
sh <= 1'b0;
cnt <= 0;
end
else begin
cnt <= cnt + 1'b1;
if( cnt==4'd2 ) begin
casex( data[15:10] )
6'b1XXXXX: serial_data <= { 3'd7, data[15:6]};
6'b01XXXX: serial_data <= { 3'd6, data[14:5]};
6'b001XXX: serial_data <= { 3'd5, data[13:4]};
6'b0001XX: serial_data <= { 3'd4, data[12:3]};
6'b00001X: serial_data <= { 3'd3, data[11:2]};
6'b000001: serial_data <= { 3'd2, data[10:1]};
default: serial_data <= { 3'd1, data[ 9:0]};
endcase
end
else serial_data <= serial_data>>1;
if( cnt==4'd10 ) sh<=1'b1;
if( cnt==4'd15 ) sh<=1'b0;
end
end
endmodule
// it produces a ~440Hz triangular signal at full scale for a 50MHz clock
module ramp_a_tone ( input rst, input clk, output reg [15:0] tone );
reg up;
always @(posedge rst or posedge clk) begin
if( rst ) begin
up <= 0;
tone <= 0;
end
else begin
if( tone == 16'hFFFE ) begin
up <= 1'b0;
end
else if( tone == 16'h1 ) begin
up <= 1'b1;
end
tone <= up ? (tone+1'b1) : (tone-1'b1);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[200010]; int main() { cin.tie(0); ios_base::sync_with_stdio(false); int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; int f = 0; for (int i = 1; i < n; i++) if (a[i] != a[i - 1]) { f = 1; break; } if (f == 0) { if (a[0] == 0) { cout << YES << endl; for (int i = 0; i < n; i++) cout << 1 << ; exit(0); } cout << NO << endl; exit(0); } long long mx = 0, mxer = 0; for (int i = 0; i < n; i++) if (a[i] > mx) mx = a[mxer = i]; while (true) { int x = mxer - 1; if (x < 0) x += n; if (a[x] == a[mxer]) mxer = x; else break; } int flag = 1; for (int i = 1; i < n; i++) { int x = mxer - 1; if (x < 0) x += n; if (flag && a[x] == 0) { a[x] += a[mxer]; flag = 0; } a[x] += a[mxer]; mxer = x; } cout << YES << endl; for (int i = 0; i < n; i++) cout << a[i] << ; return 0; } |
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a buffer that can be used the transfer streaming data from *
* one clock domain to another. *
* *
******************************************************************************/
module Computer_System_VGA_Subsystem_VGA_Pixel_FIFO (
// Inputs
clk_stream_in,
reset_stream_in,
clk_stream_out,
reset_stream_out,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bi-Directional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's data width
parameter EW = 0; // Frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk_stream_in;
input reset_stream_in;
input clk_stream_out;
input reset_stream_out;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bi-Directional
// Outputs
output stream_in_ready;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 6: 0] fifo_wr_used;
wire fifo_empty;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign stream_in_ready = ~(&(fifo_wr_used[6:4]));
assign stream_out_empty = 'h0;
assign stream_out_valid = ~fifo_empty;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
dcfifo Data_FIFO (
// Inputs
.wrclk (clk_stream_in),
.wrreq (stream_in_ready & stream_in_valid),
.data ({stream_in_data, stream_in_endofpacket, stream_in_startofpacket}),
.rdclk (clk_stream_out),
.rdreq (stream_out_ready & ~fifo_empty),
// Outputs
.wrusedw (fifo_wr_used),
.rdempty (fifo_empty),
.q ({stream_out_data, stream_out_endofpacket, stream_out_startofpacket})
// synopsys translate_off
,
.aclr (),
.wrfull (),
.wrempty (),
.rdfull (),
.rdusedw ()
// synopsys translate_on
);
defparam
Data_FIFO.intended_device_family = "Cyclone II",
Data_FIFO.lpm_hint = "MAXIMIZE_SPEED=7",
Data_FIFO.lpm_numwords = 128,
Data_FIFO.lpm_showahead = "ON",
Data_FIFO.lpm_type = "dcfifo",
Data_FIFO.lpm_width = DW + 3,
Data_FIFO.lpm_widthu = 7,
Data_FIFO.overflow_checking = "OFF",
Data_FIFO.rdsync_delaypipe = 5,
Data_FIFO.underflow_checking = "OFF",
Data_FIFO.use_eab = "ON",
Data_FIFO.wrsync_delaypipe = 5;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; const int MAX = 3e5 + 5; const long long MAX2 = 11; const long long MOD = 1000000007; const long long MOD2 = 1000005329; const long long INF = 2e18; const int dr[] = {1, 0, -1, 0, 1, 1, -1, -1, 0}; const int dc[] = {0, 1, 0, -1, 1, -1, 1, -1, 0}; const double pi = acos(-1); const double EPS = 1e-9; const int block = 555; int n; long long a, b, c, mx, ans, nw; string s[MAX]; int main() { cout << fixed << setprecision(10); ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (long long i = 1; i <= n; ++i) cin >> s[i]; for (char tgt = a ; tgt <= z ; ++tgt) { nw = 0; for (long long i = 1; i <= n; ++i) { a = b = c = mx = 0; reverse(s[i].begin(), s[i].end()); for (char j : s[i]) { if (j != tgt) break; ++a; } reverse(s[i].begin(), s[i].end()); for (char j : s[i]) { if (j != tgt) break; ++b; } for (char j : s[i]) { if (j != tgt) c = 0; else ++c, mx = max(c, mx); } if (mx == s[i].size()) nw = min(MOD, nw + (nw + 1) * mx); else nw = max(nw ? a + b + 1 : 0, mx); } ans = max(ans, nw); } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, co; int a[100019]; cin >> n >> co; int count = 0; for (int i = 0; i < n; i++) { cin >> a[i]; count += a[i] / 10; a[i] %= 10; } sort(a, a + n); reverse(a, a + n); for (int i = 0; i < n; i++) { if (co >= 10 - a[i]) { count++; co -= (10 - a[i]); } } cout << min(10 * n, count + co / 10) << endl; return 0; } |
#include<bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin>>t; while(t--) { int n; cin>>n; string a; cin>>a; if(a[0]== 2 &&a[1]== 0 &&a[2]== 2 &&a[3]== 0 ) cout<< YES << n ; else if(a[n-4]== 2 &&a[n-3]== 0 &&a[n-2]== 2 &&a[n-1]== 0 ) cout<< YES << n ; else if(a[0]== 2 &&a[1]== 0 &&a[2]== 2 &&a[n-1]== 0 ) cout<< YES << n ; else if(a[0]== 2 &&a[1]== 0 &&a[n-2]== 2 &&a[n-1]== 0 ) cout<< YES << n ; else if(a[0]== 2 &&a[n-3]== 0 &&a[n-2]== 2 &&a[n-1]== 0 ) cout<< YES << n ; else cout<< NO << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__DLCLKP_PP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLCLKP_PP_SYMBOL_V
|
// Copyright (C) 2017-2020 The Project X-Ray Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier: ISC
`default_nettype none
// ============================================================================
module idelay_calibrator #
(
parameter SITE_LOC = ""
)
(
input wire refclk, // REFCLK for IDELAYCTRL
input wire rst, // External reset
output wire rdy // Output ready signal
);
// ============================================================================
// Long reset generator (~60ns for Artix 7 according to the datasheet)
reg [6:0] r_cnt;
wire r_rst;
initial r_cnt <= 0;
always @(posedge refclk)
if (rst)
r_cnt <= 0;
else if (r_rst)
r_cnt <= r_cnt + 1;
assign r_rst = !r_cnt[6];
// ============================================================================
// IDELAYCTRL
(* KEEP, DONT_TOUCH, LOC = SITE_LOC *)
IDELAYCTRL idelayctlr
(
.REFCLK (refclk),
.RST (r_rst),
.RDY (rdy)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100; int n, x[maxn], y[maxn], r; void write(int x) { if (x <= 50) printf( %d , x); else { printf( (50+ ); write(x - 50); printf( ) ); } } void work() { for (int i = 1; i < n; i++) printf( ( ); for (int i = 1; i <= n; i++) { if (i > 1) printf( + ); printf( ( ); write(x[i]); printf( *((1-abs((t- ); write(i - 1); printf( )))+abs((abs((t- ); write(i - 1); printf( ))-1)))) ); if (i > 1) printf( ) ); } printf( n ); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d%d , x + i, y + i, &r); x[i] /= 2; y[i] /= 2; } work(); memcpy(x, y, sizeof(y)); work(); return 0; } |
`timescale 1ns / 1ps
//AND Gate
module andgate(a, b, out);
input a, b;
output out;
assign out = a & b;
endmodule
//Testbench definition for AND Gate
module andgate_tb;
wire t_out;
reg t_a, t_b;
andgate my_gate( .a(t_a), .b(t_b), .out(t_out) );
initial
begin
$monitor(t_a, t_b, t_out);
t_a = 1'b0;
t_b = 1'b0;
#5
t_a = 1'b0;
t_b = 1'b1;
#5
t_a = 1'b1;
t_b = 1'b0;
#5
t_a = 1'b1;
t_b = 1'b1;
end
endmodule
// AND Gate 16
module andgate16(a, b, out);
input [15:0] a, b;
output [15:0] out;
assign out = a & b;
endmodule
//Testbench definition for AND Gate
module andgate16_tb;
wire [15:0] t_out;
reg [15:0] t_a, t_b;
andgate16 my_gate( .a(t_a), .b(t_b), .out(t_out) );
initial
begin
$monitor(t_a, t_b, t_out);
t_a = 16'b0;
t_b = 16'b0;
#5
t_a = 16'b0;
t_b = 16'b1111111111111111;
#5
t_a = 16'b1111111111111111;
t_b = 16'b0;
#5
t_a = 16'b1111111111111111;
t_b = 16'b1111111111111111;
end
endmodule
// Mux8Way16
module mux8way16(a, b, c, d, e ,f, g, h, sel, out);
input [15:0] a, b, c, d, e, f, g, h;
input [2:0] sel;
output reg [15:0] out;
always @(sel)
begin
case (sel)
3'b000 : out = a;
3'b001 : out = b;
3'b010 : out = c;
3'b011 : out = d;
3'b100 : out = e;
3'b101 : out = f;
3'b110 : out = g;
3'b111 : out = h;
default out = 3'b000;
endcase
end
endmodule
//Testbench definition for Mux8Way16
module mux8way16_tb;
wire [15:0] t_out;
reg [15:0] t_a, t_b, t_c, t_d, t_e, t_f, t_g, t_h;
reg [2:0] t_sel;
mux8way16 my_gate( .a(t_a), .b(t_b), .c(t_c), .d(t_d), .e(t_e), .f(t_f), .g(t_g), .h(t_h), .sel(t_sel), .out(t_out) );
initial
begin
$monitor(t_a, t_b, t_c, t_d, t_e, t_f, t_g, t_h, t_out);
t_a = 16'b0000000000000000;
t_b = 16'b0000000000000011;
t_c = 16'b0000000000001100;
t_d = 16'b0000000000110000;
t_e = 16'b0000000011000000;
t_f = 16'b0000001100000000;
t_g = 16'b0000110000000000;
t_h = 16'b0011000000000000;
t_sel = 3'b000;
#5
t_sel = 3'b000;
#5
t_sel = 3'b001;
#5
t_sel = 3'b010;
#5
t_sel = 3'b011;
#5
t_sel = 3'b010;
#5
t_sel = 3'b011;
#5
t_sel = 3'b100;
#5
t_sel = 3'b101;
#5
t_sel = 3'b111;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[505]; long long mod = 998244353; long long dp[505][505]; long long get_ans(long long l, long long r) { if (dp[l][r]) return dp[l][r]; if (l >= r) return 1; long long pl = l, _min = 1e9; for (long long i = l; i <= r; i++) { if (a[i] < _min) { _min = a[i]; pl = i; } } long long Ans1 = 0, Ans2 = 0; for (long long i = pl; i >= l; i--) { Ans1 = (Ans1 + get_ans(l, i - 1) * get_ans(i, pl - 1) % mod) % mod; } for (long long j = pl; j <= r; j++) { Ans2 = (Ans2 + get_ans(pl + 1, j) % mod * get_ans(j + 1, r) % mod) % mod; } return dp[l][r] = (Ans1 * Ans2) % mod; } signed main() { long long n, m; scanf( %lld %lld , &n, &m); for (long long i = 1; i <= m; i++) scanf( %lld , &a[i]); printf( %lld , get_ans(1, n)); return 0; } |
#include <bits/stdc++.h> using namespace std; long i, j, m, n, p, q, r, s, a, b; string aa, bb; int main() { cin >> n; scanf( %ld:%ld , &a, &b); if (n == 12) { if (a == 0) aa = 01 ; else if (a >= 13) { p = a % 10; if (p == 0) { aa = 10 ; } else aa += 0 , aa += (a % 10 + 48); } else { p = a % 10; a /= 10; q = a % 10; aa += (q + 48), aa += (p + 48); } if (b == 60) bb = 00 ; else if (b > 60) { bb += 0 , bb += (b % 10 + 48); } else { p = b % 10; b /= 10; q = b % 10; bb += (q + 48), bb += (p + 48); } cout << aa << : << bb; } else { if (a >= 24) { aa += 0 , aa += (a % 10 + 48); } else { p = a % 10; a /= 10; q = a % 10; aa += (q + 48), aa += (p + 48); } if (b == 60) bb = 00 ; else if (b > 60) { bb += 0 , bb += (b % 10 + 48); } else { p = b % 10; b /= 10; q = b % 10; bb += (q + 48), bb += (p + 48); } cout << aa << : << bb; } } |
#include <bits/stdc++.h> const int N = 1e6 + 5, P = 1e9 + 9; inline int ksm(int a, int b) { int r = 1; for (; b; b >>= 1, a = (long long)a * a % P) if (b & 1) r = (long long)r * a % P; return r; } int n, q, a[N], t[N], f[N], F[N]; struct mat { int s[2][2]; inline friend mat operator+(mat a, mat b) { return a.s[0][0] = (a.s[0][0] + b.s[0][0]) % P, a.s[0][1] = (a.s[0][1] + b.s[0][1]) % P, a.s[1][0] = (a.s[1][0] + b.s[1][0]) % P, a.s[1][1] = (a.s[1][1] + b.s[1][1]) % P, a; } inline friend mat operator*(mat a, mat b) { mat c; c.s[0][0] = ((long long)a.s[0][0] * b.s[0][0] + (long long)a.s[0][1] * b.s[1][0]) % P, c.s[0][1] = ((long long)a.s[0][0] * b.s[0][1] + (long long)a.s[0][1] * b.s[1][1]) % P, c.s[1][0] = ((long long)a.s[1][0] * b.s[0][0] + (long long)a.s[1][1] * b.s[1][0]) % P, c.s[1][1] = ((long long)a.s[1][0] * b.s[0][1] + (long long)a.s[1][1] * b.s[1][1]) % P; return c; } inline friend bool operator!=(mat a, mat b) { return a.s[0][0] != b.s[0][0] || a.s[0][1] != b.s[0][1] || a.s[1][0] != b.s[1][0] || a.s[1][1] != b.s[1][1]; } inline bool INV(mat &b) { long long x = (long long)s[0][0] * s[1][1] - (long long)s[0][1] * s[1][0]; if (!x) return 0; if (x > 0) x = ksm(x % P, P - 2), b.s[0][0] = (long long)x * s[1][1] % P, b.s[1][1] = x * s[0][0] % P, b.s[0][1] = x * (P - s[0][1]) % P, b.s[1][0] = x * (P - s[1][0]) % P; else x = ksm((-x) % P, P - 2), b.s[0][0] = (long long)x * (P - s[1][1]) % P, b.s[1][1] = x * (P - s[0][0]) % P, b.s[0][1] = x * s[0][1] % P, b.s[1][0] = x * s[1][0] % P; return 1; } } E, Z, O, lz[N]; inline mat ksm(mat a, int b) { mat r = E; for (; b; b >>= 1, a = a * a) if (b & 1) r = r * a; return r; } inline int sum(int l, int r, mat v) { return ((long long)(F[r] - F[l - 1] + P) * v.s[1][1] + (long long)(F[r + 1] - F[l] + P) * v.s[1][0]) % P; } inline void tg(int p, int l, int r, mat v) { lz[p] = lz[p] + v, t[p] = (t[p] + sum(l, r, v)) % P; } inline void pushdown(int p, int l, int r, int mid) { if (lz[p] != O) tg(p << 1, l, mid, lz[p]), tg(p << 1 | 1, mid + 1, r, lz[p]), lz[p] = O; } inline void build(int p, int l, int r) { if (l == r) { t[p] = a[l]; return; } int mid = l + r >> 1; build(p << 1, l, mid), build(p << 1 | 1, mid + 1, r), t[p] = (t[p << 1] + t[p << 1 | 1]) % P; } inline void add(int p, int l, int r, int x, int y, mat v) { if (l >= x && r <= y) return tg(p, l, r, v); int mid = l + r >> 1; pushdown(p, l, r, mid); if (x <= mid) add(p << 1, l, mid, x, y, v); if (y > mid) add(p << 1 | 1, mid + 1, r, x, y, v); t[p] = (t[p << 1] + t[p << 1 | 1]) % P; } inline int query(int p, int l, int r, int x, int y) { if (l >= x && r <= y) return t[p]; int mid = l + r >> 1, res = 0; pushdown(p, l, r, mid); if (x <= mid) res = (res + query(p << 1, l, mid, x, y)) % P; if (y > mid) res = (res + query(p << 1 | 1, mid + 1, r, x, y)) % P; return res; } int main() { scanf( %d%d , &n, &q); int i, l, r, v; mat x, y; for (i = 1; i <= n; i++) scanf( %d , a + i); build(1, 1, n); for (f[1] = f[2] = 1, i = 3; i < N; i++) f[i] = (f[i - 1] + f[i - 2]) % P; for (i = 1; i < N; i++) F[i] = (F[i - 1] + f[i]) % P; E.s[0][0] = E.s[1][1] = Z.s[0][0] = Z.s[0][1] = Z.s[1][0] = 1; while (q--) if (scanf( %d%d%d , &i, &l, &r), i > 1) printf( %d n , query(1, 1, n, l, r)); else x = ksm(Z, l - 1), x.INV(y) && (add(1, 1, n, l, r, y), 0); return 0; } |
#include <bits/stdc++.h> using namespace std; unsigned long long n, H; unsigned long long bound[60]; unsigned long long cnt(unsigned long long p, unsigned long long h, unsigned long long n) { if (h == 1) { if (p == 0 && n == 1) return 1; if (p == 1 && n == 2) return 1; return 2; } unsigned long long res = 1; if (n > bound[h - 1] && p == 0 || n <= bound[h - 1] && p == 1) res += 2 * bound[h - 1] - 1; if (n > bound[h - 1]) res += cnt(0, h - 1, n - bound[h - 1]); else res += cnt(1, h - 1, n); return res; } int main() { cin >> H >> n; bound[0] = 1; for (unsigned long long i = 0; i < H; ++i) bound[i + 1] = 2 * bound[i]; cout << cnt(0, H, n); return 0; } |
//-----------------------------------------------------------------------------
// ISO14443-A support for the Proxmark III
// Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
// constants for the different modes:
`define MASTER 3'b000
`define SLAVE 3'b001
`define DELAY 3'b010
module relay_test(
pck0, ck_1356meg, ck_1356megb,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
data_in, data_out,
mod_type
);
input pck0, ck_1356meg, ck_1356megb;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input data_in;
output data_out;
input [2:0] mod_type;
reg ssp_clk = 1'b0;
reg ssp_frame = 1'b0;
reg data_out = 1'b0;
reg ssp_din = 1'b0;
reg [6:0] div_counter = 7'b0;
reg [0:0] buf_data_in = 1'b0;
reg [0:0] receive_counter = 1'b0;
reg [31:0] delay_counter = 32'h0;
reg [3:0] counter = 4'b0;
reg [7:0] receive_buffer = 8'b0;
reg sending_started = 1'b0;
reg received_complete = 1'b0;
reg [7:0] received = 8'b0;
reg [3:0] send_buf = 4'b0;
reg [16:0] to_arm_delay = 17'b0;
always @(posedge ck_1356meg)
begin
/*div_counter <= div_counter + 1;
buf_data_in = data_in;
if (div_counter[3:0] == 4'b1000) ssp_clk <= 1'b0;
if (div_counter[3:0] == 4'b0000) ssp_clk <= 1'b1;
if (sending_started == 1'b1 && received_complete == 1'b0) begin
delay_counter = delay_counter + 1;
end
if (div_counter[2:0] == 3'b100) // 1.695MHz
begin
if (mod_type == `MASTER) // Sending from ARM to other Proxmark
begin
receive_counter <= receive_counter + 1;
if (div_counter[6:4] == 3'b000) ssp_frame = 1'b1;
else ssp_frame = 1'b0;
if (receive_counter[0] == 1'b0) begin
data_out = ssp_dout;
send_buf = {send_buf[2:0], ssp_dout};
receive_buffer = {receive_buffer[6:0], buf_data_in};
if (send_buf == 4'ha && sending_started == 1'b0) begin
delay_counter = 32'b0;
sending_started = 1'b1;
end
if (receive_buffer[3:0] == 4'ha && sending_started == 1'b1) begin
receive_buffer = 8'b0;
received_complete = 1'b1;
end
end
counter <= 4'b0;
end
else if (mod_type == `SLAVE) // Sending from other Proxmark to ARM
begin
counter <= counter + 1;
if (counter[0] == 1'b0) begin
receive_buffer = {receive_buffer[6:0], buf_data_in};
data_out = buf_data_in;
ssp_frame = (receive_buffer[7:4] == 4'b1111);
if (receive_buffer[7:4] == 4'b1111) begin
received = receive_buffer;
receive_buffer = 8'b0;
end
ssp_din <= received[7];
received = {received[6:0], 1'b0};
end
receive_counter <= 4'b0;
end
else if (mod_type == `DELAY) // Sending delay to ARM
begin
if (to_arm_delay[16] == 1'b1) begin
sending_started = 1'b0;
received_complete = 1'b0;
counter <= counter + 1;
if (counter[0] == 1'b0) begin
ssp_frame = (counter[3:0] == 4'b0000);
ssp_din <= delay_counter[31];
delay_counter = {delay_counter[30:0], 1'b0};
end
if (counter[3:0] == 4'b1111) begin
to_arm_delay <= 17'b0;
end
end
else begin
to_arm_delay <= to_arm_delay + 1;
end
end
end*/
end
endmodule |
module system (
clk_50_clk,
kernel_clk_clk,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
peripheral_hps_io_emac1_inst_TX_CLK,
peripheral_hps_io_emac1_inst_TXD0,
peripheral_hps_io_emac1_inst_TXD1,
peripheral_hps_io_emac1_inst_TXD2,
peripheral_hps_io_emac1_inst_TXD3,
peripheral_hps_io_emac1_inst_RXD0,
peripheral_hps_io_emac1_inst_MDIO,
peripheral_hps_io_emac1_inst_MDC,
peripheral_hps_io_emac1_inst_RX_CTL,
peripheral_hps_io_emac1_inst_TX_CTL,
peripheral_hps_io_emac1_inst_RX_CLK,
peripheral_hps_io_emac1_inst_RXD1,
peripheral_hps_io_emac1_inst_RXD2,
peripheral_hps_io_emac1_inst_RXD3,
peripheral_hps_io_sdio_inst_CMD,
peripheral_hps_io_sdio_inst_D0,
peripheral_hps_io_sdio_inst_D1,
peripheral_hps_io_sdio_inst_CLK,
peripheral_hps_io_sdio_inst_D2,
peripheral_hps_io_sdio_inst_D3,
peripheral_hps_io_usb1_inst_D0,
peripheral_hps_io_usb1_inst_D1,
peripheral_hps_io_usb1_inst_D2,
peripheral_hps_io_usb1_inst_D3,
peripheral_hps_io_usb1_inst_D4,
peripheral_hps_io_usb1_inst_D5,
peripheral_hps_io_usb1_inst_D6,
peripheral_hps_io_usb1_inst_D7,
peripheral_hps_io_usb1_inst_CLK,
peripheral_hps_io_usb1_inst_STP,
peripheral_hps_io_usb1_inst_DIR,
peripheral_hps_io_usb1_inst_NXT,
peripheral_hps_io_uart0_inst_RX,
peripheral_hps_io_uart0_inst_TX,
peripheral_hps_io_i2c1_inst_SDA,
peripheral_hps_io_i2c1_inst_SCL,
peripheral_hps_io_gpio_inst_GPIO53,
reset_50_reset_n,
acl_iface_clock_130_clk,
acl_iface_alt_vip_itc_0_clocked_video_vid_clk,
acl_iface_alt_vip_itc_0_clocked_video_vid_data,
acl_iface_alt_vip_itc_0_clocked_video_underflow,
acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid,
acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync,
acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync,
acl_iface_alt_vip_itc_0_clocked_video_vid_f,
acl_iface_alt_vip_itc_0_clocked_video_vid_h,
acl_iface_alt_vip_itc_0_clocked_video_vid_v);
input clk_50_clk;
output kernel_clk_clk;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
output peripheral_hps_io_emac1_inst_TX_CLK;
output peripheral_hps_io_emac1_inst_TXD0;
output peripheral_hps_io_emac1_inst_TXD1;
output peripheral_hps_io_emac1_inst_TXD2;
output peripheral_hps_io_emac1_inst_TXD3;
input peripheral_hps_io_emac1_inst_RXD0;
inout peripheral_hps_io_emac1_inst_MDIO;
output peripheral_hps_io_emac1_inst_MDC;
input peripheral_hps_io_emac1_inst_RX_CTL;
output peripheral_hps_io_emac1_inst_TX_CTL;
input peripheral_hps_io_emac1_inst_RX_CLK;
input peripheral_hps_io_emac1_inst_RXD1;
input peripheral_hps_io_emac1_inst_RXD2;
input peripheral_hps_io_emac1_inst_RXD3;
inout peripheral_hps_io_sdio_inst_CMD;
inout peripheral_hps_io_sdio_inst_D0;
inout peripheral_hps_io_sdio_inst_D1;
output peripheral_hps_io_sdio_inst_CLK;
inout peripheral_hps_io_sdio_inst_D2;
inout peripheral_hps_io_sdio_inst_D3;
inout peripheral_hps_io_usb1_inst_D0;
inout peripheral_hps_io_usb1_inst_D1;
inout peripheral_hps_io_usb1_inst_D2;
inout peripheral_hps_io_usb1_inst_D3;
inout peripheral_hps_io_usb1_inst_D4;
inout peripheral_hps_io_usb1_inst_D5;
inout peripheral_hps_io_usb1_inst_D6;
inout peripheral_hps_io_usb1_inst_D7;
input peripheral_hps_io_usb1_inst_CLK;
output peripheral_hps_io_usb1_inst_STP;
input peripheral_hps_io_usb1_inst_DIR;
input peripheral_hps_io_usb1_inst_NXT;
input peripheral_hps_io_uart0_inst_RX;
output peripheral_hps_io_uart0_inst_TX;
inout peripheral_hps_io_i2c1_inst_SDA;
inout peripheral_hps_io_i2c1_inst_SCL;
inout peripheral_hps_io_gpio_inst_GPIO53;
input reset_50_reset_n;
input acl_iface_clock_130_clk;
input acl_iface_alt_vip_itc_0_clocked_video_vid_clk;
output [31:0] acl_iface_alt_vip_itc_0_clocked_video_vid_data;
output acl_iface_alt_vip_itc_0_clocked_video_underflow;
output acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid;
output acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync;
output acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync;
output acl_iface_alt_vip_itc_0_clocked_video_vid_f;
output acl_iface_alt_vip_itc_0_clocked_video_vid_h;
output acl_iface_alt_vip_itc_0_clocked_video_vid_v;
endmodule
|
module timer #
(
parameter WIDTH = 64,
parameter USE_2XCLK = 0,
parameter S_WIDTH_A = 2
)
(
input clk,
input clk2x,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH-1:0] slave_writedata,
input slave_read,
input slave_write,
input [WIDTH/8-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH-1:0] slave_readdata,
output slave_readdatavalid
);
reg [WIDTH-1:0] counter;
reg [WIDTH-1:0] counter2x;
reg clock_sel;
always@(posedge clk or negedge resetn)
if (!resetn)
clock_sel <= 1'b0;
else if (slave_write)
if (|slave_writedata)
clock_sel <= 1'b1;
else
clock_sel <= 1'b0;
always@(posedge clk or negedge resetn)
if (!resetn)
counter <= {WIDTH{1'b0}};
else if (slave_write)
counter <= {WIDTH{1'b0}};
else
counter <= counter + 2'b01;
always@(posedge clk2x or negedge resetn)
if (!resetn)
counter2x <= {WIDTH{1'b0}};
else if (slave_write)
counter2x <= {WIDTH{1'b0}};
else
counter2x <= counter2x + 2'b01;
assign slave_waitrequest = 1'b0;
assign slave_readdata = (USE_2XCLK && clock_sel) ? counter2x : counter;
assign slave_readdatavalid = slave_read;
endmodule
|
`define WIDTH_P 2
/**************************** TEST RATIONALE *******************************
1. STATE SPACE
Number of possible values for a thermometer code input of WIDTH_P is
WIDTH_P+1. Hence it is feasible to exhaustively test the DUT. This test
module generates thermometer codes as input to the DUT starting with
00...0. After every cycle this input is multiplied by 2 and incremented
by 1 and thus generating a sequence of thermometer codes. Since after
every cycle the value of the thermometer code increases by 1, a counter
can be initiated and it's count value can be used to validate the
correctness of the output of the DUT.
2. PARAMETERIZATION
The parameter WIDTH_P determines the behavior of the function in a
significant way, because each of WIDTH_P = 1, 2, 3, 4 and WIDTH_P>4 are
handled differently. So a minimal set of tests might be WIDTH_P=1,2,3,4,5.
However, since there are relatively few cases for each WIDTH_P, an
alternative approach is to test WIDTH_P=1..512, which gives us brute
force assurance.
***************************************************************************/
module test_bsg
#(
parameter cycle_time_p = 20,
parameter width_p = `WIDTH_P,
parameter reset_cycles_lo_p=1,
parameter reset_cycles_hi_p=5
);
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(1)
, .reset_cycles_hi_p(5)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display("\n\n\n");
$display("===========================================================");
$display("testing with ...");
$display("WIDTH_P: %d\n", width_p);
end
logic [width_p-1:0] test_input; // input therm code
wire [$clog2(width_p+1)-1:0] test_output; // value of input therm code
// (output of DUT)
logic [$clog2(width_p+1):0] count; // number of clock cycles after reset
logic finish_r;
bsg_cycle_counter #( .width_p($clog2(width_p+1)+1)
) bcc
( .clk_i (clk)
, .reset_i(reset)
, .ctr_r_o(count)
);
// no. of set bits in input therm code
// increases by one after every clock cycle
// cycle 1: test_input = 000, count = 1
// cycle 2: (000) << 1 + 1 = 001, 2
// cycle 3: (001) << 1 + 1 = 011, 3
// cycle 3: (011) << 1 + 1 = 111, 4
assign test_input = width_p'((1 << count) - 1);
always_ff @(posedge clk)
begin
if(reset)
finish_r <= 1'b0;
else
begin
if(&test_input) // finish with 11..1
finish_r <= 1'b1;
if(finish_r)
begin
$display("========================================================\n");
$finish;
end
end
end
always_ff @(posedge clk)
begin
/*$display("test_input: %b, count: %b, test_output: %b"
, test_input, count, test_output);*/
if(!reset)
assert(count == test_output)
else $error("mismatch on input %x;, expected output: %x;, test_output: %x"
, test_input, count, test_output);
end
bsg_thermometer_count #( .width_p(width_p)
) DUT
( .i(test_input)
, .o(test_output)
);
endmodule
|
module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter [63:0] INIT = 64'bx;
parameter CLKPOL2 = 1;
input CLK1;
input [5:0] A1ADDR;
output A1DATA;
input [5:0] B1ADDR;
input B1DATA;
input B1EN;
RAM64X1D #(
.INIT(INIT),
.IS_WCLK_INVERTED(!CLKPOL2)
) _TECHMAP_REPLACE_ (
.DPRA0(A1ADDR[0]),
.DPRA1(A1ADDR[1]),
.DPRA2(A1ADDR[2]),
.DPRA3(A1ADDR[3]),
.DPRA4(A1ADDR[4]),
.DPRA5(A1ADDR[5]),
.DPO(A1DATA),
.A0(B1ADDR[0]),
.A1(B1ADDR[1]),
.A2(B1ADDR[2]),
.A3(B1ADDR[3]),
.A4(B1ADDR[4]),
.A5(B1ADDR[5]),
.D(B1DATA),
.WCLK(CLK1),
.WE(B1EN)
);
endmodule
module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter [127:0] INIT = 128'bx;
parameter CLKPOL2 = 1;
input CLK1;
input [6:0] A1ADDR;
output A1DATA;
input [6:0] B1ADDR;
input B1DATA;
input B1EN;
RAM128X1D #(
.INIT(INIT),
.IS_WCLK_INVERTED(!CLKPOL2)
) _TECHMAP_REPLACE_ (
.DPRA(A1ADDR),
.DPO(A1DATA),
.A(B1ADDR),
.D(B1DATA),
.WCLK(CLK1),
.WE(B1EN)
);
endmodule
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