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#include <bits/stdc++.h> using namespace std; const long double eps = 1e-9; const long double pi = acos(-1.0); const long long inf = 1e+9; #pragma comment(linker, /STACK:36777216 ) template <typename T> istream &operator>>(istream &, vector<T> &); template <typename T> ostream &operator<<(ostream &, const vector<T> &); long long s, x; int bit(long long x, int pos) { return (x & (1LL << pos)) > 0; } void solve() { cin >> s >> x; int l = 45; while (bit(s, l) == 0) l--; vector<vector<long long> > dp(l + 2, vector<long long>(2, 0)); dp[0][0] = 1; for (int i = 1; i <= l + 1; i++) { int bs = bit(s, i - 1); int bx = bit(x, i - 1); if (bs == 0) { if (bx == 0) { dp[i][0] = dp[i - 1][0]; dp[i][1] = dp[i - 1][0]; } else { dp[i][1] += 2 * dp[i - 1][1]; } } else { if (bx == 0) { dp[i][0] = dp[i - 1][1]; dp[i][1] = dp[i - 1][1]; } else { dp[i][0] += 2 * dp[i - 1][0]; } } } long long ans = dp[l + 1][0]; if (x > s) ans = 0; if (x == 0) { if (s % 2 == 0) ans = 1; else ans = 0; } if (x == s) ans -= 2; cout << ans << endl; } int main() { solve(); return 0; } template <typename T> istream &operator>>(istream &is, vector<T> &v) { for (int i = 0; i < v.size(); ++i) is >> v[i]; return is; } template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { for (int i = 0; i < v.size(); ++i) os << v[i]; return os; } |
// custom_math.v
// This file was auto-generated as a prototype implementation of a module
// created in component editor. It ties off all outputs to ground and
// ignores all inputs. It needs to be edited to make it do something
// useful.
//
// This file will not be automatically regenerated. You should check it in
// to your version control system if you want to keep it.
`timescale 1 ps / 1 ps
module custom_math (
input wire [7:0] avs_s0_address, // avs_s0.address
input wire avs_s0_read, // .read
output wire [31:0] avs_s0_readdata, // .readdata
input wire avs_s0_write, // .write
input wire [31:0] avs_s0_writedata, // .writedata
output wire avs_s0_waitrequest, // .waitrequest
input wire clock_clk, // clock.clk
input wire reset_reset, // reset.reset
output wire ins_irq0_irq, // ins_irq0.irq
output wire [7:0] avm_m0_address, // avm_m0.address
output wire avm_m0_read, // .read
input wire avm_m0_waitrequest, // .waitrequest
input wire [31:0] avm_m0_readdata, // .readdata
output wire avm_m0_write, // .write
output wire [31:0] avm_m0_writedata // .writedata
);
// TODO: Auto-generated HDL template
assign avs_s0_readdata = 32'b00000000000000000000000000000000;
assign avs_s0_waitrequest = 1'b0;
assign ins_irq0_irq = 1'b0;
assign avm_m0_address = 8'b00000000;
assign avm_m0_read = 1'b0;
assign avm_m0_write = 1'b0;
assign avm_m0_writedata = 32'b00000000000000000000000000000000;
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* message_disable = "14320" *) module alt_mem_ddrx_buffer
# (
// module parameter port list
parameter
ADDR_WIDTH = 3,
DATA_WIDTH = 8,
REGISTER_OUTPUT = 0
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
write_valid,
write_address,
write_data,
// read interface
read_valid,
read_address,
read_data
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam BUFFER_DEPTH = two_pow_N(ADDR_WIDTH);
localparam BUFFER_REGISTER_OUTPUT = (REGISTER_OUTPUT) ? "CLOCK0" : "UNREGISTERED";
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
input write_valid;
input [ADDR_WIDTH-1:0] write_address;
input [DATA_WIDTH-1:0] write_data;
// read interface
input read_valid;
input [ADDR_WIDTH-1:0] read_address;
output [DATA_WIDTH-1:0] read_data;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
wire write_valid;
wire [ADDR_WIDTH-1:0] write_address;
wire [DATA_WIDTH-1:0] write_data;
// read interface
wire read_valid;
wire [ADDR_WIDTH-1:0] read_address;
wire [DATA_WIDTH-1:0] read_data;
// -----------------------------
// module definition
// -----------------------------
altsyncram altsyncram_component
(
.wren_a (write_valid),
.clock0 (ctl_clk),
.address_a (write_address),
.address_b (read_address),
.data_a (write_data),
.q_b (read_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATA_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.intended_device_family = "Stratix",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = BUFFER_DEPTH,
altsyncram_component.numwords_b = BUFFER_DEPTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = BUFFER_REGISTER_OUTPUT,
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.wrcontrol_aclr_a = "NONE";
// alt_ddrx_ram_2port
// ram_inst
// (
// .clock (ctl_clk),
// .wren (write_valid),
// .wraddress (write_address),
// .data (write_data),
// .rdaddress (read_address),
// .q (read_data)
// );
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
|
`timescale 1ns/1ns
`define NOP w_ctrl = 3'd0
`define WRITE w_ctrl = 3'd1
`define EOF_WITH_WRITE w_ctrl = 3'd2
`define EOF_WITHOUT_WRITE w_ctrl = 3'd3
`define HEAD w_ctrl = 3'd4
`define FINAL_HEAD w_ctrl = 3'd5
`define DISCARD w_ctrl = 3'd6
module testbench;
parameter ADDRWIDTH = 4;
wire w_error, r_error;
reg rst_n = 1'b0;
reg w_clk = 1'b0;
reg r_clk = 1'b0;
reg [2:0] w_ctrl = 3'b0;
reg r_en = 1'b0;
wire w_full;
wire r_valid;
wire [ADDRWIDTH:0] r_counter;
wire [ADDRWIDTH:0] w_counter;
wire [7:0] dout;
reg [7:0] din = 8'd0, expected = 8'd0;
//
`include `PATTERN
always #5 w_clk = !w_clk;
always #3 r_clk = !r_clk;
initial begin
$dumpfile("fifo.dump");
$dumpvars(0,testbench);
end
initial begin
$display("\n Time : w_full (r_valid, dout) (w_counter, r_counter) (r_addr, rbin2) - (rptr-b, rptr-d)");
forever @(posedge r_clk) begin
$display("%6.0f : %b (%b %h) (%2d %2d) (%2d %2d) - %b %d", $time,
w_full, r_valid, dout, w_counter, r_counter, dut.r_ram_addr,
dut.fifo_controller_inst.read_inst.rbin2,
dut.fifo_controller_inst.read_inst.rptr, dut.fifo_controller_inst.read_inst.rptr);
if (r_valid && (expected != dout) ) begin
$display("data mismatched at time %6.3f : dout = %h, expected = %h", $time, dout, expected);
expected = dout;
end
if (r_valid && r_en)
expected = expected + 1'b1;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// bug789 generates
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=1;
ifc #(1) itopa();
ifc #(2) itopb();
sub #(1) ca (.isub(itopa),
.i_value(4));
sub #(2) cb (.isub(itopb),
.i_value(5));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==1) begin
if (itopa.MODE != 1) $stop;
if (itopb.MODE != 2) $stop;
end
if (cyc==20) begin
if (itopa.i != 4) $stop;
if (itopb.i != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub
#(parameter MODE = 0)
(
ifc isub,
input integer i_value
);
// Commercial unsupported Xmrs into scopes within interfaces
generate
always_comb isub.i = i_value;
endgenerate
endmodule
interface ifc;
parameter MODE = 0;
// Commercial unsupported Xmrs into scopes within interfaces
generate
integer i;
endgenerate
endinterface
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 15:32:52 -0400 (Wed, 18 May 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Single-Ported BRAM
module BRAM1(CLK,
EN,
WE,
ADDR,
DI,
DO
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLK;
input EN;
input WE;
input [ADDR_WIDTH-1:0] ADDR;
input [DATA_WIDTH-1:0] DI;
output [DATA_WIDTH-1:0] DO;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1];
reg [ADDR_WIDTH-1:0] ADDR_R;
reg [DATA_WIDTH-1:0] DO_R;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
ADDR_R = { ((ADDR_WIDTH+1)/2) { 2'b10 } };
DO_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLK) begin
if (EN) begin
if (WE)
RAM[ADDR] <= `BSV_ASSIGNMENT_DELAY DI;
ADDR_R <= `BSV_ASSIGNMENT_DELAY ADDR;
end
DO_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDR_R];
end
assign DO = (PIPELINED) ? DO_R : RAM[ADDR_R];
endmodule // BRAM1
|
#include <bits/stdc++.h> using namespace std; int a[11], n; long long dp[11][111], c[111][111]; int main() { memset(c, 0, sizeof(c)); for (int i = (0); i < (111); i++) c[i][0] = 1; for (int i = (1); i < (111); i++) for (int j = (1); j <= (i); j++) c[i][j] = (c[i - 1][j - 1] + c[i - 1][j]) % 1000000007LL; cin >> n; for (int i = (0); i < (10); i++) cin >> a[i]; memset(dp, 0, sizeof(dp)); int len = 0; for (int i = a[1]; i <= n; i++) dp[1][i] = 1; len = a[1]; for (int i = (2); i < (10); i++) { for (int l = len + a[i]; l <= n; l++) { for (int j = a[i]; j <= l - len; j++) { dp[i][l] += dp[i - 1][l - j] * c[l][j] % 1000000007LL; dp[i][l] %= 1000000007LL; } } len += a[i]; } long long ans = 0; for (int l = a[0] + len; l <= n; l++) { if (l == 0) continue; for (int i = a[0]; i <= l - len; i++) { int k = l - i; ans += dp[9][k] * c[l - 1][i] % 1000000007LL; ans %= 1000000007LL; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main(int argc, const char* argv[]) { int cases; cin >> cases; while (cases--) { int num; scanf( %d , &num); vector<pair<int, int> > coords; pair<int, int> z(0, 0); coords.push_back(z); for (int i = 0; i < num; ++i) { int x, y; scanf( %d%d , &x, &y); coords.push_back({x, y}); } sort(coords.begin(), coords.end()); string out; bool ok = true; for (int i = 1; i <= num; ++i) { int diffx = coords[i].first - coords[i - 1].first; int diffy = coords[i].second - coords[i - 1].second; if (diffx < 0 || diffy < 0) { ok = false; break; } while (diffx--) out += R ; while (diffy--) out += U ; } if (ok) { cout << YES << endl; cout << out << endl; } else { cout << NO << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long INF = 1e9 + 9; const long long N = 500500; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); long long T; cin >> T; while (T--) { long long n, k; cin >> n >> k; string s, t; cin >> s; vector<pair<long long, long long> > ans; for (long long i = 1; i <= k - 1; i++) { t += () ; } for (long long i = 1; i <= (n - (2 * k) + 2) / 2; i++) { t += ( ; } for (long long i = 1; i <= (n - (2 * k) + 2) / 2; i++) { t += ) ; } for (long long i = 0; i < n; i++) { if (s[i] == t[i]) continue; for (long long j = i + 1; j < n; j++) { if (s[j] == t[i]) { ans.push_back({i + 1, j + 1}); reverse(s.begin() + i, s.begin() + j + 1); break; } } } cout << ans.size() << n ; for (auto z : ans) { cout << z.first << << z.second << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<vector<int> > a(n, vector<int>(n)); int sum = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { scanf( %d , &a[i][j]); if (i == j) sum += a[i][j]; } } sum &= 1; int q; scanf( %d , &q); const char *cc = 01 ; while (q--) { int t; scanf( %d , &t); if (t == 3) { printf( %c , cc[sum]); } else { scanf( %d , &t); sum ^= 1; } } return 0; } |
#include <bits/stdc++.h> using namespace std; string str; long long int n, k; int main() { string temp; ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int a, b, i, j, cnt = 0; cin >> str; n = str.size(); cin >> k; for (i = 0; i < k; i++) { cin >> temp; for (j = 0; j < n; j++) { a = 0, b = 0; while (j < n && (str[j] == temp[0] || str[j] == temp[1])) { if (str[j] == temp[0]) a++; else b++; j++; } cnt += min(a, b); } } cout << cnt << n ; return 0; } |
module memory_epp(
input wire mclk,
input wire epp_astb,
input wire epp_dstb,
input wire epp_wr,
output reg epp_wait,
inout wire[7:0] epp_data,
input wire[7:6] status,
input wire[31:0] address,
output wire[31:0] dout,
input wire[31:0] din,
output reg complete,
input wire complete_clr
);
// Host is Little-Endian (LSB, ..., MSB).
wire[7:0] address_array[0:3];
assign address_array[0] = address[7:0];
assign address_array[1] = address[15:8];
assign address_array[2] = address[23:16];
assign address_array[3] = address[31:24];
wire[7:0] din_array[0:3];
assign din_array[0] = din[7:0];
assign din_array[1] = din[15:8];
assign din_array[2] = din[23:16];
assign din_array[3] = din[31:24];
reg[7:0] dout_array[0:3];
assign dout[31:0] = {dout_array[3], dout_array[2], dout_array[1], dout_array[0]};
reg[7:0] epp_data_reg;
assign epp_data = epp_data_reg;
parameter max_index = 3;
reg[2:0] index = 0;
parameter epp_reg_status = 8'd0;
parameter epp_reg_mem_addr = 8'd1;
parameter epp_reg_mem_data = 8'd2;
reg[7:0] epp_address = 0;
parameter epp_state_idle = 3'b000;
parameter epp_state_data_read = 3'b001;
parameter epp_state_data_write = 3'b010;
parameter epp_state_addr_read = 3'b011;
parameter epp_state_addr_write = 3'b100;
reg[2:0] epp_state = epp_state_idle;
// EPP Controller Asserts "Complete" After:
// - Host reads 4 bytes from mem_data register
// - Host writes 4 bytes to mem_data register
// - Host writes value 1 to command register
// EPP Controller Transparently Allows:
// - Read of command register
// - Read of memory adress
always @ (posedge mclk) begin
if(complete_clr == 1) begin
complete <= 0;
end else begin
case(epp_state)
epp_state_addr_read: begin
epp_wait <= 1;
epp_data_reg <= epp_address;
if(epp_astb == 1) begin
epp_state <= epp_state_idle;
end
end
epp_state_addr_write: begin
epp_wait <= 1;
epp_address <= epp_data;
index <= 0;
if(epp_astb == 1) begin
epp_state <= epp_state_idle;
end
end
epp_state_data_read: begin
epp_wait <= 1;
case(epp_address)
epp_reg_status:
epp_data_reg <= {status, 6'b0};
epp_reg_mem_addr:
epp_data_reg <= address_array[index];
epp_reg_mem_data:
epp_data_reg <= din_array[index];
default:
epp_data_reg <= 0;
endcase
if(epp_dstb == 1) begin
if(epp_address == epp_reg_mem_data && index == max_index) begin
complete <= 1;
end
index <= index + 1;
epp_state <= epp_state_idle;
end
end
epp_state_data_write: begin
epp_wait <= 1;
if(epp_address == epp_reg_mem_data) begin
dout_array[index] <= epp_data;
end
if(epp_dstb == 1) begin
if(epp_address == epp_reg_mem_data && index == max_index) begin
complete <= 1;
end
index <= index + 1;
epp_state <= epp_state_idle;
end
end
default: begin
if(epp_astb == 0) begin
if(epp_wr == 0) begin
epp_state <= epp_state_addr_write;
end else begin
epp_state <= epp_state_addr_read;
end
end else if(epp_dstb == 0) begin
if(epp_wr == 0) begin
epp_state <= epp_state_data_write;
end else begin
epp_state <= epp_state_data_read;
end
end
epp_wait <= 0; // Asserted
epp_data_reg <= 8'bZZZZZZZZ;
end
endcase
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_read_valid_selector(
reset_n,
pll_afi_clk,
latency_shifter,
latency_counter,
read_enable,
read_valid
);
parameter MAX_LATENCY_COUNT_WIDTH = "";
localparam LATENCY_NUM = 2**MAX_LATENCY_COUNT_WIDTH;
input reset_n;
input pll_afi_clk;
input [LATENCY_NUM-1:0] latency_shifter;
input [MAX_LATENCY_COUNT_WIDTH-1:0] latency_counter;
output read_enable;
output read_valid;
wire [LATENCY_NUM-1:0] selector;
reg [LATENCY_NUM-1:0] selector_reg;
reg read_enable;
reg reading_data;
reg read_valid;
wire [LATENCY_NUM-1:0] valid_select;
lpm_decode uvalid_select(
.data (latency_counter),
.eq (selector)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock (),
.enable ()
// synopsys translate_on
);
defparam uvalid_select.lpm_decodes = LATENCY_NUM;
defparam uvalid_select.lpm_type = "LPM_DECODE";
defparam uvalid_select.lpm_width = MAX_LATENCY_COUNT_WIDTH;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
selector_reg <= {LATENCY_NUM{1'b0}};
else
selector_reg <= selector;
end
assign valid_select = selector_reg & latency_shifter;
always @(posedge pll_afi_clk or negedge reset_n)
begin
if (~reset_n)
begin
read_enable <= 1'b0;
read_valid <= 1'b0;
end
else
begin
read_enable <= |valid_select;
read_valid <= |valid_select;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[100000]; int main() { int n, a, b, c; cin >> n >> a >> b >> c; dp[a] = dp[b] = dp[c] = 1; int x = min(a, min(b, c)); for (int i = x; i <= n; i++) { if (i - a >= 0 && dp[i - a] > 0) dp[i] = max(dp[i], dp[i - a] + 1); if (i - b >= 0 && dp[i - b] > 0) dp[i] = max(dp[i], dp[i - b] + 1); if (i - c >= 0 && dp[i - c] > 0) dp[i] = max(dp[i], dp[i - c] + 1); } cout << dp[n]; return 0; } |
#include <bits/stdc++.h> using namespace std; const int modn = (int)1e9 + 7, N = (int)1e5 + 10; int a[N], p[N][6], q[N], c[6][6][6], n, m; inline void add(int &x, int y) { x += y; if (x >= modn) x %= modn; } struct zz { int power, x, s, t, tot; int v[N << 2], ls[N << 2], rs[N << 2], b[N << 2]; void build(int l, int r, int now) { b[now] = -1; if (l == r) { v[now] = (long long)a[l] * p[l][power] % modn; return; } int mid = (l + r) >> 1; ls[now] = ++tot; rs[now] = ++tot; build(l, mid, ls[now]); build(mid + 1, r, rs[now]); add(v[now], v[ls[now]]); add(v[now], v[rs[now]]); } void push(int l, int r, int now) { if (b[now] != -1 && l != r) { int mid = (l + r) >> 1; v[ls[now]] = (long long)b[now] * (p[mid][power] - p[l - 1][power] + modn) % modn; v[rs[now]] = (long long)b[now] * (p[r][power] - p[mid][power] + modn) % modn; b[rs[now]] = b[ls[now]] = b[now]; b[now] = -1; } } void make(int l, int r, int now) { if (l >= s && r <= t) { b[now] = x; v[now] = (long long)x * (p[r][power] - p[l - 1][power] + modn) % modn; return; } push(l, r, now); int mid = (l + r) >> 1; if (mid >= s) make(l, mid, ls[now]); if (mid < t) make(mid + 1, r, rs[now]); v[now] = 0; add(v[now], v[ls[now]]); add(v[now], v[rs[now]]); } int ask(int l, int r, int now) { if (l >= s && r <= t) return v[now]; push(l, r, now); int mid = (l + r) >> 1, ret = 0; if (mid >= s) add(ret, ask(l, mid, ls[now])); if (mid < t) add(ret, ask(mid + 1, r, rs[now])); v[now] = 0; add(v[now], v[ls[now]]); add(v[now], v[rs[now]]); return ret; } } T[6]; inline void read(int &ret) { ret = 0; char x = getchar(); while (x < 0 || x > 9 ) x = getchar(); while (x >= 0 && x <= 9 ) { ret = ret * 10 + x - 0 ; x = getchar(); } } inline int spj() { static int l, r, k, ch[6], pp[6]; int ret = 0; read(l); read(r); read(k); pp[0] = 1; for (int i = 0; i <= k; ++i) { if (i != 0) pp[i] = (long long)pp[i - 1] * (modn - l) % modn; T[i].s = l; T[i].t = r; ch[i] = T[i].ask(1, n, 0); } for (int i = 0; i <= k; ++i) for (int j = 0; i + j <= k; ++j) add(ret, (long long)ch[i] * c[i][j][k - i - j] % modn * pp[j] % modn); return ret; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) read(a[i]); for (int i = 1; i <= n; ++i) { p[i][0] = 1; for (int j = 1; j < 6; ++j) p[i][j] = (long long)p[i][j - 1] * i % modn; } for (int i = 0; i < 6; ++i) T[i].power = i; for (int i = 0; i < 6; ++i) T[i].build(1, n, 0); for (int i = 1; i <= n; ++i) for (int j = 0; j < 6; ++j) add(p[i][j], p[i - 1][j]); q[0] = 1; for (int i = 1; i < 6; ++i) q[i] = q[i - 1] * i; for (int i = 0; i < 6; ++i) for (int j = 0; j < 6; ++j) for (int k = 0; k < 6; ++k) if (i + j + k < 6) c[i][j][k] = q[i + j + k] / q[i] / q[j] / q[k]; for (int i = 1; i <= m; ++i) { int l, r, x; char cc = getchar(); while (cc != ? && cc != = ) cc = getchar(); if (cc == = ) { read(l); read(r); read(x); for (int i = 0; i < 6; ++i) { T[i].s = l; T[i].t = r; T[i].x = x; T[i].make(1, n, 0); } } else printf( %d n , spj()); } } |
#include <bits/stdc++.h> using namespace std; void past_code(); vector<int> v[100005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int x, y, j, k; cin >> x; for (int i = 1; i <= 2 * x; i++) { cin >> y; v[y].push_back(i); } long long sum = 0; j = 1; k = 1; for (int i = 1; i <= x; i++) { sum += abs(j - v[i][0]) + abs(k - v[i][1]); j = v[i][0]; k = v[i][1]; } cout << sum << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> using min_pq = priority_queue<T, vector<T>, greater<T>>; template <typename T> using max_pq = priority_queue<T>; const int inf = 2e9 + 5; const long long l_inf = 2e18 + 5; const int mod_v = 1e9 + 7; const int max_n = 1e5 + 5; const int dx[4] = {-1, 0, 1, 0}; const int dy[4] = {0, 1, 0, -1}; template <typename T> T gcd(T a, T b) { while (b) { T temp = a % b; a = b; b = temp; } return a; } template <typename T> tuple<T, T, T> egcd(T a, T b) { T x1 = 1, x2 = 0, y1 = 0, y2 = 1; while (b) { T q = a / b, r = a % b; T new_x = x1 - q * x2, new_y = y1 - q * y2; x1 = x2, y1 = y2, x2 = new_x, y2 = new_y; a = b, b = r; } return make_tuple(a, x1, y1); } inline long long lcm(long long a, long long b) { return a * b / gcd(a, b); } template <typename T> inline T mod(T a, T b = mod_v) { return (a % b + b) % b; } template <typename T> inline T mod_inv(T a, T b = mod_v) { return mod(get<1>(egcd(a, b)), b); } template <typename T> inline T sum(T a, T b, T m = mod_v) { return mod(mod(a, m) + mod(b, m), m); } template <typename T> inline T difference(T a, T b, T m = mod_v) { return mod(mod(a, m) - mod(b, m), m); } inline long long product(long long a, long long b, long long m = mod_v) { return mod(mod(a, m) * mod(b, m), m); } inline long long quotient(long long a, long long b, long long m = mod_v) { return mod(mod(a, m) * mod_inv(b, m), m); } template <typename T, typename T2> ostream &operator<<(ostream &s, const pair<T, T2> &p) { return s << p.first << << p.second << ; } template <typename T, typename T2> istream &operator>>(istream &s, pair<T, T2> &p) { return s >> p.first >> p.second; } template <typename T> ostream &operator<<(ostream &s, const vector<T> &v) { for (auto it : v) s << it << ; return s; } template <typename T> istream &operator>>(istream &s, vector<T> &v) { for (auto it = (v).begin(), it_ = (v).end(); it != it_; ++it) s >> *it; return s; } template <typename T> void read_range(T beg, T end) { while (beg != end) cin >> *beg++; } template <typename T> void print_range(T beg, T end) { while (beg != end) cout << *beg++ << ; } struct reader { template <typename T> reader &operator,(T &v) { cin >> v; return *this; } } rdr; struct debugger { template <typename T> debugger &operator,(const T &v) { cerr << v << , ; return *this; } } dbg; map<pair<int, int>, long long> memo; long long ar[max_n * 10], cnt[max_n * 10], cnt2[10 * max_n], comp[10 * max_n]; vector<pair<int, int>> v; long long f(int cur, int k) { if (k == 0) return 1; if (cur == -1) return 0; if (memo.find(make_pair(cur, k)) != memo.end()) return memo[make_pair(cur, k)]; return memo[make_pair(cur, k)] = (f(cur - 1, k) + (cnt[cur] * f(cur, k - 1)) % mod_v) % mod_v; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, l, k; rdr, n, l, k; ; read_range(ar, ar + n); for (int i = 0; i < n; ++i) v.emplace_back(ar[i], i); sort((v).begin(), (v).end()); int sz = 0; for (int i = 0; i < n; ++i) { while (i + 1 < n and v[i].first == v[i + 1].first) { comp[v[i].second] = sz; ++cnt[sz]; ++i; } comp[v[i].second] = sz; ++cnt[sz]; ++sz; } long long rem = l % n, seg = l / n; for (int i = 0; i < rem; ++i) ++cnt2[comp[i]]; long long ans = 0; for (int i = 1; i <= min(k, seg); ++i) { ans += ((seg - i + 1) % mod_v) * f(sz - 1, i); ans %= mod_v; } for (int i = 1; i <= min(k, seg + 1); ++i) { for (int j = 0; j < sz; ++j) { ans += cnt2[j] * f(j, i - 1); ans %= mod_v; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> void read(T& num) { char CH; bool F = false; for (CH = getchar(); CH < 0 || CH > 9 ; F = CH == - , CH = getchar()) ; for (num = 0; CH >= 0 && CH <= 9 ; num = num * 10 + CH - 0 , CH = getchar()) ; F && (num = -num); } int stk[70], tp; template <class T> inline void print(T p) { if (!p) { puts( 0 ); return; } while (p) stk[++tp] = p % 10, p /= 10; while (tp) putchar(stk[tp--] + 0 ); putchar( n ); } const long long mod = 1e9 + 7; const double PI = acos(-1.0); const int inf = 1e9; const int N = 1e5 + 10; const int maxn = 1e3 + 20; const double eps = 1e-12; int check(int x) { int l = 1, r = 1000005; if (x == 0) return 0; while (l <= r) { int mid = (l + r) >> 1; if ((long long)mid * (mid - 1) < (long long)2 * x) l = mid + 1; else r = mid - 1; } return l; } int main() { int a, b, c, d; read(a); read(b); read(c); read(d); int x = check(a), y = check(d); if (x == 0 && (b || c)) x = 1; if (y == 0 && (b || c)) y = 1; if ((long long)x * (x - 1) != (long long)2 * a || (long long)y * (y - 1) != (long long)2 * d || (long long)x * y != (long long)b + c) cout << Impossible n ; else { if (x == 0 && y == 0) printf( 0 ); else if (x == 0) { for (int i = 1; i <= y; i++) printf( 1 ); } else if (y == 0) { for (int i = 1; i <= x; i++) printf( 0 ); } else { int t = b / y, f = y - b % y; for (int i = 1; i <= t; i++) printf( 0 ), x--; for (int i = 1; i <= f; i++) printf( 1 ), y--; if (x > 0) { printf( 0 ); x--; } for (int i = 1; i <= y; i++) printf( 1 ); for (int i = 1; i <= x; i++) printf( 0 ); } } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [255:0] a;
reg [255:0] q;
reg [63:0] qq;
integer i;
always @* begin
for (i=0; i<256; i=i+1) begin
q[255-i] = a[i];
end
q[27:16] = 12'hfed;
for (i=0; i<64; i=i+1) begin
qq[63-i] = a[i];
end
qq[27:16] = 12'hfed;
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("%x/%x %x\n", q, qq, a);
`endif
if (cyc==1) begin
a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
end
if (cyc==2) begin
a = 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
if (q != 256'h64fe7e285bcf892eca128d426ed707a20eebc824d5d9127bacbc21362fed1cb7) $stop;
if (qq != 64'h64fe7e285fed892e) $stop;
end
if (cyc==3) begin
if (q != 256'h1da9cf939c0712504b5bdbbbbfbb6c47c316bd471362641958a7fabcffede870) $stop;
if (qq != 64'h1da9cf939fed1250) $stop;
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_dest_fifo_inf #(
parameter ID_WIDTH = 3,
parameter DATA_WIDTH = 64,
parameter BEATS_PER_BURST_WIDTH = 4)(
input clk,
input resetn,
input enable,
output enabled,
input req_valid,
output req_ready,
output [ID_WIDTH-1:0] response_id,
output reg [ID_WIDTH-1:0] data_id = 'h0,
input data_eot,
input response_eot,
input en,
output reg [DATA_WIDTH-1:0] dout,
output reg valid,
output reg underflow,
output xfer_req,
output fifo_ready,
input fifo_valid,
input [DATA_WIDTH-1:0] fifo_data,
input fifo_last,
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
);
`include "inc_id.vh"
reg active = 1'b0;
/* Last beat of the burst */
wire fifo_last_beat;
/* Last beat of the segment */
wire fifo_eot_beat;
assign enabled = enable;
assign fifo_ready = en & (fifo_valid | ~enable);
/* fifo_last == 1'b1 implies fifo_valid == 1'b1 */
assign fifo_last_beat = fifo_ready & fifo_last;
assign fifo_eot_beat = fifo_last_beat & data_eot;
assign req_ready = fifo_eot_beat | ~active;
assign xfer_req = active;
always @(posedge clk) begin
if (en) begin
dout <= fifo_valid ? fifo_data : {DATA_WIDTH{1'b0}};
valid <= fifo_valid & enable;
underflow <= ~(fifo_valid & enable);
end else begin
valid <= 1'b0;
underflow <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
data_id <= 'h00;
end else if (fifo_last_beat == 1'b1) begin
data_id <= inc_id(data_id);
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
active <= 1'b0;
end else if (req_valid == 1'b1) begin
active <= 1'b1;
end else if (fifo_eot_beat == 1'b1) begin
active <= 1'b0;
end
end
dmac_response_generator # (
.ID_WIDTH(ID_WIDTH)
) i_response_generator (
.clk(clk),
.resetn(resetn),
.enable(enable),
.enabled(),
.request_id(data_id),
.response_id(response_id),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[11][11] = {1}; for (int i = 0; i < n; i++) { a[i][0] = 1; a[0][i] = 1; } for (int i = 1; i < n; i++) { for (int j = 1; j < n; j++) { a[i][j] = a[i - 1][j] + a[i][j - 1]; } } cout << n << a[n - 1][n - 1]; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> using v2d = vector<vector<T> >; template <class T> bool uin(T &a, T b) { return a > b ? (a = b, true) : false; } template <class T> bool uax(T &a, T b) { return a < b ? (a = b, true) : false; } mt19937 rng(chrono::system_clock::now().time_since_epoch().count()); const int maxN = 2e3 + 10; int n, k, a[maxN], dp[maxN][maxN]; void solve() { cin >> n >> k; for (int i = 1; i <= (int)(n); ++i) { cin >> a[i]; } for (int i = (int)(0); i <= (int)(n); ++i) { for (int j = (int)(0); j <= (int)(n); ++j) { dp[i][j] = -1e9; } } dp[0][0] = 0; for (int i = 1; i <= (int)(n); ++i) { for (int j = (int)(0); j <= (int)(i); ++j) { if (j > 0) { uax(dp[i][j], dp[i - 1][j - 1]); } uax(dp[i][j], dp[i - 1][j] + (a[i] == i - j)); } } for (int i = 0; i < (int)(n); ++i) { if (dp[n][i] >= k) { cout << i << n ; return; } } cout << -1 << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int T = 1; cin >> T; while (T--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string a, b; long long team1 = 0, team2 = 0; cin >> a; cin >> b; for (int i = 0; i <= a.size(); i++) { if ((a[i] == [ && b[i] == ( ) || (a[i] == 8 && b[i] == [ ) || (a[i] == ( && b[i] == 8 )) { team1++; } else if ((b[i] == [ && a[i] == ( ) || (b[i] == 8 && a[i] == [ ) || (b[i] == ( && a[i] == 8 )) { team2++; } } if (team1 > team2) { cout << TEAM 1 WINS ; } else if (team1 < team2) { cout << TEAM 2 WINS ; } else { cout << TIE ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND2B_4_V
`define SKY130_FD_SC_HD__AND2B_4_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2b_4 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and2b_4 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND2B_4_V
|
`include "Defintions.v"
`include "Token.v"
`include "data_setup.v"
//este modulo es concido como targetsystem
module TS (
sync,
sync2,
clk,
rst,
data,
token,
busy,
data_out,
setup_data,
token_out,
);
input wire busy;
input wire clk;
input wire rst;
input wire [88:0] setup_data;
input wire [1047:0]data;
input wire [23:0] token;
input wire [31:0]sync2;
input wire [7:0] sync;
output reg [1047:0]data_out;
output reg [7:0]token_out;
reg dato_par ;
reg [1:0] speed ; // the states 00 low 01 full 10 super high speed
reg [7:0] alt_USB_Stack ;
reg [31:0] halted_enpoints_in;
reg [31:0] halted_enpoints_out;
reg [31:0] funcion_enpoints_in;
reg [31:0] funcion_enpoints_out;
reg [63:0] dato_atual ;
reg [4:0]state,next_state;
reg [6:0]addr;
reg [3:0]endp;
reg error;
reg DATA_error;
reg token_vald;
reg [6:0]Myaddr ;
reg startControl;
reg [3:0] last_token ;
wire [7:0]pid1;
wire [6:0]addr1;
wire [3:0]endp1;
wire err1;
wire [63:0] data1 ;
wire data_error;
reg extra_data_setup;
reg temp123;
//estos son los estados y los valores valios de token no se trabajo con l
//los esperciales
parameter [3:0]
IDLE = 5'b00001,
RECEIVE = 5'b00010,
STATE = 5'b00011,
TOKEN = 5'b00100,
DATA = 5'b00101,
ACK_TOKEN = 5'b00110,
SETUP_TOKEN = 5'b00111,
OUT_TOKEN = 5'b01000,
IN_TOKEN = 5'b01001,
DATA_IN = 5'b01011,
DATA_OUT = 5'b01100,
STALL = 5'b01101,
NACK_TOKEN = 5'b01111,
Token_OUT = 4'b0001,
Token_IN = 4'b1001,
Token_SOF = 4'b0101,
Token_SETUP = 4'b1101,
Data_DATA0 = 4'b0011,
Data_DATA1 = 4'b1011,
Data_DATA2 = 4'b0111,
Data_MDATA = 4'b1111,
Handshake_ACK = 4'b0010,
Handshake_NAK = 4'b1010,
Handshake_STALL = 4'b1110,
Handshake_NYET = 4'b0110,
Special_PRE = 4'b1100,
Special_ERR = 4'b1100,
Special_SPLIT = 4'b1000,
Special_PING = 4'b0100,
Special_Reserved = 4'b0000;
//token_in es una funcion que se encarga de verificar si el token es valido
token_in token_in_intance (
.data (token),
.pid (pid1),
.addr (addr1),
.endp (endp1),
.err (err1)
);
Data_set_up_pack Data_set_up_pack_intance (
.data (data1),
.packet (setup_data),
.data_error(data_error)
);
always @(posedge clk)
begin if (rst) begin #1 state = IDLE; end
else begin #1 state = next_state; end
end
always @(posedge clk)
begin
startControl = 1'b0 ;
next_state = state;
token_out = 7'b0 ;
Myaddr = 7'b1111111;
halted_enpoints_in = 0 ;
halted_enpoints_out = 0;
funcion_enpoints_in =0;
funcion_enpoints_out = 0;
addr[6:0] = addr1;
case (state)
IDLE :
begin
if (sync == 8'b01010100)
begin
speed = 01 ;
next_state = RECEIVE;
end
if (sync2 == 1)
begin
speed = 10 ;
next_state = RECEIVE;
end
if (sync2 != 1 && sync != 8'b01010100 )
begin
speed = 10 ;
next_state = RECEIVE;
end
end
RECEIVE :
begin
if (token[23] == ~token[19] && token[22] == ~token[18] && token[21] == ~token[17] && token[20] == ~token[16])
begin
next_state = STATE;
end
else next_state = IDLE;
end
STATE:
begin
if (token[23:20] == Token_OUT)
begin
if (addr[6:0] == Myaddr[6:0])
begin
if (halted_enpoints_out [endp1 ] == 1) next_state = STALL;
else
begin
last_token[3:0] = token[23:20] ;
next_state = IDLE;
end
end
else next_state = IDLE;
end
if (token[23:20] == Token_IN)
begin
if (addr[6:0] == Myaddr[6:0])
begin
if (halted_enpoints_in [endp1 ] == 1) next_state = STALL;
else
begin
last_token = token[23:20] ;
next_state = IDLE;
end
end
else next_state = IDLE;
end
if (token[23:20] == Token_SETUP)
begin
//Control mod
next_state = SETUP_TOKEN;
end
if (token[23:20] == Data_DATA0 )
begin
if (addr[6:0] == Myaddr[6:0])
begin
dato_par = 1 ;
if (last_token [3:0] == Token_SETUP) next_state = DATA_IN;
if (last_token [3:0] == Token_IN) next_state = DATA_IN;
if (last_token [3:0] == Token_OUT) next_state = DATA_OUT;
if (last_token [3:0] != Token_SETUP && last_token [3:0] != Token_SETUP && last_token [3:0] != Token_OUT) next_state = IDLE;
end
else next_state = IDLE;
end
if (token[23:20] == Data_DATA1)
begin
if (addr[6:0] == Myaddr[6:0])
begin
dato_par = 0 ;
if (last_token [3:0] == Token_IN) next_state = DATA_IN;
if (last_token [3:0] == Token_OUT) next_state = DATA_OUT;
end
else next_state = IDLE;
end
if (token[23:20] == Handshake_ACK )
begin
if (addr[6:0] == Myaddr[6:0])
begin
end
else next_state = IDLE;
end
if (token[23:20] == Handshake_NAK)
begin
if (addr[6:0] == Myaddr[6:0])
begin
//this is not used by debug class in control
end
else next_state = IDLE;
end
if (token[23:20] == Handshake_STALL)
begin
if (addr[6:0] == Myaddr[6:0])
begin
//this is not used by debug class in control
end
else next_state = IDLE;
end
end
SETUP_TOKEN:
begin
last_token = token[23:20] ;
if (endp1==0)
begin
/*if (data_error == 1'b1)
begin
//este dato
next_state = NACK_TOKEN;
end
else */
begin
next_state = IDLE;
end
end
end
NACK_TOKEN:
begin
token_out = Handshake_NAK;
next_state = IDLE;
end
ACK_TOKEN:
begin
token_out = Handshake_ACK;
next_state = IDLE;
end
STALL:
begin
token_out = Handshake_STALL;
end
DATA_IN:
begin
if (last_token == Token_SETUP)
begin
dato_atual = setup_data[80:16];
next_state = ACK_TOKEN;
end
else
begin
dato_atual= data1 ;
if (data_error == 1'b1)
begin
//este dato
next_state = NACK_TOKEN;
end
if (busy == 1'b1)
begin
//este dato
next_state = STALL;
end
end
if (busy != 1'b1 && data_error != 1'b1)
begin
next_state = ACK_TOKEN;
end
end
DATA_OUT:
begin
next_state = IDLE;
if (data_error == 1'b1)
begin
//este dato
next_state = NACK_TOKEN;
end
if (busy == 1'b1)
begin
//este dato
next_state = STALL;
end
if (busy != 1'b1 && data_error != 1'b1)
begin
next_state = ACK_TOKEN;
end
end
/**/
endcase
end
endmodule |
/* This module implements the VGA controller. It assumes a 25MHz clock is supplied as input.
*
* General approach:
* Go through each line of the screen and read the colour each pixel on that line should have from
* the Video memory. To do that for each (x,y) pixel on the screen convert (x,y) coordinate to
* a memory_address at which the pixel colour is stored in Video memory. Once the pixel colour is
* read from video memory its brightness is first increased before it is forwarded to the VGA DAC.
*/
module vga_controller( vga_clock, resetn, pixel_colour, memory_address,
VGA_R, VGA_G, VGA_B,
VGA_HS, VGA_VS, VGA_BLANK,
VGA_SYNC, VGA_CLK);
/* Screen resolution and colour depth parameters. */
parameter BITS_PER_COLOUR_CHANNEL = 1;
/* The number of bits per colour channel used to represent the colour of each pixel. A value
* of 1 means that Red, Green and Blue colour channels will use 1 bit each to represent the intensity
* of the respective colour channel. For BITS_PER_COLOUR_CHANNEL=1, the adapter can display 8 colours.
* In general, the adapter is able to use 2^(3*BITS_PER_COLOUR_CHANNEL) colours. The number of colours is
* limited by the screen resolution and the amount of on-chip memory available on the target device.
*/
parameter MONOCHROME = "FALSE";
/* Set this parameter to "TRUE" if you only wish to use black and white colours. Doing so will reduce
* the amount of memory you will use by a factor of 3. */
parameter RESOLUTION = "320x240";
/* Set this parameter to "160x120" or "320x240". It will cause the VGA adapter to draw each dot on
* the screen by using a block of 4x4 pixels ("160x120" resolution) or 2x2 pixels ("320x240" resolution).
* It effectively reduces the screen resolution to an integer fraction of 640x480. It was necessary
* to reduce the resolution for the Video Memory to fit within the on-chip memory limits.
*/
//--- Timing parameters.
/* Recall that the VGA specification requires a few more rows and columns are drawn
* when refreshing the screen than are actually present on the screen. This is necessary to
* generate the vertical and the horizontal syncronization signals. If you wish to use a
* display mode other than 640x480 you will need to modify the parameters below as well
* as change the frequency of the clock driving the monitor (VGA_CLK).
*/
parameter C_VERT_NUM_PIXELS = 10'd480;
parameter C_VERT_SYNC_START = 10'd493;
parameter C_VERT_SYNC_END = 10'd494; //(C_VERT_SYNC_START + 2 - 1);
parameter C_VERT_TOTAL_COUNT = 10'd525;
parameter C_HORZ_NUM_PIXELS = 10'd640;
parameter C_HORZ_SYNC_START = 10'd659;
parameter C_HORZ_SYNC_END = 10'd754; //(C_HORZ_SYNC_START + 96 - 1);
parameter C_HORZ_TOTAL_COUNT = 10'd800;
/*****************************************************************************/
/* Declare inputs and outputs. */
/*****************************************************************************/
input vga_clock, resetn;
input [((MONOCHROME == "TRUE") ? (0) : (BITS_PER_COLOUR_CHANNEL*3-1)):0] pixel_colour;
output [((RESOLUTION == "320x240") ? (16) : (14)):0] memory_address;
output reg [9:0] VGA_R;
output reg [9:0] VGA_G;
output reg [9:0] VGA_B;
output reg VGA_HS;
output reg VGA_VS;
output reg VGA_BLANK;
output VGA_SYNC, VGA_CLK;
/*****************************************************************************/
/* Local Signals. */
/*****************************************************************************/
reg VGA_HS1;
reg VGA_VS1;
reg VGA_BLANK1;
reg [9:0] xCounter, yCounter;
wire xCounter_clear;
wire yCounter_clear;
wire vcc;
reg [((RESOLUTION == "320x240") ? (8) : (7)):0] x;
reg [((RESOLUTION == "320x240") ? (7) : (6)):0] y;
/* Inputs to the converter. */
/*****************************************************************************/
/* Controller implementation. */
/*****************************************************************************/
assign vcc =1'b1;
/* A counter to scan through a horizontal line. */
always @(posedge vga_clock or negedge resetn)
begin
if (!resetn)
xCounter <= 10'd0;
else if (xCounter_clear)
xCounter <= 10'd0;
else
begin
xCounter <= xCounter + 1'b1;
end
end
assign xCounter_clear = (xCounter == (C_HORZ_TOTAL_COUNT-1));
/* A counter to scan vertically, indicating the row currently being drawn. */
always @(posedge vga_clock or negedge resetn)
begin
if (!resetn)
yCounter <= 10'd0;
else if (xCounter_clear && yCounter_clear)
yCounter <= 10'd0;
else if (xCounter_clear) //Increment when x counter resets
yCounter <= yCounter + 1'b1;
end
assign yCounter_clear = (yCounter == (C_VERT_TOTAL_COUNT-1));
/* Convert the xCounter/yCounter location from screen pixels (640x480) to our
* local dots (320x240 or 160x120). Here we effectively divide x/y coordinate by 2 or 4,
* depending on the resolution. */
always @(*)
begin
if (RESOLUTION == "320x240")
begin
x = xCounter[9:1];
y = yCounter[8:1];
end
else
begin
x = xCounter[9:2];
y = yCounter[8:2];
end
end
/* Change the (x,y) coordinate into a memory address. */
vga_address_translator controller_translator(
.x(x), .y(y), .mem_address(memory_address) );
defparam controller_translator.RESOLUTION = RESOLUTION;
/* Generate the vertical and horizontal synchronization pulses. */
always @(posedge vga_clock)
begin
//- Sync Generator (ACTIVE LOW)
VGA_HS1 <= ~((xCounter >= C_HORZ_SYNC_START) && (xCounter <= C_HORZ_SYNC_END));
VGA_VS1 <= ~((yCounter >= C_VERT_SYNC_START) && (yCounter <= C_VERT_SYNC_END));
//- Current X and Y is valid pixel range
VGA_BLANK1 <= ((xCounter < C_HORZ_NUM_PIXELS) && (yCounter < C_VERT_NUM_PIXELS));
//- Add 1 cycle delay
VGA_HS <= VGA_HS1;
VGA_VS <= VGA_VS1;
VGA_BLANK <= VGA_BLANK1;
end
/* VGA sync should be 1 at all times. */
assign VGA_SYNC = vcc;
/* Generate the VGA clock signal. */
assign VGA_CLK = vga_clock;
/* Brighten the colour output. */
// The colour input is first processed to brighten the image a little. Setting the top
// bits to correspond to the R,G,B colour makes the image a bit dull. To brighten the image,
// each bit of the colour is replicated through the 10 DAC colour input bits. For example,
// when BITS_PER_COLOUR_CHANNEL is 2 and the red component is set to 2'b10, then the
// VGA_R input to the DAC will be set to 10'b1010101010.
integer index;
integer sub_index;
always @(pixel_colour)
begin
VGA_R <= 'b0;
VGA_G <= 'b0;
VGA_B <= 'b0;
if (MONOCHROME == "FALSE")
begin
for (index = 10-BITS_PER_COLOUR_CHANNEL; index >= 0; index = index - BITS_PER_COLOUR_CHANNEL)
begin
for (sub_index = BITS_PER_COLOUR_CHANNEL - 1; sub_index >= 0; sub_index = sub_index - 1)
begin
VGA_R[sub_index+index] <= pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL*2];
VGA_G[sub_index+index] <= pixel_colour[sub_index + BITS_PER_COLOUR_CHANNEL];
VGA_B[sub_index+index] <= pixel_colour[sub_index];
end
end
end
else
begin
for (index = 0; index < 10; index = index + 1)
begin
VGA_R[index] <= pixel_colour[0:0];
VGA_G[index] <= pixel_colour[0:0];
VGA_B[index] <= pixel_colour[0:0];
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_4_V
`define SKY130_FD_SC_HD__O311A_4_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311a with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o311a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o311a_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o311a_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o311a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_4_V
|
#include <bits/stdc++.h> using namespace std; long long a[100]; long long b[100]; vector<long long> pos[101]; int main() { long long i, j, k, l, m, n, t; scanf( %lld , &n); scanf( %lld , &k); for (i = 0; i < n; i++) { scanf( %lld , &a[i]); pos[a[i]].push_back(i); } long long sum = 0, count = 0; long long flag = 0; for (i = 1; i <= 100; i++) { for (j = 0; j < pos[i].size(); j++) { sum = sum + a[pos[i][j]]; if (sum > k) { flag = 1; break; } b[count++] = pos[i][j]; } if (flag == 1) break; } cout << count << endl; for (j = 0; j < count; j++) cout << b[j] + 1 << ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_TB_V
`define SKY130_FD_SC_HDLL__OR4_TB_V
/**
* or4: 4-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_hdll__or4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, kk, a[200]; scanf( %d%d , &n, &kk); for (int i = 0; i < n; i++) scanf( %d , &a[i]); int sum, tp, mx = a[0]; for (int i = 0; i < n; i++) for (int j = i; j < n; j++) { priority_queue<int> la, sm; sum = 0; for (int k = 0; k < n; k++) if (k >= i && k <= j) { sm.push(-a[k]); sum += a[k]; } else la.push(a[k]); if (mx < sum) mx = sum; int ts = sum; for (int k = 0; k < kk; k++) { sum += sm.top(); la.push(-sm.top()); sm.pop(); sum += la.top(); sm.push(-la.top()); la.pop(); if (ts >= sum) break; } if (mx < sum) mx = sum; } printf( %d , mx); return 0; } |
#include <bits/stdc++.h> ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; using namespace std; long long po(long long n, long long exp) { long long prod = 1; for (long long i = 0; i < exp; i++) prod = (prod * n); return prod; } double dis(long long x1, long long y1, long long x2, long long y2) { return sqrt(((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2))); } signed main() { ios_base::sync_with_stdio(false); long long TESTS = 1; while (TESTS--) { long long n; cin >> n; long long a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; long long p = 1, ans = 0; a[n] = 1e11; for (long long i = 0; i < n; i++) { if (a[i] == a[i + 1]) { p++; } else { ans += (p * p + p) / 2; p = 1; } } cout << ans; } } |
/*
* Copyright (c) 2001 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program checks that the initial value of a memory is x. The
* verilog standard clearly states that reg values must start as x
* values, and implies that memories are the same.
*/
module main;
integer mem [0:1] ;
initial begin
if (mem[0] !== 32'hxxxx) begin
$display("FAILED -- mem[0] == %b", mem[0]);
$finish;
end
if (mem[1] !== 32'hxxxx) begin
$display("FAILED -- mem[1] == %b", mem[1]);
$finish;
end
$display("PASSED");
end // initial begin
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_PP_SYMBOL_V
`define SKY130_FD_SC_LP__BUFINV_PP_SYMBOL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bufinv (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; long long a, b, c; if (n % 3 == 0) { a = n - 2; b = 1; c = 1; } else { if ((n + 1) % 3 == 0) { a = n - 3; b = 2; c = 1; } else if ((n - 1) % 3 == 0) { a = n - 2; b = 1; c = 1; } } cout << a << << b << << c; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; mt19937 rnd(chrono::steady_clock().now().time_since_epoch().count()); const int N = 765; const long long inf = (long long)4e18; long long dp[N][N]; long long f[N]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int n, m; cin >> n >> m; long long a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < N; i++) { for (int j = 0; j < N; j++) { dp[i][j] = -inf; } } dp[n][0] = 0; for (int i = n - 1; i >= 0; i--) { for (int j = 0; j <= n; j++) { dp[i][j] = min(a[i] + dp[i + 1][j], a[i]); if (j > 0) { dp[i][j] = max(dp[i][j], dp[i + 1][j - 1]); } } } for (int j = 0; j <= n; j++) f[j] = dp[0][j]; long long b; for (int i = 1; i <= m; i++) { cin >> b; for (int i = 0; i <= n; i++) { if (b + f[i] >= 0) { cout << i << n ; break; } } } return 0; } |
module cpu( input clk,
inout [31:0] data,
output reg [11:0] adr,
output reg we);
reg [31:0] towrite;
reg [31:0]regs[15:0];
reg [31:0]ir;
reg [4:0] psr;
reg [5:0] pc;
reg halted;
integer i;
assign data = (we) ? towrite : 'bz;
initial begin
towrite = 'd0;
adr = 12'b000000000000;
we = 0;
psr = 5'b00000;
pc = 6'b000000;
ir = 'd0;
halted = 0;
for(i = 0; i< 16; i = i +1) begin
regs[i] = 'd0;
end
end
// Data in in ram 12'b111111_100000 - 12'b111111_111111
//instructions in ram 12'b000000000000 - 111111_000000
//pc points to instructions in 000000-111111 and gets the insturctin each cycle
always@(posedge clk) begin
adr = {6'b000000,pc};
#2
ir = data;
if(~halted) begin
case (ir[31:28])
0 : begin //No Op
pc = pc + 1'b1;
end
1 : begin //Load
if(ir[27] == 0) begin //load memory value
adr = ir[23:12];
#2
regs[ir[3:0]] = data;
end
else begin
regs[ir[3:0]] = ir[23:12]; //load immediate
end
psr[0] = 0;
setpsr();
end
2 : begin //Store
if(ir[26] == 0) begin //store reg value
towrite = regs[ir[15:12]];
we = 1;
adr = ir[11:0];
#2
we = 0;
end
else begin
towrite = ir[23:12];
we = 1;
adr = ir[11:0]; //store immediate
#2
we = 0;
end
psr = 0;
pc = pc+1;
end
3 : begin //Branch
case (ir[27:24])
0 : begin //Always
pc = ir[17:12];
end
1 : begin//Parity
if(psr[1]) begin
pc = ir[17:12];
end
else pc = pc +1'b1;
end
2 : begin//even
if(psr[2]) begin
pc = ir[17:12];
end
else pc = pc +1'b1;
end
3 : begin//carry
if(psr[0]) begin
pc = ir[17:12];
end
else pc = pc +1'b1;
end
4 : begin//negative
if(psr[3]) begin
pc = ir[17:12];
end
else pc = pc +1'b1;
end
5 : begin//zero
if(psr[4]) begin
pc = ir[17:12];
end
else pc = pc +1'b1;
end
6 : begin//no carry
if(~psr[0]) begin
pc = ir[17:12];
end
else pc = pc +1'b1;
end
7 : begin//positive
if(~psr[3]) begin
pc = ir[17:12];
end
else pc = pc +1'b1;
end
default : begin
$display("no such condition halting");
ir[31:28] = 8;
end
endcase
end
4 : begin //XOR
psr[0] = 0;
regs[ir[3:0]] = regs[ir[3:0]]^regs[ir[15:12]];
setpsr();
end
5 : begin //add
if(ir[27] == 0) begin
{psr[0],regs[ir[3:0]]} = regs[ir[15:12]]+regs[ir[3:0]]; //add reg values
end
else begin//add immediate in source to destination
{psr[0],regs[ir[3:0]]} = regs[ir[3:0]]+ir[15:12];//add immediate in source to destination
end
setpsr();
end
6 : begin //Rotate
psr[0] = 0;
if(ir[27] == 0) begin
if($signed(regs[ir[15:12]]) > 0) begin//rotate by value in source reg
regs[ir[3:0]] = ((regs[ir[3:0]] << regs[ir[15:12]]) | (regs[ir[3:0]] >> (16-regs[ir[15:12]])));
end
else begin
regs[ir[3:0]] = ((regs[ir[3:0]] >> (-1*$signed(regs[ir[15:12]]))) | (regs[ir[3:0]] << (16-(-1*$signed(regs[ir[15:12]])))));
end
end
else begin//rotate by immediate in source
if($signed(regs[ir[15:12]]) > 0) begin//rotate by value in source reg
regs[ir[3:0]] = ((regs[ir[3:0]] << ir[15:12]) | (regs[ir[3:0]] >> (16-ir[15:12])));
end
else begin
regs[ir[3:0]] = ((regs[ir[3:0]] >> (-1*$signed(ir[15:12]))) | (ir[3:0] << (16-(-1*$signed(ir[15:12])))));
end//rotate by immediate in source
end
setpsr();
end
7 : begin //Shift
if(ir[27] == 0) begin
if($signed(regs[ir[15:12]]) < 0) begin//shift by value in source reg
psr[0] = regs[ir[3:0]][31];
regs[ir[3:0]] = regs[ir[3:0]] << (-1*$signed(regs[ir[15:12]]));
end
else begin
psr[0] = regs[ir[3:0]][0];
regs[ir[3:0]] = regs[ir[3:0]] >> regs[ir[15:12]];
end
end
else begin //shift by immediate in source
if($signed(ir[15:12]) < 0) begin//shift by value in source reg
psr[0] = regs[ir[3:0]][31];
regs[ir[3:0]] = regs[ir[3:0]] << (-1*$signed(ir[15:12]));
end
else begin
psr[0] = regs[ir[3:0]][0];
regs[ir[3:0]] = regs[ir[3:0]] >> ir[15:12];
end
end
setpsr();
end
8 : begin //Halt
halted = 1;
$display("Halted");
end
9 : begin //Complement
regs[ir[3:0]] = ~regs[ir[15:12]];
psr[0] = 0;
setpsr();
end
10 : begin //display memory or reg value for testing
if(ir[27] == 0) begin //display memory value
adr = ir[11:0];
#2
$display($time,,"result in mem is = %b\n", data);
end
else if(ir[27] == 1) begin //display reg value
$display($time,,"result in reg is = %b\n", regs[ir[3:0]]);
end
pc = pc+1'b1;
end
default : begin
ir = 8;
$display("Error, no such operation, halting.");
end
endcase
end
end
task setpsr;
begin
psr[2] = 1;
for(i = 0; i<32; i = i+1) begin
psr[2] = psr[2] + regs[ir[3:0]][i];
end
psr[1] = ~psr[2];
if(regs[ir[3:0]] == 0) begin
psr[3] <= 0;
psr[4] <= 1;
end
else if(regs[ir[3:0]][31] == 1) begin
psr[3] <= 1;
psr[4] <= 0;
end
else begin
psr[4:3] <= 0;
end
pc <= pc + 1'b1;
end
endtask
endmodule
|
module test_RegWaitRW32(
//Avalon System control signal.
input rsi_MRST_reset, // reset_n from MCU GPIO
input csi_MCLK_clk,
//Avalon-MM Control.
input [31:0] avs_test_writedata,
output [31:0] avs_test_readdata,
input [5:0] avs_test_address,
input [3:0] avs_test_byteenable,
input avs_test_write,
input avs_test_read,
output avs_test_readdatavalid,
output avs_test_waitrequest
);
reg [31:0] out_data = 0;
reg [31:0] r_data = 0;
reg r_wait = 0;
reg [3:0] r_wait_cnt = 0;
reg r_valid = 0;
assign avs_test_readdata = out_data;
assign avs_test_waitrequest = r_wait;
assign avs_test_readdatavalid = r_valid;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
out_data <= 0;
r_data <= 0;
r_wait <= 0;
r_wait_cnt <= 0;
r_valid <= 0;
end
else begin
if(r_wait_cnt == 15) r_valid <= 1; else r_valid <= 0;
if(((r_wait_cnt > 0)&&(r_wait_cnt < 15))||(avs_test_read)||(avs_test_write)) r_wait <= 1; else r_wait <= 0;
if(avs_test_read) begin
r_wait_cnt <= r_wait_cnt + 1;
out_data <= r_data + avs_test_address;
end
else if(avs_test_write) begin
r_wait_cnt <= r_wait_cnt + 1;
case(avs_test_address)
0: begin
if(avs_test_byteenable[3]) r_data[31:24] <= avs_test_writedata[31:24];
if(avs_test_byteenable[2]) r_data[23:16] <= avs_test_writedata[23:16];
if(avs_test_byteenable[1]) r_data[15:8] <= avs_test_writedata[15:8];
if(avs_test_byteenable[0]) r_data[7:0] <= avs_test_writedata[7:0];
end
1: begin
if(avs_test_byteenable[3]) r_data[31:24] <= ~avs_test_writedata[31:24];
if(avs_test_byteenable[2]) r_data[23:16] <= ~avs_test_writedata[23:16];
if(avs_test_byteenable[1]) r_data[15:8] <= ~avs_test_writedata[15:8];
if(avs_test_byteenable[0]) r_data[7:0] <= ~avs_test_writedata[7:0];
end
default: begin
r_data <= 0;
end
endcase
end
else begin
if(r_wait_cnt > 0) r_wait_cnt <= r_wait_cnt + 1; else r_wait_cnt <= 0;
end
end
end
endmodule
|
//--------------------------------------------------------------------------------
// transmitter.v
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Takes 32bit (one sample) and sends it out on the SPI interface
// End of transmission is signalled by taking back the busy flag.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis (IED) - mygizmos.org
// 01/22/2011 - IED - Tweaked to accept meta data write requests.
//
`timescale 1ns/100ps
module spi_transmitter (
// system signals
input wire clk,
input wire rst,
// SIP signals
input wire spi_cs_n,
input wire spi_sclk,
output reg spi_miso,
//
input wire send,
input wire [31:0] send_data,
input wire [3:0] send_valid,
input wire writeMeta,
input wire [7:0] meta_data,
input wire query_id,
input wire query_dataIn,
input wire [31:0] dataIn,
output reg busy,
output reg byteDone
);
reg [31:0] sampled_send_data, next_sampled_send_data;
reg [3:0] sampled_send_valid, next_sampled_send_valid;
reg [2:0] bits, next_bits;
reg [1:0] bytesel, next_bytesel;
reg next_byteDone;
reg dly_sclk, next_dly_sclk;
reg next_busy;
reg [7:0] txBuffer, next_txBuffer;
reg next_tx;
//wire spi_miso = txBuffer[7];
reg writeReset, writeByte;
//
// Byte select mux... Revised for better synth. - IED
//
reg [7:0] dbyte;
reg disabled;
always @*
begin
dbyte = 0;
disabled = 0;
case (bytesel)
2'h0 : begin dbyte = sampled_send_data[ 7: 0]; disabled = !sampled_send_valid[0]; end
2'h1 : begin dbyte = sampled_send_data[15: 8]; disabled = !sampled_send_valid[1]; end
2'h2 : begin dbyte = sampled_send_data[23:16]; disabled = !sampled_send_valid[2]; end
2'h3 : begin dbyte = sampled_send_data[31:24]; disabled = !sampled_send_valid[3]; end
endcase
end
//
// Send one byte synchronized to falling edge of SPI clock...
//
always @(posedge clk)
begin
dly_sclk <= next_dly_sclk;
bits <= next_bits;
byteDone <= next_byteDone;
txBuffer <= next_txBuffer;
spi_miso <= next_tx;
end
always @*
begin
next_dly_sclk = spi_sclk;
next_bits = bits;
next_byteDone = byteDone;
next_txBuffer = txBuffer;
next_tx = spi_miso;
if (writeReset) // simulation clean up - IED
begin
next_bits = 0;
next_byteDone = 1'b1;
next_txBuffer = 8'hFF;
end
else if (writeByte)
begin
next_bits = 0;
next_byteDone = disabled;
next_txBuffer = dbyte;
end
else if (writeMeta)
begin
next_bits = 0;
next_byteDone = 0;
next_txBuffer = meta_data;
end
// The PIC microcontroller asserts CS# in response to FPGA
// asserting dataReady (busy signal from this module actually).
// Until CS# asserts though keep the bits counter reset...
if (spi_cs_n) next_bits = 0;
// Output on falling edge of sclk when cs asserted...
if (!spi_cs_n && dly_sclk && !spi_sclk && !byteDone)
begin
// next_txBuffer = {txBuffer,1'b1};
next_bits = bits + 1'b1;
next_byteDone = &bits;
end
next_tx = (spi_cs_n || byteDone) ? 1'b1 : next_txBuffer[~bits];
end
//
// Control FSM for sending 32 bit words out SPI interface...
//
parameter [1:0] INIT = 0, IDLE = 1, SEND = 2, POLL = 3;
reg [1:0] state, next_state;
initial state = INIT;
always @(posedge clk, posedge rst)
if (rst) begin
state <= INIT;
sampled_send_data <= 32'h0;
sampled_send_valid <= 4'h0;
bytesel <= 3'h0;
busy <= 1'b0;
end else begin
state <= next_state;
sampled_send_data <= next_sampled_send_data;
sampled_send_valid <= next_sampled_send_valid;
bytesel <= next_bytesel;
busy <= next_busy;
end
always @*
begin
next_state = state;
next_sampled_send_data = sampled_send_data;
next_sampled_send_valid = sampled_send_valid;
next_bytesel = bytesel;
next_busy = (state != IDLE) || send || !byteDone;
writeReset = 1'b0;
writeByte = 1'b0;
case (state) // when write is '1', data will be available with next cycle
INIT :
begin
writeReset = 1'b1;
next_sampled_send_data = 32'h0;
next_sampled_send_valid = 4'hF;
next_bytesel = 3'h0;
next_busy = 1'b0;
next_state = IDLE;
end
IDLE :
begin
next_sampled_send_data = send_data;
next_sampled_send_valid = send_valid;
next_bytesel = 0;
if (send)
next_state = SEND;
else if (query_id) // output dword containing "SLA1" signature
begin
next_sampled_send_data = 32'h534c4131; // "SLA1"
next_sampled_send_valid = 4'hF;
next_state = SEND;
end
else if (query_dataIn)
begin
next_sampled_send_data = dataIn;
next_sampled_send_valid = 4'hF;
next_state = SEND;
end
end
SEND : // output dword send by controller...
begin
writeByte = 1'b1;
next_bytesel = bytesel + 1'b1;
next_state = POLL;
end
POLL :
begin
if (byteDone)
next_state = (~|bytesel) ? IDLE : SEND;
end
default : next_state = INIT;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_2_V
`define SKY130_FD_SC_HS__OR3_2_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_2_V
|
#include <bits/stdc++.h> using namespace std; const int MaxN = 1e5; struct NOOD { int flag; int l; int r; int v; } num[MaxN + 5]; int ans[MaxN + 5], p[MaxN + 5]; bool ok[MaxN + 5], flag; int Max; int n, m; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d%d%d , &num[i].flag, &num[i].l, &num[i].r, &num[i].v); } for (int i = 1; i <= n; i++) ans[i] = -100000000; for (int i = m; i >= 1; i--) { if (num[i].flag == 1) { for (int j = num[i].l; j <= num[i].r; j++) ans[j] -= num[i].v; } else { for (int j = num[i].l; j <= num[i].r; j++) { if (ok[j] && ans[j] < num[i].v) continue; ans[j] = num[i].v; ok[j] = 1; } } } for (int i = 1; i <= n; i++) p[i] = ans[i]; for (int i = 1; i <= m; i++) { if (num[i].flag == 1) { for (int j = num[i].l; j <= num[i].r; j++) p[j] += num[i].v; } else { Max = -100000000; for (int j = num[i].l; j <= num[i].r; j++) Max = max(Max, p[j]); if (Max != num[i].v) flag = 1; } } if (flag) printf( NO n ); else { printf( YES n ); for (int i = 1; i <= n; i++) printf( %d , ans[i]); printf( n ); } } |
/*
Distributed under the MIT license.
Copyright (c) 2016 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`timescale 1ps / 1ps
`define DATA_SIZE 32
module ft245_host_interface (
input clk,
input rst,
//FT245 Interface
input i_ft245_clk,
inout [7:0] io_ft245_data,
input i_ft245_txe_n,
output o_ft245_wr_n,
input i_ft245_rde_n,
output o_ft245_rd_n,
output o_ft245_oe_n,
output o_ft245_siwu,
//Ingress
output ingress_clk,
input [1:0] ingress_rdy,
output reg [1:0] ingress_act,
output reg ingress_stb,
input [23:0] ingress_size,
output reg [`DATA_SIZE - 1: 0] ingress_data,
//Egress
output egress_clk,
input egress_rdy,
output reg egress_act,
output reg egress_stb,
input [23:0] egress_size,
input [`DATA_SIZE - 1: 0] egress_data,
output [31:0] ftdi_debug
);
//local parameters
localparam BYTE_COUNT = `DATA_SIZE / 8;
localparam IDLE = 0;
localparam INGRESS_READ = 1;
localparam EGRESS_PREPARE = 2;
localparam EGRESS_SEND = 3;
localparam EGRESS_SEND_TEMP_DATA = 4;
localparam EGRESS_SEND_IMMEDIATELY = 5;
//registes/wires
reg [3:0]state = IDLE;
reg [23:0] count = 0;
reg [7:0] byte_count = 0;
reg [`DATA_SIZE - 1: 0] r_ft245_ingress_data_dword;
reg [`DATA_SIZE - 1: 0] r_ft245_egress_data_dword;
reg [7:0] r_ft245_egress_data = 8'h0;
reg [7:0] r_ft245_egress_tmp_data = 8'h0;
reg r_ft245_read_tmp_data;
wire w_ft245_ingress_avail;
reg r_ft245_ingress_stb = 0;
reg r_ft245_output_enable = 0;
wire w_ft245_egress_avail;
reg r_ft245_egress_stb = 0;
reg r_ft245_egress_send_now = 0;
wire w_ingress_ready;
wire ft245_clk;
//submodules
//asynchronous logic
assign ft245_clk = i_ft245_clk;
//IBUFG ft245_clock_buf(.I(i_ft245_clk), .O(ft245_clk));
assign ingress_clk = ft245_clk;
assign egress_clk = ft245_clk;
assign w_ft245_ingress_avail = !i_ft245_rde_n;
assign w_ft245_egress_avail = !i_ft245_txe_n;
assign o_ft245_wr_n = !r_ft245_egress_stb;
assign o_ft245_rd_n = !r_ft245_ingress_stb;
assign o_ft245_oe_n = !r_ft245_output_enable;
assign o_ft245_siwu = !r_ft245_egress_send_now;
assign io_ft245_data = r_ft245_output_enable ? 8'hZZ : (r_ft245_read_tmp_data) ? r_ft245_egress_tmp_data: r_ft245_egress_data;
assign w_ingress_ready = (count < ingress_size) && !((count + 1 == ingress_size) && (byte_count == 3));
//assign ftdi_debug = 32'h0;
assign ftdi_debug[3:0] = state;
assign ftdi_debug[5:4] = ingress_rdy;
assign ftdi_debug[7:6] = ingress_act;
assign ftdi_debug[8] = ingress_stb;
assign ftdi_debug[9] = egress_rdy;
assign ftdi_debug[10] = egress_act;
assign ftdi_debug[11] = w_ingress_ready;
assign ftdi_debug[13:12] = ingress_data[1:0];
assign ftdi_debug[15:14] = egress_data[1:0];
assign ftdi_debug[31:16] = 16'h0;
//synchronous logic
always @ (posedge i_ft245_clk) begin
r_ft245_egress_stb <= 0;
r_ft245_ingress_stb <= 0;
r_ft245_egress_send_now <= 0;
ingress_stb <= 0;
egress_stb <= 0;
if (rst) begin
state <= IDLE;
count <= 0;
byte_count <= 0;
ingress_data <= 0;
r_ft245_output_enable <= 0;
r_ft245_egress_data <= 0;
r_ft245_egress_data_dword <= 0;
r_ft245_ingress_data_dword <= 0;
r_ft245_egress_tmp_data <= 0;
r_ft245_read_tmp_data <= 0;
ingress_act <= 0;
egress_act <= 0;
end
else begin
case (state)
IDLE: begin
count <= 0;
byte_count <= 0;
egress_act <= 1'b0;
r_ft245_output_enable <= 1'b0;
r_ft245_read_tmp_data <= 0;
//If you can grab an incomming FIFO get one
if ((ingress_rdy > 0) && (ingress_act == 2'b00)) begin
if (ingress_rdy[0]) begin
ingress_act[0] <= 1;
end
else begin
ingress_act[1] <= 1;
end
end
//Incomming Data and we have room for it
if (w_ft245_ingress_avail && (ingress_act > 0)) begin
r_ft245_output_enable <= 1;
state <= INGRESS_READ;
end
//Outgoing Data
else if (egress_rdy && !egress_act) begin //Will the chip lock up when it wants to send and I want to send?
egress_act <= 1;
state <= EGRESS_PREPARE;
end
end
INGRESS_READ: begin
if (count < ingress_size) begin
if (r_ft245_ingress_stb && w_ft245_ingress_avail) begin
byte_count <= byte_count + 1;
r_ft245_ingress_data_dword <= {r_ft245_ingress_data_dword[23:0], io_ft245_data};
if (byte_count >= (BYTE_COUNT - 1)) begin
ingress_data <= {r_ft245_ingress_data_dword[23:0], io_ft245_data};
byte_count <= 0;
count <= count + 1;
ingress_stb <= 1;
end
end
if (w_ft245_ingress_avail && !(((count + 1) == ingress_size) && (byte_count == 3))) begin
r_ft245_ingress_stb <= 1;
end
end
else begin
ingress_act <= 0;
state <= IDLE;
end
if (!w_ft245_ingress_avail && (byte_count == 0)) begin
ingress_act <= 0;
state <= IDLE;
end
end
EGRESS_PREPARE: begin
r_ft245_egress_data_dword <= egress_data;
//count <= count + 1;
byte_count <= 0;
if (w_ft245_egress_avail) begin
state <= EGRESS_SEND;
egress_stb <= 1;
end
end
EGRESS_SEND: begin
r_ft245_read_tmp_data <= 0;
r_ft245_egress_data <= r_ft245_egress_data_dword[31:24];
if (w_ft245_egress_avail) begin
if (byte_count < (BYTE_COUNT - 1)) begin
r_ft245_egress_stb <= 1;
r_ft245_egress_data_dword <= {r_ft245_egress_data_dword[23:0], 8'h00};
byte_count <= byte_count + 1;
end
else if (count < egress_size) begin
//Last get the next piece of data
if (count == (egress_size - 1)) begin
egress_act <= 0;
state <= EGRESS_SEND_IMMEDIATELY;
end
r_ft245_egress_data_dword <= egress_data;
count <= count + 1;
byte_count <= 0;
egress_stb <= 1;
r_ft245_egress_stb <= 1;
end
end
else if (!r_ft245_read_tmp_data && egress_act && r_ft245_egress_stb) begin
r_ft245_read_tmp_data <= 1;
r_ft245_egress_tmp_data <= r_ft245_egress_data;
state <= EGRESS_SEND_TEMP_DATA;
end
if (count >= egress_size) begin
egress_act <= 0;
byte_count <= 0;
r_ft245_egress_stb <= 1;
state <= EGRESS_SEND_IMMEDIATELY;
end
end
EGRESS_SEND_TEMP_DATA: begin
if (w_ft245_egress_avail) begin
r_ft245_egress_stb <= 1;
state <= EGRESS_SEND;
end
end
EGRESS_SEND_IMMEDIATELY: begin
if (w_ft245_egress_avail) begin
r_ft245_egress_send_now <= 1;
end
state <= IDLE;
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311O_4_V
`define SKY130_FD_SC_LS__A311O_4_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311o_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311O_4_V
|
#include <bits/stdc++.h> using namespace std; int cal(int a, int b, int ba) { int x[100], xl, y[100], yl, i, z[100]; memset(x, 0, sizeof x); memset(y, 0, sizeof y); memset(z, 0, sizeof z); xl = yl = 0; while (a > 0) { x[xl++] = a % 10; a /= 10; } while (b > 0) { y[yl++] = b % 10; b /= 10; } for (i = 0; i < max(xl, yl); i++) { z[i] += x[i] + y[i]; if (z[i] >= ba) { z[i + 1] += z[i] / ba; z[i] %= ba; } } i = max(xl, yl) + 10; while (z[i] == 0) i--; return i + 1; } int main() { int a, b, i, t, m, ans; while (scanf( %d %d , &a, &b) != EOF) { m = 0; t = a; while (t > 0) { if (t % 10 > m) m = t % 10; t /= 10; } t = b; while (t > 0) { if (t % 10 > m) m = t % 10; t /= 10; } ans = 0; for (i = m + 1; i <= 1000; i++) { t = cal(a, b, i); if (t > ans) ans = t; } printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int mod = 1000000007; const long long int inf = 1e17; const long long int N = 5005; long long int n; long long int a[N]; long long int dp[N][N]; long long int go(long long int idx, long long int flag) { long long int &ans = dp[idx][flag]; if (ans != -1) return ans; if (idx > n) { return 0; } if (flag == 0 or flag == 2) { ans = max(go(idx + 1, flag), go(idx + 1, flag + 1)) + a[idx]; } else { ans = max(go(idx + 1, flag), go(idx + 1, flag + 1)) - a[idx]; } return ans; } vector<long long int> res; void backtrack(long long int idx, long long int flag) { if (idx > n) { return; } if (flag == 0 or flag == 2) { long long int tmp1 = go(idx + 1, flag) + a[idx]; long long int tmp2 = go(idx + 1, flag + 1) + a[idx]; res.push_back(1); if (tmp1 >= tmp2) { backtrack(idx + 1, flag); } else { backtrack(idx + 1, flag + 1); } } else { long long int tmp1 = go(idx + 1, flag) - a[idx]; long long int tmp2 = go(idx + 1, flag + 1) - a[idx]; res.push_back(0); if (tmp1 >= tmp2) { backtrack(idx + 1, flag); } else { backtrack(idx + 1, flag + 1); } } } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); memset(dp, -1, sizeof(dp)); cin >> n; for (long long int i = 1; i <= n; i++) { cin >> a[i]; } long long int ans = go(0, 0); backtrack(0, 0); res.erase(res.begin()); long long int cnt = 0, idx = 0; while (res[idx] and idx < n) { cnt++; idx++; } vector<long long int> vec; vec.push_back(cnt); cnt = 0; idx = vec.back(); while (idx < n and !res[idx]) { cnt++; idx++; } vec.push_back(cnt); idx = vec[0] + vec[1]; cnt = 0; while (idx < n and res[idx]) { cnt++; idx++; } vec.push_back(cnt); idx = 0, cnt = 0; for (auto to : vec) { cnt = to; if (cnt == 0LL) { cout << idx << ; } else { cout << idx + cnt << ; idx += cnt; } } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d%d , &n, &m); printf( %d n , min(n, m) + 1); for (int i = 0; i <= min(n, m); i++) { printf( %d %d n , min(n, m) - i, i); } } |
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("select2.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("select2_tb.vcd");
$dumpvars(0, cpu_tb);
#30
`assert(result, 2);
`assert(result_empty, 0);
$finish;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: clk_ibuf.v
// /___/ /\ Date Last Modified: $Date: 2011/05/27 14:31:02 $
// \ \ / \ Date Created:Mon Aug 3 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module clk_ibuf #
(
parameter INPUT_CLK_TYPE = "DIFFERENTIAL",
// input clock type
parameter DIFF_TERM_SYSCLK = "TRUE"
// Differential Termination
)
(
// Clock inputs
input sys_clk_p, // System clock diff input
input sys_clk_n,
input sys_clk_i,
output mmcm_clk
);
(* KEEP = "TRUE" *) wire sys_clk_ibufg;
generate
if (INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_SYSCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (INPUT_CLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_i),
.O (sys_clk_ibufg)
);
end
endgenerate
assign mmcm_clk = sys_clk_ibufg;
endmodule
|
#include <bits/stdc++.h> int main() { long n, k, a, b, a2 = {0}, a3 = {0}, a5 = {0}, b2 = {0}, b3 = {0}, b5 = {0}; scanf( %d %d , &a, &b); k = 1; while (k == 1) { if (a % 2 == 0) { a = a / 2; a2++; } else k = 0; } k = 1; while (k == 1) { if (a % 3 == 0) { a = a / 3; a3++; } else k = 0; } k = 1; while (k == 1) { if (a % 5 == 0) { a = a / 5; a5++; } else k = 0; } k = 1; while (k == 1) { if (b % 2 == 0) { b = b / 2; b2++; } else k = 0; } k = 1; while (k == 1) { if (b % 3 == 0) { b = b / 3; b3++; } else k = 0; } k = 1; while (k == 1) { if (b % 5 == 0) { b5++; b = b / 5; } else k = 0; } if (a != b) printf( -1 ); else printf( %d , abs(a2 - b2) + abs(a3 - b3) + abs(a5 - b5)); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, s, a, ans, a11, r; vector<long long> aa, ab, c; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> s >> a; if (s == 11) { a11++; ans += a; } if (s == 0) c.push_back(a); if (s == 10) aa.push_back(a); if (s == 1) ab.push_back(a); } sort(aa.begin(), aa.end()); reverse(aa.begin(), aa.end()); sort(ab.begin(), ab.end()); reverse(ab.begin(), ab.end()); r = min(aa.size(), ab.size()); for (int i = r; i < aa.size(); i++) { c.push_back(aa[i]); } for (int i = r; i < ab.size(); i++) { c.push_back(ab[i]); } sort(c.begin(), c.end()); reverse(c.begin(), c.end()); for (int i = 0; i < min(a11, (long long)c.size()); i++) ans += c[i]; for (int i = 0; i < r; i++) { ans += aa[i]; ans += ab[i]; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; if (n % 2 == 0) { n = n / 2; if (n % 2 == 0) cout << 0; else cout << 1; } else { n = (n + 1) / 2; if (n % 2 == 0) cout << 0; else cout << 1; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_hd__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_hd__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
// Module ports
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hd__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, intgate, RESET);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRBN_FUNCTIONAL_V |
#include <bits/stdc++.h> int main(void) { int n, m; scanf( %d %d , &n, &m); long long a[1000 + 1]; long long t[1000 + 1 + 1][1000 + 1]; for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); } for (int j = 0; j <= n; j++) t[n + 1][j] = 0; for (int i = n; i >= 1; i--) { for (int j = 0; j <= n; j++) { t[i][j] = std::min(t[i + 1][j] - a[i], (j > 0) ? t[i + 1][j - 1] : 1LL << 60LL); t[i][j] = std::max(t[i][j], 0LL); } } std::vector<std::pair<long long, int>> values; for (int j = 0; j <= n; j++) { if (j == 0 || t[1][j] != t[1][j - 1]) values.push_back(std::make_pair(t[1][j], j)); } std::sort(values.begin(), values.end()); for (int i = 0; i < m; i++) { long long b; scanf( %lld , &b); auto it = std::lower_bound(values.begin(), values.end(), std::make_pair(b, -1)); if (it == values.end() || it->first > b) it--; printf( %d n , it->second); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; long long n, m, s, t; long long pos[maxn], T[maxn]; long long cal(long long x) { if (s < m) s += t; else s -= t; t--; return (s % n + n) % n; } int main() { cin >> n >> m >> s >> t; s--; while (t % n) s = cal(s); long long temp = t / n; long long tick = 0; while (temp--) { if (pos[s]) { temp %= tick - T[s]; s = pos[s]; } else { T[s] = tick; long long tmp = s; t = n; for (int i = 1; i <= n; i++) s = cal(s); pos[tmp] = s; tick++; } } cout << s + 1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 3005; queue<int> q; vector<int> G[MAXN]; int d[MAXN][MAXN]; bool vis[MAXN]; void bfs(int s) { memset(vis, 0, sizeof(vis)); vis[s] = true; d[s][s] = 0; q.push(s); while (!q.empty()) { int u = q.front(); q.pop(); for (int i = 0; i < G[u].size(); i++) { int v = G[u][i]; if (!vis[v]) { vis[v] = true; d[s][v] = d[s][u] + 1; q.push(v); } } } } int main() { int n, m, s1, t1, l1, s2, t2, l2; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { int a, b; scanf( %d%d , &a, &b); G[a].push_back(b); G[b].push_back(a); } scanf( %d%d%d%d%d%d , &s1, &t1, &l1, &s2, &t2, &l2); for (int i = 1; i <= n; i++) bfs(i); if (d[s1][t1] > l1 || d[s2][t2] > l2) { printf( -1 ); return 0; } int ans = max(0, m - d[s1][t1] - d[s2][t2]); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) { int d1 = d[s1][i] + d[i][j] + d[j][t1], d2 = min(d[s2][i] + d[j][t2], d[s2][j] + d[i][t2]) + d[i][j]; if (d1 <= l1 && d2 <= l2) ans = max(ans, m - d1 - d2 + d[i][j]); } printf( %d , ans); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Cal Poly Pomona
// Engineer: Byron Phung
//
// Create Date: 15:18:15 04/17/2016
// Design Name:
// Module Name: Search
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Search(
input clock,
input reset,
input [511:0] data,
input [511:0] key,
output reg match
);
reg [511:0] data1;
reg [510:0] data2;
reg [509:0] data3;
reg [508:0] data4;
wire [63:0] key1, key2, key3, key4;
reg match1, match2, match3, match4;
reg max_counter = 113;
reg [6:0] counter;
Comparator c1
(
.clock(clock),
.data(data1),
.key(key1),
.match(match1)
);
Comparator c2
(
.clock(clock),
.data(data2),
.key(key2),
.match(match2)
);
Comparator c3
(
.clock(clock),
.data(data3),
.key(key3),
.match(match3)
);
Comparator c4
(
.clock(clock),
.data(data4),
.key(key4),
.match(match4)
);
always @(posedge clock, posedge reset)
begin
if (reset)
begin
counter <= 0;
data1 <= data;
data2 <= data[511:1];
data3 <= data[511:2];
data4 <= data[511:3];
end
else
begin
if (counter == max_counter)
begin
counter <= 0;
data1 <= data;
data2 <= data[511:1];
data3 <= data[511:2];
data4 <= data[511:3];
end
else
begin
counter <= counter + 1;
data1 <= data1 << 1;
data2 <= data2 << 1;
data3 <= data3 << 1;
data4 <= data4 << 1;
end
if (match1 || match2 || match3 || match4)
match <= 1;
else
match <= 0;
end
end
endmodule
|
/* Generated by Yosys 0.5 (git sha1 c3c9fbf, gcc 4.8.2-19ubuntu1 -O2 -fstack-protector -fPIC -Os) */
(* top = 1 *)
(* src = "test.v:1" *)
module dffr_17(q, d, clk, reset);
(* src = "test.v:5" *)
input clk;
(* src = "test.v:4" *)
input [16:0] d;
(* src = "test.v:3" *)
output [16:0] q;
(* src = "test.v:5" *)
input reset;
DFFSR _00_ (
.CLK(clk),
.D(d[0]),
.Q(q[0]),
.R(reset),
.S(1'b1)
);
DFFSR _01_ (
.CLK(clk),
.D(d[1]),
.Q(q[1]),
.R(reset),
.S(1'b1)
);
DFFSR _02_ (
.CLK(clk),
.D(d[2]),
.Q(q[2]),
.R(reset),
.S(1'b1)
);
DFFSR _03_ (
.CLK(clk),
.D(d[3]),
.Q(q[3]),
.R(reset),
.S(1'b1)
);
DFFSR _04_ (
.CLK(clk),
.D(d[4]),
.Q(q[4]),
.R(reset),
.S(1'b1)
);
DFFSR _05_ (
.CLK(clk),
.D(d[5]),
.Q(q[5]),
.R(reset),
.S(1'b1)
);
DFFSR _06_ (
.CLK(clk),
.D(d[6]),
.Q(q[6]),
.R(reset),
.S(1'b1)
);
DFFSR _07_ (
.CLK(clk),
.D(d[7]),
.Q(q[7]),
.R(reset),
.S(1'b1)
);
DFFSR _08_ (
.CLK(clk),
.D(d[8]),
.Q(q[8]),
.R(reset),
.S(1'b1)
);
DFFSR _09_ (
.CLK(clk),
.D(d[9]),
.Q(q[9]),
.R(reset),
.S(1'b1)
);
DFFSR _10_ (
.CLK(clk),
.D(d[10]),
.Q(q[10]),
.R(reset),
.S(1'b1)
);
DFFSR _11_ (
.CLK(clk),
.D(d[11]),
.Q(q[11]),
.R(reset),
.S(1'b1)
);
DFFSR _12_ (
.CLK(clk),
.D(d[12]),
.Q(q[12]),
.R(reset),
.S(1'b1)
);
DFFSR _13_ (
.CLK(clk),
.D(d[13]),
.Q(q[13]),
.R(reset),
.S(1'b1)
);
DFFSR _14_ (
.CLK(clk),
.D(d[14]),
.Q(q[14]),
.R(reset),
.S(1'b1)
);
DFFSR _15_ (
.CLK(clk),
.D(d[15]),
.Q(q[15]),
.R(reset),
.S(1'b1)
);
DFFSR _16_ (
.CLK(clk),
.D(d[16]),
.Q(q[16]),
.R(reset),
.S(1'b1)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD7 = 1e9 + 7; const int MOD9 = 1e9 + 9; const double EPS = 1e-9; long long int gcd(long long int a, long long int b) { return b == 0 ? a : gcd(b, a % b); } int toint(const string &s) { stringstream second; second << s; int x; second >> x; return x; } long long int mpow(long long int a, long long int n, int mod) { long long int ret = 1; long long int b = a; while (n) { if (n & 1) ret = (ret * b) % mod; b = (b * b) % mod; n >>= 1; } return (long long int)ret; } struct cmp { bool operator()(pair<pair<int, int>, int> a, pair<pair<int, int>, int> b) { if (a.first.first < b.first.first) return true; else if (a.first.first == b.first.first) return a.first.second < b.first.second; return false; } }; map<int, int> hashm; vector<pair<int, int> > coordy, v; int main() { int tc; tc = 1; int i, n, m, k, a, b, c, d, u, w, sum, permissible, j; long long minl = 0, areamin = (long long int)9223372036854775805; int pfor[13] = {0}, pback[13] = {0}; while (tc--) { scanf( %d , &n); scanf( %d , &k); for (i = 0; i < n; i++) { scanf( %d , &a); scanf( %d , &b); scanf( %d , &c); scanf( %d , &d); coordy.push_back(make_pair(b + d, a + c)); hashm[a + c]++; } m = 0; for (map<int, int>::iterator it = hashm.begin(); it != hashm.end(); ++it) { v.push_back(make_pair(it->second, it->first)); } m = v.size(); for (i = 0; i < k; i++) pfor[i + 1] = pfor[i] + v[i].first; for (i = 0; i < k; i++) pback[i + 1] = pback[i] + v[m - 1 - i].first; sort(coordy.begin(), coordy.end()); for (i = 0; i <= k; i++) { for (j = 0; j <= k; j++) { if (i <= m - 1 - j && v[i].second <= v[m - 1 - j].second && pfor[i] + pback[j] <= k) { u = 0; w = 0; sum = 0; permissible = n - k; minl = 2 * MOD9; while (u <= w && w < n) { if (coordy[w].second >= v[i].second && coordy[w].second <= v[m - 1 - j].second) sum++; while (sum >= permissible && coordy[w].first >= coordy[u].first) { if (coordy[w].first > coordy[u].first) minl = min(minl, (long long int)(coordy[w].first - coordy[u].first)); else minl = min(minl, (long long int)2); if (coordy[u].second >= v[i].second && coordy[u].second <= v[m - 1 - j].second) sum--; u++; } w++; } if (minl != MOD9 * 2 && v[m - 1 - j].second != v[i].second) areamin = min(areamin, (long long int)minl * (v[m - 1 - j].second - v[i].second)); else if (minl != MOD9 * 2 && v[m - 1 - j].second == v[i].second) areamin = min(areamin, (long long int)minl * 2); } } } if (n == 1 || (areamin / 4) == 0) printf( 1 n ); else printf( %lld n , areamin / 4); } return 0; } |
// generated by newgenasym Mon Jan 25 15:49:40 2016
module \atsam3u1cb-au (ad12bvref, advref, dfsdm, dfsdp, dhsdm, dhsdp, erase, fwup,
gnd1, gnd2, gnd3, gndana, gndbu, gndpll, gndutmi, jtagsel,
nrst, nrstb, \pa0/pgmncmd , \pa1/pgmrdy , \pa10/pgmd2 ,
\pa11/pgmd3 , \pa12/pgmd4 , \pa13/pgmd5 , \pa14/pgmd6 ,
\pa15/pgmd7 , \pa16/pgmd8 , \pa17/pgmd9 , \pa18/pgmd10 ,
\pa19/pgmd11 , \pa2/pgmnoe , \pa20/pgmd12 , \pa21/pgmd13 ,
\pa22/pgmd14 , \pa23/pgmd15 , pa24, pa25, pa26, pa27, pa28, pa29,
\pa3/pgmnvalid , pa30, pa31, \pa4/pgmm0 , \pa5/pgmm1 , \pa6/pgmm2 ,
\pa7/pgmm3 , \pa8/pgmd0 , \pa9/pgmd1 , pb0, pb1, pb10, pb11, pb12,
pb13, pb14, pb15, pb16, pb17, pb18, pb19, pb2, pb20, pb21, pb22,
pb23, pb24, pb3, pb4, pb5, pb6, pb7, pb8, pb9, \tck/swclk , tdi,
\tdo/traceswo , \tms/swdio , tst, vbg, vddana, vddbu, vddcore1,
vddcore2, vddcore3, vddcore4, vddcore5, vddin, vddio1,
vddio2, vddio3, vddio4, vddout, vddpll, vddutmi, xin, xin32,
xout, xout32);
inout ad12bvref;
inout advref;
inout dfsdm;
inout dfsdp;
inout dhsdm;
inout dhsdp;
inout erase;
inout fwup;
inout gnd1;
inout gnd2;
inout gnd3;
inout gndana;
inout gndbu;
inout gndpll;
inout gndutmi;
inout jtagsel;
inout nrst;
inout nrstb;
inout \pa0/pgmncmd ;
inout \pa1/pgmrdy ;
inout \pa10/pgmd2 ;
inout \pa11/pgmd3 ;
inout \pa12/pgmd4 ;
inout \pa13/pgmd5 ;
inout \pa14/pgmd6 ;
inout \pa15/pgmd7 ;
inout \pa16/pgmd8 ;
inout \pa17/pgmd9 ;
inout \pa18/pgmd10 ;
inout \pa19/pgmd11 ;
inout \pa2/pgmnoe ;
inout \pa20/pgmd12 ;
inout \pa21/pgmd13 ;
inout \pa22/pgmd14 ;
inout \pa23/pgmd15 ;
inout pa24;
inout pa25;
inout pa26;
inout pa27;
inout pa28;
inout pa29;
inout \pa3/pgmnvalid ;
inout pa30;
inout pa31;
inout \pa4/pgmm0 ;
inout \pa5/pgmm1 ;
inout \pa6/pgmm2 ;
inout \pa7/pgmm3 ;
inout \pa8/pgmd0 ;
inout \pa9/pgmd1 ;
inout pb0;
inout pb1;
inout pb10;
inout pb11;
inout pb12;
inout pb13;
inout pb14;
inout pb15;
inout pb16;
inout pb17;
inout pb18;
inout pb19;
inout pb2;
inout pb20;
inout pb21;
inout pb22;
inout pb23;
inout pb24;
inout pb3;
inout pb4;
inout pb5;
inout pb6;
inout pb7;
inout pb8;
inout pb9;
inout \tck/swclk ;
inout tdi;
inout \tdo/traceswo ;
inout \tms/swdio ;
inout tst;
inout vbg;
inout vddana;
inout vddbu;
inout vddcore1;
inout vddcore2;
inout vddcore3;
inout vddcore4;
inout vddcore5;
inout vddin;
inout vddio1;
inout vddio2;
inout vddio3;
inout vddio4;
inout vddout;
inout vddpll;
inout vddutmi;
inout xin;
inout xin32;
inout xout;
inout xout32;
initial
begin
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int64_t v[200005] = {0}; int64_t fnc(int64_t h, int n) { int64_t mn = v[0]; for (int i = 1; i < n; i++) { v[i] += v[i - 1]; mn = min(mn, v[i]); } if (v[n - 1] >= 0 && h + mn > 0) return -1; int64_t ans = 0; if (h + mn <= 0) { for (int i = 0; i < n; i++) if (h + v[i] <= 0) return i + 1; } int64_t t = ceil(((-mn - h) * 1.0) / v[n - 1]); if (t < 0) t = 0; ans += n * t; h = h + t * v[n - 1]; for (int i = 0; i < n; i++) { if (h + v[i] <= 0) { ans += i + 1; break; } } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int m; int64_t h; cin >> h >> m; for (int i = 0; i < m; i++) cin >> v[i]; cout << fnc(h, m) << endl; return 0; } |
//--------------------------------------------------------------------------------
// Project : SWITCH
// File : sync_block.v
// Version : 0.2
// Author : Shreejith S
//
// Description: Clock Domain Crossing Synchronisation - XILINX
//
//
//-----------------------------------------------------------------------------
//
// (c) Copyright 2001-2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//------------------------------------------------------------------------------
// Description: Used on signals crossing from one clock domain to
// another, this is a flip-flop pair, with both flops
// placed together with RLOCs into the same slice. Thus
// the routing delay between the two is minimum to safe-
// guard against metastability issues.
`timescale 1ps / 1ps
module sync_block #(
parameter INITIALISE = 2'b00
)
(
input clk, // clock to be sync'ed to
input data_in, // Data to be 'synced'
output data_out // synced data
);
// Internal Signals
wire data_sync1;
wire data_sync2;
(* ASYNC_REG = "TRUE", RLOC = "X0Y0" *)
FD #(
.INIT (INITIALISE[0])
) data_sync (
.C (clk),
.D (data_in),
.Q (data_sync1)
);
(* RLOC = "X0Y0" *)
FD #(
.INIT (INITIALISE[1])
) data_sync_reg (
.C (clk),
.D (data_sync1),
.Q (data_sync2)
);
assign data_out = data_sync2;
endmodule
|
// -- (c) Copyright 2016 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
`timescale 1ps/1ps
module tdata_design_1_axis_broadcaster_0_0 #
(
parameter C_S_AXIS_TDATA_WIDTH = 8,
parameter C_M_AXIS_TDATA_WIDTH = 8
)
(
input wire [C_S_AXIS_TDATA_WIDTH-1:0] tdata,
output wire [C_M_AXIS_TDATA_WIDTH-1:0] tdata_out
);
assign tdata_out = {tdata[7:0],tdata[7:0]};
endmodule
|
`timescale 1ns / 1ps
`include "asserts.vh"
module tx_top_v();
reg [11:0] story_tb;
reg clk, reset;
reg [7:0] dat_i;
reg lchar_i, valid_i;
wire d_o, s_o, ready_o;
tx_top top(
.txClk(clk),
.txReset(reset),
.dat_i(dat_i),
.lchar_i(lchar_i),
.valid_i(valid_i),
.d(d_o),
.s(s_o),
.ready_o(ready_o)
);
`DEFIO(clk,H,L)
`DEFASSERT0(d,o)
`DEFASSERT0(s,o)
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
// Make sure that the S signal is stable between characters.
story_tb <= 12'h000;
{clk, valid_i, lchar_i, dat_i} <= 0;
reset <= 1;
clkL(); clkH();
reset <= 0;
clkL(); clkH();
dat_i <= 8'h02;
lchar_i <= 1;
valid_i <= 1;
clkL(); clkH();
assert_d(0); assert_s(0);
story_tb <= 12'h001;
valid_i <= 0;
clkL(); clkH(); // Drives Tx pins during this cycle...
story_tb <= 12'hFFF;
clkL(); clkH(); // ... which should appear at D/S now.
assert_d(0); assert_s(1); // Parity
story_tb <= 12'hFFE;
clkL(); clkH();
assert_d(1); assert_s(1); // LChar flag
story_tb <= 12'h002;
clkL(); clkH();
assert_d(0); assert_s(1); // D0a
story_tb <= 12'h003;
clkL(); clkH();
assert_d(1); assert_s(1); // D1a
story_tb <= 12'h004;
dat_i <= 8'h00;
valid_i <= 1;
lchar_i <= 1;
clkL(); clkH();
assert_d(1); assert_s(1); // D/S stable
story_tb <= 12'h005;
valid_i <= 0;
lchar_i <= 0;
clkL(); clkH();
clkL(); clkH();
assert_d(1); assert_s(0); // Parity
story_tb <= 12'h006;
clkL(); clkH();
assert_d(1); assert_s(1); // LChar flag
story_tb <= 12'h007;
clkL(); clkH();
assert_d(0); assert_s(1); // D0b
story_tb <= 12'h008;
clkL(); clkH();
assert_d(0); assert_s(0); // D1b
$display("@I Done.");
$stop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVKAPWR_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__INVKAPWR_PP_BLACKBOX_V
/**
* invkapwr: Inverter on keep-alive power rail.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__invkapwr (
Y ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVKAPWR_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111A_TB_V
`define SKY130_FD_SC_MS__O2111A_TB_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2111a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__o2111a dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111A_TB_V
|
#include <bits/stdc++.h> using namespace std; using cd = complex<double>; const int Inf = 1000000007; const long long mod = 1000000007; const double Pi = acos(-1); void Fastio() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); } int n, t, ans = 0; long long res = 0; int Co[4], Color[100005], a[100005]; vector<int> Adj[100005]; map<int, long long> C; int main() { Fastio(); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int j = 2; j <= n; j++) { int temp; cin >> temp; Adj[temp].emplace_back(j); Adj[j].emplace_back(temp); } queue<int> BFS; BFS.push(1); Co[1] = 1; Color[1] = 1; while (BFS.empty() == false) { int node = BFS.front(); for (auto x : Adj[node]) { if (!Color[x]) { Color[x] = 3 - Color[node]; Co[Color[x]]++; BFS.push(x); } } BFS.pop(); } for (int i = 1; i <= n; i++) { if (Adj[i].size() == 1 and i != 1) { t = Color[i]; break; } } t = 3 - t; for (int i = 1; i <= n; i++) { if (Color[i] == 3 - t) { ans ^= a[i]; C[a[i]]++; } } if (ans == 0) { res += 1ll * Co[3 - t] * (Co[3 - t] - 1) / 2; res += 1ll * Co[t] * (Co[t] - 1) / 2; } for (int i = 1; i <= n; i++) { if (Color[i] == t) { res += C[a[i] ^ ans]; } } cout << res; } |
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-9; const int INF = 2147483647; const long long LLINF = 9223372036854775807LL; template <class T> T gcd(T a, T b) { if (a < b) swap(a, b); if (b == 0) return a; return gcd(b, a % b); } template <class T> T lcm(T a, T b) { return (a * b) / gcd(a, b); } int dp[510001]; int main() { int d, n; cin >> n >> d; vector<int> c(n); for (int i = 0; i < (n); i++) cin >> c[i]; for (int i = 0; i < (n); i++) { for (int j = (510000); j >= (c[i]); j--) { dp[j] = max(dp[j], c[i] + dp[j - c[i]]); } } int ans = 0, lAns = -1, days = -1; while (ans != lAns) { lAns = ans; ans = dp[ans + d]; days++; } if (ans == 0) cout << 0 << << 0 << endl; else cout << ans << << days << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; namespace LYYY { int read() { int s = 0; char c = getchar(); int f = 1; while (c < 48 || c > 57) { if (c == 45) f = -1; c = getchar(); } while (c >= 48 && c <= 57) s = (s << 3) + (s << 1) + (c ^ 48), c = getchar(); return s * f; } long long readl() { long long s = 0; char c = getchar(); int f = 1; while (c < 48 || c > 57) { if (c == 45) f = -1; c = getchar(); } while (c >= 48 && c <= 57) s = (s << 3) + (s << 1) + (c ^ 48), c = getchar(); return s * f; } void write(int x) { if (x >= 10) write(x / 10); putchar(x % 10 + 48); } void W(int x) { if (x < 0) x = -x, putchar(45); write(x); } void writel(long long x) { if (x >= 10) write(x / 10); putchar(x % 10 + 48); } void Wl(long long x) { if (x < 0) x = -x, putchar(45); write(x); } } // namespace LYYY using namespace LYYY; const int mod = 1000 * 1000 * 1000 + 7; int mul(int x, long long k) { long long ans = 1, mid = x; while (k) { if (k & 1) ans = ans * mid % mod; mid = mid * mid % mod; k >>= 1; } return ans; } int Get(long long n, int x) { if (n < x) return 1; return (long long)mul(x, n / x) * Get(n / x, x) % mod; } int main() { int x = read(); long long n = readl(), ans = 1; for (int i = 2; i * i <= x; ++i) if (x % i == 0) { ans = ans * Get(n, i) % mod; while (x % i == 0) x /= i; } if (x > 1) ans = ans * Get(n, x) % mod; writel(ans); return 0; } |
module fifo # (parameter abits = 20, dbits = 8)(
input reset, clock,
input rd, wr,
input [dbits-1:0] din,
output [dbits-1:0] dout,
output empty,
output full,
output reg ledres
);
wire db_wr;
wire db_rd;
reg dffw1, dffr1;
reg [dbits-1:0] out;
initial ledres = 0;
reg [1:0] count;
reg [1:0] count1;
//always @ (posedge clock) dffw1 <= ~wr;
//always @ (posedge clock) dffw2 <= rd;
assign db_wr = dffw1; //monostable multivibrator to detect only one pulse of the button
//always @ (posedge clock) dffr1 <= rd;
//always @ (posedge clock) dffr2 <= dffr1;
assign db_rd = dffr1; //monostable multivibrator to detect only one pulse of the button
reg [dbits-1:0] regarray[2**abits-1:0]; //number of words in fifo = 2^(number of address bits)
reg [abits-1:0] wr_reg, wr_next, wr_succ; //points to the register that needs to be written to
reg [abits-1:0] rd_reg, rd_next, rd_succ; //points to the register that needs to be read from
reg full_reg, empty_reg, full_next, empty_next;
assign wr_en = db_wr & ~full; //only write if write signal is high and fifo is not full
always @ (posedge clock)//only write
begin
if(wr && ~rd)
begin
if(count)
begin
//dffr1<=0;
dffw1<=0;
count<=count+1;
end
else
begin
//dffr1<=0;
dffw1<=1;
count<=0;
end
end
else dffw1<=0;
end
always @ (posedge clock)//only read
begin
if(rd && ~wr)
begin
if(count1)
begin
//dffw1<=0;
dffr1<=0;
count1<=count1+1;
end
else
begin
//dffw1<=0;
dffr1<=1;
count1<=0;
end
end
else dffr1<=0;
end
//always block for write operation
always @ (posedge clock)
begin
if(wr_en)
regarray[wr_reg] <= din; //at wr_reg location of regarray store what is given at din
end
//always block for read operation
always @ (posedge clock)
begin
if(db_rd)
out <= regarray[rd_reg];
end
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
wr_reg <= 0;
rd_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
ledres=0;
end
else
begin
wr_reg <= wr_next; //created the next registers to avoid the error of mixing blocking and non blocking assignment to the same signal
rd_reg <= rd_next;
full_reg <= full_next;
empty_reg <= empty_next;
ledres=1;
end
end
always @(clock)
begin
wr_succ = wr_reg + 1; //assigned to new value as wr_next cannot be tested for in same always block
rd_succ = rd_reg + 1; //assigned to new value as rd_next cannot be tested for in same always block
wr_next = wr_reg; //defaults state stays the same
rd_next = rd_reg; //defaults state stays the same
full_next = full_reg; //defaults state stays the same
empty_next = empty_reg; //defaults state stays the same
case({db_wr,db_rd})
//2'b00: do nothing LOL..
2'b01: //read
begin
if(~empty) //if fifo is not empty continue
begin
rd_next = rd_succ;
full_next = 1'b0;
if(rd_succ == wr_reg) //all data has been read
empty_next = 1'b1; //its empty again
end
end
2'b10: //write
begin
if(~full) //if fifo is not full continue
begin
wr_next = wr_succ;
empty_next = 1'b0;
if(wr_succ == (2**abits-1)) //all registers have been written to
full_next = 1'b1; //its full now
end
end
2'b11: //read and write
begin
wr_next = wr_succ;
rd_next = rd_succ;
end
//no empty or full flag will be checked for or asserted in this state since data is being written to and read from together it can not get full in this state.
endcase
end
assign full = full_reg;
assign empty = empty_reg;
assign dout = out;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3_BEHAVIORAL_V
`define SKY130_FD_SC_LS__OR3_BEHAVIORAL_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__or3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A, C );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3_BEHAVIORAL_V |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 23801 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w1024,
w1023,
w16384,
w15361,
w256,
w15617,
w8184,
w23801;
assign w1 = i_data0;
assign w1023 = w1024 - w1;
assign w1024 = w1 << 10;
assign w15361 = w16384 - w1023;
assign w15617 = w15361 + w256;
assign w16384 = w1 << 14;
assign w23801 = w15617 + w8184;
assign w256 = w1 << 8;
assign w8184 = w1023 << 3;
assign o_data0 = w23801;
//multiplier_block area estimate = 6602.90402074559;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_engine.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The tx_engine module takes a formatted header, number of alignment
// blanks and a payloa and concatenates all three (in that order) to form a
// packet. These packets must meet max-request, max-payload, and payload
// termination requirements (see Read Completion Boundary). The tx_engine does
// not check these requirements during operation, but may do so during simulation.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_engine
#(parameter C_DATA_WIDTH = 128,
parameter C_DEPTH_PACKETS = 10,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_FORMATTER_DELAY = 1,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: TX HDR
input TX_HDR_VALID,
input [C_MAX_HDR_WIDTH-1:0] TX_HDR,
input [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
input TX_HDR_NOPAYLOAD,
output TX_HDR_READY,
// Interface: TX_DATA
input TX_DATA_VALID,
input [C_DATA_WIDTH-1:0] TX_DATA,
input TX_DATA_START_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_START_OFFSET,
input TX_DATA_END_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_END_OFFSET,
output TX_DATA_READY,
// Interface: TX_PKT
input TX_PKT_READY,
output [C_DATA_WIDTH-1:0] TX_PKT,
output TX_PKT_START_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET,
output TX_PKT_END_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET,
output TX_PKT_VALID
);
`include "functions.vh"
localparam C_PIPELINE_HDR_FIFO_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_HDR_FIFO_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_PIPELINE_HDR_INPUT = C_PIPELINE_INPUT;
localparam C_ACTUAL_HDR_FIFO_DEPTH = clog2s(C_DEPTH_PACKETS);
localparam C_USE_COMPUTE_REG = 1;
localparam C_USE_READY_REG = 1;
localparam C_USE_FWFT_HDR_FIFO = 1;
localparam C_DATA_FIFO_DEPTH = C_ACTUAL_HDR_FIFO_DEPTH + C_FORMATTER_DELAY +
C_PIPELINE_HDR_FIFO_INPUT + C_PIPELINE_HDR_FIFO_OUTPUT + C_USE_FWFT_HDR_FIFO + // Header Fifo
C_PIPELINE_HDR_INPUT + C_USE_COMPUTE_REG + C_USE_READY_REG + C_PIPELINE_OUTPUT; // Aligner
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNoPayload;
wire wTxDataReady;
wire [C_DATA_WIDTH-1:0] wTxData;
wire [clog2s(C_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
wire wTxDataStartFlag;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordValid;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordReady;
tx_data_pipeline
#(
.C_MAX_PAYLOAD (C_MAX_PAYLOAD_DWORDS*32),
.C_DEPTH_PACKETS (C_DATA_FIFO_DEPTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
tx_data_pipeline_inst
(
// Outputs
.RD_TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
.RD_TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_START_FLAG (wTxDataStartFlag),
.RD_TX_DATA_END_FLAGS (wTxDataEndFlags[(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_READY (TX_DATA_READY),
// Inputs
.RD_TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA (TX_DATA),
.WR_TX_DATA_VALID (TX_DATA_VALID),
.WR_TX_DATA_START_FLAG (TX_DATA_START_FLAG),
.WR_TX_DATA_START_OFFSET (TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_END_FLAG (TX_DATA_END_FLAG),
.WR_TX_DATA_END_OFFSET (TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Header Fifo
tx_hdr_fifo
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_HDR_FIFO_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_HDR_FIFO_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_ACTUAL_HDR_FIFO_DEPTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_VENDOR (C_VENDOR))
txhf_inst
(
// Outputs
.WR_TX_HDR_READY (TX_HDR_READY),
.RD_TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.RD_TX_HDR_VALID (wTxHdrValid),
.RD_TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
.RD_TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.RD_TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.RD_TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.WR_TX_HDR (TX_HDR[C_MAX_HDR_WIDTH-1:0]),
.WR_TX_HDR_VALID (TX_HDR_VALID),
.WR_TX_HDR_NOPAYLOAD (TX_HDR_NOPAYLOAD),
.WR_TX_HDR_PAYLOAD_LEN (TX_HDR_PAYLOAD_LEN[`SIG_LEN_W-1:0]),
.WR_TX_HDR_NONPAY_LEN (TX_HDR_NONPAY_LEN[`SIG_NONPAY_W-1:0]),
.WR_TX_HDR_PACKET_LEN (TX_HDR_PACKET_LEN[`SIG_PACKETLEN_W-1:0]),
.RD_TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Header Fifo
tx_alignment_pipeline
#(
// Parameters
.C_PIPELINE_OUTPUT (1),
.C_PIPELINE_DATA_INPUT (1),
.C_PIPELINE_HDR_INPUT (C_PIPELINE_HDR_INPUT),
.C_DATA_WIDTH (C_DATA_WIDTH),
// Parameters
/*AUTOINSTPARAM*/
// Parameters
.C_USE_COMPUTE_REG (C_USE_COMPUTE_REG),
.C_USE_READY_REG (C_USE_READY_REG),
.C_VENDOR (C_VENDOR))
tx_alignment_inst
(
// Outputs
.TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
.TX_HDR_READY (wTxHdrReady),
.TX_PKT (TX_PKT[C_DATA_WIDTH-1:0]),
.TX_PKT_VALID (TX_PKT_VALID),
.TX_PKT_START_FLAG (TX_PKT_START_FLAG),
.TX_PKT_START_OFFSET (TX_PKT_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (TX_PKT_END_FLAG),
.TX_PKT_END_OFFSET (TX_PKT_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
// Inputs
.TX_DATA_START_FLAG (wTxDataStartFlag),
.TX_DATA_END_FLAGS (wTxDataEndFlags),
.TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
.TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_PKT_READY (TX_PKT_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int i; map<string, string> mp1to2; map<string, string> mp2to1; map<string, int> mp1p; map<string, int> mp2p; for (i = 1; i <= m; i++) { string w1, w2; cin >> w1 >> w2; mp1to2[w1] = w2; mp2to1[w2] = w1; mp1p[w1]++; mp2p[w2]++; } for (i = 1; i <= n; i++) { string word; cin >> word; if (mp1p[word] > 0) { int len1 = word.length(); int len2 = mp1to2[word].length(); if (len1 <= len2) { printf( %s , word.c_str()); } else { printf( %s , mp1to2[word].c_str()); } } else { int len1 = mp2to1[word].length(); int len2 = word.length(); if (len1 <= len2) { printf( %s , mp2to1[word].c_str()); } else { printf( %s , word.c_str()); } } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_2_V
`define SKY130_FD_SC_LS__AND2B_2_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog wrapper for and2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and2b_2 (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and2b base (
.X(X),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and2b_2 (
X ,
A_N,
B
);
output X ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and2b base (
.X(X),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_2_V
|
#include <bits/stdc++.h> using namespace std; int mod = 1e9 + 7; int f[105][105][105], len[105], n, m; char s[105]; int qpow(int x, int y) { int res = 1; while (y) { if (y % 2) res = 1ll * res * x % mod; x = 1ll * x * x % mod; y /= 2; } return res; } int dfs(int x, int l, int r) { if (f[x][l][r] != -1) return f[x][l][r]; if (x <= 1) return (l == r) && (s[l] == (x + 0 )); int cnt = 0; cnt = (cnt + 1ll * dfs(x - 1, l, r) * ((r == n) ? qpow(2, len[x - 2]) : 1) % mod) % mod; cnt = (cnt + 1ll * dfs(x - 2, l, r) * ((l == 1) ? qpow(2, len[x - 1]) : 1) % mod) % mod; for (int k = l; k < r; k++) cnt = (cnt + 1ll * dfs(x - 1, l, k) * dfs(x - 2, k + 1, r) % mod) % mod; return f[x][l][r] = cnt; } int main() { ios_base::sync_with_stdio(false); cin >> n >> m; memset(f, -1, sizeof(f)); len[1] = 1; len[0] = 1; for (int i = 2; i <= m; i++) len[i] = (len[i - 1] + len[i - 2]) % (mod - 1); cin >> s + 1; printf( %d n , dfs(m, 1, n)); } |
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM64X1S #(
.INIT(64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000010)
) ram3 (
.WCLK (clk),
.A5 (sw[5]),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[3]),
.D (sw[14]),
.WE (sw[15])
);
RAM64X1S #(
.INIT(64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000010)
) ram4 (
.WCLK (clk),
.A5 (sw[5]),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[2]),
.D (sw[13]),
.WE (sw[15])
);
RAM64X1S #(
.INIT(64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000010)
) ram1 (
.WCLK (clk),
.A5 (sw[5]),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[1]),
.D (sw[12]),
.WE (sw[15])
);
RAM64X1S #(
.INIT(64'b00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000010)
) ram2 (
.WCLK (clk),
.A5 (sw[5]),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.O (led[0]),
.D (sw[11]),
.WE (sw[15])
);
assign led[15:4] = sw[15:4];
assign tx = rx;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 105; int answer[N][4]; int main() { int n, m; cin >> n >> m; int k = 0; for (int i = 1; i <= n; ++i) { if (k == m) break; answer[i][0] = ++k; if (k == m) break; answer[i][3] = ++k; } for (int i = 1; i <= n; ++i) { if (k == m) break; answer[i][1] = ++k; if (k == m) break; answer[i][2] = ++k; } for (int i = 1; i <= n; ++i) { if (answer[i][1]) cout << answer[i][1] << ; if (answer[i][0]) cout << answer[i][0] << ; if (answer[i][2]) cout << answer[i][2] << ; if (answer[i][3]) cout << answer[i][3] << ; } } |
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_broadcast
*/
module test_axis_broadcast_4;
// Parameters
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_broadcast_4.lxt");
$dumpvars(0, test_axis_broadcast_4);
end
axis_broadcast #(
.M_COUNT(M_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI outputs
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 2; void testCase() { int n, k, cnt = 0, ans = 1, s = 0; scanf( %d%d , &n, &k); vector<int> a(n), fr(101), z(101); for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); if (fr[a[i]]++ == 0) ++cnt, ++s; if (cnt == k + 1) cnt = 2, ans++; } if (s >= 2 && k == 1) { puts( -1 ); return; } cout << ans << endl; } int main() { int T = 1; scanf( %d , &T); while (T--) { testCase(); } } |
#include <bits/stdc++.h> using namespace std; const long long maxN = 1e6 + 5; const long long inf = 1e10; const long long mod = 1e9 + 7; long long n; long long x[maxN]; long long a, b; int main() { ios_base::sync_with_stdio(0); cin >> n; for (long long i = 1; i <= n; i++) cin >> x[i]; cin >> a >> b; sort(x + 1, x + 1 + n); n = unique(x + 1, x + 1 + n) - (x + 1); long long res = 0; while (a > b) { long long next = a - 1; for (long long i = 1; i <= n; i++) { long long tmp = a - a % x[i]; if (tmp < b) { x[i--] = x[--n]; } else if (tmp < next) next = tmp; } a = next; res++; } cout << res; return 0; } |
// Fetch-Issue Pipeline Register
module iss_pipe_reg
(
input wire clk,
input wire reset,
input wire clr,
input wire enable, // Active Low enable signal
input wire[31:0] next_pc_iss_pipe_reg_i,
input wire[31:0] instr_iss_pipe_reg_i,
input wire brn_pred_iss_pipe_reg_i,
input wire[31:0] curr_pc_iss_pipe_reg_i,
input wire[31:0] next_pred_pc_iss_pipe_reg_i,
output wire[31:0] next_pc_iss_pipe_reg_o,
output wire[31:0] instr_iss_pipe_reg_o,
output wire brn_pred_iss_pipe_reg_o,
output wire[31:0] curr_pc_iss_pipe_reg_o,
output wire[31:0] next_pred_pc_iss_pipe_reg_o
);
reg [31:0] next_pc_iss_pipe_reg;
reg [31:0] instr_iss_pipe_reg;
reg brn_pred_iss_pipe_reg;
reg [31:0] curr_pc_iss_pipe_reg;
reg [31:0] next_pred_pc_iss_pipe_reg;
assign next_pc_iss_pipe_reg_o = next_pc_iss_pipe_reg;
assign instr_iss_pipe_reg_o = instr_iss_pipe_reg;
assign brn_pred_iss_pipe_reg_o = brn_pred_iss_pipe_reg;
assign curr_pc_iss_pipe_reg_o = curr_pc_iss_pipe_reg;
assign next_pred_pc_iss_pipe_reg_o = next_pred_pc_iss_pipe_reg;
always @(posedge clk or posedge reset)
if (reset | clr)
begin
next_pc_iss_pipe_reg <= 31'b0;
instr_iss_pipe_reg <= 31'b0;
brn_pred_iss_pipe_reg <= 31'b0;
curr_pc_iss_pipe_reg <= 31'b0;
next_pred_pc_iss_pipe_reg <= 31'b0;
end
else if (~enable)
begin
next_pc_iss_pipe_reg <= next_pc_iss_pipe_reg_i;
instr_iss_pipe_reg <= instr_iss_pipe_reg_i;
brn_pred_iss_pipe_reg <= brn_pred_iss_pipe_reg_i;
curr_pc_iss_pipe_reg <= curr_pc_iss_pipe_reg_i;
next_pred_pc_iss_pipe_reg <= next_pred_pc_iss_pipe_reg_i;
end
endmodule
|
/*
########################################################################
Generic Clock Domain Crossing Block
########################################################################
*/
module fifo_cdc (/*AUTOARG*/
// Outputs
wait_out, access_out, packet_out,
// Inputs
clk_in, reset_in, access_in, packet_in, clk_out, reset_out,
wait_in
);
parameter DW = 104;
parameter DEPTH = 32;
/********************************/
/*Incoming Packet */
/********************************/
input clk_in;
input reset_in;
input access_in;
input [DW-1:0] packet_in;
output wait_out;
/********************************/
/*Outgoing Packet */
/********************************/
input clk_out;
input reset_out;
output access_out;
output [DW-1:0] packet_out;
input wait_in;
//Local wires
wire wr_en;
wire rd_en;
wire empty;
wire full;
wire valid;
reg access_out;
assign wr_en = access_in;//&~full
assign rd_en = ~empty & ~wait_in;
assign wait_out = full;
//Keep access high until "acknowledge"
always @ (posedge clk_out or posedge reset_out)
if(reset_out)
access_out <=1'b0;
else if(~wait_in)
access_out <=rd_en;
//Read response fifo (from master)
defparam fifo.DW = DW;
defparam fifo.DEPTH = DEPTH;
fifo_async fifo (.prog_full (full),//stay safe for now
.full (),
// Outputs
.dout (packet_out[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (reset_in),
.rd_rst (reset_out),
.wr_clk (clk_in),
.rd_clk (clk_out),
.wr_en (wr_en),
.din (packet_in[DW-1:0]),
.rd_en (rd_en)
);
endmodule // fifo_cdc
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; vector<int> v; for (int i = 0; i < n; i++) { int x; cin >> x; v.push_back(x); } sort(v.begin(), v.end()); if (v[0] == v[n / 2]) { cout << Bob << endl; } else { cout << Alice << endl; } } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const int MAXN = 1e6 + 7; const double EPS = 1e-6; const int M = 15; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); srand(time(0)); vector<vector<int> > dp(M + 1); vector<vector<pair<int, int> > > nxt(M + 1); for (int m = 0; m <= M; m++) { int N = (1 << m); dp[m].resize(N, INF); nxt[m].resize(N); queue<int> q; if (m < M) { q.push(0); dp[m][0] = 0; } else { for (int i = 0; i < 8; i++) { q.push(i << 12); dp[M][i << 12] = 0; } } while (!q.empty()) { int mask = q.front(); q.pop(); for (int a = 0; a < m; a++) { for (int k = 1; k < m; k++) { int b = a + k, c = a + 2 * k; if (c >= m) break; int mask1 = mask; mask1 ^= (1 << a); mask1 ^= (1 << b); mask1 ^= (1 << c); if (dp[m][mask1] != INF) continue; dp[m][mask1] = dp[m][mask] + 1; nxt[m][mask1] = {a, k}; q.push(mask1); } } } } int n; cin >> n; vector<int> all(n); for (int i = 0; i < n; i++) { cin >> all[i]; } if (n < 15) { int mask = 0; for (int i = n - 1; i >= 0; i--) { mask = mask * 2 + all[i]; } if (dp[n][mask] == INF) { cout << NO n ; return 0; } cout << YES n ; cout << dp[n][mask] << n ; while (mask) { int a = nxt[n][mask].first, k = nxt[n][mask].second; mask ^= (1 << a); mask ^= (1 << (a + k)); mask ^= (1 << (a + 2 * k)); cout << a + 1 << << a + 1 + k << << a + 1 + 2 * k << n ; } return 0; } cout << YES n ; vector<pair<int, int> > res; for (int i = 0, sz = M, fl = false; !fl; i += 12) { if (i >= n - 14) { sz = 14; i = n - 14; fl = true; } int mask = 0; for (int j = sz - 1; j >= 0; j--) { mask = mask * 2 + all[i + j]; } assert(dp[sz][mask] != INF); while (dp[sz][mask]) { int a = nxt[sz][mask].first, k = nxt[sz][mask].second; int b = a + k, c = a + 2 * k; all[i + a] ^= 1; all[i + b] ^= 1; all[i + c] ^= 1; mask ^= (1 << a); mask ^= (1 << b); mask ^= (1 << c); res.push_back({i + a, k}); } } for (int i = 0; i < n; i++) { assert(!all[i]); } cout << res.size() << n ; for (auto p : res) { int a = p.first, k = p.second; cout << a + 1 << << a + k + 1 << << a + 2 * k + 1 << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3_1_V
`define SKY130_FD_SC_HDLL__NOR3_1_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21A_2_V
`define SKY130_FD_SC_HS__O21A_2_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21a_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o21a_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21A_2_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
rst_sync_l, rst_both_l, rst_async_l, d, clk
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To sub1 of sub1.v, ...
input d; // To sub1 of sub1.v, ...
input rst_async_l; // To sub2 of sub2.v
input rst_both_l; // To sub1 of sub1.v, ...
input rst_sync_l; // To sub1 of sub1.v
// End of automatics
sub1 sub1 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_sync_l (rst_sync_l),
.d (d));
sub2 sub2 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_async_l (rst_async_l),
.d (d));
endmodule
module sub1 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_sync_l, d
);
input clk;
input rst_both_l;
input rst_sync_l;
//input rst_async_l;
input d;
reg q1;
reg q2;
always @(posedge clk) begin
if (~rst_sync_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end
end
always @(posedge clk) begin
q2 <= (~rst_both_l) ? 1'b0 : d;
if (0 && q1 && q2) ;
end
endmodule
module sub2 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_async_l, d
);
input clk;
input rst_both_l;
//input rst_sync_l;
input rst_async_l;
input d;
reg q1;
reg q2;
reg q3;
always @(posedge clk or negedge rst_async_l) begin
if (~rst_async_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end
end
always @(posedge clk or negedge rst_both_l) begin
q2 <= (~rst_both_l) ? 1'b0 : d;
end
// Make there be more async uses than sync uses
always @(posedge clk or negedge rst_both_l) begin
q3 <= (~rst_both_l) ? 1'b0 : d;
if (0 && q1 && q2 && q3) ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool flag; int vis[(1 << 17)]; int n, m, k; vector<pair<int, int> > vt[(1 << 17)]; void dfs(int u) { for (int i = 0; i < vt[u].size(); i++) { int v = vt[u][i].first; int c = vt[u][i].second; if (vis[v] == -1) { if (c == 1) vis[v] = vis[u]; else vis[v] = !vis[u]; dfs(v); } if (c == 1 && (vis[v] != vis[u])) flag = true; if (c == 0 && (vis[v] == vis[u])) flag = true; } } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { int u, v, c; scanf( %d%d%d , &u, &v, &c); vt[u].push_back(make_pair(v, c)); vt[v].push_back(make_pair(u, c)); } memset(vis, -1, sizeof(vis)); for (int i = 1; i <= n; i++) { if (vis[i] == -1) { vis[i] = 0; dfs(i); k++; } } long long ans = 1; if (flag) { puts( 0 ); return 0; } for (int i = 2; i <= k; i++) ans = ans * 2 % 1000000007; cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const long long PR = 1000000009; int n, m, premin[100009], sufmax[100009]; char A[100009], B[100009]; int main() { ios::sync_with_stdio(false); cin >> A >> B; n = strlen(A); m = strlen(B); for (int i = 0; i < m; i++) premin[i] = n, sufmax[i] = -1; int st = 0; for (int i = 0; i < m && st < n; i++) { while (A[st] != B[i]) { st++; if (st >= n) break; } premin[i] = st; st++; } st = n - 1; for (int i = m - 1; i >= 0 && st >= 0; i--) { while (A[st] != B[i]) { st--; if (st < 0) break; } sufmax[i] = st; st--; } int ans = m, i1 = -1, j1 = -1; for (int i = 0; i < m; i++) { if (premin[i] != n) { int mid, st = i + 1, end = m - 1; while (st < end) { mid = (st + end) / 2; if (sufmax[mid] >= premin[i] + 1) end = mid; else st = mid + 1; } if (sufmax[st] < premin[i] + 1) st = m; int now = st - i - 1; if (now < ans) { i1 = i + 1; j1 = st - 1; ans = now; } } } for (int i = m - 1; i >= 0; i--) { if (sufmax[i] == -1) break; int now = i - 1; if (now < ans) { j1 = i - 1; i1 = 0; ans = now; } } if (i1 == -1 || j1 - i1 + 1 == m) { cout << - << endl; return 0; } for (int i = 0; i < i1; i++) cout << B[i]; for (int j = j1 + 1; j < m; j++) cout << B[j]; cout << endl; return 0; }; |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Thu May 15 18:05:39 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/mono_radio/ip/dds/dds_stub.v
// Design : dds
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0,Vivado 2014.1" *)
module dds(aclk, s_axis_phase_tvalid, s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata, m_axis_phase_tvalid, m_axis_phase_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[39:0],m_axis_data_tvalid,m_axis_data_tdata[31:0],m_axis_phase_tvalid,m_axis_phase_tdata[39:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [39:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [31:0]m_axis_data_tdata;
output m_axis_phase_tvalid;
output [39:0]m_axis_phase_tdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, p; string msg, s[100001], h = <3 ; int sub(int &i, string &w) { int k = 0; for (; k < w.length() && i < msg.length(); i++) { if (w[k] == msg[i]) { ++k; } } return k == w.length(); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> s[i]; } cin >> msg; int j = 0, o = 1; for (int i = 0; o && i < n; i++) { if (!sub(j, h)) { o = 0; } if (o && !sub(j, s[i])) { o = 0; } } if (!sub(j, h)) { o = 0; } if (o) { cout << yes << n ; } else { cout << no << n ; } return 0; } |
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2008 www.xilinx.com
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : serdes_n_to_1.v
//
// Description : 1-bit generic n:1 transmitter module
// Takes in n bits of data and serialises this to 1 bit
// data is transmitted LSB first
// 0, 1, 2 ......
//
// Date - revision : August 1st 2008 - v 1.0
//
// Author : NJS
//
// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement,or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrantor
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits,cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the
// essential purpose of any limited remedies herein.
//
// Copyright © 2008 Xilinx, Inc.
// All rights reserved
//
//////////////////////////////////////////////////////////////////////////////
//
`timescale 1ps/1ps
module serdes_n_to_1 (ioclk, serdesstrobe, reset, gclk, datain, iob_data_out) ;
parameter integer SF = 8 ; // Parameter to set the serdes factor 1..8
input ioclk ; // IO Clock network
input serdesstrobe ; // Parallel data capture strobe
input reset ; // Reset
input gclk ; // Global clock
input [SF-1 : 0] datain ; // Data for output
output iob_data_out ; // output data
wire cascade_di ; //
wire cascade_do ; //
wire cascade_ti ; //
wire cascade_to ; //
wire [8:0] mdatain ; //
genvar i ; // Pad out the input data bus with 0's to 8 bits to avoid errors
generate
for (i = 0 ; i <= (SF - 1) ; i = i + 1)
begin : loop0
assign mdatain[i] = datain[i] ;
end
endgenerate
generate
for (i = (SF) ; i <= 8 ; i = i + 1)
begin : loop1
assign mdatain[i] = 1'b0 ;
end
endgenerate
OSERDES2 #(
.DATA_WIDTH (SF), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE_OQ ("SDR"), // <SDR>, DDR
.DATA_RATE_OT ("SDR"), // <SDR>, DDR
.SERDES_MODE ("MASTER"), // <DEFAULT>, MASTER, SLAVE
.OUTPUT_MODE ("DIFFERENTIAL"))
oserdes_m (
.OQ (iob_data_out),
.OCE (1'b1),
.CLK0 (ioclk),
.CLK1 (1'b0),
.IOCE (serdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.D4 (mdatain[7]),
.D3 (mdatain[6]),
.D2 (mdatain[5]),
.D1 (mdatain[4]),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TRAIN (1'b0),
.TCE (1'b1),
.SHIFTIN1 (1'b1), // Dummy input in Master
.SHIFTIN2 (1'b1), // Dummy input in Master
.SHIFTIN3 (cascade_do), // Cascade output D data from slave
.SHIFTIN4 (cascade_to), // Cascade output T data from slave
.SHIFTOUT1 (cascade_di), // Cascade input D data to slave
.SHIFTOUT2 (cascade_ti), // Cascade input T data to slave
.SHIFTOUT3 (), // Dummy output in Master
.SHIFTOUT4 ()) ; // Dummy output in Master
OSERDES2 #(
.DATA_WIDTH (SF), // SERDES word width. This should match the setting is BUFPLL
.DATA_RATE_OQ ("SDR"), // <SDR>, DDR
.DATA_RATE_OT ("SDR"), // <SDR>, DDR
.SERDES_MODE ("SLAVE"), // <DEFAULT>, MASTER, SLAVE
.OUTPUT_MODE ("DIFFERENTIAL"))
oserdes_s (
.OQ (),
.OCE (1'b1),
.CLK0 (ioclk),
.CLK1 (1'b0),
.IOCE (serdesstrobe),
.RST (reset),
.CLKDIV (gclk),
.D4 (mdatain[3]),
.D3 (mdatain[2]),
.D2 (mdatain[1]),
.D1 (mdatain[0]),
.TQ (),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TRAIN (1'b0),
.TCE (1'b1),
.SHIFTIN1 (cascade_di), // Cascade input D from Master
.SHIFTIN2 (cascade_ti), // Cascade input T from Master
.SHIFTIN3 (1'b1), // Dummy input in Slave
.SHIFTIN4 (1'b1), // Dummy input in Slave
.SHIFTOUT1 (), // Dummy output in Slave
.SHIFTOUT2 (), // Dummy output in Slave
.SHIFTOUT3 (cascade_do), // Cascade output D data to Master
.SHIFTOUT4 (cascade_to)) ; // Cascade output T data to Master
endmodule
|
#include <bits/stdc++.h> using namespace std; int pgcd(int a, int b) { if (b % a == 0) return a; pgcd(b % a, a); } int main() { int o = 0, gcd, az[1001], t[5000], j, k = 0, m, x, y, i, a, b, n; cin >> a >> b >> n; gcd = pgcd(a, b); for (i = 1; i * i <= gcd; i++) { if (gcd % i == 0) { t[k] = i; k++; t[k] = gcd / i; k++; } } for (i = 0; i < n; i++) { m = -1; cin >> x >> y; for (j = 0; j < k; j++) { if (t[j] <= y && t[j] >= x) m = max(m, t[j]); } cout << m << endl; } } |
`include "timescale.vh"
module hello (
input resn, // Reset, active low.
input clk,
output serialOut // The serial output.
);
// UART TX testing "Hello World!"
reg wr;
wire [7:0] char;
reg [3:0] state;
wire empty;
reg [3:0] messageIdx;
rom message (
.addr(messageIdx),
.clk(clk),
.q(char)
);
uartTx t1 (
.resn(resn), // Reset, active low.
.clk(clk), // Clock, (Use 50Mhz for 115200 baud).
.wr(wr), // Writes data to holding register on rising clock
.data(char), // Data to be transmitted.
.serialOut(serialOut), // The serial outout.
.empty(empty) // TRUE when ready to accept next character.
);
always @(posedge clk or negedge resn)
begin
if (!resn) begin
state <= 0;
wr <= 0;
messageIdx <= 0;
end else begin
case (state)
0 : begin
messageIdx <= messageIdx + 1;
wr <= 1;
state <= 1;
end
1: begin
wr <= 0;
state <= 2;
end
2: begin
if (empty == 1) begin
state <= 0;
end
end
default : ;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; void solve() { string s; cin >> s; vector<vector<ll>> cnt(2, vector<ll>(2, 0)); ll e = 0, o = 0; for (int i = 0; i < s.size(); i++) { o++; if (i % 2 == 0) { o += cnt[s[i] - a ][0]; e += cnt[s[i] - a ][1]; cnt[s[i] - a ][0]++; } else { e += cnt[s[i] - a ][0]; o += cnt[s[i] - a ][1]; cnt[s[i] - a ][1]++; } } cout << e << << o << n ; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int t = 1; for (int i = 1; i <= t; i++) { solve(); } return EXIT_SUCCESS; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2OI_SYMBOL_V
`define SKY130_FD_SC_HD__A2BB2OI_SYMBOL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2bb2oi (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2OI_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32O_BEHAVIORAL_V
`define SKY130_FD_SC_MS__A32O_BEHAVIORAL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32O_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int A[2006]; int B[2005]; map<int, int> mp; int main() { int a, b, n, x; while (cin >> n) { mp.clear(); int t = 1, x1, y1; for (int i = 0; i < n; i++) { scanf( %d , &A[i]); if (mp.count(A[i]) == 0) mp[A[i]] = t++; } for (int i = 0; i < n; i++) { scanf( %d , &B[i]); if (mp.count(B[i]) == 0) mp[B[i]] = t++; } int sum = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i == j) { x = A[i] ^ B[j]; if (mp.count(x) == 1) sum++; } else { x = A[i] ^ B[j]; if (mp.count(x) == 1) sum++; } } } if (sum % 2 == 0) cout << Karen << endl; else cout << Koyomi << endl; } return 0; } |
`timescale 1ns / 1ps
//Divisor de 32 bits con signo.
/*
* Números de 32 bits donde, si a es número, entonces:
* a[31] : signo de a.
* a[30:10] : parte entera de a.
* a[9:0] : parte decimal de a.
*/
module Divisor(
input wire [31:0] a,
input wire [31:0] b,
output reg [31:0] Z,
output reg ovf
);
reg [31:0] q = 32'b0;
reg [31:0] dividendo = 32'b0;
reg [31:0] divisor = 32'b0;
integer i = 0;
always @* begin
//Division by 0
if(!b[30:0]) begin
Z = 32'b0;
ovf = 1'b1;
end
else if(!a[30:0]) begin
Z = 32'b0;
ovf = 1'b0;
end else begin
dividendo = {1'b0, a[30:0]};
divisor = {1'b0, b[30:0]};
while(!dividendo[31]) dividendo = dividendo << 1;
while(!divisor[31]) divisor = divisor << 1;
for(i = 0; i < 32 && dividendo && divisor; i = i + 1) begin
if(dividendo >= divisor) begin
dividendo = dividendo - divisor;
q = (q << 1) | 32'b1;
end
else q = q << 1;
divisor = divisor >> 1;
end
//!!!
if(i < 10) begin
q = q << (11 - i);
end else begin
q = q >> (i - 11);
end
//!!!
Z[30:0] = q[30:0];
Z[31] = a[31] ^ b[31];
ovf = q[31];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int r, h, sum, n; float k, l; cin >> r >> h; n = h / r; h -= n * r; l = r / 2.0; k = sqrt(3) / 2 * r; if (h < l) sum = n * 2 + 1; if (h >= l && h < k) sum = n * 2 + 2; if (h >= k) sum = n * 2 + 3; cout << sum << endl; return 0; } |
module decoder (cx,d);
output [2:0] d;
input [8:0] cx;
reg [2:0] d;
reg [5:0] s;
reg [8:0] cx1;
parameter s0 = 6'b011001;
parameter s1 = 6'b010010;
parameter s2 = 6'b101010;
parameter s3 = 6'b100000;
parameter s4 = 6'b010000;
parameter s5 = 6'b001000;
parameter s6 = 6'b000100;
parameter s7 = 6'b000010;
parameter s8 = 6'b000001;
always @(cx)
begin
cx1[0] = cx[0];
cx1[1] = cx[1];
cx1[2] = cx[2];
cx1[3] = cx[3];
cx1[4] = cx[4];
cx1[5] = cx[5];
cx1[6] = cx[6];
cx1[7] = cx[7];
cx1[8] = cx[8];
s[0]= cx[2]+ cx[3];
s[1]= cx[0]+ cx[1]+ cx[4];
s[2]= cx[0]+ cx[2]+ cx[5];
s[3]= cx[6];
s[4]= cx[1]+ cx[2]+ cx[7];
s[5]= cx[0]+ cx[8];
case(s)
s0:
begin
if(cx[0]==1'b0)
begin
cx1[0]=1'b1;
end
else
begin
cx1[0]=1'b0;
end
end
s1:
begin
if(cx[1]==1'b0)
begin
cx1[1]=1'b1;
end
else
begin
cx1[1]=1'b0;
end
end
s2:
begin
if(cx[2]==1'b0)
begin
cx1[2]=1'b1;
end
else
begin
cx1[2]=1'b0;
end
end
s3:
begin
if(cx[3]==1'b0)
begin
cx1[3]=1'b1;
end
else
begin
cx1[3]=1'b0;
end
end
s4:
begin
if(cx[4]==1'b0)
begin
cx1[4]=1'b1;
end
else
begin
cx1[4]=1'b0;
end
end
s5:
begin
if(cx[5]==1'b0)
begin
cx1[5]=1'b1;
end
else
begin
cx1[5]=1'b0;
end
end
s6:
begin
if(cx[6]==1'b0)
begin
cx1[6]=1'b1;
end
else
begin
cx1[6]=1'b0;
end
end
s7:
begin
if(cx[7]==1'b0)
begin
cx1[7]=1'b1;
end
else
begin
cx1[7]=1'b0;
end
end
s8:
begin
if(cx[8]==1'b0)
begin
cx1[8]=1'b1;
end
else
begin
cx1[8]=1'b0;
end
end
default:
begin
cx1[0]=cx[0];
cx1[1]=cx[1];
cx1[2]=cx[2];
cx1[3]=cx[3];
cx1[4]=cx[4];
cx1[5]=cx[5];
cx1[6]=cx[6];
cx1[7]=cx[7];
cx1[8]=cx[8];
end
endcase
d[0] = cx1[0];
d[1] = cx1[1];
d[2] = cx1[2];
end
endmodule
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