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#include <bits/stdc++.h> using namespace std; using LL = long long; const int N = 2e5 + 4; int n, m, p[N], idx[N]; LL v1[N], v2[N]; vector<int> vals[N]; struct BIT { int s[N]; void init() { memset(s, 0, sizeof(s)); } void add(int i, int v) { for (; i <= n; i += i & (-i)) s[i] += v; } LL get(int i) { LL sum = 0; for (; i; i -= i & (-i)) sum += s[i]; return sum; } } bit; struct E { int id, wh, v; E() = default; E(int _id, int _wh, int _v) : id(_id), wh(_wh), v(_v) {} bool operator<(const E &rhs) const { return wh < rhs.wh; } }; struct Q { int l, r; } qs[N]; vector<E> events; int main() { bit.init(); scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , p + i); idx[p[i]] = i; } for (int i = 1; i <= n; i++) { if (!idx[i]) continue; int ii = idx[i]; for (int j = i; j <= n; j += i) { if (int ij = idx[j]) vals[ij].push_back(ii); } } events.reserve(2 * m); for (int i = 1; i <= m; i++) { int l, r; scanf( %d%d , &l, &r); if (l > 1) events.emplace_back(i, l - 1, 1); if (r <= n) events.emplace_back(i, r, 2); qs[i].l = l; qs[i].r = r; } sort(events.begin(), events.end()); for (int i = 1, j = 0, es = events.size(); i <= n && j < es; i++) { for (int v : vals[i]) bit.add(v, 1); for (; j < es && events[j].wh == i; j++) { if (events[j].v == 1) v1[events[j].id] = bit.get(qs[events[j].id].r) - bit.get(qs[events[j].id].l - 1); else v2[events[j].id] = bit.get(qs[events[j].id].r) - bit.get(qs[events[j].id].l - 1); } } for (int i = 1; i <= m; i++) { printf( %lld n , v2[i] - v1[i]); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EDFXBP_SYMBOL_V
`define SKY130_FD_SC_LP__EDFXBP_SYMBOL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__edfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EDFXBP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int INF = 1000000005; long long INFF = 1000000000000000005LL; int dirx[8] = {-1, 0, 0, 1, -1, -1, 1, 1}; int diry[8] = {0, 1, -1, 0, -1, 1, -1, 1}; double pi = 3.1415926536; int MOD = 1e9 + 7; long long power(long long x, long long n) { long long res = 1; while (n > 0) { if (n & 1) res = res * x; x = (x * x); n /= 2; } return res; } bool ok(int n, long long d) { long long sum = (n * (n + 1) / 2); if (sum < d) return false; return (d % 2 == sum % 2); } int main() { ios::sync_with_stdio(false); cin.tie(); cout.tie(); int t; cin >> t; while (t--) { int a, b; cin >> a >> b; int i = 0; while (!ok(i, abs(a - b))) i++; cout << i << n ; } } |
#include <bits/stdc++.h> using namespace std; string itos(int x) { stringstream ss; ss << x; return ss.str(); } int n, m, d[300010], vis[300010]; pair<int, int> a[300010]; vector<int> e[300010], res; int dfs(int now) { if (vis[now]) return 0; vis[now] = 1; d[now] = (d[now] == 1); for (auto x : e[now]) { int y = (a[x].first == now ? a[x].second : a[x].first); if (dfs(y)) { res.push_back((x)); d[now] ^= 1; } } return d[now] == 1; } int main() { ios_base::sync_with_stdio(false); cin >> n >> m; for (int i = 0; i < n; i++) cin >> d[i]; for (int i = 0, u, v; i < m;) { cin >> u >> v; a[++i] = make_pair((--u), (--v)); e[u].push_back((i)), e[v].push_back((i)); } int cnt1, free; cnt1 = count_if(d, d + 300010, [](int x) { return x == 1; }), free = count_if(d, d + 300010, [](int x) { return x == -1; }); if (cnt1 % 2 && not free) { cout << -1 << endl; return 0; } if (cnt1 % 2) *find(d, d + 300010, -1) = 1; dfs(0); cout << res.size() << endl; for (int i = 0; i < res.size(); i++) cout << res[i] << (i + 1 == res.size() ? n : ); return 0; } |
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_frame_length_adjust_fifo
*/
module test_axis_frame_length_adjust_fifo;
// Parameters
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter FRAME_FIFO_DEPTH = 4096;
parameter HEADER_FIFO_DEPTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_hdr_ready = 0;
reg m_axis_tready = 0;
reg [15:0] length_min = 0;
reg [15:0] length_max = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire m_axis_hdr_valid;
wire m_axis_hdr_pad;
wire m_axis_hdr_truncate;
wire [15:0] m_axis_hdr_length;
wire [15:0] m_axis_hdr_original_length;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_hdr_ready,
m_axis_tready,
length_min,
length_max
);
$to_myhdl(
s_axis_tready,
m_axis_hdr_valid,
m_axis_hdr_pad,
m_axis_hdr_truncate,
m_axis_hdr_length,
m_axis_hdr_original_length,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_frame_length_adjust_fifo.lxt");
$dumpvars(0, test_axis_frame_length_adjust_fifo);
end
axis_frame_length_adjust_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.FRAME_FIFO_DEPTH(FRAME_FIFO_DEPTH),
.HEADER_FIFO_DEPTH(HEADER_FIFO_DEPTH)
)
UUT (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_hdr_valid(m_axis_hdr_valid),
.m_axis_hdr_ready(m_axis_hdr_ready),
.m_axis_hdr_pad(m_axis_hdr_pad),
.m_axis_hdr_truncate(m_axis_hdr_truncate),
.m_axis_hdr_length(m_axis_hdr_length),
.m_axis_hdr_original_length(m_axis_hdr_original_length),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Configuration
.length_min(length_min),
.length_max(length_max)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_1_V
`define SKY130_FD_SC_LS__NAND3B_1_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3b_1 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand3b_1 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_1_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 7; const int inf = 0x3f3f3f3f; const int mod = 1e9 + 7; const double pi = acos(-1.0); const double G = 6.67430e-11; int n, q; set<int> p; multiset<int> d; void in(int x) { p.insert(x); if (p.size() == 1) return; auto pos = p.find(x); if (pos == --p.end()) { d.insert(x - *--pos); } else if (pos == p.begin()) { int y = *++pos; d.insert(y - x); } else { auto r = ++pos; pos--; auto l = --pos; pos++; d.insert(x - *l); d.insert(*r - x); d.erase(d.find(*r - *l)); } } void er(int x) { set<int>::iterator pos; pos = p.find(x); if (p.size() < 2) { p.erase(x); return; } if (pos == --p.end()) d.erase(d.find(x - *--pos)); else if (pos == p.begin()) d.erase(d.find(*++pos - x)); else { set<int>::iterator l; set<int>::iterator r; l = --pos; ++pos; r = ++pos; --pos; d.erase(d.find(x - *l)); d.erase(d.find(*r - x)); d.insert(*r - *l); } p.erase(x); } int kk() { if (p.size() <= 2) return 0; auto l = p.begin(); auto r = --p.end(); return (*r - *l - *--d.end()); } int main() { cin >> n >> q; int x; for (int i = 1; i <= n; ++i) { cin >> x; in(x); } cout << kk() << n ; int op; while (q--) { cin >> op >> x; if (op == 1) in(x); else er(x); cout << kk() << n ; } } |
//-----------------------------------------------------------------
// FPGA Audio Project SoC IP
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email:
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module mpx_top
(
// General - clocking & rst_i
clk_i,
rst_i,
en_i,
fault_o,
pause_i,
intr_i,
// Debug Register Access
dbg_reg_addr_i,
dbg_reg_out_o,
dbg_pc_o,
// UART output
uart_data_o,
uart_wr_o,
// 'HW' Multiplier
mult_a,
mult_b,
mult_hi,
mult_lo,
audio_out,
audio_wr
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] CLK_KHZ = (8192*7);
parameter MEMORY_TYPE = "XILINX_16X";
parameter [31:0] SRAM_ADDR_WIDTH = 19;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
input en_i /*verilator public*/;
output fault_o /*verilator public*/;
input pause_i /*verilator public*/;
input intr_i /*verilator public*/;
input [8:0] dbg_reg_addr_i /*verilator public*/;
output [31:0] dbg_reg_out_o /*verilator public*/;
output [31:0] dbg_pc_o /*verilator public*/;
output [7:0] uart_data_o /*verilator public*/;
output uart_wr_o /*verilator public*/;
output [31:0] mult_a /*verilator public*/;
output [31:0] mult_b /*verilator public*/;
input [31:0] mult_hi /*verilator public*/;
input [31:0] mult_lo /*verilator public*/;
output [31:0] audio_out /*verilator public*/;
output audio_wr /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
wire [31:0] ram_address;
wire [31:0] ram_data_w;
wire [31:0] ram_data_r;
wire [3:0] ram_wr;
wire ram_rd;
wire ram_busy;
wire [(SRAM_ADDR_WIDTH-1):0]asram_address;
wire [15:0] asram_data_w;
wire [15:0] asram_data_r;
wire asram_wren;
wire [1:0] asram_be;
wire fault_o;
wire [31:0] dbg_reg_out_o;
wire [31:0] dbg_pc_o;
wire [7:0] uart_data_o;
wire uart_wr_o;
wire [31:0] int_mem_addr_o;
wire [31:0] int_mem_data_o;
wire [31:0] int_mem_data_i;
wire [3:0] int_mem_wr_o;
reg [31:0] io_address;
reg [31:0] io_data_w;
reg [31:0] io_data_r;
reg [3:0] io_wr;
reg io_rd;
reg [31:0] mult_a;
reg [31:0] mult_b;
reg [31:0] audio_out;
reg audio_wr;
reg [31:0] ram_timing;
//-----------------------------------------------------------------
// Instantiation
//-----------------------------------------------------------------
asram16
#(
.SIZE(SRAM_ADDR_WIDTH)
)
u1_ram
(
.clk_i(clk_i),
.data_o(asram_data_r),
.data_i(asram_data_w),
.address_i(asram_address),
.be_i(asram_be),
.wren_i(asram_wren)
);
asram16_if
#(
.EXT_ADDR_WIDTH(SRAM_ADDR_WIDTH)
)
u1_ram_if
(
.clk_i(clk_i),
.rst_i(rst_i),
// Timing control register
.timing_ctrl_i(ram_timing),
// Asynchronous SRAM interface
.sram_address_o(asram_address),
.sram_data_o(asram_data_w),
.sram_data_i(asram_data_r),
.sram_oe_o(/*open */),
.sram_cs_o(/*open */),
.sram_be_o(asram_be),
.sram_we_o(asram_wren),
.sram_dir_out_o(/*open */),
// Internal access
.address_i(ram_address),
.data_i(ram_data_w),
.data_o(ram_data_r),
.rd_i(ram_rd),
.wr_i(ram_wr),
.busy_o(ram_busy)
);
sram4
#(
.SRAM_ADDR_WIDTH(SRAM_ADDR_WIDTH)
)
u1_bram
(
.clk_i(clk_i),
.address_i(int_mem_addr_o),
.data_i(int_mem_data_o),
.data_o(int_mem_data_i),
.wr_i(int_mem_wr_o)
);
mpx_soc
#(
.CLK_KHZ(CLK_KHZ),
.UART_BAUD(115200),
.EXTERNAL_INTERRUPTS(1),
.CORE_ID(32'h00000000),
.BOOT_VECTOR(32'h10000000),
.ISR_VECTOR(32'h1000003C)
)
u1_cpu
(
// Clock / Status
.clk_i(clk_i),
.rst_i(rst_i),
.en_i(en_i),
.ext_intr_i(intr_i),
.fault_o(fault_o),
// UART
.uart_tx_o(/* open */),
.uart_rx_i(1'b0),
// Internal Memory
.int_mem_addr_o(int_mem_addr_o),
.int_mem_data_o(int_mem_data_o),
.int_mem_data_i(int_mem_data_i),
.int_mem_wr_o(int_mem_wr_o),
.int_mem_rd_o(/*open */),
// External Memory
.ext_mem_addr_o(ram_address),
.ext_mem_data_o(ram_data_w),
.ext_mem_data_i(ram_data_r),
.ext_mem_wr_o(ram_wr),
.ext_mem_rd_o(ram_rd),
.ext_mem_pause_i(ram_busy),
// External IO
.ext_io_addr_o(io_address),
.ext_io_data_o(io_data_w),
.ext_io_data_i(io_data_r),
.ext_io_wr_o(io_wr),
.ext_io_rd_o(io_rd),
.ext_io_pause_i(1'b0),
// External Shared / DP-RAM
.ext_dpram_addr_o(/*open */),
.ext_dpram_data_o(/*open */),
.ext_dpram_data_i(32'h00000000),
.ext_dpram_wr_o(/*open */),
.ext_dpram_rd_o(/*open */),
.ext_dpram_pause_i(1'b0),
// SPI Flash
.flash_cs_o(/*open */),
.flash_si_o(/*open */),
.flash_so_i(1'b0),
.flash_sck_o(/*open */),
// Debug Register Access
.dbg_reg_addr_i(dbg_reg_addr_i),
.dbg_reg_out_o(dbg_reg_out_o),
.dbg_pc_o(dbg_pc_o),
// Debug UART output
.dbg_uart_data_o(uart_data_o),
.dbg_uart_wr_o(uart_wr_o)
);
//-----------------------------------------------------------------
// I/O Handlers
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if ((rst_i == 1'b1))
begin
audio_out <= 32'h00000000;
audio_wr <= 1'b0;
mult_a <= 32'h00000000;
mult_b <= 32'h00000000;
ram_timing <= 32'h00000777;
end
else
begin
audio_wr <= 1'b0;
// IO Write Cycle
if (io_wr != 4'b0000)
case (io_address[7:0])
// 0x60 -> MULT_A
8'h60:
mult_a <= io_data_w;
// 0x64 -> MULT_B
8'h64:
mult_b <= io_data_w;
// 0x70 -> FIFO_WRITE
8'h70:
begin
audio_out<= io_data_w;
audio_wr <= 1'b1;
end
// 0xE0 -> RAM_TIMING
8'hE0:
ram_timing <= io_data_w;
default :
;
endcase
end
end
//-----------------------------------------------------------------
// IO memory space READ handler
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
if ((rst_i == 1'b1))
io_data_r <= 32'h00000000;
else
// Read cycle?
if ((io_rd == 1'b1))
begin
case (io_address[7:0])
// 0x60 -> MULT_A
8'h60:
io_data_r <= mult_hi;
// 0x64 -> MULT_B
8'h64:
io_data_r <= mult_lo;
default :
io_data_r <= 32'h00000000;
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:32:33 05/12/2015
// Design Name:
// Module Name: IF_ID
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module IF_ID(clk,rst,if_pcplus4, stall, BJ,
if_instr,id_pcplus4, id_instr
);
input clk,rst,stall, BJ;
input wire [31:0] if_pcplus4,if_instr;
output reg [31:0] id_pcplus4,id_instr;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
id_pcplus4 <= 4;
id_instr <= 32'b100000;
end
else if(stall | BJ)
begin
id_pcplus4 <= if_pcplus4;
id_instr <= 32'b100000;
end
else
begin
id_pcplus4 <= if_pcplus4;
id_instr <= if_instr;
end
end
endmodule
//module IF_ID(clk,rst,stall,if_pcplus4, if_instr,id_pcplus4, id_instr
// );
// input clk,rst, stall;
// input wire [31:0] if_pcplus4,if_instr;
// output reg [31:0] id_pcplus4,id_instr;
//
// always @(posedge clk or posedge rst)
// begin
// if(rst)
// begin
// id_pcplus4 <= 4;
// id_instr <= 32'b100000;
// end
// else if(stall)
// begin
// id_pcplus4 <= if_pcplus4-4;
// id_instr <= 32'b100000;
// end
// else
// begin
// id_pcplus4 <= if_pcplus4;
// id_instr <= if_instr;
// end
// end
//endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_example_if0_p0_qsys_sequencer_cpu_inst_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx0;
wire unxcomplemented_resetxx1;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx0 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx0)
);
defparam the_altera_std_synchronizer.depth = 2;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iobdg_int_mondo_addr_dec.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg_int_mondo_addr_dec
// Description: Logic to generate address to
// index the mondo data table.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module iobdg_int_mondo_addr_dec (/*AUTOARG*/
// Outputs
creg_mdata0_dec, creg_mdata1_dec, creg_mbusy_dec, mondo_data_addr,
addr_invld,
// Inputs
addr_in, thr_id_in
);
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
input [`IOB_ADDR_WIDTH-1:0] addr_in;
input [`IOB_CPUTHR_INDEX-1:0] thr_id_in;
output creg_mdata0_dec;
output creg_mdata1_dec;
output creg_mbusy_dec;
output [`IOB_MONDO_DATA_INDEX-1:0] mondo_data_addr;
output addr_invld;
wire creg_mdata0_alias_dec;
wire creg_mdata1_alias_dec;
wire creg_mbusy_alias_dec;
wire creg_mdata0_proper_dec;
wire creg_mdata1_proper_dec;
wire creg_mbusy_proper_dec;
wire use_thr_addr;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
// Assertion: Decode signals should be mutually exclusive.
/*****************************************************************
* Decode for Mondo Data0, Mondo Data1, Mondo Busy access
* Assumption: addr_in is within the IOB_INT_CSR range
*****************************************************************/
// Decode alias address (what software normally uses)
assign creg_mdata0_alias_dec =
(addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0]
== `IOB_CREG_MDATA0_ALIAS);
assign creg_mdata1_alias_dec =
(addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0]
== `IOB_CREG_MDATA1_ALIAS);
assign creg_mbusy_alias_dec =
(addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0]
== `IOB_CREG_MBUSY_ALIAS);
// Decode proper address (what the TAP has to use)
assign creg_mdata0_proper_dec =
((addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0] & `IOB_THR_ADDR_MASK)
== `IOB_CREG_MDATA0);
assign creg_mdata1_proper_dec =
((addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0] & `IOB_THR_ADDR_MASK)
== `IOB_CREG_MDATA1);
assign creg_mbusy_proper_dec =
((addr_in[`IOB_LOCAL_ADDR_WIDTH-1:0] & `IOB_THR_ADDR_MASK)
== `IOB_CREG_MBUSY);
// Combine proper and alias decode results
assign creg_mdata0_dec = creg_mdata0_proper_dec | creg_mdata0_alias_dec;
assign creg_mdata1_dec = creg_mdata1_proper_dec | creg_mdata1_alias_dec;
assign creg_mbusy_dec = creg_mbusy_proper_dec | creg_mbusy_alias_dec;
assign use_thr_addr = creg_mdata0_alias_dec |
creg_mdata1_alias_dec |
creg_mbusy_alias_dec;
// Use thread ID as index into array if request comes from software
// Use the address directly if request comes from TAP
assign mondo_data_addr = use_thr_addr ? thr_id_in :
addr_in[`IOB_MONDO_DATA_INDEX-1+3:3];
/*****************************************************************
* Assert address invalid if no register address match
*****************************************************************/
assign addr_invld = ~creg_mdata0_dec &
~creg_mdata1_dec &
~creg_mbusy_dec;
endmodule // iobdg_int_mondo_addr_dec
|
//////////////////////////////////////////////////////////////////////////////////
//
// Author : Praveen Kumar Pendyala
// Create Date : 05/27/13
// Modify Date : 16/01/14
// Module Name : mapping
// Project Name : PDL
// Target Devices : Xilinx Vertix 5, XUPV5 110T
// Tool versions : 13.2 ISE
//
// Description:
// This module maps the data received by the SircHandler (from PC) to the AluPuf.
// Issues appropriate trigger signals to start puf execution.
// Maintain state of the PUF operation - Idle or execute
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`default_nettype none
module mapping #(
parameter IN_WIDTH = 128,
parameter OUT_WIDTH = 16
)(
input wire clk,
input wire reset,
input wire trigger,
input wire [IN_WIDTH-1:0] dataIn,
output reg done,
output reg [OUT_WIDTH-1:0] dataOut,
output reg xorOut // Will use this later after output network is implemented.
);
// Input network also has to be implemented.
wire [15:0] response;
reg startPUF;
reg PUFreset;
reg [4:0] countWait;
integer ind;
reg [15:0] sum;
//FSM States
localparam IDLE = 0;
localparam COMPUTE = 1;
//State Register
reg mp_state;
reg [IN_WIDTH-1:0] buffer;
always @ (posedge clk) begin
if (reset) begin
done <= 0;
dataOut <= 0;
mp_state <= IDLE;
startPUF <= 0;
countWait <= 0;
PUFreset <=1;
end
else begin
case(mp_state)
IDLE: begin
done <= 0;
sum <= 0;
PUFreset <= 0;
countWait <=0;
startPUF <=0;
if(trigger == 1)
mp_state <= COMPUTE;
buffer <= dataIn;
end
COMPUTE: begin
startPUF <=1;
countWait <= countWait + 1;
if (countWait == 15) begin //wait for 10 clock cycles
startPUF<=0;
dataOut <= response;
done <= 1;
mp_state <= IDLE;
PUFreset <=1;
end
end
endcase
end
end
endmodule
|
/* Author:- Neel_Patel */ #include <bits/stdc++.h> #define ff first #define ss second #define pb push_back #define all(c) (c).begin(),(c).end() #define vi vector<int> #define pii pair<int,int> #define pll pair<long long,long long> #define vll vector<long long> #define priq priority_queue #define sp fixed<<setprecision #define fast ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0) using namespace std; typedef long long ll; typedef unsigned long long int llu; const long double pi=3.14159265358979323846; const int inf=INT_MAX; const ll inff=LLONG_MAX; const long long int mod=1000000007; ///////////////// debug #define deb(...) print1(#__VA_ARGS__,__VA_ARGS__) void print() {cout<<endl;} template <typename T, typename... Types> void print(T var1, Types... var2) {cout << var1 << , ;print(var2...) ;} template<typename ...Args> void print1(string vars, Args&&... values) {cout<<vars<< = ;print(values...);} //////////////////// // ostream operator overloading template<typename T> ostream& operator<< (ostream& out, const vector<T>& v) { out << { ;size_t last = v.size() - 1;for(size_t i = 0; i < v.size(); ++i) { out << v[i]; if (i != last) out << , ;}out << } ;return out; } template<typename T1,typename T2> ostream & operator << (ostream &out,pair<T1,T2> x) { out<< ( <<x.ff<< , <<x.ss<< ) ;return out; } ///////////////////////// functions template<typename T> T gcd(T a,T b,T& x,T& y) // extended gcd:- x and y such that xa+yb=gcd(a,b); { if(b==0) { x=1;y=0;return a;} T x1,y1; T d=gcd(b,a%b,x1,y1); x=y1; y=x1-y1*(a/b); return d; } template<typename T> T pow(T a,T b,T M) { // if M is prime # then we can take // b=b%(M-1); // using fermat s littel theorem // b=b%(M-1); T res = 1; while(b) { if(b&1) res=(res*a)%M; a=(a*a)%M; b>>=1; } return res; } template<typename T> T modular_inverse(T n, T mod) { return pow(n, mod-2, mod); } ////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////// // check value of t(#of test case -- in main function) /////////////global variable/////////////////////// // #define int ll #define ld long double const ld eps=1e-10; ld fun(ld c,ld m,ld p,ld v) { ld ans=0; // deb(c,m,p,v); if(c>eps) { ld diff=min(c,v); ld nm=m,nc=c-diff,np=p; if(m>eps) { nm+=diff/2.0; np+=diff/2.0; } else { np+=diff; } // deb(nc,nm,np,v); ans+=c*(1.0+fun(nc,nm,np,v)); } if(m>eps) { ld diff=min(m,v); ld nm=m-diff,nc=c,np=p; if(c>eps) { nc+=diff/2.0; np+=diff/2.0; } else { np+=diff; } ans+=m*(1.0+fun(nc,nm,np,v)); } return ans+p; } ll ask(ll n) { cout<<n<<endl; cin>>n; return n; } void solve() { ld c,m,p,v; cin>>c>>m>>p>>v; cout<<sp(20)<<fun(c,m,p,v)<<endl; } // priority_queue <int, vector<int>, greater<int>> g = gq; // for small value on top //////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////// signed main() // signed int { // snippet = https://snippet-generator.app/ #ifndef ONLINE_JUDGE cout<< hi!! ; // cout<< Code is running.... n ; freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); // chrono::time_point<std::chrono::system_clock> start, end; // start = chrono::system_clock::now(); #endif // ONLINE_JUDGE fast; // cout<< hi n ; int t=1; cin>>t; while(t--) { solve(); } /* #ifndef ONLINE_JUDGE end = chrono::system_clock::now(); chrono::duration<double> elapsed_seconds = end - start; cout<<elapsed_seconds.count()<<endl; #endif // ONLINE_JUDGE */ } |
#include <bits/stdc++.h> using namespace std; int n, m, t; int main() { cin >> t; while (t--) { int s = 0, a; cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> a; s += 2 * a; } if (m < n || n < 3) { cout << -1 << endl; continue; } cout << s << endl; for (int i = 1; i < n; i++) cout << i << << i + 1 << endl; cout << n << << 1 << endl; } } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll inf = 1e18; template <typename T> void printvector(const vector<T>& foo) { for (auto el : foo) cout << el << ; cout << endl; } bool calc(vector<int>& permuration, const vector<vector<int>>& sets, vector<bool>& used) { if (permuration.size() == sets.size() + 1) { for (auto el : permuration) cout << el << ; cout << n ; return true; } if (permuration.empty()) { for (int i = 0; i < sets.size(); i++) { permuration.push_back(sets[i][0]); permuration.push_back(sets[i][1]); used[i] = true; if (calc(permuration, sets, used)) return true; swap(permuration[0], permuration[1]); if (calc(permuration, sets, used)) return true; used[i] = false; permuration.pop_back(); permuration.pop_back(); } } vector<int> last_elements; for (size_t next = 0; next < sets.size(); next++) { if (used[next]) continue; const auto& row = sets[next]; if (row.size() > permuration.size() + 1) break; while (last_elements.size() < row.size() - 1) { last_elements.push_back( permuration[permuration.size() - last_elements.size() - 1]); } sort(last_elements.begin(), last_elements.end()); vector<int> diff; set_difference(row.begin(), row.end(), last_elements.begin(), last_elements.end(), back_inserter(diff)); if (diff.size() > 1) continue; used[next] = true; permuration.push_back(diff[0]); if (calc(permuration, sets, used)) return true; used[next] = false; permuration.pop_back(); return false; } return false; } int main() { int test; cin >> test; while (test--) { int n; cin >> n; vector<vector<int>> sets(n - 1); for (auto& row : sets) { int k; cin >> k; row.resize(k); for (auto& el : row) cin >> el; } sort(sets.begin(), sets.end(), [](const vector<int>& a, const vector<int>& b) { return a.size() < b.size(); }); vector<int> permutation; vector<bool> used(n, false); calc(permutation, sets, used); } return 0; } |
#include <bits/stdc++.h> using namespace std; stringstream ss; long long p[1000010], h1[1000010], h2[1000010]; int main() { p[0] = 1; for (int i = 1; i < 1000010; i++) h1[i] = p[i] = p[i - 1] * 127LL; int n, m, a, b; cin >> n >> m; for (int i = 1; i <= m; i++) { cin >> a >> b; h1[a] += p[b]; h2[a] += p[b]; h1[b] += p[a]; h2[b] += p[a]; } sort(h1 + 1, h1 + 1 + n); sort(h2 + 1, h2 + 1 + n); long long res = 0; for (int i = 1; i <= n; i++) { long long cnt = 1; while (i + 1 <= n && h1[i] == h1[i + 1]) cnt++, i++; res += (cnt) * (cnt - 1) / 2LL; } for (int i = 1; i <= n; i++) { long long cnt = 1; while (i + 1 <= n && h2[i] == h2[i + 1]) cnt++, i++; res += (cnt) * (cnt - 1) / 2LL; } cout << res << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXBN_BLACKBOX_V
`define SKY130_FD_SC_HD__DLXBN_BLACKBOX_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXBN_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int mod = 1e9 + 7; int w[1007]; int n, x; int d[107]; int N = 101; int mat[107][107]; void mNoz(int (&a)[107][107], int (&b)[107][107], int (&c)[107][107]) { long long res[107][107]; for (int i = 1; i <= N; ++i) for (int j = 1; j <= N; ++j) res[i][j] = 0; for (int i = 1; i <= N; ++i) for (int k = 1; k <= N; ++k) for (int j = 1; j <= N; ++j) res[i][j] += ((long long)a[i][k] * b[k][j]) % mod; for (int i = 1; i <= N; ++i) for (int j = 1; j <= N; ++j) c[i][j] = res[i][j] % mod; } void pot(int (&a)[107][107], int (&c)[107][107], int k) { int res[107][107]; for (int i = 1; i <= N; ++i) for (int j = 1; j <= N; ++j) res[i][j] = i == j; while (k > 0) { if (k & 1) mNoz(res, a, res); mNoz(a, a, a); k /= 2; } for (int i = 1; i <= N; ++i) for (int j = 1; j <= N; ++j) c[i][j] = res[i][j]; } int main() { ios_base::sync_with_stdio(0); cin >> n >> x; for (int i = 1; i <= n; ++i) { int a; cin >> a; mat[1][a]++; } mat[1][N] = mat[N][N] = 1; for (int i = 1; i + 1 < N; ++i) mat[i + 1][i] = 1; pot(mat, mat, x); int wyn = mat[1][1] + mat[1][N]; wyn %= mod; cout << wyn << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a = 0, b = 0, c = 0, d = 0, n, temp, dl; cin >> n; for (int i = 0; i <= n; i++) { if (i < n) { cin >> temp; } else { temp = max(a, d) + 1; } dl = temp - a; if (dl != 1 && dl != -1) { if (!b) { b = i + 1; d = temp; } else if (!c) { c = i; } else { b = 0; c = 0; break; } } else if (!c && b) { if (dl != -1) { b = 0; c = 0; break; } } a = temp; } cout << b << << c; } |
#include <bits/stdc++.h> using namespace std; typedef long long ll; #define fastIO ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int main() { fastIO int t; cin>>t; while(t--) { int x,y; cin>>x>>y; if (x==y) cout<<x+y<< n ; else cout<<max(x,y)*2-1<< n ; } } |
#include <bits/stdc++.h> using namespace std; long long t0, t1, t2, x1, x2; long long count(long long y1, long long y2) { return t1 * y1 + t2 * y2 - t0 * (y1 + y2); } int main() { cin >> t1 >> t2 >> x1 >> x2 >> t0; if (t1 == t2) { cout << x1 << << x2; return 0; } long long by1 = 0, by2 = x2; for (long long y1 = 0; y1 <= x1; y1++) { long long l = (y1 == 0 ? 1 : 0), r = x2; while (l <= r) { long long m = (l + r) / 2; long long c = count(y1, m); if (c < 0) l = m + 1; else { if ((t1 * y1 + t2 * m) * (by1 + by2) < (t1 * by1 + t2 * by2) * (y1 + m) || ((t1 * y1 + t2 * m) * (by1 + by2) == (t1 * by1 + t2 * by2) * (y1 + m) && (by1 + by2) < (y1 + m))) { by1 = y1; by2 = m; } r = m - (r == m ? 1 : 0); } } } cout << by1 << << by2; } |
// 32-bit adder
// Using Carry Lookahead adders
module adder
(
input wire [31:0] op1,
input wire [31:0] op2,
input wire cin,
output wire [31:0] sum,
output wire carry,
output wire v_flag
);
wire[6:0] cout;
assign v_flag = carry ^ cout[6];
carry_lookahead_adder CLA1(op1[3:0], op2[3:0], cin, sum[3:0], cout[0]);
carry_lookahead_adder CLA2(op1[7:4], op2[7:4], cout[0], sum[7:4], cout[1]);
carry_lookahead_adder CLA3(op1[11:8], op2[11:8], cout[1], sum[11:8], cout[2]);
carry_lookahead_adder CLA4(op1[15:12], op2[15:12], cout[2], sum[15:12], cout[3]);
carry_lookahead_adder CLA5(op1[19:16], op2[19:16], cout[3], sum[19:16], cout[4]);
carry_lookahead_adder CLA6(op1[23:20], op2[23:20], cout[4], sum[23:20], cout[5]);
carry_lookahead_adder CLA7(op1[27:24], op2[27:24], cout[5], sum[27:24], cout[6]);
carry_lookahead_adder CLA8(op1[31:28], op2[31:28], cout[6], sum[31:28], carry);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBN_TB_V
`define SKY130_FD_SC_HS__DLRBN_TB_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlrbn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 RESET_B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 RESET_B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 RESET_B = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 RESET_B = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_hs__dlrbn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .Q_N(Q_N), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBN_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long int logx = 30; const long long int N = 1e6 + 5; const long long int INF = 1e18 + 5; const long long int mod = 321555123; const double PI = 3.14159265358979323846; inline long long int mul(long long int a, long long int b) { return (a * 1ll * b) % mod; } inline long long int sub(long long int a, long long int b) { long long int c = a - b; if (c < 0) c += mod; return c; } inline long long int add(long long int a, long long int b) { long long int c = a + b; if (c > mod) c -= mod; return c; } template <typename T> T power(T x, T y, long long int m) { T ans = 1; while (y > 0) { if (y & 1LL) ans = (ans * x) % m; y >>= 1ll; x = (x * x) % m; } return ans % m; } vector<long long int> bit[N]; long long int n, q, a[N], b[N]; void Update(long long int idx, long long int val) { idx++; while (idx <= n) { bit[idx].push_back(val); idx += (idx & -idx); } } long long int Query(long long int idx, long long int val) { long long int sum = 0; idx++; while (idx > 0) { long long int lb = lower_bound(bit[idx].begin(), bit[idx].end(), val) - bit[idx].begin(); sum += lb; idx -= (idx & -idx); } return sum; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; cin >> n; long long int sum = 0; map<long long int, long long int> first; for (long long int i = 0; i < n; i++) { cin >> a[i]; } for (long long int i = n - 1; i >= 0; i--) { first[a[i]]++; b[i] = first[a[i]]; } for (long long int i = 0; i < n; i++) { Update(i, b[i]); } for (long long int i = 1; i <= n + 1; i++) { sort(bit[i].begin(), bit[i].end()); } first.clear(); for (long long int i = 0; i < n; i++) { long long int l = i + 1; long long int r = n - 1; first[a[i]]++; sum += Query(r, first[a[i]]) - Query(l - 1, first[a[i]]); } cout << sum << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 6, inf = 2e9 + 7; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int tc; cin >> tc; while (tc--) { int n, x, y, d; cin >> n >> x >> y >> d; if (x == y) cout << 0 n ; else if (abs(y - x) % d == 0) cout << abs(y - x) / d << n ; else { int a = (x - 1) / d; if ((x - 1) % d != 0) a++; int t = n - x; int b = t / d; if (t % d != 0) b++; if ((y - 1) % d == 0) a = a + (y - 1) / d; else a = inf; if ((n - y) % d == 0) b = b + (n - y) / d; else b = inf; a = min(a, b); if (a == inf) a = -1; cout << a << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline T read() { T x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return x * f; } const int N = 100010, INF = 0x3f3f3f3f; int n, q, k, key[N]; struct Edge { int to, nxt; }; struct Graph { int head[N], tot; Edge e[N << 1]; void addedge(int x, int y) { e[++tot] = (Edge){y, head[x]}; head[x] = tot; } }; struct Tree : public Graph { int dfn[N], ti, f[N][19], dep[N]; void dfs(int x, int fa) { dfn[x] = ++ti; f[x][0] = fa; dep[x] = dep[fa] + 1; for (int i = 1; i <= 18; i++) f[x][i] = f[f[x][i - 1]][i - 1]; for (int i = head[x]; i; i = e[i].nxt) { int y = e[i].to; if (y == fa) continue; dfs(y, x); } } int lca(int x, int y) { if (dep[x] < dep[y]) swap(x, y); for (int i = 18; i >= 0; i--) { if (dep[f[x][i]] >= dep[y]) x = f[x][i]; } if (x == y) return x; for (int i = 18; i >= 0; i--) { if (f[x][i] != f[y][i]) x = f[x][i], y = f[y][i]; } return f[x][0]; } } t; struct Virtual_Tree : public Graph { int dp[N][2], d[N], st[N], tp; void build_vtree(Tree& t, int* key, int cnt) { memcpy(d, key, sizeof(int) * (cnt + 1)); sort(d + 1, d + cnt + 1, [&](int x, int y) { return t.dfn[x] < t.dfn[y]; }); head[1] = 0, tot = 0; st[tp = 1] = 1; for (int i = 1; i <= cnt; i++) { if (d[i] == 1) continue; int lc = t.lca(d[i], st[tp]); if (lc != st[tp]) { while (t.dfn[lc] < t.dfn[st[tp - 1]]) { addedge(st[tp - 1], st[tp]); tp--; } if (t.dfn[lc] != t.dfn[st[tp - 1]]) { head[lc] = 0, addedge(lc, st[tp]); st[tp] = lc; } else addedge(lc, st[tp]), tp--; } head[d[i]] = 0, st[++tp] = d[i]; } for (int i = 1; i < tp; i++) addedge(st[i], st[i + 1]); } void dfs_dp(int, int); } vt; int iskey[N]; void Virtual_Tree::dfs_dp(int x, int fa) { dp[x][0] = (!iskey[x]) * n, dp[x][1] = iskey[x] * n; int minx = INF, sum = 1, cnt = 0; for (int i = head[x]; i; i = e[i].nxt) { int y = e[i].to; if (y == fa) continue; cnt += iskey[y]; dfs_dp(y, x); if (iskey[x]) dp[x][0] += min(dp[y][1], dp[y][0] + 1); else { minx = min(minx, dp[y][0] - dp[y][1]); sum += min(dp[y][0], dp[y][1]); dp[x][1] += dp[y][1]; } } if (!iskey[x] && cnt <= 1) dp[x][0] = dp[x][1] + minx; if (!iskey[x]) dp[x][1] = min(dp[x][1], sum); } void solve() { k = read<int>(); for (int i = 1; i <= k; i++) iskey[key[i] = read<int>()] = 1; for (int i = 1; i <= k; i++) { int x = key[i]; if (iskey[t.f[x][0]]) { for (int j = 1; j <= k; j++) iskey[key[j]] = 0; puts( -1 ); return; } } vt.build_vtree(t, key, k); vt.dfs_dp(1, 0); printf( %d n , min(vt.dp[1][0], vt.dp[1][1])); for (int j = 1; j <= k; j++) iskey[key[j]] = 0; } int main() { n = read<int>(); for (int i = 1; i < n; i++) { int x = read<int>(), y = read<int>(); t.addedge(x, y); t.addedge(y, x); } t.dfs(1, 0); q = read<int>(); while (q--) solve(); return 0; } |
`include "scmem.vh"
`include "DC_define.v"
`include "logfunc.h"
module DC_1_tagbank #(parameter Width = 15, Size =256, Forward=0)
//tag 10+counter 2 bits [11:10]+states 3 bits[14:12] =>15
(
input clk
,input reset
,input req_valid
//request byte is also important ld 8 byte or store 512assign set_index=req_data[10:6];
,input ack_retry
,input write_1_tagbank //if write enable then no read and outdata=0
,input [7:0] req_pos_tag
,input [Width-1:0] req_data
,output req_retry
,output ack_valid
,output [14:0] ack_data
/////////////////////////////////////////////////////////////
//5bit loadReq
,input coretodc_ld_valid
,output coretodc_ld_retry
,input [4:0] coretodc_ld_req
// 7 bit store Req,atomic,checkpoint
,input coretodc_std_valid
,output coretodc_std_retry
,input [6:0] coretodc_std
//5 bit L2 -> DC ACK
,input l2tol1_snack_valid
// ,output l2tol1_snack_retry
,input [4:0] l2tol1_snack
// 3 bit Displacement
,output l1tol2_disp_valid//
//,input l1tol2_disp_retry//
,output [2:0] l1tol2_disp//
,output[2:0] state_cache
);
logic[14:0] ack_data_from_ram;
logic write = write_1_tagbank;
logic [14:0] req_data_1_tagbank; //15 bits=10+2+3
assign req_data_1_tagbank= req_data;
ram_1port_fast
#(.Width(Width), .Size(Size))
tagbank (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_we (write)//we=0 for read
,.req_data (req_data_1_tagbank)//search for Tag only while reading
,.ack_retry (ack_retry)
,.req_pos (req_pos_tag)//search the set index position
,.req_retry (req_retry)
,.ack_valid (ack_valid)
,.ack_data (ack_data_from_ram)
);
logic [2:0] state_bits;
assign state_bits=ack_data_from_ram[14:12];
logic [2:0] next_state_bits;
assign ack_data=ack_data_from_ram;
always@(coretodc_ld_valid or coretodc_ld_req)begin
if ($bits(coretodc_ld_req)==5) begin
coretodc_ld_retry=0;
case(coretodc_ld_req)//look***********************************************
//Loads Req that changes cache state
`CORE_LOP_L32U:begin if (state_bits==`US) next_state_bits=`US;
else if (state_bits==`UM) next_state_bits=`UM;
else if (state_bits==`S) next_state_bits=`S;
else next_state_bits = state_bits;
end
default:next_state_bits = state_bits;
endcase
write =1'b1;//write enable
req_data_1_tagbank[14:12]=next_state_bits;
end //if end
state_cache=next_state_bits;
end //always
always@( l2tol1_snack or l2tol1_snack_valid )begin
if ($bits(l2tol1_snack)==5) begin
case(l2tol1_snack)//look***********************************************
//Loads Req that changes cache state
`SC_SCMD_ACK_S :begin if (state_bits==`US) next_state_bits=`US;
else if (state_bits==`UM) next_state_bits=`UM;
else if (state_bits==`M) begin next_state_bits=`S; l1tol2_disp=`SC_DCMD_WS;l1tol2_disp_valid=1;end
else if (state_bits==`E) next_state_bits=`S;
else if (state_bits==`S) next_state_bits=`S;
else next_state_bits = state_bits;
end
`SC_SCMD_ACK_E :begin if (state_bits==`US) next_state_bits=`US;
else if (state_bits==`UM) next_state_bits=`UM;
else if (state_bits==`M) begin next_state_bits=`US; l1tol2_disp=`SC_DCMD_WS;end
else if (state_bits==`E) next_state_bits=`US;
else if (state_bits==`S) next_state_bits=`US;
else next_state_bits = state_bits;
end
`SC_SCMD_ACK_M :begin if (state_bits==`I) next_state_bits=`E;
else if (state_bits==`I) next_state_bits=`S;
else next_state_bits = state_bits;
end
default:next_state_bits = state_bits;
endcase
write ='b1;//write enable
req_data_1_tagbank[14:12]=next_state_bits;
end //if end
state_cache=next_state_bits;
end //always
always@(coretodc_std)begin
if ($bits(coretodc_std)==7 && coretodc_std_valid) begin
coretodc_std_retry=0;
case(coretodc_std)//look***********************************************
//Loads Req that changes cache state
`CORE_MOP_S32: begin if (state_bits==`US) next_state_bits=`UM;
else if (state_bits==`S) next_state_bits=`UM;
else if (state_bits==`S) next_state_bits=`M;
else next_state_bits = `M;
end
default:next_state_bits = state_bits;
endcase
end //if
state_cache=next_state_bits;
end //always
//logic [`CACHE_STATE-1:0] cache_state;
// assign cache_state=ack_data[21:23];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, k; int p; scanf( %I64d %I64d %d , &n, &k, &p); long long ndiv2 = n / 2; long long ndiv2minus1 = n / 2 - 1; long long nminusk = n - k; for (int i = 0; i < p; i++) { long long x; scanf( %I64d , &x); printf( %c , (((x == n) ? (n) : (1 + (x / 2) * ndiv2 - ((x - 1) / 2) * ndiv2minus1)) <= nminusk) ? ( . ) : ( X )); } exit: return (0); } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosII_system_nios2_qsys_0_mult_cell (
// inputs:
A_mul_src1,
A_mul_src2,
clk,
reset_n,
// outputs:
A_mul_cell_result
)
;
output [ 31: 0] A_mul_cell_result;
input [ 31: 0] A_mul_src1;
input [ 31: 0] A_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] A_mul_cell_result;
wire [ 31: 0] A_mul_cell_result_part_1;
wire [ 15: 0] A_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altmult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[15 : 0]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.intended_device_family = "CYCLONEII",
the_altmult_add_part_1.lpm_type = "altmult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altmult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (A_mul_src1[31 : 16]),
.datab (A_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (A_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.intended_device_family = "CYCLONEII",
the_altmult_add_part_2.lpm_type = "altmult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_addnsub3 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign A_mul_cell_result = {A_mul_cell_result_part_1[31 : 16] +
A_mul_cell_result_part_2,
A_mul_cell_result_part_1[15 : 0]};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//
// Example module to create problem.
//
// generate a 64 bit value with bits
// [HighMaskSel_Bot : LowMaskSel_Bot ] = 1
// [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1
// all other bits zero.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [7:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] HighLogicImm; // From example of example.v
wire [63:0] LogicImm; // From example of example.v
wire [63:0] LowLogicImm; // From example of example.v
// End of automatics
wire [5:0] LowMaskSel_Top = crc[5:0];
wire [5:0] LowMaskSel_Bot = crc[5:0];
wire [5:0] HighMaskSel_Top = crc[5:0]+{4'b0,crc[7:6]};
wire [5:0] HighMaskSel_Bot = crc[5:0]+{4'b0,crc[7:6]};
example example (/*AUTOINST*/
// Outputs
.LogicImm (LogicImm[63:0]),
.LowLogicImm (LowLogicImm[63:0]),
.HighLogicImm (HighLogicImm[63:0]),
// Inputs
.LowMaskSel_Top (LowMaskSel_Top[5:0]),
.HighMaskSel_Top (HighMaskSel_Top[5:0]),
.LowMaskSel_Bot (LowMaskSel_Bot[5:0]),
.HighMaskSel_Bot (HighMaskSel_Bot[5:0]));
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n", $time, cyc, crc,
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot,
LowLogicImm, HighLogicImm, LogicImm);
`endif
if (cyc==0) begin
// Single case
crc <= 8'h0;
sum <= 64'h0;
end
else if (cyc==1) begin
// Setup
crc <= 8'hed;
sum <= 64'h0;
end
else if (cyc<90) begin
sum <= {sum[62:0],sum[63]} ^ LogicImm;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum);
if (crc !== 8'b00111000) $stop;
if (sum !== 64'h58743ffa61e41075) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module example (/*AUTOARG*/
// Outputs
LogicImm, LowLogicImm, HighLogicImm,
// Inputs
LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot
);
input [5:0] LowMaskSel_Top, HighMaskSel_Top;
input [5:0] LowMaskSel_Bot, HighMaskSel_Bot;
output [63:0] LogicImm;
output [63:0] LowLogicImm, HighLogicImm;
wire [63:0] LowLogicImm, HighLogicImm;
/* verilator lint_off UNSIGNED */
/* verilator lint_off CMPCONST */
genvar i;
generate
for (i=0;i<64;i=i+1) begin : MaskVal
if (i >= 32) begin
assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]);
assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]);
end
else begin
assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]);
assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]);
end
end
endgenerate
/* verilator lint_on UNSIGNED */
/* verilator lint_on CMPCONST */
assign LogicImm = LowLogicImm & HighLogicImm;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long int n; long long int a[100000]; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n - 1; i++) { cout << a[i] + a[i + 1] << ; } cout << a[n - 1]; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e6 + 10; const long long int md = 1e9 + 7; long long int n, fac[MAXN], invf[MAXN]; inline long long int inv(long long int a, long long int b = 1e9 + 5ll) { long long int k = 1ll; while (b) { if (b & 1) k = (k * a) % md; a = (a * a) % md; b /= 2ll; } return k; } inline long long int ch(long long int a, long long int b) { return ((((invf[b] * invf[a - b]) % md) * fac[a]) % md); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); fac[0] = 1ll; invf[0] = 1ll; cin >> n; for (long long int i = 1ll; i < MAXN; i++) fac[i] = (fac[i - 1] * i) % md, invf[i] = inv(fac[i]); long long int ans = inv(2ll, 2ll * n + 1ll); ans--; ans = (ans + md) % md; long long int bad = 0ll; for (long long int i = n + 1; i <= 2ll * n; i++) { long long int tmp = (2ll * ch(i - 1ll, n)) % md; tmp += ((2ll * bad) % md); tmp %= md; ans = (((ans - tmp) % md) + md) % md; bad = tmp; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5006; const int mod = 1000000009; double x[maxn], y[maxn], z[maxn]; double d[maxn][maxn]; int n; double dis(double x1, double y1, double z1, double x2, double y2, double z2) { double dx = x1 - x2; double dy = y1 - y2; double dz = z1 - z2; return sqrt(dx * dx + dy * dy + dz * dz); } double getans() { double ret = 100000000000.0; for (int i = 1; i < n; ++i) for (int j = i + 1; j < n; ++j) { double dd = d[i][j] + d[0][i] + d[0][j]; ret = min(ret, dd); } return ret; } void init() { for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) d[i][j] = dis(x[i], y[i], z[i], x[j], y[j], z[j]); } int main() { while (~scanf( %d , &n)) { for (int i = 0; i < n; ++i) { scanf( %lf%lf%lf , x + i, y + i, z + i); } init(); double ans = getans(); ans /= 2; printf( %.9lf n , ans); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Rose-Hulman Institute of Technology
// Engineer: Adam Michael
// Date: 10/1/2015
// Summary: A basic distributed RAM.
//////////////////////////////////////////////////////////////////////////////////
module RAM40x7bits(Address, Din, Clock, Reset, WriteEnabled, Dout);
input [5:0] Address;
input [6:0] Din;
input Reset;
input Clock, WriteEnabled;
output [6:0] Dout;
reg [6:0] Data [39:0];
always@(posedge Clock or posedge Reset)
if (Reset == 1) begin // This spells out
Data[0] <= "E"; // ECE333 Fall 2015 Digital Systems
Data[1] <= "C";
Data[2] <= "E";
Data[3] <= "3";
Data[4] <= "3";
Data[5] <= "3";
Data[6] <= " ";
Data[7] <= "F";
Data[8] <= "a";
Data[9] <= "l";
Data[10] <= "l";
Data[11] <= " ";
Data[12] <= "2";
Data[13] <= "0";
Data[14] <= "1";
Data[15] <= "5";
Data[16] <= " ";
Data[17] <= "D";
Data[18] <= "i";
Data[19] <= "g";
Data[20] <= "i";
Data[21] <= "t";
Data[22] <= "a";
Data[23] <= "l";
Data[24] <= " ";
Data[25] <= "S";
Data[26] <= "y";
Data[27] <= "s";
Data[28] <= "t";
Data[29] <= "e";
Data[30] <= "m";
Data[31] <= "s";
Data[32] <= "\n";
Data[33] <= "\r";
end
else if (WriteEnabled == 1) Data[Address] <= Din;
assign Dout = Data[Address];
endmodule
|
/*
* Redistributions of any form whatsoever must retain and/or include the
* following acknowledgment, notices and disclaimer:
*
* This product includes software developed by Carnegie Mellon University.
*
* Copyright (c) 2004 by Babak Falsafi and James Hoe,
* Computer Architecture Lab at Carnegie Mellon (CALCM),
* Carnegie Mellon University.
*
* This source file was written and maintained by Jared Smolens
* as part of the Two-Way In-Order Superscalar project for Carnegie Mellon's
* Introduction to Computer Architecture course, 18-447. The source file
* is in part derived from code originally written by Herman Schmit and
* Diana Marculescu.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* If you modify the software you must place a notice on or within any
* modified version provided or made available to any third party stating
* that you have modified the software. The notice shall include at least
* your name, address, phone number, email address and the date and purpose
* of the modification.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANYWARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
// Top module for the ARM processor core
// NOT synthesizable Verilog!
module testbench;
reg [31:0] i;
reg [29:0] addr;
wire clk, inst_excpt, mem_excpt, halted;
wire reg_mem_clk;
wire [29:0] pc, mem_addr;
wire [31:0] inst, mem_data_in, mem_data_out;
wire [3:0] mem_write_en;
reg rst_b;
// The clock
clock CLK(clk, reg_mem_clk);
// The ARM core
arm_top top(.clk(clk), .reg_mem_clk(reg_mem_clk), .inst_addr(pc), .inst(inst),
.mem_addr(mem_addr), .mem_data_in(mem_data_in), .mem_data_out(mem_data_out),
.mem_write_en(mem_write_en),
.halted(halted), .rst_b(rst_b));
// Memory
arm_mem Memory(// Port 1 (instructions)
.addr1(pc), .data_in1(), .data_out1(inst), .we1(4'b0),
.excpt1(), .allow_kernel1(1'b1), .kernel1(),
// Port 2 (data)
.addr2(mem_addr), .data_in2(mem_data_in),
.data_out2(mem_data_out), .we2(mem_write_en),
.excpt2(), .allow_kernel2(1'b1), .kernel2(),
.rst_b(rst_b), .clk(reg_mem_clk));
initial
begin
rst_b = 0;
#75;
rst_b <= 1;
end
always @(halted)
begin
#0;
if(halted === 1'b1)
$finish;
end
endmodule
// Clock module for the ARM core. You may increase the clock period
// if your design requires it.
module clock(clockSignal, reg_mem_clk);
parameter start = 0, halfPeriod = 50;
output clockSignal;
output reg_mem_clk;
reg clockSignal;
reg reg_mem_clk;
initial begin
clockSignal = start;
reg_mem_clk = start;
end
always begin
#halfPeriod clockSignal = ~clockSignal;
#3 reg_mem_clk = clockSignal;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_V
/**
* lpflow_lsbuf_lh_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer, vpb/vnb
* taps, double-row-height cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_TAP_BEHAVIORAL_V |
#include <bits/stdc++.h> int N, K, A, B, Q, a[200001], TA[524288], TB[524288]; void P(int x) { int p = 1, l = 1, r = N; while (l < r) { int m = l + r >> 1; if (x <= m) r = m, p <<= 1; else l = m + 1, p = p << 1 | 1; } TA[p] = std::min(a[x], A); TB[p] = std::min(a[x], B); while (p > 1) { p >>= 1; TA[p] = TA[p << 1] + TA[p << 1 | 1]; TB[p] = TB[p << 1] + TB[p << 1 | 1]; } } int G(int *T, int p, int l, int r, int L, int R) { if (L <= l && r <= R) return T[p]; int m = l + r >> 1; if (R <= m) return G(T, p << 1, l, m, L, R); if (L > m) return G(T, p << 1 | 1, m + 1, r, L, R); return G(T, p << 1, l, m, L, R) + G(T, p << 1 | 1, m + 1, r, L, R); } int main() { scanf( %d%d%d%d%d , &N, &K, &A, &B, &Q); while (Q--) { int ty, u, w; scanf( %d%d , &ty, &u); if (ty == 1) { scanf( %d , &w); a[u] += w; P(u); } else printf( %d n , (u > 1 ? G(TB, 1, 1, N, 1, u - 1) : 0) + (u > N - K ? 0 : G(TA, 1, 1, N, u + K, N))); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> T abs(T x) { return x > 0 ? x : -x; } int n; int m; int mask[500][500][17]; int x[500], y[500], X[500], Y[500]; double xx[500], yy[500], XX[500], YY[500]; double vect(double x1, double y8687969, double x2, double y2) { return x1 * y2 - x2 * y8687969; } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %d%d , &x[i], &y[i]); for (int i = 0; i < m; i++) scanf( %d%d , &X[i], &Y[i]); double *cx, *cy, *CX, *CY; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { xx[j] = x[j] - x[i], yy[j] = y[j] - y[i]; } for (int j = 0; j < m; j++) { XX[j] = X[j] - x[i]; YY[j] = Y[j] - y[i]; } cx = xx + i; cy = yy + i; for (int j = i + 1; j < n; j++) { cx++; cy++; CX = XX; CY = YY; int *ap = mask[i][j], *ar = mask[j][i]; int b = 0; for (int k = 0; k < m; k++, CX++, CY++) { if ((*cx) * (*CY) - (*cy) * (*CX) > 0) (*ap) |= (1 << b); else (*ar) |= (1 << b); b++; if (b == 30) { ap++; ar++; b = 0; } } } } int ans = 0; double *jx, *jy, *kx, *ky; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { xx[j] = x[j] - x[i]; yy[j] = y[j] - y[i]; } jx = xx + i; jy = yy + i; for (int j = i + 1; j < n; j++) { jx++; jy++; kx = jx; ky = jy; for (int k = j + 1; k < n; k++) { kx++; ky++; if ((*jx) * (*ky) - (*jy) * (*kx) > 0) { ans++; for (int l = 0; l < 17; l++) if (mask[i][j][l] & mask[j][k][l] & mask[k][i][l]) { ans--; break; } } else { ans++; for (int l = 0; l < 17; l++) if (mask[i][k][l] & mask[k][j][l] & mask[j][i][l]) { ans--; break; } } } } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long dx[] = {-1, 0, 1, 0}; long long dy[] = {0, 1, 0, -1}; long long spf[1]; void sieve() { long long i, j; for (i = 0; i < 1; i++) spf[i] = i; for (i = 4; i < 1; i += 2) spf[i] = 2; for (i = 3; i * i < 1; i++) { if (spf[i] == i) { for (j = i * i; j < 1; j += i) { if (spf[j] == j) spf[j] = i; } } } } bool isvowel(char c) { switch (c) { case a : case e : case i : case o : case u : case y : return true; default: return false; } } bool isPrime(long long n) { for (long long i = 2; i <= sqrt(n); i++) { if (n % i == 0) { return false; } } return true; } long long sum(long long n) { long long ans = 0; while (n > 0) { long long d = n % 10; ans += d; n /= 10; } return ans; } vector<long long> adj[200005]; long long col[200005]; pair<long long, long long> e[200005]; long long bfs(long long node) { col[node] = 1; queue<long long> q; q.push(node); while (!q.empty()) { long long curr = q.front(); q.pop(); for (auto child : adj[curr]) { if (col[child] == -1) { col[child] = 1 - col[curr]; q.push(child); } else if (col[child] == col[curr]) { return false; } } } return true; } int32_t main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1; while (t--) { long long n, m; cin >> n >> m; for (long long i = 1; i <= m; i++) { long long u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); e[i] = {u, v}; } memset(col, -1, sizeof(col)); for (long long i = 1; i <= n; i++) { if (col[i] == -1) { if (bfs(i) == false) { cout << NO << n ; return 0; } } } cout << YES << n ; vector<long long> v; for (long long i = 1; i <= n; i++) { if (col[i] == 1) { v.push_back(i); } } for (long long i = 1; i <= m; i++) { if (col[e[i].first] == 0) { cout << 0 ; } else { cout << 1 ; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 16 + 5; string a[N], x, y; int n, m, M = -1; map<string, map<string, int> > mm; bool vis[N]; void dfs(int deep, int mod) { if (deep > n + 1) return; if (deep == n + 1) { int tot = 0, f = 1; for (int i = 1; i <= n; ++i) tot += vis[i]; for (int i = 1; i <= n; ++i) for (int j = i + 1; j <= n; ++j) if (vis[i] && vis[j]) if (mm[a[i]][a[j]]) { f = 0; break; } if (f) { if (mod) { int tot = 0; for (int i = 1; i <= n; ++i) tot += vis[i]; if (tot != M) return; printf( %d n , M); string res[N]; for (int i = 1; i <= 17; ++i) res[i] = 0 ; int pos = 1; for (int i = 1; i <= n; ++i) if (vis[i]) res[pos++] = a[i]; sort(res + 1, res + pos); pos = 1; while (res[pos] != 0 ) { cout << res[pos] << endl; pos++; } exit(0); } else if (mod == 0) M = max(M, tot); } } vis[deep] = true; dfs(deep + 1, mod); vis[deep] = false; dfs(deep + 1, mod); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= m; ++i) { cin >> x >> y; mm[x][y] = mm[y][x] = 1; } dfs(1, 0); dfs(1, 1); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> v, w; int m; long long int f(int d, int target) { long long int timeSpent = 0; long long int totDone = 0; long long int koytaDone = 0; long long int lastSpent = 0; for (int i = 0; i < v.size(); i++) { if (v[i] <= d) { timeSpent += v[i]; lastSpent += v[i]; koytaDone++; totDone++; if (totDone == target) return timeSpent; } if (koytaDone == m) { koytaDone = 0; timeSpent += lastSpent; lastSpent = 0; } } return LLONG_MAX / 3; } int main() { int t, n, inp; long long int tot; scanf( %d , &t); while (t--) { v.clear(); w.clear(); scanf( %d %d , &n, &m); cin >> tot; while (n--) { scanf( %d , &inp); v.push_back(inp); w.push_back(inp); } sort(w.begin(), w.end()); int lo = 1, hi = w.size(), ans = 0, ans_d = 1; while (lo <= hi) { int mid = (lo + hi) / 2; int tem_d = w[mid - 1]; if (f(tem_d, mid) <= tot) { ans = mid; ans_d = tem_d; lo = mid + 1; } else hi = mid - 1; } cout << ans << << ans_d << n ; } return 0; } |
/*
** -----------------------------------------------------------------------------**
** control_regs.v
**
** various control bits (what was a single control register before)
**
** Copyright (C) 2008 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
module control_regs (sclk, // @negedge
wen, // sync to address and d[0:15]
wa, // [1:0] register select
di, // [15:0] data in
/// outputs
bayer_phase, //[1:0]
hact_regen,
reset_mcontr,
break_frames, /// Enable ending frame if no more data is available
zoran,
use_sensor_clk,
xt_pol,
arst,
aro,
encnvclk,
sensor_trigger,
mrst,
external_timestamp, // use external timestamp if available
output_timestamp, // output timestamp, not just pulse
dclkmode,
pxd14,
latehact, //[1:0]=dcr[22:21];// register hact, vact N/4 Tpclk later than data (needed for MT9P001 @ 96MHz)
pclksrc, //[1:0]=dcr[25:24]; // pclk source
hfc_sel, //[2:0]=dcr[30:28];
blockvsync, // block vsync from sensor to sequencers
compressed_frames // 8-bit selection of which frames (modulo 8) to compress. deafaults to 'hff
); // [2:0] current frame modulo 8
input sclk;
input wen;
input [ 1:0] wa;
input [15:0] di;
output [ 1:0] bayer_phase; //[1:0]
output hact_regen;
output reset_mcontr;
output break_frames; /// Enable ending frame if no more data is available
output zoran;
output use_sensor_clk;
output xt_pol;
output arst;
output aro;
output encnvclk;
output sensor_trigger;
output mrst;
output external_timestamp;
output output_timestamp;
output [7:0] compressed_frames;
output dclkmode;
output pxd14;
output [1:0] latehact; //[1:0]=dcr[22:21];// register hact, vact N/4 Tpclk later than data (needed for MT9P001 @ 96MHz)
output [1:0] pclksrc; //[1:0]=dcr[25:24]; // pclk source
output [2:0] hfc_sel; //[2:0]=dcr[30:28];
output blockvsync; // block vsync from sensor to sequencers
reg [1:0] wend; // we delayed
reg [1:0] wad; // address delayed
reg [2:0] reg_wr; // write data to registers (group 0, group1)
reg [15:0] d1;
reg [31:0] d2;
reg [7:0] compressed_frames=8'hff; // TODO change other FDE_1 to registers
always @ (negedge sclk) begin
wend[1:0] <= {wend[0], wen};
if (wen) wad[1:0] <= wa[1:0];
reg_wr[2:0] <= {wend[1] & (wad[1:0]==2'h1), wend[1] & (wad[1:0]==2'h3), wend[1] & (wad[1:0]==2'h2)};
if (wen || wend[0]) d1[15:0] <= di[15:0];
if (wend[0]) d2[15: 0] <= d1[15:0];
if (wend[1]) d2[31:16] <= d1[15:0];
end
FDE_1 i_bayer_phase_0 (.C(sclk),.CE(reg_wr[0] & d2[ 2]),.D(d2[ 0]), .Q(bayer_phase[0]));
FDE_1 i_bayer_phase_1 (.C(sclk),.CE(reg_wr[0] & d2[ 2]),.D(d2[ 1]), .Q(bayer_phase[1]));
FDE_1 i_hact_regen (.C(sclk),.CE(reg_wr[0] & d2[ 4]),.D(d2[ 3]), .Q(hact_regen));
FDE_1 i_reset_mcontr (.C(sclk),.CE(reg_wr[0] & d2[ 6]),.D(d2[ 5]), .Q(reset_mcontr));
FDE_1 i_zoran (.C(sclk),.CE(reg_wr[0] & d2[ 8]),.D(d2[ 7]), .Q(zoran));
FDE_1 i_use_sensor_clk (.C(sclk),.CE(reg_wr[0] & d2[10]),.D(d2[ 9]), .Q(use_sensor_clk));
FDE_1 i_xt_pol (.C(sclk),.CE(reg_wr[0] & d2[12]),.D(d2[11]), .Q(xt_pol));
FDE_1 i_arst (.C(sclk),.CE(reg_wr[0] & d2[14]),.D(d2[13]), .Q(arst));
FDE_1 i_aro (.C(sclk),.CE(reg_wr[0] & d2[16]),.D(d2[15]), .Q(aro));
FDE_1 i_encnvclk (.C(sclk),.CE(reg_wr[0] & d2[18]),.D(d2[17]), .Q(encnvclk));
FDE_1 i_sensor_trigger (.C(sclk),.CE(reg_wr[0] & d2[20]),.D(d2[19]), .Q(sensor_trigger));
FDE_1 i_break_frames (.C(sclk),.CE(reg_wr[0] & d2[22]),.D(d2[21]), .Q(break_frames));
FDE_1 i_mrst (.C(sclk),.CE(reg_wr[1] & d2[ 1]),.D(d2[ 0]), .Q(mrst));
FDE_1 i_external_timestamp(.C(sclk),.CE(reg_wr[1] & d2[ 3]),.D(d2[ 2]), .Q(external_timestamp));
FDE_1 i_dclkmode (.C(sclk),.CE(reg_wr[1] & d2[ 5]),.D(d2[ 4]), .Q(dclkmode));
FDE_1 i_pxd14 (.C(sclk),.CE(reg_wr[1] & d2[ 7]),.D(d2[ 6]), .Q(pxd14));
FDE_1 i_latehact_0 (.C(sclk),.CE(reg_wr[1] & d2[10]),.D(d2[ 8]), .Q(latehact[0]));
FDE_1 i_latehact_1 (.C(sclk),.CE(reg_wr[1] & d2[10]),.D(d2[ 9]), .Q(latehact[1]));
FDE_1 i_pclksrc_0 (.C(sclk),.CE(reg_wr[1] & d2[13]),.D(d2[11]), .Q(pclksrc[0]));
FDE_1 i_pclksrc_1 (.C(sclk),.CE(reg_wr[1] & d2[13]),.D(d2[12]), .Q(pclksrc[1]));
FDE_1 i_hfc_sel_0 (.C(sclk),.CE(reg_wr[1] & d2[17]),.D(d2[14]), .Q(hfc_sel[0]));
FDE_1 i_hfc_sel_1 (.C(sclk),.CE(reg_wr[1] & d2[17]),.D(d2[15]), .Q(hfc_sel[1]));
FDE_1 i_hfc_sel_2 (.C(sclk),.CE(reg_wr[1] & d2[17]),.D(d2[16]), .Q(hfc_sel[2]));
FDE_1 i_blockvsync (.C(sclk),.CE(reg_wr[1] & d2[19]),.D(d2[18]), .Q(blockvsync));
FDE_1 i_output_timestamp (.C(sclk),.CE(reg_wr[1] & d2[21]),.D(d2[20]), .Q(output_timestamp));
always @ (negedge sclk) begin
if (reg_wr[2] & d2[8]) compressed_frames[7:0] <= d2[7:0];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string a, b; int n; cin >> n; cin >> a >> b; int ans = 0; for (int i = 0; i < n - 1; i++) { if (a[i] != b[i]) { ans++; if (a[i + 1] != b[i + 1] && a[i] != a[i + 1]) { swap(a[i], a[i + 1]); } else a[i] = b[i]; } } if (a[n - 1] != b[n - 1]) ans++; printf( %d n , ans); return 0; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_demux
*/
module test_eth_demux_4;
// Parameters
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_eth_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [DATA_WIDTH-1:0] s_eth_payload_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep = 0;
reg s_eth_payload_axis_tvalid = 0;
reg s_eth_payload_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_eth_payload_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_eth_payload_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_eth_payload_axis_tuser = 0;
reg [M_COUNT-1:0] m_eth_hdr_ready = 0;
reg [M_COUNT-1:0] m_eth_payload_axis_tready = 0;
reg enable = 0;
reg drop = 0;
reg [1:0] select = 0;
// Outputs
wire s_eth_hdr_ready;
wire s_eth_payload_axis_tready;
wire [M_COUNT-1:0] m_eth_hdr_valid;
wire [M_COUNT*48-1:0] m_eth_dest_mac;
wire [M_COUNT*48-1:0] m_eth_src_mac;
wire [M_COUNT*16-1:0] m_eth_type;
wire [M_COUNT*DATA_WIDTH-1:0] m_eth_payload_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep;
wire [M_COUNT-1:0] m_eth_payload_axis_tvalid;
wire [M_COUNT-1:0] m_eth_payload_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_eth_payload_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_eth_payload_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_eth_payload_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_eth_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_eth_payload_axis_tdata,
s_eth_payload_axis_tkeep,
s_eth_payload_axis_tvalid,
s_eth_payload_axis_tlast,
s_eth_payload_axis_tid,
s_eth_payload_axis_tdest,
s_eth_payload_axis_tuser,
m_eth_hdr_ready,
m_eth_payload_axis_tready,
enable,
drop,
select
);
$to_myhdl(
s_eth_hdr_ready,
s_eth_payload_axis_tready,
m_eth_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_eth_payload_axis_tdata,
m_eth_payload_axis_tkeep,
m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast,
m_eth_payload_axis_tid,
m_eth_payload_axis_tdest,
m_eth_payload_axis_tuser
);
// dump file
$dumpfile("test_eth_demux_4.lxt");
$dumpvars(0, test_eth_demux_4);
end
eth_demux #(
.M_COUNT(M_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tid(s_eth_payload_axis_tid),
.s_eth_payload_axis_tdest(s_eth_payload_axis_tdest),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// Ethernet frame outputs
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tid(m_eth_payload_axis_tid),
.m_eth_payload_axis_tdest(m_eth_payload_axis_tdest),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Control
.enable(enable),
.drop(drop),
.select(select)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int p[31111], dp[31111][800]; int main() { int i, j, n, d, u; scanf( %d%d , &n, &d); for (i = 0; i < n; i++) { scanf( %d , &u); p[u]++; } for (i = 0; i <= 30000; i++) { for (j = 0; j <= 650; j++) { dp[i][j] = -10000000; } } int ans = dp[d][300] = p[d]; for (i = d + 1; i <= 30000; i++) { for (j = 1; j <= 600; j++) { int pre = i - j - d + 300; if (pre < 0) break; if (pre >= i) continue; dp[i][j] = max(dp[pre][j], max(dp[pre][j + 1], dp[pre][j - 1])) + p[i]; ans = max(ans, dp[i][j]); } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int t; t = 1; for (long long int _ = 0; _ < t; _++) { long long int n, m, b, mod; cin >> n >> m >> b >> mod; vector<long long int> v(n + 1); for (long long int i = 1; i <= n; i++) cin >> v[i]; long long int dp[2][m + 1][b + 1]; for (long long int i = 0; i <= 1; i++) { for (long long int j = 0; j <= m; j++) { for (long long int k = 0; k <= b; k++) dp[i][j][k] = 0; } } dp[0][0][0] = 1; for (long long int i = 1; i <= n; i++) { for (long long int j = 0; j <= m; j++) { for (long long int k = 0; k <= b; k++) { if (k >= v[i] && j > 0) dp[i % 2][j][k] = (dp[1 - (i % 2)][j][k] + dp[i % 2][j - 1][k - v[i]]) % mod; else dp[i % 2][j][k] = dp[1 - (i % 2)][j][k]; } } } long long int ans = 0; for (long long int k = 0; k <= b; k++) ans = (ans + dp[n % 2][m][k]) % mod; cout << ans << n ; } return 0; } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module softusb_ram(
input sys_clk,
input sys_rst,
input usb_clk,
input usb_rst,
input [31:0] wb_adr_i,
output [31:0] wb_dat_o,
input [31:0] wb_dat_i,
input [3:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
input wb_we_i,
input pmem_ce,
input [10:0] pmem_a,
output [15:0] pmem_d,
input dmem_we,
input [12:0] dmem_a,
input [7:0] dmem_di,
output reg [7:0] dmem_do
);
always @(posedge sys_clk) begin
if(sys_rst)
wb_ack_o <= 1'b0;
else begin
if(wb_stb_i & wb_cyc_i & ~wb_ack_o)
wb_ack_o <= 1'b1;
else
wb_ack_o <= 1'b0;
end
end
wire [31:0] wb_dat_o_prog;
softusb_dpram_11_16 program(
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[12:2]),
.we(wb_stb_i & wb_cyc_i & ~wb_adr_i[17] & wb_we_i & ~wb_ack_o),
.di(wb_dat_i[15:0]),
.do(wb_dat_o_prog[15:0]),
.ce2(pmem_ce),
.a2(pmem_a),
.we2(1'b0),
.di2(16'hxxxx),
.do2(pmem_d)
);
assign wb_dat_o_prog[31:16] = 16'd0;
wire [7:0] dmem_do0;
wire [7:0] dmem_do1;
wire [7:0] dmem_do2;
wire [7:0] dmem_do3;
wire [31:0] wb_dat_o_data;
softusb_dpram_11_8 dataram0(
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[12:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[0] & ~wb_ack_o),
.di(wb_dat_i[7:0]),
.do(wb_dat_o_data[7:0]),
.ce2(1'b1),
.a2(dmem_a[12:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd3)),
.di2(dmem_di),
.do2(dmem_do0)
);
softusb_dpram_11_8 dataram1(
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[12:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[1] & ~wb_ack_o),
.di(wb_dat_i[15:8]),
.do(wb_dat_o_data[15:8]),
.ce2(1'b1),
.a2(dmem_a[12:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd2)),
.di2(dmem_di),
.do2(dmem_do1)
);
softusb_dpram_11_8 dataram2(
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[12:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[2] & ~wb_ack_o),
.di(wb_dat_i[23:16]),
.do(wb_dat_o_data[23:16]),
.ce2(1'b1),
.a2(dmem_a[12:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd1)),
.di2(dmem_di),
.do2(dmem_do2)
);
softusb_dpram_11_8 dataram3(
.clk(sys_clk),
.clk2(usb_clk),
.a(wb_adr_i[12:2]),
.we(wb_stb_i & wb_cyc_i & wb_adr_i[17] & wb_we_i & wb_sel_i[3] & ~wb_ack_o),
.di(wb_dat_i[31:24]),
.do(wb_dat_o_data[31:24]),
.ce2(1'b1),
.a2(dmem_a[12:2]),
.we2(dmem_we & (dmem_a[1:0] == 2'd0)),
.di2(dmem_di),
.do2(dmem_do3)
);
reg [1:0] dmem_a01;
always @(posedge usb_clk) dmem_a01 <= dmem_a[1:0];
always @(*) begin
case(dmem_a01)
2'd0: dmem_do = dmem_do3;
2'd1: dmem_do = dmem_do2;
2'd2: dmem_do = dmem_do1;
2'd3: dmem_do = dmem_do0;
endcase
end
reg datasel;
always @(posedge sys_clk) datasel <= wb_adr_i[17];
assign wb_dat_o = datasel ? wb_dat_o_data : wb_dat_o_prog;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000010; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int lcm(int a, int b) { return a * b / gcd(a, b); } int main(void) { int c, d, n, m, k, i, j, ans = 10000; scanf( %d %d %d %d %d , &c, &d, &n, &m, &k); for (i = 0; i <= 10000; i++) for (j = 0; j <= 10000; j++) if (i * n + j >= n * m - k) ans = min(ans, i * c + j * d); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long maxN = 1e6 + 5; const long long inf = 1e10; const long long mod = 1e9 + 7; long long n; long long ans = 1; long long res[maxN]; void normalSieve(long long n) { for (long long i = 1; i <= n; i++) res[i] = 1; for (long long i = 2; i * i <= n; i++) { if (res[i] == 1) { for (long long j = i * i; j <= n; j += i) { res[j] = 2; ans = 2; } } } } int main() { ios_base::sync_with_stdio(0); cin >> n; normalSieve(n + 1); cout << ans << endl; for (long long i = 2; i <= n + 1; i++) cout << res[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> b[5001]; for (int i = 0; i < n; i++) { string s; int a, b1, c; cin >> s >> a >> b1; if (s[0] == M ) c = 0; else c = 1; b[i].push_back(c); b[i].push_back(a); b[i].push_back(b1); } int ans = 0; for (int i = 1; i <= 366; i++) { int m[2] = {}; for (int j = 0; j < n; j++) { if (b[j][1] <= i && b[j][2] >= i) m[b[j][0]]++; } ans = max(ans, 2 * min(m[0], m[1])); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; class SegmentTree { private: vector<ll> aint; vector<ll> lazy; public: SegmentTree(int n) { aint.resize(1 + 4 * n); lazy.resize(1 + 4 * n); } void cleannode(int node, int from, int to) { int mid = (from + to) / 2; if (from < to) { lazy[node * 2] += lazy[node]; lazy[node * 2 + 1] += lazy[node]; } aint[node] = aint[node] + lazy[node]; lazy[node] = 0; } void computenode(int node, int from, int to) { if (from < to) { int mid = (from + to) / 2; aint[node] = max(aint[node * 2], aint[node * 2 + 1]); } } void update(int node, int from, int to, int x, int y, ll val) { cleannode(node, from, to); if (from == x && to == y) { lazy[node] += val; cleannode(node, from, to); } else { int mid = (from + to) / 2; cleannode(node * 2, from, mid); cleannode(node * 2 + 1, mid + 1, to); if (x <= mid) update(node * 2, from, mid, x, (((mid) < (y)) ? (mid) : (y)), val); if (mid + 1 <= y) update(node * 2 + 1, mid + 1, to, (((mid + 1) < (x)) ? (x) : (mid + 1)), y, val); computenode(node, from, to); } } ll query(int node, int from, int to, int x, int y) { cleannode(node, from, to); if (from == x && to == y) return aint[node]; else { int mid = (from + to) / 2; if (x <= mid && y <= mid) return query(node * 2, from, mid, x, y); else if (mid + 1 <= x && mid + 1 <= y) return query(node * 2 + 1, mid + 1, to, x, y); else return max(query(node * 2, from, mid, x, mid), query(node * 2 + 1, mid + 1, to, mid + 1, y)); } } }; int const nmax = 200000; int v[1 + nmax]; vector<pair<int, int>> g[1 + nmax]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) cin >> v[i]; for (int i = 1; i <= m; i++) { int x, y, cost; cin >> x >> y >> cost; g[y].push_back({x, cost}); } SegmentTree aint(n); for (int i = 1; i <= n; i++) { ll result = aint.query(1, 0, n, 0, i - 1); aint.update(1, 0, n, i, i, result); aint.update(1, 0, n, 0, i - 1, -v[i]); for (int h = 0; h < g[i].size(); h++) { int x = g[i][h].first, cost = g[i][h].second; aint.update(1, 0, n, 0, x - 1, cost); } } cout << aint.query(1, 0, n, 0, n); return 0; } |
#include <bits/stdc++.h> const int N = 120000; using namespace std; vector<string> fig; int n, m; vector<vector<string> > figs; int ans; vector<pair<pair<int, int>, int> > avec; int board[200][200]; bool bad(int a, int b) { return (a < 0 || a >= n || b < 0 || b >= m || board[a][b] == 1); } vector<string> rotate(vector<string> cur) { char temp[10][10]; for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { temp[i][j] = cur[i][j]; } } for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { cur[i][j] = temp[j][2 - i]; } } return cur; } vector<pair<pair<int, int>, int> > cur; bool can_put(int x, int y, int id) { for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { if (figs[id][i][j] == # ) { if (bad(i + x, j + y)) return false; } } } return true; } void do_put(int x, int y, int id) { for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { if (figs[id][i][j] == # ) { board[x + i][y + j] = 1; } } } cur.push_back(make_pair(make_pair(x, y), id)); } void unroll(int x, int y, int id) { for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { if (figs[id][i][j] == # ) { board[x + i][y + j] = 0; } } } cur.pop_back(); } int flag, iters; void dfs(int a, int b) { int rem_area = n * m - (a * m + b); if (cur.size() + rem_area / 5 <= avec.size()) return; ++iters; if (iters % 1024 == 0) { double R = clock() * 1.0 / CLOCKS_PER_SEC; if (R > 1.4) flag = 1; } if (flag) return; if (cur.size() > avec.size()) { avec = cur; } if (a >= n - 2) { return; } for (int i = 0; i < 4; i++) { if (can_put(a, b, i)) { do_put(a, b, i); if (b + 1 == m) dfs(a + 1, 0); else dfs(a, b + 1); unroll(a, b, i); } } if (b + 1 == m) dfs(a + 1, 0); else dfs(a, b + 1); } int main() { ios_base::sync_with_stdio(0); fig.push_back( ### ); fig.push_back( .#. ); fig.push_back( .#. ); figs.push_back(fig); for (int i = 0; i < 3; i++) { figs.push_back(rotate(figs.back())); } cin >> n >> m; dfs(0, 0); cout << avec.size() << endl; for (int i = 0; i < avec.size(); i++) { int qi, qj; qi = avec[i].first.first; qj = avec[i].first.second; for (int a = 0; a < 3; a++) { for (int b = 0; b < 3; b++) { if (figs[avec[i].second][a][b] == # ) { board[qi + a][qj + b] = i + 1; } } } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (board[i][j] == 0) cout << . ; else cout << char( A + board[i][j] - 1); } cout << endl; } cin.get(); cin.get(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a[26][26] = {0}, n, mini = -1; cin >> n; while (n--) { char c[11]; scanf( %s , c); int k = strlen(c), i = c[0] - a , j = c[k - 1] - a ; for (int m = 0; m < 26; m++) if (a[m][i]) a[m][j] = max(a[m][j], a[m][i] + k); a[i][j] = max(a[i][j], k); mini = max(mini, a[j][j]); } cout << mini; } |
// pr1755593
module main;
wire out;
reg [4:0] data;
reg [2:0] sel;
test U1(out, data[0], data[1], data[2], data[3], sel[0], sel[1]);
initial begin
for (sel=0 ; sel<4 ; sel=sel+1)
for (data=0 ; data<16 ; data=data+1) begin
#1 if (out !== data[sel]) begin
$display("FAILED -- data=%b, sel=%d", data, sel);
$finish;
end
end
$display("PASSED");
end
endmodule // main
module test (Z, D0, D1, D2, D3, E0, E1);
output Z;
input D0;
input D1;
input D2;
input D3;
input E0;
input E1;
u_test I48 (Z, D0, D1, D2, D3, E0, E1);
endmodule
primitive u_test (Z, D0, D1, D2, D3, E0, E1);
output Z;
input D0, D1, D2, D3, E0, E1;
table
0 ? ? ? 0 0 : 0 ;
1 ? ? ? 0 0 : 1 ;
? 0 ? ? 1 0 : 0 ;
? 1 ? ? 1 0 : 1 ;
? ? 0 ? 0 1 : 0 ;
? ? 1 ? 0 1 : 1 ;
? ? ? 0 1 1 : 0 ;
? ? ? 1 1 1 : 1 ;
0 0 ? ? x 0 : 0 ;
1 1 ? ? x 0 : 1 ;
? ? 0 0 x 1 : 0 ;
? ? 1 1 x 1 : 1 ;
0 ? 0 ? 0 x : 0 ;
1 ? 1 ? 0 x : 1 ;
? 0 ? 0 1 x : 0 ;
? 1 ? 1 1 x : 1 ;
0 0 0 0 x x : 0 ;
1 1 1 1 x x : 1 ;
endtable
endprimitive
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char *argv[]) { long long n, k, a[55]; cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + 1 + n); if (k > n) cout << -1 << endl; else { cout << a[n + 1 - k] << << a[n + 1 - k] << endl; } return EXIT_SUCCESS; } |
#include <bits/stdc++.h> using namespace std; long long n, s, l, r, res, cur, maxx = -9999999999; int main() { cin >> n >> s; for (long long i = 1; i <= n; i++) { cin >> l >> r; maxx = max(maxx, l + r); } cout << max(maxx, s); return 0; } |
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 4096,
the_altsyncram.numwords_a = 4096,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 100005; const int oo = 1e9 + 7; const long long mod = 1e9 + 7; const double eps = 1e-11; long long n; int main() { cin.sync_with_stdio(false); cin.tie(0); cin >> n; cout << (n - 2LL) * (n - 2LL) << endl; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:38:51 05/09/2016
// Design Name:
// Module Name: negexp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module negexp( // Input and output are in single precision floating point values
input clk,
input rst,
input [31:0] inp,
input inp_valid,
output [31:0] out,
output out_valid,
output [7:0] debug
);
// A single stage in our setup: result = 1.0 + A * B * C
// The latency of each component is zero, at least at the moment.
reg [31:0] a_q, a_d, b_q, b_d, c_q, c_d;
reg stage_start_q, stage_start_d;
wire [31:0] fmult_tdata;
wire fmult_tvalid;
reg fmult_start_q, fmult_start_d;
reg [31:0] fmult_a_q, fmult_a_d, fmult_b_q, fmult_b_d;
floating_point_mult fmult(
.aclk(clk),
.s_axis_a_tvalid(fmult_start_q),
.s_axis_b_tvalid(fmult_start_q),
.s_axis_a_tdata(fmult_a_q),
.s_axis_b_tdata(fmult_b_q),
.m_axis_result_tvalid(fmult_tvalid),
.m_axis_result_tdata(fmult_tdata)
);
reg [31:0] adder_in_q, adder_in_d;
reg adder_start_q, adder_start_d;
wire adder_valid;
wire [31:0] adder_res;
floating_point_add stage1_add(
.aclk(clk),
.s_axis_a_tvalid(adder_start_q),
.s_axis_a_tdata(adder_in_q),
.s_axis_b_tvalid(1'b1),
.s_axis_b_tdata(32'h3f800000),
.m_axis_result_tvalid(adder_valid),
.m_axis_result_tdata(adder_res)
);
// The logic to repeatadly run this stage
reg [3:0] iters_left_q, iters_left_d;
reg [31:0] out_q, out_d;
reg out_valid_q, out_valid_d, finishing_q, finishing_d;
// The logic to run multiplication, which takes two steps
reg [1:0] mult_q, mult_d;
assign out = out_q;
assign out_valid = out_valid_q;
assign debug = 8'b0;//{iters_left_q, 1'b0, stage1_valid, stage2_valid, adder_valid};
// 1, 0.5, 0.3333, 0.25
localparam CONSTANT_TABLE = {32'h3f800000, 32'h3f000000, 32'h3eaaaaab, 32'h3e800000};
//`define CONSTANT(i) (CONSTANT_TABLE[(3-i)*32-1:(3-i-1)*32]&32'hffffffff)
`define CONSTANT(i) ((CONSTANT_TABLE>>((4-i)*32))&32'hffffffff)
always @(*) begin
a_d = a_q;
b_d = b_q;
c_d = c_q;
iters_left_d = iters_left_q;
stage_start_d = 0;//stage_start_q;
out_d = out_q;
out_valid_d = 0;
finishing_d = finishing_q;
fmult_a_d = fmult_a_q;
fmult_b_d = fmult_b_q;
fmult_start_d = 0;
mult_d = mult_q;
adder_in_d = adder_in_q;
adder_start_d = 0;
if (mult_q == 1) begin // Multiplying a_q and b_q
if (fmult_tvalid) begin
mult_d = 2;
fmult_a_d = fmult_tdata;
fmult_b_d = c_d;
fmult_start_d = 1;
end
end else if (mult_q == 2) begin // Multiplying res by c_q
if (fmult_tvalid) begin
// Kick off the addition
adder_in_d = fmult_tdata;
adder_start_d = 1;
mult_d = 3;
end
end else if (iters_left_q == 0) begin
if (finishing_q) begin
out_d = adder_res;
out_valid_d = 1;
finishing_d = 0;
end
if (inp_valid) begin
// We're ready to roll!
iters_left_d = 4;
a_d = inp;
b_d = 32'h3f800000; // Start out at 1
c_d = `CONSTANT(4);
//stage_start_d = 1;
mult_d = 1;
fmult_a_d = a_d;
fmult_b_d = b_d;
fmult_start_d = 1;
end
end else if (adder_valid) begin
// We have to setup the next round
iters_left_d = iters_left_q - 1;
b_d = adder_res;
c_d = `CONSTANT(iters_left_q+1);
stage_start_d = 1;
finishing_d = 1;
mult_d = 1;
fmult_a_d = a_d;
fmult_b_d = b_d;
fmult_start_d = 1;
end
end
always @(posedge clk) begin
if (rst) begin
iters_left_q <= 0;
stage_start_q <= 0;
finishing_q <= 0;
fmult_start_q <= 0;
adder_start_q <= 0;
end else begin
stage_start_q <= stage_start_d;
a_q <= a_d;
b_q <= b_d;
c_q <= c_d;
iters_left_q <= iters_left_d;
out_q <= out_d;
out_valid_q <= out_valid_d;
finishing_q <= finishing_d;
mult_q <= mult_d;
fmult_a_q <= fmult_a_d;
fmult_b_q <= fmult_b_d;
fmult_start_q <= fmult_start_d;
adder_in_q <= adder_in_d;
adder_start_q <= adder_start_d;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int w, h, k; cin >> w >> h >> k; int s = 0; w -= 2; for (int i = 0; i < k; i++) { s += (w + h) * 2; w -= 4; h -= 4; } cout << s; } |
#include <bits/stdc++.h> using namespace std; int main() { char ch1, ch2, ch; int i, j, k, tc, res, total, temp, mx, num, num1, num2; int n, a, b; { scanf( %d %d %d , &n, &a, &b); if (b == 0) printf( %d n , a); else if (b > 0) { while (b--) { if (a == n) a = 1; else a++; } printf( %d n , a); } else { b = (-1 * b); while (b--) { if (a == 1) a = n; else a--; } printf( %d n , a); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 1; int n, m, q, p[N], dis[N], far, cur, sz[N]; vector<int> g[N]; unordered_map<int, double> dp[N]; vector<pair<int, long long>> v[N]; int get(int u) { return p[u] == u ? u : p[u] = get(p[u]); } void dfs(int u, int p, int depth) { dis[u] = max(dis[u], depth); if (dis[u] > cur) { cur = dis[u]; far = u; } for (auto i : g[u]) if (i != p) dfs(i, u, depth + 1); } double calc(int a, int b) { if (dp[a].find(b) != dp[a].end()) return dp[a][b]; double ans = 0; int mx = max(v[a].back().first, v[b].back().first); for (int i = v[a].size() - 1, j = 0; i + 1; i--) { while (j < v[b].size() && v[a][i].first + v[b][j].first + 1 <= mx) j++; ans += mx * 1LL * j; if (j < v[b].size()) { ans += v[b].back().second + v[b].size() - j + v[a][i].first * 1LL * (v[b].size() - j); if (j) ans -= v[b][j - 1].second; } } ans /= v[a].size() * 1LL * v[b].size(); return dp[a][b] = dp[b][a] = ans; } int main() { scanf( %d%d%d , &n, &m, &q); int z = sqrt(n); for (int i = 0; i < n; i++) p[i] = i, sz[i] = 1; for (int i = 0, a, b; i < m; i++) { scanf( %d%d , &a, &b); --a; --b; sz[get(b)] += sz[get(a)]; p[get(a)] = get(b); g[a].push_back(b); g[b].push_back(a); } for (int i = 0; i < n; i++) if (p[i] == i) { cur = -1e9; dfs(i, -1, 0); cur = -1e9; dfs(far, -1, 0); cur = -1e9; dfs(far, -1, 0); } for (int i = 0; i < n; i++) v[get(i)].push_back({dis[i], dis[i]}); for (int i = 0; i < n; i++) sort(v[i].begin(), v[i].end()); for (int i = 0; i < n; i++) if (i == p[i]) for (int j = 1; j < v[i].size(); j++) v[i][j].second += v[i][j - 1].second; for (int i = 0, a, b; i < q; i++) { scanf( %d%d , &a, &b); --a; --b; a = get(a); b = get(b); if (a == b) { puts( -1 ); continue; } if (sz[a] > sz[b]) swap(a, b); printf( %.10lf n , calc(a, b)); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O22AI_FUNCTIONAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_FUNCTIONAL_V |
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
David Fritz
plpid module
a simple cpuid module that is used to determine in software the board
id and frequency.
*/
module mod_plpid(rst, clk, ie, de, iaddr, daddr, drw, din, iout, dout);
input rst;
input clk;
input ie,de;
input [31:0] iaddr, daddr;
input [1:0] drw;
input [31:0] din;
output [31:0] iout, dout;
/* by spec, the iout and dout signals must go hiZ when we're not using them */
wire [31:0] idata, ddata;
assign iout = idata;
assign dout = ddata;
parameter cpu_id = 32'h00000401;
parameter board_freq = 32'h017d7840; /* 25 mhz */
assign ddata = (daddr == 0) ? cpu_id :
(daddr == 4) ? board_freq : 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR3_BLACKBOX_V
`define SKY130_FD_SC_LP__XNOR3_BLACKBOX_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xnor3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR3_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:102400000,102400000 ) const int maxn = 1e5 + 300; const int INF = 0x3f3f3f3f; int main() { int k; scanf( %d , &k); if (k == 1) { puts( YES n2 1 n1 2 ); } else if (k % 2 == 0) { puts( NO ); } else { puts( YES ); printf( %d %d n , 2 * k + 4, k * (k + 2)); for (int i = 2; i <= k; i++) { printf( 1 %d n , i); } int nn = k + 2; for (int i = 2; i <= k; i++) { printf( %d %d n , i, k + 1); printf( %d %d n , i, k + 2); for (int j = i + 1; j <= k; j++) { if (i % 2 == 0 && j == i + 1) continue; printf( %d %d n , i, j); } } printf( %d %d n , k + 1, k + 2); for (int i = 2; i <= k; i++) { printf( %d %d n , 1 + nn, i + nn); } for (int i = 2; i <= k; i++) { printf( %d %d n , i + nn, nn + k + 1); printf( %d %d n , i + nn, nn + k + 2); for (int j = i + 1; j <= k; j++) { if (i % 2 == 0 && j == i + 1) continue; printf( %d %d n , i + nn, j + nn); } } printf( %d %d n , k + 1 + nn, k + 2 + nn); printf( %d %d n , 1, nn + 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-11; int vex[4] = {1, 0, -1, 0}; int vey[4] = {0, 1, 0, -1}; long long int MOD = 1000000007; const int MAX = 3000000; string c[100005]; char s[MAX]; int main() { int n; cin >> n; using p = pair<int, pair<int, int>>; using po = pair<int, int>; vector<p> d; for (int i = 0; i < (MAX); i++) s[i] = * ; int last = 0; int a, b; for (int i = 0; i < (n); i++) { cin >> c[i]; int t = c[i].size(); cin >> a; for (int j = 0; j < (a); j++) { cin >> b; b--; d.push_back(p(b, po(b + t, i))); } } sort(d.begin(), d.end()); int in = d.size(); for (int j = 0; j < (in - 1); j++) { auto l = d[j]; auto r = d[j + 1]; if (l.first == r.first) continue; for (int k = max(l.first, last); k < l.second.first; k++) { s[k] = c[l.second.second][k - l.first]; } last = max(l.second.first, last); } auto l = d[in - 1]; for (int k = l.first; k < l.second.first; k++) { s[k] = c[l.second.second][k - l.first]; } string ans = ; int la = 0; for (int i = (MAX)-1; i >= 0; i--) { if (s[i] != * ) { la = i; break; } } for (int i = 0; i < (la + 1); i++) { if (s[i] == * ) cout << a ; else cout << s[i]; } cout << endl; } |
#include <bits/stdc++.h> using namespace std; long parent[100]; long nm[100]; vector<long> v[100]; long pp(long z) { if (parent[z] == z) { return z; } else { parent[z] = pp(parent[z]); } } int main() { long i, j, k, l, m, n, p, two, one; scanf( %ld%ld , &n, &m); for (i = 1; i <= n; i++) parent[i] = i; for (i = 1; i <= m; i++) { scanf( %ld%ld , &k, &l); parent[l] = k; } for (i = 1; i <= n; i++) { k = pp(i); } for (i = 1; i <= n; i++) { nm[parent[i]]++; if (nm[parent[i]] > 3) { printf( -1 n ); return 0; } } l = one = two = 0; for (i = 1; i <= n; i++) { if (nm[i] == 3) { k = 0; for (j = 1; j <= n; j++) { if (parent[j] == i) { v[l].push_back(j); parent[j] = -1; k++; } } nm[i] = -1; l++; } if (nm[i] == 2) two++; else if (nm[i] == 1) one++; } if (one >= two) { if ((one - two) % 3) { printf( -1 n ); return 0; } while (two) { for (i = 1; i <= n; i++) { if (nm[i] == 2) { for (j = 1; j <= n; j++) { if (nm[j] == 1) { for (k = 1; k <= n; k++) { if (parent[k] == j) { v[l].push_back(k); nm[j] = -1; parent[k] = -1; break; } } break; } } for (j = 1; j <= n; j++) { if (parent[j] == i) { v[l].push_back(j); parent[j] = -1; } } nm[i] = -1; two--; one--; l++; break; } } } while (one) { k = 0; for (i = 1; i <= n; i++) { if (nm[i] == 1) { v[l].push_back(i); nm[i] = -1; k++; one--; if (k == 3) { l++; break; } } } } for (i = 0; i < l; i++) printf( %ld %ld %ld n , v[i][0], v[i][1], v[i][2]); } else { printf( -1 n ); return 0; } return 0; } |
/**
* bsg_lru_pseudo_tree_backup.v
*
* tree pseudo LRU backup finder.
*
* Given the bit vector of disabled ways, it will tell
* you bit-mask and data to modify the original LRU bits to obtain
* the backup LRU.
*
* The algorithm to find backup_LRU is:
* start from the root of the LRU tree, and traverse down the tree in the
* direction of the LRU bits, if there is at least one unlocked way in that
* direction. If not, take the opposite direction.
*
*
* ==== Example ==============================================
*
* rank=0 [0]
* 0
* / \
* rank=1 [1] [2]
* 1 0
* / \ / \
* rank=2 [3] [4] [5] [6]
* 1 0 1 1
* / \ / \ / \ / \
* way w0 w1 w2 w3 w4 w5 w6 w7
*
*
* Let say LRU bits were 7'b110_1010 so that LRU way is w2.
* If the disabled ways are {w2}, then backup_LRU = w3.
* If the disabled are {w2,w3}, then backup_LRU = w1
* If the disabled are {w0,w1,w2,w3}, the backup_LRU = w5.
*
* ============================================================
*
* @author tommy
*
*
*/
`include "bsg_defines.v"
module bsg_lru_pseudo_tree_backup
#(parameter `BSG_INV_PARAM(ways_p)
, parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
)
(
input [ways_p-1:0] disabled_ways_i
, output logic [`BSG_SAFE_MINUS(ways_p, 2):0] modify_mask_o
, output logic [`BSG_SAFE_MINUS(ways_p, 2):0] modify_data_o
);
// If direct-mapped there is no meaning to backup LRU
if (ways_p == 1) begin: no_lru
assign modify_mask_o = 1'b1;
assign modify_data_o = 1'b0;
end
else begin: lru
// backup LRU logic
// i = rank
for (genvar i = 0; i < lg_ways_lp; i++) begin
logic [(2**(i+1))-1:0] and_reduce;
// j = bucket
for (genvar j = 0; j < (2**(i+1)); j++)
assign and_reduce[j] = &disabled_ways_i[(ways_p/(2**(i+1)))*j+:(ways_p/(2**(i+1)))];
// k = start index in LRU bits
for (genvar k = 0; k < (2**(i+1))/2; k++) begin
assign modify_data_o[(2**i)-1+k] = and_reduce[2*k];
assign modify_mask_o[(2**i)-1+k] = |and_reduce[2*k+:2];
end
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_lru_pseudo_tree_backup)
|
#include <bits/stdc++.h> int any_table[11][11]; struct DammedPascalNUmber { int tb[13][13]; DammedPascalNUmber() { int i, j; for (i = 0; i <= 12; i++) for (j = 0; j <= i; j++) { int &r = tb[i][j]; if (j == 0 || i == 0) r = 1; else r = tb[i - 1][j - 1] + tb[i - 1][j]; } } int count(int n, int m) { return tb[n][m]; } } pas; int any(int dig, int amo) { if (dig < amo) return 0; if (amo < 0) return 0; if (dig == 0) return 1; int &r = any_table[dig][amo]; int i; if (r >= 0) return r; r = 1; for (i = 0; i < amo; i++) r *= 2; for (; i < dig; i++) r *= 8; r *= pas.count(dig, amo); return r; } int check(int m, int n) { int i, j, t, r = 0; for (i = 1; i <= m; i++) { char str[15]; t = 0; sprintf(str, %d , i); for (j = 0; str[j]; j++) if (str[j] == 4 || str[j] == 7 ) t++; if (t == n) r++; } return r; } int a[13]; int dfs(int party, int quta) { int r = 0, i; if (party == 6) { return 1; } for (i = quta; i >= 0; i--) if (a[i] > 0) { int t = a[i]; a[i]--; r = (1LL * r + 1LL * t * 1LL * dfs(party + 1, quta - i) + 1LL * 1000000007) % 1000000007; a[i]++; } return r; } void test(int n, int m) { printf( any(%d,%d)=%d n , n, m, any(n, m)); } void test2(int m, int n) { printf( (%d,%d)=%d a[%d]=%d n , m, n, check(m, n), n, a[n]); } int main() { memset(any_table, -1, sizeof(any_table)); int m, s, i, j, k, sn, lucked; while (~scanf( %d , &m)) { memset(a, 0, sizeof(a)); char str[15]; sprintf(str, %d , m); for (sn = 0; str[sn]; sn++) ; for (j = sn; j > 0; j--) { a[j] = 0; lucked = 0; for (i = 0; i < sn; i++) { int p = 0, q = 0; k = str[i] - 0 - 1; for (; k >= 0; k--) if (k == 4 || k == 7) q++; else p++; if (p) a[j] += p * any(sn - i - 1, j - lucked); if (q) a[j] += q * any(sn - i - 1, j - lucked - 1); if (str[i] == 4 || str[i] == 7 ) { lucked++; } if (i == sn - 1 && lucked == j) a[j]++; } } a[0] = m; for (i = 1; i <= sn; i++) a[0] -= a[i]; int ans = 0; for (i = 1; i <= sn; i++) if (a[i]) { ans = (1LL * ans + 1LL * a[i] * dfs(0, i - 1) + 1LL * 1000000007) % 1000000007; } printf( %d n , ans); } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_64
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_64(
input wire [54:0] Data_Dec_i,
output reg [5:0] Data_Bin_o
);
parameter SWR = 55;
always @(Data_Dec_i)
begin
Data_Bin_o=6'b000000;
if(~Data_Dec_i[54]) begin Data_Bin_o = 6'b000000;//0
end else if(~Data_Dec_i[53]) begin Data_Bin_o = 6'b000001;//1
end else if(~Data_Dec_i[52]) begin Data_Bin_o = 6'b000010;//2
end else if(~Data_Dec_i[51]) begin Data_Bin_o = 6'b000011;//3
end else if(~Data_Dec_i[50]) begin Data_Bin_o = 6'b000100;//4
end else if(~Data_Dec_i[49]) begin Data_Bin_o = 6'b000101;//5
end else if(~Data_Dec_i[48]) begin Data_Bin_o = 6'b000110;//6
end else if(~Data_Dec_i[47]) begin Data_Bin_o = 6'b000111;//7
end else if(~Data_Dec_i[46]) begin Data_Bin_o = 6'b001000;//8
end else if(~Data_Dec_i[45]) begin Data_Bin_o = 6'b001001;//9
end else if(~Data_Dec_i[44]) begin Data_Bin_o = 6'b001010;//10
end else if(~Data_Dec_i[43]) begin Data_Bin_o = 6'b001011;//11
end else if(~Data_Dec_i[42]) begin Data_Bin_o = 6'b001100;//12
end else if(~Data_Dec_i[41]) begin Data_Bin_o = 6'b001101;//13
end else if(~Data_Dec_i[40]) begin Data_Bin_o = 6'b001110;//14
end else if(~Data_Dec_i[39]) begin Data_Bin_o = 6'b001111;//15
end else if(~Data_Dec_i[38]) begin Data_Bin_o = 6'b010000;//16
end else if(~Data_Dec_i[37]) begin Data_Bin_o = 6'b010001;//17
end else if(~Data_Dec_i[36]) begin Data_Bin_o = 6'b010010;//18
end else if(~Data_Dec_i[35]) begin Data_Bin_o = 6'b010011;//19
end else if(~Data_Dec_i[34]) begin Data_Bin_o = 6'b010100;//20
end else if(~Data_Dec_i[33]) begin Data_Bin_o = 6'b010101;//21
end else if(~Data_Dec_i[32]) begin Data_Bin_o = 6'b010110;//22
end else if(~Data_Dec_i[31]) begin Data_Bin_o = 6'b010111;//23
end else if(~Data_Dec_i[30]) begin Data_Bin_o = 6'b011000;//24
end else if(~Data_Dec_i[29]) begin Data_Bin_o = 6'b010101;//25
end else if(~Data_Dec_i[28]) begin Data_Bin_o = 6'b010110;//26
end else if(~Data_Dec_i[27]) begin Data_Bin_o = 6'b010111;//27
end else if(~Data_Dec_i[26]) begin Data_Bin_o = 6'b011000;//28
end else if(~Data_Dec_i[25]) begin Data_Bin_o = 6'b011001;//29
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 6'b011010;//30
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 6'b011011;//31
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 6'b011100;//32
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 6'b011101;//33
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 6'b011110;//34
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 6'b011111;//35
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 6'b100000;//36
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 6'b100001;//37
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 6'b100010;//38
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 6'b100011;//39
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 6'b100100;//40
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 6'b100101;//41
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 6'b100110;//42
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 6'b100111;//43
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 6'b101000;//44
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 6'b101001;//45
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 6'b101010;//46
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 6'b101011;//47
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 6'b101100;//48
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 6'b101101;//49
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 6'b101110;//50
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 6'b101111;//51
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 6'b110000;//52
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 6'b110001;//53
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 6'b110010;//54
end else begin Data_Bin_o = 6'b000000;//zero value
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__OR4_PP_BLACKBOX_V
/**
* or4: 4-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2020, mod = 1000000007; int n, m, t = 0, a[N] = {}, vis[N] = {}; int *f[N] = {}, *g, *h, arr[N][N << 2] = {}; vector<int> e[N]; long long ans = 0; int main() { cin >> n >> m; for (int i = 1, u, v; i <= m; ++i) { cin >> u >> v; e[u].push_back(v); e[v].push_back(u); } for (auto x : e[1]) if (!vis[x]) { int l = 1, now = x, last = 1, tmp; vis[now] = true; while (now != 1) { tmp = last; last = now; now = e[now][e[now][0] == tmp]; vis[now] = true; ++l; } a[++t] = l; } for (int i = 0; i <= t; ++i) f[i] = arr[i] + m; f[0][0] = 1; for (int i = 1; i <= t; ++i) for (int v = -m; v <= m; ++v) { if (v + a[i] <= m) f[i][v] = (f[i][v] + f[i - 1][v + a[i]]) % mod; if (v - a[i] >= -m) f[i][v] = (f[i][v] + f[i - 1][v - a[i]]) % mod; f[i][v] = (f[i][v] + f[i - 1][v]) % mod; } g = arr[t + 1] + m; h = arr[t + 2] + m; for (int i = 1; i <= t; ++i) { copy(f[t] - m, f[t] + m + 1, g - m); fill(h - m, h + m + 1, 0); for (int v = -m; v <= m; ++v) { g[v + a[i]] = (g[v + a[i]] + mod - g[v]) % mod; g[v + a[i] + a[i]] = (g[v + a[i] + a[i]] + mod - g[v]) % mod; h[v + a[i]] = g[v]; g[v] = 0; } for (int v = -a[i] + 2; v <= a[i] - 2; ++v) ans = (ans + h[v] * 2 % mod) % mod; } memset(arr, 0, sizeof(arr)); f[0][0] = 1; for (int i = 1; i <= t; ++i) for (int v = -m; v <= m; ++v) { if (v + a[i] <= m) f[i][v] = (f[i][v] + f[i - 1][v + a[i]]) % mod; if (v - a[i] >= -m) f[i][v] = (f[i][v] + f[i - 1][v - a[i]]) % mod; } g = arr[t + 1] + m; h = arr[t + 2] + m; for (int i = 1; i <= t; ++i) { copy(f[t] - m, f[t] + m + 1, g - m); fill(h - m, h + m + 1, 0); for (int v = -m; v <= m; ++v) { g[v + a[i] + a[i]] = (g[v + a[i] + a[i]] + mod - g[v]) % mod; h[v + a[i]] = g[v]; g[v] = 0; } ans = (ans + h[a[i] - 1] * 2ll + h[1 - a[i]] * 2ll) % mod; } ans = (ans + f[t][0]) % mod; cout << ans << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MUX4_FUNCTIONAL_V
`define SKY130_FD_SC_LS__MUX4_FUNCTIONAL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_4to2/sky130_fd_sc_ls__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_ls__mux4 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
// Module ports
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Local signals
wire mux_4to20_out_X;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_4to2 mux_4to20 (mux_4to20_out_X, A0, A1, A2, A3, S0, S1);
buf buf0 (X , mux_4to20_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__MUX4_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 210; int n, m, ans[maxn]; string s[maxn]; int solve(string s) { for (int i = 10; i >= 0; i--) { bool flag = 0; for (int j = 0; j < (1 << i); j++) { string t; for (int k = 0; k < i; k++) if (j & (1 << k)) t += 1 ; else t += 0 ; if (s.find(t) == s.npos) { flag = 1; break; } } if (!flag) return i; } return 0; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) cin >> s[i]; scanf( %d , &m); for (int i = n + 1; i <= n + m; i++) { int a, b; scanf( %d%d , &a, &b); s[i] = s[a] + s[b]; if (s[i].length() > 1000) s[i] = s[i].substr(0, 500) + s[i].substr(s[i].length() - 500, 500); ans[i] = max(solve(s[i]), max(ans[a], ans[b])); printf( %d n , ans[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, i, o = 0; cin >> n; long long int a[n]; for (i = 0; i < n; ++i) { cin >> a[i]; if (a[i] & 1) o++; } cout << min(o, n - o); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32AI_4_V
`define SKY130_FD_SC_HD__O32AI_4_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o32ai_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32AI_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; long long x, a, b, i, f = 1, pa, push_back; vector<pair<long long, long long> > v(n); vector<long long> ch; cin >> x; cin >> a >> b; pa = a, push_back = b; if (a + b == 7) f = 0; for (i = 1; i < n; i++) { cin >> a >> b; if (f == 1) { if (a + b != 7) { if (a == pa || a == 7 - pa || a == push_back || a == 7 - push_back) { if (b == pa || b == 7 - pa || b == push_back || b == 7 - push_back) { f = 1; } else f = 0; } else f = 0; } else f = 0; } pa = a, push_back = b; } if (f == 1) { cout << YES << endl; } else { cout << NO << endl; } } |
#include <bits/stdc++.h> using namespace std; int n, m, k, c, x, y, rem; char a[501][501]; int v[501][501]; void dfs(int x, int y) { if (rem == 0 || a[x][y] == # ) return; if (x < 0 || x >= n || y < 0 || y >= m || v[x][y] == 1) return; v[x][y] = 1; rem--; dfs(x + 1, y); dfs(x, y + 1); dfs(x, y - 1); dfs(x - 1, y); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m >> k; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> a[i][j]; if (a[i][j] == . ) { c++; if (c == 1) { x = i; y = j; } } } rem = c - k; dfs(x, y); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (v[i][j] == 0 && a[i][j] == . ) cout << X ; else cout << a[i][j]; } cout << n ; } } |
#include <bits/stdc++.h> const int N = 1e6 + 5; const int mod = 1e9 + 7; const int MOD = mod - 1; const double eps = 1e-18; const double PI = acos(-1.0); using namespace std; char s[200]; int main() { int n, m; scanf( %d , &n), scanf( %d , &m); scanf( %s , s + 1); int l = strlen(s + 1); while (m--) { int l, r; char a, b; scanf( %d %d %c %c , &l, &r, &a, &b); getchar(); for (int i = l; i <= r; i++) if (s[i] == a) s[i] = b; } puts(s + 1); } |
#include <bits/stdc++.h> using namespace std; int n, k, sum1, sum2; string a; int f[300011]; void solve() { scanf( %d%d , &n, &k); cin >> a; memset(f, -1, sizeof(f)); for (int i = 0; i < n; i++) { if (a[i] != ? ) { if (f[i % k] == -1) f[i % k] = a[i] - 0 ; else if (f[i % k] != (int)(a[i] - 0 )) { cout << NO << endl; return; } } } sum1 = sum2 = 0; for (int i = 0; i < k; i++) { sum1 += (f[i] == 0); sum2 += (f[i] == 1); } if (sum1 > k / 2 || sum2 > k / 2) cout << NO << endl; else cout << YES << endl; } int main() { int T; scanf( %d , &T); while (T--) solve(); return 0; } |
#include <bits/stdc++.h> int main() { int x; scanf( %d , &x); if (x == 3) printf( 5 n ); else { for (int i = 1; i <= 100; i += 2) { if (i * i - (i * i) / 2 >= x) { printf( %d n , i); break; } } } } |
#include <bits/stdc++.h> using namespace std; int main() { string n; cin >> n; reverse(n.begin(), n.end()); int k = n[0] + 10 * n[1]; if (k % 4 == 0) { cout << 4 << endl; } else { cout << 0 << endl; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLRBP_FUNCTIONAL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_pg/sky130_fd_sc_hs__u_dl_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrbp (
VPWR ,
VGND ,
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hs__u_dl_p_r_pg `UNIT_DELAY u_dl_p_r_pg0 (buf_Q , D, GATE, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBP_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BOI_BLACKBOX_V
`define SKY130_FD_SC_HS__A21BOI_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BOI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__MUX2_PP_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2_PP_BLACKBOX_V
|
/*
* This file is part of the DSLogic-hdl project.
*
* Copyright (C) 2014 DreamSourceLab <>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/100ps
`define D #1
module reset(
// -- raw
input core_clk,
input sample_clk,
input sd_clk,
input usb_clk,
input sys_rst,
input sys_clr,
// -- sync
output core_rst,
output sample_rst,
output sd_rst,
output sdram_rst_,
output cfg_rst,
output usb_rst
);
wire clr_rst;
assign clr_rst = sys_rst | sys_clr;
// --
// core reset sync & stretch
// --
reg [3:0] core_rst_reg;
wire [3:0] core_rst_reg_nxt;
assign core_rst = core_rst_reg[3];
assign core_rst_reg_nxt = {core_rst_reg[2:0], 1'b0};
always @(posedge core_clk or posedge clr_rst)
begin
if (clr_rst)
core_rst_reg <= `D 4'b1111;
else
core_rst_reg <= `D core_rst_reg_nxt;
end
// --
// sample reset sync & stretch
// --
reg [17:0] sample_rst_reg;
wire [17:0] sample_rst_reg_nxt;
assign sample_rst = sample_rst_reg[17];
assign sample_rst_reg_nxt = {sample_rst_reg[16:0], 1'b0};
always @(posedge sample_clk or posedge clr_rst)
begin
if (clr_rst)
sample_rst_reg <= `D 18'b111111111111111111;
else
sample_rst_reg <= `D sample_rst_reg_nxt;
end
// --
// dwrite/dread reset sync & stretch
// --
reg [3:0] sd_rst_reg;
wire [3:0] sd_rst_reg_nxt;
assign sd_rst = sd_rst_reg[3];
assign sd_rst_reg_nxt = {sd_rst_reg[2:0], 1'b0};
always @(posedge sd_clk or posedge clr_rst)
begin
if (clr_rst)
sd_rst_reg <= `D 4'b1111;
else
sd_rst_reg <= `D sd_rst_reg_nxt;
end
// --
// sdram controller reset sync & stretch
// --
reg [3:0] sdram_rst_reg = 4'b0;
wire [3:0] sdram_rst_reg_nxt;
assign sdram_rst_ = sdram_rst_reg[3];
assign sdram_rst_reg_nxt = {sdram_rst_reg[2:0], 1'b1};
always @(posedge sd_clk)
begin
sdram_rst_reg <= `D sdram_rst_reg_nxt;
end
// --
// cfg reset sync & stretch
// --
reg [3:0] cfg_rst_reg;
wire [3:0] cfg_rst_reg_nxt;
assign cfg_rst = cfg_rst_reg[3];
assign cfg_rst_reg_nxt = {cfg_rst_reg[2:0], 1'b0};
always @(posedge usb_clk or posedge sys_rst)
begin
if (sys_rst)
cfg_rst_reg <= `D 4'b1111;
else
cfg_rst_reg <= `D cfg_rst_reg_nxt;
end
// --
// usb controller reset sync & stretch
// --
reg [3:0] usb_rst_reg;
wire [3:0] usb_rst_reg_nxt;
assign usb_rst = usb_rst_reg[3];
assign usb_rst_reg_nxt = {usb_rst_reg[2:0], 1'b0};
always @(posedge usb_clk or posedge clr_rst)
begin
if (clr_rst)
usb_rst_reg <= `D 4'b1111;
else
usb_rst_reg <= `D usb_rst_reg_nxt;
end
endmodule
|
// final sub module for text
module check_text
(
input wire clk,
input wire [9:0] pix_x, pix_y,
output wire [3:0] check_on,
output reg [2:0] check_rgb
// we output text_rgb only because we have to select it according to FSM
);
// signal declaration
wire [10:0] rom_addr;
reg [6:0] char_addr, char_addr_r;
// char_addr is the final address selected by MUX
// s stands for score (and ball, but I can not use sb...)
// l stands for logo (well, our special plalindrome logo WPPW)
// r stands for registration information (in this case, student ID and name)
// o stands for over (actually game over I assume, anyway)
reg [3:0] row_addr;
reg [2:0] bit_addr;
wire [7:0] font_word;
wire word_on, font_bit;
wire [5:0] word_rom_addr;
wire [3:0] row_addr_r;
wire [2:0] bit_addr_r;
// instantiate font ROM
font_rom font_unit
(.clk(clk), .addr(rom_addr), .data(font_word));
assign word_on = (pix_x[9:7]==2) && (pix_y[9:6]==2);
assign row_addr_r = pix_y[3:0];
assign bit_addr_r = pix_x[2:0];
assign word_rom_addr = {pix_y[5:4], pix_x[6:3]};
always @*
case (word_rom_addr)
// row 1 generated by MATLAB
6'h00: char_addr_r = 7'h62;
6'h01: char_addr_r = 7'h69;
6'h02: char_addr_r = 7'h79;
6'h03: char_addr_r = 7'h20;
6'h04: char_addr_r = 7'h20;
6'h05: char_addr_r = 7'h20;
6'h06: char_addr_r = 7'h20;
6'h07: char_addr_r = 7'h20;
6'h08: char_addr_r = 7'h20;
6'h09: char_addr_r = 7'h20;
6'h0A: char_addr_r = 7'h20;
6'h0B: char_addr_r = 7'h20;
6'h0C: char_addr_r = 7'h20;
6'h0D: char_addr_r = 7'h20;
// visualization
// well
6'h0E: char_addr_r = 7'h20;
6'h0F: char_addr_r = 7'h20;
// row 2
6'h10: char_addr_r = 7'h67;
6'h11: char_addr_r = 7'h69;
6'h12: char_addr_r = 7'h72;
6'h13: char_addr_r = 7'h6c;
6'h14: char_addr_r = 7'h20;
6'h15: char_addr_r = 7'h20;
6'h16: char_addr_r = 7'h20;
6'h17: char_addr_r = 7'h20;
6'h18: char_addr_r = 7'h20;
6'h19: char_addr_r = 7'h20;
6'h1A: char_addr_r = 7'h20;
6'h1B: char_addr_r = 7'h20;
6'h1C: char_addr_r = 7'h20;
6'h1D: char_addr_r = 7'h20;
// visualization
// well
6'h1E: char_addr_r = 7'h20;
6'h1F: char_addr_r = 7'h20;
// row 3
6'h20: char_addr_r = 7'h63;
6'h21: char_addr_r = 7'h61;
6'h22: char_addr_r = 7'h74;
6'h23: char_addr_r = 7'h20;
6'h24: char_addr_r = 7'h20;
6'h25: char_addr_r = 7'h20;
6'h26: char_addr_r = 7'h20;
6'h27: char_addr_r = 7'h20;
6'h28: char_addr_r = 7'h20;
6'h29: char_addr_r = 7'h20;
6'h2A: char_addr_r = 7'h20;
6'h2B: char_addr_r = 7'h20;
6'h2C: char_addr_r = 7'h20;
6'h2D: char_addr_r = 7'h20;
// visualization
// well
6'h2E: char_addr_r = 7'h20;
6'h2F: char_addr_r = 7'h20;
// row 4
6'h30: char_addr_r = 7'h70;
6'h31: char_addr_r = 7'h6c;
6'h32: char_addr_r = 7'h65;
6'h33: char_addr_r = 7'h61;
6'h34: char_addr_r = 7'h73;
6'h35: char_addr_r = 7'h65;
6'h36: char_addr_r = 7'h20;
6'h37: char_addr_r = 7'h63;
6'h38: char_addr_r = 7'h68;
6'h39: char_addr_r = 7'h65;
6'h3A: char_addr_r = 7'h63;
6'h3B: char_addr_r = 7'h6b;
6'h3C: char_addr_r = 7'h20;
6'h3D: char_addr_r = 7'h20;
// well, this is very annoying, try consola?
6'h3E: char_addr_r = 7'h20;
6'h3F: char_addr_r = 7'h20;
endcase
//-------------------------------------------
// game over region
// - display "Game Over" at center
// - scale to 32-by-64 fonts
//-----------------------------------------
//-------------------------------------------
// mux for font ROM addresses and rgb
//-------------------------------------------
// you can adjust color here
always @*
begin
check_rgb = 3'b110; // background, yellow
if (word_on)
begin
char_addr = char_addr_r;
row_addr = row_addr_r;
bit_addr = bit_addr_r;
if (font_bit)
check_rgb = 3'b001;
end
end
assign check_on = word_on;
//-------------------------------------------
// font rom interface (well)
//-------------------------------------------
// just concatenation
assign rom_addr = {char_addr, row_addr};
assign font_bit = font_word[~bit_addr];
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 03:32:37 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_gcd_0_1/gcd_block_design_gcd_0_1_stub.v
// Design : gcd_block_design_gcd_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "gcd,Vivado 2018.2" *)
module gcd_block_design_gcd_0_1(s_axi_gcd_bus_AWADDR,
s_axi_gcd_bus_AWVALID, s_axi_gcd_bus_AWREADY, s_axi_gcd_bus_WDATA, s_axi_gcd_bus_WSTRB,
s_axi_gcd_bus_WVALID, s_axi_gcd_bus_WREADY, s_axi_gcd_bus_BRESP, s_axi_gcd_bus_BVALID,
s_axi_gcd_bus_BREADY, s_axi_gcd_bus_ARADDR, s_axi_gcd_bus_ARVALID,
s_axi_gcd_bus_ARREADY, s_axi_gcd_bus_RDATA, s_axi_gcd_bus_RRESP, s_axi_gcd_bus_RVALID,
s_axi_gcd_bus_RREADY, ap_clk, ap_rst_n, interrupt)
/* synthesis syn_black_box black_box_pad_pin="s_axi_gcd_bus_AWADDR[5:0],s_axi_gcd_bus_AWVALID,s_axi_gcd_bus_AWREADY,s_axi_gcd_bus_WDATA[31:0],s_axi_gcd_bus_WSTRB[3:0],s_axi_gcd_bus_WVALID,s_axi_gcd_bus_WREADY,s_axi_gcd_bus_BRESP[1:0],s_axi_gcd_bus_BVALID,s_axi_gcd_bus_BREADY,s_axi_gcd_bus_ARADDR[5:0],s_axi_gcd_bus_ARVALID,s_axi_gcd_bus_ARREADY,s_axi_gcd_bus_RDATA[31:0],s_axi_gcd_bus_RRESP[1:0],s_axi_gcd_bus_RVALID,s_axi_gcd_bus_RREADY,ap_clk,ap_rst_n,interrupt" */;
input [5:0]s_axi_gcd_bus_AWADDR;
input s_axi_gcd_bus_AWVALID;
output s_axi_gcd_bus_AWREADY;
input [31:0]s_axi_gcd_bus_WDATA;
input [3:0]s_axi_gcd_bus_WSTRB;
input s_axi_gcd_bus_WVALID;
output s_axi_gcd_bus_WREADY;
output [1:0]s_axi_gcd_bus_BRESP;
output s_axi_gcd_bus_BVALID;
input s_axi_gcd_bus_BREADY;
input [5:0]s_axi_gcd_bus_ARADDR;
input s_axi_gcd_bus_ARVALID;
output s_axi_gcd_bus_ARREADY;
output [31:0]s_axi_gcd_bus_RDATA;
output [1:0]s_axi_gcd_bus_RRESP;
output s_axi_gcd_bus_RVALID;
input s_axi_gcd_bus_RREADY;
input ap_clk;
input ap_rst_n;
output interrupt;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_FUNCTIONAL_V
`define SKY130_FD_SC_LP__XNOR2_FUNCTIONAL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__xnor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire xnor0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y, A, B );
buf buf0 (Y , xnor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_FUNCTIONAL_V |
/******************************************************************************/
/* LCD Controller monotone-RK 2014.12.01 */
/******************************************************************************/
`default_nettype none
`include "define.v"
module LCDCON #(parameter DIGIT = 8)
(input wire CLK,
input wire RST,
input wire [DIGIT*4-1:0] DATA,
input wire WE,
output reg TXD,
output reg READY);
reg [(DIGIT+1)*10-1:0] cmd;
reg [11:0] waitnum;
reg [(DIGIT+3):0] cnt;
reg [DIGIT*4-1:0] D;
genvar i;
generate
wire [(DIGIT+1)*10-1:0] value;
for (i=0; i<(DIGIT+1); i=i+1) begin: val
if (i == DIGIT) begin
assign value[10*(i+1)-1:10*i] = {8'h20, 2'b01}; // add space
end else begin
wire [7:0] data = (D[4*(DIGIT-i)-1:4*(DIGIT-(i+1))]<10) ? 8'd48+D[4*(DIGIT-i)-1:4*(DIGIT-(i+1))] : // 0 ~ 9
8'd87+D[4*(DIGIT-i)-1:4*(DIGIT-(i+1))]; // a ~ f
assign value[10*(i+1)-1:10*i] = {data, 2'b01};
end
end
endgenerate
always @(posedge CLK) begin
if (RST) begin
TXD <= 1;
READY <= 1;
cmd <= {((DIGIT+1)*10){1'b1}};
waitnum <= 0;
cnt <= 0;
D <= 0;
end else begin
if (READY) begin
TXD <= 1;
waitnum <= 0;
if (WE) begin
READY <= 0;
D <= DATA;
cnt <= (DIGIT+1)*10+2;
end
end else if (cnt == (DIGIT+1)*10+2) begin
cnt <= cnt - 1;
cmd <= value;
end else if (waitnum >= `SERIAL_WCNT) begin
TXD <= cmd[0];
READY <= (cnt == 1);
cmd <= {1'b1, cmd[(DIGIT+1)*10-1:1]};
waitnum <= 1;
cnt <= cnt - 1;
end else begin
waitnum <= waitnum + 1;
end
end
end
endmodule
`default_nettype wire
|
#include <bits/stdc++.h> using namespace std; const int N = 10005; const int P = 998244353; struct edge { int u, v, len; inline edge() {} inline edge(int _u, int _v, int _len) { u = _u; v = _v; len = _len; } } a[N], Q[N], res[N]; struct node { int l, r; vector<int> E; node *lson, *rson; } pool[3 * N], *root; int n, m; int OscarDaGumert; int top = -1; int Index, cnt; bitset<N> cur; bitset<N> ans; void B_T(node *now, int l, int r) { now->l = l; now->r = r; if (l == r) return; int lr = (l + r) >> 1, rl = lr + 1; now->lson = &pool[++top]; B_T(now->lson, l, lr); now->rson = &pool[++top]; B_T(now->rson, rl, r); } void change(node *now, int l, int r, int id) { if (now->l == l && now->r == r) { now->E.push_back(a[id].len); return; } int lr = (now->l + now->r) >> 1, rl = lr + 1; if (r < rl) change(now->lson, l, r, id); else if (l > lr) change(now->rson, l, r, id); else { change(now->lson, l, lr, id); change(now->rson, rl, r, id); } } inline void query(node *now) { bitset<N> tmp = cur; int len = now->E.size(); for (int i = 0; i < len; i++) { cur |= (cur << now->E[i]); } ans |= cur; if (now->l != now->r) { query(now->lson); query(now->rson); } cur = tmp; } void init() { int x1, x2, x3; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d%d , &x1, &x2, &x3); a[i] = edge(x1, x2, x3); } root = &pool[++top]; B_T(root, 1, n); for (int i = 1; i <= m; i++) change(root, a[i].u, a[i].v, i); cur[0] = 1; query(root); int cnt = 0; for (int i = 1; i <= n; i++) { if (ans[i] == 1) { cnt++; } } printf( %d n , cnt); for (int i = 1; i <= n; i++) { if (ans[i] == 1) { printf( %d , i); } } } int main(int argc, char **argv) { init(); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<long long, int> > H[1000007]; long long n, val[1000005], ans, cnt[1000005]; int S[1000005]; int m, up[1000005], p[1000005], len, b[1000005], mp[1000005]; void prepare() { int i, j; b[1] = 1; for (i = 2; i < 1000005; i++) { if (!b[i]) p[++len] = i; for (j = 1; j <= len; j++) { if (1LL * i * p[j] >= 1000005) break; b[1LL * i * p[j]] = 1; if (i % p[j] == 0) break; } } for (i = 1; i < 1000005; i++) S[i] = S[i - 1] + (!b[i]); for (i = 1; i <= len; i++) mp[p[i]] = i; for (i = 1000005 - 1; i >= 1; i--) mp[i] = mp[i] ? mp[i] : mp[i + 1]; } int SQRT(long long n) { int p = (int)(sqrt(n)); while (1LL * p * p <= n) p++; return p; } long long find(long long x, int t) { int i, u = x % 1000007, p; for (i = 0; i < H[u].size(); i++) if (H[u][i].first == x) break; p = H[u][i].second; return t > up[p] ? cnt[p] + up[p] - t : cnt[p]; } long long Pi(int t) { return cnt[t] + up[t] - 1; } void update(int t) { long long i, x = val[t], l = n / (x + 1) + 1, r = n / x; r = min(r, (long long)(sqrt(n))); for (i = l; i <= r; i++) if (!b[i]) ans += Pi(t) - S[i]; } int main() { long long i, j = 1, q = 1; long long x = 0; cin >> n; prepare(), m = 1; for (i = 1; 1LL * p[i] * p[i] * p[i] <= n; i++) ans++; for (i = 1; i <= n; i = n / (val[m++]) + 1) val[m] = n / i; m--, sort(val + 1, val + m + 1); for (i = 1; i <= m; i++) H[val[i] % 1000007].push_back(pair<long long, int>(val[i], i)); for (i = 1; i <= m; i++) up[i] = mp[SQRT(val[i])]; for (i = 1; i <= up[m]; i++) { for (j = m; j >= q; j--) { if (i != 1) { x = find(val[j] / p[i - 1], i - 1); cnt[j] = cnt[j] - x - 1; } else cnt[j] = val[j] - 1; } while (q <= m && i == up[q]) update(q++); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int SET(int n, int pos) { return n = n | (1 << pos); } int RESET(int n, int pos) { return n = n & ~(1 << pos); } int CHECK(int n, int pos) { return (bool)(n & (1 << pos)); } int str2int(string s) { stringstream ss(s); int x; ss >> x; return x; } string int2str(int a) { stringstream ss; ss << a; string str = ss.str(); return str; } string char2str(char a) { stringstream ss; ss << a; string str = ss.str(); return str; } long long int bigMod(long long int n, long long int power, long long int MOD) { if (power == 0) return 1; if (power % 2 == 0) { long long int ret = bigMod(n, power / 2, MOD); return ((ret % MOD) * (ret % MOD)) % MOD; } else return ((n % MOD) * (bigMod(n, power - 1, MOD) % MOD)) % MOD; } long long int modInverse(long long int n, long long int MOD) { return bigMod(n, MOD - 2, MOD); } int POW(int x, int y) { int res = 1; for (; y;) { if ((y & 1)) { res *= x; } x *= x; y >>= 1; } return res; } int inverse(int x) { double p = ((double)1.0) / x; return (p) + 1e-9; } int gcd(int a, int b) { while (b) b ^= a ^= b ^= a %= b; return a; } int nC2(int n) { return n * (n - 1) / 2; } long long int MOD(long long int n, long long int mod) { if (n >= 0) return n % mod; else if (-n == mod) return 0; else return mod + (n % mod); } int n, data[105], Mask[65], dp[105][(1 << 18) + 1], path[105][(1 << 18) + 1]; bool isPrime[65]; vector<int> prime; void seive_N_logN(int N) { memset(isPrime, true, sizeof isPrime); prime.clear(); isPrime[1] = false; for (int i = 4; i <= N; i = i + 2) isPrime[i] = false; for (int i = 3; i * i <= N; i = i + 2) { if (isPrime[i]) { for (int j = i * i; j <= N; j += i) isPrime[j] = false; } } for (int i = 1; i < N; i++) if (isPrime[i]) prime.push_back(i); for (int i = 1; i <= 60; i++) { for (int j = 0; j < prime.size(); j++) { if (i % prime[j] == 0) Mask[i] = SET(Mask[i], j); } } } int call(int i, int mask) { if (i >= n) { return 0; } int &ret = dp[i][mask]; if (ret != -1) return ret; ret = 1000000000; for (int j = 1; j <= 60; j++) { if (mask & Mask[j]) continue; int xx = call(i + 1, mask | Mask[j]) + abs(data[i] - j); if (xx < ret) { ret = xx; path[i][mask] = j; } } return ret; } int main() { seive_N_logN(60); int t, cas = 0; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &data[i]); } memset(dp, -1, sizeof(dp)); call(0, 0); int mask = 0; for (int i = 0; i < n; i++) { int ans = path[i][mask]; printf( %d , ans); mask |= Mask[ans]; } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, maxim, a; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a; if (a > maxim) maxim = a; } cout << (maxim ^ a); return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_2_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_2_e.v,v 1.3 2006/06/26 08:39:42 wig Exp $
// $Date: 2006/06/26 08:39:42 $
// $Log: inst_2_e.v,v $
// Revision 1.3 2006/06/26 08:39:42 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_2_e
//
// No `defines in this module
module inst_2_e
//
// Generated Module inst_2
//
(
);
// Module parameters:
parameter FOO = 10;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_2_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND3_2_V
`define SKY130_FD_SC_HS__AND3_2_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND3_2_V
|
#include <bits/stdc++.h> using namespace std; using i64 = long long; using f64 = double; using f80 = long double; using pii = pair<int, int>; using pll = pair<i64, i64>; using ptx = pair<f64, f64>; const int N = 3e5 + 5, LG = 20; int f[N], conv[N], tmp[N]; int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); int n; cin >> n; for (int t, i = 1; i <= n; ++i) { cin >> t; f[t] = conv[t] = 1; if (t == 1) { cout << 1 n ; return 0; } } for (int tid = 2; tid <= 7; ++tid) { i64 drop, st, dr; for (int i = N - 1; i >= 1; --i) { drop = st = dr = 0; for (int j = i; j < N; j += i) { drop += tmp[j]; st += conv[j]; dr += f[j]; } tmp[i] = st * dr - drop; } if (tmp[1]) { cout << tid << endl; return 0; } for (int i = 0; i < N; ++i) { conv[i] = int(tmp[i] > 0); tmp[i] = 0; } } cout << -1 n ; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:31:50 03/07/2016
// Design Name: mult4
// Module Name: C:/XilinxP/Practica1/mult4_test.v
// Project Name: Practica1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mult4
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
// Test para Multiplicador de 4 bits, Practica 1
module mult4_test;
// Inputs
reg x0;
reg x1;
reg x2;
reg x3;
reg y0;
reg y1;
reg y2;
reg y3;
// Outputs
wire z0;
wire z1;
wire z2;
wire z3;
wire z4;
wire z5;
wire z6;
wire z7;
// Instantiate the Unit Under Test (UUT)
mult4 uut (
.x0(x0),
.x1(x1),
.x2(x2),
.x3(x3),
.y0(y0),
.y1(y1),
.y2(y2),
.y3(y3),
.z0(z0),
.z1(z1),
.z2(z2),
.z3(z3),
.z4(z4),
.z5(z5),
.z6(z6),
.z7(z7)
);
initial begin
// Initialize Inputs
x0 = 0;
x1 = 0;
x2 = 0;
x3 = 0;
y0 = 0;
y1 = 0;
y2 = 0;
y3 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
x0 = 1; x1 = 1; x2 = 0; x3 = 1; y0 = 1; y1 = 0; y2 = 1; y3 = 0; //1011 * 0101
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; y0 = 1; y1 = 0; y2 = 1; y3 = 1; //1010 * 1101
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; y0 = 0; y1 = 1; y2 = 1; y3 = 1; //1111 * 1110
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; y0 = 1; y1 = 1; y2 = 1; y3 = 1; //1111 * 1111
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 0; x2 = 0; x3 = 1; y0 = 0; y1 = 0; y2 = 1; y3 = 0; //1000 * 0100
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 1; x2 = 0; x3 = 1; y0 = 1; y1 = 0; y2 = 0; y3 = 0; //1010 * 0001
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 1; x1 = 1; x2 = 1; x3 = 1; y0 = 0; y1 = 0; y2 = 0; y3 = 0; //1111 * 0000
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
x0 = 0; x1 = 1; x2 = 1; x3 = 0; y0 = 1; y1 = 0; y2 = 0; y3 = 1; //0110 * 1001
#50;
$display("x = %b%b%b%b, y = %b%b%b%b, z = %b%b%b%b%b%b%b%b", x3, x2, x1, x0, y3, y2, y1, y0, z7, z6, z5, z4, z3, z2, z1, z0);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node; typedef node *Node; const int inf = 1000000; bool fl = 0; struct node { Node left, right, link, parent; int size, prior, sum, number; set<int> all; pair<int, int> mmin; node(int number) : number(number) { left = right = link = parent = NULL; prior = rand() + (rand() << 16); update(); } int key() { int ans = 1; if (left) ans += left->size; return ans; } void update() { size = 1; sum = all.size(); if (sum == 0) mmin = make_pair(inf, inf); else mmin = make_pair(*all.begin(), number); if (left) { size += left->size; sum += left->sum; mmin = min(mmin, left->mmin); left->parent = this; } if (right) { size += right->size; sum += right->sum; mmin = min(mmin, right->mmin); right->parent = this; } } }; void upd_min(Node t) { while (t) { t->update(); t = t->parent; } } void add_ppl(Node &t, int ppl) { t->all.insert(ppl); t->sum++; upd_min(t); } void del_ppl(Node &t, int ppl) { t->all.erase(ppl); t->sum--; upd_min(t); } Node merge(Node l, Node r) { if (!l) return r; if (!r) return l; if (l->prior > r->prior) { l->right = merge(l->right, r); l->update(); return l; } else { r->left = merge(l, r->left); r->update(); return r; } } void split(Node t, int key, Node &l, Node &r) { if (!t) return void(l = r = NULL); if (t->key() <= key) { split(t->right, key - t->key(), t->right, r); l = t; } else { split(t->left, key, l, t->left); r = t; } t->update(); t->parent = NULL; } int get_pos(Node t) { vector<char> vc; Node v = t; while (v->parent) { if (v->parent->left == v) vc.push_back(0); else vc.push_back(1); v = v->parent; } reverse(vc.begin(), vc.end()); int pos = 0; for (int i = 0; i < vc.size(); ++i) { if (vc[i] == 0) v = v->left; else pos += v->key(), v = v->right; } pos += v->key(); return pos; } Node get_root(Node t) { Node ans = NULL; while (t) { ans = t; t = t->parent; } return ans; } Node leftmost(Node t) { Node ans = NULL; while (t) { ans = t; t = t->left; } return ans; } Node rightmost(Node t) { Node ans = NULL; while (t) { ans = t; t = t->right; } return ans; } void set_link(Node t, Node v) { if (!t) return; t->link = v; } void cut_out(Node t) { int pos = get_pos(t); Node l, r; split(get_root(t), pos, l, r); set_link(leftmost(r), t); } void cut_out1(Node t) { int pos = get_pos(t); Node l, r; split(get_root(t), pos - 1, l, r); set_link(leftmost(r), rightmost(l)); } void expose(Node v) { cut_out(v); v = leftmost(get_root(v)); while (v->link) { cut_out(v->link); merge(get_root(v->link), get_root(v)); set_link(v, NULL); v = leftmost(get_root(v)); } } void link(Node u, Node v) { set_link(u, v); expose(u); } void cut(Node u, Node v) { expose(v); set_link(u, NULL); } Node lca(Node v, Node u, bool &one_tree) { expose(u); if (get_root(u) == get_root(v)) { one_tree = 1; return v; } expose(v); expose(u); return leftmost(get_root(v))->link; } vector<Node> nodes; const int maxn = 100000; vector<pair<int, int> > add; vector<int> g[maxn + 1]; vector<int> deep; void dfs(int v, int p = -1) { for (int i = 0; i < g[v].size(); ++i) { int tv = g[v][i]; if (tv == p) continue; deep[tv] = deep[v] + 1; dfs(tv, v); } } void print_(Node v) { if (!v) return; print_(v->left); cout << t << v->number << << (v->link ? v->link->number : -1) << endl; print_(v->right); } void print(Node v) { print_(get_root(v)); } void print_all(int n) { for (int i = 1; i <= n; ++i) { cout << i << : n ; print(nodes[i]); cout << endl; } } void do_the_thing(Node v, int x) { Node t = get_root(v); int k = min(x, t->sum); cout << k << ; vector<pair<int, int> > add_after; for (int i = 0; i < k; ++i) { pair<int, int> cmin = t->mmin; cout << cmin.first << ; del_ppl(nodes[cmin.second], cmin.first); add_after.push_back(cmin); } cout << endl; for (int i = 0; i < add_after.size(); ++i) { pair<int, int> ct = add_after[i]; add_ppl(nodes[ct.second], ct.first); } } int main() { srand(time(NULL)); ios_base::sync_with_stdio(0); int n, m, q; cin >> n >> m >> q; nodes.resize(n + 1); deep.assign(n + 1, 0); for (int i = 1; i <= n; ++i) nodes[i] = new node(i); for (int i = 0; i < n - 1; ++i) { int a, b; cin >> a >> b; add.push_back(make_pair(a, b)); g[a].push_back(b); g[b].push_back(a); } dfs(1); for (int i = 0; i < add.size(); ++i) { int a = add[i].first; int b = add[i].second; if (deep[a] < deep[b]) swap(a, b); link(nodes[a], nodes[b]); } for (int i = 1; i <= m; ++i) { int city; cin >> city; add_ppl(nodes[city], i); } for (int i = 0; i < q; ++i) { int v, u, x; cin >> v >> u >> x; bool one_tree = 0; Node t = lca(nodes[v], nodes[u], one_tree); if (one_tree) { cut_out1(nodes[v]); do_the_thing(nodes[v], x); } else { int split_key = get_root(nodes[v])->size; cut_out1(t); merge(get_root(nodes[v]), get_root(t)); do_the_thing(nodes[v], x); Node l, r; split(get_root(nodes[v]), split_key, l, r); } } return 0; } |
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