text stringlengths 59 71.4k |
|---|
`include ""
module mux_4x1(
input [1:0] sel,
input [2*`DATA_LEN-1:0] dat0,
input [2*`DATA_LEN-1:0] dat1,
input [2*`DATA_LEN-1:0] dat2,
input [2*`DATA_LEN-1:0] dat3,
output reg [2*`DATA_LEN-1:0] out
);
always @(*) begin
case(sel)
0: begin
out = dat0;
end
1: begin
out = dat1;
end
2: begin
out = dat2;
end
3: begin
out = dat3;
end
endcase
end
endmodule // mux_4x1
// sel_lohi = md_req_out_sel[0]
module multiplier(
input signed [`DATA_LEN-1:0] src1,
input signed [`DATA_LEN-1:0] src2,
input src1_signed,
input src2_signed,
input sel_lohi,
output wire [`DATA_LEN-1:0] result
);
/*
wire src1_neg = src1[`DATA_LEN-1] & src1_signed;
wire src2_neg = src2[`DATA_LEN-1] & src2_signed;
wire [`DATA_LEN-1:0] a = src1_neg ? -src1 : src1;
wire [`DATA_LEN-1:0] b = src2_neg ? -src2 : src2;
wire [2*`DATA_LEN-1:0] c = a * b;
wire [2*`DATA_LEN-1:0] c_signed = (src1_neg ^ src2_neg) ? c : -c;
*/
wire signed [`DATA_LEN:0] src1_unsign = {1'b0, src1};
wire signed [`DATA_LEN:0] src2_unsign = {1'b0, src2};
wire signed [2*`DATA_LEN-1:0] res_ss = src1 * src2;
wire signed [2*`DATA_LEN-1:0] res_su = src1 * src2_unsign;
wire signed [2*`DATA_LEN-1:0] res_us = src1_unsign * src2;
wire signed [2*`DATA_LEN-1:0] res_uu = src1_unsign * src2_unsign;
wire [2*`DATA_LEN-1:0] res;
mux_4x1 mxres(
.sel({src1_signed, src2_signed}),
.dat0(res_uu),
.dat1(res_us),
.dat2(res_su),
.dat3(res_ss),
.out(res)
);
assign result = sel_lohi ? res[`DATA_LEN+:`DATA_LEN] : res[`DATA_LEN-1:0];
endmodule // multiplier
|
#include <bits/stdc++.h> using namespace std; int arr[111]; int main() { int n; scanf( %d , &n); arr[0] = 0; for (int i = (1); i < (n + 1); ++i) scanf( %d , &arr[i]); int ans = 0; if (n % 2 == 0 || n == 1) { printf( -1 n ); return 0; } for (int i = n; i >= 1; i -= 2) { int tmp = max(arr[i], arr[i - 1]); ans += tmp; arr[i] = arr[i - 1] = 0; arr[(i - 1) / 2] = max(0, arr[(i - 1) / 2] - tmp); } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int n; void even() { puts( YES ); printf( %d * %d = %d n , 1, 2, 2); printf( %d * %d = %d n , 2, 3, 6); printf( %d * %d = %d n , 6, 4, 24); for (int i = 5; i + 1 <= n; i += 2) { printf( %d - %d = 1 n , i + 1, i); printf( 1 * 24 = 24 n ); } } void odd() { puts( YES ); printf( 5 - 1 = 4 n ); printf( 4 - 2 = 2 n ); printf( 4 * 2 = 8 n ); printf( 8 * 3 = 24 n ); for (int i = 6; i + 1 <= n; i += 2) { printf( %d - %d = 1 n , i + 1, i); printf( 1 * 24 = 24 n ); } } int main() { cin >> n; if (n < 4) { puts( NO ); return 0; } if (n % 2 == 0) even(); else odd(); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, a[100005], mi, mid, ma; long long m, sum; bool b[100005], flag; bool check() { long long sum = 0; for (int i = 0; i < n; i++) sum += min(a[i], mid); return sum <= m; } int main() { cin >> n >> m; sum = 0; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); sum += a[i]; } if (sum < m) { printf( -1 n ); } else if (sum == m) { printf( n ); } else { mi = 0; ma = 1000000000; while (mi < ma) { mid = (mi + ma + 1) >> 1; if (check()) mi = mid; else ma = mid - 1; } for (int i = 0; i < n; i++) { m -= min(a[i], mi); a[i] -= min(a[i], mi); } memset(b, true, sizeof(b)); flag = false; for (int i = 0; b[i]; i = (i + 1) % n) { if (a[i]) { if (m) { a[i]--; m--; } else { if (flag) printf( ); flag = true; b[i] = false; printf( %d , i + 1); } } } printf( n ); } return 0; } |
/****************************************** By Lord Sanskar Bhargava******************************/ #include<bits/stdc++.h> using namespace std; typedef long long ll; typedef long double ld; typedef complex<ld> cd; typedef pair<int, int> pi; typedef pair<ll,ll> pl; typedef pair<ld,ld> pd; typedef vector<int> vi; typedef vector<ld> vd; typedef vector<ll> vl; typedef vector<pi> vpi; typedef vector<pl> vpl; typedef vector<cd> vcd; int main() { ios::sync_with_stdio(0);cin.tie(0); int tt; cin>>tt; while(tt--) { ll n;cin>>n; ll k=n%2020; if(n<2020) { cout<< NO <<endl; } else if(k*2021<=n) { cout<< YES <<endl; } else { cout<< NO <<endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; bool PIIfs(const pair<int, int>& a, const pair<int, int>& b) { return a.first < b.first || (a.first == b.first && a.second < b.second); } bool PIIsf(const pair<int, int>& a, const pair<int, int>& b) { return a.second < b.second || (a.second == b.second && a.first < b.first); } bool PIIFS(const pair<int, int>& a, const pair<int, int>& b) { return a.first > b.first || (a.first == b.first && a.second > b.second); } bool PIISF(const pair<int, int>& a, const pair<int, int>& b) { return a.second > b.second || (a.second == b.second && a.first > b.first); } bool PIIfS(const pair<int, int>& a, const pair<int, int>& b) { return a.first < b.first || (a.first == b.first && a.second > b.second); } bool PIIsF(const pair<int, int>& a, const pair<int, int>& b) { return a.second < b.second || (a.second == b.second && a.first > b.first); } bool PIIFs(const pair<int, int>& a, const pair<int, int>& b) { return a.first > b.first || (a.first == b.first && a.second < b.second); } bool PIISf(const pair<int, int>& a, const pair<int, int>& b) { return a.second > b.second || (a.second == b.second && a.first < b.first); } template <typename T> inline T max(T a, T b, T c) { return max(max(a, b), c); } template <typename T> inline T max(T a, T b, T c, T d) { return max(max(a, b, c), d); } template <typename T> inline T max(T a, T b, T c, T d, T e) { return max(max(a, b, c, d), e); } template <typename T> inline T min(T a, T b, T c) { return min(min(a, b), c); } template <typename T> inline T min(T a, T b, T c, T d) { return min(min(a, b, c), d); } template <typename T> inline T min(T a, T b, T c, T d, T e) { return min(min(a, b, c, d), e); } template <typename T> inline istream& RD(T& x) { return cin >> x; } template <typename T, typename U> inline istream& RD(T& a, U& b) { return cin >> a >> b; } template <typename T, typename U, typename V> inline istream& RD(T& a, U& b, V& c) { return cin >> a >> b >> c; } template <typename T, typename U, typename V, typename W> inline istream& RD(T& a, U& b, V& c, W& d) { return cin >> a >> b >> c >> d; } template <typename T, typename U, typename V, typename W, typename X> inline istream& RD(T& a, U& b, V& c, W& d, X& e) { return cin >> a >> b >> c >> d >> e; } template <typename T> void checkmin(T& a, const T& b) { if (b < a) a = b; } template <typename T> void checkmax(T& a, const T& b) { if (b > a) a = b; } int n; void dfs(const vector<string>& vs, bitset<300>& mark, int node, vector<int>& ans) { if (mark.test(node)) return; mark.set(node); ans.push_back(node); for (int i = 0; i < n; i++) if (vs[node][i] == 1 ) dfs(vs, mark, i, ans); } void perm(vector<int>& vi, vector<int>& si) { int x = si.size(); vector<int> tmp(x); for (int i = 0; i < (int)(x); ++i) tmp[i] = vi[si[i]]; sort(tmp.begin(), tmp.end()); sort(si.begin(), si.end()); for (int i = 0; i < (int)(x); ++i) vi[si[i]] = tmp[i]; } int main() { std::ios::sync_with_stdio(false); cin >> n; vector<int> vi(n); for (int i = 0; i < (int)(n); ++i) cin >> vi[i]; vector<string> vs; string s; for (int i = 0; i < (int)(n); ++i) { cin >> s; vs.push_back(s); } vector<set<int> > circles; bitset<300> found; for (int i = 0; i < n; i++) { vector<int> ans; dfs(vs, found, i, ans); if (ans.size() > 1) { perm(vi, ans); } } for (__typeof__(vi.begin()) it = vi.begin(); it != vi.end(); ++it) cout << *it << ; cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1000000000; long long mod = 1000000007LL; long long mod2 = 998244353LL; int n; int t, q; long long a[100005], b[100005]; long long pre[100005]; struct node { int l, r; long long mx, mn; } tree[100005 << 2]; void build(int id, int l, int r) { tree[id].l = l; tree[id].r = r; if (l == r) { tree[id].mx = pre[l]; tree[id].mn = pre[l]; return; } int mid = (l + r) / 2; build(id * 2, l, mid); build(id * 2 + 1, mid + 1, r); tree[id].mx = max(tree[id * 2].mx, tree[id * 2 + 1].mx); tree[id].mn = min(tree[id * 2].mn, tree[id * 2 + 1].mn); } long long query(int id, int l, int r, bool mx) { if (tree[id].l == l && tree[id].r == r) { return (mx ? tree[id].mx : tree[id].mn); } int mid = (tree[id].l + tree[id].r) / 2; if (r <= mid) return query(id * 2, l, r, mx); else if (l > mid) return query(id * 2 + 1, l, r, mx); else { long long r1 = query(id * 2, l, mid, mx); long long r2 = query(id * 2 + 1, mid + 1, r, mx); return (mx ? max(r1, r2) : min(r1, r2)); } } int main() { cin >> n >> q; for (int i = 1; i <= n; ++i) { scanf( %lld , &a[i]); } for (int i = 1; i <= n; ++i) { scanf( %lld , &b[i]); } pre[0] = 0LL; for (int i = 1; i <= n; ++i) { pre[i] = pre[i - 1] + b[i] - a[i]; } build(1, 1, n); while (q-- > 0) { int l, r; scanf( %d%d , &l, &r); if (pre[r] - pre[l - 1] != 0 || query(1, l, r, false) < pre[l - 1]) { puts( -1 ); } else { printf( %lld n , query(1, l, r, true) - pre[l - 1]); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4_PP_SYMBOL_V
`define SKY130_FD_SC_LS__AND4_PP_SYMBOL_V
/**
* and4: 4-input AND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } double p[200010]; int n, cnt; double ans; inline void solve(int a, int b) { ans += (double)(a - b) / 2; p[++cnt] = (double)(a + b) / 2; } int main() { n = read(); for (int i = 1; i <= n; i++) { long long a = read(), b = read(), c = read(), d = read(); if (a + b >= c + d) { solve(a, b); solve(c, d); } else { if (a >= d) solve(a - d, d - a); if (b >= c) solve(c - b, b - c); } } sort(p + 1, p + cnt + 1, greater<double>()); for (int i = 1; i <= cnt; i++) { if (i & 1) ans += p[i]; else ans -= p[i]; } printf( %.0f n , ans); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD2_TB_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD2_TB_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkdlyinv3sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__clkdlyinv3sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD2_TB_V
|
#include <bits/stdc++.h> using namespace std; int arr[1000000]; int main() { int n; while (scanf( %d , &n) != -1) { if (n == 1) { printf( 1 n ); continue; } if ((n & 1) && (n - 1) % 4) { printf( -1 n ); continue; } if (!(n & 1) && n % 4) { printf( -1 n ); continue; } for (int i = 1; i + i <= n; i += 2) arr[i] = i + 1, arr[i + 1] = n - i + 1, arr[n - i + 1] = n - i, arr[n - i] = i; if (n % 2) arr[n / 2 + 1] = n / 2 + 1; for (int i = 1; i <= n; ++i) printf(i > 1 ? %d : %d , arr[i]); printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int dp[2005][2005][2][2]; int m, d, mod = 1e9 + 7; string a, b; int solve(int i, int mm, bool aa, bool bb) { if (i == a.size()) return !mm; int &x = dp[i][mm][aa][bb]; if (x != -1) return x; x = 0; for (int j = 0; j <= 9; j++) { if (i % 2 && j != d || !(i % 2) && j == d) continue; if (!aa && a[i] - 0 > j || !bb && b[i] - 0 < j) continue; bool na = aa | a[i] - 0 < j, nb = bb | b[i] - 0 > j; x = (x + solve(i + 1, (mm * 10 + j) % m, na, nb)) % mod; } return x; } int main() { cin >> m >> d >> a >> b; memset(dp, -1, sizeof dp); cout << solve(0, 0, 0, 0); } |
#include <bits/stdc++.h> using namespace std; const char nl = n ; const int mod = 1000000007; const double pi = 4 * atan(1); const int inf = 2000000000; const long long linf = (long long)1e18; const int pr = 37; const int maxn = 1000001; const int maxn_big = 1000001; string s; vector<int> v; unsigned long long h[maxn], p[maxn]; unsigned long long get_hash(int l, int r) { int len = (r - l) + 1; if (!l) return h[r]; return h[r] - h[l - 1] * p[len]; } bool check(int pf) { unsigned long long pref_hash = get_hash(0, pf); bool has_ans = 0; for (int i = 1; i < ((int)(s.size())) - 1; ++i) { int r = i + pf; if (r >= ((int)(s.size())) - 1) break; if (get_hash(i, r) == pref_hash) { has_ans = 1; break; } } return has_ans; } int main() { ios_base ::sync_with_stdio(0); cin.tie(0); srand(time(NULL)); cin >> s; h[0] = s[0]; p[0] = 1; for (int i = 1; i < ((int)(s.size())); ++i) { h[i] = h[i - 1] * pr + s[i]; p[i] = p[i - 1] * pr; } for (int i = 0; i < ((int)(s.size())); ++i) { int l = ((int)(s.size())) - 1 - i; if (get_hash(0, i) == get_hash(l, ((int)(s.size())) - 1)) v.push_back(i); } if (!((int)(v.size()))) { cout << Just a legend ; return 0; } int l = -1, r = ((int)(v.size())); bool has = 0; while (r - l > 1) { int mid = (r + l) / 2; if (check(v[mid])) { l = mid; has = 1; } else { r = mid; } } if (!has) { cout << Just a legend ; return 0; } string res = ; for (int i = 0; i <= v[l]; ++i) res += s[i]; cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, k; int a[200007]; long long fac[200007]; long long inv[200007]; long long pw2[200007]; long long free_pw[200007]; long long fastpow(long long x, long long st) { long long ret = 1; while (st > 0) { if ((st & 1) != 0) { ret = (ret * x) % 998244353; --st; } else { x = (x * x) % 998244353; st >>= 1; } } return ret; } long long get_comb(long long x, long long y) { if (x < y) { return 0; } long long ret = fac[x]; ret = (ret * inv[y]) % 998244353; ret = (ret * inv[x - y]) % 998244353; return ret; } void input() { scanf( %I64d%I64d , &n, &k); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); } a[n + 1] = a[1]; fac[0] = pw2[0] = free_pw[0] = 1; for (int i = 1; i <= n; ++i) { fac[i] = (fac[i - 1] * i) % 998244353; pw2[i] = (pw2[i - 1] * 2) % 998244353; free_pw[i] = (free_pw[i - 1] * (k - 2)) % 998244353; } inv[n] = fastpow(fac[n], 998244353 - 2); for (int i = n - 1; i >= 0; --i) { inv[i] = (inv[i + 1] * (i + 1)) % 998244353; } } void solve() { int free = 0; long long aux = 1; for (int i = 1; i <= n; ++i) { if (a[i] == a[i + 1]) { ++free, aux = (aux * k) % 998244353; } } long long ans = 0; for (int i = 0; i < n - free; ++i) { long long w = (get_comb(n - free, i) * free_pw[i]) % 998244353; int lft = n - free - i; long long coef = pw2[lft]; if ((lft & 1) == 0) { coef = (coef - get_comb(lft, lft / 2) + 998244353) % 998244353; } coef = (coef * inv[2]) % 998244353; ans = (ans + (w * coef) % 998244353) % 998244353; } printf( %I64d n , (aux * ans) % 998244353); } int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); input(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); using namespace std; int main() { int q; long long int a, b, c; long long int ans = 0; cin >> q; while (q--) { cin >> a >> b >> c; ans = (a + b + c) / 2; cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int luck_number[105], tot; int dp[10005][7]; bool is_luck(int x) { while (x) { int y = x % 10; x = x / 10; if (y > 0 && y < 4) return false; if (y > 4 && y < 7) return false; if (y > 7) return false; } return true; } void init() { tot = 0; for (int i = 0; i <= 10000; i++) { if (is_luck(i)) luck_number[tot++] = i; } } void pre10000() { for (int i = 0; i <= 10000; i++) for (int j = 0; j <= 6; j++) dp[i][j] = -1; for (int i = 0; i <= 6; i++) { dp[0][i] = 0; } for (int i = 1; i <= 6; i++) { for (int j = 0; j < tot; j++) { int x = luck_number[j]; for (int k = x; k <= 10000; k++) { if (dp[k - x][i - 1] != -1) { dp[k][i] = x; } } } } } int main() { init(); pre10000(); int cas; scanf( %d , &cas); while (cas--) { long long N; cin >> N; if (N < 10000LL) { int n = (int)(N); if (dp[n][6] != -1) { for (int i = 6; i > 0; i--) { printf( %d , dp[n][i]); n -= dp[n][i]; } puts( ); } else printf( -1 n ); } else { int n1 = (int)(N % 4000LL); if (dp[n1][6] == -1) n1 += 4000, N -= 4000; long long res[7]; for (int i = 6; i > 0; i--) { res[i] = (long long)(dp[n1][i]); n1 -= dp[n1][i]; } long long n2 = N - n1; long long p = n2 / 4000LL, base = 1000LL; while (p) { int d = (int)(p % 10LL); if (d <= 6) { for (int i = 1; i <= d; i++) { res[i] += base * 4; } } else { for (int i = 1; i <= d - 7; i++) { res[i] += base * 4; } for (int i = 6; i >= 3; i--) { res[i] += base * 7; } } base *= 10LL; p /= 10LL; } for (int i = 1; i <= 6; i++) cout << res[i] << ; puts( ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 32768 - 1; int ans[100500]; bool use[100500]; int res; string s = ; int eval_num(int n, int &i); int eval_product(int n, int &i); int eval_sum(int n, int &i); bool eval_logick(int n, int &i); int eval_op(int n, int &i); int eval_opseq(int n, int &i); int eval_func(int n, int &i); int run(int n); const string dels = n ; const string ops = (){}+-*/;<> ; bool has(string t, char c) { for (int i = 0; i < t.length(); ++i) if (t[i] == c) return true; return false; } string getlex(int &i) { string t = ; while (has(dels, s[i])) ++i; if (has(ops, s[i])) { t += s[i++]; return t; } if (s[i] == = && s[i + 1] == = ) { t += == ; i += 2; return t; } while (!((has(dels, s[i]) || has(ops, s[i]) || s[i] == = ))) t += s[i++]; return t; } int norm(int x) { while (x < 0) x += MAXN + 1; return x % (MAXN + 1); } int eval_num(int n, int &i) { string sw = getlex(i); if (sw == n ) return n; if (sw == f ) { getlex(i); int t = eval_sum(n, i); getlex(i); return run(t); } return atoi(sw.c_str()); } int eval_product(int n, int &i) { int sum = eval_num(n, i); int j = i; string op = getlex(j); while (op == * || op == / ) { int t = eval_num(n, j); i = j; if (op == * ) sum *= t; else sum /= t; sum = norm(sum); op = getlex(j); } return sum; } int eval_sum(int n, int &i) { int sum = eval_product(n, i); int j = i; string op = getlex(j); while (op == + || op == - ) { int t = eval_product(n, j); i = j; if (op == + ) sum += t; else sum -= t; sum = norm(sum); op = getlex(j); } return sum; } bool eval_logick(int n, int &i) { int e1 = eval_sum(n, i); string op = getlex(i); int e2 = eval_sum(n, i); if (op == > ) return (e1 > e2); if (op == < ) return (e1 < e2); if (op == == ) return (e1 == e2); exit(0); return false; } int eval_op(int n, int &i) { string sw = getlex(i); if (sw == if ) { string t = getlex(i); if (t != ( ) exit(0); bool b = eval_logick(n, i); t = getlex(i); if (b) { getlex(i); } else { while (s[i] != ; ) ++i; ++i; return -1; } } int ret = eval_sum(n, i); getlex(i); return ret; } int eval_func(int n, int &i) { while (s[i] != { ) ++i; ++i; int ret = -1; while (ret < 0) { ret = eval_op(n, i); } return ret; } int run(int n) { int j = 0; if (use[n]) return ans[n]; use[n] = true; ans[n] = eval_func(n, j); return ans[n]; } int main() { cin >> res; string t; while (!feof(stdin)) { getline(cin, t); s += t + ; } s += ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; for (int i = 0; i <= MAXN; ++i) run(i); int mx = -1; for (int i = 0; i <= MAXN; ++i) if (ans[i] == res) mx = i; cout << mx; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_BLACKBOX_V
/**
* dlybuf4s25kapwr: Delay Buffer 4-stage 0.25um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s25kapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S25KAPWR_PP_BLACKBOX_V
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/simprims/LUT3.v,v 1.5 2005/03/14 21:05:15 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 8.1i (I.13)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 3-input Look-Up-Table with General Output
// /___/ /\ Filename : LUT3.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:56 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module LUT3 (O, I0, I1, I2);
parameter INIT = 8'h00;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1, I2;
wire out0, out1, a0, a1, a2;
buf b0 (a0, I0);
buf b1 (a1, I1);
buf b2 (a2, I2);
x_lut3_mux4 (out1, INIT[7], INIT[6], INIT[5], INIT[4], a1, a0);
x_lut3_mux4 (out0, INIT[3], INIT[2], INIT[1], INIT[0], a1, a0);
x_lut3_mux4 (O, 1'b0, 1'b0, out1, out0, 1'b0, a2);
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(I2 => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
primitive x_lut3_mux4 (o, d3, d2, d1, d0, s1, s0);
output o;
input d3, d2, d1, d0;
input s1, s0;
table
// d3 d2 d1 d0 s1 s0 : o;
? ? ? 1 0 0 : 1;
? ? ? 0 0 0 : 0;
? ? 1 ? 0 1 : 1;
? ? 0 ? 0 1 : 0;
? 1 ? ? 1 0 : 1;
? 0 ? ? 1 0 : 0;
1 ? ? ? 1 1 : 1;
0 ? ? ? 1 1 : 0;
? ? 0 0 0 x : 0;
? ? 1 1 0 x : 1;
0 0 ? ? 1 x : 0;
1 1 ? ? 1 x : 1;
? 0 ? 0 x 0 : 0;
? 1 ? 1 x 0 : 1;
0 ? 0 ? x 1 : 0;
1 ? 1 ? x 1 : 1;
0 0 0 0 x x : 0;
1 1 1 1 x x : 1;
endtable
endprimitive
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The top level of clint module
//
// ====================================================================
module sirv_clint_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_tiles_0_mtip,
output io_tiles_0_msip,
input io_rtcToggle
);
wire io_rtcToggle_r;
sirv_gnrl_dffr #(1) io_rtcToggle_dffr (io_rtcToggle, io_rtcToggle_r, clk, rst_n);
wire io_rtcToggle_edge = io_rtcToggle ^ io_rtcToggle_r;
wire io_rtcTick = io_rtcToggle_edge;
wire io_in_0_a_ready;
assign i_icb_cmd_ready = io_in_0_a_ready;
wire io_in_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_in_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_in_0_a_bits_param = 3'b0;
wire [2:0] io_in_0_a_bits_size = 3'd2;
wire [4:0] io_in_0_a_bits_source = 5'b0;
wire [25:0] io_in_0_a_bits_address = i_icb_cmd_addr[25:0];
wire [3:0] io_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_in_0_a_bits_data = i_icb_cmd_wdata;
wire io_in_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_in_0_d_bits_opcode;
wire [1:0] io_in_0_d_bits_param;
wire [2:0] io_in_0_d_bits_size;
wire [4:0] io_in_0_d_bits_source;
wire io_in_0_d_bits_sink;
wire [1:0] io_in_0_d_bits_addr_lo;
wire [31:0] io_in_0_d_bits_data;
wire io_in_0_d_bits_error;
wire io_in_0_d_valid;
assign i_icb_rsp_valid = io_in_0_d_valid;
assign i_icb_rsp_rdata = io_in_0_d_bits_data;
// Not used
wire io_in_0_b_ready = 1'b0;
wire io_in_0_b_valid;
wire [2:0] io_in_0_b_bits_opcode;
wire [1:0] io_in_0_b_bits_param;
wire [2:0] io_in_0_b_bits_size;
wire [4:0] io_in_0_b_bits_source;
wire [25:0] io_in_0_b_bits_address;
wire [3:0] io_in_0_b_bits_mask;
wire [31:0] io_in_0_b_bits_data;
// Not used
wire io_in_0_c_ready;
wire io_in_0_c_valid = 1'b0;
wire [2:0] io_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_in_0_c_bits_param = 3'b0;
wire [2:0] io_in_0_c_bits_size = 3'd2;
wire [4:0] io_in_0_c_bits_source = 5'b0;
wire [25:0] io_in_0_c_bits_address = 26'b0;
wire [31:0] io_in_0_c_bits_data = 32'b0;
wire io_in_0_c_bits_error = 1'b0;
// Not used
wire io_in_0_e_ready;
wire io_in_0_e_valid = 1'b0;
wire io_in_0_e_bits_sink = 1'b0;
sirv_clint u_sirv_clint(
.clock (clk ),
.reset (~rst_n ),
.io_in_0_a_ready (io_in_0_a_ready ),
.io_in_0_a_valid (io_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_in_0_a_bits_data ),
.io_in_0_b_ready (io_in_0_b_ready ),
.io_in_0_b_valid (io_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_in_0_b_bits_data ),
.io_in_0_c_ready (io_in_0_c_ready ),
.io_in_0_c_valid (io_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_in_0_c_bits_error ),
.io_in_0_d_ready (io_in_0_d_ready ),
.io_in_0_d_valid (io_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_in_0_d_bits_error ),
.io_in_0_e_ready (io_in_0_e_ready ),
.io_in_0_e_valid (io_in_0_e_valid ),
.io_in_0_e_bits_sink (io_in_0_e_bits_sink ),
.io_tiles_0_mtip (io_tiles_0_mtip),
.io_tiles_0_msip (io_tiles_0_msip),
.io_rtcTick (io_rtcTick )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4B_SYMBOL_V
`define SKY130_FD_SC_LS__NOR4B_SYMBOL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4B_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__EINVN_FUNCTIONAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVN_FUNCTIONAL_PP_V |
#ifdef LOCAL #include <prettyprint.hpp> #endif #include<bits/stdc++.h> #define endl n #define all(x) x.begin(), x.end() #define rall(x) x.rbegin(), x.rend() #define lg2(x) __lg(x) #define rem_dupl(x) sort(all(x)); x.erase(unique(all(x)), x.end()) using namespace std; typedef long long ll; typedef double db; typedef pair<int,int> ii; #define x first #define y second mt19937 rand32(chrono::steady_clock::now().time_since_epoch().count()); mt19937_64 rand64(chrono::steady_clock::now().time_since_epoch().count()); const db eps = 1e-9; const int maxn = (int)2e5 + 5; const ll mod = (int)1e9 + 7; // 998244353 int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.setf(ios::fixed); cout.precision(0); int n, m, p; cin >> n >> m >> p; vector<ll> a(n); for(auto &x:a){ x = 0; for(int i = 0; i < m; i++){ char j; cin >> j; if(j == 1 ) x |= (1ll<<i); } } ll ans = 0; for(int iter = 0; iter < 50; iter++){ ll s = a[rand32() % n]; vector<int> bits; for(int i = 0; i < m; i++) if(s & (1ll<<i)) bits.push_back(i); int p = bits.size(); vector<int>cnt(1<<p, 0), cnt2(1<<p, 0); for(auto &x:a){ int y = 0; for(int i = 0; i < p; i++){ if(x & (1ll<<bits[i])) y |= (1<<i); } cnt[y]++; } for(int mask = (1<<p) - 1; mask >= 0; mask--){ for(int s = mask; s; s = (s - 1) & mask){ cnt2[s] += cnt[mask]; } } for(int mask = 0; mask < (1<<p); mask++){ if(2*cnt2[mask] >= n){ if(__builtin_popcountll(ans) < __builtin_popcount(mask)){ ans = 0; for(int i = 0; i < p; i++) if(mask & (1ll<<i)) ans |= (1ll<<bits[i]); } } } } for(int i = 0; i < m; i++) cout << ((ans >> i) & 1); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, x[300300], y[300300]; vector<int> graph[300300]; int counter, dfs_num[300300], dfs_low[300300], dfs_parent[300300]; vector<pair<int, int> > bs; void bridges(int u) { dfs_low[u] = dfs_num[u] = counter++; for (int v : graph[u]) { if (!dfs_num[v]) { dfs_parent[v] = u; bridges(v); if (dfs_low[v] > dfs_num[u]) bs.push_back(pair<int, int>(u, v)); dfs_low[u] = min(dfs_low[u], dfs_low[v]); } else if (v != dfs_parent[u]) { dfs_low[u] = min(dfs_low[u], dfs_num[v]); } } } vector<pair<int, int> > ng[300300]; struct subset { int parent, _rank; } subsets[300300]; int Find(int i) { if (subsets[i].parent != i) subsets[i].parent = Find(subsets[i].parent); return subsets[i].parent; } void Union(int x, int y) { int xroot = Find(x), yroot = Find(y); if (subsets[xroot]._rank < subsets[yroot]._rank) subsets[xroot].parent = yroot; else if (subsets[xroot]._rank > subsets[yroot]._rank) subsets[yroot].parent = xroot; else { subsets[yroot].parent = xroot; subsets[xroot]._rank++; } } int maxi = 1, dist[300300]; void dfs(int u, int p, int d) { if (d > dist[maxi]) maxi = u; dist[u] = d; for (pair<int, int> v : ng[u]) { if (v.first != p) { dfs(v.first, u, d + v.second); } } } int main() { scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d %d , &x[i], &y[i]); graph[x[i]].push_back(y[i]); graph[y[i]].push_back(x[i]); } counter = 1; for (int i = 1; i <= n; i++) if (!dfs_num[i]) bridges(i); for (int i = 1; i <= n; i++) { subsets[i].parent = i; subsets[i]._rank = 1; } for (int i = 0; i < bs.size(); i++) { Union(bs[i].first, bs[i].second); ng[bs[i].first].push_back(pair<int, int>(bs[i].second, 1)); ng[bs[i].second].push_back(pair<int, int>(bs[i].first, 1)); } for (int i = 0; i < m; i++) { if (Find(x[i]) == Find(y[i])) continue; Union(x[i], y[i]); ng[x[i]].push_back(pair<int, int>(y[i], 0)); ng[y[i]].push_back(pair<int, int>(x[i], 0)); } dfs(1, 0, 0); memset(dist, 0, sizeof dist); dfs(maxi, 0, 0); printf( %d n , dist[maxi]); return 0; } |
// Strob signals generator
module strobgen(
input clk_sys,
input ss11, ss12, ss13, ss14, ss15,
input ok$, zw, oken,
input mode, step,
input strob_fp,
input strobb_fp,
output ldstate,
output got,
output strob1,
output strob1b,
output strob2,
output strob2b
);
localparam S_GOT = 3'd0;
localparam S_GOTW = 3'd1;
localparam S_ST1 = 3'd2;
localparam S_ST1W = 3'd3;
localparam S_ST1B = 3'd4;
localparam S_PGOT = 3'd5;
localparam S_ST2 = 3'd6;
localparam S_ST2B = 3'd7;
wire if_busy = zw & oken;
wire es1 = ss11 | (ss12 & ok$) | (ss13 & ok$) | ss14 | ss15;
wire has_strob2 = ss11 | ss12;
wire no_strob2 = ss13 | ss14 | ss15;
assign got = state == S_GOT;
assign strob1 = (state == S_ST1) | strob_fp;
assign strob1b = (state == S_ST1B) | strobb_fp;
assign strob2 = state == S_ST2;
assign strob2b = state == S_ST2B;
assign ldstate = ~if_busy & ((state == S_PGOT) | ((state == S_ST1B) & no_strob2) | (state == S_ST2B));
// * step jest uzbrajany jeśli MODE=1 i wystąpił STROB1
// * STEP zabrania przejścia do stanu STROB2 jeśli ss11 | ss12 (czyli jeśli jesteśmy w strob1 po którym jest strob2, to będziemy trzymać strob1)
// * STEP zabrania przejścia do stanu GOT jeśli ~(ss11 | ss12) (czyli jeśli jesteśmy w strob1 bez strob2, to będziemy trzymać strob1)
// * wciśnięcie STEP zeruje przerzutnik i CPU wykonuje krok (odpala się przejście do następnego stanu)
// * MODE=0 resetuje przerzutnik i trzyma go w takim stanie (czyli step nie działa przy MODE=0)
// * podsumowując: jeśli MODE=1, to podtrzymujemy bieżący stan STROB1 dopóki użytkownik nie wciśnie STOP
// STEP
reg lstep;
always @ (posedge clk_sys) begin
lstep <= step;
end
wire step_trig = ~mode | (step & ~lstep);
// STROBS
reg [0:2] state;
always @ (posedge clk_sys) begin
case (state)
// GOT
S_GOT: begin
if (es1) begin
state <= S_ST1;
end else begin
state <= S_GOTW;
end
end
S_GOTW: begin
if (es1) begin
state <= S_ST1;
end
end
// STROB1 front
S_ST1: begin
if (step_trig) state <= S_ST1B;
else state <= S_ST1W;
end
// STROB1 front (wait for STEP)
S_ST1W: begin
if (step_trig) state <= S_ST1B;
end
// STROB1 back
S_ST1B: begin
if (has_strob2) begin
state <= S_ST2;
end else if (no_strob2 & ~if_busy) begin
state <= S_GOT;
end else begin
state <= S_PGOT;
end
end
// STROB2 front
S_ST2: begin
state <= S_ST2B;
end
// STROB2 back
S_ST2B: begin
if (~if_busy) begin
state <= S_GOT;
end else begin
state <= S_PGOT;
end
end
// STROB2 back (wait for I/F operation to end)
S_PGOT: begin
if (~if_busy) begin
state <= S_GOT;
end
end
endcase
end
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31O_BLACKBOX_V
`define SKY130_FD_SC_HS__A31O_BLACKBOX_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a31o (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31O_BLACKBOX_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Packet format --
// Line 1 -- Length, 32 bits
// Line 2 -- Sequence number, 32 bits
// Last line -- CRC, 32 bits
module packet_verifier
(input clk, input reset, input clear,
input [7:0] data_i, input sof_i, input eof_i, input src_rdy_i, output dst_rdy_o,
output reg [31:0] total,
output reg [31:0] crc_err,
output reg [31:0] seq_err,
output reg [31:0] len_err);
reg [31:0] seq_num;
reg [31:0] length;
wire first_byte, last_byte;
reg second_byte, last_byte_d1;
wire match_crc;
wire calc_crc = src_rdy_i & dst_rdy_o;
crc crc(.clk(clk), .reset(reset), .clear(last_byte_d1), .data(data_i),
.calc(calc_crc), .crc_out(), .match(match_crc));
assign first_byte = src_rdy_i & dst_rdy_o & sof_i;
assign last_byte = src_rdy_i & dst_rdy_o & eof_i;
assign dst_rdy_o = ~last_byte_d1;
// stubs for now
wire match_seq = 1;
wire match_len = 1;
always @(posedge clk)
if(reset | clear)
last_byte_d1 <= 0;
else
last_byte_d1 <= last_byte;
always @(posedge clk)
if(reset | clear)
begin
total <= 0;
crc_err <= 0;
seq_err <= 0;
len_err <= 0;
end
else
if(last_byte_d1)
begin
total <= total + 1;
if(~match_crc)
crc_err <= crc_err + 1;
else if(~match_seq)
seq_err <= seq_err + 1;
else if(~match_len)
seq_err <= len_err + 1;
end
endmodule // packet_verifier
|
#include <bits/stdc++.h> using namespace std; #define ll long long #define vi vector<int> #define pii pair<int,int> #define mii map<int,int> #define pqb priority_queue<int> #define pqs priority_queue<int,vi,greater<int> > #define ff first #define ss second #define pb push_back #define mp make_pair #define PI 3.1415926535897932384626 #define MOD 1000000007 #define ps(x,y) fixed<<setprecision(y)<<x long long int fact[200005]; long long int pwr(long long int a,long long int b){ if(b==0) return 1; if(b==1) return a%MOD; long long int q = pwr((a*a)%MOD,b/2); if(b%2) return (q*a)%MOD; return q; } long long int C(long long int a,long long int b){ if(b<0) return 0; if(a<b) return 0; long long int t1 = (fact[a])%MOD; long long int t2 = (fact[b]*fact[a-b])%MOD; t2 = pwr(t2,MOD-2)%MOD; return (t1*t2)%MOD; } void solve(){ long long int n,l,r; cin>>n>>l>>r; long long int ans=0; ans = C(n,n/2)%MOD; if(n%2) ans = (ans*2)%MOD; ans = (ans*(min(1-l,r-n)))%MOD; for(long long int p=min(1-l,r-n)+1;p<=min(r,n+1-l);p++){ long long int a = p + l - 1; if(a<=0) a = 0; long long int b = n + p - r; if(b<=0) b=0; ans = (C(n-a-b,n/2-a) + ans)%MOD; if(n%2) ans = (C(n-a-b,n/2-b) + ans)%MOD; } cout<<ans<<endl; return; } int main(){ ios_base::sync_with_stdio(false); cin.tie(NULL); // freopen( input.txt , r , stdin); // freopen( error.txt , w , stderr); // freopen( output.txt , w , stdout); fact[0]=1; for(long long int i=1;i<200005;i++){ fact[i] = (fact[i-1]*i)%MOD; } int t=1; cin>>t; for(int i=1;i<=t;i++){ // cout<< Case # <<i<< : ; solve(); } cerr << time taken : << (float)clock() / CLOCKS_PER_SEC << secs << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/18/2016 10:23:41 PM
// Design Name:
// Module Name: nextRC
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "global.vh"
`ifdef CARPOOL_LK_AHEAD_RC_PS
module nextRC(
dst,
dstList,
mc,
indir,
nextPPV
);
input mc;
input [`DST_WIDTH-1:0] dst;
input [`DST_LIST_WIDTH-1:0] dstList;
input [`PC_INDEX_WIDTH-1:0] indir;
output [`NUM_PORT * 4 -1:0] nextPPV;
wire [`PC_INDEX_WIDTH - 2:0] target_outdir_0_plus1, target_outdir_1_plus2, target_outdir_2_plus3, target_outdir_3;
// Notation:
// the target outdir is either 0/1/2/3 for local flit or +1/+2/+3 for non-local flit
assign target_outdir_0_plus1 = (indir == 4) ? 2'd0 : ((indir + 2'd1) % 4);
assign target_outdir_1_plus2 = (indir == 4) ? 2'd1 : ((indir + 2'd2) % 4);
assign target_outdir_2_plus3 = (indir == 4) ? 2'd2 : ((indir + 2'd3) % 4);
assign target_outdir_3 = (indir == 4) ? 2'd3 : indir; // TODO: not sure what will result
wire [`NUM_PORT-1:0] w_ppv_0, w_ppv_1, w_ppv_2, w_ppv_3;
rc rc0(
.dst (dst),
.dstList (dstList),
.outdir (target_outdir_0_plus1),
.mc (mc),
.preferPortVector (w_ppv_0)
);
rc rc1(
.dst (dst),
.dstList (dstList),
.outdir (target_outdir_1_plus2),
.mc (mc),
.preferPortVector (w_ppv_1)
);
rc rc2(
.dst (dst),
.dstList (dstList),
.outdir (target_outdir_2_plus3),
.mc (mc),
.preferPortVector (w_ppv_2)
);
rc rc3(
.dst (dst),
.dstList (dstList),
.outdir (target_outdir_3),
.mc (mc),
.preferPortVector (w_ppv_3)
);
assign nextPPV = (indir == 4) ? {w_ppv_0, w_ppv_1, w_ppv_2, w_ppv_3} :
(indir == 3) ? {w_ppv_0, w_ppv_1, w_ppv_2, `NUM_PORT'h0} :
(indir == 2) ? {w_ppv_0, w_ppv_1, `NUM_PORT'h0, w_ppv_3} :
(indir == 1) ? {w_ppv_0, `NUM_PORT'h0, w_ppv_2, w_ppv_3} :
{`NUM_PORT'h0, w_ppv_1, w_ppv_2, w_ppv_3};
endmodule
`endif // CARPOOL_LK_AHEAD_RC_PS |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; vector<int> c[N]; vector<int> s[20][N]; int dp[20][N]; int h[N]; vector<int> v[N]; int sh(int x, int y) { for (int i = 17; i + 1; --i) if (y & (1 << i)) x = dp[i][x]; return x; } int ac(int x, int y) { if (h[x] > h[y]) x = sh(x, h[x] - h[y]); else y = sh(y, h[y] - h[x]); for (int i = 17; i + 1 && x != y; --i) if (dp[i][x] != dp[i][y]) x = dp[i][x], y = dp[i][y]; if (x == y) return x; else return dp[0][x]; } void dfs(int prec, int node) { h[node] = h[prec] + 1; dp[0][node] = prec; s[0][node] = c[node]; for (auto it : v[node]) if (it != prec) dfs(node, it); } vector<int> get(vector<int> a, vector<int> b) { if (a.empty()) return b; if (b.empty()) return a; int *p = new int[a.size() + b.size()]; merge(a.begin(), a.end(), b.begin(), b.end(), p); vector<int> as; for (int *r = p, cn = 1; cn <= a.size() + b.size() && cn <= 10; ++r, ++cn) as.push_back(*r); while (as.size() && !(*as.begin())) as.erase(as.begin()); return as; } int main(void) { int n, m, q; scanf( %d%d%d n , &n, &m, &q); int a, b; for (int i = 1; i < n; ++i) { scanf( %d%d , &a, &b); v[a].push_back(b); v[b].push_back(a); } for (int i = 1; i <= m; ++i) { scanf( %d , &a); c[a].push_back(i); } for (int i = 1; i <= n; ++i) { sort(c[i].begin(), c[i].end()); while (c[i].size() > 10) c[i].erase(c[i].end() - 1); } dfs(0, 1); for (int i = 1; i < 18; ++i) for (int j = 1; j <= n; ++j) { dp[i][j] = dp[i - 1][dp[i - 1][j]]; s[i][j] = get(s[i - 1][j], s[i - 1][dp[i - 1][j]]); } while (q--) { int a, b, mx; scanf( %d%d%d , &a, &b, &mx); int anc = ac(a, b); int disa = h[a] - h[anc]; int disb = h[b] - h[anc]; vector<int> ans; for (int i = 17; i + 1; --i) if ((1 << i) & disa) { ans = get(ans, s[i][a]); a = dp[i][a]; while (ans.size() > mx) ans.erase(ans.end() - 1); } for (int i = 17; i + 1; --i) if ((1 << i) & disb) { ans = get(ans, s[i][b]); b = dp[i][b]; while (ans.size() > mx) ans.erase(ans.end() - 1); } ans = get(ans, c[anc]); while (ans.size() > mx) ans.erase(ans.end() - 1); printf( %d , ans.size()); for (auto it : ans) printf( %d , it); printf( n ); } return 0; } |
//#############################################################################
//# Purpose: SPI master #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module spi_master # ( parameter DEPTH = 32, // fifo depth
parameter REGS = 16, // total # of regs
parameter AW = 32, // addresss width
parameter PW = 104 // packet width
)
(
//clk,reset, cfg
input clk, // core clock
input nreset, // async active low reset
input hw_en, // hardware enable pin
//IO interface
output sclk, // spi clock
output mosi, // slave input
output ss, // slave select
input miso, // slave output
//packet to transmit
input access_in, // access from core
input [PW-1:0] packet_in, // data to core
output wait_out, // pushback from spi register
//return packet
output access_out, // readback access
output [PW-1:0] packet_out, // packet from spi register
input wait_in // pushback by core
);
//###############
//# LOCAL WIRES
//###############
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] clkdiv_reg; // From spi_master_regs of spi_master_regs.v
wire cpha; // From spi_master_regs of spi_master_regs.v
wire cpol; // From spi_master_regs of spi_master_regs.v
wire [7:0] fifo_dout; // From spi_master_fifo of spi_master_fifo.v
wire fifo_empty; // From spi_master_fifo of spi_master_fifo.v
wire fifo_prog_full; // From spi_master_fifo of spi_master_fifo.v
wire fifo_read; // From spi_master_io of spi_master_io.v
wire fifo_wait; // From spi_master_fifo of spi_master_fifo.v
wire lsbfirst; // From spi_master_regs of spi_master_regs.v
wire manual_mode; // From spi_master_regs of spi_master_regs.v
wire rx_access; // From spi_master_io of spi_master_io.v
wire [63:0] rx_data; // From spi_master_io of spi_master_io.v
wire send_data; // From spi_master_regs of spi_master_regs.v
wire spi_en; // From spi_master_regs of spi_master_regs.v
wire [2:0] spi_state; // From spi_master_io of spi_master_io.v
// End of automatics
//#####################################################
//# Master control registers
//#####################################################
spi_master_regs #(.AW(AW),
.PW(PW))
spi_master_regs (/*AUTOINST*/
// Outputs
.cpol (cpol),
.cpha (cpha),
.lsbfirst (lsbfirst),
.spi_en (spi_en),
.manual_mode (manual_mode),
.send_data (send_data),
.clkdiv_reg (clkdiv_reg[7:0]),
.wait_out (wait_out),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
// Inputs
.clk (clk),
.nreset (nreset),
.hw_en (hw_en),
.rx_data (rx_data[63:0]),
.rx_access (rx_access),
.spi_state (spi_state[2:0]),
.fifo_prog_full (fifo_prog_full),
.fifo_wait (fifo_wait),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]),
.wait_in (wait_in));
//#####################################################
//# Transmit FIFO (SPI_TX)
//#####################################################
/* spi_master_fifo AUTO_TEMPLATE (.wait_out (fifo_wait),
.fifo_dout (fifo_dout[7:0]),
);
*/
spi_master_fifo #(.AW(AW),
.PW(PW),
.DEPTH(DEPTH))
spi_master_fifo(
/*AUTOINST*/
// Outputs
.fifo_prog_full (fifo_prog_full),
.wait_out (fifo_wait), // Templated
.fifo_empty (fifo_empty),
.fifo_dout (fifo_dout[7:0]), // Templated
// Inputs
.clk (clk),
.nreset (nreset),
.spi_en (spi_en),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]),
.fifo_read (fifo_read));
//#####################################################
//# SPI IO (8 bit)
//#####################################################
spi_master_io
spi_master_io (/*AUTOINST*/
// Outputs
.spi_state (spi_state[2:0]),
.fifo_read (fifo_read),
.rx_data (rx_data[63:0]),
.rx_access (rx_access),
.sclk (sclk),
.mosi (mosi),
.ss (ss),
// Inputs
.clk (clk),
.nreset (nreset),
.cpol (cpol),
.cpha (cpha),
.lsbfirst (lsbfirst),
.manual_mode (manual_mode),
.send_data (send_data),
.clkdiv_reg (clkdiv_reg[7:0]),
.fifo_dout (fifo_dout[7:0]),
.fifo_empty (fifo_empty),
.miso (miso));
endmodule // spi_master
|
module RAMB16_S4_S4(
input WEA,
input ENA,
input SSRA,
input CLKA,
input [11:0] ADDRA,
input [3:0] DIA,
// input DIPA,
// output [3:0] DOPA,
output [3:0] DOA,
input WEB,
input ENB,
input SSRB,
input CLKB,
input [11:0] ADDRB,
input [3:0] DIB,
// input DIPB,
// output [3:0] DOPB,
output [3:0] DOB);
parameter WRITE_MODE_A = "write_first";
parameter WRITE_MODE_B = "write_first";
parameter INIT_00=256'd0;
parameter INIT_01=256'd0;
parameter INIT_02=256'd0;
parameter INIT_03=256'd0;
parameter INIT_04=256'd0;
parameter INIT_05=256'd0;
parameter INIT_06=256'd0;
parameter INIT_07=256'd0;
parameter INIT_08=256'd0;
parameter INIT_09=256'd0;
parameter INIT_0A=256'd0;
parameter INIT_0B=256'd0;
parameter INIT_0C=256'd0;
parameter INIT_0D=256'd0;
parameter INIT_0E=256'd0;
parameter INIT_0F=256'd0;
parameter INIT_10=256'd0;
parameter INIT_11=256'd0;
parameter INIT_12=256'd0;
parameter INIT_13=256'd0;
parameter INIT_14=256'd0;
parameter INIT_15=256'd0;
parameter INIT_16=256'd0;
parameter INIT_17=256'd0;
parameter INIT_18=256'd0;
parameter INIT_19=256'd0;
parameter INIT_1A=256'd0;
parameter INIT_1B=256'd0;
parameter INIT_1C=256'd0;
parameter INIT_1D=256'd0;
parameter INIT_1E=256'd0;
parameter INIT_1F=256'd0;
parameter INIT_20=256'd0;
parameter INIT_21=256'd0;
parameter INIT_22=256'd0;
parameter INIT_23=256'd0;
parameter INIT_24=256'd0;
parameter INIT_25=256'd0;
parameter INIT_26=256'd0;
parameter INIT_27=256'd0;
parameter INIT_28=256'd0;
parameter INIT_29=256'd0;
parameter INIT_2A=256'd0;
parameter INIT_2B=256'd0;
parameter INIT_2C=256'd0;
parameter INIT_2D=256'd0;
parameter INIT_2E=256'd0;
parameter INIT_2F=256'd0;
parameter INIT_30=256'd0;
parameter INIT_31=256'd0;
parameter INIT_32=256'd0;
parameter INIT_33=256'd0;
parameter INIT_34=256'd0;
parameter INIT_35=256'd0;
parameter INIT_36=256'd0;
parameter INIT_37=256'd0;
parameter INIT_38=256'd0;
parameter INIT_39=256'd0;
parameter INIT_3A=256'd0;
parameter INIT_3B=256'd0;
parameter INIT_3C=256'd0;
parameter INIT_3D=256'd0;
parameter INIT_3E=256'd0;
parameter INIT_3F=256'd0;
RAMB16_RIGEL #(.WRITE_MODE_A(WRITE_MODE_A),.WRITE_MODE_B(WRITE_MODE_B),.BITS(4),.INIT_00(INIT_00),.INIT_01(INIT_01),.INIT_02(INIT_02),.INIT_03(INIT_03),.INIT_04(INIT_04),.INIT_05(INIT_05),.INIT_06(INIT_06),.INIT_07(INIT_07),.INIT_08(INIT_08),.INIT_09(INIT_09),.INIT_0A(INIT_0A),.INIT_0B(INIT_0B),.INIT_0C(INIT_0C),.INIT_0D(INIT_0D),.INIT_0E(INIT_0E),.INIT_0F(INIT_0F),.INIT_10(INIT_10),.INIT_11(INIT_11),.INIT_12(INIT_12),.INIT_13(INIT_13),.INIT_14(INIT_14),.INIT_15(INIT_15),.INIT_16(INIT_16),.INIT_17(INIT_17),.INIT_18(INIT_18),.INIT_19(INIT_19),.INIT_1A(INIT_1A),.INIT_1B(INIT_1B),.INIT_1C(INIT_1C),.INIT_1D(INIT_1D),.INIT_1E(INIT_1E),.INIT_1F(INIT_1F),.INIT_20(INIT_20),.INIT_21(INIT_21),.INIT_22(INIT_22),.INIT_23(INIT_23),.INIT_24(INIT_24),.INIT_25(INIT_25),.INIT_26(INIT_26),.INIT_27(INIT_27),.INIT_28(INIT_28),.INIT_29(INIT_29),.INIT_2A(INIT_2A),.INIT_2B(INIT_2B),.INIT_2C(INIT_2C),.INIT_2D(INIT_2D),.INIT_2E(INIT_2E),.INIT_2F(INIT_2F),.INIT_30(INIT_30),.INIT_31(INIT_31),.INIT_32(INIT_32),.INIT_33(INIT_33),.INIT_34(INIT_34),.INIT_35(INIT_35),.INIT_36(INIT_36),.INIT_37(INIT_37),.INIT_38(INIT_38),.INIT_39(INIT_39),.INIT_3A(INIT_3A),.INIT_3B(INIT_3B),.INIT_3C(INIT_3C),.INIT_3D(INIT_3D),.INIT_3E(INIT_3E),.INIT_3F(INIT_3F)) inner_ram(.WEA(WEA),.ENA(ENA),.SSRA(SSRA),.CLKA(CLKA),.ADDRA(ADDRA),.DIA(DIA),.DIPA(1'b0),.DOA(DOA),.WEB(WEB),.ENB(ENB),.SSRB(SSRB),.CLKB(CLKB),.ADDRB(ADDRB),.DIB(DIB),.DIPB(1'b0),.DOB(DOB));
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_nios2_qsys_0_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int C = 26; void add(int &x, int y) { x += y; while (x >= MOD) x -= MOD; while (x < 0) x += MOD; } int fix(int x) { while (x >= MOD) x -= MOD; while (x < 0) x += MOD; return x; } int pw(int a, int b) { int ret = 1; while (b) { if (b & 1) ret = 1ll * ret * a % MOD; b >>= 1; a = 1ll * a * a % MOD; } return ret; } const int MAXN = 105; int n, m, dp[MAXN][MAXN], l[MAXN][MAXN], r[MAXN][MAXN]; void solve() { cin >> n >> m; for (int i = 0; i < n; i++) { int k; cin >> k; for (int rep = 0; rep < k; rep++) { int a, b; cin >> a >> b; --a; for (int j = a; j < b; j++) { r[i][j] = b; l[i][j] = a; } } } for (int b = m - 1; ~b; --b) { for (int e = b + 1; e <= m; e++) { for (int k = b; k < e; k++) { int val = 0; for (int i = 0; i < n; i++) if (b <= l[i][k] && r[i][k] <= e) ++val; dp[b][e] = max(dp[b][e], val * val + dp[b][k] + dp[k + 1][e]); } } } cout << dp[0][m] << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int te = 1; for (int w = 1; w <= te; w++) { solve(); } return 0; } |
// Copyright (c) 2016 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Resize function test
module vhdl_resize_test;
logic signed [7:0] in;
logic signed [15:0] out;
vhdl_resize dut(in, out);
initial begin
in = -120;
#0;
if(out !== -115) begin
$display("FAILED 1: out = %d", out);
$finish();
end
in = 120;
#0;
if(out !== 125) begin
$display("FAILED 2: out = %d", out);
$finish();
end
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_2_V
`define SKY130_FD_SC_MS__A222O_2_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog wrapper for a222o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a222o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a222o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a222o_2 (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__OR2_PP_BLACKBOX_V
/**
* or2: 2-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2_PP_BLACKBOX_V
|
`include "../../include/incparams.vh"
module dp_sync_fifo #(
parameter WIDTH = 64,
parameter DEPTH = 1024,
parameter AWIDTH = `CLOG2(DEPTH)
)(
input rst,
input clk,
input wra,
input rda,
input [WIDTH-1:0] dina,
output [WIDTH-1:0] douta,
input wrb,
input rdb,
input [WIDTH-1:0] dinb,
output [WIDTH-1:0] doutb,
output empty,
output full,
output conflict
);
reg [AWIDTH:0] rd_ptr, wr_ptr;
wire [WIDTH-1:0] ram_douta, ram_doutb;
wire [AWIDTH-1:0] ram_addra, ram_addrb;
initial begin
wr_ptr <= 0;
rd_ptr <= 0;
end
//*************** FIFO STATUS *****************************************
assign empty = (wr_ptr == rd_ptr);
assign full = (wr_ptr[AWIDTH] != rd_ptr[AWIDTH]) &&
(wr_ptr[AWIDTH-1:0] == rd_ptr[AWIDTH-1:0]);
assign conflict = (wra && wrb) || (rda && rdb) ||
(wra && rda) || (wrb && rdb);
//*************** FIFO POINTERS ***************************************
always@(posedge clk or posedge rst) begin
if(rst) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
if (!full && (wra || wrb))
wr_ptr <= wr_ptr + 1;
if (!empty && (rda || rdb))
rd_ptr <= rd_ptr + 1;
end
end
//*************** RAM INTERFACE***************************************
assign douta = rst ? 0 : ((!empty && rda && !rdb) ? ram_douta : douta);
assign doutb = rst ? 0 : ((!empty && !rda && rdb) ? ram_doutb : doutb);
assign ram_addra = (wra && !wrb) ? wr_ptr : ((rda && !rdb) ? rd_ptr : 0);
assign ram_addrb = (!wra && wrb) ? wr_ptr : ((!rda && rdb) ? rd_ptr : 0);
dpram fifomem (
.clka (clka),
.wea (wra),
.addra (ram_addra),
.dina (dina),
.douta (ram_douta),
.clkb (clkb),
.web (wrb),
.addrb (ram_addrb),
.dinb (dinb),
.doutb (ram_doutb)
);
defparam fifomem.DATA = WIDTH;
defparam fifomem.ADDR = AWIDTH;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; for (int i = 0; i < n; i++) { cout << 3 * n + i; if (i == n - 1) cout << endl; else cout << ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_1_V
`define SKY130_FD_SC_HVL__MUX4_1_V
/**
* mux4: 4-input multiplexer.
*
* Verilog wrapper for mux4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__mux4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__mux4_1 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__mux4_1 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__mux4 base (
.X(X),
.A0(A0),
.A1(A1),
.A2(A2),
.A3(A3),
.S0(S0),
.S1(S1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_1_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; const int maxn = 1e5 + 5; int n, a[maxn]; int b[maxn]; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n; int sum = 0; map<int, int> mp; for (int i = 0; i < n; i++) { cin >> a[i]; mp[a[i]]++; } bool poss = false; for (int i = 0; i < n; i++) { if (a[i] > 0) { if (--mp[a[i]] == 0) mp.erase(a[i]); ++mp[a[i] - 1]; if (mp.size() == n) { poss = true; } if (--mp[a[i] - 1] == 0) mp.erase(a[i] - 1); ++mp[a[i]]; } } if (!poss) { cout << cslnb << n ; return 0; } sort(a, a + n); b[0] = 0; for (int i = 1; i < n; i++) { b[i] = min(a[i], b[i - 1] + 1); } for (int i = 0; i < n; i++) { sum += (a[i] - b[i] + 2) % 2; sum %= 2; } cout << (sum == 1 ? sjfnb : cslnb ) << n ; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// Testbench of CONTROL module for HIGHT Crypto Core ////
//// ////
//// This file is part of the HIGHT Crypto Core project ////
//// http://github.com/OpenSoCPlus/hight_crypto_core ////
//// http://www.opencores.org/project,hight ////
//// ////
//// Description ////
//// __description__ ////
//// ////
//// Author(s): ////
//// - JoonSoo Ha, ////
//// - Younjoo Kim, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2015 Authors, OpenSoCPlus and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module tb_CONTROL;
event do_finish;
//=====================================
//
// PARAMETERS
//
//=====================================
parameter HP_CLK = 5; // Half period of clock
//=====================================
//
// I/O PORTS
//
//=====================================
reg rstn ;
reg clk ;
reg i_mk_rdy ;
reg i_post_rdy ;
reg i_text_val ;
wire o_rdy ;
wire o_text_done ;
wire[2:0] o_xf_sel ;
wire o_rf_final ;
wire o_key_sel ;
wire[4:0] o_rnd_idx ;
wire o_wf_post_pre ;
//=====================================
//
// PORT MAPPING
//
//=====================================
CONTROL uut_CONTROL(
.rstn (rstn ) ,
.clk (clk ) ,
.i_mk_rdy (i_mk_rdy ) ,
.i_post_rdy (i_post_rdy ) ,
.i_text_val (i_text_val ) ,
.o_rdy (o_rdy ) ,
.o_text_done (o_text_done ) ,
.o_xf_sel (o_xf_sel ) ,
.o_rf_final (o_rf_final ) ,
.o_key_sel (o_key_sel ) ,
.o_rnd_idx (o_rnd_idx ) ,
.o_wf_post_pre (o_wf_post_pre)
);
//=====================================
//
// STIMULUS
//
//=====================================
// clock generation
initial begin
clk = 1'b0;
forever clk = #(HP_CLK) ~clk;
end
// reset generation
initial begin
rstn = 1'b1;
@(posedge clk);
@(negedge clk);
rstn = 1'b0;
repeat(2) @(negedge clk);
rstn = 1'b1;
end
// input generation
initial begin
$display("===== SIM START =====");
// insert your code
// initial input value
i_mk_rdy = 1'b1;
i_post_rdy = 1'b1;
i_text_val = 1'b0;
// reset time
@(negedge rstn);
@(posedge rstn);
@(negedge clk);
// Key Config Phase
@(negedge clk);
i_mk_rdy = 1'b0;
repeat(4) @(posedge clk);
@(negedge clk);
i_mk_rdy = 1'b1;
//// first ciphering ////
// insert 2 clock delay
@(posedge clk);
repeat(2) @(posedge clk);
// insert text
@(negedge clk);
i_text_val = 1'b1;
@(negedge clk);
i_text_val = 1'b0;
// wait text done
wait(o_text_done)
@(posedge clk);
// post rdy inactive
@(negedge clk);
i_post_rdy = 1'b0;
//// second ciphering ////
// insert text
@(negedge clk);
i_text_val = 1'b1;
@(negedge clk);
i_text_val = 1'b0;
// wait done state
wait(uut_CONTROL.r_pstate == uut_CONTROL.S_DONE)
@(posedge clk);
// insert 3clk delay
repeat(3) @(posedge clk);
// post rdy active
i_post_rdy = 1'b1;
repeat(10) @(posedge clk);
-> do_finish;
end
// state monitoring
reg[20*8:1] state;
always @(uut_CONTROL.r_pstate) begin
case(uut_CONTROL.r_pstate)
uut_CONTROL.S_IDLE : state <= "IDLE ";
uut_CONTROL.S_KEY_CONFIG : state <= "KEY_CONFIG";
uut_CONTROL.S_RDY : state <= "RDY ";
uut_CONTROL.S_WF1 : state <= "WF1 ";
uut_CONTROL.S_RF1 : state <= "RF1 ";
uut_CONTROL.S_RF2 : state <= "RF2 ";
uut_CONTROL.S_RF3 : state <= "RF3 ";
uut_CONTROL.S_RF4 : state <= "RF4 ";
uut_CONTROL.S_RF5 : state <= "RF5 ";
uut_CONTROL.S_RF6 : state <= "RF6 ";
uut_CONTROL.S_RF7 : state <= "RF7 ";
uut_CONTROL.S_RF8 : state <= "RF8 ";
uut_CONTROL.S_RF9 : state <= "RF9 ";
uut_CONTROL.S_RF10 : state <= "RF10 ";
uut_CONTROL.S_RF11 : state <= "RF11 ";
uut_CONTROL.S_RF12 : state <= "RF12 ";
uut_CONTROL.S_RF13 : state <= "RF13 ";
uut_CONTROL.S_RF14 : state <= "RF14 ";
uut_CONTROL.S_RF15 : state <= "RF15 ";
uut_CONTROL.S_RF16 : state <= "RF16 ";
uut_CONTROL.S_RF17 : state <= "RF17 ";
uut_CONTROL.S_RF18 : state <= "RF18 ";
uut_CONTROL.S_RF19 : state <= "RF19 ";
uut_CONTROL.S_RF20 : state <= "RF20 ";
uut_CONTROL.S_RF21 : state <= "RF21 ";
uut_CONTROL.S_RF22 : state <= "RF22 ";
uut_CONTROL.S_RF23 : state <= "RF23 ";
uut_CONTROL.S_RF24 : state <= "RF24 ";
uut_CONTROL.S_RF25 : state <= "RF25 ";
uut_CONTROL.S_RF26 : state <= "RF26 ";
uut_CONTROL.S_RF27 : state <= "RF27 ";
uut_CONTROL.S_RF28 : state <= "RF28 ";
uut_CONTROL.S_RF29 : state <= "RF29 ";
uut_CONTROL.S_RF30 : state <= "RF30 ";
uut_CONTROL.S_RF31 : state <= "RF31 ";
uut_CONTROL.S_RF32 : state <= "RF32 ";
uut_CONTROL.S_DONE : state <= "DONE ";
uut_CONTROL.S_ERROR : state <= "ERROR ";
endcase
end
// finish
initial begin
@do_finish
$finish;
end
// vcd dump
initial begin
$dumpfile("dump/sim_tb_CONTROL.vcd");
$dumpvars(0, tb_CONTROL);
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module lpddr2_cntrlr_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
lpddr2_cntrlr_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
lpddr2_cntrlr_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
lpddr2_cntrlr_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
lpddr2_cntrlr_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
lpddr2_cntrlr_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
defparam ureset_seq_clk.RESET_SYNC_STAGES = 15;
defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
lpddr2_cntrlr_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
defparam ureset_scc_clk.RESET_SYNC_STAGES = 15;
defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
lpddr2_cntrlr_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
defparam ureset_avl_clk.RESET_SYNC_STAGES = 2;
defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
lpddr2_cntrlr_p0_reset_sync #(
.RESET_SYNC_STAGES(15),
.NUM_RESET_OUTPUT(1)
)
ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
|
// Library - static, Cell - th23, View - schematic
// LAST TIME SAVED: May 23 16:36:22 2014
// NETLIST TIME: May 23 16:36:43 2014
`timescale 1ns / 1ns
module th23 ( y, a, b, c );
output y;
input a, b, c;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th23";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N14 ( .d(net32), .g(b), .s(net037), .b(cds_globals.gnd_));
nfet_b N6 ( .d(net037), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N5 ( .d(net32), .g(c), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net037), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net32), .g(a), .s(net037), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net45), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N1 ( .d(net32), .g(a), .s(net45), .b(cds_globals.gnd_));
pfet_b P11 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net035));
pfet_b P7 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net035));
pfet_b P10 ( .b(cds_globals.vdd_), .g(c), .s(net035), .d(net038));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(net038), .d(net32));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(net34), .d(net32));
pfet_b P3 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net32));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net32);
endmodule
|
#include <bits/stdc++.h> using namespace std; void read(long long &x) { x = 0; char c = getchar(); long long f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -f; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + c - 0 ; c = getchar(); } x *= f; return; } void print(long long x) { if (x < 10) { putchar(x + 0 ); return; } print(x / 10); putchar(x % 10 + 0 ); } void write(long long x) { if (x < 0) x = -x, putchar( - ); print(x); } long long maxt(long long a, long long b) { return a < b ? b : a; } long long mint(long long a, long long b) { return a < b ? a : b; } struct node { long long v, id; node(long long V, long long Id) { v = V, id = Id; } }; stack<long long> q, r; vector<node> R[1000005], G[1000005]; vector<long long> E[1000005]; long long n, m, dfn[1000005], low[1000005], cnt, w[1000005], s[1000005], bel[1000005], f[1000005], e[1000005], dep[1000005], col; void tarjan(long long u, long long fa) { q.push(u); dfn[u] = low[u] = ++cnt; for (int i = 0; i < R[u].size(); i++) { long long v = R[u][i].v, id = R[u][i].id; if (v == fa) continue; r.push(id); if (!dfn[v]) { tarjan(v, u); low[u] = mint(low[u], low[v]); if (low[v] > dfn[u]) { ++col; while (r.top() != id) { if (w[r.top()]) s[col] = 1; r.pop(); } r.pop(); while (q.top() != v) { bel[q.top()] = col; E[col].push_back(q.top()); q.pop(); } bel[v] = col; E[col].push_back(v); q.pop(); } } else low[u] = mint(low[u], dfn[v]); } if (fa == -1) { ++col; while (!r.empty()) { if (w[r.top()]) s[col] = 1; r.pop(); } while (!q.empty()) { bel[q.top()] = col; E[col].push_back(q.top()); q.pop(); } } } void dfs(long long u, long long fa) { f[u] = fa; dep[u] = dep[fa] + 1; for (int i = 0; i < G[u].size(); i++) { long long v = G[u][i].v, id = G[u][i].id; if (v == fa) continue; e[v] = id; dfs(v, u); } } int main() { read(n), read(m); for (int i = 1; i <= m; i++) { long long u, v; read(u), read(v), read(w[i]); R[u].push_back(node(v, i)); R[v].push_back(node(u, i)); } for (int i = 1; i <= n; i++) if (!dfn[i]) tarjan(i, -1); for (int i = 1; i <= col; i++) for (int j = 0; j < E[i].size(); j++) { long long u = E[i][j]; for (int k = 0; k < R[u].size(); k++) { long long v = R[u][k].v, id = R[u][k].id; if (bel[u] != bel[v]) G[bel[u]].push_back(node(bel[v], id)); } } dfs(1, 1); long long a, b; bool fl = 0; read(a), read(b); a = bel[a], b = bel[b]; if (dep[a] < dep[b]) swap(a, b); while (dep[a] > dep[b]) { if (w[e[a]] || s[a]) fl = 1; a = f[a]; } while (a != b) { if (w[e[a]] || w[e[b]] || s[a] || s[b]) fl = 1; a = f[a]; b = f[b]; } if (s[a]) fl = 1; if (fl) puts( YES ); else puts( NO ); } |
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::high_resolution_clock::now().time_since_epoch().count()); const double eps = 0.00001; const int MOD = 1000000007; const int INF = 1000055555; const long long LLINF = 1223372000000000555; const int N = 1e5 + 1e4; const int M = 1234; const int MAGIC = 10; vector<int> merge(vector<int> a, vector<int> b) { vector<int> v; int i = 0, j = 0; while (i < a.size() || j < b.size()) { if (v.size() == MAGIC) break; if (i == a.size()) v.push_back(b[j++]); else if (j == b.size()) v.push_back(a[i++]); else if (a[i] < b[j]) v.push_back(a[i++]); else v.push_back(b[j++]); if (v.size() > 1 && v[v.size() - 2] == v.back()) v.pop_back(); } return v; } vector<int> g[N]; vector<int> arr[N][20]; int tin[N], tout[N], timer = 0; int up[N][20]; void dfs(int v, int p) { tin[v] = ++timer; up[v][0] = p; for (int i = 1; i < 20; i++) { up[v][i] = up[up[v][i - 1]][i - 1]; int UP = up[v][i - 1]; arr[v][i] = merge(arr[v][i - 1], arr[UP][i - 1]); } for (int u : g[v]) { if (u != p) dfs(u, v); } tout[v] = ++timer; } bool upper(int a, int b) { return (tin[a] <= tin[b] && tout[a] >= tout[b]); } int LCA(int a, int b) { if (upper(a, b)) return a; if (upper(b, a)) return b; for (int i = 19; i >= 0; i--) { if (!upper(up[a][i], b)) a = up[a][i]; } return up[a][0]; } void out(vector<int> &v, int a) { int k = min(a, ((int)v.size())); cout << k << ; for (int i = 0; i < k; i++) { cout << v[i] << ; } cout << endl; } void solve() { int n, m, q; cin >> n >> m >> q; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } for (int i = 1; i <= m; i++) { int x; cin >> x; arr[x][0].push_back(i); } for (int i = 1; i <= n; i++) { if (arr[i][0].size() > MAGIC) arr[i][0].resize(MAGIC); } dfs(1, 1); while (q--) { int u, v, a; cin >> u >> v >> a; if (v == u) { out(arr[v][0], a); continue; } int lca = LCA(u, v); if (u == lca) { vector<int> vv; for (int i = 19; i >= 0; i--) { if (!upper(up[v][i], lca) && up[v][i]) { vv = merge(vv, arr[v][i]); v = up[v][i]; } } vv = merge(vv, arr[u][0]); vv = merge(vv, arr[v][0]); out(vv, a); continue; } if (v == lca) { vector<int> vv; for (int i = 19; i >= 0; i--) { if (!upper(up[u][i], lca)) { vv = merge(vv, arr[u][i]); u = up[u][i]; } } vv = merge(vv, arr[u][0]); vv = merge(vv, arr[v][0]); out(vv, a); continue; } vector<int> vv = arr[lca][0]; for (int i = 19; i >= 0; i--) { if (!upper(up[v][i], lca)) { vv = merge(vv, arr[v][i]); v = up[v][i]; } } for (int i = 19; i >= 0; i--) { if (!upper(up[u][i], lca)) { vv = merge(vv, arr[u][i]); u = up[u][i]; } } vv = merge(vv, arr[u][0]); vv = merge(vv, arr[v][0]); out(vv, a); } } int main() { ios_base::sync_with_stdio(false); int T = 1; while (T--) { solve(); } return 0; } |
//#############################################################################
//# Function: Rising Edge Sampled Register #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_reg1 #(parameter DW = 1 // data width
)
( input nreset, //async active low reset
input clk, // clk, latch when clk=0
input [DW-1:0] in, // input data
output [DW-1:0] out // output data (stable/latched when clk=1)
);
localparam ASIC = `CFG_ASIC;
generate
if(ASIC)
begin : g0
asic_reg1 ireg [DW-1:0] (.nreset(nreset),
.clk(clk),
.in(in[DW-1:0]),
.out(out[DW-1:0]));
end
else
begin
reg [DW-1:0] out_reg;
always @ (posedge clk or negedge nreset)
if(!nreset)
out_reg[DW-1:0] <= 'b0;
else
out_reg[DW-1:0] <= in[DW-1:0];
assign out[DW-1:0] = out_reg[DW-1:0];
end // else: !if(ASIC)
endgenerate
endmodule // ohr_reg1
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n; cin >> n; long long a[n + 2]; map<long long, long long> m; for (long long i = 1; i <= 1000; i++) { m[i] = 0; } for (long long i = 0; i < n; i++) { cin >> a[i]; m[a[i]]++; } vector<pair<long long, long long>> v; for (auto i : m) { v.push_back({i.first, i.second}); } long long d = 0; sort(v.rbegin(), v.rend()); for (long long i = 0; i < v.size(); i++) { d += v[i].second; if (d >= v[i].first) { cout << v[i].first << endl; break; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; typedef int8_t i8; typedef int16_t i16; typedef int32_t i32; typedef int64_t i64; typedef ptrdiff_t isize; typedef uint8_t u8; typedef uint16_t u16; typedef uint32_t u32; typedef uint64_t u64; typedef size_t usize; typedef float f32; typedef double f64; i64 gcd(i64 a, i64 b, i64& x, i64& y) { if (b == 0) { x = 1; y = 0; return a; } i64 x1, y1; i64 d = gcd(b, a % b, x1, y1); x = y1; y = x1 - y1 * (a / b); return d; } auto main() -> i32 { ios::sync_with_stdio(false), cin.tie(nullptr); i64 n, m, k; cin >> n >> m >> k; vector<i64> a(max(n, m) + 1); i64 M = 2 * max(n, m); vector<i64> p(M + 1, -1); if (n <= m) { for (i64 i = 1; i <= n; i++) { cin >> a[i]; } for (i64 i = 1; i <= m; i++) { i64 b; cin >> b; p[b] = i; } } else { swap(n, m); for (i64 i = 1; i <= m; i++) { i64 b; cin >> b; p[b] = i; } for (i64 i = 1; i <= n; i++) { cin >> a[i]; } } vector<i64> min_rnd(n + 1, -1); i64 g; { i64 x, y; g = gcd(n, m, x, y); } i64 lcm = m / g; for (i64 i = 1; i <= n; i++) { if (p[a[i]] != -1) { i64 dif = 0; if (i > p[a[i]]) { dif = p[a[i]] + m - i; } else { dif = p[a[i]] - i; } if (dif % g == 0) { dif /= g; i64 x, y; gcd(n / g, m / g, x, y); x = (x % lcm + lcm) % lcm; min_rnd[i] = (x * dif) % (lcm)+1; } } } i64 l = 1, r = 1e18 + 1; while (l < r) { i64 d = (l + r) / 2; i64 bad = 0; { for (i64 i = 1; i <= n; i++) { i64 rnd = d / n + (d % n >= i ? 1 : 0); if (min_rnd[i] != -1) { bad += rnd - rnd / lcm - ((rnd % lcm) >= min_rnd[i] ? 1 : 0); } else { bad += rnd; } } } if (bad >= k) { r = d; } else if (bad < k) { l = d + 1; } } cout << l; cout << n ; return 0; } |
module driver (clk, state, enable);
/*
Listen for state changes; on such changes, wait a specified number
of clock cycles, and then trigger enable bit to indicate state change.
Because the CapBoardDecoder works on the enable level rather than the enable
edge, enable should be on for some period of time. If enable is on
so long as to overlap with the next state change, this should not present a problem;
the CapBoardDecoders will then just make two consecutive changes.
*/
input clk;
input [6:0] state; //7 bit number to go on backplane logic bus
output enable; // gating signal telling listener boards when to update.
reg enableReg; //Signal to modify in procedural blocks corresponding to enable.
//Allow state to settle first for triggering enable.
reg [2:0] settleTimeCntr;
//Leave enable on for 31 clock cycles before resetting - give CapBoardDecoder a chance to make sure enable trigger is genuine.
reg [4:0] enableOnCntr;
reg settleTimeFlag; //Flag indicating whether we are waiting for state to settle.
reg enableOnFlag; //Flag indicating whether we are waiting for enable to finish its ON cycle after a settled state change.
reg [6:0] stateLast; //Store previous state to listen for changes.
//Wait times
parameter SETTLE_TIME=3'b111;
parameter ENABLE_ON_TIME=5'b11111;
initial begin
stateLast=7'b0; //Initialize stateLast.
settleTimeCntr=3'b0; //Initialize counter which increments while waiting for state to settle.
enableOnCntr=5'b0; //Initialize counter which increments while leaving the state-change-enable flag bit on.
settleTimeFlag=1'b0; //Initialize flag indicating that we are waiting for state to settle.
enableOnFlag=1'b0; //Initialize flag indicating that we should leave the enable bit ON.
//The compiler once reported that the enable was getting locked at 0;
//now, it does not report this, and I don't know what changed.
enableReg=1'b0; //Initialize enable bit to OFF.
end
//Listen for changes in state by comparing state between clock pulses.
always @(posedge clk) begin
//If there is a state change, wait for a period, then trigger enable on
//for a period, then turn off enable, update the stored state, and
//continue listening.
if(|(stateLast - state)) begin //If there is any difference between the the current and last state
//Reset settle time and enable on counter - this is in case
//there is another state change while we are waiting for state to settle.
settleTimeCntr=3'b0;
//Trigger flag for counting settle time
settleTimeFlag=1'b1;
stateLast=state; //Update state.
end
//If settleTimeFlag is ON, start incrementing counter
//which determines the time since the last state change; if it
//reaches its threshold value of 7, then the state is considered "stable"
//after its last change, and we can turn on the ENABLE bit.
if(settleTimeFlag) begin
if(settleTimeCntr==SETTLE_TIME) begin
settleTimeFlag=1'b0; //The state is settled - turn settle time wait flag off.
enableOnFlag=1'b1; //Indicate that the ENABLE on time period should begin.
settleTimeCntr=3'b0; //Zero counter.
//Zero enable on counter - this is in case there are overlapping on-times
//associated with state changes - make sure that the last state change
//gets the full enable-on period.
enableOnCntr=5'b0;
end else settleTimeCntr=settleTimeCntr+3'b1; //Increment.
end
//If enableOnFlag is ON, start incrementing counter which determines
//how long the enable bit has bin on. Once it has been on for its
//threshold period of time - when the enableOnCntr==31 - turn off
//enable and its flag.
if(enableOnFlag) begin
if(enableOnCntr==ENABLE_ON_TIME) begin
enableReg=1'b0; //Turn off enable bit.
enableOnFlag=1'b0; //Enable doesn't need to be on any more.
enableOnCntr=5'b0; //Zero counter.
end else begin
enableReg=1'b1; //Keep enable bit on.
enableOnCntr=enableOnCntr+5'b1; //Increment.
end
end
end
assign enable=enableReg; //Tie actual enable output to the associated register variable.
endmodule
|
#include <bits/stdc++.h> using namespace std; long double PI = acosl(-1); bool compare_int(int a, int b) { return (a > b); } bool compare_string(string a, string b) { return a.size() < b.size(); } bool compare_pair(const pair<int, int> &a, const pair<int, int> &b) { if (a.second == b.second) return a.first < b.first; else return (a.second > b.second); } bool cmp(pair<string, int> x, pair<string, int> y) { return (x.second < y.second); } long long int bigmod(long long int a, long long int b, long long int m) { if (b == 0) return 1 % m; long long int x = bigmod(a, b / 2, m); x = (x * x) % m; if (b % 2 == 1) x = (x * a) % m; return x; } void NA() { printf( NO n ); exit(0); } void YA() { printf( YES n ); exit(0); } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; long long int mx = 0LL, mn = 0LL; sort(a.begin(), a.end()); for (int i = 0; i < n; i++) { mx = (mx + bigmod(2, i, 1000000007) * a[i]) % 1000000007; mn = (mn + bigmod(2, n - i - 1, 1000000007) * a[i]) % 1000000007; } cout << (mx - mn + 1000000007) % 1000000007 << endl; } |
/*******************************************************************************
* Module: axi_hp_clk
* Date:2015-04-27
* Author: Andrey Filippov
* Description: Generate global clock for axi_hp
*
* Copyright (c) 2015 Elphel, Inc.
* axi_hp_clk.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* axi_hp_clk.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module axi_hp_clk#(
parameter CLKIN_PERIOD = 20, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_AXIHP = 6 // To get 150MHz for the reference clock
)(
input rst,
input clk_in,
output clk_axihp,
output locked_axihp
);
wire clkfb_axihp, clk_axihp_pre;
BUFG clk_axihp_i (.O(clk_axihp), .I(clk_axihp_pre));
pll_base #(
.CLKIN_PERIOD(CLKIN_PERIOD), // 20
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(CLKFBOUT_MULT_AXIHP), // 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
.CLKOUT0_DIVIDE(CLKFBOUT_DIV_AXIHP), // 6, // To get 300MHz for the reference clock
.REF_JITTER1(0.010),
.STARTUP_WAIT("FALSE")
) pll_base_i (
.clkin(clk_in), // input
.clkfbin(clkfb_axihp), // input
// .rst(rst), // input
.rst(rst), // input
.pwrdwn(1'b0), // input
.clkout0(clk_axihp_pre), // output
.clkout1(), // output
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout(clkfb_axihp), // output
.locked(locked_axihp) // output
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:26:00 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top zqynq_lab_1_design_auto_pc_0 -prefix
// zqynq_lab_1_design_auto_pc_0_ zqynq_lab_1_design_auto_pc_1_stub.v
// Design : zqynq_lab_1_design_auto_pc_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module zqynq_lab_1_design_auto_pc_0(aclk, aresetn, s_axi_awaddr, s_axi_awlen,
s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awregion,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr,
s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot,
s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__XOR3_BEHAVIORAL_PP_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , A, B, C );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR3_BEHAVIORAL_PP_V |
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: mor1kx processor avalon bus bridge
Copyright (C) 2013 Stefan Kristiansson <>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_bus_if_avalon
#(
parameter OPTION_AVALON_BURST_LENGTH = 4
)
(
input clk,
input rst,
output cpu_err_o,
output cpu_ack_o,
output [31:0] cpu_dat_o,
input [31:0] cpu_adr_i,
input [31:0] cpu_dat_i,
input cpu_req_i,
input [3:0] cpu_bsel_i,
input cpu_we_i,
input cpu_burst_i,
output [31:0] avm_address_o,
output [3:0] avm_byteenable_o,
output avm_read_o,
input [31:0] avm_readdata_i,
output [3:0] avm_burstcount_o,
output avm_write_o,
output [31:0] avm_writedata_o,
input avm_waitrequest_i,
input avm_readdatavalid_i
);
localparam IDLE = 4'b0001;
localparam READ = 4'b0010;
localparam BURST = 4'b0100;
localparam WRITE = 4'b1000;
reg [3:0] state;
always @(posedge clk) begin
case (state)
IDLE: begin
if (cpu_req_i & !avm_waitrequest_i) begin
if (cpu_we_i)
state <= WRITE;
else if (cpu_burst_i) begin
state <= BURST;
end else
state <= READ;
end
end
READ: begin
if (avm_readdatavalid_i)
state <= IDLE;
end
BURST: begin
/* cpu_burst_i deasserts when the last burst access starts */
if (!cpu_burst_i & avm_readdatavalid_i)
state <= IDLE;
end
WRITE: begin
state <= IDLE;
end
endcase
end
assign avm_address_o = cpu_adr_i;
assign avm_read_o = cpu_req_i & !cpu_we_i & (state == IDLE);
assign avm_byteenable_o = cpu_bsel_i;
assign avm_write_o = cpu_req_i & cpu_we_i & (state == IDLE);
assign avm_burstcount_o = cpu_burst_i & (state != BURST) ?
OPTION_AVALON_BURST_LENGTH : 4'd1;
assign avm_writedata_o = cpu_dat_i;
assign cpu_err_o = 0;
assign cpu_ack_o = avm_readdatavalid_i | state == WRITE;
assign cpu_dat_o = avm_readdata_i;
endmodule
|
/* uart */
module paula_uart (
input wire clk,
input wire clk7_en,
input wire reset,
input wire [ 8-1:0] rga_i,
input wire [ 16-1:0] data_i,
output wire [ 16-1:0] data_o,
input wire uartbrk,
input wire rbfmirror,
output wire txint,
output wire rxint,
output wire txd,
input wire rxd
);
//// registers ////
localparam REG_SERDAT = 9'h030;
localparam REG_SERDATR = 9'h018;
localparam REG_SERPER = 9'h032;
//// bits ////
localparam LONG_BIT = 15;
localparam OVRUN_BIT = 15-11;
localparam RBF_BIT = 14-11;
localparam TBE_BIT = 13-11;
localparam TSRE_BIT = 12-11;
localparam RXD_BIT = 11-11;
//// RX input sync ////
reg [ 2-1:0] rxd_sync = 2'b11;
wire rxds;
always @ (posedge clk) begin
if (clk7_en) begin
rxd_sync <= #1 {rxd_sync[0],rxd};
end
end
assign rxds = rxd_sync[1];
//// write registers ////
// SERPER
reg [ 16-1:0] serper = 16'h0000;
always @ (posedge clk) begin
if (clk7_en) begin
if (rga_i == REG_SERPER[8:1])
serper <= #1 data_i;
end
end
// SERDAT
reg [ 16-1:0] serdat = 16'h0000;
always @ (posedge clk) begin
if (clk7_en) begin
if (rga_i == REG_SERDAT[8:1])
serdat <= #1 data_i;
end
end
//// TX ////
localparam [ 2-1:0] TX_IDLE=2'd0, TX_SHIFT=2'd2;
reg [ 2-1:0] tx_state;
reg [ 16-1:0] tx_cnt;
reg [ 16-1:0] tx_shift;
reg tx_txd;
reg tx_irq;
reg tx_tbe;
reg tx_tsre;
always @ (posedge clk) begin
if (clk7_en) begin
if (reset) begin
tx_state <= #1 TX_IDLE;
tx_txd <= #1 1'b1;
tx_irq <= #1 1'b0;
tx_tbe <= #1 1'b1;
tx_tsre <= #1 1'b1;
end else begin
case (tx_state)
TX_IDLE : begin
// txd pin inactive in idle state
tx_txd <= #1 1'b1;
// check if new data loaded to serdat register
if (!tx_tbe) begin
// set interrupt request
tx_irq <= #1 1'b1;
// data buffer empty again
//tx_tbe <= #1 1'b1;
// generate start bit
tx_txd <= #1 1'b0;
// pass data to a shift register
tx_tsre <= #1 1'b0;
tx_shift <= #1 serdat;
// reload period register
tx_cnt <= #1 {serper[14:0], 1'b1};
// start bitstream generation
tx_state <= #1 TX_SHIFT;
end
end
TX_SHIFT: begin
// clear interrupt request, active by 1 cycle of clk
tx_irq <= #1 1'b0;
// count bit period
if (tx_cnt == 16'd0) begin
// check if any bit left to send out
if (tx_shift == 16'd0) begin
// set TSRE flag when serdat register is empty
if (tx_tbe) tx_tsre <= #1 1'b1;
// data sent, go to idle state
tx_state <= #1 TX_IDLE;
end else begin
// reload period counter
tx_cnt <= #1 {serper[14:0], 1'b1};
// update shift register and txd pin
tx_shift <= #1 {1'b0, tx_shift[15:1]};
tx_txd <= #1 tx_shift[0];
end
end else begin
// decrement period counter
tx_cnt <= #1 tx_cnt - 16'd1;
end
end
default: begin
// force idle state
tx_state <= #1 TX_IDLE;
end
endcase
// force break char when requested
if (uartbrk) tx_txd <= #1 1'b0;
// handle tbe bit
//if (rga_i == REG_SERDAT[8:1]) tx_tbe <= #1 1'b0;
tx_tbe <= #1 (rga_i == REG_SERDAT[8:1]) ? 1'b0 : ((tx_state == TX_IDLE) ? 1'b1 : tx_tbe);
end
end
end
//// RX ////
localparam [ 2-1:0] RX_IDLE=2'd0, RX_START=2'd1, RX_SHIFT=2'd2;
reg [ 2-1:0] rx_state;
reg [ 16-1:0] rx_cnt;
reg [ 10-1:0] rx_shift;
reg [ 10-1:0] rx_data;
reg rx_rbf;
reg rx_rxd;
reg rx_irq;
reg rx_ovrun;
always @ (posedge clk) begin
if (clk7_en) begin
if (reset) begin
rx_state <= #1 RX_IDLE;
rx_rbf <= #1 1'b0;
rx_rxd <= #1 1'b1;
rx_irq <= #1 1'b0;
rx_ovrun <= #1 1'b0;
end else begin
case (rx_state)
RX_IDLE : begin
// clear interrupt request
rx_irq <= #1 1'b0;
// wait for start condition
if (rx_rxd && !rxds) begin
// setup received data format
rx_shift <= #1 {serper[LONG_BIT], {9{1'b1}}};
rx_cnt <= #1 {1'b0, serper[14:0]};
// wait for a sampling point of a start bit
rx_state <= #1 RX_START;
end
end
RX_START : begin
// wait for a sampling point
if (rx_cnt == 16'h0) begin
// sample rxd signal
if (!rxds) begin
// start bit valid, start data shifting
rx_shift <= #1 {rxds, rx_shift[9:1]};
// restart period counter
rx_cnt <= #1 {serper[14:0], 1'b1};
// start data bits sampling
rx_state <= #1 RX_SHIFT;
end else begin
// start bit invalid, return into idle state
rx_state <= #1 RX_IDLE;
end
end else begin
rx_cnt <= #1 rx_cnt - 16'd1;
end
// check false start condition
if (!rx_rxd && rxds) begin
rx_state <= #1 RX_IDLE;
end
end
RX_SHIFT : begin
// wait for bit period
if (rx_cnt == 16'h0) begin
// store received bit
rx_shift <= #1 {rxds, rx_shift[9:1]};
// restart period counter
rx_cnt <= #1 {serper[14:0], 1'b1};
// check for all bits received
if (rx_shift[0] == 1'b0) begin
// set interrupt request flag
rx_irq <= #1 1'b1;
// handle OVRUN bit
//rx_ovrun <= #1 rbfmirror;
// update receive buffer
rx_data[9] <= #1 rxds;
if (serper[LONG_BIT]) begin
rx_data[8:0] <= #1 rx_shift[9:1];
end else begin
rx_data[8:0] <= #1 {rxds, rx_shift[9:2]};
end
// go to idle state
rx_state <= #1 RX_IDLE;
end
end else begin
rx_cnt <= #1 rx_cnt - 16'd1;
end
end
default : begin
// force idle state
rx_state <= #1 RX_IDLE;
end
endcase
// register rxds
rx_rxd <= #1 rxds;
// handle ovrun bit
rx_rbf <= #1 rbfmirror;
//if (!rbfmirror && rx_rbf) rx_ovrun <= #1 1'b0;
rx_ovrun <= #1 (!rbfmirror && rx_rbf) ? 1'b0 : (((rx_state == RX_SHIFT) && ~|rx_cnt && !rx_shift[0]) ? rbfmirror : rx_ovrun);
end
end
end
//// outputs ////
// SERDATR
wire [ 5-1:0] serdatr;
assign serdatr = {rx_ovrun, rx_rbf, tx_tbe, tx_tsre, rx_rxd};
// interrupts
assign txint = tx_irq;
assign rxint = rx_irq;
// uart output
assign txd = tx_txd;
// reg bus output
assign data_o = (rga_i == REG_SERDATR[8:1]) ? {serdatr, 1'b0, rx_data} : 16'h0000;
endmodule
|
#include <bits/stdc++.h> using namespace std; using namespace std; int main() { long long int k, b, n, t; while (cin >> k >> b >> n >> t) { long long int s = 1; long long int cas = 0; while (s <= t && cas < n) { s = s * k + b; cas++; } if (cas == n && s <= t) cout << 0 << endl; else cout << n - cas + 1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 rnd(chrono::high_resolution_clock::now().time_since_epoch().count()); int main() { ios::sync_with_stdio(0); cin.tie(0); map<string, vector<int> > mda; int n, k; cin >> n >> k; for (int i = 0; i < n; i++) { string s; cin >> s; int cost; cin >> cost; mda[s].push_back(cost); } for (auto &c : mda) { sort(c.second.rbegin(), c.second.rend()); } long long ans = 0; long long odd = 0; for (auto &c : mda) { string t = c.first; reverse(t.begin(), t.end()); if (t < c.first) { long long best = 0; long long s = 0; for (int i = 0; i < (int)c.second.size() && i < mda[t].size(); i++) { s += c.second[i]; s += mda[t][i]; best = max(best, s); } ans += best; } else if (t == c.first) { long long s = 0; int mda = 0; long long last = 0; long long fir = -1e18; for (int i = 0; i < (int)c.second.size(); i++) { if (c.second[i] > 0) { last = c.second[i]; s += c.second[i]; mda++; } else { fir = c.second[i]; break; } } if (mda % 2 == 0) { ans += s; } else { long long me = max(s - last, s + fir); long long delta_odd = s - me; ans += me; odd = max(odd, delta_odd); } } } cout << ans + odd << endl; } |
#include <bits/stdc++.h> using namespace std; long long n, ans = 0; long long f[1000001]; int main(int argc, char **argv) { cin >> n; for (int i = 1; i <= n; i++) { long long b; cin >> b; f[b - i + 400000] += b; ans = max(ans, f[b - i + 400000]); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000005; using ll = long long; int n, m, p, a[N]; struct TNode { int l, r; vector<ll> f; ll sum; } t[N << 2]; inline int lc(int pos) { return pos << 1; } inline int rc(int pos) { return pos << 1 | 1; } void pushup(int pos) { t[pos].sum = t[lc(pos)].sum + t[rc(pos)].sum; int ptr = 0; for (int i = 1; i <= t[pos].r - t[pos].l + 1; i++) t[pos].f[i] = (LLONG_MAX >> 2); for (int i = 0; i <= t[lc(pos)].r - t[lc(pos)].l + 1; i++) { if (ptr > t[rc(pos)].r - t[rc(pos)].l + 1) --ptr; while (ptr <= t[rc(pos)].r - t[rc(pos)].l + 1) { ll ret = t[rc(pos)].f[ptr] - (t[lc(pos)].sum - i * 1ll * p); ll val = t[lc(pos)].f[i + 1] - 1 + (t[lc(pos)].sum - i * 1ll * p); if (val < t[rc(pos)].f[ptr]) { if (ptr > 0) --ptr; break; } t[pos].f[i + ptr] = min(t[pos].f[i + ptr], max(t[lc(pos)].f[i], ret)); ++ptr; } } } void build(int pos, int l, int r) { t[pos].l = l; t[pos].r = r; t[pos].f.resize(r - l + 1 + 1); t[pos].f[0] = LLONG_MIN >> 2; t[pos].f.push_back(LLONG_MAX >> 2); if (l == r) { t[pos].sum = a[l]; t[pos].f[1] = p - a[l]; return; } int mid = (l + r) >> 1; build(lc(pos), l, mid); build(rc(pos), mid + 1, r); pushup(pos); } ll query(int pos, int l, int r, ll cur = 0) { if (t[pos].l == l && t[pos].r == r) { assert(cur < LLONG_MAX / 4); ll pp = upper_bound(t[pos].f.begin(), t[pos].f.end(), cur) - t[pos].f.begin() - 1; return cur + t[pos].sum - p * pp; } int mid = (t[pos].l + t[pos].r) >> 1; if (r <= mid) return query(lc(pos), l, r, cur); else if (l > mid) return query(rc(pos), l, r, cur); else return query(rc(pos), mid + 1, r, query(lc(pos), l, mid, cur)); } int main() { ios::sync_with_stdio(false); cin >> n >> m >> p; for (int i = 1; i <= n; i++) cin >> a[i]; build(1, 1, n); while (m--) { int l, r; cin >> l >> r; cout << query(1, l, r) << endl; } return 0; } |
module test
(output reg [4:0] q,
input wire [31:0] sel
/* */);
always @* begin
casez (sel)
32'b1zzz_zzzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd0;
32'b01zz_zzzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd1;
32'b001z_zzzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd2;
32'b0001_zzzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd3;
32'b0000_1zzz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd4;
32'b0000_01zz_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd5;
32'b0000_001z_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd6;
32'b0000_0001_zzzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd7;
32'b0000_0000_1zzz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd8;
32'b0000_0000_01zz_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd9;
32'b0000_0000_001z_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd10;
32'b0000_0000_0001_zzzz__zzzz_zzzz_zzzz_zzzz: q = 5'd11;
32'b0000_0000_0000_1zzz__zzzz_zzzz_zzzz_zzzz: q = 5'd12;
32'b0000_0000_0000_01zz__zzzz_zzzz_zzzz_zzzz: q = 5'd13;
32'b0000_0000_0000_001z__zzzz_zzzz_zzzz_zzzz: q = 5'd14;
32'b0000_0000_0000_0001__zzzz_zzzz_zzzz_zzzz: q = 5'd15;
32'b0000_0000_0000_0000__1zzz_zzzz_zzzz_zzzz: q = 5'd16;
32'b0000_0000_0000_0000__01zz_zzzz_zzzz_zzzz: q = 5'd17;
32'b0000_0000_0000_0000__001z_zzzz_zzzz_zzzz: q = 5'd18;
32'b0000_0000_0000_0000__0001_zzzz_zzzz_zzzz: q = 5'd19;
32'b0000_0000_0000_0000__0000_1zzz_zzzz_zzzz: q = 5'd20;
32'b0000_0000_0000_0000__0000_01zz_zzzz_zzzz: q = 5'd21;
32'b0000_0000_0000_0000__0000_001z_zzzz_zzzz: q = 5'd22;
32'b0000_0000_0000_0000__0000_0001_zzzz_zzzz: q = 5'd23;
32'b0000_0000_0000_0000__0000_0000_1zzz_zzzz: q = 5'd24;
32'b0000_0000_0000_0000__0000_0000_01zz_zzzz: q = 5'd25;
32'b0000_0000_0000_0000__0000_0000_001z_zzzz: q = 5'd26;
32'b0000_0000_0000_0000__0000_0000_0001_zzzz: q = 5'd27;
32'b0000_0000_0000_0000__0000_0000_0000_1zzz: q = 5'd28;
32'b0000_0000_0000_0000__0000_0000_0000_01zz: q = 5'd29;
32'b0000_0000_0000_0000__0000_0000_0000_001z: q = 5'd30;
32'b0000_0000_0000_0000__0000_0000_0000_0001: q = 5'd31;
default: q = 5'd0;
endcase
end // always @ *
endmodule // test
module main;
reg [31:0] sel;
wire [4:0] q;
test dut (.q(q), .sel(sel));
integer idx;
integer rept;
reg [31:0] mask, setb;
initial begin
sel = 0;
#1 if (q !== 5'd0) begin
$display("FAILED -- sel=%b, q=%b", sel, q);
$finish;
end
for (idx = 0 ; idx < 32 ; idx = idx+1) begin
mask = 32'h7fff_ffff >> idx;
setb = mask + 32'd1;
for (rept = 0 ; rept < 4 ; rept = rept+1) begin
sel = setb | (mask & $random);
#1 if (q !== idx[4:0]) begin
$display("FAILED -- sel=%b, q=%b, idx=%0d", sel, q, idx);
$finish;
end
end
end
$display("PASSED");
end
endmodule
|
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_buttons, input_switches, input_eth_rx, input_ps2, input_timer_stb, input_rs232_rx_stb, input_buttons_stb, input_switches_stb, input_eth_rx_stb, input_ps2_stb, input_timer_ack, input_rs232_rx_ack, input_buttons_ack, input_switches_ack, input_eth_rx_ack, input_ps2_ack, output_eth_tx, output_rs232_tx, output_leds, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
wire exception_140292293449776;
wire exception_140292292520776;
wire exception_140292291707392;
wire exception_140292291794560;
wire exception_140292291718680;
wire exception_140292290886400;
wire exception_140292291068416;
main_0 main_0_140292293449776(
.clk(clk),
.rst(rst),
.exception(exception_140292293449776),
.input_eth_in(input_eth_rx),
.input_eth_in_stb(input_eth_rx_stb),
.input_eth_in_ack(input_eth_rx_ack),
.output_rs232_out(output_rs232_tx),
.output_rs232_out_stb(output_rs232_tx_stb),
.output_rs232_out_ack(output_rs232_tx_ack),
.output_eth_out(output_eth_tx),
.output_eth_out_stb(output_eth_tx_stb),
.output_eth_out_ack(output_eth_tx_ack));
main_1 main_1_140292292520776(
.clk(clk),
.rst(rst),
.exception(exception_140292292520776),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_140292291707392(
.clk(clk),
.rst(rst),
.exception(exception_140292291707392),
.input_in(input_rs232_rx),
.input_in_stb(input_rs232_rx_stb),
.input_in_ack(input_rs232_rx_ack));
main_3 main_3_140292291794560(
.clk(clk),
.rst(rst),
.exception(exception_140292291794560),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_4 main_4_140292291718680(
.clk(clk),
.rst(rst),
.exception(exception_140292291718680),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_5 main_5_140292290886400(
.clk(clk),
.rst(rst),
.exception(exception_140292290886400),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_6 main_6_140292291068416(
.clk(clk),
.rst(rst),
.exception(exception_140292291068416),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
assign exception = exception_140292293449776 || exception_140292292520776 || exception_140292291707392 || exception_140292291794560 || exception_140292291718680 || exception_140292290886400 || exception_140292291068416;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_PP_SYMBOL_V
`define SKY130_FD_SC_LP__CLKBUF_PP_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_PP_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : cmm_errman_nfl.v
//--------------------------------------------------------------------------------
//--------------------------------------------------------------------------------
/***********************************************************************
Description:
This module figures out what to do for non-fatal errors:
1) count up or count down,
2) how much to add or to subtract.
It returns the number and a add/subtract_b signals to the error
tracking counter. The outputs are based on how many errors are
asserted by the error reporting modules.
***********************************************************************/
module cmm_errman_nfl (
nfl_num, // Output
inc_dec_b,
cfg_err_cpl_timeout_n,
decr_nfl,
rst,
clk
);
output nfl_num;
output inc_dec_b; // 1 = increment, 0 = decrement
input cfg_err_cpl_timeout_n;
input decr_nfl;
input rst;
input clk;
//******************************************************************//
// Reality check. //
//******************************************************************//
parameter FFD = 1; // clock to out delay model
//******************************************************************//
// Figure out how many errors to increment. //
//******************************************************************//
reg to_incr;
reg add_sub_b;
always @(cfg_err_cpl_timeout_n or decr_nfl) begin
case ({cfg_err_cpl_timeout_n, decr_nfl}) // synthesis full_case parallel_case
2'b10: begin to_incr = 1'b0;
add_sub_b = 1'b1;
end
2'b11: begin to_incr = 1'b1;
add_sub_b = 1'b0;
end
2'b00: begin to_incr = 1'b1;
add_sub_b = 1'b1;
end
2'b01: begin to_incr = 1'b0;
add_sub_b = 1'b1;
end
default: begin to_incr = 1'b0;
add_sub_b = 1'b1;
end
endcase
end
//******************************************************************//
// Register the outputs. //
//******************************************************************//
reg reg_nfl_num;
reg reg_inc_dec_b;
always @(posedge clk or posedge rst)
begin
if (rst)
begin
reg_nfl_num <= #FFD 1'b0;
reg_inc_dec_b <= #FFD 1'b0;
end
else
begin
reg_nfl_num <= #FFD to_incr;
reg_inc_dec_b <= #FFD add_sub_b;
end
end
assign nfl_num = reg_nfl_num;
assign inc_dec_b = reg_inc_dec_b;
//******************************************************************//
// //
//******************************************************************//
endmodule
|
// bsg_fifo_1r1w_large_banked
//
// MB 7/6/2016
//
// Not tested.
//
// 1R1W large fifo implementation using two banks
//
// This implementation is specifically
// intended for processes where 1RW rams
// are cheaper than 1R1W rams, like
// most ASIC processes. Versus 1r1w_large
// which employs a double width ram, this
// module implies two rams. For certain
// configurations, it will use less area.
//
// The FIFO is implemented by instantiating
// two banks.
// Each bank has a large 1-port
// fifo and a small 2-element fifo.
//
// Data is inserted directly into the 2-element fifo until
// that fifo is full. Then it is stored in
// the 1 port ram. When data is not enqued into the big fifo,
// and there is sufficient space in the small fifo
// then data is transferred from the big fifo to the small fifo.
//
// Banks are read and written in round robin fashion.
// This means that every other cycle, there is a slot
// to transfer from the big fifo to the little fifo
// if there is sufficient space in the little fifo.
//
// __________
// ___/ 1RW FIFO \___|\ _______
// / \__________/ __| |__/ 2 fifo\ ___
// /---------\ _/________________/ |/ \_______/ \| N \
// | 1-to-N |__________________ | to |___
// \---------/ \ __________ \__|\ _______ | 1 |
// \___/ 1RW FIFO \___| |__/ 2 fifo\_/|___/
// \__________/ | | \_______/
// |/
//
// We can prove that one element small
// fifo is insufficient.
//
// suppose that the small fifo #0,#1 is full.
// and that big fifo #0 is non-empty
// cycle one: no deque from small fifo
//
// cycle two: data is dequed from small fifo #0
// big fifo is deq because small fifo deq is too late
// cycle three: data is enqued into big fifo #0
// no deq from big fifo #0 is possible
// small fifo #0 is empty
// data deque from small fifo #1
//
// cycle four: no data avail in small fifo #0
//
// mbt: note bsg_fifo_two_port_bank code moved to bsg_fifo_1r1w_pseudo_large
`include "bsg_defines.v"
module bsg_fifo_1r1w_large_banked #(parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
)
(input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
, output ready_o
, output v_o
, output [width_p-1:0] data_o
, input yumi_i
);
initial assert ((els_p & 1) == 0) else
$error("odd number of elements for two port fifo not handled.");
genvar i;
wire [1:0] v_i_demux, ready_o_mux;
bsg_round_robin_1_to_n #(.width_p(width_p)
,.num_out_p(2)
) rr1n
(.clk_i (clk_i )
,.reset_i(reset_i )
,.valid_i(v_i )
,.ready_o(ready_o )
,.valid_o(v_i_demux )
,.ready_i(ready_o_mux)
);
wire [1:0] v_int, yumi_int;
wire [width_p-1:0] [1:0] data_int;
for (i = 0; i < 2; i++)
begin
//
// this module is responsible for handling one bank
// of the 1R1W FIFO.
//
// we exploit the property of the bsg_fifo_1r1w_pseudo_large fifo
// that it will never read-stall on us if we have a conflict run
// of 1 element and write data every other cycle.
//
bsg_fifo_1r1w_pseudo_large #(.width(width_p)
,.els_p(els_p >> 1)
,.early_yumi_p(1)
// ,.max_conflict_run_p (1)
) bank
(.clk_i (clk_i)
,.reset_i(reset_i)
,.v_i(v_i_demux [i])
,.data_i (data_i )
,.ready_o(ready_o_mux[i])
,.v_o (v_int [i])
,.data_o (data_int[i])
,.yumi_i (yumi_int[i])
);
end
bsg_round_robin_n_to_1 #(.width(width_p)
,.num_in_p(2)
) round_robin_n_to_1
(.clk_i (clk_i )
,.reset_i(reset_i )
,.data_i (data_int )
,.valid_i(valid_int)
,.yumi_o (yumi_int )
,.data_o (data_o )
,.valid_o(valid_o )
,.yumi_i (yumi_i )
);
endmodule // bsg_fifo_1r1w_large_banked
`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_large_banked)
|
#include <bits/stdc++.h> using namespace std; const int V = 25; int n, k, sx, sy; bool adj[V][V]; double p[V]; double mat[V * V][V * V]; int id[V][V], deg[V]; double calc_p(int i, int j) { return (i == j) ? p[i] : (adj[i][j]) ? (1 - p[i]) / deg[i] : 0.0; } void gauss(double a[][V * V], int m, int n) { for (int i = 0; i < m; i++) { int u = i; for (int r = i + 1; r < m; r++) if (fabs(a[r][i]) > fabs(a[u][i])) u = r; if (u != i) for (int j = i; j < m + n; j++) swap(a[i][j], a[u][j]); double t = a[i][i]; for (int j = i; j < m + n; j++) a[i][j] /= t; for (int c = 0; c < m; c++) if (c != i) { t = a[c][i]; for (int j = i; j < m + n; j++) a[c][j] -= t * a[i][j]; } } } int main() { int a, b; scanf( %d%d%d%d , &n, &k, &sx, &sy); sx--; sy--; memset(deg, 0, sizeof(deg)); memset(adj, 0, sizeof(adj)); for (int i = 0; i < k; i++) { scanf( %d%d , &a, &b); a--; b--; adj[a][b] = adj[b][a] = true; deg[a]++; deg[b]++; } int m = 0; for (int i = 0; i < n; i++) for (int j = i; j < n; j++) id[i][j] = id[j][i] = m++; for (int i = 0; i < n; i++) scanf( %lf , &p[i]); memset(mat, 0, sizeof(mat)); for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) { for (int x = 0; x < n; x++) for (int y = 0; y < n; y++) { mat[id[i][j]][id[x][y]] += calc_p(i, x) * calc_p(j, y); } } for (int i = 0; i < m; i++) mat[i][i] -= 1; for (int i = 0; i < n; i++) mat[id[i][i]][id[i][i]] = 1; for (int i = 0; i < n; i++) mat[id[i][i]][m + i] = 1; gauss(mat, m, n); for (int i = 0; i < n; i++) { if (i) printf( ); printf( %.9f , mat[id[sx][sy]][m + i]); } printf( n ); } |
`timescale 1 ns / 1 ps
module axis_ram_writer #
(
parameter integer ADDR_WIDTH = 20,
parameter integer AXI_ID_WIDTH = 6,
parameter integer AXI_ADDR_WIDTH = 32,
parameter integer AXI_DATA_WIDTH = 64,
parameter integer AXIS_TDATA_WIDTH = 64
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [AXI_ADDR_WIDTH-1:0] cfg_data,
output wire [ADDR_WIDTH-1:0] sts_data,
// Master side
output wire [AXI_ID_WIDTH-1:0] m_axi_awid, // AXI master: Write address ID
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr, // AXI master: Write address
output wire [3:0] m_axi_awlen, // AXI master: Write burst length
output wire [2:0] m_axi_awsize, // AXI master: Write burst size
output wire [1:0] m_axi_awburst, // AXI master: Write burst type
output wire [3:0] m_axi_awcache, // AXI master: Write memory type
output wire m_axi_awvalid, // AXI master: Write address valid
input wire m_axi_awready, // AXI master: Write address ready
output wire [AXI_ID_WIDTH-1:0] m_axi_wid, // AXI master: Write data ID
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata, // AXI master: Write data
output wire [AXI_DATA_WIDTH/8-1:0] m_axi_wstrb, // AXI master: Write strobes
output wire m_axi_wlast, // AXI master: Write last
output wire m_axi_wvalid, // AXI master: Write valid
input wire m_axi_wready, // AXI master: Write ready
input wire m_axi_bvalid, // AXI master: Write response valid
output wire m_axi_bready, // AXI master: Write response ready
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid
);
function integer clogb2 (input integer value);
for(clogb2 = 0; value > 0; clogb2 = clogb2 + 1) value = value >> 1;
endfunction
localparam integer ADDR_SIZE = clogb2((AXI_DATA_WIDTH/8)-1);
reg int_awvalid_reg, int_awvalid_next;
reg int_wvalid_reg, int_wvalid_next;
reg [ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg [AXI_ID_WIDTH-1:0] int_wid_reg, int_wid_next;
wire int_full_wire, int_empty_wire, int_rden_wire;
wire int_wlast_wire, int_tready_wire;
wire [71:0] int_wdata_wire;
assign int_tready_wire = ~int_full_wire;
assign int_wlast_wire = &int_addr_reg[3:0];
assign int_rden_wire = m_axi_wready & int_wvalid_reg;
FIFO36E1 #(
.FIRST_WORD_FALL_THROUGH("TRUE"),
.ALMOST_EMPTY_OFFSET(13'hf),
.DATA_WIDTH(72),
.FIFO_MODE("FIFO36_72")
) fifo_0 (
.FULL(int_full_wire),
.ALMOSTEMPTY(int_empty_wire),
.RST(~aresetn),
.WRCLK(aclk),
.WREN(int_tready_wire & s_axis_tvalid),
.DI({{(72-AXIS_TDATA_WIDTH){1'b0}}, s_axis_tdata}),
.RDCLK(aclk),
.RDEN(int_rden_wire),
.DO(int_wdata_wire)
);
always @(posedge aclk)
begin
if(~aresetn)
begin
int_awvalid_reg <= 1'b0;
int_wvalid_reg <= 1'b0;
int_addr_reg <= {(ADDR_WIDTH){1'b0}};
int_wid_reg <= {(AXI_ID_WIDTH){1'b0}};
end
else
begin
int_awvalid_reg <= int_awvalid_next;
int_wvalid_reg <= int_wvalid_next;
int_addr_reg <= int_addr_next;
int_wid_reg <= int_wid_next;
end
end
always @*
begin
int_awvalid_next = int_awvalid_reg;
int_wvalid_next = int_wvalid_reg;
int_addr_next = int_addr_reg;
int_wid_next = int_wid_reg;
if(~int_empty_wire & ~int_awvalid_reg & ~int_wvalid_reg)
begin
int_awvalid_next = 1'b1;
int_wvalid_next = 1'b1;
end
if(m_axi_awready & int_awvalid_reg)
begin
int_awvalid_next = 1'b0;
end
if(int_rden_wire)
begin
int_addr_next = int_addr_reg + 1'b1;
end
if(m_axi_wready & int_wlast_wire)
begin
int_wid_next = int_wid_reg + 1'b1;
if(int_empty_wire)
begin
int_wvalid_next = 1'b0;
end
else
begin
int_awvalid_next = 1'b1;
end
end
end
assign sts_data = int_addr_reg;
assign m_axi_awid = int_wid_reg;
assign m_axi_awaddr = cfg_data + {int_addr_reg, {(ADDR_SIZE){1'b0}}};
assign m_axi_awlen = 4'd15;
assign m_axi_awsize = ADDR_SIZE;
assign m_axi_awburst = 2'b01;
assign m_axi_awcache = 4'b0011;
assign m_axi_awvalid = int_awvalid_reg;
assign m_axi_wid = int_wid_reg;
assign m_axi_wdata = int_wdata_wire[AXI_DATA_WIDTH-1:0];
assign m_axi_wstrb = {(AXI_DATA_WIDTH/8){1'b1}};
assign m_axi_wlast = int_wlast_wire;
assign m_axi_wvalid = int_wvalid_reg;
assign m_axi_bready = 1'b1;
assign s_axis_tready = int_tready_wire;
endmodule
|
#include <bits/stdc++.h> using namespace std; int fa[5010], ba[5010], b[5010]; int main() { ios_base::sync_with_stdio(0); int i, j, k, l, n, m, t, tt, x = 0, y; string s, second; cin >> s; n = s.length(); fa[0] = 0; ba[n + 1] = 0; b[0] = 0; for (j = 1; j <= n; j++) { fa[j] = fa[j - 1]; b[j] = b[j - 1]; if (s[j - 1] == a ) fa[j] = fa[j] + 1; else b[j] = b[j] + 1; } if (fa[n] == n) { cout << n << n ; return 0; } for (j = n; j > 0; j--) { ba[j] = ba[j + 1]; if (s[j - 1] == a ) ba[j] = ba[j] + 1; } int mx = 0; for (i = 1; i <= n; i++) { for (j = i; j <= n; j++) { mx = max(fa[i - 1] + b[j] - b[i - 1] + ba[j + 1], mx); } } cout << mx; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int dp[2][20005]; inline void add(int &x, int y) { x += y; if (x >= mod) x -= mod; } int main() { int n; scanf( %d , &n); int ans = 0, now = 0; for (int _i = 1; _i <= n; ++_i) { memset(dp[now], 0, sizeof dp[now]); int x; scanf( %d , &x); add(ans, dp[now ^ 1][x + 10000]), add(ans, dp[now ^ 1][-x + 10000]); dp[now][x + 10000] = dp[now][-x + 10000] = 1; for (int i = x + 1; i <= 20000 - x; ++i) { if (dp[now ^ 1][i]) { add(dp[now][i + x], dp[now ^ 1][i]); add(dp[now][i - x], dp[now ^ 1][i]); } } now ^= 1; } printf( %d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLXTN_TB_V
`define SKY130_FD_SC_HDLL__DLXTN_TB_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlxtn.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_hdll__dlxtn dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLXTN_TB_V
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 100010; const int INF = 1000000; int n; stack<int> killers; int main() { cin >> n; int values[n + 1], life[n + 1]; for (int i = 1; i <= n; ++i) { cin >> values[i]; } life[0] = INF; values[0] = 0; killers.push(0); for (int i = 1; i <= n; ++i) { life[i] = 1; while (killers.size() && values[i] > values[killers.top()]) { life[i] = max(life[i], life[killers.top()] + 1); killers.pop(); } killers.push(i); } int sol = 0; for (int i = 1; i <= n; ++i) { if (life[i] < INF) { sol = max(sol, life[i]); } } cout << sol << endl; return 0; } |
#include <bits/stdc++.h> int a, b, c; long long int MOD; long long int Comb[110][110]; long long int comb(int a, int b) { if (a == b) return 1; if (b == 0) return 1; if (Comb[a][b] != -1) return Comb[a][b]; return Comb[a][b] = (comb(a - 1, b - 1) + comb(a - 1, b)) % MOD; } int check[110][110]; std::vector<long long int> ans[110][110]; void func(int k, int h) { if (check[k][h]) return; if (k == 0) { ans[k][h].push_back(1 % MOD); check[k][h] = 1; return; } int start = 0; if (h == b) start++; for (int i = 0; i <= k - 1; i++) { func(i, h + 1); func(k - i - 1, h + 1); while (ans[k][h].size() <= start + ans[i][h + 1].size() + ans[k - i - 1][h + 1].size() - 2) ans[k][h].push_back(0); for (int j1 = 0; j1 < ans[i][h + 1].size(); j1++) { for (int j2 = 0; j2 < ans[k - i - 1][h + 1].size(); j2++) { long long int t = ans[i][h + 1][j1] * ans[k - i - 1][h + 1][j2]; t %= MOD; t *= comb(k - 1, i), t %= MOD; ans[k][h][start + j1 + j2] += t, ans[k][h][start + j1 + j2] %= MOD; } } } check[k][h] = 1; } int main() { scanf( %d%d%d%lld , &a, &b, &c, &MOD); for (int i = 0; i <= a; i++) for (int j = 0; j <= a; j++) Comb[i][j] = -1; func(a, 1); if (ans[a][1].size() >= c + 1) printf( %lld , ans[a][1][c] % MOD); else printf( 0 ); } |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: thesis_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module thesis_new (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites-new/thesis_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites-new/thesis_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL thesis_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL thesis_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL thesis_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL thesis_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL thesis_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL thesis_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n, s; cin >> n >> s; long long cnt = 0, x = n; while (x) { cnt += x % 10; x /= 10; } long long ans = 0, now = 1; while (1) { if (cnt <= s) { cout << ans << endl; break; } long long p = n % 10; if (!p) p = 10; ans += (10 - p) * now; n += 10 - p; n /= 10; x = n; cnt = 0; while (x) { cnt += x % 10; x /= 10; } now *= 10; } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int skip_classes[501][501], dp[501][501], N, M, K; vector<int> timings[501]; vector<string> grid(501); void preprocess() { for (long long int i = 1; i <= N; i++) { int total_classes_on_day_i = timings[i].size(); for (int skip = 0; skip <= K; skip++) { skip_classes[i][skip] = INT_MAX; int to_attend = total_classes_on_day_i - skip; if (to_attend <= 0) skip_classes[i][skip] = 0; else for (int j = to_attend - 1; j < timings[i].size(); j++) { skip_classes[i][skip] = (skip_classes[i][skip] <= timings[i][j] - timings[i][j - to_attend + 1] + 1 ? skip_classes[i][skip] : timings[i][j] - timings[i][j - to_attend + 1] + 1); } } } return; } long long int solve_for(long long int day, long long int can_skip) { if (can_skip < 0) return INT_MAX; if (day == 0) return 0; if (dp[day][can_skip] != -1) return dp[day][can_skip]; long long int ans = INT_MAX, current_ans; for (long long int i = 0; i <= can_skip; i++) { current_ans = solve_for(day - 1, can_skip - i) + skip_classes[day][i]; ans = (ans <= current_ans ? ans : current_ans); } return dp[day][can_skip] = ans; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); memset(dp, -1, sizeof dp); cin >> N >> M >> K; for (long long int i = 1; i <= N; i++) { cin >> grid[i]; for (int j = 0; j < grid[i].size(); j++) { if (grid[i][j] == 1 ) timings[i].push_back(j + 1); } } preprocess(); long long int ans = solve_for(N, K); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int dx[] = {1, -1, 0, 0}; int dy[] = {0, 0, 1, -1}; int dddx[] = {1, -1, 0, 0, 1, 1, -1, -1}; int dddy[] = {0, 0, 1, -1, 1, -1, 1, -1}; int t; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> t; while (t--) { int n; cin >> n; vector<int> vec; for (int i = 0; i < n; i++) { int a; cin >> a; vec.push_back(a); } bool at = false; for (int i = 0; i < int(vec.size()); i++) { for (int j = i + 2; j < int(vec.size()); j++) { if (vec[j] == vec[i]) at = true; } } if (!at) cout << NO << n ; else cout << YES << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; inline int upd(int& a, int b) { return a = min(a, b); } inline int _abs(int x) { return x > 0 ? x : -x; } char c; int n, cnt[3], type[80]; int pos[3][80], leq[3][80]; int dp[80][80][80][80]; void getpos(void) { for (int p = 0; p <= 2; p++) { cnt[p] = 0; for (int y = 1; y <= n; y++) { while (y <= n && type[y] != p) y++; if (y <= n) pos[p][++cnt[p]] = y; } leq[p][0] = 0; for (int i = 1; i <= n; i++) leq[p][i] = leq[p][i - 1] + (type[i] == p); } return; } void trans(int i, int j, int k, int lst) { int p0 = pos[0][i], p1 = pos[1][j], p2 = pos[2][k]; if (i > 0) upd(dp[0][i][j][k], dp[lst][i - 1][j][k] + _abs(j - leq[1][p0]) + _abs(k - leq[2][p0])); if (j > 0) upd(dp[1][i][j][k], dp[lst][i][j - 1][k] + _abs(i - leq[0][p1]) + _abs(k - leq[2][p1])); if (k > 0 && lst != 1) upd(dp[2][i][j][k], dp[lst][i][j][k - 1] + _abs(i - leq[0][p2]) + _abs(j - leq[1][p2])); return; } int main(void) { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %c , &c); type[i] = (c == V ? 1 : (c == K ? 2 : 0)); } getpos(); memset(dp, 0x1f, sizeof(dp)); dp[0][0][0][0] = 0; for (int i = 0; i <= cnt[0]; i++) for (int j = 0; j <= cnt[1]; j++) for (int k = 0; k <= cnt[2]; k++) for (int lst = 0; lst <= 2; lst++) trans(i, j, k, lst); int ans = n * n; for (int i = 0; i <= 2; i++) upd(ans, dp[i][cnt[0]][cnt[1]][cnt[2]]); printf( %d n , ans >> 1); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 41; const int mod = 1e9 + 7; const long long INF = 1e18; const int inf = 2e9; vector<int> g[N]; long long res; int cnt[2]; int a[N]; int sz[N]; bool used[N]; int cur_sz; long long cur; void pre(int v = 1, int p = -1) { sz[v] = 1; for (int to : g[v]) if (to != p && !used[to]) { pre(to, v); sz[v] += sz[to]; } } int f(int v, int p = -1) { for (int to : g[v]) if (!used[to] && to != p && sz[to] * 2 > cur_sz) { return f(to, v); } return v; } bool kth(int val, int bit) { if (val & (1 << bit)) return true; else return false; } void addcur(int v, int p, int bit, bool pref = 0) { pref ^= kth(a[v], bit); cur += cnt[pref ^ 1]; for (int to : g[v]) if (!used[to] && to != p) { addcur(to, v, bit, pref); } } void addcnt(int v, int p, int bit, bool pref = 0) { pref ^= kth(a[v], bit); cnt[pref]++; for (int to : g[v]) if (!used[to] && to != p) { addcnt(to, v, bit, pref); } } void dfs(int v = 1) { pre(v); cur_sz = sz[v]; v = f(v); for (int bit = 0; bit < 20; ++bit) { cur = 0; cnt[1] = 0, cnt[0] = 1; for (int to : g[v]) if (!used[to]) { bool st = kth(a[v], bit); addcur(to, v, bit, st); addcnt(to, v, bit); } res += (1ll << bit) * 1ll * cur; } used[v] = 1; for (int to : g[v]) if (!used[to]) { dfs(to); } } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; int n; cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; res += a[i]; } for (int i = 1; i < n; ++i) { int a, b; cin >> a >> b; g[a].push_back(b); g[b].push_back(a); } dfs(); cout << res; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const int inf = 1 << 30; int n, qn, tot = 0, head[N], col[N], nowHead[N], deg[N], seq[N]; int dfsc = 0, id[N], siz[N], fa[N], son[N], dep[N], top[N]; bool vis[N]; struct Edge { int to, nxt; } e[N << 1]; inline void add(int from, int to) { e[++tot].to = to; e[tot].nxt = head[from]; head[from] = tot; } struct Seg { int l, r, c; inline Seg(int L = 0, int R = 0, int C = 0) { l = L, r = R, c = C; } friend bool operator<(const Seg x, const Seg y) { return x.l < y.l; } }; set<Seg> seg[N]; template <typename T> inline void read(T &X) { X = 0; char ch = 0; T op = 1; for (; ch > 9 || ch < 0 ; ch = getchar()) if (ch == - ) op = -1; for (; ch >= 0 && ch <= 9 ; ch = getchar()) X = (X << 3) + (X << 1) + ch - 48; X *= op; } namespace Bit { int s[N << 1]; inline void modify(int p, int v) { if (!p) return; for (; p < (N << 1); p += (p & (-p))) s[p] += v; } inline int query(int p) { int res = 0; for (; p > 0; p -= (p & (-p))) res += s[p]; return res; } } // namespace Bit void dfs1(int x, int fat, int depth) { fa[x] = fat, dep[x] = depth, siz[x] = 1; int maxson = -1; for (int i = head[x]; i; i = e[i].nxt) { int y = e[i].to; if (y == fat) continue; dfs1(y, x, depth + 1); siz[x] += siz[y]; if (siz[y] > maxson) { maxson = siz[y]; son[x] = y; } } } void dfs2(int x, int topf) { top[x] = topf, id[x] = ++dfsc; if (!son[x]) return; dfs2(son[x], topf); for (int i = head[x]; i; i = e[i].nxt) { int y = e[i].to; if (y == fa[x] || y == son[x]) continue; dfs2(y, y); } } inline int getLca(int x, int y) { for (; top[x] != top[y];) { if (dep[top[x]] < dep[top[y]]) swap(x, y); x = fa[top[x]]; } return dep[x] < dep[y] ? x : y; } inline int getDis(int x, int y) { return dep[x] + dep[y] - 2 * dep[getLca(x, y)]; } inline set<Seg>::iterator getSeg(set<Seg> &s, int l) { set<Seg>::iterator it = s.lower_bound(Seg(l, inf, 0)); if (it != s.end() && it->l == l) return it; --it; int nowl = it->l, nowr = it->r, nowc = it->c; s.erase(it); if (l - 1 >= nowl) s.insert(Seg(nowl, l - 1, nowc)); s.insert(Seg(l, nowr, nowc)); return s.lower_bound(Seg(l, nowr, nowc)); } inline void ins(set<Seg> &s, int l, int r, int c, int st) { set<Seg>::iterator itl = getSeg(s, l), itr; if (r + 1 <= id[st] + siz[st] - 1) itr = getSeg(s, r + 1); else itr = s.end(); for (set<Seg>::iterator it = itl; it != itr; ++it) { Bit ::modify(it->c, -((it->r) - (it->l) + 1)); } Bit ::modify(c, r - l + 1); s.erase(itl, itr), s.insert(Seg(l, r, c)); } inline void modify(int x, int y, int c) { nowHead[c] = y; for (; top[x] != top[y];) { if (dep[top[x]] < dep[top[y]]) swap(x, y); ins(seg[top[x]], id[top[x]], id[x], c, top[x]); x = fa[top[x]]; } if (dep[x] > dep[y]) swap(x, y); ins(seg[top[x]], id[x], id[y], c, top[x]); } inline int solve(int x) { int c = getSeg(seg[top[x]], id[x])->c; return Bit ::query(c - 1) + getDis(x, nowHead[c]) + 1; } int main() { read(n), read(qn); for (int x, y, i = 1; i < n; i++) { read(x), read(y); ++deg[x], ++deg[y]; add(x, y), add(y, x); } dfs1(1, 0, 1), dfs2(1, 1); int cnt = 0; set<int> q; for (int i = 1; i <= n; i++) if (deg[i] == 1) q.insert(i), vis[i] = 1; for (; !q.empty();) { int now = (*q.begin()); q.erase(*q.begin()); seq[now] = ++cnt; nowHead[cnt] = now; seg[top[now]].insert(Seg(id[now], id[now], cnt)); Bit ::modify(cnt, 1); for (int i = head[now]; i; i = e[i].nxt) { if (vis[e[i].to]) continue; --deg[e[i].to]; if (deg[e[i].to] == 1 && !vis[e[i].to]) q.insert(e[i].to), vis[e[i].to] = 1; } } int lst = n; for (char op[9]; qn--;) { scanf( %s , op); if (op[0] == u ) { int x; read(x); modify(x, lst, ++cnt); lst = x; } if (op[0] == w ) { int x; read(x); printf( %d n , solve(x)); } if (op[0] == c ) { int x, y; read(x), read(y); printf( %d n , solve(x) < solve(y) ? x : y); } } return 0; } |
module servo_driver #(parameter freq = 50_000_000) (
input wire clk,
input wire rst_n,
input wire[7:0] angle,
output reg servo_pwm = 0,
output reg cycle_done = 0
);
parameter CYCLES_1_MS = freq / 1_000;
parameter CYCLES_PER_ANGLE = (CYCLES_1_MS * 2) / 8'hFF;
parameter CYCLES_21u33_MS = CYCLES_1_MS * 21 + CYCLES_1_MS / 3;
parameter CYCLES_22_MS = CYCLES_1_MS * 22;
// INTERNAL REGISTERS
reg[7:0] angle_reg = 0; // Used for storing angle
reg[31:0] counter = 0; // Used for store one period
reg[31:0] pulse_width = 0; // Used for vary pulse width (reversed)
reg[1:0] state = 0; // FSM current state
reg[1:0] next_state = 0; // FSM next state
parameter GET_ANGLE = 2'b00;
parameter GET_WIDTH = 2'b01;
parameter HIGH_PULSE = 2'b10;
parameter LOW_PULSE = 2'b11;
// Assign new state logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state = GET_ANGLE;
end else begin
state = next_state;
end
end
// Next state logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
next_state = GET_ANGLE;
end else begin
case (state)
GET_ANGLE: begin
next_state = GET_WIDTH;
end
GET_WIDTH: begin
next_state = HIGH_PULSE;
end
HIGH_PULSE: begin
if (counter == pulse_width) begin
next_state = LOW_PULSE;
end
end
LOW_PULSE: begin
if (counter == 0) begin
next_state = GET_ANGLE;
end
end
endcase
end
end
// Outputs logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
servo_pwm = 0;
cycle_done = 0;
counter = 0;
angle_reg = 0;
pulse_width = 0;
end else begin
case (state)
GET_ANGLE: begin
angle_reg = angle;
cycle_done = 1;
counter = CYCLES_22_MS;
end
GET_WIDTH: begin
pulse_width = CYCLES_21u33_MS - angle_reg * CYCLES_PER_ANGLE;
servo_pwm = 1;
cycle_done = 0;
end
HIGH_PULSE: begin
counter = counter - 1;
servo_pwm = 1;
end
LOW_PULSE: begin
counter = counter - 1;
servo_pwm = 0;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_BLACKBOX_V
`define SKY130_FD_SC_HD__BUF_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__buf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int sq[504][504], sum[504][504], dp[2][504][504]; int main() { int n, m; ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> m; for (int i = 1; i < n + 1; ++i) for (int j = 1; j < m + 1; ++j) cin >> sq[i][j]; for (int i = 1; i < n + 1; ++i) for (int j = 1; j < m + 1; ++j) sum[i][j] = sum[i - 1][j] + sum[i][j - 1] - sum[i - 1][j - 1] + sq[i][j]; int mx = -1000000000; for (int i = 1; i < n + 1; ++i) { for (int j = 1; j < m + 1; ++j) { int n = i % 2, p = (i - 1) % 2, len = min(2 * ((i - 1) / 2) + 1, 2 * ((j - 1) / 2) + 1); dp[n][j][1] = sq[i][j]; for (int k = 3; k <= len; k += 2) { dp[n][j][k] = sum[i][j] - sum[i - k][j] - sum[i][j - k] + sum[i - k][j - k] - dp[p][j - 1][k - 2] - sq[i - k + 2][j - k + 1]; mx = max(dp[n][j][k], mx); } } } cout << mx << n ; return 0; } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.10.2017 10:51:16
// Design Name:
// Module Name: controlALU_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module controlALU_tb();
reg [1:0]ALUop;
reg [5:0]instru;
reg clk;
wire [2:0] contALU;
controlALU uut(
.ALUop(ALUop),
.instru(instru),
.clk(clk),
.contALU(contALU)
);
always begin
clk=1'b1;
#50;
clk=1'b0;
#50;
end
initial begin
ALUop=2'b00;
instru=6'bx1x_x1x;
#100;
ALUop=2'b00;
instru=6'b001_101;
#100; //200
ALUop=2'b01;
instru=6'b111_001;
#100; //300
ALUop=2'b10;
instru=6'b100000;
#100; //400
ALUop=2'b10;
instru=6'b100010;
#100; //500
ALUop=2'b10;
instru=6'b100100;
#100;
ALUop=2'b10;
instru=6'b100101;
#100;
ALUop=2'b10;
instru=6'b101010;
#100;
ALUop=2'b11;
instru=6'b111111;
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_key_pio (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 3: 0] in_port;
input reset_n;
wire clk_en;
wire [ 3: 0] data_in;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {4 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { string s; cin >> s; vector<string> s1; for (int i = 0; i < int((s).size()); i++) { string s2(int((s).size()) - i, 0 ); if (s[i] != 0 ) { s2[0] = s[i]; s1.push_back(s2); } } cout << s1.size() << n ; for (auto i : s1) { cout << i << ; } cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long t = 1; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int dirx[] = {1, -1, 0, 0, 1, 1, -1, -1}, diry[] = {0, 0, 1, -1, 1, -1, 1, -1}; long long bigmod(long long x, long long p) { long long res = 1; while (p) { if (p & 1) res = (res * x) % 1000000007; x = (x * x) % 1000000007; p >>= 1; } return res; } int32_t main() { ios_base::sync_with_stdio(false); string s; cin >> s; long long ans = 0; int n = s.size(); for (long long i = 0, j = n - 1; i < n; i++, j--) { long long bef = i * (i + 1) / 2; bef %= 1000000007; bef *= (s[i] - 0 ); ans = (ans + bigmod(10, j) * bef % 1000000007) % 1000000007; } long long cur = 0; for (long long i = 0; i < n - 1; i++) { cur += (s[i] - 0 ); cur %= 1000000007; ans = (ans + bigmod(10, n - i - 2) * (n - i - 1) % 1000000007 * cur % 1000000007) % 1000000007; } cout << ans; return 0; } |
//////////////////////////////////////////////////////////////////////
//
// clkgen
//
// Handles clock and reset generation for rest of design
//
//
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "timescale.v"
`include "orpsoc-defines.v"
module clkgen
(
// Main clocks in, depending on board
input sys_clk_pad_i,
// Asynchronous, active low reset in
input rst_n_pad_i,
// Input reset - through a buffer, asynchronous
output async_rst_o,
// Wishbone clock and reset out
output wb_clk_o,
output wb_rst_o,
// JTAG clock
`ifdef SIM
input tck_pad_i,
output dbg_tck_o,
`endif
// Main memory clocks
output sdram_clk_o,
output sdram_rst_o
);
// First, deal with the asychronous reset
wire async_rst;
wire async_rst_n;
assign async_rst_n = rst_n_pad_i;
assign async_rst = ~async_rst_n;
// Everyone likes active-high reset signals...
assign async_rst_o = ~async_rst_n;
`ifdef SIM
assign dbg_tck_o = tck_pad_i;
`endif
//
// Declare synchronous reset wires here
//
// An active-low synchronous reset signal (usually a PLL lock signal)
wire sync_rst_n;
wire pll_lock;
`ifndef SIM
pll pll0 (
.areset (async_rst),
.inclk0 (sys_clk_pad_i),
.c0 (sdram_clk_o),
.c1 (wb_clk_o),
.locked (pll_lock)
);
`else
assign sdram_clk_o = sys_clk_pad_i;
assign wb_clk_o = sys_clk_pad_i;
assign pll_lock = 1'b1;
`endif
assign sync_rst_n = pll_lock;
//
// Reset generation
//
//
// Reset generation for wishbone
reg [15:0] wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst)
if (async_rst)
wb_rst_shr <= 16'hffff;
else
wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
assign wb_rst_o = wb_rst_shr[15];
// Reset generation for SDRAM controller
reg [15:0] sdram_rst_shr;
always @(posedge sdram_clk_o or posedge async_rst)
if (async_rst)
sdram_rst_shr <= 16'hffff;
else
sdram_rst_shr <= {sdram_rst_shr[14:0], ~(sync_rst_n)};
assign sdram_rst_o = sdram_rst_shr[15];
endmodule // clkgen
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { ios::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr); int k; cin >> k; int n = 2000; k += n; int arr[n]; arr[0] = -1; for (int i = 1; i < 2000; i++) { if (k >= 1000000) arr[i] = 1000000; else arr[i] = k; k -= arr[i]; } cout << 2000 << n ; for (int i = 0; i < 2000; i++) cout << arr[i] << ; } |
#include <bits/stdc++.h> using namespace std; const long long int mod = 1000000000 + 7; long long int n, k, summ, tr, a[1000000], minn, maxx; string s, s1; map<int, int> been; int compare(const void* a, const void* b) { return ((*(long long int*)a) - (*(long long int*)b)); }; int gcd(int a, int b) { while (b != 0) { int t = b; b = a % b; a = t; } return a; } int NOK(int n1, int n2) { return n1 * n2 / gcd(n1, n2); } int main() { cin >> n; for (int i = 0; i < n; i++) { been.clear(); maxx = a - 1; minn = z + 1; cin >> s; for (int j = 0; j < s.length(); j++) { if (been[s[j]] == 1) { minn = -1000; break; } been[s[j]] = 1; minn = min(minn, (long long int)s[j]); maxx = max(maxx, (long long int)s[j]); } if (maxx - minn + 1 != s.length()) { cout << No << endl; } else { cout << Yes << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int N, M; string str[2005]; long long pr[2005][2005], pc[2005][2005]; long long dpr[2005][2005], dpd[2005][2005]; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> N >> M; for (int i = 0; i <= N - 1; i++) cin >> str[i]; bool has = 0; for (int i = N - 1; i >= 0; i--) { for (int j = M - 1; j >= 0; j--) { pr[i][j] = (i == N - 1) ? 0 : pr[i + 1][j] + (str[i + 1][j] == R ); pc[i][j] = (j == M - 1) ? 0 : pc[i][j + 1] + (str[i][j + 1] == R ); if (str[i][j] == R ) has = 1; } } if (N == 1 || M == 1) { cout << (has ? 0 : 1) << n ; return 0; } long long ans = 0; for (int i = N - 1; i >= 0; i--) { for (int j = M - 1; j >= 0; j--) { if (i == N - 1) { if (pc[i][j] == 0) dpr[i][j] = 1; dpr[i][j] = (dpr[i][j] + dpr[i + 1][j]) % 1000000007; } else if (j == M - 1) { if (pr[i][j] == 0) dpd[i][j] = 1; dpd[i][j] = (dpd[i][j] + dpd[i][j + 1]) % 1000000007; } else { int c = pc[i][j]; dpr[i][j] = (dpd[i][j + 1] - dpd[i][M - c] + 1000000007) % 1000000007; c = pr[i][j]; dpd[i][j] = (dpr[i + 1][j] - dpr[N - c][j] + 1000000007) % 1000000007; if (i == 0 && j == 0) ans = (dpd[0][0] + dpr[0][0]) % 1000000007; dpr[i][j] = (dpr[i][j] + dpr[i + 1][j]) % 1000000007; dpd[i][j] = (dpd[i][j] + dpd[i][j + 1]) % 1000000007; } } } cout << ans << n ; return 0; } |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: offset_flag_to_one_hot.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The offset_flag_to_one_hot module takes a data offset,
// and offset_enable and computes the 1-hot encoding of the offset when enabled
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
module offset_flag_to_one_hot
#(
parameter C_WIDTH = 4
)
(
input [clog2s(C_WIDTH)-1:0] WR_OFFSET,
input WR_FLAG,
output [C_WIDTH-1:0] RD_ONE_HOT
);
assign RD_ONE_HOT = {{(C_WIDTH-1){1'b0}},WR_FLAG} << WR_OFFSET;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T sqr(const T& a) { return a * a; } template <typename T> inline int sign(const T& a) { return a < 0 ? -1 : a > 0; } void task(); int main() { task(); return 0; } vector<int> z_function(string s) { int n = (int)s.length(); vector<int> z(n); for (int i = 1, l = 0, r = 0; i < n; ++i) { if (i <= r) z[i] = min(r - i + 1, z[i - l]); while (i + z[i] < n && s[z[i]] == s[i + z[i]]) ++z[i]; if (i + z[i] - 1 > r) l = i, r = i + z[i] - 1; } return z; } int n, k; string s; int ans[int(2e6) + 10]; int add[int(2e6) + 10]; int sub[int(2e6) + 10]; void task() { ios_base::sync_with_stdio(0); cin >> n >> k; cin >> s; auto z = z_function(s); z[0] = s.length(); (void(1)); for (int len = 1; len <= n; ++len) { for (int i = 0, step = 0; i < n; i += len, ++step) { if (z[i] < len) break; if (step == k - 1) { (void(1)); add[i + len - 1]++; sub[i + len - 1 + min(len, z[i + len])]++; break; } } } int cur = 0; for (int i = 0; i < n; ++i) { cur += add[i]; ans[i] = cur > 0; cur -= sub[i]; } for (int i = 0; i < n; ++i) cout << ans[i]; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTP_SYMBOL_V
`define SKY130_FD_SC_MS__DLXTP_SYMBOL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { char ch; bool flag = false; for (ch = getchar(); !isdigit(ch); ch = getchar()) if (ch == - ) flag = true; for (x = 0; isdigit(ch); x = x * 10 + ch - 0 , ch = getchar()) ; x = flag ? -x : x; } inline void write(int x) { static const int maxlen = 100; static char s[maxlen]; if (x < 0) { putchar( - ); x = -x; } if (!x) { putchar( 0 ); return; } int len = 0; for (; x; x /= 10) s[len++] = x % 10 + 0 ; for (int i = len - 1; i >= 0; --i) putchar(s[i]); } int n, m; int pre[11000], now[110], son[11000], v[11000], tot; int f[110][110][30]; char s[100]; void build(int a, int b, int c) { pre[++tot] = now[a]; now[a] = tot; son[tot] = b; v[tot] = c; } int dfs(int x, int y, int MAX) { if (f[x][y][MAX] != -1) return f[x][y][MAX]; set<int> S; for (int p = now[x]; p; p = pre[p]) if (v[p] >= MAX) S.insert(dfs(y, son[p], v[p])); int q = -1; for (auto t : S) { if (t != q + 1) break; q = t; } return f[x][y][MAX] = q + 1; } int main() { read(n); read(m); for (int i = 1; i <= m; i++) { int a, b; read(a); read(b); scanf( %s , s); build(a, b, s[0] - a + 1); } memset(f, -1, sizeof(f)); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) dfs(i, j, 0); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) if (f[i][j][0]) printf( A ); else printf( B ); puts( ); } return 0; } |
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7LL; const int MAXN = 212345; int vis[MAXN]; vector<int> g[MAXN]; long long dfs(int u) { vis[u] = 1; long long r = 1; for (int v : g[u]) if (!vis[v]) r += dfs(v); return r; } long long fexp(long long b, long long e) { if (b == 1 || e == 0) return 1; if (b == 0) return 0; long long resp = fexp(b, e / 2); resp = ((resp % MOD) * (resp % MOD)) % MOD; if (e & 1) resp = ((resp % MOD) * (b % MOD)) % MOD; return resp % MOD; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; for (int i = 0, u, v, w; i < n - 1; ++i) { cin >> u >> v >> w; if (!w) { g[u].push_back(v); g[v].push_back(u); } } long long r = fexp(n, k); for (int i = 1; i <= n; ++i) { if (!vis[i]) { r = (r % MOD - fexp(dfs(i), k) % MOD) % MOD; if (r < 0) r += MOD; r %= MOD; } } cout << r << n ; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 15:17:23 10/24/2016
// Module Name: ALU_CONTROL
// Project Name: MIPS
// Description: MIPS ALU_CONTROL module in the EXECUTE stage.
//
// Dependencies: None
//
////////////////////////////////////////////////////////////////////////////////
module ALU_CONTROL(input [5:0] funct, input [1:0] alu_op, output reg [2:0] select);
always @ *
begin
case (alu_op)
2'b00:
begin
select <= 3'b010; // LW / SW
end
2'b01:
begin
select <= 3'b110; // BRE
end
2'b10:
begin
case (funct)
6'b100000:
begin
select <= 3'b010; // R add
end
6'b100010:
begin
select <= 3'b110; // R sub
end
6'b100100:
begin
select <= 3'b000; // R and
end
6'b100101:
begin
select <= 3'b001; // R or
end
6'b101010:
begin
select <= 3'b111; // R slt
end
endcase
end
2'b11:
begin
select <= 3'b011; // Invalid input
end
endcase
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ecb_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:29 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ecb_e.v,v 1.1 2004/04/06 10:50:28 wig Exp $
// $Date: 2004/04/06 10:50:28 $
// $Log: inst_ecb_e.v,v $
// Revision 1.1 2004/04/06 10:50:28 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ecb_e
//
// No `defines in this module
module inst_ecb_e
//
// Generated module inst_ecb
//
(
nreset,
nreset_s
);
// Generated Module Inputs:
input nreset;
input nreset_s;
// Generated Wires:
wire nreset;
wire nreset_s;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ecb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4_1_V
`define SKY130_FD_SC_HD__NAND4_1_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4_1 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4_1_V
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.