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#include <bits/stdc++.h> using namespace std; const int N = 110000; const int B = 60; int n, q, mc; int aint[4 * N][B]; void update(int nod, int pozx, int pozy, int poz, int val) { int i; if (pozx == pozy) { for (i = 0; i < B; ++i) { aint[nod][i] = 1; if (i % val == 0) aint[nod][i]++; } return; } int mid = (pozx + pozy) / 2; if (mid >= poz) update(2 * nod, pozx, mid, poz, val); else update(2 * nod + 1, mid + 1, pozy, poz, val); for (i = 0; i < B; ++i) aint[nod][i] = aint[2 * nod][i] + aint[2 * nod + 1][(i + aint[2 * nod][i]) % B]; } int query(int nod, int pozx, int pozy, int poz1, int poz2) { if (poz1 <= pozx && pozy <= poz2) { int rez = aint[nod][mc]; mc = (mc + aint[nod][mc]) % B; return rez; } int mid = (pozx + pozy) / 2, rez = 0; if (mid >= poz1) rez = query(2 * nod, pozx, mid, poz1, poz2); if (mid < poz2) rez += query(2 * nod + 1, mid + 1, pozy, poz1, poz2); return rez; } int main() { int i; cin >> n; for (i = 1; i <= n; ++i) { int x; cin >> x; update(1, 1, n, i, x); } cin >> q; for (i = 1; i <= q; ++i) { char a; int p1, p2; cin >> a >> p1 >> p2; if (a == A ) { mc = 0; cout << query(1, 1, n, p1, p2 - 1) << n ; } else update(1, 1, n, p1, p2); } return 0; } |
#include <bits/stdc++.h> using namespace std; int q, n, x; void f() { cin >> n; vector<int> v; for (int i = 0; i < n; i++) { cin >> x; v.push_back(x); } sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); int maxi = v.back(); for (int i = v.size() - 1; i > 0 && v[i] + v[i - 1] > maxi; i--) for (int j = i - 1; j >= 0; j--) if (v[i] % v[j] != 0) { maxi = max(maxi, v[i] + v[j]); break; } for (int i = v.size() - 1; i > 0 && v[i] + v[i - 1] + v[i - 2] > maxi; i--) for (int j = i - 1; j > 0; j--) if (v[i] % v[j] != 0) for (int k = j - 1; k >= 0; k--) if (v[i] % v[k] != 0 && v[j] % v[k] != 0) { maxi = max(maxi, v[i] + v[j] + v[k]); break; } cout << maxi << endl; } int main() { ios::sync_with_stdio(false); cin.tie(0), cout.tie(0); cin >> q; for (int u = 0; u < q; u++) f(); return 0; } |
#include <bits/stdc++.h> int A[1000000], i, j, k, l, m, n, a, b, c, d, e, f, g, B[500000]; int main() { scanf( %d%d%d%d , &a, &b, &m, &A[0]); for (i = 1; i <= 100005; i++) { A[i] = (a * A[i - 1] + b) % m; if (B[A[i]]) { printf( %d , i - B[A[i]]); return 0; } B[A[i]] = i; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O41AI_1_V
`define SKY130_FD_SC_HD__O41AI_1_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o41ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o41ai_1 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O41AI_1_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module cdc_syncfifo #(
parameter DSIZE = 32,
parameter ASIZE = 2
) (
output wire [DSIZE-1:0] rdata,
output wire wfull,
output wire rempty,
input wire [DSIZE-1:0] wdata,
input wire winc, wclk, wrst,
input wire rinc, rclk, rrst
);
wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
cdc_sync_r2w #(
.ADDRSIZE(ASIZE)
) sync_r2w_inst (
.wq2_rptr(wq2_rptr),
.rptr(rptr),
.wclk(wclk),
.wrst(wrst)
);
cdc_sync_w2r #(
.ADDRSIZE(ASIZE)
) sync_w2r_inst (
.rq2_wptr(rq2_wptr),
.wptr(wptr),
.rclk(rclk),
.rrst(rrst)
);
cdc_fifomem #(
.DATASIZE(DSIZE),
.ADDRSIZE(ASIZE)
) cdc_fifomem_inst (
.rdata(rdata),
.wdata(wdata),
.waddr(waddr),
.raddr(raddr),
.wclken(winc),
.wfull(wfull),
.wclk(wclk)
);
rptr_empty #(
.ADDRSIZE(ASIZE)
) rptr_empty_inst (
.rempty(rempty),
.raddr(raddr),
.rptr(rptr),
.rq2_wptr(rq2_wptr),
.rinc(rinc),
.rclk(rclk),
.rrst(rrst)
);
wptr_full #(
.ADDRSIZE(ASIZE)
) wptr_full_inst (
.wfull(wfull),
.waddr(waddr),
.wptr(wptr),
.wq2_rptr(wq2_rptr),
.winc(winc),
.wclk(wclk),
.wrst(wrst)
);
endmodule
module cdc_fifomem #(
parameter DATASIZE = 32, // Memory data word width
parameter ADDRSIZE = 2 // Number of mem address
) (
output wire [DATASIZE-1:0] rdata,
input wire [DATASIZE-1:0] wdata,
input wire [ADDRSIZE-1:0] waddr, raddr,
input wire wclken, wfull, wclk
);
//`ifdef VENDORRAM
//
// // instantiation of a vendor's dual-port RAM
// vendor_ram mem (.dout(rdata), .din(wdata),
// .waddr(waddr), .raddr(raddr),
// .wclken(wclken),
// .wclken_n(wfull), .clk(wclk));
//`else
// RTL Verilog memory model
localparam DEPTH = 1<<ADDRSIZE;
reg [DATASIZE-1:0] cdc_mem [0:DEPTH-1];
assign rdata = cdc_mem[raddr];
//always @(posedge wclk)
// rdata <= mem[raddr];
always @(posedge wclk)
if (wclken && !wfull) cdc_mem[waddr] <= wdata;
// endif
endmodule
module rptr_empty #(
parameter ADDRSIZE = 2
) (
output reg rempty,
output wire [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE :0] rptr,
input wire [ADDRSIZE :0] rq2_wptr,
input wire rinc, rclk, rrst
);
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext;
//-------------------
// GRAYSTYLE2 pointer
//-------------------
//synopsys sync_set_reset "rrst"
always @(posedge rclk)
if (rrst) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + (rinc & ~rempty);
assign rgraynext = (rbinnext>>1) ^ rbinnext;
//---------------------------------------------------------------
// FIFO empty when the next rptr == synchronized wptr or on reset
//---------------------------------------------------------------
wire rempty_val;
assign rempty_val = (rgraynext == rq2_wptr);
//synopsys sync_set_reset "rrst"
always @(posedge rclk)
if (rrst) rempty <= 1'b1;
else rempty <= rempty_val;
endmodule
module wptr_full #(
parameter ADDRSIZE = 2
) (
output reg wfull,
output wire [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE :0] wptr,
input wire [ADDRSIZE :0] wq2_rptr,
input wire winc, wclk, wrst
);
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext;
// GRAYSTYLE2 pointer
//synopsys sync_set_reset "wrst"
always @(posedge wclk)
if (wrst) {wbin, wptr} <= 0;
else {wbin, wptr} <= {wbinnext, wgraynext};
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + (winc & ~wfull);
assign wgraynext = (wbinnext>>1) ^ wbinnext;
//------------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//------------------------------------------------------------------
wire wfull_val;
assign wfull_val = (wgraynext=={~wq2_rptr[ADDRSIZE:ADDRSIZE-1], wq2_rptr[ADDRSIZE-2:0]});
//synopsys sync_set_reset "wrst"
always @(posedge wclk)
if (wrst) wfull <= 1'b0;
else wfull <= wfull_val;
endmodule
module cdc_sync_r2w #(
parameter ADDRSIZE = 2
) (
output reg [ADDRSIZE:0] wq2_rptr,
input wire [ADDRSIZE:0] rptr,
input wire wclk, wrst
);
reg [ADDRSIZE:0] cdc_sync_wq1_rptr;
//synopsys sync_set_reset "wrst"
always @(posedge wclk)
if (wrst) {wq2_rptr,cdc_sync_wq1_rptr} <= 0;
else {wq2_rptr,cdc_sync_wq1_rptr} <= {cdc_sync_wq1_rptr,rptr};
endmodule
module cdc_sync_w2r #(
parameter ADDRSIZE = 2
) (
output reg [ADDRSIZE:0] rq2_wptr,
input wire [ADDRSIZE:0] wptr,
input wire rclk, rrst
);
reg [ADDRSIZE:0] cdc_sync_rq1_wptr;
//synopsys sync_set_reset "rrst"
always @(posedge rclk)
if (rrst) {rq2_wptr,cdc_sync_rq1_wptr} <= 0;
else {rq2_wptr,cdc_sync_rq1_wptr} <= {cdc_sync_rq1_wptr,wptr};
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O221AI_BEHAVIORAL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y, or1_out, or0_out, C1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_BEHAVIORAL_V |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_mask(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [11:0] dx,
input signed [11:0] dy,
input signed [17:0] tx,
input signed [17:0] ty,
input [17:0] tex_hmask,
input [17:0] tex_vmask,
output reg pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] dx_f,
output reg signed [11:0] dy_f,
output reg signed [17:0] tx_m,
output reg signed [17:0] ty_m
);
always @(posedge sys_clk) begin
if(sys_rst)
pipe_stb_o <= 1'b0;
else begin
if(pipe_ack_i)
pipe_stb_o <= 1'b0;
if(pipe_stb_i & pipe_ack_o) begin
pipe_stb_o <= 1'b1;
dx_f <= dx;
dy_f <= dy;
tx_m <= tx & tex_hmask;
ty_m <= ty & tex_vmask;
end
end
end
assign pipe_ack_o = ~pipe_stb_o | pipe_ack_i;
assign busy = pipe_stb_o;
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using vvi = vector<vector<int>>; using vl = vector<ll>; using vvl = vector<vector<ll>>; using pi = pair<int, int>; using pl = pair<ll, ll>; template <typename U> void print(U arr) { for (auto element : arr) { cout << element << ; } cout << n ; } void setup(string s) { freopen((s + .in ).c_str(), r , stdin); freopen((s + .out ).c_str(), w , stdout); } const int M = 1e9 + 7; const int mxN = 1e5 + 1; vvi adj(mxN); vi lvl(mxN, 0), sub(mxN, 0); int getSize(int i, int p) { sub[i] = 1; for (auto& e : adj[i]) { if (e != p && !lvl[e]) { sub[i] += getSize(e, i); } } return sub[i]; } ll centroid(int i, int p, int n) { for (auto& e : adj[i]) { if (e != p && !lvl[e] && sub[e] > n / 2) return centroid(e, i, n); } return i; } ll decomp(ll i, ll l) { ll cent = centroid(i, -1, getSize(i, -1)); lvl[cent] = l; for (ll j : adj[cent]) if (!lvl[j]) decomp(j, l + 1); return cent; } int main(void) { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (ll _ = 0; _ < n - 1; _++) { int a, b; cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } decomp(1, 1); for (ll i = 1; i < n + 1; i++) cout << (char)( A + lvl[i] - 1) << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0); ios::sync_with_stdio(false); cout << setprecision(12); int l; cin >> l; string s; cin >> s; size_t t = 0; for (auto c : s) t += (c == 1 ); if (t * 2 == s.length()) { cout << 2 << endl; cout << s[0] << << s.substr(1) << endl; } else { cout << 1 << endl; cout << s << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<vector<int>> v(n); int mat[4][4] = { {8, 9, 1, 13}, {3, 12, 7, 5}, {0, 2, 4, 11}, {6, 10, 15, 14}}; int ans[n][n]; for (int i = 0; i < n * n; i++) { int x = i / n; v[x].push_back(i); } int count = 0; for (int i = 0; i < n; i += 4) { for (int j = 0; j < n; j += 4) { for (int k = i; k < i + 4; k++) { for (int l = j; l < j + 4; l++) { ans[k][l] = count++; } } } } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (j == 0) cout << ans[i][j]; else cout << << ans[i][j]; } cout << endl; } return 0; } |
// A shifting buffer to buffer the input image. The buffer should be 28x28
// registers to hold the entire image and the buffer should be the size of
// the kernel (9x9) to input part of the image into the mult-adder tree.
// buffer wire[0][0] is in the bottom right corner of image so that the video
// stream can be fed directly into buffer. buffer_wire[max][max] is the top
// left corner.
`include "../network_params.h"
module shifting_window(
input clock,
input reset,
input shift_up, // shift all rows up
input shift_left, // to load new pixel into bottom row
input [`CAMERA_PIXEL_BITWIDTH:0] pixel_in,
output [`BUFFER_OUT_VECTOR_BITWIDTH:0] buffer_out
);
// paremeters
// wire declarations
wire [`CAMERA_PIXEL_BITWIDTH:0] buffer_wire [`BUFFER_BW:0][`BUFFER_BH:0];
// reg declarations
genvar i;
genvar j;
generate
for(j=1;j < `BUFFER_H; j=j+1) begin : core_buffer_h_loop
for(i=0; i < `BUFFER_W; i=i+1) begin : core_buffer_w_loop
buffer_unit unit_inst(
.clock(clock),
.reset(reset),
.shift(shift_up),
.in(buffer_wire[i][j-1]), // bottom to top (height)
.out(buffer_wire[i][j])
);
end
end
endgenerate
// loop over first row of width and height
genvar k;
generate
for (k = 1; k < `BUFFER_W; k=k+1) begin : width_row0_loop
buffer_unit w_row0_unit_inst(
.clock(clock),
.reset(reset),
.shift(shift_left),
.in(buffer_wire[k-1][0]), // right to left (width)
.out(buffer_wire[k][0])
);
end // for
endgenerate
// instantiate origin window unit
buffer_unit origin_unit_inst(
.clock(clock),
.reset(reset),
.shift(shift_left),
.in(pixel_in), // right to left (width)
.out(buffer_wire[0][0])
);
// loop to connect buffer out vector to buffer_wire
genvar n;
genvar m;
generate
for (n=0; n < `BUFFER_H; n=n+1) begin : buffer_height_loop
for (m=0; m < `BUFFER_W; m=m+1) begin : buffer_width_loop
/*
assign buffer_wire[m][n] = buffer_out[
(`CAMERA_PIXEL_WIDTH*m)+(`BUFFER_W*`CAMERA_PIXEL_WIDTH*n) +`CAMERA_PIXEL_BITWIDTH:
(`CAMERA_PIXEL_WIDTH*m)+(`BUFFER_W*`CAMERA_PIXEL_WIDTH*n)
];
*/
assign buffer_out[
(`CAMERA_PIXEL_WIDTH*m)+(`BUFFER_W*`CAMERA_PIXEL_WIDTH*n) +`CAMERA_PIXEL_BITWIDTH:
(`CAMERA_PIXEL_WIDTH*m)+(`BUFFER_W*`CAMERA_PIXEL_WIDTH*n)
] = buffer_wire[m][n];
end // for m
end // for n
endgenerate
endmodule
module buffer_unit(
input clock,
input reset,
input shift,
input [`CAMERA_PIXEL_BITWIDTH:0] in,
output reg [`CAMERA_PIXEL_BITWIDTH:0] out
);
always@(posedge clock or negedge reset) begin
if(reset == 1'b0)
out <= `CAMERA_PIXEL_WIDTH'd0;
else if(shift)
out <= in;
else
out <= out;
end // always
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long FASTIO = []() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); return 0; }(); long long n; vector<vector<long long>> ans; long long ask(long long x1, long long y1, long long x2, long long y2) { cout << ? << x1 << << y1 << << x2 << << y2 << n ; cout.flush(); long long c; cin >> c; if (c == -1) { while (1) { } } return c; } void bfs(long long x, long long y) { vector<vector<long long>> used(n + 5, vector<long long>(n + 5, true)); vector<long long> v1 = {2, 1, 0, 0, -1, -2}; vector<long long> v2 = {0, 1, 2, -2, -1, 0}; for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= n; j++) { used[i][j] = false; } } queue<pair<long long, long long>> q; q.push({x, y}); used[x][y] = true; while (!q.empty()) { long long X = q.front().first; long long Y = q.front().second; q.pop(); for (long long i = 0; i < 6; i++) { if (X + v1[i] > 0 && Y + v2[i] > 0 && !used[X + v1[i]][Y + v2[i]]) { pair<long long, long long> a = {X, Y}, b = {X + v1[i], Y + v2[i]}; if (v1[i] < 0 || v2[i] < 0) { swap(a, b); } if (b != pair<long long, long long>{n, n}) { bool t = ask(a.first, a.second, b.first, b.second); if (t) { ans[X + v1[i]][Y + v2[i]] = ans[X][Y]; } else { ans[X + v1[i]][Y + v2[i]] = !ans[X][Y]; } } used[X + v1[i]][Y + v2[i]] = true; q.push({X + v1[i], Y + v2[i]}); } } } } signed main() { cin >> n; ans.resize(n + 10, vector<long long>(n + 10, -1)); ans[1][1] = 1; ans[n][n] = 0; bfs(1, 1); long long p = 1; while (ans[p][p] == ans[p + 2][p + 2]) { ++p; } if (ask(p, p, p + 2, p + 1)) { ans[p + 2][p + 1] = ans[p][p]; bfs(p + 2, p + 1); } else if (ask(p + 1, p, p + 2, p + 2)) { ans[p + 1][p] = ans[p + 2][p + 2]; bfs(p + 1, p); } else { if (ans[p + 2][p] == 1) { ans[p + 2][p + 1] = 0; bfs(p + 2, p + 1); } else { ans[p + 1][p] = 1; bfs(p + 1, p); } } cout << ! n ; for (long long i = 1; i <= n; i++) { for (long long j = 1; j <= n; j++) { cout << ans[i][j]; } cout << n ; } } |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: Bmul.v
// /___/ /\ Timestamp: Mon May 1 00:08:59 2017
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Bmul.ngc /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Bmul.v
// Device : 3s500efg320-5
// Input file : /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Bmul.ngc
// Output file : /home/rohith/Image-Watermarking/ipcore_dir/tmp/_cg/Bmul.v
// # of Modules : 1
// Design Name : Bmul
// Xilinx : /opt/14.7/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module Bmul (
p, a
)/* synthesis syn_black_box syn_noprune=1 */;
output [7 : 0] p;
input [7 : 0] a;
// synthesis translate_off
wire [7 : 1] NlwRenamedSignal_a;
assign
p[6] = NlwRenamedSignal_a[7],
p[5] = NlwRenamedSignal_a[6],
p[4] = NlwRenamedSignal_a[5],
p[3] = NlwRenamedSignal_a[4],
p[2] = NlwRenamedSignal_a[3],
p[1] = NlwRenamedSignal_a[2],
p[0] = NlwRenamedSignal_a[1],
NlwRenamedSignal_a[7] = a[7],
NlwRenamedSignal_a[6] = a[6],
NlwRenamedSignal_a[5] = a[5],
NlwRenamedSignal_a[4] = a[4],
NlwRenamedSignal_a[3] = a[3],
NlwRenamedSignal_a[2] = a[2],
NlwRenamedSignal_a[1] = a[1];
GND \blk00000001/blk00000002 (
.G(p[7])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
#include <bits/stdc++.h> using namespace std; int main() { set<string> qq; string s, q, g[100000]; int h, j = -1; while (cin >> s) { h = 3; q = ; q = q + s[0] + s[1] + s[2]; while (h != s.length()) { while (s[h] != && s[h] != . ) { q += s[h]; h++; } q += / ; if (s[h] != . ) { j++; g[j] = q; } else break; h++; } } j++; sort(g, g + j); int p = 1, max = 1; qq.insert(g[0]); for (int i = 1; i < j; i++) { if (g[i] == g[i - 1]) p++; else p = 1; if (p > max) max = p; qq.insert(g[i]); } set<string>::iterator it; string w = , t = ; int r = 0, max2 = 0; for (it = qq.begin(); it != qq.end(); it++) { if (w == ) w = *it; else { t = ; p = 1; for (int i = 0; i < w.length(); i++) { if (i == (*it).length()) { p = 0; break; } t += (*it)[i]; } if (t != w) p = 0; if (p == 0) { w = *it; r = 0; } else { r++; } if (r > max2) max2 = r; } } cout << max2 << << max; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31AI_LP_V
`define SKY130_FD_SC_LP__O31AI_LP_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31ai_lp (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31ai_lp (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31AI_LP_V
|
#include <bits/stdc++.h> using namespace std; signed main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; auto solve = []() { int n; cin >> n; vector<pair<int, int>> a(n); for (int i = 0; i < n; i++) { cin >> a[i].first; a[i].first--; } vector<int> ans(n + n); vector<int> used(n + n); for (int i = 0; i < n; i++) { ans[i * 2] = a[i].first; a[i].second = i * 2; used[a[i].first] = 1; } for (int i = 1; i < n + n; i += 2) { int x = ans[i - 1]; int j; for (j = x + 1; j < n + n && used[j]; j++) ; if (j == n + n) { cout << -1 << n ; return 0; } used[j] = 1; ans[i] = j; } for (int i = 0; i < n + n; i++) { if (i > 0) cout << ; cout << ans[i] + 1; } cout << n ; }; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int cekTanda(char ch) { switch (ch) { case > : return 8; case < : return 9; case + : return 10; case - : return 11; case . : return 12; case , : return 13; case [ : return 14; case ] : return 15; } } int main() { char str[1024]; scanf( %s , str); int panjang = strlen(str); int res = 0; for (int i = 0; i < panjang; i++) { res = (res << 4) % 1000003; res += cekTanda(str[i]); res %= 1000003; } printf( %d , res); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_MUX_4TO2_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_MUX_4TO2_BLACKBOX_V
/**
* udp_mux_4to2: Four to one multiplexer with 2 select controls
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_mux_4to2 (
X ,
A0,
A1,
A2,
A3,
S0,
S1
);
output X ;
input A0;
input A1;
input A2;
input A3;
input S0;
input S1;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_MUX_4TO2_BLACKBOX_V
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always while (boolean_expression ) statement ;
module main ;
reg [3:0] value1,value2,value3;
initial
begin
value1 = 0; // Time 0 assignemnt
value2 = 0;
#6 ;
if(value1 != 4'h1)
begin
$display("FAILED - 3.1.7C always while (1'b1 )") ;
value2 = 1;
end
#5 ;
if(value1 != 4'h2)
begin
$display("FAILED - 3.1.7C always while (1'b1) ");
value2 = 1;
end
#5 ;
if(value1 != 4'h3)
begin
$display("FAILED - 3.1.7C always while (1'b1) ");
value2 = 1;
end
if(value2 == 0)
$display("PASSED");
$finish;
end
always while (1'b1 && 1'b1) begin
#5 ;
value1 = value1 + 1;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
//
// This is a copy of t_param.v with the parentheses around the module parameters
// removed.
module t (/*AUTOARG*/
// Inputs
clk
);
parameter PAR = 3;
m1 #PAR m1();
m3 #PAR m3();
mnooverride #10 mno();
input clk;
integer cyc=1;
reg [4:0] bitsel;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
bitsel = 0;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 1;
if (PAR[bitsel]!==1'b1) $stop;
bitsel = 2;
if (PAR[bitsel]!==1'b0) $stop;
end
if (cyc==1) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module m1;
localparam PAR1MINUS1 = PAR1DUP-2-1;
localparam PAR1DUP = PAR1+2; // Check we propagate parameters properly
parameter PAR1 = 0;
m2 #PAR1MINUS1 m2 ();
endmodule
module m2;
parameter PAR2 = 10;
initial begin
$display("%x",PAR2);
if (PAR2 !== 2) $stop;
end
endmodule
module m3;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 3) $stop;
end
endmodule
module mnooverride;
localparam LOC = 13;
parameter PAR = 10;
initial begin
$display("%x %x",LOC,PAR);
if (LOC !== 13) $stop;
if (PAR !== 10) $stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, d; cin >> n; unordered_set<int> s; int mx = n; int c = 0; for (int i = 0; i < n; i++) { cin >> d; if (d == mx) { for (int i = 0; i < c; i++) cout << n ; cout << mx; c = 0; int k = mx - 1; while (s.find(k) != s.end()) { cout << << k; s.erase(k); k--; } cout << n ; mx = k; } else { s.insert(d); c++; } } return 0; } |
module FSM_Ctrol (
input RST, // Reset maestro
input CLK, // Reloj maestro
input STM, // Iniciar multiplicacion
output reg ENpH, // Habilitaciones Rp Alto
output reg ENpL, // Habilitaciones Rp Bajo
output reg ENa, // Habilitaciones Ra
output reg ENr, // Habilitaciones Rr
output reg SEL, // Selector Mux
output reg EOM // Fin de multiplicacion
);
reg[2:0] Qp,Qn;
always @ *
begin : Combinacional
case (Qp)
3'b000 : begin // Idle
if (STM)
Qn = 3'b001;
else
Qn = Qp;
ENpH = 1'b0;
ENpL = 1'b0;
ENa = 1'b0;
ENr = 1'b0;
SEL = 1'b0;
EOM = 1'b1;
end
3'b001 : begin
Qn = 3'b010;
ENpH = 1'b1;
ENpL = 1'b0;
ENa = 1'b0;
ENr = 1'b0;
SEL = 1'b0;
EOM = 1'b0;
end
3'b010 : begin
Qn = 3'b011;
ENpH = 1'b0;
ENpL = 1'b1;
ENa = 1'b1;
ENr = 1'b0;
SEL = 1'b0;
EOM = 1'b0;
end
3'b011 : begin
Qn = 3'b000;
ENpH = 1'b0;
ENpL = 1'b0;
ENa = 1'b1;
ENr = 1'b1;
SEL = 1'b1;
EOM = 1'b0;
end
// 3'b100 : begin
// Qn = 3'b000;
// ENpH = 1'b0;
// ENpL = 1'b0;
// ENa = 1'b0;
// ENr = 1'b1;
// SEL = 1'b0;
// end
endcase
end
always @ (posedge RST or posedge CLK)
begin : Secuencial
if (RST)
Qp <= 0;
else
Qp <= Qn;
end
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// Bus address filter - squash any cycle within ranges
//
module rcn_filter
(
input clk,
input rst,
input [68:0] rcn_in,
output [68:0] rcn_out,
output reg filtered
);
parameter START_0 = 1;
parameter END_0 = 0;
parameter START_1 = 1;
parameter END_1 = 0;
parameter START_2 = 1;
parameter END_2 = 0;
parameter START_3 = 1;
parameter END_3 = 0;
reg [68:0] rin;
reg [68:0] rout;
assign rcn_out = rout;
wire [23:0] addr_start_0 = START_0;
wire [23:0] addr_end_0 = END_0;
wire filter_0 = (rin[55:34] >= addr_start_0) && (rin[55:34] <= addr_end_0);
wire [23:0] addr_start_1 = START_1;
wire [23:0] addr_end_1 = END_1;
wire filter_1 = (rin[55:34] >= addr_start_1) && (rin[55:34] <= addr_end_1);
wire [23:0] addr_start_2 = START_2;
wire [23:0] addr_end_2 = END_2;
wire filter_2 = (rin[55:34] >= addr_start_2) && (rin[55:34] <= addr_end_2);
wire [23:0] addr_start_3 = START_3;
wire [23:0] addr_end_3 = END_3;
wire filter_3 = (rin[55:34] >= addr_start_3) && (rin[55:34] <= addr_end_3);
always @ (posedge clk or posedge rst)
if (rst)
begin
rin <= 69'd0;
rout <= 69'd0;
filtered <= 1'b0;
end
else
begin
rin <= rcn_in;
rout <= (filter_0 || filter_1 || filter_2 || filter_3) ? 69'd0 : rcn_in;
filtered <= (filter_0 || filter_1 || filter_2 || filter_3);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m, x, y; cin >> n >> m >> x >> y; char a[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } } int county = 0, count = 0; if (2 * x > y) { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == . ) count++; if (j != m - 1) { if (a[i][j] == a[i][j + 1] && a[i][j] == . ) { county++; j++; } } } } cout << (county * y) + (count - county) * x; } else { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == . ) count++; } } cout << count * x; } cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; void matches(vector<int> arr) { int i; for (i = 0; i < arr.size(); i++) { if (arr[i] == 2) cout << 2 << endl; else if (arr[i] % 2 == 0 && arr[i] != 2) cout << 0 << endl; else cout << 1 << endl; } } int main() { int i, n; cin >> n; vector<int> arr(n); for (i = 0; i < n; i++) { cin >> arr[i]; } matches(arr); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int k, t; int a[11]; long long b[16], c[11], ele[11], hash_val; map<pair<int, long long>, long long> vis; void add(int i) { c[b[i]]--; hash_val -= ele[b[i]]; b[i]++; c[b[i]]++; hash_val += ele[b[i]]; } void remove(int i) { c[b[i]]--; hash_val -= ele[b[i]]; b[i]--; c[b[i]]++; hash_val += ele[b[i]]; } long long find(int ind) { if (ind == 11) return 1; pair<int, long long> mp = make_pair(ind, hash_val); if (vis.find(mp) != vis.end()) return vis[mp]; long long ans = 0; for (int i = 0; i < 16; i++) { if (b[i] >= t) continue; add(i); ans += find(ind + 1); remove(i); } vis[mp] = ans; return ans; } int main() { scanf( %d%d , &k, &t); ele[0] = 1; for (int i = 1; i < 11; i++) ele[i] = 17 * ele[i - 1]; if (t == 10) { printf( %x n , k); return 0; } c[0] = 16; hash_val = 16; int fir = 10; add(1); for (int i = 10; i > 0; i--) { long long x = 15ll * find(i + 1); if (k <= x) { fir = i; break; } else k -= x; } remove(1); for (int i = fir; i <= 10; i++) { for (int j = 0; j < 16; j++) { if (j == 0 and i == fir) continue; if (b[j] == t) continue; add(j); long long x = find(i + 1); if (k > x) { k -= x; remove(j); } else { a[i] = j; break; } } } int i = fir; while (i <= 10) { if (a[i] < 10) printf( %d , a[i]); else printf( %c , a + a[i] - 10); i++; } printf( n ); } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 2000005; int n, m; int in[MAX_N]; int inv[MAX_N]; int out[MAX_N], temp[MAX_N]; int pos2bckt[MAX_N]; int bckt[MAX_N], relabel[MAX_N]; int bpos[MAX_N]; void build() { for (int i = 0; i < n; i++) out[i] = i; sort(out, out + n, [](int a, int bckt) { return in[a] < in[bckt]; }); for (int i = 0, c = 0; i < n; i++) { bckt[i] = c; if (i + 1 == n || in[out[i]] != in[out[i + 1]]) c++; } for (int h = 1; h < n; h <<= 1) { for (int i = 0; i < n; i++) pos2bckt[out[i]] = bckt[i]; for (int i = n - 1; i >= 0; i--) bpos[bckt[i]] = i; for (int i = 0; i < n; i++) if (out[i] >= n - h) temp[bpos[bckt[i]]++] = out[i]; for (int i = 0; i < n; i++) if (out[i] >= h) temp[bpos[pos2bckt[out[i] - h]]++] = out[i] - h; for (int i = 0, c = 0; i < n; i++) { relabel[i] = c; if (i + 1 == n) break; if (bckt[i] != bckt[i + 1]) c++; else if (temp[i + 1] >= n - h || temp[i] >= n - h) c++; else if (pos2bckt[temp[i + 1] + h] != pos2bckt[temp[i] + h]) c++; } memcpy(out, temp, sizeof(temp[0]) * n); memcpy(bckt, relabel, sizeof(relabel[0]) * n); } } char str[MAX_N]; int cnt[MAX_N], mmn[MAX_N], rmmn[MAX_N]; int main() { scanf( %s , str); while (str[n]) n++; for (int i = 0; i < n; i++) in[i] = str[i] == ) ; for (int i = 0; i < n; i++) in[i + n] = in[i]; int step = 0, mn = 0; for (int i = 0; i < n; i++) { if (in[i] == 1) step--; else step++; cnt[i + 1] = step; if (mn > step) mn = step; mmn[i + 1] = mn; } int p = step; for (int i = n - 1; i >= 0; i--) { if (in[i] == 1) step++; else step--; if (p > step) p = step; rmmn[i] = p; } n *= 2; build(); n /= 2; int c[2] = { 0, }; for (int i = 0; i < n; i++) c[in[i]]++; if (c[0] >= c[1]) { for (int i = 0; i < 2 * n; i++) { if (out[i] < n && rmmn[out[i]] - cnt[out[i]] >= 0 && cnt[n] - cnt[out[i]] + mmn[out[i]] >= 0) { for (int j = 0; j < n; j++) str[j] = in[out[i] + j] == 0 ? ( : ) ; for (int j = n, k = 0; k < c[0] - c[1]; j++, k++) str[j] = ) ; break; } } } else { for (int i = 0; i < 2 * n; i++) { if (out[i] < n && rmmn[out[i]] - cnt[out[i]] >= c[0] - c[1] && cnt[n] - cnt[out[i]] + mmn[out[i]] >= c[0] - c[1]) { for (int j = 0; j < c[1] - c[0]; j++) str[j] = ( ; for (int j = c[1] - c[0], k = 0; k < n; j++, k++) str[j] = in[out[i] + k] == 0 ? ( : ) ; break; } } } puts(str); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; char c; int sum = 0; if (n % 2 == 0) { int f = 1; for (int i = 1; i <= n; i++) { cin >> c; if (c == ( ) sum++; else sum--; if (sum < -1) break; } if (sum != 0) f = 0; if (f) cout << Yes n ; else cout << No n ; } else cout << No n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NOR4_FUNCTIONAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4 (
VPWR,
VGND,
Y ,
A ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C ;
input D ;
// Local signals
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int x, y, n, tx, ty, m; scanf( %d %d , &n, &m); double res = 0; for (int i = 0; i < n; i++) { scanf( %d %d , &x, &y); if (i == 0) { tx = x, ty = y; continue; } res = res + sqrt(((x - tx) * (x - tx)) + ((y - ty) * (y - ty))); tx = x, ty = y; } if (n == 1) { res = res + abs(x - y); printf( %.9f n , res); } else { printf( %.9f n , (res / 50.0) * m); } return 0; } |
#include <bits/stdc++.h> using namespace std; int N, M; typedef struct node { double x; double y; node operator-(node b) { node ret; ret.x = x - b.x; ret.y = y - b.y; return ret; } node operator+(node b) { node ret; ret.x = x + b.x; ret.y = y + b.y; return ret; } node operator/(double c) { node ret; ret.x = x / c; ret.y = y / c; return ret; } node operator*(double c) { node ret; ret.x = x * c; ret.y = y * c; return ret; } } node; double xmul(node a, node b) { return a.x * b.y - b.x * a.y; } void getit(double &A, double &B, double &C, node a, node b) { double At = b.y - a.y; double Bt = a.x - b.x; A = -Bt; B = At; double x = (a.x + b.x) / 2; double y = (a.y + b.y) / 2; C = A * x + B * y; } node getcenter(node A, node B, node C) { double A1, B1, C1; getit(A1, B1, C1, A, B); double A2, B2, C2; getit(A2, B2, C2, B, C); double det = A1 * B2 - A2 * B1; node ret; ret.x = (B2 * C1 - B1 * C2) / det; ret.y = (A1 * C2 - A2 * C1) / det; return ret; } bool solve(node a, node b, node c) { node A = b * 2 - a; node F = getcenter(A, b, c); node G = c * 2 - F; node E = b * 2 - F; node D = a * 2 - E; if (xmul(E - D, F - E) < 1e-7 || xmul(F - E, G - F) < 1e-7 || xmul(G - F, D - G) < 1e-7 || xmul(D - G, E - D) < 1e-7) return false; printf( YES n%.9lf %.9lf %.9lf %.9lf %.9lf %.9lf %.9lf %.9lf n , D.x, D.y, E.x, E.y, F.x, F.y, G.x, G.y); return true; } int main() { int T; scanf( %d , &T); while (T--) { node a, b, c; scanf( %lf%lf%lf%lf%lf%lf , &a.x, &a.y, &b.x, &b.y, &c.x, &c.y); if (fabs(xmul(a - c, b - c)) < 1e-7 || !solve(a, b, c) && !solve(a, c, b) && !solve(c, a, b) && !solve(c, b, a) && !solve(b, a, c) && !solve(b, c, a)) printf( NO n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, x(0); cin >> n; string s; while (n--) { cin >> s; if (s[1] == + ) { ++x; } else { --x; } } cout << x << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, k, i, j, total, cnt; cin >> n >> k; double r, g, b; r = ceil((n * 2.0) / k); g = ceil((n * 5.0) / k); b = ceil((n * 8.0) / k); cout << int(r + g + b) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; scanf( %d%d%d%d , &a, &b, &c, &d); double r = (1 - 1.0 * a / b) * (1 - 1.0 * c / d); r = 1.0 / (1 - r); printf( %.10f n , r * a / b); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A311O_BEHAVIORAL_V
`define SKY130_FD_SC_HS__A311O_BEHAVIORAL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire B1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A311O_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; char s[500005], t[500005]; long long ans; int n, k, now, tmp; int main() { scanf( %d %d n , &n, &k); fread(s + 1, 1, n, stdin); getchar(); fread(t + 1, 1, n, stdin); s[n + 1] = # ; if (k == 1) return printf( %d n , n), 0; for (now = 1; s[now] == t[now]; now++) ; if (now > n) return printf( %d n , n), 0; ans = now + 1; for (int i = now + 1; i <= n; i++) { tmp = tmp << 1; if (s[i] == a ) tmp++; if (t[i] == b ) tmp++; tmp = min(k - 2, tmp); ans += tmp + 2; } printf( %lld n , ans); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long dpf[110][100][60]; long long dpg[110][100][60]; int diff; int likes_init = 0; const long long mod = 998244353; long long fast_exp(long long b, int e) { b = b % mod; if (e == 0) return 1; if (e == 1) return b; if (e % 2 == 1) return (b * fast_exp(b, e - 1)) % mod; return fast_exp((b * b) % mod, e / 2); } long long modinv(long long x) { assert(x % mod != 0); return fast_exp(x, mod - 2); } long long f(int curr, int likes, int runs) { if (dpf[curr][likes - likes_init][runs] == 1LL << 40) { int dislike = likes + runs - diff; if (curr == 0) return 0; if (runs == 0) { return curr; } if (dislike < 0) return 0; long long tmp1, tmp2, tmp3; tmp1 = (curr == 0 ? 0 : curr * f(curr + 1, likes + 1, runs - 1)); tmp2 = (likes - curr == 0 ? 0 : (likes - curr) * f(curr, likes + 1, runs - 1)); tmp3 = (dislike == 0 ? 0 : dislike * f(curr, likes, runs - 1)); long long tmp = (tmp1 + tmp2 + tmp3) % mod; long long ans = (tmp * modinv(likes + dislike)) % mod; return dpf[curr][likes - likes_init][runs] = ans; } else { return dpf[curr][likes - likes_init][runs]; } } long long g(int curr, int likes, int runs) { if (dpg[curr][likes - likes_init][runs] == 1LL << 40) { int dislike = likes + runs - diff; if (curr == 0) return 0; if (runs == 0) { return curr; } if (dislike < 0) return 0; long long tmp1 = (curr == 0 ? 0 : curr * g(curr - 1, likes, runs - 1)); long long tmp2 = (likes == 0 ? 0 : likes * g(curr, likes + 1, runs - 1)); long long tmp3 = (dislike - curr == 0 ? 0 : (dislike - curr) * g(curr, likes, runs - 1)); long long tmp = (tmp1 + tmp2 + tmp3) % mod; long long ans = (tmp * modinv(likes + dislike)) % mod; return dpg[curr][likes - likes_init][runs] = ans; } else { return dpg[curr][likes - likes_init][runs]; } } int main() { int n, m; cin >> n >> m; diff = m; int a[n]; for (int i = 0; i < 110; i++) { for (int j = 0; j < 100; j++) { for (int k = 0; k < 60; k++) { dpf[i][j][k] = 1LL << 40; dpg[i][j][k] = 1LL << 40; } } } bool good[n]; int tl = 0; for (int i = 0; i < n; i++) { cin >> good[i]; } for (int i = 0; i < n; i++) { cin >> a[i]; if (good[i]) { diff += a[i]; tl += a[i]; } else diff -= a[i]; } likes_init = tl; for (int i = 0; i < n; i++) { if (good[i]) { cout << (f(a[i], tl, m) % mod + mod) % mod << n ; } else { cout << (g(a[i], tl, m) % mod + mod) % mod << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0; char ch = getchar(); bool positive = 1; for (; !isdigit(ch); ch = getchar()) if (ch == - ) positive = 0; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 0 ; return positive ? x : -x; } inline void write(int a) { if (a >= 10) write(a / 10); putchar( 0 + a % 10); } inline void writeln(int a) { write(a); puts( ); } int n, ans; struct data { int bo; string first; }; map<string, data> M; const int N = 1005; string a[N], b[N], t; map<string, bool> MM; int main() { n = read(); for (int i = 1; i <= n; i++) { cin >> a[i] >> b[i]; if (M[a[i]].bo) t = M[a[i]].first; else t = a[i]; M[a[i]] = (data){0, a[i]}; M[b[i]] = (data){1, t}; } for (int i = 1; i <= n; i++) { if (MM[b[i]]) continue; else MM[b[i]] = 1; if (M[b[i]].bo) ans++; } MM.clear(); writeln(ans); for (int i = 1; i <= n; i++) if (M[b[i]].bo && MM[b[i]] == 0) { MM[b[i]] = 1; cout << M[b[i]].first << << b[i] << endl; } } |
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: udp_lfsr.v,v 1.1 2001/10/27 23:38:29 sib4 Exp $
module test_lfsr;
reg cp;
reg in;
wire out;
reg reset;
lfsr sr(cp, reset, in, out);
reg errors;
initial errors = 0;
integer i;
initial
begin
in = 0;
cp = 0;
#2 reset = 1;
#2 reset = 0;
#1;
for (i=0; i<512; i=i+1)
#5 cp = ~cp;
in = 0;
cp = 0;
#2 reset = 1;
#2 reset = 0;
#1;
for (i=0; i<512; i=i+1)
#5 cp <= ~cp;
#5;
if (errors == 0)
$display("PASSED");
#10 $finish;
end
reg [7:0] here;
reg [7:0] next;
reg [7:0] old;
reg [7:0] new;
always @(reset)
if (reset)
begin
here = 1;
#1;
old = {out, sr.s};
if (old === here)
begin
$display("%b RESET", old);
end
else
begin
$display("%b RESET FAILED: expect %b", old, here);
errors = 1;
end
end
always
begin
@(posedge cp) old = {out, sr.s};
next = {here[6:0], ^(here & sr.P) ^ in};
@(negedge cp) new = {out, sr.s};
if (old != here || new !== next)
begin
$display("%b->%b FAILED: expect %b->%b", old, new, here, next);
errors = 1;
end
else
begin
$display("%b->%b", old, new);
end
here = next;
end
endmodule
module lfsr (clk, reset, in, out);
parameter P = 8'b 1101_1001;
input clk;
input reset;
input in;
output out;
wire [6:0] s;
wire i = ^{P & {out,s}} ^ in;
jkff ff1 (s[0], clk, i, ~i, reset, 0);
jkff ff2 (s[1], clk, s[0], ~s[0], 0, reset);
jkff ff3 (s[2], clk, s[1], ~s[1], 0, reset);
jkff ff4 (s[3], clk, s[2], ~s[2], 0, reset);
jkff ff8 (out, clk, s[6], ~s[6], 0, reset);
jkff ff7 (s[6], clk, s[5], ~s[5], 0, reset);
jkff ff6 (s[5], clk, s[4], ~s[4], 0, reset);
jkff ff5 (s[4], clk, s[3], ~s[3], 0, reset);
endmodule
primitive jkff(q, cp, j, k, s, r);
output q;
input cp, j, k, s, r;
reg q;
table
// (cp) j k s r : q : q ;
? ? ? (?0) 0 : ? : - ;
? ? ? 0 (?0) : ? : - ;
? * ? 0 0 : ? : - ;
? ? * 0 0 : ? : - ;
? ? ? 1 0 : ? : 1 ;
? ? ? 0 1 : ? : 0 ;
? ? ? x 0 : 1 : 1 ;
? ? ? 0 x : 0 : 0 ;
(?0) ? ? 0 0 : ? : - ;
(1x) ? ? 0 0 : ? : - ;
(?1) 0 ? 0 0 : 0 : 0 ;
(?1) ? 0 0 0 : 1 : 1 ;
(0x) 0 ? 0 0 : 0 : 0 ;
(0x) ? 0 0 0 : 1 : 1 ;
(01) 1 ? 0 0 : 0 : 1 ;
(01) ? 1 0 0 : 1 : 0 ;
(01) 1 0 0 0 : x : 1 ;
(01) 0 1 0 0 : x : 0 ;
endtable
endprimitive
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cluster_header.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// The cluster header is instatiated as a hard macro.
// This model is for simulation only.
`include "sys.h"
`include "m1.behV"
`include "u1.behV"
module cluster_header (/*AUTOARG*/
// Outputs
dbginit_l, cluster_grst_l, rclk, so,
// Inputs
gclk, cluster_cken, arst_l, grst_l, adbginit_l, gdbginit_l, si,
se
);
input gclk;
input cluster_cken;
input arst_l;
input grst_l;
input adbginit_l;
input gdbginit_l;
output dbginit_l;
output cluster_grst_l;
output rclk;
input si; // scan ports for reset flop repeaters
input se;
output so;
`ifdef FPGA_SYN
// assign #10 rclk = gclk;
// assign #10 dbginit_l = gdbginit_l;
// assign #10 cluster_grst_l = grst_l;
// assign so = 1'b0;
reg dbginit_l;
reg cluster_grst_l;
assign #10 rclk = gclk;
always @(negedge rclk) begin
dbginit_l <= gdbginit_l;
cluster_grst_l <= grst_l;
end
`else
wire pre_sync_enable;
wire sync_enable;
wire cluster_grst_l;
wire dbginit_l;
wire rst_sync_so;
bw_u1_syncff_4x sync_cluster_master ( // no scan hook-up
.so(),
.q (pre_sync_enable),
.ck (gclk),
.d (cluster_cken),
.sd(1'b0),
.se(1'b0)
);
bw_u1_scanl_2x sync_cluster_slave ( // use scan lock-up latch
.so (sync_enable),
.ck (gclk),
.sd (pre_sync_enable)
);
// NOTE! Pound delay in the below statement is meant to provide 10 ps
// delay between gclk and rclk to allow the synchronizer for rst, dbginit,
// and sync pulses to be modelled accurately. gclk and rclk need to have
// at least one simulator timestep separation to allow the flop->flop
// synchronizer to work correctly.
assign #10 rclk = gclk & sync_enable;
synchronizer_asr rst_repeater (
.sync_out(cluster_grst_l),
.so(rst_sync_so),
.async_in(grst_l),
.gclk(gclk),
.rclk(rclk),
.arst_l(arst_l),
.si(si),
.se(se)
);
synchronizer_asr dbginit_repeater (
.sync_out(dbginit_l),
.so(so),
.async_in(gdbginit_l),
.gclk(gclk),
.rclk(rclk),
.arst_l(adbginit_l),
.si(rst_sync_so),
.se(se)
);
`endif
endmodule // cluster_header
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:19:56 05/01/2013
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module max_short(
input [15:0] x,
input [15:0] y,
output [15:0] z
);
assign z = ( y > x) ? y : x;
endmodule
module max_byte(
input [7:0] x,
input [7:0] y,
output [7:0] z
);
assign z = ( y > x) ? y : x;
endmodule
module max_nibble(
input [3:0] x,
input [3:0] y,
output [3:0] z
);
assign z = ( y > x) ? y : x;
endmodule
module fiveminusmax0(
input [3:0] i,
output [3:0] o
);
wire [4:0] fiveminus;
assign fiveminus = 5'd5 - {1'b0,i};
assign o = ( !fiveminus[4]) ? fiveminus[3:0] : 4'b0;
endmodule
module unit(
input [1:0] select_ms,
input [3:0] L, /* -6 <= L,U <= 7 */
input [3:0] U,
input [3:0] Y, /* 0 <= Y,Z <= 13 */
input [3:0] Z,
output [3:0] Lp,
output [3:0] Up,
output [3:0] Yp,
output [3:0] Zp
);
/*
fy = max( 0, 5-y)
fz = max( 0, 5-z)
sb = L+fy
sc = U+fz
sd = max( ms+6,sb,sc) , ms+6 in {2,5,7}
d = sd - 6
L' = d-U
U' = d-L
Y' = sd-sb
Z' = sd-sc
*/
wire [3:0] fy;
fiveminusmax0 gen_fy( .i(Y), .o(fy));
wire [3:0] fz;
fiveminusmax0 gen_fz( .i(Z), .o(fz));
wire [3:0] ms_plus_6;
assign ms_plus_6 = ( select_ms == 2'b00) ? 4'd2 : (( select_ms == 2'b01) ? 4'd5 : 4'd7);
wire [3:0] sb;
wire [3:0] sc;
wire [3:0] sd;
wire [3:0] d;
wire [3:0] sb_max_sc;
wire dummyy;
wire dummyz;
assign sb = L + fy;
assign sc = U + fz;
assign sb_max_sc = ( sb > sc) ? sb : sc;
assign sd = ( sb_max_sc > ms_plus_6) ? sb_max_sc : ms_plus_6;
assign d = sd - 4'd6;
assign Lp = d - U;
assign Up = d - L;
assign {dummyy,Yp} = {sd[3],sd} - {sb[3],sb};
assign {dummyz,Zp} = {sd[3],sd} - {sc[3],sc};
endmodule
module unitfull(
input [1:0] select_ms,
input [7:0] Hmm,
input [7:0] Hmc,
input [7:0] Hcm,
input [7:0] Ecm,
input [7:0] Fmc,
output [7:0] Hcc,
output [7:0] Ecc,
output [7:0] Fcc
);
/*
Hcc = max( Hmm + ms, Ecc, Fcc)
Ecc = max( Hcm - 6, Ecm - 1)
Fcc = max( Hmc - 6, Fmc - 1)
*/
wire [7:0] Hcc0;
wire [7:0] Ecc0;
wire [7:0] Ecc1;
wire [7:0] Fcc0;
wire [7:0] Fcc1;
wire [7:0] ms;
assign ms = ( select_ms == 2'b00) ? -8'd4 : (( select_ms == 2'b01) ? -8'd1 : 8'd1);
assign Hcc0 = Hmm + ms;
assign Ecc0 = Hcm - 8'd6;
assign Ecc1 = Ecm - 8'd1;
assign Fcc0 = Hmc - 8'd6;
assign Fcc1 = Fmc - 8'd1;
wire [7:0] Ecc_max_Fcc;
assign Ecc_max_Fcc = ( Ecc > Fcc) ? Ecc : Fcc;
assign Hcc = ( Hcc0 > Ecc_max_Fcc) ? Hcc0 : Ecc_max_Fcc;
assign Ecc = ( Ecc0 > Ecc1) ? Ecc0 : Ecc1;
assign Fcc = ( Fcc0 > Fcc1) ? Fcc0 : Fcc1;
endmodule
module top(
input USER_CLOCK,
output [3:0] z
);
wire clk;
clockdrv clockdrv
(// Clock in ports
.CLK_IN1(USER_CLOCK), // IN
// Clock out ports
.CLK_OUT1(clk)); // OUT
reg [41:0] state;
assign z = state[27:24];
always @(posedge clk)
begin
state = state + 1;
end
//wire [15:0] short1;
//wire [15:0] short0;
//assign { short1, short0} = state;
//wire [15:0] short_max;
//max_short max_short( .x(short0), .y(short1), .z(short_max));
wire [3:0] L;
wire [3:0] U;
wire [3:0] Y;
wire [3:0] Z;
wire [3:0] Lp;
wire [3:0] Up;
wire [3:0] Yp;
wire [3:0] Zp;
wire [1:0] select_ms;
unit unit( .select_ms(select_ms), .L(L), .U(U), .Y(Y), .Z(Z), .Lp(Lp), .Up(Up), .Yp(Yp), .Zp(Zp));
//wire [7:0] Hmm;
//wire [7:0] Hmc;
//wire [7:0] Hcm;
//wire [7:0] Ecm;
//wire [7:0] Fmc;
//wire [7:0] Hcc;
//wire [7:0] Ecc;
//wire [7:0] Fcc;
//unitfull unit( .select_ms(select_ms), .Hmm(Hmm), .Hmc(Hmc), .Hcm(Hcm), .Ecm(Ecm), .Fmc(Fmc), .Hcc(Hcc), .Ecc(Ecc), .Fcc(Fcc));
//wire [7:0] byte1;
//wire [7:0] byte0;
//assign {byte1, byte0} = state[15:0];
//wire [7:0] byte_max;
//max_byte max_byte( .x(byte0), .y(byte1), .z(byte_max));
//wire [3:0] nibble2;
//wire [3:0] nibble1;
//wire [3:0] nibble0;
//assign nibble2 = 4'd5;
//assign {nibble1,nibble0} = state[7:0];
//wire [3:0] nibble_max;
// wire [3:0] yy;
//max_nibble max_nibble( .x(nibble0), .y(nibble1), .z(nibble_max));
// assign yy = ( y > nibble2) ? y : nibble2;
wire [35:0] CONTROL0;
wire [35:0] CONTROL1;
wire [31:0] combout0;
wire [31:0] combout1;
wire [31:0] combin0;
wire [31:0] combin1;
assign {select_ms,L,U,Y,Z} = combin0[17:0];
assign combout0 = {16'b0,Lp,Up,Yp,Zp};
assign combout1 = 32'b0;
//assign {Hmc,Hcm,Ecm,Fmc} = combin0;
//assign {select_ms,Hmm} = combin1[9:0];
//assign combout0 = { 8'b0, Hcc, Ecc, Fcc};
//assign combout1 = 32'b0;
//assign {select_ms,Hmm,Hmc,Hcm,Ecm,Fmc} = state[41:0];
//wire [31:0] trig0;
//assign trig0 = { L, U, Y, Z, Lp, Up, Yp, Zp};
//assign trig0 = { 8'b0, Hcc, Ecc, Fcc};
icon2 icon2 (
.CONTROL0(CONTROL0), // INOUT BUS [35:0]
.CONTROL1(CONTROL1) // INOUT BUS [35:0]
);
vio vio0 (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.ASYNC_IN(combout0), // IN BUS [31:0]
.ASYNC_OUT(combin0) // OUT BUS [31:0]
);
vio vio1 (
.CONTROL(CONTROL1), // INOUT BUS [35:0]
.ASYNC_IN(combout1), // IN BUS [31:0]
.ASYNC_OUT(combin1) // OUT BUS [31:0]
);
endmodule
|
/*
Copyright (c) 2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 125MHz
*/
input wire CLOCK_50,
/*
* GPIO
*/
input wire [3:0] KEY,
input wire [17:0] SW,
output wire [8:0] LEDG,
output wire [17:0] LEDR,
output wire [6:0] HEX0,
output wire [6:0] HEX1,
output wire [6:0] HEX2,
output wire [6:0] HEX3,
output wire [6:0] HEX4,
output wire [6:0] HEX5,
output wire [6:0] HEX6,
output wire [6:0] HEX7,
output wire [35:0] GPIO,
/*
* Ethernet: 1000BASE-T RGMII
*/
output wire ENET0_GTX_CLK,
output wire [3:0] ENET0_TX_DATA,
output wire ENET0_TX_EN,
input wire ENET0_RX_CLK,
input wire [3:0] ENET0_RX_DATA,
input wire ENET0_RX_DV,
output wire ENET0_RST_N,
input wire ENET0_INT_N,
output wire ENET1_GTX_CLK,
output wire [3:0] ENET1_TX_DATA,
output wire ENET1_TX_EN,
input wire ENET1_RX_CLK,
input wire [3:0] ENET1_RX_DATA,
input wire ENET1_RX_DV,
output wire ENET1_RST_N,
input wire ENET1_INT_N
);
// Clock and reset
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire pll_rst = ~KEY[3];
wire pll_locked;
wire clk90_int;
altpll #(
.bandwidth_type("AUTO"),
.clk0_divide_by(2),
.clk0_duty_cycle(50),
.clk0_multiply_by(5),
.clk0_phase_shift("0"),
.clk1_divide_by(2),
.clk1_duty_cycle(50),
.clk1_multiply_by(5),
.clk1_phase_shift("2000"),
.compensate_clock("CLK0"),
.inclk0_input_frequency(20000),
.intended_device_family("Cyclone IV E"),
.operation_mode("NORMAL"),
.pll_type("AUTO"),
.port_activeclock("PORT_UNUSED"),
.port_areset("PORT_USED"),
.port_clkbad0("PORT_UNUSED"),
.port_clkbad1("PORT_UNUSED"),
.port_clkloss("PORT_UNUSED"),
.port_clkswitch("PORT_UNUSED"),
.port_configupdate("PORT_UNUSED"),
.port_fbin("PORT_UNUSED"),
.port_inclk0("PORT_USED"),
.port_inclk1("PORT_UNUSED"),
.port_locked("PORT_USED"),
.port_pfdena("PORT_UNUSED"),
.port_phasecounterselect("PORT_UNUSED"),
.port_phasedone("PORT_UNUSED"),
.port_phasestep("PORT_UNUSED"),
.port_phaseupdown("PORT_UNUSED"),
.port_pllena("PORT_UNUSED"),
.port_scanaclr("PORT_UNUSED"),
.port_scanclk("PORT_UNUSED"),
.port_scanclkena("PORT_UNUSED"),
.port_scandata("PORT_UNUSED"),
.port_scandataout("PORT_UNUSED"),
.port_scandone("PORT_UNUSED"),
.port_scanread("PORT_UNUSED"),
.port_scanwrite("PORT_UNUSED"),
.port_clk0("PORT_USED"),
.port_clk1("PORT_USED"),
.port_clk2("PORT_UNUSED"),
.port_clk3("PORT_UNUSED"),
.port_clk4("PORT_UNUSED"),
.port_clk5("PORT_UNUSED"),
.port_clkena0("PORT_UNUSED"),
.port_clkena1("PORT_UNUSED"),
.port_clkena2("PORT_UNUSED"),
.port_clkena3("PORT_UNUSED"),
.port_clkena4("PORT_UNUSED"),
.port_clkena5("PORT_UNUSED"),
.port_extclk0("PORT_UNUSED"),
.port_extclk1("PORT_UNUSED"),
.port_extclk2("PORT_UNUSED"),
.port_extclk3("PORT_UNUSED"),
.self_reset_on_loss_lock("ON"),
.width_clock(5)
)
altpll_component (
.areset(pll_rst),
.inclk({1'b0, CLOCK_50}),
.clk({clk90_int, clk_int}),
.locked(pll_locked),
.activeclock(),
.clkbad(),
.clkena({6{1'b1}}),
.clkloss(),
.clkswitch(1'b0),
.configupdate(1'b0),
.enable0(),
.enable1(),
.extclk(),
.extclkena({4{1'b1}}),
.fbin(1'b1),
.fbmimicbidir(),
.fbout(),
.fref(),
.icdrclk(),
.pfdena(1'b1),
.phasecounterselect({4{1'b1}}),
.phasedone(),
.phasestep(1'b1),
.phaseupdown(1'b1),
.pllena(1'b1),
.scanaclr(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0),
.scandataout(),
.scandone(),
.scanread(1'b0),
.scanwrite(1'b0),
.sclkout0(),
.sclkout1(),
.vcooverrange(),
.vcounderrange()
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~pll_locked),
.out(rst_int)
);
// GPIO
wire [3:0] btn_int;
wire [17:0] sw_int;
debounce_switch #(
.WIDTH(4+18),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({~KEY,
SW}),
.out({btn_int,
sw_int})
);
fpga_core #(
.TARGET("ALTERA")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.clk90(clk90_int),
.rst(rst_int),
/*
* GPIO
*/
.btn(btn_int),
.sw(sw_int),
.ledg(LEDG),
.ledr(LEDR),
.hex0(HEX0),
.hex1(HEX1),
.hex2(HEX2),
.hex3(HEX3),
.hex4(HEX4),
.hex5(HEX5),
.hex6(HEX6),
.hex7(HEX7),
.gpio(GPIO),
/*
* Ethernet: 1000BASE-T RGMII
*/
.phy0_rx_clk(ENET0_RX_CLK),
.phy0_rxd(ENET0_RX_DATA),
.phy0_rx_ctl(ENET0_RX_DV),
.phy0_tx_clk(ENET0_GTX_CLK),
.phy0_txd(ENET0_TX_DATA),
.phy0_tx_ctl(ENET0_TX_EN),
.phy0_reset_n(ENET0_RST_N),
.phy0_int_n(ENET0_INT_N),
.phy1_rx_clk(ENET1_RX_CLK),
.phy1_rxd(ENET1_RX_DATA),
.phy1_rx_ctl(ENET1_RX_DV),
.phy1_tx_clk(ENET1_GTX_CLK),
.phy1_txd(ENET1_TX_DATA),
.phy1_tx_ctl(ENET1_TX_EN),
.phy1_reset_n(ENET1_RST_N),
.phy1_int_n(ENET1_INT_N)
);
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; int main() { int n, c, a, b; scanf( %d %d %d %d , &n, &c, &a, &b); a--; b--; int ca = a % c, cb = b % c; if (ca == 0) { if ((cb == (c - 1)) or b == (n - 1)) printf( 1 n ); else if (b / c == a / c) printf( 1 n ); else printf( 2 n ); } else if (cb == (c - 1)) { if (b / c == a / c) printf( 1 n ); else printf( 2 n ); } else if (a / c == b / c) printf( 1 n ); else if (b / c == a / c + 1) printf( 2 n ); else if (b == (n - 1)) printf( 2 n ); else if (b % c == (a % c) - 1) printf( 2 n ); else printf( 3 n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 2e3 + 10, INF = 1e9 + 10; long long dp[N][2], a[N], n, k; inline bool check(long long x) { for (long long i = 1; i <= n; i++) dp[i][0] = i - 1; for (long long i = 1; i <= n; i++) for (long long j = i - 1; j; --j) { if (a[i] + (i - j) * x < a[j] || a[i] - (i - j) * x > a[j]) continue; dp[i][0] = min(dp[i][0], dp[j][0] + i - j - 1); } for (long long i = n; i; i--) dp[i][1] = n - i; for (long long i = n; i; i--) for (long long j = i + 1; j <= n; ++j) { if (a[i] + (j - i) * x < a[j] || a[i] - (j - i) * x > a[j]) continue; dp[i][1] = min(dp[i][1], dp[j][1] + j - i - 1); } for (long long i = 1; i <= n; i++) if (dp[i][0] + dp[i][1] <= k) return 1; return 0; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> k; if (k == n) return cout << 0 , 0; for (long long i = 1; i <= n; i++) cin >> a[i]; long long lo = 0, hi = 2e9 + 5; while (hi - lo > 0) { long long mid = (hi + lo) / 2; if (check(mid)) hi = mid; else lo = mid + 1; } cout << lo; return 0; } |
module Online_test1(
// Input signals
clk,
rst_n,
in_valid,
in,
mode,
// Output signals
out_valid,
out
);
//---------------------------------------------------------------------
// INPUT AND OUTPUT DECLARATION
//---------------------------------------------------------------------
input clk;
input rst_n;
input [3:0] in;
input in_valid;
input [1:0] mode;
output reg [10:0] out;
output reg out_valid;
//---------------------------------------------------------------------
// PARAMETER DECLARATION
//---------------------------------------------------------------------
parameter INIT = 3'd0;
parameter INPUT = 3'd1;
parameter OUTPUT = 3'd2;
parameter MODE = 3'd3;
parameter OPER = 3'd4;
parameter WAIT = 3'd5;
//---------------------------------------------------------------------
// WIRE AND REG DECLARATION
//---------------------------------------------------------------------
reg [2:0] cstate, nstate;
reg [1:0] mod;
reg finish;
reg [4:0] n1, n2, n3, n4, n5, n6, n7, n8, n9;
reg [10:0] ans;
reg [4:0] max, min;
reg [3:0] cnt;
reg [3:0] getIn;
//---------------------------------------------------------------------
// Finite-State Mechine
//---------------------------------------------------------------------
// cstate
always@(posedge clk, negedge rst_n)
begin
if(!rst_n) cstate <= INIT;
else cstate <= nstate;
end
// nstate
always@(*)
begin
case(cstate)
INIT:
begin
if(in_valid) nstate = INPUT;
else nstate = INIT;
end
INPUT:
begin
end
OUTPUT:
begin
nstate = INIT;
end
MODE:
begin
nstate = OPER;
end
OPER:
begin
if(finish) nstate = OUTPUT;
else nstate = OPER;
end
WAIT:
begin
if(in_valid) nstate = INPUT;
else nstate = WAIT;
end
default:
begin
nstate = INIT;
end
endcase
end
//---------------------------------------------------------------------
// Design Description
//---------------------------------------------------------------------
// getIn
always@(
// max, min
always@(posedge clk, negedge rst_n)
begin
if(!rst_n)
begin
max <= 0;
min <= 0;
end
else
case(cstate)
INIT:
begin
max <= 0;
min <= 0;
end
OPER:
if(mod != 2)
begin
case(cnt)
0:
begin
max <= n1;
min <= n1;
end
1:
begin
if(max < n2) max <= n2;
else max <= max;
if(min > n2) min <= n2;
else min <= min;
end
2:
begin
if(max < n3) max <= n3;
else max <= max;
if(min > n3) min <= n3;
else min <= min;
end
3:
begin
if(max < n4) max <= n4;
else max <= max;
if(min > n4) min <= n4;
else min <= min;
end
4:
begin
if(max < n5) max <= n5;
else max <= max;
if(min > n5) min <= n5;
else min <= min;
end
5:
begin
if(max < n6) max <= n6;
else max <= max;
if(min > n6) min <= n6;
else min <= min;
end
6:
begin
if(max < n7) max <= n7;
else max <= max;
if(min > n7) min <= n7;
else min <= min;
end
7:
begin
if(max < n8) max <= n8;
else max <= max;
if(min > n8) min <= n8;
else min <= min;
end
8:
begin
if(max < n9) max <= n9;
else max <= max;
if(min > n9) min <= n9;
else min <= min;
end
default:
begin
max <= max;
min <= min;
end
endcase
end
default:
begin
max <= max; min <= min;
end
endcase
end
// ans, finish
always@(posedge clk, negedge rst_n)
begin
if(!rst_n)
begin
ans <= 0;
finish <= 0;
end
else
case(cstate)
INIT:
begin
ans <= 0;
finish <= 0;
end
INPUT:
begin
ans <= ans+in;
end
OPER:
begin
case(mod)
0:
begin
if(cnt == 9)
begin
ans <= max;
finish <= 1;
end
else
begin
ans <= ans; finish <= finish;
end
end
1:
begin
if(cnt == 9)
begin
ans <= min;
finish <= 1;
end
else
begin
ans <= ans; finish <= finish;
end
end
2:
begin
finish <= 1;
end
default:
begin
finish <= finish;
end
endcase
end
default:
begin
ans <= ans; finish <= finish;
end
endcase
end
// out, out_valid
always@(posedge clk, negedge rst_n)
begin
if(!rst_n)
begin
out <= 0;
out_valid <= 0;
end
else
case(nstate)
INIT:
begin
out <= 0;
out_valid <= 0;
end
OUTPUT:
begin
out <= ans;
out_valid <= 1;
end
default:
begin
out <= out; out_valid <= out_valid;
end
endcase
end
// n, mod
always@(posedge clk, negedge rst_n)
begin
if(!rst_n)
begin
n1 <= 0; n2 <= 0; n3 <= 0; n4 <= 0; n5 <= 0; n6 <= 0; n7 <= 0; n8 <= 0; n9 <= 0;
mod <= 0;
end
else
case(nstate)
INIT:
begin
n1 <= 0; n2 <= 0; n3 <= 0; n4 <= 0; n5 <= 0; n6 <= 0; n7 <= 0; n8 <= 0; n9 <= 0;
mod <= 0;
end
INPUT:
begin
case(in)
1: n1 <= n1+1;
2: n2 <= n2+1;
3: n3 <= n3+1;
4: n4 <= n4+1;
5: n5 <= n5+1;
6: n6 <= n6+1;
7: n7 <= n7+1;
8: n8 <= n8+1;
9: n9 <= n9+1;
default:
begin
n1 <= n1; n2 <= n2; n3 <= n3; n4 <= n4; n5 <= n5; n6 <= n6; n7 <= n7; n8 <= n8; n9 <= n9;
end
endcase
end
MODE:
begin
mod <= mode;
end
default:
begin
n1 <= n1; n2 <= n2; n3 <= n3; n4 <= n4; n5 <= n5; n6 <= n6; n7 <= n7; n8 <= n8; n9 <= n9;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> void swap(int *a, int *b) { int temp = *a; *a = *b; *b = temp; } int max(int a, int b) { return (a > b) ? a : b; } int main() { int t, n, k, a[1005], b[1005]; scanf( %d , &t); while (t--) { int total = 0; scanf( %d %d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); total += a[i]; } for (int i = 0; i < n; i++) { scanf( %d , &b[i]); } for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { if (a[i] > a[j]) swap(&a[i], &a[j]); if (b[i] < b[j]) swap(&b[i], &b[j]); } } for (int i = 0; i < k; i++) { total -= a[i]; total += max(a[i], b[i]); } printf( %d n , total); } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y, ans = 0; scanf( %d , &n); while (n--) scanf( %d%d , &x, &y), ans = max(ans, x + y); printf( %d , ans); } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const double eps = 1e-6; const int INF = 1e12; const int maxnnn = 2e8 + 30; const long long zero = 0; long long gcd(long long a, long long b) { if (a < b) swap(a, b); if (a % b == 0) return b; else gcd(b, a % b); } string ntos(long long a) { string str; stringstream ss; ss << a; ss >> str; return str; } long long ston(string a) { long long x; stringstream ss; ss << a; ss >> x; return x; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); bool flag; long long zimu[26]; long long n, m, a, b, t, y, fans, c, x, z, sw; string s, s1, s2; cin >> m >> n; vector<long long> py(m + 1); sw = 0; py.clear(); for (long long i = 0; i < n; ++i) { cin >> a >> b; py[min(a, b)]++; if (py[min(a, b)] == 1) sw++; } cin >> c; while (c--) { cin >> x; if (x == 3) { cout << m - sw << endl; } else if (x == 1) { cin >> y >> z; py[min(y, z)]++; if (py[min(y, z)] == 1) sw++; } else { cin >> y >> z; py[min(y, z)]--; if (py[min(y, z)] == 0) sw--; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32A_TB_V
`define SKY130_FD_SC_MS__O32A_TB_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o32a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__o32a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32A_TB_V
|
#include <bits/stdc++.h> const int maxn = 150010; const int INF = 0x3f3f3f3f; using namespace std; vector<int> V; int a[maxn]; long long ans = 0; int ok(int i) { if (i & 1) return a[i] < a[i - 1] && a[i] < a[i + 1]; return a[i] > a[i + 1] && a[i] > a[i - 1]; } int ok2(int i, int j) { int f = 1; swap(a[i], a[j]); if (!ok(i)) f = 0; if (!ok(j)) f = 0; for (int k = 0; k < V.size(); k++) { if (!ok(V[k])) f = 0; } swap(a[i], a[j]); return f; } void fun(int idx, int n) { for (int i = 1; i <= n; i++) { if (ok2(idx, i)) { ++ans; } } } int main() { int n, i; while (~scanf( %d , &n)) { for (i = 1; i <= n; i++) { scanf( %d , &a[i]); } a[0] = INF; a[n + 1] = (n + 1) % 2 ? -INF : INF; V.empty(); for (i = 1; i <= n; i++) { if (!ok(i)) { V.push_back(i); } } if (V.size() > 6) { printf( 0 n ); continue; } ans = 0; for (i = 0; i < V.size(); i++) { fun(V[i], n); for (int j = i + 1; j < V.size(); j++) { if (ok2(V[i], V[j])) { --ans; } } } printf( %d n , ans); } } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module sp_mux_9to1_sel4_6_1 #(
parameter
ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
din7_WIDTH = 32,
din8_WIDTH = 32,
din9_WIDTH = 32,
din10_WIDTH = 32,
dout_WIDTH = 32
)(
input [5 : 0] din1,
input [5 : 0] din2,
input [5 : 0] din3,
input [5 : 0] din4,
input [5 : 0] din5,
input [5 : 0] din6,
input [5 : 0] din7,
input [5 : 0] din8,
input [5 : 0] din9,
input [3 : 0] din10,
output [5 : 0] dout);
// puts internal signals
wire [3 : 0] sel;
// level 1 signals
wire [5 : 0] mux_1_0;
wire [5 : 0] mux_1_1;
wire [5 : 0] mux_1_2;
wire [5 : 0] mux_1_3;
wire [5 : 0] mux_1_4;
// level 2 signals
wire [5 : 0] mux_2_0;
wire [5 : 0] mux_2_1;
wire [5 : 0] mux_2_2;
// level 3 signals
wire [5 : 0] mux_3_0;
wire [5 : 0] mux_3_1;
// level 4 signals
wire [5 : 0] mux_4_0;
assign sel = din10;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0)? din1 : din2;
assign mux_1_1 = (sel[0] == 0)? din3 : din4;
assign mux_1_2 = (sel[0] == 0)? din5 : din6;
assign mux_1_3 = (sel[0] == 0)? din7 : din8;
assign mux_1_4 = din9;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1;
assign mux_2_1 = (sel[1] == 0)? mux_1_2 : mux_1_3;
assign mux_2_2 = mux_1_4;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0)? mux_2_0 : mux_2_1;
assign mux_3_1 = mux_2_2;
// Generate level 4 logic
assign mux_4_0 = (sel[3] == 0)? mux_3_0 : mux_3_1;
// output logic
assign dout = mux_4_0;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> prime_Numbers; bool primes[1000005]; void prime(int n) { for (int i = 2; i <= n; i++) primes[i] = true; for (int i = 2; i <= n; i++) { if (primes[i] == true) { prime_Numbers.push_back(i); for (int j = i + i; j <= n; j += i) primes[j] = false; } } } int fib(int n) { if (n == 1 || n == 0) return n; return fib(n - 1) + fib(n - 2); } long long fastpower(int b, int p) { if (p == 0) return 1; long long term = fastpower(b, p / 2); term *= term; if (p % 2 != 0) return term *= b; return term; } long long arr[3005]; int main() { int t; cin >> t; while (t--) { int n, k, d; cin >> n >> k >> d; int arr[n + 2]; set<int> st; map<int, int> mp; for (int i = 0; i < n; i++) { cin >> arr[i]; } for (int i = 0; i < d; i++) { st.insert(arr[i]); mp[arr[i]]++; } int mnm = st.size(); for (int i = d; i < n; i++) { mp[arr[i - d]]--; if (mp[arr[i - d]] == 0) st.erase(arr[i - d]); st.insert(arr[i]); mp[arr[i]]++; mnm = min(mnm, (int)st.size()); } cout << min(mnm, (int)st.size()) << endl; } return 0; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_ll_bridge
*/
module test_axis_ll_bridge;
// Parameters
parameter DATA_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg ll_dst_rdy_in_n = 1;
// Outputs
wire [DATA_WIDTH-1:0] ll_data_out;
wire ll_sof_out_n;
wire ll_eof_out_n;
wire ll_src_rdy_out_n;
wire s_axis_tready;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tvalid,
s_axis_tlast,
ll_dst_rdy_in_n
);
$to_myhdl(
ll_data_out,
ll_sof_out_n,
ll_eof_out_n,
ll_src_rdy_out_n,
s_axis_tready
);
// dump file
$dumpfile("test_axis_ll_bridge.lxt");
$dumpvars(0, test_axis_ll_bridge);
end
axis_ll_bridge #(
.DATA_WIDTH(DATA_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// axi input
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
// locallink output
.ll_data_out(ll_data_out),
.ll_sof_out_n(ll_sof_out_n),
.ll_eof_out_n(ll_eof_out_n),
.ll_src_rdy_out_n(ll_src_rdy_out_n),
.ll_dst_rdy_in_n(ll_dst_rdy_in_n)
);
endmodule
|
module top_receptor (ready, clk, reset, CharSalida, rxd, String);
input clk;
input reset;
input rxd;
output [0:6] CharSalida;
output ready;
output [0:76] String;
// wire [0:76] String;
wire [0:6] char;
wire clk_2;
wire WriteChar;
wire error;
wire [2:0] char_count;
wire CharReady;
wire StringReady;
wire WriteString;
wire PossibleStart;
wire check;
wire parity;
wire [3:0] str_count;
counter counter(.clk_2(clk_2), .char_count(char_count), .str_count(str_count), .reset(reset), .WriteChar(WriteChar), .WriteString(WriteString));
Wait Wait(.reset(reset), .clk(clk), .clk_2(clk_2), .check(check), .PossibleStart(PossibleStart), .WriteChar(WriteChar));
StringComparator StringComparator(.str_count(str_count), .StringReady(StringReady));
Parity Parity(.char(char), .rxd(rxd), .parity(parity));
mstring mstring(.WriteString(WriteString), .char(char), .String(String), .reset(reset), .clk_2(clk_2));
control_o control_o(.reset(reset), .rxd(rxd), .StringReady(StringReady), .CharReady(CharReady), .parity(parity), .ready(ready), .error(error), .WriteChar(WriteChar), .WriteString(WriteString), .PossibleStart(PossibleStart), .clk_2(clk_2), .check(check));
CharComparator CharComparator (.char_count(char_count), .CharReady(CharReady));
Char Char (.clk_2(clk_2), .rxd(rxd), .WriteChar(WriteChar), .error(error), .reset(reset), .char(char));
test test (.String(String), .CharSalida(CharSalida), .clk(clk), .ready(ready), .reset(reset));
endmodule // top_receptor
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXBP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > E[1010]; int deg[1010], vis[1010]; vector<pair<int, pair<int, int> > > ans; int N, P; int main() { int u, v, d; while (~scanf( %d%d , &N, &P)) { for (int i = 0; i < N; i++) deg[i] = 0, E[i].clear(); for (int i = 0; i < P; i++) scanf( %d%d%d , &u, &v, &d), u--, v--, deg[v]++, E[u].push_back(make_pair(v, d)); ans.clear(); for (int i = 0; i < N; i++) if (deg[i] == 0) { int dd = 1 << 30, u = i; for (u = i; E[u].size() > 0; u = E[u][0].first) dd = min(dd, E[u][0].second); if (dd < (1 << 30)) ans.push_back(make_pair(i, make_pair(u, dd))); } sort(ans.begin(), ans.end()); printf( %d n , ans.size()); for (int i = 0; i < ans.size(); i++) printf( %d %d %d n , ans[i].first + 1, ans[i].second.first + 1, ans[i].second.second); } return 0; } |
`timescale 1ns/1ps
module I2CFSM (
input Reset_n_i,
input Clk_i,
// FSM control
input Start_i,
output reg Done_o,
output reg Error_o,
output reg [7:0] Byte0_o,
output reg [7:0] Byte1_o,
// to/from I2C_Master
// I2C control
output reg I2C_ReceiveSend_n_o,
output reg [7:0] I2C_ReadCount_o,
output reg I2C_StartProcess_o,
input I2C_Busy_i,
// I2C FIFO
output reg I2C_FIFOReadNext_o,
output reg I2C_FIFOWrite_o,
output reg [7:0] I2C_Data_o,
input [7:0] I2C_Data_i,
// I2C error
input I2C_Error_i,
// parameters
input [15:0] ParamCounterPreset_i
);
// ADT7410 I2C Temperature Sensor
// - ADT7410 is very similar to ADT7310
// - it uses different register addresses
// - instead of the "SPI Command Byte" it uses the normal I2C address byte
// including its R/W bit
// - One-Shot Measurement
// - initiate one-shot mode: write 0x20 to config register at 0x03
// - "10010aa0" "00000011" "00100000"
// - wait for 240ms
// - read temperature register at 0x00:
// - 1st transaction: write reg. address: "10010aa0" "00000000"
// - 2nd transaction: read two bytes: "10010aa1" "smmmmmmm" "lllllfff"
// - Temperature = "smmmmmmmlllll", flags "fff" are unused
//
// I2C Master
// - write address + N bytes, see I2C Bus Controller Documentation, testcase 4
// - ReceiveSend_o = '0'
// - FIFOWrite_o = '1', Data_o = ..., N+1 cycles
// - FIFOWrite_o = '0', StartProcess_o = '1' for 1 cycles only, Busy_i
// goes high immediately <-- really?
// - wait until Busy_i goes low again
// - read N bytes, see testcase 7
// - ReceiveSend_o = '1', ReadCount_o = N
// - FIFOWrite_o = '1', Data_o = address, 1 cycle
// - FIFOWrite_o = '0', StartProcess_o = '1' for 1 cycles only, Busy_i
// goes high immediately
// - wait until Busy_i goes low again
// - read bytes from FIFO via Data_i and FIFOReadNext_o
//
// I2C FSM
localparam stIdle = 4'b0000;
localparam stWriteReq1 = 4'b0001;
localparam stWriteReq2 = 4'b0010;
localparam stStartReq = 4'b0011;
localparam stWaitReq = 4'b0100;
localparam stWait = 4'b0101;
localparam stWriteAddr1 = 4'b0110;
localparam stStartAddr = 4'b0111;
localparam stWaitAddr = 4'b1000;
localparam stStartQuery = 4'b1001;
localparam stWaitQuery = 4'b1010;
localparam stRead1 = 4'b1011;
localparam stPause = 4'b1100;
reg [3:0] I2C_FSM_State;
reg [3:0] I2C_FSM_NextState;
wire I2C_FSM_TimerOvfl;
reg I2C_FSM_TimerPreset;
reg I2C_FSM_TimerEnable;
reg I2C_FSM_Wr1;
reg I2C_FSM_Wr0;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
I2C_FSM_State <= stIdle;
end
else
begin
I2C_FSM_State <= I2C_FSM_NextState;
end
end
always @(I2C_FSM_State, Start_i, I2C_Busy_i, I2C_Error_i, I2C_FSM_TimerOvfl)
begin // process I2C_FSM_CombProc
I2C_FSM_NextState = I2C_FSM_State;
// control signal default values
Done_o = 1'b0;
Error_o = 1'b0;
// to I2C Master
I2C_ReceiveSend_n_o = 1'b0;
I2C_ReadCount_o = 8'h00;
I2C_StartProcess_o = 1'b0;
I2C_FIFOReadNext_o = 1'b0;
I2C_FIFOWrite_o = 1'b0;
I2C_Data_o = 8'h00;
// to other processes in this module
I2C_FSM_TimerPreset = 1'b1;
I2C_FSM_TimerEnable = 1'b0;
I2C_FSM_Wr1 = 1'b0;
I2C_FSM_Wr0 = 1'b0;
// next state and output logic
case (I2C_FSM_State)
stIdle: begin
if (Start_i == 1'b1)
begin
// single-shot measurement mode: write 0x20 to config register at 0x03
// "10010aa0" "00000011" "00100000"
I2C_FSM_NextState = stWriteReq1;
I2C_Data_o = 8'b10010000;
I2C_FIFOWrite_o = 1'b1;
end
else
begin
// nobody cares about the value, so simplify the MUX
I2C_Data_o = 8'b10010000;
end
end
stWriteReq1: begin
I2C_FSM_NextState = stWriteReq2;
I2C_Data_o = 8'b00000011;
I2C_FIFOWrite_o = 1'b1;
end
stWriteReq2: begin
I2C_FSM_NextState = stStartReq;
I2C_Data_o = 8'h20;
I2C_FIFOWrite_o = 1'b1;
end
stStartReq: begin
I2C_StartProcess_o = 1'b1;
I2C_FSM_NextState = stWaitReq;
end
stWaitReq: begin
// wait until I2C transmission has finished
if (I2C_Error_i == 1'b1)
begin
I2C_FSM_NextState = stIdle;
Error_o = 1'b1;
end
else if (I2C_Busy_i == 1'b0)
begin
I2C_FSM_NextState = stWait;
I2C_FSM_TimerPreset = 1'b0;
I2C_FSM_TimerEnable = 1'b1; // start timer
end
end
stWait: begin
// wait for 240ms
if (I2C_FSM_TimerOvfl == 1'b0)
begin
I2C_FSM_TimerPreset = 1'b0;
I2C_FSM_TimerEnable = 1'b1; // timer running
// nobody cares about the value, so simplify the MUX
I2C_Data_o = 8'b10010000;
end
else
begin
// timer overflow -> continue: write register address: "10010aa0" "00000000"
I2C_FSM_NextState = stWriteAddr1;
I2C_Data_o = 8'b10010000;
I2C_FIFOWrite_o = 1'b1;
end
end
stWriteAddr1: begin
I2C_FSM_NextState = stStartAddr;
I2C_Data_o = 8'b00000000;
I2C_FIFOWrite_o = 1'b1;
end
stStartAddr: begin
// start sending register address
I2C_StartProcess_o = 1'b1;
I2C_FSM_NextState = stWaitAddr;
end
stWaitAddr: begin
// wait until I2C transmission has finished
if (I2C_Busy_i == 1'b0)
begin
I2C_FSM_NextState = stStartQuery;
I2C_Data_o = 8'b10010001; // read transfer: R/W = 1
I2C_FIFOWrite_o = 1'b1;
end
else
begin
// nobody cares about the value, so simplify the MUX
I2C_Data_o = 8'b10010001; // read transfer: R/W = 1
end
end
stStartQuery: begin
// start sending read transfer
I2C_ReceiveSend_n_o = 1'b1;
I2C_ReadCount_o = 8'h02;
I2C_StartProcess_o = 1'b1;
I2C_FSM_NextState = stWaitQuery;
end
stWaitQuery: begin
I2C_ReceiveSend_n_o = 1'b1;
I2C_ReadCount_o = 8'h02;
// wait until I2C transmission has finished
if (I2C_Busy_i == 1'b0)
begin
I2C_FSM_NextState = stRead1;
// consume and store first byte
I2C_FIFOReadNext_o = 1'b1;
I2C_FSM_Wr1 = 1'b1;
end
end
stRead1: begin
// consume and store second byte
I2C_FIFOReadNext_o = 1'b1;
I2C_FSM_Wr0 = 1'b1;
I2C_FSM_NextState = stPause;
end
stPause: begin
Done_o = 1'b1;
I2C_FSM_NextState = stIdle;
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Byte-wide Memory /////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Byte0_o <= 8'd0;
Byte1_o <= 8'd0;
end
else
begin
if (I2C_FSM_Wr0)
begin
Byte0_o <= I2C_Data_i;
end
if (I2C_FSM_Wr1)
begin
Byte1_o <= I2C_Data_i;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [15:0] I2C_FSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
I2C_FSM_Timer <= 16'd0;
end
else
begin
if (I2C_FSM_TimerPreset)
begin
I2C_FSM_Timer <= ParamCounterPreset_i;
end
else if (I2C_FSM_TimerEnable)
begin
I2C_FSM_Timer <= I2C_FSM_Timer - 1'b1;
end
end
end
assign I2C_FSM_TimerOvfl = (I2C_FSM_Timer == 0) ? 1'b1 : 1'b0;
endmodule // I2CFSM
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_1_V
`define SKY130_FD_SC_HDLL__SDFRTP_1_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Use this file as a template for submitting bugs, etc.
// This module takes a single clock input, and should either
// $write("*-* All Finished *-*\n");
// $finish;
// on success, or $stop.
//
// The code as shown applies a random vector to the Test
// module, then calculates a CRC on the Test module's outputs.
//
// **If you do not wish for your code to be released to the public
// please note it here, otherwise:**
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by ____YOUR_NAME_HERE____.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
// Replace this module with the device under test.
//
// Change the code in the t module to apply values to the inputs and
// merge the output values into the result vector.
input clk;
input [31:0] in;
output reg [31:0] out;
always @(posedge clk) begin
out <= in;
end
endmodule
|
//lpm_divide CBX_SINGLE_OUTPUT_FILE="ON" LPM_DREPRESENTATION="UNSIGNED" LPM_HINT="LPM_REMAINDERPOSITIVE=TRUE" LPM_NREPRESENTATION="UNSIGNED" LPM_TYPE="LPM_DIVIDE" LPM_WIDTHD=8 LPM_WIDTHN=8 denom numer quotient remain
//VERSION_BEGIN 16.0 cbx_mgl 2016:07:21:01:49:21:SJ cbx_stratixii 2016:07:21:01:48:16:SJ cbx_util_mgl 2016:07:21:01:48:16:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = lpm_divide 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mgqfk
(
denom,
numer,
quotient,
remain) /* synthesis synthesis_clearbox=1 */;
input [7:0] denom;
input [7:0] numer;
output [7:0] quotient;
output [7:0] remain;
wire [7:0] wire_mgl_prim1_quotient;
wire [7:0] wire_mgl_prim1_remain;
lpm_divide mgl_prim1
(
.denom(denom),
.numer(numer),
.quotient(wire_mgl_prim1_quotient),
.remain(wire_mgl_prim1_remain));
defparam
mgl_prim1.lpm_drepresentation = "UNSIGNED",
mgl_prim1.lpm_nrepresentation = "UNSIGNED",
mgl_prim1.lpm_type = "LPM_DIVIDE",
mgl_prim1.lpm_widthd = 8,
mgl_prim1.lpm_widthn = 8,
mgl_prim1.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
assign
quotient = wire_mgl_prim1_quotient,
remain = wire_mgl_prim1_remain;
endmodule //mgqfk
//VALID FILE
|
//======================================================================
//
// gcm_ghash.v
// -----------
// GHASH module for the GCM core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2018, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module gcm_ghash(
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire [127 : 0] h0,
input wire [127 : 0] x,
output wire [127 : 0] y,
output wire ready
);
//----------------------------------------------------------------
// Gaolis multiplication functions.
//----------------------------------------------------------------
function [127 : 0] gm2(input [127 : 0] op);
begin
gm2 = {op[126 : 0], 1'b0} ^ (128'h1b & {128{op[127]}});
end
endfunction // gm2
function [127 : 0] gm3(input [127 : 0] op);
begin
gm3 = gm2(op) ^ op;
end
endfunction // gm3
function [127 : 0] gm4(input [127 : 0] op);
begin
gm4 = gm2(gm2(op));
end
endfunction // gm4
function [127 : 0] gm7(input [127 : 0] op);
begin
gm7 = gm4(op) ^ gm3(op);
end
endfunction // gm7
function [127 : 0] gm8(input [127 : 0] op);
begin
gm8 = gm2(gm4(op));
end
endfunction // gm8
function [127 : 0] gm16(input [127 : 0] op);
begin
gm16 = gm4(gm4(op));
end
endfunction // gm16
function [127 : 0] gm128(input [127 : 0] op);
begin
gm128 = gm8(gm16(op));
end
endfunction // gm128
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [127 : 0] op_reg;
reg [127 : 0] res_new;
reg [127 : 0] res_reg;
reg [127 : 0] pipe1_reg;
reg [127 : 0] pipe1_new;
reg [127 : 0] pipe2_reg;
reg [127 : 0] pipe2_new;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign y = res_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
op_reg <= 128'h0;
res_reg <= 128'h0;
pipe1_reg <= 128'h0;
pipe2_reg <= 128'h0;
end
else
begin
op_reg <= op;
res_reg <= res_new;
pipe1_reg <= pipe1_new;
pipe2_reg <= pipe2_new;
end
end // reg_update
//----------------------------------------------------------------
// gmult_logic
//----------------------------------------------------------------
always @*
begin : gmult_logic
pipe1_new = gm128(op_reg);
pipe2_new = gm7(op_reg) + gm2(op_reg) + op_reg + 1'b1;
res_new = pipe1_reg + pipe2_reg;
end // gmult_logic
endmodule // gcm_gmult
//======================================================================
// EOF gcm_ghash.v
//======================================================================
|
#include <bits/stdc++.h> using namespace std; vector<int> v[1000005]; int n, ar[100005]; int main() { cin >> n; set<int> st; for (int i = 0; i < n; i++) { cin >> ar[i]; st.insert(ar[i]); v[ar[i]].push_back(i + 1); } vector<int> fr(st.begin(), st.end()); int mx = 0, l = 1, r = n, mnd = INT_MAX; for (int i = 0; i < fr.size(); i++) { int x = fr[i]; if (v[fr[i]].size() >= mx) { if (mx < v[fr[i]].size() || v[x][v[x].size() - 1] - v[x][0] < mnd) { l = v[x][0]; r = v[x][v[x].size() - 1]; mnd = v[x][v[x].size() - 1] - v[x][0]; mx = v[x].size(); } } } cout << l << << r << endl; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 19 11:36:02 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[0:0],probe14[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [0:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [0:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[25][25][5], ans, n, t; int main() { cin >> n >> t; for (int i = 1; i <= 4; i++) for (int j = i + 1; j <= 4; j++) dp[2][1][j]++; for (int i = 3; i <= n; i++) for (int j = 1; j <= t * 2; j++) for (int k = 1; k <= 4; k++) { if (j & 1) for (int l = 1; l < k; l++) dp[i][j][k] += dp[i - 1][j][l] + dp[i - 1][j - 1][l]; else for (int l = k + 1; l <= 4; l++) dp[i][j][k] += dp[i - 1][j][l] + dp[i - 1][j - 1][l]; } for (int i = 1; i <= 4; i++) ans += dp[n][t * 2][i]; cout << ans; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUF_SYMBOL_V
`define SKY130_FD_SC_LP__LSBUF_SYMBOL_V
/**
* lsbuf: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUF_SYMBOL_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eb_e
//
// Generated
// by: wig
// on: Tue Mar 30 18:39:52 2004
// cmd: H:\work\mix_new\MIX\mix_0.pl -strip -nodelta ../../autoopen.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eb_e.v,v 1.2 2006/01/19 08:50:42 wig Exp $
// $Date: 2006/01/19 08:50:42 $
// $Log: inst_eb_e.v,v $
// Revision 1.2 2006/01/19 08:50:42 wig
// Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
//
// Revision 1.1 2004/04/06 11:19:55 wig
// Adding result/autoopen
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.39 2004/03/30 11:05:58 wig Exp
//
// Generator: mix_0.pl Revision: 1.28 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_eb_e
//
// No `defines in this module
module inst_eb_e
//
// Generated module inst_eb
//
(
p_mix_s_eo2_gi
);
// Generated Module Inputs:
input p_mix_s_eo2_gi;
// Generated Wires:
wire p_mix_s_eo2_gi;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire s_eo2; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign s_eo2 = p_mix_s_eo2_gi; // __I_I_BIT_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_eba
inst_eba_e inst_eba(
.s_eo2(s_eo2)
);
// End of Generated Instance Port Map for inst_eba
endmodule
//
// End of Generated Module rtl of inst_eb_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR3_4_V
`define SKY130_FD_SC_HS__OR3_4_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3_4 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or3_4 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR3_4_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100010, inf = 1e9; int n, ty, l, r, x; bitset<maxn> v[26], ans; char s[maxn], s2[maxn], c; inline void read(int &k) { int f = 1; k = 0; char c = getchar(); while (c < 0 || c > 9 ) c == - && (f = -1), c = getchar(); while (c <= 9 && c >= 0 ) k = k * 10 + c - 0 , c = getchar(); k *= f; } int main() { scanf( %s , s + 1); int len = strlen(s + 1); for (int i = 1; i <= len; i++) v[s[i] - a ][i] = 1; read(n); for (int i = 1; i <= n; i++) { read(ty); if (ty == 1) { read(x); scanf( %c , &c); v[s[x] - a ][x] = 0; v[(s[x] = c) - a ][x] = 1; } else { read(l); read(r); scanf( %s , s2); int m = strlen(s2); if (r - l + 1 < m) { puts( 0 ); continue; } ans.set(); for (int j = 0; j < m; j++) ans &= (v[s2[j] - a ] >> j); printf( %d n , (int)(ans >> (l)).count() - (int)(ans >> (r - m + 2)).count()); } } } |
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module sync_r2w
#(
parameter ASIZE = 4
)(
input wire wclk,
input wire wrst_n,
input wire [ASIZE:0] rptr,
output reg [ASIZE:0] wq2_rptr
);
reg [ASIZE:0] wq1_rptr;
always @(posedge wclk or negedge wrst_n) begin
if (!wrst_n)
{wq2_rptr,wq1_rptr} <= 0;
else
{wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
end
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; mt19937 rnd; const long long maxn = 2e6 + 5; const long long mod = 1e9 + 7; long long fac[maxn]; long long inv[maxn]; vector<char> prime(maxn, true); long long spf[maxn]; long long binpow(long long a, long long b) { if (b == 0) return 1; if (b == 1) return a % mod; if (b == 2) return (a * a) % mod; if (b % 2 == 0) return binpow((a * a) % mod, b / 2); if (b % 2 == 1) return (a * binpow((a * a) % mod, b / 2)) % mod; } void buildprimes() { prime[0] = prime[1] = false; for (long long i = 2; i < maxn; ++i) { if (prime[i]) { spf[i] = i; if (i * 1ll * i < maxn) { for (long long j = i * i; j < maxn; j += i) { prime[j] = false; spf[j] = i; } } } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); fac[1] = fac[0] = 1; for (long long i = 2; i < maxn; i++) { fac[i] = (fac[i - 1] * i) % mod; } for (long long i = 1; i < maxn; i++) { inv[i] = binpow(fac[i], mod - 2); } buildprimes(); int q; cin >> q; while (q--) { int x, y; cin >> x >> y; if (y == 1) { cout << 1 n ; continue; } long long ans = 1; ans = binpow(2, y - 1); while (x > 1) { long long cur = 0; long long p = spf[x]; while (x % p == 0) { x /= p; cur++; } long long C = (((fac[cur + y - 1] * inv[y - 1]) % mod) * inv[cur]) % mod; ans = (ans * C) % mod; } cout << ans << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_4_V
`define SKY130_FD_SC_HDLL__XNOR2_4_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xnor2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xnor2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_4_V
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: nuny_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module nuny_new2 (
address,
clock,
q);
input [14:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites-new/nuny_new2.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32768,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 15,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/nuny_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/nuny_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL nuny_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int pw = 1 << 17; const int maxn = 1e5 + 20; int ans[maxn]; void work() { int n, x; cin >> n >> x; if (n == 1) { printf( YES n ); cout << x << endl; return; } else if (n == 2 && x == 0) { printf( NO n ); return; } printf( YES n ); int t = x; for (int i = 0; i < n; ++i) ans[i] = i; for (int i = 0; i < n - 1; ++i) { t ^= ans[i]; } if (t <= n - 2) { ans[t] ^= pw; if (t == n - 2) ans[t - 1] ^= pw; else if (t == 0) ans[t + 1] ^= pw; else ans[t + 1] ^= pw; } ans[n - 1] = t; int res = 0; for (int i = 0; i < n; ++i) { printf( %d , ans[i]); res ^= ans[i]; } } int main() { work(); return 0; } |
#include <bits/stdc++.h> std::mt19937 rng( (int)std::chrono::steady_clock::now().time_since_epoch().count()); const int ms = 101; long long memo[ms][ms], memo2[ms][ms][ms]; long long a[ms]; std::string str; long long dp(int l, int r); long long dp2(int l, int r, int x) { if (r - l <= 0) return 0; long long &ans = memo2[l][r][x]; if (ans != -1) return ans; ans = dp(l + 1, r) + a[x]; for (int i = l + 1; i < r; i++) { if (str[i] == str[l]) { ans = std::max(ans, dp(l + 1, i) + dp2(i, r, x + 1)); } } return ans; } long long dp(int l, int r) { if (r - l <= 0) return 0; else if (r - l == 1) return a[1]; long long &ans = memo[l][r]; if (ans != -1) return ans; ans = 0; for (int m = l; m < r; m++) { ans = std::max(ans, dp2(m, r, 1) + dp(l, m)); } return ans; } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(NULL); int n; std::cin >> n >> str; for (int i = 0; i < n; i++) { std::cin >> a[i + 1]; } memset(memo, -1, sizeof memo); memset(memo2, -1, sizeof memo2); std::cout << dp(0, n) << n ; } |
#include <bits/stdc++.h> using namespace std; int l[6]; int main() { int n, m, a; cin >> m >> n; for (int i = 0; i < m; i++) { for (int i = 1; i <= n; i++) { cin >> a; l[i] = max(l[i - 1], l[i]) + a; } cout << l[n] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T1> void print_list(const T1& a) { cerr << a << endl; } template <typename T1, typename T2> void print_list(const T1& a, const T2& b) { cerr << a << << b << endl; } template <typename T1, typename T2, typename T3> void print_list(const T1& a, const T2& b, const T3& c) { cerr << a << << b << << c << endl; } template <typename T1, typename T2, typename T3, typename T4> void print_list(const T1& a, const T2& b, const T3& c, const T4& d) { cerr << a << << b << << c << << d << endl; } template <typename T1, typename T2, typename T3, typename T4, typename T5> void print_list(const T1& a, const T2& b, const T3& c, const T4& d, const T5& e) { cerr << a << << b << << c << << d << << e << endl; } template <typename T1, typename T2, typename T3, typename T4, typename T5, typename T6> void print_list(const T1& a, const T2& b, const T3& c, const T4& d, const T5& e, const T6& f) { cerr << a << << b << << c << << d << << e << << f << endl; } template <typename T1, typename T2, typename T3, typename T4, typename T5, typename T6, typename T7> void print_list(const T1& a, const T2& b, const T3& c, const T4& d, const T5& e, const T6& f, const T7& g) { cerr << a << << b << << c << << d << << e << << f << << g << endl; } template <typename A, typename B> ostream& operator<<(ostream& out, const pair<A, B>& pp) { out << ( << pp.first << , << pp.second << ) ; return out; } template <typename A, typename B> istream& operator<<(istream& in, pair<A, B>& pp) { cerr << A pair wanted << endl; in >> pp.first >> pp.second; return in; } template <typename T> ostream& operator<<(ostream& out, const vector<T>& vect) { out << length = << vect.size() << endl; for (int i = 0; i < vect.size(); i++) out << vect[i] << ; out << endl; return out; } template <typename T> istream& operator>>(istream& in, vector<T>& vect) { vect.clear(); int n; cerr << A integer of length wanted << endl; in >> n; vect.resize(n); cerr << n << elements wanted << endl; for (int i = 0; i < n; i++) in >> vect[i]; return in; } template <typename T> ostream& operator<<(ostream& out, const vector<vector<T> >& vect) { out << row number= << vect.size() << endl; for (int i = 0; i < vect.size(); i++) { out << row # << i << : ; for (int j = 0; j < vect[i].size(); j++) out << << vect[i][j]; out << endl; } return out; } template <typename T> istream& operator>>(istream& in, vector<vector<T> >& vect) { vect.clear(); int n, m; cerr << Two integers wnated << endl; in >> n >> m; vect.resize(n); cerr << A matrix << n << X << m << wanted << endl; for (int i = 0; i < n; i++) { vect[i].resize(m); for (int j = 0; j < m; j++) in >> vect[i][j]; } return in; } template <typename T> inline void updateMax(T& a, const T& b) { a = max(a, b); } template <typename T> inline void updateMin(T& a, const T& b) { a = min(a, b); } template <typename T> inline vector<T> erase(vector<T> table, int ind) { assert(ind < table.size()); table.erase(table.begin() + ind); return table; } template <typename T> vector<T> unique(vector<T> table) { sort(table.begin(), table.end()); return vector<T>(table.begin(), unique(table.begin(), table.end())); } template <class T> vector<T> parse(const string& ss, const char* cut = ) { vector<T> re; for (int j = 0; j < ss.size(); j++) { string s; while (j < ss.size() && NULL == strchr(cut, ss[j])) s += ss[j++]; if (!s.empty()) { T tmp; istringstream is(s); is >> tmp; re.push_back(tmp); } } return re; } int countBit(int n) { int re = 0; while (n) re++, n ^= ((((n) ^ ((n)-1)) & n)); return re; } int MSB(int n) { if (n == 0) return 0; while (((((n) ^ ((n)-1)) & n)) != n) n ^= ((((n) ^ ((n)-1)) & n)); return n; } void initHash(int n, int hash[]) { for (int i = 0; i < n; i++) hash[((1) << (i))] = i; } void initBcnt(int n, int bcnt[]) { bcnt[0] = 0; for (int i = 1; i < ((1) << (n)); i++) bcnt[i] = bcnt[i ^ ((((i) ^ ((i)-1)) & i))] + 1; } template <typename T> T __gcd(T n, T m, T& a, T& b) { T a1 = 0, b1 = 1; a = 1, b = 0; while (m) { T c = n / m; T r = n - m * c; T t; t = a; a = a1; a1 = t - c * a1; t = b; b = b1; b1 = t - c * b1; n = m; m = r; } return n; } struct Node { int r, c, d; int v; Node(int x, int y, int z, int v1) : r(x), c(y), d(z), v(v1){}; bool operator<(const Node& other) const { return v > other.v; }; }; priority_queue<Node> heap; const int dir[][2] = {{-1, 0}, {0, 1}, {1, 0}, {0, -1}, {1, 1}, {1, -1}, {-1, 1}, {-1, -1}}; const char dname[] = NWSE ; const string vv[] = { ......... , ....O.... , ..O...O.. , ..O.O.O.. , O.O...O.O , O.O.O.O.O , O.OO.OO.O }; const string hh[] = { ......... , ....O.... , O.......O , O...O...O , O.O...O.O , O.O.O.O.O , OOO...OOO }; char grid[2000][2000]; int dom[1000][1000]; long long int col1[1000], col2[1000]; long long int dp[1000]; const long long int mod = 1000000007; long long int buf[1000]; int main() { map<string, int> mem; for (int i = 0; i < 7; i++) { mem[vv[i]] |= 1; mem[hh[i]] |= 2; } int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < 4 * n + 1; i++) { scanf( %s , grid[i]); } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int x = 4 * i + 1; int y = 4 * j + 1; string s(9, . ); for (int a = 0; a < 3; a++) for (int b = 0; b < 3; b++) { s[a * 3 + b] = grid[x + a][y + b]; } assert(mem.count(s)); dom[i][j] = mem[s]; } for (int i = 0; i < m; i++) { col1[i] = 1 - (n & 1); for (int j = 1; j < n && col1[i]; j += 2) { if (0 == (dom[j][i] & 1) || 0 == (dom[j - 1][i] & 1)) { col1[i]--; break; } } } for (int i = 0; i + 1 < m; i++) { dp[0] = 1; for (int j = 1; j <= n; j++) { dp[j] = 0; if ((dom[j - 1][i] & 2) && (dom[j - 1][i + 1] & 2)) { dp[j] += dp[j - 1]; } if (j >= 2 && (dom[j - 1][i] & 1) && (dom[j - 2][i] & 1) && (dom[j - 1][i + 1] & 1) && (dom[j - 2][i + 1] & 1)) { dp[j] += dp[j - 2]; } dp[j] %= mod; } col2[i] = dp[n]; } dp[0] = 1; for (int i = 1; i <= m; i++) { dp[i] = 0; dp[i] += col1[i - 1] * dp[i - 1]; if (i >= 2) { dp[i] += (col2[i - 2] + mod - col1[i - 1] * col1[i - 2]) * dp[i - 2]; } dp[i] %= mod; } cout << dp[m] << endl; return 0; } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_async_fifo;
// Inputs
reg input_clk = 0;
reg input_rst = 0;
reg output_clk = 0;
reg output_rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(input_clk,
input_rst,
output_clk,
output_rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
// dump file
$dumpfile("test_axis_async_fifo.lxt");
$dumpvars(0, test_axis_async_fifo);
end
axis_async_fifo #(
.ADDR_WIDTH(2),
.DATA_WIDTH(8)
)
UUT (
// AXI input
.input_clk(input_clk),
.input_rst(input_rst),
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_clk(output_clk),
.output_rst(output_rst),
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser)
);
endmodule
|
#include <bits/stdc++.h> const bool DEBUG = false; using namespace std; const long long maxn = 2e5 + 5; const long long INF = 1e18 + 1; const long long M = 1e9 + 7; const int lg = 21; int n, m, x[maxn], b[maxn], a[maxn], y[maxn]; vector<pair<int, int> > v; set<int> s; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) cin >> x[i] >> y[i]; for (int i = 0; i < m; i++) cin >> a[i] >> b[i]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[j] == b[j] or x[i] == y[i]) continue; if (a[j] == x[i] and b[j] == y[i]) continue; if (a[j] == y[i] and b[j] == x[i]) continue; if (a[j] != x[i] and a[j] != y[i] and b[j] != x[i] and b[j] != y[i]) continue; if (a[j] == x[i] or a[j] == y[i]) s.insert(a[j]); else s.insert(b[j]); } } if (s.size() == 1) return cout << (*s.begin()) << endl, 0; for (int i = 0; i < n; i++) { vector<int> v; set<int> s; for (int j = 0; j < m; j++) { if (a[j] == b[j] or x[i] == y[i]) continue; if (a[j] == x[i] and b[j] == y[i]) continue; if (a[j] == y[i] and b[j] == x[i]) continue; if (a[j] != x[i] and a[j] != y[i] and b[j] != x[i] and b[j] != y[i]) continue; if (x[i] == a[j] or x[i] == b[j]) s.insert(x[i]); else s.insert(y[i]); } if (s.size() > 1) return cout << -1 << endl, 0; } for (int i = 0; i < m; i++) { vector<int> v; set<int> s; for (int j = 0; j < n; j++) { if (a[i] == b[i] or x[j] == y[j]) continue; if (a[i] == x[j] and b[i] == y[j]) continue; if (a[i] == y[j] and b[i] == x[j]) continue; if (a[i] != x[j] and a[i] != y[j] and b[i] != x[j] and b[i] != y[j]) continue; if (x[j] == a[i] or a[i] == y[j]) s.insert(a[i]); else s.insert(b[i]); } if (s.size() > 1) return cout << -1 << endl, 0; } cout << 0 << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21OI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A21OI_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21oi (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21OI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n; double p[110], S; int main() { scanf( %d , &n); for (int i = 0; i <= n; i++) scanf( %lf , p + i); for (int i = 0; i < n; i++) for (int j = i + 1; j <= n; j++) if (i * 2 <= n && n <= j * 2) S = max( S, (n * 0.5 - j) / (i - j) * p[i] + (n * 0.5 - i) / (j - i) * p[j]); printf( %.9lf n , S); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int b, g; cin >> b; int i; int B[n]; for (i = 0; i < n; i++) { B[i] = 0; } int bb[b]; for (i = 0; i < b; i++) { cin >> bb[i]; B[bb[i]] = 1; } cin >> g; int G[m]; for (i = 0; i < m; i++) { G[i] = 0; } int gg[g]; for (i = 0; i < g; i++) { cin >> gg[i]; G[gg[i]] = 1; } for (i = 0; i < 10000; i++) { if (B[i % n] == 1) { G[i % m] = 1; } if (G[i % m] == 1) { B[i % n] = 1; } } i = 0; while (i < n) { if (B[i] == 0) { cout << No ; return 0; } if (B[i] == 1) { i++; } } i = 0; while (i < m) { if (G[i] == 0) { cout << No ; return 0; } if (G[i] == 1) { i++; } } cout << Yes ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND2_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int a[10000]; int n, m, mn, mn1; multiset<int> s; int main() { cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a[i]; s.insert(a[i]); } int q = *s.rbegin() + m; while (m--) { int t = *s.begin(); s.erase(s.begin()); s.insert(t + 1); } cout << *s.rbegin() << << q; return 0; } |
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Wishbone register
*/
module wb_async_reg #
(
parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
parameter ADDR_WIDTH = 32, // width of address bus in bits
parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
)
(
// master side
input wire wbm_clk,
input wire wbm_rst,
input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address
input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
input wire wbm_we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
input wire wbm_stb_i, // STB_I strobe input
output wire wbm_ack_o, // ACK_O acknowledge output
output wire wbm_err_o, // ERR_O error output
output wire wbm_rty_o, // RTY_O retry output
input wire wbm_cyc_i, // CYC_I cycle input
// slave side
input wire wbs_clk,
input wire wbs_rst,
output wire [ADDR_WIDTH-1:0] wbs_adr_o, // ADR_O() address
input wire [DATA_WIDTH-1:0] wbs_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbs_dat_o, // DAT_O() data out
output wire wbs_we_o, // WE_O write enable output
output wire [SELECT_WIDTH-1:0] wbs_sel_o, // SEL_O() select output
output wire wbs_stb_o, // STB_O strobe output
input wire wbs_ack_i, // ACK_I acknowledge input
input wire wbs_err_i, // ERR_I error input
input wire wbs_rty_i, // RTY_I retry input
output wire wbs_cyc_o // CYC_O cycle output
);
reg [ADDR_WIDTH-1:0] wbm_adr_i_reg = 0;
reg [DATA_WIDTH-1:0] wbm_dat_i_reg = 0;
reg [DATA_WIDTH-1:0] wbm_dat_o_reg = 0;
reg wbm_we_i_reg = 0;
reg [SELECT_WIDTH-1:0] wbm_sel_i_reg = 0;
reg wbm_stb_i_reg = 0;
reg wbm_ack_o_reg = 0;
reg wbm_err_o_reg = 0;
reg wbm_rty_o_reg = 0;
reg wbm_cyc_i_reg = 0;
reg wbm_done_sync1 = 0;
reg wbm_done_sync2 = 0;
reg wbm_done_sync3 = 0;
reg [ADDR_WIDTH-1:0] wbs_adr_o_reg = 0;
reg [DATA_WIDTH-1:0] wbs_dat_i_reg = 0;
reg [DATA_WIDTH-1:0] wbs_dat_o_reg = 0;
reg wbs_we_o_reg = 0;
reg [SELECT_WIDTH-1:0] wbs_sel_o_reg = 0;
reg wbs_stb_o_reg = 0;
reg wbs_ack_i_reg = 0;
reg wbs_err_i_reg = 0;
reg wbs_rty_i_reg = 0;
reg wbs_cyc_o_reg = 0;
reg wbs_cyc_o_sync1 = 0;
reg wbs_cyc_o_sync2 = 0;
reg wbs_cyc_o_sync3 = 0;
reg wbs_stb_o_sync1 = 0;
reg wbs_stb_o_sync2 = 0;
reg wbs_stb_o_sync3 = 0;
reg wbs_done_reg = 0;
assign wbm_dat_o = wbm_dat_o_reg;
assign wbm_ack_o = wbm_ack_o_reg;
assign wbm_err_o = wbm_err_o_reg;
assign wbm_rty_o = wbm_rty_o_reg;
assign wbs_adr_o = wbs_adr_o_reg;
assign wbs_dat_o = wbs_dat_o_reg;
assign wbs_we_o = wbs_we_o_reg;
assign wbs_sel_o = wbs_sel_o_reg;
assign wbs_stb_o = wbs_stb_o_reg;
assign wbs_cyc_o = wbs_cyc_o_reg;
// master side logic
always @(posedge wbm_clk) begin
if (wbm_rst) begin
wbm_adr_i_reg <= 0;
wbm_dat_i_reg <= 0;
wbm_dat_o_reg <= 0;
wbm_we_i_reg <= 0;
wbm_sel_i_reg <= 0;
wbm_stb_i_reg <= 0;
wbm_ack_o_reg <= 0;
wbm_err_o_reg <= 0;
wbm_rty_o_reg <= 0;
wbm_cyc_i_reg <= 0;
end else begin
if (wbm_cyc_i_reg & wbm_stb_i_reg) begin
// cycle - hold master
if (wbm_done_sync2 & ~wbm_done_sync3) begin
// end of cycle - store slave
wbm_dat_o_reg <= wbs_dat_i_reg;
wbm_ack_o_reg <= wbs_ack_i_reg;
wbm_err_o_reg <= wbs_err_i_reg;
wbm_rty_o_reg <= wbs_rty_i_reg;
wbm_we_i_reg <= 0;
wbm_stb_i_reg <= 0;
end
end else begin
// idle - store master
wbm_adr_i_reg <= wbm_adr_i;
wbm_dat_i_reg <= wbm_dat_i;
wbm_dat_o_reg <= 0;
wbm_we_i_reg <= wbm_we_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
wbm_sel_i_reg <= wbm_sel_i;
wbm_stb_i_reg <= wbm_stb_i & ~(wbm_ack_o | wbm_err_o | wbm_rty_o);
wbm_ack_o_reg <= 0;
wbm_err_o_reg <= 0;
wbm_rty_o_reg <= 0;
wbm_cyc_i_reg <= wbm_cyc_i;
end
end
// synchronize signals
wbm_done_sync1 <= wbs_done_reg;
wbm_done_sync2 <= wbm_done_sync1;
wbm_done_sync3 <= wbm_done_sync2;
end
// slave side logic
always @(posedge wbs_clk) begin
if (wbs_rst) begin
wbs_adr_o_reg <= 0;
wbs_dat_i_reg <= 0;
wbs_dat_o_reg <= 0;
wbs_we_o_reg <= 0;
wbs_sel_o_reg <= 0;
wbs_stb_o_reg <= 0;
wbs_ack_i_reg <= 0;
wbs_err_i_reg <= 0;
wbs_rty_i_reg <= 0;
wbs_cyc_o_reg <= 0;
wbs_done_reg <= 0;
end else begin
if (wbs_ack_i | wbs_err_i | wbs_rty_i) begin
// end of cycle - store slave
wbs_dat_i_reg <= wbs_dat_i;
wbs_ack_i_reg <= wbs_ack_i;
wbs_err_i_reg <= wbs_err_i;
wbs_rty_i_reg <= wbs_rty_i;
wbs_we_o_reg <= 0;
wbs_stb_o_reg <= 0;
wbs_done_reg <= 1;
end else if (wbs_stb_o_sync2 & ~wbs_stb_o_sync3) begin
// beginning of cycle - store master
wbs_adr_o_reg <= wbm_adr_i_reg;
wbs_dat_i_reg <= 0;
wbs_dat_o_reg <= wbm_dat_i_reg;
wbs_we_o_reg <= wbm_we_i_reg;
wbs_sel_o_reg <= wbm_sel_i_reg;
wbs_stb_o_reg <= wbm_stb_i_reg;
wbs_ack_i_reg <= 0;
wbs_err_i_reg <= 0;
wbs_rty_i_reg <= 0;
wbs_cyc_o_reg <= wbm_cyc_i_reg;
wbs_done_reg <= 0;
end else if (~wbs_cyc_o_sync2 & wbs_cyc_o_sync3) begin
// cyc deassert
wbs_adr_o_reg <= 0;
wbs_dat_i_reg <= 0;
wbs_dat_o_reg <= 0;
wbs_we_o_reg <= 0;
wbs_sel_o_reg <= 0;
wbs_stb_o_reg <= 0;
wbs_ack_i_reg <= 0;
wbs_err_i_reg <= 0;
wbs_rty_i_reg <= 0;
wbs_cyc_o_reg <= 0;
wbs_done_reg <= 0;
end
end
// synchronize signals
wbs_cyc_o_sync1 <= wbm_cyc_i_reg;
wbs_cyc_o_sync2 <= wbs_cyc_o_sync1;
wbs_cyc_o_sync3 <= wbs_cyc_o_sync2;
wbs_stb_o_sync1 <= wbm_stb_i_reg;
wbs_stb_o_sync2 <= wbs_stb_o_sync1;
wbs_stb_o_sync3 <= wbs_stb_o_sync2;
end
endmodule
|
#include <bits/stdc++.h> template <typename T> inline void read(T &x) { x = 0; char c = getchar(); bool flag = false; while (!isdigit(c)) { if (c == - ) flag = true; c = getchar(); } while (isdigit(c)) x = x * 10 + (c ^ 48), c = getchar(); if (flag) x = -x; } using namespace std; const int inf = 987654321; int n, m, s, t; struct edge { int nxt, to, val; edge() {} edge(int jzp, int zzz, int lsr) { nxt = jzp, to = zzz, val = lsr; } } e[5001000]; int head[101000], ecnt = 1, hcur[101000]; inline void addedge(int from, int to, int val) { e[++ecnt] = edge(head[from], to, val); head[from] = ecnt; } inline void Addedge(int u, int v, int w) { addedge(u, v, w), addedge(v, u, 0); } int ls[101000], rs[101000], root_in, root_out, ttot; void build_out(int L, int R, int &cur) { cur = ++ttot; if (L == R) return Addedge(s, cur, 1), void(); int mid = (L + R) >> 1; build_out(L, mid, ls[cur]), build_out(mid + 1, R, rs[cur]); Addedge(ls[cur], cur, inf); Addedge(rs[cur], cur, inf); } void build_in(int L, int R, int &cur) { cur = ++ttot; if (L == R) return Addedge(cur, t, 1), void(); int mid = (L + R) >> 1; build_in(L, mid, ls[cur]), build_in(mid + 1, R, rs[cur]); Addedge(cur, ls[cur], inf), Addedge(cur, rs[cur], inf); } void Addedge_out(int L, int R, int l, int r, int p, int cur) { if (l <= L && R <= r) return Addedge(cur, p, inf), void(); int mid = (L + R) >> 1; if (l <= mid) Addedge_out(L, mid, l, r, p, ls[cur]); if (r > mid) Addedge_out(mid + 1, R, l, r, p, rs[cur]); } void Addedge_in(int L, int R, int l, int r, int p, int cur) { if (l <= L && R <= r) return Addedge(p, cur, inf), void(); int mid = (L + R) >> 1; if (l <= mid) Addedge_in(L, mid, l, r, p, ls[cur]); if (r > mid) Addedge_in(mid + 1, R, l, r, p, rs[cur]); } inline void Seg_Addedge(int l, int r, int d, int u) { if (l > r || d > u) return; ++ttot; Addedge_out(1, n, l, r, ttot, root_out); Addedge_in(1, n, d, u, ttot, root_in); } struct node { int x, l, r, t; node() {} node(int jzp, int zzz, int lsr, int chr) { x = jzp, l = zzz, r = lsr, t = chr; } } nd[101000]; int ntot; inline bool cmp(const node &a, const node &b) { return a.x < b.x || (a.x == b.x && a.t > b.t); } struct ODT { int l, r, v; ODT() {} ODT(int jzp, int zzz, int lsr) { l = jzp, r = zzz, v = lsr; } inline bool operator<(const ODT &a) const { return l < a.l; } }; set<ODT> st; inline set<ODT>::iterator Split(int p) { if (p > n) return st.end(); set<ODT>::iterator it = --st.upper_bound(ODT(p, 0, 0)); if (it->l == p) return it; if (it->r < p) return ++it; int l = it->l, r = it->r, v = it->v; st.erase(it); st.insert(ODT(l, p - 1, v)); return st.insert(ODT(p, r, v)).first; } inline void Assign(int l, int r, int x) { set<ODT>::iterator itr = Split(r + 1), itl = Split(l); for (set<ODT>::iterator it = itl; it != itr; ++it) { Seg_Addedge(it->v, x - 1, it->l, it->r); } st.erase(itl, itr); } inline void Insert(int l, int r, int v) { st.insert(ODT(l, r, v)); } int dep[101000], que[101000], front, rear; inline bool bfs() { memset(dep, 0x3f, sizeof(dep)); front = rear = 0; for (int i = 1; i <= ttot; ++i) hcur[i] = head[i]; dep[s] = 0; que[++rear] = s; while (front < rear) { int cur = que[++front]; for (int i = head[cur]; i; i = e[i].nxt) { int to = e[i].to; if (!e[i].val || dep[to] < 5001000) continue; que[++rear] = to; dep[to] = dep[cur] + 1; } } return dep[t] <= 5001000; } int dfs(int cur, int limi) { if (cur == t || !limi) return limi; int flow = 0; for (int i = hcur[cur]; i; i = e[i].nxt) { int to = e[i].to; hcur[cur] = i; if (dep[to] != dep[cur] + 1) continue; int tmp = dfs(to, min(e[i].val, limi)); if (!tmp) continue; e[i].val -= tmp; e[i ^ 1].val += tmp; flow += tmp; limi -= tmp; if (!limi) break; } return flow; } int main() { read(n); read(m); for (int i = 1; i <= m; ++i) { int x_1, y_1, x_2, y_2; read(x_1), read(y_1), read(x_2), read(y_2); nd[++ntot] = node(x_1, y_1, y_2, 0); nd[++ntot] = node(x_2 + 1, y_1, y_2, 1); } sort(nd + 1, nd + 1 + ntot, cmp); s = 1, t = 2; ttot = 2; build_out(1, n, root_out); build_in(1, n, root_in); Insert(1, n, 1); for (int i = 1; i <= ntot; ++i) { int x = nd[i].x, l = nd[i].l, r = nd[i].r, t = nd[i].t; if (t == 0) { Assign(l, r, x); } else { Insert(l, r, x); } } for (set<ODT>::iterator it = st.begin(); it != st.end(); ++it) { Seg_Addedge(it->v, n, it->l, it->r); } int mxflow = 0; while (bfs()) mxflow += dfs(s, inf); printf( %d n , mxflow); return 0; } |
// MBT 7/7/2016
//
// 1 read-port, 1 write-port ram
//
// reads are synchronous
//
// although we could merge this with normal bsg_mem_1r1w
// and select with a parameter, we do not do this because
// it's typically a very big change to the instantiating code
// to move to/from sync/async, and we want to reflect this.
//
// NOTE: Users of BaseJump STL should not instantiate this module directly
// they should use bsg_mem_1r1w_sync.
`include "bsg_defines.v"
module bsg_mem_1r1w_sync_synth #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=0
)
(input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [`BSG_SAFE_MINUS(width_p, 1):0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [`BSG_SAFE_MINUS(width_p, 1):0] r_data_o
);
wire unused = reset_i;
if (width_p == 0)
begin: z
wire unused0 = &{clk_i, w_v_i, w_addr_i, r_v_i, r_addr_i};
assign r_data_o = '0;
end
else
begin: nz
logic [width_p-1:0] mem [els_p-1:0];
// this treats the ram as an array of registers for which the
// read addr is latched on the clock, the write
// is done on the clock edge, and actually multiplexing
// of the registers for reading is done after the clock edge.
// logically, this means that reads happen in time after
// the writes, and "simultaneous" reads and writes to the
// register file are allowed -- IF read_write_same_addr is set.
// note that this behavior is generally incompatible with
// hardened 1r1w rams, so it's better not to take advantage
// of it if not necessary
// we explicitly 'X out the read address if valid is not set
// to avoid accidental use of data when the valid signal was not
// asserted. without this, the output of the register file would
// "auto-update" based on new writes to the ram, a spooky behavior
// that would never correspond to that of a hardened ram.
logic [addr_width_lp-1:0] r_addr_r;
always_ff @(posedge clk_i)
if (r_v_i)
r_addr_r <= r_addr_i;
else
r_addr_r <= 'X;
assign r_data_o = mem[r_addr_r];
always_ff @(posedge clk_i)
if (w_v_i)
mem[w_addr_i] <= w_data_i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync_synth)
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2005; const int MOD = 1e9 + 7; long long int dp[MAXN][MAXN]; void c() { for (int i = 0; i < MAXN; i++) { for (int j = 0; j < MAXN; j++) { if (i == j) dp[i][j] = 1; else if (j == 0) dp[i][j] = 1; else if (i == 0) dp[i][j] = 0; else { dp[i][j] = (dp[i - 1][j - 1] + dp[i - 1][j]) % MOD; } } } } int main() { c(); int n, m, k; cin >> n >> m >> k; cout << (dp[n - 1][2 * k] * dp[m - 1][2 * k]) % MOD << n ; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 500; char s[MAX_N + 2][MAX_N + 2]; int D[2][MAX_N + 1][MAX_N + 1]; int main() { int N, M; scanf( %d%d n , &N, &M); for (int i = 0; i <= M; ++i) s[0][i] = # ; for (int i = 1; i <= N; ++i) { s[i][0] = # ; gets(s[i] + 1); } for (int i = 1; i <= N; ++i) for (int j = 1; j <= M; ++j) { D[0][i][j] = D[0][i - 1][j] + D[0][i][j - 1] - D[0][i - 1][j - 1] + (((s[i][j - 1] != # )) & -(s[i][j] != # )); D[1][i][j] = D[1][i - 1][j] + D[1][i][j - 1] - D[1][i - 1][j - 1] + (((s[i - 1][j] != # )) & -(s[i][j] != # )); } int numQuery; scanf( %d , &numQuery); while (numQuery--) { int x, y, X, Y; scanf( %d%d%d%d , &x, &y, &X, &Y); y++; int SUM = D[0][X][Y] - D[0][x - 1][Y] - D[0][X][y - 1] + D[0][x - 1][y - 1]; y--; x++; SUM += D[1][X][Y] - D[1][x - 1][Y] - D[1][X][y - 1] + D[1][x - 1][y - 1]; printf( %d n , SUM); } return 0; } |
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.3 (win64) Build Mon Sep 28 20:06:43 MDT 2015
// Date : Wed Mar 30 14:50:02 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/SKL/Desktop/ECE532/repo/streamed_encoder_ip_prj2/project_1.runs/mult_gen_0_synth_1/mult_gen_0_stub.v
// Design : mult_gen_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a200tsbg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_9,Vivado 2015.3" *)
module mult_gen_0(A, B, P)
/* synthesis syn_black_box black_box_pad_pin="A[32:0],B[13:0],P[53:0]" */;
input [32:0]A;
input [13:0]B;
output [53:0]P;
endmodule
|
#include <bits/stdc++.h> using namespace std; long double ans; long long one, two; map<pair<long long, long long>, pair<long long, long long> > o, t; map<pair<long long, long long>, pair<long long, long long> >::iterator ii; void add(long long a, long long b, long long c, long long ind) { pair<long long, long long> p = make_pair(a, b); if (c > o[p].first && ind != t[p].second) { t[p] = o[p]; o[p] = {c, ind}; } if (c > t[p].first && ind != o[p].second) t[p] = {c, ind}; } int main() { long long n, i, j; cin >> n; for (i = 1; i <= n; i++) { long long a, b, c; cin >> a >> b >> c; long long t = min(a, min(b, c)); long double cur = 1.0 * t / 2; if (cur > ans) { ans = cur; one = i; } add(a, b, c, i); add(a, c, b, i); add(b, a, c, i); add(b, c, a, i); add(c, a, b, i); add(c, b, a, i); } for (ii = t.begin(); ii != t.end(); ii++) { long long cur = ii->second.first + o[ii->first].first; long long Min = min(cur, min(ii->first.first, ii->first.second)); long double curans = 1.0 * Min / 2; if (curans > ans) { ans = curans; one = ii->second.second; two = o[ii->first].second; } } if (one != 0 && two != 0) cout << 2 n << one << << two; else cout << 1 n << one; return 0; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 25041 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w32,
w31,
w16384,
w16353,
w8192,
w24545,
w496,
w25041;
assign w1 = i_data0;
assign w16353 = w16384 - w31;
assign w16384 = w1 << 14;
assign w24545 = w16353 + w8192;
assign w25041 = w24545 + w496;
assign w31 = w32 - w1;
assign w32 = w1 << 5;
assign w496 = w31 << 4;
assign w8192 = w1 << 13;
assign o_data0 = w25041;
//multiplier_block area estimate = 6566.313589725;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for fg_ip_packet_gen
*/
module test_fg_ip_packet_gen;
// Parameters
parameter DEST_WIDTH = 8;
parameter DATA_WIDTH = 64;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter MAC_PREFIX = 48'hDA0000000000;
parameter IP_PREFIX = 32'hc0a80100;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg input_bd_valid = 0;
reg [DEST_WIDTH-1:0] input_bd_dest = 0;
reg [31:0] input_bd_burst_len = 0;
reg output_ip_hdr_ready = 0;
reg output_ip_payload_tready = 0;
reg [47:0] local_mac = 0;
reg [31:0] local_ip = 0;
reg [15:0] frame_mtu = 0;
reg dest_wr_en = 0;
reg [DEST_WIDTH-1:0] dest_index = 0;
reg [47:0] dest_mac = 0;
reg [31:0] dest_ip = 0;
// Outputs
wire input_bd_ready;
wire output_ip_hdr_valid;
wire [47:0] output_ip_eth_dest_mac;
wire [47:0] output_ip_eth_src_mac;
wire [15:0] output_ip_eth_type;
wire [5:0] output_ip_dscp;
wire [1:0] output_ip_ecn;
wire [15:0] output_ip_length;
wire [15:0] output_ip_identification;
wire [2:0] output_ip_flags;
wire [12:0] output_ip_fragment_offset;
wire [7:0] output_ip_ttl;
wire [7:0] output_ip_protocol;
wire [31:0] output_ip_source_ip;
wire [31:0] output_ip_dest_ip;
wire [DATA_WIDTH-1:0] output_ip_payload_tdata;
wire [KEEP_WIDTH-1:0] output_ip_payload_tkeep;
wire output_ip_payload_tvalid;
wire output_ip_payload_tlast;
wire output_ip_payload_tuser;
wire busy;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_bd_valid,
input_bd_dest,
input_bd_burst_len,
output_ip_hdr_ready,
output_ip_payload_tready,
local_mac,
local_ip,
frame_mtu,
dest_wr_en,
dest_index,
dest_mac,
dest_ip);
$to_myhdl(input_bd_ready,
output_ip_hdr_valid,
output_ip_eth_dest_mac,
output_ip_eth_src_mac,
output_ip_eth_type,
output_ip_dscp,
output_ip_ecn,
output_ip_length,
output_ip_identification,
output_ip_flags,
output_ip_fragment_offset,
output_ip_ttl,
output_ip_protocol,
output_ip_source_ip,
output_ip_dest_ip,
output_ip_payload_tdata,
output_ip_payload_tkeep,
output_ip_payload_tvalid,
output_ip_payload_tlast,
output_ip_payload_tuser,
busy);
// dump file
$dumpfile("test_fg_ip_packet_gen.lxt");
$dumpvars(0, test_fg_ip_packet_gen);
end
fg_ip_packet_gen #(
.DEST_WIDTH(DEST_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.MAC_PREFIX(MAC_PREFIX),
.IP_PREFIX (IP_PREFIX)
)
UUT (
.clk(clk),
.rst(rst),
.input_bd_valid(input_bd_valid),
.input_bd_ready(input_bd_ready),
.input_bd_dest(input_bd_dest),
.input_bd_burst_len(input_bd_burst_len),
.output_ip_hdr_valid(output_ip_hdr_valid),
.output_ip_hdr_ready(output_ip_hdr_ready),
.output_ip_eth_dest_mac(output_ip_eth_dest_mac),
.output_ip_eth_src_mac(output_ip_eth_src_mac),
.output_ip_eth_type(output_ip_eth_type),
.output_ip_dscp(output_ip_dscp),
.output_ip_ecn(output_ip_ecn),
.output_ip_length(output_ip_length),
.output_ip_identification(output_ip_identification),
.output_ip_flags(output_ip_flags),
.output_ip_fragment_offset(output_ip_fragment_offset),
.output_ip_ttl(output_ip_ttl),
.output_ip_protocol(output_ip_protocol),
.output_ip_source_ip(output_ip_source_ip),
.output_ip_dest_ip(output_ip_dest_ip),
.output_ip_payload_tdata(output_ip_payload_tdata),
.output_ip_payload_tkeep(output_ip_payload_tkeep),
.output_ip_payload_tvalid(output_ip_payload_tvalid),
.output_ip_payload_tready(output_ip_payload_tready),
.output_ip_payload_tlast(output_ip_payload_tlast),
.output_ip_payload_tuser(output_ip_payload_tuser),
.busy(busy),
.local_mac(local_mac),
.local_ip(local_ip),
.frame_mtu(frame_mtu),
.dest_wr_en(dest_wr_en),
.dest_index(dest_index),
.dest_mac(dest_mac),
.dest_ip(dest_ip)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
`ifdef ALLOW_UNOPT
/*verilator lint_off UNOPTFLAT*/
`endif
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] b; // From file of file.v
wire [31:0] c; // From file of file.v
wire [31:0] d; // From file of file.v
// End of automatics
file file (/*AUTOINST*/
// Outputs
.b (b[31:0]),
.c (c[31:0]),
.d (d[31:0]),
// Inputs
.crc (crc[31:0]));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n", $time, cyc, crc, sum, b, d);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {b, d}
^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h649ee1713d624dd9) $stop;
$finish;
end
end
endmodule
module file (/*AUTOARG*/
// Outputs
b, c, d,
// Inputs
crc
);
input [31:0] crc;
`ifdef ISOLATE
output reg [31:0] b /* verilator isolate_assignments*/;
`else
output reg [31:0] b;
`endif
output reg [31:0] c;
output reg [31:0] d;
always @* begin
// Note that while c and b depend on crc, b doesn't depend on c.
casez (crc[3:0])
4'b??01: begin
b = {crc[15:0],get_31_16(crc)};
d = c;
end
4'b??00: begin
b = {crc[15:0],~crc[31:16]};
d = {crc[15:0],~c[31:16]};
end
default: begin
set_b_d(crc, c);
end
endcase
end
`ifdef ISOLATE
function [31:16] get_31_16 /* verilator isolate_assignments*/;
input [31:0] t_crc /* verilator isolate_assignments*/;
get_31_16 = t_crc[31:16];
endfunction
`else
function [31:16] get_31_16;
input [31:0] t_crc;
get_31_16 = t_crc[31:16];
endfunction
`endif
task set_b_d;
`ifdef ISOLATE
input [31:0] t_crc /* verilator isolate_assignments*/;
input [31:0] t_c /* verilator isolate_assignments*/;
`else
input [31:0] t_crc;
input [31:0] t_c;
`endif
begin
b = {t_crc[31:16],~t_crc[23:8]};
d = {t_crc[31:16], ~t_c[23:8]};
end
endtask
always @* begin
// Any complicated equation we can't optimize
casez (crc[3:0])
4'b00??: begin
c = {b[29:0],2'b11};
end
4'b01??: begin
c = {b[30:1],2'b01};
end
4'b10??: begin
c = {b[31:2],2'b10};
end
4'b11??: begin
c = {b[31:2],2'b00};
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
module nkmd_dai_tx_t;
// ins
reg clk;
parameter TCLK = 20;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg rst;
reg pop;
reg [31:0] nkmd_data_i;
wire [31:0] nkmd_data_o;
reg [31:0] nkmd_addr;
reg nkmd_we;
nkmd_dai_tx uut(
.clk(clk),
.rst(rst),
.tx_pop_i(pop),
.data_i(nkmd_data_i),
.data_o(nkmd_data_o),
.addr_i(nkmd_addr),
.we_i(nkmd_we));
task queue;
input wire [23:0] sample;
begin
nkmd_addr = 32'h0000d001;
nkmd_data_i = {8'h0, sample};
nkmd_we = 1'b1;
#(TCLK);
nkmd_we = 1'b0;
end
endtask
task trigger_pop;
begin
pop = 1'b1;
#(TCLK);
pop = 1'b0;
end
endtask
reg [31:0] i;
initial begin
$dumpfile("nkmd_dai_tx_t.lxt");
$dumpvars(0, nkmd_dai_tx_t);
pop = 0;
nkmd_data_i = 32'h0;
nkmd_addr = 32'h0;
nkmd_we = 1'b0;
rst = 1'b1;
#(TCLK);
rst = 1'b0;
#(TCLK);
nkmd_addr = 32'h0000d001;
#(TCLK);
$display("expect %h, actual %h : queued_ff peek", 6'h0, uut.queued_ff);
$display("expect %h, actual %h : queued_ff ram read", 32'h0, nkmd_data_o);
queue(24'hcafebb);
nkmd_addr = 32'h0000e000;
#(TCLK);
$display("expect %h, actual %h : ringbuf ram read", 32'h00cafebb, nkmd_data_o);
nkmd_addr = 32'h0000d001;
#(TCLK);
$display("expect %h, actual %h : queued_ff peek", 6'h1, uut.queued_ff);
$display("expect %h, actual %h : queued_ff ram read", 32'h1, nkmd_data_o);
trigger_pop();
nkmd_addr = 32'h0000d001;
#(TCLK);
$display("expect %h, actual %h : queued_ff peek", 6'h0, uut.queued_ff);
$display("expect %h, actual %h : queued_ff ram read", 32'h0, nkmd_data_o);
for (i = 0; i < 63; i = i + 1) begin
queue(i);
end
$display("expect %h, actual %h : queued_ff peek", 6'd63, uut.queued_ff);
for (i = 0; i < 63; i = i + 1) begin
trigger_pop();
end
for (i = 63; i < 80; i = i + 1) begin
queue(i);
end
for (i = 63; i < 80; i = i + 1) begin
trigger_pop();
end
#(TCLK*3);
$finish(2);
end
always @(posedge clk) begin
if (uut.tx_ack_o)
$display("tx emit sample %h", uut.tx_data_o);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, ns, a[1111]; void ok(long long x) { long long l = 0, r = min(2000000000ll, (1ll << 62) / (x + 1) + 1); while (l < r) { long long m = (l + r) / 2; if (m * (m - 1) / 2 + m * x >= n) r = m; else l = m + 1; if (m * (m - 1) / 2 + m * x == n && m % 2) a[++ns] = m + m * x; } } int main() { while (cin >> n) { ns = 0; for (int i = 0; i < 62; i++) ok((1ll << i) - 1); if (!ns) cout << -1 << endl; else { for (int i = 1; i <= ns; i++) cout << a[i] << endl; } } return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ccx_iob_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ccx_iob_rptr (/*AUTOARG*/
// Outputs
sig_buf,
// Inputs
sig
);
// This repeater has 136 bits
output [135:0] sig_buf;
input [135:0] sig;
assign sig_buf = sig;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); for (int i = 0; i < n - 2; i++) { if (a[i] == a[i + 1] && a[i] == a[i + 2]) { cout << NO ; return 0; } } cout << YES << endl; vector<int> v1, v2; v1.push_back(a[0]); for (int i = 1; i < n; i++) { if (a[i] != a[i - 1]) v1.push_back(a[i]); else v2.push_back(a[i]); } int p = v1.size(); int r = v2.size(); cout << p << endl; for (int i = 0; i < p; i++) { cout << v1[i] << ; } cout << endl; cout << r << endl; for (int i = r - 1; i >= 0; i--) { cout << v2[i] << ; } } |
#include <bits/stdc++.h> using namespace std; template <class _T> inline _T sqr(const _T& x) { return x * x; } template <class _T> inline string tostr(const _T& a) { ostringstream os( ); os << a; return os.str(); } const long double PI = 3.1415926535897932384626433832795; const long double EPS = 1e-11; const int dx[4] = {0, -1, 0, 1}; const int dy[4] = {-1, 0, 1, 0}; int n, m, k; char a[1024][1024]; char a0[1024][1024]; int c[1024][1024]; bool u[1024][1024]; bool u2[12]; void dfs(int x, int y, int px, int py) { u[x][y] = true; int cnt = 0; int t[4] = {0, 1, 2, 3}; for (int i = 0; i < (int)(4); i++) { swap(t[i], t[rand() % 4]); } for (int l1 = 0; l1 < (int)(4); l1++) { int l = t[l1]; int xn = x + dx[l]; int yn = y + dy[l]; if (xn < 0 || xn >= n || yn < 0 || yn >= m || u[xn][yn] || a[xn][yn] == # ) continue; dfs(xn, yn, x, y); if (c[xn][yn] == -1) cnt++; } if (cnt) { for (int l = 0; l < (int)(4); l++) { int xn = x + dx[l]; int yn = y + dy[l]; if (xn < 0 || xn >= n || yn < 0 || yn >= m || a[xn][yn] == # || c[xn][yn] != -1 || (xn == px && yn == py)) continue; c[xn][yn] = k; } c[x][y] = k++; } } void dfs2(int x, int y, int col) { u[x][y] = true; for (int l = 0; l < (int)(4); l++) { int xn = x + dx[l]; int yn = y + dy[l]; if (xn < 0 || xn >= n || yn < 0 || yn >= m || a[xn][yn] == # ) continue; if (c[xn][yn] == col) { if (!u[xn][yn]) dfs2(xn, yn, col); } else if (a[xn][yn] != . ) { u2[a[xn][yn] - 0 ] = true; } } } void dfs3(int x, int y, int col, int nc) { a[x][y] = 0 + nc; c[x][y] = -1; for (int l = 0; l < (int)(4); l++) { int xn = x + dx[l]; int yn = y + dy[l]; if (xn < 0 || xn >= n || yn < 0 || yn >= m || a[xn][yn] == # ) continue; if (c[xn][yn] == col) { dfs3(xn, yn, col, nc); } } } int check(int x, int y) { int ans = 1; u[x][y] = true; for (int l = 0; l < (int)(4); l++) { int xn = x + dx[l]; int yn = y + dy[l]; if (xn < 0 || xn >= n || yn < 0 || yn >= m || u[xn][yn] || a[xn][yn] == # || a[xn][yn] != a[x][y]) continue; ans += check(xn, yn); } return ans; } int check2(int x, int y) { int ans = 1; u[x][y] = true; for (int l = 0; l < (int)(4); l++) { int xn = x + dx[l]; int yn = y + dy[l]; if (xn < 0 || xn >= n || yn < 0 || yn >= m || u[xn][yn] || a[xn][yn] == # || c[xn][yn] != c[x][y]) continue; ans += check2(xn, yn); } return ans; } int main() { cout << setiosflags(ios::fixed) << setprecision(10); srand(672465); memset(c, 0xff, sizeof(c)); scanf( %d%d , &n, &m); memset((a), 0, sizeof(a)); for (int i = 0; i < (int)(n); i++) { scanf( %s , a[i]); a[i][m] = 0 ; } memcpy(a0, a, sizeof(a)); memset((u), 0, sizeof(u)); k = 0; for (int i = 0; i < (int)(n); i++) { for (int j = 0; j < (int)(m); j++) { if (!u[i][j] && a[i][j] != # ) { dfs(i, j, -1, -1); if (c[i][j] == -1) { bool bb = true; for (int l = 0; l < (int)(4); l++) { int xn = i + dx[l]; int yn = j + dy[l]; if (xn < 0 || xn >= n || yn < 0 || yn >= m || a[xn][yn] == # ) continue; if (c[xn][yn] != -1) { c[i][j] = c[xn][yn]; bb = false; break; } } if (bb) { puts( -1 ); return 0; } } } } } memset((u), 0, sizeof(u)); for (int i = 0; i < (int)(n); i++) { for (int j = 0; j < (int)(m); j++) { if (!u[i][j] && a[i][j] != # ) { int cnt = check2(i, j); if (cnt < 2 || cnt > 5) { } } } } memset((u), 0, sizeof(u)); for (int i = 0; i < (int)(n); i++) { for (int j = 0; j < (int)(m); j++) { if (a[i][j] == . ) { memset((u2), 0, sizeof(u2)); dfs2(i, j, c[i][j]); bool bbb = true; for (int t = 0; t < (int)(12); t++) { if (!u2[t]) { dfs3(i, j, c[i][j], t); bbb = false; break; } } if (bbb) return 1; } } } memset((u), 0, sizeof(u)); for (int i = 0; i < (int)(n); i++) { for (int j = 0; j < (int)(m); j++) { if (a0[i][j] == # ) { if (a[i][j] != # ) cout << Botwa ! 1 ! << endl; } else { if (!isdigit(a[i][j])) cout << Botwa ! 2 ! << endl; } if (a[i][j] != # && !isdigit(a[i][j])) cout << a[ << i << ][ << j << ] = << a[i][j] << << endl; if (!u[i][j] && a[i][j] != # ) { int cnt = check(i, j); if (cnt < 2 || cnt > 5) { for (int ii = (-4); ii <= (int)(4); ii++) { for (int jj = (-4); jj <= (int)(4); jj++) { if (i + ii >= 0 && j + jj >= 0) cout << a[i + ii][j + jj]; } if (i + ii >= 0) cout << endl; } cout << ? << cnt << << a[i][j] << endl; } } } } for (int i = 0; i < (int)(n); i++) { puts(a[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; if (y1 == y2) cout << abs(x2 - x1) << n ; else if (x1 == x2) cout << abs(y2 - y1) << n ; else { int x, y; x = abs(x2 - x1); y = abs(y2 - y1); cout << x + y + 2 << n ; } } } |
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