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#include <bits/stdc++.h> using namespace std; inline int read() { int ans = 0; char ch = getchar(); while (!isdigit(ch)) { ch = getchar(); } while (isdigit(ch)) { ans = (ans << 3) + (ans << 1) + (ch ^ 48), ch = getchar(); } ans = ans + 0 + 0; return ans; } int first[100005], n, cnt, dep[100005]; double ans = 0; struct edge { int v, next; } e[100005 << 1]; inline void add(int u, int v) { e[++cnt].v = v, e[cnt].next = first[u], first[u] = cnt; } inline void dfs(int p, int fa) { for (int i = first[p]; i; i = e[i].next) { int v = e[i].v; if (v == fa) continue; dep[v] = dep[p] + 1, dfs(v, p); } } int main() { n = read(); for (int i = 1; i < n; ++i) { int u = read(), v = read(); add(u, v), add(v, u); } dep[1] = 1, dfs(1, 1); for (int i = 1; i <= n; ++i) ans += 1.0 / (1.0 * dep[i]); printf( %.20lf , ans); return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:48:47 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_ethernetlite_0_0/system_axi_ethernetlite_0_0_stub.v
// Design : system_axi_ethernetlite_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_ethernetlite,Vivado 2016.4" *)
module system_axi_ethernetlite_0_0(s_axi_aclk, s_axi_aresetn, ip2intc_irpt,
s_axi_awaddr, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid,
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, phy_tx_clk, phy_rx_clk,
phy_crs, phy_dv, phy_rx_data, phy_col, phy_rx_er, phy_rst_n, phy_tx_en, phy_tx_data, phy_mdio_i,
phy_mdio_o, phy_mdio_t, phy_mdc)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,ip2intc_irpt,s_axi_awaddr[12:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[12:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,phy_tx_clk,phy_rx_clk,phy_crs,phy_dv,phy_rx_data[3:0],phy_col,phy_rx_er,phy_rst_n,phy_tx_en,phy_tx_data[3:0],phy_mdio_i,phy_mdio_o,phy_mdio_t,phy_mdc" */;
input s_axi_aclk;
input s_axi_aresetn;
output ip2intc_irpt;
input [12:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [12:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
input phy_tx_clk;
input phy_rx_clk;
input phy_crs;
input phy_dv;
input [3:0]phy_rx_data;
input phy_col;
input phy_rx_er;
output phy_rst_n;
output phy_tx_en;
output [3:0]phy_tx_data;
input phy_mdio_i;
output phy_mdio_o;
output phy_mdio_t;
output phy_mdc;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int T = 1, inf = 10000000000; bool check(long long int n) { long long int flag = 1; while (n > 0) { if (n % 10 != 4 && n % 10 != 7) { flag = 0; break; } n /= 10; } return flag; } int main() { ios::sync_with_stdio(0); cin.tie(0); while (T--) { long long int n, sz = 3, ans = 0, blag = 0, u, mn, ev = 0, mx, mini, i, v, q, p, j, k, w, h, l, m, x, y, od = 0, total = 0, cc = 0, pp = 0, flag = 0, klag = 0, sum = 0; string s, s3, s1 = YES , s2 = NO ; bool ok = 0; cin >> n; for (i = 4; i <= n; i += 1) { if (n % i == 0) { if (check(i)) { cout << s1; return 0; } } } cout << s2; return 0; } return 0; } |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module Block_Mat_exit45_pro (
ap_clk,
ap_rst,
ap_start,
start_full_n,
ap_done,
ap_continue,
ap_idle,
ap_ready,
start_out,
start_write,
in_width,
in_height,
out_width,
out_height,
img_in_rows_V_out_din,
img_in_rows_V_out_full_n,
img_in_rows_V_out_write,
img_in_cols_V_out_din,
img_in_cols_V_out_full_n,
img_in_cols_V_out_write,
img_out_rows_V_out_din,
img_out_rows_V_out_full_n,
img_out_rows_V_out_write,
img_out_cols_V_out_din,
img_out_cols_V_out_full_n,
img_out_cols_V_out_write
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
input start_full_n;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
output start_out;
output start_write;
input [31:0] in_width;
input [31:0] in_height;
input [31:0] out_width;
input [31:0] out_height;
output [31:0] img_in_rows_V_out_din;
input img_in_rows_V_out_full_n;
output img_in_rows_V_out_write;
output [31:0] img_in_cols_V_out_din;
input img_in_cols_V_out_full_n;
output img_in_cols_V_out_write;
output [31:0] img_out_rows_V_out_din;
input img_out_rows_V_out_full_n;
output img_out_rows_V_out_write;
output [31:0] img_out_cols_V_out_din;
input img_out_cols_V_out_full_n;
output img_out_cols_V_out_write;
reg ap_done;
reg ap_idle;
reg start_write;
reg img_in_rows_V_out_write;
reg img_in_cols_V_out_write;
reg img_out_rows_V_out_write;
reg img_out_cols_V_out_write;
reg real_start;
reg start_once_reg;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg internal_ap_ready;
reg img_in_rows_V_out_blk_n;
reg img_in_cols_V_out_blk_n;
reg img_out_rows_V_out_blk_n;
reg img_out_cols_V_out_blk_n;
reg ap_block_state1;
reg [0:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 start_once_reg = 1'b0;
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 1'd1;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if ((~((real_start == 1'b0) | (img_out_cols_V_out_full_n == 1'b0) | (img_out_rows_V_out_full_n == 1'b0) | (img_in_cols_V_out_full_n == 1'b0) | (img_in_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
start_once_reg <= 1'b0;
end else begin
if (((internal_ap_ready == 1'b0) & (real_start == 1'b1))) begin
start_once_reg <= 1'b1;
end else if ((internal_ap_ready == 1'b1)) begin
start_once_reg <= 1'b0;
end
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (img_out_cols_V_out_full_n == 1'b0) | (img_out_rows_V_out_full_n == 1'b0) | (img_in_cols_V_out_full_n == 1'b0) | (img_in_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((real_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img_in_cols_V_out_blk_n = img_in_cols_V_out_full_n;
end else begin
img_in_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (img_out_cols_V_out_full_n == 1'b0) | (img_out_rows_V_out_full_n == 1'b0) | (img_in_cols_V_out_full_n == 1'b0) | (img_in_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_in_cols_V_out_write = 1'b1;
end else begin
img_in_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img_in_rows_V_out_blk_n = img_in_rows_V_out_full_n;
end else begin
img_in_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (img_out_cols_V_out_full_n == 1'b0) | (img_out_rows_V_out_full_n == 1'b0) | (img_in_cols_V_out_full_n == 1'b0) | (img_in_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_in_rows_V_out_write = 1'b1;
end else begin
img_in_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img_out_cols_V_out_blk_n = img_out_cols_V_out_full_n;
end else begin
img_out_cols_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (img_out_cols_V_out_full_n == 1'b0) | (img_out_rows_V_out_full_n == 1'b0) | (img_in_cols_V_out_full_n == 1'b0) | (img_in_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_out_cols_V_out_write = 1'b1;
end else begin
img_out_cols_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state1)) begin
img_out_rows_V_out_blk_n = img_out_rows_V_out_full_n;
end else begin
img_out_rows_V_out_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (img_out_cols_V_out_full_n == 1'b0) | (img_out_rows_V_out_full_n == 1'b0) | (img_in_cols_V_out_full_n == 1'b0) | (img_in_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
img_out_rows_V_out_write = 1'b1;
end else begin
img_out_rows_V_out_write = 1'b0;
end
end
always @ (*) begin
if ((~((real_start == 1'b0) | (img_out_cols_V_out_full_n == 1'b0) | (img_out_rows_V_out_full_n == 1'b0) | (img_in_cols_V_out_full_n == 1'b0) | (img_in_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
internal_ap_ready = 1'b1;
end else begin
internal_ap_ready = 1'b0;
end
end
always @ (*) begin
if (((start_full_n == 1'b0) & (start_once_reg == 1'b0))) begin
real_start = 1'b0;
end else begin
real_start = ap_start;
end
end
always @ (*) begin
if (((start_once_reg == 1'b0) & (real_start == 1'b1))) begin
start_write = 1'b1;
end else begin
start_write = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
always @ (*) begin
ap_block_state1 = ((real_start == 1'b0) | (img_out_cols_V_out_full_n == 1'b0) | (img_out_rows_V_out_full_n == 1'b0) | (img_in_cols_V_out_full_n == 1'b0) | (img_in_rows_V_out_full_n == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_ready = internal_ap_ready;
assign img_in_cols_V_out_din = in_width;
assign img_in_rows_V_out_din = in_height;
assign img_out_cols_V_out_din = out_width;
assign img_out_rows_V_out_din = out_height;
assign start_out = real_start;
endmodule //Block_Mat_exit45_pro
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 201001; const int MAXK = 51; const double inf = 1e100; const double eps = 1e-10; int K, N; int tab[MAXN]; long long sum[MAXN]; double res[MAXN]; double odw[MAXN]; double dp[MAXK][MAXN]; struct Pt { double x, y; }; int ccw(const Pt& a, const Pt& b, const Pt& c) { double w = 0; w += a.x * (b.y - c.y); w += b.x * (c.y - a.y); w += c.x * (a.y - b.y); return w < -eps ? -1 : w > eps; } int main() { scanf( %d %d , &N, &K); for (int i = (1); i <= (N); ++i) { scanf( %d , &tab[i]); sum[i] = sum[i - 1] + tab[i]; odw[i] = odw[i - 1] + 1. / tab[i]; res[i] = res[i - 1] + (double)sum[i] / tab[i]; } for (int i = (1); i <= (N); ++i) dp[1][i] = res[i]; for (int k = (2); k <= (K); ++k) { vector<Pt> v; for (int i = (k - 1); i <= (N); ++i) { Pt pt = {-1. * sum[i], dp[k - 1][i] - res[i] + sum[i] * odw[i]}; while (v.size() >= 2 && ccw(v[((int)((v).size())) - 2], v.back(), pt) > 0) v.pop_back(); v.push_back(pt); } int p = 0; for (int i = (k); i <= (N); ++i) { while (p + 1 < ((int)((v).size())) && v[p].x * odw[i] + v[p].y > v[p + 1].x * odw[i] + v[p + 1].y) ++p; dp[k][i] = v[p].x * odw[i] + v[p].y + res[i]; } } printf( %.10lf n , dp[K][N]); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BAI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O21BAI_FUNCTIONAL_PP_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o21bai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BAI_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_PP_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBN_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxN = 1000009; map<string, int> mapa; int n, m, k, a, parent[maxN], used[maxN], rozmiar[maxN], centr[maxN], q; vector<int> graf[maxN]; string s, s1; void DFS(int start) { used[start] = 1; for (int i = 0; i < graf[start].size(); i++) { if (!used[graf[start][i]]) { DFS(graf[start][i]); rozmiar[start] += rozmiar[graf[start][i]]; } } rozmiar[start]++; for (int i = 0; i < graf[start].size(); i++) { if (graf[start][i] != parent[start]) { if (rozmiar[graf[start][i]] > rozmiar[start] / 2) { if (rozmiar[start] - rozmiar[centr[graf[start][i]]] <= rozmiar[start] / 2) centr[start] = centr[graf[start][i]]; else { int x = parent[centr[graf[start][i]]]; while (1) { if (rozmiar[start] - rozmiar[x] <= rozmiar[start] / 2) { centr[start] = x; break; } x = parent[x]; } } } } } if (centr[start] == 0) centr[start] = start; } int main() { scanf( %d%d , &n, &q); for (int i = 2; i <= n; i++) { scanf( %d , &a); parent[i] = a; graf[i].push_back(a); graf[a].push_back(i); } DFS(1); for (int i = 0; i < q; i++) { scanf( %d , &a); printf( %d n , centr[a]); } return 0; } |
#include <bits/stdc++.h> #define endl n #define IOS ios::sync_with_stdio(false); cin.tie(nullptr), cout.tie(nullptr) using namespace std; typedef long long LL; typedef pair<int, int> PII; const int maxn = 1e3 + 5; string input; int cnt[maxn], mx; double a, b; inline double randrand(){ return (double ) rand() / RAND_MAX; } int main(){ IOS; srand(time(nullptr)); int n, m, c1, c2; char c; cin >> n >> m; for(int j = 0; j < m; j++){ cin >> input; a = b = 0; if(j){ for (int i = 0; i < n; i++){ if (input[i] == 0 ) { a += pow(0.9, cnt[i]); } else { b += pow(0.9, cnt[i]); } } } if(a == b) cout << 1 << endl; else cout << (randrand() <= a / (a + b) ? 0 : 1) << endl; cout.flush(); cin >> c; for(int i = 0; i < n; i++){ cnt[i] += (input[i] != c); } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__BUF_PP_SYMBOL_V
/**
* buf: Buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__buf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; int n, m, f = 0; cin >> n >> m; cin >> s; for (int i = 0; i < n; i++) { if (s[i] == # ) f++; else f = 0; if (f >= m) { cout << NO ; return 0; } } cout << YES ; return 0; } |
#include <bits/stdc++.h> using namespace std; void fast() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } long long gcd(long long a, long long b) { if (b == 0) return a; else gcd(b, a % b); } long long lcd(long long a, long long b) { return (a * b) / gcd(a, b); } int main() { int t; cin >> t; while (t--) { int n, a[100] = {0}; vector<int> v; cin >> n; for (int i = 0; i < 2 * n; i++) { int temp; cin >> temp; if (a[temp] == 0) v.push_back(temp); a[temp] = 1; } for (int i = 0; i < v.size(); i++) cout << v[i] << ; cout << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S2S_SYMBOL_V
`define SKY130_FD_SC_LP__DLYMETAL6S2S_SYMBOL_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlymetal6s2s (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S2S_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int v[3005], inv = 0, n; double sol; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> v[i]; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) if (v[i] > v[j]) inv++; sol = double(inv) - inv / 2 + (inv / 2) * 3.0; cout << fixed; cout << setprecision(6); cout << sol << n ; return 0; } |
#include <bits/stdc++.h> void out(int x) { if (x) { std::cout << x << std::endl; } else { std::cout << Impossible << std::endl; } exit(0); } bool string_is_palindorome(const std::string& s) { for (int i = 0, j = s.size() - 1; i < j; i++, j--) if (s[i] != s[j]) return false; return true; } int main(int argc, char** argv) { std::cin.tie(0); std::ios_base::sync_with_stdio(0); std::cout << std::fixed << std::setprecision(6); std::cerr << std::fixed << std::setprecision(6); std::string s, t; std::cin >> s; t = s; int size = s.size(); if (size <= 3) out(0); for (int i = 1; i < size; i++) { std::rotate(std::begin(t), std::begin(t) + 1, std::end(t)); if (!string_is_palindorome(t)) continue; if (t != s) out(1); } for (int i = 1; i <= size / 2; i++) for (int j = 0, k = size - i; j < i; j++, k++) { assert(k < size); if (s[k] != s[j]) out(2); } out(0); return 0; } |
#include <bits/stdc++.h> int main() { int n, x, y, z, sum1 = 0, sum2 = 0, sum3 = 0; scanf( %d , &n); while (n--) { scanf( %d %d %d , &x, &y, &z); sum1 = sum1 + x; sum2 = sum2 + y; sum3 = sum3 + z; } if (sum1 == 0 && sum2 == 0 && sum3 == 0) printf( YES ); else printf( NO ); return 0; } |
module tenv_descstd_device();
//IFACE
reg[7:0] bNumConfigurations=8'h00;
reg[7:0] iSerialNumber=8'h00;
reg[7:0] iProduct=8'h00;
reg[7:0] iManufacturer=8'h00;
reg[15:0] bcdDevice=16'h0000;
reg[15:0] idProduct=16'h0000;
reg[15:0] idVendor=16'h0000;
reg[7:0] bMaxPacketSize0=8'h08;
reg[7:0] bDeviceProtocol=8'hFF;
reg[7:0] bDeviceSubClass=8'hFF;
reg[7:0] bDeviceClass=8'hFF;
reg[15:0] bcdUSB=16'h0110;
reg[7:0] bDescriptorType=8'h01;
reg[7:0] bLength=8'd18;
reg[(18*8)-1:0] data_bybit;
reg[7:0] data_bybyte[17:0];
//LOCAL
integer i;
initial
begin
data_bybit={
bNumConfigurations,
iSerialNumber,
iProduct,
iManufacturer,
bcdDevice,
idProduct,
idVendor,
bMaxPacketSize0,
bDeviceProtocol,
bDeviceSubClass,
bDeviceClass,
bcdUSB,
bDescriptorType,
bLength
};
i=0;
while(i<(18*8))
begin
data_bybyte[i/8][i%8]=data_bybit[i];
i= i+1;
end
end
endmodule
|
#include <bits/stdc++.h> using std::list; const int N = 128; struct car { int coord, length, req; }; list<car> cars; int InsertCar(int length, int req, int b, int f) { list<car>::iterator i = cars.begin(), j = ++cars.begin(); int from, to; while (j != cars.end()) { from = i->coord + i->length + b; to = j->coord - f; if (to - from >= length) { cars.insert(j, (car){from, length, req}); return from; } ++i, ++j; } return -1; } void DeleteCar(int req) { list<car>::iterator i = cars.begin(); while (i != cars.end()) { if (i->req == req) { cars.erase(i); break; } ++i; } } int main() { int l, b, f, n; scanf( %d%d%d%d , &l, &b, &f, &n); cars.push_back((car){-b, 0, -1}); cars.push_back((car){l + f, 0, -1}); int type, req; for (int i = 0; i < n; ++i) { scanf( %d%d , &type, &req); if (type == 1) printf( %d n , InsertCar(req, i, b, f)); else DeleteCar(req - 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, a[1010], b[1010], cnt, x[1010], y[1010], z[1010], w[1010]; int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &a[i]); for (int i = 1; i <= n; ++i) scanf( %d , &b[i]); for (int i = 1; i <= n; ++i) { if (a[i] == i && b[i] == i) continue; ++cnt; for (int j = i; j <= n; ++j) if (a[j] == i) x[cnt] = j, y[cnt] = i, swap(a[j], a[i]); for (int j = i; j <= n; ++j) if (b[j] == i) z[cnt] = i, w[cnt] = j, swap(b[j], b[i]); } printf( %d n , cnt); for (int i = 1; i <= cnt; ++i) printf( %d %d %d %d n , x[i], y[i], z[i], w[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1e9 + 9; const int Mod = 1e9 + 7; inline int dcmp(double x) { if (fabs(x) <= 1e-9) return 0; return x < 0 ? -1 : 1; } inline int scan() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } inline long long scan(long long x) { int f = 1; char ch = getchar(); x = 0; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } struct Point { int x, y, id; Point(int x = 0, int y = 0) : x(x), y(y) {} Point operator-(const Point &a) const { return Point(x - a.x, y - a.y); } Point operator*(const long long &a) const { return Point(x * a, y * a); } Point operator+(const Point &a) const { return Point(x + a.x, y + a.y); } bool operator==(const Point &a) const { return dcmp(x - a.x) == 0 && dcmp(y - a.y) == 0; } bool operator<(const Point &a) const { if (x == a.x) return y < a.y; return x < a.x; } void read() { scanf( %d%d , &x, &y); } void out() { cout << x << << y << endl; } }; double Dot(Point a, Point b) { return a.x * b.x + a.y * b.y; } double dis(Point a) { return sqrt(Dot(a, a)); } long long Cross(Point a, Point b) { return a.x * 1LL * b.y - a.y * 1LL * b.x; } bool chk(Point p1, Point p2, Point p3, Point p) { return abs(Cross(p2 - p, p1 - p)) + abs(Cross(p3 - p, p2 - p)) + abs(Cross(p1 - p, p3 - p)) == abs(Cross(p2 - p1, p3 - p1)); } int n, k, ti; int a[200005], vis[200005]; void solve() { n = scan(); k = scan(); for (int i = 1; i <= n; i++) a[i] = scan(); memset(vis, 0, sizeof(vis)); sort(a + 1, a + 1 + n); for (int i = 1; i <= n; i++) { ti = i; while (ti - 1) { ti--; if (vis[ti]) break; if (a[ti] + k < a[i]) break; if (a[ti] < a[i]) vis[ti] = 1; else break; } } ti = 0; for (int i = 1; i <= n; i++) { if (!vis[i]) ti++; } cout << ti << endl; } int main() { int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int const maxn = 4e6; int tr01[maxn][2], x; int len, check[maxn], n, tot; void insert(int x) { int ex, v = 0; for (int i = 29; i >= 0; i--) { ex = !!(x & (1 << i)); if (tr01[v][ex]) v = tr01[v][ex]; else { tr01[v][ex] = ++tot; v = tot; } } } void init() { tot = 0; memset(tr01, 0, sizeof(tr01)); } int work(int x, int wei) { if (!tr01[x][0] && !tr01[x][1]) return 0; if (tr01[x][0] == 0) return work(tr01[x][1], wei - 1); if (tr01[x][1] == 0) return work(tr01[x][0], wei - 1); return (1 << wei) + min(work(tr01[x][1], wei - 1), work(tr01[x][0], wei - 1)); } int main() { scanf( %d , &n); init(); for (int i = 1; i <= n; i++) { scanf( %d , &x); insert(x); } printf( %d n , work(0, 29)); return 0; } |
#include <bits/stdc++.h> using namespace std; void run(); signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cout << fixed << setprecision(3); srand(42); run(); } template <typename T1, typename T2> bool mini(T1 &a, const T2 &b) { if (a > b) { a = b; return true; } return false; } template <typename T1, typename T2> bool maxi(T1 &a, const T2 &b) { if (a < b) { a = b; return true; } return false; } const long long N = 52; long long rcnt[N]; long long ccnt[N]; void run() { long long n, m; cin >> n >> m; set<long long> masks; for (long long i = 0; i < n; i++) { long long kek = 0; for (long long j = 0; j < m; j++) { char c; cin >> c; if (c == # ) kek |= (1LL << j); } masks.insert(kek); } for (auto it1 = masks.begin(); it1 != masks.end(); it1++) { auto it2 = it1; it2++; for (; it2 != masks.end(); it2++) { if ((*it1) & (*(it2))) { cout << No ; return; } } } cout << Yes ; } |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Idle Inserter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & out_ready) begin
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
received_esc <= 1;
end else begin
received_esc <= 0;
end
end
end
end
always @* begin
//we are always valid
out_valid = 1'b1;
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
in_data; //send data
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, c, b; long ans = 0; cin >> n >> m; long a[n + 1]; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 0; i < m; i++) { cin >> c >> b; ans += min(a[c], a[b]); } cout << ans; } |
module Sec6_SM(
//input [7:0] data,
input clk_i,
input reset_n,
output reg [2:0] sel
//output [6:0] segments
);
reg [1:0] state;
reg [1:0] state_next;
reg [3:0] num_int; //Internal number storage
parameter S0 = 2'b00; //Disp Digit 1
parameter S1 = 2'b01; //Disp Digit 2
parameter S2 = 2'b10; //Disp Digit 3
parameter S3 = 2'b11; //Disp Digit 4
//Async reset
always @ (posedge clk_i, negedge reset_n)
begin
if(!reset_n)
state <= S0;
else
state <= state_next;
end
//Next state logic
always @ (*)
begin
case(state)
S0: state_next = S1;
S1: state_next = S2;
S2: state_next = S3;
S3: state_next = S0;
default: state_next = S0;
endcase
end
//"Determine #" Block
always @ (*)
begin
case (state)
S0:
begin
sel = 3'b000; //Select Digit 1
// num_int = 4'd4;
end
S1:
begin
sel = 3'b001; //Select Digit 2
// num_int = 4'd3;
end
S2:
begin
sel = 3'b011; //Select Digit 3
// num_int = 4'd2;
end
S3:
begin
sel = 3'b100; //Select Digit 4
// num_int = 4'd1;
end
endcase
end
// sevenSeg segDecoder(num_int, segments);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__MAJ3_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__MAJ3_PP_BLACKBOX_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__maj3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__MAJ3_PP_BLACKBOX_V
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
wire psl_valid_test_expr;
reg xzdetect_bit;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
assign psl_valid_test_expr = ~(test_expr ^ test_expr);
always@( reset_n or psl_valid_test_expr )
begin
if( reset_n == 1'b0 )
begin
xzdetect_bit = 1'b0;
end
else
begin
if( psl_valid_test_expr )
begin
//Do nothing
end
else
begin
xzdetect_bit = ~xzdetect_bit;
end
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin : assert_checks
assert_proposition_assert
assert_proposition_assert (
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.xzdetect_bit(xzdetect_bit),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_proposition.vlib
//Module to be replicated for assert checks
//This module is bound to the PSL vunits with assert checks
module assert_proposition_assert (reset_n, test_expr, xzdetect_bit, xzcheck_enable);
input reset_n, test_expr;
input xzdetect_bit, xzcheck_enable;
endmodule
|
/*******************************************************************************
* Module: simul_axi_master_wraddr
* Date:2014-03-24
* Author: Andrey Filippov
* Description: Simulation model for AXI write address channel
*
* Copyright (c) 2014 Elphel, Inc..
* simul_axi_master_wraddr.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_axi_master_wraddr.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module simul_axi_master_wraddr
#(
parameter integer ID_WIDTH=12,
parameter integer ADDRESS_WIDTH=32,
parameter integer LATENCY=0, // minimal delay between inout and output ( 0 - next cycle)
parameter integer DEPTH=8, // maximal number of commands in FIFO
parameter DATA_DELAY = 3.5,
parameter VALID_DELAY = 4.0
)(
input clk,
input reset,
input [ID_WIDTH-1:0] awid_in,
input [ADDRESS_WIDTH-1:0] awaddr_in,
input [3:0] awlen_in,
input [1:0] awsize_in,
input [1:0] awburst_in,
input [3:0] awcache_in,
input [2:0] awprot_in,
output [ID_WIDTH-1:0] awid,
output [ADDRESS_WIDTH-1:0] awaddr,
output [3:0] awlen,
output [1:0] awsize,
output [1:0] awburst,
output [3:0] awcache,
output [2:0] awprot,
output awvalid,
input awready,
input set_cmd, // latch all other input data at posedge of clock
output ready // command/data FIFO can accept command
);
wire [ID_WIDTH-1:0] awid_out;
wire [ADDRESS_WIDTH-1:0] awaddr_out;
wire [3:0] awlen_out;
wire [1:0] awsize_out;
wire [1:0] awburst_out;
wire [3:0] awcache_out;
wire [2:0] awprot_out;
wire awvalid_out;
assign #(DATA_DELAY) awid= awid_out;
assign #(DATA_DELAY) awaddr= awaddr_out;
assign #(DATA_DELAY) awlen= awlen_out;
assign #(DATA_DELAY) awsize= awsize_out;
assign #(DATA_DELAY) awburst= awburst_out;
assign #(DATA_DELAY) awcache= awcache_out;
assign #(DATA_DELAY) awprot= awprot_out;
assign #(VALID_DELAY) awvalid= awvalid_out;
simul_axi_fifo
#(
.WIDTH(ID_WIDTH+ADDRESS_WIDTH+15), // total number of output bits
.LATENCY(LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(DEPTH) // maximal number of commands in FIFO
// parameter OUT_DELAY = 3.5,
) simul_axi_fifo_i (
.clk(clk), // input clk,
.reset(reset), // input reset,
.data_in({awid_in,awaddr_in,awlen_in,awsize_in,awburst_in,awcache_in,awprot_in}), // input [WIDTH-1:0] data_in,
.load(set_cmd), // input load,
.input_ready(ready), // output input_ready,
.data_out({awid_out,awaddr_out,awlen_out,awsize_out,awburst_out,awcache_out,awprot_out}), // output [WIDTH-1:0] data_out,
.valid(awvalid_out), // output valid,
.ready(awready)); // input ready);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1000000000 + 7; const double esp = 1e-13; struct node { int x, y; bool operator<(const node &op) const { return op.x > x || (op.x == x && op.y > y); } } a[2000 + 10]; int h, w, n; long long res[2000 + 10], gt[200000 + 10], rev[200000 + 10]; long long power(long long a, long long n) { long long ans = 1; while (n) { if (n % 2) ans = ans * a % INF; a = a * a % INF; n /= 2; } return ans; } long long C(int n, int k) { return gt[n] * rev[k] % INF * rev[n - k] % INF; } int main() { ios_base::sync_with_stdio(false); cin.tie(); cin >> h >> w >> n; for (long long i = 1; i <= n; i++) cin >> a[i].x >> a[i].y; a[++n] = {h, w}; sort(a + 1, a + n + 1); gt[0] = 1; rev[0] = power(1, INF - 2); for (long long i = 1; i <= 200000; i++) { gt[i] = gt[i - 1] * i % INF; rev[i] = power(gt[i], INF - 2); } for (long long i = 1; i <= n; i++) { res[i] = C(a[i].x + a[i].y - 2, a[i].x - 1); for (long long j = 1; j <= i - 1; j++) if (a[i].x >= a[j].x && a[i].y >= a[j].y) { res[i] -= res[j] * C(a[i].x - a[j].x + a[i].y - a[j].y, a[i].x - a[j].x) % INF; if (res[i] < 0) res[i] += INF; } } cout << res[n]; } |
#include <bits/stdc++.h> using namespace std; int main() { long long m, n, p[30], ans; cin >> m >> n; for (__typeof(0) i = 0; i <= n - 1; i++) { cout << 1 n ; fflush(stdout); cin >> ans; if (ans == 0) return 0; if (ans == -1) p[i] = 0; else p[i] = 1; } long long low = 1, high = m, mid, i = 0; while (low <= high) { mid = (low + high) / 2; cout << mid << n ; fflush(stdout); cin >> ans; if (p[i] == 0) ans *= -1; i = (i + 1) % n; if (ans == 0 || ans == -2 || ans == 2) return 0; if (ans == -1) high = mid - 1; else if (ans == 1) low = mid + 1; else return 0; } return 0; } |
module testbench_BoothPPG_32R4_NORM();
reg[31:0] mulcand;
reg[2:0] r4input;
reg sign;
wire[33:0] pp;
reg[33:0] expectPP;
task check(input [31:0]cand);
reg[3:0] i;
reg errorFlag;
begin
errorFlag = 0;
mulcand = cand;
sign = 1;
for(i = 4'b0;i <= 4'b0111; i = i+1) begin
r4input = i;
case(i[2:0])
3'b000: expectPP[32:0] = 33'b0;
3'b001: expectPP[32:0] = {cand[31], cand[31:0]};
3'b010: expectPP[32:0] = {cand[31], cand[31:0]};
3'b011: expectPP[32:0] = {cand[31:0], 1'b0};
3'b100: expectPP[32:0] = ~{cand[31:0], 1'b0};
3'b101: expectPP[32:0] = ~{cand[31], cand[31:0]};
3'b110: expectPP[32:0] = ~{cand[31], cand[31:0]};
3'b111: expectPP[32:0] = ~33'b0;
endcase
expectPP[33] = expectPP[32];
#10;
if(pp !== expectPP) begin
$display("fail: cand = %x, r4input = %3b, sign = %x, expect pp = %x, but actual pp = %x", cand , r4input, sign, expectPP, pp);
errorFlag = 1;
end
end
sign = 0;
for(i = 4'b0;i <= 4'b0111; i = i+1) begin
r4input = i;
case(i[2:0])
3'b000: expectPP[32:0] = 33'b0;
3'b001: expectPP[32:0] = {1'b0, cand[31:0]};
3'b010: expectPP[32:0] = {1'b0, cand[31:0]};
3'b011: expectPP[32:0] = {cand[31:0], 1'b0};
3'b100: expectPP[32:0] = ~{cand[31:0], 1'b0};
3'b101: expectPP[32:0] = ~{1'b0, cand[31:0]};
3'b110: expectPP[32:0] = ~{1'b0, cand[31:0]};
3'b111: expectPP[32:0] = ~33'b0;
endcase
expectPP[33] = r4input[2];
#10;
if(pp !== expectPP) begin
$display("fail: cand = %x, r4input = %3b, sign = %x, expect pp = %x, but actual pp = %x", cand , r4input, sign, expectPP, pp);
errorFlag = 1;
end
end
if(errorFlag === 0) begin
$display("mulcand = %x passed", cand);
end
else begin
$display("mulcand = %x failed", cand);
end
end
endtask
integer loopchk;
initial begin
for(loopchk = 0; loopchk < 100; loopchk = loopchk+1) begin
check($random());
end
check(32'h00000001);
check(32'h00000001);
check(32'h10000001);
check(32'hffffffff);
check(32'hdeadbeef);
end
BoothPPG_32R4_NORM ppg(.mulcand(mulcand), .r4input(r4input), .sign(sign), .pp(pp));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 1; int plot[MAX], n, k; void input() { cin >> n >> k; for (int i = 1; i <= n; i++) scanf( %d , &plot[i]); } int main() { input(); int res = 0, k1 = 0, k2 = 0; for (int i = 1; i <= n; i++) { if (plot[i] != k1) k2++; if (plot[i] == k1) res = max(res, k2), k2 = 1; k1 = plot[i]; } res = max(res, k2); cout << res; } |
// $Id: c_regfile.v 1922 2010-04-15 03:47:49Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// generic register file
module c_regfile
(clk, write_enable, write_address, write_data, read_address, read_data);
`include "c_functions.v"
`include "c_constants.v"
// number of entries
parameter depth = 8;
// width of each entry
parameter width = 64;
// number of read ports
parameter num_read_ports = 1;
// select implementation variant
parameter regfile_type = `REGFILE_TYPE_FF_2D;
// width required to swelect an entry
localparam addr_width = clogb(depth);
input clk;
// if high, write to entry selected by write_address
input write_enable;
// entry to be written to
input [0:addr_width-1] write_address;
// data to be written
input [0:width-1] write_data;
// entry to read out
input [0:num_read_ports*addr_width-1] read_address;
// contents of entry selected by read_address
output [0:num_read_ports*width-1] read_data;
wire [0:num_read_ports*width-1] read_data;
genvar level;
genvar read_port;
generate
case(regfile_type)
`REGFILE_TYPE_FF_2D, `REGFILE_TYPE_LAT_2D:
begin
reg [0:width-1] storage [0:depth-1];
case(regfile_type)
`REGFILE_TYPE_FF_2D:
always @(posedge clk)
if(write_enable)
storage[write_address] <= write_data;
`REGFILE_TYPE_LAT_2D:
always @(clk, write_enable, write_address, write_data)
if(~clk)
if(write_enable)
storage[write_address] <= write_data;
endcase
for(read_port = 0; read_port < num_read_ports;
read_port = read_port + 1)
begin:read_ports
wire [0:addr_width-1] port_read_address;
assign port_read_address
= read_address[read_port*addr_width:
(read_port+1)*addr_width-1];
wire [0:width-1] port_read_data;
assign port_read_data = storage[port_read_address];
assign read_data[read_port*width:(read_port+1)*width-1]
= port_read_data;
end
end
`REGFILE_TYPE_FF_1D_MUX, `REGFILE_TYPE_LAT_1D_MUX:
begin
wire [0:depth*width-1] read_data_lvl;
for(level = 0; level < depth; level = level + 1)
begin:mux_levels
wire write;
assign write = write_enable && (write_address == level);
reg [0:width-1] storage;
case(regfile_type)
`REGFILE_TYPE_FF_1D_MUX:
always @(posedge clk)
if(write)
storage <= write_data;
`REGFILE_TYPE_LAT_1D_MUX:
always @(clk, write, write_data)
if(~clk)
if(write)
storage <= write_data;
endcase
assign read_data_lvl[level*width:(level+1)*width-1] = storage;
end
assign read_data = read_data_lvl[read_address*width +: width];
end
`REGFILE_TYPE_FF_1D_TRISTATE, `REGFILE_TYPE_LAT_1D_TRISTATE:
begin
for(level = 0; level < depth; level = level + 1)
begin:tristate_levels
wire write;
assign write = write_enable && (write_address == level);
reg [0:width-1] storage;
case(regfile_type)
`REGFILE_TYPE_FF_1D_TRISTATE:
always @(posedge clk)
if(write)
storage <= write_data;
`REGFILE_TYPE_LAT_1D_TRISTATE:
always @(clk, write, write_data)
if(~clk)
if(write)
storage <= write_data;
endcase
for(read_port = 0; read_port < num_read_ports;
read_port = read_port + 1)
begin:read_ports
wire [0:addr_width-1] port_read_address;
assign port_read_address
= read_address[read_port*addr_width:
(read_port+1)*addr_width-1];
wire read;
assign read = (port_read_address == level);
wire [0:width-1] port_read_data;
assign port_read_data = read ? storage : {width{1'bz}};
assign read_data[read_port*width:(read_port+1)*width-1]
= port_read_data;
end
end
end
`REGFILE_TYPE_FF_DW, `REGFILE_TYPE_LAT_DW:
begin
wire write_enable_b;
assign write_enable_b = ~write_enable;
case(num_read_ports)
1:
begin
case(regfile_type)
`REGFILE_TYPE_FF_DW:
begin
DW_ram_r_w_s_dff
#(.data_width(width),
.depth(depth),
.rst_mode(1))
DW_rf_dff
(.clk(clk),
.rst_n(1'b1),
.cs_n(write_enable_b),
.wr_n(write_enable_b),
.rd_addr(read_address),
.wr_addr(write_address),
.data_in(write_data),
.data_out(read_data));
end
`REGFILE_TYPE_LAT_DW:
begin
DW_ram_r_w_s_lat
#(.data_width(width),
.depth(depth))
DW_rf_lat
(.clk(clk),
.cs_n(write_enable_b),
.wr_n(write_enable_b),
.rd_addr(read_address),
.wr_addr(write_address),
.data_in(write_data),
.data_out(read_data));
end
endcase
end
2:
begin
wire [0:addr_width-1] read_address_1;
assign read_address_1
= read_address[0:addr_width-1];
wire [0:addr_width-1] read_address_2;
assign read_address_2
= read_address[addr_width:2*addr_width-1];
wire [0:width-1] read_data_1;
wire [0:width-1] read_data_2;
case(regfile_type)
`REGFILE_TYPE_FF_DW:
begin
DW_ram_r_w_s_dff
#(.data_width(width),
.depth(depth),
.rst_mode(1))
DW_rf_dff
(.clk(clk),
.rst_n(1'b1),
.cs_n(write_enable_b),
.wr_n(write_enable_b),
.rd1_addr(read_address_1),
.rd2_addr(read_address_2),
.wr_addr(write_address),
.data_in(write_data),
.data_rd1_out(read_data_1),
.data_rd2_out(read_data_2));
end
`REGFILE_TYPE_LAT_DW:
begin
DW_ram_r_w_s_lat
#(.data_width(width),
.depth(depth))
DW_rf_lat
(.clk(clk),
.cs_n(write_enable_b),
.wr_n(write_enable_b),
.rd1_addr(read_address_1),
.rd2_addr(read_address_2),
.wr_addr(write_address),
.data_in(write_data),
.data_rd1_out(read_data_1),
.data_rd2_out(read_data_2));
end
endcase
assign read_data = {read_data_1, read_data_2};
end
default:
begin
// synopsys translate_off
initial
begin
$display({"ERROR: Register file %m does not support ",
"DesignWare register file models with %d ",
"read ports."}, num_read_ports);
$stop;
end
// synopsys translate_on
end
endcase
end
endcase
//----------------------------------------------------------------------
// check parameter validity
//----------------------------------------------------------------------
// synopsys translate_off
if(depth < 2)
begin
initial
begin
$display({"ERROR: The register file module requires a depth of ",
"two or more entries."});
$stop;
end
end
// synopsys translate_on
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[400001], b[400001]; int main(void) { ios::sync_with_stdio(0); cin.tie(0); unsigned n; cin >> n; for (unsigned i = 1; i <= n / 2; ++i) cin >> b[i]; a[1] = 0; a[n] = b[1]; for (unsigned i = 2; i <= n / 2; ++i) { if (b[i] - a[i - 1] <= a[n - i + 2]) { a[i] = a[i - 1]; a[n - i + 1] = b[i] - a[i]; } else { a[n - i + 1] = a[n - i + 2]; a[i] = b[i] - a[n - i + 1]; } } for (unsigned i = 1; i <= n; ++i) cout << a[i] << ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPMET1_FUNCTIONAL_V
`define SKY130_FD_SC_MS__TAPMET1_FUNCTIONAL_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapmet1 ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPMET1_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int n, r; int x[105], y[105]; vector<pair<int, int> > pos, neg; bool cmp(pair<int, int> p1, pair<int, int> p2) { return p1.first + p1.second > p2.first + p2.second; } int main() { cin >> n >> r; for (int i = 0; i < n; i++) { scanf( %d%d , &x[i], &y[i]); if (y[i] >= 0) pos.push_back(pair<int, int>(x[i], y[i])); else neg.push_back(pair<int, int>(x[i], y[i])); } sort(pos.begin(), pos.end()); sort(neg.begin(), neg.end(), cmp); for (int i = 0; i < pos.size(); i++) { if (pos[i].first <= r) r += pos[i].second; else { printf( NO n ); return 0; } } for (int i = 0; i < neg.size(); i++) { if (neg[i].first <= r) r += neg[i].second; else { printf( NO n ); return 0; } if (r < 0) { printf( NO n ); return 0; } } printf( YES n ); return 0; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__PROBE_P_SYMBOL_V
`define SKY130_FD_SC_HVL__PROBE_P_SYMBOL_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__probe_p (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__PROBE_P_SYMBOL_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( -Ofast ) using namespace std; void rearrange(long long arr[], long long n) { long long temp[n]; long long small = 0, large = n - 1; long long flag = true; for (long long i = 0; i < n; i++) { if (flag) temp[i] = arr[large--]; else temp[i] = arr[small++]; flag = !flag; } for (long long i = 0; i < n; i++) arr[i] = temp[i]; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string a; cin >> a; long long k, i; cin >> k; long long snow = 0, candy = 0; for (i = 0; i < a.size(); i++) { if (a[i] == * ) snow++; else if (a[i] == ? ) candy++; } long long cha = k - (a.size() - snow - candy); if (cha > 0) { if (snow == 0) cout << Impossible ; else { string ans = ; for (i = a.size() - 1; i >= 0; i--) { if (a[i] == ? ) continue; if (a[i] == * ) { while (cha > 0) { ans = ans + a[i - 1]; cha--; } } else { ans = ans + a[i]; } } reverse(ans.begin(), ans.end()); cout << ans; } } else { if (a.size() - 2 * snow - 2 * candy > k) cout << Impossible ; else { vector<char> v(a.size(), 1 ); for (i = a.size() - 1; i >= 0; i--) { if (a[i] == ? || a[i] == * ) { i--; } else { v[i] = a[i]; k--; } } for (i = a.size() - 1; i >= 0; i--) { if (k > 0 && (a[i] == ? || a[i] == * )) { k--; v[i] = a[i - 1]; } } for (i = 0; i < a.size(); i++) { if (v[i] != 1 ) cout << v[i]; } } } } |
module automatic_events3();
reg [1:0] Source;
initial begin
Source[0] = 1'b0;
forever begin
#20 Source[0] = 1'b1;
#20 Source[0] = 1'b0;
end
end
initial begin
Source[1] = 1'b0;
#15;
forever begin
#10 Source[1] = 1'bx;
#10 Source[1] = 1'b1;
#10 Source[1] = 1'bx;
#10 Source[1] = 1'b0;
end
end
task automatic ReportPosEdge0;
begin
@(posedge Source[0]);
$display("Time %4t : Source[0] rise", $time);
end
endtask
task automatic ReportNegEdge0;
begin
@(negedge Source[0]);
$display("Time %4t : Source[0] fall", $time);
end
endtask
task automatic ReportAnyEdge0;
time t;
begin
@(Source[0]) t = $time;
#1 $display("Time %4t : Source[0] edge", t);
end
endtask
task automatic ReportPosEdge1;
begin
@(posedge Source[1]);
$display("Time %4t : Source[1] rise", $time);
end
endtask
task automatic ReportNegEdge1;
begin
@(negedge Source[1]);
$display("Time %4t : Source[1] fall", $time);
end
endtask
task automatic ReportAnyEdge1;
time t;
begin
@(Source[1]) t = $time;
#1 $display("Time %4t : Source[1] edge", t);
end
endtask
initial begin
#1;
fork
repeat(2) ReportPosEdge0;
repeat(2) ReportNegEdge0;
repeat(4) ReportAnyEdge0;
repeat(4) ReportPosEdge1;
repeat(4) ReportNegEdge1;
repeat(8) ReportAnyEdge1;
join
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; char x; int min, max; cin >> x >> min >> max; if (min > max) { swap(min, max); } for (int i = 0; i < n - 1; i += 1) { char y; int m, n; cin >> y >> m >> n; if (y == + ) { if (m > n) { swap(m, n); } if (m > min) { min = m; } if (n > max) { max = n; } } else { if (m > n) { swap(m, n); } if (m >= min && n >= max) { cout << YES << endl; } else { cout << NO << endl; } } } } |
#include <bits/stdc++.h> using namespace std; int pri[26] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, -1}; long long mo[5] = {223092870ll, 2756205443ll, 907383479ll, 42600829ll, 97ll}; int N, M, d, t, len, i, j, u; int b[100]; long long a[20000], c, ans; char ss[100]; vector<long long> f[17][5]; int num(int d, char c) { return c == ? ? d : (c <= 9 ? c - 0 : c - A + 10); } void prework() { int i, j, k, l; for (i = 2; i <= 16; i++) { for (j = 0, k = l = 1; k <= N; k *= i, l *= i + 1) ; for (j = 0; j < 5; j++) f[i][j].resize(l, -1); } } int calc(int d, int p) { int i, j, x = 0, y = 0; for (i = 0; i < t; i++) x = x * (d + 1) + b[i]; if (f[d][p][x] != -1) return x; f[d][p][x] = 1; for (i = 0; i < t; i++) if (b[i] == d) { for (j = 0; j < d; j++) b[i] = j, f[d][p][x] = (f[d][p][x] * f[d][p][calc(d, p)]) % mo[p]; b[i] = d; return x; } for (i = 0; i < t; i++) y = y * d + b[i]; if (y < N) f[d][p][x] = a[y] % mo[p]; return x; } int main() { scanf( %d , &N); for (i = 0; i < N; i++) scanf( %I64d , &a[i]); scanf( %d , &M); prework(); while (M--) { scanf( %d%s%I64d , &d, ss, &c); for (j = 1, t = 0; j <= N; t++, j *= d) ; len = strlen(ss); for (j = 0; j < t; j++) if (len - t + j >= 0) b[j] = num(d, ss[len - t + j]); else b[j] = 0; for (i = 0; i < 5; i++) { j = calc(d, i); ans = (f[d][i][j] + c) % mo[i]; for (j = 0; j < 25; j++) if (mo[i] % pri[j] == 0 && ans % pri[j] == 0) break; if (j < 25) break; } printf( %d n , pri[j]); } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1 << 23; bool a[maxn]; bool vis[maxn]; int n, m, x; void dfs(int x) { if (vis[x]) return; vis[x] = true; for (int i = 0; i <= n; i++) if (x & (1 << i)) dfs(x ^ (1 << i)); if (a[x]) dfs((1 << n) - 1 - x); } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) scanf( %d , &x), a[x] = true; int ans = 0; for (int i = 0; i < (1 << n); i++) if (!vis[i] && a[i]) dfs(i), ans++; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const long double pi = acos(-1); long long a[200002] = {}; long long b[200002] = {}; long long c[200002] = {}; string s = , ss = ; long long n, m, k, w; long long ans, ans1; long long mod = 1e9 + 7; int main() { cin.tie(0); cin.sync_with_stdio(0); int t = 1; while (t--) { cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; ; b[n - 1] = a[n - 1]; for (int i = n - 2; i >= 0; i--) b[i] = max(b[i + 1], a[i]); c[0] = a[0]; for (long long i = 1; i < n; i++) c[i] = min(a[i], c[i - 1]); ans = m; for (long long i = 0; i < n - 1; i++) { k = m / c[i]; k *= b[i + 1]; k += m % c[i]; ans = max(ans, k); } cout << ans; } return 0; } |
Require Import List.
Require Import ZArith.
Require Import Bool.
Require Import sort_lectures.
(* Inserts an element in to a sorted list *)
Function insert (x : Z) (lst : list Z) :=
match lst with
| nil => x :: nil
| hd :: tl => if (x <=? hd)%Z then x :: hd :: tl else hd :: insert x tl
end.
(* Insertion sort *)
Function insertionSort (lst : list Z) :=
match lst with
| nil => nil
| hd :: tl => insert hd (insertionSort tl)
end.
(* Insertion of an element keeps the list sorted *)
Lemma insert_keeps_list_sorted (x : Z) (lst : list Z):
urejen lst -> urejen (insert x lst).
Proof.
intros.
induction lst.
- auto.
- simpl.
case_eq (x <=? a)%Z.
+ intro.
simpl.
firstorder.
now apply Z.leb_le.
+ intro.
apply Z.leb_gt in H0.
simpl.
destruct lst; simpl.
* firstorder.
* firstorder.
case_eq (x <=? z)%Z.
intro.
firstorder.
now apply Zle_bool_imp_le.
intro.
firstorder.
replace (z :: insert x lst) with (insert x (z :: lst)).
assumption.
simpl.
case_eq (x <=? z)%Z.
intro.
absurd ((x <=? z)%Z = false); auto.
now rewrite <- not_false_iff_true in H4.
auto.
Qed.
(* InsertionSort always returns sorted list *)
Lemma returns_sorted_list :
forall l : list Z, urejen (insertionSort l).
Proof.
intro.
induction l.
- now simpl.
- simpl.
now apply insert_keeps_list_sorted.
Qed.
(* Number of occurrences of x increases if we insert another x into a list *)
Lemma occurrence_of_x (x : Z) (l : list Z) :
pojavi x (insert x l) = S (pojavi x l).
Proof.
induction l.
- simpl.
now rewrite Z.eqb_refl.
- simpl.
case_eq (x <=? a)%Z.
+ intro.
case_eq (x =? a)%Z.
* intro.
replace a with x.
simpl.
replace (x =? x)%Z with true.
auto.
now rewrite Z.eqb_refl.
auto.
now apply Z.eqb_eq.
* intro.
simpl.
replace (x =? a)%Z with false.
replace (x =? x)%Z with true.
auto.
now rewrite Z.eqb_refl.
+ intro.
case_eq (x =? a)%Z.
* intro.
replace a with x.
simpl.
replace (x =? x)%Z with true.
auto.
now rewrite Z.eqb_refl.
now apply Z.eqb_eq.
* intro.
simpl.
now replace (x =? a)%Z with false.
Qed.
(* Number of occurrences of x does not change if we insert a different element into a list *)
Lemma occurrence_of_x_2 (x y : Z) (l : list Z) :
((x =? y)%Z = false) -> pojavi x (insert y l) = pojavi x l.
Proof.
intro.
induction l.
- simpl.
now replace (x =? y)%Z with false.
- simpl.
case_eq (y <=? a)%Z.
+ intro.
case_eq (x =? a)%Z.
* intro.
replace a with x.
simpl.
replace (x =? y)%Z with false.
replace (x =? x)%Z with true.
auto.
now rewrite Z.eqb_refl.
now apply Z.eqb_eq.
* intro.
simpl.
replace (x =? y)%Z with false.
now replace (x =? a)%Z with false.
+ intro.
case_eq (x =? a)%Z.
* intro.
simpl.
replace (x =? a)%Z with true.
auto.
* intro.
simpl.
now replace (x =? a)%Z with false.
Qed.
(* InsertionSort always returns same list (permutation of a list) *)
Lemma returns_permuted_list :
forall l : list Z, permutiran l (insertionSort l).
Proof.
intro.
induction l.
- firstorder.
- intro.
simpl.
case_eq (x =? a)%Z.
+ intro.
replace a with x.
* rewrite (occurrence_of_x x (insertionSort l)).
now rewrite IHl.
* now apply Z.eqb_eq.
+ intro.
rewrite (occurrence_of_x_2 x a).
* now rewrite IHl.
* assumption.
Qed.
(* Theorem that states that our insertionSort works properly *)
Theorem insertionSort_works :
forall l : list Z, permutiran l (insertionSort l) /\ urejen (insertionSort l).
Proof.
split.
apply returns_permuted_list.
apply returns_sorted_list.
Qed.
|
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 100ps/100ps
module ArbitorTest;
wire [1:0] w_grant_2;
wire [3:0] w_grant_4;
reg [3:0] r_request;
reg r_error;
FixedPriorityArbitor arbitor_2(
.i_request(r_request[1:0]),
.o_grant (w_grant_2 ));
FixedPriorityArbitor #(.width(4)) arbitor_4(
.i_request(r_request ),
.o_grant (w_grant_4 ));
always @ (posedge r_error) begin
$display("unexpected grant %b for request %b", w_grant_4, r_request);
end
initial begin
//$dumpfile("Arbitor.vcd");
//$dumpvars(0, arbitor_4);
r_error <= 1'b0;
r_request <= 4'b0000;
#1
r_error <= w_grant_4 != 4'b0000;
#1
r_request <= 4'b0001;
#1
r_error <= w_grant_4 != 4'b0001;
#1
r_request <= 4'b0010;
#1
r_error <= w_grant_4 != 4'b0010;
#1
r_request <= 4'b0100;
#1
r_error <= w_grant_4 != 4'b0100;
#1
r_request <= 4'b1000;
#1
r_error <= w_grant_4 != 4'b1000;
#1
r_request <= 4'b0101;
#1
r_error <= w_grant_4 != 4'b0001;
#1
r_request <= 4'b1110;
#1
r_error <= w_grant_4 != 4'b0010;
#1
r_request <= 4'b1111;
#1
r_error <= w_grant_4 != 4'b0001;
#1
$finish;
end
endmodule // ParityTest
|
module xyz
#(parameter int FOO=1, BAR=2,
parameter logic [5:0] BLUP=3, ZOT=4,
parameter LDWRDS=5)
( input x1, x2,
input int i1, i2,
input logic [5:0] i3, i4,
input i5,
output y);
endmodule
module pdq;
input x; output y;
parameter int FOO=1;
endmodule
module abc;
xyz XYZ
#(/*AUTOINSTPARAM*/
// Parameters
.FOO (FOO),
.BAR (BAR),
.BLUP (BLUP[5:0]),
.ZOT (ZOT[5:0]),
.LDWRDS (LDWRDS))
(/*AUTOINST*/
// Outputs
.y (y),
// Inputs
.x1 (x1),
.x2 (x2),
.i1 (i1),
.i2 (i2),
.i3 (i3[5:0]),
.i4 (i4[5:0]),
.i5 (i5));
pdq PDQ
#(/*AUTOINSTPARAM*/
// Parameters
.FOO (FOO))
(/*AUTOINST*/
// Outputs
.y (y),
// Inputs
.x (x));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100010; const int INF = 0x7f7f7f7f; const double pi = 4.0 * atan(1.0); int cases; struct Segment_Tree { long long lazy[MAXN << 2]; long long data[MAXN << 2]; long long flag[MAXN << 2]; void pushup(int o) { data[o] = data[(o << 1)] + data[(o << 1) | 1]; if (flag[(o << 1)] != flag[(o << 1) | 1]) { flag[o] = 0; } else { flag[o] = flag[(o << 1)]; } } void setlazy(int o, int m, long long v) { lazy[o] += v; data[o] += m * v; } void pushdown(int o, int m) { if (lazy[o]) { setlazy((o << 1), m - (m >> 1), lazy[o]); setlazy((o << 1) | 1, m >> 1, lazy[o]); flag[(o << 1)] = flag[(o << 1) | 1] = flag[o]; lazy[o] = 0; } } void build_tree(int o, int l, int r) { if (l == r) { flag[o] = l; return; } int mid = (l + r) >> 1; build_tree((o << 1), l, mid); build_tree((o << 1) | 1, mid + 1, r); pushup(o); } void update(int o, int l, int r, int x, int y, long long v) { if (x <= l && r <= y && flag[o] != 0) { lazy[o] += abs(flag[o] - v); data[o] += (long long)(r - l + 1) * abs(flag[o] - v); flag[o] = v; return; } pushdown(o, r - l + 1); int mid = (l + r) >> 1; if (x <= mid) update((o << 1), l, mid, x, y, v); if (y > mid) update((o << 1) | 1, mid + 1, r, x, y, v); pushup(o); } long long query(int o, int l, int r, int x, int y) { if (x <= l && r <= y) { return data[o]; } pushdown(o, r - l + 1); int mid = (l + r) >> 1; if (y <= mid) return query((o << 1), l, mid, x, y); if (x > mid) return query((o << 1) | 1, mid + 1, r, x, y); return query((o << 1), l, mid, x, y) + query((o << 1) | 1, mid + 1, r, x, y); } } segtree; int main() { int n, m, op, x, y; long long z; scanf( %d%d , &n, &m); segtree.build_tree(1, 1, n); for (int i = 0; i < m; i++) { scanf( %d , &op); if (op == 1) { scanf( %d%d%lld , &x, &y, &z); segtree.update(1, 1, n, x, y, z); } else if (op == 2) { scanf( %d%d , &x, &y); printf( %lld n , segtree.query(1, 1, n, x, y)); } } } |
#include <bits/stdc++.h> using namespace std; const int N = 138; int n, Ans, x, y, z, GG[N][N][5][5]; int main() { memset(GG, -63, sizeof(GG)); cin >> n; int i, j, k, p; for (i = 1; i <= n; ++i) { cin >> x >> y >> z; GG[i][i][z][x] = GG[i][i][x][z] = y; } for (i = n; i >= 1; --i) for (j = i; j <= n; ++j) for (int x = 1; x <= 4; ++x) for (int y = 1; y <= 4; ++y) for (k = i; k <= j; ++k) { GG[i][j][x][y] = max(GG[i][j][x][y], max(GG[i][k][x][y], GG[k + 1][j][x][y])); for (p = 1; p <= 4; ++p) GG[i][j][x][y] = max(GG[i][j][x][y], max(GG[i][k][x][p] + GG[k + 1][j][p][y], GG[i][k][p][y] + GG[k + 1][j][x][p])); Ans = max(Ans, GG[i][j][x][y]); } cout << Ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int perm[55]; int main() { int n; long long m; scanf( %d%lld , &n, &m); m--; int l = 1; int r = n; for (long long i = n - 2; i >= 0; i--) { if (m & (1LL << i)) { perm[r] = n - 2 - i + 1; r--; } else { perm[l] = n - 2 - i + 1; l++; } } perm[l] = n; for (int i = 1; i <= n; i++) { printf( %d , perm[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 110; string s[maxn]; int cur[maxn], c[maxn]; int n, m, ans = 0; void dfs(int x) { if (x == n) { int flag = 1; for (int i = 1; i <= m; i++) if (cur[i] - c[i]) flag = 0; ans += flag; return; } for (char v = 0 ; v <= 1 ; v++) { int can = 1; for (int i = 1; i <= m; i++) { cur[i] += (v == s[i][x]); if (cur[i] > c[i]) can = 0; } if (can) dfs(x + 1); for (int i = 1; i <= m; i++) cur[i] -= (v == s[i][x]); } } int main() { cin >> n >> m; for (int i = 1; i <= m; i++) cin >> s[i] >> c[i]; memset(cur, 0, sizeof(cur)); dfs(0); cout << ans << endl; return 0; } |
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
WindowGenerator
:Function
Generate window.
The lowest "color_width" bits of "out_data" is the top left corner pixel of the window!
In pipeline mode, it will give the first output after window_width / 2 + 1 cycles while the input enable.
In req-ack mode, before the first window can be output, it will give a input ack for every req, then you can give the next input data.
:Module
Main module
:Version
1.0
:Modified
2015-05-19
Copyright (C) 2015 Tianyu Dai (dtysky) <>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module WindowGenerator(
clk,
rst_n,
in_enable,
in_data,
out_ready,
out_data,
input_ack
);
/*
::description
This module's working mode.
::range
0 for Pipline, 1 for Req-ack
*/
parameter[0 : 0] work_mode = 0;
/*
::description
The width(and height) of window.
::range
2 - 15
*/
parameter[3 : 0] window_width = 3;
/*
::description
Color's bit wide.
::range
1 - 12
*/
parameter[3: 0] color_width = 8;
parameter[2 : 0] window_width_half = window_width >> 1;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [color_width * window_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output[color_width * window_width * window_width - 1 : 0] out_data;
/*
::description
Input ack, only used for req-ack mode, this port will give a ack while the input_data received.
*/
output input_ack;
reg[color_width * window_width - 1 : 0] reg_out_data[0 : window_width - 1];
reg[3 : 0] con_init;
genvar y;
genvar x;
generate
if(work_mode == 0) begin
assign input_ack = 0;
reg reg_out_ready;
assign out_ready = reg_out_ready;
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable) begin
con_init <= 0;
reg_out_ready <= 0;
end else if(con_init == window_width_half) begin
con_init <= con_init;
reg_out_ready <= 1;
end else begin
con_init <= con_init + 1;
reg_out_ready <= 0;
end
end
for (y = 0; y < window_width; y = y + 1) begin
for (x = 0; x < window_width; x = x + 1) begin
if (x == 0) begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
reg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= 0;
else
reg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= in_data[(y + 1) * color_width - 1 : y * color_width];
end
end else begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
reg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= 0;
else
reg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= reg_out_data[y][x * color_width - 1 : (x - 1)* color_width];
end
end
end
assign out_data[(y + 1) * color_width * window_width - 1 : y * color_width * window_width] =
out_ready ? reg_out_data[y] : 0;
end
end else begin
reg in_enable_last;
always @(posedge clk)
in_enable_last <= in_enable;
reg reg_input_ack;
assign input_ack = reg_input_ack;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
con_init <= 0;
else if(con_init == window_width_half + 1)
con_init <= con_init;
else if(~in_enable_last & in_enable)
con_init <= con_init + 1;
else
con_init <= con_init;
end
assign out_ready = con_init == window_width_half + 1 ? 1 : 0;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_input_ack <= 0;
else if(~in_enable_last & in_enable)
reg_input_ack <= 1;
else if(in_enable_last & ~in_enable)
reg_input_ack <= 0;
end
for (y = 0; y < window_width; y = y + 1) begin
for (x = 0; x < window_width; x = x + 1) begin
if (x == 0) begin
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= 0;
else if(~in_enable_last & in_enable)
reg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= in_data[(y + 1) * color_width - 1 : y * color_width];
else
reg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= reg_out_data[y][(x + 1) * color_width - 1 : x * color_width];
end
end else begin
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= 0;
else if(~in_enable_last & in_enable)
reg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= reg_out_data[y][x * color_width - 1 : (x - 1)* color_width];
else
reg_out_data[y][(x + 1) * color_width - 1 : x * color_width] <= reg_out_data[y][(x + 1) * color_width - 1 : x * color_width];
end
end
end
assign out_data[(y + 1) * color_width * window_width - 1 : y * color_width * window_width] =
out_ready ? reg_out_data[y] : 0;
end
end
endgenerate
endmodule |
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:102400000,102400000 ) template <class T> void chkmax(T &a, T b) { if (a < b) a = b; } template <class T> void chkmin(T &a, T b) { if (a > b) a = b; } const int inf = 0x3f3f3f3f; const long long linf = 2e18 + 100; const double dinf = 2e18 + 100; const double eps = 1e-7; const double pi = 3.14159265358979323846264338327950288L; bool scanld(double &first) { double xx; int f = scanf( %lf , &xx); first = xx; return f > 0; } void printld(const double &first) { printf( %.10lf , fabs(first) < eps ? 0 : (double)first); } inline char nc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } template <class T> void read(T &first) { char c = nc(), b = 1; for (; !((c >= 0 && c <= 9 ) || c == EOF); c = nc()) if (c == - ) b = -b; for (first = 0; c >= 0 && c <= 9 ; first = first * 10 + c - 0 , c = nc()) ; first *= b; } inline void read(char *s) { char c = nc(); int len = 0; for (; c == || c == t || c == n ; c = nc()) ; for (; !(c == || c == t || c == n || c == EOF); s[len++] = c, c = nc()) ; s[len] = 0; } int n, P[100005], len; vector<int> v[100005]; int ds[100005]; void dfs(int k, int pa) { P[k] = pa; for (auto first : v[k]) { if (first == pa) continue; dfs(first, k); } return; } int mx[100005][3], id[100005][3]; void dfs_2(int k, int pa) { mx[k][0] = 1, mx[k][1] = 0, mx[k][2] = 0; id[k][0] = k, id[k][1] = 0, id[k][2] = 0; for (auto first : v[k]) { if (first == pa) continue; dfs_2(first, k); int d = mx[first][0] + 1; if (d > mx[k][2]) mx[k][2] = d, id[k][2] = first; if (mx[k][2] > mx[k][1]) swap(mx[k][1], mx[k][2]), swap(id[k][1], id[k][2]); if (mx[k][1] > mx[k][0]) swap(mx[k][1], mx[k][0]), swap(id[k][1], id[k][0]); } return; } bool ok[100005]; int pmx[100005]; void dfs_3(int k, int pa) { if (!pa) pmx[k] = 0; else { int d = id[pa][0] == k ? mx[pa][1] : mx[pa][0]; chkmax(d, pmx[pa]); pmx[k] = d + 1; } if (mx[k][2] > len || mx[k][1] > len && pmx[k] > len) ok[k] = 1; else ok[k] = 0; for (auto first : v[k]) { if (first == pa) continue; dfs_3(first, k); } return; } int G, st[100005], fs[100005]; int p[100005][17], dp[100005]; void dfs_4(int k, int pa) { dp[k] = dp[pa] + 1; p[k][0] = pa; st[k] = ++G; for (int i = 1; i <= 16; i++) p[k][i] = p[p[k][i - 1]][i - 1]; ds[k] = k; for (auto first : v[k]) { if (first == pa) continue; dfs_4(first, k); if (dp[ds[first]] > dp[ds[k]]) ds[k] = ds[first]; } fs[k] = ++G; return; } int kth_father(int first, int k) { for (int i = 16; i >= 0; i--) if (k & (1 << i)) first = p[first][i]; return first; } bool is_anc(int p, int first) { return st[p] <= st[first] && fs[first] <= fs[p]; } bool chk[100005]; int head, tail; int main() { int T; for (read(T); T--;) { read(n); read(head), read(tail); int first, second; for (int i = 1; i < n; i++) { read(first), read(second); v[first].push_back(second); v[second].push_back(first); } dfs(head, 0); len = 0; int t = tail; while (t != head) { len++; t = P[t]; } dfs_2(head, 0); dfs_3(head, 0); int R = -1; for (int i = 1; i <= n; i++) if (ok[i]) R = i; if (R < 0) puts( NO ); else { dfs_4(R, 0); int dph = dp[head], dpt = dp[tail]; bool yes = is_anc(head, tail) || is_anc(tail, head); if (!yes) { int ch = head, ct = tail; int lca = R; for (int i = 1; i <= n; i++) if (is_anc(i, ch) && is_anc(i, ct) && st[i] > st[lca]) lca = i; int lh = dp[ch] - dp[lca], lt = dp[ct] - dp[lca]; bool fh = 0; while (!yes) { if (fh && chk[ch]) break; if (fh) chk[ch] = 1; if (fh) { ch = ds[ch]; if (dp[ch] - dp[lca] >= len) yes = 1; else { lh = dp[ch] - dp[lca]; ct = kth_father(ct, lt - (len - lh)); lt = dp[ct] - dp[lca]; } } else { ct = ds[ct]; if (dp[ct] - dp[lca] >= len) yes = 1; else { lt = dp[ct] - dp[lca]; ch = kth_father(ch, lh - (len - lt)); lh = dp[ch] - dp[lca]; } } fh ^= 1; } } puts(yes ? YES : NO ); } for (int i = 1; i <= n; i++) v[i].clear(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 100; const int mod = 1e9 + 7; int main() { ios::sync_with_stdio(0); int t; cin >> t; while (t--) { int n, x, y; cin >> n >> x >> y; cout << max(min(n, x + y - n + 1), 1) << << min(x + y - 1, n) << endl; } } |
#include <bits/stdc++.h> using namespace std; long long a[100005], b; int n, k; pair<long long, int> pvec[100005]; int solve() { for (int i = 0; i < n - 1; i++) pvec[i] = make_pair(a[i], i + 1); sort(pvec, pvec + n); reverse(pvec, pvec + n); long long total = 0; int ans = n; for (int i = 0; i < k; i++) { total += pvec[i].first; ans = min(ans, pvec[i].second); } if (total > b) { if (k > 1) b = b - (total - pvec[k - 1].first); for (int j = 0; j < n; j++) { if (a[j] > b) return j + 1; } } else return n; return 0; } int main() { cin >> n >> k; cin >> b; for (int i = 0; i < n; i++) cin >> a[i]; cout << solve() << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTN_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DFRTN_FUNCTIONAL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_lp__udp_dff_pr.v"
`celldefine
module sky130_fd_sc_lp__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intclk, CLK_N );
sky130_fd_sc_lp__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , D, intclk, RESET);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTN_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int maxn = 132222; const long long mod = 1000000007; char s[maxn]; int main() { int n; cin >> n; cin >> s + 1; int len = strlen(s + 1); int l = -1, r = -1; for (int i = (1); i < (len + 1); i++) { if (s[i] == L && l == -1) l = i; if (s[i] == R && r == -1) r = i; } if (l != -1 && r == -1) { int x; for (int i = len; i >= 1; i--) { if (s[i] == L ) { x = i; break; } } cout << x << << l - 1 << endl; return 0; } if (l == -1 && r != -1) { int x; for (int i = len; i >= 1; i--) { if (s[i] == R ) { x = i; break; } } cout << r << << x + 1 << endl; return 0; } if (l != -1 && r != -1) { cout << r << << l - 1 << endl; return 0; } } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1000 * 1000 * 1000 + 7; const int INF = 2000 * 1000 * 1000; const double EPS = 1e-9; const double pi = acos(-1.0); template <typename T> inline T sqr(T n) { return (n * n); } long long gcd(int a, int b) { while (a && b) { a %= b; swap(a, b); } return a + b; } struct Point { long long x, y; Point() {} Point(int x, int y) : x(x), y(y) {} Point(const Point& a) { *this = a; } Point operator-(const Point& a) const { return Point(x - a.x, y - a.y); } inline long long dist() { return sqr(x) + sqr(y); } bool operator<(const Point& p1) const { return (x < p1.x || (x == p1.x && y < p1.y)); } }; struct Line { long long a, b, c; Line() {} inline void normalize() { if (a < 0 || (a == 0 && b < 0)) { a *= -1; b *= -1; c *= -1; } long long g = gcd(gcd(abs(a), abs(b)), abs(c)); if (g > 1) { a /= g; b /= g; c /= g; } } Line(int aa, int bb, int cc) { a = aa, b = bb, c = cc; normalize(); } Line(const Point& p1, const Point& p2) { a = p2.y - p1.y; b = p1.x - p2.x; c = p1.y * p2.x - p1.x * p2.y; normalize(); } }; const int maxn = 300010; vector<pair<Point, int> > v[maxn]; vector<int> vec[maxn]; map<long long, int> position; vector<Point> tmp[maxn]; Point center[2000]; long long rad[2000]; long long get_hash(const Line& l) { long long a = l.a + 50000; long long b = l.b + 50000; long long c = l.c + 2000000000; long long ret = c * 2000000000LL; ret += a * 100000; ret += b; return ret; } void prepare(int pos) { vector<pair<Point, int> >& cur = v[pos]; sort((cur).begin(), (cur).end()); vec[pos].resize(cur.size()); int cnt = 0; for (size_t i = 0; i < cur.size(); i++) { if (cur[i].second == 0) cnt++; else cnt--; vec[pos][i] = cnt; } } long long get_ans(const Point& p1, const Point& p2) { Line cur(p1, p2); Point mid((p1.x + p2.x) / 2, (p1.y + p2.y) / 2); Point norm(cur.a, cur.b); norm.x += mid.x; norm.y += mid.y; cur = Line(mid, norm); long long h = get_hash(cur); if (!position.count(h)) return 0; int pos = position[h]; int q = upper_bound((v[pos]).begin(), (v[pos]).end(), make_pair(mid, 1)) - v[pos].begin() - 1; if (q != -1) return vec[pos][q]; return 0; } int main() { int n, m; scanf( %d%d , &n, &m); Point p1, p2; int sz = 0; for (int i = 0; i < n; i++) { scanf( %I64d%I64d%I64d%I64d , &p1.x, &p1.y, &p2.x, &p2.y); p1.x *= 2, p1.y *= 2; p2.x *= 2, p2.y *= 2; Line cur(p1, p2); long long h = get_hash(cur); int pos = 0; if (position.count(h)) pos = position[h]; else { pos = sz++; position[h] = pos; } v[pos].push_back(make_pair(p1, (p1 < p2) ? 0 : 2)); v[pos].push_back(make_pair(p2, (p1 < p2) ? 2 : 0)); } for (int i = 0; i < sz; i++) prepare(i); long long ans = 0; for (int i = 0; i < m; i++) { scanf( %I64d%I64d%I64d , ¢er[i].x, ¢er[i].y, &rad[i]); center[i].x *= 2; center[i].y *= 2; rad[i] *= 2; for (size_t j = 0; j < tmp[rad[i]].size(); j++) { if ((center[i] - tmp[rad[i]][j]).dist() > 4 * sqr(rad[i])) ans += get_ans(center[i], tmp[rad[i]][j]); } tmp[rad[i]].push_back(center[i]); } printf( %I64d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; string s; cin >> s; vector<string> all; for (long long i = 0; i <= 9; i++) { all.push_back(s); for (char &c : s) if (c == 9 ) c = 0 ; else c++; } string ans = s; for (string &x : all) { for (long long i = 0; i < n; i++) { string y = x; rotate(y.begin(), y.begin() + y.size() - i, y.end()); ans = min(y, ans); } } cout << ans << n ; } void solve(bool testcase) { long long t; cin >> t; while (t--) solve(); } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int N, M; long long f[155][155][155][2][2], g[155][155][2][2]; void doit() { scanf( %d %d , &N, &M); int ans = 0; for (int i = 1; i <= N; i++) { for (int j = 1; j <= M; j++) for (int k = j; k <= M; k++) { f[i][j][k][0][0] = i == 1 ? 1 : (g[k][k][0][0] - g[j - 1][k][0][0] - g[k][j - 1][0][0] + g[j - 1][j - 1][0][0]) % 1000000007; f[i][j][k][0][1] = ((g[k][M][0][0] - g[j - 1][M][0][0] - g[k][k + 1 - 1][0][0] + g[j - 1][k + 1 - 1][0][0]) % 1000000007 + (g[k][M][0][1] - g[j - 1][M][0][1] - g[k][k - 1][0][1] + g[j - 1][k - 1][0][1]) % 1000000007) % 1000000007; f[i][j][k][1][0] = ((g[j - 1][k][0][0] - g[1 - 1][k][0][0] - g[j - 1][j - 1][0][0] + g[1 - 1][j - 1][0][0]) % 1000000007 + (g[j][k][1][0] - g[1 - 1][k][1][0] - g[j][j - 1][1][0] + g[1 - 1][j - 1][1][0]) % 1000000007) % 1000000007; f[i][j][k][1][1] = ((g[j - 1][M][0][0] - g[1 - 1][M][0][0] - g[j - 1][k + 1 - 1][0][0] + g[1 - 1][k + 1 - 1][0][0]) % 1000000007 + (g[j - 1][M][0][1] - g[1 - 1][M][0][1] - g[j - 1][k - 1][0][1] + g[1 - 1][k - 1][0][1]) % 1000000007 + (g[j][M][1][0] - g[1 - 1][M][1][0] - g[j][k + 1 - 1][1][0] + g[1 - 1][k + 1 - 1][1][0]) % 1000000007 + (g[j][M][1][1] - g[1 - 1][M][1][1] - g[j][k - 1][1][1] + g[1 - 1][k - 1][1][1]) % 1000000007) % 1000000007; } for (int j = 1; j <= M; j++) for (int k = 1; k <= M; k++) for (int x = 0; x < 4; x++) g[j][k][x / 2][x & 1] = (f[i][j][k][x / 2][x & 1] + g[j - 1][k][x / 2][x & 1] + g[j][k - 1][x / 2][x & 1] - g[j - 1][k - 1][x / 2][x & 1]) % 1000000007; for (int x = 0; x < 4; x++) (ans += g[M][M][x / 2][x & 1] * (N - i + 1) % 1000000007) %= 1000000007; } cout << (ans + 1000000007) % 1000000007 << endl; } int main() { doit(); return 0; } |
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-31 16:28:45
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`include "global.v"
module Simple_KOA_STAGE_2
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
//assign i = Stop_I;
if (SW <= 7) begin : GENSTOP
mult2 #(.SW(SW))
inst_mult (
.DatA(Data_A_i),
.DatB(Data_B_i),
.DatO(sgf_result_o)
);
end else begin : RECURSIVE
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
wire [SW-1:0] Q_left;
wire [SW-1:0] Q_right;
wire [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
mult2 #(.SW(SW/2)) left(
.clk(clk),
.DatA(Data_A_i[SW-1:SW-SW/2]),
.DatB(Data_B_i[SW-1:SW-SW/2]),
.DatO(Q_left)
);
mult2 #(.SW(SW/2)) right(
.clk(clk),
.DatA(Data_A_i[SW-SW/2-1:0]),
.DatB(Data_B_i[SW-SW/2-1:0]),
.DatO(Q_right)
);
mult2 #(.SW((SW/2)+1)) middle (
.clk(clk),
.DatA(result_A_adder),
.DatB(result_B_adder),
.DatO(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
mult2 #(.SW(SW/2)) left(
.clk(clk),
.DatA(Data_A_i[SW-1:SW-SW/2]),
.DatB(Data_B_i[SW-1:SW-SW/2]),
.DatO(Q_left)
);
mult2 #(.SW((SW/2)+1)) right(
.clk(clk),
.DatA(Data_A_i[SW-SW/2-1:0]),
.DatB(Data_B_i[SW-SW/2-1:0]),
.DatO(Q_right)
);
mult2 #(.SW(SW/2+2)) middle (
.clk(clk),
.DatA(result_A_adder),
.DatB(result_B_adder),
.DatO(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
end
endgenerate
endmodule
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream 4 port demultiplexer
*/
module axis_demux_4 #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI outputs
*/
output wire [DATA_WIDTH-1:0] output_0_axis_tdata,
output wire output_0_axis_tvalid,
input wire output_0_axis_tready,
output wire output_0_axis_tlast,
output wire output_0_axis_tuser,
output wire [DATA_WIDTH-1:0] output_1_axis_tdata,
output wire output_1_axis_tvalid,
input wire output_1_axis_tready,
output wire output_1_axis_tlast,
output wire output_1_axis_tuser,
output wire [DATA_WIDTH-1:0] output_2_axis_tdata,
output wire output_2_axis_tvalid,
input wire output_2_axis_tready,
output wire output_2_axis_tlast,
output wire output_2_axis_tuser,
output wire [DATA_WIDTH-1:0] output_3_axis_tdata,
output wire output_3_axis_tvalid,
input wire output_3_axis_tready,
output wire output_3_axis_tlast,
output wire output_3_axis_tuser,
/*
* Control
*/
input wire enable,
input wire [1:0] select
);
reg [1:0] select_reg = 0, select_next;
reg frame_reg = 0, frame_next;
reg input_axis_tready_reg = 0, input_axis_tready_next;
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
assign input_axis_tready = input_axis_tready_reg;
// mux for output control signals
reg current_output_tready;
reg current_output_tvalid;
always @* begin
case (select_reg)
2'd0: begin
current_output_tvalid = output_0_axis_tvalid;
current_output_tready = output_0_axis_tready;
end
2'd1: begin
current_output_tvalid = output_1_axis_tvalid;
current_output_tready = output_1_axis_tready;
end
2'd2: begin
current_output_tvalid = output_2_axis_tvalid;
current_output_tready = output_2_axis_tready;
end
2'd3: begin
current_output_tvalid = output_3_axis_tvalid;
current_output_tready = output_3_axis_tready;
end
endcase
end
always @* begin
select_next = select_reg;
frame_next = frame_reg;
input_axis_tready_next = 0;
if (frame_reg) begin
if (input_axis_tvalid & input_axis_tready) begin
// end of frame detection
frame_next = ~input_axis_tlast;
end
end else if (enable & input_axis_tvalid & ~current_output_tvalid) begin
// start of frame, grab select value
frame_next = 1;
select_next = select;
end
input_axis_tready_next = output_axis_tready_int_early & frame_next;
output_axis_tdata_int = input_axis_tdata;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 0;
input_axis_tready_reg <= 0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
input_axis_tready_reg <= input_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
reg output_0_axis_tvalid_reg = 0;
reg output_1_axis_tvalid_reg = 0;
reg output_2_axis_tvalid_reg = 0;
reg output_3_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign output_0_axis_tdata = output_axis_tdata_reg;
assign output_0_axis_tvalid = output_0_axis_tvalid_reg;
assign output_0_axis_tlast = output_axis_tlast_reg;
assign output_0_axis_tuser = output_axis_tuser_reg;
assign output_1_axis_tdata = output_axis_tdata_reg;
assign output_1_axis_tvalid = output_1_axis_tvalid_reg;
assign output_1_axis_tlast = output_axis_tlast_reg;
assign output_1_axis_tuser = output_axis_tuser_reg;
assign output_2_axis_tdata = output_axis_tdata_reg;
assign output_2_axis_tvalid = output_2_axis_tvalid_reg;
assign output_2_axis_tlast = output_axis_tlast_reg;
assign output_2_axis_tuser = output_axis_tuser_reg;
assign output_3_axis_tdata = output_axis_tdata_reg;
assign output_3_axis_tvalid = output_3_axis_tvalid_reg;
assign output_3_axis_tlast = output_axis_tlast_reg;
assign output_3_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = current_output_tready | (~temp_axis_tvalid_reg & ~current_output_tvalid) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_0_axis_tvalid_reg <= 0;
output_1_axis_tvalid_reg <= 0;
output_2_axis_tvalid_reg <= 0;
output_3_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (current_output_tready | ~current_output_tvalid) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
case (select_reg)
2'd0: output_0_axis_tvalid_reg <= output_axis_tvalid_int;
2'd1: output_1_axis_tvalid_reg <= output_axis_tvalid_int;
2'd2: output_2_axis_tvalid_reg <= output_axis_tvalid_int;
2'd3: output_3_axis_tvalid_reg <= output_axis_tvalid_int;
endcase
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (current_output_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
case (select_reg)
2'd0: output_0_axis_tvalid_reg <= temp_axis_tvalid_reg;
2'd1: output_1_axis_tvalid_reg <= temp_axis_tvalid_reg;
2'd2: output_2_axis_tvalid_reg <= temp_axis_tvalid_reg;
2'd3: output_3_axis_tvalid_reg <= temp_axis_tvalid_reg;
endcase
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 85; long long fibo[N + 5]; long long dp[N + 5][3][3]; long long arr[N + 5]; void pre() { fibo[0] = 1, fibo[1] = 2; for (int i = 2; i <= N; i++) { fibo[i] = fibo[i - 1] + fibo[i - 2]; } } long long solve(int idx, int cur1, int cur2) { if (idx == -1) { if (cur1 + cur2 != 0) return 0; return 1; } long long &res = dp[idx][cur1][cur2]; if (res != -1) return res; res = 0; if (cur1 + arr[idx] > 2) return 0; if (cur1 + arr[idx] <= 1) res += solve(idx - 1, cur2, 0); if (cur1 + arr[idx] == 1) res += solve(idx - 1, cur2 + 1, 1); if (cur1 + arr[idx] == 2) res += solve(idx - 1, cur2 + 1, 1); return res; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); pre(); int ntc; cin >> ntc; while (ntc--) { long long x; cin >> x; for (int i = N; i >= 0; i--) { arr[i] = 0; if (x < fibo[i]) continue; x -= fibo[i]; arr[i] = 1; } memset(dp, -1, sizeof dp); cout << solve(N, 0, 0) << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int N, M; scanf( %d %d , &N, &M); int beat[N + 5], i; memset(beat, 0, sizeof(beat)); set<int> S; for (int i = 1; i <= N; i++) S.insert(i); int L, R, W; set<int>::iterator it; while (M--) { scanf( %d %d %d , &L, &R, &W); set<int>::iterator lt = S.lower_bound(L); set<int>::iterator rt = S.upper_bound(R); for (it = lt; it != rt; it++) { int val = *it; if (val != W) beat[val] = W; } S.erase(lt, rt); S.insert(W); } for (int i = 1; i <= N - 1; i++) printf( %d , beat[i]); printf( %d n , beat[N]); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& a) { in >> a.first >> a.second; return in; } template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2> a) { out << a.first << << a.second; return out; } template <typename T, typename T1> T amax(T& a, T1 b) { if (b > a) a = b; return a; } template <typename T, typename T1> T amin(T& a, T1 b) { if (b < a) a = b; return a; } template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } void solve() { long long n, k; cin >> n >> k; long long a[n], cnt = 0, l = 0, r = -1, l3, r3; for (long long i = 0; i < n; ++i) { cin >> a[i]; if (a[i] == 0) cnt++; if (cnt <= k) r++; } long long ans = r - l + 1; l3 = l; r3 = r; for (long long i = r + 1; i < n; ++i) { if (r == n - 1) break; if (a[i] == 0) { if (ans < r - l + 1) { ans = r - l + 1; l3 = l; r3 = r; } long long l1 = l; for (long long j = l1; j < n; ++j) { l++; if (a[j] == 0) break; } r++; } else r++; } if (ans < r - l + 1) { ans = r - l + 1; l3 = l; r3 = r; } cout << ans << n ; for (long long i = 0; i < n; ++i) { if (i >= l3 && i <= r3) cout << 1 << ; else cout << a[i] << ; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int arr[100005]; int brr[100005]; char s[1234][1234]; int vis[1234][1234]; int has[1234][1234]; int f[1234567]; int n, m, c, g; void dfs(int x, int y) { if (x < 0 || y < 0 || x == n || y == m || vis[x][y] || s[x][y] == * ) return; if (s[x][y] == . ) { vis[x][y] = 1; has[x][y] = g; f[g]++; dfs(x, y + 1); dfs(x, y - 1); dfs(x - 1, y); dfs(x + 1, y); } } int main() { cin >> n >> m; int i, j; for (i = 0; i < n; i++) { for (j = 0; j < m; ++j) { cin >> s[i][j]; } } for (i = 0; i < n; ++i) { for (j = 0; j < m; ++j) { if (s[i][j] == . && vis[i][j] == 0) { g++; dfs(i, j); } } } for (i = 0; i < n; ++i) { for (j = 0; j < m; ++j) { c = 1; set<int> se; if (s[i][j] == * ) { if (j > 0) se.insert(has[i][j - 1]); if (i > 0) se.insert(has[i - 1][j]); if (j + 1 < m) se.insert(has[i][j + 1]); if (i + 1 < n) se.insert(has[i + 1][j]); for (set<int>::iterator it = se.begin(); it != se.end(); ++it) { c = c + f[*it]; } cout << c % 10; } else cout << . ; } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string c; cin >> c; for (int i = 1; i <= n; i++) if (n % i == 0) reverse(c.begin(), c.begin() + i); cout << c; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_TB_V
`define SKY130_FD_SC_HD__DLYMETAL6S2S_TB_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlymetal6s2s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__dlymetal6s2s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_TB_V
|
#include <bits/stdc++.h> int main() { int h, w, bh, bw, th, tw; long long ar, ba; bh = bw = ba = 0; scanf( %d %d , &h, &w); int tmp; for (int i = 30; i >= 0; i--) { tmp = (1 << i); if (tmp <= w) { long long x = (long long)tmp * 8; long long y = (long long)tmp * 125; if (x % 10 != 0) x = x / 10 + 1; else x = x / 10; y /= 100; if (y <= h) { th = y; tw = tmp; ar = (long long)th * (long long)tw; if (ar > ba || ar == ba && th > bh) { bh = th; bw = tw; ba = (long long)bh * (long long)bw; } } else if (x <= h) { th = h; tw = tmp; ar = (long long)th * (long long)tw; if (ar > ba || ar == ba && th > bh) { bh = th; bw = tw; ba = (long long)bh * (long long)bw; } } } } for (int i = 30; i >= 0; i--) { tmp = (1 << i); if (tmp <= h) { int x = (int)((double)tmp / 1.25); int y = (int)((double)tmp / 0.8); if ((double)y * 0.8 < (double)tmp) y++; if ((double)x * 1.25 > (double)tmp) x--; if (y <= w) { th = tmp; tw = y; ar = (long long)th * (long long)tw; if (ar > ba || ar == ba && th > bh) { bh = th; bw = tw; ba = (long long)bh * (long long)bw; } } else if (x < w) { th = tmp; tw = w; ar = (long long)th * (long long)tw; if (ar > ba || ar == ba && th > bh) { bh = th; bw = tw; ba = (long long)bh * (long long)bw; } } } } if (bw > bh && bw <= h) std::swap(bw, bh); printf( %d %d n , bh, bw); return 0; } |
#include <bits/stdc++.h> using namespace std; int const mod = 1e9 + 7; inline void SAFE_ADD(int& a, int b) { a += b; if (a >= mod) a -= mod; } struct Matr { vector<vector<int> > _data; Matr(int sz) : _data(sz, vector<int>(sz, 0)) {} void ones() { for (int i = 0; i < _data.size(); ++i) _data[i][i] = 1; } }; Matr operator*(Matr const& a, Matr const& b) { int n = a._data.size(); Matr ans(n); for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) for (int k = 0; k < n; ++k) { SAFE_ADD(ans._data[i][k], a._data[i][j] * 1LL * b._data[j][k] % mod); } return ans; } inline int getnum(char c) { if (c >= a && c <= z ) return c - a ; else return 26 + c - A ; } Matr pow(Matr const& a, long long b) { Matr ans(a._data.size()); ans.ones(); Matr tmp(a); while (b) { if (b & 1) ans = ans * tmp; tmp = tmp * tmp; b >>= 1; } return ans; } int main() { ios_base::sync_with_stdio(false); long long n; int m, k; cin >> n >> m >> k; if (n == 1) { cout << m << n ; return 0; }; Matr a(m); for (int i = 0; i < m; ++i) for (int j = 0; j < m; ++j) a._data[i][j] = 1; for (int i = 0; i < k; ++i) { string tmp; cin >> tmp; a._data[getnum(tmp[0])][getnum(tmp[1])] = 0; } a = pow(a, n - 1); int ans = 0; for (int i = 0; i < m; ++i) for (int j = 0; j < m; ++j) SAFE_ADD(ans, a._data[i][j]); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, dem = 0; cin >> n; dem = n / 2520; cout << dem; } |
#include <bits/stdc++.h> const double PI = acos(-1); using namespace std; const int mod = 1e9 + 7; const long long oo = 0x3f3f3f3f; const int nn = 1e2 + 15; vector<pair<int, int>> gr[nn], shifts; map<char, int> vis; long long get_distance(pair<int, int> a, pair<int, int> b) { return ((a.first - b.first) * 1LL * (a.first - b.first) + (a.second - b.second) * (a.second - b.second)); } int main() { ios_base::sync_with_stdio(false); cout.tie(NULL); cin.tie(NULL); ; int n, m, x; cin >> n >> m >> x; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { char c; cin >> c; if (c == S ) shifts.push_back(make_pair(i, j)); else gr[c - a ].push_back(make_pair(i, j)); } } int len; cin >> len; string s; cin >> s; int res = 0; for (int i = 0; i < len; i++) { if (isupper(s[i])) { s[i] = tolower(s[i]); if (!((int)((gr[s[i] - a ]).size())) || !((int)((shifts).size()))) return cout << -1, 0; else { if (vis[s[i]]) { if (vis[s[i]] > x * x) res++; continue; } int mn = oo; for (int j = 0; j < ((int)((shifts).size())); j++) { for (int k = 0; k < ((int)((gr[s[i] - a ]).size())); k++) { int dist = get_distance(shifts[j], gr[s[i] - a ][k]); mn = min(mn, dist); } } if (mn > x * x) res++; vis[s[i]] = mn; } } else { if (!((int)((gr[s[i] - a ]).size()))) return cout << -1, 0; } } cout << res; } |
#include <bits/stdc++.h> using namespace std; inline int toInt(string s) { int v; istringstream sin(s); sin >> v; return v; } template <class T> inline string toString(T x) { ostringstream sout; sout << x; return sout.str(); } inline int readInt() { int x; scanf( %d , &x); return x; } int a[55]; int main() { int n; scanf( %d , &n); for (int i = 0; i < (int)n; ++i) scanf( %d , &a[i]); sort(a, a + n); if (a[0] == a[n / 2]) printf( Bob n ); else printf( Alice n ); return 0; } |
#include <bits/stdc++.h> #define all(x) (x).begin(),(x).end() #define sz(x) int(x.size()) using namespace std; using ll = long long; using pii = pair<int, int>; template<typename... T> void rd(T&... args) {((cin>>args), ...);} template<typename... T> void wr(T... args) {((cout<<args<< ), ...); cout<< n ;} int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int tt; cin>>tt; next: while (tt--) { int n, u, v; cin>>n>>u>>v; vector<int> a(n); for (auto& i : a) cin>>i; int ans=2e9; for (int i=1; i<n; i++) { if (abs(a[i]-a[i-1])>1) { cout<< 0 n ; goto next; } if (abs(a[i]-a[i-1])==1) ans=min(ans, min(u, v)); } ans=min(ans, v+min(u, v)); cout<<ans<< n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD1_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD1_BEHAVIORAL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__dlygate4sd1 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD1_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int n, x; bool vis[300010]; int a[300010]; int ans = 1; int main() { scanf( %d , &n); x = n; printf( %d , ans); for (int i = 1; i < n; i++) { scanf( %d , &a[i]); vis[a[i]] = 1; bool p = 0; bool v = 0; while (vis[x]) { ans--; x--; } ans++; printf( %d , ans); } printf( %d , 1); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
//Simple debug:
//wire [1:1] wir_a [3:3] [2:2]; //11
//logic [1:1] log_a [3:3] [2:2]; //12
//wire [3:3] [2:2] [1:1] wir_p; //13
//logic [3:3] [2:2] [1:1] log_p; //14
integer cyc; initial cyc = 0;
`ifdef IVERILOG
reg [7:0] arr [3:0];
wire [7:0] arr_w [3:0];
`else
reg [3:0] [7:0] arr;
wire [3:0] [7:0] arr_w;
`endif
reg [7:0] sum;
reg [7:0] sum_w;
integer i0;
initial begin
for (i0=0; i0<5; i0=i0+1) begin
arr[i0] = 1 << (i0[1:0]*2);
end
end
assign arr_w = arr;
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
sum <= 0;
sum_w <= 0;
end
else if (cyc >= 10 && cyc < 14) begin
sum <= sum + arr[cyc-10];
sum_w <= sum_w + arr_w[cyc-10];
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d sum=%x\n", $time, cyc, sum);
if (sum != 8'h55) $stop;
if (sum != sum_w) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
// Test ordering of packed dimensions
logic [31:0] data_out;
logic [31:0] data_out2;
logic [0:0] [2:0] [31:0] data_in;
logic [31:0] data_in2 [0:0] [2:0];
assign data_out = data_in[0][0] + data_in[0][1] + data_in[0][2];
assign data_out2 = data_in2[0][0] + data_in2[0][1] + data_in2[0][2];
logic [31:0] last_data_out;
always @ (posedge clk) begin
if (cyc <= 2) begin
data_in[0][0] <= 0;
data_in[0][1] <= 0;
data_in[0][2] <= 0;
data_in2[0][0] <= 0;
data_in2[0][1] <= 0;
data_in2[0][2] <= 0;
end
else if (cyc > 2 && cyc < 99) begin
data_in[0][0] <= data_in[0][0] + 1;
data_in[0][1] <= data_in[0][1] + 1;
data_in[0][2] <= data_in[0][2] + 1;
data_in2[0][0] <= data_in2[0][0] + 1;
data_in2[0][1] <= data_in2[0][1] + 1;
data_in2[0][2] <= data_in2[0][2] + 1;
last_data_out <= data_out;
`ifdef TEST_VERBOSE
$write("data_out %0x %0x\n", data_out, last_data_out);
`endif
if (cyc > 4 && data_out != last_data_out + 3) $stop;
if (cyc > 4 && data_out != data_out2) $stop;
end
end
// Test for mixed implicit/explicit dimensions and all implicit packed
bit [3:0][7:0][1:0] vld [1:0][1:0];
bit [3:0][7:0][1:0] vld2;
// There are specific nodes for Or, Xor, Xnor and And
logic vld_or;
logic vld2_or;
assign vld_or = |vld[0][0];
assign vld2_or = |vld2;
logic vld_xor;
logic vld2_xor;
assign vld_xor = ^vld[0][0];
assign vld2_xor = ^vld2;
logic vld_xnor;
logic vld2_xnor;
assign vld_xnor = ~^vld[0][0];
assign vld2_xnor = ~^vld2;
logic vld_and;
logic vld2_and;
assign vld_and = &vld[0][0];
assign vld2_and = &vld2;
// Bit reductions should be cloned, other unary operations should clone the
// entire assign.
bit [3:0][7:0][1:0] not_lhs;
bit [3:0][7:0][1:0] not_rhs;
assign not_lhs = ~not_rhs;
// Test an AstNodeUniop that shouldn't be expanded
bit [3:0][7:0][1:0] vld2_inv;
assign vld2_inv = ~vld2;
initial begin
for (int i=0; i<4; i=i+2) begin
for (int j=0; j<8; j=j+2) begin
vld[0][0][i][j] = 2'b00;
vld[0][0][i+1][j+1] = 2'b00;
vld2[i][j] = 2'b00;
vld2[i+1][j+1] = 2'b00;
not_rhs[i][j] = i[1:0];
not_rhs[i+1][j+1] = i[1:0];
end
end
end
logic [3:0] expect_cyc; initial expect_cyc = 'd15;
always @(posedge clk) begin
expect_cyc <= expect_cyc + 1;
for (int i=0; i<4; i=i+1) begin
for (int j=0; j<8; j=j+1) begin
vld[0][0][i][j] <= vld[0][0][i][j] + 1;
vld2[i][j] <= vld2[i][j] + 1;
if (not_rhs[i][j] != ~not_lhs[i][j]) $stop;
not_rhs[i][j] <= not_rhs[i][j] + 1;
end
end
if (cyc % 8 == 0) begin
vld[0][0][0][0] <= vld[0][0][0][0] - 1;
vld2[0][0] <= vld2[0][0] - 1;
end
if (expect_cyc < 8 && !vld_xor) $stop;
else if (expect_cyc > 7 && vld_xor) $stop;
if (expect_cyc < 8 && vld_xnor) $stop;
else if (expect_cyc > 7 && !vld_xnor) $stop;
if (expect_cyc == 15 && vld_or) $stop;
else if (expect_cyc == 11 && vld_or) $stop;
else if (expect_cyc != 15 && expect_cyc != 11 && !vld_or) $stop;
if (expect_cyc == 10 && !vld_and) $stop;
else if (expect_cyc == 14 && !vld_and) $stop;
else if (expect_cyc != 10 && expect_cyc != 14 && vld_and) $stop;
if (vld_xor != vld2_xor) $stop;
if (vld_xnor != vld2_xnor) $stop;
if (vld_or != vld2_or) $stop;
if (vld_and != vld2_and) $stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; vector<long long> a(n); vector<long long> v; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n - 1; i++) { v.push_back(abs(a[i] - a[i + 1])); } long long ans = a[n - 1] - a[0]; sort(v.begin(), v.end()); int y = v.size() - 1; k--; while (k--) { ans = ans - v[y--]; } cout << ans; return 0; } |
// Copyright 2007 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design
// License Agreement (either as signed by you or found at www.altera.com). By
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation. In the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. By making this reference
// design file available, Altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by Altera.
/////////////////////////////////////////////////////////////////////////////
// baeckler - 2-13-2006
// compute sum of 36 bit lines
//
// uses nine 6:3 compressors = 27 six-luts
// plus a 5 bit carry propagate output adder (one bit falls through)
module thirtysix_six_comp (data,sum);
input [31:0] data;
output [31:0] sum;
wire [31:0] sum;
wire [5:0] word_l;
wire [5:0] word_m;
wire [5:0] word_h;
wire [2:0] sa,sb,sc,sd,se,sf;
wire [2:0] slo,sme,shi;
six_three_comp a (.data(data[5:0]),.sum(sa));
six_three_comp b (.data(data[11:6]),.sum(sb));
six_three_comp c (.data(data[17:12]),.sum(sc));
six_three_comp d (.data(data[23:18]),.sum(sd));
six_three_comp e (.data(data[29:24]),.sum(se));
six_three_comp f (.data({4'b0,data[31:30]}),.sum(sf));
six_three_comp lo (.data({sa[0],sb[0],sc[0],sd[0],se[0],sf[0]}),.sum(slo));
six_three_comp me (.data({sa[1],sb[1],sc[1],sd[1],se[1],sf[1]}),.sum(sme));
six_three_comp hi (.data({sa[2],sb[2],sc[2],sd[2],se[2],sf[2]}),.sum(shi));
wire [7:0] tmp_sum;
ternary_add t (.a({3'b0,slo}),
.b({2'b0,sme,1'b0}),
.c({1'b0,shi,2'b0}),
.o(tmp_sum));
defparam t .WIDTH = 6;
assign sum = {26'b0,tmp_sum[5:0]};
endmodule
|
#include <bits/stdc++.h> namespace io { int F() { int F = 1, n = 0; char ch; while ((ch = getchar()) != - && (ch < 0 || ch > 9 )) ; ch == - ? F = 0 : n = ch - 0 ; while ((ch = getchar()) >= 0 && ch <= 9 ) n = n * 10 + ch - 0 ; return F ? n : -n; } long long G() { long long F = 1, n = 0; char ch; while ((ch = getchar()) != - && (ch < 0 || ch > 9 )) ; ch == - ? F = 0 : n = ch - 0 ; while ((ch = getchar()) >= 0 && ch <= 9 ) n = n * 10 + ch - 0 ; return F ? n : -n; } } // namespace io int R(int l, int r) { return (rand() << 15 | rand()) % (r - l + 1) + l; } int main() { long long n = io::G(), l = io::G() - 1, r = io::G() - 1, k = io::G(); long long B = l <= r ? r - l + 1 : n - (l - r - 1), S = n - B; long long ans = -1; int fl = 1; start:; if ((k - B) / n <= 22000000) { int u = (k - B) / n; for (register int x = 0; x <= u; ++x) { long long re = k - B - x * n; if (x == 0) { if (re <= B && re >= 0) if (fl || re) (ans < (S + re) ? ans = (S + re), 1 : 0); } else { long long B1 = re % x, S1 = re / x - B1; if (B1 > B || S1 < 0) continue; if (S1 <= S) { if (fl || B1) (ans < (B1 + S1) ? ans = (B1 + S1), 1 : 0); } else { long long T = S1 - S; long long ex = (T + x) / (x + 1); B1 += ex * x; S1 -= ex * (x + 1); if (S1 >= 0 && B1 <= B) if (fl || B1) (ans < (B1 + S1) ? ans = (B1 + S1), 1 : 0); } } } } else { for (register long long S1 = 0; S1 <= S; ++S1) for (register long long B1 = 0; B1 <= B; ++B1) { long long y = k - B1 - B; long long a = S1 + B1 + n; if (y == 0 && a == 0 || a && y % a == 0 && y / a >= 0) if (fl || B1) (ans < (S1 + B1) ? ans = (S1 + B1), 1 : 0); } } if (fl) { k = k + 1; fl = 0; goto start; } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int s = 1000000; int a[1000001]; bool belongs[1000001]; bool used[1000001]; vector<int> ans; int main() { int n; cin >> n; for (int i = 0; i <= s; i++) belongs[i] = used[i] = false; for (int i = 0; i < n; i++) { scanf( %i , &a[i]); belongs[a[i]] = true; } int u = 1; for (int i = 0; i < n; i++) if (!used[a[i]]) { if (belongs[a[i]] && !belongs[s - a[i] + 1] && !used[s - a[i] + 1]) { ans.push_back(s - a[i] + 1); used[s - a[i] + 1] = true; used[a[i]] = true; } else if (belongs[a[i]] && belongs[s - a[i] + 1]) { while (u <= s && (belongs[u] || belongs[s - u + 1] || used[u] || used[s - u + 1])) u++; used[u] = true; used[s - u + 1] = true; used[s - a[i] + 1] = true; used[a[i]] = true; ans.push_back(u); ans.push_back(s - u + 1); u++; } else assert(false); } cout << int(ans.size()) << endl; for (int i = 0; i < int(ans.size()); i++) printf( %i , ans[i]); cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long bigmod(long long base, long long power, long long mod) { if (power == 0) return 1; else if (power % 2 == 1) { long long p1 = base % mod; long long p2 = (bigmod(base, power - 1, mod)) % mod; return (p1 * p2) % mod; } else if (power % 2 == 0) { long long p1 = (bigmod(base, power / 2, mod)) % mod; return (p1 * p1) % mod; } } long long ncr(long long n, long long k) { long long C[n + 1][k + 1]; long long i, j; for (i = 0; i <= n; i++) { for (j = 0; j <= min(i, k); j++) { if (j == 0 || j == i) C[i][j] = 1; else C[i][j] = C[i - 1][j - 1] + C[i - 1][j]; } } return C[n][k]; } long long prime[500008]; long long sp[500008]; void seive() { for (int i = 2; i <= 500008; i += 2) sp[i] = 2; for (int i = 3; i <= 500008; i += 2) sp[i] = i; long long x = sqrt(500008); for (int i = 3; i <= x; i += 2) { if (sp[i] == i) { for (int j = i * i; j <= 500008; j += i) { sp[j] = i; } } } } map<long long, long long> m; void pf(long long n) { while (1) { if (n <= 1) break; long long x = sp[n]; while (n % x == 0) { n /= x; m[x]++; } } } int main() { ios_base::sync_with_stdio(false); long long t = 1; seive(); while (t--) { long long k, a, b; cin >> k >> a >> b; string s; cin >> s; long long n = s.size(); long long x = n / k; long long y = ceil(n / (1.0 * k)); if (x >= a && y <= b) { int j = 0; long long rem = n % k; for (int i = 1; i <= rem; i++) { for (int z = 0; z <= x; z++) { cout << s[j++]; } cout << endl; } for (int i = 1; i <= k - rem; i++) { for (int z = 0; z < x; z++) { cout << s[j++]; } cout << endl; } } else cout << No solution << endl; } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
logic [3:0] array_simp [1:0] [3:0]; // big endian array
int irep[1:2][1:6];
initial begin
array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0};
if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 16'h3210) $stop;
// verilator lint_off WIDTH
array_simp[0] = '{ 3 ,2 ,1, 0 };
// verilator lint_on WIDTH
if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 16'h3210) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
//array_simp[0] = '{ 1:4'd3, default:13 };
//if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop;
array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 32'h3210_1234) $stop;
// Doesn't seem to work for unpacked arrays in other simulators
array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 32'h3210_3210) $stop;
array_simp = '{2{ '{4{ 4'd3 }} }};
if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0],
array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]}
!== 32'h3333_3333) $stop;
// Not legal in other simulators - replication doesn't match
// However IEEE suggests this is legal.
//array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2}
// Replication
irep = '{2{ '{3 {4, 5}}}};
if ({irep[1][1], irep[1][2], irep[1][3], irep[1][4], irep[1][5], irep[1][6]}
!= {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop;
if ({irep[2][1], irep[2][2], irep[2][3], irep[2][4], irep[2][5], irep[2][6]}
!= {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3B_4_V
`define SKY130_FD_SC_LS__AND3B_4_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3b_4 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3b_4 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3B_4_V
|
module Computer_Datapath_RegisterFile(
output reg [WORD_WIDTH-1:0] ADDR_bus_out,
output reg [WORD_WIDTH-1:0] B_data_out,
input [CNTRL_WIDTH-1:0] CNTRL_bus_in,
input [WORD_WIDTH-1:0] D_bus_in,
input CLK,
input RST
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SA_WIDTH = DR_WIDTH;
parameter SB_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter FS_WIDTH = 4;
parameter CNTRL_FLAGS_WIDTH = 7;
parameter CNTRL_WIDTH = DR_WIDTH+SA_WIDTH+SB_WIDTH+FS_WIDTH+CNTRL_FLAGS_WIDTH;
wire RW = CNTRL_bus_in[4];
wire [SA_WIDTH-1:0] DA = CNTRL_bus_in[19:17];
wire [SA_WIDTH-1:0] AA = CNTRL_bus_in[16:14];
wire [SA_WIDTH-1:0] BA = CNTRL_bus_in[13:11];
reg [WORD_WIDTH-1:0] SYNC_RAM0 [2**DR_WIDTH-1:0];
reg [WORD_WIDTH-1:0] SYNC_RAM1 [2**DR_WIDTH-1:0];
reg [DR_WIDTH-1:0] i;
always@(posedge CLK) begin
/*
if (!RST)
for (i=3'b0;i<2**DR_WIDTH-3'b1;i = i + 3'b1) begin
SYNC_RAM1[i] <= 0;
SYNC_RAM0[i] <= 0;
end
else if (RW) begin
*/
if(RW) begin
SYNC_RAM0[DA] <= D_bus_in;
SYNC_RAM1[DA] <= D_bus_in;
end
end
always@(*) begin
ADDR_bus_out <= SYNC_RAM0[AA];
B_data_out <= SYNC_RAM1[BA];
end
endmodule
|
//ft_fifo_tester.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x800000000000C594
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:ft_fifo_tester
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0F
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2016/08/14
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:3
*/
module ft_fifo_tester (
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int
//output o_wbs_int
);
//Local Parameters
localparam ADDR_0 = 32'h00000000;
localparam ADDR_1 = 32'h00000001;
localparam ADDR_2 = 32'h00000002;
//Local Registers/Wires
reg [31:0] r_test_data;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
r_test_data <= 0;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
ADDR_0: begin
//writing something to address 0
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
r_test_data <= i_wbs_dat;
end
ADDR_1: begin
//writing something to address 1
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
ADDR_2: begin
//writing something to address 3
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
else begin
//read request
case (i_wbs_adr)
ADDR_0: begin
//reading something from address 0
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
//$display("user read %h", ADDR_0);
//o_wbs_dat <= ADDR_0;
o_wbs_dat <= r_test_data;
end
ADDR_1: begin
//reading something from address 1
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_1);
o_wbs_dat <= ADDR_1;
end
ADDR_2: begin
//reading soething from address 2
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_2);
o_wbs_dat <= ADDR_2;
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
o_wbs_ack <= 1;
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR4BB_BEHAVIORAL_V
`define SKY130_FD_SC_HS__OR4BB_BEHAVIORAL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
// Local signals
wire DN nand0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR4BB_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int M = 2e6 + 10; int a[M], b[M], c[M], d[M], e[M], f[M]; vector<int> T[M]; struct NTT { static const int G = 3, P = 998244353; int N, na, nb, w[2][M], rev[M]; long long kpow(long long a, int b) { long long c = 1; for (; b; b >>= 1, a = a * a % P) if (b & 1) c = c * a % P; return c; } void FFT(int *a, int f) { for (int i = (0); i < (N); i++) if (i < rev[i]) swap(a[i], a[rev[i]]); for (int i = 1; i < N; i <<= 1) for (int j = 0, t = N / (i << 1); j < N; j += i << 1) for (int k = 0, l = 0, x, y; k < i; k++, l += t) x = (long long)w[f][l] * a[j + k + i] % P, y = a[j + k], a[j + k] = (y + x) % P, a[j + k + i] = (y - x + P) % P; if (f) for (int i = 0, x = kpow(N, P - 2); i < N; i++) a[i] = (long long)a[i] * x % P; } void work() { int d = __builtin_ctz(N); w[0][0] = w[1][0] = 1; for (int i = 1, x = kpow(G, (P - 1) / N), y = kpow(x, P - 2); i < N; i++) { rev[i] = (rev[i >> 1] >> 1) | ((i & 1) << (d - 1)); w[0][i] = (long long)x * w[0][i - 1] % P, w[1][i] = (long long)y * w[1][i - 1] % P; } } void doit(int *a, int *b, int na, int nb) { for (N = 1; N < na + nb - 1; N <<= 1) ; for (int i = (na); i < (N); i++) a[i] = 0; for (int i = (nb); i < (N); i++) b[i] = 0; work(), FFT(a, 0), FFT(b, 0); for (int i = (0); i < (N); i++) a[i] = (long long)a[i] * b[i] % P; FFT(a, 1); } void get_inv(int *a, int *b, int na) { if (na == 1) { b[0] = kpow(a[0], P - 2); return; } get_inv(a, b, (na + 1) >> 1); for (N = 1; N < (na << 1); N <<= 1) ; work(); for (int i = (0); i < (na); i++) c[i] = a[i]; for (int i = (na); i < (N); i++) c[i] = 0; FFT(c, 0), FFT(b, 0); for (int i = (0); i < (N); i++) b[i] = 1ll * (2 - 1ll * c[i] * b[i] % P + P) % P * b[i] % P; FFT(b, 1); for (int i = (na); i < (N); i++) b[i] = 0; } void get_ln(int *a, int *b, int na) { for (int i = (0); i < (na - 1); i++) d[i] = (long long)(a[i + 1]) * (i + 1) % P; for (int i = (na); i < (N); i++) d[i] = 0; d[na - 1] = 0; get_inv(a, b, na); doit(b, d, na, na); for (int i = (na)-1; i >= (1); i--) b[i] = (long long)b[i - 1] * kpow(i, P - 2) % P; b[0] = 0; } void get_exp(int *a, int *b, int na) { if (na == 1) { b[0] = 1; return; } get_exp(a, b, (na + 1) >> 1); for (int i = 0; i < (na << 1); i++) f[i] = 0; get_ln(b, f, na); for (N = 1; N < (na << 1); N <<= 1) ; work(); f[0] = ((long long)a[0] + 1 - f[0] + P) % P; for (int i = (1); i < (na); i++) f[i] = ((long long)a[i] - f[i] + P) % P; FFT(f, 0); FFT(b, 0); for (int i = (0); i < (N); i++) b[i] = (long long)b[i] * f[i] % P; FFT(b, 1); for (int i = (na); i < (N); i++) b[i] = f[i] = 0; } void get_pow(int *a, int *b, int na, int k) { get_ln(a, e, na); for (int i = (0); i < (na); i++) e[i] = (long long)e[i] * k % P; get_exp(e, b, na); } void fast_pow(int *a, int *b, int na, int k, int maxn) { for (N = 1; N < max(((maxn + 1) << 1), (na << 1)); N <<= 1) ; for (int i = (na); i < (N); i++) a[i] = 0; for (int i = (0); i < (N); i++) b[i] = 0; b[0] = 1; work(); while (k) { FFT(a, 0); if (k & 1) { FFT(b, 0); for (int i = (0); i < (N); i++) b[i] = (long long)a[i] * b[i] % P; FFT(b, 1); for (int i = (max(na, maxn + 1)); i < (N); i++) b[i] = 0; } for (int i = (0); i < (N); i++) a[i] = (long long)a[i] * a[i] % P; FFT(a, 1); for (int i = (max(na, maxn + 1)); i < (N); i++) a[i] = 0; k >>= 1; } } priority_queue<pair<int, int> > H; void Merge(int m) { while (!H.empty()) H.pop(); for (int i = (1); i < (m + 1); i++) H.emplace(make_pair(-T[i].size(), i)); while (H.size() >= 2) { int x = H.top().second; H.pop(); int y = H.top().second; H.pop(); for (int i = (0); i < (T[x].size()); i++) a[i] = T[x][i]; for (int i = (0); i < (T[y].size()); i++) b[i] = T[y][i]; doit(a, b, T[x].size(), T[y].size()); int na = T[x].size() + T[y].size(); T[x].clear(); T[y].clear(); for (int i = (0); i < (na); i++) T[x].push_back(a[i]); H.emplace(-T[x].size(), x); } } } ntt; int F[10]; int dis[300000 + 10][7][7]; int find(int i) { if (F[i] == i) return i; return F[i] = find(F[i]); } int main() { string s, t; cin >> s >> t; int n = s.size(), m = t.size(); reverse(t.begin(), t.end()); for (int i = (0); i < (6); i++) { for (int j = (0); j < (6); j++) { if (i == j) continue; for (int k = (0); k < (n); k++) { if (s[k] == i + a ) a[k] = 1; else a[k] = 0; } for (int k = (0); k < (m); k++) { if (t[k] == j + a ) b[k] = 1; else b[k] = 0; } ntt.doit(a, b, n, m); for (int k = (m - 1); k < (n); k++) { dis[k][i][j] = a[k]; } } } for (int i = (m - 1); i < (n); i++) { for (int j = (0); j < (6); j++) F[j] = j; for (int j = (0); j < (6); j++) { for (int k = (0); k < (6); k++) { if (j == k) continue; if (dis[i][j][k]) F[find(j)] = find(k); } } int ans = 0; for (int j = (0); j < (6); j++) { if (F[j] == j) ans++; } cout << 6 - ans << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 233; const int INF = numeric_limits<int>::max(); void read(int &x) { x = 0; char ch = getchar(); int f = 1; while (!isdigit(ch)) (ch == - ? f = -1 : 0), ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); x *= f; } int f[N][105], g[105]; int n, K, p, a[N], nw, s[N]; int x, sum, st[N], tp; signed main() { memset(g, 0x7f, sizeof(g)); memset(f, 0x7f, sizeof(f)); read(n); read(K); read(p); if (p * K > n) { for (int i = 1; i <= n; ++i) { read(x); x %= p; a[i] = x; sum = (sum + a[i]) % p; f[i][1] = sum; g[1] = sum; for (int j = min(K, i); j >= 2; --j) if (i == j) { f[i][j] = f[i - 1][j - 1] + x; g[j] = x; } else { int l = f[i - 1][j - 1] + x; int r = f[i - 1][j] + x; if (g[j] + x >= p) r -= p; if (l < r) f[i][j] = l, g[j] = x; else if (l > r) f[i][j] = r, g[j] = (g[j] + x) % p; else f[i][j] = l, g[j] = max(x, (g[j] + x) % p); } } return printf( %d , f[n][K]), 0; } for (int i = 1; i <= n; ++i) read(a[i]), a[i] %= p, sum += a[i], s[i] = (s[i - 1] + a[i]) % p; for (int i = 1; i <= n - 1; ++i) { int pos = upper_bound(st + 1, st + 1 + tp, s[i]) - st; if (pos > tp) ++tp; st[pos] = s[i]; } int pos = upper_bound(st + 1, st + 1 + tp, s[n]) - st; if (pos >= K) printf( %d , s[n]); else printf( %d , s[n] + p); return 0; } |
#include <bits/stdc++.h> using namespace std; double n, h; char c[10]; double ans; double ksm(double x, long long y) { double maretu = 1.0; for (; y; y >>= 1) { if (y & 1) { maretu *= x; } x *= x; } return maretu; } int main() { scanf( %s , c); if (c[0] == A ) { scanf( %lf%lf , &n, &h); ans = n; for (double i = 1; i <= h; ++i) { for (double j = 1; j <= n; ++j) { ans += (n - j) * (1.0 / (double)(1LL << (long long)(2 * i))) * ksm(1.0 - (1.0 / (double)(1LL << (long long)i)), (long long)(j - 1.0)) * ((double)(1LL << ((long long)i)) - (double)(1LL << (long long)(i - 1)) * (1.0 + (j - 1.0) / ((double)(1LL << (long long)(i)) - 1.0))); } } printf( %.10lf , ans); } else { scanf( %lf%lf , &n, &h); printf( %lf , n); } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's IC TAGs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instatiation of instruction cache tag rams ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_ic_tag(
// Clock and reset
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, tag_v, tag
);
parameter dw = `OR1200_ICTAG_W;
parameter aw = `OR1200_ICTAG;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Internal i/f
//
input [aw-1:0] addr;
input en;
input we;
input [dw-1:0] datain;
output tag_v;
output [dw-2:0] tag;
`ifdef OR1200_NO_IC
//
// Insn cache not implemented
//
assign tag = {dw-1{1'b0}};
assign tag_v = 1'b0;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of TAG RAM block
//
`ifdef OR1200_IC_1W_512B
or1200_spram_32x24 ic_tag0(
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram_256x21 ic_tag0(
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram_512x20 ic_tag0(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq({tag, tag_v})
);
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFBUF_PP_SYMBOL_V
`define SKY130_FD_SC_LS__BUFBUF_PP_SYMBOL_V
/**
* bufbuf: Double buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__bufbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFBUF_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n; cin >> t; while (t--) { cin >> n; cout << n / 2 << endl; } } |
//****************************************************************************/
// ARTY CM0 Design Start
// RTL IMPLEMENTATION, Synchronous Version
//
// Copyright (C) yyyy Ronan Barzic -
// Date : Tue Nov 10 23:56:32 2015
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,MA 02110-1301,USA.
//
//
// Filename : cmsdk_ahb_ram.v
//
// Description : Custom ram implementation for simulation and FPGA
// Use exactly the same interface than the original file from CM0 designstart
//
//
//****************************************************************************/
module cmsdk_ahb_ram(/*AUTOARG*/
// Outputs
HREADYOUT, HRDATA, HRESP,
// Inputs
HCLK, HRESETn, HSEL, HADDR, HTRANS, HSIZE, HWRITE, HWDATA, HREADY
);
parameter AW = 16;// Address width
parameter ROM = 0;
parameter filename = "";
input HCLK; // Clock
input HRESETn; // Reset
// AHB inputs
input HSEL; // Device select
input [AW-1:0] HADDR; // Address
input [1:0] HTRANS; // Transfer control
input [2:0] HSIZE; // Transfer size
input HWRITE; // Write control
input [31:0] HWDATA; // Write data
input HREADY; // Transfer phase done
// AHB Outputs
output HREADYOUT; // Device ready
output [31:0] HRDATA; // Read data output
output HRESP; // Device response (always OKAY)
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOREG*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [AW-1:0] ahb_sram_addr; // From U_AHB_TO_SSRAM of ahb_to_ssram.v
wire [31:0] ahb_sram_din; // From U_AHB_TO_SSRAM of ahb_to_ssram.v
wire [3:0] ahb_sram_wb; // From U_AHB_TO_SSRAM of ahb_to_ssram.v
wire [31:0] sram_ahb_dout; // From U_RAM of bytewrite_ram_1b.v
// End of automatics
wire [3:0] ahb_sram_wb_qual;
ahb_to_ssram #(.AW(AW)) U_AHB_TO_SSRAM
(
.ahb_sram_we (),
.ahb_sram_en (),
.ahb_sram_enb (),
/*AUTOINST*/
// Outputs
.HREADYOUT (HREADYOUT),
.HRDATA (HRDATA[31:0]),
.HRESP (HRESP),
.ahb_sram_addr (ahb_sram_addr[AW-1:0]),
.ahb_sram_wb (ahb_sram_wb[3:0]),
.ahb_sram_din (ahb_sram_din[31:0]),
// Inputs
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (HSEL),
.HADDR (HADDR[AW-1:0]),
.HTRANS (HTRANS[1:0]),
.HSIZE (HSIZE[2:0]),
.HWRITE (HWRITE),
.HWDATA (HWDATA[31:0]),
.HREADY (HREADY),
.sram_ahb_dout (sram_ahb_dout[31:0]));
assign ahb_sram_wb_qual = ahb_sram_wb & {4{!ROM}};
/* -----\/----- EXCLUDED -----\/-----
/-* sync_ram_wf_x32 AUTO_TEMPLATE(
.dout (sram_ahb_dout[31:0]),
.din (ahb_sram_din[31:0]),
.enb (ahb_sram_enb[@]),
.addr (ahb_sram_addr[9:0]),
.clk(HCLK),
); *-/
sync_ram_wf_x32 #(.ADDR_WIDTH(AW-2))
U_RAM(
.web (ahb_sram_wb_qual[3:0]),
/-*AUTOINST*-/
// Outputs
.dout (sram_ahb_dout[31:0]),
// Inputs
.clk (HCLK),
.enb (ahb_sram_enb[3:0]),
.addr (ahb_sram_addr[9:0]),
.din (ahb_sram_din[31:0]));
-----/\----- EXCLUDED -----/\----- */
/* bytewrite_ram_32bits AUTO_TEMPLATE(
.dout (sram_ahb_dout[31:0]),
.din (ahb_sram_din[31:0]),
.enb (ahb_sram_enb[@]),
.we (ahb_sram_wb[3:0]),
.addr (ahb_sram_addr[9:0]),
.clk(HCLK),
); */
bytewrite_ram_32bits
#(.SIZE(1<<(AW-2)),.ADDR_WIDTH(AW-2))
U_RAM (
/*AUTOINST*/
// Outputs
.dout (sram_ahb_dout[31:0]), // Templated
// Inputs
.clk (HCLK), // Templated
.we (ahb_sram_wb[3:0]), // Templated
.addr (ahb_sram_addr[AW-1:2]), // Templated
.din (ahb_sram_din[31:0])); // Templated
endmodule
/*
Local Variables:
verilog-library-directories:(
"."
"../import/amba_components/ahb_to_ssram/rtl/verilog"
)
End:
*/
|
#include <bits/stdc++.h> using namespace std; int t, i; int c[32650]; void ciu(); unsigned long long int p, q; unsigned long long int minim = 0xffffffffffffffff; vector<unsigned long long int> v; int main() { cin >> t; ciu(); while (t--) { minim = 0xffffffffffffffff; cin >> p >> q; if (p % q != 0) cout << p << n ; else { for (i = 0; i < v.size() && v[i] * v[i] <= q; i++) if (q % v[i] == 0) { unsigned long long int exp = 0, rez = 1; while (q % v[i] == 0) { q /= v[i]; exp++; rez *= v[i]; } if (rez != 1) { unsigned long long int expx = 0, rezx = 1; unsigned long long int cp = p; cp /= rez; while (cp % v[i] == 0) { cp /= v[i]; expx++; rezx *= v[i]; } rezx *= v[i]; if (rezx < minim) minim = rezx; } } if (q != 1) { unsigned long long int expq = 0, rezq = 1; unsigned long long int cp = p; cp /= q; while (cp % q == 0) { cp /= q; expq++; rezq *= q; } rezq *= q; if (rezq < minim) minim = rezq; } cout << p / minim << n ; } } return 0; } void ciu() { int i, j; for (i = 2; i * i < 32650; i++) if (!c[i]) for (j = i * i; j < 32650; j += i) c[j] = 1; for (i = 2; i < 32650; i++) if (!c[i]) v.push_back(i); } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
(* X_CORE_INFO = "xlslice,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "design_1_xlslice_4_2,xlslice,{}" *)
(* CORE_GENERATION_INFO = "design_1_xlslice_4_2,xlslice,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,DIN_WIDTH=32,DIN_FROM=29,DIN_TO=6}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_4_2 (
Din,
Dout
);
input wire [31 : 0] Din;
output wire [23 : 0] Dout;
xlslice #(
.DIN_WIDTH(32),
.DIN_FROM(29),
.DIN_TO(6)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int scan() { int x; scanf( %d , &x); return x; } struct data { int first; int edge_used; int prev; data() { first = 0; edge_used = 0; prev = 0; } }; vector<pair<int, int> > v[100005]; bool edge[100005] = {0}; pair<int, int> edges[100005]; data nodes[100005]; bool visited[100005] = {0}; bool used[100005] = {0}; int dist[100005]; int main() { int n = scan(), m = scan(); for (int i = 1; i <= m; i++) { int x = scan(), y = scan(), z = scan(); v[x].push_back(make_pair(y, i)); v[y].push_back(make_pair(x, i)); edge[i] = z; edges[i] = make_pair(x, y); } queue<int> q; q.push(1); visited[1] = 1; for (int i = 0; i <= n; i++) dist[i] = 999999; dist[1] = 0; bool aslivisit[100001] = {0}; while (!q.empty()) { int node = q.front(); aslivisit[node] = 1; q.pop(); int x = v[node].size(); int num = nodes[node].first; for (int i = 0; i < x; i++) { int next = v[node][i].first; if (aslivisit[next]) continue; int num2 = num; if (edge[v[node][i].second] == 0) { num2++; } if (!visited[next]) { visited[next] = 1; q.push(next); nodes[next].first = num2; nodes[next].edge_used = v[node][i].second; nodes[next].prev = node; dist[next] = dist[node] + 1; } else if (dist[next] >= dist[node] + 1) { if (num2 < nodes[next].first) { nodes[next].first = num2; nodes[next].edge_used = v[node][i].second; nodes[next].prev = node; } } } } int cur = n; while (cur != 0) { used[nodes[cur].edge_used] = 1; cur = nodes[cur].prev; } int counter = 0; queue<pair<pair<int, int>, bool> > ans; for (int i = 1; i <= m; i++) { if (!used[i] && edge[i] == 1) { counter++; ans.push(make_pair(edges[i], 0)); } else if (used[i] && edge[i] == 0) { counter++; ans.push(make_pair(edges[i], 1)); } } printf( %d n , counter); while (!ans.empty()) { printf( %d %d %d n , ans.front().first.first, ans.front().first.second, ans.front().second); ans.pop(); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O2BB2AI_FUNCTIONAL_PP_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2AI_FUNCTIONAL_PP_V |
`timescale 1ns/1ps
module BigSDRAMSim;
reg clock0;
reg clock180;
reg clock270;
reg clock2x0;
reg clock2x90;
reg clock2x180;
reg reset;
wire [7:0] leds;
wire ddr_cke;
wire ddr_csn;
wire ddr_rasn;
wire ddr_casn;
wire ddr_wen;
wire [1:0] ddr_ba;
wire [12:0] ddr_addr;
wire [1:0] ddr_dm;
wire [15:0] ddr_dq;
wire [1:0] ddr_dqs;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#800000 $finish;
end
initial begin
#0 clock0 = 1;
forever #10 clock0 = ~clock0;
end
initial begin
#10 clock180 = 1;
forever #10 clock180 = ~clock180;
end
initial begin
#15 clock270 = 1;
forever #10 clock270 = ~clock270;
end
initial begin
#0 clock2x0 = 1;
forever #5 clock2x0 = ~clock2x0;
end
initial begin
#2.5 clock2x90 = 1;
forever #5 clock2x90 = ~clock2x90;
end
initial begin
#5 clock2x180 = 1;
forever #5 clock2x180 = ~clock2x180;
end
initial begin
#0 reset = 0;
#60 reset = 1;
#40 reset = 0;
end
Ddr
ddr (.Clk(clock2x0),
.Clk_n(clock2x180),
.Cke(ddr_cke),
.Cs_n(ddr_csn),
.Ras_n(ddr_rasn),
.Cas_n(ddr_casn),
.We_n(ddr_wen),
.Ba(ddr_ba),
.Addr(ddr_addr),
.Dm(ddr_dm),
.Dq(ddr_dq),
.Dqs(ddr_dqs));
BigSDRAM
bigsdram (.clock0(clock0),
.clock180(clock180),
.clock270(clock270),
.reset(reset),
.leds(leds),
.ddr_clock0(clock2x0),
.ddr_clock90(clock2x90),
.ddr_cke(ddr_cke),
.ddr_csn(ddr_csn),
.ddr_rasn(ddr_rasn),
.ddr_casn(ddr_casn),
.ddr_wen(ddr_wen),
.ddr_ba(ddr_ba),
.ddr_addr(ddr_addr),
.ddr_dm(ddr_dm),
.ddr_dq(ddr_dq),
.ddr_dqs(ddr_dqs));
endmodule // BigSDRAMSim
|
`include "hglobal.v"
`default_nettype none
`define NS_NUM_TEST 7
`define NS_TEST_MIN_ADDR 1
`define NS_TEST_MAX_ADDR 14
`define NS_TEST_REF_ADDR 23
`define NS_NUM_DBG_CASES 12
module test_top
#(parameter
PSZ=`NS_PACKET_SIZE,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
input i_clk,
input i_Switch_1,
input i_Switch_2,
input i_Switch_3,
input i_Switch_4,
output o_Segment1_A,
output o_Segment1_B,
output o_Segment1_C,
output o_Segment1_D,
output o_Segment1_E,
output o_Segment1_F,
output o_Segment1_G,
output o_Segment2_A,
output o_Segment2_B,
output o_Segment2_C,
output o_Segment2_D,
output o_Segment2_E,
output o_Segment2_F,
output o_Segment2_G,
output o_LED_1,
output o_LED_2,
output o_LED_3,
output o_LED_4
);
reg [0:0] reset = 0;
wire ready;
wire w_Switch_1;
reg r_Switch_1 = `NS_OFF;
wire w_Switch_2;
reg r_Switch_2 = `NS_OFF;
wire w_Switch_3;
reg r_Switch_3 = `NS_OFF;
wire w_Switch_4;
reg r_Switch_4 = `NS_OFF;
localparam TOT_DEBOUNCE_CLICK = 250000; // 10 ms at 25 MHz
`NS_DECLARE_GLB_LINK(gch0)
assign gch0_clk = i_clk;
assign gch0_reset = reset;
`NS_DEBOUNCER_DBG_BUT(gch0, 1)
`NS_DEBOUNCER_DBG_BUT(gch0, 2)
`NS_DEBOUNCER_DBG_BUT(gch0, 3)
`NS_DEBOUNCER_DBG_BUT(gch0, 4)
wire w_Segment1_A;
wire w_Segment1_B;
wire w_Segment1_C;
wire w_Segment1_D;
wire w_Segment1_E;
wire w_Segment1_F;
wire w_Segment1_G;
wire w_Segment2_A;
wire w_Segment2_B;
wire w_Segment2_C;
wire w_Segment2_D;
wire w_Segment2_E;
wire w_Segment2_F;
wire w_Segment2_G;
localparam CLK_WDH = 17;
localparam CLK_IDX_WDH = 2;
reg [CLK_WDH-1:0] lim_clks_arr [6:0]; // 2, 3, 5, 7, 11, 13, 17
reg [CLK_IDX_WDH:0] lims_idxs [3:0];
reg lims_idxs_inited = 0;
reg clk_lims_inited = 0;
`NS_DECLARE_DBG_CLK(kl0, 0, 17'b00000000000000010) // 2
`NS_DECLARE_DBG_CLK(kl1, 1, 2) // 3
`NS_DECLARE_DBG_CLK(kl2, 2, 2) // 5
`NS_DECLARE_DBG_CLK(kl3, 3, 2) // 7
reg [3:0] changing_clks = 0;
always @(posedge i_clk)
begin
if(changing_clks == 0) begin
`NS_INC_DBG_CLK(kl0, i_clk)
`NS_INC_DBG_CLK(kl1, i_clk)
`NS_INC_DBG_CLK(kl2, i_clk)
`NS_INC_DBG_CLK(kl3, i_clk)
end
end
always @(posedge i_clk)
begin
if(! clk_lims_inited) begin
clk_lims_inited <= 1;
lim_clks_arr[0] <= 17'b00000000000000010; // 2
lim_clks_arr[1] <= 17'b00000000000000100; // 3
lim_clks_arr[2] <= 17'b00000000000010000; // 5
lim_clks_arr[3] <= 17'b00000000001000000; // 7
lim_clks_arr[4] <= 17'b00000010000000000; // 11
lim_clks_arr[5] <= 17'b00001000000000000; // 13
lim_clks_arr[6] <= 17'b10000000000000000; // 17
end
end
`NS_DECLARE_DBG_LINK(dbg0)
assign dbg0_case = 0;
assign dbg0_doit = 0;
// LNK_0
`NS_DECLARE_PAKIO_LINK(lnk_0)
// LNK_1_
`NS_DECLARE_LINK(lnk_1)
// LNK_2
`NS_DECLARE_LINK(lnk_2)
pakout
gt_01 (
`NS_INSTA_GLB_CHNL_VALS(gch, clk_kl2, reset, ready),
// out0
`NS_INSTA_SND_PAKIO_CHNL(snd0, lnk_0),
// in0
`NS_INSTA_RCV_CHNL(rcv0, lnk_1)
);
pakout_io #(.MIN_ADDR(`NS_TEST_MIN_ADDR), .MAX_ADDR(`NS_TEST_MAX_ADDR))
gt_02 (
.src_clk(clk_kl0),
.snk_clk(clk_kl1),
.reset(reset),
// SRC0
`NS_INSTA_SND_CHNL(o0, lnk_1),
// SNK0
`NS_INSTA_RCV_PAKIO_CHNL(i0, lnk_0),
`NS_INSTA_DBG_CHNL(dbg, dbg0, i_clk)
);
localparam TOT_TM_LIMS = 250000;
reg [$clog2(TOT_TM_LIMS):0] cnt_inc_lims = 0;
always @(posedge i_clk)
begin
if(cnt_inc_lims == TOT_TM_LIMS) begin
cnt_inc_lims <= 1;
`NS_INC_DBG_IDXS_ARR(lims_idxs, 6)
`NS_SET_LIM_DBG_CLK(kl0, lim_clks_arr, lims_idxs)
`NS_SET_LIM_DBG_CLK(kl1, lim_clks_arr, lims_idxs)
`NS_SET_LIM_DBG_CLK(kl2, lim_clks_arr, lims_idxs)
`NS_SET_LIM_DBG_CLK(kl3, lim_clks_arr, lims_idxs)
end
else begin
cnt_inc_lims <= cnt_inc_lims + 1;
end
end
/*
`NS_DECLARE_REG_DBG(dd1)
wire sw2_ON = ((w_Switch_2 == `NS_ON) && (r_Switch_2 == `NS_OFF));
wire sw2_OFF = ((w_Switch_2 == `NS_OFF) && (r_Switch_2 == `NS_ON));
always @(posedge i_clk)
begin
r_Switch_2 <= w_Switch_2;
if(sw2_ON)
begin
dd1_disp0 <= dbg0_disp0;
dd1_disp1 <= dbg0_disp1;
end
end
bin_to_disp disp_0(
.i_Clk(i_clk),
.i_Binary_Num(dd1_disp0),
.o_Segment_A(w_Segment1_A),
.o_Segment_B(w_Segment1_B),
.o_Segment_C(w_Segment1_C),
.o_Segment_D(w_Segment1_D),
.o_Segment_E(w_Segment1_E),
.o_Segment_F(w_Segment1_F),
.o_Segment_G(w_Segment1_G)
);
bin_to_disp disp1(
.i_Clk(i_clk),
.i_Binary_Num(dd1_disp1),
.o_Segment_A(w_Segment2_A),
.o_Segment_B(w_Segment2_B),
.o_Segment_C(w_Segment2_C),
.o_Segment_D(w_Segment2_D),
.o_Segment_E(w_Segment2_E),
.o_Segment_F(w_Segment2_F),
.o_Segment_G(w_Segment2_G)
);
assign o_Segment1_A = ~w_Segment1_A;
assign o_Segment1_B = ~w_Segment1_B;
assign o_Segment1_C = ~w_Segment1_C;
assign o_Segment1_D = ~w_Segment1_D;
assign o_Segment1_E = ~w_Segment1_E;
assign o_Segment1_F = ~w_Segment1_F;
assign o_Segment1_G = ~w_Segment1_G;
assign o_Segment2_A = ~w_Segment2_A;
assign o_Segment2_B = ~w_Segment2_B;
assign o_Segment2_C = ~w_Segment2_C;
assign o_Segment2_D = ~w_Segment2_D;
assign o_Segment2_E = ~w_Segment2_E;
assign o_Segment2_F = ~w_Segment2_F;
assign o_Segment2_G = ~w_Segment2_G;
*/
assign o_Segment1_A = ~(lims_idxs[0][0]);
assign o_Segment1_B = ~(lims_idxs[0][1]);
assign o_Segment1_C = ~(lims_idxs[0][2]);
assign o_Segment1_D = ~(lims_idxs[1][0]);
assign o_Segment1_E = ~(lims_idxs[1][1]);
assign o_Segment1_F = ~(lims_idxs[1][2]);
assign o_Segment1_G = 1;
assign o_Segment2_A = ~(lims_idxs[2][0]);
assign o_Segment2_B = ~(lims_idxs[2][1]);
assign o_Segment2_C = ~(lims_idxs[2][2]);
assign o_Segment2_D = ~(lims_idxs[3][0]);
assign o_Segment2_E = ~(lims_idxs[3][1]);
assign o_Segment2_F = ~(lims_idxs[3][2]);
assign o_Segment2_G = 1;
assign o_LED_1 = dbg0_leds[0:0];
assign o_LED_2 = dbg0_leds[1:1];
assign o_LED_3 = dbg0_leds[2:2];
assign o_LED_4 = dbg0_leds[3:3];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t, i, x; cin >> t; while (t--) { int angle; cin >> angle; x = 360 % (180 - angle); if (x == 0) { cout << YES << endl; } else cout << NO << endl; } return 0; } |
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