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// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
write_strobe,
strobe_ena_hr_clock_in,
capture_strobe_tracking,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
lfifo_rdata_en,
lfifo_rdata_en_full,
lfifo_rd_latency,
lfifo_reset_n,
lfifo_rdata_valid,
vfifo_qvld,
vfifo_inc_wr_ptr,
vfifo_reset_n,
rfifo_reset_n,
dll_delayctrl_in
);
input [7-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input [3:0] write_strobe;
input strobe_ena_hr_clock_in;
output capture_strobe_tracking;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [16-1:0] parallelterminationcontrol_in;
input [16-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
input [2-1:0] lfifo_rdata_en;
input [2-1:0] lfifo_rdata_en_full;
input [4:0] lfifo_rd_latency;
input lfifo_reset_n;
output lfifo_rdata_valid;
input [2-1:0] vfifo_qvld;
input [2-1:0] vfifo_inc_wr_ptr;
input vfifo_reset_n;
input rfifo_reset_n;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.write_strobe(write_strobe),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.capture_strobe_tracking (capture_strobe_tracking),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.lfifo_rdata_en(lfifo_rdata_en),
.lfifo_rdata_en_full(lfifo_rdata_en_full),
.lfifo_rd_latency(lfifo_rd_latency),
.lfifo_reset_n(lfifo_reset_n),
.lfifo_rdata_valid(lfifo_rdata_valid),
.vfifo_qvld(vfifo_qvld),
.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
.vfifo_reset_n(vfifo_reset_n),
.rfifo_reset_n(rfifo_reset_n),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 400.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "2500 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.DLL_WIDTH = 7;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "false";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
defparam altdq_dqs2_inst.HHP_HPS = "true";
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4B_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__NAND4B_FUNCTIONAL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nand4b (
Y ,
A_N,
B ,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, D, C, B, not0_out);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4B_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int n, k, p; int dp[105][55]; int modd(int x) { if (x < 0) return x + p; else if (x >= p) return x - p; return x; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); cerr.tie(nullptr); cin >> n >> k >> p; memset(dp, 128, sizeof dp); dp[0][0] = 0; int z = 0; for (int i = 1; i <= n; i++) { int x; cin >> x; z = (z + x) % p; vector<int> vz(55, -2e9); for (int l = 0; l < k; l++) { for (int j = 0; j < p; j++) { vz[l + 1] = max(vz[l + 1], dp[j][l] + modd(z - j + p)); } } for (int i = 0; i < 55; i++) dp[z][i] = max(dp[z][i], vz[i]); } cout << dp[z][k] << n ; } |
#include <bits/stdc++.h> using namespace std; void abc() { cout << endl; } template <typename T, typename... U> void abc(T a, U... b) { cout << a << , abc(b...); } template <typename T> void printv(T l, T r) { while (l != r) cout << *l << n [++l == r]; } template <typename A, typename B> istream& operator>>(istream& o, pair<A, B>& a) { return o >> a.first >> a.second; } template <typename A, typename B> ostream& operator<<(ostream& o, pair<A, B> a) { return o << ( << a.first << , << a.second << ) ; } template <typename T> ostream& operator<<(ostream& o, vector<T> a) { bool is = false; for (T i : a) { o << (is ? : { ), is = true, o << i; } return o << } ; } template <typename T> struct vv : vector<vector<T>> { vv(int n, int m, T v) : vector<vector<T>>(n, vector<T>(m, v)) {} vv() {} }; template <typename T> struct vvv : vector<vv<T>> { vvv(int n, int m, int k, T v) : vector<vv<T>>(n, vv<T>(m, k, v)) {} vvv() {} }; const int mod = 1e9 + 7, N = 200001, logN = 20, K = 80000; long long int modpow(long long int a, int b) { long long int ans = 1; for (; b; b >>= 1, a = a * a % mod) { if (b & 1) ans = ans * a % mod; } return ans; } int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> a(n); vv<long long int> inv(n, n, 0); for (int i = 0; i < n; ++i) { cin >> a[i]; } for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) { inv[i][j] = modpow((a[i] + a[j]) % mod, mod - 2); } vv<long long int> pre(1 << n, n, 1); vv<long long int> pw(n, n + 1, 1); for (int i = 0; i < n; ++i) { for (int j = 1; j <= n; ++j) { pw[i][j] = pw[i][j - 1] * a[i] % mod; } } for (int i = 0; i < n; ++i) { for (int s = 0; s < 1 << n; ++s) { for (int j = 0; j < n; ++j) if (s >> j & 1) { pre[s][i] = pre[s][i] * inv[i][j] % mod; } } } vector<long long int> dp(1 << n, 1); for (int s = 0; s < 1 << n; ++s) { for (int t = s ^ (s & (-s)); t > 0; t = (t - 1) & s) { long long int res = dp[t]; for (int j = 0; j < n; ++j) if (t >> j & 1) { res = res * pre[t ^ s][j] % mod * pw[j][__builtin_popcount(t ^ s)] % mod; } dp[s] -= res; if (dp[s] < 0) dp[s] += mod; } } long long int ans = 0; for (int s = 0; s < 1 << n; ++s) { int k = __builtin_popcount(s); long long int res = dp[s]; for (int i = 0; i < n; ++i) if (s >> i & 1) { for (int j = 0; j < n; ++j) if (~s >> j & 1) { res = res * a[i] % mod * inv[i][j] % mod; } } ans += res * k % mod; if (ans >= mod) ans -= mod; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; bool vis[305][305]; string s[305]; int len[305][305]; int d[305]; int hs[305][305]; int n; const int mod = 9e8 + 7; int qpow(int x, int y) { long long ret = 1; long long now = x; while (y) { if (y & 1) ret = ret * now % mod; now = now * now % mod; y >>= 1; } return ret; } void init() { memset(vis, false, sizeof(vis)); for (int i = 1; i <= n; i++) { d[i] = 0; len[i][0] = s[i].size(); for (int j = 0; j < s[i].size(); j++) { d[i] = (d[i] * 233LL + s[i][j] - a + 1) % mod; } } for (int i = 1; i <= n; i++) { hs[i][0] = d[i]; for (int j = 1; j + i <= n; j++) { len[i][j] = len[i + j][0] + len[i][j - 1]; hs[i][j] = (1LL * hs[i][j - 1] * 2333LL + d[i + j]) % mod; } } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) cin >> s[i]; init(); int ans = 0; for (int i = 1; i <= n; i++) { int ls = 0; for (int j = 0; i + j <= n; j++) { ls += len[i + j][0]; int nx = i + j + 1; int cnt = 1; while (nx + j <= n) { if (hs[i][j] == hs[nx][j] && len[i][j] == len[nx][j]) { cnt++; nx += j + 1; } else { nx++; } } if (cnt > 1) ans = max(ans, (ls - 1) * cnt); } } ans = n - 1 - ans; for (int i = 1; i <= n; i++) ans += len[i][0]; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { int cases; cin >> cases; while (cases--) { int length, target; cin >> length >> target; vector<vector<int>> BGR(3, vector<int>(length, 0)); string inp; cin >> inp; for (size_t i = 0, tok; i < inp.length(); ++i) { if (inp[i] == B ) tok = 0; else if (inp[i] == G ) tok = 1; else tok = 2; BGR[(tok + i) % 3][i] = 1; } int ans = target; for (auto x : BGR) { size_t j = 0; int init = target; for (; j < target; ++j) init -= x[j]; ans = init < ans ? init : ans; for (size_t i = 0; j < x.size(); ++i, ++j) { init += x[i] - x[j]; ans = init < ans ? init : ans; } } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct rect { int x1, y1, x2, y2; }; struct rect a[40001], c[40001]; int b[40001]; int w, h, n, nr; void enter() { scanf( %d%d%d , &w, &h, &n); nr = 1; a[1].x1 = 0; a[1].y1 = 0; a[1].x2 = w; a[1].y2 = h; } void call1(int x1, int y1, int x2, int y2) { int i; for (i = 1; i <= nr; i++) if ((a[i].x1 < x1) && (x2 < a[i].x2) && (a[i].y1 == y1) && (a[i].y2 == y2)) break; nr++; a[nr] = a[i]; a[i].x2 = x2; a[nr].x1 = x2; } void call2(int x1, int y1, int x2, int y2) { int i; for (i = 1; i <= nr; i++) if ((a[i].y1 < y1) && (y2 < a[i].y2) && (a[i].x1 == x1) && (a[i].x2 == x2)) break; nr++; a[nr] = a[i]; a[i].y2 = y2; a[nr].y1 = y2; } void solve() { int x1, y1, x2, y2, t; for (int i = 1; i <= n; i++) { scanf( %d%d%d%d , &x1, &y1, &x2, &y2); c[i].x1 = x1; c[i].x2 = x2; c[i].y1 = y1; c[i].y2 = y2; b[i] = 1; } for (int i = 1; i <= n; i++) { t = 0; for (int j = 1; j <= n; j++) if ((b[j] == 1) && (t == 0)) { x1 = c[j].x1; x2 = c[j].x2; y1 = c[j].y1; y2 = c[j].y2; for (int k = 1; k <= nr; k++) if (((y1 == y2) && (a[k].y1 < y1) && (y2 < a[k].y2) && (a[k].x1 == x1) && (a[k].x2 == x2)) || ((x1 == x2) && (a[k].x1 < x1) && (x2 < a[k].x2) && (a[k].y1 == y1) && (a[k].y2 == y2))) t = j; } b[t] = 0; x1 = c[t].x1; x2 = c[t].x2; y1 = c[t].y1; y2 = c[t].y2; if (x1 == x2) call1(x1, y1, x2, y2); else call2(x1, y1, x2, y2); } for (int i = 1; i <= w * h; i++) b[i] = 0; for (int i = 1; i <= nr; i++) b[(a[i].x2 - a[i].x1) * (a[i].y2 - a[i].y1)]++; } void print() { for (int i = 1; i <= w * h; i++) for (int j = 1; j <= b[i]; j++) printf( %d , i); } int main() { enter(); solve(); print(); return (0); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, r; cin >> n >> m >> r; int s[n], b[m]; for (int i = 0; i < n; i++) cin >> s[i]; for (int i = 0; i < m; i++) cin >> b[i]; sort(s, s + n); sort(b, b + m); int x = r / s[0]; int remind = r % s[0]; int y = x * b[m - 1]; if (y + remind > r) cout << y + remind; else cout << r; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2I_SYMBOL_V
`define SKY130_FD_SC_MS__MUX2I_SYMBOL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux2i (
//# {{data|Data Signals}}
input A0,
input A1,
output Y ,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2I_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DECAP_8_V
`define SKY130_FD_SC_HDLL__DECAP_8_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__decap_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__decap_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DECAP_8_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: altera_primitive_sync_fifo_showahead_97in_97out_32depth.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_primitive_sync_fifo_showahead_97in_97out_32depth (
aclr,
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [96:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [96:0] q;
output [4:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [96:0] sub_wire2;
wire [4:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [96:0] q = sub_wire2[96:0];
wire [4:0] usedw = sub_wire3[4:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.sclr (sclr),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.usedw (sub_wire3),
.almost_empty (),
.almost_full (),
.eccstatus ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Cyclone V",
scfifo_component.lpm_numwords = 32,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 97,
scfifo_component.lpm_widthu = 5,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "97"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "97"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "97"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 97 0 INPUT NODEFVAL "data[96..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 97 0 OUTPUT NODEFVAL "q[96..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: usedw 0 0 5 0 OUTPUT NODEFVAL "usedw[4..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 97 0 data 0 0 97 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 97 0 @q 0 0 97 0
// Retrieval info: CONNECT: usedw 0 0 5 0 @usedw 0 0 5 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_showahead_97in_97out_32depth.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_showahead_97in_97out_32depth.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_showahead_97in_97out_32depth.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_showahead_97in_97out_32depth.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_showahead_97in_97out_32depth_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_primitive_sync_fifo_showahead_97in_97out_32depth_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
module radio_controller_TxTiming
(
clk,
reset,
Tx_swEnable,
TxGain_target,
TxGain_rampGainStep,
TxGain_rampTimeStep,
dly_hwTxEn,
dly_TxStart,
dly_PowerAmpEn,
dly_RampGain,
hw_TxEn,
hw_TxGain,
hw_PAEn,
hw_TxStart
);
input clk;
input reset;
input Tx_swEnable;
input [0:5] TxGain_target;
input [0:3] TxGain_rampGainStep;
input [0:3] TxGain_rampTimeStep;
input [0:7] dly_hwTxEn;
input [0:11] dly_TxStart;
input [0:7] dly_PowerAmpEn;
input [0:7] dly_RampGain;
output hw_TxEn;
output hw_TxStart;
output hw_PAEn;
output [0:5] hw_TxGain;
reg [0:7] GainRamp_clockEn_counter;
reg [0:7] timing_counter;
reg [0:11] timing_counter_big;
wire [0:6] NewTxGain;
reg [0:6] TxGainBig;
wire AutoGainRampEn;
//The output gain signal is the output of an accumulator, enabled after dly_RampGain clock cycles
//This signal is the input to the accumulator register. TxGainBig has one extra MSB to ease overflow detection
assign NewTxGain = ( (TxGainBig + TxGain_rampGainStep) > TxGain_target) ? TxGain_target : (TxGainBig + TxGain_rampGainStep);
//The hw_TxGain output, which eventually connects to the radio's parallel gain control bus,
// gets the 6 LSB of the internal accumulator value
assign hw_TxGain = TxGainBig[1:6];
//Enable the outputs when the timing counter has excedded the various control thresholds given by the dly_* inputs
// A delay value of 254 will hold the corresponding output high forever
// A delay value of 255 will hold the corresponding output low forever (the counter below never reaches 255)
assign hw_TxEn = (timing_counter > dly_hwTxEn) || dly_hwTxEn == 8'd254;
assign hw_PAEn = (timing_counter > dly_PowerAmpEn) || dly_PowerAmpEn == 8'd254;
//TxStart can have a longer delay, up to 2^12 cycles (probably overkill)
// A delay value of 2^12-2 (4094) will hold TxStart high forever
// A delay value of 2^12-1 (4095) will hold TxStart low forever (timing_counter_big never reaches 4095)
assign hw_TxStart = (timing_counter_big > dly_TxStart) || dly_TxStart == 12'd4094;
//Enable the gain ramp accumulator after the given delay
// A delay value of 254 or 255 will disable the gain ramp, regardless of the ramp parameters
assign AutoGainRampEn = timing_counter > dly_RampGain;
//Instiantiates a counter which runs once the timing counter exceeds the threshold
// for starting the ramping of Tx gains; the counter increments every TxGain_rampTimeStep cycles
always @( posedge clk )
begin
if(reset | ~Tx_swEnable)
TxGainBig <= 0;
else if( AutoGainRampEn & (GainRamp_clockEn_counter==1))
TxGainBig <= NewTxGain;
end
//Instantiate a counter that starts when the software enables Tx mode
// This counter intentionally stops at 253, allowing delay values of 254 and 255 to have other uses
always @( posedge clk )
begin
if(reset | ~Tx_swEnable)
timing_counter <= 0;
else if(Tx_swEnable & timing_counter < 254)
timing_counter <= timing_counter + 1;
end
//Instantiate a counter that starts when the software enables Tx mode
// This counter intentionally stops at 4093, allowing delay values of 4094 and 4095 to have other uses
always @( posedge clk )
begin
if(reset | ~Tx_swEnable)
timing_counter_big <= 0;
else if(Tx_swEnable & timing_counter_big < 4094)
timing_counter_big <= timing_counter_big + 1;
end
//Instantiate a counter used to drive the clock enable of the gain ramp counter above
always @( posedge clk )
begin
if(reset | GainRamp_clockEn_counter == TxGain_rampTimeStep)
GainRamp_clockEn_counter <= 0;
else
GainRamp_clockEn_counter <= GainRamp_clockEn_counter + 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISOLATCH_TB_V
`define SKY130_FD_SC_LP__INPUTISOLATCH_TB_V
/**
* inputisolatch: Latching input isolator with inverted enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inputisolatch.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SLEEP_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 SLEEP_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP_B = 1'bx;
#600 D = 1'bx;
end
sky130_fd_sc_lp__inputisolatch dut (.D(D), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISOLATCH_TB_V
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
Require Export IVT.
(**
* Roots of polynomials of odd degree *)
Section CPoly_Big.
(**
** Monic polynomials are positive near infinity
%\begin{convention}% Let [R] be an ordered field.
%\end{convention}%
*)
Variable R : COrdField.
(* begin hide *)
Let RX := (cpoly R).
(* end hide *)
Lemma Cbigger : forall x y : R, {z : R | x [<=] z | y [<=] z}.
Proof.
intros.
elim (less_cotransitive_unfolded _ x (x[+][1]) (less_plusOne _ _) y); intro.
exists (y[+][1]); apply less_leEq.
apply less_leEq_trans with y. auto. apply less_leEq; apply less_plusOne.
apply less_plusOne.
exists (x[+][1]); apply less_leEq.
apply less_plusOne.
auto.
Qed.
Lemma Ccpoly_big : forall (p : RX) n, 0 < n ->
monic n p -> forall Y, {X : R | forall x, X [<=] x -> Y [<=] p ! x}.
Proof.
intro. elim p.
unfold monic in |- *. simpl in |- *. intros. elim H0. intros H1 H2.
cut ([0][~=] ([1]:R)). intro. elim (H3 H1).
apply ap_imp_neq. apply ap_symmetric_unfolded. apply ring_non_triv.
intros c q. intros H n H0 H1 Y.
elim (O_or_S n); intro y. elim y. intro m. intro y0.
rewrite <- y0 in H1.
elim (zerop m); intro y1. simpl in |- *.
exists (Y[-]c). intros.
rewrite y1 in H1.
apply shift_leEq_plus'.
cut (q ! x [=] [1]). intro.
astepr (x[*][1]). astepr x. auto.
apply monic_one with c. auto.
cut (monic m q). intro H2.
elim (Cbigger [0] (Y[-]c)). intro Y'. intros H3 H4.
elim (H m y1 H2 Y'). intro X'. intro H5.
simpl in |- *.
elim (Cbigger [1] X'). intro X. intros H6 H7.
exists X. intros.
apply shift_leEq_plus'.
apply leEq_transitive with ([1][*]Y').
astepr Y'. auto.
apply mult_resp_leEq_both; auto.
apply less_leEq. apply pos_one.
apply leEq_transitive with X; auto.
change (Y' [<=] q ! x) in |- *.
apply H5.
apply leEq_transitive with X; auto.
apply monic_cpoly_linear with c; auto.
rewrite <- y in H0.
elim (lt_irrefl _ H0).
Qed.
Lemma cpoly_pos : forall (p : RX) n, 0 < n -> monic n p -> {x : R | [0] [<=] p ! x}.
Proof.
intros.
elim (Ccpoly_big _ _ H H0 [0]). intros x H1.
exists (x[+][1]).
apply H1. apply less_leEq. apply less_plusOne.
Qed.
Lemma Ccpoly_pos' : forall (p : RX) a n, 0 < n -> monic n p -> {x : R | a [<] x | [0] [<=] p ! x}.
Proof.
intros.
elim (Ccpoly_big _ _ H H0 [0]). intro x'. intro H1.
elim (Cbigger (a[+][1]) x'). intro x. intros.
exists x; auto.
apply less_leEq_trans with (a[+][1]).
apply less_plusOne. auto.
Qed.
End CPoly_Big.
Section Flip_Poly.
(**
** Flipping a polynomial
%\begin{convention}% Let [R] be a ring.
%\end{convention}%
*)
Variable R : CRing.
Add Ring R: (CRing_Ring R).
(* begin hide *)
Let RX := (cpoly R).
(* end hide *)
Fixpoint flip (p : RX) : RX :=
match p with
| cpoly_zero => cpoly_zero _
| cpoly_linear c q => cpoly_inv _ (cpoly_linear _ c (flip q))
end.
Lemma flip_poly : forall (p : RX) x, (flip p) ! x [=] [--]p ! ( [--]x).
Proof.
intro p. elim p.
intros. simpl in |- *. algebra.
intros c q. intros.
change ( [--]c[+]x[*] (cpoly_inv _ (flip q)) ! x [=] [--] (c[+][--]x[*]q ! ( [--]x))) in |- *.
astepl ( [--]c[+]x[*][--] (flip q) ! x).
astepl ( [--]c[+]x[*][--][--]q ! ( [--]x)).
ring.
Qed.
Lemma flip_coefficient : forall (p : RX) i,
nth_coeff i (flip p) [=] [--] ( [--][1][^]i) [*]nth_coeff i p.
Proof.
intro p. elim p.
simpl in |- *. algebra.
intros c q. intros.
elim i. simpl in |- *. ring.
intros. simpl in |- *.
astepl ( [--] (nth_coeff n (flip q))).
astepl ( [--] ( [--] ( [--][1][^]n) [*]nth_coeff n q)).
simpl in |- *. ring.
Qed.
Hint Resolve flip_coefficient: algebra.
Lemma flip_odd : forall (p : RX) n, odd n -> monic n p -> monic n (flip p).
Proof.
unfold monic in |- *. unfold degree_le in |- *.
intros.
elim H0. clear H0. intros.
split.
astepl ( [--] ( [--][1][^]n) [*]nth_coeff n p).
astepl ( [--][--] ([1][^]n) [*]nth_coeff n p).
astepl ([1][^]n[*]nth_coeff n p).
astepl ([1][*]nth_coeff n p).
Step_final ([1][*] ([1]:R)).
intros.
astepl ( [--] ( [--][1][^]m) [*]nth_coeff m p).
Step_final ( [--] ( [--][1][^]m) [*] ([0]:R)).
Qed.
End Flip_Poly.
Hint Resolve flip_poly: algebra.
Section OddPoly_Signs.
(**
** Sign of a polynomial of odd degree
%\begin{convention}% Let [R] be an ordered field.
%\end{convention}%
*)
Variable R : COrdField.
(* begin hide *)
Let RX := (cpoly R).
(* end hide *)
Lemma oddpoly_pos : forall (p : RX) n, odd n -> monic n p -> {x : R | [0] [<=] p ! x}.
Proof.
intros.
apply cpoly_pos with n; auto.
elim H. intros. auto with arith.
Qed.
Lemma oddpoly_pos' : forall (p : RX) a n,
odd n -> monic n p -> {x : R | a [<] x | [0] [<=] p ! x}.
Proof.
intros.
elim (Ccpoly_pos' _ p a n). intros x H1 H2.
exists x; assumption.
elim H; auto with arith.
assumption.
Qed.
Lemma oddpoly_neg : forall (p : RX) n, odd n -> monic n p -> {x : R | p ! x [<=] [0]}.
Proof.
intros.
elim (oddpoly_pos _ _ H (flip_odd _ _ _ H H0)). intro x. intros.
exists ( [--]x).
astepl ( [--][--]p ! ( [--]x)). astepr ( [--] ([0]:R)).
apply inv_resp_leEq.
astepr (flip _ p) ! x. auto.
Qed.
End OddPoly_Signs.
Section Poly_Norm.
(**
** The norm of a polynomial
%\begin{convention}% Let [R] be a field, and [RX] the polynomials over
this field.
%\end{convention}%
*)
Variable R : CField.
(* begin hide *)
Let RX := cpoly_cring R.
(* end hide *)
Lemma poly_norm_aux : forall (p : RX) n, degree n p -> nth_coeff n p [#] [0].
Proof.
unfold degree in |- *. intros p n H.
elim H. auto.
Qed.
Definition poly_norm p n H := _C_ ([1][/] _[//]poly_norm_aux p n H) [*]p.
Lemma poly_norm_monic : forall p n H, monic n (poly_norm p n H).
Proof.
unfold poly_norm in |- *. unfold monic in |- *. unfold degree in |- *. unfold degree_le in |- *. intros.
elim H. intros H0 H1.
split.
Step_final (([1][/] nth_coeff n p[//]poly_norm_aux p n (pair H0 H1)) [*] nth_coeff n p).
intros.
astepl (([1][/] nth_coeff n p[//]poly_norm_aux p n (pair H0 H1)) [*] nth_coeff m p).
Step_final (([1][/] nth_coeff n p[//]poly_norm_aux p n H) [*][0]).
Qed.
Lemma poly_norm_apply : forall p n H x, (poly_norm p n H) ! x [=] [0] -> p ! x [=] [0].
Proof.
unfold poly_norm in |- *. intros.
apply mult_cancel_lft with ([1][/] nth_coeff n p[//]poly_norm_aux p n H).
apply div_resp_ap_zero_rev. apply ring_non_triv.
astepl ((_C_ ([1][/] nth_coeff n p[//]poly_norm_aux p n H)) ! x[*]p ! x).
astepl (_C_ ([1][/] nth_coeff n p[//]poly_norm_aux p n H) [*]p) ! x.
Step_final ([0]:R).
Qed.
End Poly_Norm.
Section OddPoly_Root.
(**
** Roots of polynomials of odd degree
Polynomials of odd degree over the reals always have a root. *)
Lemma oddpoly_root' : forall f n, odd n -> monic n f -> {x : IR | f ! x [=] [0]}.
Proof.
intros.
elim (oddpoly_neg _ f n); auto. intro a. intro H1.
elim (oddpoly_pos' _ f a n); auto. intro b. intros H2 H3.
cut {x : IR | a [<=] x /\ x [<=] b /\ f ! x [=] [0]}.
intro H4.
elim H4. clear H4. intros x H4.
elim H4. clear H4. intros H4 H5.
elim H5. clear H5. intros.
exists x. auto.
apply Civt_poly; auto.
apply monic_apzero with n; auto.
Qed.
Lemma oddpoly_root : forall f n, odd n -> degree n f -> {x : IR | f ! x [=] [0]}.
Proof.
intros f n H H0.
elim (oddpoly_root' (poly_norm _ f n H0) n); auto.
intros. exists x.
apply poly_norm_apply with n H0; auto.
apply poly_norm_monic; auto.
Qed.
Lemma realpolyn_oddhaszero : forall f, odd_cpoly _ f -> {x : IR | f ! x [=] [0]}.
Proof.
unfold odd_cpoly in |- *.
intros f H.
elim H. clear H. intro n. intros H H0.
cut (odd n).
intro.
elim (oddpoly_root f n H1 H0). intros. exists x. auto.
apply Codd_to.
assumption.
Qed.
End OddPoly_Root.
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
write_strobe,
strobe_ena_hr_clock_in,
capture_strobe_tracking,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
lfifo_rdata_en,
lfifo_rdata_en_full,
lfifo_rd_latency,
lfifo_reset_n,
lfifo_rdata_valid,
vfifo_qvld,
vfifo_inc_wr_ptr,
vfifo_reset_n,
rfifo_reset_n,
dll_delayctrl_in
);
input [7-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input [3:0] write_strobe;
input strobe_ena_hr_clock_in;
output capture_strobe_tracking;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [16-1:0] parallelterminationcontrol_in;
input [16-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
input [2-1:0] lfifo_rdata_en;
input [2-1:0] lfifo_rdata_en_full;
input [4:0] lfifo_rd_latency;
input lfifo_reset_n;
output lfifo_rdata_valid;
input [2-1:0] vfifo_qvld;
input [2-1:0] vfifo_inc_wr_ptr;
input vfifo_reset_n;
input rfifo_reset_n;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.write_strobe(write_strobe),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.capture_strobe_tracking (capture_strobe_tracking),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.lfifo_rdata_en(lfifo_rdata_en),
.lfifo_rdata_en_full(lfifo_rdata_en_full),
.lfifo_rd_latency(lfifo_rd_latency),
.lfifo_reset_n(lfifo_reset_n),
.lfifo_rdata_valid(lfifo_rdata_valid),
.vfifo_qvld(vfifo_qvld),
.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
.vfifo_reset_n(vfifo_reset_n),
.rfifo_reset_n(rfifo_reset_n),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 300.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "3333 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.DLL_WIDTH = 7;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "false";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
defparam altdq_dqs2_inst.HHP_HPS = "true";
endmodule
|
#include <bits/stdc++.h> using namespace std; int nor[200100 * 2], n, t, m, a[200100], b[200100], sola, solb, sol, pcta, pctb; int main() { cin >> n; nor[++t] = 0; for (int i = 1; i <= n; ++i) { cin >> a[i]; nor[++t] = a[i]; } cin >> m; for (int i = 1; i <= m; ++i) { cin >> b[i]; nor[++t] = b[i]; } sort(nor + 1, nor + t + 1); sort(a + 1, a + n + 1); sort(b + 1, b + m + 1); nor[++t] = max(a[n], b[n]) + 1; sol = -(1 << 30); for (int i = 1; i <= t; ++i) { int mij; int st = 1, dr = n; while (st <= dr) { mij = (st + dr) >> 1; if (a[mij] <= nor[i]) st = mij + 1; else dr = mij - 1; } pcta = (st - 1) * 2 + (n - (st - 1)) * 3; st = 1, dr = m; while (st <= dr) { mij = (st + dr) >> 1; if (b[mij] <= nor[i]) st = mij + 1; else dr = mij - 1; } pctb = (st - 1) * 2 + (m - (st - 1)) * 3; if (pcta - pctb > sol) { sol = pcta - pctb; sola = pcta; solb = pctb; } else if (pcta - pctb == sol && pcta > sola) { sola = pcta; solb = pctb; } } cout << sola << : << solb; return 0; } |
//
// Copyright (c) 2000 Stephen Williams ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// Check support for event lists with named events.
//
module main ();
reg flag1, flag2, flag12;
event event_1, event_2;
always @ event_1 flag1 = ~flag1;
always @ event_2 flag2 = ~flag2;
always @(event_1 or event_2) flag12 = ~flag12;
initial begin
flag1 = 0;
flag2 = 0;
flag12 = 0;
#1 -> event_1;
#1
if (flag1 !== 1) begin
$display("FAILED -- event_1 didn't trigger flag1");
$finish;
end
if (flag2 !== 0) begin
$display("FAILED -- event_1 DID trigger flag2");
$finish;
end
if (flag12 !== 1) begin
$display("FAILED -- event_1 didn't trigger flag12");
$finish;
end
flag1 = 0;
flag2 = 0;
flag12 = 0;
#1 -> event_2;
#1
if (flag1 !== 0) begin
$display("FAILED -- event_2 DID trigger flag1");
$finish;
end
if (flag2 !== 1) begin
$display("FAILED -- event_2 didn't trigger flag2");
$finish;
end
if (flag12 !== 1) begin
$display("FAILED -- event_1 didn't trigger flag12");
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.14159265358979323846; const double EPS = 1e-15; const int INF = 1e9 + 7; const long long LINF = 8e18 + 7; const int N = 2e5 + 7; vector<long long> t[4 * N]; int a[N]; long long s[N]; void build(int v, int L, int R) { if (L + 1 == R) { t[v].push_back(s[L]); return; } int M = L + R >> 1; build(v << 1, L, M); build(v << 1 | 1, M, R); t[v].resize(t[v << 1].size() + t[v << 1 | 1].size()); merge(t[v << 1].begin(), t[v << 1].end(), t[v << 1 | 1].begin(), t[v << 1 | 1].end(), t[v].begin()); } int get(int v, int L, int R, int l, int r, long long val) { if (L == l && R == r) { return t[v].end() - upper_bound(t[v].begin(), t[v].end(), val); } int M = L + R >> 1; int ans = 0; if (l < M) { ans += get(v << 1, L, M, l, min(M, r), val); } if (r > M) { ans += get(v << 1 | 1, M, R, max(l, M), r, val); } return ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; long long t; cin >> n >> t; for (int i = 0; i < int(n); ++i) { cin >> a[i]; s[i + 1] = a[i] + s[i]; } build(1, 0, n + 1); long long ans = 0; for (int i = 0; i < int(n); ++i) { ans += get(1, 0, n + 1, 0, i + 1, s[i + 1] - t); } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; void solve() { string s, a = , b; cin >> s; unordered_map<string, int> m; m[s]++; for (int i = s.length() - 1; i >= 0; i--) { a += s[i]; b = a; reverse(b.begin(), b.end()); m[b + s.substr(0, i)]++; } cout << m.size() << endl; } int main() { { solve(); } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize(3) #pragma GCC optimize(2) using namespace std; const int maxn = 510; const int inf32 = 1e9 + 10; const long long inf64 = 1e18 + 10; const int mod = 998244353; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int N; cin >> N; vector<long long> a(N), b(N); for (int i = 0; i < N; ++i) cin >> a[i]; sort(a.begin(), a.end()); for (int i = 0; i < N; ++i) b[i] = a[N - 1] - a[i]; vector<vector<long long>> dp(65, vector<long long>(N + 1, inf64)); vector<vector<int>> sum(N + 1, vector<int>(2)); dp[0][0] = 0; for (int i = 1; i <= 63; ++i) { int current_bit = i - 1; vector<int> p(N); for (int j = 0; j < N; ++j) p[j] = j; sort(p.begin(), p.end(), [&](int& l, int& r) { return b[l] % (1ll << current_bit) < b[r] % (1ll << current_bit); }); for (int j = 0; j <= N; ++j) { for (int k = 0; k < 2; ++k) { sum[j][k] = 0; } } for (int j = 1; j <= N; ++j) { ++sum[j][b[p[j - 1]] >> current_bit & 1]; } for (int j = 1; j <= N; ++j) { for (int k = 0; k < 2; ++k) { sum[j][k] += sum[j - 1][k]; } } for (int j = 0; j <= N; ++j) { int new_carry = sum[N][1] - sum[N - j][1]; int cost = sum[N - j][1] + sum[N][0] - sum[N - j][0]; dp[i][new_carry] = min(dp[i][new_carry], dp[i - 1][j] + cost); new_carry = sum[N][1] - sum[N - j][1] + sum[N][0] - sum[N - j][0] + sum[N - j][1]; cost = sum[N - j][0] + sum[N][1] - sum[N - j][1]; dp[i][new_carry] = min(dp[i][new_carry], dp[i - 1][j] + cost); } } cout << dp[63][0] << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2_FUNCTIONAL_V
`define SKY130_FD_SC_MS__OR2_FUNCTIONAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int MAXN = 9e4; const int INF = 1 << 30; const long long mod = 1e9 + 7; const double eps = 1e-8; int main() { long long a[100] = {0, 4, 10, 20, 35, 56, 83, 116, 155, 198, 244, 292, 341, 390, 439}; long long n; while (cin >> n) if (n <= 14) cout << a[n] << endl; else cout << a[14] + (long long)49 * (n - 14) << endl; } |
//*******************************************************************************************
//Author: Zhiyoong Foo, Yejoong Kim
//Last Modified: Dec 16 2016
//Description: MBus CLK/DATA Swapper
// - Generates Data & Clock Flip Interrupt;
// - Maintains Last seen Clock State
//Update History: Mar 06 2013 - First Commit (Zhiyoong Foo)
// May 21 2016 - Included in MBus r03 (Yejoong Kim)
// Dec 16 2016 - Included in MBus r04 (Yejoong Kim)
//*******************************************************************************************
module flpv3l_mbus_swapper (
//Inputs
input CLK,
input RESETn,
input DATA,
input INT_FLAG_RESETn,
//Outputs
output reg LAST_CLK,
output reg INT_FLAG
);
//Internal Declerations
wire negp_reset;
wire posp_reset;
//Negative Phase Clock Resets
reg pose_negp_clk_0; //Positive Edge
reg nege_negp_clk_1; //Negative Edge
reg pose_negp_clk_2;
reg nege_negp_clk_3;
reg pose_negp_clk_4;
reg nege_negp_clk_5;
wire negp_int; //Negative Phase Interrupt
//Interrupt Reset
wire int_resetn;
assign negp_reset = ~( CLK && RESETn);
//////////////////////////////////////////
// Interrupt Generation
//////////////////////////////////////////
//Negative Phase Clock Resets
always @(posedge DATA or posedge negp_reset) begin
if (negp_reset) begin
pose_negp_clk_0 = 0;
pose_negp_clk_2 = 0;
pose_negp_clk_4 = 0;
end
else begin
pose_negp_clk_0 = 1;
pose_negp_clk_2 = nege_negp_clk_1;
pose_negp_clk_4 = nege_negp_clk_3;
end
end
always @(negedge DATA or posedge negp_reset) begin
if (negp_reset) begin
nege_negp_clk_1 = 0;
nege_negp_clk_3 = 0;
nege_negp_clk_5 = 0;
end
else begin
nege_negp_clk_1 = pose_negp_clk_0;
nege_negp_clk_3 = pose_negp_clk_2;
nege_negp_clk_5 = pose_negp_clk_4;
end
end
//Negative Phase Interrupt Generation
assign negp_int = pose_negp_clk_0 && nege_negp_clk_1 &&
pose_negp_clk_2 && nege_negp_clk_3 &&
pose_negp_clk_4 && nege_negp_clk_5;
//Interrupt Check & Clear
assign int_resetn = RESETn && INT_FLAG_RESETn;
always @(posedge negp_int or negedge int_resetn) begin
if (~int_resetn) INT_FLAG = 0;
else INT_FLAG = 1;
end
//////////////////////////////////////////
// Last Seen Clock
//////////////////////////////////////////
always @(posedge negp_int or negedge RESETn) begin
if (~RESETn) LAST_CLK = 0;
else LAST_CLK = CLK;
end
endmodule // flpv3l_mbus_swapper
|
#include <bits/stdc++.h> using namespace std; double Cnk(int n, int k) { double result = 1; for (int i = 1; i <= k; ++i) { result *= n - k + i; result /= i; } return result; } double Power(int n, int power) { double result = 1; for (int i = 0; i < power; ++i) { result *= n; } return result; } int main() { int n, m; cin >> n >> m; vector<int> a(m); for (int i = 0; i < m; ++i) { cin >> a[i]; } vector<vector<vector<double> > > p(n + 1); for (int i = 0; i <= n; ++i) { p[i].resize(m + 1); for (int j = 0; j <= m; ++j) { p[i][j].assign(n + 1, 0); } } for (int j = 0; j <= m; ++j) { p[0][j][0] = 1; for (int i = 1; i <= n; ++i) { p[0][j][i] = 0; p[i][j][0] = 0; } } for (int i = 0; i <= n; ++i) { for (int k = 0; k <= n; ++k) { if (k == (i + a[0] - 1) / a[0]) { p[i][1][k] = 1; } else { p[i][1][k] = 0; } } } for (int j = 2; j <= m; ++j) { for (int i = 1; i <= n; ++i) { for (int k = 1; k <= n; ++k) { p[i][j][k] = 0; for (int h = a[j - 1] * k - a[j - 1] + 1; (h <= i) && (h < a[j - 1] * (k + 1) - a[j - 1] + 1); ++h) { double sum = 0; for (int l = 0; l <= k; ++l) { sum += p[i - h][j - 1][l]; } p[i][j][k] += Cnk(i, h) * Power(j - 1, i - h) * sum; } for (int h = 0; (h <= i) && (h < k * a[j - 1] - a[j - 1] + 1); ++h) { p[i][j][k] += Cnk(i, h) * Power(j - 1, i - h) * p[i - h][j - 1][k]; } p[i][j][k] /= Power(j, i); } } } double E = 0; for (int i = 0; i <= n; ++i) { E += i * p[n][m][i]; } printf( %.10lf , E); getchar(); getchar(); return 0; } |
`timescale 1 ns / 1 ps
`default_nettype none
`define WIDTH 16
module SB_RAM2048x2(
output [1:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
input [10:0] WADDR,
input [1:0] MASK, WDATA
);
parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
wire [15:0] rd;
SB_RAM40_4K #(
.WRITE_MODE(3),
.READ_MODE(3),
.INIT_0(INIT_0),
.INIT_1(INIT_1),
.INIT_2(INIT_2),
.INIT_3(INIT_3),
.INIT_4(INIT_4),
.INIT_5(INIT_5),
.INIT_6(INIT_6),
.INIT_7(INIT_7),
.INIT_8(INIT_8),
.INIT_9(INIT_9),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.INIT_C(INIT_C),
.INIT_D(INIT_D),
.INIT_E(INIT_E),
.INIT_F(INIT_F)
) _ram (
.RDATA(rd),
.RADDR(RADDR),
.RCLK(RCLK), .RCLKE(RCLKE), .RE(RE),
.WCLK(WCLK), .WCLKE(WCLKE), .WE(WE),
.WADDR(WADDR),
.MASK(16'h0000), .WDATA({4'b0, WDATA[1], 7'b0, WDATA[0], 3'b0}));
assign RDATA[0] = rd[3];
assign RDATA[1] = rd[11];
endmodule
module top(input clk, output D1, output D2, output D3, output D4, output D5,
output TXD, // UART TX
input RXD, // UART RX
output PIOS_00, // flash SCK
input PIOS_01, // flash MISO
output PIOS_02, // flash MOSI
output PIOS_03, // flash CS
inout PIO1_02, // PMOD 1
inout PIO1_03, // PMOD 2
inout PIO1_04, // PMOD 3
inout PIO1_05, // PMOD 4
inout PIO1_06, // PMOD 5
inout PIO1_07, // PMOD 6
inout PIO1_08, // PMOD 7
inout PIO1_09, // PMOD 8
output PIO1_18, // IR TXD
input PIO1_19, // IR RXD
output PIO1_20, // IR SD
input resetq,
);
localparam MHZ = 12;
wire io_rd, io_wr;
wire [15:0] mem_addr;
wire mem_wr;
wire [15:0] dout;
wire [15:0] io_din;
wire [12:0] code_addr;
reg unlocked = 0;
`include "../build/ram.v"
j1 _j1(
.clk(clk),
.resetq(resetq),
.io_rd(io_rd),
.io_wr(io_wr),
.mem_wr(mem_wr),
.dout(dout),
.io_din(io_din),
.mem_addr(mem_addr),
.code_addr(code_addr),
.insn(insn));
/*
// ###### TICKS #########################################
reg [15:0] ticks;
always @(posedge clk)
ticks <= ticks + 16'd1;
*/
// ###### IO SIGNALS ####################################
reg io_wr_, io_rd_;
reg [15:0] dout_;
reg [15:0] io_addr_;
always @(posedge clk) begin
{io_rd_, io_wr_, dout_} <= {io_rd, io_wr, dout};
if (io_rd | io_wr)
io_addr_ <= mem_addr;
end
// ###### PMOD ##########################################
reg [7:0] pmod_dir; // 1:output, 0:input
reg [7:0] pmod_out;
wire [7:0] pmod_in;
SB_IO #(.PIN_TYPE(6'b1010_01)) io0 (.PACKAGE_PIN(PIO1_02), .D_OUT_0(pmod_out[0]), .D_IN_0(pmod_in[0]), .OUTPUT_ENABLE(pmod_dir[0]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io1 (.PACKAGE_PIN(PIO1_03), .D_OUT_0(pmod_out[1]), .D_IN_0(pmod_in[1]), .OUTPUT_ENABLE(pmod_dir[1]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io2 (.PACKAGE_PIN(PIO1_04), .D_OUT_0(pmod_out[2]), .D_IN_0(pmod_in[2]), .OUTPUT_ENABLE(pmod_dir[2]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io3 (.PACKAGE_PIN(PIO1_05), .D_OUT_0(pmod_out[3]), .D_IN_0(pmod_in[3]), .OUTPUT_ENABLE(pmod_dir[3]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io4 (.PACKAGE_PIN(PIO1_06), .D_OUT_0(pmod_out[4]), .D_IN_0(pmod_in[4]), .OUTPUT_ENABLE(pmod_dir[4]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io5 (.PACKAGE_PIN(PIO1_07), .D_OUT_0(pmod_out[5]), .D_IN_0(pmod_in[5]), .OUTPUT_ENABLE(pmod_dir[5]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io6 (.PACKAGE_PIN(PIO1_08), .D_OUT_0(pmod_out[6]), .D_IN_0(pmod_in[6]), .OUTPUT_ENABLE(pmod_dir[6]));
SB_IO #(.PIN_TYPE(6'b1010_01)) io7 (.PACKAGE_PIN(PIO1_09), .D_OUT_0(pmod_out[7]), .D_IN_0(pmod_in[7]), .OUTPUT_ENABLE(pmod_dir[7]));
// ###### UART ##########################################
wire uart0_valid, uart0_busy;
wire [7:0] uart0_data;
wire uart0_wr = io_wr_ & io_addr_[12];
wire uart0_rd = io_rd_ & io_addr_[12];
reg [31:0] uart_baud = 115200;
wire UART0_RX;
buart #(.CLKFREQ(MHZ * )) _uart0 (
.clk(clk),
.resetq(1'b1),
.baud(uart_baud),
.rx(RXD),
.tx(TXD),
.rd(uart0_rd),
.wr(uart0_wr),
.valid(uart0_valid),
.busy(uart0_busy),
.tx_data(dout_[7:0]),
.rx_data(uart0_data));
reg [4:0] PIOS;
assign {PIO1_20, PIO1_18, PIOS_00, PIOS_02, PIOS_03} = PIOS;
reg [4:0] LEDS;
assign {D1,D2,D3,D4,D5} = LEDS;
// ###### IO PORTS ######################################
/* bit READ WRITE
0001 0 PMOD rd PMOD wr
0002 1 PMOD direction
0004 2 LEDS
0008 3 misc.out
1000 12 UART RX UART TX
2000 13 misc.in
*/
assign io_din =
(io_addr_[ 0] ? {8'd0, pmod_in} : 16'd0) |
(io_addr_[ 1] ? {8'd0, pmod_dir} : 16'd0) |
(io_addr_[12] ? {8'd0, uart0_data} : 16'd0) |
(io_addr_[13] ? {12'd0, PIO1_19, PIOS_01, uart0_valid, !uart0_busy} : 16'd0);
always @(posedge clk) begin
if (io_wr_ & io_addr_[0])
pmod_out <= dout_[7:0];
if (io_wr_ & io_addr_[1])
pmod_dir <= dout_[7:0];
if (io_wr_ & io_addr_[2])
LEDS <= dout_[4:0];
if (io_wr_ & io_addr_[3])
PIOS <= dout_[4:0];
end
/*
SB_IO #(
.PIN_TYPE(6'b011001)
) io0 (
.PACKAGE_PIN(PIO1_02));
*/
always @(negedge resetq or posedge clk)
if (!resetq)
unlocked <= 0;
else
unlocked <= unlocked | io_wr_;
endmodule // top
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_32_128x8_dp_be.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 176 10/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ram_32_128x8_dp_be (
address_a,
address_b,
byteena_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [2:0] address_a;
input [4:0] address_b;
input [3:0] byteena_b;
input clock_a;
input clock_b;
input [127:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [127:0] q_a;
output [31:0] q_b;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1024"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "128"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: BYTEENA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "4"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 3 0 INPUT NODEFVAL address_a[2..0]
// Retrieval info: USED_PORT: address_b 0 0 5 0 INPUT NODEFVAL address_b[4..0]
// Retrieval info: USED_PORT: byteena_b 0 0 4 0 INPUT VCC byteena_b[3..0]
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT NODEFVAL clock_a
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
// Retrieval info: USED_PORT: data_a 0 0 128 0 INPUT NODEFVAL data_a[127..0]
// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL data_b[31..0]
// Retrieval info: USED_PORT: q_a 0 0 128 0 OUTPUT NODEFVAL q_a[127..0]
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL q_b[31..0]
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT VCC wren_a
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT VCC wren_b
// Retrieval info: CONNECT: @data_a 0 0 128 0 data_a 0 0 128 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 128 0 @q_a 0 0 128 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: CONNECT: @address_a 0 0 3 0 address_a 0 0 3 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
// Retrieval info: CONNECT: @address_b 0 0 5 0 address_b 0 0 5 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: @byteena_b 0 0 4 0 byteena_b 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_128x8_dp_be.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_128x8_dp_be.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_128x8_dp_be.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_128x8_dp_be.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_128x8_dp_be_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_128x8_dp_be_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_128x8_dp_be_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32_128x8_dp_be_wave*.jpg FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DIODE_TB_V
`define SKY130_FD_SC_HS__DIODE_TB_V
/**
* diode: Antenna tie-down diode.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__diode.v"
module top();
// Inputs are registered
reg DIODE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
DIODE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 DIODE = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 DIODE = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 DIODE = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 DIODE = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 DIODE = 1'bx;
end
sky130_fd_sc_hs__diode dut (.DIODE(DIODE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DIODE_TB_V
|
#include <bits/stdc++.h> using namespace std; struct Pair { long long f, s; Pair() { f = s = 0; } Pair(long long f, long long s) { this->f = f; this->s = s; } }; const int maxn = 36 + 100; Pair d[maxn][maxn]; int pr[maxn][maxn]; long long _10(int); void print(int, int); int main() { int n; string str; cin >> n >> str; for (int i = 0; i <= n; i++) for (int j = 0; j <= n; j++) { if (i) { pr[i][j] = 1; d[i][j].f = d[i - 1][j].f + _10(n - i) * (str[i + j - 1] - 0 ); d[i][j].s = d[i - 1][j].s; } if (j) { if (d[i][j].f + d[i][j].s < d[i][j - 1].f + d[i][j - 1].s + _10(n - j) * (str[i + j - 1] - 0 )) { pr[i][j] = 0; d[i][j].f = d[i][j - 1].f; d[i][j].s = d[i][j - 1].s + _10(n - j) * (str[i + j - 1] - 0 ); } } } print(n, n); cout << endl; } long long _10(int k) { long long res = 1; while (k--) res *= 10; return res; } void print(int i, int j) { if (!i && !j) return; if (pr[i][j]) { print(i - 1, j); cout << H ; return; } print(i, j - 1); cout << M ; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void cmn(T &a, const T &b) { if (b < a) a = b; } template <class T> inline void cmx(T &a, const T &b) { if (b > a) a = b; } const double eps = 1e-9; const long double leps = 1e-14; string inp; const int MN = 1000 + 100; int cnt[MN]; bool mp[MN]; bool mark[MN]; int n, cc; int main(int argc, char *argv[]) { ios_base::sync_with_stdio(false); cin >> inp; n = ((int((inp).size()))); for (int i = 2; i <= n; i++) if (mp[i] == 0) for (int j = 2 * i; j <= n; j += i) mp[j] = 1; for (int i = 0; i < n; i++) cnt[inp[i] - a ]++; for (int i = 2; i <= n; i++) if (i == 2 || mp[i] || (!mp[i] && 2 * i <= n)) cc++, mark[i] = 1; bool fnd = false; cerr << (( cc )) << = << ((cc)) << << n ; for (int i = 0; i < 30; i++) if (cnt[i] >= cc) { fnd = true; for (int j = 0; j < n; j++) if (mark[j + 1]) inp[j] = (i + a ), cnt[i]--; break; } if (!fnd) { cout << NO << n ; return 0; } cout << YES << n ; int p = 0; for (int i = 0; i < n; i++) if (!mark[i + 1]) { while (cnt[p] == 0) p++; inp[i] = (p + a ), cnt[p]--; } cout << inp << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n = 0, m = 0, z = 0, res = 0; cin >> n >> m >> z; for (int i = 1; i <= z; i++) if (i % n == 0 && i % m == 0) res++; cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 2147483647; const double PI = 3.141592653589793; const int N = 40005; map<pair<int, int>, int> mapa; int n, m, k, t, a, b, c, pocz[N], waste[N], r, i; int main() { scanf( %d %d %d %d , &n, &m, &k, &t); for (i = 0; i < n; i++) waste[i] = 0; mapa.clear(); while (k--) { scanf( %d %d , &a, &b); a--; b--; mapa[pair<int, int>(a, b)] = 1; waste[a]++; } pocz[0] = 0; for (i = 1; i < n; i++) pocz[i] = (pocz[i - 1] + m - waste[i - 1]) % 3; while (t--) { scanf( %d %d , &a, &b); a--; b--; if (mapa.count(pair<int, int>(a, b)) > 0) printf( Waste n ); else { c = 0; while (mapa.count(pair<int, int>(a, c)) > 0) c++; r = pocz[a]; while (c != b) { c++; while (mapa.count(pair<int, int>(a, c)) > 0) c++; r = (r + 1) % 3; } if (r == 0) printf( Carrots n ); else if (r == 1) printf( Kiwis n ); else printf( Grapes n ); } } return 0; } |
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHRU_5 (
CLK,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3,
read_4,
write_4,
EN_write_4
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
output [DATA_SZ-1:0] read_3;
input [DATA_SZ-1:0] write_3;
input EN_write_3;
output [DATA_SZ-1:0] read_4;
input [DATA_SZ-1:0] write_4;
input EN_write_4;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
wire [DATA_SZ-1:0] wire_4;
wire [DATA_SZ-1:0] wire_5;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign wire_4 = EN_write_3 ? write_3 : wire_3;
assign wire_5 = EN_write_4 ? write_4 : wire_4;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
assign read_3 = wire_3;
assign read_4 = wire_4;
always @(posedge CLK) begin
r <= wire_5;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int mx1, my1, mx2, my2; string in; int main() { ios::sync_with_stdio(0); cin >> in; mx1 = in[0] - a + 1; my1 = in[1] - 0 ; cin >> in; mx2 = in[0] - a + 1; my2 = in[1] - 0 ; cout << max(abs(mx1 - mx2), abs(my1 - my2)) << endl; while (1) { if (mx1 == mx2 && my1 == my2) break; if (mx1 > mx2) { cout << L ; mx1 -= 1; } else if (mx1 < mx2) { cout << R ; mx1 += 1; } if (my1 < my2) { cout << U ; my1 += 1; } else if (my1 > my2) { cout << D ; my1 -= 1; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> T abs(T x) { return x > 0 ? x : (-x); } template <class T> T sqr(T x) { return x * x; } const int maxn = 1000 * 1000 * 2; const int BUBEN = 40; long long fib[BUBEN]; int a[maxn]; int n; long long X, Y; long long P; struct M { long long a[2][2]; M() { memset(a, 0, sizeof(a)); } long long* operator[](int x) { return a[x]; } M operator*(M m) { M res; for (int i = 0; i < 2; ++i) for (int j = 0; j < 2; ++j) for (int k = 0; k < 2; ++k) res[i][j] = (res[i][j] + a[i][k] * m[k][j]) % P; return res; } }; M pw(M x, long long y) { M res; res[0][0] = res[1][1] = 1; while (y) { if (y % 2LL == 1LL) res = res * x, --y; else x = x * x, y /= 2LL; } return res; } const double alpha = (1. + sqrt(5.)) * 0.5; bool cmp(pair<long long, long long> p, pair<long long, long long> q) { if (X >= BUBEN - 2) return p.first * alpha + p.second > q.first * alpha + q.second; return p.first * fib[X + 1] + p.second * fib[X] > q.first * fib[X + 1] + q.second * fib[X]; } int main() { fib[0] = 0; fib[1] = 1; for (int i = 2; i < BUBEN; ++i) fib[i] = fib[i - 1] + fib[i - 2]; cin >> n >> X >> Y >> P; long long sum = 0; for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); sum += a[i]; sum %= P; } sort(a, a + n); if (0) { vector<int> v; for (int i = 0; i < n; ++i) v.push_back(a[i]); for (int i = 0; i < X; ++i) { vector<int> w; w.push_back(v[0]); for (int j = 1; j < ((int)(v).size()); ++j) w.push_back(v[j - 1] + v[j]), w.push_back(v[j]); v = w; } sort((v).begin(), (v).end()); for (int i = 0; i < Y; ++i) { vector<int> w; w.push_back(v[0]); for (int j = 1; j < ((int)(v).size()); ++j) w.push_back(v[j - 1] + v[j]), w.push_back(v[j]); v = w; } long long res = 0; for (int i = 0; i < ((int)(v).size()); ++i) res += v[i]; res %= P; cerr << res << n ; } if (n == 1) { cout << (a[0] % P) << n ; return 0; } long long l1 = a[0], r1 = a[n - 1]; long long l2 = a[0]; pair<long long, long long> _r2(-1, -1); for (int i = 0; i < n - 1; ++i) { long long x = a[i], y = a[i + 1]; if (x < y) swap(x, y); pair<long long, long long> cur(x, y); if (cmp(cur, _r2)) _r2 = cur; } M mf; mf[0][0] = mf[0][1] = mf[1][0] = 1; M F = pw(mf, X); long long r2 = F[0][0] * (_r2.first % P) + F[0][1] * (_r2.second % P); r2 %= P; M m1; m1[0][0] = 3; m1[0][1] = (P - 1) % P; m1[1][1] = 1; M m2 = pw(m1, X); long long T1 = l1 + r1; long long T2 = l2 + r2; T1 %= P; T2 %= P; long long s0 = m2[0][0] * sum + m2[0][1] * (T1); s0 %= P; M m3 = pw(m1, Y); long long res = m3[0][0] * s0 + m3[0][1] * (T2); res %= P; res += P; res %= P; cout << res << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; string s; int x; cin >> n >> m >> k; int a[n][m]; int b[n][m]; int c[n][m]; for (int i = 0; i < n; i++) { cin >> s; for (int j = 0; j < m; j++) { cin >> x; a[i][j] = x; cin >> x; b[i][j] = x; cin >> x; c[i][j] = x; } } int sum_max = 0; int sum; vector<pair<int, int> > abc; abc.reserve(m); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i == j) continue; sum = 0; abc.clear(); for (int ii = 0; ii < m; ii++) { abc.push_back(make_pair(b[j][ii] - a[i][ii], c[i][ii])); } sort(abc.begin(), abc.end()); int left = k; for (int ii = m - 1; ii >= 0 && left > 0; ii--) { int d = min(left, abc[ii].second); if (abc[ii].first > 0) { sum += d * abc[ii].first; left -= d; } } if (sum > sum_max) { sum_max = sum; } } } cout << sum_max << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, mini = 0, maxi = 0; int x[200005]; bool o[200005]; int main() { cin >> n; for (int i = 0; i < (n); i++) { int a; cin >> a; x[a]++; } for (int i = 0; i < (n + 1); i++) { while (i < n + 1 && x[i] == 0) i++; if (i == n + 1) break; mini++; i += 2; } for (int i = 0; i < (n + 1); i++) { while (i < n + 1 && x[i] == 0) i++; if (i == n + 1) break; for (int j = 0; j < (min(3, x[i])); j++) { if (!o[i - 1]) { o[i - 1] = true; maxi++; } else if (!o[i]) { o[i] = true; maxi++; } else if (!o[i + 1]) { o[i + 1] = true; maxi++; } } } cout << mini << << maxi << endl; } |
#include <bits/stdc++.h> using namespace std; char s[100050]; bool vis; int main() { scanf( %s , s + 1); int len = strlen(s + 1); if (len <= 2) { printf( No n ); return 0; } for (int i = 1; i <= len - 2; i++) { if (s[i] != s[i + 1] && s[i + 1] != s[i + 2] && s[i] != s[i + 2] && s[i] != . && s[i + 1] != . && s[i + 2] != . ) { vis = 1; break; } } if (vis == 1) printf( Yes n ); else printf( No n ); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO0P_BLACKBOX_V
`define SKY130_FD_SC_LP__LSBUFISO0P_BLACKBOX_V
/**
* lsbufiso0p: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbufiso0p (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO0P_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int oo = (int)1e9; const double PI = 2 * acos(0.0); const double eps = 1e-9; int n, m; vector<int> len; vector<pair<int, int> > pos; deque<int> ans; vector<bool> vis; int find(int x) { for (int i = 0; i < (int)len.size(); ++i) { if (len[i] == x and !vis[i]) return i; } return -1; } int main() { cin >> n >> m; pos = vector<pair<int, int> >(n); len = vector<int>(m); for (int i = 0; i < n; ++i) cin >> pos[i].first >> pos[i].second; for (int i = 0; i < m; ++i) cin >> len[i]; if (n % 2) { cout << NO n ; return 0; } bool good = 0; vis = vector<bool>(m, 0); ans = deque<int>(); for (int i = 0; i < n; i += 2) { int prev = (i + n - 1) % n; int dist1 = (int)hypot(pos[prev].first - pos[i].first, pos[prev].second - pos[i].second); int dist2 = (int)hypot(pos[i + 1].first - pos[i].first, pos[i + 1].second - pos[i].second); int idx = find(dist1 + dist2); if (idx != -1) { vis[idx] = 1; ans.push_back(idx); } else goto no; } cout << YES << endl; for (int i = 0; i < n; ++i) { if (i % 2 == 1) cout << -1 << ; else { cout << ans.front() + 1 << ; ans.pop_front(); } } cout << endl; return 0; no:; vis = vector<bool>(m, 0); ans = deque<int>(); for (int i = 1; i < n; i += 2) { int nxt = (i + n + 1) % n; int dist1 = (int)hypot(pos[i - 1].first - pos[i].first, pos[i - 1].second - pos[i].second); int dist2 = (int)hypot(pos[nxt].first - pos[i].first, pos[nxt].second - pos[i].second); int idx = find(dist1 + dist2); if (idx != -1) { vis[idx] = 1; ans.push_back(idx); } else { good = 0; goto noo; } } cout << YES << endl; for (int i = 0; i < n; ++i) { if (i % 2 == 0) cout << -1 << ; else { cout << ans.front() + 1 << ; ans.pop_front(); } } cout << endl; return 0; noo:; cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const double sn = 1e-6; int n, k; char arr[55][10]; string s[55]; string res[55]; int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n - k + 1; i++) { scanf( %s , arr[i]); string st(arr[i]); s[i] = st; } string val = Aa ; for (int i = 0; i < n - k + 1; i++) { if (s[i] == NO ) { if (res[i] != ) { res[i + k - 1] = res[i]; continue; } res[i] = val; res[i + k - 1] = val; val[1] = val[1] + 1; if (val[1] > z ) { val[0] = val[0] + 1; val[1] = a ; } } } for (int i = 0; i < n; i++) { if (res[i] == ) { res[i] = val; val[1] = val[1] + 1; if (val[1] > z ) { val[0] = val[0] + 1; val[1] = a ; } } } for (int i = 0; i < n; i++) { printf( %s , res[i].c_str()); if (i != n - 1) printf( ); } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 101000; int n, m, k[N], g[50][50], cnt[50], tmp[50]; vector<pair<int, int> > v[N]; inline int gcd(int first, int second) { return (!second) ? first : gcd(second, first % second); } inline void init() { int i, j; for (i = 1; i <= 40; ++i) for (j = 1; j <= 40; ++j) g[i][j] = gcd(i, j); } inline bool insert(pair<int, int> p) { int i; for (i = 1; i <= 40; ++i) if (cnt[i] && (p.second - tmp[i]) % g[k[p.first]][i]) return 0; return tmp[k[p.first]] = p.second, ++cnt[k[p.first]], 1; } inline void erase(pair<int, int> p) { --cnt[k[p.first]]; if (!cnt[k[p.first]]) tmp[k[p.first]] = 0; } inline void solve(int first) { int i = 0, j = 0, ans = 0, t = 0; memset(cnt, 0, sizeof(cnt)); while (j < v[first].size()) { while (j < v[first].size() && j - i == v[first][j].first - v[first][i].first && insert(v[first][j])) ++j; ans = max(ans, j - i); erase(v[first][i]), ++i; } cout << ans << endl; } int main() { ios ::sync_with_stdio(false); int i, j, first; init(); cin >> n >> m; for (i = 1; i <= n; ++i) { cin >> k[i]; for (j = 1; j <= k[i]; ++j) cin >> first, v[first].push_back(make_pair(i, j)); } for (i = 1; i <= m; ++i) solve(i); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T &f) { f = 0; T fu = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) fu = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { f = (f << 3) + (f << 1) + (c & 15); c = getchar(); } f *= fu; } template <typename T> void print(T x) { if (x < 0) putchar( - ), x = -x; if (x < 10) putchar(x + 48); else print(x / 10), putchar(x % 10 + 48); } template <typename T> void print(T x, char t) { print(x); putchar(t); } const int N = 55, M = 7777; char c[N]; int isp[M + 5], val[N]; int T, n; bool check(int x) { for (int i = 2; i * i <= x; i++) { if (x % i == 0) return 0; } return 1; } int main() { for (int i = 2; i <= M; i++) isp[i] = check(i); read(T); while (T--) { read(n); scanf( %s , c + 1); for (int i = 1; i <= M; i++) { if (isp[i]) continue; int len = 0, tmp = i; while (tmp) { val[++len] = tmp % 10; tmp /= 10; } reverse(val + 1, val + len + 1); int pos = 1; for (int j = 1; j <= n; j++) { if (c[j] - 0 == val[pos]) ++pos; if (pos == len + 1) break; } if (pos == len + 1) { print(len, n ); print(i, n ); break; } } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2B_SYMBOL_V
`define SKY130_FD_SC_LP__NAND2B_SYMBOL_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int a, b, c, d, e, i, j, ii, jj, zx, xc, p[10009], ji, F[10009], G[10009]; pair<int, int> k[10009]; vector<int> v; vector<int>::iterator it; int ask(int q, int w) { int qw = 0; cout << ? << q << << w << endl; cin >> qw; return qw; } int fun(int q) { int qw = 0; if (q != k[0].first) { qw = ask(q, k[0].first); } else { qw = ask(q, k[0].second); } for (j = 1; j <= ji; j++) { if (q != k[j].first) { e = ask(q, k[j].first); } else { e = ask(q, k[j].second); } qw &= e; } return qw; } void answer() { cout << ! ; for (j = 1; j <= a; j++) { cout << << p[j]; } exit(0); } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> a; for (j = 0;; j++) { if ((1 << j) >= a) break; ji = j; } while (1) { for (j = 0; j <= ji; j++) { if (k[j].first == 0) break; } if (j == ji + 1) break; c = rand() % a + 1; d = rand() % a + 1; if (c == d) continue; e = ask(c, d); for (jj = 0; jj <= ji; jj++) { if ((e & (1 << jj)) == 0) { k[jj].first = c; k[jj].second = d; } } } for (i = 1; i <= a; i++) { c = rand() % (a - i + 1) + 1; G[i] = c; v.push_back(i); } for (i = 1; i <= a; i++) { F[i] = v[G[i] - 1]; it = v.begin() + (G[i] - 1); v.erase(it); } p[F[1]] = fun(F[1]); c = F[1]; for (i = 2; i <= a; i++) { e = ask(c, F[i]); if (p[c] == e) { c = F[i]; p[c] = fun(c); } } p[c] = 0; for (i = 1; i <= a; i++) { if (i == c) continue; p[i] = ask(i, c); } answer(); return 0; } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module seq_gen #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter MEM_BYTES = 16384,
parameter OUT_BITS = 8
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
input wire SEQ_EXT_START,
input wire SEQ_CLK,
output wire [OUT_BITS-1:0] SEQ_OUT
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
seq_gen_core #(
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(MEM_BYTES),
.OUT_BITS(OUT_BITS)
) i_seq_gen_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.SEQ_EXT_START(SEQ_EXT_START),
.SEQ_CLK(SEQ_CLK),
.SEQ_OUT(SEQ_OUT)
);
endmodule
|
`timescale 1ns / 1ns
module udp_rxq
(input clk,
input [7:0] rxd, input rxdv, input rxlast,
output [7:0] qrxd, output qrxdv, output qrxlast);
// this module accepts the off-the-wire UDP payload and buffers it until
// we can determine if this was a valid UDP payload or not. (i.e., if the
// ethernet FCS matched, and if the IP and UDP headers were sane)
//////////////////////////////////////////////////////////////////
// input section
// we're getting one word per 4 clocks.
wire [3:0] rxdv_shift;
wire rxdv_d4 = rxdv_shift[3];
r #(4) rxdv_shift_r
(.c(clk), .d({rxdv_shift[2:0], rxdv}), .rst(1'b0), .en(1'b1), .q(rxdv_shift));
wire rxdv_end = ~rxdv & rxdv_d4;
wire [31:0] rxd_shift;
wire [7:0] rxd_d4 = rxd_shift[31:24];
r #(32) rxd_shift_r
(.c(clk), .rst(1'b0), .en(1'b1), .d({rxd_shift[23:0], rxd}), .q(rxd_shift));
wire rxlast_d1, rxlast_d2, rxlast_d3, rxlast_d4;
r rxlast_d1_r(.c(clk), .rst(1'b0), .en(1'b1), .d(rxlast), .q(rxlast_d1));
r rxlast_d2_r(.c(clk), .rst(1'b0), .en(1'b1), .d(rxlast_d1), .q(rxlast_d2));
r rxlast_d3_r(.c(clk), .rst(1'b0), .en(1'b1), .d(rxlast_d2), .q(rxlast_d3));
r rxlast_d4_r(.c(clk), .rst(1'b0), .en(1'b1), .d(rxlast_d3), .q(rxlast_d4));
wire [10:0] dfifo_usedw;
wire dfifo_empty;
wire dfifo_rdreq;
wire [8:0] dfifo_q;
scfifo #(.lpm_width(9),
.lpm_numwords(2048),
.lpm_widthu(11),
.lpm_showahead("ON"),
.use_eab("ON"),
.intended_device_family("CYCLONE V")) dfifo // data fifo
(.clock(clk),
.wrreq(rxdv_d4), .data({rxdv_end, rxd_d4}),
.rdreq(dfifo_rdreq), .q(dfifo_q),
.empty(dfifo_empty),
.usedw(dfifo_usedw),
.aclr(1'b0), .sclr(1'b0));
assign qrxd = dfifo_q[7:0];
// shift through 22 samples of rxlast in case we see any that are high
// which indicates that (after potentially up to 22 octets on short packets)
// the FCS and length fields all checked out OK
// (of course this could be short-circuited for long packets; revisit this
// design if that ever matters).
localparam RXLAST_SHIFT_LEN = 26;
wire [RXLAST_SHIFT_LEN-1:0] rxlast_shift;
r #(RXLAST_SHIFT_LEN) rxlast_shift_r
(.c(clk), .en(1'b1), .rst(1'b0),
.d({rxlast_shift[RXLAST_SHIFT_LEN-2:0], rxlast_d4}), .q(rxlast_shift));
wire [RXLAST_SHIFT_LEN-1:0] rxdv_end_shift;
r #(RXLAST_SHIFT_LEN) rxdv_end_shift_r
(.c(clk), .en(1'b1), .rst(1'b0),
.d({rxdv_end_shift[RXLAST_SHIFT_LEN-2:0], rxdv_end}),
.q(rxdv_end_shift));
wire vfifo_wrreq = rxdv_end_shift[RXLAST_SHIFT_LEN-1];
wire found_rxlast = |rxlast_shift;
wire vfifo_q;
wire vfifo_rdreq, vfifo_empty;
wire [4:0] vfifo_usedw;
scfifo #(.lpm_width(1),
.lpm_numwords(32),
.lpm_widthu(5),
.lpm_showahead("ON"),
.intended_device_family("CYCLONE V")) vfifo // valid fifo
(.clock(clk),
.wrreq(vfifo_wrreq), .rdreq(vfifo_rdreq),
.empty(vfifo_empty), .usedw(vfifo_usedw),
.data(found_rxlast), .q(vfifo_q),
.aclr(1'b0), .sclr(1'b0));
//////////////////////////////////////////////////////////////////
// output section
wire pkt_draining, pkt_draining_en;
r pkt_draining_r(.c(clk), .rst(1'b0), .en(1'b1),
.d(pkt_draining_en), .q(pkt_draining));
assign pkt_draining_en = pkt_draining ?
~dfifo_q[8] : // stop when you hit a prior rxdv_end
~vfifo_empty;
assign qrxdv = pkt_draining & vfifo_q; // mask qrxdv on its rxlast flag
assign qrxlast = pkt_draining & dfifo_q[8] & vfifo_q;
assign dfifo_rdreq = pkt_draining;
assign vfifo_rdreq = pkt_draining & dfifo_q[8];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SDLCLKP_PP_SYMBOL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDLCLKP_PP_SYMBOL_V
|
// niosii_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [26:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [26:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
niosii_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_BEHAVIORAL_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_BEHAVIORAL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlygate4sd2 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_BEHAVIORAL_V |
module PushButton_Debouncer#(parameter COUNTER_WIDTH = 16) (
input wire clk,
input wire PB, // "PB" is the glitchy, asynchronous to clk, active low push-button signal
// from which we make three outputs, all synchronous to the clock
output reg PB_state, // 1 as long as the push-button is active (down)
output wire PB_down, // 1 for one clock cycle when the push-button goes down (i.e. just pushed)
output wire PB_up // 1 for one clock cycle when the push-button goes up (i.e. just released)
);
// First use two flip-flops to synchronize the PB signal the "clk" clock domain
reg PB_sync_0; always @(posedge clk) PB_sync_0 <= PB; // invert PB to make PB_sync_0 active high
reg PB_sync_1; always @(posedge clk) PB_sync_1 <= PB_sync_0;
// Next declare a 16-bits counter
reg [COUNTER_WIDTH-1:0] PB_cnt;
// When the push-button is pushed or released, we increment the counter
// The counter has to be maxed out before we decide that the push-button state has changed
wire PB_idle = (PB_state==PB_sync_1);
wire PB_cnt_max = &PB_cnt; // true when all bits of PB_cnt are 1's
always @(posedge clk)
if(PB_idle)
PB_cnt <= 0; // nothing's going on
else
begin
PB_cnt <= PB_cnt + 16'd1; // something's going on, increment the counter
if(PB_cnt_max) PB_state <= ~PB_state; // if the counter is maxed out, PB changed!
end
assign PB_down = ~PB_idle & PB_cnt_max & ~PB_state;
assign PB_up = ~PB_idle & PB_cnt_max & PB_state;
endmodule |
#include <bits/stdc++.h> using namespace std; priority_queue<int> a, b; int c = 0; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { int x; cin >> x; a.push(x); } cin >> n; for (int i = 0; i < n; i++) { int x; cin >> x; b.push(x); } while (!b.empty() && !a.empty()) { if (abs(a.top() - b.top()) < 2) { c++; a.pop(); b.pop(); continue; } if (a.top() > b.top()) a.pop(); else b.pop(); } cout << c; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111A_1_V
`define SKY130_FD_SC_LS__O2111A_1_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111a_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o2111a_1 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111A_1_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7, maxn = 1e6 + 6; int n, m, k, x, res = 1, fact[maxn]; map<vector<int>, int> f; vector<int> a[maxn]; int main() { fact[0] = 1; for (int i = 1; i < maxn; ++i) fact[i] = 1LL * fact[i - 1] * i % mod; scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) { scanf( %d , &k); for (int j = 1; j <= k; ++j) { scanf( %d , &x); a[x].push_back(i); } } for (int i = 1; i <= m; ++i) sort(a[i].begin(), a[i].end()), ++f[a[i]]; for (map<vector<int>, int>::iterator it = f.begin(); it != f.end(); ++it) { res = 1LL * res * fact[it->second] % mod; } printf( %d , res); } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d, e, f, mn1, mn2, res, ans1, ans2; cin >> a >> b >> c >> d >> e >> f; res = d; mn2 = min(b, min(c, d)); d = abs(mn2 - d); mn1 = min(a, d); ans1 = (mn2 * f) + (mn1 * e); mn1 = min(a, res); res = abs(mn1 - res); mn2 = min(b, min(c, res)); ans2 = (mn2 * f) + (mn1 * e); cout << max(ans1, ans2) << endl; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; const long long N = 1e5 + 5; map<long long, long long> freq, freq2; void func1(long long a[], long long n) { int i = 0, j = 0; while (i < n) { if (a[i] == 0) { i++; continue; } j = i; while (j < n && a[j] != 0) { j++; } for (int p = 1; p <= (j - i); p++) { freq[p] += (j - i) - p + 1; } i = j; } } void func2(long long a[], long long n) { int i = 0, j = 0; while (i < n) { if (a[i] == 0) { i++; continue; } j = i; while (j < n && a[j] != 0) { j++; } for (int p = 1; p <= (j - i); p++) { freq2[p] += (j - i) - p + 1; } i = j; } } int main() { long long n, a[N], b[N], r = 0, c = 0, ans = 0, cnt = 0, sum = 0, k, m; cin >> n >> m >> k; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < m; i++) cin >> b[i]; func1(a, n); func2(b, m); for (int p = 1; p <= sqrt(k); p++) { if (k % p == 0) { ans += freq[p] * freq2[k / p]; if (p != (k / p)) ans += freq[k / p] * freq2[p]; } } cout << ans; return 0; } |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Mon Oct 17 14:00:22 2016
/////////////////////////////////////////////////////////////
module FSM_Add_Subtract ( clk, rst, rst_FSM, beg_FSM, zero_flag_i,
norm_iteration_i, add_overflow_i, round_i, load_1_o, load_2_o,
load_3_o, load_8_o, A_S_op_o, load_4_o, left_right_o, bit_shift_o,
load_5_o, load_6_o, load_7_o, ctrl_a_o, ctrl_b_o, ctrl_b_load_o,
ctrl_c_o, ctrl_d_o, rst_int, ready );
output [1:0] ctrl_b_o;
input clk, rst, rst_FSM, beg_FSM, zero_flag_i, norm_iteration_i,
add_overflow_i, round_i;
output load_1_o, load_2_o, load_3_o, load_8_o, A_S_op_o, load_4_o,
left_right_o, bit_shift_o, load_5_o, load_6_o, load_7_o, ctrl_a_o,
ctrl_b_load_o, ctrl_c_o, ctrl_d_o, rst_int, ready;
wire n1, n2, n4, ctrl_a_o, n7, n8, n9, n10, n11, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33,
n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56;
wire [3:0] state_reg;
assign ctrl_d_o = ctrl_a_o;
INVX2TS U3 ( .A(rst), .Y(n1) );
DFFRX2TS \state_reg_reg[3] ( .D(n55), .CK(clk), .RN(n1), .Q(state_reg[3]),
.QN(n9) );
DFFRX2TS \state_reg_reg[1] ( .D(n54), .CK(clk), .RN(n1), .Q(state_reg[1]),
.QN(n16) );
DFFRX2TS \state_reg_reg[0] ( .D(n56), .CK(clk), .RN(n1), .Q(state_reg[0]),
.QN(n17) );
DFFRX2TS \state_reg_reg[2] ( .D(n53), .CK(clk), .RN(n1), .Q(state_reg[2]),
.QN(n15) );
NAND3X1TS U4 ( .A(state_reg[1]), .B(n49), .C(state_reg[3]), .Y(n20) );
NOR3X1TS U5 ( .A(load_2_o), .B(load_1_o), .C(load_7_o), .Y(n31) );
NOR2X1TS U6 ( .A(n16), .B(state_reg[3]), .Y(n51) );
AOI21X1TS U7 ( .A0(load_2_o), .A1(zero_flag_i), .B0(load_7_o), .Y(n22) );
NOR3BX1TS U8 ( .AN(n45), .B(n17), .C(state_reg[1]), .Y(n25) );
NAND3X1TS U9 ( .A(n16), .B(n9), .C(n49), .Y(n41) );
NAND3X1TS U10 ( .A(n16), .B(n9), .C(n50), .Y(n32) );
NAND3X1TS U11 ( .A(state_reg[1]), .B(n17), .C(n45), .Y(n29) );
NAND2X1TS U12 ( .A(n43), .B(n27), .Y(load_5_o) );
NOR2BX1TS U13 ( .AN(ctrl_b_load_o), .B(add_overflow_i), .Y(ctrl_b_o[0]) );
OA21XLTS U14 ( .A0(n36), .A1(load_8_o), .B0(add_overflow_i), .Y(bit_shift_o)
);
INVX2TS U15 ( .A(n43), .Y(ctrl_c_o) );
INVX2TS U16 ( .A(n20), .Y(ready) );
OAI21X1TS U17 ( .A0(n32), .A1(n18), .B0(n24), .Y(n36) );
INVX2TS U18 ( .A(n40), .Y(load_2_o) );
INVX2TS U19 ( .A(n22), .Y(n10) );
INVX2TS U20 ( .A(n32), .Y(n8) );
NAND2X1TS U21 ( .A(n51), .B(n49), .Y(n43) );
NAND2X1TS U22 ( .A(n50), .B(n51), .Y(n27) );
INVX2TS U23 ( .A(n41), .Y(n4) );
INVX2TS U24 ( .A(n29), .Y(n7) );
INVX2TS U25 ( .A(n39), .Y(rst_int) );
INVX2TS U26 ( .A(n44), .Y(load_6_o) );
NOR4XLTS U27 ( .A(n48), .B(ctrl_b_load_o), .C(load_5_o), .D(load_4_o), .Y(
n47) );
NAND2X1TS U28 ( .A(n32), .B(n24), .Y(load_4_o) );
NAND3X1TS U29 ( .A(n20), .B(n39), .C(n42), .Y(n48) );
AOI211X1TS U30 ( .A0(n4), .A1(n18), .B0(n50), .C0(n25), .Y(n46) );
NAND2X1TS U31 ( .A(n44), .B(n29), .Y(ctrl_b_load_o) );
NAND4X1TS U32 ( .A(add_overflow_i), .B(n31), .C(n46), .D(n47), .Y(A_S_op_o)
);
OAI21X1TS U33 ( .A0(n18), .A1(n41), .B0(n33), .Y(load_8_o) );
OAI2BB1X1TS U34 ( .A0N(load_6_o), .A1N(add_overflow_i), .B0(n29), .Y(
ctrl_b_o[1]) );
AOI211X1TS U35 ( .A0(n41), .A1(n32), .B0(n18), .C0(add_overflow_i), .Y(
left_right_o) );
INVX2TS U36 ( .A(n28), .Y(ctrl_a_o) );
OAI22X1TS U37 ( .A0(beg_FSM), .A1(n39), .B0(rst_FSM), .B1(n20), .Y(n26) );
NAND4BX1TS U38 ( .AN(load_5_o), .B(n33), .C(n34), .D(n35), .Y(n55) );
AOI21X1TS U39 ( .A0(n25), .A1(n19), .B0(n7), .Y(n34) );
AOI211X1TS U40 ( .A0(state_reg[3]), .A1(n26), .B0(n36), .C0(n10), .Y(n35) );
INVX2TS U41 ( .A(round_i), .Y(n19) );
NAND4X1TS U42 ( .A(n27), .B(n28), .C(n29), .D(n30), .Y(n54) );
AOI221X1TS U43 ( .A0(n8), .A1(n18), .B0(state_reg[1]), .B1(n26), .C0(n11),
.Y(n30) );
INVX2TS U44 ( .A(n31), .Y(n11) );
NOR2X1TS U45 ( .A(n15), .B(state_reg[0]), .Y(n49) );
NAND3X1TS U46 ( .A(n21), .B(n22), .C(n23), .Y(n53) );
NOR4BX1TS U47 ( .AN(n24), .B(load_3_o), .C(load_6_o), .D(n25), .Y(n23) );
AOI22X1TS U48 ( .A0(n8), .A1(n18), .B0(state_reg[2]), .B1(n26), .Y(n21) );
NAND3X1TS U49 ( .A(n41), .B(n42), .C(n33), .Y(load_3_o) );
AOI31X1TS U50 ( .A0(n37), .A1(n2), .A2(n38), .B0(n26), .Y(n56) );
INVX2TS U51 ( .A(n36), .Y(n2) );
AOI2BB1X1TS U52 ( .A0N(n40), .A1N(zero_flag_i), .B0(n7), .Y(n37) );
NOR3X1TS U53 ( .A(n25), .B(rst_int), .C(n4), .Y(n38) );
AND2X2TS U54 ( .A(n52), .B(state_reg[0]), .Y(load_1_o) );
NOR2X1TS U55 ( .A(n9), .B(state_reg[2]), .Y(n45) );
NOR2X1TS U56 ( .A(n17), .B(n15), .Y(n50) );
NOR3X1TS U57 ( .A(state_reg[2]), .B(state_reg[3]), .C(state_reg[1]), .Y(n52)
);
NAND3X1TS U58 ( .A(n51), .B(n15), .C(state_reg[0]), .Y(n42) );
NAND2X1TS U59 ( .A(n52), .B(n17), .Y(n39) );
NAND3X1TS U60 ( .A(n17), .B(n15), .C(n51), .Y(n40) );
NAND3X1TS U61 ( .A(n49), .B(n16), .C(state_reg[3]), .Y(n24) );
AND3X2TS U62 ( .A(n50), .B(state_reg[3]), .C(n16), .Y(load_7_o) );
NAND3X1TS U63 ( .A(n17), .B(n16), .C(n45), .Y(n44) );
NAND3X1TS U64 ( .A(state_reg[0]), .B(state_reg[1]), .C(n45), .Y(n33) );
NAND2X1TS U65 ( .A(round_i), .B(n25), .Y(n28) );
INVX2TS U66 ( .A(norm_iteration_i), .Y(n18) );
endmodule
module FPU_Add_Subtract_Function_W32_EW8_SW23_SWR26_EWR5_FSM_Add_Subtract (
clk, rst, beg_FSM, ack_FSM, Data_X, Data_Y, add_subt, r_mode,
overflow_flag, underflow_flag, ready, final_result_ieee );
input [31:0] Data_X;
input [31:0] Data_Y;
input [1:0] r_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
FSM_Add_Subtract FS_Module ( .clk(clk), .rst(rst), .rst_FSM(ack_FSM),
.beg_FSM(beg_FSM), .zero_flag_i(1'b0), .norm_iteration_i(1'b0),
.add_overflow_i(1'b0), .round_i(1'b0), .ready(ready) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21OI_SYMBOL_V
`define SKY130_FD_SC_HDLL__A21OI_SYMBOL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21OI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int n; string name[1001]; int fen[1001]; vector<pair<string, int> > old; vector<pair<int, string> > xin; vector<int> ff; int main(int argc, char *argv[]) { cin >> n; for (int i = 0; i < n; i++) { cin >> name[i] >> fen[i]; old.push_back(make_pair(name[i], fen[i])); } sort(old.begin(), old.end()); for (int i = 0; i < (int)old.size(); i++) { if (i == (int)old.size() - 1 || old[i].first != old[i + 1].first) { xin.push_back(make_pair(old[i].second, old[i].first)); } } sort(xin.begin(), xin.end()); for (int i = 0; i < (int)xin.size(); i++) { ff.push_back(xin[i].first); } int sz = ff.size(), wz; cout << sz << endl; for (int i = 0; i < (int)xin.size(); i++) { wz = sz - (upper_bound(ff.begin(), ff.end(), ff[i]) - ff.begin()); if (wz * 2 > sz) { cout << xin[i].second << noob n ; } else if (wz * 5 > sz) { cout << xin[i].second << random n ; } else if (wz * 10 > sz) { cout << xin[i].second << average n ; } else if (wz * 100 > sz) { cout << xin[i].second << hardcore n ; } else { cout << xin[i].second << pro n ; } } return EXIT_SUCCESS; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2005, maxv = 4e6 + 5; long long a, b, c, X1, X2, Y1, Y2; pair<long double, long double> va[6], vb[6]; void exgcd(long long a, long long b, long long &x, long long &y) { if (!b) { x = 1, y = 0; return; } exgcd(b, a % b, y, x); y -= a / b * x; } long double sqr(long double x) { return x * x; } int main() { scanf( %lld %lld %lld , &a, &b, &c); scanf( %lld %lld %lld %lld , &X1, &Y1, &X2, &Y2); long double ans = abs(X1 - X2) + abs(Y1 - Y2); if (a != 0 && b != 0) { va[0] = make_pair(X1, (long double)(-c - a * X1) / b); va[1] = make_pair((long double)(-c - b * Y1) / a, Y1); vb[0] = make_pair(X2, (long double)(-c - a * X2) / b); vb[1] = make_pair((long double)(-c - b * Y2) / a, Y2); for (int i = 0; i <= 1; i++) for (int j = 0; j <= 1; j++) { long double ans1 = fabs(X1 - va[i].first) + fabs(Y1 - va[i].second) + fabs(X2 - vb[j].first) + fabs(Y2 - vb[j].second); ans1 += sqrt(sqr(va[i].first - vb[j].first) + sqr(va[i].second - vb[j].second)); ans = min(ans, ans1); } } printf( %.9f n , (double)ans); } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_tlu_dec64.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_tlu_dec64
// Description:
// 6 -> 64 decoder
*/
module sparc_tlu_dec64(/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [5:0] in;
output [63:0] out;
wire [5:0] in;
reg [63:0] out;
integer i;
always @ (in)
begin
for (i=0;i<64;i=i+1)
begin
if (i[5:0] == in[5:0])
out[i] = 1'b1;
else
out[i] = 1'b0;
end
end
endmodule // sparc_tlu_dec64
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; vector<int> a(2 * n); for (auto &it : a) cin >> it; vector<int> kop(n); vector<int> ARR; for (int i = 0; i < 2 * n; ++i) { if (!kop[a[i] - 1]) { kop[a[i] - 1] = true; ARR.push_back(a[i]); } } for (auto it : ARR) cout << it << ; cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int a, b, xa, ya, xb, yb; int main() { scanf( %d%d%d%d%d%d , &a, &b, &xa, &ya, &xb, &yb); a <<= 1, b <<= 1; int x1 = (xa + ya), y1 = (xa - ya), x2 = (xb + yb), y2 = (xb - yb); int sector_1_x = (x1 / a) - (x1 < 0), sector_1_y = (y1 / b) - (y1 < 0); int sector_2_x = (x2 / a) - (x2 < 0), sector_2_y = (y2 / b) - (y2 < 0); printf( %d n , max(abs(sector_1_x - sector_2_x), abs(sector_1_y - sector_2_y))); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; const int maxn = 100010; const int INF = ~0U >> 1; const double eps = 1e-9; void getint(int &ret) { char ch; while (ch = getchar(), ch < 0 || ch > 9 ) ; ret = ch - 0 ; while (ch = getchar(), ch >= 0 && ch <= 9 ) ret = ret * 10 + ch - 0 ; } const int maxN = 210; const int maxK = 42; int nxt[maxN * 2], first[maxN], to[maxN * 2], vis[maxN], tot; void add_edge(int x, int y) { nxt[++tot] = first[x]; first[x] = tot; to[tot] = y; } int dp[maxN][maxK * 2]; int f[maxK * 2][maxK * 2], g[maxK * 2][maxK * 2]; vector<int> son[maxN]; int n, k; void dfs(int x) { vis[x] = 1; for (int i = first[x]; i; i = nxt[i]) if (!vis[to[i]]) { son[x].push_back(to[i]); dfs(to[i]); } if (son[x].empty()) { dp[x][1 + k] = 1; dp[x][-k + k] = 1; return; } memset(f, 0, sizeof(f)); for (int i = -k; i <= k; i++) { f[i + k][i + k] = (f[i + k][i + k] + dp[son[x][0]][i + k]) % mod; } for (int kt = 1; kt < son[x].size(); kt++) { int Son = son[x][kt]; memset(g, 0, sizeof(g)); for (int Min = -k; Min <= k; Min++) for (int Max = Min; Max <= k; Max++) { if (f[Min + k][Max + k]) { for (int L = -k; L <= k; L++) { long long tmp = dp[Son][L + k]; g[min(Min, L) + k][max(Max, L) + k] = (g[min(Min, L) + k][max(Max, L) + k] + 1ll * f[Min + k][Max + k] * tmp % mod) % mod; } } } for (int Min = -k; Min <= k; Min++) for (int Max = Min; Max <= k; Max++) f[Min + k][Max + k] = g[Min + k][Max + k]; } for (int Min = -k; Min <= k; Min++) for (int Max = Min; Max <= k; Max++) { if (Min < k) { if (Max + Min + 1 <= 0) dp[x][Min + 1 + k] = (dp[x][Min + 1 + k] + f[Min + k][Max + k]) % mod; else if (Max < k) dp[x][Max + 1 + k] = (dp[x][Max + 1 + k] + f[Min + k][Max + k]) % mod; } dp[x][-k + k] = (dp[x][-k + k] + f[Min + k][Max + k]) % mod; } } int main() { cin >> n >> k; if (k == 0) { puts( 1 ); return 0; } for (int i = 1; i < n; i++) { int x, y; scanf( %d%d , &x, &y); add_edge(x, y); add_edge(y, x); } int ans = 0; dfs(1); for (int i = -k; i <= 0; i++) ans = (ans + dp[1][i + k]) % mod; cout << ans; return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ef_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:59 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ef_e.v,v 1.1 2004/04/06 10:50:55 wig Exp $
// $Date: 2004/04/06 10:50:55 $
// $Log: inst_ef_e.v,v $
// Revision 1.1 2004/04/06 10:50:55 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ef_e
//
// No `defines in this module
module inst_ef_e
//
// Generated module inst_ef
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ef_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=5000 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=Display_PLL" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" width_clock=5 areset clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:14:18:59:15:SJ cbx_altiobuf_bidir 2015:10:14:18:59:15:SJ cbx_altiobuf_in 2015:10:14:18:59:15:SJ cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_altpll 2015:10:14:18:59:15:SJ cbx_cycloneii 2015:10:14:18:59:15:SJ cbx_lpm_add_sub 2015:10:14:18:59:15:SJ cbx_lpm_compare 2015:10:14:18:59:15:SJ cbx_lpm_counter 2015:10:14:18:59:15:SJ cbx_lpm_decode 2015:10:14:18:59:15:SJ cbx_lpm_mux 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_nadder 2015:10:14:18:59:15:SJ cbx_stratix 2015:10:14:18:59:15:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
//CBXI_INSTANCE_NAME="UART_Display_PLL_display0_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module Display_PLL_altpll
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
wire wire_pll1_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll1_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll1
(
.activeclock(),
.areset(areset),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(wire_pll1_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 5000,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.self_reset_on_loss_lock = "off",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]},
locked = (wire_pll1_locked & pll_lock_sync);
endmodule //Display_PLL_altpll
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; int main() { int n, l; cin >> n >> l; double a[n]; for (int i = 0; i < n; i++) cin >> a[i]; sort(&a[0], &a[n]); float x = a[0] - 0; float y = l - a[n - 1]; for (int i = 0; i < n - 1; i++) a[i] = (a[i + 1] - a[i]) / 2; if (x > y) a[n - 1] = x; else a[n - 1] = y; sort(&a[0], &a[n]); cout << std::fixed << a[n - 1]; } |
module Proc;
// Declare global parameters
parameter WIDTH = 32;
parameter NUMREG = 16;
parameter MEMSIZE = (1<<13);
// Declare storage elements in ISA
reg[7:0] MEM[0:MEMSIZE-1]; //main memory
reg[WIDTH-1:0] R[0:NUMREG-1]; //General purpose registers
reg[WIDTH-1:0] PC; //Program Counter
reg[WIDTH-1:0] IR; //Instruction register
reg RUN; //Execute while Run=1
reg C; //Carry Flag
reg V; //Overflow flag
reg Z; //Zero Flag
reg N; //Negative Flag
`define ra NUMREG-1 //return address register is last register
// Declare internal registers for ALU operations
reg[WIDTH-1:0] op1; //internal register for ALU
reg[WIDTH-1:0] op2; //internal register for ALU
reg[WIDTH:0] res; //internal register for ALU - extra bit for carry
// Define opcode and condition codes
`include "ISA.v"
// Trace conditions
`define TRACE_PC 1
`define TRACE_REG 1
`define TRACE_CC 1
// Main fetch-execute loop
reg[WIDTH-1:0] num_instrs;
initial begin
$readmemh("d", MEM, 0, 71);
RUN = 1;
PC = 0;
num_instrs = 0;
while(RUN==1) begin
num_instrs += 1;
fetch;
execute;
print_trace;
end
$writememh("data.hex", MEM, 100, 110);
$display("\nTotal instructions executed %d \n", num_instrs);
$finish;
end
// Task and function definitions
task fetch;
begin
IR = readMem32(PC);
PC += 4;
end
endtask
task execute;
begin
case(`OPCODE)
//R Type Arithmetic
`ADD: begin
op1 = R[`rs];
op2 = R[`rt];
res = op1 + op2;
R[`rd] = res;
setc(op1, op2, res, 0);
end
`SUB: begin
op1 = R[`rs];
op2 = R[`rt];
res = op1 - op2;
R[`rd] = res;
setc(op1, op2, res, 1);
end
`AND: begin
op1 = R[`rs];
op2 = R[`rt];
res = op1 & op2;
R[`rd] = res;
Z = ~|res;
end
`OR: begin
op1 = R[`rs];
op2 = R[`rt];
res = op1 | op2;
R[`rd] = res;
Z = ~|res;
end
`XOR: begin
op1 = R[`rs];
op2 = R[`rt];
res = op1 ^ op2;
R[`rd] = res;
Z = ~|res;
end
`SLL: begin
op1 = R[`rt];
res = op1 << `shamt;
R[`rd] = res;
C = op1[WIDTH - `shamt - 1];
Z = ~|res;
end
`SRL: begin
op1 = R[`rt];
res = op1 >> `shamt;
R[`rd] = res;
C = op1[`shamt];
Z = ~|res;
end
`SRA: begin
op1 = R[`rt];
res = op1 >> 1;
res = {op1[WIDTH-1], res[15:0]};
R[`rd] = res;
C = op1[0];
Z = ~|res;
end
`SLLV: begin
op1 = R[`rt];
op2 = R[`rs];
res = op1 << op2;
R[`rd] = res;
C = op1[WIDTH - op2 - 1];
Z = ~|res;
end
`SRLV: begin
op1 = R[`rt];
op2 = R[`rs];
res = op1 >> op2;
R[`rd] = res;
C = op1[op2];
Z = ~|res;
end
`MOV: R[`rd] = R[`rs];
`SWAP: begin
op1 = R[`rd];
op2 = R[`rs];
R[`rd] = op2;
R[`rs] = op1;
end
//I Type arithmetic
`ADDI: begin
op1 = R[`rs];
op2 = sext16(`imm);
res = op1 + op2;
R[`rd] = res;
setc(op1, op2, res, 1);
end
`ORI: begin
op1 = R[`rs];
op2 = sext16(`imm);
res = op1 | op2;
R[`rd] = res;
Z = ~|res;
end
`ANDI: begin
op1 = R[`rs];
op2 = sext16(`imm);
res = op1 & op2;
R[`rd] = res;
Z = ~|res;
end
//Load - Stores - I Type
`LUI: begin
op1 = sext16(`imm);
R[`rd] = op1 << 'd16;
end
`LDI: begin
R[`rd] = sext16(`imm);
//R[`rd] = `imm;
end
`LW: begin
R[`rd] = readMem32(R[`rs] + `imm);
end
`LH: begin
R[`rd] = readMem16(R[`rs] + `imm);
end
`LD: begin
R[`rd] = readMem8(R[`rs] + `imm);
end
`SW: begin
writeMem32(R[`rs] + `imm, R[`rd]);
end
`SH: begin
writeMem16(R[`rs] + `imm, R[`rd][15:0]);
end
`SD: begin
writeMem8(R[`rs] + `imm, R[`rd][7:0]);
end
`BEQ: if ($signed(R[`rd]) == $signed(R[`rs]))
PC = PC + sext16(`imm);
`BNE: if ($signed(R[`rd]) != $signed(R[`rs]))
PC = PC + sext16(`imm);
`BGTZ: if ($signed(R[`rd]) > 0)
PC = PC + sext16(`imm);
`BLTZ: if ($signed(R[`rd]) < 0)
PC = PC + sext16(`imm);
`BGEZ: begin
if ($signed(R[`rd]) >= 0)
PC = PC + sext16(`imm);
$display("%d", PC);
end
`BLEZ: if ($signed(R[`rd]) <= 0)
PC = PC + sext16(`imm);
`JR: begin
op1 = R[`rd];
op2 = sext16(`imm);
PC = op1 + op2;
end
`JALR: begin
op1 = R[`rd];
op2 = sext16(`imm);
R[`ra] = PC;
PC = op1 + op2;
end
`J: PC = `tgt;
`JAL: begin
R[`ra] = PC;
PC = `tgt;
end
`NOP:;
`HALT: RUN = 0;
default: begin
$display("Undefined OpCode: %d", `OPCODE);
RUN = 0;
end
endcase
end
endtask
// Utility operations and functions
//function to read mem - big-endian
function [WIDTH-1:0] readMem32(
input [WIDTH-1:0] addr); //address to read
readMem32 = {MEM[addr], MEM[addr+1], MEM[addr+2], MEM[addr+3]};
endfunction //end read_mem
function [15:0] readMem16(
input [WIDTH-1:0] addr); //address to read
readMem16 = {MEM[addr], MEM[addr+1]};
endfunction
function [7:0] readMem8(
input [WIDTH-1:0] addr); //address to read
readMem8 = MEM[addr];
endfunction
task writeMem32(
input [WIDTH-1:0] addr,
input [WIDTH-1:0] data);
{MEM[addr], MEM[addr+1], MEM[addr+2], MEM[addr+3]} = data;
endtask
task writeMem16(
input [WIDTH-1:0] addr,
input [15:0] data);
{MEM[addr], MEM[addr+1]} = data;
endtask
task writeMem8(
input [WIDTH-1:0] addr,
input [7:0] data);
MEM[addr] = data;
endtask
//function to print trace
task print_trace;
integer i,j,k;
begin
`ifdef TRACE_PC
begin
$display("Ins. No.= %d\tPC= %d\tOpCode=%d", num_instrs, PC, `OPCODE);
end
`endif
`ifdef TRACE_REG
begin
k=0;
for(i=0;i<16;i+=4)
begin
//$write("R[%d] = ", k);
for(j=0;j<4;j++)
begin
$write("R[%d] = %h \t", k, R[k]);
k +=1;
end
$write("\n");
end
end
`endif
`ifdef TRACE_CC
begin
$display("C = %b\tZ = %b\tN = %b\tV = %b", C, Z, N, V);
end
`endif
end
endtask
task setc(
input [WIDTH-1:0] op1, op2,
input [WIDTH:0] res,
input subt);
begin
C = res[WIDTH];
Z = ~|res;
N = res[WIDTH-1];
V = ( res[WIDTH-1] & op1[WIDTH-1] & ~(subt ^ op2[WIDTH-1])) | (~res[WIDTH-1] & op1[WIDTH-1] & (subt ^ op2[WIDTH-1]));
end
endtask
function [WIDTH-1:0] sext16(
input [15:0] d_in);
begin
sext16[WIDTH-1:0] = {{(WIDTH-16){d_in[15]}}, d_in};
end
endfunction
function [WIDTH-1:0] sext25(
input [24:0] d_in);
sext25[WIDTH-1:0] = {{(WIDTH-25){d_in[24]}}, d_in};
endfunction
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD1_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD1_PP_BLACKBOX_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD1_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; typedef long long ll; typedef pair<ll,ll> pi; typedef vector <ll> vi; typedef vector <pi> vpi; typedef pair<pi,ll> pii; typedef set <ll> si; typedef long double ld; #define f first #define s second #define FOR(i,s,e) for(ll i=s;i<=ll(e);++i) #define DEC(i,s,e) for(ll i=s;i>=ll(e);--i) #define pb push_back #define all(x) (x).begin(), (x).end() #define lbd(x, y) lower_bound(all(x), y) #define ubd(x, y) upper_bound(all(x), y) #define aFOR(i,x) for (auto i: x) #define mem(x,i) memset(x,i,sizeof x) #define fast ios_base::sync_with_stdio(false),cin.tie(0) int N,Q,a,b; string S,F; struct node{ int s,e,m, val, lazy = 0, sz; node *l,*r; node (int ss,int ee){ s = ss; e = ee; m = (s+e) / 2; sz = e - s + 1; if (s != e){ l = new node(s,m); r = new node(m+1,e); } } void prop(){ if (lazy == 0 || s == e) return; l->lazy = r->lazy = lazy; l->val = lazy * l->sz; r->val = lazy * r->sz; lazy = 0; } void upd(int a,int b,int c){ prop(); if (a <= s && e <= b){ lazy = c; val = c * sz; }else if (a > e || s > b) return; else{ l->upd(a,b,c); r->upd(a,b,c); val = l->val + r->val; } } int qry(int a,int b){ prop(); if (a <= s && e <= b) return val; else if (a > e || s > b) return 0; else return l->qry(a,b) + r->qry(a,b); } }*root; void solve(){ cin >> N >> Q >> S >> F; swap(S,F); root = new node(1,N); FOR(i,0,N-1) root->upd(i + 1,i + 1, (S[i] == 0 ? -1 : 1)); vpi v; FOR(i,1,Q){ cin >> a >> b; v.pb(pi(a,b)); } reverse(all(v)); aFOR(i,v){ a = i.f, b = i.s; int x = root->qry(a,b); if (x == 0){ cout << NO n ; return; }else if (x < 0) root->upd(a,b,-1); else root->upd(a,b,1); } FOR(i,0,N-1){ if (root->qry(i+1,i+1) != (F[i] == 0 ? -1 : 1)){ cout << NO n ; return; } } cout << YES n ; } int main(){ fast; int TC; cin >> TC; while (TC--) solve(); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); long long t; cin >> t; while (t--) { long long a; cin >> a; long long b; cin >> b; if (b >= a) { if (b % a == 0 && pow(2, (long long)log2(b / a)) == b / a) { if ((long long)(log2(b / a)) % 3 == 0) { cout << (long long)log2(b / a) / 3 << endl; } else { cout << (long long)(1 + (log2(b / a) / 3)) << endl; } } else { cout << -1 << endl; } } else { if (a % b == 0 && pow(2, (long long)log2(a / b)) == a / b) { if ((long long)(log2(a / b)) % 3 == 0) { cout << (long long)log2(a / b) / 3 << endl; } else { cout << (long long)(1 + (log2(a / b) / 3)) << endl; } } else { cout << -1 << endl; } } } return 0; } |
/*
*
* Copyright (c) 2011
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (
input CLK_100MHZ
);
//// PLL
wire hash_clk;
`ifndef SIM
main_pll pll_blk (.CLK_IN1(CLK_100MHZ), .CLK_OUT1(hash_clk));
`else
assign hash_clk = CLK_100MHZ;
`endif
//// Mining Cores
reg [255:0] midstate_buf = 0, data_buf = 0;
wire [1:0] is_golden_ticket;
wire [31:0] golden_nonce0, golden_nonce1;
mining_core # (.LOOP_LOG2(0), .NONCE_WIDTH(31), .NONCE_PREFIX(1'b0)) mining_core_0 (
.hash_clk(hash_clk),
.rx_midstate(midstate_buf),
.rx_data(data_buf[95:0]),
.tx_is_golden_ticket(is_golden_ticket[0]),
.tx_golden_nonce(golden_nonce0)
);
mining_core # (.LOOP_LOG2(0), .NONCE_WIDTH(31), .NONCE_PREFIX(1'b1)) mining_core_1 (
.hash_clk(hash_clk),
.rx_midstate(midstate_buf),
.rx_data(data_buf[95:0]),
.tx_is_golden_ticket(is_golden_ticket[1]),
.tx_golden_nonce(golden_nonce1)
);
//// Virtual Wire Control
wire [255:0] midstate_vw, data2_vw;
`ifndef SIM
wire [35:0] control0, control1, control2;
chipscope_icon ICON_inst ( .CONTROL0(control0), .CONTROL1(control1), .CONTROL2(control2));
chipscope_vio_tochip midstate_vw_blk ( .CONTROL(control0), .CLK(hash_clk), .SYNC_OUT(midstate_vw) );
chipscope_vio_tochip data_vw_blk ( .CONTROL(control1), .CLK(hash_clk), .SYNC_OUT(data2_vw) );
`endif
//// Virtual Wire Output
reg [31:0] golden_nonce = 0;
`ifndef SIM
chipscope_vio_fromchip golden_nonce_vw_blk ( .CONTROL(control2), .CLK(hash_clk), .SYNC_IN(golden_nonce) );
`endif
//// Control Unit
always @ (posedge hash_clk)
begin
`ifdef SIM
//midstate_buf <= 256'h2b3f81261b3cfd001db436cfd4c8f3f9c7450c9a0d049bee71cba0ea2619c0b5;
//data_buf <= 256'h00000000000000000000000080000000_00000000_39f3001b6b7b8d4dc14bfc31;
//nonce <= 30411740;
`else
midstate_buf <= midstate_vw;
data_buf <= data2_vw;
`endif
if (is_golden_ticket[0])
golden_nonce <= golden_nonce0;
else if (is_golden_ticket[1])
golden_nonce <= golden_nonce1;
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sine.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sine (
address,
clock,
q);
input [7:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../../Samples/Sine/sine8x8.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../../Samples/Sine/sine8x8.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../Samples/Sine/sine8x8.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sine.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sine.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sine.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sine.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sine_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sine_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module xillyvga #(
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_ADDR_WIDTH = 32,
parameter C_M_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_MIN_SIZE = 32'h000001ff,
parameter C_USE_WSTRB = 1,
parameter C_DPHASE_TIMEOUT = 8,
parameter C_BASEADDR = 32'h79c00000,
parameter C_HIGHADDR = 32'h79c0ffff,
parameter C_SLV_AWIDTH = 32,
parameter C_SLV_DWIDTH = 32,
parameter C_MAX_BURST_LEN = 256,
parameter C_NATIVE_DATA_WIDTH = 32
)
(
input S_AXI_ACLK,
input [31:0] S_AXI_ARADDR,
input S_AXI_ARESETN,
input S_AXI_ARVALID,
input [31:0] S_AXI_AWADDR,
input S_AXI_AWVALID,
input S_AXI_BREADY,
input S_AXI_RREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
input clk_in,
input m_axi_aclk,
input m_axi_aresetn,
input m_axi_arready,
input m_axi_awready,
input [1:0] m_axi_bresp,
input m_axi_bvalid,
input [31:0] m_axi_rdata,
input m_axi_rlast,
input [1:0] m_axi_rresp,
input m_axi_rvalid,
input m_axi_wready,
output S_AXI_ARREADY,
output S_AXI_AWREADY,
output [1:0] S_AXI_BRESP,
output S_AXI_BVALID,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
output S_AXI_WREADY,
output [31:0] m_axi_araddr,
output [1:0] m_axi_arburst,
output [3:0] m_axi_arcache,
output [3:0] m_axi_arlen,
output [2:0] m_axi_arprot,
output [2:0] m_axi_arsize,
output m_axi_arvalid,
output [31:0] m_axi_awaddr,
output [1:0] m_axi_awburst,
output [3:0] m_axi_awcache,
output [3:0] m_axi_awlen,
output [2:0] m_axi_awprot,
output [2:0] m_axi_awsize,
output m_axi_awvalid,
output m_axi_bready,
output m_axi_rready,
output [31:0] m_axi_wdata,
output m_axi_wlast,
output [3:0] m_axi_wstrb,
output m_axi_wvalid,
output vga_clk,
output [7:0] vga_blue,
output [7:0] vga_green,
output vga_hsync,
output [7:0] vga_red,
output vga_vsync,
output vga_de
);
xillyvga_core xillyvga_core_ins (
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_RREADY(S_AXI_RREADY),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.clk_in(clk_in),
.m_axi_aclk(m_axi_aclk),
.m_axi_aresetn(m_axi_aresetn),
.m_axi_arready(m_axi_arready),
.m_axi_awready(m_axi_awready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rlast(m_axi_rlast),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_arlen(m_axi_arlen),
.m_axi_arprot(m_axi_arprot),
.m_axi_arsize(m_axi_arsize),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awlen(m_axi_awlen),
.m_axi_awprot(m_axi_awprot),
.m_axi_awsize(m_axi_awsize),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_rready(m_axi_rready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wlast(m_axi_wlast),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wvalid(m_axi_wvalid),
.vga_clk(vga_clk),
.vga_blue(vga_blue),
.vga_green(vga_green),
.vga_hsync(vga_hsync),
.vga_red(vga_red),
.vga_vsync(vga_vsync),
.vga_de(vga_de)
);
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: i2c_master_top.v,v 1.1 2008-11-08 13:15:10 sfielding Exp $
//
// $Date: 2008-11-08 13:15:10 $
// $Revision: 1.1 $
// $Author: sfielding $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.11 2005/02/27 09:26:24 rherveille
// Fixed register overwrite issue.
// Removed full_case pragma, replaced it by a default statement.
//
// Revision 1.10 2003/09/01 10:34:38 rherveille
// Fix a blocking vs. non-blocking error in the wb_dat output mux.
//
// Revision 1.9 2003/01/09 16:44:45 rherveille
// Fixed a bug in the Command Register declaration.
//
// Revision 1.8 2002/12/26 16:05:12 rherveille
// Small code simplifications
//
// Revision 1.7 2002/12/26 15:02:32 rherveille
// Core is now a Multimaster I2C controller
//
// Revision 1.6 2002/11/30 22:24:40 rherveille
// Cleaned up code
//
// Revision 1.5 2001/11/10 10:52:55 rherveille
// Changed PRER reset value from 0x0000 to 0xffff, conform specs.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "i2c_master_defines.v"
module i2c_master_top(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
// parameters
parameter ARST_LVL = 1'b0; // asynchronous reset level
//
// inputs & outputs
//
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input arst_i; // asynchronous reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
reg [7:0] wb_dat_o;
reg wb_ack_o;
reg wb_inta_o;
// I2C signals
// i2c clock line
input scl_pad_i; // SCL-line input
output scl_pad_o; // SCL-line output (always 1'b0)
output scl_padoen_o; // SCL-line output enable (active low)
// i2c data line
input sda_pad_i; // SDA-line input
output sda_pad_o; // SDA-line output (always 1'b0)
output sda_padoen_o; // SDA-line output enable (active low)
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i)
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsis parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsis parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
default: ;
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (~rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 2'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int h, w, x, y, star = 0, sum, flag; char arr[505][505]; cin >> h >> w; for (int i = 1; i <= h; i++) { for (int j = 1; j <= w; j++) { cin >> arr[i][j]; if (arr[i][j] == * ) { star++; if (arr[i][j - 1] == * && arr[i - 1][j] == * ) { sum = 3; x = i; y = j; } } } } if (sum == 3) { if (arr[x][y + 1] == * && arr[x + 1][y] == * ) { sum = sum + 2; } if (sum == 5) { flag = 1; if (x + 2 <= h) { for (int i = x + 2; i <= h; i++) { if (arr[i][y] == * ) sum++; else break; } } if (x - 2 > 0) { for (int i = x - 2; i > 0; i--) { if (arr[i][y] == * ) sum++; else break; } } if (y + 2 <= w) for (int i = y + 2; i <= w; i++) { if (arr[x][i] == * ) sum++; else break; } if (y - 2 > 0) { for (int i = y - 2; i > 0; i--) { if (arr[x][i] == * ) sum++; else break; } } } } if (star == sum && sum >= 5) cout << YES ; else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long mod(long long n, long long m) { long long ret = n % m; if (ret < 0) ret += m; return ret; } long long gcd(long long a, long long b) { return (b == 0 ? a : gcd(b, a % b)); } long long exp(long long a, long long b, long long m) { if (b == 0) return 1; if (b == 1) return mod(a, m); long long k = mod(exp(a, b / 2, m), m); if (b & 1) { return mod(a * mod(k * k, m), m); } else return mod(k * k, m); } map<vector<long long>, long long> mp; long long a[500100]; vector<long long> adj[500100]; void solve() { mp.clear(); long long n, m; cin >> n >> m; for (long long i = 1; i <= n; i++) { adj[i].clear(); cin >> a[i]; } for (long long i = 0; i < m; i++) { long long a, b; cin >> a >> b; adj[b].push_back(a); } for (long long i = 1; i <= n; i++) { sort(adj[i].begin(), adj[i].end()); if (adj[i].size()) { mp[adj[i]] += a[i]; } } long long g = -1; for (map<vector<long long>, long long>::iterator it = mp.begin(); it != mp.end(); it++) { if (g == -1) g = it->second; else g = gcd(g, it->second); } if (g == -1) g = 0; cout << g << n ; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t; cin >> t; while (t--) { solve(); } } |
`include "defines.v"
// Do not touch these otherwise the implementation will break
`define dir_east 1'b1
`define dir_west 1'b0
`define dir_north 1'b0
`define dir_south 1'b1
`define wrap_offset 1'b1
module RouteCompute(
input `control_w control_in,
input `addrx_w addrx,
input `addry_w addry,
input `addrx_w addrx_max,
input `addry_w addry_max,
input clk,
input rst,
output resource_go,
output `rmatrix_w rmatrix);
// Break out control signals
wire valid;
wire `addrx_w destx;
wire `addry_w desty;
/*******************
* Control In Format
* [12] Valid
* [11:8] Source
* [7:4] Dest
* [3:0] Age
*******************/
assign valid = control_in[`valid_f];
assign destx = control_in[`destx_f];
assign desty = control_in[`desty_f];
// Tell resource that we are not sending to it
assign resource_go = ((addrx == destx) && (addry == desty)) ? 1'b1 : 1'b0;
// Temporary registers for calculations
reg `addrx_w resultx;
reg `addry_w resulty;
// Assign our actual output
assign rmatrix = {resultx, resulty};
always @(*) begin
/***************
* rmatrix format
* |West|East|South|North|
* | 3 | 2 | 1 | 0 |
* A result of 0 indicates that we are at our destination
***************/
// We are at our destination
if ((destx == addrx) && (desty == addry)) begin
resultx = 2'b00;
resulty = 2'b00;
end else begin
// Choose which direction to take in the x direction
if (destx > addrx) begin
resultx = 2'b01; // East
end else if (destx < addrx) begin
resultx = 2'b10; // West
end else begin
resultx = 2'b00;
end
if (desty > addry) begin
resulty = 2'b10; // South
end else if (desty < addry) begin
resulty = 2'b01; // North
end else begin
resulty = 2'b00;
end
end
end
endmodule
|
#include <bits/stdc++.h> int mod = 1000000007; const int M = INT_MAX; using namespace std; int powb(int x, int y) { int res = 1; x = x % M; while (y > 0) { if (y % 2) res = (res * x) % M; y /= 2; x = (x * x) % M; } return res; } int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } int solve() { int n, t, s = 0, x, s1 = 0, i, j; cin >> n >> t; vector<int> v(2 * n); for (i = 0; i < n; i++) { cin >> x; s1 += x; v[i] = x; v[i + n] = x; } if (s1 <= t) return n; int max = 0; x = 0; for (i = 0; i < 2 * n; i++) { s += v[i]; if (s > t) { s -= v[i]; break; } x++; if (x > max) max = x; } for (i = 1; i < n; i++) { s -= v[i - 1]; x--; for (j = i + x; j < n; j++) { s += v[j]; if (s > t) { s -= v[j]; break; } x++; if (x > max) max = x; } if (j == n - 1) break; } return max; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout << solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, ara[500005], k, ara2[500005]; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); long long l, h, i, j, m, z, t, o, a, b; cin >> n >> k; a = 0; for (i = 0; i < n; i++) cin >> ara[i]; l = 1; h = 10000000000; z = 0; while (l < h) { m = (l + h) / 2; t = 0; for (i = 0; i < n; i++) t += max(m - ara[i], z); if (t <= k) l = m + 1; else h = m - 1; } o = 1; for (j = (max(o, l - 50)); j < l + 50; j++) { t = 0; for (i = 0; i < n; i++) t += max(j - ara[i], z); if (t > k) { if (j == 1) l = j; else l = j - 1; break; } } t = 0; for (i = 0; i < n; i++) { t += max(l - ara[i], z); ara[i] = max(ara[i], l); } for (i = 0; i < n; i++) { if (ara[i] == l && k != t) { ara[i]++; t++; } } l = 1; h = 10000000000; z = 0; while (l < h) { m = (l + h) / 2; t = 0; for (i = 0; i < n; i++) t += max(ara[i] - m, z); if (t <= k) h = m; else l = m + 1; } for (j = h + 50; j >= max(o, h - 50); j--) { t = 0; for (i = 0; i < n; i++) t += max(ara[i] - j, z); if (t > k) { l = j + 1; break; } } t = 0; for (i = 0; i < n; i++) { t += max(ara[i] - l, z); ara[i] = min(ara[i], l); } for (i = 0; i < n; i++) { if (ara[i] == l && k != t) { ara[i]--; t++; } } sort(ara, ara + n); cout << ara[n - 1] - ara[0]; return 0; } |
// Code your design here
module main();
reg [31:0] x, y, newx;
reg real alpha [0:15];
reg real powers [0:16];
reg real currangle, x_out, y_out;
integer i;
reg real AG_CONST, AG;
initial begin
AG_CONST = 1.20;///0.;
AG = 2458;
x = AG;
y = 0;
alpha[0] = 0;
alpha[1] = 31.47292;
alpha[2] = 14.63407;
alpha[3] = 7.19962;
alpha[4] = 3.58565;
alpha[5] = 1.79107;
alpha[6] = 0.89531;
alpha[7] = 0.44763;
alpha[8] = 0.22381;
alpha[9] = 0.11190;
alpha[10] = 0.05595;
alpha[11] = 0.02797;
alpha[12] = 0.01398;
alpha[13] = 0.00699;
alpha[14] = 0.00349;
alpha[15] = 0.00174;
powers[0] = 0.00048828125; //2^-11
powers[1] = 0.; //2^-10
powers[2] = 0.001953125; //2^-9
powers[3] = 0.00390625; //2^-8
powers[4] = 0.; //2^-7
powers[5] = 0.015625; //2^-6
powers[6] = 0.03125; //2^-5
powers[7] = 0.0625; //2^-4
powers[8] = 0.125; //2^-3
powers[9] = 0.25; //2^-2
powers[10] = 0.5; //2^-1
powers[11] = 1.0;
powers[12] = 2.0;
powers[13] = 4.0;
powers[14] = 8.0;
powers[15] = 16.0;
powers[16] = 32.0;
currangle = 90.0;
for (i = 1; i < 15; i = i + 1) begin
if (currangle > 0) begin
while(currangle >= alpha[i]) begin
newx = x + (y>>i);
y = y+ (x >> i);
x = newx;
currangle = currangle - alpha[i];
end
end else begin
while(currangle <= alpha[i]) begin
newx = x - (y>>i);
y = y- (x >> i);
x = newx;
currangle = currangle + alpha[i];
end
end
end
$display("x %f\n", x/2048.0);
$display("y %f\n", y/2048.0);
x_out = 0;
y_out = 0;
for (i = 0; i < 17; i = i + 1) begin
x_out = (x[i]) ? x_out + powers[i] : x_out;
y_out = (y[i]) ? y_out + powers[i] : y_out;
end
$display("x %f\n", x_out);
$display("y %f\n", y_out);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int n, u, v; vector<int> arr[100001]; long double ans = 0.0; long long int siz[100001]{0}; void dfs(int to, int from, int val) { int ret = 1; ans += 1.0 / val; for (auto i : arr[to]) { if (i != from) { dfs(i, to, val + 1); siz[to] += siz[i]; } } } void pre() {} void solve() { cin >> n; for (int i = 0; i < n - 1; i++) { cin >> u >> v; arr[u].push_back(v); arr[v].push_back(u); } dfs(1, 0, 1); cout << setprecision(26) << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); pre(); solve(); } |
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_envelope_generator.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU length counter; building block used by several other APU components. Provides automatic
* duration control for the NES APU waveform channels. Once loaded with a value, it can optionally
* count down and silence the channel when it reaches zero.
***************************************************************************************************/
module apu_envelope_generator
(
input clk_in, // system clock signal
input rst_in, // reset signal
input eg_pulse_in, // 1 clk pulse for every env gen update
input [5:0] env_in, // envelope value (e.g., via $4000)
input env_wr_in, // envelope value write
input env_restart, // envelope restart
output [3:0] env_out // output volume
);
reg [5:0] q_reg;
wire [5:0] d_reg;
reg [3:0] q_cnt, d_cnt;
reg q_start_flag, d_start_flag;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_reg <= 6'h00;
q_cnt <= 4'h0;
q_start_flag <= 1'b0;
end
else
begin
q_reg <= d_reg;
q_cnt <= d_cnt;
q_start_flag <= d_start_flag;
end
end
reg divider_pulse_in;
reg divider_reload;
wire divider_pulse_out;
apu_div #(.PERIOD_BITS(4)) divider(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(divider_pulse_in),
.reload_in(divider_reload),
.period_in(q_reg[3:0]),
.pulse_out(divider_pulse_out)
);
always @*
begin
d_cnt = q_cnt;
d_start_flag = q_start_flag;
divider_pulse_in = 1'b0;
divider_reload = 1'b0;
// When the divider outputs a clock, one of two actions occurs: If the counter is non-zero, it
// is decremented, otherwise if the loop flag is set, the counter is loaded with 15.
if (divider_pulse_out)
begin
divider_reload = 1'b1;
if (q_cnt != 4'h0)
d_cnt = q_cnt - 4'h1;
else if (q_reg[5])
d_cnt = 4'hF;
end
// When clocked by the frame counter, one of two actions occurs: if the start flag is clear,
// the divider is clocked, otherwise the start flag is cleared, the counter is loaded with 15,
// and the divider's period is immediately reloaded.
if (eg_pulse_in)
begin
if (q_start_flag == 1'b0)
begin
divider_pulse_in = 1'b1;
end
else
begin
d_start_flag = 1'b0;
d_cnt = 4'hF;
end
end
if (env_restart)
d_start_flag = 1'b1;
end
assign d_reg = (env_wr_in) ? env_in : q_reg;
// The envelope unit's volume output depends on the constant volume flag: if set, the envelope
// parameter directly sets the volume, otherwise the counter's value is the current volume.
assign env_out = (q_reg[4]) ? q_reg[3:0] : q_cnt;
endmodule
|
// File: RAMConcur_TBV.v
// Generated by MyHDL 0.10
// Date: Wed Jun 27 01:12:16 2018
`timescale 1ns/10ps
module RAMConcur_TBV (
);
// Verilog Only Testbench for `RAMConcur`
reg [3:0] addr = 0;
wire [3:0] dout;
reg clk = 0;
reg [3:0] din = 0;
reg writeE = 0;
reg [3:0] RAMConcur0_0_1_2_memory [0:4-1];
initial begin: INITIALIZE_RAMCONCUR0_0_1_2_MEMORY
integer i;
for(i=0; i<4; i=i+1) begin
RAMConcur0_0_1_2_memory[i] = 0;
end
end
always @(posedge clk) begin: RAMCONCUR_TBV_RAMCONCUR0_0_1_2_WRITEACTION
if (writeE) begin
RAMConcur0_0_1_2_memory[addr] <= din;
end
end
assign dout = RAMConcur0_0_1_2_memory[addr];
initial begin: RAMCONCUR_TBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: RAMCONCUR_TBV_STIMULES
integer i;
for (i=0; i<1; i=i+1) begin
@(negedge clk);
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
writeE <= 1'b1;
addr <= i;
case (i)
0: din <= 3;
1: din <= 2;
2: din <= 1;
default: din <= 0;
endcase
end
for (i=0; i<1; i=i+1) begin
@(posedge clk);
writeE <= 1'b0;
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
addr <= i;
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
writeE <= 1'b1;
addr <= i;
case ((-i))
0: din <= 3;
1: din <= 2;
2: din <= 1;
default: din <= 0;
endcase
end
for (i=0; i<1; i=i+1) begin
@(posedge clk);
writeE <= 1'b0;
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
addr <= i;
end
$finish;
end
always @(posedge clk) begin: RAMCONCUR_TBV_PRINT_DATA
$write("%h", addr);
$write(" ");
$write("%h", din);
$write(" ");
$write("%h", writeE);
$write(" ");
$write("%h", dout);
$write(" ");
$write("%h", clk);
$write("\n");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool prime(long long x) { if (x == 2) return 1; if (x % 2 == 0) return 0; for (long long j = 3; j * j <= x; j += 2) { if (x % j == 0) return 0; } return 1; } int main() { long long t; cin >> t; while (t--) { long long n, m; cin >> n >> m; if (n - m > 1) { cout << NO << endl; } else { if (prime(n + m)) { cout << YES << endl; } else { cout << NO << endl; } } } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, m = 0, c = 0; scanf( %d , &n); while (n--) { scanf( %d%d , &a, &b); if (a > b) { m++; } else if (a < b) { c++; } } if (m > c) { printf( Mishka ); } else if (m < c) { printf( Chris ); } else { printf( Friendship is magic!^^ ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INFLL = 2 * (long long)1e18 + 100; const long long INFINT = 2 * (long long)1e9 + 100; const double PI = atan(1) * 4; const double EPS = 1e-6; const long long SEED = (long long)1e3 + 7; const long long MOD = 998244353; const long long NMAX = (long long)1e5 + 5; vector<long long> v; long long sum[NMAX]; long long solve(long long n) { vector<long long> temp; for (long long i = 1; i <= n; i++) temp.push_back(i); do { for (auto i : temp) v.push_back(i); } while (next_permutation(temp.begin(), temp.end())); long long sol = 0; for (long long i = 1; i <= v.size(); i++) { sum[i] = sum[i - 1] + v[i - 1]; if (i >= n) { long long here = sum[i] - sum[i - n]; if (here == n * (n + 1) / 2) sol++; } } return sol; } long long fact(long long x) { if (x == 1) return 1; return x * fact(x - 1) % MOD; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; long long sol = n * fact(n) % MOD; long long prev = 1; for (long long i = n; i >= 2; i--) { prev = prev * i % MOD; sol = sol - prev; if (sol < 0) sol += MOD; } cout << sol; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, x, y, a, b; int main() { cin >> n >> m >> x >> y >> a >> b; long long W = min(n, (m * a) / b); long long divA = a, divB = b; for (long long i = 2; i * i <= divB; i++) { while (divB % i == 0) { if (divA % i == 0) { divA /= i; } divB /= i; } } if (divA % divB == 0) divA /= divB; W -= (W % divA); long long H = (W * b) / a; long long x1 = x - ((W + 1) / 2); long long y1 = y - ((H + 1) / 2); long long x2 = x1 + W; long long y2 = y1 + H; if (x2 > n) { x2 = n; x1 = x2 - W; } if (x1 < 0) { x1 = 0; x2 = W; } if (y2 > m) { y2 = m; y1 = y2 - H; } if (y1 < 0) { y1 = 0; y2 = H; } W = x2 - x1; H = y2 - y1; cout << x1 << << y1 << << x2 << << y2 << endl; } |
/* Title: Homework 1
* Description: Homework assignment #1 for EET-4020
* Author: Sergiy Kolodyazhnyy
* Date: 2/23/2017
*
*/
/* #1: Create your own 2-input verilog gates
* called my_or,my_and,and my_not from 2-input nand gates.
*/
module my_and(C,A,B);
// Output definitions
output C;
input A,B;
wire W1;
// AND gate implemented with NAND gates is
// effectively two nand gates, daisy chained.
nand input_nand(W1,A,B);
nand output_nand(C,W1,W1);
endmodule
module my_or(C,A,B);
// input and output definitions
output C;
input A,B;
wire A_out;
wire B_out;
// or gate can be implemented via two
// not gates implemented with nand, and output of each
// sent to another nand
nand input_nand1(A_out,A,A);
nand input_nand2(B_out,B,B);
nand output_nand(C,A_out,B_out);
endmodule
module my_not(C,A);
output C;
input A;
nand output_nand(C,A,A);
endmodule
/*
* #2: Create a 2-input xorg gate, built
* from the gates you designed in problem #1
*/
module my_xor(Z,X,Y);
//output and input definitions
output Z;
input X,Y;
wire Y_not,X_not,x_and_Yprime,Y_and_Xprime;
// instantiate the gates
my_not mn1(Y_not,Y);
my_not mn2(X_not,X);
my_and ma1(X_and_Yprime,mn1,X);
my_and ma2(Y_and_Xprime,mn2,Y);
my_or mo(Z,X_and_Yprime,Y_and_Xprime);
endmodule
/* #3: Design a 2-to-1 multiplexer using bufif0 and bufif1 gates
*
*/
module mux_2to1(OUT,IN0,IN1,S0);
output OUT;
input IN0,IN1,S0;
wire S0_not;
not(S0_not,S0);
bufif0 b0(OUT,IN0,S0_not);
bufif1 b1(OUT, IN1,S0);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_comm_vpi.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor () ////
//// Gyorgy Jeney () ////
//// Nathan Yawn () ////
//// Raul Fajardo () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2008 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_comm_vpi.v,v $
// Revision 1.2.1 2009/09/08 14:57 rfajardo
// Changed clock and reset outputs to inputs for minsoc
//
// $Log: dbg_comm_vpi.v,v $
// Revision 1.2 2009/05/17 20:55:57 Nathan
// Changed email address to opencores.org
//
// Revision 1.1 2008/07/26 17:33:20 Nathan
// Added debug comm module for use with VPI / network communication.
//
// Revision 1.1 2002/03/28 19:59:54 lampret
// Added bench directory
//
// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
// First import.
//
// Revision 1.3 2001/09/24 14:06:13 mohor
// Changes connected to the OpenRISC access (SPR read, SPR write).
//
// Revision 1.2 2001/09/20 10:10:30 mohor
// Working version. Few bugs fixed, comments added.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
//
//
//
//
`include "timescale.v"
`define JP_PORT "4567"
`define TIMEOUT_COUNT 6'd20 // 1/2 of a TCK clock will be this many SYS_CLK ticks. Must be less than 6 bits.
module dbg_comm_vpi (
SYS_CLK,
P_TMS,
P_TCK,
P_TRST,
P_TDI,
P_TDO
);
//parameter Tp = 20;
input SYS_CLK;
output P_TMS;
output P_TCK;
output P_TRST;
output P_TDI;
input P_TDO;
reg [4:0] memory; // [0:0];
wire P_TCK;
wire P_TRST;
wire P_TDI;
wire P_TMS;
wire P_TDO;
reg [3:0] in_word_r;
reg [5:0] clk_count;
// Handle commands from the upper level
initial
begin
in_word_r = 5'b0;
memory = 5'b0;
$jp_init(`JP_PORT);
#5500; // Wait until reset is complete
while(1)
begin
#1;
$jp_in(memory); // This will not change memory[][] if no command has been sent from jp
if(memory[4]) // was memory[0][4]
begin
in_word_r = memory[3:0];
memory = memory & 4'b1111;
clk_count = 6'b000000; // Reset the timeout clock in case jp wants to wait for a timeout / half TCK period
end
end
end
// Send the output bit to the upper layer
always @ (P_TDO)
begin
$jp_out(P_TDO);
end
assign P_TCK = in_word_r[0];
assign P_TRST = in_word_r[1];
assign P_TDI = in_word_r[2];
assign P_TMS = in_word_r[3];
// Send timeouts / wait periods to the upper layer
always @ (posedge SYS_CLK)
begin
if(clk_count < `TIMEOUT_COUNT) clk_count[5:0] = clk_count[5:0] + 1;
else if(clk_count == `TIMEOUT_COUNT) begin
$jp_wait_time();
clk_count[5:0] = clk_count[5:0] + 1;
end
// else it's already timed out, don't do anything
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); vector<int> A(n); for (int& a : A) scanf( %d , &a); sort(A.begin(), A.end()); int m = A[n - 1]; vector<bool> B(m + 2); for (int a : A) { if (a > 1 && !B[a - 1]) B[a - 1] = true; else if (!B[a]) B[a] = true; else if (!B[a + 1]) B[a + 1] = true; } printf( %lu n , count(B.begin(), B.end(), true)); } |
#include <bits/stdc++.h> using namespace std; int n, m; string s; string change(string s, int l, int r, char c1, char c2) { for (int i = l - 1; i < r; i++) { if (s[i] == c1) { s[i] = c2; } } return s; } int main() { cin >> n >> m; cin >> s; for (int i = 0; i < m; i++) { int l, r; char c1, c2; cin >> l >> r >> c1 >> c2; s = change(s, l, r, c1, c2); } cout << s; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221A_SYMBOL_V
`define SKY130_FD_SC_HD__O221A_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o221a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221A_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e3 + 20; bool A[maxn][maxn]; int d[maxn]; vector<pair<int, int> > ans; void solve(set<int> &a) { if ((int)a.size() == 1) { int k = *a.begin(); for (int i = 0; i < k + 1; i++) for (int j = i + 1; j < k + 1; j++) A[i][j] = A[j][i] = 1; return; } set<int> tmp; int k = *a.rbegin(), mn = *a.begin(); for (auto x : a) if (x != k) tmp.insert(k - x); solve(tmp); for (int i = 0; i <= k - mn; i++) for (int j = i + 1; j <= k - mn; j++) A[i][j] = !A[i][j], A[j][i] = !A[j][i]; for (int i = 0; i <= k - mn; i++) for (int j = k - mn + 1; j <= k; j++) A[i][j] = A[j][i] = 1; for (int i = k - mn + 1; i <= k; i++) for (int j = i + 1; j <= k; j++) A[i][j] = A[j][i] = 1; } int main() { int m; cin >> m; set<int> tmp; for (int i = 0; i < m; i++) cin >> d[i], tmp.insert(d[i]); solve(tmp); for (int i = 0; i <= d[m - 1]; i++) for (int j = i + 1; j <= d[m - 1]; j++) if (A[i][j]) ans.push_back({i, j}); printf( %d n , (int)ans.size()); for (auto x : ans) printf( %d %d n , x.first + 1, x.second + 1); } |
#include <bits/stdc++.h> using namespace std; int sdf[30] = {4, 22, 27, 58, 85, 94, 121, 166, 202, 265, 274, 319, 346, 355, 378, 382, 391, 438, 454, 483, 517, 526, 535, 562, 576, 588, 627, 634, 636, 645}; long long int a[71720], b, c, d, n, m, i, j, k, sum, sumend; bool cmp(int a, int b) { return a > b; } int gcd(int a, int b) { if (!b) return a; return gcd(b, a % b); } int gqt(int n) { if (!n || n) return 0; if (n == 2) return 1; for (int i = 3; i <= sqrt(n); i++) if (n % i == 0) return 0; return 1; } int main() { cin >> n; for (i = 1; i <= n; i++) cin >> a[i]; sum = a[n]; sort(a + 1, a + n + 1); sumend = a[n]; cout << (sumend ^ sum) << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3_2_V
`define SKY130_FD_SC_HS__NOR3_2_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3_2 (
Y ,
A ,
B ,
C ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3_2_V
|
module top;
reg pass;
real rarr [1:0];
reg [2:0] arr [1:0];
integer index;
integer base;
reg [3*8:1] res;
initial begin
pass = 1'b1;
rarr[0] = 1.0;
rarr[1] = 2.0;
arr[0] = 1;
arr[1] = 2;
base = 0;
// Check an in range word select.
index = 0;
$sformat(res, "%3.1f", rarr[index+base]);
if (res != "1.0") begin
$display("Failed &A<> (real, index=0, thr.), expected 1.0, got %s", res);
pass = 1'b0;
end
$sformat(res, "%3.1f", rarr[index]);
if (res != "1.0") begin
$display("Failed &A<> (real, index=0, sig.), expected 1.0, got %s", res);
pass = 1'b0;
end
if (rarr[index] != 1.0) begin
$display("Failed var select (real, index=0), expected 1.0");
pass = 1'b0;
end
$sformat(res, "%3b", arr[index+base]);
if (res != "001") begin
$display("Failed &A<> (reg, index=0, thr.), expected 001, got %s", res);
pass = 1'b0;
end
$sformat(res, "%3b", arr[index]);
if (res != "001") begin
$display("Failed &A<> (reg, index=0, sig.), expected 001, got %s", res);
pass = 1'b0;
end
if (arr[index] != 3'b001) begin
$display("Failed var select (reg, index=0), expected 3'b001");
pass = 1'b0;
end
// Check an undefined array word select.
index = 'bx;
$sformat(res, "%3.1f", rarr[index+base]);
if (res != "0.0") begin
$display("Failed &A<> (real, index=x, thr.), expected 0.0, got %s", res);
pass = 1'b0;
end
$sformat(res, "%3.1f", rarr[index]);
if (res != "0.0") begin
$display("Failed &A<> (real, index=x, sig.), expected 0.0, got %s", res);
pass = 1'b0;
end
if (rarr[index] != 0.0) begin
$display("Failed var select (real, index=x), expected 0.0");
pass = 1'b0;
end
$sformat(res, "%3b", arr[index+base]);
if (res != "xxx") begin
$display("Failed &A<> (reg, index=x, thr.), expected xxx, got %s", res);
pass = 1'b0;
end
$sformat(res, "%3b", arr[index]);
if (res != "xxx") begin
$display("Failed &A<> (reg, index=x, sig.), expected xxx, got %s", res);
pass = 1'b0;
end
if (arr[index] != 3'bxxx) begin
$display("Failed var select (reg, index=x), expected 3'bxxx");
pass = 1'b0;
end
// Check a before the array word select.
index = -1;
$sformat(res, "%3.1f", rarr[index+base]);
if (res != "0.0") begin
$display("Failed &A<> (real, index=-1, thr.), expected 0.0, got %s", res);
pass = 1'b0;
end
$sformat(res, "%3.1f", rarr[index]);
if (res != "0.0") begin
$display("Failed &A<> (real, index=-1, sig.), expected 0.0, got %s", res);
pass = 1'b0;
end
if (rarr[index] != 0.0) begin
$display("Failed var select (real, index=-1), expected 0.0");
pass = 1'b0;
end
$sformat(res, "%3b", arr[index+base]);
if (res != "xxx") begin
$display("Failed &A<> (reg, index=-1, thr.), expected xxx, got %s", res);
pass = 1'b0;
end
$sformat(res, "%3b", arr[index]);
if (res != "xxx") begin
$display("Failed &A<> (reg, index=-1, sig.), expected xxx, got %s", res);
pass = 1'b0;
end
if (arr[index] != 3'bxxx) begin
$display("Failed var select (reg, index=-1), expected 3'bxxx");
pass = 1'b0;
end
// Check an after the array word select.
index = 2;
$sformat(res, "%3.1f", rarr[index+base]);
if (res != "0.0") begin
$display("Failed &A<> (real, index=2, thr.), expected 0.0, got %s", res);
pass = 1'b0;
end
$sformat(res, "%3.1f", rarr[index]);
if (res != "0.0") begin
$display("Failed &A<> (real, index=2, sig.), expected 0.0, got %s", res);
pass = 1'b0;
end
if (rarr[index] != 0.0) begin
$display("Failed var select (real, index=2), expected 0.0");
pass = 1'b0;
end
$sformat(res, "%3b", arr[index+base]);
if (res != "xxx") begin
$display("Failed &A<> (reg, index=2, thr.), expected xxx, got %s", res);
pass = 1'b0;
end
$sformat(res, "%3b", arr[index]);
if (res != "xxx") begin
$display("Failed &A<> (reg, index=2, sig.), expected xxx, got %s", res);
pass = 1'b0;
end
if (arr[index] != 3'bxxx) begin
$display("Failed var select (reg, index=2), expected 3'bxxx");
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int n1, n2, n3, n4, n5, n6, n7; int a, b, c; void doA(int i) { if (n1 >= i) n1 -= i; else n1 = 0; } void doB(int i) { if (n2 >= i) n2 -= i; else { doA(i - n2); n2 = 0; } } void doC(int i) { if (n3 >= i) n3 -= i; else { doB(i - n3); n3 = 0; } } void work() { int ans = 0; ans = n7; ans += n6; doA(n6); ans += n5; doB(n5); if (c < a + b) { ans += n4; doC(n4); int ANS = 0x3fffffff; for (int i = 0; i <= n3; i++) { int N1 = n1, N2 = n2, N3 = n3; int j = n3 - i; int now = max(i, j); if (i > j) { doB(i - j); doA(i - j); } else doB(j - i); now += max((n2 + 1) / 2, (n1 + n2 + 2) / 3); ANS = min(ANS, now); n1 = N1; n2 = N2; n3 = N3; } cout << ans + ANS << endl; } else { int ANS = 0x3fffffff; for (int i = n4; i <= n3 + n4; i++) { int N1 = n1, N2 = n2, N3 = n3; int j = n3 + n4 - i; int now = max(i, j); if (i > j) { doB(i - j); doA(i - j); } else doB(j - i); now += max((n2 + 1) / 2, (n1 + n2 + 2) / 3); ANS = min(ANS, now); n1 = N1; n2 = N2; n3 = N3; } cout << ans + ANS << endl; } } int main() { cin >> n; cin >> a >> b >> c; if (c < b) swap(b, c); if (b < a) swap(a, b); if (c < b) swap(b, c); int x1 = min(a + b, c), x2 = max(a + b, c); for (int i = 1; i <= n; i++) { int t; scanf( %d , &t); if (t > a + b + c) { cout << -1 << endl; return 0; } if (t <= a) n1++; else if (t <= b) n2++; else if (t <= x1) n3++; else if (t <= x2) n4++; else if (t <= a + c) n5++; else if (t <= b + c) n6++; else n7++; } work(); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:34:18 10/12/2013
// Design Name:
// Module Name: Logica_Bola
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Logica_Bola(
input clock,
input reset,
input actualizar_posicion,
input revisar_bordes,
input choque_barra,
output reg [9:0] ball_x,
output reg [8:0] ball_y );
reg dir_x_positiva;
reg dir_y_positiva;
initial
begin
dir_x_positiva <= 1'b1;
dir_y_positiva <= 1'b1;
ball_x <= `X_INICIAL_BOLA;
ball_y <= `Y_INICIAL_BOLA;
end
always @(posedge clock or posedge reset)
begin
if(reset)
begin
dir_x_positiva <= 1'b1;
dir_y_positiva <= 1'b1;
ball_x <= `X_INICIAL_BOLA;
ball_y <= `Y_INICIAL_BOLA;
end
else
begin
if(actualizar_posicion)
begin
if(dir_x_positiva)
ball_x <= ball_x + `VELOCIDAD_BOLA; //Hacia derecha
else
ball_x <= ball_x - `VELOCIDAD_BOLA; //Hacia izquierda
if(dir_y_positiva)
ball_y <= ball_y + `VELOCIDAD_BOLA; //Hacia abajo
else
ball_y <= ball_y - `VELOCIDAD_BOLA; //Hacia arriba
end
if(revisar_bordes)
begin
if ( ball_x > `LIMITE_DER_X_BOLA )
begin
ball_x <= `LIMITE_DER_X_BOLA;
dir_x_positiva <= 1'b0;
end
else if(choque_barra)
begin
ball_x <= `X_INICIAL_BARRA + `ANCHO_BARRA;
dir_x_positiva <= 1'b1;
end
else
begin
ball_x <= ball_x;
dir_x_positiva <= dir_x_positiva;
end
if( ball_y < `LIMITE_SUP_Y_BOLA )
begin
ball_y <= `LIMITE_SUP_Y_BOLA;
dir_y_positiva <= 1'b1;
end
else if( ball_y > `LIMITE_INF_Y_BOLA )
begin
ball_y <= `LIMITE_INF_Y_BOLA;
dir_y_positiva <= 1'b0;
end
else
begin
ball_y <= ball_y;
dir_y_positiva <= dir_y_positiva;
end
end
end /** Fin else NO reset */
end /** Fin always */
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 10, M = 1e6 + 7, K = 200, p = 1e9 + 7; int n, e[N], s[M], wf[K], q[N][K], f[N][N], ans[N][M]; bitset<40> op, wq[N][M]; unordered_map<bitset<40>, int> rt[N]; inline int read() { int num = 0; char g = getchar(); while (g < 48 || 57 < g) g = getchar(); while (47 < g && g < 58) num = (num << 1) + (num << 3) + g - 48, g = getchar(); return num; } inline long long pows(long long u, int v) { long long ans = 1; while (v > 0) { if (v & 1) ans = ans * u % p; u = u * u % p, v = v >> 1; } return ans; } inline void find(int u) { q[u][0] = 0; int os = 0, of = 0; for (int i = 0; i < (1 << n); i++) if (s[i] == u) q[u][++q[u][0]] = i, wf[i] = ++os; for (int i = 1; i <= e[u - 1]; i++) { if (!ans[u - 1][i]) continue; for (int h = 1; h < (1 << n); h++) { long long opq = 1; for (int c = 0; c < n; c++) if ((1 << c) & h) opq = opq * f[u][c + 1] % p; else opq = opq * (1 - f[u][c + 1] + p) % p; bitset<40> c = wq[u - 1][i], hc = op; bool tg = 0; for (int x = 1; x <= q[u - 1][0]; x++) { if (c[x] == 1) { for (int t = 0; t < n; t++) if (((1 << t) & h) && (!(q[u - 1][x] & (1 << t)))) { hc[wf[q[u - 1][x] | (1 << t)]] = 1, tg = 1; } } } if (!tg) continue; int pos; if (rt[u][hc] == 0) rt[u][hc] = ++of, e[u]++, wq[u][e[u]] = hc; pos = rt[u][hc]; ans[u][pos] = (ans[u][pos] + opq * ans[u - 1][i]) % p; } } } int main() { n = read(); for (int i = 0; i <= (1 << n); i++) s[i] = __builtin_popcount(i); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) f[i][j] = read() * pows(100, p - 2) % p; q[0][0] = 1; e[0] = 1, ans[0][1] = 1, wq[0][1][1] = 1; for (int i = 1; i <= n; i++) find(i); cout << ans[n][1] << endl; return 0; } |
#include <bits/stdc++.h> const int maxn = 4e5 + 10; const int maxm = 2e5 + 10; const int inf = 0x3f3f3f3f; const long long mod = 1e9 + 7; const double eps = 1e-7; using namespace std; long long cnt[25][25], dp[1 << 21]; int n; vector<int> col[25]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { int x; cin >> x; col[x].push_back(i); } for (int i = 1; i <= 20; ++i) for (int j = 1; j <= 20; ++j) if (i != j) { if (!col[i].size() || !col[j].size()) continue; int l = 0; for (int k = 0; k < col[i].size(); ++k) { while (true) { if (l == col[j].size() - 1 || col[j][l + 1] > col[i][k]) break; l++; } if (col[j][l] < col[i][k]) cnt[i][j] += l + 1; } } memset(dp, 0x3f, sizeof dp); dp[0] = 0; for (int S = 0; S < 1 << 20; ++S) { for (int i = 0; i < 20; ++i) if (!(S >> i & 1)) { long long sum(0); for (int j = 0; j < 20; ++j) if (S >> j & 1) sum += cnt[j + 1][i + 1]; dp[S | (1 << i)] = min(dp[S | (1 << i)], dp[S] + sum); } } cout << dp[(1 << 20) - 1] << endl; return ~~(0 - 0); } |
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