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#include <bits/stdc++.h> using namespace std; long long n, s, x, y, nb; vector<pair<long long, long long> > t, v; long long dp[102]; bool cmp(pair<long long, long long> a, pair<long long, long long> b) { return a.first + a.second > b.first + b.second; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> s; for (long long i = 0; i < n; i++) { cin >> x >> y; if (y >= 0) { t.push_back(make_pair(x, y)); } else { v.push_back(make_pair(y, x)); } } sort(t.begin(), t.end()); for (long long i = 0; i < t.size(); i++) { if (t[i].first > s) break; s += t[i].second; nb++; } sort(v.begin(), v.end(), cmp); n = v.size(); for (long long i = 1; i < n + 1; i++) dp[i] = -1; dp[0] = s; for (long long i = 0; i < n; i++) { for (long long j = i + 1; j > 0; j--) { if (dp[j - 1] >= v[i].second) dp[j] = max(dp[j], dp[j - 1] + v[i].first); } } long long i; for (i = n; dp[i] == -1; i--) ; cout << nb + i << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> T Bitcnt(T a) { int sum = 0; while (a) { if (a & 1) sum++; a /= 2; } return sum; } template <class T> T Max3(T a, T b, T c) { return max(a, max(b, c)); } template <class T> T Lcm(T a, T b) { T tmp = __gcd(a, b); return (a / tmp) * b; } template <class T> T Pow(T a, T b) { T ans = 1; T base = a; while (b) { if (b & 1) ans = (ans * base); base = (base * base); b /= 2; } return ans; } long long Bigmod(long long a, long long b) { long long res = 1; long long pw = a % 1000000007LL; while (b > 0) { if (b & 1) res = (res * pw) % 1000000007LL; pw = (pw * pw) % 1000000007LL; b /= 2; } return res; } int a_x[] = {1, -1, 0, 0}; int a_y[] = {0, 0, 1, -1}; long long X, Y; void extend_euclid(long long a, long long b) { if (b == 0) { X = a; Y = 0; return; } extend_euclid(b, a % b); long long x, y; x = Y; y = X - (a / b) * Y; X = x; Y = y; } long long inverse_modulo(long long a, long long b) { extend_euclid(a, b); return (X + 1000000007LL) % 1000000007LL; } int main() { long long x; cin >> x; if (x == 2) { cout << -1; return 0; } if (x % 2 == 0) { long long b = (x / 2) * (x / 2) - 1; long long c = b + 2; cout << b << << c; return 0; } else { long long b = (x * x - 1) / 2; long long c = (x * x + 1) / 2; if (b <= 0 || c <= 0) { cout << -1; return 0; } cout << b << << c << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; template <class T> typename T::value_type arr_sum(const T& v, int n) { typename T::value_type sum = 0; for (int i = (0); i < (n); ++i) sum += v[i]; return sum; } struct Sync_stdio { Sync_stdio() { cin.tie(NULL); ios_base::sync_with_stdio(false); } } _sync_stdio; int main() { int n; cin >> n; if (n == 1) { cout << 0; return 0; } list<int> a; a.push_back(0); for (int i = (0); i < (n); ++i) { int x; cin >> x; a.push_back(x); } a.push_back(0); auto i = a.begin(); auto j = i; ++j; auto k = j; ++k; long long res = 0; while (k != a.end()) { if (*i >= *j && *j <= *k) { res += min(*i, *k); a.erase(j); j = i; --i; } else { ++i; ++j; ++k; } } i = a.begin(); j = i; ++j; k = j; ++k; a.pop_back(); a.pop_front(); while (a.size() >= 3) { if (a.front() < a.back()) { res += a.front(); a.pop_front(); } else { res += a.back(); a.pop_back(); } } cout << res; } |
#include <bits/stdc++.h> using namespace std; int n, m, k; long long pow2(int x) { if (x == 0) return 1; if (x == 1) return 2; long long h = pow2(x / 2); return (h * h * (x & 1 ? 2 : 1)) % 1000000009; } int main() { cin >> n >> m >> k; int x = n / k; int y = n % k; int z = m - (x * (k - 1) + y); if (z > 0) { long long v = ((pow2(z + 1) + 1000000009 - 2 - z) * k) % 1000000009; long long res = (v + m) % 1000000009; cout << res << endl; } else { cout << m << endl; } } |
#include <bits/stdc++.h> using namespace std; string name[105], body[105]; int n; string s; int d[105]; map<string, int> macro_id; int add(string& s, int& ptr); void go(int k); int un(string& s, int& ptr) { if (s[ptr] == ( ) { ptr++; int r = add(s, ptr); if (r & 2) r ^= 2; if (r & 4) r ^= 4; ptr++; return r; } string id = ; while (ptr < s.size() && (isalpha(s[ptr]) || isdigit(s[ptr]))) { id += s[ptr++]; } if (macro_id.count(id)) { int k = macro_id[id]; go(k); return d[k]; } else { return 0; } } int mul(string& s, int& ptr) { int ret = un(s, ptr); int cnt = 1; char last_op = * ; bool f = true; while (ptr < s.size() && (s[ptr] == * || s[ptr] == / )) { if (f && (ret & 2)) { ret |= 1; } f = false; last_op = s[ptr]; ptr++; int next = un(s, ptr); if (next & 4) ret |= 4; if (next & 1) ret |= 1; if (next & 2) ret |= 1; if (last_op == / && (next & 4)) ret |= 1; cnt++; } if (cnt > 1) ret |= 4; return ret; } int add(string& s, int& ptr) { int ret = mul(s, ptr); int cnt = 1; char last_op = + ; while (ptr < s.size() && (s[ptr] == + || s[ptr] == - )) { last_op = s[ptr]; ptr++; int next = mul(s, ptr); if (next & 2) ret |= 2; if (next & 1) ret |= 1; if (last_op == - && (next & 2)) ret |= 1; cnt++; } if (cnt > 1) { if (ret & 4) ret ^= 4; ret |= 2; } return ret; } void go(int k) { if (d[k] != -1) { return; } string str = body[k]; int ptr = 0; int code = add(str, ptr); d[k] = code; } int main() { scanf( %d n , &n); for (int i = 0; i < int(n); i++) { getline(cin, s); while (s[0] == ) s.erase(0, 1); s.erase(0, 1); while (s[0] == ) s.erase(0, 1); s.erase(0, 7); while (s[0] == ) s.erase(0, 1); int p = s.find( ); name[i] = s.substr(0, p); s.erase(0, p + 1); for (int j = 0; j < int(s.size()); j++) { if (s[j] != ) { body[i] += s[j]; } } macro_id[name[i]] = i; } getline(cin, s); for (int j = 0; j < int(s.size()); j++) { if (s[j] != ) { body[n] += s[j]; } } for (int i = 0; i < int(n + 1); i++) { d[i] = -1; } go(n); if (d[n] & 1) { printf( Suspicious n ); } else { printf( OK n ); } return 0; } |
// bsg_rp_clk_gen_coarse_delay_element
//
// o contains controllably delayed signal
//
// module bsg_clk_gen_coarse_delay_element #(parameter `BSG_INV_PARAM(start_tap_p))
//
module bsg_rp_clk_gen_atomic_delay_tuner
(input i
, input sel_i
, input we_async_i
, input we_inited_i // basically says we_async_i should have successfully passed through
// the generated clock's synchronizers; i.e. the generated clock is
// running and the bsg_tag_slave and client have been initialized
, input async_reset_neg_i
, output we_o
, output o
);
wire [1:0] sel_r;
wire [8:0] signal;
wire we_o_pre_buf;
assign signal[0] = i;
// synopsys rp_group (bsg_clk_gen_adt)
// synopsys rp_fill (13 2 LX)
CKND2BWP I1 (.I(signal[0]), .ZN(signal[1]) );
CKND2BWP I2 (.I(signal[1]), .ZN(signal[2]) );
CKND4BWP I2a (.I(signal[1]), .ZN() );
CKND2BWP I3 (.I(signal[2]), .ZN(signal[3]) );
CKND2BWP I4 (.I(signal[3]), .ZN(signal[4]) );
CKND4BWP I4a (.I(signal[3]), .ZN() );
CKND2BWP I4b (.I(signal[3]), .ZN() ); // this is an extra gate because
// we are not attaching to the mux
// cap tries to match that of mux input
CKND2BWP I5 (.I(signal[4]), .ZN(signal[5]) );
CKND2BWP I6 (.I(signal[5]), .ZN(signal[6]) );
CKND4BWP I6a (.I(signal[5]), .ZN() );
CKND2BWP I7 (.I(signal[6]), .ZN(signal[7]) );
CKND2BWP I8 (.I(signal[7]), .ZN(signal[8]) );
CKND4BWP I8a (.I(signal[7]), .ZN() );
CKND3BWP I8b (.I(signal[7]), .ZN() ); // fudge factor capacitance
// synopsys rp_fill (0 1 RX)
wire zero_bit;
MUX4ND4BWP M1 ( .I0(signal[8])
,.I1(signal[6])
,.I2(zero_bit)
,.I3(signal[0])
,.S0(sel_r[0])
,.S1(sel_r[1])
,.ZN(o )
);
wire [1:0] mux_lo;
wire we_i_sync, we_i_sync_sync, we_i_sync_sync_nand;
// synopsys rp_fill (0 0 RX)
// this gate picks input 01 when async reset is low, initializing the oscillator
IND2D2BWP NB (.A1(sel_r[0]), .B1(async_reset_neg_i), .ZN(sel_r[1]));
TIELBWP ZB (.ZN(zero_bit));
DFCND4BWP sel_r_reg_0 (.D(mux_lo[0]), .CP(o) ,.CDN(async_reset_neg_i), .Q(sel_r[0]), .QN());
//LHCND4BWP sel_r_latch_0 (.D(mux_lo[0]), .E(o) ,.CDN(async_reset_neg_i), .Q(sel_r[0]), .QN());
// 40nm: non-inverting mux 32.5ps + load S->Z
// 40nm: inverting mux 43ps + load S->ZN
// inputs are reversed because select is inverted
// we_i&we_inited_i=1 -> new value (I0)
// we_i&we_inited-i=0 -> use value in register (I1)
MUX2D1BWP MX1 ( .I0(sel_i), .I1(sel_r[0]), .S(we_i_sync_sync_nand), .Z(mux_lo[0]));
// nand 10ps versus 22ps
ND2D1BWP bsg_we_nand (.A1(we_i_sync_sync), .A2(we_inited_i), .ZN(we_i_sync_sync_nand));
// synchronizer flops; negative edge triggered
//DFND1BWP bsg_SYNC_2_r (.D(we_i_sync), .CPN(o), .Q(we_i_sync_sync), .QN());
//DFND1BWP bsg_SYNC_1_r (.D(we_async_i), .CPN(o), .Q(we_i_sync), .QN());
DFNCND1BWP bsg_SYNC_2_r (.D(we_i_sync), .CPN(o), .CDN(async_reset_neg_i), .Q(we_i_sync_sync), .QN());
DFNCND1BWP bsg_SYNC_1_r (.D(we_async_i), .CPN(o), .CDN(async_reset_neg_i), .Q(we_i_sync), .QN());
// drive we signal to next CDT; minimize capacitive load on critical we_i path
INVD0BWP we_o_pre (.I(we_i_sync_sync_nand), .ZN(we_o_pre_buf));
BUFFD4BWP we_o_buf (.I(we_o_pre_buf),. Z(we_o));
// synopsys rp_endgroup (bsg_clk_gen_adt)
endmodule
`BSG_ABSTRACT_MODULE(bsg_rp_clk_gen_atomic_delay_tuner)
|
#include <bits/stdc++.h> using namespace std; class Edge { public: int neighbour; int edge_number; int weight; Edge(int neigh, int edge_no, int weig) { neighbour = neigh; edge_number = edge_no; weight = weig; } }; int main() { int n, m; cin >> n >> m; vector<vector<Edge> > adj_list(n + 1); for (int i = 1; i <= m; i++) { int vertex1, vertex2, weight; cin >> vertex1 >> vertex2 >> weight; Edge temp = Edge(vertex2, i, weight); adj_list[vertex1].push_back(temp); temp = Edge(vertex1, i, weight); adj_list[vertex2].push_back(temp); } int source; cin >> source; vector<bool> check_list(n + 1, false); priority_queue<pair<long long int, int> > pq; vector<pair<int, int> > parent(n + 1, make_pair(0, 0)); for (int i = 1; i <= n; i++) { if (i != source) pq.push(make_pair(LLONG_MIN, i)); else pq.push(make_pair(0, i)); } vector<pair<long long int, int> > dist(n + 1, make_pair(LLONG_MAX, 0)); dist[source].first = 0; while (!pq.empty()) { int vertex = pq.top().second; pq.pop(); if (check_list[vertex] == false) { check_list[vertex] = true; for (int i = 0; i < adj_list[vertex].size(); i++) { if (dist[adj_list[vertex][i].neighbour].first > dist[vertex].first + adj_list[vertex][i].weight) { parent[adj_list[vertex][i].neighbour].first = adj_list[vertex][i].edge_number; parent[adj_list[vertex][i].neighbour].second = adj_list[vertex][i].weight; dist[adj_list[vertex][i].neighbour].first = dist[vertex].first + adj_list[vertex][i].weight; dist[adj_list[vertex][i].neighbour].second = adj_list[vertex][i].weight; pq.push(make_pair((-1) * (dist[adj_list[vertex][i].neighbour].first), adj_list[vertex][i].neighbour)); } else if (dist[adj_list[vertex][i].neighbour].first == dist[vertex].first + adj_list[vertex][i].weight) { if (dist[adj_list[vertex][i].neighbour].second > adj_list[vertex][i].weight) { parent[adj_list[vertex][i].neighbour].first = adj_list[vertex][i].edge_number; parent[adj_list[vertex][i].neighbour].second = adj_list[vertex][i].weight; dist[adj_list[vertex][i].neighbour].second = adj_list[vertex][i].weight; } } } } } long long int ans = 0; for (int i = 1; i <= n; i++) { ans += parent[i].second; } cout << ans << endl; for (int i = 1; i <= n; i++) { if (source != i) cout << parent[i].first << ; } } |
#include <bits/stdc++.h> const int32_t MAX_N = 1000; bool isInA[MAX_N + 5], isInB[MAX_N + 5], isVisited[MAX_N + 5]; std::vector<int32_t> v[MAX_N + 5]; int32_t Dfs(int32_t nd) { isVisited[nd] = true; if (isInA[nd]) { return nd; } int32_t ans = INT32_MAX; for (auto &x : v[nd]) { if (!isVisited[x]) { ans = std::min(ans, Dfs(x)); } } return ans; } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(nullptr); int32_t cntTests; std::cin >> cntTests; for (int32_t cs = 1; cs <= cntTests; cs++) { int32_t n; std::cin >> n; for (int32_t i = 1; i <= n; i++) { v[i].clear(); } for (int32_t i = 0; i < n - 1; i++) { int32_t a, b; std::cin >> a >> b; v[a].push_back(b); v[b].push_back(a); } memset(isInA, 0, sizeof(isInA)); memset(isInB, 0, sizeof(isInB)); int32_t k1; std::cin >> k1; std::vector<int32_t> v1(k1); for (int32_t i = 0; i < k1; i++) { std::cin >> v1[i]; isInA[v1[i]] = true; } int32_t k2; std::cin >> k2; std::vector<int32_t> v2(k2); for (int32_t i = 0; i < k2; i++) { std::cin >> v2[i]; isInB[v2[i]] = true; } std::cout << B << v2[0] << n << std::flush; int32_t stNode; std::cin >> stNode; memset(isVisited, 0, sizeof(isVisited)); int32_t target = Dfs(stNode); std::cout << A << target << n << std::flush; int32_t res; std::cin >> res; if (isInB[res]) { std::cout << C << target << n << std::flush; } else { std::cout << C << -1 << n << std::flush; } } } |
/*
Execute Module (64-bit, Combined)
*/
`include "ExOp64_3A.v"
`include "ExOp64_3B.v"
module ExOp64_3C(
/* verilator lint_off UNUSED */
clock, reset,
opStepPc, idInGenPc, regOutOK,
regIdRs1, regValRs1, regIdRt1, regValRt1,
regIdRn1, regValRn1, regIdRw1, regValRw1,
immValRi1, opCmd1,
regIdRs2, regValRs2, regIdRt2, regValRt2,
regIdRn2, regValRn2, regIdRw2, regValRw2,
immValRi2, opCmd2,
regIdRs3, regValRs3, regIdRt3, regValRt3,
regIdRn3, regValRn3, regIdRw3, regValRw3,
immValRi3, opCmd3,
regIdRs4, regValRs4, regIdRt4, regValRt4,
regIdRn4, regValRn4, regIdRw4, regValRw4,
immValRi4, opCmd4,
regIdRs5, regValRs5, regIdRt5, regValRt5,
regIdRn5, regValRn5, regIdRw5, regValRw5,
immValRi5, opCmd5,
memAddr, memData,
memLoad, memStore,
memOpMode, memOpCmd2,
ctlInSr, ctlOutSr,
ctlInPr, ctlOutPr,
ctlInPc, ctlOutPc,
ctlInMach, ctlOutMach,
ctlInMacl, ctlOutMacl,
ctlInSp, ctlOutSp,
ctlInGbr, ctlOutGbr,
ctlInVbr, ctlOutVbr,
ctlInSSr, ctlOutSSr,
ctlInSPc, ctlOutSPc,
ctlInSGr, ctlOutSGr
);
input clock;
input reset;
input[3:0] opStepPc;
input[63:0] idInGenPc; //ID's Next PC (Next Fetch)
output[1:0] regOutOK; //execute status
/* Lane 1 */
input[6:0] regIdRs1;
input[6:0] regIdRt1;
input[6:0] regIdRn1;
output[6:0] regIdRw1; //Rn, value to write
input[63:0] regValRs1; //Rs input value
input[63:0] regValRt1; //Rt input value
input[63:0] regValRn1; //Rn input value
output[63:0] regValRw1; //Rn output value
input[63:0] immValRi1; //immediate/disp value
input[7:0] opCmd1; //command opcode
/* Lane 2 */
input[6:0] regIdRs2;
input[6:0] regIdRt2;
input[6:0] regIdRn2;
output[6:0] regIdRw2; //Rn, value to write
input[63:0] regValRs2; //Rs input value
input[63:0] regValRt2; //Rt input value
input[63:0] regValRn2; //Rn input value
output[63:0] regValRw2; //Rn output value
input[63:0] immValRi2; //immediate/disp value
input[7:0] opCmd2; //command opcode
/* Lane 3 */
input[6:0] regIdRs3;
input[6:0] regIdRt3;
input[6:0] regIdRn3;
output[6:0] regIdRw3; //Rn, value to write
input[63:0] regValRs3; //Rs input value
input[63:0] regValRt3; //Rt input value
input[63:0] regValRn3; //Rn input value
output[63:0] regValRw3; //Rn output value
input[63:0] immValRi3; //immediate/disp value
input[7:0] opCmd3; //command opcode
/* Lane 4 */
input[6:0] regIdRs4;
input[6:0] regIdRt4;
input[6:0] regIdRn4;
output[6:0] regIdRw4; //Rn, value to write
input[63:0] regValRs4; //Rs input value
input[63:0] regValRt4; //Rt input value
input[63:0] regValRn4; //Rn input value
output[63:0] regValRw4; //Rn output value
input[63:0] immValRi4; //immediate/disp value
input[7:0] opCmd4; //command opcode
/* Lane 5 */
input[6:0] regIdRs5;
input[6:0] regIdRt5;
input[6:0] regIdRn5;
output[6:0] regIdRw5; //Rn, value to write
input[63:0] regValRs5; //Rs input value
input[63:0] regValRt5; //Rt input value
input[63:0] regValRn5; //Rn input value
output[63:0] regValRw5; //Rn output value
input[63:0] immValRi5; //immediate/disp value
input[7:0] opCmd5; //command opcode
/* Memory */
output[63:0] memAddr; //memory address
output[63:0] memData; //memory data (write)
output memLoad; //load from memory
output memStore; //store to memory
output[4:0] memOpMode; //mem op mode
output[7:0] memOpCmd2; //mem EX chain
/* Special Registers */
input[63:0] ctlInSr; //SR in
input[63:0] ctlInPr; //PR in
input[63:0] ctlInPc; //PC in
output[63:0] ctlOutSr; //SR out
output[63:0] ctlOutPr; //PR out
output[63:0] ctlOutPc; //PC out
input[63:0] ctlInMach; //MACH:MACL in
input[63:0] ctlInMacl; //MACH:MACL in
output[63:0] ctlOutMach; //MACH:MACL out
output[63:0] ctlOutMacl; //MACH:MACL out
input[63:0] ctlInSp; //SP in
output[63:0] ctlOutSp; //SP out
input[63:0] ctlInGbr;
input[63:0] ctlInVbr;
input[63:0] ctlInSSr;
input[63:0] ctlInSPc;
input[63:0] ctlInSGr;
output[63:0] ctlOutGbr;
output[63:0] ctlOutVbr;
output[63:0] ctlOutSSr;
output[63:0] ctlOutSPc;
output[63:0] ctlOutSGr;
wire[1:0] tRegOutOK;
wire[1:0] tRegOutOK1;
wire[1:0] tRegOutOK2;
wire[1:0] tRegOutOK3;
wire[1:0] tRegOutOK4;
wire[1:0] tRegOutOK5;
wire tRegOutHold;
wire tRegOutFault;
assign tRegOutHold =
((tRegOutOK1==UMEM_OK_HOLD) ||
(tRegOutOK2==UMEM_OK_HOLD) ||
(tRegOutOK3==UMEM_OK_HOLD) ||
(tRegOutOK4==UMEM_OK_HOLD) ||
(tRegOutOK5==UMEM_OK_HOLD));
assign tRegOutFault =
((tRegOutOK1==UMEM_OK_FAULT) ||
(tRegOutOK2==UMEM_OK_FAULT) ||
(tRegOutOK3==UMEM_OK_FAULT) ||
(tRegOutOK4==UMEM_OK_FAULT) ||
(tRegOutOK5==UMEM_OK_FAULT));
assign tRegOutOK =
tRegOutHold ? UMEM_OK_HOLD :
tRegOutFault ? UMEM_OK_FAULT :
UMEM_OK_OK;
assign regOutOK = tRegOutOK;
ExOp64_3A ex3a1(
clock, reset,
opCmd1, opStepPc,
regIdRs1, regValRs1,
regIdRt1, regValRt1,
regIdRn1, regValRn1,
immValRi1, idInGenPc,
regIdRw1, regValRw1,
tRegOutOK1,
memAddr, memData,
memLoad, memStore,
memOpMode, memOpCmd2,
ctlInSr, ctlOutSr,
ctlInPr, ctlOutPr,
ctlInPc, ctlOutPc,
ctlInMach, ctlOutMach,
ctlInMacl, ctlOutMacl,
ctlInSp, ctlOutSp,
ctlInGbr, ctlOutGbr,
ctlInVbr, ctlOutVbr,
ctlInSSr, ctlOutSSr,
ctlInSPc, ctlOutSPc,
ctlInSGr, ctlOutSGr
);
ExOp64_3B ex3b2(
clock, reset,
opCmd2, opStepPc,
regIdRs2, regValRs2,
regIdRt2, regValRt2,
regIdRn2, regValRn2,
immValRi2, idInGenPc,
regIdRw2, regValRw2,
tRegOutOK2, ctlInSr);
ExOp64_3B ex3b3(
clock, reset,
opCmd3, opStepPc,
regIdRs3, regValRs3,
regIdRt3, regValRt3,
regIdRn3, regValRn3,
immValRi3, idInGenPc,
regIdRw3, regValRw3,
tRegOutOK3, ctlInSr);
ExOp64_3B ex3b4(
clock, reset,
opCmd4, opStepPc,
regIdRs4, regValRs4,
regIdRt4, regValRt4,
regIdRn4, regValRn4,
immValRi4, idInGenPc,
regIdRw4, regValRw4,
tRegOutOK4, ctlInSr);
ExOp64_3B ex3b5(
clock, reset,
opCmd5, opStepPc,
regIdRs5, regValRs5,
regIdRt5, regValRt5,
regIdRn5, regValRn5,
immValRi5, idInGenPc,
regIdRw5, regValRw5,
tRegOutOK5, ctlInSr);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__SRDLXTP_PP_BLACKBOX_V
/**
* srdlxtp: ????.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srdlxtp (
Q ,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLXTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); long long a, b, c; cin >> a >> b >> c; if (a > b) swap(a, b); cout << a + min(c, a + b) + min(b, a + c); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
always @ (negedge clk) begin
AssertionFalse1: assert (cyc<100);
assert (!(cyc==5) || toggle);
// FIX cover {cyc==3 || cyc==4};
// FIX cover {cyc==9} report "DefaultClock,expect=1";
// FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==7) assert (cyc[0] == cyc[1]); // bug743
if (cyc==9) begin
`ifdef FAILING_ASSERTIONS
assert (0) else $info;
assert (0) else $info("Info message");
assert (0) else $info("Info message, cyc=%d", cyc);
InWarningBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0);
InErrorBlock: assert (0) else $error("Error....");
assert (0) else $fatal(1,"Fatal....");
`endif
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const double EPS = 1e-6; const long long oo = 1LL << 60; const int INF = 0x3f3f3f3f; const int MOD = 1e9 + 7; const int N = 100005; struct segTree { int num; long long sum[5]; } node[N << 2]; struct Query { int type, num; } q[N]; void pushup(int rt) { node[rt].num = (node[(rt << 1)].num + node[(rt << 1 | 1)].num) % 5; int leftSonNum = node[(rt << 1)].num; for (int i = 0; i < 5; ++i) node[rt].sum[i] = node[(rt << 1)].sum[i] + node[(rt << 1 | 1)].sum[(i - leftSonNum + 5) % 5]; } void update(int l, int r, int rt, int p, int v) { if (l == r) { node[rt].num = (v > 0); node[rt].sum[1] = (v > 0 ? v : 0); return; } if (p <= ((l + r) >> 1)) update(l, ((l + r) >> 1), (rt << 1), p, v); else update(((l + r) >> 1) + 1, r, (rt << 1 | 1), p, v); pushup(rt); } vector<int> arr; int pos[N]; int main() { int n; char s[5]; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %s , s); if (s[0] == a ) { scanf( %d , &q[i].num); q[i].type = 1; arr.push_back(q[i].num); } else if (s[0] == d ) { scanf( %d , &q[i].num); q[i].type = 2; } else q[i].type = 0; } sort((arr).begin(), (arr).end()); arr.erase(unique((arr).begin(), (arr).end()), arr.end()); for (int i = 0; i < n; ++i) if (q[i].type) pos[i] = lower_bound((arr).begin(), (arr).end(), q[i].num) - arr.begin() + 1; int siz = (int(arr.size())); for (int i = 0; i < n; ++i) { if (q[i].type == 1) update(1, siz, 1, pos[i], q[i].num); else if (q[i].type == 2) update(1, siz, 1, pos[i], -q[i].num); else printf( %I64d n , node[1].sum[3]); } return 0; } |
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
// Everything here was verified on a MV4 board
module z80ctrl(
input [4:2] SDA_L,
input [15:11] SDA_U,
input nSDRD, nSDWR,
input nMREQ, nIORQ,
input nSDW, // From NEO-C1
input nRESET,
output reg nZ80NMI,
output nSDZ80R, nSDZ80W, // To NEO-C1
output nSDZ80CLR, // To NEO-C1
output nSDROM,
output nSDMRD, nSDMWR,
output nSDRD0, nSDRD1,
output n2610CS,
output n2610RD, n2610WR,
output nZRAMCS
);
reg nNMI_EN;
wire nIORD, nIOWR;
wire nNMI_SET, nNMI_RESET;
// $0000~$F7FF: ROM
// $F800~$FFFF: RAM
assign nSDROM = &{SDA_U};
assign nZRAMCS = ~nSDROM;
assign nSDMRD = nMREQ | nSDRD; // RAM read
assign nSDMWR = nMREQ | nSDWR; // RAM write
assign nIORD = nIORQ | nSDRD; // Port read
assign nIOWR = nIORQ | nSDWR; // Port write
// Port $x0, $x1, $x2, $x3 read
assign nSDZ80R = (nIORD | SDA_L[3] | SDA_L[2]);
// Port $x0, $x1, $x2, $x3 write
assign nSDZ80CLR = (nIOWR | SDA_L[3] | SDA_L[2]);
// Port $x4, $x5, $x6, $x7 read
assign n2610RD = (nIORD | SDA_L[3] | ~SDA_L[2]);
// Port $x4, $x5, $x6, $x7 write
assign n2610WR = (nIOWR | SDA_L[3] | ~SDA_L[2]);
assign n2610CS = n2610RD & n2610WR;
// Port $x8, $x9, $xA, $xB read
assign nSDRD0 = (nIORD | ~SDA_L[3] | SDA_L[2]);
// Port $x8, $x9, $xA, $xB write
assign nNMI_SET = (nIOWR | ~SDA_L[3] | SDA_L[2]);
// Port $xC, $xD, $xE, $xF read
assign nSDRD1 = (nIORD | ~SDA_L[3] | ~SDA_L[2]);
// Port $xC, $xD, $xE, $xF write
assign nSDZ80W = (nIOWR | ~SDA_L[3] | ~SDA_L[2]);
assign nNMI_RESET = nSDZ80R & nRESET;
// NMI enable DFF
always @(posedge nNMI_SET or negedge nRESET)
begin
if (!nRESET)
nNMI_EN <= 1'b1;
else
nNMI_EN <= SDA_L[4];
end
// NMI trig DFF
always @(posedge nSDW or negedge nNMI_RESET)
begin
if (!nNMI_RESET)
nZ80NMI <= 1'b1;
else
nZ80NMI <= nNMI_EN;
end
endmodule
|
// file: clk_wiz_v3_6.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____25.000______0.000______50.0_____1000.000____150.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_v3_6,clk_wiz_v3_6,{component_name=clk_wiz_v3_6,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module clk_wiz_v3_6
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
wire clkfx;
DCM_SP
#(.CLKDV_DIVIDE (4.000),
.CLKFX_DIVIDE (8),
.CLKFX_MULTIPLY (2),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (clkfx),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (1'b0),
// Unused pin- tie low
.DSSEN (1'b0));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfb),
.I (clk0));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int get(int x) { int t = log2(x); if ((1 << t) < x) t++; return (1 << t) - x; } unordered_map<int, int> to, pos; unordered_map<int, vector<pair<pair<int, int>, int> > > mp; int a[200005]; pair<pair<int, int>, int> num[200005]; int len = 0; signed main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; int ans = 0, a1 = 0, a2 = 0; for (int i = 1; i <= n; i++) cin >> a[i], pos[a[i]] = i; sort(a + 1, a + n + 1, greater<int>()); for (int i = 1; i <= n; i++) { int x = a[i]; int cnt = 0; while (x) { int t = get(x); cnt++; mp[t].emplace_back(make_pair(make_pair(cnt, x), pos[a[i]])); to[x] = t; if (pos.count(t)) { if (cnt > ans) { ans = cnt; a1 = pos[a[i]]; a2 = pos[t]; } } x = t; } } for (auto u : mp) { len = 0; for (auto tu : u.second) { num[++len] = tu; } sort(num + 1, num + len + 1); pair<pair<int, int>, int> now = num[len]; while (len && num[len].first.second == now.first.second) len--; if (len) { pair<pair<int, int>, int> p2 = num[len]; if (now.first.first + p2.first.first > ans) { ans = now.first.first + p2.first.first; a1 = now.second; a2 = p2.second; } } } cout << a1 << << a2 << << ans; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_MS__SDLCLKP_PP_SYMBOL_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdlclkp (
//# {{scanchain|Scan Chain}}
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDLCLKP_PP_SYMBOL_V
|
module rd_memory ( remapping_memory, full,
rd_data, rd_clk, rd_en, rd_addr,
reset );
/* Parameters */
parameter RD_DATA_WIDTH = 1;
parameter RD_ADDR_WIDTH = 2;
parameter MEM_DEPTH = 4;
/* Ports */
input wire [MEM_DEPTH - 1 : 0] remapping_memory;
input wire full;
output reg [RD_DATA_WIDTH - 1 : 0] rd_data;
input wire [RD_ADDR_WIDTH - 1 : 0] rd_addr;
input wire rd_clk, rd_en;
input wire reset;
/* Variables */
reg [RD_DATA_WIDTH - 1 : 0] memory [MEM_DEPTH - 1 : 0];
integer i;
/* Behavioral */
always @(negedge full or posedge reset) begin
if(reset)
for(i = 0; i < MEM_DEPTH; i = i + 1)
memory[i] <= 0;
else
for(i = 0; i < MEM_DEPTH; i = i + 1)
memory[i] <= remapping_memory[i];
end
always @(posedge rd_clk or posedge reset) begin
if(reset)
rd_data <= 0;
else
if(rd_en)
rd_data <= memory[rd_addr];
end
endmodule |
#include <bits/stdc++.h> inline long long read() { long long x = 0; char ch = getchar(), w = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * w; } void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } inline void writeln(long long x) { write(x); puts( ); } using namespace std; const int N = 5e5 + 656666; long long n, m, c, c0; struct TT { long long t, a, b; } a[N]; bool cmp(TT x, TT y) { return x.t < y.t; } map<long long, long long> q; long long cal() { q.clear(); long long ans = 0; q[0] = c0; long long now = c0, cap = c; for (int i = 1; i <= n; ++i) { long long rest = a[i].t - a[i - 1].t; long long val = 0; now -= rest; while (!q.empty() && rest) { val = min(rest, q.begin()->second); rest -= val; q.begin()->second -= val; ans += val * q.begin()->first; if (!q.begin()->second) q.erase(q.begin()); } if (rest) return -1; long long ned = min(cap - now, a[i].a); now += ned; while (!q.empty() && a[i].b < q.rbegin()->first && ned < a[i].a) { val = min(q.rbegin()->second, a[i].a - ned); q.rbegin()->second -= val; ned += val; if (!q.rbegin()->second) q.erase(--q.end()); } q[a[i].b] += ned; } return ans; } int main() { int T = read(); while (T--) { n = read(), m = read(), c = read(), c0 = read(); for (int i = 1; i <= n; ++i) { a[i].t = read(); a[i].a = read(); a[i].b = read(); } a[++n] = (TT){m, 0, 0}; sort(a + 1, a + 1 + n, cmp); writeln(cal()); } return 0; } |
#include <bits/stdc++.h> using namespace std; int d[(1 << 17) + 20][100], par[(1 << 17) + 20][100]; int prime[20] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53}; int sum[70], a[100]; int ret, temp; int ans = 10000000; void pre() { for (int i = 1; i < 59; i++) { for (int j = 0; j < 17; j++) { if (prime[j] > 1 && i % prime[j] == 0) sum[i] += (1 << j); } } } void pp(int mask, int ind) { if (ind > 0) pp(mask - sum[par[mask][ind]], ind - 1); cout << par[mask][ind] << ; return; } int main() { ios::sync_with_stdio(false); int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; pre(); for (int mask = 0; mask < (1 << 17); mask++) { ret = ans; for (int val = 1; val < 59; val++) { temp = ret; if ((sum[val] & mask) == sum[val]) ret = min(ret, abs(val - a[0])); if (temp > ret) par[mask][0] = val; } d[mask][0] = ret; } for (int mask = 0; mask < (1 << 17); mask++) { for (int ind = 0; ind < n; ind++) { ret = ans; for (int val = 1; val < 59; val++) { temp = ret; if ((sum[val] & mask) == sum[val]) ret = min(d[mask - sum[val]][ind - 1] + abs(val - a[ind]), ret); if (temp > ret) { par[mask][ind] = val; } } d[mask][ind] = ret; } } pp((1 << 17) - 1, n - 1); return 0; } |
// EE 471 Lab 1, Beck Pang, Spring 2015
// Main function for calling different counter onto the board
// @require: only call one counter a time
module DE1_SoC (CLOCK_50, LEDR, SW, KEY);
input CLOCK_50; // connect to system 50 MHz clock
output reg [9:0] LEDR;
input [9:0] SW;
input [3:0] KEY;
wire clk;
wire [15:0] data;
reg [6:0] hold;
reg WrEn, regWR;
reg [10:0] adx;
reg [15:0] store;
wire [1:0] state, blockSel;
wire clkControl, rst, slowClk, outSel;
reg [4:0] readAdd0, readAdd1, writeAdd;
reg [31:0] writeData;
wire [31:0] readOutput0, readOutput1;
//reg [15:0] data;
//assign data[6:0] = SW[6:0]
assign clkControl = SW[8];
assign state = SW[7:6];
assign blockSel = SW[5:4];
assign outSel = SW[3];
assign rst = SW[9];
assign data = WrEn ? 16'bZ : store;
SRAM2Kby16 memory(clk, adx, WrEn, data);
clkSlower counter(slowClk, CLOCK_50, rst);
registerFile regs(clk, readAdd0, readAdd1, writeAdd, regWR, writeData, readOutput0, readOutput1);
always @(posedge clk) begin
if(rst) begin
hold = 0;
adx = 0;
WrEn = 1;
LEDR = 0;
end else if(state == 0) begin
WrEn = 0;
adx = hold;
store = 7'b1111111 - hold;
LEDR[6:0] = hold;
end else if(state == 1) begin
WrEn = 1;
regWR = 1;
writeAdd = hold[4:0];
adx = blockSel * 32 + hold[4:0];
writeData[15:0] = data;
end else if(state == 2) begin
WrEn = 1;
regWR = 0;
readAdd0 = hold[3:0];
readAdd1 = 16 + hold[3:0];
LEDR = outSel ? readOutput0[9:0] : readOutput1[9:0];
end else if(state == 3) begin
WrEn = 0;
regWR = 0;
if(blockSel[0]) begin
readAdd1 = hold[5:2] + 16;
if(hold[0]) begin
store = readOutput1[15:0];
adx = 179 + hold[5:2];
end else begin
store = readOutput1[15:0];
adx = 145 + hold[5:2];
end
end else begin
readAdd0 = hold[5:2];
if(hold[0]) begin
store = readOutput0[15:0];
adx = 162 + hold[5:2];
end else begin
store = readOutput0[15:0];
adx = 128 + hold[5:2];
end
end
end
hold = hold + 1'b1;
end
assign clk = clkControl ? slowClk : CLOCK_50;
endmodule
module SendP2SBufferTestbench();
reg CLOCK_50; // connect to system 50 MHz clock
wire [9:0] LEDR;
reg [9:0] SW;
reg [3:0] KEY;
DE1_SoC dut (CLOCK_50, LEDR, SW, KEY);
// Set up the clocking
parameter d = 20;
initial begin
CLOCK_50 = 1;
SW = 12;
KEY = 0;
end
always #(d/2) CLOCK_50 = ~CLOCK_50;
// Set up the inputs to the design
initial begin
#(d*10); SW[9] = 1;
#d; SW[9] = 0; SW[8] = 1;
#(d*500); SW[8] = 0;
#d SW[5:0] = 64;
#d SW[5:0] = 32;
#d SW[5:0] = 16;
#d SW[5:0] = 8;
#d SW[5:0] = 120;
$stop;
end
endmodule |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) const int inf = 0x3f3f3f3f; const long long LL_INF = 0x3f3f3f3f3f3f3f3f; template <typename T> T gcd(T a, T b) { if (a == 0) return b; return gcd(b % a, a); } long long power(long long a, long long b, long long m = 1000000007) { long long answer = 1; while (b) { if (b & 1) answer = (answer * a) % m; b /= 2; a = (a * a) % m; } return answer; } using namespace std; bool chk[1048576]; int main() { set<int> st; int n; cin >> n; for (int i = 0; i < n; i++) { int x; cin >> x; set<int>::iterator it; set<int> st2; for (it = st.begin(); it != st.end(); it++) { int y = *it; st2.insert(y | x); } st2.insert(x); st = st2; st2.clear(); for (it = st.begin(); it != st.end(); it++) { chk[*it] = 1; } } int cnt = 0; for (int i = 0; i < 1048576; i++) { if (chk[i]) cnt++; } cout << cnt; return 0; } |
(** * Maps: Total and Partial Maps *)
(** Maps (or dictionaries) are ubiquitous data structures both
generally and in the theory of programming languages in
particular; we're going to need them in many places in the coming
chapters. They also make a nice case study using ideas we've seen
in previous chapters, including building data structures out of
higher-order functions (from [Basics] and [Poly]) and the use of
reflection to streamline proofs (from [IndProp]).
We'll define two flavors of maps: _total_ maps, which include a
"default" element to be returned when a key being looked up
doesn't exist, and _partial_ maps, which return an [option] to
indicate success or failure. The latter is defined in terms of
the former, using [None] as the default element. *)
(* ################################################################# *)
(** * The Coq Standard Library *)
(** One small digression before we get to maps.
Unlike the chapters we have seen so far, this one does not
[Require Import] the chapter before it (and, transitively, all the
earlier chapters). Instead, in this chapter and from now, on
we're going to import the definitions and theorems we need
directly from Coq's standard library stuff. You should not notice
much difference, though, because we've been careful to name our
own definitions and theorems the same as their counterparts in the
standard library, wherever they overlap. *)
Require Import Coq.Arith.Arith.
Require Import Coq.Bool.Bool.
Require Import Coq.Strings.String.
Require Import Coq.Logic.FunctionalExtensionality.
(** Documentation for the standard library can be found at
http://coq.inria.fr/library/.
The [Search] command is a good way to look for theorems involving
objects of specific types. Take a minute now to experiment with it. *)
(* ################################################################# *)
(** * Identifiers *)
(** First, we need a type for the keys that we use to index into our
maps. For this purpose, we again use the type [id] from the
[Lists] chapter. To make this chapter self contained, we repeat
its definition here, together with the equality comparison
function for [id]s and its fundamental property. *)
Inductive id : Type :=
| Id : string -> id.
Definition beq_id x y :=
match x,y with
| Id n1, Id n2 => if string_dec n1 n2 then true else false
end.
(** (The function [string_dec] comes from Coq's string library.
If you check its result type, you'll see that it does not actually
return a [bool], but rather a type that looks like [{x = y} + {x
<> y}], called a [sumbool], which can be thought of as an
"evidence-carrying boolean." Formally, an element of [sumbool] is
either a proof that two things are equal or a proof that they are
unequal, together with a tag indicating which. But for present
purposes you can think of it as just a fancy [bool].) *)
Theorem beq_id_refl : forall id, true = beq_id id id.
Proof.
intros [n]. simpl. destruct (string_dec n n).
- reflexivity.
- destruct n0. reflexivity.
Qed.
(** The following useful property of [beq_id] follows from an
analogous lemma about strings: *)
Theorem beq_id_true_iff : forall x y : id,
beq_id x y = true <-> x = y.
Proof.
intros [n1] [n2].
unfold beq_id.
destruct (string_dec n1 n2).
- subst. split. reflexivity. reflexivity.
- split.
+ intros contra. inversion contra.
+ intros H. inversion H. subst. destruct n. reflexivity.
Qed.
(** Similarly: *)
Theorem beq_id_false_iff : forall x y : id,
beq_id x y = false
<-> x <> y.
Proof.
intros x y. rewrite <- beq_id_true_iff.
rewrite not_true_iff_false. reflexivity. Qed.
(** This useful variant follows just by rewriting: *)
Theorem false_beq_id : forall x y : id,
x <> y
-> beq_id x y = false.
Proof.
intros x y. rewrite beq_id_false_iff.
intros H. apply H. Qed.
(* ################################################################# *)
(** * Total Maps *)
(** Our main job in this chapter will be to build a definition of
partial maps that is similar in behavior to the one we saw in the
[Lists] chapter, plus accompanying lemmas about its behavior.
This time around, though, we're going to use _functions_, rather
than lists of key-value pairs, to build maps. The advantage of
this representation is that it offers a more _extensional_ view of
maps, where two maps that respond to queries in the same way will
be represented as literally the same thing (the very same function),
rather than just "equivalent" data structures. This, in turn,
simplifies proofs that use maps.
We build partial maps in two steps. First, we define a type of
_total maps_ that return a default value when we look up a key
that is not present in the map. *)
Definition total_map (A:Type) := id -> A.
(** Intuitively, a total map over an element type [A] is just a
function that can be used to look up [id]s, yielding [A]s.
The function [t_empty] yields an empty total map, given a default
element; this map always returns the default element when applied
to any id. *)
Definition t_empty {A:Type} (v : A) : total_map A :=
(fun _ => v).
(** More interesting is the [update] function, which (as before) takes
a map [m], a key [x], and a value [v] and returns a new map that
takes [x] to [v] and takes every other key to whatever [m] does. *)
Definition t_update {A:Type} (m : total_map A)
(x : id) (v : A) :=
fun x' => if beq_id x x' then v else m x'.
(** This definition is a nice example of higher-order programming:
[t_update] takes a _function_ [m] and yields a new function
[fun x' => ...] that behaves like the desired map.
For example, we can build a map taking [id]s to [bool]s, where [Id
3] is mapped to [true] and every other key is mapped to [false],
like this: *)
Definition examplemap :=
t_update (t_update (t_empty false) (Id "foo") false)
(Id "bar") true.
(** This completes the definition of total maps. Note that we don't
need to define a [find] operation because it is just function
application! *)
Example update_example1 : examplemap (Id "baz") = false.
Proof. reflexivity. Qed.
Example update_example2 : examplemap (Id "foo") = false.
Proof. reflexivity. Qed.
Example update_example3 : examplemap (Id "quux") = false.
Proof. reflexivity. Qed.
Example update_example4 : examplemap (Id "bar") = true.
Proof. reflexivity. Qed.
(** To use maps in later chapters, we'll need several fundamental
facts about how they behave. Even if you don't work the following
exercises, make sure you thoroughly understand the statements of
the lemmas! (Some of the proofs require the functional
extensionality axiom, which is discussed in the [Logic]
chapter.) *)
(** **** Exercise: 1 star, optional (t_apply_empty) *)
(** First, the empty map returns its default element for all keys: *)
Lemma t_apply_empty: forall A x v, @t_empty A v x = v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_eq) *)
(** Next, if we update a map [m] at a key [x] with a new value [v]
and then look up [x] in the map resulting from the [update], we
get back [v]: *)
Lemma t_update_eq : forall A (m: total_map A) x v,
(t_update m x v) x = v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_neq) *)
(** On the other hand, if we update a map [m] at a key [x1] and then
look up a _different_ key [x2] in the resulting map, we get the
same result that [m] would have given: *)
Theorem t_update_neq : forall (X:Type) v x1 x2
(m : total_map X),
x1 <> x2 ->
(t_update m x1 v) x2 = m x2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_shadow) *)
(** If we update a map [m] at a key [x] with a value [v1] and then
update again with the same key [x] and another value [v2], the
resulting map behaves the same (gives the same result when applied
to any key) as the simpler map obtained by performing just
the second [update] on [m]: *)
Lemma t_update_shadow : forall A (m: total_map A) v1 v2 x,
t_update (t_update m x v1) x v2
= t_update m x v2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** For the final two lemmas about total maps, it's convenient to use
the reflection idioms introduced in chapter [IndProp]. We begin
by proving a fundamental _reflection lemma_ relating the equality
proposition on [id]s with the boolean function [beq_id]. *)
(** **** Exercise: 2 stars, optional (beq_idP) *)
(** Use the proof of [beq_natP] in chapter [IndProp] as a template to
prove the following: *)
Lemma beq_idP : forall x y, reflect (x = y) (beq_id x y).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Now, given [id]s [x1] and [x2], we can use the [destruct (beq_idP
x1 x2)] to simultaneously perform case analysis on the result of
[beq_id x1 x2] and generate hypotheses about the equality (in the
sense of [=]) of [x1] and [x2]. *)
(** **** Exercise: 2 stars (t_update_same) *)
(** With the example in chapter [IndProp] as a template, use
[beq_idP] to prove the following theorem, which states that if we
update a map to assign key [x] the same value as it already has in
[m], then the result is equal to [m]: *)
Theorem t_update_same : forall X x (m : total_map X),
t_update m x (m x) = m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, recommended (t_update_permute) *)
(** Use [beq_idP] to prove one final property of the [update]
function: If we update a map [m] at two distinct keys, it doesn't
matter in which order we do the updates. *)
Theorem t_update_permute : forall (X:Type) v1 v2 x1 x2
(m : total_map X),
x2 <> x1 ->
(t_update (t_update m x2 v2) x1 v1)
= (t_update (t_update m x1 v1) x2 v2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Partial maps *)
(** Finally, we define _partial maps_ on top of total maps. A partial
map with elements of type [A] is simply a total map with elements
of type [option A] and default element [None]. *)
Definition partial_map (A:Type) := total_map (option A).
Definition empty {A:Type} : partial_map A :=
t_empty None.
Definition update {A:Type} (m : partial_map A)
(x : id) (v : A) :=
t_update m x (Some v).
(** We now straightforwardly lift all of the basic lemmas about total
maps to partial maps. *)
Lemma apply_empty : forall A x, @empty A x = None.
Proof.
intros. unfold empty. rewrite t_apply_empty.
reflexivity.
Qed.
Lemma update_eq : forall A (m: partial_map A) x v,
(update m x v) x = Some v.
Proof.
intros. unfold update. rewrite t_update_eq.
reflexivity.
Qed.
Theorem update_neq : forall (X:Type) v x1 x2
(m : partial_map X),
x2 <> x1 ->
(update m x2 v) x1 = m x1.
Proof.
intros X v x1 x2 m H.
unfold update. rewrite t_update_neq. reflexivity.
apply H. Qed.
Lemma update_shadow : forall A (m: partial_map A) v1 v2 x,
update (update m x v1) x v2 = update m x v2.
Proof.
intros A m v1 v2 x1. unfold update. rewrite t_update_shadow.
reflexivity.
Qed.
Theorem update_same : forall X v x (m : partial_map X),
m x = Some v ->
update m x v = m.
Proof.
intros X v x m H. unfold update. rewrite <- H.
apply t_update_same.
Qed.
Theorem update_permute : forall (X:Type) v1 v2 x1 x2
(m : partial_map X),
x2 <> x1 ->
(update (update m x2 v2) x1 v1)
= (update (update m x1 v1) x2 v2).
Proof.
intros X v1 v2 x1 x2 m. unfold update.
apply t_update_permute.
Qed.
(** $Date: 2017-03-05 16:25:50 -0500 (Sun, 05 Mar 2017) $ *)
|
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module gpmc16_to_fifo36
#(
parameter FIFO_SIZE = 9,
//not ready until minimum xfers of space available
parameter MIN_SPACE16 = 128
)
(
//input interface
input gpif_clk, input gpif_rst,
input [15:0] in_data,
input valid,
output reg ready,
//output fifo interface
input fifo_clk, input fifo_rst,
output [35:0] out_data,
output out_src_rdy,
input out_dst_rdy
);
wire [35:0] data_int;
wire src_rdy_int, dst_rdy_int;
wire [18:0] refr_data;
wire refr_src_rdy, refr_dst_rdy;
wire [15:0] fifo_space;
always @(posedge gpif_clk)
ready <= (fifo_space >= MIN_SPACE16/2);
packet_reframer packet_reframer
(.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
.data_i(in_data), .src_rdy_i(valid), .dst_rdy_o(),
.data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy));
fifo19_to_fifo36 #(.LE(1)) f19_to_f36
(.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
.f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy),
.f36_dataout(data_int), .f36_src_rdy_o(src_rdy_int), .f36_dst_rdy_i(dst_rdy_int));
fifo_2clock_cascade #(.WIDTH(36), .SIZE(FIFO_SIZE)) fifo_2clk
(.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(fifo_space),
.rclk(fifo_clk), .dataout(out_data), .src_rdy_o(out_src_rdy), .dst_rdy_i(out_dst_rdy), .occupied(),
.arst(fifo_rst | gpif_rst));
endmodule //fifo_to_gpmc16
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$PR_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PR_PP_PG_N_SYMBOL_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module sp_mux_4to1_sel2_7_1 #(
parameter
ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
dout_WIDTH = 32
)(
input [6 : 0] din1,
input [6 : 0] din2,
input [6 : 0] din3,
input [6 : 0] din4,
input [1 : 0] din5,
output [6 : 0] dout);
// puts internal signals
wire [1 : 0] sel;
// level 1 signals
wire [6 : 0] mux_1_0;
wire [6 : 0] mux_1_1;
// level 2 signals
wire [6 : 0] mux_2_0;
assign sel = din5;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0)? din1 : din2;
assign mux_1_1 = (sel[0] == 0)? din3 : din4;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1;
// output logic
assign dout = mux_2_0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int x[100] = {4, 22, 27, 58, 85, 94, 121, 166, 202, 265, 274, 319, 346, 355, 378, 382, 391, 438, 454, 483, 517, 526, 535, 562, 576, 588, 627, 634, 636, 645, 648, 654, 663, 666, 690, 706, 728, 729, 762, 778, 825, 852, 861, 895, 913, 915, 922, 958, 985, 1086, 1111, 1165}; int main() { int a; cin >> a; cout << x[a - 1]; } |
#include <bits/stdc++.h> using namespace std; const long long oo = 1e18; const long long MAXN = 110; long long N; vector<string> query(long long a, long long b) { cout << ? << << a << << b << n ; fflush(stdout); long long sz = b - a + 1; vector<string> vect; for (long long i = 0; i < sz * (sz + 1) / 2; i++) { string cad; cin >> cad; vect.push_back(cad); } return vect; } void res(string cad) { cout << ! << << cad << n ; fflush(stdout); } struct edge { long long nodo; char a, b; }; vector<edge> L[MAXN]; char xx, yy; void solve(vector<string> vect, long long des) { vector<string> arr[MAXN]; long long sz = 0; for (long long i = 0; i < vect.size(); i++) { arr[vect[i].size()].push_back(vect[i]); sz = max(sz, (long long)vect[i].size()); } map<char, long long> cont; for (long long i = 0; i < sz; i++) { cont[arr[sz][0][i]]++; } vector<edge> vv; for (long long i = 2; i <= sz / 2 + 1; i++) { map<char, long long> mp; map<char, long long> temp; for (auto x : cont) { temp[x.first] = x.second * i; } for (long long i = 0; i < vv.size(); i++) { temp[vv[i].a] += i + 1; temp[vv[i].b] += i + 1; } for (auto cad : arr[i]) { for (long long x = 0; x < i; x++) { mp[cad[x]]++; } } char a, b; for (auto x : temp) { if (x.second > mp[x.first]) { a = x.first; break; } } temp[a]--; for (auto x : temp) { if (x.second > mp[x.first]) { b = x.first; break; } } cont[a]--; cont[b]--; vv.push_back({0, a, b}); L[i - 1 + des].push_back({sz - i + 2 + des, a, b}); L[sz - i + 2 + des].push_back({i - 1 + des, a, b}); if (i == 2 && des == 0) { xx = a; yy = b; } } } char ss[MAXN]; void DFS(long long nodo, long long padre, char c) { ss[nodo] = c; for (auto v : L[nodo]) { if (v.nodo != padre) { char temp; if (v.a == c) temp = v.b; else temp = v.a; DFS(v.nodo, nodo, temp); } } } int32_t main() { cin >> N; vector<string> vect = query(1, N); if (N == 1) { res(vect[0]); return 0; } solve(vect, 0); vect = query(2, N); solve(vect, 1); if (xx != yy) { vect = query(1, 1); DFS(1, -1, vect[0][0]); string st; for (long long i = 1; i <= N; i++) st += ss[i]; res(st); } else { DFS(1, -1, xx); string st; for (long long i = 1; i <= N; i++) st += ss[i]; for (long long i = 0; i < N; i++) { if (st[i] != st[N - i - 1]) { vect = query(i + 1, i + 1); char cc = vect[0][0]; if (st[i] != cc) { reverse(st.begin(), st.end()); } break; } } res(st); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_MUX_2TO1_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_MUX_2TO1_BLACKBOX_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_mux_2to1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_MUX_2TO1_BLACKBOX_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = (CIN & S) | (DI & ~S);
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (DI),
.S (S)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long n, d; cin >> n >> d; pair<long long, long long> s[n]; deque<long long> p; long long ind, cnt = 1; for (long long i = 0; i < n; i++) { cin >> s[i].first; s[i].second = i; } for (long long i = 0; i < n; i++) { long long tmp; cin >> tmp; p.push_back(tmp); } s[d - 1].first += p[0]; long long num = s[d - 1].first; p.pop_front(); for (long long i = 0; i < n; i++) { if (s[i].second != d - 1 && s[i].first + p[p.size() - 1] <= num) { s[i].first += p[p.size() - 1]; p.pop_back(); } else if (s[i].second != d - 1) { s[i].first += p[0]; p.pop_front(); } } sort(s, s + n); for (long long i = n - 1; s[i].second != d - 1; i--) { if (s[i].first != num) { cnt++; } } cout << cnt; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, x0; cin >> n >> x0; int x = x0; int a[n][2]; for (int i = 0; i < n; i++) cin >> a[i][0] >> a[i][1]; int c = 0, d = 0; for (int i = 0; i < n; i++) { if (min(a[i][0], a[i][1]) > x) { x = min(a[i][0], a[i][1]); c++; } else if (max(a[i][0], a[i][1]) < x) { d++; x = max(a[i][0], a[i][1]); } if (c > 0 && d > 0) break; } if (c > 0 && d > 0) cout << -1 n ; else { c = 0; for (int i = 0; i < n; i++) { if (x >= min(a[i][0], a[i][1]) && x <= max(a[i][0], a[i][1])) c++; } if (c == n) cout << abs(x - x0) << endl; else cout << -1 n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; int a[100005]; cin >> n; int fa = 1; for (int i = 1; i <= n; i++) { cin >> a[i]; if (a[i] != i) { fa = 0; } } if (fa == 1) { cout << 0 ; } else { int ji = n - 1; while (a[ji] < a[ji + 1]) { ji--; } cout << ji; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_TB_V
`define SKY130_FD_SC_LP__A32O_TB_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a32o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__a32o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_TB_V
|
module main(x,y,p);
input [7:0] x,y;
output [15:0] p;
wire [6:0] ip1;
wire [7:0] ip2,ip3,ip4,ip5,ip6,ip7,ip8,si,iip;
wire [6:0] s1,s2,s3,s4,s5,s6;
wire [7:0] c1,c2,c3,c4,c5,c6,c7;
wire c;
// first AND array
and fi1(p[0],y[0],x[0]);
and fi2(ip1[0],y[0],x[1]);
and fi3(ip1[1],y[0],x[2]);
and fi4(ip1[2],y[0],x[3]);
and fi5(ip1[3],y[0],x[4]);
and fi6(ip1[4],y[0],x[5]);
and fi7(ip1[5],y[0],x[6]);
and fi8(ip1[6],y[0],x[7]);
not n1(si[0],ip1[6]);
// second AND array and NOT GATES
and se1(ip2[0],y[1],x[0]);
and se2(ip2[1],y[1],x[1]);
and se3(ip2[2],y[1],x[2]);
and se4(ip2[3],y[1],x[3]);
and se5(ip2[4],y[1],x[4]);
and se6(ip2[5],y[1],x[5]);
and se7(ip2[6],y[1],x[6]);
and se8(ip2[7],y[1],x[7]);
not n2(si[1],ip2[7]);
//third
and th1(ip3[0],y[2],x[0]);
and th2(ip3[1],y[2],x[1]);
and th3(ip3[2],y[2],x[2]);
and th4(ip3[3],y[2],x[3]);
and th5(ip3[4],y[2],x[4]);
and th6(ip3[5],y[2],x[5]);
and th7(ip3[6],y[2],x[6]);
and th8(ip3[7],y[2],x[7]);
not n3(si[2],ip3[7]);
//fourth
and fo1(ip4[0],y[3],x[0]);
and fo2(ip4[1],y[3],x[1]);
and fo3(ip4[2],y[3],x[2]);
and fo4(ip4[3],y[3],x[3]);
and fo5(ip4[4],y[3],x[4]);
and fo6(ip4[5],y[3],x[5]);
and fo7(ip4[6],y[3],x[6]);
and fo8(ip4[7],y[3],x[7]);
not n4(si[3],ip4[7]);
//fifth
and fif1(ip5[0],y[4],x[0]);
and fif2(ip5[1],y[4],x[1]);
and fif3(ip5[2],y[4],x[2]);
and fif4(ip5[3],y[4],x[3]);
and fif5(ip5[4],y[4],x[4]);
and fif6(ip5[5],y[4],x[5]);
and fif7(ip5[6],y[4],x[6]);
and fif8(ip5[7],y[4],x[7]);
not n5(si[4],ip5[7]);
//sixth
and si1(ip6[0],y[5],x[0]);
and si2(ip6[1],y[5],x[1]);
and si3(ip6[2],y[5],x[2]);
and si4(ip6[3],y[5],x[3]);
and si5(ip6[4],y[5],x[4]);
and si6(ip6[5],y[5],x[5]);
and si7(ip6[6],y[5],x[6]);
and si8(ip6[7],y[5],x[7]);
not n6(si[5],ip6[7]);
//seventh
and sev1(ip7[0],y[6],x[0]);
and sev2(ip7[1],y[6],x[1]);
and sev3(ip7[2],y[6],x[2]);
and sev4(ip7[3],y[6],x[3]);
and sev5(ip7[4],y[6],x[4]);
and sev6(ip7[5],y[6],x[5]);
and sev7(ip7[6],y[6],x[6]);
and sev8(ip7[7],y[6],x[7]);
not n7(si[6],ip7[7]);
//eight
and eii1(iip[0],y[7],x[0]);
and eii2(iip[1],y[7],x[1]);
and eii3(iip[2],y[7],x[2]);
and eii4(iip[3],y[7],x[3]);
and eii5(iip[4],y[7],x[4]);
and eii6(iip[5],y[7],x[5]);
and eii7(iip[6],y[7],x[6]);
and eii8(iip[7],y[7],x[7]);
xor ei1(ip8[0],y[7],iip[0]);
xor ei2(ip8[1],y[7],iip[1]);
xor ei3(ip8[2],y[7],iip[2]);
xor ei4(ip8[3],y[7],iip[3]);
xor ei5(ip8[4],y[7],iip[4]);
xor ei6(ip8[5],y[7],iip[5]);
xor ei7(ip8[6],y[7],iip[6]);
xor ei8(ip8[7],y[7],iip[7]);
not n8(si[7],ip8[7]);
//first adder array
HA ha1(ip1[0],ip2[0],c1[0],p[1]);
FA fa1(ip1[1],ip2[1],c1[0],c1[1],s1[0]);
FA fa2(ip1[2],ip2[2],c1[1],c1[2],s1[1]);
FA fa3(ip1[3],ip2[3],c1[2],c1[3],s1[2]);
FA fa4(ip1[4],ip2[4],c1[3],c1[4],s1[3]);
FA fa5(ip1[5],ip2[5],c1[4],c1[5],s1[4]);
FA fa6(ip1[6],ip2[6],c1[5],c1[6],s1[5]);
FA fa7(si[0],si[1],c1[6],c1[7],s1[6]);
//second adder array
HA ha2(s1[0],ip3[0],c2[0],p[2]);
FA sa1(s1[1],ip3[1],c2[0],c2[1],s2[0]);
FA sa2(s1[2],ip3[2],c2[1],c2[2],s2[1]);
FA sa3(s1[3],ip3[3],c2[2],c2[3],s2[2]);
FA sa4(s1[4],ip3[4],c2[3],c2[4],s2[3]);
FA sa5(s1[5],ip3[5],c2[4],c2[5],s2[4]);
FA sa6(s1[6],ip3[6],c2[5],c2[6],s2[5]);
FA sa7(c1[7],si[2],c2[6],c2[7],s2[6]);
//third adder
HA ha3(s2[0],ip4[0],c3[0],p[3]);
FA ta1(s2[1],ip4[1],c3[0],c3[1],s3[0]);
FA ta2(s2[2],ip4[2],c3[1],c3[2],s3[1]);
FA ta3(s2[3],ip4[3],c3[2],c3[3],s3[2]);
FA ta4(s2[4],ip4[4],c3[3],c3[4],s3[3]);
FA ta5(s2[5],ip4[5],c3[4],c3[5],s3[4]);
FA ta6(s2[6],ip4[6],c3[5],c3[6],s3[5]);
FA ta7(c2[7],si[3],c3[6],c3[7],s3[6]);
//fourth adder
HA ha4(s3[0],ip5[0],c4[0],p[4]);
FA foa1(s3[1],ip5[1],c4[0],c4[1],s4[0]);
FA foa2(s3[2],ip5[2],c4[1],c4[2],s4[1]);
FA foa3(s3[3],ip5[3],c4[2],c4[3],s4[2]);
FA foa4(s3[4],ip5[4],c4[3],c4[4],s4[3]);
FA foa5(s3[5],ip5[5],c4[4],c4[5],s4[4]);
FA foa6(s3[6],ip5[6],c4[5],c4[6],s4[5]);
FA foa7(c3[7],si[4],c4[6],c4[7],s4[6]);
//fifth adder
HA ha5(s4[0],ip6[0],c5[0],p[5]);
FA fia1(s4[1],ip6[1],c5[0],c5[1],s5[0]);
FA fia2(s4[2],ip6[2],c5[1],c5[2],s5[1]);
FA fia3(s4[3],ip6[3],c5[2],c5[3],s5[2]);
FA fia4(s4[4],ip6[4],c5[3],c5[4],s5[3]);
FA fia5(s4[5],ip6[5],c5[4],c5[5],s5[4]);
FA fia6(s4[6],ip6[6],c5[5],c5[6],s5[5]);
FA fia7(c4[7],si[5],c5[6],c5[7],s5[6]);
//sixth adder
HA ha6(s5[0],ip7[0],c6[0],p[6]);
FA sia1(s5[1],ip7[1],c6[0],c6[1],s6[0]);
FA sia2(s5[2],ip7[2],c6[1],c6[2],s6[1]);
FA sia3(s5[3],ip7[3],c6[2],c6[3],s6[2]);
FA sia4(s5[4],ip7[4],c6[3],c6[4],s6[3]);
FA sia5(s5[5],ip7[5],c6[4],c6[5],s6[4]);
FA sia6(s5[6],ip7[6],c6[5],c6[6],s6[5]);
FA sia7(c5[7],si[6],c6[6],c6[7],s6[6]);
//seventh adder
FA ha7(s6[0],ip8[0],y[7],c7[0],p[7]);
FA sea1(s6[1],ip8[1],c7[0],c7[1],p[8]);
FA sea2(s6[2],ip8[2],c7[1],c7[2],p[9]);
FA sea3(s6[3],ip8[3],c7[2],c7[3],p[10]);
FA sea4(s6[4],ip8[4],c7[3],c7[4],p[11]);
FA sea5(s6[5],ip8[5],c7[4],c7[5],p[12]);
FA sea6(s6[6],ip8[6],c7[5],c7[6],p[13]);
FA sea7(c6[7],si[7],c7[6],c7[7],p[14]);
HA ha8(c7[7],1'b1,c,p[15]);
endmodule
module HA(a,b,c,s);
input a,b;
output c,s;
xor x1(s,a,b);
and a1(c,a,b);
endmodule
module FA(a,b,c,cy,sm);
input a,b,c;
output cy,sm;
wire x,y,z;
HA h1(a,b,x,z);
HA h2(z,c,y,sm);
or o1(cy,x,y);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long int> xi; vector<long long int> hi; int main() { long long int n, x, h, ans = 1, temp, temp1, curr, i; scanf( %lld , &n); for (i = 0; i < n; i++) { scanf( %lld %lld , &x, &h); xi.push_back(x); hi.push_back(h); } curr = xi[0]; for (i = 1; i < n; i++) { temp = xi[i] - hi[i]; temp1 = xi[i] + hi[i]; if (temp > curr) { ans++; curr = xi[i]; } else { if (i + 1 < n && temp1 < xi[i + 1]) { ans++; curr = temp1; } else { if (i + 1 == n) ans++; curr = xi[i]; } } } printf( %lld n , ans); return 0; } |
/*
* Copyright (c) 2014, Olof Kindgren <>
* All rights reserved.
*
* Redistribution and use in source and non-source forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in non-source form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module wb_ram_tb;
localparam MEMORY_SIZE_WORDS = 128;
localparam WB_PORTS = 1;
vlog_tb_utils vlog_tb_utils0();
reg wbm_rst = 1'b1;
reg wb_clk = 1'b1;
reg wb_rst = 1'b1;
initial #1800 wbm_rst <= 1'b0;
initial #200 wb_rst <= 1'b0;
always #100 wb_clk <= !wb_clk;
wire [WB_PORTS*32-1:0] wb_adr;
wire [WB_PORTS-1:0] wb_stb;
wire [WB_PORTS-1:0] wb_cyc;
wire [WB_PORTS*3-1:0] wb_cti;
wire [WB_PORTS*2-1:0] wb_bte;
wire [WB_PORTS-1:0] wb_we;
wire [WB_PORTS*4-1:0] wb_sel;
wire [WB_PORTS*32-1:0] wb_dat;
wire [WB_PORTS*32-1:0] wb_rdt;
wire [WB_PORTS-1:0] wb_ack;
wire [31:0] slave_writes;
wire [31:0] slave_reads;
wire [WB_PORTS-1:0] done_int;
genvar i;
generate
for(i=0;i<WB_PORTS;i=i+1) begin : masters
wb_bfm_transactor
#(.MEM_HIGH (MEMORY_SIZE_WORDS*(i+1)-1),
.MEM_LOW (MEMORY_SIZE_WORDS*i),
.VERBOSE (1))
wb_bfm_transactor0
(.wb_clk_i (wb_clk),
.wb_rst_i (wbm_rst),
.wb_adr_o (wb_adr[i*32+:32]),
.wb_dat_o (wb_dat[i*32+:32]),
.wb_sel_o (wb_sel[i*4+:4]),
.wb_we_o (wb_we[i] ),
.wb_cyc_o (wb_cyc[i]),
.wb_stb_o (wb_stb[i]),
.wb_cti_o (wb_cti[i*3+:3]),
.wb_bte_o (wb_bte[i*2+:2]),
.wb_dat_i (wb_rdt[i*32+:32]),
.wb_ack_i (wb_ack[i]),
.wb_err_i (1'b0),
.wb_rty_i (1'b0),
//Test Control
.done(done_int[i]));
end // block: slaves
endgenerate
integer idx;
time start_time[WB_PORTS-1:0];
time ack_delay[WB_PORTS-1:0];
integer num_transactions[WB_PORTS-1:0];
assign done = &done_int;
always @(done) begin
if(done === 1) begin
$display("Average wait times");
for(idx=0;idx<WB_PORTS;idx=idx+1)
$display("Master %0d : %f",idx, ack_delay[idx]/num_transactions[idx]);
$display("All tests passed!");
$finish;
end
end
generate
for(i=0;i<WB_PORTS;i=i+1) begin : wait_time
initial begin
ack_delay[i] = 0;
num_transactions[i] = 0;
while(1) begin
@(posedge wb_cyc[i]);
start_time[i] = $time;
@(posedge wb_ack[i]);
ack_delay[i] = ack_delay[i] + $time-start_time[i];
num_transactions[i] = num_transactions[i]+1;
end
end
end
endgenerate
wb_ram
#(.depth (MEMORY_SIZE_WORDS))
wb_ram0
(// Wishbone interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wb_adr[$clog2(MEMORY_SIZE_WORDS)-1:0]),
.wb_stb_i (wb_stb),
.wb_cyc_i (wb_cyc),
.wb_cti_i (wb_cti),
.wb_bte_i (wb_bte),
.wb_we_i (wb_we) ,
.wb_sel_i (wb_sel),
.wb_dat_i (wb_dat),
.wb_dat_o (wb_rdt),
.wb_ack_o (wb_ack),
.wb_err_o ());
endmodule
|
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_encoder
// ============================================================
// File Name: alt_ddrx_encoder_40.v
// Megafunction Name(s):
// altecc_encoder
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Internal Build 157 07/06/2009 PN Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_encoder CBX_AUTO_BLACKBOX="ALL" device_family="Stratix" lpm_pipeline=1 width_codeword=39 width_dataword=32 clock data q
//VERSION_BEGIN 9.1 cbx_altecc_encoder 2009:06:09:13:39:47:PN cbx_mgl 2009:07:03:02:47:54:PN VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lut 39
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_ddrx_encoder_40_altecc_encoder_plb
(
clock,
data,
q) ;
input clock;
input [31:0] data;
output [38:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [38:0] output_pipeline0c;
wire aclr;
wire clocken;
wire [31:0] data_wire;
wire [17:0] parity_01_wire;
wire [9:0] parity_02_wire;
wire [4:0] parity_03_wire;
wire [1:0] parity_04_wire;
wire [0:0] parity_05_wire;
wire [5:0] parity_06_wire;
wire [37:0] parity_final_wire;
wire [38:0] q_wire;
// synopsys translate_off
initial
output_pipeline0c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) output_pipeline0c <= 39'b0;
else if (clocken == 1'b1) output_pipeline0c <= q_wire;
assign
aclr = 1'b0,
clocken = 1'b1,
data_wire = data,
parity_01_wire = {(data_wire[30] ^ parity_01_wire[16]), (data_wire[28] ^ parity_01_wire[15]), (data_wire[26] ^ parity_01_wire[14]), (data_wire[25] ^ parity_01_wire[13]), (data_wire[23] ^ parity_01_wire[12]), (data_wire[21] ^ parity_01_wire[11]), (data_wire[19] ^ parity_01_wire[10]), (data_wire[17] ^ parity_01_wire[9]), (data_wire[15] ^ parity_01_wire[8]), (data_wire[13] ^ parity_01_wire[7]), (data_wire[11] ^ parity_01_wire[6]), (data_wire[10] ^ parity_01_wire[5]), (data_wire[8] ^ parity_01_wire[4]), (data_wire[6] ^ parity_01_wire[3]), (data_wire[4] ^ parity_01_wire[2]), (data_wire[3] ^ parity_01_wire[1]), (data_wire[1] ^ parity_01_wire[0]), data_wire[0]},
parity_02_wire = {(data_wire[31] ^ parity_02_wire[8]), ((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]), ((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]), ((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]), ((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]), ((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]), ((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]), ((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]), ((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]), data_wire[0]},
parity_03_wire = {(((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ parity_03_wire[3]), ((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]), ((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]), ((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]), ((data_wire[1] ^ data_wire[2]) ^ data_wire[3])},
parity_04_wire = {((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]), ((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])},
parity_05_wire = {((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])},
parity_06_wire = {(data_wire[31] ^ parity_06_wire[4]), (data_wire[30] ^ parity_06_wire[3]), (data_wire[29] ^ parity_06_wire[2]), (data_wire[28] ^ parity_06_wire[1]), (data_wire[27] ^ parity_06_wire[0]), data_wire[26]},
parity_final_wire = {(q_wire[37] ^ parity_final_wire[36]), (q_wire[36] ^ parity_final_wire[35]), (q_wire[35] ^ parity_final_wire[34]), (q_wire[34] ^ parity_final_wire[33]), (q_wire[33] ^ parity_final_wire[32]), (q_wire[32] ^ parity_final_wire[31]), (q_wire[31] ^ parity_final_wire[30]), (q_wire[30] ^ parity_final_wire[29]), (q_wire[29] ^ parity_final_wire[28]), (q_wire[28] ^ parity_final_wire[27]), (q_wire[27] ^ parity_final_wire[26]), (q_wire[26] ^ parity_final_wire[25]), (q_wire[25] ^ parity_final_wire[24]), (q_wire[24] ^ parity_final_wire[23]), (q_wire[23] ^ parity_final_wire[22]), (q_wire[22] ^ parity_final_wire[21]), (q_wire[21] ^ parity_final_wire[20]), (q_wire[20] ^ parity_final_wire[19]), (q_wire[19] ^ parity_final_wire[18]), (q_wire[18] ^ parity_final_wire[17]), (q_wire[17] ^ parity_final_wire[16]), (q_wire[16] ^ parity_final_wire[15]), (q_wire[15] ^ parity_final_wire[14]), (q_wire[14] ^ parity_final_wire[13]), (q_wire[13] ^ parity_final_wire[12]), (q_wire[12] ^ parity_final_wire[11]), (q_wire[11] ^ parity_final_wire[10]), (q_wire[10] ^ parity_final_wire[9]), (q_wire[9] ^ parity_final_wire[8]), (q_wire[8] ^ parity_final_wire[7]), (q_wire[7] ^ parity_final_wire[6]), (q_wire[6] ^ parity_final_wire[5]), (q_wire[5] ^ parity_final_wire[4]), (q_wire[4] ^ parity_final_wire[3]), (q_wire[3] ^ parity_final_wire[2]), (q_wire[2] ^ parity_final_wire[1]), (q_wire[1] ^ parity_final_wire[0]), q_wire[0]},
q = output_pipeline0c,
q_wire = {parity_final_wire[37], parity_06_wire[5], parity_05_wire[0], parity_04_wire[1], parity_03_wire[4], parity_02_wire[9], parity_01_wire[17], data_wire};
endmodule //alt_ddrx_encoder_40_altecc_encoder_plb
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_ddrx_encoder_40 (
clock,
data,
q);
input clock;
input [31:0] data;
output [38:0] q;
wire [38:0] sub_wire0;
wire [38:0] q = sub_wire0[38:0];
alt_ddrx_encoder_40_altecc_encoder_plb alt_ddrx_encoder_40_altecc_encoder_plb_component (
.clock (clock),
.data (data),
.q (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "1"
// Retrieval info: CONSTANT: width_codeword NUMERIC "39"
// Retrieval info: CONSTANT: width_dataword NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 39 0 OUTPUT NODEFVAL "q[38..0]"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 39 0 @q 0 0 39 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_ddrx_encoder_40_bb.v FALSE
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module \$__QLF_RAM16K (
output [31:0] RDATA,
input RCLK, RE,
input [8:0] RADDR,
input WCLK, WE,
input [8:0] WADDR,
input [31:0] WENB,
input [31:0] WDATA
);
generate
DP_RAM16K #()
_TECHMAP_REPLACE_ (
.d_out(RDATA),
.rclk (RCLK ),
.wclk (WCLK ),
.ren (RE ),
.raddr(RADDR),
.wen (WE ),
.waddr(WADDR),
.wenb (WENB ),
.d_in (WDATA)
);
endgenerate
endmodule
module \$__QLF_RAM16K_M0 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter [4095:0] INIT = 4096'bx;
input CLK1;
input [8:0] A1ADDR;
output [31:0] A1DATA;
input A1EN;
input [8:0] B1ADDR;
input [31:0] B1DATA;
input B1EN;
wire [31:0] WENB;
assign WENB = 32'hFFFFFFFF;
\$__QLF_RAM16K #()
_TECHMAP_REPLACE_ (
.RDATA(A1DATA),
.RADDR(A1ADDR),
.RCLK (CLK1 ),
.RE (A1EN ),
.WDATA(B1DATA),
.WADDR(B1ADDR),
.WCLK (CLK1 ),
.WE (B1EN ),
.WENB (WENB )
);
endmodule
module \$__QLF_RAM16K_M1 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter [4095:0] INIT = 4096'bx;
input CLK1;
input [9:0] A1ADDR;
output [31:0] A1DATA;
input A1EN;
input [9:0] B1ADDR;
input [31:0] B1DATA;
input B1EN;
wire [31:0] WENB;
wire [31:0] WDATA;
generate
wire A1BAR;
assign A1BAR = ~A1ADDR[0];
assign WDATA = { {2{B1DATA[15:0]}}};
endgenerate
assign WENB = { {16{A1ADDR[0]}} , {16{A1BAR}}};
\$__QLF_RAM16K #()
_TECHMAP_REPLACE_ (
.RDATA(A1DATA ),
.RADDR(A1ADDR ),
.RCLK (CLK1 ),
.RE (A1EN ),
.WDATA(WDATA ),
.WADDR(B1ADDR[9:1]),
.WCLK (CLK1 ),
.WENB (WENB ),
.WE (B1EN )
);
endmodule
module \$__QLF_RAM16K_M2 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter [4095:0] INIT = 4096'bx;
input CLK1;
input [10:0] A1ADDR;
output [31:0] A1DATA;
input A1EN;
input [10:0] B1ADDR;
input [7:0] B1DATA;
input B1EN;
wire [31:0] WENB;
wire [31:0] WDATA;
generate
wire A1BAR0, A1BAR1;
assign A1BAR0 = ~A1ADDR[0];
assign A1BAR1 = ~A1ADDR[1];
assign WDATA = { {4{B1DATA[7:0]}}};
endgenerate
assign WENB = { {8{A1ADDR[1]& A1ADDR[0]}},
{8{A1ADDR[1]& A1BAR0}} ,
{8{A1BAR1 & A1ADDR[0]}},
{8{A1BAR1 & A1BAR0}}} ;
\$__QLF_RAM16K #()
_TECHMAP_REPLACE_ (
.RDATA(A1DATA ),
.RADDR(A1ADDR ),
.RCLK (CLK1 ),
.RE (A1EN ),
.WDATA(B1DATA ),
.WADDR(B1ADDR[10:2]),
.WCLK (CLK1 ),
.WENB (WENB ),
.WE (B1EN )
);
endmodule
module \$__QLF_RAM16K_M3 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter [4095:0] INIT = 4096'bx;
input CLK1;
input [11:0] A1ADDR;
output [31:0] A1DATA;
input A1EN;
input [11:0] B1ADDR;
input [3:0] B1DATA;
input B1EN;
wire [31:0] WENB;
wire [31:0] WDATA;
generate
assign WDATA = { {8{B1DATA[3:0]}}};
wire A1BAR0, A1BAR1, A1BAR2;
assign A1BAR0 = ~A1ADDR[0];
assign A1BAR1 = ~A1ADDR[1];
assign A1BAR2 = ~A1ADDR[2];
endgenerate
assign WENB = { {4{A1ADDR[2] &A1ADDR[1] & A1ADDR[0]}},
{4{A1ADDR[2] &A1ADDR[1] & A1BAR0}} ,
{4{A1ADDR[2] &A1BAR1 & A1ADDR[0]}},
{4{A1ADDR[2] &A1BAR1 & A1BAR0}} ,
{4{A1BAR2 &A1ADDR[1] & A1ADDR[0]}},
{4{A1BAR2 &A1ADDR[1] & A1BAR0}} ,
{4{A1BAR2 &A1BAR1 & A1ADDR[0]}},
{4{A1BAR2 &A1BAR1 & A1BAR0}}} ;
\$__QLF_RAM16K #()
_TECHMAP_REPLACE_ (
.RDATA(A1DATA ),
.RADDR(A1ADDR ),
.RCLK (CLK1 ),
.RE (A1EN ),
.WDATA(B1DATA ),
.WADDR(B1ADDR[11:3]),
.WCLK (CLK1 ),
.WENB (WENB ),
.WE (B1EN )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, i; double am, vm2, d, tant, ti, vm, t, s, daux, tfin; int main() { scanf( %d %lf %lf , &n, &am, &d); tant = 0; for (i = 0; i < n; i++) { scanf( %lf %lf , &ti, &vm); t = (vm / am); s = 0.5 * (vm * vm / am); daux = d - s; if (daux < 0) { vm2 = sqrt(2 * d * am); tfin = vm2 / am; tfin += ti; } else { tfin = daux / vm; tfin += (ti + t); } if (tfin > tant) { tant = tfin; } printf( %.10lf n , tant); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; for (int i = 0; i < T; i++) { int N; cin >> N; vector<int> vec(N); for (int j = 0; j < N; j++) { cin >> vec.at(j); } if (vec.at(0) + vec.at(1) <= vec.at(N - 1)) { cout << 1 << << 2 << << N << endl; } else { cout << -1 << endl; } } } |
#include <bits/stdc++.h> using namespace std; #define rep(i,a,b) for(int i = (a); i < b; ++i) #define rrep(i,a,b) for(int i = (b); i --> (a);) #define trav(x, v) for(auto &x : v) #define all(v) (v).begin(),(v).end() #define sz(v) (int)(v).size() bool que_big(int s, string x){ cout << s+1 << << x << endl; string res; cin >> res; return res == yes ; } int main(){ int n = 200, b = 200; cin >> n >> b; vector<string> ub(n, string(b, 1 )); string lb(b, 0 ); deque<int> ko; rep(i,0,n) ko.push_back(i); string nxt = string(b, 1 ); nxt[0] = 0 ; while(true){ int s = ko.front(); if(ub[s] < lb){ ko.pop_front(); continue; } if(ub[s] == lb){ cout << 0 << << lb << endl; return 0; } if(que_big(s, nxt)){ lb = nxt; rrep(i,0,b){ if(lb[i]== 0 ){ lb[i] = 1 ; nxt[i] = 1 ; break; } else { lb[i] = 0 ; } } } else { ub[s] = nxt; ko.pop_front(); ko.push_back(s); rep(i,0,b) if(nxt[i] > lb[i]){ nxt[i] = 0 ; break; } } } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:49:08 02/22/2015
// Design Name:
// Module Name: NormaliseProdMult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module NormaliseProdMult(
input [32:0] zout_Multiply,
input [49:0] productout_Multiply,
input clock,
input idle_Multiply,
output reg idle_NormaliseProd,
output reg [32:0] zout_NormaliseProd,
output reg [49:0] productout_NormaliseProd
);
parameter no_idle = 1'b0,
put_idle = 1'b1;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
assign z_sign = zout_Multiply[32];
assign z_exponent = zout_Multiply[31:24];
assign z_mantissa = {zout_Multiply[23:0]};
always @ (posedge clock) begin
idle_NormaliseProd <= idle_Multiply;
if (idle_Multiply == no_idle) begin
// This case will never arise. This is because for input with exponent less than -12 multiply isn't used.
if ($signed(z_exponent) < -126) begin
zout_NormaliseProd[32] <= z_sign;
zout_NormaliseProd[31:24] <= z_exponent + 1;
zout_NormaliseProd[23:0] <= z_mantissa;
productout_NormaliseProd <= productout_Multiply >> 1;
end
// This could be problematic. Will have to test for average number of cycles
// Current solution is to hard code for all cases like normalisation in addition.
else if (productout_Multiply[49] == 0) begin
zout_NormaliseProd[32] <= z_sign;
zout_NormaliseProd[31:24] <= z_exponent - 1;
zout_NormaliseProd[23:0] <= {productout_Multiply[48:25]};
productout_NormaliseProd <= productout_Multiply << 1;
end
else begin
zout_NormaliseProd[32] <= z_sign;
zout_NormaliseProd[31:24] <= z_exponent;
zout_NormaliseProd[23:0] <= {productout_Multiply[49:26]};
productout_NormaliseProd <= productout_Multiply;
end
end
else begin
zout_NormaliseProd <= zout_Multiply;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLXTP_TB_V
`define SKY130_FD_SC_MS__DLXTP_TB_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dlxtp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ms__dlxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLXTP_TB_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file FIFO.v when simulating
// the core, FIFO. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module FIFO(
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full);
input [15 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [15 : 0] dout;
output empty;
output full;
// synthesis translate_off
FIFO_GENERATOR_V5_1 #(
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(4),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(16),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(16),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_FAMILY("spartan3"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(15),
.C_PROG_FULL_THRESH_NEGATE_VAL(14),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(4),
.C_WR_DEPTH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_RESPONSE_LATENCY(1))
inst (
.DIN(din),
.RD_CLK(rd_clk),
.RD_EN(rd_en),
.RST(rst),
.WR_CLK(wr_clk),
.WR_EN(wr_en),
.DOUT(dout),
.EMPTY(empty),
.FULL(full),
.CLK(),
.INT_CLK(),
.BACKUP(),
.BACKUP_MARKER(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.RD_RST(),
.SRST(),
.WR_RST(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_EMPTY(),
.ALMOST_FULL(),
.DATA_COUNT(),
.OVERFLOW(),
.PROG_EMPTY(),
.PROG_FULL(),
.VALID(),
.RD_DATA_COUNT(),
.UNDERFLOW(),
.WR_ACK(),
.WR_DATA_COUNT(),
.SBITERR(),
.DBITERR());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of FIFO is "black_box"
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, a[101], nxt, l, h; int main(int argc, const char* argv[]) { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } int mn = 10001; for (int i = 0; i < n; i++) { nxt = i + 1; nxt %= n; if (mn > abs(a[i] - a[nxt])) { mn = abs(a[i] - a[nxt]); l = i; h = nxt; } } printf( %d %d n , l + 1, h + 1); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__OR3B_BEHAVIORAL_PP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { string s, t; cin >> s; for (int i = s.length() - 1; i >= 0; i--) { if (t == ) { t.push_back(s[i]); } else if (t.back() <= s[i]) { t.push_back(s[i]); } } reverse(t.begin(), t.end()); cout << t; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLXTP_PP_SYMBOL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTP_PP_SYMBOL_V
|
`default_nettype none
//All DFF* have INIT, but the hardware is always initialised to the reset
//value regardless. The parameter is ignored.
// DFFN D Flip-Flop with Negative-Edge Clock
module \$_DFF_N_ (input D, C, output Q);
DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFF D Flip-Flop
module \$_DFF_P_ (input D, C, output Q);
DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFE D Flip-Flop with Clock Enable
module \$_DFFE_PP_ (input D, C, E, output Q);
DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable
module \$_DFFE_NP_ (input D, C, E, output Q);
DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFR D Flip-Flop with Synchronous Reset
module \$_SDFF_PP0_ (input D, C, R, output Q);
DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset
module \$_SDFF_NP0_ (input D, C, R, output Q);
DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset
module \$_SDFFE_PP0P_ (input D, C, R, E, output Q);
DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
module \$_SDFFE_NP0P_ (input D, C, R, E, output Q);
DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFS D Flip-Flop with Synchronous Set
module \$_SDFF_PP1_ (input D, C, R, output Q);
DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set
module \$_SDFF_NP1_ (input D, C, R, output Q);
DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFSE D Flip-Flop with Clock Enable and Synchronous Set
module \$_SDFFE_PP1P_ (input D, C, R, E, output Q);
DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
module \$_SDFFE_NP1P_ (input D, C, R, E, output Q);
DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFP D Flip-Flop with Asynchronous Preset
module \$_DFF_PP1_ (input D, C, R, output Q);
DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
module \$_DFF_NP1_ (input D, C, R, output Q);
DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFC D Flip-Flop with Asynchronous Clear
module \$_DFF_PP0_ (input D, C, R, output Q);
DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
module \$_DFF_NP0_ (input D, C, R, output Q);
DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset
module \$_DFFE_PP1P_ (input D, C, R, E, output Q);
DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
module \$_DFFE_NP1P_ (input D, C, R, E, output Q);
DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear
module \$_DFFE_PP0P_ (input D, C, R, E, output Q);
DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
module \$_DFFE_NP0P_ (input D, C, R, E, output Q);
DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E));
wire _TECHMAP_REMOVEINIT_Q_ = 1;
endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]));
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]));
end else
if (WIDTH == 3) begin
LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]));
end else
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else
if (WIDTH == 5) begin
wire f0, f1;
\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0));
\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1));
MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y));
end else
if (WIDTH == 6) begin
wire f0, f1;
\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0));
\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1));
MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y));
end else
if (WIDTH == 7) begin
wire f0, f1;
\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0));
\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1));
MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y));
end else
if (WIDTH == 8) begin
wire f0, f1;
\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0));
\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1));
MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y));
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule
|
// verilog mode bug1346 testcase
module design(/*AUTOARG*/
// Outputs
y10, y11, y12, y13, y14, y15, y16, y17, y18, y19, y20, y21, y22, y23, y24, y25, y26, y27, y30,
y31, y32, y33, y34, y35, y36, y40, y41, y42, y43, y44, y45,
// Inputs
i0, i1
);
parameter w1 = 2;
parameter w2 = 4;
parameter w3 = 256;
input [w1:0] i0;
input [w2:0] i1;
output [w2*w1 :0] y10; // 8:0
output [w2/w1 :0] y11; // 2:0
output [w2+w1 :0] y12; // 6:0
output [w2-w1 :0] y13; // 2:0
output [w2>>w1 :0] y14; // 1:0
output [w2>>>w1:0] y15; // 1:0
output [w2<<w1 :0] y16; //16:0
output [w2<<<w1:0] y17; //16:0
output [w2<>>w1:0] y18; //4<>>2:0
output [w2>><w1:0] y19; //4>><2:0
output [w1*w2/w1+w1 :0] y20; // 6:0
output [w2*w1/w1+w1 :0] y21; // 6:0
output [w1*w2/(w2-w1)+w1 :0] y22; // 6:0
output [w2*w1/(w2-w1)+w2-w1 :0] y23; // 6:0
output [w2*w1/(w2-w1)+w1<<1>>1 :0] y24; // 6:0
output [w2*w1/(w2-w1)+w1<<w1-w1:0] y25; // 6:0
output [(8*4)-1 :0] y26; // 31:0
output [((w3>>3)-1) :0] y27; // 31:0
output [w2*w1/w1 +w2+w1 <<w2 >>w1 :0] y30; // 40:0
output [w2*w1/w1 +w1+w2 <<w1+w1 >>w2-w1:0] y31; // 40:0
output [w2*w1/w1 +w1+w2 <<w1+w1 >>w2/w1:0] y32; // 40:0
output [w1*w2/w1 +w1+w2 <<w2 >>w1 :0] y33; // 40:0
output [w1*w2/(w2-w1) +w1+w2 <<w2 >>w1 :0] y34; // 40:0
output [w1*w2/(w2/w1) +w1+w2 <<w2 >>w2-w1:0] y35; // 40:0
output [w1*w2/(w1+0) +w1+w2 <<w2 >>w1 :0] y36; // 40:0
output [w2*w1/w1 +w2*1+w1 <<w2/1 *1 >>w1 *1:0] y40; // 40:0
output [w2*w1/w1 +w1*1+w2 <<w1/1+w1*1 >>w2-w1*1:0] y41; // 40:0
output [w2*w1/w1 +w1*1+w2 <<w1/1+w1*1 >>w2/w1*1:0] y42; // 40:0
output [w1*w2/w1 +w1*1+w2 <<w2/1 *1 >>w1 *1:0] y43; // 40:0
output [w1*w2/(w2-w1) +w1*1+w2 <<w2/1 *1 >>w1 *1:0] y44; // 40:0
output [w1*w2/(w2/w1) +w1*1+w2 <<w2/1 *1 >>w2-w1*1:0] y45; // 40:0
endmodule // design
module test(/*AUTOARG*/
// Outputs
y10, y11, y12, y13, y14, y15, y16, y17, y18, y19, y20, y21, y22, y23, y24, y25, y26, y27, y30,
y31, y32, y33, y34, y35, y36, y40, y41, y42, y43, y44, y45,
// Inputs
i0, i1
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [2:0] i0; // To i0_design of design.v
input [4:0] i1; // To i0_design of design.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [8:0] y10; // From i0_design of design.v
output [2:0] y11; // From i0_design of design.v
output [6:0] y12; // From i0_design of design.v
output [2:0] y13; // From i0_design of design.v
output [1:0] y14; // From i0_design of design.v
output [1:0] y15; // From i0_design of design.v
output [16:0] y16; // From i0_design of design.v
output [16:0] y17; // From i0_design of design.v
output [4<>>2:0] y18; // From i0_design of design.v
output [4>><2:0] y19; // From i0_design of design.v
output [6:0] y20; // From i0_design of design.v
output [6:0] y21; // From i0_design of design.v
output [6:0] y22; // From i0_design of design.v
output [6:0] y23; // From i0_design of design.v
output [6:0] y24; // From i0_design of design.v
output [6:0] y25; // From i0_design of design.v
output [31:0] y26; // From i0_design of design.v
output [31:0] y27; // From i0_design of design.v
output [40:0] y30; // From i0_design of design.v
output [40:0] y31; // From i0_design of design.v
output [40:0] y32; // From i0_design of design.v
output [40:0] y33; // From i0_design of design.v
output [40:0] y34; // From i0_design of design.v
output [40:0] y35; // From i0_design of design.v
output [40:0] y36; // From i0_design of design.v
output [40:0] y40; // From i0_design of design.v
output [40:0] y41; // From i0_design of design.v
output [40:0] y42; // From i0_design of design.v
output [40:0] y43; // From i0_design of design.v
output [40:0] y44; // From i0_design of design.v
output [40:0] y45; // From i0_design of design.v
// End of automatics
design #(.w1(2),.w2(4),.w3(256)) i0_design(/*AUTOINST*/
// Outputs
.y10 (y10[8:0]),
.y11 (y11[2:0]),
.y12 (y12[6:0]),
.y13 (y13[2:0]),
.y14 (y14[1:0]),
.y15 (y15[1:0]),
.y16 (y16[16:0]),
.y17 (y17[16:0]),
.y18 (y18[4<>>2:0]),
.y19 (y19[4>><2:0]),
.y20 (y20[6:0]),
.y21 (y21[6:0]),
.y22 (y22[6:0]),
.y23 (y23[6:0]),
.y24 (y24[6:0]),
.y25 (y25[6:0]),
.y26 (y26[31:0]),
.y27 (y27[31:0]),
.y30 (y30[40:0]),
.y31 (y31[40:0]),
.y32 (y32[40:0]),
.y33 (y33[40:0]),
.y34 (y34[40:0]),
.y35 (y35[40:0]),
.y36 (y36[40:0]),
.y40 (y40[40:0]),
.y41 (y41[40:0]),
.y42 (y42[40:0]),
.y43 (y43[40:0]),
.y44 (y44[40:0]),
.y45 (y45[40:0]),
// Inputs
.i0 (i0[2:0]),
.i1 (i1[4:0]));
endmodule // test
// Local Variables:
// verilog-auto-inst-param-value: t
// End:
|
#include <bits/stdc++.h> using namespace std; int main() { vector<int> v, v1; char a[8][8]; for (int i = 0; i < 8; i++) for (int j = 0; j < 8; j++) cin >> a[i][j]; for (int i = 0; i < 8; i++) for (int j = 0; j < 8; j++) { if (a[i][j] == B ) { int b = 0; bool t = true; for (int k = i + 1; k < 8; k++) { b++; if (a[k][j] == B || a[k][j] == W ) { t = false; break; } } if (t == true) v.push_back(b); } if (a[i][j] == W ) { int z = 0; bool t = true; for (int k = i - 1; k >= 0; k--) { z++; if (a[k][j] == B || a[k][j] == W ) { t = false; break; } } if (t == true) { v1.push_back(z); } } } int m = 999, m1 = 999; for (int i = 0; i < v.size(); i++) { m = min(m, v[i]); } for (int i = 0; i < v1.size(); i++) { m1 = min(m1, v1[i]); } if (m >= m1) cout << A ; else cout << B ; return 0; } |
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Generic source synchronous SDR input
*/
module ssio_sdr_in_diff #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire input_clk_p,
input wire input_clk_n,
input wire [WIDTH-1:0] input_d_p,
input wire [WIDTH-1:0] input_d_n,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
wire input_clk;
wire [WIDTH-1:0] input_d;
genvar n;
generate
if (TARGET == "XILINX") begin
IBUFDS
clk_ibufds_inst (
.I(input_clk_p),
.IB(input_clk_n),
.O(input_clk)
);
for (n = 0; n < WIDTH; n = n + 1) begin
IBUFDS
data_ibufds_inst (
.I(input_d_p[n]),
.IB(input_d_n[n]),
.O(input_d[n])
);
end
end else if (TARGET == "ALTERA") begin
ALT_INBUF_DIFF
clk_inbuf_diff_inst (
.i(input_clk_p),
.ibar(input_clk_n),
.o(input_clk)
);
for (n = 0; n < WIDTH; n = n + 1) begin
ALT_INBUF_DIFF
data_inbuf_diff_inst (
.i(input_d_p[n]),
.ibar(input_d_n[n]),
.o(input_d[n])
);
end
end else begin
assign input_clk = input_clk_p;
assign input_d = input_d_p;
end
endgenerate
ssio_sdr_in #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
.WIDTH(WIDTH)
)
ssio_ddr_in_inst(
.input_clk(input_clk),
.input_d(input_d),
.output_clk(output_clk),
.output_q(output_q)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const int MOD = 1e9 + 7; const int dx[4] = {0, 0, -1, 1}; const int dy[4] = {-1, 1, 0, 0}; const int N = 1e5 + 1; int n; long long a[N], s[N], p[N], k; int ans = INF; bool Check(int val) { long long ans = k + 1; for (int l = 1, r = 1; l <= n; l++) { while (r <= n && a[r] - a[l] <= val) r++; r--; long long x = (a[l] * l - p[l]) + (s[r + 1] - (a[l] + val) * (n - r)); ans = min(ans, x); } for (int r = n, l = n; r > 0; r--) { while (l > 0 && a[r] - a[l] <= val) l--; l++; long long x = (s[r] - a[r] * (n - r + 1)) + ((a[r] - val) * (l - 1) - p[l - 1]); ans = min(ans, x); } return (ans <= k); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> k; for (int i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + 1 + n); for (int i = 1; i <= n; i++) p[i] = ((i == 1) ? a[i] : p[i - 1] + a[i]); for (int i = n; i > 0; i--) s[i] = ((i == n) ? a[i] : s[i + 1] + a[i]); int l = 0; int r = INF; while (l <= r) { int m = (l + r) / 2; if (Check(m)) { ans = m; r = m - 1; } else l = m + 1; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int tc; cin >> tc; while (tc--) { int n; cin >> n >> ws; string str; cin >> str; int flag = 0, i; for (i = 0; i < str.size() - 1; i++) { if (str[i] > str[i + 1]) { flag = 1; break; } } if (flag == 0) { cout << str << endl; continue; } string clean_str; for (i = 0; i < str.size(); i++) { if (str[i] == 1 ) break; clean_str.push_back( 0 ); } clean_str.push_back( 0 ); for (i = str.size() - 1; i >= 0; i--) { if (str[i] == 0 ) break; clean_str.push_back( 1 ); } cout << clean_str << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int MOD = 998244353; long long int n; cin >> n; pair<long long int, long long int> arr[n]; for (long long int i = 0; i < n; ++i) cin >> arr[i].first >> arr[i].second; long long int fact[n + 1]; fact[0] = 1; for (long long int i = 1; i <= n; ++i) { fact[i] = (fact[i - 1] * i + MOD) % MOD; } map<long long int, long long int> count1; map<long long int, long long int> count2; map<pair<long long int, long long int>, long long int> count3; for (long long int i = 0; i < n; ++i) { count1[arr[i].first]++; count2[arr[i].second]++; count3[make_pair(arr[i].first, arr[i].second)]++; } long long int n1 = 1, n2 = 1, n3 = 1; map<long long int, long long int>::iterator it; for (it = count1.begin(); it != count1.end(); ++it) { n1 = (n1 * (fact[it->second]) + MOD) % MOD; } for (it = count2.begin(); it != count2.end(); ++it) { n2 = (n2 * (fact[it->second]) + MOD) % MOD; } map<pair<long long int, long long int>, long long int>::iterator itd; long long int last2 = -1; for (itd = count3.begin(); itd != count3.end(); ++itd) { n3 = (n3 * (fact[itd->second]) + MOD) % MOD; if (itd->first.second < last2) { n3 = 0; break; } last2 = itd->first.second; } long long int ans = (fact[n] - n1 - n2 + n3 + 2 * MOD) % MOD; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; cout << (regex_match(s, regex( (1|14|144)* )) ? YES : NO ); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__NOR3B_FUNCTIONAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> #include <iostream> #define ll long long using namespace std; const long long mod=998244353; const long long mod2=1ll<<32; const double pi = 2 * acos(0.0); const ll N=200001; bool compare(pair<int,int> quan1,pair<int,int> quan2) { return quan1.second <quan2.second ; } ll power(ll base,ll expo) { ll ans=1; while(expo>0) { if(expo%2==1) { ans*=base; ans=(ans)%mod; expo--; } else { base*=base; base=(base)%mod; expo/=2; } } return ans; } ll minimax(ll t, bool isMax,ll score,ll h,ll scores[]) { if (t+1 == h) return score; if (isMax&&scores[t]!=1) { if(scores[t]%2==0) { return max(minimax(t+1, false, score+scores[t]-1, h,scores), minimax(t+1,true, score+scores[t], h,scores)); } else { return max(minimax(t+1, true, score+scores[t]-1, h,scores), minimax(t+1, false, score+scores[t], h,scores)); } } else if (isMax&&scores[t]==1) { return minimax(t+1, false, score+1, h,scores); } else if (!isMax&&scores[t]!=1) { if(scores[t]%2==0) { return max(minimax(t+1, true, score, h,scores), minimax(t+1,false, score, h,scores)); } else { return max(minimax(t+1, false, score, h,scores), minimax(t+1, true, score, h,scores)); } } else if (!isMax&&scores[t]==1) { return minimax(t+1, true, score, h,scores); } } long long exponentiation(long long num_one,long long num_two,long long Mod) { long long answer= 1; num_one = ((num_one)+Mod) % Mod; while (num_two > 0) { if (num_two & 1) { answer =(((answer*num_one))+Mod) % Mod; } num_two = num_two>>1; num_one = (((num_one*num_one))+Mod) % Mod; } return ((answer%Mod))%Mod; } ll combi(ll n,ll r,ll mod) { if(r==0) { return 1; } if(r>n) { return 0; } ll factorial[N+1]; ll inverse_fac[N+1]; factorial[0]=1; inverse_fac[0]=1; for(ll i=1;i<=n;i++) { factorial[i]=(factorial[i-1]*i)%mod; inverse_fac[i]=power(factorial[i],mod-2); } return factorial[n]* inverse_fac[r]%mod* inverse_fac[n-r]%mod; } long long gcd(long long a,long long b) { if(b==0) { return a; } else { return gcd(b,a%b); } } ll LCM(ll aa[],ll n,ll Mod) { ll lcm = aa[0]; for (ll i=1;i<n;i++) { lcm = ((((aa[i]*lcm)%Mod)+Mod)%Mod)/(gcd(aa[i],lcm)); } return lcm; } vector<ll> finding_all_prime_factors(ll n) { vector<ll> v; while(n%2==0) { v.push_back(2); n = n/2; } for (ll y=3;y*y<=(n);y+=2) { while (n%y==0) { v.push_back(y); n = n/y; } } if(n>2) { v.push_back(n); } return v; } ll dfs(unordered_map<ll,ll> &size,ll node,bool visit[],vector<ll> adj[]) { visit[node]=true; ll s=1; for(int i=0;i<adj[node].size();i++) { if(visit[adj[node][i]]==false) { s+=dfs(size,adj[node][i],visit,adj); } } size[node]=s; return size[node]; } ll node; void b_f_s(ll visited[],queue<ll> q,ll vertex,vector<ll> v[],vector<ll> adj[]) { q.push(vertex); visited[vertex]=1; while(q.size()>0) { node=q.front(); visited[node]=1; q.pop(); for(ll i=0;i<adj[node].size();i++) { if(visited[adj[node][i]]==0) { //visited[adj[node][i]]=1; q.push(adj[node][i]); v[adj[node][i]]=v[node]; v[adj[node][i]].push_back(node); } } } } void sieve_to_count_primes(ll n) { ll is_it_prime[1000001]; for(ll i=1;i<=1000000;i++) { is_it_prime[i]=1; } for(ll i=2;i<=sqrt(1000000);i++) { if(is_it_prime[i]==1) { for(ll j=i*i;j<=1000000;) { is_it_prime[j]=0; j+=i; } } } } ll LIS_Size(vector<ll>& v) { if(v.size()==0) { return 0; } vector<ll> vv(v.size(),0); ll size=1; vv[0]=v[0]; for (ll i=1;i<v.size();i++) { auto b=vv.begin(),e =vv.begin()+size; auto iter=lower_bound(b,e,v[i]); if(iter==vv.begin()+size) { vv[size]=v[i]; size++; } else { *iter=v[i]; } } return size; } ll sum_in_rational_form_up(ll n,ll ups[],ll downs[],ll Mod) { ll ans_down=LCM(downs,n,Mod); ll ans_up=0; for (ll j=0;j<n;j++) { ans_up=(ans_up+((ups[j])*(ans_down/downs[j])))%Mod; } ll g_c_d=gcd(ans_up,ans_down); ans_up/=g_c_d; ans_down/=g_c_d; //cout<<ans_up<< <<ans_down; return ((ans_up%Mod)+Mod)%Mod; //cout<<ans.first<< <<ans.second; } ll sum_in_rational_form_down(ll n,ll ups[],ll downs[],ll Mod) { ll ans_down=LCM(downs,n,Mod); ll ans_up=0; for (ll j=0;j<n;j++) { ans_up=(ans_up+((ups[j])*(ans_down/downs[j])))%Mod; } ll g_c_d=gcd(ans_up,ans_down); ans_up/=g_c_d; ans_down/=g_c_d; //cout<<ans_up<< <<ans_down; return (ans_down%Mod+Mod)%Mod; //cout<<ans.first<< <<ans.second; } ll mod_inverse(ll a,ll m) { ll GCD=gcd(a,m); if(GCD==1) { return power(a,m-2); } } bool possible(ll ind,vector<ll>& from_left,ll val1,ll val2,vector<ll>& from_right) { ll n=from_left.size(); if(ind>=1&&(ind+2)<n) { if(val2>=from_left[ind-1]&&((val1-(val2-from_left[ind-1]))==from_right[ind+2])) { return true; } else { return false; } } else if(ind==0) { if(((val1-val2)==from_right[ind+2])) { return true; } else { return false; } } else { if(((val2-val1)==from_left[ind-1])) { return true; } else { return false; } } } int main() { ios::sync_with_stdio(false); cin.tie(0); ll t,n,k,m; cin>>t; while(t--) { cin>>n; vector<ll> aa(n); for(ll i=0;i<n;i++) { cin>>aa[i]; } if(n==2) { if(aa[0]==aa[1]) { cout<< YES <<endl; } else { cout<< NO <<endl; } } else { vector<ll> bb(n); bb=aa; vector<ll> from_left(n),from_right(n); from_left[0]=bb[0]; for(ll i=1;i<n;i++) { if(bb[i]<from_left[i-1]) { from_left[i]=LLONG_MIN; continue; } if(from_left[i-1]==LLONG_MIN) { from_left[i]=LLONG_MIN; continue; } from_left[i]=bb[i]-from_left[i-1]; } bb=aa; from_right[n-1]=bb[n-1]; for(ll i=n-2;i>=0;i--) { if(bb[i]<from_right[i+1]) { from_right[i]=LLONG_MIN; continue; } if(from_right[i+1]==LLONG_MIN) { from_right[i]=LLONG_MIN; continue; } from_right[i]=bb[i]-from_right[i+1]; } ll f=0; if(from_left[n-1]==0||from_right[0]==0) { f=1; } for(ll i=0;i<n-1;i++) { if(i>=1&&from_left[i-1]==LLONG_MIN) { continue; } if(i+2<=(n-1)&&from_right[i+2]==LLONG_MIN) { continue; } if(possible(i,from_left,aa[i],aa[i+1],from_right)==true) { f=1; break; } } if(f==1) { cout<< YES <<endl; } else { cout<< NO <<endl; } } } return 0; } |
module top(input count, count_sw, thresh_sw,
output gtu, gts, ltu, lts, geu, ges, leu, les, zero, max,
output gtu_n, gts_n, ltu_n, lts_n, geu_n, ges_n, leu_n, les_n, zero_n, max_n
);
reg [31:0] threshold = 32'b0;
reg [31:0] threshold_down = 32'b0;
reg [31:0] counter = 32'b0;
reg [31:0] counter_down = 32'b0;
wire clk;
BUFG bufg(.I(count), .O(clk));
always @(posedge clk) begin
if (count_sw) begin
counter <= counter + 1;
counter_down <= counter_down - 1;
end
if (thresh_sw) begin
threshold <= counter - 32'd31;
threshold_down <= counter_down + 32'd31;
end else begin
threshold <= threshold + 1;
threshold_down <= threshold_down - 1;
end
end
assign zero = counter == 32'b0;
assign max = counter == 32'hFFFFFFFF;
assign gtu = counter > threshold;
assign gts = $signed(counter) > $signed(threshold);
assign ltu = counter < threshold;
assign lts = $signed(counter) < $signed(threshold);
assign geu = counter >= threshold;
assign ges = $signed(counter) >= $signed(threshold);
assign leu = counter <= threshold;
assign les = $signed(counter) <= $signed(threshold);
assign zero_n = counter_down == 32'b0;
assign max_n = counter_down == 32'hFFFFFFFF;
assign gtu_n = counter_down > threshold_down;
assign gts_n = $signed(counter_down) > $signed(threshold_down);
assign ltu_n = counter_down < threshold_down;
assign lts_n = $signed(counter_down) < $signed(threshold_down);
assign geu_n = counter_down >= threshold_down;
assign ges_n = $signed(counter_down) >= $signed(threshold_down);
assign leu_n = counter_down <= threshold_down;
assign les_n = $signed(counter_down) <= $signed(threshold_down);
endmodule
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Top level module for pipelined memory access.
//
// Properties - Coalesced: No, Ordered: N/A, Hazard-Safe: Yes, Pipelined: Yes
// (see lsu_top.v for details)
//
// Description: Requests are submitted as soon as they are received.
// Pipelined access to memory so multiple requests can be
// in flight at a time.
// Pipelined read unit:
// Accept read requests on the upstream interface. When a request is
// received, store the requested byte address in the request fifo and
// pass the request through to the avalon interface. Response data
// is buffered in the response fifo and the appropriate word is muxed
// out of the response fifo based on the address in the request fifo.
// The response fifo has limited capacity, so a counter is used to track
// the number of pending responses to generate an upstream stall if
// we run out of room.
// altera message_off 10036
module lsu_enabled_read
(
clk, reset, o_stall, i_valid, i_address, i_burstcount, i_stall, o_valid, o_readdata,
o_active, //Debugging signal
avm_enable, avm_address, avm_read, avm_readdata, avm_waitrequest, avm_byteenable,
avm_readdatavalid,
avm_burstcount
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // The max number of live threads
parameter BURSTCOUNT_WIDTH=6; // Size of Avalon burst count port
// Derived parameters
localparam MAX_BURST=2**(BURSTCOUNT_WIDTH-1);
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [BURSTCOUNT_WIDTH-1:0] i_burstcount;
// Downstream interface
input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;
output reg o_active;
// Avalon interface
output avm_enable;
output [AWIDTH-1:0] avm_address;
output avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_readdatavalid;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
/***************
* Architecture *
***************/
wire [BYTE_SELECT_BITS-1:0] byte_select;
always @(posedge clk) begin
if (reset) begin
o_active <= 1'b0;
end else begin
o_active <= i_valid & ~i_stall;
end
end
// Optional Pipeline register before return
//
reg r_avm_readdatavalid;
reg [MWIDTH-1:0] r_avm_readdata;
// Don't register the return
always@(*)
begin
r_avm_readdata = avm_readdata;
r_avm_readdatavalid = avm_readdatavalid;
end
wire [WIDTH-1:0] rdata;
// Byte-addresses enter a FIFO so we can demux the appropriate data back out.
generate
if(SEGMENT_SELECT_BITS > 0)
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_address_out;
wire [SEGMENT_SELECT_BITS-1:0] segment_address_in;
assign segment_address_in = i_address[ALIGNMENT_ABITS +: BYTE_SELECT_BITS-ALIGNMENT_ABITS];
acl_data_fifo #(
.DATA_WIDTH(SEGMENT_SELECT_BITS),
.DEPTH(KERNEL_SIDE_MEM_LATENCY - 1),
.ALLOW_FULL_WRITE(1),
.IMPL("shift_reg")
) req_fifo (
.clock(clk),
.resetn(~reset),
.data_in( segment_address_in ),
.data_out( segment_address_out ),
.valid_in(i_valid), //should be tied to 1 in enable cluster
.valid_out(),
.stall_in(i_stall),
.stall_out()
);
assign byte_select = (segment_address_out << ALIGNMENT_ABITS);
assign rdata = r_avm_readdata[8*byte_select +: WIDTH];
end
else
begin
assign byte_select = '0;
assign rdata = r_avm_readdata;
end
endgenerate
assign avm_byteenable = {MWIDTH_BYTES{1'b1}};
assign avm_address = ((i_address >> BYTE_SELECT_BITS) << BYTE_SELECT_BITS);
assign avm_read = i_valid;
assign avm_burstcount = i_burstcount;
assign avm_enable = ~i_stall;
assign o_stall = i_stall; //not used by enable cluster
assign o_valid = r_avm_readdatavalid; //not used by enable cluster
assign o_readdata = rdata;
endmodule
/******************************************************************************/
// Pipelined write unit:
// Accept write requests on the upstream interface. Mux the data into the
// appropriate word lines based on the segment select bits. Also toggle
// the appropriate byte-enable lines to preserve data we are not
// overwriting. A counter keeps track of how many requests have been
// send but not yet acknowledged by downstream blocks.
module lsu_enabled_write
(
clk, reset, o_stall, i_valid, i_address, i_writedata, i_stall, o_valid, i_byteenable,
o_active, //Debugging signal
avm_enable, avm_address, avm_write, avm_writeack, avm_writedata, avm_byteenable, avm_waitrequest
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access
parameter MWIDTH_BYTES=32; // Width of the global memory bus
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter USE_BYTE_EN=0;
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
localparam SEGMENT_WIDTH=8*(2**ALIGNMENT_ABITS);
localparam SEGMENT_WIDTH_BYTES=(2**ALIGNMENT_ABITS);
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
input [WIDTH_BYTES-1:0] i_byteenable;
// Downstream interface
input i_stall;
output o_valid;
output reg o_active;
// Avalon interface
output avm_enable;
output [AWIDTH-1:0] avm_address;
output avm_write;
input avm_writeack;
output reg [MWIDTH-1:0] avm_writedata;
output reg [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
/***************
* Architecture *
***************/
wire [WIDTH_BYTES-1:0] byteenable;
assign byteenable = USE_BYTE_EN ? i_byteenable : {WIDTH_BYTES{1'b1}};
// Avalon interface
assign avm_address = ((i_address >> BYTE_SELECT_BITS) << BYTE_SELECT_BITS);
assign avm_write = i_valid;
// Mux in the correct data
generate
if(SEGMENT_SELECT_BITS > 0)
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_select;
assign segment_select = i_address[ALIGNMENT_ABITS +: BYTE_SELECT_BITS-ALIGNMENT_ABITS];
always@(*)
begin
avm_writedata = {MWIDTH{1'bx}};
avm_writedata[segment_select*SEGMENT_WIDTH +: WIDTH] = i_writedata;
avm_byteenable = {MWIDTH_BYTES{1'b0}};
avm_byteenable[segment_select*SEGMENT_WIDTH_BYTES +: WIDTH_BYTES] = byteenable;
end
end
else
begin
always@(*)
begin
avm_writedata = i_writedata;
avm_byteenable = byteenable;
end
end
endgenerate
assign avm_enable = ~i_stall;
assign o_stall = i_stall; //not used in enable cluster
assign o_valid = avm_writeack; //not used in enable cluster
endmodule
|
#include <bits/stdc++.h> int a[201][3]; using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; vector<string> a; for (int i = 0; i < n; i++) { string r; cin >> r; a.push_back(r); } int count = 0, ans = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < a[i].size(); j++) { if (a[i][j] == 4 || a[i][j] == 7 ) count++; if (count > k) break; } if (count <= k) ans++; count = 0; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; bool prime[1007]; int n; void sieve() { for (int i = 4; i <= 1005; i += 2) prime[i] = false, prime[i - 1] = true; prime[2] = true; for (int i = 3; i <= 1000; i += 2) { if (prime[i]) { for (int j = i * i; j <= 1005; j += i * 2) prime[j] = false; } } } int main() { ios::sync_with_stdio(false); sieve(); scanf( %d , &n); vector<int> ans; for (int i = 1; i <= n; i++) { if (prime[i]) { int q = 1; while (q <= n / i) { q *= i; ans.push_back(q); } } } cout << (ans.size()) << endl; for (int i : ans) { printf( %d , i); } return 0; } |
#include <bits/stdc++.h> using namespace std; struct type { int a, b; } b[17]; int p[17]; int a[17]; int ans[101]; bitset<2001> f[65536]; int n, K, L, i, j, k, l, sum, len, s, tot; bool cmp(type a, type b) { return a.b > b.b; } int main() { p[1] = 1; for (i = 2; i <= 16; i++) p[i] = p[i - 1] << 1; scanf( %d%d , &n, &K); L = (p[n] << 1) - 1; for (i = 1; i <= n; i++) scanf( %d , &a[i]), sum += a[i]; sum /= K; f[0][0] = 1; for (i = 1; i <= L; i++) { for (j = 1; j <= n; j++) if (i & p[j]) f[i] |= f[i ^ p[j]] << a[j]; for (j = sum; j >= 1; j--) if (f[i][j * K]) f[i][j] = 1; } if (!f[L][1]) printf( NO n ); else { printf( YES n ); s = L; j = 1; while (j) { if (j <= sum && f[s][j * K]) { j *= K; ans[++len] = -1; continue; } for (i = 1; i <= n; i++) if (s & p[i] && j >= a[i] && f[s - p[i]][j - a[i]]) { s -= p[i]; j -= a[i]; ans[++len] = i; break; } } j = 0; for (i = 1; i <= len; i++) if (ans[i] == -1) ++j; else b[++tot] = {a[ans[i]], -j}; while (tot > 1) { sort(b + 1, b + tot + 1, cmp); printf( %d %d n , b[tot - 1].a, b[tot].a); b[tot - 1].a += b[tot].a; --tot; while (!(b[tot].a % K)) b[tot].a /= K, ++b[tot].b; } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O211AI_PP_SYMBOL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o211ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; string a, b; int k; int main() { cin >> a; k = 1; if (a.size() % 2 == 0) { while (k != a.size() + 1) { if (k % 2 != 0) { b += a[a.size() - k / 2 - 1]; } else { b += a[k / 2 - 1]; } k++; } } else { while (k != a.size() + 1) { if (k % 2 == 0) { b += a[a.size() - k / 2]; } else { b += a[k / 2]; } k++; } } reverse(b.begin(), b.end()); cout << b; } |
//-------------------------------------------------------------------
//-- tristate1_tb.v
//-- Banco de pruebas para la puerta tri-estado
//-------------------------------------------------------------------
//-- BQ November 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL license
//-------------------------------------------------------------------
//-------------------------------------------------------------------
//-- Este codigo simula bien, pero NO se sintetiza con Yosys + icestorm:
//-- Todavía el sopote para puertas tri-estado no es completo
//-- Mensaje de error:
/*
*/
module error2_tb();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Led a controlar
wire [1:0] leds;
//-- Instanciar el componente
error2
dut(
.clk(clk),
.leds(leds)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk = ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("error2_tb.vcd");
$dumpvars(0, error2_tb);
# 100 $display("FIN de la simulacion");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1000000007; const long long linf = 1LL << 62; const unsigned long long ulinf = 1ULL << 63; const double eps = 0.000001; const double pi = 3.14159265358979323846; template <class T> T abs(T a) { return a >= 0 ? a : -a; } template <class T> T sqr(T a) { return a * a; } template <class T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } template <class T> T mod(T a, T b) { return (a % b + b) % b; } template <class T> T addmod(T a, T b, T c) { return (T)mod((long long)a + b, (long long)c); } template <class T> T mulmod(T a, T b, T c) { return (T)mod((long long)a * b, (long long)c); } template <class T> T powmod(T a, T b, T c) { return (T)mod( b ? mulmod(mod(sqr((long long)powmod(a, b >> 1, c)), (long long)c), (b & 1LL) ? a : 1LL, (long long)c) : 1LL, (long long)c); } template <class T> void maxe(T &a, T b) { a = max(a, b); } template <class T> void mine(T &a, T b) { a = min(a, b); } template <class T> void mode(T &a, T b) { a = mod(a, b); } template <class T> void addmode(T &a, T b, T c) { a = addmod(a, b, c); } template <class T> void mulmode(T &a, T b, T c) { a = mulmod(a, b, c); } template <class T> void powmode(T &a, T b, T c) { a = powmod(a, b, c); } int iszero(double a) { return abs(a) <= eps; } template <class T> void geti(T &a) { a = 0; long long b = 1; char c = getchar(); if (c == - ) b = -1; else a = c - 48; while ((c = getchar()) != && c != n ) a = a * 10 + c - 48; a *= b; } void fileio_in_out() { freopen( .in , r , stdin); freopen( .out , w , stdout); } void fileio_txt() { freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); } const int N = 1111111; const int M = 1111111; int test; long long n, m, k, ans; long long dp[N]; long long s[N], sinv[N]; const long long md = inf; long long c(long long a, long long b) { return s[a] * (sinv[b] * sinv[a - b] % md) % md; } long long inv(long long a, long long p) { return powmod(a, p - 2, p); } long long getans() { if (n == 0) return k ^ (m > 1); if (m == 0) return k ^ (n & 1); s[0] = sinv[0] = 1; for (long long i = 1; i <= n + m; i++) { s[i] = s[i - 1] * i % md; sinv[i] = sinv[i - 1] * inv(i, md) % md; } if (k) n--; dp[0] = (m > 1); for (long long i = 1; i <= n; i++) dp[i] = (c(i + m, i) - dp[i - 1] + md) % md; return dp[n]; } int main() { scanf( %I64d%I64d%I64d , &n, &m, &k); ans = getans(); printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> const int N = 200020; int _, n, m, x, y, flag, a[N], c[N], d[N]; std::queue<int> q; std::pair<int, int> b[N]; std::vector<int> g[N], ans; void f(int u) { if (++a[u] > g[u].size() && !c[u]) q.push(u), c[u] = 1; } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= m; i++) { scanf( %d%d , &x, &y); b[i] = {x, y}; g[x].push_back(i); g[y].push_back(i); } for (int i = 1; i <= n; i++) f(i); for (; q.size(); q.pop()) for (int u : g[q.front()]) if (!d[u]) ans.push_back(u), f(b[u].first), f(b[u].second), d[u] = 1; if (ans.size() == m) { puts( ALIVE ); reverse(ans.begin(), ans.end()); for (int j : ans) printf( %d , j); } else puts( DEAD ); } |
#include <bits/stdc++.h> using namespace std; char vis[305][305]; int main() { int n; cin >> n; vector<int> v(n); for (int i = 0; i < n; i++) cin >> v[i]; char c; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> vis[i][j]; } } for (int k = 0; k < n; k++) { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (vis[i][k] == 1 && vis[k][j] == 1 ) vis[i][j] = 1 ; } } } for (int i = 0; i < n; i++) { int in = i; for (int j = i + 1; j < n; j++) { if (v[in] > v[j] && vis[in][j] == 1 ) { in = j; } } swap(v[i], v[in]); } for (int i = 0; i < n; i++) cout << v[i] << ; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
// SPDX-License-Identifier: CC0-1.0
// Test for trace file interface aliasing
typedef struct packed {
integer val100;
integer val200;
} struct_t;
// This interface is not connected to any cells
interface ifc_inner(input integer cyc);
integer value;
endinterface
interface ifc (input logic clk,
input integer cyc);
integer value;
struct_t the_struct;
ifc_inner inner (.*);
endinterface
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
ifc intf_1(.*);
ifc intf_2(.*);
always @(*) begin
intf_1.value = cyc + 1;
intf_2.value = cyc + 2;
end
sub_struct s1 (.intf_for_struct(intf_1));
sub_struct s2 (.intf_for_struct(intf_2));
sub_check c1 (.intf_for_check(intf_1));
sub_check c2 (.intf_for_check(intf_2));
sub_all a (.intf_one(intf_1),
.intf_two(intf_2));
// Intentionally longer scope name
sub_all abcdefghijklmnopqrstuvwxyz (.intf_one(intf_2),
.intf_two(intf_1));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==20) begin
if (intf_1.value != 21) $stop;
if (intf_2.value != 22) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub_struct
(
ifc intf_for_struct
);
always @(*) begin
intf_for_struct.the_struct.val100 = intf_for_struct.value + 100;
intf_for_struct.the_struct.val200 = intf_for_struct.value + 200;
end
endmodule
module sub_check
(
ifc intf_for_check
);
`ifdef NO_INLINE_A
//verilator no_inline_module
`endif
always @(posedge intf_for_check.clk) begin
if (intf_for_check.the_struct.val100 != intf_for_check.value + 100) $stop;
if (intf_for_check.the_struct.val200 != intf_for_check.value + 200) $stop;
end
endmodule
module sub_all
(
ifc intf_one,
ifc intf_two
);
`ifdef NO_INLINE_B
//verilator no_inline_module
`endif
ifc intf_in_sub_all (
.clk(intf_one.clk),
.cyc(intf_one.cyc)
);
assign intf_in_sub_all.value = intf_one.value + 1000;
sub_check ac1 (.intf_for_check(intf_one));
sub_check ac2 (.intf_for_check(intf_two));
sub_struct as3 (.intf_for_struct(intf_in_sub_all));
sub_check ac3 (.intf_for_check(intf_in_sub_all));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string x, y; cin >> x >> y; for (long long int i = 0; i < x.size(); i++) { if (x[i] == y[i]) cout << 0; else cout << 1; } } |
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; int main() { int n, d, h; cin >> n >> d >> h; if (h * 2 < d || h > n || d > n || h > d || n < d + 1 || (h == 1 && d == 1 && (n != 2))) cout << -1; else { if (h == 1) { for (int i = 2; i <= n; i++) cout << 1 << << i << endl; return 0; } for (int i = 1; i <= h; i++) cout << i << << i + 1 << endl; for (int i = 1; i <= d - h; i++) cout << ((i == 1) ? 1 : i + h) << << i + h + 1 << endl; for (int i = 0; i < n - d - 1; i++) cout << 2 << << n - i << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; using pii = pair<int, int>; using ll = long long; const int N = 3e3 + 3; int a[N][N]; pii sum[N]; int main() { ios_base::sync_with_stdio(false); int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) cin >> a[i][j]; } vector<int> res; int mn = 1e9; for (int i = 0; i < n - 1; i++) { vector<pii> ve; int sum = 0; for (int j = 0; j < m; j++) { sum += a[j][i] - a[j][n - 1]; ve.push_back({a[j][i] - a[j][n - 1], j}); } sort(ve.begin(), ve.end()); vector<int> cur; for (int i = 0; i < m; i++) { if (sum >= 0) break; sum -= ve[i].first; cur.push_back(ve[i].second); } if (cur.size() < mn) { mn = cur.size(); res = cur; } } cout << res.size() << n ; for (auto x : res) cout << ++x << ; cout << n ; return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:23:10 01/08/2015
// Design Name: Top_N3_Computer_IOBUS_VGA_PS2
// Module Name: E:/Study/PentiumX/Hardware/PentiumX_OnSoC/test_Top.v
// Project Name: PentiumX_OnSoC
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Top_N3_Computer_IOBUS_VGA_PS2
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_Top;
// Inputs
reg clk_100mhz;
reg [3:0] BTN;
reg [7:0] SW;
reg PS2_clk;
reg PS2_Data;
reg uart_rx;
// Outputs
wire [7:0] LED;
wire [7:0] SEGMENT;
wire [3:0] AN_SEL;
wire [2:0] Red;
wire [2:0] Green;
wire [1:0] Blue;
wire HSYNC;
wire VSYNC;
wire uart_tx;
// Instantiate the Unit Under Test (UUT)
Top_N3_Computer_IOBUS_VGA_PS2 uut (
.clk_100mhz(clk_100mhz),
.BTN(BTN),
.SW(SW),
.LED(LED),
.SEGMENT(SEGMENT),
.AN_SEL(AN_SEL),
.PS2_clk(PS2_clk),
.PS2_Data(PS2_Data),
.Red(Red),
.Green(Green),
.Blue(Blue),
.HSYNC(HSYNC),
.VSYNC(VSYNC),
.uart_rx(uart_rx),
.uart_tx(uart_tx)
);
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
initial forever begin
clk_100mhz = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk_100mhz = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
initial forever begin
PS2_clk = 1'b0;
#(10*PERIOD-(10*PERIOD*DUTY_CYCLE)) PS2_clk = 1'b1;
#(10*PERIOD*DUTY_CYCLE);
end
initial begin
// Initialize Inputs
//clk_100mhz = 0;
BTN = 0;
SW = 0;
//PS2_clk = 0;
PS2_Data = 0;
uart_rx = 0;
// Wait 100 ns for global reset to finish
#100;
#100 BTN[3] = 1;
#100 BTN[3] = 0;
//#13500;
#650000;
#100 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
#3000 uart_rx = 0;
#400 uart_rx = 1;
// Add stimulus here
// #200 PS2_Data = 1;
// #200 PS2_Data = 1;
// #200 PS2_Data = 0;
// #200 PS2_Data = 1;
// #200 PS2_Data = 0;
// #200 PS2_Data = 0;
// #200 PS2_Data = 1;
// #200 PS2_Data = 0;
// #200 PS2_Data = 1;
// #200 PS2_Data = 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; pair<int, int> p; void sort() { int temp = 0; if (p.first < p.second) { temp = p.first; p.first = p.second; p.second = temp; } } int main() { int n; cin >> n; for (int i = 0; i < n; i++) { int op = 0; cin >> p.first >> p.second; if (p.first == p.second) op = 1; else { if (p.first % p.second == 0) op = p.first / p.second; else { while (p.first % p.second != 0) { sort(); op += p.first / p.second; p.first = p.first % p.second; } } } cout << op << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int T, N, P, ap[109][109]; int main() { scanf( %d , &T); while (T--) { scanf( %d %d , &N, &P), P += 2 * N; for (int df = 1; df < N && P; df++) for (int i = 0; i < N && P; i++) ap[i][(i + df) % N] = 1, P--; for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) if (ap[i][j]) printf( %d %d n , i + 1, j + 1); for (int i = 0; i < N; i++) for (int j = 0; j < N; j++) ap[i][j] = 0; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_M_V
`define SKY130_FD_SC_LP__NAND3_M_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_m (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_m (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_M_V
|
#include <bits/stdc++.h> using namespace std; long long int arr[105]; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int n, x, y, t, l, m, k = 0, r = 0, a, b, c, d, p = 0, q = 0, s, i, j, ans = 0, ans1 = 0; string s1; char ch; cin >> t; while (t--) { cin >> n >> a >> b >> c >> d; q = a + b; p = a - b; s = c + d; r = c - d; x = p * n; y = q * n; if (x > s || y < r) cout << No << n ; else cout << Yes << n ; } return 0; } |
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: STEUERUNG.v
// Version: 1.0
// Date: 30 May 2015
//
// Copyright (C) 2015 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// STEUERUNG The control logic of M32632
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module STEUERUNG( BCLK, BRESET, DC_ACC_DONE, ACB_ZERO, DONE, INT_N, NMI_N, DC_ABORT, IC_INIT, DC_INIT, SAVE_PC, CFG,
IACC_STAT, PROT_ERROR, IC_DIN, PC_NEW, PSR, STRING, TRAPS, IC_READ, DATA_HOLD, LD_DIN, LD_IMME,
WREN, WR_REG, GENSTAT, ILO, COP_OP, IC_USER, ACC_FELD, DISP, IC_TEX, IMME_Q, INFO_AU, LD_OUT,
DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE, WRADR, RWVAL, Y_INIT,
ENA_HK, STOP_CINV );
input BCLK;
input BRESET;
input DC_ACC_DONE;
input ACB_ZERO;
input DONE;
input INT_N;
input NMI_N;
input DC_ABORT;
input IC_INIT;
input DC_INIT;
input SAVE_PC;
input Y_INIT;
input [8:0] CFG;
input [3:0] IACC_STAT;
input PROT_ERROR;
input [31:0] IC_DIN;
input [31:0] PC_NEW;
input [11:0] PSR;
input [4:0] STRING;
input [5:0] TRAPS;
input STOP_CINV;
output IC_READ;
output DATA_HOLD;
output LD_DIN;
output LD_IMME;
output WREN;
output WR_REG;
output [2:0] GENSTAT;
output IC_USER;
output [14:0] ACC_FELD;
output [31:0] DISP;
output [2:0] IC_TEX;
output [31:0] IMME_Q;
output [6:0] INFO_AU;
output [1:0] LD_OUT;
output [12:0] DETOIP;
output [1:0] MMU_UPDATE;
output [10:0] OPER;
output [31:0] PC_ARCHI;
output [31:0] PC_ICACHE;
output [7:0] RDAA;
output [7:0] RDAB;
output [1:0] START;
output [1:0] WMASKE;
output [5:0] WRADR;
output [2:0] RWVAL;
output ENA_HK;
output ILO;
output [23:0] COP_OP;
wire [55:0] OPREG;
wire IC_ABORT;
wire INIT_DONE;
wire UNDEF;
wire ILLEGAL;
wire [2:0] ANZ_VAL;
wire [31:0] PC_SAVE;
wire NEW;
wire RESTART;
wire STOP_IC;
wire [1:0] ALSB;
wire [2:0] USED;
wire NEXT_ADR;
wire NEW_PC;
wire NEXT_PCA;
wire LOAD_PC;
wire [31:0] DISP_BR;
DECODER BEFEHLS_DEC(
.BCLK(BCLK),
.BRESET(BRESET),
.ACC_DONE(DC_ACC_DONE),
.ACB_ZERO(ACB_ZERO),
.DONE(DONE),
.NMI_N(NMI_N),
.INT_N(INT_N),
.DC_ABORT(DC_ABORT),
.IC_ABORT(IC_ABORT),
.INIT_DONE(INIT_DONE),
.UNDEF(UNDEF),
.ILL(ILLEGAL),
.IC_READ(IC_READ),
.ANZ_VAL(ANZ_VAL),
.CFG(CFG),
.OPREG(OPREG),
.PC_SAVE(PC_SAVE),
.PSR(PSR),
.STRING(STRING),
.TRAPS(TRAPS),
.NEW(NEW),
.WREN(WREN),
.LD_DIN(LD_DIN),
.LD_IMME(LD_IMME),
.NEXT_PCA(NEXT_PCA),
.WR_REG(WR_REG),
.LOAD_PC(LOAD_PC),
.GENSTAT(GENSTAT),
.RESTART(RESTART),
.STOP_IC(STOP_IC),
.ACC_FELD(ACC_FELD),
.DISP(DISP),
.DISP_BR(DISP_BR),
.IMME_Q(IMME_Q),
.INFO_AU(INFO_AU),
.LD_OUT(LD_OUT),
.DETOIP(DETOIP),
.MMU_UPDATE(MMU_UPDATE),
.OPER(OPER),
.RDAA(RDAA),
.RDAB(RDAB),
.START(START),
.USED(USED),
.WMASKE(WMASKE),
.WRADR(WRADR),
.RWVAL(RWVAL),
.ENA_HK(ENA_HK),
.ILO(ILO),
.COP_OP(COP_OP),
.STOP_CINV(STOP_CINV) );
ILL_UNDEF CHECKER(
.USER(PSR[8]),
.ANZ_VAL(ANZ_VAL),
.CFG(CFG[3:1]),
.OPREG(OPREG[23:0]),
.ILL(ILLEGAL),
.UNDEF(UNDEF));
OPDEC_REG OPC_REG(
.BCLK(BCLK),
.BRESET(BRESET),
.NEW(NEW),
.DC_INIT(DC_INIT),
.IC_INIT(IC_INIT),
.Y_INIT(Y_INIT),
.RESTART(RESTART),
.STOP_IC(STOP_IC),
.ACC_STAT(IACC_STAT),
.PROT_ERROR(PROT_ERROR),
.ALSB(ALSB),
.IC_DIN(IC_DIN),
.USED(USED),
.IC_READ(IC_READ),
.NEXT_ADR(NEXT_ADR),
.DATA_HOLD(DATA_HOLD),
.NEW_PC(NEW_PC),
.ABORT(IC_ABORT),
.INIT_DONE(INIT_DONE),
.ANZ_VAL(ANZ_VAL),
.IC_TEX(IC_TEX),
.OPREG(OPREG));
PROG_COUNTER PCS(
.BCLK(BCLK),
.BRESET(BRESET),
.NEXT_ADR(NEXT_ADR),
.NEW_PC(NEW_PC),
.NEXT_PCA(NEXT_PCA),
.NEW(NEW),
.LOAD_PC(LOAD_PC),
.USER(PSR[8]),
.SAVE_PC(SAVE_PC),
.FPU_TRAP(TRAPS[0]),
.ADIVAR(INFO_AU[3]),
.DISP(DISP_BR),
.PC_NEW(PC_NEW),
.USED(USED),
.IC_USER(IC_USER),
.ALSB(ALSB),
.PC_ARCHI(PC_ARCHI),
.PC_ICACHE(PC_ICACHE),
.PC_SAVE(PC_SAVE));
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int n, q, m; cin >> n >> q >> m; vector<int> b(n + 1), a(m + 1); for (int i = 1; i <= n; i++) cin >> b[i]; int t[q], l[q], r[q]; for (int i = 0; i < q; i++) cin >> t[i] >> l[i] >> r[i]; for (int i = 1; i <= m; i++) { cin >> a[i]; } for (int i = 1; i <= m; i++) { for (int j = q - 1; j >= 0; j--) { if (l[j] > a[i] || r[j] < a[i]) continue; if (t[j] & 1) { if (a[i] == l[j]) { a[i] = r[j]; } else { --a[i]; } } else { a[i] = r[j] + l[j] - a[i]; } } } for (int i = 1; i <= m; i++) { cout << b[a[i]] << ; } } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int t = 1; while (t--) { solve(); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_BLACKBOX_V
`define SKY130_FD_SC_LP__NAND2_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_BLACKBOX_V
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module hps_sdram_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
output ctl_reset_n;
output ctl_reset_export_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n;
hps_sdram_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 15;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
hps_sdram_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync ({ctl_reset_n, ctl_reset_export_n})
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 15;
defparam ureset_ctl_reset_clk.NUM_RESET_OUTPUT = 2;
hps_sdram_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
defparam ureset_addr_cmd_clk.RESET_SYNC_STAGES = 15;
defparam ureset_addr_cmd_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
defparam ureset_resync_clk.RESET_SYNC_STAGES = 15;
defparam ureset_resync_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
defparam ureset_seq_clk.RESET_SYNC_STAGES = 15;
defparam ureset_seq_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
defparam ureset_scc_clk.RESET_SYNC_STAGES = 15;
defparam ureset_scc_clk.NUM_RESET_OUTPUT = 1;
hps_sdram_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
defparam ureset_avl_clk.RESET_SYNC_STAGES = 2;
defparam ureset_avl_clk.NUM_RESET_OUTPUT = 1;
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
hps_sdram_p0_reset_sync #(
.RESET_SYNC_STAGES(15),
.NUM_RESET_OUTPUT(1)
)
ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& a) { in >> a.first >> a.second; return in; } template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2> a) { out << a.first << << a.second; return out; } template <typename T, typename T1> T amax(T& a, T1 b) { if (b > a) a = b; return a; } template <typename T, typename T1> T amin(T& a, T1 b) { if (b < a) a = b; return a; } const long long INF = 1e18; const int32_t M = 1e9 + 7; const int32_t MM = 998244353; const double inf = 2 * INF; const long long N = 0; vector<long long> tmp, v; long long pw(long long a, long long p) { long long result = 1; while (p > 0) { if (p & 1) result = a * result; a = a * a; p >>= 1; } return result; } long long sq(long long x) { long long ans = sqrt(x); while (ans * ans < x) { ans++; } while (ans * ans > x) { ans--; } return ans; } void precompute() { for (long long i = 3; i < 61; i++) { for (long long j = 2; j < INF; j++) { if (pow(j, i) >= inf) { break; } tmp.push_back(pw(j, i)); } } sort((tmp).begin(), (tmp).end()); (tmp).erase(unique((tmp).begin(), (tmp).end()), (tmp).end()); for (long long x : tmp) { long long t = sq(x); if (t * t == x) { continue; } v.push_back(x); } } void solve() { long long n; cin >> n; long long ans = upper_bound((v).begin(), (v).end(), n) - v.begin(); long long x = sq(n) - 1; ans += x; ans = n - 1 - ans; cout << ans << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); precompute(); long long t = 1; cin >> t; while (t--) solve(); return 0; } |
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_convert_to_ieee_double(clock, resetn, mantissa, exponent, sign, result, valid_in, valid_out, stall_in, stall_out, enable);
input clock, resetn;
input [55:0] mantissa;
input [11:0] exponent;
input sign;
output [63:0] result;
input valid_in, stall_in, enable;
output valid_out, stall_out;
parameter FINITE_MATH_ONLY = 1;
assign valid_out = valid_in;
assign stall_out = stall_in;
generate
if (FINITE_MATH_ONLY == 0)
assign result = {sign, {11{exponent[11]}} | exponent[10:0], mantissa[54:3]};
else
assign result = {sign, exponent[10:0], mantissa[54:3]};
endgenerate
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_a
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_a.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_a.v,v $
// Revision 1.1 2006/11/15 16:04:10 wig
// Added Files: Testcase for verilog include import
// ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
// ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_a
//
// No user `defines in this module
module ent_a
//
// Generated Module inst_a
//
(
p_mix_sig_01_go,
p_mix_sig_03_go,
p_mix_sig_04_gi,
p_mix_sig_05_2_1_go,
p_mix_sig_06_gi,
p_mix_sig_i_ae_gi,
p_mix_sig_o_ae_go,
port_i_a, // Input Port
port_o_a, // Output Port
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_i_a2, // Input Port
sig_o_a2 // Output Port
);
// Generated Module Inputs:
input p_mix_sig_04_gi;
input [3:0] p_mix_sig_06_gi;
input [6:0] p_mix_sig_i_ae_gi;
input port_i_a;
input [5:0] sig_07;
input sig_i_a2;
// Generated Module Outputs:
output p_mix_sig_01_go;
output p_mix_sig_03_go;
output [1:0] p_mix_sig_05_2_1_go;
output [7:0] p_mix_sig_o_ae_go;
output port_o_a;
output [8:2] sig_08;
output [4:0] sig_13;
output sig_o_a2;
// Generated Wires:
wire p_mix_sig_01_go;
wire p_mix_sig_03_go;
wire p_mix_sig_04_gi;
wire [1:0] p_mix_sig_05_2_1_go;
wire [3:0] p_mix_sig_06_gi;
wire [6:0] p_mix_sig_i_ae_gi;
wire [7:0] p_mix_sig_o_ae_go;
wire port_i_a;
wire port_o_a;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire sig_i_a2;
wire sig_o_a2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] sig_02;
wire sig_03; // __W_PORT_SIGNAL_MAP_REQ
wire sig_04; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_05; // __W_PORT_SIGNAL_MAP_REQ
wire [3:0] sig_06; // __W_PORT_SIGNAL_MAP_REQ
wire [6:0] sig_14;
wire [6:0] sig_i_ae; // __W_PORT_SIGNAL_MAP_REQ
wire [7:0] sig_o_ae; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_sig_01_go = sig_01; // __I_O_BIT_PORT
assign p_mix_sig_03_go = sig_03; // __I_O_BIT_PORT
assign sig_04 = p_mix_sig_04_gi; // __I_I_BIT_PORT
assign p_mix_sig_05_2_1_go[1:0] = sig_05[2:1]; // __I_O_SLICE_PORT
assign sig_06 = p_mix_sig_06_gi; // __I_I_BUS_PORT
assign sig_i_ae = p_mix_sig_i_ae_gi; // __I_I_BUS_PORT
assign p_mix_sig_o_ae_go = sig_o_ae; // __I_O_BUS_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_aa_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_aa_2(sig_02[0]), // Use internally test2, no port generated
.port_aa_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_aa_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_aa_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_aa_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.port_ab_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_ab_2(sig_02[1]), // Use internally test2, no port generated
.sig_13(sig_13), // Create internal signal name
.sig_14(sig_14) // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_ac_2(sig_02[3]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_ad_2(sig_02[4]) // Use internally test2, no port generated
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_ae_2[1:0](sig_02[1:0]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_2[4:3](sig_02[4:3]), // Use internally test2, no port generated// __E_CANNOT_COMBINE_SPLICES
.port_ae_5(sig_05), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_ae_6(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_i_ae(sig_i_ae), // Input Bus
.sig_o_ae(sig_o_ae) // Output Bus
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of ent_a
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int pai[1000010]; int find(int x) { if (pai[x] == x) return x; return pai[x] = find(pai[x]); } void join(int a, int b) { pai[find(a)] = find(b); } int main() { int n, m, q; cin >> n >> m >> q; for (int i = 1; i <= n + m; i++) pai[i] = i; for (int i = 0; i < q; i++) { int a, b; cin >> a >> b; b += n; join(a, b); } int comps = 0; for (int i = 1; i <= n + m; i++) comps += pai[i] == i; cout << comps - 1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; set<int> s; const int MAX = 150000; int t[MAX]; int main() { int n, q, k; cin >> n >> k >> q; for (int i = 0; i < n; i++) scanf( %d , t + i); for (int i = 0; i < q; i++) { int query; scanf( %d , &query); int x; scanf( %d , &x); x = t[x - 1]; if (query == 1) { if (s.size() == k) { set<int>::iterator it = s.begin(); if (x > *it) { s.erase(*it); s.insert(x); } } else { s.insert(x); } } else { if (s.count(x)) printf( YES n ); else printf( NO n ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long f[10]; void ge() { f[0] = 1; for (int i = 1; i <= 9; i++) { f[i] = f[i - 1] * 10; } } long long a[100005], b[100005]; int main() { ge(); int n, k; long long ans = 1; int i, j; scanf( %d%d , &n, &k); for (i = 0; i < n / k; i++) { scanf( %I64d , &a[i]); } for (i = 0; i < n / k; i++) { scanf( %I64d , &b[i]); } for (i = 0; i < n / k; i++) { long long n1 = (f[k] - 1) / a[i] + 1; long long n2 = (f[k - 1] - 1) / a[i] + 1; long long n3 = (f[k - 1] * (b[i] + 1) - 1) / a[i] + 1 - (f[k - 1] * b[i] - 1) / a[i] - 1; if (b[i] == 0) ans *= n1 - n2; else ans *= n1 - n3; ans %= 1000000007; } printf( %I64d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { int n, c0, c1, h; cin >> n >> c0 >> c1 >> h; string s; cin >> s; int ans = 0; for (char ch : s) { if (ch == 0 ) { ans += min(c0, c1 + h); } else { ans += min(c1, c0 + h); } } cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int tc = 1; cin >> tc; while (tc--) { solve(); } return 0; } |
#include <bits/stdc++.h> int atob(int t, int a, int b) { int ret = 0, p = 1; while (t) { ret += t % b * p; p *= a; t /= b; } return ret; } int maxbit(int t) { int ret = t % 10; while (t) { if (ret < t % 10) ret = t % 10; t /= 10; } return ret; } int len(int t) { int cnt = 0; while (t) { cnt++; t /= 10; } return cnt; } int main() { int a, b, base, res = 0; scanf( %d%d , &a, &b); base = maxbit(a) + 1; if (base < maxbit(b) + 1) base = maxbit(b) + 1; for (; base <= 10; ++base) { int ta = atob(a, base, 10), tb = atob(b, base, 10), t = atob(ta + tb, 10, base); if (res < len(t)) res = len(t); } printf( %d , res); return 0; } |
#include <bits/stdc++.h> using namespace std; int A[500][500]; int B[500][500]; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) cin >> A[i][j]; int mx = -1e9; for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) B[i][j] = A[i][j] - (i && j ? B[i - 1][j - 1] : 0) + (i ? B[i - 1][j] : 0) + (j ? B[i][j - 1] : 0); for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) { int rx = A[i][j]; for (int k = 1; i + k < n && i - k > -1 && j + k < m && j - k > -1; ++k) { rx += A[i - k + 1][j - k]; rx = B[i + k][j + k] + (i - k && j - k ? B[i - k - 1][j - k - 1] : 0) - (i - k ? B[i - k - 1][j + k] : 0) - (j - k ? B[i + k][j - k - 1] : 0) - rx; mx = max(mx, rx); } } cout << mx; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__HA_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__HA_PP_BLACKBOX_V
/**
* ha: Half adder.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__HA_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int n, k; char s[N]; int chk(char s[]) { for (int i = 1; i <= n; i += k) { for (int j = 1; j <= k; j++) { if (i + j - 1 > n || i + j - 1 + k > n) break; if (s[i + j - 1] != s[i + j - 1 + k]) { if (s[i + j - 1] > s[i + j - 1 + k]) return -1; else return 1; } } } return 0; } int main() { cin >> n >> k; scanf( %s , s + 1); int flag = chk(s); if (flag == 0) { printf( %d n , n); printf( %s n , s + 1); return 0; } else if (flag == -1) { for (int i = 1; i <= n; i += k) { for (int j = 1; j <= k; j++) { if (i + j - 1 > n || i + j - 1 + k > n) break; s[i + j - 1 + k] = s[i + j - 1]; } } printf( %d n , n); printf( %s n , s + 1); return 0; } else { bool ff = 0; if (s[k] == 9 ) s[k] = 0 , ff = 1; else s[k]++; if (ff) { for (int i = k - 1; i >= 1; i--) { if (s[i] == 9 ) { s[i] = 0 ; continue; } s[i]++; break; } } for (int i = 1; i <= n; i += k) { for (int j = 1; j <= k; j++) { if (i + j - 1 > n || i + j - 1 + k > n) break; s[i + j - 1 + k] = s[i + j - 1]; } } printf( %d n , n); printf( %s n , s + 1); return 0; } return 0; } |
// MBT 8-18-2014
//
// BSG Assembler Out (Ring --> Assembler)
//
// prefer ready_o to yumi_o
// prefer yumi_i to ready_i
//
//
// takes a single wide channel and strict round-robin
// distributes it across a number of input channels.
//
// most of the heavy lifting is done by
// bsg_round_robin_fifo_to_fifo. this module
// places a set of fifos between the wide channel
// and the bsg_round_robin_fifo_to_fifo to support
// partial dequeuing from the wide channel.
//
`include "bsg_defines.v"
module bsg_assembler_out #(parameter `BSG_INV_PARAM(width_p )
,parameter `BSG_INV_PARAM(num_in_p )
,parameter `BSG_INV_PARAM(num_out_p )
,parameter out_channel_count_mask_p=(1 << (num_out_p-1)))
(input clk
, input reset
, input calibration_done_i
, input valid_i
, input [num_in_p*width_p-1:0] data_i
, output ready_o // more permissive than yumi_o
, input [`BSG_MAX($clog2(num_in_p)-1,0):0] in_top_channel_i
, input [`BSG_MAX($clog2(num_out_p)-1,0):0] out_top_channel_i
, output [num_out_p-1:0] valid_o
, output [width_p-1:0] data_o [num_out_p-1:0]
, input [num_out_p-1:0] ready_i // we need to peek before deciding what to do.
);
wire [num_in_p-1:0] fifo_valid_vec, fifo_not_full_vec, fifo_deq_vec;
wire [width_p-1:0] fifo_data_vec [num_in_p-1:0];
wire ready_o_tmp = (& fifo_not_full_vec) & calibration_done_i;
// enque if not fifo is full
assign ready_o = ready_o_tmp;
// generate fifos to hold words of input packet
genvar i;
for (i = 0; i < num_in_p; i=i+1)
begin : fifos
bsg_two_fifo #(.width_p(width_p)
,.ready_THEN_valid_p(1)
) ring_packet_fifo
(.clk_i (clk)
,.reset_i(reset)
// input side
,.ready_o(fifo_not_full_vec[i])
,.v_i (valid_i & ready_o_tmp)
,.data_i (data_i[width_p*i+:width_p])
// output side
,.v_o (fifo_valid_vec[i])
,.data_o (fifo_data_vec [i])
,.yumi_i (fifo_deq_vec [i])
);
end
bsg_round_robin_fifo_to_fifo #(.width_p(width_p)
,. num_in_p(num_in_p)
,. num_out_p(num_out_p)
,. out_channel_count_mask_p(out_channel_count_mask_p)
) rr_fifo_to_fifo
(.clk(clk)
,.reset(reset)
,.in_top_channel_i (in_top_channel_i)
,.out_top_channel_i(out_top_channel_i)
,.valid_i(fifo_valid_vec)
,.data_i(fifo_data_vec)
,.yumi_o(fifo_deq_vec)
,.valid_o(valid_o)
,.data_o(data_o)
,.ready_i(ready_i)
);
endmodule // bsg_assembler_out
`BSG_ABSTRACT_MODULE(bsg_assembler_out)
|
// megafunction wizard: %ALTCLKCTRL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altclkctrl
// ============================================================
// File Name: PH2_CLK.v
// Megafunction Name(s):
// altclkctrl
//
// Simulation Library Files(s):
// cycloneii
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altclkctrl CBX_AUTO_BLACKBOX="ALL" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Cyclone II" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" clkselect ena inclk outclk
//VERSION_BEGIN 13.0 cbx_altclkbuf 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = clkctrl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module PH2_CLK_altclkctrl_6df
(
clkselect,
ena,
inclk,
outclk) ;
input [1:0] clkselect;
input ena;
input [3:0] inclk;
output outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] clkselect;
tri1 ena;
tri0 [3:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_clkctrl1_outclk;
wire [1:0] clkselect_wire;
wire [3:0] inclk_wire;
cycloneii_clkctrl clkctrl1
(
.clkselect(clkselect_wire),
.ena(ena),
.inclk(inclk_wire),
.outclk(wire_clkctrl1_outclk)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
clkctrl1.clock_type = "Global Clock",
clkctrl1.ena_register_mode = "falling edge",
clkctrl1.lpm_type = "cycloneii_clkctrl";
assign
clkselect_wire = {clkselect},
inclk_wire = {inclk},
outclk = wire_clkctrl1_outclk;
endmodule //PH2_CLK_altclkctrl_6df
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module PH2_CLK (
inclk,
outclk);
input inclk;
output outclk;
wire sub_wire0;
wire [1:0] sub_wire1 = 2'h0;
wire sub_wire2 = 1'h1;
wire [2:0] sub_wire5 = 3'h0;
wire outclk = sub_wire0;
wire sub_wire3 = inclk;
wire [3:0] sub_wire4 = {sub_wire5, sub_wire3};
PH2_CLK_altclkctrl_6df PH2_CLK_altclkctrl_6df_component (
.clkselect (sub_wire1),
.ena (sub_wire2),
.inclk (sub_wire4),
.outclk (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: clock_inputs NUMERIC "1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION STRING "OFF"
// Retrieval info: CONSTANT: clock_type STRING "Global Clock"
// Retrieval info: USED_PORT: inclk 0 0 0 0 INPUT NODEFVAL "inclk"
// Retrieval info: USED_PORT: outclk 0 0 0 0 OUTPUT NODEFVAL "outclk"
// Retrieval info: CONNECT: @clkselect 0 0 2 0 GND 0 0 2 0
// Retrieval info: CONNECT: @ena 0 0 0 0 VCC 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 3 1 GND 0 0 3 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk 0 0 0 0
// Retrieval info: CONNECT: outclk 0 0 0 0 @outclk 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PH2_CLK_bb.v TRUE
// Retrieval info: LIB_FILE: cycloneii
|
#include <bits/stdc++.h> using namespace std; bool matrix[2005][2005]; int main() { ios::sync_with_stdio(false); int n, m, k; cin >> n >> m >> k; string s; getline(cin, s); for (int y = 0; y < n; y++) { getline(cin, s); for (int x = 0; x < m; x++) matrix[x][y] = s[x] == . ; } int result = 0; for (int x = 0; x < m; x++) { int cnt = 0; for (int y = 0; y < n; y++) { if (matrix[x][y]) cnt++; else { result += max(0, cnt - k + 1); cnt = 0; } } result += max(0, cnt - k + 1); } if (k != 1) { for (int y = 0; y < n; y++) { int cnt = 0; for (int x = 0; x < m; x++) { if (matrix[x][y]) cnt++; else { result += max(0, cnt - k + 1); cnt = 0; } } result += max(0, cnt - k + 1); } } cout << result << endl; } |
module lcd
(
input wire clk,
output reg [4:0] ctl,
output reg [7:0] data
);
localparam RW = 0;
localparam RS = 1;
localparam ON = 2;
localparam EN = 3;
localparam BLON = 4;
localparam INITIAL = 0;
localparam LINE1 = 5;
localparam CHLINE = LINE1 + 16;
localparam LINE2 = CHLINE + 1;
localparam SIZE = LINE2 + 16;
reg [8:0] chr[SIZE];
reg [63:0] cnt;
integer pos, state, i;
initial begin
for (i = 0; i < SIZE; i = i + 1)
chr[i] = 9'h141 - LINE1 + i;
chr[CHLINE] = 9'h0C0;
chr[INITIAL+0] = 9'h038;
chr[INITIAL+1] = 9'h00C;
chr[INITIAL+2] = 9'h001;
chr[INITIAL+3] = 9'h006;
chr[INITIAL+4] = 9'h080;
cnt <= 0;
pos <= 0;
state <= 0;
end
always @* begin
ctl[RW] <= 0;
ctl[ON] <= 1;
ctl[BLON] <= 1;
end
always @ (posedge clk) begin
if (pos < SIZE) begin
case (state)
0: begin
ctl[EN] <= 1;
ctl[RS] <= chr[pos][8];
data <= chr[pos][7:0];
cnt <= 0;
state <= 1;
end
1: begin
if (cnt < 16)
cnt <= cnt + 1;
else begin
ctl[EN] <= 0;
cnt <= 0;
state <= 2;
end
end
2: begin
if (cnt < 'h3FFFE)
cnt <= cnt + 1;
else begin
pos <= pos + 1;
state <= 0;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; sort(a.begin(), a.end()); int ans = a.back() - a[0]; int eachCanRemove = (n - 2) / 2; for (int i = 0; i + eachCanRemove + 1 < n; ++i) { ans = min(ans, a[i + eachCanRemove + 1] - a[i]); } cout << ans << n ; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:45:00 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_ilmb_v10_0/system_ilmb_v10_0_stub.v
// Design : system_ilmb_v10_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "lmb_v10,Vivado 2016.4" *)
module system_ilmb_v10_0(LMB_Clk, SYS_Rst, LMB_Rst, M_ABus, M_ReadStrobe,
M_WriteStrobe, M_AddrStrobe, M_DBus, M_BE, Sl_DBus, Sl_Ready, Sl_Wait, Sl_UE, Sl_CE, LMB_ABus,
LMB_ReadStrobe, LMB_WriteStrobe, LMB_AddrStrobe, LMB_ReadDBus, LMB_WriteDBus, LMB_Ready,
LMB_Wait, LMB_UE, LMB_CE, LMB_BE)
/* synthesis syn_black_box black_box_pad_pin="LMB_Clk,SYS_Rst,LMB_Rst,M_ABus[0:31],M_ReadStrobe,M_WriteStrobe,M_AddrStrobe,M_DBus[0:31],M_BE[0:3],Sl_DBus[0:31],Sl_Ready[0:0],Sl_Wait[0:0],Sl_UE[0:0],Sl_CE[0:0],LMB_ABus[0:31],LMB_ReadStrobe,LMB_WriteStrobe,LMB_AddrStrobe,LMB_ReadDBus[0:31],LMB_WriteDBus[0:31],LMB_Ready,LMB_Wait,LMB_UE,LMB_CE,LMB_BE[0:3]" */;
input LMB_Clk;
input SYS_Rst;
output LMB_Rst;
input [0:31]M_ABus;
input M_ReadStrobe;
input M_WriteStrobe;
input M_AddrStrobe;
input [0:31]M_DBus;
input [0:3]M_BE;
input [0:31]Sl_DBus;
input [0:0]Sl_Ready;
input [0:0]Sl_Wait;
input [0:0]Sl_UE;
input [0:0]Sl_CE;
output [0:31]LMB_ABus;
output LMB_ReadStrobe;
output LMB_WriteStrobe;
output LMB_AddrStrobe;
output [0:31]LMB_ReadDBus;
output [0:31]LMB_WriteDBus;
output LMB_Ready;
output LMB_Wait;
output LMB_UE;
output LMB_CE;
output [0:3]LMB_BE;
endmodule
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