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#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2,fma ) #pragma GCC optimize( unroll-loops ) using namespace std; long long MOD = 998244353; double eps = 1e-12; void solve() { long long n; cin >> n; for (long long i = 0; i <= n; i++) { for (long long j = 0; j <= n; j++) { for (long long k = 0; k <= n; k++) { if ((i * 3 + j * 5 + k * 7) == n) { cout << i << << j << << k << n ; return; } } } } cout << -1 << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; for (int it = 1; it <= t; it++) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long read() { char c = getchar(); long long f = 1, x = 0; while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = (x << 1) + (x << 3) + (c ^ 0 ); c = getchar(); } return x * f; } long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } char s[3]; char b[3]; int main() { scanf( %s , s + 1); long long flag = 0; long long ff = 0, f = 0, fff = 0; long long n = read(); for (int i = 1; i <= n; i++) { memset(b, 0 , sizeof(b)); scanf( %s , b + 1); if (b[1] == s[1] && b[2] == s[2]) { fff = 1; } if (b[1] == s[2] && b[2] == s[1]) { flag = 1; } if (b[2] == s[1]) { f = 1; } if (b[1] == s[2]) { ff = 1; } } if (flag != 0 || ff + f == 2 || fff == 1) { printf( YES n ); } else { printf( NO n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const int N = 5e5 + 3, M = 2e5 + 3; int MOD; string s, t, ts; int n, m, pw[N], hs[N], ht, Z[N + M]; bool check_prime(int x) { for (int i = 2; i * i <= x; ++i) { if (x % i == 0) return false; } return true; } int add(int x, int y) { x += y; while (x >= MOD) x -= MOD; while (x < 0) x += MOD; return x; } int mul(int x, int y) { return (x * 1LL * y) % MOD; } int get_hash(int l, int r) { return add(hs[r], -mul(hs[l - 1], pw[r - l + 1])); } void init() { while (true) { MOD = uniform_int_distribution<int>(1e8, 1e9)(rng); if (check_prime(MOD)) break; } cin >> s >> t; n = s.size(), m = t.size(); ts = + t + s, s = + s, t = + t; pw[0] = 1; for (int i = 1; i <= n; ++i) pw[i] = mul(pw[i - 1], 10); for (int i = 1; i <= n; ++i) hs[i] = add(s[i] - 0 , mul(hs[i - 1], 10)); for (int i = 1; i <= m; ++i) ht = add(t[i] - 0 , mul(ht, 10)); Z[1] = n + m; int l = 1, r = 1; for (int i = 2; i <= n + m; ++i) { if (i > r) { l = r = i; while (r <= n + m && ts[r] == ts[r - l + 1]) ++r; Z[i] = r - l; r--; } else { int k = i - l + 1; if (Z[k] < r - i + 1) Z[i] = Z[k]; else { l = i; while (r <= n + m && ts[r] == ts[r - l + 1]) ++r; Z[i] = r - l; r--; } } } } void solve() { init(); for (int i = 1; i + 2 * (m - 1) - 1 <= n; ++i) { int x = get_hash(i, i + m - 2); int x2 = get_hash(i + m - 1, i + 2 * m - 3); x = add(x, x2); if (x == ht) { cout << i << << i + m - 2 << n << i + m - 1 << << i + 2 * m - 3; return; } } for (int i = 1; i + m - 1 <= n; ++i) { int x = get_hash(i, i + m - 1); if (m - Z[i + m] > 0) { if (i - m + Z[i + m] > 0) { int x2 = get_hash(i - m + Z[i + m], i - 1); x = add(x, x2); if (x == ht) { cout << i - m + Z[i + m] << << i - 1 << n << i << << i + m - 1; return; } x = add(x, -x2); } if (i + 2 * m - Z[i + m] - 1 <= n) { int x2 = get_hash(i + m, i + 2 * m - Z[i + m] - 1); x = add(x, x2); if (x == ht) { cout << i << << i + m - 1 << n << i + m << << i + 2 * m - Z[i + m] - 1; return; } x = add(x, -x2); } } if (m - Z[i + m] - 1 > 0) { if (i - m + Z[i + m] + 1 > 0) { int x2 = get_hash(i - m + Z[i + m] + 1, i - 1); x = add(x, x2); if (x == ht) { cout << i - m + Z[i + m] + 1 << << i - 1 << n << i << << i + m - 1; return; } x = add(x, -x2); } if (i + 2 * m - Z[i + m] - 2 <= n) { int x2 = get_hash(i + m, i + 2 * m - Z[i + m] - 2); x = add(x, x2); if (x == ht) { cout << i << << i + m - 1 << n << i + m << << i + 2 * m - Z[i + m] - 2; return; } x = add(x, -x2); } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int test; scanf( %d , &test); while (test--) { int fuck; string str; scanf( %d , &fuck); cin >> str; string ans = ; for (auto &x : str) { if ((x - 0 ) % 2 == 1) { ans += x; if (ans.size() == 2) { break; } } } if (ans.size() == 2) { puts(ans.c_str()); continue; } puts( -1 ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); int n, m; cin >> n >> m; int ver[n + 1]; ver[n] = 1e9; for (int i = 0; i < n; i++) cin >> ver[i]; int hor[m]; for (int i = 0; i < m; i++) { int x1, x2, y; cin >> x1 >> x2 >> y; if (x1 > 1) hor[i] = 0; else hor[i] = x2; } if (m == 0) { cout << 0 << endl; return 0; } sort(ver, ver + n); sort(hor, hor + m); int wy = 10000000; int poz = m; int a = 0; for (int i = 0; i < n + 1; i++) { while (a < m and hor[a] < ver[i]) { poz--; a++; } wy = min(wy, poz + i); } cout << wy << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; bool f[1005]; vector<int> x[1005]; vector<int> y[1005]; int dx[4] = {1, 1, -1, -1}; int dy[4] = {1, -1, 1, -1}; int main() { for (int i = 1; i <= 1000; i++) { for (int j = 1; j <= 1000; j++) { int p = i * i + j * j; int u = (int)(sqrt(p)); if (u * u == p && u <= 1000) { f[u] = 1; x[u].push_back(i); y[u].push_back(j); } } } int a, b; scanf( %d%d , &a, &b); if (f[a] && f[b]) { for (int r = 0; r < x[a].size(); r++) for (int s = 0; s < x[b].size(); s++) { int u = x[a][r], v = y[a][r]; for (int i = 0; i < 4; i++) { int p = u * dx[i]; int q = v * dy[i]; if (x[b][s] * p + y[b][s] * q == 0 && (x[b][s] != p && y[b][s] != q)) { printf( YES n ); printf( 0 0 n ); printf( %d %d n , x[b][s], y[b][s]); printf( %d %d n , p, q); return 0; } } swap(u, v); for (int i = 0; i < 4; i++) { int p = u * dx[i]; int q = v * dy[i]; if (x[b][s] * p + y[b][s] * q == 0 && (x[b][s] != p && y[b][s] != q)) { printf( YES n ); printf( 0 0 n ); printf( %d %d n , x[b][s], y[b][s]); printf( %d %d n , p, q); return 0; } } } printf( NO n ); } else printf( NO n ); return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9739a_core (
// dac interface
dac_div_clk,
dac_rst,
dac_data_00,
dac_data_01,
dac_data_02,
dac_data_03,
dac_data_04,
dac_data_05,
dac_data_06,
dac_data_07,
dac_data_08,
dac_data_09,
dac_data_10,
dac_data_11,
dac_data_12,
dac_data_13,
dac_data_14,
dac_data_15,
dac_status,
// dma interface
dac_valid,
dac_enable,
dac_ddata,
dac_dovf,
dac_dunf,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter PCORE_ID = 0;
parameter DP_DISABLE = 0;
// dac interface
input dac_div_clk;
output dac_rst;
output [ 15:0] dac_data_00;
output [ 15:0] dac_data_01;
output [ 15:0] dac_data_02;
output [ 15:0] dac_data_03;
output [ 15:0] dac_data_04;
output [ 15:0] dac_data_05;
output [ 15:0] dac_data_06;
output [ 15:0] dac_data_07;
output [ 15:0] dac_data_08;
output [ 15:0] dac_data_09;
output [ 15:0] dac_data_10;
output [ 15:0] dac_data_11;
output [ 15:0] dac_data_12;
output [ 15:0] dac_data_13;
output [ 15:0] dac_data_14;
output [ 15:0] dac_data_15;
input dac_status;
// dma interface
output dac_valid;
output dac_enable;
input [255:0] dac_ddata;
input dac_dovf;
input dac_dunf;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [ 13:0] up_waddr;
input [ 31:0] up_wdata;
output up_wack;
input up_rreq;
input [ 13:0] up_raddr;
output [ 31:0] up_rdata;
output up_rack;
// internal registers
reg [ 31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal signals
wire dac_sync_s;
wire dac_datafmt_s;
wire [ 31:0] up_rdata_0_s;
wire up_rack_0_s;
wire up_wack_0_s;
wire [ 31:0] up_rdata_s;
wire up_rack_s;
wire up_wack_s;
// defaults
assign dac_valid = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s | up_rdata_0_s;
up_rack <= up_rack_s | up_rack_0_s;
up_wack <= up_wack_s | up_wack_0_s;
end
end
// dac channel
axi_ad9739a_channel #(
.CHID(0),
.DP_DISABLE(DP_DISABLE))
i_channel_0 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable),
.dac_data_00 (dac_data_00),
.dac_data_01 (dac_data_01),
.dac_data_02 (dac_data_02),
.dac_data_03 (dac_data_03),
.dac_data_04 (dac_data_04),
.dac_data_05 (dac_data_05),
.dac_data_06 (dac_data_06),
.dac_data_07 (dac_data_07),
.dac_data_08 (dac_data_08),
.dac_data_09 (dac_data_09),
.dac_data_10 (dac_data_10),
.dac_data_11 (dac_data_11),
.dac_data_12 (dac_data_12),
.dac_data_13 (dac_data_13),
.dac_data_14 (dac_data_14),
.dac_data_15 (dac_data_15),
.dma_data (dac_ddata),
.dac_data_sync (dac_sync_s),
.dac_dds_format (dac_datafmt_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_0_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_0_s),
.up_rack (up_rack_0_s));
// dac common processor interface
up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common (
.mmcm_rst (),
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_sync (dac_sync_s),
.dac_frame (),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.dac_datafmt (dac_datafmt_s),
.dac_datarate (),
.dac_status (dac_status),
.dac_status_ovf (dac_dovf),
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd4),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd1),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd1),
.up_dac_gpio_in (32'd0),
.up_dac_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/26/2016 07:28:40 AM
// Design Name:
// Module Name: LZD
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//dc_script_begin
// set LIB_NAME scx3_cmos8rf_lpvt_tt_1p2v_25c.db
// set CLK_PERIOD 10
// set CLK_NAME clk
// set INPUT_DELAY_MAX 3
// #set the fastest input data arrival time to check for hold time changes to 1000pS
// set INPUT_DELAY_MIN 2
// # set the setup time requirements for the next block to 2nS
// set OUTPUT_DELAY_MAX 3
// # set the hold time requirements for the next block to 150pS
// set OUTPUT_DELAY_MIN 1
// set CLK_TRANSITION 1
// set_input_delay -max $INPUT_DELAY_MAX -clock $CLK_NAME $ALL_IN_EX_CLK_NAME
// set_input_delay -min $INPUT_DELAY_MIN -clock $CLK_NAME $ALL_IN_EX_CLK_NAME
// #Configuración del retardo en las señales de salida -> page 5-26, 7-18
// set_output_delay -max $OUTPUT_DELAY_MAX -clock $CLK_NAME $ALL_OUT_NAME
// set_output_delay -min $OUTPUT_DELAY_MIN -clock $CLK_NAME $ALL_OUT_NAME
//set_clock_transition $CLK_TRANSITION [get_clocks $CLK_NAME]
//dc_script_end
module LZD#(parameter SWR=26, parameter EWR=5)(
//#(parameter SWR=55, parameter EWR=6)(
input wire clk,
input wire rst,
input wire load_i,
input wire [SWR-1:0] Add_subt_result_i,
/////////////////////////////////////////////7
output wire [EWR-1:0] Shift_Value_o
);
wire [EWR-1:0] Codec_to_Reg;
generate
case (SWR)
26:begin : LZD_SINGLEBLK
Priority_Codec_32 Codec_32(
.Data_Dec_i(Add_subt_result_i),
.Data_Bin_o(Codec_to_Reg)
);
end
55:begin : LZD_DOUBLEBLK
Priority_Codec_64 Codec_64(
.Data_Dec_i(Add_subt_result_i),
.Data_Bin_o(Codec_to_Reg)
);
end
endcase
endgenerate
RegisterAdd #(.W(EWR)) Output_Reg(
.clk(clk),
.rst(rst),
.load(load_i),
.D(Codec_to_Reg),
.Q(Shift_Value_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = (int)1e5 + 113; const double eps = 1e-7; struct pt { long double x, y; int ind; pt(long double x = 0, long double y = 0, int ind = 0) : x(x), y(y), ind(ind) {} }; long double dist(pt a, pt b) { return (a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y); } int n; pt a, b, t, rat[N]; pt mnA[2], mnB[2]; int used[N]; long double ans = 1000000000000, newAns; bool cnt1(pt x, pt y) { long double toX = sqrt(dist(a, x)) + sqrt(dist(t, y)); long double toY = sqrt(dist(a, y)) + sqrt(dist(t, x)); return (toX - toY < eps); } bool cnt2(pt x, pt y) { long double toX = sqrt(dist(b, x)) + sqrt(dist(t, y)); long double toY = sqrt(dist(b, y)) + sqrt(dist(t, x)); return (toX - toY < eps); } int main() { cout.precision(30); cin >> a.x >> a.y >> b.x >> b.y >> t.x >> t.y; cin >> n; for (int i = 1; i <= n; i++) { cin >> rat[i].x >> rat[i].y; rat[i].ind = i; } sort(rat + 1, rat + n + 1, cnt1); mnA[0] = rat[1]; mnA[1] = rat[2]; sort(rat + 1, rat + n + 1, cnt2); mnB[0] = rat[1]; mnB[1] = rat[2]; if (n == 1) { ans = min(sqrt(dist(a, rat[1])), sqrt(dist(b, rat[1]))) + sqrt(dist(rat[1], t)); cout << ans; return 0; } ans = sqrt(dist(a, mnA[0])) + sqrt(dist(mnA[0], t)); used[mnA[0].ind] = 1; for (int i = 1; i <= n; i++) { if (used[rat[i].ind]) continue; ans += 2 * sqrt(dist(t, rat[i])); } memset(used, 0, sizeof(used)); newAns = sqrt(dist(b, mnB[0])) + sqrt(dist(mnB[0], t)); used[mnB[0].ind] = 1; for (int i = 1; i <= n; i++) { if (used[rat[i].ind]) continue; newAns += 2 * sqrt(dist(t, rat[i])); } ans = min(ans, newAns); memset(used, 0, sizeof(used)); newAns = sqrt(dist(a, mnA[0])) + sqrt(dist(mnA[0], t)); used[mnA[0].ind] = 1; if (used[mnB[0].ind]) { newAns += sqrt(dist(b, mnB[1])) + sqrt(dist(mnB[1], t)); used[mnB[1].ind] = 1; } else { newAns += sqrt(dist(b, mnB[0])) + sqrt(dist(mnB[0], t)); used[mnB[0].ind] = 1; } for (int i = 1; i <= n; i++) { if (used[rat[i].ind]) continue; newAns += 2 * sqrt(dist(t, rat[i])); } ans = min(ans, newAns); memset(used, 0, sizeof(used)); newAns = sqrt(dist(b, mnB[0])) + sqrt(dist(mnB[0], t)); used[mnB[0].ind] = 1; if (used[mnA[0].ind]) { newAns += sqrt(dist(a, mnA[1])) + sqrt(dist(mnA[1], t)); used[mnA[1].ind] = 1; } else { newAns += sqrt(dist(a, mnA[0])) + sqrt(dist(mnA[0], t)); used[mnA[0].ind] = 1; } for (int i = 1; i <= n; i++) { if (used[rat[i].ind]) continue; newAns += 2 * sqrt(dist(t, rat[i])); } ans = min(ans, newAns); cout << ans; } |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
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// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Address Write Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// aw_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_aw_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
output reg cmd_w_valid,
output wire cmd_w_check,
output wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
input wire cmd_w_ready,
input wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
input wire cmd_b_ready,
// Slave Interface Write Address Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for burst types.
localparam [2-1:0] C_FIX_BURST = 2'b00;
localparam [2-1:0] C_INCR_BURST = 2'b01;
localparam [2-1:0] C_WRAP_BURST = 2'b10;
// Constants for size.
localparam [3-1:0] C_OPTIMIZED_SIZE = 3'b011;
// Constants for length.
localparam [4-1:0] C_OPTIMIZED_LEN = 4'b0011;
// Constants for cacheline address.
localparam [4-1:0] C_NO_ADDR_OFFSET = 5'b0;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Transaction properties.
wire access_is_incr;
wire access_is_wrap;
wire access_is_coherent;
wire access_optimized_size;
wire incr_addr_boundary;
wire incr_is_optimized;
wire wrap_is_optimized;
wire access_is_optimized;
// Command FIFO.
wire cmd_w_push;
reg cmd_full;
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
wire [C_FIFO_DEPTH_LOG-1:0] all_addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
/////////////////////////////////////////////////////////////////////////////
// Transaction Decode:
//
// Detect if transaction is of correct typ, size and length to qualify as
// an optimized transaction that has to be checked for errors.
//
/////////////////////////////////////////////////////////////////////////////
// Transaction burst type.
assign access_is_incr = ( S_AXI_AWBURST == C_INCR_BURST );
assign access_is_wrap = ( S_AXI_AWBURST == C_WRAP_BURST );
// Transaction has to be Coherent.
assign access_is_coherent = ( S_AXI_AWUSER[0] == 1'b1 ) &
( S_AXI_AWCACHE[1] == 1'b1 );
// Transaction cacheline boundary address.
assign incr_addr_boundary = ( S_AXI_AWADDR[4:0] == C_NO_ADDR_OFFSET );
// Transaction length & size.
assign access_optimized_size = ( S_AXI_AWSIZE == C_OPTIMIZED_SIZE ) &
( S_AXI_AWLEN == C_OPTIMIZED_LEN );
// Transaction is optimized.
assign incr_is_optimized = access_is_incr & access_is_coherent & access_optimized_size & incr_addr_boundary;
assign wrap_is_optimized = access_is_wrap & access_is_coherent & access_optimized_size;
assign access_is_optimized = ( incr_is_optimized | wrap_is_optimized );
/////////////////////////////////////////////////////////////////////////////
// Command FIFO:
//
// Since supported write interleaving is only 1, it is safe to use only a
// simple SRL based FIFO as a command queue.
//
/////////////////////////////////////////////////////////////////////////////
// Determine when transaction infromation is pushed to the FIFO.
assign cmd_w_push = S_AXI_AWVALID & M_AXI_AWREADY & ~cmd_full;
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_w_push & ~cmd_w_ready ) begin
addr_ptr <= addr_ptr + 1;
end else if ( ~cmd_w_push & cmd_w_ready ) begin
addr_ptr <= addr_ptr - 1;
end
end
end
// Total number of buffered commands.
assign all_addr_ptr = addr_ptr + cmd_b_addr + 2;
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_full <= 1'b0;
cmd_w_valid <= 1'b0;
end else begin
if ( cmd_w_push & ~cmd_w_ready ) begin
cmd_w_valid <= 1'b1;
end else if ( ~cmd_w_push & cmd_w_ready ) begin
cmd_w_valid <= ( addr_ptr != 0 );
end
if ( cmd_w_push & ~cmd_b_ready ) begin
// Going to full.
cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-3 );
end else if ( ~cmd_w_push & cmd_b_ready ) begin
// Pop in middle of queue doesn't affect full status.
cmd_full <= ( all_addr_ptr == C_FIFO_DEPTH-2 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_w_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {access_is_optimized, S_AXI_AWID};
end
end
// Get current transaction info.
assign {cmd_w_check, cmd_w_id} = data_srl[addr_ptr];
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_AWVALID = S_AXI_AWVALID & ~cmd_full;
// Return ready with push back.
assign S_AXI_AWREADY = M_AXI_AWREADY & ~cmd_full;
/////////////////////////////////////////////////////////////////////////////
// Address Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWUSER = S_AXI_AWUSER;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, s, idx; cin >> n >> s; s--; int a[n], b[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { cin >> b[i]; } if (a[0] == 1) { for (int i = 0; i < n; i++) { if (i == s && a[i] == 1) { cout << YES ; return 0; } else if (i > s && a[i] == 1 && b[i] == 1) { for (int j = i; j >= 0; j--) { if (j == s && b[j] == 1) { cout << YES ; return 0; } } } } } cout << NO ; } |
module ISERDESE2 (/*AUTOARG*/
// Outputs
O, Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, SHIFTOUT1, SHIFTOUT2,
// Inputs
BITSLIP, CE1, CE2, CLK, CLKB, CLKDIV, CLKDIVP, D, DDLY,
DYNCLKDIVSEL, DYNCLKSEL, OCLK, OCLKB, OFB, RST, SHIFTIN1, SHIFTIN2
);
parameter DATA_RATE = 0; // "DDR" or "SDR"
parameter DATA_WIDTH = 0; // 4,2,3,5,6,7,8,10,14
parameter DYN_CLK_INV_EN = 0; // "FALSE", "TRUE"
parameter DYN_CLKDIV_INV_EN = 0; // "FALSE", "TRUE"
parameter INIT_Q1 = 0; // 1'b0 to 1'b1
parameter INIT_Q2 = 0; // 1'b0 to 1'b1
parameter INIT_Q3 = 0; // 1'b0 to 1'b1
parameter INIT_Q4 = 0; // 1'b0 to 1'b1
parameter INTERFACE_TYPE = 0; // "MEMORY","MEMORY_DDR3", "MEMORY_QDR",
// "NETWORKING", "OVERSAMPLE"
parameter IOBDELAY = 0; // "NONE", "BOTH", "IBUF", "IFD"
parameter NUM_CE = 0; // 2,1
parameter OFB_USED = 0; // "FALSE", "TRUE"
parameter SERDES_MODE = 0; // "MASTER" or "SLAVE"
parameter SRVAL_Q1 = 0; // 1'b0 or 1'b1
parameter SRVAL_Q2 = 0; // 1'b0 or 1'b1
parameter SRVAL_Q3 = 0; // 1'b0 or 1'b1
parameter SRVAL_Q4 = 0; // 1'b0 or 1'b1
input BITSLIP; // performs bitslip operation
input CE1; // clock enable
input CE2; // clock enable
input CLK; // high speed clock input
input CLKB; // high speed clock input (inverted)
input CLKDIV; // divided clock (for bitslip and CE module
input CLKDIVP; // for MIG only
input D; // serial input data pin
input DDLY; // serial input data from IDELAYE2
input DYNCLKDIVSEL; // dynamically select CLKDIV inversion
input DYNCLKSEL; // dynamically select CLK and CLKB inversion.
input OCLK; // clock for strobe based memory interfaces
input OCLKB; // clock for strobe based memory interfaces
input OFB; // data feebdack from OSERDESE2?
input RST; // asynchronous reset
input SHIFTIN1; // slave of multie serdes
input SHIFTIN2; // slave of multie serdes
//outputs
output O; // pass through from D or DDLY
output Q1; // parallel data out (last bit)
output Q2;
output Q3;
output Q4;
output Q5;
output Q6;
output Q7;
output Q8; // first bit of D appears here
output SHIFTOUT1; // master of multi serdes
output SHIFTOUT2; // master of multi serdes
reg [3:0] even_samples;
reg [3:0] odd_samples;
always @ (posedge CLK)
even_samples[3:0] <= {even_samples[2:0],D};
always @ (negedge CLK)
odd_samples[3:0] <= {odd_samples[2:0],D};
assign Q1 = odd_samples[0];
assign Q2 = even_samples[0];
assign Q3 = odd_samples[1];
assign Q4 = even_samples[1];
assign Q5 = odd_samples[2];
assign Q6 = even_samples[2];
assign Q7 = odd_samples[3];
assign Q8 = even_samples[3];
//pass through
assign O=D;
//not implemented
assign SHIFTOUT1=1'b0;
assign SHIFTOUT2=1'b0;
endmodule // ISERDESE2
|
#include <bits/stdc++.h> using namespace std; const long long N_MAX = 1123; const long long MOD = 998244353; long long w; long long h; long long result = 1; int main() { ios_base::sync_with_stdio(0); cin >> w; cin >> h; for (long long i = 1; i <= w; i++) { for (long long j = 1; j <= h; j++) { if (i == 1 && j == 1) { result *= 4; } else if (i == 1) { result *= 2; } else if (j == 1) { result *= 2; } result %= MOD; } } cout << result << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long read() { long long s = 0, w = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) w = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) s = s * 10 + ch - 0 , ch = getchar(); return s * w; } const long long p = 998244353; long long qp(long long x, long long y) { long long res = 1; for (long long t = x; y; y >>= 1, t = t * t % p) if (y & 1) res = res * t % p; return res; } struct node { long long u, v, w; } a[1000003]; vector<node> v[1000003]; long long f[1000003], g[1000003]; long long c[1000003]; signed main() { long long n = read(), m = read(), k = read() + 1; for (long long i = 1; i <= m; ++i) { long long X = read(); a[i].u = read(); a[i].v = read(); a[i].w = read(); v[X].push_back(a[i]); } long long ans = 1e18; memset(f, -1, sizeof(f)), memset(g, -1, sizeof(g)); memset(c, -1, sizeof(c)); long long S = 0, C = 0; for (long long i = 1; i <= 1000000; ++i) { for (node j : v[i]) if (j.v == 0) { if (c[j.u] == -1) { S += j.w, ++C, c[j.u] = j.w; } else if (c[j.u] > j.w) { S -= c[j.u] - j.w, c[j.u] = j.w; } } if (C == n) f[i] = S; } S = 0, C = 0; memset(c, -1, sizeof(c)); for (long long i = 1000000; i >= 1; --i) { for (node j : v[i]) if (j.u == 0) { if (c[j.v] == -1) { S += j.w, ++C, c[j.v] = j.w; } else if (c[j.v] > j.w) { S -= c[j.v] - j.w, c[j.v] = j.w; } } if (C == n) g[i] = S; } for (long long i = 1; i + k <= 1000000; ++i) if (f[i] > -1 && g[i + k] > -1) { ans = min(ans, f[i] + g[i + k]); } if (ans > 1e17) puts( -1 ); else printf( %lld n , ans); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [255:0] a;
reg [60:0] divisor;
reg [60:0] qq;
reg [60:0] rq;
reg signed [60:0] qqs;
reg signed [60:0] rqs;
always @* begin
qq = a[60:0] / divisor;
rq = a[60:0] % divisor;
qqs = $signed(a[60:0]) / $signed(divisor);
rqs = $signed(a[60:0]) % $signed(divisor);
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs);
if (cyc==1) begin
a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
divisor <= 61'h12371;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
end
if (cyc==2) begin
a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
divisor <= 61'h1238123771;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
if (qq!==61'h00000403ad81c0da) $stop;
if (rq!==61'h00000000000090ec) $stop;
if (qqs!==61'h00000403ad81c0da) $stop;
if (rqs!==61'h00000000000090ec) $stop;
end
if (cyc==3) begin
a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8;
divisor <= 61'hf1b;
a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed
if (qq!==61'h000000000090832e) $stop;
if (rq!==61'h0000000334becc6a) $stop;
if (qqs!==61'h000000000090832e) $stop;
if (rqs!==61'h0000000334becc6a) $stop;
end
if (cyc==4) begin
a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0001eda37cca1be8) $stop;
if (rq!==61'h0000000000000c40) $stop;
if (qqs!==61'h1fffcf5187c76510) $stop;
if (rqs!==61'h1ffffffffffffd08) $stop;
end
if (cyc==5) begin
a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0000000000000000) $stop;
if (rq!==61'h0d20a48e00f395b8) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h0d20a48e00f395b8) $stop;
end
if (cyc==6) begin
if (qq!==61'h0000000000000001) $stop;
if (rq!==61'h0d20a48e00f3869d) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h1d20a48e00f395b8) $stop;
end
// Div by zero
if (cyc==9) begin
divisor <= 61'd0;
end
if (cyc==10) begin
`ifdef verilator
if (qq !== {61{1'b0}}) $stop;
if (rq !== {61{1'b0}}) $stop;
`else
if (qq !== {61{1'bx}}) $stop;
if (rq !== {61{1'bx}}) $stop;
`endif
if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors
if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors
end
if (cyc==19) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, A, B; long long toi(string s) { istringstream is(s); long long x; is >> x; return x; } string tos(long long t) { stringstream st; st << t; return st.str(); } long long F[1000005], FP[1000005]; bool f(long long x) { while (x > 0) { if (x % 10 != A && x % 10 != B) return 0; x /= 10; } return 1; } long long pow(long long a, long long b, long long c) { long long x = 1, y = a; while (b > 0) { if (b & 1) x = (x * y) % c; y = (y * y) % c; b >>= 1; } return x; } int main() { F[0] = 1; for (int i = 1; i < 1000005; ++i) { F[i] = i * F[i - 1]; if (F[i] >= 1000000007) F[i] %= 1000000007; } FP[1000005 - 1] = pow(F[1000005 - 1], 1000000007 - 2, 1000000007); for (int i = 1000005 - 2; i >= 0; --i) { FP[i] = FP[i + 1] * (i + 1); if (FP[i] >= 1000000007) FP[i] %= 1000000007; } while (cin >> A >> B >> n) { long long cnt = 0; for (int i = 0; i <= n; ++i) if (f(i * A + (n - i) * B)) { long long num = F[n], den = FP[i] * FP[n - i]; if (den >= 1000000007) den %= 1000000007; num *= den; if (num >= 1000000007) num %= 1000000007; cnt += num; if (cnt >= 1000000007) cnt -= 1000000007; } cout << cnt << endl; } } |
#include <bits/stdc++.h> using namespace std; int n; bool isValid(int x1, int y1, int x2, int y2) { return x1 <= x2 && y1 <= y2; } int ask(int x1, int y1, int x2, int y2) { int ret = 0; cout << ? << x1 << << y1 << << x2 << << y2 << n ; cout.flush(); cin >> ret; return ret; } bool check(int x1, int y1, int x2, int y2, int x3, int y3, int x4, int y4) { if (!isValid(x1, y1, x2, y2)) return 0; if (!isValid(x3, y3, x4, y4)) return 0; int ret1 = ask(x1, y1, x2, y2); int ret2 = ask(x3, y3, x4, y4); return (ret1 > 0 && ret2 > 0); } int main() { ios::sync_with_stdio(0); cin >> n; int x1, y1, x2, y2, x3, y3, x4, y4; int l, r; l = 1; r = n; while (l <= r) { int s = (l + r) / 2; if (ask(s, 1, n, n) == 2) { l = s + 1; x1 = s; } else { r = s - 1; } } l = 1; r = n; while (l <= r) { int s = (l + r) / 2; if (ask(s, 1, n, n) >= 1) { l = s + 1; x3 = s; } else { r = s - 1; } } l = 1; r = n; while (l <= r) { int s = (l + r) / 2; if (ask(1, 1, s, n) == 2) { r = s - 1; x2 = s; } else { l = s + 1; } } l = 1; r = n; while (l <= r) { int s = (l + r) / 2; if (ask(1, 1, s, n) >= 1) { r = s - 1; x4 = s; } else { l = s + 1; } } l = 1; r = n; while (l <= r) { int s = (l + r) / 2; if (ask(1, s, n, n) == 2) { l = s + 1; y1 = s; } else { r = s - 1; } } l = 1; r = n; while (l <= r) { int s = (l + r) / 2; if (ask(1, s, n, n) >= 1) { l = s + 1; y3 = s; } else { r = s - 1; } } l = 1; r = n; while (l <= r) { int s = (l + r) / 2; if (ask(1, 1, n, s) == 2) { r = s - 1; y2 = s; } else { l = s + 1; } } l = 1; r = n; while (l <= r) { int s = (l + r) / 2; if (ask(1, 1, n, s) >= 1) { r = s - 1; y4 = s; } else { l = s + 1; } } vector<int> xx1{x1, x3}; vector<int> xx2{x2, x4}; vector<int> yy1{y1, y3}; vector<int> yy2{y2, y4}; int xxx3 = xx1[1]; for (int xxx1 : xx1) { int xxx4 = xx2[1]; for (int xxx2 : xx2) { int yyy3 = yy1[1]; for (int yyy1 : yy1) { int yyy4 = yy2[1]; for (int yyy2 : yy2) { if (check(xxx1, yyy1, xxx2, yyy2, xxx3, yyy3, xxx4, yyy4)) { cout << ! << xxx1 << << yyy1 << << xxx2 << << yyy2 << << xxx3 << << yyy3 << << xxx4 << << yyy4; return 0; } yyy4 = yyy2; } yyy3 = yyy1; } xxx4 = xxx2; } xxx3 = xxx1; } return 0; } |
#include <bits/stdc++.h> using namespace std; int add(int _a, int _b) { _a = (_a + 1000000007) % 1000000007; _b = (_b + 1000000007) % 1000000007; return (_a + _b) % 1000000007; } int mul(int _a, int _b) { _a = (_a + 1000000007) % 1000000007; _b = (_b + 1000000007) % 1000000007; return ((long long int)((long long int)_a * (long long int)_b)) % 1000000007; } int n, k, sbtr[100010], sum[210], dif[100010][210], sol = 0, fac[100010], inv[100010], h[100010][210], f[210][210]; vector<int> adj[100010]; void input() { int i, j; scanf( %d %d , &n, &k); for (i = 0; i < n - 1; i++) { int u, v; scanf( %d %d , &u, &v), u--, v--; adj[u].push_back(v), adj[v].push_back(u); } } int bigMod(int v, int p) { if (p == 0) { return 1; } int ret = bigMod(v, p / 2); if (p % 2 == 0) { return mul(ret, ret); } else { return mul(ret, mul(ret, v)); } } void factorial() { int i, j; for (i = 1, fac[0] = inv[0] = 1; i < 100010 - 1; i++) { fac[i] = mul(fac[i - 1], i); inv[i] = mul(inv[i - 1], bigMod(i, 1000000007 - 2)); } } void H(int src) { int sz = adj[src].size(), i, j, l, u, x; for (i = sz - 1; i >= 0; i--) { for (u = adj[src][i], j = 0; j <= min(k, sbtr[src] - 1); j++) { if (i == sz - 1) { if (j == 0) { h[i][j] = add(1, dif[u][j]); } else { h[i][j] = add(dif[u][j], mul(j, dif[u][j - 1])); } continue; } for (l = 0, h[i][j] = 0; l <= min(sbtr[u], j); l++) { x = mul(fac[j], mul(inv[l], inv[j - l])); if (l == 0) { x = mul(x, add(1, dif[u][0])); } else { x = mul(x, add(dif[u][l], mul(l, dif[u][l - 1]))); } x = mul(x, h[i + 1][j - l]); h[i][j] = add(h[i][j], x); } } } } int F(int u, int v) { int ret = 0; if (v > u) { return 0; } if (v == 0) { return 0; } if (u == 1) { return 1; } if (f[u][v] != -1) { return f[u][v]; } ret = add(mul(v, F(u - 1, v)), F(u - 1, v - 1)); return f[u][v] = ret; } bool cmp(int lhs, int rhs) { return sbtr[lhs] < sbtr[rhs]; } void dfs(int src, int par) { int i, j, idx = -1, mns, ret, u, x; sbtr[src] = 1, ret = 0; for (i = 0; i < adj[src].size(); i++) { u = adj[src][i]; if (u == par) { idx = i; break; } } if (idx != -1) { adj[src].erase(adj[src].begin() + idx); } for (i = 0, dif[src][0] = 2, mns = 0; i < adj[src].size(); i++) { u = adj[src][i]; dfs(u, src); sbtr[src] += sbtr[u]; dif[src][0] = mul(dif[src][0], add(1, dif[u][0])); } sort(adj[src].begin(), adj[src].end(), cmp); dif[src][0] = add(dif[src][0], -1); for (j = 0; j <= k; j++) { for (i = 0, sum[j] = 0; i < adj[src].size(); i++) { int u = adj[src][i]; sum[j] = add(sum[j], dif[u][j]); } } H(src); for (i = 1; i <= min(k, sbtr[src] - 1); i++) { u = adj[src][0]; x = mul(2, h[0][i]); dif[src][i] = x; x = add(x, -sum[i]); x = add(x, -(mul(i, sum[i - 1]))); x = mul(x, F(k, i)); ret = add(ret, x); } sol = add(sol, ret); } void solve() { int i, j; memset(f, -1, sizeof(f)); factorial(); dfs(0, -1); printf( %d , sol); puts( ); } int main() { input(); solve(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTN_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFRTN_PP_BLACKBOX_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTN_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_16_V
`define SKY130_FD_SC_LP__CLKINV_16_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_16_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR2_2_V
`define SKY130_FD_SC_LS__XNOR2_2_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xnor2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xnor2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR2_2_V
|
#include <bits/stdc++.h> using namespace std; char board[500][500]; int n, m, k; int w = 0, e = 0; int t; bool used[500][500]; bool inBound(int a, int b) { return (a >= 0 && a < n && b >= 0 && b < m); } bool dfs(int a, int b) { if (t == 0) return false; bool check = true; used[a][b] = true; for (int i = -1; i < 2; i++) { for (int j = -1; j < 2; j++) { if (abs(i) + abs(j) == 1 && inBound(a + i, b + j) && board[a + i][b + j] == . ) { if (!used[a + i][b + j]) { check = dfs(a + i, b + j); } } } } if (t == 0) { return false; } if (check) { board[a][b] = X ; t--; } return check; } int main() { for (int i = 0; i < 500; i++) { for (int j = 0; j < 500; j++) { used[i][j] = false; } } cin >> n >> m >> k; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> board[i][j]; if (board[i][j] == . ) e++; else w++; } } t = k; bool bla = false; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (board[i][j] == . ) { dfs(i, j); bla = true; break; } } if (bla) break; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << board[i][j]; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int a[30]; bool mark[N]; bool dp[30][1000]; int n; void update() { dp[0][0] = 1; for (int i = 1; i <= n; i++) for (int j = 0; j < 1000; j++) { dp[i][j] = dp[i - 1][j]; if (j >= a[i] && !mark[i]) dp[i][j] |= dp[i - 1][j - a[i]]; } } int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + n + 1); update(); int k = n; for (int i = 1; i <= n; i++) { int t = a[i] - 1; for (int j = i - 1; j >= 1; j--) { if (a[j] != a[i] - 1 && a[j] <= t && !mark[j] && dp[j - 1][t - a[j]]) { update(); mark[j] = 1; t -= a[j]; k--; } } if (t) k = 200; } if (k == 1) cout << YES ; else cout << NO ; return 0; } |
#include <bits/stdc++.h> int main() { int days, time, count, free; int x = 0; scanf( %d , &days); scanf( %d , &time); int busyTime[days]; for (x = 0; x < days; x++) { scanf( %d , &busyTime[x]); } count = 0; while (time > 0) { free = 86400 - busyTime[count]; time -= free; count++; } printf( %d , count); } |
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: many_drivers.v,v 1.2 2001/07/21 02:30:44 stevewilliams Exp $
// $Log: many_drivers.v,v $
// Revision 1.2 2001/07/21 02:30:44 stevewilliams
// Get the expected blended values right.
//
// Revision 1.1 2001/07/18 01:22:26 sib4
// test for nets with many drivers
//
module test;
reg [66:0] in;
wire out;
buf (out, in[ 0]);
buf (out, in[ 1]);
buf (out, in[ 2]);
buf (out, in[ 3]);
buf (out, in[ 4]);
buf (out, in[ 5]);
buf (out, in[ 6]);
buf (out, in[ 7]);
buf (out, in[ 8]);
buf (out, in[ 9]);
buf (out, in[10]);
buf (out, in[11]);
buf (out, in[12]);
buf (out, in[13]);
buf (out, in[14]);
buf (out, in[15]);
buf (out, in[16]);
buf (out, in[17]);
buf (out, in[18]);
buf (out, in[19]);
buf (out, in[20]);
buf (out, in[21]);
buf (out, in[22]);
buf (out, in[23]);
buf (out, in[24]);
buf (out, in[25]);
buf (out, in[26]);
buf (out, in[27]);
buf (out, in[28]);
buf (out, in[29]);
buf (out, in[30]);
buf (out, in[31]);
buf (out, in[32]);
buf (out, in[33]);
buf (out, in[34]);
buf (out, in[35]);
buf (out, in[36]);
buf (out, in[37]);
buf (out, in[38]);
buf (out, in[39]);
buf (out, in[40]);
buf (out, in[41]);
buf (out, in[42]);
buf (out, in[43]);
buf (out, in[44]);
buf (out, in[45]);
buf (out, in[46]);
buf (out, in[47]);
buf (out, in[48]);
buf (out, in[49]);
buf (out, in[50]);
buf (out, in[51]);
buf (out, in[52]);
buf (out, in[53]);
buf (out, in[54]);
buf (out, in[55]);
buf (out, in[56]);
buf (out, in[57]);
buf (out, in[58]);
buf (out, in[59]);
buf (out, in[60]);
buf (out, in[61]);
buf (out, in[62]);
buf (out, in[63]);
buf (out, in[64]);
buf (out, in[65]);
buf (out, in[66]);
reg err;
// Verilog-XL yields out=x for all but the first two
initial
begin
err = 0;
in = 67'b0;
#1 $display("in=%b out=%b", in, out);
if (out!==1'b0) err = 1;
in = ~67'b0;
#1 $display("in=%b out=%b", in, out);
if (out!==1'b1) err = 1;
in = 67'bz;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = 67'bx;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = 67'h 5_55555555_55555555;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = ~67'h 5_55555555_55555555;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = 67'h 0_xxxxxxxx_00000000;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = ~67'h 0_xxxxxxxx_00000000;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = 67'h x_xxxxxxxx_00000000;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = ~67'h x_xxxxxxxx_00000000;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = 67'h x_55555555_55555555;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = ~67'h x_55555555_55555555;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = 67'h 1_ffffxxxx_00000000;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
in = ~67'h 1_ffffxxxx_00000000;
#1 $display("in=%b out=%b", in, out);
if (out!==1'bx) err = 1;
if (err)
$display("FAILED");
else
$display("PASSED");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e6 + 666; struct palindromic_tree { int len[MAXN], link[MAXN], cnt[MAXN]; char s[MAXN]; vector<pair<char, int>> to[MAXN]; int n, last, sz; void clear() { fill(to, to + MAXN, vector<pair<char, int>>()); memset(len, 0, sizeof(len)); memset(link, 0, sizeof(link)); memset(cnt, 0, sizeof(cnt)); memset(s, 0, sizeof(s)); n = last = 0; link[0] = 1; len[1] = -1; s[n++] = 27; sz = 2; } palindromic_tree() { clear(); } int get_link(int v) { while (s[n - len[v] - 2] != s[n - 1]) v = link[v]; return v; } int tr(int v, int c) { for (auto it : to[v]) if (it.first == c) return it.second; return 0; } int add_letter(int c) { s[n++] = c; int cur = get_link(last); if (!tr(cur, c)) { len[sz] = len[cur] + 2; link[sz] = tr(get_link(link[cur]), c); to[cur].push_back({c, sz++}); } last = tr(cur, c); return cnt[last] = cnt[link[last]] + 1; } }; struct palindromic_tree me; const int MOD = 51123987; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; string s; cin >> s; int start[n], finish[n]; for (int i = 0; i < n; i++) finish[i] = me.add_letter(s[i] - a ); me.clear(); for (int i = 0; i < n; i++) start[n - i - 1] = me.add_letter(s[n - i - 1] - a ); int64_t ans = accumulate(start, start + n, 0ll) % MOD; ans = ans * (ans - 1) / 2 % MOD; int64_t sum = 0; for (int i = 1; i < n; i++) { sum = (sum + finish[i - 1]) % MOD; ans = (ans - sum * start[i]) % MOD; if (ans < 0) ans += MOD; } cout << ans << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAP_2_V
`define SKY130_FD_SC_LP__TAP_2_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog wrapper for tap with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__tap_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__tap_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__tap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAP_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DFXBP_FUNCTIONAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXBP_FUNCTIONAL_PP_V |
// Generated by FIR Compiler 9.0 [Altera, IP Toolbench 1.3.0 Build 132]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2015 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module matchfilter (
clk,
reset_n,
ast_sink_data,
ast_sink_valid,
ast_source_ready,
ast_sink_error,
ast_source_data,
ast_sink_ready,
ast_source_valid,
ast_source_error);
input clk;
input reset_n;
input [14:0] ast_sink_data;
input ast_sink_valid;
input ast_source_ready;
input [1:0] ast_sink_error;
output [29:0] ast_source_data;
output ast_sink_ready;
output ast_source_valid;
output [1:0] ast_source_error;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O211AI_BEHAVIORAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211AI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int MAX = (1 << 22) + 5; int full, n, m; bool v[MAX], b[MAX], h[MAX]; void dfsans(int now); void dfs(int now) { if (v[now]) return; v[now] = true; if (h[now]) dfsans(now); for (int i = 0; i < n; i++) { if (!(now & (1 << i))) continue; dfs(now ^ (1 << i)); } } void dfsans(int now) { if (b[now]) return; b[now] = true; dfs(now ^ full); } int main() { scanf( %d%d , &n, &m); full = (1 << n) - 1; for (int i = 0; i < m; i++) { int x; scanf( %d , &x); h[x] = true; } int ans = 0; for (int i = 0; i < (full + 1); i++) { if (!h[i] || b[i]) continue; ans++; dfsans(i); } printf( %d n , ans); } |
#include <bits/stdc++.h> int main() { int N; std::cin >> N; std::set<std::pair<int, int>> doubled; std::set<std::pair<int, int>> pending; int to_double = 0; int l_doubled = 0; int64_t total_damage = 0; int t; int d; for (int i = 0; i < N; i++) { std::cin >> t; std::cin >> d; total_damage += d; to_double += t * (d > 0 ? 1 : -1); if (d > 0) { pending.insert({d, t}); } else { auto search = doubled.find({-d, t}); if (search != doubled.end()) { doubled.erase(search); l_doubled -= t; total_damage += d; } else { pending.erase(pending.find({-d, t})); } } if (to_double > doubled.size()) { if (pending.size() > 0) { auto it_pending = --pending.end(); std::pair<int, int> max = *it_pending; doubled.insert(max); pending.erase(it_pending); l_doubled += max.second; total_damage += max.first; } } else if (to_double < doubled.size()) { if (doubled.size() > 0) { auto it_doubled = doubled.begin(); std::pair<int, int> min = *it_doubled; doubled.erase(it_doubled); pending.insert(min); l_doubled -= min.second; total_damage -= min.first; } } else { if (to_double > 0 && pending.size() > 0) { auto it_doubled = doubled.begin(); auto it_pending = --pending.end(); std::pair<int, int> max = *it_pending; std::pair<int, int> min = *it_doubled; if (max > min) { doubled.erase(it_doubled); pending.erase(it_pending); doubled.insert(max); pending.insert(min); l_doubled += max.second - min.second; total_damage += max.first - min.first; } } } if (doubled.size() == to_double && l_doubled == to_double && to_double > 0) { auto it_doubled = doubled.begin(); std::pair<int, int> min = *it_doubled; doubled.erase(it_doubled); total_damage -= min.first; l_doubled--; if (pending.size() > 0) { auto it_pending = --pending.end(); std::pair<int, int> max = *it_pending; pending.erase(it_pending); doubled.insert(max); total_damage += max.first; } pending.insert(min); } std::cout << total_damage << std::endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 4 == 1 || n % 4 == 2) cout << 1; else cout << 0; } |
// file: DemoInterconnect_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// ____aclk____72.000______0.000______50.0______499.161____686.541
// ____uart____12.000______0.000______50.0______680.336____686.541
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary______________12____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "DemoInterconnect_clk_wiz_0_0,clk_wiz_v5_4_2_0,{component_name=DemoInterconnect_clk_wiz_0_0,use_phase_alignment=true,use_min_o_jitter=true,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=83.333,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module DemoInterconnect_clk_wiz_0_0
(
// Clock out ports
output aclk,
output uart,
// Status and control signals
input reset,
output locked,
// Clock in ports
input clk_in1
);
DemoInterconnect_clk_wiz_0_0_clk_wiz inst
(
// Clock out ports
.aclk(aclk),
.uart(uart),
// Status and control signals
.reset(reset),
.locked(locked),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_cmdram_wrap.v
// Version : v1.0
// Description: command ram wrapper module: To manage the read/write
// addresses to cmdram module.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_cmdram_wrap #
(
parameter C_FAMILY = "virtex7",
parameter C_ATG_BASIC_AXI4 = 1 ,
parameter C_M_AXI_DATA_WIDTH = 32 ,
parameter C_RAMINIT_CMDRAM0_F = "NONE",
parameter C_RAMINIT_CMDRAM1_F = "NONE",
parameter C_RAMINIT_CMDRAM2_F = "NONE",
parameter C_RAMINIT_CMDRAM3_F = "NONE"
) (
input Clk ,
input rst_l ,
input [15:0 ] cmdram_we ,
input [15:0 ] aw_agen_addr ,
input reg0_m_enable_ff ,
input [9:0 ] reg0_mw_ptr_update , //maw_ptr_new
input [9:0 ] reg0_mr_ptr_update , //mar_ptr_new
input [9:0 ] mar_ptr_new_ff ,
input [15:0 ] ar_agen0_addr ,
input [63:0 ] slvram_wr_data ,
input arfifo_valid ,
input [71:0 ] arfifo_out ,
input [23:0 ] param_cmdr_submitcnt_ff ,
input [23:0 ] param_cmdw_submitcnt_ff ,
input [9:0 ] maw_ptr_new_ff ,
output [127:0] cmd_out_mr_i ,
output cmdram_mr_regslice_id_stable,
output [127:0] cmd_out_mw_regslice ,
output [127:0] cmd_out_mr_regslice ,
output [127:0] cmd_out_mw_regslice_ff ,
output [127:0] cmd_out_mr_regslice_ff ,
output cmdram_mw_regslice_id_stable
);
wire [9:0] maw_ptr_new = reg0_mw_ptr_update;
wire [9:0] mar_ptr_new = reg0_mr_ptr_update;
wire [127:0] cmd_out_mw_i;
wire [15:0] cmdram_addra = (reg0_m_enable_ff) ?
{ 4'b0001, maw_ptr_new[7:0], 4'b0000 } :
{ 3'b000, aw_agen_addr[12:4], 4'b0000 };
wire [15:0] cmdram_addrb = (reg0_m_enable_ff) ?
{ 4'b0000, mar_ptr_new[7:0], 4'b0000 } :
{ 3'b000, ar_agen0_addr[12:4], 4'b0000 };
wire [127:0] cmd_out_mw_raw;
wire [127:0] cmd_out_mr_raw;
generate if (C_ATG_BASIC_AXI4 == 0 ) begin : CMDRAM_FULLAXI
assign cmd_out_mw_i = cmd_out_mw_raw;
assign cmd_out_mr_i = cmd_out_mr_raw;
end
endgenerate
//
//Fixed controls for a basic axi4 support.
//
wire [2:0] size;
generate if(C_M_AXI_DATA_WIDTH == 32 ) begin : CMDWRAP_SISE32
assign size = 3'b010;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 64 ) begin : CMDWRAP_SISE64
assign size = 3'b011;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 128 ) begin : CMDWRAP_SISE128
assign size = 3'b100;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 256 ) begin : CMDWRAP_SISE256
assign size = 3'b101;
end
endgenerate
generate if(C_M_AXI_DATA_WIDTH == 512 ) begin : CMDWRAP_SISE512
assign size = 3'b110;
end
endgenerate
wire fixed_lock = 1'b0;
wire [1:0] fixed_burst = 2'b01;
wire [2:0] fixed_prot = 3'b010;
wire [3:0] fixed_cache = 4'h0;
wire [7:0] fixed_user = 7'h0;
wire [2:0] fixed_size = size;
wire [3:0] fixed_qos = 4'h0;
generate if (C_ATG_BASIC_AXI4 == 1 ) begin : CMDRAM_BASICAXI
assign cmd_out_mw_i = {
cmd_out_mw_raw[127],fixed_qos,fixed_user,fixed_cache,cmd_out_mw_raw[99:96],
cmd_out_mw_raw[95:64],
cmd_out_mw_raw[63:56],fixed_prot,cmd_out_mw_raw[52:47],fixed_size,fixed_burst,cmd_out_mw_raw[41],fixed_lock,cmd_out_mw_raw[39:32],
cmd_out_mw_raw[31:0]
};
assign cmd_out_mr_i = {
cmd_out_mr_raw[127],fixed_qos,fixed_user,fixed_cache,cmd_out_mr_raw[99:96],
cmd_out_mr_raw[95:64],
cmd_out_mr_raw[63:56],fixed_prot,cmd_out_mr_raw[52:47],fixed_size,fixed_burst,cmd_out_mr_raw[41],fixed_lock,cmd_out_mr_raw[39:32],
cmd_out_mr_raw[31:0]
};
end
endgenerate
axi_traffic_gen_v2_0_cmdram #(
.C_FAMILY (C_FAMILY ),
.C_INITRAM_0(C_RAMINIT_CMDRAM0_F),
.C_INITRAM_1(C_RAMINIT_CMDRAM1_F),
.C_INITRAM_2(C_RAMINIT_CMDRAM2_F),
.C_INITRAM_3(C_RAMINIT_CMDRAM3_F)
) Cmdram (
.reset (~rst_l ),
.clk_a (Clk ),
.we_a (cmdram_we[15:0] ),
.active (reg0_m_enable_ff ),
.addr_a_idle ({ 3'b000, aw_agen_addr[12:4], 4'b0000 } ),
.addr_a_active ( { 4'b0001, maw_ptr_new_ff[7:0], 4'b0000 }),
.wr_data_a ({ 2 { slvram_wr_data[63:0] } } ),
.rd_data_a (cmd_out_mw_raw[127:0] ),
.clk_b (Clk ),
.addr_b_idle_latch(arfifo_valid ),
.addr_b_idle ({ 3'b000, arfifo_out[12:4], 4'b0000 } ),
.addr_b_active ({ 4'b0000, mar_ptr_new_ff[7:0], 4'b0000 } ),
.rd_data_b (cmd_out_mr_raw[127:0] )
);
// id is a mix of submitcnt,mar_ptr -- so can ID new cmds even if just a repeat
wire [9:0] cmdram_mr_regslice_idin = {param_cmdr_submitcnt_ff[0],1'b0, mar_ptr_new_ff[7:0]};
wire [9:0] cmdram_mw_regslice_idin = {param_cmdw_submitcnt_ff[0],reg0_m_enable_ff, maw_ptr_new_ff[7:0]};
axi_traffic_gen_v2_0_regslice
#(
.DWIDTH (128 ),
.IDWIDTH (10 ),
.DATADEPTH(`REGSLICE_CMDRAM_MR_DATA),
.IDDEPTH (`REGSLICE_CMDRAM_MR_ID )
)
cmdram_regslice_r
(
.din (cmd_out_mr_i ),
.dout (cmd_out_mr_regslice_ff ),
.dout_early (cmd_out_mr_regslice ),
.idin (cmdram_mr_regslice_idin ),
.idout ( ),
.id_stable (cmdram_mr_regslice_id_stable),
.id_stable_ff( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
axi_traffic_gen_v2_0_regslice
#(
.DWIDTH (128 ),
.IDWIDTH (10 ),
.DATADEPTH(`REGSLICE_CMDRAM_MW_DATA),
.IDDEPTH (`REGSLICE_CMDRAM_MW_ID )
)
cmdram_regslice_w
(
.din (cmd_out_mw_i ),
.dout (cmd_out_mw_regslice_ff ),
.dout_early (cmd_out_mw_regslice ),
.idin (cmdram_mw_regslice_idin ),
.idout ( ),
.id_stable (cmdram_mw_regslice_id_stable),
.id_stable_ff( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mxn = 5e3 + 100; long long dp[25][mxn]; long long arr[mxn]; long long n, k; bool Check(long long id, long long lo, long long hi, long long rtk) { while (lo <= hi) { long long mid = (lo + hi) / 2; if (dp[id][mid] > rtk) hi = mid - 1; else if (dp[id][mid] < rtk) lo = mid + 1; else return true; } return false; } int main() { scanf( %lld%lld , &n, &k); for (int i = 1; i <= n; i++) scanf( %lld , &arr[i]); sort(arr + 1, arr + n + 1); for (int i = 1; i <= n; i++) dp[1][i] = arr[i]; for (int i = 2; i <= k; i++) { for (long long j = 1; j <= n; j++) dp[i][j] = arr[j] * i; } long long q; scanf( %lld , &q); while (q--) { long long tk; scanf( %lld , &tk); long long mn = 1e9; long long ans = 0; for (int i = 1; i <= k; i++) { for (int j = 1; j <= n; j++) { long long tmp = dp[i][j]; if (tmp > tk) break; long long ans = i; long long rem = k - i; if (tmp == tk) mn = min(ans, mn); else { for (int jj = 1; jj <= rem; jj++) { if (Check(jj, j + 1, n, tk - tmp)) { mn = min(ans + jj, mn); break; } } } } } if (mn == 1e9) mn = -1; printf( %lld n , mn); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 1e5 + 9; int n, v[MAX]; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n; for (int i = 0, x; i < n; i++) cin >> x, v[x % n] = i; for (int i = 0, x; i < n; i++) cin >> x, cout << v[x % n] + 1 << ; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; while (cin >> n) { long long ans = 0; for (int i = 0; i <= 8 && i <= n; i++) { for (int j = 0; j <= (i == 0 ? 8 : 4) && i + j <= n; j++) { ans += n + 1 - i - j; } } cout << ans << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A41OI_BEHAVIORAL_PP_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; struct CC { long long x1, x2, y1, y2; }; CC jiao(CC a, CC b) { CC c1; c1.x1 = max(a.x1, b.x1); c1.y1 = max(a.y1, b.y1); c1.x2 = min(a.x2, b.x2); c1.y2 = min(a.y2, b.y2); return c1; } int main() { CC w, b1, b2; cin >> w.x1 >> w.y1 >> w.x2 >> w.y2 >> b1.x1 >> b1.y1 >> b1.x2 >> b1.y2 >> b2.x1 >> b2.y1 >> b2.x2 >> b2.y2; CC j1 = jiao(w, b1); CC j2 = jiao(w, b2); CC j3 = jiao(j1, j2); long long s, s1, s2, s3; s = (w.x2 - w.x1) * (w.y2 - w.y1); if (j1.x1 > j1.x2 || j1.y1 > j1.y2) s1 = 0; else s1 = (j1.x2 - j1.x1) * (j1.y2 - j1.y1); if (j2.x1 > j2.x2 || j2.y1 > j2.y2) s2 = 0; else s2 = (j2.x2 - j2.x1) * (j2.y2 - j2.y1); if (j3.x1 > j3.x2 || j3.y1 > j3.y2) s3 = 0; else s3 = (j3.x2 - j3.x1) * (j3.y2 - j3.y1); if (s1 + s2 - s3 == s) cout << NO << endl; else cout << YES << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); string cad; cin >> cad; map<char, int> M; for (int i = 0; i < cad.size(); i++) M[cad[i]]++; int xx = M[ x ]; int yy = M[ y ]; int ans = max(xx, yy) - min(xx, yy); if (max(xx, yy) == M[ x ]) cout << string(ans, x ) << endl; else cout << string(ans, y ) << endl; return 0; } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:39:36 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_bram_0/zynq_design_1_axi_bram_ctrl_0_bram_0_stub.v
// Design : zynq_design_1_axi_bram_ctrl_0_bram_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_3_6,Vivado 2017.2" *)
module zynq_design_1_axi_bram_ctrl_0_bram_0(clka, rsta, ena, wea, addra, dina, douta, clkb, rstb, enb,
web, addrb, dinb, doutb)
/* synthesis syn_black_box black_box_pad_pin="clka,rsta,ena,wea[3:0],addra[31:0],dina[31:0],douta[31:0],clkb,rstb,enb,web[3:0],addrb[31:0],dinb[31:0],doutb[31:0]" */;
input clka;
input rsta;
input ena;
input [3:0]wea;
input [31:0]addra;
input [31:0]dina;
output [31:0]douta;
input clkb;
input rstb;
input enb;
input [3:0]web;
input [31:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: COMMAND_PAGE.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module COMMAND_PAGE (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [15:0] data;
input [7:0] rdaddress;
input [8:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
// Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL "wraddress[8..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:10:33 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xbar_0_stub.v
// Design : zqynq_lab_1_design_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast[0:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast[0:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awid[47:0],m_axi_awaddr[127:0],m_axi_awlen[31:0],m_axi_awsize[11:0],m_axi_awburst[7:0],m_axi_awlock[3:0],m_axi_awcache[15:0],m_axi_awprot[11:0],m_axi_awregion[15:0],m_axi_awqos[15:0],m_axi_awvalid[3:0],m_axi_awready[3:0],m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast[3:0],m_axi_wvalid[3:0],m_axi_wready[3:0],m_axi_bid[47:0],m_axi_bresp[7:0],m_axi_bvalid[3:0],m_axi_bready[3:0],m_axi_arid[47:0],m_axi_araddr[127:0],m_axi_arlen[31:0],m_axi_arsize[11:0],m_axi_arburst[7:0],m_axi_arlock[3:0],m_axi_arcache[15:0],m_axi_arprot[11:0],m_axi_arregion[15:0],m_axi_arqos[15:0],m_axi_arvalid[3:0],m_axi_arready[3:0],m_axi_rid[47:0],m_axi_rdata[127:0],m_axi_rresp[7:0],m_axi_rlast[3:0],m_axi_rvalid[3:0],m_axi_rready[3:0]" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [47:0]m_axi_awid;
output [127:0]m_axi_awaddr;
output [31:0]m_axi_awlen;
output [11:0]m_axi_awsize;
output [7:0]m_axi_awburst;
output [3:0]m_axi_awlock;
output [15:0]m_axi_awcache;
output [11:0]m_axi_awprot;
output [15:0]m_axi_awregion;
output [15:0]m_axi_awqos;
output [3:0]m_axi_awvalid;
input [3:0]m_axi_awready;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output [3:0]m_axi_wlast;
output [3:0]m_axi_wvalid;
input [3:0]m_axi_wready;
input [47:0]m_axi_bid;
input [7:0]m_axi_bresp;
input [3:0]m_axi_bvalid;
output [3:0]m_axi_bready;
output [47:0]m_axi_arid;
output [127:0]m_axi_araddr;
output [31:0]m_axi_arlen;
output [11:0]m_axi_arsize;
output [7:0]m_axi_arburst;
output [3:0]m_axi_arlock;
output [15:0]m_axi_arcache;
output [11:0]m_axi_arprot;
output [15:0]m_axi_arregion;
output [15:0]m_axi_arqos;
output [3:0]m_axi_arvalid;
input [3:0]m_axi_arready;
input [47:0]m_axi_rid;
input [127:0]m_axi_rdata;
input [7:0]m_axi_rresp;
input [3:0]m_axi_rlast;
input [3:0]m_axi_rvalid;
output [3:0]m_axi_rready;
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module alt_mem_ddrx_buffer
# (
// module parameter port list
parameter
ADDR_WIDTH = 3,
DATA_WIDTH = 8
)
(
// port list
ctl_clk,
ctl_reset_n,
// write interface
write_valid,
write_address,
write_data,
// read interface
read_valid,
read_address,
read_data
);
// -----------------------------
// local parameter declaration
// -----------------------------
localparam BUFFER_DEPTH = two_pow_N(ADDR_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// write interface
input write_valid;
input [ADDR_WIDTH-1:0] write_address;
input [DATA_WIDTH-1:0] write_data;
// read interface
input read_valid;
input [ADDR_WIDTH-1:0] read_address;
output [DATA_WIDTH-1:0] read_data;
// -----------------------------
// port type declaration
// -----------------------------
wire ctl_clk;
wire ctl_reset_n;
// write interface
wire write_valid;
wire [ADDR_WIDTH-1:0] write_address;
wire [DATA_WIDTH-1:0] write_data;
// read interface
wire read_valid;
wire [ADDR_WIDTH-1:0] read_address;
wire [DATA_WIDTH-1:0] read_data;
// -----------------------------
// module definition
// -----------------------------
altsyncram altsyncram_component
(
.wren_a (write_valid),
.clock0 (ctl_clk),
.address_a (write_address),
.address_b (read_address),
.data_a (write_data),
.q_b (read_data),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({DATA_WIDTH{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.indata_aclr_a = "NONE",
altsyncram_component.intended_device_family = "Stratix",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = BUFFER_DEPTH,
altsyncram_component.numwords_b = BUFFER_DEPTH,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = ADDR_WIDTH,
altsyncram_component.widthad_b = ADDR_WIDTH,
altsyncram_component.width_a = DATA_WIDTH,
altsyncram_component.width_b = DATA_WIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.wrcontrol_aclr_a = "NONE";
// alt_ddrx_ram_2port
// ram_inst
// (
// .clock (ctl_clk),
// .wren (write_valid),
// .wraddress (write_address),
// .data (write_data),
// .rdaddress (read_address),
// .q (read_data)
// );
function integer two_pow_N;
input integer value;
begin
two_pow_N = 2 << (value-1);
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008-2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
wire [9:0] I1 = crc[9:0];
wire [9:0] I2 = crc[19:10];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [9:0] S; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.S (S[9:0]),
// Inputs
.I1 (I1[9:0]),
.I2 (I2[9:0]));
wire [63:0] result = {32'h0, 22'h0, S};
`define EXPECTED_SUM 64'h24c38b77b0fcc2e7
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
S,
// Inputs
I1, I2
);
input [9:0] I1/*verilator public*/;
input [9:0] I2/*verilator public*/;
output reg [9:0] S/*verilator public*/;
always @(I1 or I2)
t2(I1,I2,S);
task t1;
input In1,In2;
output Sum;
Sum = In1 ^ In2;
endtask
task t2;
input[9:0] In1,In2;
output [9:0] Sum;
integer I;
begin
for (I=0;I<10;I=I+1)
t1(In1[I],In2[I],Sum[I]);
end
endtask
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// NOTE This only works for N=4, max interp rate of 128
// NOTE signal "rate" is ONE LESS THAN the actual rate
module cic_int_shifter(rate,signal_in,signal_out);
parameter bw = 16;
parameter maxbitgain = 21;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case(rate)
// Exact Cases
8'd4 : bitgain = 6;
8'd8 : bitgain = 9;
8'd16 : bitgain = 12;
8'd32 : bitgain = 15;
8'd64 : bitgain = 18;
8'd128 : bitgain = 21;
// Nearest without overflow
8'd5 : bitgain = 7;
8'd6 : bitgain = 8;
8'd7 : bitgain = 9;
8'd9,8'd10 : bitgain = 10;
8'd11,8'd12 : bitgain = 11;
8'd13,8'd14,8'd15 : bitgain = 12;
8'd17,8'd18,8'd19,8'd20 : bitgain = 13;
8'd21,8'd22,8'd23,8'd24,8'd25 : bitgain = 14;
8'd26,8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 15;
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38,8'd39,8'd40 : bitgain = 16;
8'd41,8'd42,8'd43,8'd44,8'd45,8'd46,8'd47,8'd48,8'd49,8'd50 : bitgain = 17;
8'd51,8'd52,8'd53,8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 18;
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76,8'd77,8'd78,8'd79,8'd80 : bitgain = 19;
8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90,8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101 : bitgain = 20;
default : bitgain = 21;
endcase // case(rate)
endfunction // bitgain
wire [4:0] shift = bitgain(rate+1);
// We should be able to do this, but can't ....
// assign signal_out = signal_in[shift+bw-1:shift];
always @*
case(shift)
5'd6 : signal_out = signal_in[6+bw-1:6];
5'd9 : signal_out = signal_in[9+bw-1:9];
5'd12 : signal_out = signal_in[12+bw-1:12];
5'd15 : signal_out = signal_in[15+bw-1:15];
5'd18 : signal_out = signal_in[18+bw-1:18];
5'd21 : signal_out = signal_in[21+bw-1:21];
5'd7 : signal_out = signal_in[7+bw-1:7];
5'd8 : signal_out = signal_in[8+bw-1:8];
5'd10 : signal_out = signal_in[10+bw-1:10];
5'd11 : signal_out = signal_in[11+bw-1:11];
5'd13 : signal_out = signal_in[13+bw-1:13];
5'd14 : signal_out = signal_in[14+bw-1:14];
5'd16 : signal_out = signal_in[16+bw-1:16];
5'd17 : signal_out = signal_in[17+bw-1:17];
5'd19 : signal_out = signal_in[19+bw-1:19];
5'd20 : signal_out = signal_in[20+bw-1:20];
default : signal_out = signal_in[21+bw-1:21];
endcase // case(shift)
endmodule // cic_int_shifter
|
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: dotinid.v,v 1.1 2001/06/26 00:32:18 sib4 Exp $
// $Log: dotinid.v,v $
// Revision 1.1 2001/06/26 00:32:18 sib4
// Two new tests for identifier parsing/elaboration
//
//
// IVL parser/elaboration test for escaped names with .
module a;
wire \a.b ;
m \c.d (\a.b );
initial
begin
\c.d . \y.z <= 1'b1;
#1;
if (\a.b === 1'b1)
$display("PASSED");
else
$display("FAILED");
end
endmodule
module m(x);
output x;
reg \y.z ;
assign x = \y.z ;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool mul_overflow(long long a, long long b) { return (a > (LLONG_MAX / b)); } bool add_overflow(long long a, long long b) { return (a > (LLONG_MAX - b)); } const int N = 1e6 + 5; int n; long double a[N][3]; bool sol(long double mid) { long double l = -1e8, r = 1e8; for (int i = 1; i <= n; i++) { long double rs = 2 * mid * a[i][2] - a[i][2] * a[i][2]; if (rs < 0) { l = -1e8, r = 1e8; } else { l = max(l, a[i][1] - sqrt(rs)); r = min(r, a[i][1] + sqrt(rs)); } } cout << (l <= r) << n ; return (l <= r); } int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i][1] >> a[i][2]; } int f = -1; if (a[1][1] >= 0 && a[1][2] >= 0 || a[1][2] >= 0 && a[1][1] <= 0) f = 1; else f = 0; for (int i = 2; i <= n; i++) { if (f == 1) { if (!(a[i][1] >= 0 && a[i][2] >= 0 || a[i][2] >= 0 && a[i][1] <= 0)) { cout << -1 n ; return 0; } } else { if (a[i][1] >= 0 && a[i][2] >= 0 || a[i][2] >= 0 && a[i][1] <= 0) { cout << -1 n ; return 0; } } } if (n == 1) { cout << a[1][2] / 2 << n ; return 0; } long double lo = 0, hi = 1e18; for (int i = 1; i <= 100; i++) { long double xl = -1e18, xr = 1e18; long double r = (lo + hi) / 2; bool f = 0; for (int i = 1; i <= n; i++) { long double x = a[i][1], y = abs(a[i][2]); long double t = 2 * y * r - y * y; if (t < 0) { f = 1; break; } t = sqrt(t); xl = max(xl, x - t); xr = min(xr, x + t); } if (f == false && xr > xl) { hi = r; } else lo = r; } cout << fixed << setprecision(11) << lo << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int n; cin >> n; int cnt = 0; while (n > 1) { if (n % 5 == 0) { n = (4 * n) / 5; cnt++; continue; } else if (n % 3 == 0) { n = (2 * n) / 3; cnt++; continue; } else if (n % 2 == 0) { n = (n) / 2; cnt++; continue; } else { cnt = -1; break; } } cout << cnt << endl; } } |
module opicorv32_mul_wrap (
pcpi_rs2,
pcpi_rs1,
pcpi_insn,
pcpi_valid,
resetn,
clk,
pcpi_wr,
pcpi_rd,
pcpi_wait,
pcpi_ready
);
input [31:0] pcpi_rs2;
input [31:0] pcpi_rs1;
input [31:0] pcpi_insn;
input pcpi_valid;
input resetn;
input clk;
output pcpi_wr;
output [31:0] pcpi_rd;
output pcpi_wait;
output pcpi_ready;
/* signal declarations */
wire _1746;
wire _1742;
wire compare_pcpi_ready;
wire _1748;
wire _1749;
wire _1743;
wire compare_pcpi_wait;
wire _1751;
wire [31:0] _1752;
wire [31:0] _1744;
wire [31:0] compare_pcpi_rd;
wire [31:0] _1754;
wire [34:0] _1739;
wire _1755;
wire [34:0] _1741;
wire _1745;
wire compare_pcpi_wr;
wire _1757;
/* logic */
assign _1746 = _1739[34:34];
assign _1742 = _1741[34:34];
assign compare_pcpi_ready = _1742 ^ _1746;
assign _1748 = compare_pcpi_ready ^ _1746;
assign _1749 = _1739[33:33];
assign _1743 = _1741[33:33];
assign compare_pcpi_wait = _1743 ^ _1749;
assign _1751 = compare_pcpi_wait ^ _1749;
assign _1752 = _1739[32:1];
assign _1744 = _1741[32:1];
assign compare_pcpi_rd = _1744 ^ _1752;
assign _1754 = compare_pcpi_rd ^ _1752;
picorv32_mul
the_picorv32_mul
( .clk(clk), .resetn(resetn), .pcpi_valid(pcpi_valid), .pcpi_insn(pcpi_insn), .pcpi_rs1(pcpi_rs1), .pcpi_rs2(pcpi_rs2), .pcpi_ready(_1739[34:34]), .pcpi_wait(_1739[33:33]), .pcpi_rd(_1739[32:1]), .pcpi_wr(_1739[0:0]) );
assign _1755 = _1739[0:0];
opicorv32_mul
the_opicorv32_mul
( .clk(clk), .resetn(resetn), .pcpi_valid(pcpi_valid), .pcpi_insn(pcpi_insn), .pcpi_rs1(pcpi_rs1), .pcpi_rs2(pcpi_rs2), .pcpi_ready(_1741[34:34]), .pcpi_wait(_1741[33:33]), .pcpi_rd(_1741[32:1]), .pcpi_wr(_1741[0:0]) );
assign _1745 = _1741[0:0];
assign compare_pcpi_wr = _1745 ^ _1755;
assign _1757 = compare_pcpi_wr ^ _1755;
/* aliases */
/* output assignments */
assign pcpi_wr = _1757;
assign pcpi_rd = _1754;
assign pcpi_wait = _1751;
assign pcpi_ready = _1748;
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const long long MOD = 1e9 + 7; long long a[200012]; long long in[200021], out[200012]; void solve() { long long n, m, i, j, c, sum; i = j = c = sum = 0; cin >> n; for (i = 0; i < n; ++i) { cin >> a[i]; --a[i]; if (a[i] != -1) { ++in[a[i]]; ++out[i]; } } vector<long long> loops; for (i = 0; i < n; ++i) { if (in[i] == 0 and out[i] == 0) { loops.push_back(i); } } if (loops.size() == 1) { long long init = loops[0]; for (i = 0; i < n; ++i) { if (in[i] == 0 and i != init) { a[init] = i; ++out[init]; ++in[i]; break; } } } else if (loops.size() > 1) { for (i = 0; i < loops.size(); ++i) { long long curr = loops[i]; long long nxt = loops[(i + 1) % loops.size()]; a[curr] = nxt; ++in[nxt]; ++out[curr]; } } vector<long long> ins, outs; for (i = 0; i < n; ++i) { if (in[i] == 0) ins.push_back(i); if (out[i] == 0) outs.push_back(i); } for (i = 0; i < outs.size(); ++i) { a[outs[i]] = ins[i]; } for (i = 0; i < n; ++i) { cout << a[i] + 1 << ; } cout << n ; } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> void start(int *ST, int *END, int n, char *A) { int i, kol_vo = 0; for (i = n; i > 0; i--) { if (A[i] == A && END[0] == -1) { kol_vo++; END[0] = i; } if (A[i] == B && END[1] == -1) END[1] = i; kol_vo++; ; if (A[i] == C && END[2] == -1) END[2] = i; kol_vo++; if (A[i] == D && END[3] == -1) END[3] = i; kol_vo++; if (A[i] == E && END[4] == -1) END[4] = i; kol_vo++; if (A[i] == F && END[5] == -1) END[5] = i; kol_vo++; if (A[i] == G && END[6] == -1) END[6] = i; kol_vo++; if (A[i] == H && END[7] == -1) END[7] = i; kol_vo++; if (A[i] == I && END[8] == -1) END[8] = i; kol_vo++; if (A[i] == J && END[9] == -1) END[9] = i; kol_vo++; if (A[i] == K && END[10] == -1) { END[10] = i; kol_vo++; } if (A[i] == L && END[11] == -1) { END[11] = i; kol_vo++; } if (A[i] == M && END[12] == -1) { END[12] = i; kol_vo++; } if (A[i] == N && END[13] == -1) { END[13] = i; kol_vo++; } if (A[i] == O && END[14] == -1) { END[14] = i; kol_vo++; } if (A[i] == P && END[15] == -1) { END[15] = i; kol_vo++; } if (A[i] == Q && END[16] == -1) { END[16] = i; kol_vo++; } if (A[i] == R && END[17] == -1) { END[17] = i; kol_vo++; } if (A[i] == S && END[18] == -1) { END[18] = i; kol_vo++; } if (A[i] == T && END[19] == -1) { END[19] = i; kol_vo++; } if (A[i] == U && END[20] == -1) { END[20] = i; kol_vo++; } if (A[i] == V && END[21] == -1) { END[21] = i; kol_vo++; } if (A[i] == W && END[22] == -1) { END[22] = i; kol_vo++; } if (A[i] == X && END[23] == -1) { END[23] = i; kol_vo++; } if (A[i] == Y && END[24] == -1) { END[24] = i; kol_vo++; } if (A[i] == Z && END[25] == -1) { END[25] = i; kol_vo++; } if (kol_vo == 26) break; } } int main() { int n, k, i, ST[26], END[26], answ = 1; char *Guest, tmp; scanf( %d %d , &n, &k); n++; Guest = (char *)malloc(n * sizeof(char)); for (i = 0; i < n; i++) scanf( %c , &Guest[i]); for (i = 0; i < 26; i++) { ST[i] = -1; END[i] = -1; } start(ST, END, n, Guest); for (i = 1; i < n; i++) { if (Guest[i] == A && ST[0] == -1) { ST[0] = 1; k--; if (k < 0) answ = -1; } if (END[0] == i) k++; if (Guest[i] == B && ST[1] == -1) { ST[1] = 1; k--; if (k < 0) answ = -1; } if (END[1] == i) k++; if (Guest[i] == C && ST[2] == -1) { ST[2] = 1; k--; if (k < 0) answ = -1; } if (END[2] == i) k++; if (Guest[i] == D && ST[3] == -1) { ST[3] = 1; k--; if (k < 0) answ = -1; } if (END[3] == i) k++; if (Guest[i] == E && ST[4] == -1) { ST[4] = 1; k--; if (k < 0) answ = -1; } if (END[4] == i) k++; if (Guest[i] == F && ST[5] == -1) { ST[5] = 1; k--; if (k < 0) answ = -1; } if (END[5] == i) k++; if (Guest[i] == G && ST[6] == -1) { ST[6] = 1; k--; if (k < 0) answ = -1; } if (END[6] == i) k++; if (Guest[i] == H && ST[7] == -1) { ST[7] = 1; k--; if (k < 0) answ = -1; } if (END[7] == i) k++; if (Guest[i] == I && ST[8] == -1) { ST[8] = 1; k--; if (k < 0) answ = -1; } if (END[8] == i) k++; if (Guest[i] == J && ST[9] == -1) { ST[9] = 1; k--; if (k < 0) answ = -1; } if (END[9] == i) k++; if (Guest[i] == K && ST[10] == -1) { ST[10] = 1; k--; if (k < 0) answ = -1; } if (END[10] == i) k++; if (Guest[i] == L && ST[11] == -1) { ST[11] = 1; k--; if (k < 0) answ = -1; } if (END[11] == i) k++; if (Guest[i] == M && ST[12] == -1) { ST[12] = 1; k--; if (k < 0) answ = -1; } if (END[12] == i) k++; if (Guest[i] == N && ST[13] == -1) { ST[13] = 1; k--; if (k < 0) answ = -1; } if (END[13] == i) k++; if (Guest[i] == O && ST[14] == -1) { ST[14] = 1; k--; if (k < 0) answ = -1; } if (END[14] == i) k++; if (Guest[i] == P && ST[15] == -1) { ST[15] = 1; k--; if (k < 0) answ = -1; } if (END[15] == i) k++; if (Guest[i] == Q && ST[16] == -1) { ST[16] = 1; k--; if (k < 0) answ = -1; } if (END[16] == i) k++; if (Guest[i] == R && ST[17] == -1) { ST[17] = 1; k--; if (k < 0) answ = -1; } if (END[17] == i) k++; if (Guest[i] == S && ST[18] == -1) { ST[18] = 1; k--; if (k < 0) answ = -1; } if (END[18] == i) k++; if (Guest[i] == T && ST[19] == -1) { ST[19] = 1; k--; if (k < 0) answ = -1; } if (END[19] == i) k++; if (Guest[i] == U && ST[20] == -1) { ST[20] = 1; k--; if (k < 0) answ = -1; } if (END[20] == i) k++; if (Guest[i] == V && ST[21] == -1) { ST[21] = 1; k--; if (k < 0) answ = -1; } if (END[21] == i) k++; if (Guest[i] == W && ST[22] == -1) { ST[22] = 1; k--; if (k < 0) answ = -1; } if (END[22] == i) k++; if (Guest[i] == X && ST[23] == -1) { ST[23] = 1; k--; if (k < 0) answ = -1; } if (END[23] == i) k++; if (Guest[i] == Y && ST[24] == -1) { ST[24] = 1; k--; if (k < 0) answ = -1; } if (END[24] == i) k++; if (Guest[i] == Z && ST[25] == -1) { ST[25] = 1; k--; if (k < 0) answ = -1; } if (END[25] == i) k++; } if (answ == -1) printf( YES ); else printf( NO ); return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bram_2048_1 (
clka,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [10 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [19 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [19 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("bram_2048_1.mif"),
.C_INIT_FILE("bram_2048_1.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(20),
.C_READ_WIDTH_A(20),
.C_WRITE_DEPTH_A(2048),
.C_READ_DEPTH_A(2048),
.C_ADDRA_WIDTH(11),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(20),
.C_READ_WIDTH_B(20),
.C_WRITE_DEPTH_B(2048),
.C_READ_DEPTH_B(2048),
.C_ADDRB_WIDTH(11),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.9373 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(11'B0),
.dinb(20'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(20'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// ghrd_10as066n2_avlmm_pr_freeze_bridge_1.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_avlmm_pr_freeze_bridge_1 (
input wire clock, // clock.clk
input wire freeze_conduit_freeze, // freeze_conduit.freeze
output wire freeze_conduit_illegal_request, // .illegal_request
input wire mst_bridge_to_pr_read, // mst_bridge_to_pr.read
output wire mst_bridge_to_pr_waitrequest, // .waitrequest
input wire mst_bridge_to_pr_write, // .write
input wire [31:0] mst_bridge_to_pr_address, // .address
input wire [3:0] mst_bridge_to_pr_byteenable, // .byteenable
input wire [31:0] mst_bridge_to_pr_writedata, // .writedata
output wire [31:0] mst_bridge_to_pr_readdata, // .readdata
input wire [2:0] mst_bridge_to_pr_burstcount, // .burstcount
output wire mst_bridge_to_pr_readdatavalid, // .readdatavalid
input wire mst_bridge_to_pr_beginbursttransfer, // .beginbursttransfer
input wire mst_bridge_to_pr_debugaccess, // .debugaccess
output wire [1:0] mst_bridge_to_pr_response, // .response
input wire mst_bridge_to_pr_lock, // .lock
output wire mst_bridge_to_pr_writeresponsevalid, // .writeresponsevalid
output wire mst_bridge_to_sr_read, // mst_bridge_to_sr.read
input wire mst_bridge_to_sr_waitrequest, // .waitrequest
output wire mst_bridge_to_sr_write, // .write
output wire [31:0] mst_bridge_to_sr_address, // .address
output wire [3:0] mst_bridge_to_sr_byteenable, // .byteenable
output wire [31:0] mst_bridge_to_sr_writedata, // .writedata
input wire [31:0] mst_bridge_to_sr_readdata, // .readdata
output wire [2:0] mst_bridge_to_sr_burstcount, // .burstcount
input wire mst_bridge_to_sr_readdatavalid, // .readdatavalid
output wire mst_bridge_to_sr_beginbursttransfer, // .beginbursttransfer
output wire mst_bridge_to_sr_debugaccess, // .debugaccess
input wire [1:0] mst_bridge_to_sr_response, // .response
output wire mst_bridge_to_sr_lock, // .lock
input wire mst_bridge_to_sr_writeresponsevalid, // .writeresponsevalid
input wire reset_n // reset_n.reset_n
);
ghrd_10as066n2_avlmm_pr_freeze_bridge_1_altera_avlmm_pr_freeze_bridge_171_yvsimhi #(
.ENABLE_FREEZE_FROM_PR_REGION (0),
.ENABLE_TRAFFIC_TRACKING (0)
) avlmm_pr_freeze_bridge_1 (
.clock (clock), // input, width = 1, clock.clk
.freeze_conduit_freeze (freeze_conduit_freeze), // input, width = 1, freeze_conduit.freeze
.freeze_conduit_illegal_request (freeze_conduit_illegal_request), // output, width = 1, .illegal_request
.mst_bridge_to_pr_read (mst_bridge_to_pr_read), // input, width = 1, mst_bridge_to_pr.read
.mst_bridge_to_pr_waitrequest (mst_bridge_to_pr_waitrequest), // output, width = 1, .waitrequest
.mst_bridge_to_pr_write (mst_bridge_to_pr_write), // input, width = 1, .write
.mst_bridge_to_pr_address (mst_bridge_to_pr_address), // input, width = 32, .address
.mst_bridge_to_pr_byteenable (mst_bridge_to_pr_byteenable), // input, width = 4, .byteenable
.mst_bridge_to_pr_writedata (mst_bridge_to_pr_writedata), // input, width = 32, .writedata
.mst_bridge_to_pr_readdata (mst_bridge_to_pr_readdata), // output, width = 32, .readdata
.mst_bridge_to_pr_burstcount (mst_bridge_to_pr_burstcount), // input, width = 3, .burstcount
.mst_bridge_to_pr_readdatavalid (mst_bridge_to_pr_readdatavalid), // output, width = 1, .readdatavalid
.mst_bridge_to_pr_beginbursttransfer (mst_bridge_to_pr_beginbursttransfer), // input, width = 1, .beginbursttransfer
.mst_bridge_to_pr_debugaccess (mst_bridge_to_pr_debugaccess), // input, width = 1, .debugaccess
.mst_bridge_to_pr_response (mst_bridge_to_pr_response), // output, width = 2, .response
.mst_bridge_to_pr_lock (mst_bridge_to_pr_lock), // input, width = 1, .lock
.mst_bridge_to_pr_writeresponsevalid (mst_bridge_to_pr_writeresponsevalid), // output, width = 1, .writeresponsevalid
.mst_bridge_to_sr_read (mst_bridge_to_sr_read), // output, width = 1, mst_bridge_to_sr.read
.mst_bridge_to_sr_waitrequest (mst_bridge_to_sr_waitrequest), // input, width = 1, .waitrequest
.mst_bridge_to_sr_write (mst_bridge_to_sr_write), // output, width = 1, .write
.mst_bridge_to_sr_address (mst_bridge_to_sr_address), // output, width = 32, .address
.mst_bridge_to_sr_byteenable (mst_bridge_to_sr_byteenable), // output, width = 4, .byteenable
.mst_bridge_to_sr_writedata (mst_bridge_to_sr_writedata), // output, width = 32, .writedata
.mst_bridge_to_sr_readdata (mst_bridge_to_sr_readdata), // input, width = 32, .readdata
.mst_bridge_to_sr_burstcount (mst_bridge_to_sr_burstcount), // output, width = 3, .burstcount
.mst_bridge_to_sr_readdatavalid (mst_bridge_to_sr_readdatavalid), // input, width = 1, .readdatavalid
.mst_bridge_to_sr_beginbursttransfer (mst_bridge_to_sr_beginbursttransfer), // output, width = 1, .beginbursttransfer
.mst_bridge_to_sr_debugaccess (mst_bridge_to_sr_debugaccess), // output, width = 1, .debugaccess
.mst_bridge_to_sr_response (mst_bridge_to_sr_response), // input, width = 2, .response
.mst_bridge_to_sr_lock (mst_bridge_to_sr_lock), // output, width = 1, .lock
.mst_bridge_to_sr_writeresponsevalid (mst_bridge_to_sr_writeresponsevalid), // input, width = 1, .writeresponsevalid
.reset_n (reset_n) // input, width = 1, reset_n.reset_n
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_pcie_bram_7x.v
// Version : 1.3
// Description : single bram wrapper for the mb pcie block
// The bram A port is the write port
// the B port is the read port
//
//
//-----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_3_pcie_bram_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DOB_REG = 0, // 1 - use the output register;
// 0 - don't use the output register
parameter WIDTH = 0 // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
// 72 - uses RAMB36SDP
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = ((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ?
"WRITE_FIRST" : "NO_CHANGE";
localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6";
localparam BRAM_SIZE = "36Kb";
localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ?
((WIDTH <= 9) ? 1 :
(WIDTH > 9 && WIDTH <= 18) ? 2 :
(WIDTH > 18 && WIDTH <= 36) ? 4 :
(WIDTH > 36 && WIDTH <= 72) ? 8 :
(BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8;
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp
BRAM_SDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DO_REG (DOB_REG),
.READ_WIDTH (WIDTH),
.WRITE_WIDTH (WIDTH),
.WRITE_MODE (WRITE_MODE)
)
ramb36sdp(
.DO (rdata_o[WIDTH-1:0]),
.DI (wdata_i[WIDTH-1:0]),
.RDADDR (raddr_i[ADDR_MSB:0]),
.RDCLK (user_clk_i),
.RDEN (ren_i),
.REGCE (rce_i),
.RST (reset_i),
.WE ({WE_WIDTH{1'b1}}),
.WRADDR (waddr_i[ADDR_MSB:0]),
.WRCLK (user_clk_i),
.WREN (wen_i)
);
end // block: use_sdp
else if (WIDTH <= 36) begin : use_tdp
// use RAMB36's if the width is 4, 9, 18, or 36
BRAM_TDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (WIDTH),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (WIDTH),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.DOA (),
.DOB (rdata_o[WIDTH-1:0]),
.ADDRA (waddr_i[ADDR_MSB:0]),
.ADDRB (raddr_i[ADDR_MSB:0]),
.CLKA (user_clk_i),
.CLKB (user_clk_i),
.DIA (wdata_i[WIDTH-1:0]),
.DIB ({WIDTH{1'b0}}),
.ENA (wen_i),
.ENB (ren_i),
.REGCEA (1'b0),
.REGCEB (rce_i),
.RSTA (reset_i),
.RSTB (reset_i),
.WEA ({WE_WIDTH{1'b1}}),
.WEB ({WE_WIDTH{1'b0}})
);
end // block: use_tdp
endgenerate
endmodule // pcie_bram_7x
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2_BEHAVIORAL_V
`define SKY130_FD_SC_LS__AND2_BEHAVIORAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2_BEHAVIORAL_V |
module tx(output wire ALERT_TransmitSOP_MessageFailed,
output wire ALERT_TransmitSuccessful,
output wire MessageID_mismatch,
output wire SOP_mismatch,
output wire MessageID_SOP_match,
output wire [7:0] TRANSMIT_BYTE_COUNT,
output wire [7:0] TRANSMIT_HEADER_LOW,
output wire [7:0] TRANSMIT_HEADER_HIGH,
output wire [7:0] TRANSMIT_DATA_OBJECTS,
output wire Start_CRCReceiveTimer,
output wire Stop_CRCReceiverTimer,
output wire MessageIDCounter,
output wire MessageID,
input wire [2:0] TRANSMIT,
input wire PRL_Rx_Message_Discard,
input wire Hard_Reset_received,
input wire Cable_Reset_received,
input wire RetryCounter,
input wire CRCReceiveTimer_Timeout,
input wire GoodCRC_Response_from_PHY,
input wire Message_discarded_bus_Idle,
input wire [7:0] TX_BUF_HEADER_BYTE_1,
input wire [7:0] RX_BUF_HEADER_BYTE_1,
input wire [7:0] RX_BUF_FRAME_TYPE,
input wire CLK,
input wire RESET);
wire RetryCounter_bigger;
wire RetryCounter_smaller;
reg [7:0] CurrentState;
reg [7:0] NextState;
reg [8:0] CRCReceive_timer;
localparam Wait_for_Transmit_Request = 8'b00000001;
localparam Reset_RetryCounter = 8'b00000010;
localparam Construct_Message = 8'b00000100;
localparam Wait_for_PHY_response = 8'b00001000;
localparam Match_MessageID = 8'b00010000;
localparam Check_RetryCounter = 8'b00100000;
localparam Report_Failure = 8'b01000000;
localparam Report_Success = 8'b10000000;
localparam nRetryCounter = 2'b10; //definir el valor maximo
// Logica prox estado
always@( * )
begin
NextState = CurrentState;
case(CurrentState)
Wait_for_Transmit_Request:
begin
if(PRL_Rx_Message_Discard || Hard_Reset_received || Cable_Reset_received) begin NextState = Reset_RetryCounter; end
end
Reset_RetryCounter:
begin
NextState = Construct_Message;
end
Construct_Message:
begin
NextState = Wait_for_PHY_response;
end
Wait_for_PHY_response:
begin
if (GoodCRC_Response_from_PHY) NextState = Match_MessageID;
else if(Message_discarded_bus_Idle || CRCReceiveTimer_Timeout) NextState= Check_RetryCounter;
end
Match_MessageID:
begin
if(MessageID_mismatch || SOP_mismatch) NextState = Check_RetryCounter;
else if(MessageID_SOP_match) NextState = Report_Success;
end
Check_RetryCounter:
begin
if(RetryCounter_bigger) NextState = Report_Failure;
else if(RetryCounter_smaller) NextState = Construct_Message;
end
Report_Success:
begin
NextState = Wait_for_Transmit_Request;
end
Report_Failure:
begin
NextState = Wait_for_Transmit_Request;
end
endcase
// if (CurrentState==Reset_RetryCounter) RetryCounter=0;
//else if (CurrentState==Check_RetryCounter) RetryCounter = RetryCounter+1;
end
// Logica de salidas
assign TRANSMIT_BYTE_COUNT = CurrentState==0;
assign TRANSMIT_HEADER_LOW=0;
assign TRANSMIT_HEADER_HIGH=0;
assign TRANSMIT_DATA_OBJECTS=0;
assign Start_CRCReceiveTimer = CurrentState==Wait_for_PHY_response;
assign Stop_CRCReceiverTimer = CurrentState== Match_MessageID;
assign MessageIDCounter = CurrentState==Match_MessageID;
assign MessageID_mismatch = (CurrentState==Match_MessageID) && (TX_BUF_HEADER_BYTE_1 != RX_BUF_HEADER_BYTE_1);
assign SOP_mismatch = (CurrentState==Match_MessageID) && (TRANSMIT[2:0] != RX_BUF_FRAME_TYPE);
assign MessageID_SOP_match = !MessageID_mismatch && !SOP_mismatch;
assign RetryCounter_bigger = RetryCounter>=nRetryCounter && CurrentState==Check_RetryCounter;
assign RetryCounter_smaller = RetryCounter<nRetryCounter && CurrentState==Check_RetryCounter;
assign ALERT_TransmitSOP_MessageFailed= CurrentState==Report_Failure;
assign ALERT_TransmitSuccessful= CurrentState==Report_Success;
// Cambio de estado
always@(posedge CLK)
begin
if(RESET) CurrentState <= Wait_for_Transmit_Request;
else CurrentState <= NextState;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = numeric_limits<int>::max(); const long long LLINF = numeric_limits<long long>::max(); const unsigned long long ULLINF = numeric_limits<unsigned long long>::max(); const double PI = acos(-1.0); int sz = 1; vector<int> compressed; vector<pair<int, pair<int, int>>> queries; map<int, int> order; vector<int> t; vector<set<int>> vert; void build(int n) { while (sz < n) sz <<= 1; t.resize(sz + sz, 0); } void update(int i) { i += sz; if (vert[i - sz].size() == 0) t[i] = 0; else t[i] = *vert[i - sz].rbegin(); while ((i >> 1) > 0) { i >>= 1; t[i] = max(t[i + i], t[i + i + 1]); } } int query(int v, int tl, int tr, int l, int r) { if (l > r) return 0; if (tl == l && tr == r) return t[v]; int tm = (tl + tr) >> 1; return max(query(v + v, tl, tm, l, min(r, tm)), query(v + v + 1, tm + 1, tr, max(tm + 1, l), r)); } int getX(int v, int tl, int tr, int l, int y) { if (t[v] <= y) return INF; if (tr <= l) return INF; if (tl == tr) return tl; int mid = (tl + tr) >> 1; if (tl > l) { if (t[v + v] > y) return getX(v + v, tl, mid, l, y); else return getX(v + v + 1, mid + 1, tr, l, y); } return min(getX(v + v, tl, mid, l, y), getX(v + v + 1, mid + 1, tr, l, y)); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; queries.resize(n); set<int> d; for (int i = 0; i < n; i++) { string type; cin >> type; if (type == add ) queries[i].first = 0; else if (type == remove ) queries[i].first = 1; else queries[i].first = 2; cin >> queries[i].second.first >> queries[i].second.second; queries[i].second.first, queries[i].second.second; d.insert(queries[i].second.first); } for (auto k : d) { order[k] = compressed.size(); compressed.push_back(k); } build(compressed.size()); vert.resize(compressed.size()); for (auto q : queries) { if (q.first == 0) { vert[order[q.second.first]].insert(q.second.second); update(order[q.second.first]); } else if (q.first == 1) { vert[order[q.second.first]].erase(q.second.second); update(order[q.second.first]); } else { int ans = getX(1, 0, sz - 1, order[q.second.first], q.second.second); if (ans == INF) cout << -1 n ; else { int y = *vert[ans].upper_bound(q.second.second); cout << compressed[ans] << << y << n ; } } } return 0; } |
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This sample tests that the supply0 and supply1 nets take on
* the proper initial value.
*/
module test;
supply0 gnd;
supply1 vdd;
initial begin
#1;
if (gnd !== 0) begin
$display("FAILED -- gnd == %b", gnd);
$finish;
end
if (vdd !== 1) begin
$display("FAILED -- vdd == %b", vdd);
$finish;
end
$display("PASSED");
end
endmodule
|
module STRUCT_NEURAL_TEST;
reg [16:1]
inputA,
inputB,
c111,
c112,
c121,
c122,
c211,
c212,
c221,
c222,
b11,
b12,
b21,
b22;
wire [16:1]
out1,
out2;
STRUCT_NEURAL sn(
inputA,
inputB,
c111,
c112,
c121,
c122,
c211,
c212,
c221,
c222,
b11,
b12,
b21,
b22,
out1,
out2
);
parameter P0 = 16'h0000;
parameter P1 = 16'h0100;
initial begin
$dumpfile("neural_test.vcd");
$dumpvars(0,STRUCT_NEURAL_TEST);
$monitor (
"%t: A = %04x , B = %04x , %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x",
$time,
inputA,
inputB,
c111,
c112,
c121,
c122,
c211,
c212,
c221,
c222,
b11,
b12,
b21,
b22,
out1,
out2
);
b11=0;
b12=0;
b21=0;
b22=0;
inputA=P0; inputB=P0; c111=P0; c112=P0; c121=P0; c122=P0; c211=P0; c212=P0; c221=P0; c222=P0;
#1 inputA=P1; inputB=P1; c111=P1; c112=P1; c121=P1; c122=P1; c211=P1; c212=P1; c221=P1; c222=P1;
#1 inputA=P1; inputB=P1; c111=P0; c112=P0; c121=P1; c122=P1; c211=P1; c212=P1; c221=P1; c222=P1;
#1 inputA=P1; inputB=P1; c111=P0; c112=P0; c121=P1; c122=P1; c211=P1; c212=P0; c221=P1; c222=P0;
#1 inputA=P1; inputB=P1; c111=P1; c112=P1; c121=P0; c122=P0; c211=P1; c212=P1; c221=P1; c222=P1;
#1 inputA=P1; inputB=P1; c111=P0; c112=P0; c121=P0; c122=P0; c211=P1; c212=P1; c221=P1; c222=P1;
#1 inputA=P1; inputB=P1; c111=P1; c112=P1; c121=P1; c122=P1; c211=P0; c212=P0; c221=P1; c222=P1;
#1 inputA=P1; inputB=P1; c111=P1; c112=P1; c121=P1; c122=P1; c211=P0; c212=P0; c221=P0; c222=P0;
#1 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 1000000007; const int N = 105; int n, m, k, nl, d[N][N], ok; struct point { int x, y; point(){}; point(int x, int y) : x(x), y(y) {} }; string a[N]; vector<point> l[N * N]; int s[N * N], p[N * N]; void input() { cin >> n >> m >> k; getline(cin, a[0]); for (int i = 0; i < n; i++) { getline(cin, a[i]); } } int vx[] = {0, 1, 0, -1}; int vy[] = {-1, 0, 1, 0}; int check(int x, int y) { return x >= 0 && x < n && y >= 0 && y < m; } void dfs(int x, int y) { l[nl].push_back(point(x, y)); s[nl]++; d[x][y] = 1; for (int k = 0; k < 4; k++) { int u = x + vx[k]; int v = y + vy[k]; if (!check(u, v)) { ok = 0; continue; } if (a[u][v] != . || d[u][v]) continue; dfs(u, v); } } int cmp(int x, int y) { return s[x] < s[y]; } void solve() { for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i][j] == . && !d[i][j]) { l[nl].clear(); s[nl] = 0; p[nl] = nl; ok = 1; dfs(i, j); if (ok) nl++; } } } sort(p, p + nl, cmp); int ans = 0; for (int i = 0; i < nl - k; i++) { ans += s[p[i]]; for (int j = 0; j < l[p[i]].size(); j++) { int u = l[p[i]][j].x; int v = l[p[i]][j].y; a[u][v] = * ; } } cout << ans << endl; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cout << a[i][j]; } cout << endl; } } int main() { int test = 1; while (test--) { input(); solve(); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:35:55 11/19/2013
// Design Name:
// Module Name: sounds_bank
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sounds_bank (
input lrck,
input c_pad_sync,
input d_pad_sync,
input e_pad_sync,
input f_pad_sync,
input g_pad_sync,
input play,
output[15:0] c_data_out,
output[15:0] d_data_out,
output[15:0] e_data_out,
output[15:0] f_data_out,
output[15:0] g_data_out
);
wire[15:0] sine_c, sine_d, sine_e, sine_f, sine_g;
nco_c gen_c (
.clk(lrck), // input clk
.sine(sine_c) // output [15 : 0] sine
);
mux2x1 mux_c (
.selector(play & c_pad_sync),
.data(sine_c),
.out(c_data_out)
);
nco_d gen_d (
.clk(lrck), // input clk
.sine(sine_d) // output [15 : 0] sine
);
mux2x1 mux_d (
.selector(play & d_pad_sync),
.data(sine_d),
.out(d_data_out)
);
nco_e gen_e (
.clk(lrck), // input clk
.sine(sine_e) // output [15 : 0] sine
);
mux2x1 mux_e (
.selector(play & e_pad_sync),
.data(sine_e),
.out(e_data_out)
);
nco_f gen_f (
.clk(lrck), // input clk
.sine(sine_f) // output [15 : 0] sine
);
mux2x1 mux_f (
.selector(play & f_pad_sync),
.data(sine_f),
.out(f_data_out)
);
nco_g gen_g (
.clk(lrck), // input clk
.sine(sine_g) // output [15 : 0] sine
);
mux2x1 mux_g (
.selector(play & g_pad_sync),
.data(sine_g),
.out(g_data_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void rwFile() { freopen( INP.inp , r , stdin); freopen( OUT.out , w , stdout); } void solveC_VanyaAndScales() { long long w, m; cin >> w >> m; if (w == 2) { cout << YES ; return; } int able = 1; while (m) { long long tmp = m % w; m /= w; if (tmp == w - 1) { m++; continue; } if (tmp == 1 || tmp == 0) continue; able = 0; break; } if (able == 1) cout << YES ; else cout << NO ; } int main() { ios_base::sync_with_stdio(0); cin.tie(nullptr); cout.tie(nullptr); solveC_VanyaAndScales(); } |
`timescale 1 ns / 1 ps
module axis_bram_writer #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer BRAM_DATA_WIDTH = 32,
parameter integer BRAM_ADDR_WIDTH = 10
)
(
// System signals
input wire aclk,
input wire aresetn,
output wire [BRAM_ADDR_WIDTH-1:0] sts_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
output wire [BRAM_DATA_WIDTH-1:0] bram_porta_wrdata,
output wire [BRAM_DATA_WIDTH/8-1:0] bram_porta_we
);
reg [BRAM_ADDR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg int_enbl_reg, int_enbl_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_addr_reg <= {(BRAM_ADDR_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
end
else
begin
int_addr_reg <= int_addr_next;
int_enbl_reg <= int_enbl_next;
end
end
always @*
begin
int_addr_next = int_addr_reg;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg)
begin
int_enbl_next = 1'b1;
end
if(s_axis_tvalid & int_enbl_reg)
begin
int_addr_next = int_addr_reg + 1'b1;
end
end
assign sts_data = int_addr_reg;
assign s_axis_tready = int_enbl_reg;
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = int_addr_reg;
assign bram_porta_wrdata = s_axis_tdata;
assign bram_porta_we = {(BRAM_DATA_WIDTH/8){s_axis_tvalid & int_enbl_reg}};
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> std::pair<T, U> operator+(const std::pair<T, U>& l, const std::pair<T, U>& r) { return {l.first + r.first, l.second + r.second}; } typedef void (*callback_function)(void); const long long ZERO = 0LL; const long long INF64 = 1e18; const long long INF32 = 1e9; const long long MOD = 1e9 + 7; const long double PI = acos(-1.0L); const long double EPS = static_cast<long double>(1e-9); long long inv(long long a, long long b) { if (a != 1) { return b - (inv(b % a, a) * b) / a; } return 1; } inline long long Pow(long long a, long long k) { long long s = 1; for (; k; k >>= 1) { k& 1 ? s = 1LL * s * a % MOD : 0; a = 1LL * a * a % MOD; } return s; } const long long N = 1e6 + 7; void input() {} void output() {} void preprocess() {} void debug() { if (true) { } } void solve() { preprocess(); long long n; cin >> n; pair<long long, long long> a[n]; for (long long i = (0); i < (n); i++) { long long m; cin >> m; long long b[m]; for (long long i = (0); i < (m); i++) { cin >> b[i]; } a[i] = pair<long long, long long>(*max_element(b, b + m), m); } long long mx = (*max_element(a, a + n)).first; long long res = 0; for (long long i = (0); i < (n); i++) { res += (mx - a[i].first) * a[i].second; } cout << res << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(); { input(); solve(); output(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100000 + 10; struct node { int x, h; int num; int ans; }; node a[maxn]; int ans[maxn]; stack<int> s; int n; void init() { cin >> n; for (int i = 1; i <= n; i++) { a[i].num = i; cin >> a[i].x >> a[i].h; } } bool cmp1(const node &a, const node &b) { return a.x < b.x; } bool cmp2(const node &a, const node &b) { return a.num < b.num; } void solve() { s.push(n); a[n].ans = 1; for (int i = n - 1; i >= 1; i--) { int j = i; while (!s.empty() && a[i].x + a[i].h > a[s.top()].x) { j = s.top(); s.pop(); } s.push(i); if (j == i) a[i].ans = 1; else a[i].ans = j - i + a[j].ans; } sort(a + 1, a + 1 + n, cmp2); for (int i = 1; i < n; i++) cout << a[i].ans << ; cout << a[n].ans << endl; } int main() { init(); sort(a + 1, a + 1 + n, cmp1); solve(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_V |
// file: clock_divider.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1_____7.143______0.000______50.0______244.806____114.212
// CLK_OUT2____25.000______0.000______50.0______191.696____114.212
// CLK_OUT3___100.000______0.000______50.0______144.719____114.212
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clock_divider_clk_wiz
(// Clock in ports
input CLOCK_PLL,
// Clock out ports
output CLOCK_7_143,
output CLOCK_25,
output CLOCK_100,
// Status and control signals
input reset,
output locked
);
// Input buffering
//------------------------------------
IBUF clkin1_ibufg
(.O (CLOCK_PLL_clock_divider),
.I (CLOCK_PLL));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_clock_divider;
wire clkfbout_buf_clock_divider;
wire clkfboutb_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
PLLE2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (8),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (112),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (32),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DIVIDE (8),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (10.0))
plle2_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_clock_divider),
.CLKOUT0 (CLOCK_7_143_clock_divider),
.CLKOUT1 (CLOCK_25_clock_divider),
.CLKOUT2 (CLOCK_100_clock_divider),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_clock_divider),
.CLKIN1 (CLOCK_PLL_clock_divider),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (locked_int),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
assign locked = locked_int;
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_clock_divider),
.I (clkfbout_clock_divider));
BUFG clkout1_buf
(.O (CLOCK_7_143),
.I (CLOCK_7_143_clock_divider));
BUFG clkout2_buf
(.O (CLOCK_25),
.I (CLOCK_25_clock_divider));
BUFG clkout3_buf
(.O (CLOCK_100),
.I (CLOCK_100_clock_divider));
endmodule
|
`timescale 1 ns / 1 ps
module axis_decimator #
(
parameter integer AXIS_TDATA_WIDTH = 32
)
(
// System signals
input wire aclk,
input wire aresetn,
// I2S signals
inout wire [3:0] gpio_data,
// ALEX signals
input wire alex_flag,
input wire [3:0] alex_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
localparam I2S_DATA_WIDTH = AXIS_TDATA_WIDTH / 2;
localparam CNTR_WIDTH = 6;
reg [2:0] int_bclk_reg, int_lrclk_reg;
reg [1:0] int_data_reg;
reg [1:0] adc_case_reg, adc_case_next;
reg [CNTR_WIDTH-1:0] adc_cntr_reg, adc_cntr_next;
reg [I2S_DATA_WIDTH-1:0] adc_data_reg, adc_data_next;
reg [AXIS_TDATA_WIDTH-1:0] adc_tdata_reg, adc_tdata_next;
reg adc_tvalid_reg, adc_tvalid_next;
reg [1:0] dac_case_reg, dac_case_next;
reg [I2S_DATA_WIDTH-1:0] dac_data_reg, dac_data_next;
reg [AXIS_TDATA_WIDTH-1:0] dac_tdata_reg, dac_tdata_next;
wire i2s_bclk, i2s_lrclk, i2s_adc_data, i2s_dac_data;
wire not_alex_flag = ~alex_flag;
IOBUF buf_bclk (.O(i2s_bclk), .IO(gpio_data[0]), .I(alex_data[0]), .T(not_alex_flag));
IOBUF buf_adc_data (.O(i2s_adc_data), .IO(gpio_data[1]), .I(alex_data[1]), .T(not_alex_flag));
IOBUF buf_dac_data (.O(), .IO(gpio_data[2]), .I(alex_flag ? alex_data[2] : i2s_dac_data), .T(1'b0));
IOBUF buf_lrclk (.O(i2s_lrclk), .IO(gpio_data[3]), .I(alex_data[3]), .T(not_alex_flag));
always @(posedge aclk)
begin
if(~aresetn)
begin
int_bclk_reg <= 3'd0;
int_lrclk_reg <= 3'd0;
int_data_reg <= 2'd0;
adc_case_reg <= 2'd0;
adc_cntr_reg <= {(CNTR_WIDTH){1'b0}};
adc_data_reg <= {(I2S_DATA_WIDTH){1'b0}};
adc_tdata_reg <= {(AXIS_TDATA_WIDTH){1'b0}};
adc_tvalid_reg <= 1'b0;
dac_case_reg <= 2'd0;
dac_data_reg <= {(I2S_DATA_WIDTH){1'b0}};
dac_tdata_reg <= {(AXIS_TDATA_WIDTH){1'b0}};
end
else
begin
int_bclk_reg <= {int_bclk_reg[1:0], i2s_bclk};
int_lrclk_reg <= {int_lrclk_reg[1:0], i2s_lrclk};
int_data_reg <= {int_data_reg[0], i2s_adc_data};
adc_case_reg <= adc_case_next;
adc_cntr_reg <= adc_cntr_next;
adc_data_reg <= adc_data_next;
adc_tdata_reg <= adc_tdata_next;
adc_tvalid_reg <= adc_tvalid_next;
dac_case_reg <= dac_case_next;
dac_data_reg <= dac_data_next;
dac_tdata_reg <= dac_tdata_next;
end
end
assign int_bclk_posedge = int_bclk_reg[1] & ~int_bclk_reg[2];
assign int_bclk_negedge = ~int_bclk_reg[1] & int_bclk_reg[2];
assign int_lrclk_negedge = ~int_lrclk_reg[1] & int_lrclk_reg[2];
always @*
begin
adc_case_next = adc_case_reg;
adc_cntr_next = adc_cntr_reg;
adc_data_next = adc_data_reg;
adc_tdata_next = adc_tdata_reg;
adc_tvalid_next = adc_tvalid_reg;
if(int_bclk_posedge & (adc_cntr_reg < I2S_DATA_WIDTH))
begin
adc_data_next = {adc_data_reg[I2S_DATA_WIDTH-2:0], int_data_reg[1]};
adc_cntr_next = adc_cntr_reg + 1'b1;
end
if(m_axis_tready & adc_tvalid_reg)
begin
adc_tvalid_next = 1'b0;
end
case(adc_case_reg)
2'd0:
begin
if(int_lrclk_reg[1] ^ int_lrclk_reg[2])
begin
adc_case_next = 2'd1;
end
end
2'd1:
begin
if(int_bclk_posedge)
begin
adc_cntr_next = {(CNTR_WIDTH){1'b0}};
adc_case_next = 2'd2;
end
end
2'd2:
begin
if(int_bclk_posedge)
begin
adc_tvalid_next = ~int_lrclk_reg[1];
adc_tdata_next = {adc_tdata_reg[I2S_DATA_WIDTH-1:0], adc_data_reg};
adc_case_next = 2'd0;
end
end
endcase
end
always @*
begin
dac_case_next = dac_case_reg;
dac_data_next = dac_data_reg;
dac_tdata_next = dac_tdata_reg;
if(int_bclk_negedge)
begin
dac_data_next = {dac_data_reg[I2S_DATA_WIDTH-2:0], 1'b0};
end
if(int_lrclk_negedge)
begin
dac_tdata_next = s_axis_tvalid ? s_axis_tdata : {(AXIS_TDATA_WIDTH){1'b0}};
end
case(dac_case_reg)
2'd0:
begin
if(int_lrclk_reg[1] ^ int_lrclk_reg[2])
begin
dac_case_next = 2'd1;
end
end
2'd1:
begin
if(int_bclk_posedge)
begin
dac_case_next = 2'd2;
end
end
2'd2:
begin
if(int_bclk_negedge)
begin
dac_data_next = int_lrclk_reg[1] ? dac_tdata_reg[I2S_DATA_WIDTH-1:0] : dac_tdata_reg[AXIS_TDATA_WIDTH-1:I2S_DATA_WIDTH];
dac_case_next = 2'd0;
end
end
endcase
end
assign i2s_dac_data = dac_data_reg[I2S_DATA_WIDTH-1];
assign s_axis_tready = int_lrclk_negedge;
assign m_axis_tdata = adc_tdata_reg;
assign m_axis_tvalid = adc_tvalid_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long ccw(pair<int, int> a, pair<int, int> b, pair<int, int> c) { int dx1 = b.first - a.first; int dy1 = b.second - a.second; int dx2 = c.first - a.first; int dy2 = c.second - a.second; return 1ll * dx1 * dy2 - 1ll * dy1 * dx2; } long long dist(pair<int, int> a, pair<int, int> b) { int dx = b.first - a.first; int dy = b.second - a.second; return 1ll * dx * dx + 1ll * dy * dy; } pair<int, int> a[5005]; int n; vector<pair<int, int> > hull; long long mxarea = 0; int r1, r2, r3; void solve() { for (int i = 0; i + 2 < hull.size(); i++) { int p2 = i + 1, p3 = i + 2; while (p2 + 1 < hull.size()) { p3 = max(p3, p2 + 1); while (p3 + 1 < hull.size() && ccw(hull[i], hull[p2], hull[p3]) < ccw(hull[i], hull[p2], hull[p3 + 1])) { p3++; } if (mxarea < ccw(hull[i], hull[p2], hull[p3])) { mxarea = ccw(hull[i], hull[p2], hull[p3]); tie(r1, r2, r3) = make_tuple(i, p2, p3); } p2++; } } int x1 = hull[r1].first + hull[r2].first - hull[r3].first; int x2 = hull[r2].first + hull[r3].first - hull[r1].first; int x3 = hull[r3].first + hull[r1].first - hull[r2].first; int y1 = hull[r1].second + hull[r2].second - hull[r3].second; int y2 = hull[r2].second + hull[r3].second - hull[r1].second; int y3 = hull[r3].second + hull[r1].second - hull[r2].second; printf( %d %d n%d %d n%d %d , x1, y1, x2, y2, x3, y3); } int main() { long long x; cin >> n >> x; for (int i = 0; i < n; i++) { cin >> a[i].first >> a[i].second; } swap(a[0], *min_element(a, a + n)); sort(a + 1, a + n, [&](const pair<int, int> &aa, const pair<int, int> &bb) { long long t = ccw(a[0], aa, bb); if (t != 0) return t > 0; return dist(a[0], aa) < dist(a[0], bb); }); for (int i = 0; i < n; i++) { while (hull.size() >= 2 && ccw(hull[hull.size() - 2], hull.back(), a[i]) <= 0) { hull.pop_back(); } hull.push_back(a[i]); } solve(); } |
#include <bits/stdc++.h> using namespace std; using ll = long long; bool judge(string& s, string& t) { auto f = [](string& x, vector<int>& cnt) { ll res = 0; for (char c : x) { int v = c - a ; for (int i = v + 1; i < 26; i++) res += cnt[i]; cnt[v]++; } return res; }; vector<int> vecS(26); vector<int> vecT(26); int nums = f(s, vecS), numt = f(t, vecT); return (nums % 2 == numt % 2 || *max_element(vecS.begin(), vecS.end()) >= 2) && vecS == vecT; } int main() { int q; cin >> q; while (q--) { int n; cin >> n; string s, t; cin >> s >> t; cout << (judge(s, t) ? YES : NO ) << endl; } return 0; } |
#include <bits/stdc++.h> const int inf = 1 << 30; const long long INF = 1ll << 61; using namespace std; const int MOD = 1000000; int n; int nnum[500000 + 55]; int vis[1000000 + 55]; int flag[1000000 + 55]; vector<int> G; void init() { memset(flag, 0, sizeof(flag)); memset(nnum, 0, sizeof(nnum)); memset(vis, 0, sizeof(vis)); G.clear(); } bool input() { while (cin >> n) { for (int i = 0; i < n; i++) { scanf( %d , &nnum[i]); vis[nnum[i]]++; } return false; } return true; } void cal() { int cnt = 0; for (int i = 0; i < n; i++) { if (vis[nnum[i]] && !vis[MOD - nnum[i] + 1]) { flag[MOD - nnum[i] + 1]++; cnt++; } } for (int i = 1; i <= MOD && cnt < n; i++) { if (!vis[i] && !vis[MOD - i + 1]) { flag[i] = 1; cnt++; flag[MOD - i + 1] = 1; cnt++; } } cout << cnt << endl; for (int i = 1; i <= MOD; i++) if (flag[i]) printf( %d , i); puts( ); } void output() {} int main() { while (true) { init(); if (input()) return 0; cal(); output(); } return 0; } |
#include <bits/stdc++.h> using namespace std; double n, m, k, r; double f(int x, int y) { x++; y++; return (min(n + 1, x + r) - max((double)x, r)) * (min(m + 1, y + r) - max((double)y, r)); } int main() { cin >> n >> m >> r >> k; double ans = 0; double nbpos = (n - r + 1) * (m - r + 1); int tot = 0; priority_queue<pair<double, pair<int, int> > > q; pair<double, pair<int, int> > cur; q.push(make_pair(f(n / 2, m / 2), make_pair(n / 2, m / 2))); set<pair<int, int> > done; done.insert(make_pair(n / 2, m / 2)); pair<int, int> pos; while (tot < k) { cur = q.top(); pos = cur.second; q.pop(); ans += cur.first; if (pos.first - 1 >= 0 && done.find(make_pair(pos.first - 1, pos.second)) == done.end()) { q.push(make_pair(f(pos.first - 1, pos.second), make_pair(pos.first - 1, pos.second))); done.insert(make_pair(pos.first - 1, pos.second)); } if (pos.first + 1 < n && done.find(make_pair(pos.first + 1, pos.second)) == done.end()) { q.push(make_pair(f(pos.first + 1, pos.second), make_pair(pos.first + 1, pos.second))); done.insert(make_pair(pos.first + 1, pos.second)); } if (pos.second - 1 >= 0 && done.find(make_pair(pos.first, pos.second - 1)) == done.end()) { q.push(make_pair(f(pos.first, pos.second - 1), make_pair(pos.first, pos.second - 1))); done.insert(make_pair(pos.first, pos.second - 1)); } if (pos.second + 1 < m && done.find(make_pair(pos.first, pos.second + 1)) == done.end()) { q.push(make_pair(f(pos.first, pos.second + 1), make_pair(pos.first, pos.second + 1))); done.insert(make_pair(pos.first, pos.second + 1)); } tot++; } cout << setprecision(11) << ans / nbpos << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, count = 0, i, flag = 1; cin >> n; char s[n + 1], c; cin >> s; int l = 0, r = 0; l++; for (i = 1; i < n; i++) { c = s[i]; if (c == s[0]) l++; else r++; if (r > l && flag == 1) { flag = 0; count++; } if (r < l && flag == 0) { flag = 1; count++; } } cout << count << endl; return 0; } |
`timescale 1ns/1ps
//changed to synchrounous reset
module y86_seq(
input clk,
input rst,
output [31:0] bus_A,
input [31:0] bus_in,
output [31:0] bus_out,
output bus_WE, bus_RE,
output [7:0] current_opcode);
// global control
reg [5:1] full;
wire [4:0] ue={ full[4:1], full[5] };
always @(posedge clk) begin
if(rst)
full<='b10000;
else
full<={ ue[4], ue[3], ue[2], ue[1], ue[0] };
end
// stage 1 IF
reg [31:0] IR;
always @(posedge clk)
if(ue[0]) IR<=bus_in;
// stage 2 ID
reg [31:0] IP, A, B;
wire [31:0] Aop, Bop;
wire [7:0] opcode=IR[7:0];
wire [1:0] mod=IR[15:14];
reg ZF;
wire load=opcode=='h8b && mod==1;
wire move=opcode=='h89 && mod==3;
wire store=opcode=='h89 && mod==1;
wire memory=load || store;
wire add=opcode=='h01;
wire sub=opcode=='h29;
wire halt=opcode=='hf4;
wire aluop=add || sub;
wire jnez=opcode=='h75;
wire [4:0] RD=IR[10:8];
wire [4:0] RS=IR[13:11];
wire [4:0] Aad=memory?6:RD,
Bad=RS;
wire [31:0] distance={ { 24 { IR[15] } }, IR[15:8] };
wire [31:0] displacement={ { 24 { IR[23] } }, IR[23:16] };
wire btaken=jnez && !ZF;
wire [1:0] length=memory ?3:
(aluop || move || jnez)?2:
1;
always @(posedge clk)
if(rst)
IP<=0;
else if(ue[1]) begin
A<=Aop;
B<=Bop;
if(!halt)
begin
IP<=IP+length+(btaken?distance:0);
end
else
begin
$finish;
end
end
// stage 3 EX
reg [31:0] MAR, MDRw, C;
wire [31:0] ALU_op2=memory?displacement:sub?~B:B;
wire [31:0] ALUout=A+ALU_op2+sub;
always @(posedge clk)
if(rst)
ZF=0;
else if(ue[2]) begin
MAR<=ALUout;
C<=move?B:ALUout;
MDRw<=B;
if(aluop) ZF<=(ALUout==0);
end
// stage 4 MEM
reg [31:0] MDRr;
always @(posedge clk)
if(ue[3] && load) MDRr<=bus_in;
assign bus_A=ue[3]?MAR:ue[0]?IP:0;
assign bus_RE=ue[0] || (ue[3] && load);
// stage 5 WB
reg [31:0] R[7:0];
assign Aop=R[Aad];
assign Bop=R[Bad];
assign bus_WE=ue[3] && store;
assign bus_out=MDRw;
always @(posedge clk)
if(rst) begin
R[00]<=0; R[01]<=0; R[02]<=0; R[03]<=0; R[04]<=0; R[05]<=0; R[06]<=0; R[07]<=0;
end
else if(ue[4])
if(aluop || move || load)
if(load)//rausgezogen
R[RS]<=MDRr;
else
R[RD]<=C;
assign current_opcode = opcode;
// ... and now for something completely different.
// synthesis translate_off
wire [31:0] eax = R[0];
wire [31:0] ecx = R[1];
wire [31:0] edx = R[2];
wire [31:0] ebx = R[3];
wire [31:0] esp = R[4];
wire [31:0] ebp = R[5];
wire [31:0] esi = R[6];
wire [31:0] edi = R[7];
wire [7:0] regs = IR[15:8];
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void read(T &x) { x = 0; char c = getchar(); int f = 1; while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } x *= f; } template <class T> inline void umin(T &x, T y) { x = x < y ? x : y; } template <class T> inline void umax(T &x, T y) { x = x > y ? x : y; } inline unsigned int R() { static unsigned int seed = 416; return seed ^= seed >> 5, seed ^= seed << 17, seed ^= seed >> 13; } const int N = 20200; int a[N], n, m; vector<int> b[N]; int main() { read(n); read(m); while (m--) { int x, y; read(x); read(y); int d = y >= x ? y - x : y - x + n; b[x].push_back(d); } for (register int i = (1); i <= (n); i++) sort(b[i].begin(), b[i].end()); for (register int i = (1); i <= (n); i++) if (((int)b[i].size())) a[i] = b[i][0] + n * (((int)b[i].size()) - 1); else a[i] = -1e9; for (register int i = (1); i <= (n); i++) { int res = 0; for (int j = i, t = 0; t < n; t++, j = j + 1 <= n ? j + 1 : 1) umax(res, t + a[j]); printf( %d , res); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d; cin >> a >> b >> c >> d; if (d > 2 * c || 2 * d < c || d >= b) { printf( -1 n ); return 0; } int tmp = max(c, d); cout << max(d * 2 + 2, a) << endl; cout << max(d * 2 + 1, b) << endl; cout << tmp << endl; } |
#include <bits/stdc++.h> using namespace std; struct Aho { Aho *son[26]; Aho *fail; int cntstr, faildp; Aho() { for (int i = 0; i < 26; ++i) son[i] = NULL; fail = NULL; cntstr = 0; faildp = -1; } }; void insert(Aho *x, int i, const string &str) { if (i < str.size()) { if (x->son[str[i] - a ] == NULL) { x->son[str[i] - a ] = new Aho(); } insert(x->son[str[i] - a ], i + 1, str); } else { x->cntstr++; } } void calcFailEdges(Aho *root) { deque<Aho *> q; root->fail = root; q.push_back(root); while (!q.empty()) { Aho *x = q.front(); q.pop_front(); for (int i = 0; i < 26; ++i) { if (x->son[i] != NULL) { q.push_back(x->son[i]); Aho *pnt = x->fail; if (x == root) x->son[i]->fail = root; else { while (pnt != root && pnt->son[i] == NULL) { pnt = pnt->fail; } if (pnt->son[i] != NULL) x->son[i]->fail = pnt->son[i]; else x->son[i]->fail = root; } } } } } int getDp(Aho *t) { if (t->faildp == -1) { t->faildp = t->cntstr; t->faildp += getDp(t->fail); } return t->faildp; } const int MAX_N = 200000; Aho *state[1 + MAX_N]; Aho *advance(Aho *t, char ch) { while (t->fail != t && t->son[ch - a ] == NULL) t = t->fail; if (t->son[ch - a ] == NULL) return t; return t->son[ch - a ]; } Aho *state1[MAX_N], *state2[MAX_N]; void doStuff(int n, Aho **state, const string &str, const vector<string> &vec) { Aho *T = new Aho(); for (int i = 0; i < n; ++i) insert(T, 0, vec[i]); T->faildp = T->cntstr; calcFailEdges(T); Aho *pnt = T; for (int i = 1; i <= str.size(); ++i) { pnt = advance(pnt, str[i - 1]); state[i] = pnt; } } int main() { int n; string str; cin >> str >> n; vector<string> vec; for (int i = 0; i < n; ++i) { string p; cin >> p; vec.push_back(p); } doStuff(n, state1, str, vec); for (int i = 0; i < n; ++i) reverse(vec[i].begin(), vec[i].end()); reverse(str.begin(), str.end()); doStuff(n, state2, str, vec); long long rez = 0LL; for (int i = 1; i < str.size(); ++i) rez = (long long)getDp(state1[i]) * getDp(state2[str.size() - i]) + rez; printf( %lld , rez); return 0; } |
#include <bits/stdc++.h> using namespace std; long long parse(string s) { long long k = 1, ret = 0; for (int i = 0; i < s.size(); i++) ret += k * (long long)(s[s.size() - i - 1] - 0 ), k *= 4; return ret; } string change(string s) { string ret = s; for (int i = 0; i < ret.size(); i++) { if (ret[i] == 1 ) ret[i] = 2 ; else if (ret[i] == 2 ) ret[i] = 3 ; else if (ret[i] == 3 ) ret[i] = 1 ; } return ret; } int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { long long n; cin >> n; long long idx = (n + 2) / 3, m = n % 3; long long k = 0, sum = 0; while (sum < idx) sum += (1ll << (2 * k)), k++; k--; long long buf = (1ll << (2 * k)), c = sum - buf + 1; string ans = 1 ; for (int i = k - 1; i >= 0; i--) { long long div = (1ll << (2 * i)); long long d = (idx - c) / div; ans += (char)( 0 + d); c += div * d; } long long f = parse(ans); long long s = parse(change(ans)); if (m == 1) cout << f << n ; else if (m == 2) cout << s << n ; else cout << (f ^ s) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; void dbvar() { cerr << ] << endl; } template <class H, class... T> void dbvar(H h, T... t) { cerr << to_string(h); if (sizeof...(t)) cerr << , ; dbvar(t...); } const int INF = (int)(1e9); const long long int INFL = (long long int)(1e18); const long double pi = acos(-1.0); const int dx[4] = {-1, 0, 1, 0}; const int dy[4] = {0, 1, 0, -1}; long long int power(long long int n, long long int m) { if (m == 0) return 1; long long int val = power(n, m / 2); if (m % 2 == 0) return (val * val); else return ((val * val) * n); } long long int powermod(long long int n, long long int m, long long int _MOD) { if (m == 0) return 1; long long int val = powermod(n, m / 2, _MOD); val %= _MOD; if (m % 2 == 0) return (val * val) % _MOD; else return (((val * val) % _MOD) * n) % _MOD; } const int mxN = 2e5 + 100; vector<int> tree[mxN]; int depth[mxN], subtree[mxN], ans[mxN]; void dfs(int v, int p) { depth[v] = depth[p] + 1; subtree[v] = 1; for (auto x : tree[v]) { if (x != p) { dfs(x, v); subtree[v] += subtree[x]; } } ans[v] = subtree[v] - depth[v]; } void solve() { int n, k; cin >> n >> k; for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; tree[x].push_back(y); tree[y].push_back(x); } depth[0] = 0; dfs(1, 0); sort(ans + 1, ans + n + 1, greater<int>()); long long int res = 0; for (int i = 1; i <= n - k; i++) res += ans[i]; cout << res << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); int t = 1; for (int i = 1; i <= t; i++) { solve(); } return 0; } |
/* Note : helluva implementation. Link : Boka hoye gelum... */ #include bits/stdc++.h #define sp << #define el << n #define S second #define F first #define pb push_back #define all(ar) ar.begin(),ar.end() #define pii pair<ll,ll> using namespace std; using ll = long long; using ld = long double; const ll mod = 1000000007; const ll oo = 3372036000000000; const ll si = 300005; vector<pair<pii,char>> vec; ll ans[si],in[si],n,m; char dir[si]; bool don[si]; void sm_dir(char q){ stack<pii> od,ev; for(ll i = q == L ? 0 : n - 1; i < n && i >= 0; q == L ? i++ : i--){ if(don[vec[i].F.S] || vec[i].S != q) continue; pii da,cur = vec[i].F; if(cur.F & 1){ if(od.empty()){ od.push(cur); continue; } da = od.top(); od.pop(); }else{ if(ev.empty()){ ev.push(cur); continue; } da = ev.top(); ev.pop(); } ll tim = abs(da.F - cur.F)/2; if(q == R ) tim += m - da.F; else tim += da.F; don[da.S] = don[cur.S] = 1; ans[da.S] = ans[cur.S] = tim; } } void baki(){ stack<pii> od,ev; for(ll i = 0; i < n; i++){ if(don[vec[i].F.S]) continue; if(vec[i].S == L ){ if(vec[i].F.F&1) od.push(vec[i].F); else ev.push(vec[i].F); } } for(ll i = n-1; i >= 0; i--){ if(don[vec[i].F.S]) continue; if(vec[i].S == R ){ pii cur = vec[i].F,da; if(cur.F & 1){ if(od.empty()) continue; da = od.top(); od.pop(); }else{ if(ev.empty()) continue; da = ev.top(); ev.pop(); } ll tim = 0; if(m - cur.F > da.F){ ll wae = m - cur.F,nda = (wae - da.F); // sure? ll dis = (m - nda)/2; tim += wae; tim += dis; }else{ ll wae = da.F, nda = ((2 * m) - (cur.F + wae))/2; tim += (wae + nda); } ans[cur.S] = ans[da.S] = tim; } } } signed main(){ ios_base::sync_with_stdio(false); cin.tie(NULL); //* #ifndef ONLINE_JUDGE freopen( input.txt , r ,stdin); freopen( output.txt , w ,stdout); #endif //*/ ll t; cin>>t; while(t--){ vec.clear(); memset(ans,-1,sizeof(ans)); memset(don,0,sizeof(don)); cin>>n>>m; for(ll i = 0; i < n; i++) cin>>in[i]; for(ll i = 0; i < n; i++) cin>>dir[i]; for(ll i = 0; i < n; i++){ ll x = in[i]; char d = dir[i]; vec.pb({{x,i},d}); } sort(all(vec)); stack<pii> ev,od; for(ll i = 0; i < n; i++){ if(vec[i].S == R ){ if(vec[i].F.F & 1) od.push(vec[i].F); else ev.push(vec[i].F); }else{ pii da,cur = vec[i].F; if(vec[i].F.F & 1){ if(od.empty()) continue; da = od.top(); od.pop(); }else{ if(ev.empty()) continue; da = ev.top(); ev.pop(); } ll tim = (cur.F - da.F)/2; don[cur.S] = don[da.S] = 1; ans[cur.S] = ans[da.S] = tim; } } sm_dir( L ); sm_dir( R ); baki(); for(ll i = 0; i < n; i++) cout<<ans[i] sp; cout el; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__SDFXTP_PP_BLACKBOX_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; inline int init() { int now = 0, ju = 1; char c; bool flag = false; while (1) { c = getchar(); if (c == - ) ju = -1; else if (c >= 0 && c <= 9 ) { now = now * 10 + c - 0 ; flag = true; } else if (flag) return now * ju; } } inline long long llinit() { long long now = 0, ju = 1; char c; bool flag = false; while (1) { c = getchar(); if (c == - ) ju = -1; else if (c >= 0 && c <= 9 ) { now = now * 10 + c - 0 ; flag = true; } else if (flag) return now * ju; } } char str[200005]; long long mod; long long fastpow(long long base, long long power) { long long ret = 1; for (; power; power >>= 1) { if (power & 1) { ret = (ret * base) % mod; } base = (base * base) % mod; } return ret; } int main() { long long ans = 0x7fffffffffffll, nowans = 0; scanf( %s , str + 1); mod = llinit(); int n = strlen(str + 1); for (int i = 1; i <= n; i++) { nowans *= 10; nowans %= mod; nowans += (str[i] - 0 ); nowans %= mod; } ans = min(ans, nowans); for (int i = 1; i <= n - 1; i++) { nowans -= (1LL * (str[i] - 0 ) * fastpow(10, n - 1)); while (nowans < 0) nowans += mod; nowans %= mod; nowans *= 10; nowans %= mod; nowans += (str[i] - 0 ); nowans %= mod; if (str[i + 1] != 0 ) { ans = min(ans, nowans); } } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const int MOD = 1e9 + 7; const int N = 0, BAR = 1e6, LIM = 5e6; int x, y, n; int main() { scanf( %d , &n); int xa = inf, xb = -inf, ya = inf, yb = -inf; while (n--) { scanf( %d%d , &x, &y); x += BAR, y += BAR; xa = min(xa, x - y - 1), xb = max(xb, x + y + 1); ya = min(ya, x - (LIM - y + 1)), yb = max(yb, x + (LIM - y + 1)); } int ans = 0; int rya = (LIM - (yb - ya) / 2); ans += (yb - ya) % 2; int ryb = (xb - xa) / 2; ans += (xb - xa) % 2; ans += 2 * (ryb - rya); cout << ans; } |
#include <bits/stdc++.h> using namespace std; vector<vector<int>> tr; int n; int mx_bits = 40; int ind = 0; long long xor_sum = 0; long long ans; vector<long long> v; void insert_tr(long long num) { int node = 0; for (int i = (int)mx_bits; i >= (int)0; --i) { bool bit = ((num >> i) & 1) > 0; if (tr[node][bit] == -1) { tr.push_back(vector<int>(2, -1)); ++ind; tr[node][bit] = ind; } node = tr[node][bit]; } } long long query_tr(long long num) { long long ret = 0; int node = 0; long long val = 1; for (int i = (int)mx_bits; i >= (int)0; --i) { bool bit = ((num >> i) & 1) > 0; if (tr[node][1 - bit] != -1) { ret += val << i; node = tr[node][1 - bit]; } else node = tr[node][bit]; } return ret; } void solve() { ans = xor_sum; long long cur = 0; insert_tr(cur); for (int i = (int)0; i < (int)n; ++i) { cur ^= v[i]; insert_tr(cur); long long ret = query_tr(xor_sum ^ cur); ans = max(ans, ret); } cout << ans; } int main() { ios_base::sync_with_stdio(false); tr.push_back(vector<int>(2, -1)); cin >> n; v.resize(n); for (int i = (int)0; i < (int)n; ++i) { cin >> v[i]; xor_sum = xor_sum ^ v[i]; } solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_S_TB_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_S_TB_V
/**
* udp_dff$PR_pp$PKG$s: Positive edge triggered D flip-flop with
* active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dff_pr_pp_pkg_s.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg SLEEP_B;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
RESET = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 RESET = 1'b0;
#80 SLEEP_B = 1'b0;
#100 VGND = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 KAPWR = 1'b1;
#180 RESET = 1'b1;
#200 SLEEP_B = 1'b1;
#220 VGND = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 KAPWR = 1'b0;
#300 RESET = 1'b0;
#320 SLEEP_B = 1'b0;
#340 VGND = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VGND = 1'b1;
#420 SLEEP_B = 1'b1;
#440 RESET = 1'b1;
#460 KAPWR = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VGND = 1'bx;
#540 SLEEP_B = 1'bx;
#560 RESET = 1'bx;
#580 KAPWR = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hs__udp_dff$PR_pp$PKG$s dut (.D(D), .RESET(RESET), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_S_TB_V
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_sq_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 11,
parameter P_FIFO_DEPTH_WIDTH = 2
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 2;
localparam LP_ADDR_TOTAL_WITDH = 10;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
`define SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
/**
* lpflow_decapkapwr: Decoupling capacitance filler on keep-alive
* rail.
*
* Verilog wrapper for lpflow_decapkapwr with size of 3 units
* (invalid?).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_decapkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr_3 (
VPWR ,
KAPWR,
VGND ,
VPB ,
VNB
);
input VPWR ;
input KAPWR;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_decapkapwr base (
.VPWR(VPWR),
.KAPWR(KAPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_decapkapwr_3 ();
// Voltage supply signals
supply1 VPWR ;
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_decapkapwr base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_DECAPKAPWR_3_V
|
#include <bits/stdc++.h> using namespace std; const long long Size = 501; const long long mod = 1e9 + 7; long long a[Size], num[Size]; bool vis[Size]; long long f[Size], d[Size]; long long dp[Size][Size]; inline long long min(long long a, long long b) { return a < b ? a : b; } inline long long max(long long a, long long b) { return a > b ? a : b; } long long fastpow(long long b, long long p, long long k) { long long ans = 1; while (p) { if (p & 1) ans = ans * b % k; b = b * b % k; p >>= 1; } return ans; } void init() { f[0] = 1; for (long long i = 1; i <= 300; i++) f[i] = f[i - 1] * i % mod; d[300] = fastpow(f[300], mod - 2, mod); for (long long i = 299; i >= 0; i--) d[i] = d[i + 1] * (i + 1) % mod; } long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = 10 * x + ch - 0 ; ch = getchar(); } return x * f; } long long C(long long a, long long b) { if (a < 0 || b < 0 || a < b) return 0; if (!b || a == b) return 1; return (f[a] * d[b] % mod) * d[a - b] % mod; } int main() { init(); C(2, 1); long long n = read(), size = 0; for (long long i = 1; i <= n; i++) a[i] = read(); for (long long i = 1; i <= n; i++) { if (!vis[i]) { size++; for (long long j = i; j <= n; j++) { if (sqrt(a[i] * a[j]) == (long long)sqrt(a[i] * a[j])) { vis[j] = true; num[size]++; } } } } long long sum = num[1] - 1; dp[1][sum] = 1; for (long long i = 2; i <= size; sum += num[i++]) { for (long long j = 0; j <= sum; j++) { if (!dp[i - 1][j]) continue; for (long long k = 0; k <= num[i]; k++) { long long tmp = min(j, k + 1), temp; for (long long l = 0; l <= tmp; l++) { temp = dp[i - 1][j] * C(num[i] - 1, k) % mod * C(j, l) % mod * C(sum + 2 - j, k - l + 1) % mod; dp[i][j + num[i] - 1 - k - l] += temp; dp[i][j + num[i] - 1 - k - l] %= mod; } } } } long long ans = dp[size][0]; for (long long i = 1; i <= size; i++) ans = ans * f[num[i]] % mod; printf( %I64d , ans); return 0; } |
#include <bits/stdc++.h> int m, n, s; int main() { scanf( %d%d , &n, &m); int ans = 0; for (int i = 0; i <= 40; i++) for (int j = 0; j <= 40; j++) { if (i * i + j == n && j * j + i == m) ans++; } printf( %d n , ans); } |
module DramReaderBuf(
input fclk,
input rst_n,
//AXI port
output M2S_AXI_ACLK,
//
output reg M2S_AXI_ARVALID,
input M2S_AXI_ARREADY,
output reg [31:0] M2S_AXI_ARADDR,
output [1:0] M2S_AXI_ARBURST,
output [3:0] M2S_AXI_ARLEN,
output [1:0] M2S_AXI_ARSIZE,
//
input M2S_AXI_RVALID,
output M2S_AXI_RREADY,
input M2S_AXI_RLAST,
input [63:0] M2S_AXI_RDATA,
//
input [1:0] M2S_AXI_RRESP,
//Control config
input rd_frame_valid,
output reg rd_frame_ready,
input [31:0] rd_FRAME_BYTES,
input [31:0] rd_BUF_ADDR,
output [1:0] debug_astate,
//RAM port
input dout_ready,
output dout_valid,
output [63:0] dout
);
assign M2S_AXI_ACLK = fclk;
assign M2S_AXI_ARLEN = 4'b1111;
assign M2S_AXI_ARSIZE = 2'b11;
assign M2S_AXI_ARBURST = 2'b01;
wire dramout_burst_ready;
wire dramout_ready;
wire dramout_valid;
wire [63:0] dramout_data;
reg [31:0] BUF_ADDR;
reg [31:0] FRAME_BYTES;
`REG(fclk, BUF_ADDR, 0, rd_frame_valid && rd_frame_ready ? rd_BUF_ADDR : BUF_ADDR)
`REG(fclk, FRAME_BYTES, 0, rd_frame_valid && rd_frame_ready ? rd_FRAME_BYTES : FRAME_BYTES)
wire frame_done;
assign frame_done = (M2S_AXI_ARADDR + 128)==(BUF_ADDR+FRAME_BYTES);
localparam A_IDLE = 0, A_FRAME_IDLE = 1, A_FRAME_WAIT=2;
//ADDR logic
reg [1:0] a_state;
//wire [1:0] debug_astate;
assign debug_astate = a_state;
always @(posedge fclk or negedge rst_n) begin
if (!rst_n) begin
a_state <= A_IDLE;
M2S_AXI_ARADDR <= 0;
M2S_AXI_ARVALID <= 0;
rd_frame_ready <= 0;
end
else begin
M2S_AXI_ARVALID <= 0;
rd_frame_ready <= 0;
case(a_state)
A_IDLE : begin
rd_frame_ready <= 1;
if (rd_frame_valid) begin
M2S_AXI_ARADDR <= rd_BUF_ADDR;
a_state <= A_FRAME_IDLE;
end
end
A_FRAME_IDLE : begin
if (dramout_burst_ready && M2S_AXI_ARREADY) begin
a_state <= A_FRAME_WAIT ;
M2S_AXI_ARVALID <= 1 ;
end
end
A_FRAME_WAIT: begin
if (r_state == R_IDLE) begin
M2S_AXI_ARADDR <= M2S_AXI_ARADDR + 128; // Bursts are 128 bytes long
a_state <= frame_done ? A_IDLE : A_FRAME_IDLE ;
end
end
endcase
end
end
localparam R_IDLE=0, R_WAIT=1;
//READ logic
reg [3:0] b_count;
reg r_state;
assign M2S_AXI_RREADY = (r_state == R_WAIT) && dramout_ready;
always @(posedge fclk or negedge rst_n) begin
if (rst_n == 0) begin
r_state <= R_IDLE;
b_count <= 0;
end else case(r_state)
R_IDLE: begin
if (a_state==A_FRAME_IDLE && dramout_burst_ready && M2S_AXI_ARREADY) begin
b_count <= 4'd15;
r_state <= R_WAIT;
end
end
R_WAIT: begin
if (M2S_AXI_RVALID && dramout_ready) begin
if(b_count == 4'h0) begin
r_state <= R_IDLE;
end
b_count <= b_count - 1'b1; // each valid cycle the bus provides 8 bytes
end
end
endcase
end
wire [8:0] rd_data_count;
wire [8:0] wr_data_count;
wire fifo_full;
wire fifo_empty;
assign dramout_data = M2S_AXI_RDATA;
assign dramout_valid = M2S_AXI_RVALID && (r_state == R_WAIT);
assign dramout_burst_ready = (wr_data_count < 9'd450);
assign dramout_ready = !fifo_full;
fifo_64w_64r_512d pipefifo (
.rst(!rst_n), // input rst
.wr_clk(fclk), // input wr_clk
.rd_clk(fclk), // input rd_clk
.din(dramout_data[63:0]), // input [63 : 0] din
.wr_en(dramout_valid), // input wr_en
.rd_en(dout_ready), // input rd_en
.dout(dout[63:0]), // output [63 : 0] dramout
.full(fifo_full), // output full
.empty(fifo_empty), // output empty
.rd_data_count(rd_data_count[8:0]), // output [8 : 0] rd_data_count
.wr_data_count(wr_data_count[8:0]) // output [8 : 0] wr_data_count
);
assign dout_valid = !fifo_empty;
endmodule : DramReaderBuf
|
#include <bits/stdc++.h> using namespace std; template <typename T> istream& operator>>(istream& is, vector<T>& v) { for (T& x : v) is >> x; return is; } template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { for (int i = 0; i < (int)v.size(); i++) { os << v[i] << (i + 1 == (int)v.size() ? : ); } return os; } template <typename T, typename U> ostream& operator<<(ostream& os, const pair<T, U>& p) { os << ( << p.first << , << p.second << ) ; return os; } template <typename T, typename U> ostream& operator<<(ostream& os, const map<T, U>& m) { os << { ; for (auto itr = m.begin(); itr != m.end();) { os << ( << itr->first << , << itr->second << ) ; if (++itr != m.end()) os << , ; } os << } ; return os; } template <typename T, typename U> ostream& operator<<(ostream& os, const unordered_map<T, U>& m) { os << { ; for (auto itr = m.begin(); itr != m.end();) { os << ( << itr->first << , << itr->second << ) ; if (++itr != m.end()) os << , ; } os << } ; return os; } template <typename T> ostream& operator<<(ostream& os, const set<T>& s) { os << { ; for (auto itr = s.begin(); itr != s.end();) { os << *itr; if (++itr != s.end()) os << , ; } os << } ; return os; } template <typename T> ostream& operator<<(ostream& os, const multiset<T>& s) { os << { ; for (auto itr = s.begin(); itr != s.end();) { os << *itr; if (++itr != s.end()) os << , ; } os << } ; return os; } template <typename T> ostream& operator<<(ostream& os, const unordered_set<T>& s) { os << { ; for (auto itr = s.begin(); itr != s.end();) { os << *itr; if (++itr != s.end()) os << , ; } os << } ; return os; } template <typename T> ostream& operator<<(ostream& os, const deque<T>& v) { for (int i = 0; i < (int)v.size(); i++) { os << v[i] << (i + 1 == (int)v.size() ? : ); } return os; } template <int i, typename T> void print_tuple(ostream&, const T&) {} template <int i, typename T, typename H, class... Args> void print_tuple(ostream& os, const T& t) { if (i) os << , ; os << get<i>(t); print_tuple<i + 1, T, Args...>(os, t); } template <typename... Args> ostream& operator<<(ostream& os, const tuple<Args...>& t) { os << { ; print_tuple<0, tuple<Args...>, Args...>(os, t); return os << } ; } void debug_out() { cerr << n ; } template <class Head, class... Tail> void debug_out(Head&& head, Tail&&... tail) { cerr << head; if (sizeof...(Tail) > 0) cerr << , ; debug_out(move(tail)...); } template <typename T> T gcd(T x, T y) { return y != 0 ? gcd(y, x % y) : x; } template <typename T> T lcm(T x, T y) { return x / gcd(x, y) * y; } int topbit(signed t) { return t == 0 ? -1 : 31 - __builtin_clz(t); } int topbit(long long t) { return t == 0 ? -1 : 63 - __builtin_clzll(t); } int botbit(signed a) { return a == 0 ? 32 : __builtin_ctz(a); } int botbit(long long a) { return a == 0 ? 64 : __builtin_ctzll(a); } int popcount(signed t) { return __builtin_popcount(t); } int popcount(long long t) { return __builtin_popcountll(t); } bool ispow2(int i) { return i && (i & -i) == i; } template <class T> T ceil(T x, T y) { assert(y >= 1); return (x > 0 ? (x + y - 1) / y : x / y); } template <class T> T floor(T x, T y) { assert(y >= 1); return (x > 0 ? x / y : (x - y + 1) / y); } template <class T1, class T2> inline bool chmin(T1& a, T2 b) { if (a > b) { a = b; return true; } return false; } template <class T1, class T2> inline bool chmax(T1& a, T2 b) { if (a < b) { a = b; return true; } return false; } const int INF = 1e9; const long long IINF = 1e18; const int dx[4] = {1, 0, -1, 0}, dy[4] = {0, 1, 0, -1}; const char dir[4] = { D , R , U , L }; const long long MOD = 1000000007; const int MAX_X = 2010; void solve() { int n; cin >> n; vector<int> dp(MAX_X, INF), ndp(MAX_X, INF); dp[0] = 0; for (; n--;) { int a; cin >> a; for (int i = 0; i < MAX_X; i++) { if (dp[i] == INF) continue; if (i + a < MAX_X) chmin(ndp[i + a], max(0, dp[i] - a)); chmin(ndp[max(0, i - a)], dp[i] + a); dp[i] = INF; } swap(dp, ndp); } int ans = INF; for (int i = 0; i < MAX_X; i++) chmin(ans, i + dp[i]); cout << ans << n ; } int main() { cin.tie(0); ios::sync_with_stdio(false); int t; cin >> t; for (; t--;) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e6 + 10; string rs; int pre[maxn]; void matchprefix() { int n = rs.length(); pre[0] = 0; int k = 0; for (int i = 1; i < n; i++) { while (k > 0 && rs[k] != rs[i]) k = pre[k - 1]; if (rs[k] == rs[i]) k++; pre[i] = k; } } int z[maxn]; void Z_function() { int n = rs.length(); z[0] = 0; int L = 0, R = 0; for (int i = 1; i < n; i++) { z[i] = 0; if (i <= R) { if (z[i - L] < R - i + 1) z[i] = z[i - L]; else { z[i] = min(z[i - L], R - i + 1); while (i + z[i] < n && rs[i + z[i]] == rs[z[i]]) z[i]++; L = i; R = i + z[i] - 1; } } else { while (i + z[i] < n && rs[i + z[i]] == rs[z[i]]) z[i]++; L = i; R = i + z[i] - 1; } } } int main() { string s, t; getline(cin, s); getline(cin, t); int n = s.length(); if (n != t.length()) { cout << -1 -1 ; return 0; } rs = s; reverse(rs.begin(), rs.end()); rs.push_back( n ); rs += t; matchprefix(); rs = t + n + s + n ; Z_function(); int ansi = -1, ansj = -1; for (int i = 0; i + 1 < n; i++) { if (s[i] != t[n - 1 - i]) break; int len_0_i = i + 1; int len_i_j = z[n + i + 2]; int len_j_n = pre[n + n - i - 1]; if (len_j_n > 0 && len_0_i + len_i_j + len_j_n >= n) { ansi = i; ansj = n - len_j_n; } } cout << ansi << << ansj; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, t, c, i, x, suma, resultado; cin >> n >> t >> c; suma = 0; resultado = 0; for (i = 0; i < n; i++) { cin >> x; if (x > t) suma = 0; else suma++; if (suma >= c) resultado++; } cout << resultado; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, x, y, z; cin >> a >> b >> c >> x >> y >> z; int a1, b1, c1, a2, b2, c2, m = 0, n = 0; if (a > x) { if (abs(a - x) >= 2) { if ((a - x) % 2 == 0) m = m + a - x; else m = m + a - x - 1; } } else n = n + a - x; if (b > y) { if (abs(b - y) >= 2) { if ((b - y) % 2 == 0) m = m + b - y; else m = m + b - y - 1; } } else n = n + b - y; if (c > z) { if (abs(c - z) >= 2) { if ((c - z) % 2 == 0) m = m + c - z; else m = m + c - z - 1; } } else n = n + c - z; if (m >= n * -2) cout << Yes << endl; else cout << No << endl; return 0; } |
// Asynchronous load and store register
module register # (parameter N = 8)
(input clk,
input [N-1:0] in,
output reg [N-1:0] out,
input load,
input clear
);
always @ (posedge clk or posedge clear)
if (clear) out <= 0;
else if (load) out <= in;
else out <= in;
endmodule
// Asynchronous load and store register with signals to control
// high and low bits seperately or at the same time
module register_hl # (parameter N = 16)
(input clk,
input [N/2-1:0] inh,
input [N/2-1:0] inl,
input loadh,
input loadl,
input clear,
output reg [N-1:0] out
);
always @ (posedge clk or posedge clear)
if (clear) out <= 0;
else begin
if (loadh) out[N-1:N/2] <= inh;
if (loadl) out[N/2-1:0] <= inl;
end
endmodule
// micro-PC, asynchronous reset
// Active high load
// Active low increment
module upcreg(
input clk,
input reset,
input load_incr,
input [4:0] upc_next,
output reg [4:0] upc);
always @ (posedge clk, posedge reset)
if (reset) upc <= 5'b00000;
else if (load_incr) upc <= upc_next;
else if (~load_incr) upc <= upc + 1;
else upc <= 5'b00000; //should never get here
endmodule
// 5:1 MULTIPLEXER
module mux5 (input d0, d1, d2, d3, d4,
input [2:0] s,
output reg y);
always @( * )
case(s)
3'b000: y <= d0;
3'b001: y <= d1;
3'b010: y <= d2;
3'b011: y <= d3;
3'b100: y <= d4;
default: y <= 1'b0;
endcase
endmodule
// 8-bit Adder/Subtractor (active low subtract)
module addsub
(
input [7:0] dataa,
input [7:0] datab,
input add_sub, // if this is 1, add; else subtract
input clk,
output reg [7:0] result
);
always @ (*)
begin
if (add_sub)
result <= dataa + datab;
else
result <= dataa - datab;
end
endmodule
// Counter that decrements from WIDTH to 0 at every positive clock edge.
module counter_down
(
clk,
reset,
ena,
result
);
input clk;
input reset;
input ena;
output reg [7:0] result;
always @(posedge clk or posedge reset)
begin
if (reset)
result = 7;
else if (ena)
result = result - 1;
end
endmodule
|
module mix(/*AUTOARG*/
// Outputs
OA, OB, OC,
// Inputs
a, b, c, clk, shift
);
input [31:0] a, b, c;
output [31:0] OA, OB, OC;
input clk;
input [4:0] shift;
assign OA = (a - c) ^ ( (c << shift) | (c >> (32 - shift)) );
assign OC = c + b;
assign OB = b;
endmodule
module lookup3(/*AUTOARG*/
// Outputs
x, y, z, done,
// Inputs
k0, k1, k2, clk, en, rst, length
);
output [31:0] x, y, z;
output done;
input [31:0] k0, k1, k2;
input clk;
input en;
input rst;
reg [31:0] x, y, z;
reg [4:0] shift;
wire [31:0] OA, OB, OC;
reg [31:0] a, b, c;
mix M0(/*AUTOINST*/
// Outputs
.OA (OA[31:0]),
.OB (OB[31:0]),
.OC (OC[31:0]),
// Inputs
.a (a[31:0]),
.b (b[31:0]),
.c (c[31:0]),
.clk (clk),
.shift (shift[4:0]));
reg [2:0] round;
always @(posedge clk)
if (rst)
round <= #1 0;
else if (en)
round <= #1 round + 1;
input [31:0] length;
wire [31:0] length_val = (length << 2) + 32'hdeadbeef;
always @(posedge clk)
if (en)
case (round)
/* a -= c; a ^= rot(c, 4); c += b; */
0: begin
a <= #1 k0 + length_val;
b <= #1 k1 + length_val;
c <= #1 k2 + length_val;
shift <= #1 4;
end
/* b -= a; b ^= rot(a, 6); a += c; */
1: begin /* DONE */
a <= #1 OB /* b */;
b <= #1 OC /* c */;
c <= #1 OA /* a */;
shift <= #1 6;
end
/* c -= b; c ^= rot(b, 8); b += a; */
2: begin
a <= #1 OB /* c */;
b <= #1 OC /* a */;
c <= #1 OA /* b */;
shift <= #1 8;
end
/* a -= c; a ^= rot(c,16); c += b; */
3: begin
a <= #1 OB/* a */;
b <= #1 OC/* b */;
c <= #1 OA/* c */;
shift <= #1 16;
end
/* b -= a; b ^= rot(a,19); a += c */
4: begin
a <= #1 OB/* b */;
b <= #1 OC/* c */;
c <= #1 OA/* a */;
shift <= #1 19;
end
/* c -= b; c ^= rot(b, 4); b += a; */
5: begin
a <= #1 OB/* c */;
b <= #1 OC/* a */;
c <= #1 OA/* b */;
shift <= #1 4;
end
endcase
always @(posedge clk)
if (round == 6) begin
x <= #1 OA;
y <= #1 OB;
z <= #1 OC;
end
assign done = round == 7;
endmodule // lookup3 |
#include <bits/stdc++.h> using namespace std; class Solution { public: int count(vector<int>& pieces, int p) { int n = pieces.size(); preprocess(n); vector<vector<vector<int>>> cur( n + 1, vector<vector<int>>(n + 1, vector<int>(n + 1, 0))); vector<vector<vector<int>>> nxt( n + 1, vector<vector<int>>(n + 1, vector<int>(n + 1, 0))); cur[0][0][0] = 1; for (int i = 0; i < n; ++i) { vector<int> cv; if (pieces[i] == -1) { cv.push_back(0); cv.push_back(1); } else { cv.push_back(pieces[i]); } for (auto& vv : nxt) { for (auto& v : vv) { fill(v.begin(), v.end(), 0); } } for (int j = 0; j <= i; ++j) { for (int k = 0; k <= j; ++k) { for (int l = 0; l <= i - j; ++l) { if (cur[j][k][l] == 0) { continue; } for (auto c : cv) { if (c == 0) { int nj = j + 1; nxt[nj][k + 1][l] = add(nxt[nj][k + 1][l], multiply(cur[j][k][l], multiply(1LL << j, multiply(1LL << (i - j - l), csums[l][0])))); nxt[nj][k][l] = add(nxt[nj][k][l], multiply(cur[j][k][l], multiply(1LL << j, multiply(1LL << (i - j - l), csums[l][1])))); } else { int nj = j; nxt[nj][k][l + 1] = add( nxt[nj][k][l + 1], multiply(cur[j][k][l], multiply(1LL << (i - j), multiply(1LL << (j - k), csums[k][0])))); nxt[nj][k][l] = add( nxt[nj][k][l], multiply(cur[j][k][l], multiply(1LL << (i - j), multiply(1LL << (j - k), csums[k][1])))); } } } } } cur.swap(nxt); } long long res = 0; for (int i = 0; i <= n; ++i) { for (int j = 0; j <= i; ++j) { for (int k = 0; k <= n - i; ++k) { if ((j + k) % 2 == p) { res = add(res, cur[i][j][k]); } } } } return res; } private: const static int M = 1e9 + 7; vector<int> fv; vector<int> ifv; vector<vector<int>> cs; vector<vector<int>> csums; long long add(long long a, long long b) { long long res = (a + b) % M; return res; } long long multiply(long long a, long long b) { return (a * b) % M; } long long pow(long long x, long long e) { long long res = 1; while (e > 0) { if (e & 1) { res = multiply(res, x); } x = multiply(x, x); e >>= 1; } return res; } void preprocess(int n) { fv.clear(); fv.resize(n + 1); ifv.clear(); ifv.resize(n + 1); cs.clear(); cs.resize(n + 1); csums.clear(); csums.resize(n + 1); for (auto& v : csums) { v.resize(2); fill(v.begin(), v.end(), 0); } fv[0] = 1; for (int i = 1; i <= n; ++i) { fv[i] = multiply(fv[i - 1], i); } ifv[0] = 1; ifv[n] = pow(fv[n], M - 2); for (int i = n - 1; i >= 1; --i) { ifv[i] = multiply(ifv[i + 1], i + 1); } for (int i = 1; i <= n; ++i) { cs[i].resize(i + 1); for (int j = 0; j <= i; ++j) { cs[i][j] = multiply(multiply(fv[i], ifv[j]), ifv[i - j]); } } csums[0][0] = 1; for (int i = 1; i <= n; ++i) { for (int j = 0; j <= i; ++j) { if (j % 2) { csums[i][1] = add(csums[i][1], cs[i][j]); } else { csums[i][0] = add(csums[i][0], cs[i][j]); } } } } }; int main(int argc, char** argv) { ios::sync_with_stdio(false); cin.tie(0); int n; int p; cin >> n >> p; vector<int> nums(n); for (int i = 0; i < n; ++i) { cin >> nums[i]; } Solution sol; cout << sol.count(nums, p) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2005; const char vow[] = { a , e , i , o , u , y }; char str[maxn]; bool check(char ch) { for (int i = 0; i < 6; ++i) { if (ch == vow[i]) return true; } return false; } int main() { int n; while (~scanf( %d , &n)) { scanf( %s , str); for (int i = 0; i < n; ++i) { if (check(str[i])) { for (int j = i + 1; j < n; ++j) { if (str[i] == 0) continue; if (check(str[j])) str[j] = 0; else break; } } } for (int i = 0; i < n; ++i) { if (str[i]) putchar(str[i]); } puts( ); } return 0; } |
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