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// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// dc filter- y(n) = c*x(n) + (1-c)*y(n-1)
`timescale 1ps/1ps
module ad_dcfilter (
// data interface
clk,
valid,
data,
valid_out,
data_out,
// control interface
dcfilt_enb,
dcfilt_coeff,
dcfilt_offset);
// data interface
input clk;
input valid;
input [15:0] data;
output valid_out;
output [15:0] data_out;
// control interface
input dcfilt_enb;
input [15:0] dcfilt_coeff;
input [15:0] dcfilt_offset;
// internal registers
reg valid_d = 'd0;
reg [15:0] data_d = 'd0;
reg valid_2d = 'd0;
reg [15:0] data_2d = 'd0;
reg valid_out = 'd0;
reg [15:0] data_out = 'd0;
// cancelling the dc offset
always @(posedge clk) begin
dc_offset <= 16'h0;
valid_d <= valid;
if (valid == 1'b1) begin
data_d <= data + dcfilt_offset;
end
valid_2d <= valid_d;
data_2d <= data_d - dc_offset;
if (dcfilt_enb == 1'b1) begin
valid_out <= valid_2d;
data_out <= data_d; // DC filter not implemented in this version
end else begin
valid_out <= valid_d;
data_out <= data_d;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int n; double V1; double V2[100005]; double L[100005]; double D[100005]; double X[100005]; bool check(double T) { bool ok1 = false; bool ok1b = false; bool ok2 = false; bool ok2b = false; double l = 0; double r = 1000000; vector<pair<double, double> > V; V.clear(); for (int i = 1; i <= n; i++) { if (D[i] == 1 && !ok1) { if (L[i] <= V2[i] * T) { ok1 = true; } else { double TS = T - L[i] / (V1 + V2[i]); double MS = 1 / (V1 - V2[i]) - V2[i] / (V1 * V1 - V2[i] * V2[i]); if (TS < 0) continue; ok1b = true; double x; if (TS > MS * 10000000) x = 1000000; else x = TS / MS; if (x < 1) x = 0; if (X[i] > l) l = X[i]; if (X[i] + x < r) r = X[i] + x; V.push_back(make_pair(X[i], X[i] + x)); } } } for (int i = 1; i <= n; i++) { if (D[i] == 2 && !ok2) { if (L[i] <= V2[i] * T) { ok2 = true; } else { double TS = T - L[i] / (V1 + V2[i]); double MS = 1 / (V1 - V2[i]) - V2[i] / (V1 * V1 - V2[i] * V2[i]); if (TS < 0) continue; ok2b = true; double x; if (TS > MS * 10000000) x = 1000000; else x = TS / MS; if (x < 1) x = 0; if (X[i] - x > l) l = X[i] - x; if (X[i] < r) r = X[i]; for (int j = 0; j < V.size(); j++) if ((V[j].first <= X[i] && X[i] <= V[j].second) || (V[j].first <= (X[i] - x) && (X[i] - x) <= V[j].second)) { return true; } } } } return ((ok1 && ok2b) || (ok2 && ok1b) || (ok1 && ok2)); } int main() { cin >> n >> V1; for (int i = 1; i <= n; i++) { cin >> X[i] >> V2[i] >> D[i]; if (D[i] == 1) L[i] = X[i]; else L[i] = 1000000 - X[i]; } double l = 0; double r = 10000000; while (0.0000001 <= r - l) { double m = (l + r) / 2; if (check(m)) r = m - 0.00000001; else l = m + 0.00000001; } printf( %0.8f n , r); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCON_1_V
`define SKY130_FD_SC_MS__FAHCON_1_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog wrapper for fahcon with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__fahcon.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fahcon_1 (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__fahcon_1 (
COUT_N,
SUM ,
A ,
B ,
CI
);
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__fahcon base (
.COUT_N(COUT_N),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCON_1_V
|
//
// Every HW component class has to be derived from :class:`hwt.synthesizer.unit.Unit` class
//
// .. hwt-autodoc::
//
module Showcase0 (
input wire[31:0] a,
input wire signed[31:0] b,
output reg[31:0] c,
input wire clk,
output reg cmp_0,
output reg cmp_1,
output reg cmp_2,
output reg cmp_3,
output reg cmp_4,
output reg cmp_5,
output reg[31:0] contOut,
input wire[31:0] d,
input wire e,
output wire f,
output reg[15:0] fitted,
output reg[7:0] g,
output reg[7:0] h,
input wire[1:0] i,
output reg[7:0] j,
output reg[31:0] k,
output wire out,
output wire output_0,
input wire rst_n,
output reg[7:0] sc_signal
);
localparam [31:0] const_private_signal = 32'h0000007b;
reg signed[7:0] fallingEdgeRam[0:3];
reg r = 1'b0;
reg[1:0] r_0 = 2'b00;
reg[1:0] r_1 = 2'b00;
reg r_next;
wire[1:0] r_next_0;
wire[1:0] r_next_1;
reg[7:0] rom[0:3];
always @(a, b) begin: assig_process_c
c = a + $signed(b);
end
always @(a) begin: assig_process_cmp_0
cmp_0 = a < 32'h00000004;
end
always @(a) begin: assig_process_cmp_1
cmp_1 = a > 32'h00000004;
end
always @(b) begin: assig_process_cmp_2
cmp_2 = b <= $signed(32'h00000004);
end
always @(b) begin: assig_process_cmp_3
cmp_3 = b >= $signed(32'h00000004);
end
always @(b) begin: assig_process_cmp_4
cmp_4 = b != $signed(32'h00000004);
end
always @(b) begin: assig_process_cmp_5
cmp_5 = b == $signed(32'h00000004);
end
always @(*) begin: assig_process_contOut
contOut = const_private_signal;
end
assign f = r;
always @(negedge clk) begin: assig_process_fallingEdgeRam
fallingEdgeRam[r_1] <= $unsigned(a[7:0]);
k <= {24'h000000, $signed(fallingEdgeRam[r_1])};
end
always @(a) begin: assig_process_fitted
fitted = a[15:0];
end
always @(a, b) begin: assig_process_g
g = {{a[1] & b[1], a[0] ^ b[0] | a[1]}, a[5:0]};
end
always @(a, r) begin: assig_process_h
if (a[2])
if (r)
h = 8'h00;
else if (a[1])
h = 8'h01;
else
h = 8'h02;
end
always @(posedge clk) begin: assig_process_j
j <= rom[r_1];
end
assign out = 1'b0;
assign output_0 = 1'bx;
always @(posedge clk) begin: assig_process_r
if (rst_n == 1'b0) begin
r_1 <= 2'b00;
r_0 <= 2'b00;
r <= 1'b0;
end else begin
r_1 <= r_next_1;
r_0 <= r_next_0;
r <= r_next;
end
end
assign r_next_0 = i;
assign r_next_1 = r_0;
always @(e, r) begin: assig_process_r_next_1
if (~r)
r_next = e;
else
r_next = r;
end
always @(a) begin: assig_process_sc_signal
case(a)
32'h00000001:
sc_signal = 8'h00;
32'h00000002:
sc_signal = 8'h01;
32'h00000003:
sc_signal = 8'h03;
default:
sc_signal = 8'h04;
endcase
end
initial begin
rom[0] = 0;
rom[1] = 1;
rom[2] = 2;
rom[3] = 3;
end
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet PHY
*/
module eth_phy_10g #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* XGMII interface
*/
input wire [DATA_WIDTH-1:0] xgmii_txd,
input wire [CTRL_WIDTH-1:0] xgmii_txc,
output wire [DATA_WIDTH-1:0] xgmii_rxd,
output wire [CTRL_WIDTH-1:0] xgmii_rxc,
/*
* SERDES interface
*/
output wire [DATA_WIDTH-1:0] serdes_tx_data,
output wire [HDR_WIDTH-1:0] serdes_tx_hdr,
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire [6:0] rx_error_count,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire tx_prbs31_enable,
input wire rx_prbs31_enable
);
eth_phy_10g_rx #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_error_count(rx_error_count),
.rx_bad_block(rx_bad_block),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
eth_phy_10g_tx #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(TX_SERDES_PIPELINE)
)
eth_phy_10g_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.serdes_tx_data(serdes_tx_data),
.serdes_tx_hdr(serdes_tx_hdr),
.tx_prbs31_enable(tx_prbs31_enable)
);
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:256000000 ) using namespace std; const int SZ = 110; const int INF = 1000 * 1000 * 1000; double start, finish; void prepare(string s) { if ((int)s.size() != 0) { freopen((s + .in ).c_str(), r , stdin); freopen((s + .out ).c_str(), w , stdout); } } void startTimer() {} void stopTimer() {} int n; vector<int> g; vector<vector<int> > p; void getData() { cin >> n; g.resize(n); for (int i = 0; i < n; ++i) { cin >> g[i]; } p.resize(n); for (int i = 0; i < n; ++i) { p[i].resize(g[i]); for (int j = 0; j < g[i]; ++j) { cin >> p[i][j]; } } } void solve() { int ans = INF; g.assign(n, 0); for (int i = 0; i < n; ++i) { int cnt = 0; for (int j = 0; j < (int)p[i].size(); ++j) { cnt += p[i][j] * 5 + 15; } ans = min(ans, cnt); } cout << ans << endl; } int main() { prepare( ); ios::sync_with_stdio(false); startTimer(); getData(); solve(); stopTimer(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6; int pref[MAXN + 1]; string S; int n, k; void fast_io() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } pair<int, int> query(int s) { int lo = s, hi = n; int res = -1; while (lo <= hi) { int mid = (lo + hi) >> 1; if (pref[mid] - pref[s - 1] >= k) res = mid, hi = mid - 1; else lo = mid + 1; } if (res == -1 or (pref[res] - pref[s - 1]) != k) return make_pair(-1, -1); pair<int, int> p = make_pair(res, -1); lo = res, hi = n; res = -1; while (lo <= hi) { int mid = (lo + hi) >> 1; if (pref[mid] - pref[s - 1] <= k) res = mid, lo = mid + 1; else hi = mid - 1; } p.second = res; return p; } int main() { fast_io(); cin >> k >> S; n = S.length(); S = $ + S; for (int i = 1; i <= n; i++) { pref[i] = (S[i] - 0 ) + pref[i - 1]; } long long ans = 0; for (int i = 1; i <= n; i++) { pair<int, int> p = query(i); if (p.first == -1) continue; ans += (p.second - p.first + 1); } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; inline void boost() { ios_base::sync_with_stdio(); cin.tie(0); } const long long MAX = 1e5 + 111; const long long mod = 1e9 + 7; map<string, int> maap; vector<int> g[MAX]; int main() { boost(); int n; bool ans = false; cin >> n; string a[n + 1]; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i <= n; i++) { if (a[i][0] == O && a[i][1] == O ) { a[i].erase(0, 2); a[i].insert(0, ++ ); ans = true; break; } if (a[i][3] == O && a[i][4] == O ) { a[i].erase(3, 4); a[i].insert(3, ++ ); ans = true; break; } } if (ans == true) { cout << YES n ; for (int i = 1; i <= n; i++) { cout << a[i] << n ; } } else { cout << NO ; } exit(0); } |
#include <bits/stdc++.h> using namespace std; int main() { string s; while (cin >> s) { string integer; string decimal; bool isnegative = false; bool isdecimal = false; int pos = 0; if (s[0] == - ) { isnegative = true; pos++; } for (; pos < s.size(); pos++) { if (s[pos] == . ) { isdecimal = true; } else if (!isdecimal) { integer += s[pos]; } else { decimal += s[pos]; } } reverse(integer.begin(), integer.end()); string integerWithComma; for (int i = 0; i < integer.size(); i++) { integerWithComma += integer[i]; if (i != integer.size() - 1 && i % 3 == 2) { integerWithComma += , ; } } reverse(integerWithComma.begin(), integerWithComma.end()); string decimalProcess; if (decimal.size() == 0) { decimalProcess = .00 ; } else if (decimal.size() == 1) { decimalProcess = . + decimal + 0 ; } else { decimalProcess = . + decimal.substr(0, 2); } if (isnegative) { cout << ( ; } cout << $ ; cout << integerWithComma; cout << decimalProcess; if (isnegative) { cout << ) ; } cout << endl; } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] cyc; initial cyc = 0;
reg [31:0] loops;
reg [31:0] loops2;
integer i;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
$write("[%0t] t_loop: Running\n", $time);
// Unwind <
loops = 0;
loops2 = 0;
for (i=0; i<16; i=i+1) begin
loops = loops + i; // surefire lint_off_line ASWEMB
loops2 = loops2 + i; // surefire lint_off_line ASWEMB
end
if (i !== 16) $stop;
if (loops !== 120) $stop;
if (loops2 !== 120) $stop;
// Unwind <=
loops = 0;
for (i=0; i<=16; i=i+1) begin
loops = loops + 1;
end
if (i !== 17) $stop;
if (loops !== 17) $stop;
// Don't unwind breaked loops
loops = 0;
for (i=0; i<16; i=i+1) begin
loops = loops + 1;
if (i==7) i=99; // break out of loop
end
if (loops !== 8) $stop;
// Don't unwind large loops!
loops = 0;
for (i=0; i<100000; i=i+1) begin
loops = loops + 1;
end
if (loops !== 100000) $stop;
// Test post-increment
loops = 0;
for (i=0; i<=16; i++) begin
loops = loops + 1;
end
if (i !== 17) $stop;
if (loops !== 17) $stop;
// Test pre-increment
loops = 0;
for (i=0; i<=16; ++i) begin
loops = loops + 1;
end
if (i !== 17) $stop;
if (loops !== 17) $stop;
// Test post-decrement
loops = 0;
for (i=16; i>=0; i--) begin
loops = loops + 1;
end
if (i !== -1) $stop;
if (loops !== 17) $stop;
// Test pre-decrement
loops = 0;
for (i=16; i>=0; --i) begin
loops = loops + 1;
end
if (i !== -1) $stop;
if (loops !== 17) $stop;
//
// 1800-2017 optionals init/expr/incr
loops = 0;
i = 0;
for (; i<10; ++i) ++loops;
if (loops !== 10) $stop;
//
loops = 0;
i = 0;
for (i=0; i<10; ) begin ++loops; ++i; end
if (loops !== 10) $stop;
//
loops = 0;
i = 0;
for (; ; ++i) begin ++loops; break; end
if (loops !== 1) $stop;
//
// bug1605
i = 1;
for (i=20; 0; ) ;
if (i != 20) $stop;
for (i=30; i<10; i++) ;
if (i != 30) $stop;
// Comma
loops = 0;
for (i=0; i<20; ++i, ++loops);
if (loops !== 20) $stop;
loops = 0;
for (i=0; i<20; ++loops, ++i);
if (loops !== 20) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
* This module generates a CRC16 value from an incomming bitstream
* the value is generated from bit that is currently shifting out
* The final crc is valid after the last bit is sent, it might be
* necessary to send this value one clock cycle before
*
* Last two bytes of the data
* CCCCCCCCCCCCCCCC
* C = CRC bit
*
* Hold in reset when not using
*
* Online documentation is way to fucking complicated
* x^16 + x^12 + x^5 + 1
* To find the polynomial remove the top x^16 then add 2^12 + 2^5 + 1 = 0x1021
*
*
* Changes:
* 2015.08.08: Initial Add
*
*/
module crc16_2bit #(
parameter POLYNOMIAL = 16'h1021,
parameter SEED = 16'h0000
)(
input clk,
input rst,
input en,
input bit0,
input bit1,
output reg [15:0] crc
);
//local parameters
//registes/wires
wire inv0;
wire inv1;
//submodules
//asynchronous logic
assign inv1 = bit1 ^ crc[15];
assign inv0 = (bit0 ^ crc[14]);
always @ (posedge clk) begin
if (rst) begin
crc <= 0;
end
else begin
//Shift the output value
if (en) begin
crc[15] <= crc[13];
crc[14] <= crc[12];
crc[13] <= crc[11] ^ inv1;
crc[12] <= crc[10] ^ inv0;
crc[11] <= crc[9];
crc[10] <= crc[8];
crc[9] <= crc[7];
crc[8] <= crc[6];
crc[7] <= crc[5];
crc[6] <= crc[4] ^ inv1;
crc[5] <= crc[3] ^ inv0;
crc[4] <= crc[2];
crc[3] <= crc[1];
crc[2] <= crc[0];
crc[1] <= inv1;
crc[0] <= inv0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, s, a[100005], p, w[100005], ans; multiset<long long> st; int main() { cin >> n >> s; for (int k = 1; k <= n; k++) cin >> a[k]; cin >> p; for (int k = 1; k <= n; k++) cin >> w[k]; for (int k = 1; k <= n; k++) { st.insert(w[k]); while (s < a[k]) { if (st.size() == 0) { cout << -1; return 0; } ans += *st.begin(); st.erase(st.begin()); s += p; } } cout << ans; return 0; } |
module nios_tester (
audio_in_data,
audio_in_valid,
audio_in_ready,
audio_out_data,
audio_out_valid,
audio_out_ready,
dummy_export,
io_ack,
io_rdata,
io_read,
io_wdata,
io_write,
io_address,
io_irq,
io_u2p_ack,
io_u2p_rdata,
io_u2p_read,
io_u2p_wdata,
io_u2p_write,
io_u2p_address,
io_u2p_irq,
jtag0_jtag_tck,
jtag0_jtag_tms,
jtag0_jtag_tdi,
jtag0_jtag_tdo,
jtag1_jtag_tck,
jtag1_jtag_tms,
jtag1_jtag_tdi,
jtag1_jtag_tdo,
jtag_in_data,
jtag_in_valid,
jtag_in_ready,
mem_mem_req_address,
mem_mem_req_byte_en,
mem_mem_req_read_writen,
mem_mem_req_request,
mem_mem_req_tag,
mem_mem_req_wdata,
mem_mem_resp_dack_tag,
mem_mem_resp_data,
mem_mem_resp_rack_tag,
pio_in_port,
pio_out_port,
spi_MISO,
spi_MOSI,
spi_SCLK,
spi_SS_n,
sys_clock_clk,
sys_reset_reset_n);
input [31:0] audio_in_data;
input audio_in_valid;
output audio_in_ready;
output [31:0] audio_out_data;
output audio_out_valid;
input audio_out_ready;
input dummy_export;
input io_ack;
input [7:0] io_rdata;
output io_read;
output [7:0] io_wdata;
output io_write;
output [19:0] io_address;
input io_irq;
input io_u2p_ack;
input [7:0] io_u2p_rdata;
output io_u2p_read;
output [7:0] io_u2p_wdata;
output io_u2p_write;
output [19:0] io_u2p_address;
input io_u2p_irq;
output jtag0_jtag_tck;
output jtag0_jtag_tms;
output jtag0_jtag_tdi;
input jtag0_jtag_tdo;
output jtag1_jtag_tck;
output jtag1_jtag_tms;
output jtag1_jtag_tdi;
input jtag1_jtag_tdo;
input [7:0] jtag_in_data;
input jtag_in_valid;
output jtag_in_ready;
output [25:0] mem_mem_req_address;
output [3:0] mem_mem_req_byte_en;
output mem_mem_req_read_writen;
output mem_mem_req_request;
output [7:0] mem_mem_req_tag;
output [31:0] mem_mem_req_wdata;
input [7:0] mem_mem_resp_dack_tag;
input [31:0] mem_mem_resp_data;
input [7:0] mem_mem_resp_rack_tag;
input [31:0] pio_in_port;
output [31:0] pio_out_port;
input spi_MISO;
output spi_MOSI;
output spi_SCLK;
output spi_SS_n;
input sys_clock_clk;
input sys_reset_reset_n;
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4.1 (win64) Build Thu Feb 19 16:23:09 MST 2015
//Date : Fri Nov 10 02:35:34 2017
//Host : aCentauri running 64-bit Service Pack 1 (build 7601)
//Command : generate_target OpenSSD2_wrapper.bd
//Design : OpenSSD2_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module OpenSSD2_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
IO_NAND_CH0_DQ,
IO_NAND_CH0_DQS_N,
IO_NAND_CH0_DQS_P,
IO_NAND_CH1_DQ,
IO_NAND_CH1_DQS_N,
IO_NAND_CH1_DQS_P,
I_NAND_CH0_RB,
I_NAND_CH1_RB,
O_DEBUG,
O_NAND_CH0_ALE,
O_NAND_CH0_CE,
O_NAND_CH0_CLE,
O_NAND_CH0_RE_N,
O_NAND_CH0_RE_P,
O_NAND_CH0_WE,
O_NAND_CH0_WP,
O_NAND_CH1_ALE,
O_NAND_CH1_CE,
O_NAND_CH1_CLE,
O_NAND_CH1_RE_N,
O_NAND_CH1_RE_P,
O_NAND_CH1_WE,
O_NAND_CH1_WP,
pcie_perst_n,
pcie_ref_clk_n,
pcie_ref_clk_p,
pcie_rx_n,
pcie_rx_p,
pcie_tx_n,
pcie_tx_p);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
inout [7:0]IO_NAND_CH0_DQ;
inout IO_NAND_CH0_DQS_N;
inout IO_NAND_CH0_DQS_P;
inout [7:0]IO_NAND_CH1_DQ;
inout IO_NAND_CH1_DQS_N;
inout IO_NAND_CH1_DQS_P;
input [7:0]I_NAND_CH0_RB;
input [7:0]I_NAND_CH1_RB;
output [31:0]O_DEBUG;
output O_NAND_CH0_ALE;
output [7:0]O_NAND_CH0_CE;
output O_NAND_CH0_CLE;
output O_NAND_CH0_RE_N;
output O_NAND_CH0_RE_P;
output O_NAND_CH0_WE;
output O_NAND_CH0_WP;
output O_NAND_CH1_ALE;
output [7:0]O_NAND_CH1_CE;
output O_NAND_CH1_CLE;
output O_NAND_CH1_RE_N;
output O_NAND_CH1_RE_P;
output O_NAND_CH1_WE;
output O_NAND_CH1_WP;
input pcie_perst_n;
input pcie_ref_clk_n;
input pcie_ref_clk_p;
input [7:0]pcie_rx_n;
input [7:0]pcie_rx_p;
output [7:0]pcie_tx_n;
output [7:0]pcie_tx_p;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [7:0]IO_NAND_CH0_DQ;
wire IO_NAND_CH0_DQS_N;
wire IO_NAND_CH0_DQS_P;
wire [7:0]IO_NAND_CH1_DQ;
wire IO_NAND_CH1_DQS_N;
wire IO_NAND_CH1_DQS_P;
wire [7:0]I_NAND_CH0_RB;
wire [7:0]I_NAND_CH1_RB;
wire [31:0]O_DEBUG;
wire O_NAND_CH0_ALE;
wire [7:0]O_NAND_CH0_CE;
wire O_NAND_CH0_CLE;
wire O_NAND_CH0_RE_N;
wire O_NAND_CH0_RE_P;
wire O_NAND_CH0_WE;
wire O_NAND_CH0_WP;
wire O_NAND_CH1_ALE;
wire [7:0]O_NAND_CH1_CE;
wire O_NAND_CH1_CLE;
wire O_NAND_CH1_RE_N;
wire O_NAND_CH1_RE_P;
wire O_NAND_CH1_WE;
wire O_NAND_CH1_WP;
wire pcie_perst_n;
wire pcie_ref_clk_n;
wire pcie_ref_clk_p;
wire [7:0]pcie_rx_n;
wire [7:0]pcie_rx_p;
wire [7:0]pcie_tx_n;
wire [7:0]pcie_tx_p;
OpenSSD2 OpenSSD2_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.IO_NAND_CH0_DQ(IO_NAND_CH0_DQ),
.IO_NAND_CH0_DQS_N(IO_NAND_CH0_DQS_N),
.IO_NAND_CH0_DQS_P(IO_NAND_CH0_DQS_P),
.IO_NAND_CH1_DQ(IO_NAND_CH1_DQ),
.IO_NAND_CH1_DQS_N(IO_NAND_CH1_DQS_N),
.IO_NAND_CH1_DQS_P(IO_NAND_CH1_DQS_P),
.I_NAND_CH0_RB(I_NAND_CH0_RB),
.I_NAND_CH1_RB(I_NAND_CH1_RB),
.O_DEBUG(O_DEBUG),
.O_NAND_CH0_ALE(O_NAND_CH0_ALE),
.O_NAND_CH0_CE(O_NAND_CH0_CE),
.O_NAND_CH0_CLE(O_NAND_CH0_CLE),
.O_NAND_CH0_RE_N(O_NAND_CH0_RE_N),
.O_NAND_CH0_RE_P(O_NAND_CH0_RE_P),
.O_NAND_CH0_WE(O_NAND_CH0_WE),
.O_NAND_CH0_WP(O_NAND_CH0_WP),
.O_NAND_CH1_ALE(O_NAND_CH1_ALE),
.O_NAND_CH1_CE(O_NAND_CH1_CE),
.O_NAND_CH1_CLE(O_NAND_CH1_CLE),
.O_NAND_CH1_RE_N(O_NAND_CH1_RE_N),
.O_NAND_CH1_RE_P(O_NAND_CH1_RE_P),
.O_NAND_CH1_WE(O_NAND_CH1_WE),
.O_NAND_CH1_WP(O_NAND_CH1_WP),
.pcie_perst_n(pcie_perst_n),
.pcie_ref_clk_n(pcie_ref_clk_n),
.pcie_ref_clk_p(pcie_ref_clk_p),
.pcie_rx_n(pcie_rx_n),
.pcie_rx_p(pcie_rx_p),
.pcie_tx_n(pcie_tx_n),
.pcie_tx_p(pcie_tx_p));
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 14:33:05 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mul8_16_stub.v
// Design : mul8_16
// Purpose : Stub declaration of top-level module interface
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[7:0],B[15:0],P[15:0]" */;
input CLK;
input [7:0]A;
input [15:0]B;
output [15:0]P;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBN_TB_V
`define SKY130_FD_SC_LP__DLRBN_TB_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrbn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_lp__dlrbn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBN_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; cout << n / (2520LL); return 0; } |
#include <bits/stdc++.h> using namespace std; struct point { int n; int value; vector<int> next; } p[100010]; queue<struct point> q; int main() { int n, m, x, y, flag = 1, t; scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d %d , &x, &y); p[x].next.push_back(y); p[x].n++; p[y].next.push_back(x); p[y].n++; } for (int i = 1; i <= n; i++) { if (!flag) break; if (p[i].n && !p[i].value) { p[i].value = 1; q.push(p[i]); while (!q.empty()) { for (int j = 0; j < q.front().n; j++) { if (!p[q.front().next[j]].value) { p[q.front().next[j]].value = q.front().value % 2 + 1; q.push(p[q.front().next[j]]); } else { if (p[q.front().next[j]].value != q.front().value % 2 + 1) { flag = 0; break; } } } q.pop(); } } } if (flag) { int ans = 0; for (int i = 1; i <= n; i++) { if (p[i].value == 1) ans++; } printf( %d n , ans); for (int i = 1; i <= n; i++) { if (p[i].value == 1) { printf( %d , i); } } printf( n ); ans = 0; for (int i = 1; i <= n; i++) { if (p[i].value == 2) ans++; } printf( %d n , ans); for (int i = 1; i <= n; i++) { if (p[i].value == 2) { printf( %d , i); } } } else { printf( -1 ); } } |
#include <bits/stdc++.h> using namespace std; const double EPS = 1E-9; const int INF = 1000000000; const long long INF64 = (long long)1E18; const double PI = 3.1415926535897932384626433832795; long long gcd(long long a, long long b) { if (a < b) return gcd(b, a); if (b == 0) return a; return gcd(b, a % b); } int main() { char *s = new char[2000000]; char *z = new char[2000000]; long long i, j, n, a, b, c, x = 0, y = 0, slen; memset(s, 0, 2000000); memset(z, 0, 2000000); cin >> s; slen = strlen(s); for (i = 0; i < slen; ++i) if (s[i] == x ) x++; else y++; if (x > y) { x = x - y; for (i = 0; i < x; ++i) z[i] = x ; } else { y = y - x; for (i = 0; i < y; ++i) z[i] = y ; } cout << z; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLCLKP_PP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLCLKP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31OI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A31OI_PP_BLACKBOX_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31OI_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
module Lab8(LCD_ENABLE, LCD_RW, LCD_DI, LCD_CS1, LCD_CS2, LCD_RST, LCD_DATA, rst_n, clk, DIGIT, DISPLAY, ROW, COLUMN);
input clk, rst_n;
output [3:0] DIGIT;
output [8:0] DISPLAY;
output [3:0] ROW;
input [3:0] COLUMN;
output LCD_ENABLE, LCD_RW, LCD_DI, LCD_CS1, LCD_CS2, LCD_RST;
output [7:0] LCD_DATA;
wire clk_LCD, clk_7seg, clk_1s, clk_500ms, clk_1us;
wire [15:0] mole16bit;
wire [255:0] PATTERN;
wire CLEAR, CALLFORPATTERN;
wire PRESS_VALID;
wire db_rst_n;
wire [3:0]TTen, TOne, STen, SOne, KEY_IN;
wire isFinished;
Timer timer(
TTen,
TOne,
isFinished,
clk_1s,
db_rst_n
);
CLK_DIV CD1(clk_LCD, clk_7seg, clk_1s, clk_500ms, clk_1us, clk);
debounce db(db_rst_n, rst_n, clk);
KeyBoard_ctrl kbc(ROW, KEY_IN, COLUMN, clk, rst_n);
LED7SEG led (DIGIT, DISPLAY, TTen, TOne, STen, SOne, 0, 0, 0, clk_7seg);
LCD_DISPLAY_CTRL LCDDC1(PATTERN, CLEAR, CALLFORPATTERN, mole16bit, rst_n, clk_LCD);
LCD_DISPLAY LCDD1(LCD_ENABLE, LCD_RW, LCD_DI, LCD_CS1, LCD_CS2, LCD_RST, LCD_DATA, CLEAR, CALLFORPATTERN, PATTERN, rst_n, clk_LCD);
GameCtr gtr(
STen,
SOne,
mole16bit,
KEY_IN,
PRESS_VALID,
isFinished,
clk_1s,
clk_1us,
db_rst_n
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; long long a[200010] = {}; vector<int> e[200010]; long long t[200010] = {}; long long q[200010] = {}; int s, b; long long ans = -222147483600ll; bool cmp(long long x, long long y) { return x > y; } void dfs(int x, int y) { vector<long long> w; t[x] += a[x]; q[x] = -2221483600ll; for (int i = 0; i < e[x].size(); i++) { if (e[x][i] == y) continue; dfs(e[x][i], x); t[x] += t[e[x][i]]; q[x] = max(q[x], q[e[x][i]]); w.push_back(q[e[x][i]]); } sort(w.begin(), w.end(), cmp); q[x] = max(t[x], q[x]); if (w.size() >= 2) { ans = max(w[0] + w[1], ans); } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); } for (int i = 1; i < n; i++) { scanf( %d%d , &s, &b); e[s].push_back(b); e[b].push_back(s); } dfs(1, 0); if (ans == -222147483600ll) cout << Impossible << endl; else cout << ans << endl; return 0; } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 23:00:32 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_0_1/zqynq_lab_1_design_axi_gpio_0_1_stub.v
// Design : zqynq_lab_1_design_axi_gpio_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.2" *)
module zqynq_lab_1_design_axi_gpio_0_1(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_o)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output [7:0]gpio_io_o;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: clock_generator_ddr_s8_diff.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: September 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: BUFIO2 Based DDR clock generator. Takes in a differential clock
// and instantiates two sets of 2 BUFIO2s, one for each half bank
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module clock_generator_ddr_s8_diff (clkin_p, clkin_n, ioclkap, ioclkan, serdesstrobea, ioclkbp, ioclkbn, serdesstrobeb, gclk) ;
parameter integer S = 8 ; // Parameter to set the serdes factor 1..8
parameter DIFF_TERM = "FALSE" ; // Parameter to enable internal differential termination
input clkin_p, clkin_n ; // differential clock input
output ioclkap ; // A P ioclock from BUFIO2
output ioclkan ; // A N ioclock from BUFIO2
output serdesstrobea ; // A serdes strobe from BUFIO2
output ioclkbp ; // B P ioclock from BUFIO2 - leave open if not required
output ioclkbn ; // B N ioclock from BUFIO2 - leave open if not required
output serdesstrobeb ; // B serdes strobe from BUFIO2 - leave open if not required
output gclk ; // global clock output from BUFIO2
wire clkint ; //
wire gclk_int ; //
wire freqgen_in_p ; //
wire tx_bufio2_x1 ; //
assign gclk = gclk_int ;
IBUFGDS #(
.DIFF_TERM (DIFF_TERM))
clk_iob_in (
.I (clkin_p),
.IB (clkin_n),
.O (freqgen_in_p));
BUFIO2 #(
.DIVIDE (S), // The DIVCLK divider divide-by value; default 1
.I_INVERT ("FALSE"), //
.DIVIDE_BYPASS ("FALSE"), //
.USE_DOUBLER ("TRUE"))
bufio2_inst1 (
.I (freqgen_in_p), // Input source clock 0 degrees
.IOCLK (ioclkap), // Output Clock for IO
.DIVCLK (tx_bufio2_x1), // Output Divided Clock
.SERDESSTROBE (serdesstrobea)) ; // Output SERDES strobe (Clock Enable)
BUFIO2 #(
.I_INVERT ("TRUE"),
.DIVIDE_BYPASS ("FALSE"), //
.USE_DOUBLER ("FALSE")) //
bufio2_inst2 (
.I (freqgen_in_p), // N_clk input from IDELAY
.IOCLK (ioclkan), // Output Clock
.DIVCLK (), // Output Divided Clock
.SERDESSTROBE ()) ; // Output SERDES strobe (Clock Enable)
BUFIO2 #(
.DIVIDE (S), // The DIVCLK divider divide-by value; default 1
.I_INVERT ("FALSE"), //
.DIVIDE_BYPASS ("FALSE"), //
.USE_DOUBLER ("TRUE")) //
bufio2_inst3 (
.I (freqgen_in_p), // Input source clock 0 degrees
.IOCLK (ioclkbp), // Output Clock for IO
.DIVCLK (), // Output Divided Clock
.SERDESSTROBE (serdesstrobeb)) ; // Output SERDES strobe (Clock Enable)
BUFIO2 #(
.I_INVERT ("TRUE"),
.DIVIDE_BYPASS ("FALSE"), //
.USE_DOUBLER ("FALSE")) //
bufio2_inst4 (
.I (freqgen_in_p), // N_clk input from IDELAY
.IOCLK (ioclkbn), // Output Clock
.DIVCLK (), // Output Divided Clock
.SERDESSTROBE ()) ; // Output SERDES strobe (Clock Enable)
BUFG bufg_tx (.I (tx_bufio2_x1), .O (gclk_int)) ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0); ios_base::sync_with_stdio(0); string s; cin >> s; int c[2]; c[0] = c[1] = 0; const int m[] = {2, 1}; for (int i = 0; i < s.size(); i++) { int d = s[i] - 0 ; cout << ((c[d]++ * m[d]) % 4) + 1 << << d + 1 << n ; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int N = 2e5 + 5; int dist[N]; vector<int> open[N], close[N]; int n, k; bool done[N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> k; for (auto i = 0; i < (long long)(n); i++) { int l, r; cin >> l >> r; open[l].push_back(i); close[r + 1].push_back(i); dist[i] = r + 1; } set<int> pool; set<pair<int, int> > dist_idx; vector<int> res; for (auto i = 1; i < (long long)(N); i++) { for (auto j : close[i]) { if (done[j]) continue; pool.erase(j); dist_idx.erase({dist[j], j}); } for (auto j : open[i]) { pool.insert(j); dist_idx.insert({dist[j], j}); } while (((int)((pool).size())) > k) { auto it = dist_idx.end(); it--; int idx = (*it).second; res.push_back(idx + 1); dist_idx.erase(it); pool.erase(idx); done[idx] = true; } } cout << ((int)((res).size())) << n ; for (auto i : res) cout << i << ; cout << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSTP_SYMBOL_V
`define SKY130_FD_SC_LS__DFSTP_SYMBOL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int pr[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53}; const int m = 16; const int INF = 1e9; int n, d[110], por[110], vv[110], opr[110]; int f[110][65560], to[110][65560], pi[110][65560]; void init() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &d[i]); for (int i = 1; i < 59; i++) { for (int j = 0; j < m; j++) if (!(i % pr[j])) opr[i] |= (1 << j); } for (int i = 0; i <= n; i++) for (int j = 0; j <= 65536; j++) f[i][j] = INF; } int main() { init(); f[0][0] = 0; for (int i = 1; i <= n; i++) { for (int k = 0; k < (1 << m); k++) if (f[i - 1][k] != INF) { for (int j = 1; j < 59; j++) { if (!(k & opr[j]) && f[i][k | opr[j]] > f[i - 1][k] + abs(d[i] - j)) { f[i][k | opr[j]] = f[i - 1][k] + abs(d[i] - j); to[i][k | opr[j]] = k; pi[i][k | opr[j]] = j; } } } } int ss = INF, yu = 0; for (int i = 0; i < (1 << m); i++) if (ss > f[n][i]) ss = f[n][i], yu = i; for (int i = yu, c = n; c > 0; i = to[c][i], c--) vv[c] = pi[c][i]; for (int i = 1; i <= n; i++) printf( %d , vv[i]); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; bool prime[1000001]; const double gr = 1.6180339887; void SieveOfErat(long long int mn) { memset(prime, true, sizeof(prime)); for (long long i = 2; i * i <= mn; i++) { if (prime[i] == true) { for (long long j = i * 2; j <= 1000000; j += i) prime[j] = false; } } } long long int num; signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> num; vector<long long int> v(num); vector<long long int> v1(num); for (long long int i = 0; i < num; i++) { cin >> v[i] >> v1[i]; } sort(v.begin(), v.end()); sort(v1.begin(), v1.end()); long long int val = num; for (long long int i = 0; i < num; i++) { if (v[i] >= v1[i]) val = val + v[i]; else val = val + v1[i]; } cout << val << endl; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 2-to-1 Lookup Table Multiplexer with General Output
// /___/ /\ Filename : MUXF8.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:56 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/04/05 - Rev 0.0.1 Remove input/output bufs; Remove unnessasary begin/end;
// 05/10/07 - When input same, output same for any sel value. (CR434611).
// 08/23/07 - User block statement (CR446704).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module MUXF8 (O, I0, I1, S);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I0, I1, S;
reg O_out;
always @(I0 or I1 or S)
if (S)
O_out = I1;
else
O_out = I0;
assign O = O_out;
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(S => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; namespace FGF { const int N = 1e5 + 5, mo = 1e9 + 7, inv2 = (mo + 1) / 2; int a[N], b[N], pre[N], lst[N], nxt[N], sum[N << 2][4], ta[N << 2][2], n, st[N], tp, mi[N], mx[N], ans, cnt[N]; void pushtag(int ro, int l, int r, int x, int o) { sum[ro][3] = 1ll * x * sum[ro][o ^ 1] % mo; sum[ro][o] = 1ll * (r - l + 1) * x % mo; ta[ro][o] = x; if (!o) sum[ro][2] = 1ll * (r + l) * (r - l + 1) % mo * inv2 % mo * x % mo; } void pushdown(int ro, int l, int r) { for (int i = 0; i <= 1; i++) if (ta[ro][i]) pushtag(ro << 1, l, ((l + r) >> 1), ta[ro][i], i), pushtag(ro << 1 | 1, ((l + r) >> 1) + 1, r, ta[ro][i], i), ta[ro][i] = 0; } void pushup(int ro) { for (int i = 0; i < 4; i++) sum[ro][i] = (sum[ro << 1][i] + sum[ro << 1 | 1][i]) % mo; } void updat(int ro, int l, int r, int L, int R, int x, int o) { if (L <= l && r <= R) return pushtag(ro, l, r, x, o); pushdown(ro, l, r); if (L <= ((l + r) >> 1)) updat(ro << 1, l, ((l + r) >> 1), L, R, x, o); if (R > ((l + r) >> 1)) updat(ro << 1 | 1, ((l + r) >> 1) + 1, r, L, R, x, o); pushup(ro); } int query(int ro, int l, int r, int L, int R, int o) { if (L <= l && r <= R) return sum[ro][o]; pushdown(ro, l, r); return ((L <= ((l + r) >> 1) ? query(ro << 1, l, ((l + r) >> 1), L, R, o) : 0) + (R > ((l + r) >> 1) ? query(ro << 1 | 1, ((l + r) >> 1) + 1, r, L, R, o) : 0)) % mo; } void work() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]), b[i] = a[i]; sort(b + 1, b + n + 1); for (int i = 1; i <= n; i++) a[i] = lower_bound(b + 1, b + n + 1, a[i]) - b; for (int i = 1; i <= n; i++) pre[i] = lst[a[i]] + 1, lst[a[i]] = i; for (int i = n; i; i--) lst[i] = n + 1; for (int i = n; i; i--) nxt[i] = lst[a[i]] - 1, lst[a[i]] = i; for (int i = n; i; i--) { while (tp && pre[i] > pre[st[tp]]) tp--; mx[i] = tp ? st[tp] - 1 : n, st[++tp] = i; } tp = 0; for (int i = n; i; i--) { while (tp && nxt[i] < nxt[st[tp]]) tp--; mi[i] = tp ? st[tp] - 1 : n, st[++tp] = i; } for (int i = n, j = n; i; i--) { updat(1, 1, n, i, mx[i], pre[i], 0), updat(1, 1, n, i, mi[i], nxt[i], 1); cnt[a[i]]++; while (cnt[a[i]] > 1) cnt[a[j]]--, j--; ans = (ans + 1ll * i * query(1, 1, n, i, j, 1) % mo + query(1, 1, n, i, j, 2) - 1ll * i * (i + j) % mo * (j - i + 1) % mo * inv2 % mo - query(1, 1, n, i, j, 3)) % mo; } printf( %d n , (ans + mo) % mo); } } // namespace FGF int main() { FGF::work(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int T = 1; while (T--) { int n, u; cin >> n >> u; vector<int> v; for (int i = 0; i < n; i++) { int t; cin >> t; v.push_back(t); } int I, K, J; double ans = 0.0; for (int i = 0; i < n - 2; i++) { I = v[i]; J = v[i + 1]; K = lower_bound((v).begin(), (v).end(), u + I) - v.begin(); if (K == n) { K = n - 1; } else if (v[K] != u + I) { K--; } K = v[K]; double a = double(K - J) / (K - I); ans = max(a, ans); } if (ans == 0) { cout << -1; exit(0); } printf( %.20f , ans); } return 0; } |
module VGA_Controller ( // Host Side
iRed,
iGreen,
iBlue,
oCurrent_X,
oCurrent_Y,
oAddress,
oRequest,
// VGA Side
oVGA_R,
oVGA_G,
oVGA_B,
oVGA_HS,
oVGA_VS,
oVGA_SYNC,
oVGA_BLANK,
oVGA_CLOCK,
// Control Signal
iCLK,
iRST_N );
// Host Side
input [9:0] iRed;
input [9:0] iGreen;
input [9:0] iBlue;
output [21:0] oAddress;
output [10:0] oCurrent_X;
output [10:0] oCurrent_Y;
output oRequest;
// VGA Side
output [9:0] oVGA_R;
output [9:0] oVGA_G;
output [9:0] oVGA_B;
reg [9:0] VGA_R, VGA_G, VGA_B;
reg [10:0] VGA_X,VGA_Y;
output reg oVGA_HS;
output reg oVGA_VS;
output oVGA_SYNC;
output oVGA_BLANK;
output oVGA_CLOCK;
// Control Signal
input iCLK;
input iRST_N;
// Internal Registers
reg [10:0] H_Cont;
reg [10:0] V_Cont;
////////////////////////////////////////////////////////////
// Horizontal Parameter
parameter H_FRONT = 16;
parameter H_SYNC = 96;
parameter H_BACK = 48;
parameter H_ACT = 640;
parameter H_BLANK = H_FRONT+H_SYNC+H_BACK;
parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;
////////////////////////////////////////////////////////////
// Vertical Parameter
parameter V_FRONT = 11;
parameter V_SYNC = 2;
parameter V_BACK = 31;
parameter V_ACT = 480;
parameter V_BLANK = V_FRONT+V_SYNC+V_BACK;
parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;
////////////////////////////////////////////////////////////
assign oVGA_SYNC = 1'b1; // This pin is unused.
assign oVGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK));
assign oVGA_CLOCK = ~iCLK;
assign oVGA_R = VGA_R;
assign oVGA_G = VGA_G;
assign oVGA_B = VGA_B;
assign oCurrent_X = VGA_X;
assign oCurrent_Y = VGA_Y;
assign oAddress = oCurrent_Y*H_ACT+oCurrent_X;
assign oRequest = ((H_Cont>=H_BLANK && H_Cont<H_TOTAL) &&
(V_Cont>=V_BLANK && V_Cont<V_TOTAL));
//assign oCurrent_X = (H_Cont>=H_BLANK) ? H_Cont-H_BLANK : 11'h0 ;
//assign oCurrent_Y = (V_Cont>=V_BLANK) ? V_Cont-V_BLANK : 11'h0 ;
// Horizontal Generator: Refer to the pixel clock
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
H_Cont <= 0;
oVGA_HS <= 1;
end
else
begin
if(H_Cont<H_TOTAL)
H_Cont <= H_Cont+1'b1;
else
H_Cont <= 0;
// Horizontal Sync
if(H_Cont==H_FRONT-1) // Front porch end
oVGA_HS <= 1'b0;
if(H_Cont==H_FRONT+H_SYNC-1) // Sync pulse end
oVGA_HS <= 1'b1;
end
end
// Vertical Generator: Refer to the horizontal sync
always@(posedge oVGA_HS or negedge iRST_N)
begin
if(!iRST_N)
begin
V_Cont <= 0;
oVGA_VS <= 1;
end
else
begin
if(V_Cont<V_TOTAL)
V_Cont <= V_Cont+1'b1;
else
V_Cont <= 0;
// Vertical Sync
if(V_Cont==V_FRONT-1) // Front porch end
oVGA_VS <= 1'b0;
if(V_Cont==V_FRONT+V_SYNC-1) // Sync pulse end
oVGA_VS <= 1'b1;
end
end
always @(posedge iCLK)
begin
if(H_Cont>=H_BLANK)
VGA_X <= H_Cont-H_BLANK;
else
VGA_X <= 11'h0;
if(V_Cont>=V_BLANK)
VGA_Y <= V_Cont-V_BLANK;
else
VGA_Y <= 11'h0;
if(VGA_X == 320)
begin
VGA_R <= 10'hFfF;
VGA_G <= 10'h0;
VGA_B <= 10'h0;
end
else if(VGA_Y == 240)
begin
VGA_R <= 10'hfFF;
VGA_G <= 10'h0;
VGA_B <= 10'h0;
end
else if(VGA_X == 180)
begin
VGA_R <= 10'hFfF;
VGA_G <= 10'h0;
VGA_B <= 10'h0;
end
else if(VGA_Y == 120)
begin
VGA_R <= 10'hfFF;
VGA_G <= 10'h0;
VGA_B <= 10'h0;
end
else
begin
VGA_R <= iRed;
VGA_G <= iGreen;
VGA_B <= iBlue;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ii = pair<int, int>; using pll = pair<ll, ll>; const int N = 100010; int m, n, q[N], a[N]; int main() { scanf( %d , &m); for (int i = 0; i < m; i++) scanf( %d , &q[i]); scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); int mn = *min_element(q, q + m) + 2; int ans = 0; for (int i = 0; i < n; i++) ans += a[i]; sort(a, a + n); reverse(a, a + n); for (int i = mn - 2; i < n; i += mn) { ans -= a[i]; if (i + 1 < n) ans -= a[i + 1]; } printf( %d n , ans); } |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// Behavioral model for the 32-bit program counter
module program_counter2 (next_pc,rst,clk);
// Output signals...
// Incremented value of the program counter
output [0:31] next_pc;
// ===============================================================
// Input signals
// Clock signal for the program counter
input clk;
// Reset signal for the program counter
input rst;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*/
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:31] next_pc; // Output signals
// ===============================================================
always @(posedge clk)
begin
// If the reset signal sis set to HIGH
if(rst)
begin
// Set its value to ZERO
next_pc<=32'd0;
end
else
begin
next_pc<=next_pc+32'd4;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 11, N = 2e5 + 5; int n, k; int a[N]; map<int, int> rem[M]; long long solve() { long long ans = 0; for (int i = 0; i < n; ++i) { unsigned long long f = 10; int ln = ((int)(to_string(a[i])).size()); for (int l = 1; l < M; ++l) { int r = (k - (int)((f * a[i]) % k)) % k; ans += rem[l][r]; if (l == ln && r == a[i] % k) ans--; f *= 10; } } return ans; } int main() { ios::sync_with_stdio(0); cin.tie(nullptr); cout.tie(nullptr); cin >> n >> k; for (int i = 0; i < n; ++i) { cin >> a[i]; int l = ((int)(to_string(a[i])).size()); rem[l][a[i] % k]++; } cout << solve() << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22OI_2_V
`define SKY130_FD_SC_LP__A22OI_2_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22oi_2 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22OI_2_V
|
#include <bits/stdc++.h> using namespace std; const int N = 110, M = 10010; int n; long double x; int c[N], all; long double binom[N][N]; long double f[N][M]; int main() { cin >> n >> x; for (int i = 1; i <= n; i++) scanf( %d , &c[i]), all += c[i]; f[0][0] = 1; for (int i = 0; i <= n; i++) { binom[i][0] = binom[i][i] = 1; for (int j = 1; j < i; j++) binom[i][j] = binom[i - 1][j] + binom[i - 1][j - 1]; } f[0][0] = 1; for (int id = 1; id <= n; id++) { for (int i = id; i; i--) { for (int j = all; j >= c[id]; j--) { f[i][j] += f[i - 1][j - c[id]]; } } } long double ans = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= all; j++) { long double v = f[i][j]; v /= binom[n][i]; v *= min(x / 2 + x / 2 * n / i, (long double)j / (long double)i); ans += v; } } printf( %.15Lf n , ans); } |
#include <bits/stdc++.h> int main() { int n, s, k = 0; scanf( %d %d , &n, &s); while (s > 0) { s -= n; k++; } printf( %d , k); return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1e5 + 9, lg = 20; int n, q, timer = 1; vector<int> adj[inf], level[inf]; int depth[inf], in[inf], out[inf], parent[inf][lg]; void dfs(int u, int par) { in[u] = timer++; level[depth[u]].push_back(in[u]); for (auto v : adj[u]) if (v != par) parent[v][0] = u, depth[v] = depth[u] + 1, dfs(v, u); out[u] = timer++; } int KthParent(int u, int k) { for (int j = lg - 1; j >= 0; j--) if (k & (1ll << j)) u = parent[u][j]; return u; } int CntLevelInSubtree(int u, int h) { return upper_bound(level[h].begin(), level[h].end(), out[u]) - lower_bound(level[h].begin(), level[h].end(), in[u]); } int main() { cin >> n; for (int i = 1; i <= n; i++) { int tmp; cin >> tmp; if (tmp) adj[tmp].push_back(i), adj[i].push_back(tmp); } for (int i = 1; i <= n; i++) if (!in[i]) dfs(i, 0); for (int j = 1; j < lg; j++) for (int i = 1; i <= n; i++) parent[i][j] = parent[parent[i][j - 1]][j - 1]; cin >> q; while (q--) { int v, p; cin >> v >> p; if (depth[v] < p) { cout << 0 << ; continue; } int u = KthParent(v, p); cout << CntLevelInSubtree(u, depth[v]) - 1 << ; } } |
`timescale 1ns / 1ps
/*
-- Module Name: DES Sbox 5
-- Description: Sbox 5 del algoritmo DES
-- Dependencies: -- none
-- Parameters: -- none
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 05 de Junio 2015
*/
module des_sbox5
(
// -- inputs --------------------------------------------------------- >>>>>
input wire [0:5] right_xor_key_segment_din,
// -- outputs -------------------------------------------------------- >>>>>
output reg [0:3] sbox_dout
);
always @(*)
case ({right_xor_key_segment_din[0], right_xor_key_segment_din[5]})
2'b00:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd2;
4'd1: sbox_dout = 4'd12;
4'd2: sbox_dout = 4'd4;
4'd3: sbox_dout = 4'd1;
4'd4: sbox_dout = 4'd7;
4'd5: sbox_dout = 4'd10;
4'd6: sbox_dout = 4'd11;
4'd7: sbox_dout = 4'd6;
4'd8: sbox_dout = 4'd8;
4'd9: sbox_dout = 4'd5;
4'd10: sbox_dout = 4'd3;
4'd11: sbox_dout = 4'd15;
4'd12: sbox_dout = 4'd13;
4'd13: sbox_dout = 4'd0;
4'd14: sbox_dout = 4'd14;
4'd15: sbox_dout = 4'd9;
endcase
2'b01:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd14;
4'd1: sbox_dout = 4'd11;
4'd2: sbox_dout = 4'd2;
4'd3: sbox_dout = 4'd12;
4'd4: sbox_dout = 4'd4;
4'd5: sbox_dout = 4'd7;
4'd6: sbox_dout = 4'd13;
4'd7: sbox_dout = 4'd1;
4'd8: sbox_dout = 4'd5;
4'd9: sbox_dout = 4'd0;
4'd10: sbox_dout = 4'd15;
4'd11: sbox_dout = 4'd10;
4'd12: sbox_dout = 4'd3;
4'd13: sbox_dout = 4'd9;
4'd14: sbox_dout = 4'd8;
4'd15: sbox_dout = 4'd6;
endcase
2'b10:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd4;
4'd1: sbox_dout = 4'd2;
4'd2: sbox_dout = 4'd1;
4'd3: sbox_dout = 4'd11;
4'd4: sbox_dout = 4'd10;
4'd5: sbox_dout = 4'd13;
4'd6: sbox_dout = 4'd7;
4'd7: sbox_dout = 4'd8;
4'd8: sbox_dout = 4'd15;
4'd9: sbox_dout = 4'd9;
4'd10: sbox_dout = 4'd12;
4'd11: sbox_dout = 4'd5;
4'd12: sbox_dout = 4'd6;
4'd13: sbox_dout = 4'd3;
4'd14: sbox_dout = 4'd0;
4'd15: sbox_dout = 4'd14;
endcase
2'b11:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd11;
4'd1: sbox_dout = 4'd8;
4'd2: sbox_dout = 4'd12;
4'd3: sbox_dout = 4'd7;
4'd4: sbox_dout = 4'd1;
4'd5: sbox_dout = 4'd14;
4'd6: sbox_dout = 4'd2;
4'd7: sbox_dout = 4'd13;
4'd8: sbox_dout = 4'd6;
4'd9: sbox_dout = 4'd15;
4'd10: sbox_dout = 4'd0;
4'd11: sbox_dout = 4'd9;
4'd12: sbox_dout = 4'd10;
4'd13: sbox_dout = 4'd4;
4'd14: sbox_dout = 4'd5;
4'd15: sbox_dout = 4'd3;
endcase
endcase // right_xor_key_segment_din[0], right_xor_key_segment_din[5]
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
des_sbox5 sbox5
(
// -- inputs ------------------------------------------------- >>>>>
.right_xor_key_segment_din (right_xor_key_segment),
// -- outputs ------------------------------------------------ >>>>>
sbox_dout (sbox_dout)
);
*/ |
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; vector<int> arr(n); vector<pair<int, int>> sorted_arr(n); for (int i = 0; i < n; i++) { cin >> arr[i]; sorted_arr[i] = {arr[i], i}; } sort(sorted_arr.begin(), sorted_arr.end()); vector<int> pos(n); for (int i = 0; i < n; i++) { pos[i] = sorted_arr[i].second; } vector<int> next(n), prev(n); next[n - 1] = n; for (int i = n - 2; i >= 0; i--) { int j = i + 1; while (j < n && arr[i] > arr[j]) { j = next[j]; } next[i] = j; } prev[0] = -1; for (int i = 1; i < n; i++) { int j = i - 1; while (j >= 0 && arr[i] > arr[j]) { j = prev[j]; } prev[i] = j; } int ans = 0; for (int i = 1; i < n - 1; i++) { if (i - prev[i] < next[i] - i) { for (int j = prev[i] + 1; j < i; j++) { int k = pos[arr[i] - arr[j] - 1]; if (i < k && k < next[i]) ans++; } } else { for (int j = next[i] - 1; j > i; j--) { int k = pos[arr[i] - arr[j] - 1]; if (prev[i] < k && k < i) ans++; } } } cout << ans; } signed main() { ios_base::sync_with_stdio(false), cin.tie(nullptr), cout.tie(nullptr); solve(); cout << n ; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 50, M = 55; int B, bl[N]; vector<int> bcc[N]; inline void update(int &a, int b) { a = max(a, b); } int n, m, d; int dp[N * M]; char op[N][M]; vector<int> G[N], G2[N], G3[N]; void add(int u, int v, vector<int> G[]) { G[u].push_back(v); } bool vis[N][M]; bool tv[N]; int val[N * M]; int c[N][M], tot; vector<int> path; void dfs(int u, int j, vector<int> G[], int col) { vis[u][j] = 1; c[u][j] = col; if (op[u][j] == 1 && !tv[u]) { tv[u] = 1; ++val[col]; path.push_back(u); } for (int v : G[u]) { if (!vis[v][(j + 1) % d]) dfs(v, (j + 1) % d, G, col); } } void doit(int bid) { for (int bx : bcc[bid]) for (int j = 0; j < d; ++j) if (!vis[bx][j]) { path.clear(); dfs(bx, j, G2, ++tot); for (int x : path) tv[x] = 0; } } int topo(vector<int> G[]) { for (int i = 0; i < B; ++i) { for (int bx : bcc[i]) for (int j = 0; j < d; ++j) { int uc = c[bx][j], u = bx; for (int v : G[u]) { int vc = c[v][(j + d - 1) % d]; update(dp[vc], dp[uc] + val[uc]); } } } int cc = c[0][0]; return dp[cc] + val[cc]; } pair<int, int> e[N]; namespace tarjan { int low[N], dfn[N], clk; void init(int n) { B = clk = 0; memset(dfn, 0, sizeof(int) * (n + 1)); for (int i = 0; i < n; ++i) bcc[i].clear(); } void tarjan(int u) { static int st[N], p; static bool in[N]; dfn[u] = low[u] = ++clk; st[p++] = u; in[u] = true; for (int &v : G[u]) { if (!dfn[v]) { tarjan(v); low[u] = min(low[u], low[v]); } else if (in[v]) low[u] = min(low[u], dfn[v]); } if (dfn[u] == low[u]) { while (1) { int x = st[--p]; in[x] = false; bl[x] = B; bcc[B].push_back(x); if (x == u) break; } ++B; } } void go(int n) { init(n); for (int i = 0; i < n; ++i) { if (!dfn[i]) tarjan(i); } } } // namespace tarjan int main(int argc, char const *argv[]) { scanf( %d%d%d , &n, &m, &d); for (int i = 0; i < m; ++i) { scanf( %d%d , &e[i].first, &e[i].second); --e[i].first; --e[i].second; add(e[i].first, e[i].second, G); } for (int i = 0; i < n; ++i) scanf( %s , op[i]); tarjan::go(n); for (int i = 0; i < m; ++i) { int u = e[i].first, v = e[i].second; if (bl[u] == bl[v]) add(u, v, G2); else add(v, u, G3); } for (int i = 0; i < B; ++i) doit(i); int ans = topo(G3); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int M = 1000000007; const int MM = 998244353; template <typename T, typename U> static inline void amin(T &x, U y) { if (y < x) x = y; } template <typename T, typename U> static inline void amax(T &x, U y) { if (x < y) x = y; } int _runtimeTerror_() { int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } sort(a.begin(), a.end()); string s; cin >> s; vector<int> ans(n + 1); vector<char> dir(n); dir[0] = s[0]; ans[0] = 0; char heavy = s[0]; for (int i = 1; i < n; ++i) { if (s[i] == heavy) { if (i & 1) { dir[i] = L ^ R ^ heavy; ans[i] += 0; ++ans[0]; --ans[i]; } else { dir[i] = heavy; ans[i] += 0; ++ans[0]; --ans[i]; } } else { ans[i] += i; dir[i] = s[i]; ans[i + 1] -= i; } heavy = s[i]; } for (int i = 1; i < n; ++i) { ans[i] += ans[i - 1]; } for (int i = 0; i < n; ++i) { cout << a[ans[i]] << << dir[i] << n ; } return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) _runtimeTerror_(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, i; int a[3007]; while (~scanf( %d , &n)) { for (i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n); for (i = 0; i < n; i++) if (a[i] != i + 1) break; printf( %d n , i + 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e5 + 10, tsz = 5 * maxn, offset = 1e5; vector<int> graph[maxn]; int sz[maxn]; bool big[maxn]; int a[maxn], b[maxn]; long long dp[maxn]; struct Line { int m; long long c; } tree[tsz]; int Left[tsz], Right[tsz], idn = 1, track[tsz], idt = 0; bool exist[tsz]; inline long long f(Line &line, long long x) { return (long long)line.m * (x - offset) + line.c; } void add_line(long long lo, long long hi, Line line, long long node) { if (!exist[node]) track[idt++] = node; exist[node] = 1; if (lo == hi) { if (f(line, lo) < f(tree[node], lo)) tree[node] = line; return; } long long mid = lo + hi >> 1; bool l = f(line, lo) < f(tree[node], lo); bool m = f(line, mid) < f(tree[node], mid); if (m) swap(tree[node], line); if (l != m) { if (!Left[node]) Left[node] = ++idn; add_line(lo, mid, line, Left[node]); } else { if (!Right[node]) Right[node] = ++idn; add_line(mid + 1, hi, line, Right[node]); } } long long query(long long lo, long long hi, long long p, long long node) { if (lo == hi) return f(tree[node], p); long long mid = lo + hi >> 1, ret = f(tree[node], p); if (p <= mid && Left[node]) ret = min(ret, query(lo, mid, p, Left[node])); else if (p > mid && Right[node]) ret = min(ret, query(mid + 1, hi, p, Right[node])); return ret; } void szdfs(long long u, long long p) { sz[u] = 1; for (long long i = 0; i < graph[u].size(); i++) { long long nd = graph[u][i]; if (nd == p) continue; szdfs(nd, u); sz[u] += sz[nd]; } } void add(long long u, long long p) { for (auto v : graph[u]) { if (v != p && !big[v]) { add_line(0, maxn + offset, {b[v], dp[v]}, 1); add(v, u); } } } void dfs(long long u, long long p, bool keep) { long long mx = -1, bigChild = -1; for (auto v : graph[u]) if (v != p && sz[v] > mx) mx = sz[v], bigChild = v; for (auto v : graph[u]) if (v != p && v != bigChild) dfs(v, u, 0); if (bigChild != -1) { dfs(bigChild, u, 1); big[bigChild] = 1; } add(u, p); if (graph[u].size() == 1 && u != 1) dp[u] = 0; else dp[u] = query(0, maxn + offset, a[u] + offset, 1); if (keep) add_line(0, maxn + offset, {b[u], dp[u]}, 1); if (bigChild != -1) big[bigChild] = 0; if (keep == 0) { idn = 1; while (idt) { int node = track[--idt]; tree[node] = {0, (1LL << 62)}; exist[node] = Left[node] = Right[node] = 0; } } } int main() { for (long long i = 0; i < tsz; ++i) tree[i] = {0, (1LL << 62)}; long long n; cin >> n; for (long long i = 1; i <= n; ++i) scanf( %d , &a[i]); for (long long i = 1; i <= n; ++i) scanf( %d , &b[i]); for (long long i = 1; i < n; i++) { long long u, v; scanf( %lld , &u), scanf( %lld , &v); graph[u].push_back(v); graph[v].push_back(u); } szdfs(1, -1); dfs(1, -1, 0); for (long long i = 1; i <= n; ++i) { if (i != 1) printf( ); printf( %lld , dp[i]); } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; char bb[111][111]; int in[111][111]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) scanf( %s , bb[i]); vector<pair<pair<int, int>, int>> stars; for (int i = 1; i < n - 1; i++) { for (int j = 1; j < m - 1; j++) { if (bb[i][j] != * ) continue; int l, r, u, d; l = r = i; u = d = j; for (int k = i; k < n; k++) if (bb[k][j] == * ) r = k; else break; for (int k = i; k >= 0; k--) if (bb[k][j] == * ) l = k; else break; for (int k = j; k < m; k++) if (bb[i][k] == * ) d = k; else break; for (int k = j; k >= 0; k--) if (bb[i][k] == * ) u = k; else break; int starLevel = min(min(r - i, i - l), min(d - j, j - u)); if (starLevel) { for (int k = i - starLevel; k <= i + starLevel; k++) in[k][j] = 1; for (int k = j - starLevel; k <= j + starLevel; k++) in[i][k] = 1; stars.push_back({{i + 1, j + 1}, starLevel}); } } } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if ((bb[i][j] == * && in[i][j] == 0) || (in[i][j] == 1 && bb[i][j] == . )) return puts( -1 ); cout << stars.size() << endl; for (auto u : stars) { printf( %d %d %d n , u.first.first, u.first.second, u.second); } return 0; } |
#include <bits/stdc++.h> int main() { long i, n, d = 0; scanf( %ld , &n); for (i = 1; i <= n / 2; i++) { if (n % i == 0) d++; } printf( %d , d); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__HA_1_V
`define SKY130_FD_SC_LP__HA_1_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ha_1 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ha_1 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__HA_1_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
//`include "mono_data_rx/mono_data_rx_core.v"
module mono_data_rx
#(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter IDENTYFIER = 2'b00
)(
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire [63:0] TIMESTAMP,
input wire CLK_BX,
input wire RX_TOKEN, RX_DATA, RX_CLK,
output wire RX_READ, RX_FREEZE,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
output wire LOST_ERROR
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #( .BASEADDR(BASEADDR), .HIGHADDR(HIGHADDR), .ABUSWIDTH(ABUSWIDTH) ) i_bus_to_ip
(
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
mono_data_rx_core
#(
.ABUSWIDTH(ABUSWIDTH),
.IDENTYFIER(IDENTYFIER)
) mono_data_rx_core
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CLK_BX(CLK_BX),
.RX_TOKEN(RX_TOKEN),
.RX_DATA(RX_DATA),
.RX_CLK(RX_CLK),
.RX_READ(RX_READ),
.RX_FREEZE(RX_FREEZE),
.TIMESTAMP(TIMESTAMP),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.LOST_ERROR(LOST_ERROR)
);
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_xlconcat_0_1,xlconcat_v2_1_1_xlconcat,{}" *)
(* CORE_GENERATION_INFO = "zqynq_lab_1_design_xlconcat_0_1,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WI\
DTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=2,NUM_PORTS=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zqynq_lab_1_design_xlconcat_0_1 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long s, x; string S, X; long long dp[64][2]; long long d__p(int i, int st) { if (i == S.size() && st) return 0; else if (i == S.size()) return 1; long long &res = dp[i][st]; if (res != -1) return res; res = 0; int x = S[i] - 0 ; int y = X[i] - 0 ; for (int a = 0; a <= 1; a++) { for (int b = 0; b <= 1; b++) { int remember = (a + b + st) > 1; int Sum = a + b + st; Sum %= 2; int Xor = a ^ b; if (Sum != x || Xor != y) continue; res += d__p(i + 1, remember); } } return res; } int main() { cin >> s >> x; for (int i = 63; i >= 0; i--) { if (s & (1LL << i)) S += 1 ; else S += 0 ; if (x & (1LL << i)) X += 1 ; else X += 0 ; } reverse(S.begin(), S.end()); reverse(X.begin(), X.end()); memset(dp, -1, sizeof dp); cout << d__p(0, 0) - 2 * (s == x); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, d; cin >> n >> d; int t; cin >> t; while (t--) { long long int x, y; cin >> x >> y; long long int eq1 = y * (n - d) - ((n - d) * (x - d)); long long int eq2 = (y - (n - d)) + (x - (n)); long long int eq3 = ((y - n) - (x - (n - d))); long long int eq4 = (y - d) + (x); if (eq1 >= 0 && eq2 <= 0 && eq3 <= 0 && eq4 >= 0) cout << YES n ; else cout << NO n ; } } |
#include <bits/stdc++.h> using namespace std; const long double EPS = (long double)1e-7; const long double PI = acos(0) * 2; bool isZero(const long double& x) { return abs(x) <= EPS; } int sign(const long double& x) { return isZero(x) ? 0 : (0 < x ? 1 : -1); } long long gcd(long long a, long long b) { for (; b; a %= b, swap(a, b)) { } return abs(a); } pair<long long, long long> operator+(const pair<long long, long long>& a, const pair<long long, long long>& b) { return pair<long long, long long>(a.first + b.first, a.second + b.second); } pair<long long, long long> operator-(const pair<long long, long long>& a, const pair<long long, long long>& b) { return pair<long long, long long>(a.first - b.first, a.second - b.second); } pair<long long, long long> operator*(const pair<long long, long long>& a, const long long& b) { return pair<long long, long long>(a.first * b, a.second * b); } long long operator*(const pair<long long, long long>& a, const pair<long long, long long>& b) { return a.first * b.second - b.first * a.second; } long long ccw(const pair<long long, long long>& a, const pair<long long, long long>& b, const pair<long long, long long>& c) { return a * b + b * c + c * a; } void fg(vector<int> G[], int a, int b) { G[a].emplace_back(b); G[b].emplace_back(a); } void fg(vector<pair<int, int> > G[], int a, int b, int c) { G[a].emplace_back(b, c); G[b].emplace_back(a, c); } long long A, B, C; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> A >> B >> C; if (!A && !B) { puts(C ? 0 : -1 ); exit(0); } if (!A) { printf( 1 n%.10lf n , double(-C) / B); exit(0); } long long D = B * B - 4 * A * C; if (D < 0) { puts( 0 ); exit(0); } if (!D) { printf( 1 n%.10lf n , double(-B) / A / 2); exit(0); } if (A < 0) { A = -A; B = -B; C = -C; } printf( 2 n%.10lf n%.10lf n , double(-B - sqrt(D)) / A / 2, double(-B + sqrt(D)) / A / 2); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__AND3_PP_BLACKBOX_V
/**
* and3: 3-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, m, len; int arr[110]; int brr[110]; int main() { int i, j, k, t, a, b; ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); cin >> n >> m; for (i = 0; i < m; i++) { memset(arr, 0, sizeof(arr)); for (j = 0; j < n; j++) { cin >> arr[j]; } int winner = -1; int maxz = -1; for (j = 0; j < n; j++) { if (arr[j] > maxz) { maxz = arr[j]; winner = j; } } brr[winner]++; } int winner = -1; int maxz = -1; for (i = 0; i < n; i++) { if (brr[i] > maxz) { maxz = brr[i]; winner = i; } } cout << winner + 1 << n ; return 0; } |
`timescale 1ns / 1ps
/* All files are owned by Kris Kalavantavanich.
* Feel free to use/modify/distribute in the condition that this copyright header is kept unmodified.
* Github: https://github.com/kkalavantavanich/SD2017 */
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 05/19/2017 10:23:10 PM
// Design Name: SPI_SEND
// Module Name: spiSend
// Project Name: SD_2017
// Target Devices: Xilinx Basys3
// Description: Submodule of main.v. Send 48-bit cmd command `CMD`. Output is in `bitout`.
// Sending process will start on `start` HIGH (synchronous with negedge)
// Process finish is notified by `finish` HIGH (synchronous with negedge)
// Dependencies: main.v
// Revision: 1.00
// Revision 1.00 - Finished Read Operation
// Revision 0.01 - File Created
// Additional Comments: SET ON NEGEDGE!!!!
//////////////////////////////////////////////////////////////////////////////////
module spiSend(
spiClock,
start,
cmd,
bitout,
finish
);
parameter byteSize = 6;
// 'public' variables
input spiClock;
input start;
input [(byteSize * 8) - 1:0] cmd;
output bitout;
output reg finish;
// 'private' variables
wire _start;
assign _start = start;
reg _running = 0, _waiting = 0;
reg [(byteSize * 8) - 1:0] _cmdBuffer;
reg [byteSize - 1:0] _i;
assign bitout = _running ? _cmdBuffer[47] : 1'b1; /// active low
reg _error = 0;
// main //
always @ (negedge spiClock) begin
if (_start && ~_running && ~_waiting) begin
// initial
finish <= 0;
_cmdBuffer <= cmd; // cmd always start with 0
_running <= 1;
_i <= 47; // this loop sends a `0`
end else if (_start && _running && ~_waiting) begin
// looping
_i = _i - 1;
_cmdBuffer = _cmdBuffer << 1;
if (_i == 0) begin
// end
_running <= 0;
_waiting <= 1;
end
end else if (_start && _waiting) begin
finish <= 1;
end else if (~_start) begin
finish <= 0;
_waiting <= 0;
end else begin
_error = 1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, ans = 0; string s; cin >> n; while (cin >> s) { int cnt = 0; for (int i = 0; i < s.length(); ++i) { if (s[i] >= A && s[i] <= Z ) { ++cnt; } } ans = max(ans, cnt); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; cout << 0 0 << endl; int l = 1, r = (int)1e9, mid = l + (r - l) / 2; string s; cin >> s; int first; if (s[0] == b ) { first = 0; } else { first = 1; } for (int i = 1; i < n; i++) { cout << mid << << mid << endl; cin >> s; if ((s[0] == w ) == first) { l = mid + 1; } else { r = mid; } mid = l + (r - l) / 2; } if (l >= r && mid != (int)1e9) { cout << mid - 1 << << mid << << mid << << mid - 1 << endl; } else { cout << mid << << 0 << << mid << << 1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e3, MOD = 1e9 + 7, UNDEF = -1; int readInt() { bool minus = false; int result = 0; char ch; ch = getchar(); while (true) { if (ch == - ) break; if (ch >= 0 && ch <= 9 ) break; ch = getchar(); } if (ch == - ) minus = true; else result = ch - 0 ; while (true) { ch = getchar(); if (ch < 0 || ch > 9 ) break; result = result * 10 + (ch - 0 ); } if (minus) return -result; else return result; } char readChar() { char result = getchar(); while (isspace(result)) { result = getchar(); } return result; } char w[N + 1][N + 1]; pair<pair<short, short>, pair<short, short> > cur; int n, m; int dp1[2 * N + 1][2 * N + 1], dp2[2 * N + 1][2 * N + 1]; int S[2 * N + 1], cnt[2 * N + 1]; int curx, cury; bool ispal(string s) { string d = s; reverse(s.begin(), s.end()); return d == s; } int o(int x1, int y1) { return x1 + S[x1 + y1] - S[x1 + y1 - 1]; } void add(int x1, int y1, int x2, int y2) { dp1[curx][cury] += dp2[o(x1, y1)][o(x2, y2)]; if (dp1[curx][cury] >= MOD) { dp1[curx][cury] -= MOD; } } vector<pair<short, short> > p1[2 * N + 1], p2[2 * N + 1]; int main() { n = readInt(), m = readInt(); int s = (n + m - 2) / 2; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cnt[i + j]++; w[i][j] = readChar(); p1[i + j - 2].push_back(make_pair(i, j)); p2[n + m - 2 - (i + j - 2)].push_back(make_pair(i, j)); } } for (int i = 2; i <= n + m; i++) { S[i] = S[i - 1] + cnt[i]; } if (w[1][1] != w[n][m]) { cout << 0; return 0; } int ans = n * n + 2 * (n - 1) * n; for (int i = s; i >= 0; i--) { for (int j = 0; j < p1[i].size(); j++) { for (int k = 0; k < p2[i].size(); k++) { int x1, y1, x2, y2; x1 = p1[i][j].first; y1 = p1[i][j].second; x2 = p2[i][k].first; y2 = p2[i][k].second; if (w[x1][y1] == w[x2][y2]) { if (x1 <= x2 && y1 <= y2) { if (x2 - x1 + y2 - y1 <= 1) { dp1[o(x1, y1)][o(x2, y2)] = 1; } else { curx = o(x1, y1); cury = o(x2, y2); if (x1 == x2) { add(x1, y1 + 1, x2, y2 - 1); } else if (y1 == y2) { add(x1 + 1, y1, x2 - 1, y2); } else { add(x1, y1 + 1, x2 - 1, y2); add(x1 + 1, y1, x2, y2 - 1); if (y2 - 1 >= y1 + 1) { add(x1, y1 + 1, x2, y2 - 1); } if (x2 - 1 >= x1 + 1) { add(x1 + 1, y1, x2 - 1, y2); } } } } } } } for (int i = 0; i <= 2 * n + m; i++) { for (int j = 0; j <= 2 * n + m; j++) { dp2[i][j] = dp1[i][j]; dp1[i][j] = 0; } } } cout << dp2[o(1, 1)][o(n, m)]; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); vector<int> a(n); long long sum = 0; for (int& x : a) { scanf( %d , &x); sum += x; } if (sum != 0) { puts( YES ); puts( 1 ); printf( %d %d n , 1, n); exit(0); } sum = 0; for (int i = 0; i < n; i++) { sum += a[i]; if (sum != 0) { puts( YES ); puts( 2 ); printf( %d %d n , 1, i + 1); printf( %d %d n , i + 2, n); exit(0); } } puts( NO ); } |
#include <bits/stdc++.h> using namespace std; const int N = 100100; int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } int tree[N << 2]; void pushup(int ind) { tree[ind] = gcd(tree[ind << 1], tree[ind << 1 | 1]); } int a[N]; void build(int ind, int ll, int rr) { if (ll == rr) { tree[ind] = a[ll]; return; } int mid = (ll + rr) >> 1; build(((ind) << 1), ll, mid); build(((ind) << 1 | 1), mid + 1, rr); pushup(ind); } int query(int ind, int ll, int rr, int l, int r) { if (ll == l && rr == r) { return tree[ind]; } int mid = (ll + rr) >> 1; if (r <= mid) { return query(((ind) << 1), ll, mid, l, r); } else if (l > mid) { return query(((ind) << 1 | 1), mid + 1, rr, l, r); } else { int a = query(((ind) << 1), ll, mid, l, mid); int b = query(((ind) << 1 | 1), mid + 1, rr, mid + 1, r); return gcd(a, b); } } pair<int, int> re[N]; int t[N], w[N], cnt; struct PBT { int ls[N * 20], rs[N * 20], c[N * 20], tree[N * 20]; int idx, mx; int build(int l, int r) { int rt = idx++; c[rt] = 0; if (l != r) { int mid = (l + r) >> 1; ls[rt] = build(l, mid); rs[rt] = build(mid + 1, r); } return rt; } int update(int rt, int pos, int val) { int nrt = idx++, ret = nrt; c[nrt] = c[rt] + val; int l = 1, r = mx; while (l != r) { int mid = (l + r) >> 1; if (pos <= mid) { ls[nrt] = idx++; rs[nrt] = rs[rt]; nrt = ls[nrt]; rt = ls[rt]; r = mid; } else { rs[nrt] = idx++; ls[nrt] = ls[rt]; nrt = rs[nrt]; rt = rs[rt]; l = mid + 1; } c[nrt] = c[rt] + val; } return ret; } int query(int lrt, int rrt, int pos) { int l = 1, r = mx; while (l != r) { int mid = (l + r) >> 1; if (pos <= mid) { lrt = ls[lrt]; rrt = ls[rrt]; r = mid; } else { lrt = rs[lrt]; rrt = rs[rrt]; l = mid + 1; } } return c[rrt] - c[lrt]; } } pbt; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } build(1, 1, n); int q; scanf( %d , &q); for (int i = 0; i < q; i++) { scanf( %d%d , &re[i].first, &re[i].second); t[++cnt] = query(1, 1, n, re[i].first, re[i].second); w[i] = t[cnt]; } sort(t + 1, t + cnt + 1); cnt = unique(t + 1, t + cnt + 1) - t - 1; map<int, int> idx; for (int i = 1; i <= cnt; i++) { idx[t[i]] = i; } pbt.mx = cnt; pbt.tree[0] = pbt.build(1, cnt); for (int i = 1; i <= n; i++) { if (idx.count(a[i])) { int x = idx[a[i]]; pbt.tree[i] = pbt.update(pbt.tree[i - 1], x, 1); } else { pbt.tree[i] = pbt.tree[i - 1]; } } for (int i = 0; i < q; i++) { int x = re[i].first, y = re[i].second; int ret = pbt.query(pbt.tree[x - 1], pbt.tree[y], idx[w[i]]); printf( %d n , re[i].second - re[i].first + 1 - ret); } return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_app_v6.v
// Version : 1.7
//--
//-- Description: PCI Express Endpoint sample application
//-- design.
//--
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
`define PCI_EXP_EP_OUI 24'h000A35
`define PCI_EXP_EP_DSN_1 {{8'h1},`PCI_EXP_EP_OUI}
`define PCI_EXP_EP_DSN_2 32'h00000001
module pcie_app_v6
(
input trn_clk,
input trn_reset_n,
input trn_lnk_up_n,
// Tx
input [5:0] trn_tbuf_av,
input trn_tcfg_req_n,
input trn_terr_drop_n,
input trn_tdst_rdy_n,
output [63:0] trn_td,
output trn_trem_n,
output trn_tsof_n,
output trn_teof_n,
output trn_tsrc_rdy_n,
output trn_tsrc_dsc_n,
output trn_terrfwd_n,
output trn_tcfg_gnt_n,
output trn_tstr_n,
// Rx
input [63:0] trn_rd,
input trn_rrem_n,
input trn_rsof_n,
input trn_reof_n,
input trn_rsrc_rdy_n,
input trn_rsrc_dsc_n,
input trn_rerrfwd_n,
input [6:0] trn_rbar_hit_n,
output trn_rdst_rdy_n,
output trn_rnp_ok_n,
// Flow Control
input [11:0] trn_fc_cpld,
input [7:0] trn_fc_cplh,
input [11:0] trn_fc_npd,
input [7:0] trn_fc_nph,
input [11:0] trn_fc_pd,
input [7:0] trn_fc_ph,
output [2:0] trn_fc_sel,
input [31:0] cfg_do,
input cfg_rd_wr_done_n,
output [31:0] cfg_di,
output [3:0] cfg_byte_en_n,
output [9:0] cfg_dwaddr,
output cfg_wr_en_n,
output cfg_rd_en_n,
output cfg_err_cor_n,
output cfg_err_ur_n,
output cfg_err_ecrc_n,
output cfg_err_cpl_timeout_n,
output cfg_err_cpl_abort_n,
output cfg_err_cpl_unexpect_n,
output cfg_err_posted_n,
output cfg_err_locked_n,
output [47:0] cfg_err_tlp_cpl_header,
input cfg_err_cpl_rdy_n,
output cfg_interrupt_n,
input cfg_interrupt_rdy_n,
output cfg_interrupt_assert_n,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_turnoff_ok_n,
input cfg_to_turnoff_n,
output cfg_trn_pending_n,
output cfg_pm_wake_n,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number,
input [15:0] cfg_status,
input [15:0] cfg_command,
input [15:0] cfg_dstatus,
input [15:0] cfg_dcommand,
input [15:0] cfg_lstatus,
input [15:0] cfg_lcommand,
input [15:0] cfg_dcommand2,
input [2:0] cfg_pcie_link_state_n,
output [1:0] pl_directed_link_change,
input [5:0] pl_ltssm_state,
output [1:0] pl_directed_link_width,
output pl_directed_link_speed,
output pl_directed_link_auton,
output pl_upstream_prefer_deemph,
input [1:0] pl_sel_link_width,
input pl_sel_link_rate,
input pl_link_gen2_capable,
input pl_link_partner_gen2_supported,
input [2:0] pl_initial_link_width,
input pl_link_upcfg_capable,
input [1:0] pl_lane_reversal_mode,
input pl_received_hot_rst,
output [63:0] cfg_dsn
);
wire [7:0] trn_trem;
//
// Core input tie-offs
//
assign trn_fc_sel = 3'b0;
assign trn_rnp_ok_n = 1'b0;
assign trn_terrfwd_n = 1'b1;
assign trn_tcfg_gnt_n = 1'b0;
assign trn_tecrc_gen_n = 1'b1;
assign cfg_err_cor_n = 1'b1;
assign cfg_err_ur_n = 1'b1;
assign cfg_err_ecrc_n = 1'b1;
assign cfg_err_cpl_timeout_n = 1'b1;
assign cfg_err_cpl_abort_n = 1'b1;
assign cfg_err_cpl_unexpect_n = 1'b1;
assign cfg_err_posted_n = 1'b0;
assign cfg_err_locked_n = 1'b1;
assign cfg_pm_wake_n = 1'b1;
assign cfg_trn_pending_n = 1'b1;
assign trn_tstr_n = 1'b0;
assign cfg_interrupt_assert_n = 1'b1;
assign cfg_interrupt_n = 1'b1;
assign cfg_dwaddr = 0;
assign cfg_rd_en_n = 1;
assign pl_directed_link_change = 0;
assign pl_directed_link_width = 0;
assign pl_directed_link_speed = 0;
assign pl_directed_link_auton = 0;
assign pl_upstream_prefer_deemph = 1'b1;
assign cfg_interrupt_di = 8'b0;
assign cfg_err_tlp_cpl_header = 47'h0;
assign cfg_di = 0;
assign cfg_byte_en_n = 4'hf;
assign cfg_wr_en_n = 1;
assign cfg_dsn = {`PCI_EXP_EP_DSN_2, `PCI_EXP_EP_DSN_1};
assign trn_trem_n = (trn_trem == 8'h0F) ? 1'b1 : 1'b0;
//
// Programmable I/O Module
//
wire [15:0] cfg_completer_id = { cfg_bus_number, cfg_device_number, cfg_function_number };
wire cfg_bus_mstr_enable = cfg_command[2];
PIO PIO (
.trn_clk ( trn_clk ), // I
.trn_reset_n ( trn_reset_n ), // I
.trn_lnk_up_n ( trn_lnk_up_n ), // I
.trn_td ( trn_td ), // O [63:0]
.trn_trem_n ( trn_trem ), // O [7:0]
.trn_tsof_n ( trn_tsof_n ), // O
.trn_teof_n ( trn_teof_n ), // O
.trn_tsrc_rdy_n ( trn_tsrc_rdy_n ), // O
.trn_tsrc_dsc_n ( trn_tsrc_dsc_n ), // O
.trn_tdst_rdy_n ( trn_tdst_rdy_n ), // I
.trn_tdst_dsc_n ( 1'b1 ), // I
.trn_rd ( trn_rd ), // I [63:0]
.trn_rrem_n ( (trn_rrem_n == 1'b1) ? 8'h0F : 8'h00), // I [7:0]
.trn_rsof_n ( trn_rsof_n ), // I
.trn_reof_n ( trn_reof_n ), // I
.trn_rsrc_rdy_n ( trn_rsrc_rdy_n ), // I
.trn_rsrc_dsc_n ( trn_rsrc_dsc_n ), // I
.trn_rdst_rdy_n ( trn_rdst_rdy_n ), // O
.trn_rbar_hit_n ( trn_rbar_hit_n ), // I [6:0]
.cfg_to_turnoff_n ( cfg_to_turnoff_n ), // I
.cfg_turnoff_ok_n ( cfg_turnoff_ok_n ), // O
.cfg_completer_id ( cfg_completer_id ), // I [15:0]
.cfg_bus_mstr_enable (cfg_bus_mstr_enable ) // I
);
endmodule // pcie_app
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x; cin >> n; if (n % 2 == 0) { x = n / 2; cout << x * (x + 1); } else { x = (n + 1) / 2; cout << (x - 1) * x + x; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); printf( %d n , (n + 1) / 2); return 0; } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart #(
//parameter csr_addr = 4'h0,
parameter clk_freq = 100000000,
parameter baud = 115200
) (
//cpu_read_write
//wb_input
input [31:0] dat_i,
input [31:0] adr_i,
input we_i,
input stb_i,
//wb_output
output reg [31:0] dat_o,
output ack_o,
input sys_clk,
input sys_rst,
output rx_irq,
output tx_irq,
input uart_rx,
output uart_tx,
input rx_iack
);
reg [15:0] divisor;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_wr;
wire rx_done, tx_done;
wire tx_busy;
wire full_rx, full_tx, empty_rx, empty_tx;
reg thru = 0;
wire uart_tx_transceiver;
wire [7:0] rx_data_out;
reg fifo_rx_wr = 0;
reg tmpflag = 0;
wire fifo_rx_rd;
reg fifo_rd_once = 0;
wire [7:0] tx_data_out;
wire fifo_tx_rd;
reg tran_tx_wr = 0;
reg fifo_busy;
wire uart_wr;
uart_transceiver transceiver(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.uart_rx(uart_rx),
.uart_tx(uart_tx_transceiver),
.divisor(divisor),
.rx_data(rx_data),
.rx_done(rx_done),
.tx_data(tx_data_out),
.tx_wr(tran_tx_wr),
.tx_done(tx_done),
.tx_busy(tx_busy),
.rx_busy(rx_busy)
);
// always @(posedge sys_clk) begin
// if(rx_done & ~fifo_rx_wr) fifo_rx_wr = 1;
// else if(~rx_done & fifo_rx_wr & ~tmpflag) begin
// fifo_rx_wr = 1;
// tmpflag = 1;
// end
// else if(tmpflag) begin
// fifo_rx_wr = 0;
// tmpflag = 0;
// end
// end
always @(posedge sys_clk) begin
if(rx_done) fifo_rx_wr = 1;
else fifo_rx_wr = 0;
end
assign fifo_rx_rd = rx_wr & ~fifo_rd_once;
always @(posedge sys_clk) begin
if(rx_wr) fifo_rd_once = 1;
else fifo_rd_once = 0;
end
assign rx_irq = full_rx & ~rx_iack;
uart_fifo fifo_rx (
.clk(sys_clk), // input clk
.rst(sys_rst), // input rst
.din(rx_data), // input [7 : 0] din
.wr_en(fifo_rx_wr), // input wr_en
.rd_en(fifo_rx_rd), // input rd_en
.dout(rx_data_out), // output [7 : 0] dout
.full(full_rx), // output full
.empty(empty_rx), // output empty
.data_count() // output [7 : 0] data_count
);
assign fifo_tx_rd = ~tx_busy & ~empty_tx;
always @(posedge sys_clk) begin
tran_tx_wr = fifo_tx_rd;
end
always @(posedge sys_clk) begin
if(tx_wr) fifo_busy = 1;
else fifo_busy = 0;
end
//assign tx_irq = full_tx;
uart_fifo fifo_tx (
.clk(sys_clk), // input clk
.rst(sys_rst), // input rst
.din(tx_data), // input [7 : 0] din
.wr_en(tx_wr & ~fifo_busy), // input wr_en
.rd_en(tran_tx_wr & tx_done/*fifo_tx_rd*/), // input rd_en
.dout(tx_data_out), // output [7 : 0] dout
.full(full_tx), // output full
.empty(empty_tx), // output empty
.data_count() // output [7 : 0] data_count
);
assign uart_tx = thru ? uart_rx : uart_tx_transceiver;
/* CSR interface */
//wire csr_selected = csr_a[13:10] == csr_addr;
assign tx_data = dat_i[7:0];
//assign tx_wr = csr_selected & csr_we & (csr_a[1:0] == 2'b00);
assign tx_wr = stb_i & ack_o & we_i & (adr_i[1:0] == 2'b00);
assign rx_wr = stb_i & ack_o & ~we_i & (adr_i[1:0] == 2'b00) & ~empty_rx;
parameter default_divisor = clk_freq/baud/16;
assign ack_o = stb_i & (we_i?~full_tx:1) ;//& ((we_i&~full_tx) | (~we_i&~empty_rx));
assign uart_wr = stb_i && ack_o;
always @(posedge sys_clk or posedge sys_rst) begin
if(sys_rst) begin
divisor <= default_divisor;
dat_o <= 32'd0;
end else if(uart_wr) begin
dat_o <= 32'd0;
case(adr_i[1:0])
2'b00: if(rx_wr) begin dat_o <= {23'h0, 1'b1, rx_data_out}; end
2'b01: dat_o <= divisor;
2'b10: dat_o <= thru;
endcase
if(we_i/*csr_we*/) begin
case(adr_i[1:0])
2'b00:; /* handled by transceiver */
2'b01: divisor <= dat_i[15:0];
2'b10: thru <= dat_i[0];
endcase
end
end
end
//always @(posedge sys_clk) begin
// if(sys_rst) begin
// divisor <= default_divisor;
// dat_o <= 32'd0;
// end else begin
// dat_o <= 32'd0;
// if(stb_i && ack_o/*csr_selected*/) begin
// case(adr_i[1:0])
// 2'b00: dat_o <= rx_data;
// 2'b01: dat_o <= divisor;
// 2'b10: dat_o <= thru;
// endcase
// if(we_i/*csr_we*/) begin
// case(adr_i[1:0])
// 2'b00:; /* handled by transceiver */
// 2'b01: divisor <= dat_i[15:0];
// 2'b10: thru <= dat_i[0];
// endcase
// end
// end
// end
//end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
integer i;
string v;
// verilator lint_off UNUSED
integer unused[];
// verilator lint_on UNUSED
typedef bit [7:0] byte_t;
byte_t a[];
byte_t b[];
// wide data array
typedef struct packed {
logic [15:0] header;
logic [223:0] payload;
logic [15:0] checksum;
} pck256_t;
pck256_t p256[];
string s[] = { "hello", "sad", "world" };
always @ (posedge clk) begin
cyc <= cyc + 1;
begin
`checkh(a.size, 0);
v = $sformatf("%p", a); `checks(v, "'{}");
`checkh(s.size, 3);
`checks(s[0], "hello");
`checks(s[1], "sad");
`checks(s[2], "world");
a = new [3];
`checkh(a.size, 3);
a[0] = 10;
a[1] = 11;
a[2] = 12;
`checkh(a[0], 10);
`checkh(a[1], 11);
`checkh(a[2], 12);
v = $sformatf("%p", a); `checks(v, "'{'ha, 'hb, 'hc} ");
a.delete;
`checkh(a.size, 0);
a = '{15, 16};
`checkh(a.size, 2);
`checkh(a[0], 15);
`checkh(a[1], 16)
a = {17, 18};
`checkh(a.size, 2);
`checkh(a[0], 17);
`checkh(a[1], 18)
a = '{17};
`checkh(a.size, 1); // IEEE says resizes to smallest that fits pattern
`checkh(a[0], 17);
a = new[2];
a[0] = 5;
a[1] = 6;
`checkh(a[0], 5);
`checkh(a[1], 6);
a = new[2];
`ifdef verilator // bug2618
a[0] = 0;
a[1] = 0;
`endif
`checkh(a[0], 0);
`checkh(a[1], 0);
a[0] = 5;
a[1] = 6;
`checkh(a[0], 5);
`checkh(a[1], 6);
b = new [4](a);
`checkh(b.size, 4);
`checkh(b[0], 5);
`checkh(b[1], 6);
`ifdef verilator // bug2618
b[2] = 0;
b[3] = 0;
`endif
`checkh(b[2], 0);
`checkh(b[3], 0);
a = b;
`checkh(a.size, 4);
`checkh(a[0], 5);
`checkh(a[1], 6);
`checkh(a[2], 0);
`checkh(a[3], 0);
a = new [0];
`checkh(a.size, 0);
b = new [4](a);
`checkh(b.size, 4);
`ifdef verilator // bug2618
b[0] = 0;
b[1] = 0;
b[2] = 0;
b[3] = 0;
`endif
`checkh(b[0], 0);
`checkh(b[1], 0);
`checkh(b[2], 0);
`checkh(b[3], 0);
a = new[4] ('{8'd1,8'd2,8'd3,8'd4});
`checkh(a.size, 4);
`checkh(a[0], 1);
`checkh(a[1], 2);
`checkh(a[2], 3);
`checkh(a[3], 4);
i = 0;
foreach (a[j]) i += int'(a[j]);
`checkh(i, 1 + 2 + 3 + 4);
// test wide dynamic array
p256 = new [11];
`checkh(p256.size, 11);
`checkh(p256.size(), 11);
p256[1].header = 16'hcafe;
p256[1].payload = {14{16'hbabe}};
p256[1].checksum = 16'hdead;
`checkh(p256[1].header, 16'hcafe);
`checkh(p256[1], {16'hcafe,{14{16'hbabe}},16'hdead});
//X's: `checkh(p256[0], 'x);
p256[5] = '1;
`checkh(p256[5], {32{8'hff}});
p256[5].header = 16'h2;
`checkh(p256[5], {16'h2,{30{8'hff}}});
p256[2] = ( p256[5].header == 2 ) ? p256[1] : p256[5];
`checkh(p256[2], {16'hcafe,{14{16'hbabe}},16'hdead});
p256.delete();
`checkh(p256.size, 0);
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n & 1) { cout << Ehab ; } else { cout << Mahmoud ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int dist[600 + 15][600 + 15]; int start[200 + 15]; int MAX_ = INT_MAX / 2 - 5; vector<pair<int, int> > sas[1000]; int cap[250000 + 15]; int v, e, n, k; int pop_w[1000]; int pop_kr[1000]; int group[1000]; int last_checked[1000]; int dead[1000]; int res; int num = 0; bool b = 0; int to_add; bool DFS(int w, int bneck) { if (w == n + v + 2) { to_add = bneck; res += to_add; return 1; } for (int i = last_checked[w] + 1; i < sas[w].size(); i++) { int do_ = sas[w][i].first; int neck = min(bneck, cap[sas[w][i].second]); last_checked[w] = i; if (neck && !dead[do_]) if (DFS(do_, neck)) { cap[sas[w][i].second] -= to_add; cap[sas[w][i].second ^ 1] += to_add; return 1; } } return 0; } int DINIC() { for (int i = 0; i <= n + v + 3; i++) { group[i] = -1; dead[i] = 0; last_checked[i] = -1; } queue<pair<int, int> > q; q.push({0, 0}); group[0] = 0; while (!q.empty()) { int top_w = q.front().first; int top_g = q.front().second; q.pop(); for (int i = 0; i < sas[top_w].size(); i++) if (group[sas[top_w][i].first] == -1) { group[sas[top_w][i].first] = top_g + 1; q.push({sas[top_w][i].first, top_g + 1}); } } int ile = 0; while (DFS(0, INT_MAX)) ile++; return ile; } bool CHECK(int t) { for (int i = 0; i <= n + v + 3; i++) sas[i].clear(); int place; num = 0; for (int i = 1; i <= n; i++) { place = start[i]; for (int j = 1; j <= v; j++) { if (dist[place][j] <= t) { sas[i].push_back({j + n, num}); sas[j + n].push_back({i, num + 1}); cap[num] = 1; cap[num + 1] = 0; num += 2; } } } for (int i = 1; i <= n; i++) { sas[0].push_back({i, num}); sas[i].push_back({0, num + 1}); cap[num] = 1; cap[num + 1] = 0; num += 2; } for (int i = n + 1; i <= n + v; i++) { sas[i].push_back({n + v + 2, num}); sas[n + v + 2].push_back({i, num + 1}); cap[num] = 1; cap[num + 1] = 0; num += 2; } res = 0; while (DINIC()) { }; if (res >= k) return 1; return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> v >> e >> n >> k; for (int i = 1; i <= n; i++) cin >> start[i]; for (int i = 1; i <= v; i++) for (int j = 1; j <= v; j++) dist[i][j] = MAX_; for (int i = 1; i <= v; i++) dist[i][i] = 0; int h, j, r; for (int i = 1; i <= e; i++) { cin >> h >> j >> r; dist[h][j] = min(dist[h][j], r); dist[j][h] = min(dist[j][h], r); } for (int mid = 1; mid <= v; mid++) for (int x = 1; x <= v; x++) for (int y = 1; y <= v; y++) dist[x][y] = min(dist[x][y], dist[x][mid] + dist[mid][y]); if (!CHECK(1731311)) { cout << -1; return 0; } int b = 0; int e = 1731311; while (b <= e) { int mid = (b + e) / 2; if (CHECK(mid)) e = mid - 1; else b = mid + 1; } cout << b; } |
module Computer(
inout [WORD_WIDTH-1:0] ADDR_bus_inout,
inout [WORD_WIDTH-1:0] DATA_bus_inout,
input CLK_in,
input RST_in
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SA_WIDTH = DR_WIDTH;
parameter SB_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter FS_WIDTH = 4;
parameter CNTRL_FLAGS_WIDTH = 7;
parameter ULA_FLAG_WIDTH = 4;
parameter CNTRL_WIDTH = DR_WIDTH+SA_WIDTH+SB_WIDTH+FS_WIDTH+CNTRL_FLAGS_WIDTH;
wire [WORD_WIDTH-1:0] INSTR_bus, CONST_bus, DMEM_bus, COUNTER_bus;
wire [CNTRL_WIDTH-1:0] CNTRL_bus;
wire [ULA_FLAG_WIDTH-1:0] ULA_FLAG_bus;
Computer_InstructionMemory IM0(
.INSTR_out(INSTR_bus),
.COUNTER_in(COUNTER_bus)
);
Computer_ControlUnit CU0(
.CONST_bus_out(CONST_bus),
.CNTRL_bus_out(CNTRL_bus),
.COUNTER_bus_out(COUNTER_bus),
.ADDR_bus_in(ADDR_bus_inout),
.INSTR_bus_in(INSTR_bus),
.ULA_FLAG_bus_in(ULA_FLAG_bus),
.CLK(CLK_in),
.RST(RST_in)
);
Computer_Datapath DP0(
.ADDR_bus_out(ADDR_bus_inout),
.DATA_bus_out(DATA_bus_inout),
.FLAG_bus_out(ULA_FLAG_bus),
.CNTRL_bus_in(CNTRL_bus),
.CONST_bus_in(CONST_bus),
.DMEM_bus_in(DMEM_bus),
.CLK(CLK_in),
.RST(RST_in)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t > 0) { t--; string s, x; cin >> s; x.push_back(s[0]); for (int i = 1; i < s.size(); i++) { if (i % 2 != 0) x.push_back(s[i]); } cout << x << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; char a[500001 + 10], b[500001 + 10], s[(500001 << 1) + 10]; int n, m; struct BIT { long long c[500001 << 1]; long long query(int x) { if (x <= 0) return 0; long long ans = 0; for (int i = x; i; i -= (i & -i)) ans += c[i]; return ans; } void add(int x, long long p) { if (x <= 0) x = 1; for (int i = x; i <= 1000000; i += (i & -i)) c[i] += p; } } b1, b2; int za[500001 * 3], zb[500001 * 3]; char mod[500001 * 3]; void zfunc(char *s, int n, int *z) { int l = 0, r = 0; z[1] = n; int pt; for (int i = 2; i <= n; ++i) { if (r < i) { for (pt = i; pt <= n && s[pt] == s[pt - i + 1]; ++pt) ; --pt; z[i] = pt - i + 1; if (z[i]) l = i, r = pt; } else { int b = r - i + 1, i_ = i - l + 1; if (z[i_] < b) z[i] = z[i_]; else { for (pt = r + 1; pt <= n && s[pt] == s[pt - i + 1]; ++pt) ; --pt; z[i] = pt - i + 1; l = i, r = pt; } } } } int main() { scanf( %d%d , &n, &m); scanf( %s%s%s , a + 1, b + 1, s + 1); memcpy(mod + 1, s + 1, m - 1); mod[m] = $ ; memcpy(mod + m + 1, a + 1, n); zfunc(mod, n + m, za); for (int i = 1; i <= n; ++i) za[i] = za[i + m]; reverse(s + 1, s + 1 + m); reverse(b + 1, b + 1 + n); memcpy(mod + 1, s + 1, m - 1); mod[m] = $ ; memcpy(mod + m + 1, b + 1, n); zfunc(mod, n + m, zb); for (int i = 1; i <= n; ++i) zb[i] = zb[i + m]; reverse(zb + 1, zb + 1 + n); int cur = 1; long long ans = 0; for (int i = 1; i <= n; ++i) { while (cur <= min(i + m - 2, n)) b1.add(m - 1 - zb[cur], 1), b2.add(m - 1 - zb[cur], zb[cur]), ++cur; ans += 1ll * b1.query(za[i]) * (za[i] - m + 1) + b2.query(za[i]); b1.add(m - 1 - zb[i], -1), b2.add(m - 1 - zb[i], -zb[i]); } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; double esp = 1e-11; const double PI = acos(-1.0); const long long int INF = 0x3f3f3f3f; const long long int MOD = 1e9 + 7; const int maxn = 200010; int main() { int a, b, c; scanf( %d%d%d , &a, &b, &c); long double x = (-b + sqrt((long double)b * b - 4 * a * c)) / (2 * a); long double y = (-b - sqrt((long double)b * b - 4 * a * c)) / (2 * a); if (x < y) swap(x, y); printf( %.6f n%.6f n , (double)x, (double)y); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int v, e; cin >> v >> e; vector<set<int> > g(v); int a, b; for (int i = 0; i < e; i++) { cin >> a >> b; g[a - 1].insert(b - 1); g[b - 1].insert(a - 1); } int ans = 0; while (1) { vector<int> ve; for (int i = 0; i < v; i++) { if (g[i].size() == 1) { ve.push_back(i); } } for (int i = 0; i < ve.size(); i++) { set<int>::iterator it = g[ve[i]].begin(); g[ve[i]].clear(); g[*it].erase(ve[i]); } if (ve.size()) ans++; else break; } cout << ans << endl; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_top_rs
//
// Generated
// by: wig
// on: Tue Apr 25 19:40:28 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_top_rs.v,v 1.1 2006/07/10 07:30:08 wig Exp $
// $Date: 2006/07/10 07:30:08 $
// $Log: avfb_top_rs.v,v $
// Revision 1.1 2006/07/10 07:30:08 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_top_rs
//
// No user `defines in this module
module avfb_top_rs
//
// Generated module i_avfb_top_rs
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for i_rs_i2c_dcs
rs_I2C_DCS i_rs_i2c_dcs (
);
// End of Generated Instance Port Map for i_rs_i2c_dcs
endmodule
//
// End of Generated Module rtl of avfb_top_rs
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; void min_self(int& a, int b) { a = min(a, b); } void max_self(int& a, int b) { a = max(a, b); } const int NAX = (int)(2e5 + 5); int v[NAX], visited[NAX]; int component_size; void visit(int i) { if (!visited[i]) { ++component_size; visited[i] = 1; visit(v[i]); visited[i] = component_size; return; } return; } int main() { int t, n; scanf( %d , &t); while (t--) { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %d , &v[i]); for (int i = 1; i <= n; ++i) { component_size = 0; visit(i); } for (int i = 1; i <= n; ++i) printf( %d , visited[i]); printf( n ); for (int i = 1; i <= n; ++i) visited[i] = 0; } return 0; } |
#include <bits/stdc++.h> using namespace std; class Constellation { static const long long N = 100010; inline long long sign(long long x) { return x > 0 ? 1 : x == 0 ? 0 : -1; } struct point { long long x, y, num; } b[N]; long long n; long long cross(const point &a, const point &b, const point &c) { return sign((b.x - a.x) * (c.y - a.y) - (b.y - a.y) * (c.x - a.x)); } bool contain(const point &a, const point &b, const point &c, const point &p) { long long v1 = cross(a, b, p), v2 = cross(b, c, p), v3 = cross(c, a, p); return v1 * v2 >= 0 && v2 * v3 >= 0 && v3 * v1 >= 0; } public: void solve() { cin >> n; for (long long i = 1; i <= n; ++i) cin >> b[i].x >> b[i].y; long long p1 = 1, p2 = 2, p3 = 0; for (long long i = 3; i <= n; ++i) if (cross(b[p1], b[p2], b[i])) { p3 = i; break; } for (long long i = 1; i <= n; ++i) if (i != p1 && i != p2 && i != p3 && contain(b[p1], b[p2], b[p3], b[i])) { if (cross(b[p1], b[p2], b[i])) p3 = i; else p2 = i; } cout << p1 << << p2 << << p3 << endl; } } T; int main() { T.solve(); } |
#include <bits/stdc++.h> using namespace std; int arr[11][11]; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { arr[1][i] = 1; } for (int i = 2; i <= n; i++) { for (int j = 1; j <= n; j++) { arr[i][j] = arr[i - 1][j] + arr[i][j - 1]; } } cout << arr[n][n] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long double eps = (long double)1 / 1e9; long long inf = LLONG_MAX, mod1 = 1e9 + 7, mod2 = 998244353; long long sqr(long long a) { return a * a; } long long qb(long long a) { return a * a * a; } long long gcd(long long a, long long b) { return !a ? b : gcd(b % a, a); } long long binpow(long long a, long long b, long long mod) { return b ? (b % 2 ? (a * (sqr(binpow(a, b / 2, mod)) % mod)) % mod : sqr(binpow(a, b / 2, mod)) % mod) : 1; } long long binmult(long long a, long long b, long long mod) { return b ? (b % 2 ? (2 * binmult(a, b / 2, mod) + a) % mod : (2 * binmult(a, b / 2, mod)) % mod) : 0; } long long b[51], kl[27]; bool used[51]; char ans[51]; int main() { cout.tie(0), cin.tie(0), ios_base::sync_with_stdio(0); long long q, n, i, j, ps, kt; string a; cin >> q; while (q--) { cin >> a >> n; ps = 25; for (i = 0; i < 26; i++) kl[i] = 0; for (i = 0; i < a.size(); i++) kl[a[i] - a ]++; for (i = 1; i <= n; i++) cin >> b[i], used[i] = 0; while (1) { kt = 0; for (i = 1; i <= n; i++) if (!b[i] && !used[i]) kt++; if (!kt) break; while (kl[ps] < kt) ps--; vector<long long> vc; for (i = 1; i <= n; i++) if (!b[i] && !used[i]) used[i] = 1, vc.push_back(i); for (auto f : vc) { ans[f] = a + ps; for (j = 1; j <= n; j++) if (!used[j]) b[j] -= abs(j - f); } ps--; } for (i = 1; i <= n; i++) cout << ans[i]; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long dr[] = {-1, 1, 0, 0, -1, 1, -1, 1}; long long dc[] = {0, 0, -1, 1, -1, -1, 1, 1}; int main() { long long T; cin >> T; while (T--) { string a, b; cin >> a >> b; if (a < b) { cout << a << n ; continue; } bool f = 0; long long sz = min(a.size(), b.size()); long long loop = 0; for (long long i = 0; i < sz; i++) { if (a[i] < b[i]) { f = 1; break; } else { long long indx = -1; char mn = b[i]; for (long long j = i + 1; j < a.size(); j++) { if (a[j] <= mn) { mn = a[j]; indx = j; } } if (indx == -1 and a[i] > b[i]) { break; } else if (indx == -1 and a[i] == b[i]) { continue; } if (a[i] == a[indx]) continue; swap(a[i], a[indx]); loop++; if (a < b) { f = 1; } break; } } if (f == 1) { cout << a << n ; } else { cout << --- << n ; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR2_PP_SYMBOL_V
`define SKY130_FD_SC_LS__XNOR2_PP_SYMBOL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__xnor2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR2_PP_SYMBOL_V
|
// part of NeoGS project
//
// (c) NedoPC 2013
//
// mp3 data dma controller
module dma_mp3
(
input wire clk,
input wire rst_n,
output wire [ 7:0] md_din, // mp3 data interface
output wire md_start, //
input wire md_rdy, //
input wire md_dreq, //
// signals for ports.v
//
input wire [7:0] din, // input and output from ports.v
output reg [7:0] dout,
//
input wire module_select, // =1 - module selected for read-write operations from ports.v
input wire write_strobe, // one-cycle positive write strobe - writes to the selected registers from din
//
input wire [1:0] regsel, // 2'b00 - high address, 2'b01 - middle address, 2'b10 - low address, 2'b11 - control register
// signals for DMA controller/DMA sequencer
//
output reg [21:0] dma_addr,
input wire [7:0] dma_rd, // data read from DMA
output wire dma_rnw,
//
output reg dma_req,
input wire dma_ack,
input wire dma_end,
output wire int_req
);
reg dma_on;
wire dma_finish;
wire w511;
wire rdone;
reg [3:0] state,next_state;
assign int_req = dma_finish;
assign dma_rnw = 1'b1;
localparam _HAD = 2'b00; // high address
localparam _MAD = 2'b01; // mid address
localparam _LAD = 2'b10; // low address
localparam _CST = 2'b11; // control and status
// control dout bus
always @*
case( regsel[1:0] )
_HAD: dout = { 2'b00, dma_addr[21:16] };
_MAD: dout = dma_addr[15:8];
_LAD: dout = dma_addr[7:0];
_CST: dout = { dma_on, 7'bXXX_XXXX };
endcase
// dma_on control
always @(posedge clk, negedge rst_n)
if( !rst_n )
dma_on <= 1'b0;
else if( dma_finish )
dma_on <= 1'b0;
else if( module_select && write_strobe && (regsel==_CST) )
dma_on <= din[7];
// dma_addr control
always @(posedge clk)
if( dma_req && dma_ack && dma_on )
dma_addr <= dma_addr + 22'd1; // increment on successfull DMA transfer
else if( module_select && write_strobe )
begin
if( regsel==_HAD )
dma_addr[21:16] <= din[5:0];
else if( regsel==_MAD )
dma_addr[15:8] <= din[7:0];
else if( regsel==_LAD )
dma_addr[7:0] <= din[7:0];
end
localparam _IDLE = 4'd0;
localparam _START = 4'd1;
localparam _DMARD = 4'd2;
localparam _MP3W1 = 4'd3;
localparam _MP3W2 = 4'd4;
localparam _MP3W3 = 4'd5;
localparam _STOP = 4'd6;
always @(posedge clk, negedge dma_on)
if( !dma_on )
state <= _IDLE;
else
state <= next_state;
always @*
case( state )
_IDLE: next_state = _START;
_START: next_state = _DMARD;
_DMARD:begin
if( dma_req )
next_state = _DMARD;
else
next_state = _MP3W1;
end
_MP3W1: next_state = _MP3W2;
_MP3W2:begin
if( md_rdy && md_dreq )
next_state = _MP3W3;
else
next_state = _MP3W2;
end
_MP3W3:begin
if( rdone )
next_state = _STOP;
else
next_state = _MP3W2;
end
_STOP: next_state = _STOP;
endcase
assign md_start = ( state==_MP3W3 );
assign dma_finish = ( state==_STOP );
always @(posedge clk, negedge dma_on)
if( !dma_on )
dma_req <= 1'b0;
else if( state==_START )
dma_req <= 1'b1;
else if( dma_ack && w511 )
dma_req <= 1'b0;
dma_fifo_oneshot dma_fifo_oneshot
(
.clk (clk ),
.rst_n(dma_on),
.wr_stb( dma_end ),
.rd_stb( md_start || state==_MP3W1 ),
.wdone( ),
.rdone(rdone),
.empty( ),
.w511 (w511 ),
.wd(dma_rd),
.rd(md_din)
);
endmodule
|
/*
servo controller
Based on code from Mojo tutorial
https://embeddedmicro.com/tutorials/mojo/servos
takes an 8-bit position as an input
output a single pwm signal with period of ~20ms
pulse width = 1ms -> 2ms full scale. 1.5ms is center position
approximate scaling.
position = 0 -> 42,240 (should be 50,000)
position = 255 -> 107,520 (should be 100,000)
This means that it will probably reach it's limits at either end
and not quite scale correctly
*/
module servo_controller (
input clk,
input rst,
input [7:0] position,
output servo
);
reg pwm_q, pwm_d;
reg [19:0] ctr_q, ctr_d;
assign servo = pwm_q;
//position = 0-255
//I want to map this to 50,000-100,000 (which corresponds to 1ms-2ms @ 50MHz)
//this is approximately (position+165)<<8
//The servo output is set by comparing the position input with the value of the counter (ctr_q)
always @(*) begin
ctr_d = ctr_q + 1'b1;
if (position + 9'd165 > ctr_q[19:8]) begin
pwm_d = 1'b1;
end else begin
pwm_d = 1'b0;
end
end
//standard always block triggered on positive edge of clk
//rst sets the counter to zero.
//otherwise the output (ctr_q) is set to the input (ctr_d)
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
end else begin
ctr_q <= ctr_d;
end
pwm_q <= pwm_d;
end
endmodule |
/**
Abstract: библиотека триггеров и регистров
*/
`include "vconst_lib.v"
/*
триггер пока что с разрешением работы и асинхронным сбросом
a_dff #(.WIDTH()) label_(
.clk(), .aclr(), .ena(),
.data(), .q());
*/
module a_dff(clk, aclr, ena, data, q);
parameter WIDTH = 8;
input clk, aclr, ena;
input [WIDTH-1:0] data;
output reg [WIDTH-1:0] q;
// logic
always @ (posedge clk or posedge aclr)
begin
if (aclr)
q <= 1'b0;
else if (ena)
q <= data;
end
endmodule
/**
триггер с синхр. установкой и асинхронным сбросом
dffe_flag gflag(
.clk(clk), .rst(rst), .clk_ena(_ena),
.d(d));
// в принципе можено получить из первого
*/
module dffe_flag(clk, rst, clk_ena, d);
input clk, rst, clk_ena;
output d;
// local
reg tmp;
// logic
always @(posedge clk or posedge rst)
begin
if(rst)
tmp <= 'b0; // !!в ноль сбрасывается только так
else if(clk_ena)
tmp <= 'b1; // защелкивает единицу по разрешению
end
// out
assign d = tmp;
endmodule
/*
Abstract: PE Register with synchronous load,
intialize, hold
Connect:
register_pe label_rp(
.clk(clk), .rst(rst), .clk_ena(clk_ena),
// control
.load(load),
// datastream
.datain(), .dforload(), // inputs
.dataout()
);
*/
module register_pe(
clk, rst, clk_ena,
// control
load,
// datastream
// in
datain, dforload,
// out
dataout
);
input clk, rst, clk_ena; // ? rst нужен или нет
// control
input load;
// data
input [`G_WIDTH-1:0] datain, dforload;
output [`G_WIDTH-1:0] dataout;
// local
reg [`G_WIDTH-1:0] out;
// logic
always @(posedge clk or posedge rst)
begin
if(rst)
out <= 0;
else if(clk_ena) // если тактирование разрешено
if(load) // синфронная загрузка
out <= dforload;
else
out <= datain; // сквозное прохождение сигнала
end
// out
assign dataout = out;
endmodule
// версия предыдущего, но с разрешением такта
module register_pe_new(
clk, rst, clk_ena,
// control
load, init,
// datastream
datain, initdata, // inputs
dataout
);
input clk, rst, clk_ena;
// control
input load, init;
// data
input [`G_WIDTH-1:0] datain, initdata;
output [`G_WIDTH-1:0] dataout;
// local
reg [`G_WIDTH-1:0] out;
// logic
always @(posedge clk)
begin
if(rst)
out <= 'b0;
else if(clk_ena)
if(init)
out <= initdata; // по сути загрузка синдрома
else if(load)
out <= datain; // рабочий режим
end
// out
assign dataout = out;
endmodule
|
/*
* Copyright (c) 2002 Jane Skinner
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* PR#542 */
module top;
parameter[3:0] DAC = 8;
wire d_pm_in_dac_st;
reg [10:0] pm_next_st;
assign d_pm_in_dac_st = (pm_next_st[DAC]);
initial begin
pm_next_st = 10'h100;
#1;
$display("d_pm_in_dac_st = %0b",d_pm_in_dac_st);
$display("d_pm_in_dac_st = %0b",pm_next_st[DAC]);
$finish;
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:05:32 EST 2014
//
//
// Ports:
// Name I/O size props
// RDY_s_request_put O 1
// s_response_get O 153
// RDY_s_response_get O 1
// c0_request_get O 153
// RDY_c0_request_get O 1
// RDY_c0_response_put O 1
// c1_request_get O 153
// RDY_c1_request_get O 1
// RDY_c1_response_put O 1
// pfk I 14
// CLK I 1 clock
// RST_N I 1 reset
// s_request_put I 153
// c0_response_put I 153
// c1_response_put I 153
// EN_s_request_put I 1
// EN_c0_response_put I 1
// EN_c1_response_put I 1
// EN_s_response_get I 1
// EN_c0_request_get I 1
// EN_c1_request_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkTLPSM(pfk,
CLK,
RST_N,
s_request_put,
EN_s_request_put,
RDY_s_request_put,
EN_s_response_get,
s_response_get,
RDY_s_response_get,
EN_c0_request_get,
c0_request_get,
RDY_c0_request_get,
c0_response_put,
EN_c0_response_put,
RDY_c0_response_put,
EN_c1_request_get,
c1_request_get,
RDY_c1_request_get,
c1_response_put,
EN_c1_response_put,
RDY_c1_response_put);
input [13 : 0] pfk;
input CLK;
input RST_N;
// action method s_request_put
input [152 : 0] s_request_put;
input EN_s_request_put;
output RDY_s_request_put;
// actionvalue method s_response_get
input EN_s_response_get;
output [152 : 0] s_response_get;
output RDY_s_response_get;
// actionvalue method c0_request_get
input EN_c0_request_get;
output [152 : 0] c0_request_get;
output RDY_c0_request_get;
// action method c0_response_put
input [152 : 0] c0_response_put;
input EN_c0_response_put;
output RDY_c0_response_put;
// actionvalue method c1_request_get
input EN_c1_request_get;
output [152 : 0] c1_request_get;
output RDY_c1_request_get;
// action method c1_response_put
input [152 : 0] c1_response_put;
input EN_c1_response_put;
output RDY_c1_response_put;
// signals for module outputs
wire [152 : 0] c0_request_get, c1_request_get, s_response_get;
wire RDY_c0_request_get,
RDY_c0_response_put,
RDY_c1_request_get,
RDY_c1_response_put,
RDY_s_request_put,
RDY_s_response_get;
// ports of submodule pktFork
wire [152 : 0] pktFork_iport_put, pktFork_oport0_get, pktFork_oport1_get;
wire pktFork_EN_iport_put,
pktFork_EN_oport0_get,
pktFork_EN_oport1_get,
pktFork_RDY_iport_put,
pktFork_RDY_oport0_get,
pktFork_RDY_oport1_get;
// ports of submodule pktMerge
wire [152 : 0] pktMerge_iport0_put, pktMerge_iport1_put, pktMerge_oport_get;
wire pktMerge_EN_iport0_put,
pktMerge_EN_iport1_put,
pktMerge_EN_oport_get,
pktMerge_RDY_iport0_put,
pktMerge_RDY_iport1_put,
pktMerge_RDY_oport_get;
// remaining internal signals
reg [1 : 0] CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1;
wire [13 : 0] x__h110;
// action method s_request_put
assign RDY_s_request_put = pktFork_RDY_iport_put ;
// actionvalue method s_response_get
assign s_response_get = pktMerge_oport_get ;
assign RDY_s_response_get = pktMerge_RDY_oport_get ;
// actionvalue method c0_request_get
assign c0_request_get = pktFork_oport0_get ;
assign RDY_c0_request_get = pktFork_RDY_oport0_get ;
// action method c0_response_put
assign RDY_c0_response_put = pktMerge_RDY_iport0_put ;
// actionvalue method c1_request_get
assign c1_request_get = pktFork_oport1_get ;
assign RDY_c1_request_get = pktFork_RDY_oport1_get ;
// action method c1_response_put
assign RDY_c1_response_put = pktMerge_RDY_iport1_put ;
// submodule pktFork
mkPktFork pktFork(.pfk(x__h110),
.CLK(CLK),
.RST_N(RST_N),
.iport_put(pktFork_iport_put),
.EN_iport_put(pktFork_EN_iport_put),
.EN_oport0_get(pktFork_EN_oport0_get),
.EN_oport1_get(pktFork_EN_oport1_get),
.RDY_iport_put(pktFork_RDY_iport_put),
.oport0_get(pktFork_oport0_get),
.RDY_oport0_get(pktFork_RDY_oport0_get),
.oport1_get(pktFork_oport1_get),
.RDY_oport1_get(pktFork_RDY_oport1_get));
// submodule pktMerge
mkPktMerge pktMerge(.CLK(CLK),
.RST_N(RST_N),
.iport0_put(pktMerge_iport0_put),
.iport1_put(pktMerge_iport1_put),
.EN_iport0_put(pktMerge_EN_iport0_put),
.EN_iport1_put(pktMerge_EN_iport1_put),
.EN_oport_get(pktMerge_EN_oport_get),
.RDY_iport0_put(pktMerge_RDY_iport0_put),
.RDY_iport1_put(pktMerge_RDY_iport1_put),
.oport_get(pktMerge_oport_get),
.RDY_oport_get(pktMerge_RDY_oport_get));
// submodule pktFork
assign pktFork_iport_put = s_request_put ;
assign pktFork_EN_iport_put = EN_s_request_put ;
assign pktFork_EN_oport0_get = EN_c0_request_get ;
assign pktFork_EN_oport1_get = EN_c1_request_get ;
// submodule pktMerge
assign pktMerge_iport0_put = c0_response_put ;
assign pktMerge_iport1_put = c1_response_put ;
assign pktMerge_EN_iport0_put = EN_c0_response_put ;
assign pktMerge_EN_iport1_put = EN_c1_response_put ;
assign pktMerge_EN_oport_get = EN_s_response_get ;
// remaining internal signals
assign x__h110 =
{ CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1,
pfk[11:0] } ;
always@(pfk)
begin
case (pfk[13:12])
2'd0, 2'd1, 2'd2:
CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = pfk[13:12];
2'd3: CASE_pfk_BITS_13_TO_12_0_pfk_BITS_13_TO_12_1_p_ETC__q1 = 2'd3;
endcase
end
endmodule // mkTLPSM
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSTP_BLACKBOX_V
`define SKY130_FD_SC_HD__DFSTP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfstp (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSTP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32A_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O32A_PP_SYMBOL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o32a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { while (b != 0) { int r = a % b; a = b; b = r; } return a; } void FindMinimum(int a[], int &n) { int g = gcd(a[0], a[1]); for (int i = 2; i < n; ++i) g = gcd(a[i], g); cout << g * n; } int main() { int n, a[100]; cin >> n; for (int i = 0; i < n; ++i) cin >> a[i]; sort(a, a + n); FindMinimum(a, n); return 0; } |
#include <bits/stdc++.h> using namespace std; bool chk(int n, int first) { return n & (1 << first); } void set(int& n, int first) { n = n | (1 << first); } void reset(int& n, int first) { n = n & ~(1 << first); } const int mx = 600010; bool f[mx]; int a[mx][3], _size; char s[mx]; int new_node() { ++_size; for (int i = 0; i < 3; i++) a[_size][i] = 0; f[_size] = false; return _size; } void Insert(char str[]) { int cur = 0, i = -1; while (str[++i] != 0 ) { int& next = a[cur][str[i] - a ]; if (next == 0) next = new_node(); cur = next; } f[cur] = true; } bool Search(int i, int cur, bool flag) { if (s[i] == 0 ) return f[cur] && flag; if (flag) { int next = a[cur][s[i] - a ]; if (next == 0) return false; return Search(i + 1, next, 1); } else { int next = a[cur][s[i] - a ]; if (next > 0 && Search(i + 1, next, 0)) return true; for (int j = 0; j < 3; j++) { next = a[cur][j]; if (next == 0) continue; if (s[i] == j + a ) continue; if (Search(i + 1, next, 1)) return true; } return false; } } int main() { int i, j, k, n, m; while (scanf( %d%d , &n, &m) == 2) { _size = -1; new_node(); for (i = 0; i < n; i++) { scanf( %s , s); Insert(s); } for (i = 0; i < m; i++) { scanf( %s , s); if (Search(0, 0, 0)) printf( YES n ); else printf( NO n ); } } } |
#include <bits/stdc++.h> using namespace std; const long long N = 3e4 + 10, M = 1e3 + 10; long long n, p[N], d, dp[N][M + 10]; long long solve(long long pos, long long L) { if (pos > 30000) return 0; long long wh = L - d + M / 2; if (dp[pos][wh] != -1) return dp[pos][wh]; long long ret = 0; if (L == 1) ret = max(solve(pos + L, L), solve(pos + L + 1, L + 1)); else ret = max({solve(pos + L - 1, L - 1), solve(pos + L, L), solve(pos + L + 1, L + 1)}); ret += p[pos]; dp[pos][wh] = ret; return ret; } int main() { for (long long i = 0; i < N; i++) for (long long j = 0; j < M; j++) dp[i][j] = -1; cin >> n >> d; for (long long i = 1; i <= n; i++) { long long x; cin >> x; p[x]++; } cout << solve(d, d) << n ; } |
// Copyright (c) 2014 CERN
// Maciej Suminski <>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for casting a dynamic array to vector type
// using Icarus specific VPI functions
module sv_cast_string();
bit [7:0] darr [];
bit [63:0] darr_64 [];
bit [7*8 - 1:0] arr;
bit [127:0] arr_128;
initial begin
darr_64 = new[2];
darr_64[0] = "ABCDEFGH";
darr_64[1] = "IJKLMNOP";
darr = new[7];
// Set darr to '{"a","b","c","d","e","f","g"}
foreach(darr[i])
darr[i] = "a" + i;
// Casting dynamic array to vector
$ivl_darray_method$to_vec(darr, arr);
if(arr !== "abcdefg") begin
$display("FAILED 1");
$finish();
end
$ivl_darray_method$to_vec(darr_64, arr_128);
if(arr_128 !== "ABCDEFGHIJKLMNOP") begin
$display("FAILED 2");
$finish();
end
// Reset the stored data to perform reverse casting test
arr = "";
arr_128 = "cafedeadbeefc0de";
// Casting vector to dynamic array
$ivl_darray_method$from_vec(darr, arr);
foreach(darr[i]) begin
if(darr[i] != "0" + i) begin
$display("FAILED 3");
$finish();
end
end
$ivl_darray_method$from_vec(darr_64, arr_128);
if(darr_64[0] !== "cafedead" || darr_64[1] !== "beefc0de") begin
$display("FAILED 4");
$finish();
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, k; long long mx, p1, p2, val, sum, res, res1; long long m[200007][27]; int main() { ios_base::sync_with_stdio(); cin.tie(); cout.tie(); ; cin >> n >> k; res = 1000000007.0; for (int i = 1; i <= n; i++) { cin >> val; mx = max(val, mx); m[val][0]++; if (m[val][0] >= k) res = 0; } mx /= 2; for (long long i = mx; i >= 0; i--) { if (i == 0) { sum = m[0][0]; for (int j = 0; j <= 19; j++) { m[0][j + 1] += m[1][j]; sum += m[i][j + 1]; } } else { p1 = 2 * i; p2 = 2 * i + 1; sum = m[i][0]; for (int j = 0; j <= 19; j++) { m[i][j + 1] += m[p1][j] + m[p2][j]; sum += m[i][j + 1]; } } if (sum >= k) { sum = 0; res1 = 0; for (long long j = 0; j <= 19; j++) { res1 += m[i][j] * j; sum += m[i][j]; if (sum >= k) { res = min(res, (res1 - (sum - k) * j)); break; } } } } cout << res << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CONB_BLACKBOX_V
`define SKY130_FD_SC_HDLL__CONB_BLACKBOX_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__conb (
HI,
LO
);
output HI;
output LO;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CONB_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXBN_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DLXBN_PP_SYMBOL_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input GATE_N,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXBN_PP_SYMBOL_V
|
`timescale 1ns / 1ps
module regfile_16x32b_4rd_2wr_tb;
// Inputs
reg clk;
reg rst;
reg [3:0] rdport1_ctrl_add;
reg [3:0] rdport2_ctrl_add;
reg [3:0] rdport3_ctrl_add;
reg [3:0] rdport4_ctrl_add;
reg [3:0] wrport1_ctrl_add;
reg [31:0] wrport1_data_in;
reg wrport1_wren;
reg [3:0] wrport2_ctrl_add;
reg [31:0] wrport2_data_in;
reg wrport2_wren;
// Outputs
wire [31:0] rdport1_data_out;
wire [31:0] rdport2_data_out;
wire [31:0] rdport3_data_out;
wire [31:0] rdport4_data_out;
// Variables
integer i = 0;
// Instantiate the Unit Under Test (UUT)
regfile_16x32b_4rd_2wr uut (
.clk(clk),
.rst(rst),
.rdport1_ctrl_add(rdport1_ctrl_add),
.rdport1_data_out(rdport1_data_out),
.rdport2_ctrl_add(rdport2_ctrl_add),
.rdport2_data_out(rdport2_data_out),
.rdport3_ctrl_add(rdport3_ctrl_add),
.rdport3_data_out(rdport3_data_out),
.rdport4_ctrl_add(rdport4_ctrl_add),
.rdport4_data_out(rdport4_data_out),
.wrport1_ctrl_add(wrport1_ctrl_add),
.wrport1_data_in(wrport1_data_in),
.wrport1_wren(wrport1_wren),
.wrport2_ctrl_add(wrport2_ctrl_add),
.wrport2_data_in(wrport2_data_in),
.wrport2_wren(wrport2_wren)
);
task expectRead;
input [31:0] exp_out0;
input [31:0] exp_out1;
input [31:0] exp_out2;
input [31:0] exp_out3;
if ((rdport1_data_out !== exp_out0) || (rdport2_data_out !== exp_out1) || (rdport3_data_out !== exp_out2) || (rdport4_data_out !== exp_out3)) begin
$display("TEST FAILED");
$display("At time %0d rdport1_ctrl_add=%0d, rdport1_data_out=%0d, rdport2_ctrl_add=%0d, rdport2_data_out=%0d, rdport3_ctrl_add=%0d, rdport3_data_out=%0d, rdport4_ctrl_add=%0d, rdport4_data_out=%0d ",
$time,
rdport1_ctrl_add, rdport1_data_out,
rdport2_ctrl_add, rdport2_data_out,
rdport3_ctrl_add, rdport3_data_out,
rdport4_ctrl_add, rdport4_data_out);
$display("rdport1_data_out, rdport2_data_out, rdport3_data_out, rdport4_data_out should be %0d, %0d, %0d, %0d",
exp_out0, exp_out1, exp_out2, exp_out3 );
$finish;
end
else begin
$display("At time %0d rdport1_ctrl_add=%0d, rdport1_data_out=%0d, rdport2_ctrl_add=%0d, rdport2_data_out=%0d, rdport3_ctrl_add=%0d, rdport3_data_out=%0d, rdport4_ctrl_add=%0d, rdport4_data_out=%0d ",
$time,
rdport1_ctrl_add, rdport1_data_out,
rdport2_ctrl_add, rdport2_data_out,
rdport3_ctrl_add, rdport3_data_out,
rdport4_ctrl_add, rdport4_data_out);
end
endtask
// Clock and sync reset stimulus
initial begin
clk = 1'b0;
rst = 1'b1;
// hold sync reset for next 2 cc
repeat(4) #10 clk = ~clk;
// deassert reset
rst = 1'b0;
// clock forever
forever #10 clk = ~clk;
end
// Stimulus
initial begin
// Initialize Inputs
rdport1_ctrl_add = 0;
rdport2_ctrl_add = 0;
rdport3_ctrl_add = 0;
rdport4_ctrl_add = 0;
wrport1_ctrl_add = 0;
wrport1_data_in = 0;
wrport1_wren = 0;
wrport2_ctrl_add = 0;
wrport2_data_in = 0;
wrport2_wren = 0;
// wait for reset to deassert
@(negedge rst);
// write to first 8 registers using port 1 and last 8 registers using port 2
// write values 16x1, 16x2, 16x3..16x8 by wr port 1 to the first 8 registers
// write values 16x9, 16x10, 16x11..16x16 by wr port 2 to the next 8 registers
for( i = 0; i < 8 ; i = i+1)
begin
wrport1_ctrl_add = i;
wrport1_data_in = (i+1)*16;
wrport2_ctrl_add = i + 8;
wrport2_data_in = (i+9)*16;
wrport1_wren = 1;
wrport2_wren = 1;
// wait for negative clock edge
@(negedge clk);
end
// Deassert write enables
wrport1_wren = 0;
wrport2_wren = 0;
// Read back all 16 registers using 4 read ports
// with per port reading 4 registers
// RDP1(R0-R3), RDP2(R4-R7), RDP3(R8-R11), RDP4(R12-R15)
for( i = 0; i < 4 ; i = i+1)
begin
rdport1_ctrl_add = i;
rdport2_ctrl_add = i+4;
rdport3_ctrl_add = i+8;
rdport4_ctrl_add = i+12;
// wait for negative clock edge
@(negedge clk);
expectRead( 16*(i+1), 16*(i+5), 16*(i+9), 16*(i+13));
end
// Test write collision: write to same register
// simulataneously from two write ports with different values.
// only write by first write port should go through while
// the write by second port should be ignored
wrport1_ctrl_add = 10;
wrport1_data_in = 100;
wrport2_ctrl_add =10;
wrport2_data_in = 1000;
wrport1_wren = 1;
wrport2_wren = 1;
// wait for negative clock edge
@(negedge clk);
wrport1_wren = 0;
wrport2_wren = 0;
// read same register using all 4 read ports
// to check which of the two collision writes
// went through. this also verifies if we can
// simulataneously read from same register using
// all 4 ports
rdport1_ctrl_add = 10;
rdport2_ctrl_add = 10;
rdport3_ctrl_add = 10;
rdport4_ctrl_add = 10;
@(negedge clk);
expectRead( 100, 100, 100, 100);
$display("TEST PASSED");
$finish;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ff_jbi_sc1_1.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module ff_jbi_sc1_1(/*AUTOARG*/
// Outputs
jbi_sctag_req_d1, scbuf_jbi_data_d1, jbi_scbuf_ecc_d1,
jbi_sctag_req_vld_d1, scbuf_jbi_ctag_vld_d1, scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1, sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1, so,
// Inputs
jbi_sctag_req, scbuf_jbi_data, jbi_scbuf_ecc, jbi_sctag_req_vld,
scbuf_jbi_ctag_vld, scbuf_jbi_ue_err, sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue, sctag_jbi_por_req, rclk, si, se
);
output [31:0] jbi_sctag_req_d1;
output [31:0] scbuf_jbi_data_d1;
output [6:0] jbi_scbuf_ecc_d1;
output jbi_sctag_req_vld_d1;
output scbuf_jbi_ctag_vld_d1;
output scbuf_jbi_ue_err_d1;
output sctag_jbi_iq_dequeue_d1;
output sctag_jbi_wib_dequeue_d1;
output sctag_jbi_por_req_d1;
input [31:0] jbi_sctag_req;
input [31:0] scbuf_jbi_data;
input [6:0] jbi_scbuf_ecc;
input jbi_sctag_req_vld;
input scbuf_jbi_ctag_vld;
input scbuf_jbi_ue_err;
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
input sctag_jbi_por_req;
input rclk;
input si, se;
output so;
wire int_scanout;
// connect scanout of the last flop to int_scanout.
// The output of the lockup latch is
// the scanout of this dbb (so)
bw_u1_scanlg_2x so_lockup(.so(so), .sd(int_scanout), .ck(rclk), .se(se));
dff_s #(32) ff_flop_row0 (.q(jbi_sctag_req_d1[31:0]),
.din(jbi_sctag_req[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(32) ff_flop_row1 (.q(scbuf_jbi_data_d1[31:0]),
.din(scbuf_jbi_data[31:0]),
.clk(rclk), .se(1'b0), .si(), .so() );
dff_s #(13) ff_flop_row2 (.q({ jbi_scbuf_ecc_d1[6:0],
jbi_sctag_req_vld_d1,
scbuf_jbi_ctag_vld_d1,
scbuf_jbi_ue_err_d1,
sctag_jbi_iq_dequeue_d1,
sctag_jbi_wib_dequeue_d1,
sctag_jbi_por_req_d1}),
.din({ jbi_scbuf_ecc[6:0],
jbi_sctag_req_vld,
scbuf_jbi_ctag_vld,
scbuf_jbi_ue_err,
sctag_jbi_iq_dequeue,
sctag_jbi_wib_dequeue,
sctag_jbi_por_req}),
.clk(rclk), .se(1'b0), .si(), .so() );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCON_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__FAHCON_FUNCTIONAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire pwrgood_pp1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , pwrgood_pp0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCON_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S50_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLYGATE4S50_PP_SYMBOL_V
/**
* dlygate4s50: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlygate4s50 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S50_PP_SYMBOL_V
|
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