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#include <bits/stdc++.h> using namespace std; string p; bool cap = false, l = false, dig = false; char digits[10] = { 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 }; int main() { cin >> p; int s = p.length(); if (s < 5) { cout << Too weak ; return 0; } for (int i = 0; i < s; i++) { if (isupper(p[i])) cap = true; else if (islower(p[i])) l = true; for (int j = 0; j < 10; j++) if (p[i] == digits[j]) dig = true; } if (cap == true && l == true && dig == true) cout << Correct ; else cout << Too weak ; return 0; } |
#include <bits/stdc++.h> using namespace std; char buf[10001], buf2[1000001]; int tab[100001][26]; int main() { scanf( %s %s , buf, buf2); int len = strlen(buf), len2 = strlen(buf2); for (int i = 0; i < 26; i++) tab[len - 1][i] = -1; for (int ti = 2 * len - 2; ti >= 0; ti--) { int i = ti % len; for (int j = 0; j < 26; j++) tab[i][j] = buf[i] == a + j ? i : tab[(i + 1) % len][j]; } for (int i = 0; i < len; i++) { for (int j = 0; j < 26; j++) if (tab[i][j] != -1) ; ; } int ind = len - 1, loop = 0; for (int i = 0; i < len2; i++) { int c = buf2[i] - a ; int newind = tab[(ind + 1) % len][c]; ; if (newind <= ind) loop++; if (newind == -1) { printf( -1 n ); return 0; } ind = newind; } printf( %d n , loop); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, dx[]{-1, 0, 0, 1}, dy[]{0, -1, 1, 0}; vector<string> tab; vector<vector<int>> dist; priority_queue<pair<int, pair<int, int>>> PQ; int dijkstra(int x, int y) { dist.assign(n, vector<int>(m, INT_MAX / 2)); dist[x][y] = 1; PQ.push({0, {x, y}}); while (!PQ.empty()) { int d = -PQ.top().first; x = PQ.top().second.first; y = PQ.top().second.second; PQ.pop(); if (d > dist[x][y]) continue; for (int i = 0; i < 4; i++) { int x2 = x + dx[i], y2 = y + dy[i]; if (x2 < 0 or x2 >= n or y2 < 0 or y2 >= m) continue; d = dist[x][y] + (tab[x][y] != tab[x2][y2]); if (dist[x2][y2] > d) { dist[x2][y2] = d; PQ.push({-d, {x2, y2}}); } } } int maxi = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (tab[i][j] == B ) maxi = max(maxi, dist[i][j]); return maxi; } int main() { cin >> n >> m; tab.resize(n); for (int i = 0; i < n; i++) cin >> tab[i]; int ans = INT_MAX; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) ans = min(ans, dijkstra(i, j)); printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s1; while (cin >> s1) { string s2 = ; for (int i = 0; i < s1.size(); i++) { if (s1[i] != + ) s2 += s1[i]; } sort(s2.begin(), s2.end()); for (int i = 0; i < s2.size(); i++) { if (i) cout << + ; cout << s2[i]; } cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; cin.ignore(); while (n--) { string str1, str2; getline(cin, str1); getline(cin, str2); bool test = true; long long j = 0, i = 0; char last_ch = str1[0]; while (j < str2.size() && i < str1.size()) { if (str2[j] == str1[i]) last_ch = str1[i], i++, j++; else if (str2[j] == last_ch) { while (str2[j] == last_ch) j++; } else { test = false; break; } } while (j < str2.size()) { if (str2[j] != last_ch) { test = false; break; } j++; } if (!test) { cout << NO << endl; continue; } if (i < str1.size()) { cout << NO << endl; continue; } cout << YES << endl; } return 0; } |
// MBT 10-29-14
//
//
`include "bsg_defines.v"
module bsg_nonsynth_ascii_writer
#(parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(values_p )
, parameter `BSG_INV_PARAM(filename_p )
, parameter fopen_param_p = "w"
, parameter format_p = "%x ")
(input clk
, input reset_i
, input valid_i
, input [width_p*values_p-1:0] data_i
);
integer file = -1;
integer i;
// fixme: check error condition
always @(posedge reset_i)
if (file == -1)
begin
file = $fopen(filename_p,fopen_param_p);
end
logic [width_p*values_p-1:0] capture_data_r;
logic capture_valid_r;
// delay the data by one cycle to avoid races
// in timing simulation
always @(posedge clk)
begin
capture_data_r <= data_i;
capture_valid_r <= valid_i;
end
// format does not work as parameter
always @(negedge clk)
if (capture_valid_r && file != -1)
begin
for (i = 0; i < values_p; i++)
begin
$fwrite(file,format_p,capture_data_r[i*width_p+:width_p]);
end
$fwrite(file,"\n");
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_ascii_writer)
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pcie_bram_7x.v
// Version : 1.11
// Description : single bram wrapper for the mb pcie block
// The bram A port is the write port
// the B port is the read port
//
//
//-----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_11_0_pcie_bram_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DOB_REG = 0, // 1 - use the output register;
// 0 - don't use the output register
parameter WIDTH = 0 // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
// 72 - uses RAMB36SDP
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = ((WIDTH == 72) && (!((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)))) ? "WRITE_FIRST" :
((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ? "WRITE_FIRST" : "NO_CHANGE";
localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6";
localparam BRAM_SIZE = "36Kb";
localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ?
((WIDTH <= 9) ? 1 :
(WIDTH > 9 && WIDTH <= 18) ? 2 :
(WIDTH > 18 && WIDTH <= 36) ? 4 :
(WIDTH > 36 && WIDTH <= 72) ? 8 :
(BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8;
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp
BRAM_SDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DO_REG (DOB_REG),
.READ_WIDTH (WIDTH),
.WRITE_WIDTH (WIDTH),
.WRITE_MODE (WRITE_MODE)
)
ramb36sdp(
.DO (rdata_o[WIDTH-1:0]),
.DI (wdata_i[WIDTH-1:0]),
.RDADDR (raddr_i[ADDR_MSB:0]),
.RDCLK (user_clk_i),
.RDEN (ren_i),
.REGCE (rce_i),
.RST (reset_i),
.WE ({WE_WIDTH{1'b1}}),
.WRADDR (waddr_i[ADDR_MSB:0]),
.WRCLK (user_clk_i),
.WREN (wen_i)
);
end // block: use_sdp
else if (WIDTH <= 36) begin : use_tdp
// use RAMB36's if the width is 4, 9, 18, or 36
BRAM_TDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (WIDTH),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (WIDTH),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.DOA (),
.DOB (rdata_o[WIDTH-1:0]),
.ADDRA (waddr_i[ADDR_MSB:0]),
.ADDRB (raddr_i[ADDR_MSB:0]),
.CLKA (user_clk_i),
.CLKB (user_clk_i),
.DIA (wdata_i[WIDTH-1:0]),
.DIB ({WIDTH{1'b0}}),
.ENA (wen_i),
.ENB (ren_i),
.REGCEA (1'b0),
.REGCEB (rce_i),
.RSTA (reset_i),
.RSTB (reset_i),
.WEA ({WE_WIDTH{1'b1}}),
.WEB ({WE_WIDTH{1'b0}})
);
end // block: use_tdp
endgenerate
endmodule // pcie_bram_7x
|
/*.
* DSI Shield
* Copyright (C) 2013-2014 twl <>
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 3 of the License, or (at your option) any later version.
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/1ps
module pll_drp_ram
(
input clk_a_i,
input [4:0] aa_i,
input [39:0] da_i,
input wea_i,
input clk_b_i,
input [4:0] ab_i,
output reg [39:0] qb_o
);
reg [39:0] ram [0:31];
always@(posedge clk_a_i)
if(wea_i)
ram[aa_i] <= da_i;
always@(posedge clk_b_i)
qb_o <= ram[ab_i];
endmodule // reconf_ram
module pll_drp_sequencer
(
input clk_sys_i,
input clk_reconf_i,
input [31:0] r_pll_ctl0_i,
input [31:0] r_pll_ctl1_i,
output [31:0] r_pll_status_o,
input pll_locked_i,
output reg pll_rst_o,
output reg [15:0] pll_di_o,
input [15:0] pll_do_i,
input pll_drdy_i,
output reg [4:0] pll_daddr_o,
output reg pll_den_o,
output reg pll_dwe_o,
output busy_o
);
wire [4:0] r_cfg_addr = r_pll_ctl0_i[4:0];
wire [39:0] r_cfg_data = {r_pll_ctl0_i[23:16], r_pll_ctl1_i[31:0]};
wire r_cfg_we = r_pll_ctl0_i[5];
wire r_cfg_trigger = r_pll_ctl0_i[6];
wire [4:0] r_n_regs = r_pll_ctl0_i[11:7];
reg [4:0] index;
wire [39:0] reg_val;
pll_drp_ram ConfRam
(
.clk_a_i(clk_sys_i),
.wea_i(r_cfg_we),
.da_i(r_cfg_data),
.aa_i(r_cfg_addr),
.clk_b_i(clk_reconf_i),
.ab_i(index),
.qb_o(reg_val)
);
`define ST_IDLE 0
`define ST_START_CONFIG 5
`define ST_READ_DRP 1
`define ST_WAIT_READ_DRP 2
`define ST_WRITE_DRP 3
`define ST_WAIT_WRITE_DRP 4
`define ST_READ_ROM 6
`define ST_WAIT_LOCK 7
reg [2:0] state;
reg trig_d0, trig_d1, trig_d2;
reg restart;
reg [15:0] readback;
reg [7:0] powerup_delay = 'hff;
reg rst_powerup = 1;
always@(posedge clk_reconf_i)
if(powerup_delay == 0)
rst_powerup <= 0;
else
powerup_delay <= powerup_delay - 1;
always@(posedge clk_reconf_i or posedge rst_powerup)
if (rst_powerup ) begin
trig_d0 <= 0;
trig_d1 <= 0;
trig_d2 <= 0;
restart <= 0;
end else begin
trig_d0 <= r_cfg_trigger;
trig_d1 <= trig_d0;
trig_d2 <= trig_d1;
restart <= ~trig_d2 & trig_d1;
end
reg [15:0] pll_do_reg;
always@(posedge clk_reconf_i or posedge rst_powerup)
if ( rst_powerup ) begin
state <= `ST_IDLE;
pll_rst_o <= 0;
pll_dwe_o <= 0;
pll_den_o <= 0;
pll_daddr_o <= 0;
end else begin
if(restart)
state <= `ST_START_CONFIG;
else case (state)
`ST_IDLE:
begin
pll_rst_o <= 0;
pll_dwe_o <= 0;
pll_daddr_o <= 0;
pll_den_o <= 0;
index <= 0;
end
`ST_START_CONFIG:
begin
pll_rst_o <= 1;
index <= 0;
state <= `ST_READ_ROM;
end
`ST_READ_ROM:
begin
pll_daddr_o <= reg_val[36:32];
state <= `ST_READ_DRP;
end
`ST_READ_DRP:
begin
pll_den_o <= 1;
pll_dwe_o <= 0;
state <= `ST_WAIT_READ_DRP;
end
`ST_WAIT_READ_DRP:
begin
pll_den_o <= 0;
if (pll_drdy_i)
begin
state <= `ST_WRITE_DRP;
pll_do_reg <= pll_do_i;
end
end
`ST_WRITE_DRP:
begin
pll_di_o <= (pll_do_reg & reg_val[31:16]) | reg_val[15:0];
index <= index + 1;
pll_den_o <= 1;
pll_dwe_o <= 1;
state <= `ST_WAIT_WRITE_DRP;
end
`ST_WAIT_WRITE_DRP:
begin
pll_den_o <= 0;
pll_dwe_o <= 0;
if(pll_drdy_i)
begin
if( index == r_n_regs )
state <= `ST_WAIT_LOCK;
else
state <= `ST_READ_ROM;
end
end // case: `ST_WAIT_WRITE_DRP
`ST_WAIT_LOCK:
begin
pll_rst_o <= 0;
if (pll_locked_i)
state <= `ST_IDLE;
end
endcase // case (state)
end
assign r_pll_status_o[18] = pll_locked_i;
assign busy_o = (state != `ST_IDLE);
endmodule // pll_drp_sequencer
|
#include <bits/stdc++.h> using namespace std; const double PI = 2.0 * acos(0.0); inline int getInt() { int x; scanf( %d , &x); return x; } inline long long getLL() { long long x; scanf( %lld , &x); return x; }; inline int NUM(char c) { return (int)c - 48; } inline char CHR(int n) { return (char)(n + 48); } template <class T> inline T MAX(T a, T b) { if (a > b) return a; return b; } template <class T> inline T MIN(T a, T b) { if (a < b) return a; return b; } inline void OPEN(string s) { freopen((s + .in ).c_str(), r , stdin); freopen((s + .out ).c_str(), w , stdout); } int N; int A[100000 + 5]; int sorted[100000 + 5]; map<int, stack<int> > MAP; int pos[100000 + 5]; int idx = -1; inline bool islucky(int x) { if (x == 0) return false; while (x) { if (x % 10 != 4 && x % 10 != 7) return false; x /= 10; } return true; } vector<pair<int, int> > sol; stack<int> tumpuk; bool found[100000 + 5]; inline int jelajah(int i) { found[i] = true; int root = i; while (pos[i] != root) { sol.push_back(make_pair(i, pos[i])); i = pos[i]; found[i] = true; } return i; } int main() { scanf( %d , &N); for (int i = 0, _n = (N); i < _n; i++) { scanf( %d , &A[i]); if (islucky(A[i])) idx = i; sorted[i] = A[i]; } sort(sorted, sorted + N); bool so = true; for (int i = 0, _n = (N); i < _n; i++) { if (A[i] != sorted[i]) { so = false; } } if (idx == -1 && !so) { puts( -1 ); return 0; } else if (idx == -1) { puts( 0 ); return 0; } for (int i = (N)-1; i >= 0; i--) { MAP[sorted[i]].push(i); } for (int i = 0, _n = (N); i < _n; i++) { int x = A[i]; A[i] = MAP[x].top(); MAP[x].pop(); pos[A[i]] = i; } idx = jelajah(idx); for (int i = 0, _n = (N); i < _n; i++) { if (!found[i]) { tumpuk.push(idx); sol.push_back(make_pair(idx, i)); idx = jelajah(i); } } while ((tumpuk).size() > 0) { sol.push_back(make_pair(idx, tumpuk.top())); idx = tumpuk.top(); tumpuk.pop(); } printf( %d n , (sol).size()); for (int i = 0, _n = ((sol).size()); i < _n; i++) { printf( %d %d n , sol[i].first + 1, sol[i].second + 1); } return 0; } |
/////////////////////////////////////////////////////
// DCM SPI Controller
/////////////////////////////////////////////////////
`timescale 1ns / 1ps
module dcmspi (
input RST, //Synchronous Reset
input PROGCLK, //SPI clock
input PROGDONE, //DCM is ready to take next command
input DFSLCKD,
input [7:0] M, //DCM M value
input [7:0] D, //DCM D value
input GO, //Go programme the M and D value into DCM(1 cycle pulse)
output reg BUSY,
output reg PROGEN, //SlaveSelect,
output reg PROGDATA //CommandData
);
parameter TCQ = 1;
wire [9:0] mval = {M, 1'b1, 1'b1}; //M command: 11,M0-M7
wire [9:0] dval = {D, 1'b0, 1'b1}; //D command: 10,D0-D7
reg dfslckd_q;
reg dfslckd_rising;
always @ (posedge PROGCLK)
begin
dfslckd_q <=#TCQ DFSLCKD;
dfslckd_rising <=#TCQ !dfslckd_q & DFSLCKD;
end
always @ (posedge PROGCLK)
begin
if(RST || (PROGDONE & dfslckd_rising))
BUSY <=#TCQ 1'b0;
else if (GO)
BUSY <=#TCQ 1'b1;
end
reg [9:0] sndval;
reg sndm = 1'b0;
reg sndd = 1'b0;
wire ddone;
SRL16E VCNT (
.Q(ddone), // SRL data output
.A0(1'b1), // Select[0] input
.A1(1'b0), // Select[1] input
.A2(1'b0), // Select[2] input
.A3(1'b1), // Select[3] input
.CE(1'b1), //clock enable
.CLK(PROGCLK), // Clock input
.D(GO) // SRL data input
);
// The following defparam declaration
defparam VCNT.INIT = 16'h0;
always @ (posedge PROGCLK)
begin
if(RST || ddone)
sndd <=#TCQ 1'b0;
else if(GO)
sndd <=#TCQ 1'b1;
end
//V has been sent now it is M's turn
wire ldm;
SRL16E DMGAP (
.Q(ldm), // SRL data output
.A0(1'b0), // Select[0] input
.A1(1'b0), // Select[1] input
.A2(1'b1), // Select[2] input
.A3(1'b0), // Select[3] input
.CE(1'b1), //clock enable
.CLK(PROGCLK), // Clock input
.D(ddone) // SRL data input
);
// The following defparam declaration
defparam DMGAP.INIT = 16'h0;
wire mdone;
SRL16E MCNT (
.Q(mdone), // SRL data output
.A0(1'b1), // Select[0] input
.A1(1'b0), // Select[1] input
.A2(1'b0), // Select[2] input
.A3(1'b1), // Select[3] input
.CE(1'b1), //clock enable
.CLK(PROGCLK), // Clock input
.D(ldm) // SRL data input
);
// The following defparam declaration
defparam MCNT.INIT = 16'h0;
always @ (posedge PROGCLK)
begin
if(RST || mdone)
sndm <=#TCQ 1'b0;
else if(ldm)
sndm <=#TCQ 1'b1;
end
wire gocmd;
SRL16E GOGAP (
.Q(gocmd), // SRL data output
.A0(1'b0), // Select[0] input
.A1(1'b0), // Select[1] input
.A2(1'b1), // Select[2] input
.A3(1'b0), // Select[3] input
.CE(1'b1), //clock enable
.CLK(PROGCLK), // Clock input
.D(mdone) // SRL data input
);
// The following defparam declaration
defparam GOGAP.INIT = 16'h0;
always @ (posedge PROGCLK)
begin
if(RST)
sndval <=#TCQ 10'h0;
else if(GO) //send D first
sndval <=#TCQ dval;
else if(ldm)
sndval <=#TCQ mval;
else if(sndm || sndd)
sndval <=#TCQ sndval >> 1;
end
always @ (posedge PROGCLK)
begin
PROGEN <=#TCQ sndd | sndm | gocmd;
end
always @ (posedge PROGCLK)
begin
if(sndm || sndd)
PROGDATA <=#TCQ sndval[0];
else
PROGDATA <=#TCQ 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MM = 1005; const long long MOD = 1000000007; int vis[MM][MM] = {0}; int n, m, k; bool judge(int x, int y) { if (x - 1 >= 0 && y - 1 >= 0) { if (vis[x - 1][y - 1] && vis[x - 1][y] && vis[x][y - 1]) return true; } if (x - 1 >= 0 && y + 1 < m) { if (vis[x - 1][y + 1] && vis[x - 1][y] && vis[x][y + 1]) return true; } if (x + 1 < n && y - 1 >= 0) { if (vis[x + 1][y - 1] && vis[x][y - 1] && vis[x + 1][y]) return true; } if (x + 1 < n && y + 1 < m) { if (vis[x + 1][y + 1] && vis[x + 1][y] && vis[x][y + 1]) return true; } return false; } int main() { int ans = 0, flag = 0; scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < k; i++) { int x, y; scanf( %d%d , &x, &y); x--; y--; vis[x][y] = 1; if (!flag && judge(x, y)) { ans = i + 1; flag = 1; } } if (!flag) puts( 0 ); else printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 400005; int n, q, K, m, i, j, k, h[N], t[N], num, fa[N], s[N], id[N], size[N], son[N], tp[N], dep[N], head[N], adj[N * 2], nxt[N * 2], p[N], cnt, stk[N], top, g[N], Head[N], Adj[N * 2], Nxt[N * 2], l, f[N]; void dfs(int x, int dad) { size[x] = 1; for (int y = head[x]; y; y = nxt[y]) if (adj[y] != dad) { dep[adj[y]] = dep[x] + 1; fa[adj[y]] = x; dfs(adj[y], x); size[x] += size[adj[y]]; if (!son[x] || size[adj[y]] > size[son[x]]) son[x] = adj[y]; } } void Dfs(int x, int dad) { id[x] = ++i; if (son[x]) { tp[son[x]] = tp[x]; Dfs(son[x], x); } for (int y = head[x]; y; y = nxt[y]) if (adj[y] != dad && adj[y] != son[x]) { tp[adj[y]] = adj[y]; Dfs(adj[y], x); } } int lca(int a, int b) { while (tp[a] != tp[b]) { if (dep[tp[a]] < dep[tp[b]]) swap(a, b); a = fa[tp[a]]; } return dep[a] < dep[b] ? a : b; } int dis(int a, int b) { return dep[a] + dep[b] - 2 * dep[lca(a, b)]; } bool cmp(int a, int b) { return id[a] < id[b]; } void addedge(int u, int v) { Adj[++l] = v; Nxt[l] = Head[u]; Head[u] = l; Adj[++l] = u; Nxt[l] = Head[v]; Head[v] = l; } void dzx(int x, int dad) { if (s[x]) f[x] = x; else f[x] = 0; for (int y = Head[x], a, b; y; y = Nxt[y]) if (Adj[y] != dad) { dzx(Adj[y], x); if (f[Adj[y]] && (!f[x] || 1ll * (a = dis(f[Adj[y]], x) - 1) / s[f[Adj[y]]] < 1ll * (b = dis(f[x], x) - 1) / s[f[x]] || 1ll * (a = dis(f[Adj[y]], x) - 1) / s[f[Adj[y]]] == 1ll * (b = dis(f[x], x) - 1) / s[f[x]] && h[f[Adj[y]]] < h[f[x]])) f[x] = f[Adj[y]]; } if (s[x]) f[x] = x; } void phh(int x, int dad, int u) { int a, b; if (u) { if (u && (!f[x] || 1ll * (a = dis(u, x) - 1) / s[u] < 1ll * (b = dis(f[x], x) - 1) / s[f[x]] || 1ll * (a = dis(u, x) - 1) / s[u] == 1ll * (b = dis(f[x], x) - 1) / s[f[x]] && h[u] < h[f[x]])) f[x] = u; } if (s[x]) f[x] = x; for (int y = Head[x]; y; y = Nxt[y]) if (Adj[y] != dad) phh(Adj[y], x, f[x]); Head[x] = 0; } int main() { scanf( %d , &n); for (i = 1; i < n; ++i) { scanf( %d%d , &j, &k); adj[i * 2 - 1] = k; nxt[i * 2 - 1] = head[j]; head[j] = i * 2 - 1; adj[i * 2] = j; nxt[i * 2] = head[k]; head[k] = i * 2; } dfs(1, -1); tp[1] = 1; i = 0; Dfs(1, -1); scanf( %d , &q); while (q--) { if (n == 10) { for (i = 1; i <= n; ++i) Head[i] = h[i] = s[i] = g[i] = t[i] = p[i] = 0; } scanf( %d%d , &K, &m); num = 0; for (i = 1; i <= K; ++i) { scanf( %d%d , &j, &k); s[j] = k; h[j] = i; t[++num] = j; } for (i = 1; i <= m; ++i) { scanf( %d , &j); g[i] = t[++num] = j; } t[++num] = 1; sort(t + 1, t + 1 + num, cmp); cnt = 0; for (i = 1; i <= num; i = j) { for (j = i; j <= num && t[i] == t[j]; ++j) ; p[++cnt] = t[i]; } if (cnt == 1) { puts( 1 ); continue; } l = 0; stk[1] = p[1], stk[2] = p[2]; top = 2; for (i = 3; i <= cnt; ++i) { while (top > 1 && dep[lca(stk[top], p[i])] <= dep[stk[top - 1]]) { addedge(stk[top - 1], stk[top]); --top; } if ((j = lca(p[i], stk[top])) == stk[top]) stk[++top] = p[i]; else { addedge(j, stk[top]); stk[top] = j; stk[++top] = p[i]; } } while (top > 1) { addedge(stk[top - 1], stk[top]); --top; } dzx(1, -1); phh(1, -1, 0); for (i = 1; i <= m; ++i) printf( %d , h[f[g[i]]]); puts( ); for (i = 1; i <= cnt; ++i) s[p[i]] = 0; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFINV_8_V
`define SKY130_FD_SC_HDLL__BUFINV_8_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog wrapper for bufinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__bufinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__bufinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__bufinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__bufinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFINV_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SEDFXBP_2_V
`define SKY130_FD_SC_HS__SEDFXBP_2_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sedfxbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sedfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sedfxbp_2 (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sedfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SEDFXBP_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int TESTS = 1; while (TESTS--) { int n; cin >> n; vector<long long int> a(n); for (long long int i = 0; i < n; i++) cin >> a[i]; sort((a).begin(), (a).end()); int c = 0; for (long long int i = 0; i < n; i++) { int m = upper_bound((a).begin(), (a).end(), a[i] + 5) - a.begin() - i; if (m > c) c = m; } cout << c; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CONB_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__CONB_PP_BLACKBOX_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CONB_PP_BLACKBOX_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This block is used to breakout the 256 bit streaming ports to and from the write master.
The information sent through the streaming ports is a bundle of wires and buses so it's
fairly inconvenient to constantly refer to them by their position amungst the 256 lines.
This block also provides a layer of abstraction since the descriptor buffers block has
no clue what format the descriptors are in except that the 'go' bit is written to. This
means that using this block you could move descriptor information around without affecting
the top level dispatcher logic.
1.0 06/29/2009 - First version of this block of wires
1.1 02/15/2011 - Added read_early_done_enable to the wire breakout
1.2 11/15/2012 - Added in an additional 32 bits of address for extended descriptors
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_signal_breakout (
read_command_data_in, // descriptor from the read FIFO
read_command_data_out, // reformated descriptor to the read master
// breakout of command information
read_address,
read_length,
read_transmit_channel,
read_generate_sop,
read_generate_eop,
read_park,
read_transfer_complete_IRQ_mask,
read_burst_count, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_stride, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_sequence_number, // when 'ENHANCED_FEATURES' is 0 this will be driven to ground
read_transmit_error,
read_early_done_enable,
// additional control information that needs to go out asynchronously with the command data
read_stop,
read_sw_reset
);
parameter DATA_WIDTH = 256; // 256 bits when enhanced settings are enabled otherwise 128 bits
input [DATA_WIDTH-1:0] read_command_data_in;
output wire [255:0] read_command_data_out;
output wire [63:0] read_address;
output wire [31:0] read_length;
output wire [7:0] read_transmit_channel;
output wire read_generate_sop;
output wire read_generate_eop;
output wire read_park;
output wire read_transfer_complete_IRQ_mask;
output wire [7:0] read_burst_count;
output wire [15:0] read_stride;
output wire [15:0] read_sequence_number;
output wire [7:0] read_transmit_error;
output wire read_early_done_enable;
input read_stop;
input read_sw_reset;
assign read_address[31:0] = read_command_data_in[31:0];
assign read_length = read_command_data_in[95:64];
generate
if (DATA_WIDTH == 256)
begin
assign read_early_done_enable = read_command_data_in[248];
assign read_transmit_error = read_command_data_in[247:240];
assign read_transmit_channel = read_command_data_in[231:224];
assign read_generate_sop = read_command_data_in[232];
assign read_generate_eop = read_command_data_in[233];
assign read_park = read_command_data_in[234];
assign read_transfer_complete_IRQ_mask = read_command_data_in[238];
assign read_burst_count = read_command_data_in[119:112];
assign read_stride = read_command_data_in[143:128];
assign read_sequence_number = read_command_data_in[111:96];
assign read_address[63:32] = read_command_data_in[191:160];
end
else
begin
assign read_early_done_enable = read_command_data_in[120];
assign read_transmit_error = read_command_data_in[119:112];
assign read_transmit_channel = read_command_data_in[103:96];
assign read_generate_sop = read_command_data_in[104];
assign read_generate_eop = read_command_data_in[105];
assign read_park = read_command_data_in[106];
assign read_transfer_complete_IRQ_mask = read_command_data_in[110];
assign read_burst_count = 8'h00;
assign read_stride = 16'h0000;
assign read_sequence_number = 16'h0000;
assign read_address[63:32] = 32'h00000000;
end
endgenerate
// big concat statement to glue all the signals back together to go out to the read master (MSBs to LSBs)
assign read_command_data_out = {{115{1'b0}}, // zero pad the upper 115 bits
read_address[63:32],
read_early_done_enable,
read_transmit_error,
read_stride,
read_burst_count,
read_sw_reset,
read_stop,
read_generate_eop,
read_generate_sop,
read_transmit_channel,
read_length,
read_address[31:0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, q, fa[50005], ff[50005], h[50005], tot, e[50005 << 1], nxt[50005 << 1], mx[50005][256], cnt[50005][256], Ans[50005][256], ans, val[50005], dep[50005]; template <class T> inline void read(T &x) { x = 0; bool emm = 1; char c; for (c = getchar(); c < 0 || c > 9 ; c = getchar()) if (c == - ) emm = -1; for (; c >= 0 && c <= 9 ; c = getchar()) x = (x << 1) + (x << 3) + c - 0 ; x *= emm; } inline void add(int x, int y) { e[++tot] = y, nxt[tot] = h[x], h[x] = tot; } inline void dfs(int x) { dep[x] = dep[fa[x]] + 1; int i; if (dep[x] >= 256) { int l, r, mid, s; for (i = x; dep[x] - dep[i] < 256; i = fa[i]) { mx[x][val[i] >> 8] = max(mx[x][val[i] >> 8], (dep[x] - dep[i] ^ val[i]) & 255); cnt[x][val[i] >> 8]++; } ff[x] = i; for (i = 1; i < 256; i++) cnt[x][i] += cnt[x][i - 1]; for (i = 0; i <= (n - 1) / 256; i++) { for (l = s = 0, r = 256, mid = r >> 1; l < r - 1; mid = l + r >> 1) { if ((s ^ i) < mid) { if (cnt[x][r - 1] > cnt[x][mid - 1]) s |= r - mid, l = mid; else r = mid; } else { if (cnt[x][mid - 1] > ((l) ? cnt[x][l - 1] : 0)) s |= r - mid, r = mid; else l = mid; } } Ans[x][i] = (s << 8) | mx[x][l]; } } for (i = h[x]; i; i = nxt[i]) if (e[i] != fa[x]) fa[e[i]] = x, dfs(e[i]); } int main() { read(n), read(q); for (int i = 1; i <= n; i++) read(val[i]); for (int x, y, i = 1; i < n; i++) read(x), read(y), add(x, y), add(y, x); for (dfs(1); q--;) { int u, v, dis; read(u), read(v); for (dis = ans = 0; dep[v] - dep[u] >= 256; v = ff[v], dis++) ans = max(ans, Ans[v][dis]); for (dis <<= 8; v != fa[u]; v = fa[v], dis++) ans = max(ans, dis ^ val[v]); printf( %d n , ans); } return 0; } |
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 10-12-2018
*/
module jt12_decim #(parameter calcw=18, inw=16,
n=2, // number of stages
m=1, // depth of comb filter
rate=2 // it will stuff with as many as (rate-1) zeros
)(
input rst,
input clk,
(* direct_enable *) input cen_in,
(* direct_enable *) input cen_out,
input signed [inw-1:0] snd_in,
output reg signed [inw-1:0] snd_out
);
reg signed [calcw-1:0] inter6;
wire signed [calcw-1:0] integ_op, comb_op;
localparam wdiff = calcw - inw;
// integrator at clk x cen sampling rate
generate
genvar k2;
reg [calcw-1:0] integ_data[0:n];
assign integ_op = integ_data[n];
always @(*)
integ_data[0] = { {wdiff{snd_in[inw-1]}}, snd_in };
for(k2=1;k2<=n;k2=k2+1) begin : integ_gen
always @(posedge clk)
if(rst) begin
integ_data[k2] <= {calcw{1'b0}};
end else if(cen_in) begin
integ_data[k2] <= integ_data[k2] + integ_data[k2-1];
end
end
endgenerate
// interpolator
always @(posedge clk)
if(rst) begin
inter6 <= {calcw{1'b0}};
end else if(cen_out) begin
inter6 <= integ_op;
end
generate
genvar k;
wire [calcw-1:0] comb_data[0:n];
assign comb_data[0] = inter6;
assign comb_op = comb_data[n];
for(k=0;k<n;k=k+1) begin : com_gen
jt12_comb #(.w(calcw),.m(m)) u_comb(
.rst ( rst ),
.clk ( clk ),
.cen ( cen_out ),
.snd_in ( comb_data[k] ),
.snd_out( comb_data[k+1] )
);
end
endgenerate
// Comb filter at synthesizer sampling rate
always @(posedge clk)
if(rst) begin
snd_out <= {inw{1'b0}};
end else if(cen_out) begin
snd_out<= comb_op[calcw-1:wdiff];
end
endmodule |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:52:04 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_ov7670_controller_1_0 -prefix
// system_ov7670_controller_1_0_ system_ov7670_controller_0_0_stub.v
// Design : system_ov7670_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_controller,Vivado 2016.4" *)
module system_ov7670_controller_1_0(clk, resend, config_finished, sioc, siod, reset,
pwdn, xclk)
/* synthesis syn_black_box black_box_pad_pin="clk,resend,config_finished,sioc,siod,reset,pwdn,xclk" */;
input clk;
input resend;
output config_finished;
output sioc;
inout siod;
output reset;
output pwdn;
output xclk;
endmodule
|
//----------------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact :
//----------------------------------------------------------------------------
// Filename : dbf_clip3.v
// Author : Chewein
// Created : 2014-04-18
// Description : return [x i y]
//----------------------------------------------------------------------------
module db_clip3_str(o,x,y,i);
//---------------------------------------------------------------------------
//
// INPUT/OUTPUT DECLARATION
//
//----------------------------------------------------------------------------
input [7:0] x,y;
input [8:0] i ;
output wire [7:0] o;
assign o = (i<x) ? x : ((i>y) ? y : i[7:0]);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2_4_V
`define SKY130_FD_SC_MS__OR2_4_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2_4_V
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char** argv) { int t; cin >> t; while (t--) { long long int n, k; cin >> n >> k; long long int q = k / (n - 1); long long int r = k % (n - 1); if (r == 0) { cout << n * q - 1 << n ; } else { cout << n * q + r << n ; } } return 0; } |
`default_nettype none
module mmu_table_load(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Load Req
input wire iLD_REQ,
input wire [31:0] iLD_ADDR,
output wire oLD_BUSY,
//Memory Pipe - REQ
output wire oMEM_REQ,
input wire iMEM_LOCK,
output wire [31:0] oMEM_ADDR,
//Memory Pipe - ACK
input wire iMEM_VALID,
input wire [63:0] iMEM_DATA,
//DONE
output wire oDONE_VALID,
output wire [31:0] oDONE_DATA,
output wire [11:0] oDONE_FLAG0,
output wire [11:0] oDONE_FLAG1
);
reg [1:0] b_main_state;
reg [31:0] b_req_addr;
localparam PL_MAIN_STT_IDLE = 2'h0;
localparam PL_MAIN_STT_REQ = 2'h1;
localparam PL_MAIN_STT_WAITING = 2'h2;
wire latch_condition = iLD_REQ && (b_main_state == PL_MAIN_STT_IDLE);
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_req_addr <= 32'h0;
end
else if(iRESET_SYNC)begin
b_req_addr <= 32'h0;
end
else begin
if(latch_condition)begin
b_req_addr <= iLD_ADDR;
end
end
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_main_state <= PL_MAIN_STT_IDLE;
end
else if(iRESET_SYNC)begin
b_main_state <= PL_MAIN_STT_IDLE;
end
else begin
case(b_main_state)
PL_MAIN_STT_IDLE:
begin
if(latch_condition)begin
if(iMEM_LOCK)begin
b_main_state <= PL_MAIN_STT_REQ;
end
else begin
b_main_state <= PL_MAIN_STT_WAITING;
end
end
end
PL_MAIN_STT_REQ:
begin
if(!iMEM_LOCK)begin
b_main_state <= PL_MAIN_STT_WAITING;
end
end
PL_MAIN_STT_WAITING:
begin
if(iMEM_VALID)begin
b_main_state <= PL_MAIN_STT_IDLE;
end
end
default:
begin
b_main_state <= PL_MAIN_STT_IDLE;
end
endcase
end
end
/*
reg b_buff_valid;
reg [31:0] b_buff_data;
reg [11:0] b_buff_flag0;
reg [11:0] b_buff_flag1;
always@(posedge iCLOCK or negedge inRESET)begin
b_buff_valid <= (b_main_state == PL_MAIN_STT_WAITING) && iMEM_VALID;
end
always@(posedge iCLOCK or negedge inRESET)begin
b_buff_data <= (b_req_addr[2])? iMEM_DATA[63:32] : iMEM_DATA[31:0];
b_buff_flag0 <= iMEM_DATA[11:0];
b_buff_flag1 <= iMEM_DATA[43:32];
end
*/
assign oLD_BUSY = (b_main_state != PL_MAIN_STT_IDLE);
//Memory Pipe - REQ
assign oMEM_REQ = (b_main_state == PL_MAIN_STT_REQ) || latch_condition;
assign oMEM_ADDR = (b_main_state == PL_MAIN_STT_REQ)? b_req_addr : iLD_ADDR;
//DONE
assign oDONE_VALID = (b_main_state == PL_MAIN_STT_WAITING) && iMEM_VALID;
assign oDONE_DATA = (b_req_addr[2])? iMEM_DATA[63:32] : iMEM_DATA[31:0];
assign oDONE_FLAG0 = iMEM_DATA[11:0];
assign oDONE_FLAG1 = iMEM_DATA[43:32];
/*
assign oDONE_VALID = b_buff_valid;
assign oDONE_DATA = b_buff_data;
assign oDONE_FLAG0 = b_buff_flag0;
assign oDONE_FLAG1 = b_buff_flag1;
*/
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4BB_2_V
`define SKY130_FD_SC_MS__NAND4BB_2_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4bb_2 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4bb_2 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4BB_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int a; cin >> a; vector<int> b(a); vector<int> c(a); for (int i = 0; i < a; i++) { cin >> b[i]; c[i] = b[i]; } sort(b.begin(), b.end()); int i0 = 0, i1 = 0; for (int i = 0; i < a; i++) { if (c[i] == b[0]) i0 = i; if (c[i] == b[a - 1]) i1 = i; } i1++; i0++; cout << max(max(max(abs(a - i0), abs(a - i1)), abs(1 - i0)), abs(1 - i1)); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EDFXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__EDFXTP_PP_SYMBOL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__edfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input DE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EDFXTP_PP_SYMBOL_V
|
`timescale 1 ns / 1 ps
module intermediator(
input reset,
input clk,
input valid0,
input [63:0] value0,
input [9:0] row0,
input valid1,
input [63:0] value1,
input [9:0] row1,
output store,
output [63:0] store_value,
output add,
output [63:0] add0,
output [63:0] add1,
output [9:0] add_row,
input flush
);
reg [2:0] ctl0_stg0, ctl0_stg1, ctl0_stg2, ctl0_stg3, ctl0_stg4;
reg [2:0] ctl1_stg0, ctl1_stg1, ctl1_stg2, ctl1_stg3, ctl1_stg4;
reg ctl_com_stg0, ctl_com_stg1, ctl_com_stg2, ctl_com_stg3, ctl_com_stg4;
reg [63:0] value0_stg0, value0_stg1, value0_stg2, value0_stg3, value0_stg4;
reg [9:0] row0_stg0, row0_stg1, row0_stg2, row0_stg3, row0_stg4;
reg [63:0] value1_stg0, value1_stg1, value1_stg2, value1_stg3, value1_stg4;
reg [9:0] row1_stg0, row1_stg1, row1_stg2, row1_stg3, row1_stg4;
reg [9:0] lur, har;
reg [31:0] waiter;
reg [1:0] waiter_state;
`define IDLE 0
`define START 1
`define STEADY 2
`define FINISH 3
reg store_ready;
reg r_store;
reg [63:0] r_store_value;
reg r_add;
reg [63:0] r_add0;
reg [63:0] r_add1;
reg [63:0] r_add_row;
wire [63:0] ram_value0, ram_value1;
//OPTIONAL: reduce latency by getting values later.
always @(posedge clk) begin
if(reset) begin
ctl0_stg0 <= 0;
ctl1_stg0 <= 0;
ctl_com_stg0 <= 0;
end else begin
ctl0_stg0 <= {2'H0, valid0};
ctl1_stg0 <= {2'H0, valid1};
ctl_com_stg0 <= 0;
end
value0_stg0 <= value0;
row0_stg0 <= row0;
value1_stg0 <= value1;
row1_stg0 <= row1;
end
always @(posedge clk) begin
ctl0_stg1 <= ctl0_stg0;
ctl1_stg1 <= ctl1_stg0;
ctl_com_stg1 <= (row1_stg0 == row0_stg0) && ctl0_stg0[0] && ctl1_stg0[0];
value0_stg1 <= value0_stg0;
row0_stg1 <= row0_stg0;
value1_stg1 <= value1_stg0;
row1_stg1 <= row1_stg0;
end
always @(posedge clk) begin
ctl0_stg2 <= ctl0_stg1;
ctl1_stg2 <= ctl1_stg1;
if(ctl_com_stg1) begin
ctl0_stg2[1:0] <= 0;
ctl1_stg2[1:0] <= 0;
end
ctl_com_stg2 <= ctl_com_stg1;
value0_stg2 <= value0_stg1;
row0_stg2 <= row0_stg1;
value1_stg2 <= value1_stg1;
row1_stg2 <= row1_stg1;
if(store_ready) begin
if(!(ctl0_stg1[0])) begin
ctl0_stg2[2] <= 1;
row0_stg2 <= lur;
end else if(!ctl1_stg1[0]) begin
ctl1_stg2[2] <= 1;
row1_stg2 <= lur;
end
end
end
//TODO: add state: IDLE, Start, Steady, Finish
//waiter logic
always @(posedge clk) begin
if(reset) begin
lur <= 0;
har <= 0;
waiter <= 0;
waiter_state <= `IDLE;
store_ready <= 0;
end else begin
store_ready <= 0;
har <= {row0_stg0[9:4] + 1, 4'H0};
if(har[4] == row0_stg0[4]) begin
if(har[4])
waiter[31:16] <= 0;
else
waiter[15:0] <= 0;
end
case(waiter_state)
`IDLE: begin
if(ctl0_stg0[0]) begin
waiter_state <= `START;
lur <= {row0_stg0[9:4], 4'H0};
end
waiter <= 0;
end
`START: begin
if(lur[9:4] + 6'H3 == har[9:4])
waiter_state <= `STEADY;
if(flush)
waiter_state <= `FINISH;
end
`STEADY: begin
if(lur[9:4] + 6'H3 != har[9:4])begin
store_ready <= 1;
end
if(flush)
waiter_state <= `FINISH;
end
`FINISH: begin
store_ready <= 1;
if(lur == har)
waiter_state <= `IDLE;
end
endcase
if((!ctl0_stg1[0] || !ctl1_stg1[0]) && store_ready)
lur <= lur + 1;
if(ctl0_stg2[0]) begin
waiter[row0_stg2[4:0]] <= ~waiter[row0_stg2[4:0]];
end
if(ctl1_stg2[0])
waiter[row1_stg2[4:0]] <= ~waiter[row1_stg2[4:0]];
end
end
wire occupied0, occupied1;
assign occupied0 = waiter[row0_stg2[4:0]];
assign occupied1 = waiter[row1_stg2[4:0]];
always @(posedge clk) begin
ctl0_stg3 <= ctl0_stg2;
ctl1_stg3 <= ctl1_stg2;
ctl0_stg3[1] <= ctl0_stg2[0] && !occupied0;
ctl1_stg3[1] <= ctl1_stg2[0] && !occupied1;
ctl_com_stg3 <= ctl_com_stg2;
value0_stg3 <= value0_stg2;
row0_stg3 <= row0_stg2;
value1_stg3 <= value1_stg2;
row1_stg3 <= row1_stg2;
end
block_ram_64x1024 ram(
.clka(clk),
.wea(ctl0_stg3[1]),
.addra(row0_stg3),
.dina(value0_stg3),
.douta(ram_value0),
.clkb(clk),
.web(ctl1_stg3[1]),
.addrb(row1_stg3),
.dinb(value1_stg3),
.doutb(ram_value1));
always @(posedge clk) begin
ctl0_stg4 <= ctl0_stg3;
ctl1_stg4 <= ctl1_stg3;
ctl_com_stg4 <= ctl_com_stg3;
value0_stg4 <= value0_stg3;
row0_stg4 <= row0_stg3;
value1_stg4 <= value1_stg3;
row1_stg4 <= row1_stg3;
end
wire overflow_fifo_rd;
reg overflow_fifo_rd1;
wire overflow_fifo_empty, overflow_fifo_full;
wire [9:0] overflow_fifo_row;
wire [63:0] overflow_fifo_value0;
wire [63:0] overflow_fifo_value1;
assign overflow_fifo_rd = (ctl0_stg3[1:0] != 2'H1) && !ctl_com_stg3 && !overflow_fifo_empty;
always @(posedge clk) begin
overflow_fifo_rd1 <= overflow_fifo_rd;
end
fifo_138x16_shift overflow_fifo(
.clk(clk),
.srst(reset),
.din({row1_stg4, value1_stg4, ram_value1}),
.wr_en((ctl1_stg4[1:0] == 2'H1)),
.rd_en(overflow_fifo_rd),
.dout({overflow_fifo_row, overflow_fifo_value0, overflow_fifo_value1}),
.full(overflow_fifo_full),
.empty(overflow_fifo_empty));
always @(posedge clk) begin
r_add <= 0;
r_add0 <= 0;
r_add1 <= 0;
r_add_row <= 0;
if(ctl_com_stg4) begin
r_add <= 1;
r_add0 <= value0_stg4;
r_add1 <= value1_stg4;
r_add_row <= row0_stg4;
end else if(ctl0_stg4[1:0] == 2'H1) begin
r_add <= 1;
r_add0 <= value0_stg4;
r_add1 <= ram_value0;
r_add_row <= row0_stg4;
end else if(overflow_fifo_rd1) begin
r_add <= 1;
r_add0 <= overflow_fifo_value0;
r_add1 <= overflow_fifo_value1;
r_add_row <= overflow_fifo_row;
end
end
assign add = r_add;
assign add0 = r_add0;
assign add1 = r_add1;
assign add_row = r_add_row;
always @(posedge clk) begin
r_store <= 0;
r_store_value <= 0;
if(reset)
r_store <= 0;
if(ctl0_stg4[2]) begin
r_store <= 1;
r_store_value <= ram_value0;
end else if(ctl1_stg4[2]) begin
r_store <= 1;
r_store_value <= ram_value1;
end
end
assign store = r_store;
assign store_value = r_store_value;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200007; int n, m, q, p[N], a[N], apre[N], lst[N], ppre[N], fa[N], dep[N], w[N], b[N]; vector<int> G[N]; int max(int a, int b) { return a > b ? a : b; } int min(int a, int b) { return a < b ? a : b; } int read() { int x; scanf( %d , &x); return x; } void dfs(int u) { int i, v; b[dep[u]] = u, w[u] = dep[u] >= n ? b[dep[u] - (n - 1)] : m + 1; for (i = G[u].size() - 1; ~i; --i) v = G[u][i], dep[v] = dep[u] + 1, dfs(v); } int main() { n = read(), m = read(), q = read(); int i, j; for (i = 1; i <= n; ++i) p[i] = read(); p[0] = p[n]; for (i = 1; i <= n; ++i) ppre[p[i]] = p[i - 1]; for (i = 1; i <= m; ++i) { a[i] = read(), apre[i] = lst[a[i]], lst[a[i]] = i; for (j = lst[ppre[a[i]]]; j && !fa[j]; j = apre[j]) fa[j] = i; } for (i = 1; i <= m; ++i) fa[i] ? G[fa[i]].push_back(i) : G[0].push_back(i); dfs(0); for (i = m - 1; i; --i) w[i] = min(w[i + 1], w[i]); while (q--) i = read(), j = read(), putchar(48 + (w[i] <= j)); } |
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: wb_ram_32x8192.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module wb_ram_32x8192 (
address,
byteena,
clock,
data,
wren,
q);
input [12:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "TRUE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL wb_ram_32x8192.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL wb_ram_32x8192.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL wb_ram_32x8192.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL wb_ram_32x8192.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL wb_ram_32x8192_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL wb_ram_32x8192_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:2000000 ) #pragma comment(linker, /HEAP:2000000 ) using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; long long m[n][n], a[n]; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> m[i][j]; } } long long x = sqrt((m[0][1] * m[0][2]) / m[1][2]); cout << x << ; for (int i = 1; i < n; i++) { cout << m[0][i] / x << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; char inp[200005]; int main() { bool ok; queue<int> zeroes, ones; vector<int> vec[200005]; int n_vec = 0, n_z = 0, n_o = 0, tam; scanf( %s , inp); tam = strlen(inp); if (inp[0] == 1 ) cout << -1 << endl; else { vec[n_vec++].push_back(0); zeroes.push(0); n_z++; ok = true; for (int i = 1; i < tam; i++) { if (inp[i] == 0 ) { if (n_o == 0) { vec[n_vec++].push_back(i); zeroes.push(n_vec - 1); n_z++; } else { int q = ones.front(); vec[q].push_back(i); zeroes.push(q); n_z++; ones.pop(); n_o--; } } else { if (n_z == 0) { ok = false; break; } else { int q = zeroes.front(); vec[q].push_back(i); ones.push(q); n_o++; zeroes.pop(); n_z--; } } } if (n_o != 0) ok = false; if (!ok) printf( -1 n ); else { printf( %d n , n_vec); vector<int>::iterator vit; for (int i = 0; i < n_vec; i++) { printf( %d , vec[i].size()); vit = vec[i].begin(); while (vit != vec[i].end()) { printf( %d , (*vit) + 1); vit++; } printf( n ); } } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DFF_P_PP_PG_N_BLACKBOX_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$P_pp$PG$N (
Q ,
D ,
CLK ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_P_PP_PG_N_BLACKBOX_V
|
//#############################################################################
//# Function: Generic Memory #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_ram # (parameter DW = 104, // memory width
parameter DEPTH = 32, // memory depth
parameter REG = 1, // register output
parameter DUALPORT= 1, // limit dual port
parameter AW = $clog2(DEPTH) // address width
)
(// read-port
input rd_clk,// rd clock
input rd_en, // memory access
input [AW-1:0] rd_addr, // address
output [DW-1:0] rd_dout, // data output
// write-port
input wr_clk,// wr clock
input wr_en, // memory access
input [AW-1:0] wr_addr, // address
input [DW-1:0] wr_wem, // write enable vector
input [DW-1:0] wr_din, // data input
// BIST interface
input bist_en, // bist enable
input bist_we, // write enable global signal
input [DW-1:0] bist_wem, // write enable vector
input [AW-1:0] bist_addr, // address
input [DW-1:0] bist_din, // data input
input [DW-1:0] bist_dout, // data input
// Power/repair (hard macro only)
input shutdown, // shutdown signal
input vss, // ground signal
input vdd, // memory array power
input vddio, // periphery/io power
input [7:0] memconfig, // generic memory config
input [7:0] memrepair // repair vector
);
reg [DW-1:0] ram [0:DEPTH-1];
wire [DW-1:0] rdata;
wire [AW-1:0] dp_addr;
integer i;
//#########################################
//limiting dual port
//#########################################
assign dp_addr[AW-1:0] = (DUALPORT==1) ? rd_addr[AW-1:0] :
wr_addr[AW-1:0];
//#########################################
//write port
//#########################################
always @(posedge wr_clk)
for (i=0;i<DW;i=i+1)
if (wr_en & wr_wem[i])
ram[wr_addr[AW-1:0]][i] <= wr_din[i];
//#########################################
//read port
//#########################################
assign rdata[DW-1:0] = ram[dp_addr[AW-1:0]];
//Configurable output register
reg [DW-1:0] rd_reg;
always @ (posedge rd_clk)
if(rd_en)
rd_reg[DW-1:0] <= rdata[DW-1:0];
//Drive output from register or RAM directly
assign rd_dout[DW-1:0] = (REG==1) ? rd_reg[DW-1:0] :
rdata[DW-1:0];
endmodule // oh_ram
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Physical-Channel (Channel-level) Flow-Control
* ============================================
*
*
* Credit Counter Optimization (for credit-based flow-control)
* ===========================
*
* optimized_credit_counter = 0 | 1
*
* Set to '1' to move credit counter logic to start of next clock cycle.
* Remove add/sub from critical path.
*
* To move add/sub logic we buffer the last credit rec. and the any
* flit sent on the output.
*
*/
module LAG_pl_fc_out (flits_valid,
channel_cntrl_in,
pl_status, // pl_status[pl]=1 if blocked (fifo is full)
pl_empty, // pl_empty[pl]=1 if PL fifo is empty (credits=init_credits)
pl_credits,
clk, rst_n);
parameter num_pls = 4;
parameter init_credits = 4;
parameter optimized_credit_counter = 1;
// +1 as has to hold 'init_credits' value
parameter counter_bits = clogb2(init_credits+1);
input [num_pls-1:0] flits_valid;
input [num_pls-1:0] channel_cntrl_in;
output logic [num_pls-1:0] pl_status;
output [num_pls-1:0] pl_empty;
output [num_pls-1:0][counter_bits-1:0] pl_credits;
input clk, rst_n;
logic [num_pls-1:0][counter_bits-1:0] counter;
logic [num_pls-1:0] inc, dec;
// buffer credit and flit pl id.'s so we can move counter in credit counter optimization
logic [num_pls-1:0] last_flits_valid;
logic [num_pls-1:0] last_credits;
logic [num_pls-1:0][counter_bits-1:0] counter_current;
logic [num_pls-1:0] pl_empty;
genvar i;
// fsm states
parameter stop=1'b0, go=1'b1;
logic [num_pls-1:0] current_state, next_state;
generate
if (optimized_credit_counter) begin
// ***********************************
// optimized credit-counter (moves counter logic off critical path)
// ***********************************
always@(posedge clk) begin
last_credits <= channel_cntrl_in;
last_flits_valid <= flits_valid;
// $display ("empty=%b", pl_empty);
end
assign pl_credits = counter_current;
for (i=0; i<num_pls; i++) begin:perpl1
always_comb begin:addsub
if (inc[i] && !dec[i])
counter_current[i]=counter[i]+1;
else if (dec[i] && !inc[i])
counter_current[i]=counter[i]-1;
else
counter_current[i]=counter[i];
end
always@(posedge clk) begin
if (!rst_n) begin
counter[i]<=init_credits;
pl_empty[i]<='1;
end else begin
counter[i]<=counter_current[i];
if ((counter_current[i]==0) ||
((counter_current[i]==1) && flits_valid[i]) &&
!(channel_cntrl_in[i])) begin
pl_status[i] <= 1'b1;
pl_empty[i] <= 1'b0;
end else begin
pl_status[i] <= 1'b0;
pl_empty[i] <= (counter_current[i]==init_credits);
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
assign inc[i] = last_credits[i];
assign dec[i] = last_flits_valid[i];
end
end else begin
assign pl_credits = counter;
// ***********************************
// unoptimized credit-counter
// ***********************************
for (i=0; i<num_pls; i++) begin:perpl
always@(posedge clk) begin
if (!rst_n) begin
counter[i]<=init_credits;
end else begin
if (inc[i] && !dec[i]) begin
assert (counter[i]!=init_credits) else $fatal;
counter[i]<=counter[i]+1;
end
if (dec[i] && !inc[i]) begin
assert (counter[i]!=0) else $fatal;
counter[i]<=counter[i]-1;
end
end // else: !if(!rst_n)
end
// received credit for PL i?
assign inc[i]= channel_cntrl_in[i];
// flit sent, one less credit
assign dec[i] = flits_valid[i];
// if counter==0, PL is blocked
assign pl_status[i]=(counter[i]==0);
// if counter==init_credits, PL buffer is empty
assign pl_empty[i]=(counter[i]==init_credits);
end // block: perpl
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_SYMBOL_V
`define SKY130_FD_SC_HS__O221AI_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o221ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_SYMBOL_V
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_softusb();
reg sys_clk;
reg sys_rst;
reg usb_clk;
reg [31:0] wb_adr_i;
reg [31:0] wb_dat_i;
wire [31:0] wb_dat_o;
reg wb_cyc_i;
reg wb_stb_i;
reg wb_we_i;
wire wb_ack_o;
reg [13:0] csr_a;
reg csr_we;
reg [31:0] csr_di;
wire [31:0] csr_do;
wire irq;
/* 100MHz system clock */
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
/* 50MHz USB clock (should be 48) */
initial usb_clk = 1'b0;
always #10 usb_clk = ~usb_clk;
wire usba_vp;
wire usba_vm;
softusb dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.usb_clk(usb_clk),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_do(csr_do),
.csr_di(csr_di),
.irq(irq),
.wb_adr_i(wb_adr_i),
.wb_dat_i(wb_dat_i),
.wb_dat_o(wb_dat_o),
.wb_cyc_i(wb_cyc_i),
.wb_stb_i(wb_stb_i),
.wb_we_i(wb_we_i),
.wb_sel_i(4'hf),
.wb_ack_o(wb_ack_o),
.usba_spd(),
.usba_oe_n(),
.usba_rcv(usba_vp),
.usba_vp(usba_vp),
.usba_vm(usba_vm),
.usbb_spd(),
.usbb_oe_n(),
.usbb_rcv(),
.usbb_vp(),
.usbb_vm()
);
task waitclock;
begin
@(posedge sys_clk);
#1;
end
endtask
task wbwrite;
input [31:0] address;
input [31:0] data;
integer i;
begin
wb_adr_i = address;
wb_dat_i = data;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b1;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
waitclock;
$display("WB Write: %x=%x acked in %d clocks", address, data, i);
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task wbread;
input [31:0] address;
integer i;
begin
wb_adr_i = address;
wb_cyc_i = 1'b1;
wb_stb_i = 1'b1;
wb_we_i = 1'b0;
i = 0;
while(~wb_ack_o) begin
i = i+1;
waitclock;
end
$display("WB Read : %x=%x acked in %d clocks", address, wb_dat_o, i);
waitclock;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
end
endtask
task csrwrite;
input [31:0] address;
input [31:0] data;
begin
csr_a = address[16:2];
csr_di = data;
csr_we = 1'b1;
waitclock;
$display("CSR write: %x=%x", address, data);
csr_we = 1'b0;
end
endtask
task csrread;
input [31:0] address;
begin
csr_a = address[16:2];
waitclock;
$display("CSR read : %x=%x", address, csr_do);
end
endtask
always begin
$dumpfile("softusb.vcd");
$dumpvars(0, dut);
/* Reset / Initialize our logic */
sys_rst = 1'b1;
wb_adr_i = 32'd0;
wb_dat_i = 32'd0;
wb_cyc_i = 1'b0;
wb_stb_i = 1'b0;
wb_we_i = 1'b0;
waitclock;
sys_rst = 1'b0;
waitclock;
csrwrite(32'h00, 32'h00);
#7000;
wbread(32'h00020000);
wbread(32'h00020004);
$finish;
end
/* transmitter */
reg usb_clk_tx;
initial usb_clk_tx = 1'b0;
always #10 usb_clk_tx = ~usb_clk_tx;
reg usb_rst_tx;
reg [7:0] tx_data;
reg tx_valid;
wire txp;
wire txm;
wire txoe;
softusb_tx tx(
.usb_clk(usb_clk_tx),
.usb_rst(usb_rst_tx),
.tx_data(tx_data),
.tx_valid(tx_valid),
.tx_ready(),
.txp(txp),
.txm(txm),
.txoe(txoe),
.low_speed(1'b0),
.generate_eop(1'b0)
);
pullup(usba_vp);
pulldown(usba_vm);
assign usba_vp = txoe ? txp : 1'bz;
assign usba_vm = txoe ? txm : 1'bz;
initial begin
$dumpvars(0, tx);
usb_rst_tx = 1'b1;
tx_valid = 1'b0;
#20;
usb_rst_tx = 1'b0;
#4000;
tx_data = 8'h80;
tx_valid = 1'b1;
#400;
tx_data = 8'h56;
#400;
tx_valid = 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > Sh; const int tmax = 155; char table[tmax][tmax]; pair<int, int> mow[tmax]; pair<int, int> ccount(int row, int side, int ai) { if (mow[row].second == 0 && mow[row + 1].second == 0) return make_pair(0, ai); if (mow[row].second == 0) { if (side == 0 && ai < mow[row + 1].second) return make_pair(mow[row + 1].second - ai, mow[row + 1].second); else if (side == 1 && ai >= mow[row + 1].first) return make_pair(ai - mow[row + 1].first, mow[row + 1].first); else return make_pair(0, ai); } if (mow[row + 1].second == 0) { if (side == 0) return make_pair(mow[row].second - ai, mow[row].second); else return make_pair(ai - mow[row].first, mow[row].first); } if (side == 0) return make_pair(max(mow[row + 1].second, mow[row].second) - ai, max(mow[row + 1].second, mow[row].second)); else return make_pair(ai - min(mow[row + 1].first, mow[row].first), min(mow[row + 1].first, mow[row].first)); } int main() { int N, M; scanf( %d %d , &N, &M); for (int i = 0; i < tmax; i++) mow[i].first = 1 << 30, mow[i].second = 0; int last = 0; for (int i = 1; i <= N; i++) { for (int j = 1; j <= M; j++) { scanf( %c , &table[i][j]); if (table[i][j] == W ) { mow[i].first = min(j, mow[i].first); mow[i].second = max(j, mow[i].second); last = max(last, i); } } } int side = 0, howmany = 0; int ai = 1; for (int i = 1; i < N; i++) { pair<int, int> ret = ccount(i, side, ai); howmany += ret.first; ai = ret.second; side ^= 1; } if (mow[N].second) { if (side) howmany += ai - mow[N].first; else howmany += mow[N].second - ai; } printf( %d n , max(howmany + last - 1, 0)); return 0; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate task w/ simple input.
module main;
reg globvar;
task my_task ;
input in1;
globvar = in1;
endtask
initial
begin
globvar = 1'b0;
my_task(1'b1);
if(globvar)
$display("PASSED");
else
$display("FAILED - task 3.14B task didn't correctly affect global var");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int ans = 0, visited[200005] = {0}; vector<int> edges[200005]; void dfs(int x) { visited[x] = 1; if (visited[edges[x][0]] == 1) ans++; else dfs(edges[x][0]); } int main() { int n, i, x, count = 0; cin >> n; for (i = 1; i <= n; i++) { cin >> x; edges[i].push_back(x); } for (i = 1; i <= n; i++) { cin >> x; if (x == 1) count++; } for (i = 1; i <= n; i++) if (visited[i] == 0) dfs(i); if (ans == 1) ans = 0; if (count % 2 == 0) ans++; cout << ans; } |
#include <bits/stdc++.h> using namespace std; vector<string> tmp; long long num(string str) { int len = str.size(); long long res = 0; for (int i = 0; i < len; i++) { res = res * 10 + str[i] - 0 ; } return res; } void solve(int N) { queue<string> q; q.push( 11 ); q.push( 22 ); q.push( 33 ); q.push( 44 ); q.push( 55 ); q.push( 66 ); q.push( 77 ); q.push( 88 ); q.push( 99 ); tmp.push_back( 11 ); tmp.push_back( 22 ); tmp.push_back( 33 ); tmp.push_back( 44 ); tmp.push_back( 55 ); tmp.push_back( 66 ); tmp.push_back( 77 ); tmp.push_back( 88 ); tmp.push_back( 99 ); while (!q.empty()) { string str = q.front(); q.pop(); if (tmp.size() >= N) return; for (int i = 0; i < 10; i++) { char ch = i + 48; int l = str.size() / 2; string kp = str.substr(0, l) + ch + ch + str.substr(l, l); tmp.push_back(kp); q.push(kp); } } } int main() { int k, p; scanf( %d%d , &k, &p); solve(k); long long res = 0; for (int i = 0; i < k; i++) { res = (res + num(tmp[i])) % p; } cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { int n, k; cin >> n >> k; long long a1[n], b1[n]; for (int i = 0; i < n; i++) cin >> a1[i] >> b1[i]; long long dp[n][k]; vector<long long> a, b; vector<pair<pair<long long, long long>, long long> > e; vector<long long> ans; long long mx = 0; for (int p = 0; p < n; p++) { a.clear(); b.clear(); e.clear(); for (int i = 0; i < n; i++) if (i == p) continue; else e.push_back(make_pair(make_pair(b1[i], a1[i]), i)); sort(e.begin(), e.end()); a.push_back(0); b.push_back(0); for (int i = 0; i < e.size(); i++) { a.push_back(e[i].first.second); b.push_back(e[i].first.first); } for (int i = 0; i < n; i++) for (int j = 0; j < k; j++) dp[i][j] = -1e9; dp[0][0] = 0; for (int i = 1; i < n; i++) for (int j = 0; j < k; j++) { dp[i][j] = max(dp[i][j], dp[i - 1][j] + b[i] * (k - 1)); if (j > 0) dp[i][j] = max(dp[i][j], dp[i - 1][j - 1] + b[i] * (j - 1) + a[i]); } if (mx < a1[p] + b1[p] * (k - 1) + dp[n - 1][k - 1]) { mx = a1[p] + b1[p] * (k - 1) + dp[n - 1][k - 1]; vector<long long> x, bad; int i = n - 1, j = k - 1; while (dp[i][j] > 0) { if (j > 0) { if (dp[i - 1][j - 1] + b[i] * (j - 1) + a[i] == dp[i][j]) { x.push_back(e[i - 1].second + 1); i--; j--; } else { bad.push_back(-e[i - 1].second - 1); bad.push_back(e[i - 1].second + 1); i--; } } else { bad.push_back(-e[i - 1].second - 1); bad.push_back(e[i - 1].second + 1); i--; } } reverse(x.begin(), x.end()); reverse(bad.begin(), bad.end()); for (int i = 0; i < bad.size(); i++) x.push_back(bad[i]); x.push_back(p + 1); ans = x; } } cout << ans.size() << n ; for (int i = 0; i < ans.size(); i++) cout << ans[i] << ; cout << n ; } int main() { ios::sync_with_stdio(0); int q; cin >> q; while (q--) solve(); } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_2_cols_V_channel_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_2_cols_V_channel (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_2_cols_V_channel_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_2_cols_V_channel_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUF_4_V
`define SKY130_FD_SC_HDLL__BUF_4_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__buf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__buf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUF_4_V
|
#include <bits/stdc++.h> using namespace std; const int MX_N = (1e3) + 3; int a[MX_N][MX_N]; int main() { int n; scanf( %d , &n); if (n == 4) puts( -1 ); else { for (int i = 0; i < n; ++i) { for (int j = i - 2; j >= 0; j -= 2) a[i][j] = 1; for (int j = i + 1; j < n; j += 2) a[i][j] = 1; } if (!(n & 1)) { a[0][n - 1] = 0; a[n - 1][0] = 1; a[0][2] = 1; a[2][0] = 0; } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { if (j) printf( ); printf( %d , a[i][j]); } printf( n ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; list<char> lanc; using It = list<char>::iterator; bool torolni_kell(It mit) { if (*mit == - ) return false; char akt = *mit, el = *prev(mit), kov = *next(mit); return (el != - && el != akt) || (kov != - && kov != akt); } int main() { ios_base::sync_with_stdio(false); string be; cin >> be; be = - + be + - ; lanc.insert(begin(lanc), begin(be), end(be)); int valasz = 0; vector<It> to_check; for (It it = next(lanc.begin()); *it != - ; ++it) to_check.push_back(it); while (1) { vector<It> torlendok; for (It akt : to_check) if (torolni_kell(akt)) torlendok.push_back(akt); to_check = {}; for (int i = 0; i < torlendok.size(); i++) { if ((i == 0 || prev(torlendok[i]) != torlendok[i - 1]) && (to_check.empty() || to_check.back() != prev(torlendok[i]))) to_check.push_back(prev(torlendok[i])); if ((i + 1 == torlendok.size() || next(torlendok[i]) != torlendok[i + 1]) && (to_check.empty() || to_check.back() != next(torlendok[i]))) to_check.push_back(next(torlendok[i])); } if (torlendok.empty()) break; for (auto akt : torlendok) lanc.erase(akt); valasz++; } cout << valasz; } |
#include <bits/stdc++.h> using namespace std; typedef const int &ci; inline int read() { int x = 0; char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); while ( 0 <= c && c <= 9 ) x = 10 * x + c - 0 , c = getchar(); return x; } inline void Max(int &x, ci y) { if (x < y) x = y; } const int N = 2003; int n, m, k, Ans, ans[N]; int px[N], py[N]; char c[N][N]; int f[N][N]; int u[N][N], d[N][N]; int h1, t1, q1[N]; int h2, t2, q2[N]; inline void Calc(int *a, int *b) { q1[h1 = t1 = 1] = 1, q2[h2 = t2 = 1] = 1; for (int l = 1, r = 1; r <= m; l++) { while (h1 <= t1 && q1[h1] < l) h1++; while (h2 <= t2 && q2[h2] < l) h2++; while (r < l || r - l + 1 <= a[q1[h1]] + b[q2[h2]] - 1) { Max(Ans, r - l + 1), r++; while (h1 <= t1 && a[q1[t1]] >= a[r]) t1--; q1[++t1] = r; while (h2 <= t2 && b[q2[t2]] >= b[r]) t2--; q2[++t2] = r; } Max(Ans, a[q1[h1]] + b[q2[h2]] - 1); } } int main() { n = read(), m = read(), k = read(); for (int i = 1; i <= n; i++) scanf( %s , c[i] + 1); for (int i = 1; i <= k; i++) { px[i] = read(), py[i] = read(); c[px[i]][py[i]] = # ; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (c[i][j] == . ) { f[i][j] = min(f[i - 1][j - 1], min(f[i - 1][j], f[i][j - 1])) + 1; Max(Ans, f[i][j]); u[i][j] = u[i - 1][j] + 1; } for (int i = n; i >= 1; i--) for (int j = m; j >= 1; j--) if (c[i][j] == . ) d[i][j] = d[i + 1][j] + 1; for (int Cas = k, x, y; Cas >= 1; Cas--) { ans[Cas] = Ans, c[x = px[Cas]][y = py[Cas]] = . ; for (int i = x; i <= n; i++) if (c[i][y] == . ) u[i][y] = u[i - 1][y] + 1; for (int i = x; i >= 1; i--) if (c[i][y] == . ) d[i][y] = d[i + 1][y] + 1; Calc(u[x], d[x]); } for (int i = 1; i <= k; i++) printf( %d n , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MX = 100 * 1000 + 7; int a[MX]; int hup[MX], hdown[MX]; long long cup[MX], cdown[MX]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int i = 1; i <= n; i++) { int cost = 0; if (a[i] <= hup[i - 1]) cost = (hup[i - 1] + 1 - a[i]); hup[i] = a[i] + cost; cup[i] = cup[i - 1] + cost; } for (int i = n; i >= 1; i--) { int cost = 0; if (a[i] <= hdown[i + 1]) cost = (hdown[i + 1] + 1 - a[i]); hdown[i] = a[i] + cost; cdown[i] = cdown[i + 1] + cost; } long long res = (long long)1e18; for (int i = 1; i <= n; i++) { int need = max(hup[i - 1] + 1, hdown[i + 1] + 1); int cost = 0; if (a[i] < need) cost = need - a[i]; res = min(res, cup[i - 1] + cdown[i + 1] + cost); } printf( %lld n , res); } |
// file: int_skew_dcm.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___120.005______0.000______50.0______200.000_____60.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________120.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "int_skew_dcm,clk_wiz_v3_2,{component_name=int_skew_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=8.333,clkin2_period=8.333,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module int_skew_dcm
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
assign clkin1 = CLK_IN1;
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (1),
.CLKFX_MULTIPLY (4),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (8.333),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (RESET),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
assign clkfb = CLK_OUT1;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clk0));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxl = 100000; map<int, int> SG, num; int n, x, tmp, ans = 0, prime[maxl], tot = 0; bool notprime[maxl + 1]; inline void init() { notprime[1] = 1; for (int i = 2; i <= maxl; i++) { if (!notprime[i]) prime[++tot] = i; for (int j = 1; j <= tot && i * prime[j] <= maxl; j++) { notprime[i * prime[j]] = 1; if (i % prime[j] == 0) break; } } } inline int solve(int x) { if (x == 0) return 0; if (SG.count(x)) return SG[x]; map<int, int> vis; int p = x, t = 0; while (p) { p /= 2; t++; } for (int i = 1; i <= t; i++) vis[solve((x >> i) | (x & ((1 << (i - 1)) - 1)))] = 1; for (int i = 0;; i++) if (!vis[i]) return SG[x] = i; } int main() { init(); scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &x); for (int pos = 1; prime[pos] * prime[pos] <= x; pos++) { tmp = 0; while (x % prime[pos] == 0) { x /= prime[pos]; tmp++; } if (tmp != 0) num[prime[pos]] = num[prime[pos]] | (1 << (tmp - 1)); } if (x != 1) num[x] |= 1; } for (map<int, int>::iterator it = num.begin(); it != num.end(); it++) ans = ans ^ solve(it->second); if (ans == 0) puts( Arpa ); else puts( Mojtaba ); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const int N = 3e5 + 10; int flag[N]; set<int> s[N]; int a[N]; int pos[N]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); pos[a[i]] = i; } while (m--) { int x, y; scanf( %d%d , &x, &y); if (x == a[n]) continue; if (y == a[n]) { flag[x] = 1; } s[x].emplace(y); } int ans = n; for (int i = n - 1; i > 0; i--) { if (flag[a[i]]) { int cnt = 0; for (auto& x : s[a[i]]) { if (pos[x] < i) continue; if (pos[x] >= ans) continue; cnt++; } if (cnt != ans - i - 1) flag[a[i]] = 0; else { for (int j = i; j < ans; j++) { int x = a[j], y = a[j + 1]; swap(a[j], a[j + 1]); swap(pos[x], pos[y]); } ans--; } } } printf( %d n , n - ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int _1e5 = 100000; const int _1e7 = 10000000; const int _1e9 = 1000000000; template <typename A, typename B> ostream& operator<<(ostream& str, const pair<A, B>& p) { return str << ( << p.first << , << p.second << ) ; } template <typename T> ostream& operator<<(ostream& str, const vector<T>& v) { str << [ ; for (const auto& n : v) str << n << , ; str << ] ; return str; } template <typename T> ostream& operator<<(ostream& str, const set<T>& v) { str << { ; for (const auto& n : v) { str << n << , ; } str << } ; return str; } template <typename K, typename V> ostream& operator<<(ostream& str, const unordered_map<K, V>& v) { str << { ; for (const auto& p : v) { str << p.first << => << p.second << , ; } str << } ; return str; } int main() { ios_base::sync_with_stdio(false); cout.setf(std::ios::fixed); cout.precision(12); int n; cin >> n; string a; cin >> a; vector<int> f(10); f[0] = 0; for (int i = 1; i <= 9; ++i) { cin >> f[i]; } int left_start = -1; for (int i = 0; i < a.size(); ++i) { int digit = a[i] - 0 ; if (f[digit] > digit) { left_start = i; break; } } if (left_start == -1) { cout << a << endl; return 0; } while (true) { if (left_start >= a.size()) { break; } int digit = a[left_start] - 0 ; if (f[digit] < digit) { break; } a[left_start++] = 0 + f[digit]; } cout << a << endl; } |
#include <bits/stdc++.h> char chars[200005]; int main() { int n; scanf( %d , &n); scanf( %s , chars); int sum = 0; for (int i = 0; i < n; i++) { if (chars[i] == < ) { sum++; } else { break; } } for (int i = n - 1; i >= 0 && sum < n; i--) { if (chars[i] == > ) { sum++; } else { break; } } printf( %d n , sum); } |
`timescale 1 ns / 1 ps
module axis_measure_pulse #
(
parameter integer AXIS_TDATA_WIDTH = 16,
parameter integer CNTR_WIDTH = 16,
parameter integer PULSE_WIDTH = 16,
parameter integer BRAM_DATA_WIDTH = 16,
parameter integer BRAM_ADDR_WIDTH = 16
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [PULSE_WIDTH*4+95:0] cfg_data,
output wire overload,
output wire [2:0] case_id,
output wire [31:0] sts_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
output wire m_axis_tlast,
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata
);
wire [PULSE_WIDTH-1:0] total_sweeps,ramp,width,offset_width;
wire [BRAM_ADDR_WIDTH-1:0] waveform_length, pulse_length;
wire signed [31:0] threshold, magnitude;
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next, int_cntr_sweeps_reg, int_cntr_sweeps_next;
reg [2:0] int_case_reg, int_case_next;
reg signed [31:0] pulse,pulse_next,offset,offset_next,result,result_next;
reg [BRAM_ADDR_WIDTH-1:0] wfrm_start,wfrm_start_next,wfrm_point,wfrm_point_next;
reg [BRAM_ADDR_WIDTH-1:0] int_addr, int_addr_next;
reg int_enbl_reg, int_enbl_next;
reg int_last_pulse_reg, int_last_pulse_next;
wire int_comp_wire, int_tlast_wire, wfrm_point_comp;
// default cfg_data: total_sweeps[16]:ramp[16]:width[16]:unused[16]:threshold[32]:waveform_length[32]:pulse_length[32]
assign total_sweeps = cfg_data[PULSE_WIDTH-1:0];
assign ramp = cfg_data[PULSE_WIDTH*2-1:PULSE_WIDTH];
assign width = cfg_data[PULSE_WIDTH*3-1:PULSE_WIDTH*2];
assign offset_width = width[PULSE_WIDTH-2:1];
assign threshold = $signed(cfg_data[PULSE_WIDTH*4+31:PULSE_WIDTH*4]);
assign waveform_length = cfg_data[PULSE_WIDTH*4+BRAM_ADDR_WIDTH+31:PULSE_WIDTH*4+32];
assign pulse_length = cfg_data[PULSE_WIDTH*4+BRAM_ADDR_WIDTH+63:PULSE_WIDTH*4+64];
assign magnitude = $signed(pulse) - $signed(offset);
always @(posedge aclk)
begin
if(~aresetn)
begin
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
int_cntr_sweeps_reg <= {(CNTR_WIDTH){1'b0}};
int_case_reg <= 3'd0;
pulse <= 32'd0;
offset <= 32'd0;
result <= 32'd0;
wfrm_start <= {(BRAM_ADDR_WIDTH){1'b0}};
wfrm_point <= {(BRAM_ADDR_WIDTH){1'b0}};
int_addr <= {(BRAM_ADDR_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
int_last_pulse_reg <= 1'b0;
end
else
begin
int_cntr_reg <= int_cntr_next;
int_cntr_sweeps_reg <= int_cntr_sweeps_next;
int_case_reg <= int_case_next;
pulse <= pulse_next;
offset <= offset_next;
result <= result_next;
wfrm_start <= wfrm_start_next;
wfrm_point <= wfrm_point_next;
int_addr <= int_addr_next;
int_enbl_reg <= int_enbl_next;
int_last_pulse_reg <= int_last_pulse_next;
end
end
assign int_comp_wire = wfrm_start < waveform_length;
assign int_tlast_wire = ~int_comp_wire;
assign wfrm_point_comp = wfrm_point < pulse_length;
always @*
begin
int_cntr_next = int_cntr_reg;
int_cntr_sweeps_next = int_cntr_sweeps_reg;
int_case_next = int_case_reg;
offset_next=offset;
result_next=result;
int_addr_next = int_addr;
pulse_next = pulse;
wfrm_start_next = wfrm_start;
wfrm_point_next = wfrm_point;
int_enbl_next = int_enbl_reg;
int_last_pulse_next = int_last_pulse_reg;
if(int_case_reg < 3'd5)
begin
if(wfrm_start < ( waveform_length - pulse_length) )
int_last_pulse_next = 1'b0;
else
int_last_pulse_next = 1'b1;
if(~int_enbl_reg & int_comp_wire)
int_enbl_next = 1'b1;
if(m_axis_tready & int_enbl_reg & wfrm_point_comp)
begin
wfrm_point_next = wfrm_point + 1'b1;
int_addr_next = wfrm_start + wfrm_point;
end
if(m_axis_tready & int_enbl_reg & ~wfrm_point_comp)
begin
wfrm_point_next = 32'b0;
int_addr_next = wfrm_start + wfrm_point;
end
if(s_axis_tvalid)
begin
case(int_case_reg)
// measure signal offset front
0:
begin
if(int_cntr_reg < offset_width )
begin
offset_next = $signed(offset) + $signed(s_axis_tdata);
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_case_next = int_case_reg + 3'd1;
end
end
// skip ramp up
1:
begin
if(int_cntr_reg < ramp )
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_case_next = int_case_reg + 3'd1;
end
end
// measure pulse
2:
begin
if(int_cntr_reg < width )
begin
pulse_next = $signed(pulse) + $signed(s_axis_tdata);
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_case_next = int_case_reg + 3'd1;
end
end
// skip ramp down
3:
begin
if(int_cntr_reg < ramp )
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_case_next = int_case_reg + 3'd1;
end
end
// post offset
4:
begin
if(int_cntr_reg < offset_width )
begin
offset_next = $signed(offset) + $signed(s_axis_tdata);
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_case_next = 3'd0;
result_next = magnitude; // assume 50% duty cycle
offset_next = 32'd0;
pulse_next = 32'd0;
wfrm_point_next = {(BRAM_ADDR_WIDTH){1'b0}};
int_addr_next = wfrm_start + wfrm_point;
if((magnitude < threshold) & ~int_last_pulse_reg )
begin
wfrm_start_next = wfrm_start + pulse_length + 1;
end
else
begin
wfrm_start_next = {(BRAM_ADDR_WIDTH){1'b0}};
if(int_cntr_sweeps_reg < total_sweeps )
begin
int_cntr_sweeps_next = int_cntr_sweeps_reg + 1'b1;
end
else
begin
int_enbl_next = 1'b0;
wfrm_point_next = {(BRAM_ADDR_WIDTH){1'b0}};
int_case_next = 3'd5;
end
end
end
end
5:
begin
int_enbl_next = 1'b0;
wfrm_start_next = {(BRAM_ADDR_WIDTH){1'b0}};
wfrm_point_next = {(BRAM_ADDR_WIDTH){1'b0}};
end
endcase
end
end
end
assign overload = result < threshold;
assign s_axis_tready = 1'b1;
assign m_axis_tdata = bram_porta_rddata;
assign m_axis_tvalid = int_enbl_reg;
assign m_axis_tlast = int_enbl_reg & int_tlast_wire;
// assign sts_data = result ;
assign sts_data = {result[31:8],5'b0,int_case_reg};
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = m_axis_tready & int_enbl_reg ? int_addr_next : int_addr;
assign case_id = int_case_reg;
// assign bram_porta_addr = int_addr;
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { string a, b; cin >> a >> b; int x = 0, y = 0, z = 0; for (int i = 0; i < a.length(); i++) { if (a[i] != b[i]) { if (a[i] == 4 ) x++; else y++; } } cout << min(x, y) + abs(x - y); } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int n; cin >> n; vector<long long int> arr; long long int num; for (int i = 0; i < n; i++) { cin >> num; arr.push_back(num); } sort(arr.begin(), arr.end()); long long int sum = 0; for (int i = 0; i < n - 1; i++) { if (arr[i] != arr[i + 1]) { sum++; } } cout << sum + 1 << endl; } } |
#include <bits/stdc++.h> using namespace std; char s[2002000], t[2002000]; int n; int a = 0, b = 0, c = 0, d = 0; int main() { cin >> n >> s >> t; for (int i = 0; i < 2 * n; i++) { if (s[i] == 1 && t[i] == 1 ) a++; else if (s[i] == 1 ) b++; else if (t[i] == 1 ) c++; else d++; } int ans1 = 0, ans2 = 0; int m = 2 * n; while (m) { if (a) ans1 += 1, a--; else if (b) ans1 += 1, b--; else if (c) c--; else d--; if (a) ans2++, a--; else if (c) ans2++, c--; else if (b) b--; else d--; m -= 2; } if (ans1 > ans2) puts( First ); else if (ans1 < ans2) puts( Second ); else puts( Draw ); return 0; } |
#include <bits/stdc++.h> using namespace std; int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 3) + (x << 1) + (ch ^ 48); ch = getchar(); } return x * f; } int n, m, k, cnt, a[200005], Of, Os; char ch[200005]; int abs(int x, int y) { if (x > y) return x - y; else return y - x; } int main() { n = read(); m = read(); k = read(); ; for (int i = 1; i <= n; i++) { scanf( %s , (ch + 1)); int f = 0, s = 0, ff = 0, ss = 0; for (int j = 1; j <= m; j++) { if (ch[j] == G ) f = j, ff++; if (ch[j] == R ) s = j, ss++; } if (f == 0 && s != 0 && ss != m) Os = 1; if (f != 0 && s == 0 && ff != m) Of = 1; if (f && s) a[++cnt] = abs(s - f) - 1; } if (Os == 1 && Of == 1) puts( Draw ); else if (Os == 1 && Of == 0) puts( Second ); else if (Of == 1 && Os == 0) puts( First ); else { for (int i = 0; i <= 8; i++) { int ff = 0; for (int j = 1; j <= cnt; j++) ff += ((a[j] >> i) & 1); if (ff % (k + 1)) { puts( First ); return 0; } } puts( Second ); } } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tb_pixelfeed();
reg sys_clk;
initial sys_clk = 1'b0;
always #5 sys_clk = ~sys_clk;
reg sys_rst;
reg vga_rst;
wire pixel_valid;
wire fml_stb;
wire [25:0] fml_adr;
initial begin
sys_rst = 1'b1;
vga_rst = 1'b1;
#20 sys_rst = 1'b0;
#20 vga_rst = 1'b0;
end
vgafb_pixelfeed dut(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.vga_rst(vga_rst),
.nbursts(18'd100),
.baseaddress(26'd1024),
.baseaddress_ack(),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_ack(fml_stb),
.fml_di(64'hcafebabedeadbeef),
.pixel_valid(pixel_valid),
.pixel(),
.pixel_ack(pixel_valid)
);
always @(posedge sys_clk) $display("%x", fml_adr);
initial #600 $finish;
endmodule
|
#include <bits/stdc++.h> using namespace std; void fast() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } void in(long long int *a, long long int n) { for (long long int i = 0; i < n; i++) { cin >> a[i]; } } void out(long long int *a, long long int n) { for (long long int i = 0; i < n; i++) { cout << a[i] << ; } } long long int count(long long int n) { long long int add = 0; while (n > 0) { if (n % 10 == 9) add = add + 1; else break; n = n / 10; } return add; } int main() { fast(); long long int tc = 1; while (tc--) { long long int n, m; cin >> n >> m; n = n * (n + 1) / 2; long long int t = m % n; for (long long int i = 1; i <= m; i++) { if (t < i) break; t = t - i; } cout << t << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; using namespace std::chrono; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; if (n % 2 == 0) { cout << NO << endl; return 0; } cout << YES << endl; int arr[2 * n + 5]; for (int i = 1, j = 2 * n; i <= n; i++) { if (i % 2 == 1) { arr[i] = j; j--; arr[i + n] = j; j--; } else { arr[i + n] = j; j--; arr[i] = j; j--; } } for (int i = 1; i <= 2 * n; i++) { cout << arr[i] << ; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long n; cin >> n; string s; while (1) { if (n % 7 == 0) { n = n / 7; for (long long i = 0; i < n; i++) s.push_back( 7 ); break; } else { if (n > 0) { s.push_back( 4 ); n -= 4; } else { cout << -1; return 0; } } } if (s.empty()) cout << -1; else cout << s; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_pixelq_op_img_data_stream_0_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_pixelq_op_img_data_stream_0_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_pixelq_op_img_data_stream_0_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_pixelq_op_img_data_stream_0_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD(1000000007); const int INF((1 << 30) - 1); const int MAXN(30); string a[MAXN]; int type[200] = {0}; int main() { int n, m, x; scanf( %d%d%d , &n, &m, &x); for (int i = 0; i < n; i++) cin >> a[i]; for (int i = A ; i <= Z ; i++) type[i] = INF; for (int i = a ; i <= z ; i++) type[i] = INF; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { if (a[i][j] != S ) type[a[i][j]] = 1; else { for (int k = 0; k < n; k++) for (int l = 0; l < m; l++) if (a[k][l] != S ) type[a[k][l] - a + A ] = min(type[a[k][l] - a + A ], (i - k) * (i - k) + (j - l) * (j - l)); } } int q; scanf( %d , &q); int ans = 0; while (q--) { char c; scanf( %c , &c); if (type[c] == INF) { printf( -1 ); return 0; } else if (c >= A && c <= Z && type[c] > x * x) ans++; } printf( %d , ans); } |
#include <bits/stdc++.h> using namespace std; template <typename T> void gmin(T &a, T b) { a = a < b ? a : b; } template <typename T> void gmax(T &a, T b) { a = a > b ? a : b; } const int MAXV = 410; const int MAXE = 1650; const int INF = 0x3f3f3f3f; struct Edge { int to, cap, nxt, cost; Edge() {} Edge(int to, int cap, int nxt, int cost) : to(to), cap(cap), nxt(nxt), cost(cost) {} } edge[MAXE << 1]; int head[MAXV], cnt; void initedge() { memset(head, -1, sizeof(head)); cnt = 0; } inline void addedge(int from, int to, int cap, int cost) { edge[cnt] = Edge(to, cap, head[from], cost); head[from] = cnt++; } inline void addedge2(int from, int to, int cap, int cost) { addedge(from, to, cap, cost); addedge(to, from, 0, -cost); } int dist[MAXV]; int iter[MAXV]; bool inq[MAXV]; bool SPFA(int S, int T) { static int q[MAXV]; int f = 0, r = 0; memset(dist, INF, sizeof(dist)); memset(inq, 0, sizeof(inq)); dist[S] = 0; q[r++] = S; inq[S] = true; while (f != r) { int x = q[f++]; inq[x] = false; if (f == MAXV) f = 0; for (int p = head[x]; ~p; p = edge[p].nxt) { Edge e = edge[p]; if (e.cap && dist[e.to] > dist[x] + e.cost) { dist[e.to] = dist[x] + e.cost; if (!inq[e.to]) { q[r++] = e.to; inq[e.to] = true; if (r == MAXV) r = 0; } } } } return dist[T] < INF; } int getflow(int x, int lim, int T) { if (x == T) return lim; inq[x] = true; int nowflow = 0, newflow; for (register int &p = iter[x]; ~p; p = edge[p].nxt) { register Edge &e = edge[p]; if (!inq[e.to] && e.cap && dist[e.to] == dist[x] + e.cost) { newflow = getflow(e.to, min(e.cap, lim - nowflow), T); e.cap -= newflow; edge[p ^ 1].cap += newflow; nowflow += newflow; if (nowflow >= lim) break; } } return nowflow; } int mincostmaxflow(int S, int T) { int nowcost = 0, newflow; while (SPFA(S, T)) { for (int i = 0; i < MAXV; i++) iter[i] = head[i]; memset(inq, 0, sizeof(inq)); do { newflow = getflow(S, INF, T); nowcost += newflow * dist[T]; } while (newflow); } return nowcost; } const int MAXN = 210; const int MAXM = 210; int S, T, second, TT; int n1, n2, m, r, b; int id[MAXM]; int delta[MAXV]; char s[MAXN]; int ans; int main() { initedge(); scanf( %d%d%d%d%d , &n1, &n2, &m, &r, &b); S = 0; T = n1 + n2 + 1; scanf( %s , s); for (int i = 1; i <= n1; i++) { char c = s[i - 1]; if (c == R ) { addedge2(i, T, INF - 1, 0); delta[i] -= 1; delta[T] += 1; } if (c == B ) { addedge2(S, i, INF - 1, 0); delta[S] -= 1; delta[i] += 1; } if (c == U ) { addedge2(S, i, INF - 0, 0); addedge2(i, T, INF - 0, 0); } } scanf( %s , s); for (int i = 1; i <= n2; i++) { char c = s[i - 1]; if (c == B ) { addedge2(n1 + i, T, INF - 1, 0); delta[n1 + i] -= 1; delta[T] += 1; } if (c == R ) { addedge2(S, n1 + i, INF - 1, 0); delta[S] -= 1; delta[n1 + i] += 1; } if (c == U ) { addedge2(S, n1 + i, INF - 0, 0); addedge2(n1 + i, T, INF - 0, 0); } } for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); id[i] = cnt; addedge2(x, n1 + y, 1 - 0, b); addedge2(n1 + y, x, 1 - 0, r); } addedge2(T, S, INF - 0, 0); second = n1 + n2 + 2; TT = n1 + n2 + 3; int sum = 0; for (int i = S; i <= T; i++) { if (delta[i] > 0) addedge2(second, i, delta[i], 0), sum += delta[i]; if (delta[i] < 0) addedge2(i, TT, -delta[i], 0); } ans = mincostmaxflow(second, TT); sum = 0; for (int p = head[second]; ~p; p = edge[p].nxt) sum += edge[p].cap; if (!sum) { printf( %d n , ans); for (int i = 0; i < m; i++) { if (edge[id[i]].cap == 0) putchar( B ); else if (edge[id[i] + 2].cap == 0) putchar( R ); else putchar( U ); } putchar( n ); } else printf( -1 n ); return 0; } |
#include <bits/stdc++.h> using namespace std; std::vector<long long> a; long long sm = 0; long long n, m; bool doo(long long x) { long long res = 0; for (long long i = 0; i < x; ++i) { res += a[i]; long long k = i + x; long long count = 1; while (k < n and a[k] - count > 0) { res += max(0ll, a[k] - count); k += x; count++; } } return res >= m; } signed main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); cin >> n >> m; (a).clear(), (a).resize(n); for (long long i = 0; i < n; ++i) { cin >> a[i]; sm += a[i]; } sort((a).rbegin(), (a).rend()); if (sm < m) { cout << -1 ; exit(0); } long long l = 1, h = n + 1; long long mid; long long ans = -1; while (l <= h) { mid = (l + h) / 2; if (doo(mid)) { ans = mid; h = mid - 1; } else l = mid + 1; } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, mn = 200, c = 0, x, y, i; int main() { cin >> n; for (i = 0; i < n; i++) { cin >> x >> y; mn = min(mn, y); c += x * mn; } cout << c; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2,tune=native ) using namespace std; template <typename T1, typename T2> void ckmin(T1 &a, T2 b) { if (a > b) a = b; } template <typename T1, typename T2> void ckmax(T1 &a, T2 b) { if (a < b) a = b; } int read() { int x = 0, f = 0; char ch = getchar(); while (!isdigit(ch)) f |= ch == - , ch = getchar(); while (isdigit(ch)) x = 10 * x + ch - 0 , ch = getchar(); return f ? -x : x; } template <typename T> void print(T x) { if (x < 0) putchar( - ), x = -x; if (x >= 10) print(x / 10); putchar(x % 10 + 0 ); } template <typename T> void print(T x, char let) { print(x), putchar(let); } const int mod = 998244353; const int G = 3, Gi = 332748118; void uad(int &x, int y) { x += y; if (x >= mod) x -= mod; } int add(int x, int y) { if ((x += y) >= mod) x -= mod; return x; } int sub(int x, int y) { if ((x -= y) < 0) x += mod; return x; } int qpow(int a, int b = mod - 2) { int res = 1; while (b > 0) { if (b & 1) res = 1ll * res * a % mod; a = 1ll * a * a % mod; b >>= 1; } return res; } namespace Module { using namespace std; const int N = 1 << 19, P = 998244353; int Pow(long long x, int y = P - 2) { int ans = 1; for (; y; y >>= 1, x = x * x % P) if (y & 1) ans = ans * x % P; return ans; } int w[N]; unsigned long long F[N]; struct init { init() { for (int i = 1; i < N; i <<= 1) { w[i] = 1; int t = Pow(3, (P - 1) / i / 2); for (int j = 1; j < i; ++j) w[i + j] = (long long)w[i + j - 1] * t % P; } } } foo; int Get(int x) { int n = 1; while (n <= x) n <<= 1; return n; } void DFT(vector<int> &f, int n) { if ((int)f.size() != n) f.resize(n); for (int i = 0, j = 0; i < n; ++i) { F[i] = f[j]; for (int k = n >> 1; (j ^= k) < k; k >>= 1) ; } for (int i = 1; i < n; i <<= 1) for (int j = 0; j < n; j += i << 1) { int *W = w + i; unsigned long long *F0 = F + j, *F1 = F + j + i; for (int k = j; k < j + i; ++k, ++W, ++F0, ++F1) { unsigned long long t = (*F1) * *W % P; (*F1) = *F0 + P - t, (*F0) += t; } } for (int i = 0; i < n; ++i) f[i] = F[i] % P; } void IDFT(vector<int> &f, int n) { f.resize(n), reverse(f.begin() + 1, f.end()), DFT(f, n); int I = 1; for (int i = 1; i < n; i <<= 1) I = (long long)I * (P + 1) / 2 % P; for (int i = 0; i < n; ++i) f[i] = (long long)f[i] * I % P; } vector<int> operator+(const vector<int> &f, const vector<int> &g) { vector<int> ans = f; ans.resize(max(f.size(), g.size())); for (int i = 0; i < (int)g.size(); ++i) (ans[i] += g[i]) %= P; return ans; } vector<int> operator*(const vector<int> &f, const vector<int> &g) { vector<int> F, G; F = f, G = g; int p = Get(f.size() + g.size() - 2); DFT(F, p), DFT(G, p); for (int i = 0; i < p; ++i) F[i] = (long long)F[i] * G[i] % P; IDFT(F, p); return F.resize(f.size() + g.size() - 1), F; } vector<int> Inv(const vector<int> &f, int n = -1) { if (n == -1) n = f.size(); if (n == 1) return {Pow(f[0])}; vector<int> ans = Inv(f, (n + 1) / 2), tmp(f.begin(), f.begin() + n); int p = Get(n * 2 - 2); DFT(tmp, p), DFT(ans, p); for (int i = 0; i < p; ++i) ans[i] = (2 - (long long)ans[i] * tmp[i] % P + P) * ans[i] % P; IDFT(ans, p); return ans.resize(n), ans; } vector<int> Mod(const vector<int> &a, const vector<int> &b) { if (b.size() > a.size()) return a; vector<int> A = a, B = b, iB; int n = a.size(), m = b.size(); reverse(A.begin(), A.end()), reverse(B.begin(), B.end()); B.resize(n - m + 1), iB = Inv(B, n - m + 1); vector<int> d = A * iB; d.resize(n - m + 1), reverse(d.begin(), d.end()); vector<int> r = b * d; r.resize(m - 1); for (int i = 0; i < m - 1; ++i) r[i] = (a[i] - r[i] + P) % P; return r; } vector<int> Prod(const vector<int> &a, const vector<int> &b) { return a * b; } void wf(vector<int> &a) { int n = a.size(); for (int i = 0; i < n; i++) a[i] = 1ll * (i + 1) * a[i + 1] % mod; a[n - 1] = 0; } void jf(vector<int> &a) { int n = a.size(); for (int i = n - 1; i >= 1; i--) a[i] = 1ll * a[i - 1] * qpow(i) % mod; a[0] = 0; } vector<int> Ln(vector<int> a) { vector<int> ta = a; wf(ta); int len = a.size(); a = ta * Inv(a), jf(a); a.resize(len); return a; } vector<int> Exp(vector<int> a) { if ((int(a.size())) == 1) return vector<int>(1, 1); int len = a.size(); vector<int> ta = a; ta.resize((len + 1) / 2); vector<int> tb = Exp(ta); tb.resize(len); vector<int> Lnb = Ln(tb); assert(Lnb.size() == len); for (int i = 0; i < len; i++) Lnb[i] = (a[i] - Lnb[i] + mod) % mod; Lnb[0] = (Lnb[0] + 1) % mod; tb = tb * Lnb; tb.resize(len); return tb; } } // namespace Module using Module::operator*; const int N = 250005; const int B = 30; vector<int> adj[N]; int n; int son[N]; void dfs1(int u, int fa) { for (auto v : adj[u]) { if (v == fa) continue; son[u]++; dfs1(v, u); } } int two[N], len; vector<int> solve(int l, int r) { if (l > r) return {1}; if (l == r) return {1, mod - two[l]}; int mid = l + r >> 1; return solve(l, mid) * solve(mid + 1, r); } int fac[N], inv[N]; int fuck[N]; int main() { n = read(); inv[1] = 1; for (int i = 2; i <= n; i++) inv[i] = 1ull * (mod - mod / i) * inv[mod % i] % mod; fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = 1ull * fac[i - 1] * i % mod; for (int i = 1; i <= n - 1; i++) { int u = read(), v = read(); adj[u].push_back(v), adj[v].push_back(u); } dfs1(1, 0); vector<int> ONE(n + 1); for (int i = 1; i <= n; i++) { if (son[i] > B) { two[++len] = son[i]; } else { fuck[son[i]]++; } } for (int i = 1; i <= B; i++) { int coef = 1; for (int j = 1; j <= n; j++) { coef = 1ull * coef * i % mod; ONE[j] = sub(ONE[j], 1ull * fuck[i] * coef % mod * inv[j] % mod); } } ONE = Module::Exp(ONE); vector<int> TWO = solve(1, len); vector<int> f = ONE * TWO; int ans = 0; for (int i = 0; i <= n - 1; i++) ans = (ans + 1ll * fac[n - i] * f[i]) % mod; print(ans, n ); return 0; } |
/* lab4_part4.v - 50 Mhz Clock
*
* Copyright (c) 2014, Artem Tovbin <arty99 at gmail dot com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module lab4_part4 (CLOCK_50, HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, LEDR, KEY);
input CLOCK_50;
input [3:0] KEY;
output [15:0] LEDR;
output [0:6] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;
wire [25:0] Q;
wire [15:0] Q2;
reg Clr, Clr2;
counter_26bit C0 (1, CLOCK_50, Clr, Q);
counter_16bit DISPLAY (1, Clr, Clr2, Q2);
always @ (negedge CLOCK_50) begin
if (Q >= 50000000) begin
Clr = 1;
end else begin
Clr = 0;
end
end
always @ (negedge Clr) begin
if (Q2 >= 9) begin
Clr2 = 1;
end else begin
Clr2 = 0;
end
end
t_flipflop T0 (1, Clr, 0, LEDR[4]);
b2d_ssd H0 (Q2[3:0], HEX0);
endmodule
module b2d_ssd (X, SSD);
input [3:0] X;
output reg [0:6] SSD;
always begin
case(X)
0:SSD=7'b0000001;
1:SSD=7'b1001111;
2:SSD=7'b0010010;
3:SSD=7'b0000110;
4:SSD=7'b1001100;
5:SSD=7'b0100100;
6:SSD=7'b0100000;
7:SSD=7'b0001111;
8:SSD=7'b0000000;
9:SSD=7'b0001100;
endcase
end
endmodule
module hex_ssd (BIN, SSD);
input [15:0] BIN;
output reg [0:6] SSD;
always begin
case(BIN)
0:SSD=7'b0000001;
1:SSD=7'b1001111;
2:SSD=7'b0010010;
3:SSD=7'b0000110;
4:SSD=7'b1001100;
5:SSD=7'b0100100;
6:SSD=7'b0100000;
7:SSD=7'b0001111;
8:SSD=7'b0000000;
9:SSD=7'b0001100;
10:SSD=7'b0001000;
11:SSD=7'b1100000;
12:SSD=7'b0110001;
13:SSD=7'b1000010;
14:SSD=7'b0110000;
15:SSD=7'b0111000;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; const long long MAX = 100005; const long double PI = 3.14159265359; const long double G = 9.807; const long long INF = 1e18; const long double EPS = 1e-6; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } bool isprime(long long a) { if (a == 2) return 1; if (!(a & 1)) return 0; for (long long i = 3; i * i <= a; i += 2) if (a % i == 0) return 0; return 1; } long long mpow(long long base, long long exponent, long long modulus) { if (modulus == 1) return 0; long long result = 1; base = base % modulus; while (exponent) { if (exponent % 2 == 1) result = (result * base) % modulus; exponent = exponent >> 1; base = (base * base) % modulus; } return result; } long long minv(long long a, long long mod) { long long _gcd = gcd(a, mod); assert(_gcd == 1); return mpow(a, mod - 2, mod); } long long n; long long ans; long long a[1005]; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; } for (int i = 2; i < n; ++i) { if (a[i - 1] > a[i] and a[i] < a[i + 1]) ans++; else if (a[i - 1] < a[i] and a[i] > a[i + 1]) ans++; } cout << ans; return 0; } |
#include <bits/stdc++.h> using lint = long long; using ld = long double; template <class T> using numr = std::numeric_limits<T>; struct input_t { template <class T> operator T() { T t; std::cin >> t; return t; } } input; namespace ns { using namespace std; template <int mod> struct NumberTheoreticTransform { vector<int> rev, rts; int base, max_base, root; NumberTheoreticTransform() : base(1), rev{0, 1}, rts{0, 1} { assert(mod >= 3 && mod % 2 == 1); auto tmp = mod - 1; max_base = 0; while (tmp % 2 == 0) tmp >>= 1, max_base++; root = 2; while (mod_pow(root, (mod - 1) >> 1) == 1) ++root; assert(mod_pow(root, mod - 1) == 1); root = mod_pow(root, (mod - 1) >> max_base); } inline int mod_pow(int x, int n) { int ret = 1; while (n > 0) { if (n & 1) ret = mul(ret, x); x = mul(x, x); n >>= 1; } return ret; } inline int inverse(int x) { return mod_pow(x, mod - 2); } inline unsigned add(unsigned x, unsigned y) { x += y; if (x >= mod) x -= mod; return x; } inline unsigned mul(unsigned a, unsigned b) { return 1ull * a * b % (unsigned long long)mod; } void ensure_base(int nbase) { if (nbase <= base) return; rev.resize(1 << nbase); rts.resize(1 << nbase); for (int i = 0; i < (1 << nbase); i++) { rev[i] = (rev[i >> 1] >> 1) + ((i & 1) << (nbase - 1)); } assert(nbase <= max_base); while (base < nbase) { int z = mod_pow(root, 1 << (max_base - 1 - base)); for (int i = 1 << (base - 1); i < (1 << base); i++) { rts[i << 1] = rts[i]; rts[(i << 1) + 1] = mul(rts[i], z); } ++base; } } void ntt(vector<int> &a) { const int n = (int)a.size(); assert((n & (n - 1)) == 0); int zeros = __builtin_ctz(n); ensure_base(zeros); int shift = base - zeros; for (int i = 0; i < n; i++) { if (i < (rev[i] >> shift)) { swap(a[i], a[rev[i] >> shift]); } } for (int k = 1; k < n; k <<= 1) { for (int i = 0; i < n; i += 2 * k) { for (int j = 0; j < k; j++) { int z = mul(a[i + j + k], rts[j + k]); a[i + j + k] = add(a[i + j], mod - z); a[i + j] = add(a[i + j], z); } } } } vector<int> multiply(vector<int> a, vector<int> b) { int need = a.size() + b.size() - 1; int nbase = 1; while ((1 << nbase) < need) nbase++; ensure_base(nbase); int sz = 1 << nbase; a.resize(sz, 0); b.resize(sz, 0); ntt(a); ntt(b); int inv_sz = inverse(sz); for (int i = 0; i < sz; i++) { a[i] = mul(a[i], mul(b[i], inv_sz)); } reverse(a.begin() + 1, a.end()); ntt(a); a.resize(need); return a; } }; } // namespace ns constexpr int mod = 998244353; lint inverse(lint x) { assert(x % mod); lint y = 1, u = mod, v = 0; while (x) { lint q = u / x; u -= q * x; std::swap(u, x); v -= q * y; std::swap(v, y); } assert(x == 0 && std::abs(u) == 1 && std::abs(y) == mod && std::abs(v) < mod); return v < 0 ? v + mod : v; } lint normalized(lint x) { if (x <= -mod || mod <= x) x %= mod; if (x < 0) x += mod; return x; } struct mint { lint value; mint() = default; mint(lint x) : value(normalized(x)) {} }; std::ostream &operator<<(std::ostream &os, mint x) { return os << x.value; } mint operator+(mint x, mint y) { lint z = x.value + y.value; if (mod <= z) z -= mod; return mint{z}; } mint operator-(mint x, mint y) { lint z = x.value - y.value; if (z < 0) z += mod; return mint{z}; } mint operator*(mint x, mint y) { return mint{x.value * y.value % mod}; } mint operator/(mint x, mint y) { return mint{x.value * inverse(y.value) % mod}; } mint &operator+=(mint &x, mint y) { return x = x + y; } mint &operator-=(mint &x, mint y) { return x = x - y; } mint &operator*=(mint &x, mint y) { return x = x * y; } mint &operator/=(mint &x, mint y) { return x = x / y; } bool operator==(mint x, mint y) { return x.value == y.value; } bool operator!=(mint x, mint y) { return x.value != y.value; } mint power(mint x, lint y) { mint z = 1; for (; y; y >>= 1) { if (y & 1) z *= x; x *= x; } return z; } int main() { std::cin.tie(nullptr); std::ios_base::sync_with_stdio(false); std::cout.setf(std::ios_base::fixed); std::cout.precision(15); lint n = (lint)input / 2, k = input; std::vector<int> a(10); while (k--) { int x = input; a.at(x) = 1; } while (!a.back()) a.pop_back(); ns::NumberTheoreticTransform<mod> ntt; std::vector<int> b = {1}; for (; n; n >>= 1) { if (n & 1ll) b = ntt.multiply(a, b); a = ntt.multiply(a, a); } std::vector<mint> c(b.size()); std::transform(std::begin(b), std::end(b), c.begin(), [](int x) { return x; }); std::cout << std::accumulate(std::begin(c), std::end(c), mint{0}, [](mint acc, mint x) { return acc + x * x; }) << n ; } |
#include <bits/stdc++.h> using namespace std; int c1, c2, c3, c4, n, m; const int maxn = 1050; int a[maxn], b[maxn]; int p, q, r, s; int x, y; int main() { cin >> c1 >> c2 >> c3 >> c4; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a[i]; x += min(c1 * a[i], c2); } for (int i = 0; i < m; i++) { cin >> b[i]; y += min(c1 * b[i], c2); } cout << min(min(x, c3) + min(y, c3), c4) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { char str[25]; gets(str); int let[26]; for (int i = 0; i < 26; i++) { let[i] = 0; } int len = 0; for (int i = 0; str[i]; i++) { let[str[i] - a ]++; len++; } long long c = 0; for (int i = 0; i < 26; i++) { c = c + (len + 1) - let[i]; } cout << c << endl; return 0; } |
//==================================================================================================
// Filename : antares_divider.v
// Created On : Thu Sep 3 08:41:07 2015
// Last Modified : Sat Nov 07 12:01:42 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : A multi-cycle divider unit.
// op_div and op_divu MUST BE dis-asserted after the setup
// cycle for normal operation, or the operation will be restarted.
// WARNING: no exception if divisor == 0.
//==================================================================================================
module antares_divider (
input clk,
input rst,
input op_divs,
input op_divu,
input [31:0] dividend,
input [31:0] divisor,
output [31:0] quotient,
output [31:0] remainder,
output div_stall
);
//--------------------------------------------------------------------------
// Signal Declaration: reg
//--------------------------------------------------------------------------
reg active; // 1 while running
reg neg_result; // 1 if the result must be negative
reg neg_remainder; // 1 if the remainder must be negative
reg [4:0] cycle; // number of cycles needed.
reg [31:0] result; // Store the result.
reg [31:0] denominator; // divisor
reg [31:0] residual; // current remainder
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
wire [32:0] partial_sub; // temp
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign quotient = !neg_result ? result : -result;
assign remainder = !neg_remainder ? residual : -residual;
assign div_stall = active;
assign partial_sub = {residual[30:0], result[31]} - denominator; // calculate partial result
//--------------------------------------------------------------------------
// State Machine. This needs 32 cycles to calculate the result.
// The result is loaded after 34 cycles
// The first cycle is setup.
//--------------------------------------------------------------------------
always @(posedge clk) begin
if (rst) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
active <= 1'h0;
cycle <= 5'h0;
denominator <= 32'h0;
neg_result <= 1'h0;
neg_remainder <= 1'h0;
residual <= 32'h0;
result <= 32'h0;
// End of automatics
end
else begin
if(op_divs) begin
// Signed division.
cycle <= 5'd31;
result <= (dividend[31] == 1'b0) ? dividend : -dividend;
denominator <= (divisor[31] == 1'b0) ? divisor : -divisor;
residual <= 32'b0;
neg_result <= dividend[31] ^ divisor[31];
neg_remainder <= dividend[31];
active <= 1'b1;
end
else if (op_divu) begin
// Unsigned division.
cycle <= 5'd31;
result <= dividend;
denominator <= divisor;
residual <= 32'b0;
neg_result <= 1'b0;
neg_remainder <= 1'h0;
active <= 1'b1;
end
else if (active) begin
// run a iteration
if(partial_sub[32] == 1'b0) begin
residual <= partial_sub[31:0];
result <= {result[30:0], 1'b1};
end
else begin
residual <= {residual[30:0], result[31]};
result <= {result[30:0], 1'b0};
end
if (cycle == 5'b0) begin
active <= 1'b0;
end
cycle <= cycle - 5'd1;
end
end
end
endmodule // antares_divider
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "TimeHoldOver_Qsys_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 2560,
the_altsyncram.numwords_a = 2560,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "M9K",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 09 02:07:22 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_sim_netlist.v
// Design : system_xlconstant_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *)
(* NotValidForBitStream *)
module system_xlconstant_0_0
(dout);
output [0:0]dout;
wire \<const1> ;
assign dout[0] = \<const1> ;
VCC VCC
(.P(\<const1> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int x; while (cin >> x) { map<char, int> p1; string str, strr; ; bool l = 0; int sum; cin >> str; for (int i = 0; i < str.size(); i++) { p1[str[i]]++; } for (int i = 0; i < str.size(); i++) { if (p1[str[i]] % x != 0) { l = 1; break; } } if (l == 0) { for (char i = a ; i <= z ; i++) { sum = 0; if (p1[i] > 0) { sum = p1[i] / x; } while (sum--) { strr += i; } } while (x--) { cout << strr; } } else cout << -1; cout << endl; } } |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
// generate training pattern
// pattern is f4c2, it occupies two clock cycles
`timescale 1ns / 1ps
module RCB_FRL_TrainingPattern(
input clk,
input rst,
output reg [7:0] trainingpattern
);
always @ (posedge clk) begin
if(rst) begin
trainingpattern <= 8'h00;
end else begin
if(trainingpattern == 8'hf4)
trainingpattern <= 8'hc2;
else
trainingpattern <= 8'hf4;
end
end
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg_hwbrk.v
//
// *Module Description:
// Hardware Breakpoint / Watchpoint module
//
// *Author(s):
// - Olivier Girard,
//
//----------------------------------------------------------------------------
// $Rev: 57 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2010-02-01 23:56:03 +0100 (Mo, 01 Feb 2010) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
module omsp_dbg_hwbrk (
// OUTPUTs
brk_halt, // Hardware breakpoint command
brk_pnd, // Hardware break/watch-point pending
brk_dout, // Hardware break/watch-point register data input
// INPUTs
brk_reg_rd, // Hardware break/watch-point register read select
brk_reg_wr, // Hardware break/watch-point register write select
dbg_din, // Debug register data input
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
eu_mdb_in, // Memory data bus input
eu_mdb_out, // Memory data bus output
exec_done, // Execution completed
fe_mb_en, // Frontend Memory bus enable
mclk, // Main system clock
pc, // Program counter
por // Power on reset
);
// OUTPUTs
//=========
output brk_halt; // Hardware breakpoint command
output brk_pnd; // Hardware break/watch-point pending
output [15:0] brk_dout; // Hardware break/watch-point register data input
// INPUTs
//=========
input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
input [15:0] dbg_din; // Debug register data input
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] eu_mdb_in; // Memory data bus input
input [15:0] eu_mdb_out; // Memory data bus output
input exec_done; // Execution completed
input fe_mb_en; // Frontend Memory bus enable
input mclk; // Main system clock
input [15:0] pc; // Program counter
input por; // Power on reset
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
wire range_wr_set;
wire range_rd_set;
wire addr1_wr_set;
wire addr1_rd_set;
wire addr0_wr_set;
wire addr0_rd_set;
parameter BRK_CTL = 0,
BRK_STAT = 1,
BRK_ADDR0 = 2,
BRK_ADDR1 = 3;
//=============================================================================
// 2) CONFIGURATION REGISTERS
//=============================================================================
// BRK_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE
//
// ACCESS_MODE: - 00 : Disabled
// - 01 : Detect read access
// - 10 : Detect write access
// - 11 : Detect read/write access
// NOTE: '10' & '11' modes are not supported on the instruction flow
//
// BREAK_EN: - 0 : Watchmode enable
// - 1 : Break enable
//
// INST_EN: - 0 : Checks are done on the execution unit (data flow)
// - 1 : Checks are done on the frontend (instruction flow)
//
// RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1
// - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range
//
//-----------------------------------------------------------------------------
reg [4:0] brk_ctl;
wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
always @ (posedge mclk or posedge por)
if (por) brk_ctl <= 5'h00;
else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
// BRK_STAT Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD
//-----------------------------------------------------------------------------
reg [5:0] brk_stat;
wire brk_stat_wr = brk_reg_wr[BRK_STAT];
wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE,
range_rd_set & `HWBRK_RANGE,
addr1_wr_set, addr1_rd_set,
addr0_wr_set, addr0_rd_set};
wire [5:0] brk_stat_clr = ~dbg_din[5:0];
always @ (posedge mclk or posedge por)
if (por) brk_stat <= 6'h00;
else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
else brk_stat <= (brk_stat | brk_stat_set);
wire [7:0] brk_stat_full = {2'b00, brk_stat};
wire brk_pnd = |brk_stat;
// BRK_ADDR0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr0;
wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
always @ (posedge mclk or posedge por)
if (por) brk_addr0 <= 16'h0000;
else if (brk_addr0_wr) brk_addr0 <= dbg_din;
// BRK_ADDR1/DATA0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr1;
wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
always @ (posedge mclk or posedge por)
if (por) brk_addr1 <= 16'h0000;
else if (brk_addr1_wr) brk_addr1 <= dbg_din;
//============================================================================
// 3) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] brk_ctl_rd = {8'h00, brk_ctl_full} & {16{brk_reg_rd[BRK_CTL]}};
wire [15:0] brk_stat_rd = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}};
wire [15:0] brk_addr0_rd = brk_addr0 & {16{brk_reg_rd[BRK_ADDR0]}};
wire [15:0] brk_addr1_rd = brk_addr1 & {16{brk_reg_rd[BRK_ADDR1]}};
wire [15:0] brk_dout = brk_ctl_rd |
brk_stat_rd |
brk_addr0_rd |
brk_addr1_rd;
//============================================================================
// 4) BREAKPOINT / WATCHPOINT GENERATION
//============================================================================
// Comparators
//---------------------------
// Note: here the comparison logic is instanciated several times in order
// to improve the timings, at the cost of a bit more area.
wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
reg fe_mb_en_buf;
always @ (posedge mclk or posedge por)
if (por) fe_mb_en_buf <= 1'b0;
else fe_mb_en_buf <= fe_mb_en;
wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
// Detect accesses
//---------------------------
// Detect Instruction read access
wire i_addr0_rd = equ_i_addr0 & brk_ctl[`BRK_I_EN];
wire i_addr1_rd = equ_i_addr1 & brk_ctl[`BRK_I_EN];
wire i_range_rd = equ_i_range & brk_ctl[`BRK_I_EN];
// Detect Execution-Unit write access
wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
// Detect DATA read access
// Whenever an "ADD r9. &0x200" instruction is executed, &0x200 will be read
// before being written back. In that case, the read flag should not be set.
// In general, We should here make sure no write access occures during the
// same instruction cycle before setting the read flag.
reg [2:0] d_rd_trig;
always @ (posedge mclk or posedge por)
if (por) d_rd_trig <= 3'h0;
else if (exec_done) d_rd_trig <= 3'h0;
else d_rd_trig <= {equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr,
equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr};
wire d_addr0_rd = d_rd_trig[0] & exec_done & ~d_addr0_wr;
wire d_addr1_rd = d_rd_trig[1] & exec_done & ~d_addr1_wr;
wire d_range_rd = d_rd_trig[2] & exec_done & ~d_range_wr;
// Set flags
assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd);
assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr;
assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd);
assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr1_wr;
assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd | i_range_rd);
assign range_wr_set = brk_ctl[`BRK_MODE_WR] & d_range_wr;
// Break CPU
assign brk_halt = brk_ctl[`BRK_EN] & |brk_stat_set;
endmodule // omsp_dbg_hwbrk
`include "openMSP430_undefines.v"
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: jtag_bus.v
// Project: NF2 (NF2 Control Network FPGA)
// Description: NF2/CPCI bus interface.
//
// Provides synchronization logic for CPCI register bus
// including logic to insert/remove from the FIFOs.
//
// Does not implement the register processing logic.
//
// Note: bus_rd_data and bus_rd_data are NOT registers on input
//
///////////////////////////////////////////////////////////////////////////////
module jtag_bus
#(
parameter CPCI_NF2_ADDR_WIDTH = 27,
parameter CPCI_NF2_DATA_WIDTH = 32
)
(
// --- These are sigs to/from pins going to CPCI device
input jtag_rd_wr_L,
input jtag_req,
input [CPCI_NF2_ADDR_WIDTH-1:0] jtag_addr,
input [CPCI_NF2_DATA_WIDTH-1:0] jtag_wr_data,
output wire [CPCI_NF2_DATA_WIDTH-1:0] jtag_rd_data,
//output wire control_port_read_datavalid,
output reg cpci_wr_rdy,
output /*reg xCG*/ cpci_rd_rdy,
// --- Internal signals to/from register rd/wr logic
//
output fifo_empty, // functions like a bus_req signal
input fifo_rd_en,
output wire bus_rd_wr_L,
output [CPCI_NF2_ADDR_WIDTH-1:0] bus_addr,
output [CPCI_NF2_DATA_WIDTH-1:0] bus_wr_data,
input wire [CPCI_NF2_DATA_WIDTH-1:0] bus_rd_data,
input bus_rd_vld,
// --- Misc
input reset,
input core_clk
);
// --------------------------------------------------------
// Local registers/wires
// --------------------------------------------------------
// all p2n_* signals are cpci signals registered
reg p2n_rd_wr_L;
reg p2n_req;
reg p2n_req_d1;
reg [CPCI_NF2_ADDR_WIDTH-1:0] p2n_addr;
reg [CPCI_NF2_DATA_WIDTH-1:0] p2n_wr_data;
reg p2n_wr_rdy;
reg p2n_rd_rdy;
reg cpci_wr_rdy_nxt;
reg cpci_rd_rdy_nxt;
//reg cpci_wr_rdy;
//reg cpci_rd_rdy;
wire p2n_almost_full;
wire p2n_prog_full;
wire [CPCI_NF2_DATA_WIDTH-1:0] n2p_rd_data;
wire n2p_rd_rdy;
// Read/write enables for the N2P fifo
wire n2p_rd_en;
wire n2p_wr_en;
// Full/empty signals for n2p fifo
wire n2p_fifo_empty;
wire n2p_almost_full;
wire [CPCI_NF2_DATA_WIDTH-1:0] cpci_rd_data_nxt;
reg [CPCI_NF2_DATA_WIDTH-1:0] jtag_rd_data_reg;
reg jtag_rd_datavalid_reg;
// -----------------------------------------------------------------
// - Registering of all P2N signals
// -----------------------------------------------------------------
/* We register everything coming in from the pins so that we have a
timing-consistent view of the signals.
Note: the wr_rdy and rd_rdy signals are recorded as we need to be able to
identify whether the other would have recorded the operation as a success
or failure
*/
always @(posedge core_clk) begin
p2n_rd_wr_L <= jtag_rd_wr_L;
p2n_addr <= jtag_addr;
p2n_req <= jtag_req;
p2n_wr_data <= jtag_wr_data;
p2n_wr_rdy <= cpci_wr_rdy;
p2n_rd_rdy <= cpci_rd_rdy;
end
always @(*) begin
//if (bus_rd_vld) begin
jtag_rd_data_reg = bus_rd_data;
jtag_rd_datavalid_reg = bus_rd_vld;
//end xCG
end
assign jtag_rd_data = jtag_rd_data_reg;
assign control_port_read_datavalid = jtag_rd_datavalid_reg;
assign cpci_rd_rdy = jtag_rd_datavalid_reg; //xCG
/*
-----------------------------------------------------------------
- CPCI -> NF2 requests
-----------------------------------------------------------------
*/
// All requests get funnelled into a 60-bit wide FIFO.
// 60-bits = 32 (data) + 27 (address) + 1 (rd_wr_L)
// Write in new addr/data when req and wr_rdy are high
// In the current design, the CPCI chip PCI clock period is 30ns, the register
// access interface between the CPCI chip and the NetFPGA chip has clock period 16ns,
// the NetFPGA chip internal clock period is 8ns.
// The pkt DMA TX is through the register access interface at this moment (to be
// changed to use the dedicated DMA interface later). So there are a few performance
// requirements:
// 1. When DMA TX is in progress, the register access interface will see register
// write requests back to back on two consecutive clock cycles sometimes.
// 2. The reg_grp and the DMA module must finish acking to DMA TX register write request
// in no more than 3 clock cycles (3 * 8ns = 24ns < 30ns) to prevent the p2n fifo
// from filling up and overflowing. The DMA TX queue full signal to CPCI chip
// is currently indicating whether the cpu queue is full, not whether the pci2net_fifo
// is full.
reg [1:0] p2n_state;
reg [1:0] p2n_state_nxt;
reg p2n_wr_en;
wire p2n_full;
localparam
P2N_IDLE = 2'h 0,
READING = 2'h 1,
P2N_RD_DONE = 2'h 2;
// this state machine runs in the pci-clk domain
always @* begin
// set default values
p2n_wr_en = 1'b0;
p2n_state_nxt = p2n_state;
if (reset)
p2n_state_nxt = P2N_IDLE;
else begin
case (p2n_state)
P2N_IDLE: begin
// Only process the request if the PCI2NET fifo has space for the
// request
if (p2n_req && !p2n_full) begin
p2n_wr_en = 1'b1;
if (p2n_rd_wr_L)
p2n_state_nxt = READING;
end // if
end // P2N_IDLE
READING: begin
// Wait until the result is ready to return
if (p2n_rd_rdy)
p2n_state_nxt = P2N_RD_DONE;
end //READING
P2N_RD_DONE:
// Don't return to idle until the other side deasserts the request
// signal
if ( ! p2n_req )
p2n_state_nxt = P2N_IDLE;
endcase
end
end
always @(posedge core_clk) begin
p2n_state <= p2n_state_nxt;
end
always @*
if (reset) begin
cpci_wr_rdy_nxt = 1'b0;
cpci_rd_rdy_nxt = 1'b0;
end
else begin
cpci_wr_rdy_nxt = !p2n_prog_full;
//cpci_rd_rdy_nxt = !fifo_empty; xCG, original fifo was in different direction
end
always @(posedge core_clk) begin
//cpci_rd_rdy <= cpci_rd_rdy_nxt; xCG
cpci_wr_rdy <= cpci_wr_rdy_nxt;
end
/*
-----------------------------------------------------------------
- NF2 -> CPCI responses
-----------------------------------------------------------------
*/
// Fifo to cross from the PCI clock domain to the core domain
/*
pci2net_16x60 pci2net_fifo (
.din ({p2n_rd_wr_L, p2n_addr, p2n_wr_data}),
.rd_clk (core_clk),
.rd_en (fifo_rd_en),
.rst (reset),
.wr_clk (pci_clk),
.wr_en (p2n_wr_en),
.almost_full (p2n_almost_full),
.prog_full (p2n_prog_full),
.dout ({bus_rd_wr_L, bus_addr, bus_wr_data}),
.empty (fifo_empty),
.full (p2n_full)
);
*/
pci2net_16x60 pci2net_fifo (
.aclr ( reset ),
.clock ( core_clk ),
.data ( {p2n_rd_wr_L, p2n_addr, p2n_wr_data} ),
.rdreq ( fifo_rd_en ),
.wrreq ( p2n_wr_en ),
.almost_empty ( ),
.almost_full ( p2n_prog_full ),
.empty ( fifo_empty ),
.full ( p2n_full ),
.q ( {bus_rd_wr_L, bus_addr, bus_wr_data} ),
.usedw ( )
);
// synthesis translate_on
endmodule // cpci_bus
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFBUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__BUFBUF_FUNCTIONAL_PP_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__bufbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFBUF_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5 + 6; const long long MOD = 1e9 + 7; int par[MAX]; long long sz[MAX]; long long triplets(long long x) { return x * (x - 1) * (x - 2); } bool isLucky(long long x) { while (x) { if (x % 10 != 4 and x % 10 != 7) return false; x /= 10; } return true; } int Find(int u) { if (u == par[u]) return u; return par[u] = Find(par[u]); } void Union(int u, int v) { u = Find(u); v = Find(v); if (sz[u] < sz[v]) swap(u, v); if (u != v) { par[v] = u; sz[u] += sz[v]; } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n; cin >> n; for (int i = 1; i <= n; i++) par[i] = i, sz[i] = 1; for (int i = 1; i <= n - 1; i++) { long long u, v, w; cin >> u >> v >> w; if (!isLucky(w)) Union(u, v); } long long ans = n * (n - 1) * (n - 2); for (int i = 1; i <= n; i++) { if (Find(i) == i) { ans -= 2 * sz[i] * (sz[i] - 1) * (n - sz[i]) + sz[i] * (sz[i] - 1) * (sz[i] - 2); } } cout << ans; } |
#include <bits/stdc++.h> using namespace std; struct ee { int d; int y; }; ee e[120]; ee r[1200]; bool ok(ee a, ee b) { return a.y > b.y; } int main() { int n; int k; while (cin >> n >> k) { memset(e, 0, sizeof(e)); memset(r, 0, sizeof(r)); for (int i = 0; i < n; i++) { cin >> e[i].y; e[i].d = i + 1; } sort(e, e + n, ok); int m = 0, m2 = 0; int ss; for (int i = 0; i < k; i++) { ss = e[0].y - e[n - 1].y; if (ss <= 1) { break; } e[0].y--; e[n - 1].y++; r[i].d = e[0].d; r[i].y = e[n - 1].d; sort(e, e + n, ok); m++; if (ss > e[0].y - e[n - 1].y) { m2 = m; ss = e[0].y - e[n - 1].y; } } cout << ss << << m2 << endl; for (int i = 0; i < m2; i++) { cout << r[i].d << << r[i].y << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 5000; int p[MAXN], size[MAXN], n, m; int find_set(int v) { return v == p[v] ? v : p[v] = find_set(p[v]); } void union_set(int x, int y) { x = find_set(x); y = find_set(y); if (x != y) { if (size[x] < size[y]) swap(x, y); p[x] = y; size[y] += size[x]; } } int main() { cin >> n >> m; for (int i = 1; i <= n; i++) size[i] = 1, p[i] = i; while (m--) { int x, y; cin >> x >> y; union_set(x, y); } int mx = 0; cin >> m; while (m--) { int x, y; cin >> x >> y; if (find_set(x) == find_set(y)) size[find_set(x)] = 0; } for (int i = 1; i <= n; i++) { mx = max(mx, size[find_set(i)]); } cout << mx << endl; } |
#include <bits/stdc++.h> using namespace std; const int oo = 0x3f3f3f3f; const long long ooo = 9223372036854775807ll; const int _cnt = 1000 * 1000 + 7; const int _p = 1000 * 1000 * 1000 + 7; const int N = 1001005; const double PI = acos(-1.0); const double eps = 1e-9; int o(int x) { return x % _p; } int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } int lcm(int a, int b) { return a / gcd(a, b) * b; } void file_put() { freopen( filename.in , r , stdin); freopen( filename.out , w , stdout); } long long a, b, p, x, r[N], tt = 1, q[N], x0, ans = 0, T = 1, T_rev; bool v[N]; long long Pow(long long x, long long k) { long long ans = 1; for (; k; k >>= 1, (x *= x) %= p) if (k & 1) (ans *= x) %= p; return ans; } int main() { scanf( %I64d%I64d%I64d%I64d , &a, &b, &p, &x); if (a == 1) if (x < b) return 0 * printf( 0 n ); else return 0 * printf( %I64d n , (x - b) / p + 1); v[1] = 1; while (1) { (tt *= a) %= p; if (v[tt]) break; v[tt] = 1; T++; } r[1] = tt = 1; for (int i = (1); i <= (T - 1); ++i) q[(tt *= a) %= p] = i; q[1] = 0; T_rev = Pow(T, p - 2); for (int i = (2); i <= (p - 1); ++i) r[i] = (p - p / i) * r[p % i] % p; for (int i = (1); i <= (p - 1); ++i) { if (i > 1 && !q[i]) continue; long long t = i; x0 = (r[t] * b % p * T * T_rev + q[t] * p) % (p * T); if (x < x0) continue; ans += (x - x0) / (p * T) + 1; } printf( %I64d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; char mat[100][100]; char c; vector<int> us; int main() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> mat[i]; for (int i = 0; i < n; i++) { us.clear(); for (int j = 0; j < m; j++) { if (mat[i][j] == # ) us.push_back(j); } if (us.size() > 0) { for (int j = 0; j < n; j++) { c = mat[j][us[0]]; for (int k = 1; k < (int)us.size(); k++) { if (mat[j][us[k]] != c) { cout << No ; return 0; } } } } } for (int i = 0; i < m; i++) { us.clear(); for (int j = 0; j < n; j++) { if (mat[j][i] == # ) us.push_back(j); } if (us.size() > 0) { for (int j = 0; j < m; j++) { c = mat[us[0]][j]; for (int k = 1; k < (int)us.size(); k++) { if (mat[us[k]][j] != c) { cout << No ; return 0; } } } } } cout << Yes ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long i, t, n, m, c, d, a[100005]; cin >> n >> m; if (n == 1 && m == 0) { cout << 10000000; return 0; } if (m < n / 2 || n < 2) { cout << -1; return 0; } c = 1000000000LL; for (int i = n - 1; i > 1; i--) { a[i] = c--; } int tem; if (n % 2) m = m - (n - 3) / 2; else m = m - (n - 2) / 2; a[1] = m; a[0] = m * 2; for (__typeof(0) i = 0; i <= n - 1; i++) cout << a[i] << ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__AND2B_FUNCTIONAL_PP_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2B_FUNCTIONAL_PP_V |
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; bool debug = false; int n, m, k; int dx[4] = {0, 1, 0, -1}, dy[4] = {1, 0, -1, 0}; map<string, int> lesha; vector<int> v; int nxt[500035][16], sz, w[1 << 15][16]; const int maxk = 110; int dp[1 << 15][maxk]; void ii() { for (int s = 0; s < (1 << n); s++) { for (int j = 1; j <= n; j++) { int x = (1 << n) - 1 - ((1 << j) - 1); w[s][j] = __builtin_popcount(x & s); } } } void init() { sz = (int)v.size(); for (int(i) = 0; (i) < (int)(sz + 1); (i)++) for (int(j) = 0; (j) < (int)(n + 1); (j)++) nxt[i][j] = 1 << 30; for (int i = sz - 1; i >= 0; i--) { for (int j = 1; j <= n; j++) nxt[i][j] = nxt[i + 1][j]; nxt[i][v[i]] = i + 1; } } int cal() { init(); for (int(i) = 0; (i) < (int)(1 << n); (i)++) for (int(k) = 0; (k) < (int)(maxk); (k)++) dp[i][k] = 1 << 30; dp[0][0] = 0; dp[1 << (v[0] - 1)][0] = 1; for (int s = 0; s < (1 << n); s++) { for (int k = 0; k < maxk; k++) for (int x = 1; x <= n; x++) if (dp[s][k] < 1 << 30 && k + w[s][x] < maxk) { int tmp = dp[s | (1 << (x - 1))][k + w[s][x]]; dp[s | (1 << (x - 1))][k + w[s][x]] = min(tmp, nxt[dp[s][k]][x]); } } for (int k = 0; k < maxk; k++) if (dp[(1 << n) - 1][k] != 1 << 30) { return k; } return 1 << 30; } int main() { scanf( %d , &n); string tmp; for (int(i) = 0; (i) < (int)(n); (i)++) { cin >> tmp; lesha[tmp] = i + 1; } scanf( %d , &m); ii(); int ans = 1 << 30; int aa = 0; for (int(i) = 0; (i) < (int)(m); (i)++) { scanf( %d , &k); v.clear(); for (int(j) = 0; (j) < (int)(k); (j)++) { cin >> tmp; if (lesha.find(tmp) != lesha.end()) { v.push_back(lesha[tmp]); } } if (v.empty()) continue; int tt = cal(); if (tt < ans) { ans = tt; aa = i + 1; } } if (!aa) puts( Brand new problem! ); else { int count = (n - 1) * n / 2 - ans + 1; printf( %d n , aa); printf( [: ); for (int(i) = 0; (i) < (int)(count); (i)++) printf( | ); puts( :] ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int t, n, m, i, j, k, sum; long long int a[100001]; cin >> n >> k; bool yo = false; for (i = 1; i <= k; i++) cin >> a[i]; sum = LONG_LONG_MAX; for (i = 1; i <= k; i++) { if (n % a[i] < sum) { sum = n % a[i]; j = i; m = n / a[i]; } } cout << j << << m; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 9; long long Pow(long long a, long long x) { long long res = 1; while (x) { if (x & 1) res = res * a % mod; a = a * a % mod; x >>= 1; } return res; } long long inv(long long a) { return Pow(a, mod - 2); } long long n, a, b, k; string s; int main() { std::ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> a >> b >> k; cin >> s; long long ans = 0; for (int i = 0; i < k; ++i) { int f = s[i] == - ? -1 : 1; ans = (ans + (f * Pow(a, n - i) * Pow(b, i) % mod + mod) % mod) % mod; } long long q = Pow(inv(a) * b % mod, k); if (q == 1) { long long res = (n + 1) / k; ans = ans * res % mod; } else { long long res = Pow(q, (n + 1) / k); res--; if (res < 0) res += mod; res = res * inv(q - 1) % mod; ans = res * ans % mod; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int INF = 1000000007; string s; int n, k, c, v, ans; int fat[1000100], siz[1000100]; vector<int> edge[1000100]; struct node { int l, r, xo; node(int _l = 0, int _r = 0, int _xo = 0) : l(_l), r(_r), xo(_xo) {} int get() { return min(l, r); } void operator+=(node th) { l += th.l; r += th.r; if (l > INF) l = INF; if (r > INF) r = INF; } } val[1000100]; pair<int, int> uu, vv; pair<int, int> trace(int x) { if (fat[x] < 0) return make_pair(x, 0); pair<int, int> pp = trace(fat[x]); fat[x] = pp.first; val[x].xo ^= pp.second; return make_pair(fat[x], val[x].xo); } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> n >> k >> s; s = ? + s; for (int i = 1; i <= k; i++) { fat[i] = -1; siz[i] = 1; val[i] = node(1, 0, 0); cin >> c; for (int j = 1; j <= c; j++) { cin >> v; edge[v].push_back(i); } } int ans = 0; int id; for (int i = 1; i <= n; i++) { int tp = (s[i] - 0 ) ^ 1; if (edge[i].size() == 1) { id = edge[i][0]; uu = trace(id); ans -= val[uu.first].get(); val[uu.first] += node((tp == uu.second) * INF, (tp != uu.second) * INF); ans += val[uu.first].get(); } else if (edge[i].size() == 2) { id = edge[i][0]; uu = trace(id); id = edge[i][1]; vv = trace(id); if (uu.first != vv.first) { ans -= (val[uu.first].get() + val[vv.first].get()); if (siz[uu.first] > siz[vv.first]) swap(uu, vv); if (uu.second ^ vv.second ^ tp) { swap(val[vv.first].l, val[vv.first].r); val[vv.first].xo = 1; } siz[uu.first] += siz[vv.first]; fat[vv.first] = uu.first; val[uu.first] += val[vv.first]; ans += val[uu.first].get(); } } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const int INF = int(1e9); const int MAX = 200; int num[MAX], mixt[MAX]; int n; bool substring(string &a, string &b) { for (int i = 0; i < n; i++) { bool found = true; for (int j = 0; j < 3; j++) { if (a[i + j] != b[j]) { found = false; } } if (found) { return true; } } return false; } int main() { ios_base::sync_with_stdio(false); string s; cin >> s; n = s.size(); string t = ABC ; do { if (substring(s, t)) { cout << Yes n ; return 0; } } while (next_permutation(t.begin(), t.end())); cout << No n ; return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9361_rx_pnmon (
// adc interface
adc_clk,
adc_valid,
adc_data_i,
adc_data_q,
// pn out of sync and error
adc_pn_oos,
adc_pn_err);
// adc interface
input adc_clk;
input adc_valid;
input [11:0] adc_data_i;
input [11:0] adc_data_q;
// pn out of sync and error
output adc_pn_oos;
output adc_pn_err;
// internal registers
reg [15:0] adc_data = 'd0;
reg [15:0] adc_pn_data = 'd0;
reg adc_valid_d = 'd0;
reg adc_iq_match = 'd0;
reg adc_pn_match_d = 'd0;
reg adc_pn_match_z = 'd0;
reg adc_pn_err = 'd0;
reg [ 6:0] adc_pn_oos_count = 'd0;
reg adc_pn_oos = 'd0;
// internal signals
wire [11:0] adc_data_i_s;
wire [11:0] adc_data_q_s;
wire [11:0] adc_data_q_rev_s;
wire [15:0] adc_data_s;
wire adc_iq_match_s;
wire [15:0] adc_pn_data_s;
wire adc_pn_match_d_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
// prbs function
function [15:0] pnfn;
input [15:0] din;
reg [15:0] dout;
begin
dout = {din[14:0], ~((^din[15:4]) ^ (^din[2:1]))};
pnfn = dout;
end
endfunction
// bit reversal function
function [11:0] brfn;
input [11:0] din;
reg [11:0] dout;
begin
dout[11] = din[ 0];
dout[10] = din[ 1];
dout[ 9] = din[ 2];
dout[ 8] = din[ 3];
dout[ 7] = din[ 4];
dout[ 6] = din[ 5];
dout[ 5] = din[ 6];
dout[ 4] = din[ 7];
dout[ 3] = din[ 8];
dout[ 2] = din[ 9];
dout[ 1] = din[10];
dout[ 0] = din[11];
brfn = dout;
end
endfunction
// assuming lower nibble is lost-
assign adc_data_i_s = ~adc_data_i;
assign adc_data_q_s = ~adc_data_q;
assign adc_data_q_rev_s = brfn(adc_data_q_s);
assign adc_data_s = {adc_data_i_s, adc_data_q_rev_s[3:0]};
assign adc_iq_match_s = (adc_data_i_s[7:0] == adc_data_q_rev_s[11:4]) ? 1'b1 : 1'b0;
// pn sequence checking algorithm is commonly used in most applications.
// if oos is asserted (pn is out of sync):
// next sequence is generated from the incoming data.
// if 64 sequences match consecutively, oos is cleared (de-asserted).
// if oos is de-asserted (pn is in sync)
// next sequence is generated from the current sequence.
// if 64 sequences mismatch consecutively, oos is set (asserted).
// if oos is de-asserted, any spurious mismatches sets the error register.
// ideally, processor should make sure both oos == 0x0 and err == 0x0.
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_data_s : adc_pn_data;
assign adc_pn_match_d_s = (adc_data_s == adc_pn_data) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_data_s == adc_data) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_iq_match & adc_pn_match_d & adc_pn_match_z;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// pn oos and counters (64 to clear and set).
always @(posedge adc_clk) begin
if (adc_valid == 1'b1) begin
adc_data <= adc_data_s;
adc_pn_data <= pnfn(adc_pn_data_s);
end
adc_valid_d <= adc_valid;
adc_iq_match <= adc_iq_match_s;
adc_pn_match_d <= adc_pn_match_d_s;
adc_pn_match_z <= adc_pn_match_z_s;
if (adc_valid_d == 1'b1) begin
adc_pn_err <= adc_pn_err_s;
if (adc_pn_update_s == 1'b1) begin
if (adc_pn_oos_count >= 16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= ~adc_pn_oos;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= adc_pn_oos;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= adc_pn_oos;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int main() { int M[3][3]; for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { cin >> M[i][j]; } } for (int i = 0; i < 3; i++) { int c = 0; for (int j = 0; j < 3; j++) { c = (i > 0 ? M[i - 1][j] : 0); c += (j > 0 ? M[i][j - 1] : 0); c += M[i][j]; c += (j < 2 ? M[i][j + 1] : 0); c += (i < 2 ? M[i + 1][j] : 0); if (!(c % 2)) cout << 1; else cout << 0; } cout << endl; } } |
module NEURAL_LAYER_TEST;
reg [16:1] A,B,cAA,cAB,cBA,cBB,b1,b2;
wire [16:1] o1,o2;
NEURAL_LAYER nl(A,B,cAA,cAB,cBA,cBB,b1,b2,o1,o2);
initial begin
$dumpfile("neural_layer_test.vcd");
$dumpvars(0,NEURAL_LAYER_TEST);
$monitor (
"%t: A=%04x B=%04x cAA=%04x cAB=%04x cBA=%04x cBB=%04x b1=%04x b2=%04x o1=%04x o2=%04x",
$time,A,B,cAA,cAB,cBA,cBB,b1,b2,o1,o2
);
A=16'h0100; B=16'h0100; cAA=16'h0000; cAB=16'h0000; cBA=16'h0000; cBB=16'h0000; b1=16'h0000; b2=16'h0000;
#10 A=16'h0100; B=16'h0100; cAA=16'h0100; cAB=16'h0100; cBA=16'h0000; cBB=16'h0000; b1=16'h0000; b2=16'h0000;
#10 A=16'h0100; B=16'h0100; cAA=16'h0000; cAB=16'h0000; cBA=16'h0100; cBB=16'h0100; b1=16'h0000; b2=16'h0000;
#10 A=16'h0100; B=16'h0100; cAA=16'h0100; cAB=16'h0100; cBA=16'h0100; cBB=16'h0100; b1=16'h0000; b2=16'h0000;
#10 A=16'h0100; B=16'h0100; cAA=16'hFFFF; cAB=16'hFFFF; cBA=16'h0100; cBB=16'h0100; b1=16'h0000; b2=16'h0000;
#10 A=16'h0100; B=16'h0100; cAA=16'h0000; cAB=16'h0000; cBA=16'h0000; cBB=16'h0000; b1=16'h0100; b2=16'h0100;
#10 A=16'h0100; B=16'h0100; cAA=16'h0100; cAB=16'h0100; cBA=16'h0000; cBB=16'h0000; b1=16'h0100; b2=16'h0100;
#10 A=16'h0100; B=16'h0100; cAA=16'h0000; cAB=16'h0000; cBA=16'h0100; cBB=16'h0100; b1=16'h0100; b2=16'h0100;
#10 A=16'h0100; B=16'h0100; cAA=16'h0100; cAB=16'h0100; cBA=16'h0100; cBB=16'h0100; b1=16'h0100; b2=16'h0100;
#10 A=16'h0100; B=16'h0100; cAA=16'hFFFF; cAB=16'hFFFF; cBA=16'h0100; cBB=16'h0100; b1=16'h0100; b2=16'h0100;
end
endmodule
|
module host_interface
(
//OUTPUTS
output [31:0] HRDATA,
output HREADYOUT,
output HRESP,
output [31:0] bus_wr,
output [ 1:0] crc_poly_size,
output [ 1:0] bus_size,
output [ 1:0] rev_in_type,
output rev_out_type,
output crc_init_en,
output crc_idr_en,
output crc_poly_en,
output buffer_write_en,
output reset_chain,
//INPUTS
input [31:0] HWDATA,
input [31:0] HADDR,
input [ 2:0] HSIZE,
input [ 1:0] HTRANS,
input HWRITE,
input HSElx,
input HREADY,
input HRESETn,
input HCLK,
input [31:0] crc_poly_out,
input [31:0] crc_out,
input [31:0] crc_init_out,
input [ 7:0] crc_idr_out,
input buffer_full,
input reset_pending,
input read_wait
);
//Reset Values
localparam RESET_CRC_CR = 6'h00;
//CRC Register Map
localparam CRC_DR = 3'h0;
localparam CRC_IDR = 3'h1;
localparam CRC_CR = 3'h2;
localparam CRC_INIT = 3'h4;
localparam CRC_POL = 3'h5;
//Transfer Type Encoding
localparam IDLE = 2'b00;
localparam BUSY = 2'b01;
localparam NON_SEQ = 2'b10;
localparam SEQ = 2'b11;
//HRESP Encoding
localparam OK = 1'b0;
localparam ERROR = 1'b1;
//Pipeline flops
reg [2:0] haddr_pp;
reg [2:0] hsize_pp;
reg [1:0] htrans_pp;
reg hwrite_pp;
reg hselx_pp;
//Flops
reg [4:0] crc_cr_ff;
//Internal Signals
wire [31:0] crc_cr_rd;
wire crc_dr_sel;
wire crc_init_sel;
wire crc_idr_sel;
wire crc_poly_sel;
wire crc_cr_sel;
wire ahb_enable;
wire write_en;
wire read_en;
wire crc_cr_en;
wire sample_bus;
wire buffer_read_en;
//Pipeline Registers for Address Phase of AHB Protocol
always @(posedge HCLK)
begin
if(!HRESETn)
begin
hselx_pp <= 1'b0;
end
else
if(sample_bus)
begin
haddr_pp <= HADDR[4:2];
hsize_pp <= HSIZE;
htrans_pp <= HTRANS;
hwrite_pp <= HWRITE;
hselx_pp <= HSElx;
end
end
//Enable Signals
assign ahb_enable = (htrans_pp == NON_SEQ);
assign write_en = hselx_pp && hwrite_pp && ahb_enable;
assign read_en = hselx_pp && !hwrite_pp && ahb_enable;
//Registers decoding
assign crc_dr_sel = (haddr_pp == CRC_DR );
assign crc_init_sel = (haddr_pp == CRC_INIT);
assign crc_idr_sel = (haddr_pp == CRC_IDR );
assign crc_poly_sel = (haddr_pp == CRC_POL );
assign crc_cr_sel = (haddr_pp == CRC_CR );
//Write Esnables Signals for Registers
assign buffer_write_en = crc_dr_sel && write_en;
assign crc_init_en = crc_init_sel && write_en;
assign crc_idr_en = crc_idr_sel && write_en;
assign crc_poly_en = crc_poly_sel && write_en;
assign crc_cr_en = crc_cr_sel && write_en;
//Indicates reading operation request to crc_dr register
assign buffer_read_en = crc_dr_sel && read_en;
//Bus Size is the output of HSIZE pipeline register
assign bus_size = hsize_pp;
//The Write Bus is not pipelined
assign bus_wr = HWDATA;
//HREADY Signal outputed to Master
assign HREADYOUT = !((buffer_write_en && buffer_full ) ||
(buffer_read_en && read_wait ) ||
(crc_init_en && reset_pending ) );
//Signal to control sampling of bus
assign sample_bus = HREADYOUT && HREADY;
//HRESP Signal outputed to Master
//This implementation never signalize bus error to master
assign HRESP = OK;
//CRC_CR Data Read
assign crc_cr_rd = {24'h0, crc_cr_ff[4:0], 3'h0};
//Mux to HRDATA
assign HRDATA = ({32{crc_dr_sel }} & crc_out ) |
({32{crc_init_sel}} & crc_init_out ) |
({32{crc_idr_sel }} & {24'h0, crc_idr_out}) |
({32{crc_poly_sel}} & crc_poly_out ) |
({32{crc_cr_sel }} & crc_cr_rd ) ;
//Control Register
always @(posedge HCLK)
begin
if(!HRESETn)
crc_cr_ff <= RESET_CRC_CR;
else
if(crc_cr_en)
crc_cr_ff <= {HWDATA[7], HWDATA[6:5], HWDATA[4:3]};
end
//Configuration Signals
assign reset_chain = (crc_cr_en && HWDATA[0]);
assign crc_poly_size = crc_cr_ff[1:0];
assign rev_in_type = crc_cr_ff[3:2];
assign rev_out_type = crc_cr_ff[4];
endmodule
|
#include <bits/stdc++.h> using namespace std; char x[55]; int swim(char *c = x, int res = 0, int round = 0) { int l = strlen(c); if (round == 2) { if (l == 0 || l > 7 || (c[0] == 0 && l > 1)) return -1; int ba2y; sscanf(c, %d , &ba2y); if (ba2y > 1000000) return -1; return ba2y + res; } int ma3aya = 0; int nateg = -1; for (; c[0]; c++) { ma3aya *= 10; ma3aya += c[0] - 0 ; nateg = max(nateg, swim(c + 1, ma3aya + res, round + 1)); if (ma3aya == 0 || (ma3aya * 10) + (c[1]) - 0 > 1000000) break; } return nateg; } int main() { scanf( %s , &x); printf( %d , swim()); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxN(2e5 + 10); typedef int i_N[maxN]; int N, K; namespace graph { i_N A, P, is_us, Cus, deg; pair<int, int> edge[maxN]; vector<int> adj[maxN], node[maxN]; void link(const int u, const int v) { adj[u].push_back(v); } void dfs(const int u) { for (int i = 0; i < (int)adj[u].size(); i++) { const int v(adj[u][i]); if (P[v]) continue; P[v] = u; dfs(v); Cus[u] += Cus[v]; } Cus[u] += is_us[u]; } } // namespace graph int main() { ios_base::sync_with_stdio(0); { using namespace graph; cin >> N >> K; for (int i = 0; i < K * 2; i++) cin >> A[i], is_us[A[i]] = 1; for (int i = 0; i < N - 1; i++) { int u, v; cin >> u >> v; edge[i] = pair<int, int>(u, v); link(u, v); link(v, u); } } { using namespace graph; P[1] = -1; dfs(1); } { using namespace graph; for (int i = 0; i < N - 1; i++) { const int v(P[edge[i].first] == edge[i].second ? edge[i].first : edge[i].second); const int u(P[v]); if (Cus[v] && 2 * K - Cus[v]) deg[u]++, deg[v]++; } long long ans(0); queue<int> bfs_node; for (int u = 1; u <= N; u++) if (deg[u] == 1) node[1].push_back(u); for (int i = 1; i <= 2 * K; i++) { for (int j = 0; j < (int)node[i].size(); j++) { const int u(node[i][j]); deg[u] = 0; for (int k = 0; k < (int)adj[u].size(); k++) { const int v(adj[u][k]); if (!deg[v]) continue; ans += is_us[u]; deg[v]--; is_us[v] += is_us[u]; if (deg[v] == 1) node[is_us[v]].push_back(v); } } } cout << ans; } } |
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