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(** * Extraction: Extracting ML from Coq *)
(* ################################################################# *)
(** * Basic Extraction *)
(** In its simplest form, extracting an efficient program from one
written in Coq is completely straightforward.
First we say what language we want to extract into. Options are
OCaml (the most mature), Haskell (which mostly works), and
Scheme (a bit out of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Compile the present
[.v] file and have a look at [imp1.ml] now. *)
(* ################################################################# *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ################################################################# *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and prints
out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
magic declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ################################################################# *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. Of
course, the parser we're using is not certified, since we didn't
prove anything about it! *)
(** $Date: 2016-05-26 12:03:56 -0400 (Thu, 26 May 2016) $ *)
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Tue Sep 17 19:44:45 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_processing_system7_0_0/gcd_zynq_snick_processing_system7_0_0_stub.v
// Design : gcd_zynq_snick_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-3
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
module gcd_zynq_snick_processing_system7_0_0(GPIO_I, GPIO_O, GPIO_T, M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID,
M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID, M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID,
M_AXI_GP0_RID, M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0,
FCLK_CLK1, FCLK_CLK2, FCLK_CLK3, FCLK_RESET0_N, FCLK_RESET1_N, FCLK_RESET2_N, FCLK_RESET3_N,
MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB,
DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK,
PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="GPIO_I[63:0],GPIO_O[63:0],GPIO_T[63:0],M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_CLK1,FCLK_CLK2,FCLK_CLK3,FCLK_RESET0_N,FCLK_RESET1_N,FCLK_RESET2_N,FCLK_RESET3_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_CLK1;
output FCLK_CLK2;
output FCLK_CLK3;
output FCLK_RESET0_N;
output FCLK_RESET1_N;
output FCLK_RESET2_N;
output FCLK_RESET3_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2000 + 20; int a[maxn]; int main() { int n, k; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); int ans = 0; for (int i = n - 1; i >= 0; i -= k) { ans += 2 * (a[i] - 1); } cout << ans << endl; return 0; } |
// Permuter Block
`include "globalVariable.v"
module permuterBlock (inFlit0, inFlit1, stage, position, portStatus, outFlit0, outFlit1);
input stage, position;
input [4*`PORT_STAT_SIZE-1:0] portStatus;
input [`IN_ROUTER_SIZE-1:0] inFlit0,inFlit1;
output [`IN_ROUTER_SIZE-1:0] outFlit0, outFlit1;
wire winningChannel, flit0DesiredPort, flit1DesiredPort;
wire [`IN_ROUTER_SIZE-1:0] swapFlit [1:0];
wire [`IN_ROUTER_SIZE-1:0] straightFlit [1:0];
reg swap;
wire [`PORT_STAT_SIZE-1:0] wPortStatus [3:0];
genvar i;
generate
for (i=0; i<4; i= i+1) begin : split_bus
assign wPortStatus[i] = portStatus[i*`PORT_STAT_SIZE+:`PORT_STAT_SIZE];
end
endgenerate
arbiter PNArbiter(
.GP0 (inFlit0[`GOLDEN]),
.GP1 (inFlit1[`GOLDEN]),
.inPktID0 (inFlit0[`FLIT_NUM]),
.inPktID1 (inFlit1[`FLIT_NUM]),
.valid0 (inFlit0[`VALID]),
.valid1 (inFlit1[`VALID]),
.winner (winningChannel)
);
steer steerUp(inFlit0[`PROD_VECTOR_NO_LOCAL],stage,flit0DesiredPort);
steer steerDown(inFlit1[`PROD_VECTOR_NO_LOCAL],stage,flit1DesiredPort);
always @ * begin
if (
((stage==1'b0 && position==1'b0) && (wPortStatus[3]==`INACTIVE | wPortStatus[1]==`INACTIVE))
| ((stage==1'b0 && position==1'b1) && (wPortStatus[2]==`INACTIVE | wPortStatus[0]==`INACTIVE))
| ((stage==1'b1 && position==1'b0) && (wPortStatus[3]==`INACTIVE | wPortStatus[2]==`INACTIVE))
| ((stage==1'b1 && position==1'b1) && (wPortStatus[1]==`INACTIVE | wPortStatus[0]==`INACTIVE))
)
swap <= 0;
else if ((winningChannel == 0 && flit0DesiredPort == 1) || (winningChannel == 1 && flit1DesiredPort == 0))
swap <= 1;
end
demux1to2InRouter demux0(
.dataIn (inFlit0),
.sel (swap),
.aOut (straightFlit[0]),
.bOut (swapFlit[0])
);
demux1to2InRouter demux1(
.dataIn (inFlit1),
.sel (swap),
.aOut (straightFlit[1]),
.bOut (swapFlit[1])
);
mux2to1InRouter mux0(
.aIn (straightFlit[0]),
.bIn (swapFlit[1]),
.sel (swap),
.dataOut (outFlit0)
);
mux2to1InRouter mux1(
.aIn (straightFlit[1]),
.bIn (swapFlit[0]),
.sel (swap),
.dataOut (outFlit1)
);
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module simple_gemac_rx
(input reset,
input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
output rx_clk, output [7:0] rx_data, output reg rx_valid, output rx_error, output reg rx_ack,
input [47:0] ucast_addr, input [47:0] mcast_addr,
input pass_ucast, input pass_mcast, input pass_bcast, input pass_pause, input pass_all,
output reg [15:0] pause_quanta_rcvd, output pause_rcvd,
output [31:0] debug );
localparam RX_IDLE = 0;
localparam RX_PREAMBLE = 1;
localparam RX_FRAME = 2;
localparam RX_GOODFRAME = 3;
localparam RX_DO_PAUSE = 4;
localparam RX_ERROR = 5;
localparam RX_DROP = 6;
localparam RX_PAUSE = 16;
localparam RX_PAUSE_CHK88 = RX_PAUSE + 5;
localparam RX_PAUSE_CHK08 = RX_PAUSE_CHK88 + 1;
localparam RX_PAUSE_CHK00 = RX_PAUSE_CHK08 + 1;
localparam RX_PAUSE_CHK01 = RX_PAUSE_CHK00 + 1;
localparam RX_PAUSE_STORE_MSB = RX_PAUSE_CHK01 + 1;
localparam RX_PAUSE_STORE_LSB = RX_PAUSE_STORE_MSB + 1;
localparam RX_PAUSE_WAIT_CRC = RX_PAUSE_STORE_LSB + 1;
reg [7:0] rxd_d1;
reg rx_dv_d1, rx_er_d1;
assign rx_clk = GMII_RX_CLK;
always @(posedge rx_clk)
begin
rx_dv_d1 <= GMII_RX_DV;
rx_er_d1 <= GMII_RX_ER;
rxd_d1 <= GMII_RXD;
end
reg [7:0] rx_state;
wire [7:0] rxd_del;
wire rx_dv_del, rx_er_del;
reg go_filt;
wire match_crc;
wire clear_crc = rx_state == RX_IDLE;
wire calc_crc = (rx_state == RX_FRAME) | rx_state[7:4]==4'h1;
localparam DELAY = 6;
delay_line #(.WIDTH(10)) rx_delay
(.clk(rx_clk), .delay(DELAY), .din({rx_dv_d1,rx_er_d1,rxd_d1}),.dout({rx_dv_del,rx_er_del,rxd_del}));
always @(posedge rx_clk)
if(reset)
rx_ack <= 0;
else
rx_ack <= (rx_state == RX_GOODFRAME);
wire is_ucast, is_bcast, is_mcast, is_pause, is_any_ucast;
wire keep_packet = (pass_all & is_any_ucast) | (pass_ucast & is_ucast) | (pass_mcast & is_mcast) |
(pass_bcast & is_bcast) | (pass_pause & is_pause);
assign rx_data = rxd_del;
assign rx_error = (rx_state == RX_ERROR);
always @(posedge rx_clk)
if(reset)
rx_valid <= 0;
else if(keep_packet)
rx_valid <= 1;
else if((rx_state == RX_IDLE)|(rx_state == RX_ERROR))
rx_valid <= 0;
address_filter af_ucast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
.address(ucast_addr), .match(is_ucast), .done());
address_filter af_mcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
.address(mcast_addr), .match(is_mcast), .done());
address_filter af_bcast (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
.address(48'hFFFF_FFFF_FFFF), .match(is_bcast), .done());
address_filter af_pause (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
.address(48'h0180_c200_0001), .match(is_pause), .done());
address_filter_promisc af_promisc (.clk(rx_clk), .reset(reset), .go(go_filt), .data(rxd_d1),
.match(is_any_ucast), .done());
always @(posedge rx_clk)
go_filt <= (rx_state==RX_PREAMBLE) & (rxd_d1 == 8'hD5);
reg [15:0] pkt_len_ctr;
always @(posedge rx_clk)
if(reset |(rx_state == RX_IDLE))
pkt_len_ctr <= 0;
else
pkt_len_ctr <= pkt_len_ctr + 1;
localparam MIN_PAUSE_LEN = 71; // 6
wire pkt_long_enough = (pkt_len_ctr >= MIN_PAUSE_LEN);
always @(posedge rx_clk)
if(reset)
rx_state <= RX_IDLE;
else
if(rx_er_d1) // | (~pkt_long_enough & ~rx_dv_d1) & (rx_state != RX_IDLE))
rx_state <= RX_ERROR;
else
case(rx_state)
RX_IDLE :
if(rx_dv_d1)
if(rxd_d1 == 8'h55)
rx_state <= RX_PREAMBLE;
else
rx_state <= RX_ERROR;
RX_PREAMBLE :
if(~rx_dv_d1)
rx_state <= RX_ERROR;
else if(rxd_d1 == 8'hD5)
rx_state <= RX_FRAME;
else if(rxd_d1 != 8'h55)
rx_state <= RX_ERROR;
RX_FRAME :
if(is_pause)
rx_state <= RX_PAUSE;
else if(~rx_dv_d1)
if(match_crc)
rx_state <= RX_GOODFRAME;
else
rx_state <= RX_ERROR;
RX_PAUSE_CHK88 :
if(rxd_d1 != 8'h88)
rx_state <= RX_DROP;
else
rx_state <= RX_PAUSE_CHK08;
RX_PAUSE_CHK08 :
if(rxd_d1 != 8'h08)
rx_state <= RX_DROP;
else
rx_state <= RX_PAUSE_CHK00;
RX_PAUSE_CHK00 :
if(rxd_d1 != 8'h00)
rx_state <= RX_DROP;
else
rx_state <= RX_PAUSE_CHK01;
RX_PAUSE_CHK01 :
if(rxd_d1 != 8'h01)
rx_state <= RX_DROP;
else
rx_state <= RX_PAUSE_STORE_MSB;
RX_PAUSE_WAIT_CRC :
if(pkt_long_enough)
if(match_crc)
rx_state <= RX_DO_PAUSE;
else
rx_state <= RX_DROP;
RX_DO_PAUSE :
rx_state <= RX_IDLE;
RX_GOODFRAME :
rx_state <= RX_IDLE;
RX_DROP, RX_ERROR :
if(~rx_dv_d1)
rx_state <= RX_IDLE;
default
rx_state <= rx_state + 1;
endcase // case (rx_state)
assign pause_rcvd = (rx_state == RX_DO_PAUSE);
crc crc_check(.clk(rx_clk),.reset(reset),.clear(clear_crc),
.data(rxd_d1),.calc(calc_crc),.crc_out(),.match(match_crc));
always @(posedge rx_clk)
if(reset)
pause_quanta_rcvd <= 0;
else if(rx_state == RX_PAUSE_STORE_MSB)
pause_quanta_rcvd[15:8] <= rxd_d1;
else if(rx_state == RX_PAUSE_STORE_LSB)
pause_quanta_rcvd[7:0] <= rxd_d1;
assign rx_clk = GMII_RX_CLK;
assign debug = rx_state;
endmodule // simple_gemac_rx
|
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-5; const int MOD = int(1e9) + 7, MX = int(5e4) + 1; long long memo[100][3001][2]; int n, l; pair<int, int> A[101]; long long dp(int i, int len, int f) { if (len == l) return 1; if (i == n || len > l) return 0; long long &ret = memo[i][len][f]; if (ret + 1) return ret; ret = 0; int L = A[i].first, W = A[i].second; if (f) swap(L, W); for (int j = 0; j < n; j++) { if (j != i) { if (A[j].first == W) ret += dp(j, len + A[j].first, 0); else if (A[j].second == W) ret += dp(j, len + A[j].second, 1); if (ret >= MOD) ret -= MOD; } } return ret; } long long sol() { memset(memo, -1, sizeof memo); long long res = 0; for (int i = 0; i < n; i++) { res += dp(i, A[i].first, 0) + (A[i].first - A[i].second ? dp(i, A[i].second, 1) : 0); if (res >= MOD) res -= MOD; } return res; } void solve() { scanf( %d %d , &n, &l); for (int i = 0; i < n; i++) { scanf( %d %d , &A[i].first, &A[i].second); } printf( %lld n , sol() % MOD); } int main() { solve(); } |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
module altpciexpav_stif_rx_resp
#(
parameter CG_COMMON_CLOCK_MODE = 1
)
( input Clk_i,
input AvlClk_i,
input Rstn_i,
input RxmRstn_i,
// Interface to Transaction layer
input CplReq_i,
input [4:0] CplDesc_i,
/// interface to completion buffer
output [8:0] CplRdAddr_o,
input [65:0] CplBufData_i,
// interface to tx control
output TagRelease_o,
// interface to Avalon slave
output [63:0] TxsReadData_o,
output TxsReadDataValid_o
);
//state machine encoding
localparam RXCPL_IDLE = 3'h0;
localparam RXCPL_RDPIPE = 3'h3;
localparam RXCPL_RD_VALID = 3'h5;
wire last_qword;
wire dw_swap;
reg dw_swap_reg;
reg [2:0] rxcpl_state;
reg [2:0] rxcpl_nxt_state;
wire rdpipe_st;
wire rdvalid_st;
reg [5:0] rd_addr_cntr;
reg [2:0] hol_cntr;
reg [7:0] tag_status_reg;
reg [7:0] last_cpl_reg;
reg cpl_req_reg;
wire cpl_req;
wire cpl_done;
reg cpl_done_reg;
wire [3:0] tag;
wire cpl_ack_reg;
wire cpl_req_int;
wire last_cpl;
wire rxcpl_idle_state;
wire cpl_req_rise;
wire cpl_eop;
///// NEW codes
// outstanding read status based on tag
always @(posedge AvlClk_i or negedge RxmRstn_i)
begin
if(~RxmRstn_i)
cpl_req_reg <= 1'b0;
else
cpl_req_reg <= CplReq_i;
end
assign cpl_req_rise = ~cpl_req_reg & CplReq_i;
assign tag = CplDesc_i[2:0];
assign last_cpl = CplDesc_i[4];
assign cpl_eop = CplBufData_i[65];
generate
genvar i;
for(i=0; i< 8; i=i+1)
begin: tag_status_register
always @(posedge AvlClk_i or negedge RxmRstn_i)
begin
if(~RxmRstn_i)
last_cpl_reg[i] <= 1'b0;
else if(cpl_req_rise & tag == i)
last_cpl_reg[i] <= last_cpl;
else if(cpl_done & hol_cntr == i & last_cpl_reg[i]) // release the tag
last_cpl_reg[i] <= 1'b0;
end
always @(posedge AvlClk_i or negedge RxmRstn_i)
begin
if(~RxmRstn_i)
tag_status_reg[i] <= 1'b0;
else if(cpl_req_rise & last_cpl & tag == i)
tag_status_reg[i] <= 1'b1;
else if(cpl_done & hol_cntr == i) // release the tag
tag_status_reg[i] <= 1'b0;
end
end
endgenerate
always @(posedge AvlClk_i or negedge RxmRstn_i) // state machine registers
begin
if(~RxmRstn_i)
rxcpl_state <= RXCPL_IDLE;
else
rxcpl_state <= rxcpl_nxt_state;
end
always @*
begin
case(rxcpl_state)
RXCPL_IDLE :
if(tag_status_reg[hol_cntr])
rxcpl_nxt_state <= RXCPL_RDPIPE; // read pipe state
else
rxcpl_nxt_state <= RXCPL_IDLE;
RXCPL_RDPIPE:
if(cpl_eop)
rxcpl_nxt_state <= RXCPL_IDLE;
else
rxcpl_nxt_state <= RXCPL_RD_VALID;
RXCPL_RD_VALID:
if(cpl_eop)
rxcpl_nxt_state <= RXCPL_IDLE;
else
rxcpl_nxt_state <= RXCPL_RD_VALID;
default:
rxcpl_nxt_state <= RXCPL_IDLE;
endcase
end
assign rxcpl_idle_state = ~rxcpl_state[0];
assign rdpipe_st = rxcpl_state[1];
assign rdvalid_st = rxcpl_state[2];
assign TxsReadDataValid_o = rdpipe_st | rdvalid_st;
assign TxsReadData_o[63:0] = CplBufData_i[63:0];
assign cpl_done = (rdvalid_st | rdpipe_st) & cpl_eop ;
//assign TagRelease_o = rxcpl_idle_state & (last_cpl_reg[hol_cntr]);
always @(posedge AvlClk_i or negedge RxmRstn_i)
begin
if(~RxmRstn_i)
cpl_done_reg <= 1'b0;
else
cpl_done_reg <= cpl_done;
end
assign TagRelease_o = cpl_done_reg;
// head of line counter
always @(posedge AvlClk_i or negedge RxmRstn_i)
begin
if(~RxmRstn_i)
hol_cntr <= 3'h0;
else if(cpl_done & last_cpl_reg[hol_cntr])
hol_cntr <= hol_cntr + 3'h1;
end
/// completion buffer address counter
always @(posedge AvlClk_i or negedge RxmRstn_i)
begin
if(~RxmRstn_i)
rd_addr_cntr <= 6'h0;
else if(cpl_done)
rd_addr_cntr <= 6'h0;
else if(rdpipe_st | rdvalid_st | (rxcpl_idle_state & tag_status_reg[hol_cntr]))
rd_addr_cntr <= rd_addr_cntr + 6'h1;
end
assign CplRdAddr_o = { hol_cntr, rd_addr_cntr};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k; cin >> n >> k; if (n == k || k == 0) cout << 0 << << 0; else { long long int min = 1, max; if (2 * k + k < n) max = 2 * k; else max = n - k; cout << min << << max; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int b, g, n; cin >> b >> g >> n; cout << min(g, n) - max(0LL, n - b) + 1; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUF_FUNCTIONAL_V
`define SKY130_FD_SC_LP__BUF_FUNCTIONAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__buf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUF_FUNCTIONAL_V |
`timescale 1ns/10ps
module AluSim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire [7:0] result;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`Alu_LDI,8'hAB};
inst_en = 1;
#4 inst = {`Alu_ADD,8'h01};
inst_en = 1;
#4 inst = {`Alu_SUB,8'h02};
inst_en = 1;
#4 inst = {`Alu_NOT,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Alu_AND,8'h16};
inst_en = 1;
#4 inst = {`Alu_IOR,8'h22};
inst_en = 1;
#4 inst = {`Alu_XOR,8'hF9};
inst_en = 1;
#4 inst = {`Alu_SHL,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Alu_SHR,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hAB};
inst_en = 1;
#4 inst = {`Alu_EQL,8'hAB};
inst_en = 1;
#4 inst = {`Alu_EQL,8'h0F};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hAB};
inst_en = 1;
#4 inst = {`Alu_NEQ,8'h0F};
inst_en = 1;
#4 inst = {`Alu_NEQ,8'h01};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hAA};
inst_en = 1;
#4 inst = {`Alu_LTS,8'hBB};
inst_en = 1;
#4 inst = {`Alu_LTE,8'h01};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hAA};
inst_en = 1;
#4 inst = {`Alu_LTS,8'h43};
inst_en = 1;
#4 inst = {`Alu_LTE,8'h00};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hAA};
inst_en = 1;
#4 inst = {`Alu_GTS,8'h43};
inst_en = 1;
#4 inst = {`Alu_GTE,8'h01};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hAA};
inst_en = 1;
#4 inst = {`Alu_GTS,8'hBB};
inst_en = 1;
#4 inst = {`Alu_GTE,8'hCC};
inst_en = 1;
#4 inst = {`Alu_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`Alu_LDI,8'h0A};
inst_en = 0;
#4 inst = {`Alu_ADD,8'h01};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,8'h10};
inst_en = 1;
#4 inst = {`Alu_LDI,8'hA0};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`Alu_LDI,8'hB0};
inst_en = 1;
#4 inst = {`Alu_NOP,8'bxxxxxxxx};
inst_en = 1;
end
Alu
alu (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.result(result));
endmodule // AluSim
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Sep 20 15:37:03 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[7:0],probe8[7:0],probe9[1:0],probe10[0:0],probe11[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [7:0]probe7;
input [7:0]probe8;
input [1:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
endmodule
|
#include <bits/stdc++.h> #pragma warning(disable : 4996) using namespace std; const int maxn = 100010; int n, m, k, t, t1, t2, t3, t4; struct node { int x, y; int xd, xx, yd, yx; } a[maxn]; int main() { scanf( %d , &t); while (t--) { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d%d%d%d%d%d , &a[i].x, &a[i].y, &t1, &t2, &t3, &t4); if (t1 == 1) { a[i].xx = -100000; } else if (t1 == 0) { a[i].xx = a[i].x; } if (t2 == 1) { a[i].yd = 100000; } else if (t2 == 0) { a[i].yd = a[i].y; } if (t3 == 1) { a[i].xd = 100000; } else if (t3 == 0) { a[i].xd = a[i].x; } if (t4 == 1) { a[i].yx = -100000; } else if (t4 == 0) { a[i].yx = a[i].y; } } bool flag = true; int xmaxn = a[0].xd, xmin = a[0].xx, ymaxn = a[0].yd, ymin = a[0].yx; for (int i = 1; i < n; i++) { if (xmaxn < a[i].xx || xmin > a[i].xd || ymaxn < a[i].yx || ymin > a[i].yd) { printf( 0 n ); flag = false; break; } if (xmaxn > a[i].xd) { xmaxn = a[i].xd; } if (xmin < a[i].xx) { xmin = a[i].xx; } if (ymaxn > a[i].yd) { ymaxn = a[i].yd; } if (ymin < a[i].yx) { ymin = a[i].yx; } } if (flag) { printf( 1 %d %d n , xmin, ymin); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; if (n > m) swap(m, n); long long cc = 0; for (int i = 1; i <= n; i++) { cc += (m + i) / 5 - i / 5; } cout << cc << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2_SYMBOL_V
`define SKY130_FD_SC_HS__MUX2_SYMBOL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux2 (
//# {{data|Data Signals}}
input A0,
input A1,
output X ,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int t; double pi = acos(-1.0); double d, h, v, e; int main() { scanf( %lf%lf%lf%lf , &d, &h, &v, &e); double r = d / 2; if (pi * r * r * e > v) cout << NO << endl; else { double s = (pi * r * r * h) / (v - pi * r * r * e); cout << YES << endl; printf( %.12f n , s); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int visited1[200005], visited2[200005], step1[200005], step2[200005], ar[200005]; long long int n; void fill_array(long long int ar[], long long int value, long long int size) { for (long long int i = 0; i < size; i++) ar[i] = value; } long long int dfs(long long int node, long long int step, long long int parent) { if (step == 1) { visited1[node] = 1; if (node + ar[node] > n) step1[node] = ar[node]; else { if (visited2[node + ar[node]]) { if (step2[node + ar[node]] < 0) step1[node] = -1; else if (step2[node + ar[node]] == 0) step1[node] = -1; else step1[node] = step2[node + ar[node]] + ar[node]; } else { long long int temp = dfs(node + ar[node], 2, node); if (temp < 0) step1[node] = -1; else step1[node] = temp + ar[node]; } } return step1[node]; } else { visited2[node] = 1; if (node - ar[node] < 1) step2[node] = ar[node]; else if (node - ar[node] == 1) step2[node] = -1; else { if (visited1[node - ar[node]]) { if (step1[node - ar[node]] < 0) step2[node] = -1; else if (step1[node - ar[node]] == 0) step2[node] = -1; else step2[node] = step1[node - ar[node]] + ar[node]; } else { long long int temp = dfs(node - ar[node], 1, node); if (temp < 0) step2[node] = -1; else step2[node] = temp + ar[node]; } } return step2[node]; } } int main() { cin >> n; for (long long int i = 2; i <= n; i++) cin >> ar[i]; fill_array(visited1, 0, n + 1); fill_array(visited2, 0, n + 1); fill_array(step1, 0, n + 1); fill_array(step2, 0, n + 1); for (long long int i = 2; i <= n; i++) { if (!visited1[i]) dfs(i, 1, -1); if (!visited2[i]) dfs(i, 2, -1); } for (long long int i = 2; i <= n; i++) { if (step2[i] == -1) cout << -1 n ; else cout << step2[i] + i - 1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); string s; cin >> s; int count = 0; while (s.size() != 1) { int sum = 0; for (int i = 0; i < s.size(); i++) sum += s[i] - 48; string res = ; while (sum) { int digit = sum % 10; sum /= 10; res += (char)(digit + 48); } s = res; count++; } cout << count; } |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// vacram.v: Vacancy RAM //
// //
// Author: Ameer M. S. Abdelhadi ( ; ) //
// SRAM-based Modular II-2D-BCAM ; The University of British Columbia , Sep. 2014 //
////////////////////////////////////////////////////////////////////////////////////
//
`include "utils.vh"
module vacram
#( parameter CDEP = 4 , // depth (k-entries, power of 2)
parameter PIPE = 1 ) // pipelined?
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(CDEP)+9:0] wAddr , // write address
input oldPattV , // is old (rewritten) pattern valid? / input from setram
input oldPattMultiOcc,
input newPattMultiOcc,
input [4 :0] oldIdx ,
output [4 :0] vacFLoc ); // vacancy first location
wire [`log2(CDEP)+4:0] wAddrH = wAddr[`log2(CDEP)+9:5];
wire [31:0] rVac;
wire [31:0] cVac;
wire [31:0] wVac;
mwm20k #( .WWID (32 ), // write width
.RWID (32 ), // read width
.WDEP (CDEP*1024/32), // write lines depth
.OREG (0 ), // read output reg
.INIT (1 )) // initialize to zeros
vacrami ( .clk (clk ), // clock // input
.rst (rst ), // global reset // input
.wEnb (wEnb ), // write enable // input : choose block
.wAddr(wAddrH ), // write address // input [`log2(WDEP)-1 :0]
.wData(wVac ), // write data // input [WWID-1 :0]
.rAddr(wAddrH ), // read address // input [`log2(WDEP/(RWID/WWID))-1:0]
.rData(rVac )); // read data // output [RWID-1 :0]
///////////////////////////////////////////////////////////////////////////////
// generate address of first vacancy
wire NC;
`ifdef SIM
pe_bhv #( .OHW(32) ) // behavioural priority encoder
`else
pe_vac // generated automatically by ./pe script
`endif
pe_vac_inst (
.clk(clk ), // clock for pipelined priority encoder
.rst(rst ), // registers reset for pipelined priority encoder
.oht(cVac ), // one-hot match input / in : [ CDEP -1:0]
.bin(vacFLoc), // first match index / out: [`log2(CDEP)-1:0]
.vld(NC ) // match indicator / out
);
///////////////////////////////////////////////////////////////////////////////
// oldIdx one-hot decoder
reg [31:0] oldIdxOH;
always @(*) begin
oldIdxOH = {32{1'b0}};
oldIdxOH[oldIdx] = 1'b1 ;
end
///////////////////////////////////////////////////////////////////////////////
// vacFLoc one-hot decoder
reg [31:0] vacFLocOH;
always @(*) begin
vacFLocOH = {32{1'b0}};
vacFLocOH[vacFLoc] = 1'b1 ;
end
///////////////////////////////////////////////////////////////////////////////
// masking logic
assign cVac = (~rVac) | ( oldIdxOH & {32{!oldPattMultiOcc && oldPattV}}) ; // current vacancy with old data place
assign wVac = ~( cVac & ((~vacFLocOH) | {32{ newPattMultiOcc }})); // write-back vacancy status
///////////////////////////////////////////////////////////////////////////////
endmodule
|
#include <bits/stdc++.h> using namespace std; char mat[55][55]; int n; int A[] = {-1, 0, 1, 0}; int B[] = {0, 1, 0, -1}; vector<pair<int, int> > ilha1, ilha2; void flood_fill(int i, int j, bool prima) { if (i < 0 or j < 0 or i >= n or j >= n or mat[i][j] != 0 ) return; mat[i][j] = 1 ; if (prima) ilha1.push_back({i, j}); else ilha2.push_back({i, j}); for (int k = 0; k < 4; k++) { flood_fill(i + A[k], j + B[k], prima); } } int main() { pair<int, int> p1, p2; scanf( %d , &n); scanf( %d%d%d%d , &p1.first, &p1.second, &p2.first, &p2.second); p1.first--; p1.second--; p2.first--; p2.second--; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { scanf( %c , &mat[i][j]); } } flood_fill(p1.first, p1.second, true); if (mat[p2.first][p2.second] == 1 ) { puts( 0 ); return 0; } flood_fill(p2.first, p2.second, false); int ans = INT_MAX; for (int i = 0; i < (int)ilha1.size(); i++) { for (int j = 0; j < (int)ilha2.size(); j++) { int a = abs(ilha1[i].first - ilha2[j].first); int b = abs(ilha1[i].second - ilha2[j].second); ans = min(ans, a * a + b * b); } } cout << ans << endl; return 0; } |
`timescale 1ns / 1ps
module vga640x480(
input wire clk50,
input wire pclk, //pixel clock: 25MHz
input wire clr, //asynchronous reset
output wire hsync, //horizontal sync out
output wire vsync, //vertical sync out
output wire vblank,
output reg [12:0] front_vram_addr,
inout wire [7:0] front_vram_data,
output reg front_vram_rd_low,
output reg [1:0] red, //red vga output
output reg [1:0] green, //green vga output
output reg [1:0] blue //blue vga output
);
// video structure constants
parameter hpixels = 800;// horizontal pixels per line
parameter vlines = 521; // vertical lines per frame
parameter hpulse = 96; // hsync pulse length
parameter vpulse = 2; // vsync pulse length
parameter hbp = 144; // end of horizontal back porch
parameter hfp = 784; // beginning of horizontal front porch
parameter vbp = 31; // end of vertical back porch
parameter vfp = 511; // beginning of vertical front porch
// active horizontal video is therefore: 784 - 144 = 640
// active vertical video is therefore: 511 - 31 = 480
// registers for storing the horizontal & vertical counters
reg [9:0] hc;
reg [9:0] vc;
reg [9:0] hpos;
reg [9:0] vpos;
reg [2:0] hdot;
reg [3:0] vdot;
reg [6:0] hchar;
reg [5:0] vchar;
wire font_pixel;
reg fetch_attribute;
reg [7:0] char_data;
reg [7:0] attribute_data;
// Horizontal & vertical counters --
// this is how we keep track of where we are on the screen.
// ------------------------
// Sequential "always block", which is a block that is
// only triggered on signal transitions or "edges".
// posedge = rising edge & negedge = falling edge
// Assignment statements can only be used on type "reg" and need to be of the "non-blocking" type: <=
always @(posedge pclk or posedge clr)
begin
// reset condition
if (clr == 1)
begin
hc <= 0;
vc <= 0;
end
else
begin
// keep counting until the end of the line
if (hc < hpixels - 1)
hc <= hc + 1;
else
// When we hit the end of the line, reset the horizontal
// counter and increment the vertical counter.
// If vertical counter is at the end of the frame, then
// reset that one too.
begin
hc <= 0;
if (vc < vlines - 1)
vc <= vc + 1;
else
vc <= 0;
end
end
end
assign hsync = (hc < hpulse) ? 0:1;
assign vsync = (vc < vpulse) ? 0:1;
assign vblank = (vc >= vbp && vc < vfp) ? 0:1;
pc_vga_8x16 char_rom(
.clk(clk50),
.col(hdot),
.row(vdot),
.ascii(char_data),
.pixel(font_pixel)
);
always @(posedge clk50)
begin
// inside active region
if ((vc >= vbp && vc < vfp) && (hc >= hbp && hc < hfp))
begin
front_vram_rd_low = 0;
hpos = hc - hbp;
vpos = vc - vbp;
hdot = hpos[2:0];
vdot = vpos[3:0];
hchar = hpos[9:3];
vchar = vpos[9:4];
if (fetch_attribute) begin
front_vram_addr = 80 * vchar + hchar;
attribute_data = front_vram_data;
end
else begin
front_vram_addr = 80 * vchar + hchar + 2400;
char_data = front_vram_data;
end
fetch_attribute = ~fetch_attribute;
red = font_pixel ? attribute_data[5:4] : 0;
green = font_pixel ? attribute_data[3:2] : 0;
blue = font_pixel ? attribute_data[1:0] : 0;
end
// outside active region
else
begin
fetch_attribute = 1;
front_vram_rd_low = 1;
front_vram_addr = 13'bzzzzzzzzzzzz;
red = 0;
green = 0;
blue = 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int v[100010]; int j[100010]; string ss; bool haha; int m; void jump(int n) { if (n < 0 || n >= m) { haha = true; return; } else if (j[n] == 1) { haha = false; return; } else { int p; if (ss[n] == < ) p = -1; else if (ss[n] == > ) p = 1; j[n] = 1; jump(n + p * v[n]); return; } } int main(int argc, const char* argv[]) { memset(j, 0, sizeof(j)); memset(v, 0, sizeof(v)); int n; cin >> n; m = n; cin >> ss; haha = true; for (int i = 0; i < n; i++) { cin >> v[i]; } jump(0); if (haha) { printf( FINITE n ); } else { printf( INFINITE n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, l, v1, v2, k; long double dn, dl, dv1, dv2, dk; long long times; long double x; double T; int main() { scanf( %lld%lld%lld%lld%lld , &n, &l, &v1, &v2, &k); dn = n; dl = l; dv1 = v1; dv2 = v2; dk = k; times = (n - 1) / k + 1; x = l / (v2 * times - (dv2 - dv1) / (dv2 + dv1) * dv2 * (times - 1)); T = x * (times + (dv2 - dv1) / (dv2 + dv1) * (times - 1)); printf( %lf n , T); return 0; } |
#include <bits/stdc++.h> using namespace std; bool cmp(pair<int, int> a, pair<int, int> b) { return abs(a.first) + abs(a.second) < abs(b.first) + abs(b.second); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<pair<int, int>> q1; vector<pair<int, int>> q2; vector<pair<int, int>> q3; vector<pair<int, int>> q4; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; if (x > 0 && y >= 0) { q1.push_back(make_pair(x, y)); } if (x <= 0 && y > 0) { q2.push_back(make_pair(x, y)); } if (x < 0 && y <= 0) { q3.push_back(make_pair(x, y)); } if (x >= 0 && y < 0) { q4.push_back(make_pair(x, y)); } } sort(q1.begin(), q1.end(), cmp); sort(q2.begin(), q2.end(), cmp); sort(q3.begin(), q3.end(), cmp); sort(q4.begin(), q4.end(), cmp); int ans = 0; for (int i = 0; i < q1.size(); i++) { ans += 4; if (q1[i].second != 0) { ans += 2; } } for (int i = 0; i < q2.size(); i++) { ans += 4; if (q2[i].first != 0) { ans += 2; } } for (int i = 0; i < q3.size(); i++) { ans += 4; if (q3[i].second != 0) { ans += 2; } } for (int i = 0; i < q4.size(); i++) { ans += 4; if (q4[i].first != 0) { ans += 2; } } cout << ans << endl; for (int i = 0; i < q1.size(); i++) { cout << 1 << abs(q1[i].first) << R n ; if (q1[i].second != 0) { cout << 1 << abs(q1[i].second) << U n ; } cout << 2 << endl; if (q1[i].second != 0) { cout << 1 << abs(q1[i].second) << D n ; } cout << 1 << abs(q1[i].first) << L n ; cout << 3 << endl; } for (int i = 0; i < q2.size(); i++) { cout << 1 << abs(q2[i].second) << U n ; if (q2[i].first != 0) { cout << 1 << abs(q2[i].first) << L n ; } cout << 2 << endl; if (q2[i].first != 0) { cout << 1 << abs(q2[i].first) << R n ; } cout << 1 << abs(q2[i].second) << D n ; cout << 3 << endl; } for (int i = 0; i < q3.size(); i++) { cout << 1 << abs(q3[i].first) << L n ; if (q3[i].second != 0) { cout << 1 << abs(q3[i].second) << D n ; } cout << 2 << endl; if (q3[i].second != 0) { cout << 1 << abs(q3[i].second) << U n ; } cout << 1 << abs(q3[i].first) << R n ; cout << 3 << endl; } for (int i = 0; i < q4.size(); i++) { cout << 1 << abs(q4[i].second) << D n ; if (q4[i].first != 0) { cout << 1 << abs(q4[i].first) << R n ; } cout << 2 << endl; if (q4[i].first != 0) { cout << 1 << abs(q4[i].first) << L n ; } cout << 1 << abs(q4[i].second) << U n ; cout << 3 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1000000000; const int maxn = 100010; int a[maxn]; int max(int a, int b) { return a > b ? a : b; } int min(int a, int b) { return a > b ? b : a; } int main() { int n, l, r, i, j; string s; while (cin >> n) { for (i = 0; i < n; i++) cin >> a[i]; cin >> s; l = -inf, r = inf; for (i = 4; i < n; i++) { if (s[i] == 1 ) { int maxi = -inf; for (j = i; j >= i - 4; j--) { maxi = max(maxi, a[j]); } int cnt = 0; for (j = i; j >= i - 4; j--) { if (s[j] == 0 ) cnt++; } if (cnt == 4) { l = max(l, maxi + 1); } } else if (s[i] == 0 ) { int mina = inf; for (j = i; j >= i - 4; j--) { mina = min(mina, a[j]); } int cnt = 0; for (j = i; j >= i - 4; j--) { if (s[j] == 1 ) cnt++; } if (cnt == 4) { r = min(r, mina - 1); } } } cout << l << << r << endl; } return 0; } |
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-1-2017
*/
module jt12_mod(
input s1_enters,
input s2_enters,
input s3_enters,
input s4_enters,
input [2:0] alg_I,
output reg xuse_prevprev1,
output reg xuse_internal,
output reg yuse_internal,
output reg xuse_prev2,
output reg yuse_prev1,
output reg yuse_prev2
);
parameter num_ch=6;
reg [7:0] alg_hot;
always @(*) begin
case( alg_I )
3'd0: alg_hot = 8'h1; // D0
3'd1: alg_hot = 8'h2; // D1
3'd2: alg_hot = 8'h4; // D2
3'd3: alg_hot = 8'h8; // D3
3'd4: alg_hot = 8'h10; // D4
3'd5: alg_hot = 8'h20; // D5
3'd6: alg_hot = 8'h40; // D6
3'd7: alg_hot = 8'h80; // D7
endcase
end
// prev2 cannot modulate with prevprev1 at the same time
// x = prev2, prevprev1, internal_x
// y = prev1, internal_y
generate
if( num_ch==6 ) begin
always @(*) begin
xuse_prevprev1 = s1_enters | (s3_enters&alg_hot[5]);
xuse_prev2 = (s3_enters&(|alg_hot[2:0])) | (s4_enters&alg_hot[3]);
xuse_internal = s4_enters & alg_hot[2];
yuse_internal = s4_enters & (|{alg_hot[4:3],alg_hot[1:0]});
yuse_prev1 = s1_enters | (s3_enters&alg_hot[1]) |
(s2_enters&(|{alg_hot[6:3],alg_hot[0]}) )|
(s4_enters&(|{alg_hot[5],alg_hot[2]}));
yuse_prev2 = 1'b0; // unused for 6 channels
end
end else begin
reg [2:0] xuse_s4, xuse_s3, xuse_s2, xuse_s1;
reg [2:0] yuse_s4, yuse_s3, yuse_s2, yuse_s1;
always @(*) begin // 3 ch
// S1
{ xuse_s1, yuse_s1 } = { 3'b001, 3'b100 };
// S2
casez( 1'b1 )
// S2 modulated by S1
alg_hot[6], alg_hot[5], alg_hot[4], alg_hot[3], alg_hot[0]:
{ xuse_s2, yuse_s2 } = { 3'b000, 3'b100 }; // prev1
default: { xuse_s2, yuse_s2 } = 6'd0;
endcase
// S3
casez( 1'b1 )
// S3 modulated by S1
alg_hot[5]:
{ xuse_s3, yuse_s3 } = { 3'b000, 3'b100 }; // prev1
// S3 modulated by S2
alg_hot[2], alg_hot[0]:
{ xuse_s3, yuse_s3 } = { 3'b000, 3'b010 }; // prev2
// S3 modulated by S2+S1
alg_hot[1]:
{ xuse_s3, yuse_s3 } = { 3'b010, 3'b100 }; // prev2 + prev1
default: { xuse_s3, yuse_s3 } = 6'd0;
endcase
// S4
casez( 1'b1 )
// S4 modulated by S1
alg_hot[5]:
{ xuse_s4, yuse_s4 } = { 3'b000, 3'b100 }; // prev1
// S4 modulated by S3
alg_hot[4], alg_hot[1], alg_hot[0]:
{ xuse_s4, yuse_s4 } = { 3'b100, 3'b000 }; // prevprev1
// S4 modulated by S3+S2
alg_hot[3]:
{ xuse_s4, yuse_s4 } = { 3'b100, 3'b010 }; // prevprev1+prev2
// S4 modulated by S3+S1
alg_hot[2]:
{ xuse_s4, yuse_s4 } = { 3'b100, 3'b100 }; // prevprev1+prev1
default: { xuse_s4, yuse_s4 } = 6'd0;
endcase
case( {s4_enters, s3_enters, s2_enters, s1_enters})
4'b1000: begin
{xuse_prevprev1, xuse_prev2, xuse_internal} = xuse_s4;
{yuse_prev1, yuse_prev2, yuse_internal } = yuse_s4;
end
4'b0100: begin
{xuse_prevprev1, xuse_prev2, xuse_internal} = xuse_s3;
{yuse_prev1, yuse_prev2, yuse_internal } = yuse_s3;
end
4'b0010: begin
{xuse_prevprev1, xuse_prev2, xuse_internal} = xuse_s2;
{yuse_prev1, yuse_prev2, yuse_internal } = yuse_s2;
end
4'b0001: begin
{xuse_prevprev1, xuse_prev2, xuse_internal} = xuse_s1;
{yuse_prev1, yuse_prev2, yuse_internal } = yuse_s1;
end
default: begin
{xuse_prevprev1, xuse_prev2, xuse_internal} = 3'b0;
{yuse_prev1, yuse_prev2, yuse_internal } = 3'b0;
end
endcase
end
end
endgenerate
// Control signals for simulation: should be 2'b0 or 2'b1
// wire [1:0] xusage = xuse_prevprev1+xuse_prev2+xuse_internal;
// wire [1:0] yusage = yuse_prev1+yuse_internal;
//
// always @(xusage,yusage)
// if( xusage>2'b1 || yusage>2'b1 ) begin
// $display("ERROR: x/y over use in jt12_mod");
// $finish;
// end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__OR4B_PP_BLACKBOX_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); int people_in_queue[n]; for (int i = 0; i < n; i++) { scanf( %d , &people_in_queue[i]); } int num_of_product[n][100], sum[n]; for (int i = 0; i < n; i++) { sum[i] = 0; for (int j = 0; j < people_in_queue[i]; j++) { scanf( %d , &num_of_product[i][j]); sum[i] = sum[i] + num_of_product[i][j]; } } int time[n]; for (int i = 0; i < n; i++) { time[i] = sum[i] * 5 + people_in_queue[i] * 15; } int min = time[0]; for (int i = 0; i < n; i++) { if (min > time[i]) { min = time[i]; } } printf( %d , min); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); long long int a[n + 2]; for (int i = 1; i <= n; i++) { scanf( %lld , &a[i]); } long long int mx = 1; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (i != j) { mx = max(mx, a[i] | a[j]); } for (int k = 1; k <= n; k++) { if (i != j && i != k && j != k) { mx = max(mx, a[i] | a[j] | a[k]); } } } } printf( %lld , mx); return 0; } |
#include <bits/stdc++.h> using namespace std; struct Point { double x, y; }; struct Line { double A, B, C; }; Line Build(Point A, Point B) { Line res; res.A = A.y - B.y; res.B = B.x - A.x; res.C = A.x * B.y - B.x * A.y; return res; } Line Per(Line l, Point A) { Line res; res.A = -l.B; res.B = l.A; res.C = -(res.A * A.x + res.B * A.y); return res; } Line Par(Line l, Point A) { Line res; res.A = l.A; res.B = l.B; res.C = -(l.A * A.x + l.B * A.y); return res; } Point Inter(Line a, Line b) { Point res; res.x = (a.B * b.C - b.B * a.C) / (a.A * b.B - b.A * a.B); res.y = (a.A * b.C - b.A * a.C) / (b.A * a.B - b.B * a.A); return res; } Point Middle(Point A, Point B) { Point res; res.x = (A.x + B.x) / 2.0; res.y = (A.y + B.y) / 2.0; return res; } double Dist(Point A, Point B) { double res = sqrt((A.x - B.x) * (A.x - B.x) + (A.y - B.y) * (A.y - B.y)); return res; } double Dist2(Point A, Point B) { double res = (A.x - B.x) * (A.x - B.x) + (A.y - B.y) * (A.y - B.y); return res; } Point Mir(Point A, Point B) { Point res; res.x = B.x * 2 - A.x; res.y = B.y * 2 - A.y; return res; } double Cp2(Point A, Point B) { double res = A.x * B.y - A.y * B.x; return res; } double Cp3(Point O, Point A, Point B) { double res = (A.x - O.x) * (B.y - O.y) - (B.x - O.x) * (A.y - O.y); return res; } bool Zero(double x) { return (fabs(x) < 1e-9 ? true : false); } Line Midper(Point A, Point B) { Line res = Per(Build(A, B), Middle(A, B)); return res; } bool Check(Point ans[]) { double tmp; for (int i = 0; i < 4; i++) { if (Zero(Cp3(ans[i], ans[(i + 1) % 4], ans[(i + 2) % 4]))) return false; if (i == 0) tmp = Cp3(ans[i], ans[(i + 1) % 4], ans[(i + 2) % 4]); else if (tmp * Cp3(ans[i], ans[(i + 1) % 4], ans[(i + 2) % 4]) < 0) return false; } return true; } bool Mak(Point A, Point B, Point C) { if (Cp3(A, B, C) > 1e-9) swap(B, C); Line l1 = Midper(B, A); Line l2 = Midper(B, C); Point E = Inter(l1, l2); Point F = Mir(E, B); Point ans[4]; ans[0] = Inter(Par(l2, F), l1); ans[1] = Mir(ans[0], B); ans[2] = Mir(ans[1], C); ans[3] = Mir(ans[0], A); if (Check(ans) == false) return false; puts( YES ); for (int i = 3; i < 7; i++) { printf( %.9f %.9f , ans[i & 3].x, ans[i & 3].y); putchar(i < 6 ? 32 : 10); } return true; } int main() { int t; scanf( %d , &t); while (t--) { Point a, b, c; scanf( %lf%lf%lf%lf%lf%lf , &a.x, &a.y, &b.x, &b.y, &c.x, &c.y); if (!Zero(Cp3(a, b, c)) && (Mak(a, b, c) || Mak(b, c, a) || Mak(c, a, b))) continue; puts( NO n ); } return 0; } |
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// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : mig_wrap_mig_7series_0_0.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Wrapper module for the user design top level file. This module can be
// instantiated in the system and interconnect as shown in example design
// (example_top module).
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_wrap_mig_7series_0_0 (
// Inouts
inout [15:0] ddr2_dq,
inout [1:0] ddr2_dqs_n,
inout [1:0] ddr2_dqs_p,
// Outputs
output [12:0] ddr2_addr,
output [2:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [0:0] ddr2_ck_p,
output [0:0] ddr2_ck_n,
output [0:0] ddr2_cke,
output [0:0] ddr2_cs_n,
output [1:0] ddr2_dm,
output [0:0] ddr2_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
// Single-ended iodelayctrl clk (reference clock)
input clk_ref_i,
// user interface signals
output ui_clk,
output ui_clk_sync_rst,
output mmcm_locked,
input aresetn,
output app_sr_active,
output app_ref_ack,
output app_zq_ack,
// Slave Interface Write Address Ports
input [3:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [0:0] s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input [3:0] s_axi_awqos,
input s_axi_awvalid,
output s_axi_awready,
// Slave Interface Write Data Ports
input [31:0] s_axi_wdata,
input [3:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// Slave Interface Write Response Ports
input s_axi_bready,
output [3:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
// Slave Interface Read Address Ports
input [3:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [0:0] s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input [3:0] s_axi_arqos,
input s_axi_arvalid,
output s_axi_arready,
// Slave Interface Read Data Ports
input s_axi_rready,
output [3:0] s_axi_rid,
output [31:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
output init_calib_complete,
input sys_rst
);
// Start of IP top instance
mig_wrap_mig_7series_0_0_mig u_mig_wrap_mig_7series_0_0_mig (
// Memory interface ports
.ddr2_addr (ddr2_addr),
.ddr2_ba (ddr2_ba),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_ck_n (ddr2_ck_n),
.ddr2_ck_p (ddr2_ck_p),
.ddr2_cke (ddr2_cke),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_dq (ddr2_dq),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_dqs_p (ddr2_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_dm (ddr2_dm),
.ddr2_odt (ddr2_odt),
// Application interface ports
.ui_clk (ui_clk),
.ui_clk_sync_rst (ui_clk_sync_rst),
.mmcm_locked (mmcm_locked),
.aresetn (aresetn),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (s_axi_awqos),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (s_axi_arqos),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// System Clock Ports
.sys_clk_i (sys_clk_i),
// Reference Clock Ports
.clk_ref_i (clk_ref_i),
.sys_rst (sys_rst)
);
// End of IP top instance
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[102][102][102] = {}; int main() { string s; int n, m, k; cin >> n >> m >> k; for (int i = 1; i < n + 1; ++i) { for (int j = 1; j < m + 1; ++j) { cin >> s; for (int t = 1; t < k + 1; ++t) a[i][j][t] = s[t - 1] - 0 ; } } int ans = 0; for (int i = 1; i < n + 1; ++i) for (int j = 1; j < m + 1; ++j) for (int t = 1; t < k + 1; ++t) if (a[i][j][t] && ((a[i][j][t - 1] && (a[i][j][t + 1] || (a[i][j + 1][t] && !a[i][j + 1][t - 1]) || (a[i + 1][j][t] && !a[i + 1][j][t - 1]))) || (a[i][j - 1][t] && (a[i][j + 1][t] || (a[i][j][t + 1] && !a[i][j - 1][t + 1]) || (a[i + 1][j][t] && !a[i + 1][j - 1][t]))) || (a[i - 1][j][t] && (a[i + 1][j][t] || (a[i][j][t + 1] && !a[i - 1][j][t + 1]) || (a[i][j + 1][t] && !a[i - 1][j + 1][t]))))) ++ans; cout << ans; return 0; } |
/*
Copyright (C) {2014} {Shawn Jain} <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
// From Lab 4
// Generates a square wave that flips every Hz clock cycles
module Square #(parameter Hz = 27000000) (
input clock, reset,
output reg square = 0);
wire oneHertz_enable;
ClockDivider #(.Hz(Hz)) Sqr (
.clock(clock),
.reset(reset),
.fastMode(1'b0),
.oneHertz_enable(oneHertz_enable)
);
always @ (posedge oneHertz_enable) begin
square <= ~square;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); long long s, x; cin >> s >> x; bool flag = true; bool valid = true; if ((s & 1) != (x & 1)) valid = false; long long ans = 1; for (int i = 62; i >= 1; i--) { long long sb = (s >> i) & 1; long long xb = (x >> i) & 1; long long sp = (s >> (i - 1)) & 1; long long xp = (x >> (i - 1)) & 1; if (sb == 0 && xb == 0) { if (sp == 0 && xp == 1) valid = false; } if (sb == 0 && xb == 1) { if (sp == 1 && xp == 1) valid = false; } if (sb == 1 && xb == 0) { if (sp == 1 && xp == 1) valid = false; } if (sb == 1 && xb == 1) { if (sp == 0 && xp == 1) valid = false; } if (xb != sb) flag = false; } for (int i = 0; i < 62; i++) if ((x >> i) & 1) ans *= 2; if (!valid) cout << 0 n ; else cout << ans - flag * 2 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { long long n, a, b; cin >> n >> a >> b; long long dp[4][n + 1]; string s; cin >> s; vector<long long> v(n + 1, 0); for (long long i = 1; i <= n; i++) if (s[i - 1] == 1 ) v[i] = 1; dp[0][0] = dp[1][0] = dp[2][0] = dp[3][0] = b; for (long long i = 1; i <= n; i++) { if (i == 1) { dp[0][i] = dp[0][0] + a + b; dp[1][i] = dp[0][0] + 2 * a + 2 * b; continue; } if (v[i] && v[i - 1]) dp[0][i] = dp[1][i] = dp[1][i - 1] + a + 2 * b; else if (v[i] && !v[i - 1]) { dp[0][i] = dp[1][i] = min(dp[1][i - 1], dp[0][i - 2] + 2 * a + 2 * b) + a + 2 * b; } else if (!v[i] && !v[i - 1]) { dp[0][i] = min(dp[0][i - 1], dp[1][i - 1] + a) + b + a; dp[1][i] = min(dp[1][i - 1] + a, dp[0][i - 1] + 2 * a) + 2 * b; } else if (!v[i] && v[i - 1]) { dp[0][i] = dp[1][i - 1] + 2 * a + b; dp[1][i] = dp[1][i - 1] + 2 * b + a; } } cout << dp[0][n] << endl; } return 0; } |
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* DMA INTERFACE */
/*---------------------------------------------------------------------------*/
/* Test the DMA interface: */
/* - Check Memory RD/WR features. */
/* */
/* Author(s): */
/* - Olivier Girard, */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev$ */
/* $LastChangedBy$ */
/* $LastChangedDate$ */
/*===========================================================================*/
`define VERY_LONG_TIMEOUT
parameter TMPL16B_CNTRL1 = (((`PER_SIZE-'h0070) & 'h7ff8)+'h0000);
parameter TMPL16B_CNTRL2 = (((`PER_SIZE-'h0070) & 'h7ff8)+'h0002);
parameter TMPL16B_CNTRL3 = (((`PER_SIZE-'h0070) & 'h7ff8)+'h0004);
parameter TMPL16B_CNTRL4 = (((`PER_SIZE-'h0070) & 'h7ff8)+'h0006);
integer jj;
integer inst_number_old;
integer inst_number_diff;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
`ifdef DMA_IF_EN
// Disable automatic DMA verification
#10;
dma_verif_on = 0;
repeat(30) @(posedge mclk);
stimulus_done = 0;
//-------------------------------------------------------------
// LOW/HIGH PRIORITY DMA
//-------------------------------------------------------------
for ( jj=0; jj<=1; jj=jj+1)
begin
if (jj==0)
begin
dma_priority=0;
$display("\n\n---------------------------------------");
$display(" LOW Priority 16B DMA transfer tests");
$display("---------------------------------------\n");
end
else
begin
dma_priority=1;
$display("\n\n---------------------------------------");
$display(" HIGH Priority 16B DMA transfer tests");
$display("---------------------------------------\n");
end
// RD/WR ACCESS: Program memory (16b)
//--------------------------------------------------------
$display("MARCH-X: Program memory 16b:");
// Wait random time until MARCH-X starts
dma_rand_wait = $urandom_range(1,40);
repeat(dma_rand_wait) @(posedge mclk);
// Run MARCH-X on program memory
// (make sure we don't overwrite firmware, i.e. the first 48 bytes)
inst_number_old=inst_number;
march_x_16b(('h10000-`PMEM_SIZE+48), 16'hfffe, 1);
inst_number_diff=inst_number-inst_number_old;
if ( dma_priority & (inst_number_diff>2)) tb_error("CPU is not stopped in high priority mode");
if (~dma_priority & (inst_number_diff<500)) tb_error("CPU is stopped in low priority mode");
// RD/WR ACCESS: Data memory (16b)
//--------------------------------------------------------
$display("\n\nMARCH-X: Data memory 16b:");
// Wait random time until MARCH-X starts
dma_rand_wait = $urandom_range(1,40);
repeat(dma_rand_wait) @(posedge mclk);
// Run MARCH-X on data memory
// (make sure we don't overwrite firmware data, i.e. DMEM_200)
inst_number_old=inst_number;
march_x_16b((`PER_SIZE+2), (`PER_SIZE+`DMEM_SIZE-2), 1);
inst_number_diff=inst_number-inst_number_old;
if ( dma_priority & (inst_number_diff>2)) tb_error("CPU is not stopped in high priority mode");
if (~dma_priority & (inst_number_diff<100)) tb_error("CPU is stopped in low priority mode");
// RD/WR ACCESS: Peripheral memory (16b)
//--------------------------------------------------------
$display("\n\nMARCH-X: Peripheral memory 16b ...");
// Wait random time until MARCH-X starts
dma_rand_wait = $urandom_range(1,40);
repeat(dma_rand_wait) @(posedge mclk);
// Run MARCH-X on 16B template peripheral
inst_number_old=inst_number;
repeat(100) march_x_16b(TMPL16B_CNTRL1, TMPL16B_CNTRL4, 0);
inst_number_diff=inst_number-inst_number_old;
if ( dma_priority & (inst_number_diff>2)) tb_error("CPU is not stopped in high priority mode");
if (~dma_priority & (inst_number_diff<500)) tb_error("CPU is stopped in low priority mode");
end
// End of test
//--------------------------------------------------
$display("\n");
repeat(3000) @(posedge mclk);
dma_write_16b(16'h0000-`PMEM_SIZE, 16'h0001, 1'b0);
@(r15==16'h2000);
if (r10 !== mem200) tb_error("Final Increment counter missmatch... firmware execution failed");
stimulus_done = 1;
`else
tb_skip_finish("| (DMA interface support not included) |");
`endif
end
//-------------------------------------------------------------
// Make sure firmware executes properly during the whole test
//-------------------------------------------------------------
// Make sure there is the right amount of clock cycle between the counter increments
// (low-priority mode only)
integer mclk_cnt;
always @(posedge mclk) mclk_cnt=mclk_cnt+1;
// Check counter increment
initial
begin
// Wait for firmware to start
@(r15==16'h1000);
// Synchronize with first increment
@(mem200); @(negedge mclk);
mclk_cnt=0;
forever
begin
// When register R10 is incremented, make sure DMEM_200 = R10-1
@(r10); @(negedge mclk);
if (r10 !== (mem200+1)) tb_error("R10 Increment counter missmatch... firmware execution failed");
if (~dma_priority & ((mclk_cnt < 4) | (mclk_cnt > 10))) tb_error("DMEM_200 -> R10 exec time error... firmware execution failed");
mclk_cnt=0;
// When DMEM_200 is incremented, make sure DMEM_200 = R10
@(mem200); @(negedge mclk);
if (r10 !== mem200) tb_error("DMEM_200 Increment counter missmatch... firmware execution failed");
if (~dma_priority & ((mclk_cnt < 3) | (mclk_cnt > 9))) tb_error("R10 -> DMEM_200 exec time error... firmware execution failed");
mclk_cnt=0;
end
end
//------------------------------------------------------
// MARCH-X functions
//------------------------------------------------------
task march_x_16b;
input [15:0] addr_start;
input [15:0] addr_end;
input verbose;
integer ii;
begin
// MARCH X : down (w0); up (r0,w1); down (r1,w0); up (r0)
if (verbose) $display(" - down(w0) ... ");
for ( ii=addr_end; ii >= addr_start; ii=ii-2)
begin
dma_write_16b(ii, 16'h0000, 1'b0);
end
if (verbose) $display(" - up(r0,w1) ... ");
for ( ii=addr_start; ii <= addr_end; ii=ii+2)
begin
dma_read_16b(ii, 16'h0000, 1'b0);
dma_write_16b(ii, 16'hffff, 1'b0);
end
if (verbose) $display(" - down(r1,w0) ... ");
for ( ii=addr_end; ii >= addr_start; ii=ii-2)
begin
dma_read_16b(ii, 16'hffff, 1'b0);
dma_write_16b(ii, 16'h0000, 1'b0);
end
if (verbose) $display(" - up(r0) ... ");
for ( ii=addr_start; ii <= addr_end; ii=ii+2)
begin
dma_read_16b(ii, 16'h0000, 1'b0);
end
end
endtask // march_x_16b
|
#include <bits/stdc++.h> using namespace std; int n, m, k, l[100100], c[100100]; vector<int> g[100100]; vector<int> s; void dfs(int t) { s.push_back(t); l[t] = s.size(); for (auto v : g[t]) { if (!l[v]) dfs(v); else { if (l[t] - l[v] + 1 >= k) { printf( 2 n%d n , l[t] - l[v] + 1); for (int i = l[v] - 1; i < l[t]; i++) printf( %d , s[i]); exit(0); } } } if (!c[t]) for (auto v : g[t]) c[v] = 1; s.pop_back(); } int main() { int i, a, b; scanf( %d %d , &n, &m); for (i = 0; i < m; i++) { scanf( %d %d , &a, &b); g[a].push_back(b); g[b].push_back(a); } while (k * k < n) k++; dfs(1); printf( 1 n ); for (i = 1; k; i++) { if (!c[i]) { printf( %d , i); k--; } } } |
/******************************************************************************
* File Name : counter.v
* Package Module Name : Elliptic Curve Cryptoprocessor for GF(2^233)
* Author : Chester Rebeiro
* Date of Creation : 3/Apr/2008
* Type of file : Verilog source code
* Synopsis : counts down from 233 to 0. When 0 is reached e is
* set to indicate count is done.
******************************************************************************/
`ifndef __COUNTER_V__
`define __COUNTER_V__
`define KEYSIZE 32
`define KEYMSB 31
/*---------------------------------------------------------------------------
* Module Name : counter
* Synopsis :
* The counter will start from 233 and go downto 0.
* Load counter with nrst low.
* Counter ends when e goes low for one clock cycle.
---------------------------------------------------------------------------*/
module counter (clk, nrst, e);
input wire clk; /* clock used for the counter */
input wire nrst; /* active low reset */
output wire e; /* set to 0 if count = 0 */
reg [7:0] count; /* ...and the register which actually decrements */
/* activate e when count reaches 0 */
assign e = |count;
always @(posedge clk or negedge nrst) begin
if(nrst == 1'b0)
count <= 8'd`KEYMSB;
else
count <= count - 1'b1;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BAI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O21BAI_BEHAVIORAL_PP_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , b, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BAI_BEHAVIORAL_PP_V |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_charReceived (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg d1_data_in;
reg d2_data_in;
wire data_in;
reg edge_capture;
wire edge_capture_wr_strobe;
wire edge_detect;
wire irq;
reg irq_mask;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask) |
({1 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture <= 0;
else if (edge_detect)
edge_capture <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in & ~d2_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char c = getchar(); while ((c < 0 || c > 9 ) && (c != - )) c = getchar(); if (c == - ) f = -1, c = getchar(); while (c >= 0 && c <= 9 ) x = x * 10 + c - 0 , c = getchar(); return x * f; } const int N = 3e4 + 10; int n; vector<int> e[N]; int cnt, p[N], fa[N], vis[N]; bool flag[N]; inline void dfs(int u) { vis[u] = 1; for (auto v : e[u]) { if (v == fa[u]) continue; fa[v] = u; if (!vis[v]) dfs(v); else { for (int now = u; now != v; now = fa[now]) flag[p[++cnt] = now] = 1; flag[p[++cnt] = v] = 1; } if (cnt) break; } } long long f[N], g[N], siz[N]; inline void dfs(int u, int fa) { siz[u] = 1; for (auto v : e[u]) { if (v == fa || flag[v]) continue; dfs(v, u), f[u] += g[v], siz[u] += siz[v]; } g[u] = f[u] + siz[u]; } long long dp[N], last[N], pre[N], ans; inline void dfs(int u, int fa, long long sum) { ans = max(ans, sum + n + f[u]); for (auto v : e[u]) if (v != fa) dfs(v, u, sum + n - siz[v] + f[u] - g[v]); } inline void solve() { long long sum = 0; for (register int i = (1); i <= (cnt * 2); i++) last[i] = siz[p[i]], pre[i] = pre[i - 1] + last[i], sum += f[p[i]]; for (register int i = (2); i <= (cnt - 1); i++) { for (register int l = (1); l <= (cnt * 2 - i + 1); l++) { int r = l + i - 1; long long tmp = pre[r] - pre[l - 1]; dp[l] = max(last[l] + tmp, last[l + 1] + tmp); } for (register int j = (1); j <= (cnt * 2 - i + 1); j++) last[j] = dp[j]; } ans = 0; for (register int i = (1); i <= (cnt); i++) { ans = max(ans, n + sum / 2 + dp[i + 1]); for (auto v : e[p[i]]) if (!flag[v]) dfs(v, p[i], n - siz[v] + sum / 2 - f[p[i]] + f[p[i]] - g[v] + dp[i + 1]); } printf( %lld n , ans); } int main() { n = read(); for (register int i = (1); i <= (n); i++) { int x = read() + 1, y = read() + 1; e[x].push_back(y), e[y].push_back(x); } dfs(1); for (register int i = (1); i <= (cnt); i++) dfs(p[i], 0); for (register int i = (1); i <= (cnt); i++) p[cnt + i] = p[i]; solve(); } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) using namespace std; const long long INF = 1e18; const long long MOD = 1e9 + 7; const long long N = 2e6 + 10; const long long dx[8] = {1, 0, -1, 0, 1, 1, -1, -1}, dy[8] = {0, 1, 0, -1, -1, 1, -1, 1}; bool TC = 0; long long binpow(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = res * 1LL * a; a = a * 1LL * a; b >>= 1; } return res; } long long s(long long n) { long long res = 0; while (n) { res += n % 10; n /= 10; } return res; } void test_case() { long long a, b, c; cin >> a >> b >> c; vector<long long> v; for (long long i = 1; i <= 81; i++) { long long var = b * ((long long)binpow(i, a)) + c; if (s(var) == i && var < 1e9) v.push_back(var); } cout << (long long)((v).size()) << n ; for (long long i = 0; i < (long long)((v).size()); i++) { cout << v[i] << ; } } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); if (TC) { long long T; cin >> T; while (T--) test_case(); } else test_case(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { long long int n; cin >> n; if (n % 2 == 0) cout << n / 2 << << n / 2 << n ; else { long long int x = -1; for (long long int i = 3; i <= sqrt(n); i += 2) { if (n % i == 0) { x = i; break; } } if (x == -1) cout << n - 1 << << 1 << n ; else { long long int y = n / x; cout << y * 1 << << y * (x - 1) << n ; } } } } |
#include <bits/stdc++.h> using namespace std; const int N = 15e4 + 10; long long a[N]; bool vis[N]; int main() { int n; scanf( %d , &n); set<pair<long long, int> > se; for (int i = 0; i < n; i++) { scanf( %lld , a + i); se.insert(pair<long long, int>(a[i], i)); } int sz = n; while (!se.empty()) { pair<long long, int> x = *se.begin(); if (!se.empty()) { se.erase(se.begin()); pair<long long, int> y = *se.begin(); if (x.first == y.first) { se.erase(se.begin()); se.insert(pair<long long, int>(y.first * 2, y.second)); vis[x.second] = true; sz--; a[y.second] = y.first * 2; } } else break; } printf( %d n , sz); for (int i = 0; i < n; i++) { if (vis[i]) continue; printf( %lld , a[i]); } return 0; } |
#include <bits/stdc++.h> using std::cin; using std::cout; using std::endl; using std::string; using std::vector; int zfn[100010]; int count = 0, nodes_count; string P, T; vector<string> str; vector<vector<int> > connections; void kmpPreprocess() { int i = 0, j = -1; zfn[0] = -1; while (i < P.size()) { while (j >= 0 && P[i] != P[j]) j = zfn[j]; i++; j++; zfn[i] = j; } } void kmp_DFS(int current, int j) { string T = str[current]; int i = 0; while (i < T.size()) { while (j >= 0 && T[i] != P[j]) j = zfn[j]; i++; j++; if (j == P.size()) { count++; j = zfn[j]; } } for (vector<int>::iterator it = connections.at(current).begin(); it != connections.at(current).end(); ++it) { kmp_DFS(*it, j); } } int main() { cin.sync_with_stdio(false); cin >> nodes_count; str.resize(nodes_count + 1); for (int i = 0; i < nodes_count; i++) { vector<int> v; connections.push_back(v); } int current_parent; for (int current_node = 0; current_node < nodes_count - 1; current_node++) { T = ; cin >> current_parent >> T; connections[current_parent - 1].push_back(current_node + 1); str.at(current_node + 1) = T; } cin >> P; kmpPreprocess(); T = ; kmp_DFS(0, 0); cout << count << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; double a, b, jav = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a >> b; jav += b; } jav /= n; cout << jav + 5; } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:26:00 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top zqynq_lab_1_design_auto_pc_2 -prefix
// zqynq_lab_1_design_auto_pc_2_ zqynq_lab_1_design_auto_pc_1_stub.v
// Design : zqynq_lab_1_design_auto_pc_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module zqynq_lab_1_design_auto_pc_2(aclk, aresetn, s_axi_awaddr, s_axi_awlen,
s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot, s_axi_awregion,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr,
s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot,
s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
/* or1200_top_wrapper.b */
// only removes all un-needed signals
module or1200_top_wrapper #(
parameter AW = 24
)(
// system
input wire clk,
input wire rst,
// data bus
output wire dcpu_cs,
output wire dcpu_we,
output wire [ 4-1:0] dcpu_sel,
output wire [ AW-1:0] dcpu_adr,
output wire [ 32-1:0] dcpu_dat_w,
input wire [ 32-1:0] dcpu_dat_r,
input wire dcpu_ack,
// instruction bus
output wire icpu_cs,
output wire icpu_we,
output wire [ 4-1:0] icpu_sel,
output wire [ AW-1:0] icpu_adr,
output wire [ 32-1:0] icpu_dat_w,
input wire [ 32-1:0] icpu_dat_r,
input wire icpu_ack
);
// icpu_we is always 0
assign icpu_we = 1'b0;
// icpu_sel is always all-ones
assign icpu_sel = 4'b1111;
// icpu_dat_w is don't care
assign icpu_dat_w = 32'hxxxxxxxx;
// cut address to desired width
wire [ 32-1:0] iadr;
wire [ 32-1:0] dadr;
assign dcpu_adr = dadr[AW-1:0];
assign icpu_adr = iadr[AW-1:0];
// OR1200 cpu
or1200_top or1200 (
// system
.clk_i (clk),
.rst_i (rst),
.clmode_i (2'b00),
.pic_ints_i (4'b0000),
// Instruction wishbone
.iwb_clk_i (1'b0),
.iwb_rst_i (1'b1),
.iwb_ack_i (1'b0),
.iwb_err_i (1'b0),
.iwb_rty_i (1'b0),
.iwb_dat_i (32'h00000000),
.iwb_cyc_o (),
.iwb_adr_o (),
.iwb_stb_o (),
.iwb_we_o (),
.iwb_sel_o (),
.iwb_dat_o (),
// .iwb_cab_o (),
// .iwb_cti_o (),
// .iwb_bte_o (),
// Data wishbone
.dwb_clk_i (1'b0),
.dwb_rst_i (1'b1),
.dwb_ack_i (1'b0),
.dwb_err_i (1'b0),
.dwb_rty_i (1'b0),
.dwb_dat_i (32'h00000000),
.dwb_cyc_o (),
.dwb_adr_o (),
.dwb_stb_o (),
.dwb_we_o (),
.dwb_sel_o (),
.dwb_dat_o (),
// .dwb_cab_o (),
// .dwb_cti_o (),
// .dwb_bte_o (),
// Debug interface
.dbg_stall_i (1'b0),
.dbg_ewt_i (1'b0),
.dbg_lss_o (),
.dbg_is_o (),
.dbg_wp_o (),
.dbg_bp_o (),
.dbg_stb_i (1'b0),
.dbg_we_i (1'b0),
.dbg_adr_i (32'h00000000),
.dbg_dat_i (32'h00000000),
.dbg_dat_o (),
.dbg_ack_o (),
// QMEM interface
.dqmem_ce_o (dcpu_cs),
.dqmem_we_o (dcpu_we),
.dqmem_sel_o (dcpu_sel),
.dqmem_addr_o (dadr),
.dqmem_do_o (dcpu_dat_w),
.dqmem_di_i (dcpu_dat_r),
.dqmem_ack_i (dcpu_ack && dcpu_cs),
.iqmem_ce_o (icpu_cs),
.iqmem_sel_o (),
.iqmem_addr_o (iadr),
.iqmem_di_i (icpu_dat_r),
.iqmem_ack_i (icpu_ack && icpu_cs),
// Power management
.pm_cpustall_i (1'b0),
.pm_clksd_o (),
.pm_dc_gate_o (),
.pm_ic_gate_o (),
.pm_dmmu_gate_o (),
.pm_immu_gate_o (),
.pm_tt_gate_o (),
.pm_cpu_gate_o (),
.pm_wakeup_o (),
.pm_lvolt_o ()
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DFBBP_BEHAVIORAL_PP_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_lp__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBP_BEHAVIORAL_PP_V |
// File: mm_sop2.v
// Generated by MyHDL 0.9dev
// Date: Fri Mar 28 22:21:18 2014
`timescale 1ns/10ps
module mm_sop2 (
clock,
reset,
x,
y
);
input clock;
input reset;
input signed [15:0] x;
output signed [15:0] y;
reg signed [15:0] y;
wire signed [34:0] wwire;
wire signed [30:0] cgens_g_11_y;
wire signed [33:0] cgens_g_11_x;
wire signed [30:0] cgens_g_10_y;
wire signed [32:0] cgens_g_10_x;
wire signed [30:0] cgens_g_9_y;
wire signed [31:0] cgens_g_9_x;
wire signed [30:0] cgens_g_8_x;
reg signed [15:0] cgens_g_7_x;
reg signed [15:0] cgens_g_6_x;
reg signed [15:0] cgens_g_5_x;
reg signed [15:0] cgens_g_4_x;
always @(posedge clock, negedge reset) begin: MM_SOP2_CGENS_G_0_RTL_DFF
if (reset == 0) begin
cgens_g_4_x <= 0;
end
else begin
cgens_g_4_x <= x;
end
end
always @(posedge clock, negedge reset) begin: MM_SOP2_CGENS_G_1_RTL_DFF
if (reset == 0) begin
cgens_g_5_x <= 0;
end
else begin
cgens_g_5_x <= cgens_g_4_x;
end
end
always @(posedge clock, negedge reset) begin: MM_SOP2_CGENS_G_2_RTL_DFF
if (reset == 0) begin
cgens_g_6_x <= 0;
end
else begin
cgens_g_6_x <= cgens_g_5_x;
end
end
always @(posedge clock, negedge reset) begin: MM_SOP2_CGENS_G_3_RTL_DFF
if (reset == 0) begin
cgens_g_7_x <= 0;
end
else begin
cgens_g_7_x <= cgens_g_6_x;
end
end
assign cgens_g_8_x = (cgens_g_4_x * 64);
assign cgens_g_9_y = (cgens_g_5_x * 64);
assign cgens_g_10_y = (cgens_g_6_x * 64);
assign cgens_g_11_y = (cgens_g_7_x * 64);
assign cgens_g_9_x = (cgens_g_8_x + 0);
assign cgens_g_10_x = (cgens_g_9_x + cgens_g_9_y);
assign cgens_g_11_x = (cgens_g_10_x + cgens_g_10_y);
assign wwire = (cgens_g_11_x + cgens_g_11_y);
always @(posedge clock, negedge reset) begin: MM_SOP2_RTL_SCALE
if (reset == 0) begin
y <= 0;
end
else begin
y <= $signed(wwire >>> 8);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_BLACKBOX_V
`define SKY130_FD_SC_LP__O221AI_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long sq(long long x) { return x * x; } long double ptos(pair<long long, long long> A, pair<long long, long long> B, pair<long long, long long> C) { long long area = abs((B.first - A.first) * (C.second - A.second) - (B.second - A.second) * (C.first - A.first)); long long llen = sq(B.first - C.first) + sq(B.second - C.second); return 1.0l * area / sqrtl(llen); } int main() { int n; scanf( %d , &n); vector<pair<long long, long long> > p(n); for (int i = 0; i < n; ++i) { int first, second; scanf( %d %d , &first, &second); p[i].first = first, p[i].second = second; } p.push_back(p[0]); long double dans = 1e18l; for (int i = 0; i < n; ++i) { dans = min(dans, ptos(p[i], p[(i - 1 + n) % n], p[i + 1])); for (int j = 0; j < n; ++j) { if (i != j) { dans = min(dans, sqrtl(sq(p[i].first - p[j].first) + sq(p[i].second - p[j].second))); } if (i != j && i != (j + 1) % n) { dans = min(dans, ptos(p[i], p[j], p[j + 1])); } } } printf( %.10lf n , (double)(dans / 2)); return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long int; using ull = unsigned long long int; using dd = double; using ldd = long double; int main() { ios_base::sync_with_stdio(0); cin.tie(0); ll n, r; cin >> n >> r; vector<ll> arr((ll(1)) << n); ll sum = 0; n = ((ll)1) << n; for (int i = 0; i < n; ++i) { cin >> arr[i]; sum += arr[i]; } cout.precision(10); cout << ((dd)sum) / (dd(n)) << n ; for (int i = 0; i < r; ++i) { ll a, b; cin >> a >> b; sum -= arr[a]; sum += b; arr[a] = b; cout << ((dd)sum) / (dd(n)) << n ; } } |
#include <bits/stdc++.h> using namespace std; int prim[10] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29}; int n; long long ans; void DFS(int a, int b, long long temp) { if (temp < ans && a == n) ans = temp; if (a >= n) return; for (int i = 1; i <= 64; i++) { if (ans / prim[b] < temp) break; temp *= prim[b]; DFS(a * (i + 1), (b + 1), temp); } } int main() { while (scanf( %d , &n) != EOF) { ans = LONG_LONG_MAX; DFS(1, 0, 1); printf( %lld n , ans); } return 0; } |
/**
* This module first zeros out video memory, then accepts
* requests to write to individual pixels.
*
* @author Robert Fotino, 2016
*/
`include "definitions.vh"
`define STATE_CLEAR_SCREEN_WRITE 0
`define STATE_CLEAR_SCREEN_CMD 1
`define STATE_PIXEL_WRITE 2
`define STATE_PIXEL_CMD 3
module pixel_writer
(
input clk,
input calib_done,
output reg clear_screen_done,
output pixel_wr_done,
input pixel_en,
input [7:0] pixel_rgb,
input [7:0] pixel_x,
input [7:0] pixel_y,
output reg mem_cmd_en,
output wire [2:0] mem_cmd_instr,
output reg [5:0] mem_cmd_bl,
output reg [29:0] mem_cmd_byte_addr,
input mem_cmd_empty,
input mem_cmd_full,
output reg mem_wr_en,
output reg [3:0] mem_wr_mask,
output reg [31:0] mem_wr_data,
input mem_wr_full,
input mem_wr_empty,
input [6:0] mem_wr_count,
input mem_wr_underrun,
input mem_wr_error
);
initial begin
clear_screen_done = 0;
mem_cmd_en = 0;
mem_cmd_bl = 6'b000000;
mem_cmd_byte_addr = { `GRAPHICS_MEM_PREFIX, 16'h0000 };
mem_wr_en = 0;
mem_wr_mask = 4'b0000;
mem_wr_data = 32'h00000000;
end
assign mem_cmd_instr = 3'b000; // write
// The pixel writer will have a state machine to talk to RAM
reg [1:0] state = `STATE_CLEAR_SCREEN_WRITE;
assign pixel_wr_done = `STATE_PIXEL_WRITE == state && !mem_cmd_full && !mem_wr_full;
reg [6:0] word_index = 0;
reg [7:0] line_index = 0;
always @ (posedge clk) begin
mem_cmd_en <= 0;
mem_wr_en <= 0;
if (calib_done) begin
case (state)
`STATE_CLEAR_SCREEN_WRITE: begin
mem_wr_en <= 1;
mem_wr_data <= 32'h00000000;
mem_wr_mask <= 4'b0000;
word_index <= word_index + 1;
if (word_index == 64) begin
word_index <= 0;
mem_wr_en <= 0;
mem_cmd_en <= 1;
mem_cmd_bl <= 6'b111111;
mem_cmd_byte_addr <= {
`GRAPHICS_MEM_PREFIX,
line_index,
8'b00000000
};
state <= `STATE_CLEAR_SCREEN_CMD;
end
end
`STATE_CLEAR_SCREEN_CMD: begin
if (mem_wr_empty) begin
if (line_index == 191) begin
clear_screen_done <= 1;
state <= `STATE_PIXEL_WRITE;
end else begin
line_index <= line_index + 1;
state <= `STATE_CLEAR_SCREEN_WRITE;
end
end
end
`STATE_PIXEL_WRITE: begin
if (pixel_en && pixel_wr_done) begin
mem_wr_en <= 1;
mem_wr_data <= {4{pixel_rgb}};
mem_wr_mask <= 0 == pixel_x[1:0] ? 4'b1110 :
1 == pixel_x[1:0] ? 4'b1101 :
2 == pixel_x[1:0] ? 4'b1011 : 4'b0111;
mem_cmd_byte_addr <= {
`GRAPHICS_MEM_PREFIX,
pixel_y, pixel_x[7:2], 2'b00
};
state <= `STATE_PIXEL_CMD;
end
end
`STATE_PIXEL_CMD: begin
mem_cmd_bl <= 6'b000000;
mem_cmd_en <= 1;
state <= `STATE_PIXEL_WRITE;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long read() { char ch = getchar(); long long nega = 1; while (!isdigit(ch)) { if (ch == - ) nega = -1; ch = getchar(); } long long ans = 0; while (isdigit(ch)) { ans = ans * 10 + ch - 48; ch = getchar(); } if (nega == -1) return -ans; return ans; } inline long long min(long long x, long long y, long long z) { return min(x, min(y, z)); } inline long long max(long long x, long long y, long long z) { return max(x, max(y, z)); } inline long long add(long long x, long long y) { return x + y >= 998244353 ? x + y - 998244353 : x + y; } inline long long add(long long x, long long y, long long z) { return add(add(x, y), z); } inline long long sub(long long x, long long y) { return x - y < 0 ? x - y + 998244353 : x - y; } inline long long mul(long long x, long long y) { return 1LL * x * y % 998244353; } inline long long mul(long long x, long long y, long long z) { return mul(mul(x, y), z); } vector<long long> a, b; vector<char> ans; long long n; void solve1() { if (a[0] == b[0]) cout << SMALL n0 n ; else cout << IMPOSSIBLE n ; } bool rsame(vector<long long> x, vector<long long> y) { reverse(x.begin(), x.end()); return x == y; } void fail() { cout << IMPOSSIBLE n , exit(0); } bool push_back(char s) { if ((long long)ans.size() <= 200000) { ans.push_back(s); return 1; } return 0; } void solve2() { long long tot = 0, sum = 0; while (a != b && !rsame(a, b)) { if (b[0] > b[1]) swap(b[0], b[1]), tot++, push_back( R ); if (a[0] > a[1] && b[0] == a[1]) { if (b[0] == 0) fail(); if (b[1] < a[0]) fail(); long long ned = b[1] - a[0]; if (ned % b[0] != 0) fail(); sum += ned / b[0], tot += ned / b[0] + 1; if (sum <= 200000) { for (long long i = 1; i <= ned / b[0]; i++) push_back( P ); push_back( R ); } if (sum <= 200000) { cout << SMALL n ; reverse(ans.begin(), ans.end()); cout << (long long)ans.size() << endl; for (auto i : ans) putchar(i); } else { cout << BIG n ; cout << sum << endl; } exit(0); } if (b[0] == a[0]) { if (b[0] == 0) fail(); if (b[1] < a[1]) fail(); long long ned = b[1] - a[1]; if (ned % b[0] != 0) fail(); sum += ned / b[0], tot += ned / b[0] + 1; if (sum <= 200000) { for (long long i = 1; i <= ned / b[0]; i++) push_back( P ); push_back( R ); } if (sum <= 200000) { cout << SMALL n ; reverse(ans.begin(), ans.end()); cout << (long long)ans.size() << endl; for (auto i : ans) putchar(i); } else { cout << BIG n ; cout << sum << endl; } exit(0); } if (b[0] == 0) fail(); tot += b[1] / b[0]; sum += b[1] / b[0]; if (sum <= 200000) { for (long long i = 1; i <= b[1] / b[0]; i++) push_back( P ); } b[1] %= b[0]; } if (a != b) swap(b[0], b[1]), tot++, push_back( R ); if (sum <= 200000) { cout << SMALL n ; reverse(ans.begin(), ans.end()); cout << (long long)ans.size() << endl; for (auto i : ans) putchar(i); } else { cout << BIG n ; cout << sum << endl; } exit(0); } bool inc(vector<long long> x) { for (long long i = 1; i < n; i++) { if (x[i] < x[i - 1]) return 0; } return 1; } bool dec(vector<long long> x) { for (long long i = 1; i < n; i++) { if (x[i] > x[i - 1]) return 0; } return 1; } bool alz(vector<long long> x) { for (long long i = 0; i < n - 1; i++) if (x[i] != 0) return 0; return 1; } void print(vector<long long> x) { for (long long i : x) printf( %lld , i); cout << n ; } void solve3() { long long tot = 0, sum = 0; while (a != b && !rsame(a, b)) { if (alz(b)) fail(); if (dec(b)) reverse(b.begin(), b.end()), tot++, push_back( R ); if (!inc(b)) fail(); sum++; tot++; push_back( P ); for (long long i = n - 1; i > 0; i--) b[i] -= b[i - 1]; } if (a != b) reverse(b.begin(), b.end()), tot++, push_back( R ); if (sum <= 200000) { cout << SMALL n ; cout << ans.size() << endl; reverse(ans.begin(), ans.end()); for (auto i : ans) putchar(i); } else { cout << BIG n ; cout << sum << endl; } } signed main() { cin >> n; a.resize(n), b.resize(n); for (long long i = 0; i < n; i++) a[i] = read(); for (long long i = 0; i < n; i++) b[i] = read(); if (n >= 3) solve3(); else if (n == 2) solve2(); else solve1(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100 + 2; const int MOD = 1 << 30; const double pi = acos(-1); struct line { double a, b, c; }; struct point { double x, y; }; void pointsToLine(point p1, point p2, line &l) { if (fabs(p1.x - p2.x) < 1e-2) { l.a = 1.0; l.b = 0.0; l.c = -p1.x; } else { l.a = -(double)(p1.y - p2.y) / (p1.x - p2.x); l.b = 1.0; l.c = -(double)(l.a * p1.x) - p1.y; } } bool areParallel(line l1, line l2) { return ((fabs(l1.a - l2.a) < 1e-2) && (fabs(l2.b - l2.b) < 1e-2)); } bool areSame(line l1, line l2) { return (areParallel(l1, l2) && (fabs(l1.c - l2.c) < 1e-2)); } bool areIntersect(line l1, line l2, point &p) { if (areParallel(l1, l2)) return false; p.x = (l2.b * l1.c - l1.b * l2.c) / (l2.a * l1.b - l1.a * l2.b); if (fabs(l1.b) > 1e-2) p.y = -(l1.a * p.x + l1.c); else p.y = -(l2.a * p.x + l2.c); return true; } vector<pair<int, int> > AdjList[N]; int n, m; int vis[N]; void dfs(int u, int c) { vis[u] = true; for (int i = 0; i < (int)AdjList[u].size(); ++i) { pair<int, int> v = AdjList[u][i]; if (!vis[v.first]) { if (v.second == c) dfs(v.first, v.second); } } } void solve() { cin >> n >> m; for (int i = 0; i < m; ++i) { int u, v, w; cin >> u >> v >> w; AdjList[u].push_back({v, w}); AdjList[v].push_back({u, w}); } int q; cin >> q; while (q--) { int u, v; cin >> u >> v; int ans = 0; for (int i = 1; i <= m; ++i) { memset(vis, false, sizeof vis); dfs(u, i); if (vis[v]) ans++; } cout << ans << n ; } } int main(void) { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int tc = 1; while (tc--) solve(); } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:64000000 ) using namespace std; int n, b[110], l, r, c, t, q[110], m; int main() { cin >> m >> n; for (int i = 1; i <= m; i++) b[i] = 1 << 30; for (int i = 0; i < n; i++) { cin >> l >> r >> t >> c; for (int j = l; j <= r; j++) { if (t < b[j]) b[j] = t, q[j] = c; } } int s = 0; for (int i = 1; i <= m; i++) { s += q[i]; } cout << s; return 0; } |
#include <bits/stdc++.h> const int MOD = 1e9 + 7; int primes[100000]; using namespace std; bool cmp(const pair<int, int>& a, const pair<int, int>& b) { return a.first > b.first; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int n, k; cin >> n >> k; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } long long sum = 0; long long ans = 0; for (int i = 0; i < n; i++) { sum += a[i]; long long p = sum / k; cout << abs(p - ans) << ; ans = p; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31AI_2_V
`define SKY130_FD_SC_HS__O31AI_2_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o31ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o31ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o31ai_2 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o31ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31AI_2_V
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 2e5; vector<int> gr[MAX_N]; int indx(int h, int t) { return h * 450 + t; } int win = 1e9; int lose = 0; bool draw = false; int used[MAX_N] = {0}; void bfs(int st_indx) { queue<pair<int, int>> q; q.push({0, st_indx}); used[st_indx] = 1; while (!q.empty()) { auto [d, v] = q.front(); q.pop(); if (v == 0) { win = min(win, d); } for (auto e : gr[v]) { if (!used[e]) { used[e] = 1; q.push({d + 1, e}); } } } } void dfs(int v) { used[v] = 1; for (auto e : gr[v]) { if (used[e] == 1) { draw = true; } else if (!used[e]) { dfs(e); } } used[v] = 2; } int d[MAX_N]; void dij(int st) { fill(d, d + MAX_N, 1e9); set<pair<int, int>> s; d[st] = 0; s.insert({0, st}); while (!s.empty()) { int v = s.begin()->second; if (gr[v].empty()) { lose = max(lose, -d[v]); } s.erase(s.begin()); for (auto e : gr[v]) { if (d[e] > d[v] - 1) { s.erase({d[e], e}); d[e] = d[v] - 1; s.insert({d[e], e}); } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int h, t, r, n; cin >> h >> t >> r >> n; vector<pair<int, int>> a(n + 1); for (int i = 1; i <= n; ++i) { cin >> a[i].first >> a[i].second; } int m; cin >> m; vector<pair<int, int>> b(m + 1); for (int i = 1; i <= m; ++i) { cin >> b[i].first >> b[i].second; } for (int h1 = 0; h1 <= r; ++h1) { for (int t1 = 0; t1 <= r; ++t1) { if (h1 + t1 > r || !(h1 + t1)) { continue; } for (int chop_h = 1; chop_h <= min(h1, n); ++chop_h) { int h2 = h1 - chop_h + a[chop_h].first; int t2 = t1 + a[chop_h].second; gr[indx(h1, t1)].push_back(indx(h2, t2)); } for (int chop_t = 1; chop_t <= min(t1, m); ++chop_t) { int h2 = h1 + b[chop_t].first; int t2 = t1 - chop_t + b[chop_t].second; gr[indx(h1, t1)].push_back(indx(h2, t2)); } } } bfs(indx(h, t)); memset(used, 0, sizeof(used)); dfs(indx(h, t)); if (win != 1e9) { cout << Ivan n << win; } else if (draw) { cout << Draw ; } else { dij(indx(h, t)); cout << Zmey n << lose; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxN(1e5 + 10); typedef int i_N[maxN]; int N, Gx[maxN][2], Fx[maxN][2][2]; i_N A; string S; int main() { scanf( %d n , &N); getline(cin, S); for (int i = 0; i < (int)S.size(); i++) A[i + 1] = S[i] == 1 ; A[0] = A[N + 1] = -1; for (int i = N; i; i--) { Gx[i][0] = Gx[i + 1][0]; Gx[i][1] = Gx[i + 1][1]; if (A[i] == 0) Gx[i][0] = max(Gx[i][0], Gx[i + 1][1] + 1); else Gx[i][1] = max(Gx[i][1], Gx[i + 1][0] + 1); } int ans(0); for (int i = 1; i <= N; i++) { for (int j = 0; j < 2; j++) for (int k = 0; k < 2; k++) Fx[i][j][k] = Fx[i - 1][j][k]; if (A[i] == 0) { Fx[i][0][0] = max(Fx[i][0][0], Fx[i - 1][1][0] + 1); Fx[i][1][1] = max(Fx[i][1][1], max(Fx[i - 1][0][0], Fx[i - 1][0][1]) + 1); } else { Fx[i][1][0] = max(Fx[i][1][0], Fx[i - 1][0][0] + 1); Fx[i][0][1] = max(Fx[i][0][1], max(Fx[i - 1][1][0], Fx[i - 1][1][1]) + 1); } ans = max(ans, max(Fx[i][0][1] + Gx[i + 1][1], Fx[i][1][1] + Gx[i + 1][0])); } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int i, j, k, n, m, ans = 0; cin >> n >> m >> k; ans = n + m + k; cout << min(ans / 3, ans - max(n, max(m, k))); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3B_4_V
`define SKY130_FD_SC_HDLL__NAND3B_4_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3b_4 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand3b_4 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3B_4_V
|
#include <bits/stdc++.h> using namespace std; long long n; pair<long long, long long> loc[2001]; long long cp[2001]; long long cw[2001]; pair<long long, pair<long long, long long> > road[4000001]; long long ct = 0; long long val[2001]; long long ans = 0; long long ansleft; long long ansr = 0; bool cs[4000001]; struct node { long long r, f; } opt[100001]; long long fd(long long x) { if (x != opt[x].f) opt[x].f = fd(opt[x].f); return opt[x].f; } void mdf(long long x, long long y) { x = fd(x), y = fd(y); if (x == y) return; if (opt[x].r < opt[y].r) opt[x].f = y, opt[y].r += opt[x].r; else opt[y].f = x, opt[x].r += opt[y].r; } long long dis(long long x, long long y) { return abs(loc[x].first - loc[y].first) + abs(loc[x].second - loc[y].second); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long i, j; for (long long i = 1; i <= 100000; i++) opt[i].f = i, opt[i].r = 1; cin >> n, ansleft = n; for (i = 1; i <= n; i++) cin >> loc[i].first >> loc[i].second; for (i = 1; i <= n; i++) cin >> cp[i]; for (i = 1; i <= n; i++) cin >> cw[i]; for (i = 1; i <= n; i++) val[i] = cp[i]; for (i = 1; i <= n; i++) ans += cp[i]; for (i = 1; i <= n; i++) for (j = i + 1; j <= n; j++) road[++ct] = pair<long long, pair<long long, long long> >( dis(i, j) * (cw[i] + cw[j]), pair<long long, long long>(i, j)); sort(road + 1, road + ct + 1); for (i = 1; i <= ct; i++) { pair<long long, pair<long long, long long> > f = road[i]; long long aa = fd(f.second.first), bb = fd(f.second.second); if (aa != bb && f.first < max(val[aa], val[bb])) { mdf(aa, bb); long long father = fd(aa); ans -= max(val[aa], val[bb]) - f.first; val[father] = min(val[aa], val[bb]); ansleft--, ansr++; cs[i] = true; } } cout << ans << endl; cout << ansleft << endl; for (i = 1; i <= n; i++) { if (cp[i] == val[fd(i)]) cout << i << , val[fd(i)] = -1; } cout << endl; cout << ansr << endl; for (i = 1; i <= ct; i++) if (cs[i]) cout << road[i].second.first << << road[i].second.second << endl; return 0; } |
// megafunction wizard: %LPM_RAM_DQ%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: lpm_ram_dq1.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module lpm_ram_dq1 (
address,
clock,
data,
wren,
q);
input [4:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "PH_l"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria GX"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=PH_l"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL address[4..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq1_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; int n; vector<pair<int, int> > v[maxn]; int size[maxn]; long long mi, mx; void dfs(int first, int fa) { size[first] = 1; for (pair<int, int> i : v[first]) { if (i.first == fa) continue; dfs(i.first, first); if (size[i.first] & 1) mi += 1LL * i.second; size[first] += size[i.first]; mx += 1LL * min(n - size[i.first], size[i.first]) * i.second; } } void solve() { scanf( %d , &n); n = n * 2; for (int i = 1; i <= n; i++) v[i].clear(); for (int i = 1, first, second, z; i < n; i++) { scanf( %d%d%d , &first, &second, &z); v[first].push_back({second, z}); v[second].push_back({first, z}); } mi = 0, mx = 0; dfs(1, 0); printf( %lld %lld n , mi, mx); } int T; int main() { scanf( %d , &T); while (T--) solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR3_2_V
`define SKY130_FD_SC_HD__XNOR3_2_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog wrapper for xnor3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__xnor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xnor3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__xnor3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__xnor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR3_2_V
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; const int INF = 1e9 + 7; const int N = 4e5 + 7; const int M = 5e6 + 7; int vis[M]; int p[N]; int qt[N]; signed main() { ios::sync_with_stdio(false); int q, x, y; cin >> q >> x; set<pair<int, int>> vals; for (int i = 0; i < x; i++) vals.insert({qt[i], i}); while (q--) { int y; cin >> y; y %= x; vals.erase({qt[y], y}); vals.insert({++qt[y], y}); auto k = *vals.begin(); int nVal = k.first * x + k.second; cout << nVal << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long ans; int n, l, w, x, pn; vector<int> pos, neg; int cal(long long a, int b) { if (b == 0) return (a > 0 ? INT_MAX : -INT_MAX); if (a < 0) { if (a % b != 0) return (a / b - 1); } return a / b; } int main() { ios::sync_with_stdio(false); scanf( %d%d%d , &n, &l, &w); for (int i = 1; i <= n; i++) { scanf( %d%d , &x, &pn); if (pn == -1) neg.push_back(x); else pos.push_back(x); } sort(neg.begin(), neg.end()); sort(pos.begin(), pos.end()); for (int i = 0; i < neg.size(); i++) { int v = neg[i]; auto now = lower_bound(pos.begin(), pos.end(), -v - l); int max1 = cal((long long)(v + l) * (w + 1) - 1, w - 1); int max2 = cal((long long)(v + l) * (w - 1) - 1, w + 1); ans += (upper_bound(pos.begin(), now, max1) - pos.begin()) + (upper_bound(now, pos.end(), min(max2, v)) - now); } cout << ans << endl; return 0; } |
/*
* Copyright (c) 2012, Stefan Kristiansson <>
* All rights reserved.
*
* Based on vga_fifo_dc.v in Richard Herveille's VGA/LCD core
* Copyright (C) 2001 Richard Herveille <>
*
* Redistribution and use in source and non-source forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in non-source form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module dual_clock_fifo #(
parameter ADDR_WIDTH = 3,
parameter DATA_WIDTH = 32
)
(
input wire wr_rst_i,
input wire wr_clk_i,
input wire wr_en_i,
input wire [DATA_WIDTH-1:0] wr_data_i,
input wire rd_rst_i,
input wire rd_clk_i,
input wire rd_en_i,
output reg [DATA_WIDTH-1:0] rd_data_o,
output reg full_o,
output reg empty_o
);
reg [ADDR_WIDTH-1:0] wr_addr;
reg [ADDR_WIDTH-1:0] wr_addr_gray;
reg [ADDR_WIDTH-1:0] wr_addr_gray_rd;
reg [ADDR_WIDTH-1:0] wr_addr_gray_rd_r;
reg [ADDR_WIDTH-1:0] rd_addr;
reg [ADDR_WIDTH-1:0] rd_addr_gray;
reg [ADDR_WIDTH-1:0] rd_addr_gray_wr;
reg [ADDR_WIDTH-1:0] rd_addr_gray_wr_r;
function [ADDR_WIDTH-1:0] gray_conv;
input [ADDR_WIDTH-1:0] in;
begin
gray_conv = {in[ADDR_WIDTH-1],
in[ADDR_WIDTH-2:0] ^ in[ADDR_WIDTH-1:1]};
end
endfunction
always @(posedge wr_clk_i) begin
if (wr_rst_i) begin
wr_addr <= 0;
wr_addr_gray <= 0;
end else if (wr_en_i) begin
wr_addr <= wr_addr + 1;
wr_addr_gray <= gray_conv(wr_addr + 1);
end
end
// synchronize read address to write clock domain
always @(posedge wr_clk_i) begin
rd_addr_gray_wr <= rd_addr_gray;
rd_addr_gray_wr_r <= rd_addr_gray_wr;
end
always @(posedge wr_clk_i)
if (wr_rst_i)
full_o <= 0;
else if (wr_en_i)
full_o <= gray_conv(wr_addr + 2) == rd_addr_gray_wr_r;
else
full_o <= full_o & (gray_conv(wr_addr + 1) == rd_addr_gray_wr_r);
always @(posedge rd_clk_i) begin
if (rd_rst_i) begin
rd_addr <= 0;
rd_addr_gray <= 0;
end else if (rd_en_i) begin
rd_addr <= rd_addr + 1'b1;
rd_addr_gray <= gray_conv(rd_addr + 1'b1);
end
end
// synchronize write address to read clock domain
always @(posedge rd_clk_i) begin
wr_addr_gray_rd <= wr_addr_gray;
wr_addr_gray_rd_r <= wr_addr_gray_rd;
end
always @(posedge rd_clk_i)
if (rd_rst_i)
empty_o <= 1'b1;
else if (rd_en_i)
empty_o <= gray_conv(rd_addr + 1) == wr_addr_gray_rd_r;
else
empty_o <= empty_o & (gray_conv(rd_addr) == wr_addr_gray_rd_r);
// generate dual clocked memory
reg [DATA_WIDTH-1:0] mem[(1<<ADDR_WIDTH)-1:0];
always @(posedge rd_clk_i)
if (rd_en_i)
rd_data_o <= mem[rd_addr];
always @(posedge wr_clk_i)
if (wr_en_i)
mem[wr_addr] <= wr_data_i;
endmodule |
//------------------------------------------------------------------------------
// File : axi_pipe.v
// Author : Xilinx Inc.
// -----------------------------------------------------------------------------
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
// Description: A simple pipeline module to simplify the timing where a pattern
// generator and address swap module can be muxed into the data path
//
//------------------------------------------------------------------------------
`timescale 1 ps/1 ps
module axi_pipe (
input axi_tclk,
input axi_tresetn,
input [7:0] rx_axis_fifo_tdata_in,
input rx_axis_fifo_tvalid_in,
input rx_axis_fifo_tlast_in,
output rx_axis_fifo_tready_in,
output [7:0] rx_axis_fifo_tdata_out,
output rx_axis_fifo_tvalid_out,
output rx_axis_fifo_tlast_out,
input rx_axis_fifo_tready_out
);
reg [5:0] rd_addr;
reg [5:0] wr_addr;
reg wea;
reg rx_axis_fifo_tready_int;
reg rx_axis_fifo_tvalid_int;
wire [1:0] wr_block;
wire [1:0] rd_block;
assign rx_axis_fifo_tready_in = rx_axis_fifo_tready_int;
assign rx_axis_fifo_tvalid_out = rx_axis_fifo_tvalid_int;
// should always write when valid data is accepted
always @(rx_axis_fifo_tvalid_in or rx_axis_fifo_tready_int)
begin
wea = rx_axis_fifo_tvalid_in & rx_axis_fifo_tready_int;
end
// simply increment the write address after any valid write
always @(posedge axi_tclk)
begin
if (!axi_tresetn) begin
wr_addr <= 0;
end
else begin
if (rx_axis_fifo_tvalid_in & rx_axis_fifo_tready_int)
wr_addr <= wr_addr + 1;
end
end
// simply increment the read address after any validated read
always @(posedge axi_tclk)
begin
if (!axi_tresetn) begin
rd_addr <= 0;
end
else begin
if (rx_axis_fifo_tvalid_int & rx_axis_fifo_tready_out)
rd_addr <= rd_addr + 1;
end
end
assign wr_block = wr_addr[5:4];
assign rd_block = rd_addr[5:4]-1;
// need to generate the ready output - this is entirely dependant upon the full state
// of the fifo
always @(posedge axi_tclk)
begin
if (!axi_tresetn) begin
rx_axis_fifo_tready_int <= 0;
end
else begin
if (wr_block == rd_block)
rx_axis_fifo_tready_int <= 0;
else
rx_axis_fifo_tready_int <= 1;
end
end
// need to generate the valid output - this is entirely dependant upon the full state
// of the fifo
always @(rd_addr or wr_addr)
begin
if (rd_addr == wr_addr)
rx_axis_fifo_tvalid_int <= 0;
else
rx_axis_fifo_tvalid_int <= 1;
end
genvar i;
generate
for (i=0; i<=7; i=i+1) begin
RAM64X1D RAM64X1D_inst (
.DPO (rx_axis_fifo_tdata_out[i]),
.SPO (),
.A0 (wr_addr[0]),
.A1 (wr_addr[1]),
.A2 (wr_addr[2]),
.A3 (wr_addr[3]),
.A4 (wr_addr[4]),
.A5 (wr_addr[5]),
.D (rx_axis_fifo_tdata_in[i]),
.DPRA0 (rd_addr[0]),
.DPRA1 (rd_addr[1]),
.DPRA2 (rd_addr[2]),
.DPRA3 (rd_addr[3]),
.DPRA4 (rd_addr[4]),
.DPRA5 (rd_addr[5]),
.WCLK (axi_tclk),
.WE (wea)
);
end
endgenerate
RAM64X1D RAM64X1D_inst_last (
.DPO (rx_axis_fifo_tlast_out),
.SPO (),
.A0 (wr_addr[0]),
.A1 (wr_addr[1]),
.A2 (wr_addr[2]),
.A3 (wr_addr[3]),
.A4 (wr_addr[4]),
.A5 (wr_addr[5]),
.D (rx_axis_fifo_tlast_in),
.DPRA0 (rd_addr[0]),
.DPRA1 (rd_addr[1]),
.DPRA2 (rd_addr[2]),
.DPRA3 (rd_addr[3]),
.DPRA4 (rd_addr[4]),
.DPRA5 (rd_addr[5]),
.WCLK (axi_tclk),
.WE (wea)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int n; const long long int mod = 1000000007; long long int f(long long int x, long long int k) { long long int res = 1; while (k) { if (k & 1) res = res * x % mod; x = x * x % mod; k >>= 1; } return res; } int main() { cin >> n; n++; if (n == 1) cout << 1 ; else { long long int a = f(4, n - 2); long long int b = f(2, n - 2); a = a * 2 % mod; cout << (a + b) % mod; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFBBP_PP_SYMBOL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBP_PP_SYMBOL_V
|
`default_nettype none
module j1(
input wire clk,
input wire resetq,
output wire io_rd,
output wire io_wr,
output wire [15:0] mem_addr,
output wire mem_wr,
output wire [15:0] dout,
input wire [15:0] io_din,
output wire [12:0] code_addr,
input wire [15:0] insn_from_memory,
input wire interrupt_request
);
reg interrupt_enable = 0;
wire interrupt = interrupt_request & interrupt_enable;
reg [4:0] dsp, dspN; // Data stack pointer
reg [15:0] st0, st0N; // Top of data stack
reg dstkW; // Data stack write
reg [12:0] pc, pcN; // Program Counter
wire [15:0] insn = interrupt ? 16'h4FFF : insn_from_memory; // Interrupt: Execute "Call 1FFE".
wire [12:0] pc_plus_1 = interrupt ? pc : pc + 13'd1; // Do not increment PC for interrupts to continue later at the same location.
wire fetch = pc[12] & ~interrupt; // Memory fetch data on pc[12] only valid if this is no interrupt entry.
reg rstkW; // Return stack write
wire [15:0] rstkD; // Return stack write value
reg notreboot = 0;
assign mem_addr = st0[15:0];
assign code_addr = pcN;
// The D and R stacks
wire [15:0] st1, rst0;
reg [1:0] dspI, rspI;
stack2 #(.DEPTH(16)) rstack(.clk(clk), .rd(rst0), .we(rstkW), .wd(rstkD), .delta(rspI));
stack2 #(.DEPTH(16)) dstack(.clk(clk), .rd(st1), .we(dstkW), .wd(st0), .delta(dspI));
wire [16:0] minus = {1'b1, ~st0} + st1 + 1;
wire signedless = st0[15] ^ st1[15] ? st1[15] : minus[16];
always @*
begin
// Compute the new value of st0
casez ({fetch, insn[15:8]})
9'b1_???_?????: st0N = insn_from_memory; // Memory fetch
9'b0_1??_?????: st0N = { 1'b0, insn[14:0] }; // Literal
9'b0_000_?????: st0N = st0; // Jump
9'b0_010_?????: st0N = st0; // Call
9'b0_001_?????: st0N = st1; // Conditional jump
9'b0_011_?0000: st0N = st0; // TOS
9'b0_011_?0001: st0N = st1; // NOS
9'b0_011_?0010: st0N = st0 + st1; // +
9'b0_011_?0011: st0N = st0 & st1; // and
9'b0_011_?0100: st0N = st0 | st1; // or
9'b0_011_?0101: st0N = st0 ^ st1; // xor
9'b0_011_?0110: st0N = ~st0; // invert
9'b0_011_?0111: st0N = {16{(minus == 0)}}; // =
9'b0_011_?1000: st0N = {16{signedless}}; // <
9'b0_011_?1001: st0N = {st0[15], st0[15:1]}; // 1 arshift
9'b0_011_?1010: st0N = {st0[14:0], 1'b0}; // 1 lshift
9'b0_011_?1011: st0N = rst0; // r@
9'b0_011_?1100: st0N = minus[15:0]; // -
9'b0_011_?1101: st0N = io_din; // Read IO
9'b0_011_?1110: st0N = {11'b0, dsp}; // depth
9'b0_011_?1111: st0N = {16{(minus[16])}}; // u<
default: st0N = {16{1'bx}};
endcase
end
wire func_T_N = (insn[6:4] == 1);
wire func_T_R = (insn[6:4] == 2);
wire func_write = (insn[6:4] == 3);
wire func_iow = (insn[6:4] == 4);
wire func_ior = (insn[6:4] == 5);
wire func_dint = (insn[6:4] == 6);
wire func_eint = (insn[6:4] == 7);
wire is_alu = !fetch & (insn[15:13] == 3'b011);
assign mem_wr = notreboot & is_alu & func_write;
assign io_wr = notreboot & is_alu & func_iow;
assign io_rd = notreboot & is_alu & func_ior;
assign dout = st1;
wire eint = notreboot & is_alu & func_eint;
wire dint = notreboot & is_alu & func_dint;
wire interrupt_enableN = (interrupt_enable | eint) & ~dint;
// Value which could be written to return stack: Either return address in case of a call or TOS.
assign rstkD = (insn[13] == 1'b0) ? {2'b0, pc_plus_1, interrupt_enable} : st0;
always @*
begin
casez ({fetch, insn[15:13]}) // Calculate new data stack pointer
4'b1_???,
4'b0_1??: {dstkW, dspI} = {1'b1, 2'b01}; // Memory Fetch & Literal
4'b0_001: {dstkW, dspI} = {1'b0, 2'b11}; // Conditional jump
4'b0_011: {dstkW, dspI} = {func_T_N, {insn[1:0]}}; // ALU
default: {dstkW, dspI} = {1'b0, 2'b00}; // Default: Unchanged
endcase
dspN = dsp + {dspI[1], dspI[1], dspI[1], dspI};
casez ({fetch, insn[15:13]}) // Calculate new return stack pointer
4'b1_???: {rstkW, rspI} = {1'b0, 2'b11}; // Memory Fetch, triggered by high address bit set
4'b0_010: {rstkW, rspI} = {1'b1, 2'b01}; // Call
4'b0_011: {rstkW, rspI} = {func_T_R, insn[3:2]}; // ALU
default: {rstkW, rspI} = {1'b0, 2'b00}; // Default: Unchanged
endcase
casez ({notreboot, fetch, insn[15:13], insn[7], |st0}) // New address for PC
7'b0_0_???_?_?: pcN = 0; // Boot: Start at address zero
7'b1_0_000_?_?,
7'b1_0_010_?_?,
7'b1_0_001_?_0: pcN = insn[12:0]; // Jumps & Calls: Destination address
7'b1_1_???_?_?,
7'b1_0_011_1_?: pcN = rst0[13:1]; // Memory Fetch & ALU+exit: Return
default: pcN = pc_plus_1; // Default: Increment PC to next opcode
endcase
end
always @(negedge resetq or posedge clk)
begin
if (!resetq) begin
notreboot <= 0;
{ pc, dsp, st0, interrupt_enable } <= 0;
end else begin
notreboot <= 1;
{ pc, dsp, st0, interrupt_enable} <= { pcN, dspN, st0N, interrupt_enableN };
end
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize(3) #pragma GCC optimize(2) #pragma GCC optimize( Ofast ) using namespace std; vector<int> g[2097312]; int a[2097312][2]; char st[2097312]; int f[2097312]; int find(int x) { if (f[x] == x) return x; return f[x] = find(f[x]); } int main() { int n, i, j, cnt; scanf( %d , &n); scanf( %s , st + 1); for (i = n; i >= 1; --i) { if (st[i] != 1 ) { a[i][0] = a[i + 1][0] + 1; } if (st[i] != 0 ) { a[i][1] = a[i + 1][1] + 1; } g[max(a[i][1], a[i][0])].push_back(i); f[i] = i; } f[n + 1] = n + 1; for (i = 1; i <= n; ++i) { j = 1, cnt = 0; while (j <= n) { j = find(j); if (j > n) { break; } cnt++; j += i; } printf( %d , cnt); for (auto v : g[i]) { f[v] = v + 1; } } return 0; } |
#include <bits/stdc++.h> int main() { int t; scanf( %d , &t); int a[t], b[t], c[t]; for (int i = 0; i < t; i++) scanf( %d %d %d , &a[i], &b[i], &c[i]); for (int i = 0; i < t; i++) { if (a[i] == b[i] && b[i] == c[i]) { printf( YES n ); printf( %d %d %d n , a[i], a[i], a[i]); } else if (a[i] == b[i] && a[i] > c[i]) { printf( YES n ); printf( %d %d %d n , a[i], c[i], c[i]); } else if (b[i] == c[i] && b[i] > a[i]) { printf( YES n ); printf( %d %d %d n , b[i], a[i], a[i]); } else if (a[i] == c[i] && a[i] > b[i]) { printf( YES n ); printf( %d %d %d n , a[i], b[i], b[i]); } else { printf( NO n ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1.0); const int INF = 0x3f3f3f3f; const int MOD = 1e9 + 7; const double EPS = 1e-9; int n, a[100015]; int main() { scanf( %d , &n); if (n % 4) { printf( ! -1 n ); fflush(stdout); } else { printf( ? %d n , 1); fflush(stdout); scanf( %d , &a[1]); printf( ? %d n , 1 + n / 2); fflush(stdout); scanf( %d , &a[1 + n / 2]); int s, e; if (a[1] == a[1 + n / 2]) { printf( ! 1 n ); fflush(stdout); return 0; } else { if (a[1] < a[1 + n / 2]) { s = 1, e = 1 + n / 2; } else { s = 1 + n / 2, e = 1 + n; } } while (s <= e) { int mi = s + e >> 1; int x = (mi + n - 1) % n + 1; int y = (mi + n + n / 2 - 1) % n + 1; printf( ? %d n , x); fflush(stdout); scanf( %d , &a[x]); printf( ? %d n , y); fflush(stdout); scanf( %d , &a[y]); if (a[x] == a[y]) { printf( ! %d n , x); fflush(stdout); return 0; } else if (a[x] < a[y]) { s = mi + 1; } else { e = mi - 1; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; int main() { int T, t1 = 0, t2, maxn = 0, flag = 1, sum = 0, sum1 = 0; scanf( %d , &T); while (T--) { scanf( %d , &t2); if (flag && t2 == 0) { maxn = max(maxn, sum); sum1 = sum; sum = 0; flag = 0; continue; } if (t2 == 0) { maxn = max(maxn, sum); sum = 0; continue; } sum++; if (T == 0) { maxn = max(sum + sum1, maxn); } } printf( %d n , maxn); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1005; const int mod1 = 998244353; const int mod2 = 1e9 + 7; const int b1 = 337; const int b2 = 421; const int inf = 2147483647; struct Pair { int x[2] = {}; bool operator<(const Pair a) const { return x[0] < a.x[0] || x[0] == a.x[0] && x[1] < a.x[1]; } }; struct BitSet { unsigned long long b[16] = {}; inline void reset() { memset(b, 0, sizeof(b)); } inline void set(int x) { b[x / 64] |= (1ull << (x % 64)); } inline void operator^=(const BitSet &a) { for (int i = 0; i < 16; ++i) b[i] ^= a.b[i]; } inline Pair getHashVal() { Pair ans; for (int i = 0; i < 16; ++i) { ans.x[0] = (1ll * ans.x[0] * b1 % mod1 + b[i] % mod1) % mod1; ans.x[1] = (1ll * ans.x[1] * b2 % mod2 + b[i] % mod2) % mod2; } return ans; } }; int n, s, d; BitSet bs[31], sta[1 << 20], cur; int cnt[1 << 20], m; map<Pair, int> mp; void init() { m = min(s, 20); for (int i = 0; i < m; ++i) { cnt[1 << i] = 1; sta[1 << i] = bs[i]; } for (int i = 0; i < (1 << m); ++i) { if (i != (i & -i)) { cnt[i] = cnt[i - (i & -i)] + 1; sta[i] = sta[i - (i & -i)]; sta[i] ^= sta[i & -i]; } Pair x = sta[i].getHashVal(); if (!mp.count(x) || mp[x] > cnt[i]) { mp[x] = cnt[i]; } } for (int i = 0; i < (s - m); ++i) { sta[1 << i] = bs[i + m]; } for (int i = 1; i < (1 << (s - m)); ++i) { if (i == (i & -i)) continue; sta[i] = sta[i - (i & -i)]; sta[i] ^= sta[i & -i]; } } int getans() { BitSet now; int ans = inf; for (int i = 0; i < (1 << (s - m)); ++i) { if (cnt[i] >= ans) continue; now = cur, now ^= sta[i]; Pair x = now.getHashVal(); if (mp.count(x) && mp[x] + cnt[i] < ans) { ans = mp[x] + cnt[i]; } } return ans == inf ? -1 : ans; } int main() { scanf( %d%d%d , &n, &s, &d); for (int i = 0; i < s; ++i) { int c; scanf( %d , &c); for (int j = 0; j < c; ++j) { int u; scanf( %d , &u); u--; bs[i].set(u); } } init(); vector<int> ans; for (int i = 0; i < d; ++i) { int t; scanf( %d , &t); cur.reset(); while (t--) { int u; scanf( %d , &u); u--; cur.set(u); } ans.push_back(getans()); } for (int i = 0; i < ans.size(); ++i) printf( %d n , ans[i]); puts( ); } |
#include <bits/stdc++.h> using namespace std; int ans[100005], t, n, d; signed main() { cin >> t; while (t--) { scanf( %d , &n); int sum = ans[0] = 1; for (int i = 1; i <= n; ++i) { if (sum + (1 << (i + 1)) > n) { d = i; break; } sum += (1 << i); ans[i] = (1 << i); } if (n - sum <= (1 << d)) { ans[d] = n - sum; } else { ans[d] = (n - sum) / 2; ans[d + 1] = n - sum - ans[d]; d++; } printf( %d n , d); for (int i = 1; i < d; ++i) { printf( %d , ans[i] - ans[i - 1]); } printf( %d n , ans[d] - ans[d - 1]); } return 0; } |
//-----------------------------------------------------
// This is FSM demo program using function
// Design Name : fsm_using_function
// File Name : fsm_using_function.v
//-----------------------------------------------------
module fsm_using_function (
clock , // clock
reset , // Active high, syn reset
req_0 , // Request 0
req_1 , // Request 1
gnt_0 , // Grant 0
gnt_1
);
//-------------Input Ports-----------------------------
input clock,reset,req_0,req_1;
//-------------Output Ports----------------------------
output gnt_0,gnt_1;
//-------------Input ports Data Type-------------------
wire clock,reset,req_0,req_1;
//-------------Output Ports Data Type------------------
reg gnt_0,gnt_1;
//-------------Internal Constants--------------------------
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
//-------------Internal Variables---------------------------
reg [SIZE-1:0] state ;// Seq part of the FSM
wire [SIZE-1:0] next_state ;// combo part of FSM
//----------Code startes Here------------------------
assign next_state = fsm_function(state, req_0, req_1);
//----------Function for Combo Logic-----------------
function [SIZE-1:0] fsm_function;
input [SIZE-1:0] state ;
input req_0 ;
input req_1 ;
case(state)
IDLE : if (req_0 == 1'b1) begin
fsm_function = GNT0;
end else if (req_1 == 1'b1) begin
fsm_function= GNT1;
end else begin
fsm_function = IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
fsm_function = GNT0;
end else begin
fsm_function = IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
fsm_function = GNT1;
end else begin
fsm_function = IDLE;
end
default : fsm_function = IDLE;
endcase
endfunction
//----------Seq Logic-----------------------------
always @ (posedge clock)
begin : FSM_SEQ
if (reset == 1'b1) begin
state <= #1 IDLE;
end else begin
state <= #1 next_state;
end
end
//----------Output Logic-----------------------------
always @ (posedge clock)
begin : OUTPUT_LOGIC
if (reset == 1'b1) begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b0;
end
else begin
case(state)
IDLE : begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b0;
end
GNT0 : begin
gnt_0 <= #1 1'b1;
gnt_1 <= #1 1'b0;
end
GNT1 : begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b1;
end
default : begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b0;
end
endcase
end
end // End Of Block OUTPUT_LOGIC
endmodule // End of Module arbiter
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:38:47 03/02/2016
// Design Name:
// Module Name: Ctr
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Ctr(
input [5:0] opCode,
output regDst,
output aluSrc,
output memToReg,
output regWrite,
output memRead,
output memWrite,
output branch,
output [1:0] aluOp,
output jump
);
reg regDst;
reg aluSrc;
reg memToReg;
reg regWrite;
reg memRead;
reg memWrite;
reg branch;
reg[1:0] aluOp;
reg jump;
always @(opCode)
begin
case(opCode)
6'b000010: //jump
begin
regDst=0;
aluSrc=0;
memToReg=0;
regWrite=0;
memRead=0;
memWrite=0;
branch=0;
aluOp=2'b00;
jump=1;
end
6'b000000: //R
begin
regDst=1;
aluSrc=0;
memToReg=0;
regWrite=1;
memRead=0;
memWrite=0;
branch=0;
aluOp=2'b10;
jump=0;
end
6'b100011: //lw
begin
regDst=0;
aluSrc=1;
memToReg=1;
regWrite=1;
memRead=1;
memWrite=0;
branch=0;
aluOp=2'b00;
jump=0;
end
6'b101011: //sw
begin
//regDst=1;
aluSrc=1;
//memToReg=0;
regWrite=0;
memRead=0;
memWrite=1;
branch=0;
aluOp=2'b00;
jump=0;
end
6'b000100: //beq
begin
//regDst=1;
aluSrc=0;
//memToReg=0;
regWrite=0;
memRead=0;
memWrite=0;
branch=1;
aluOp=2'b01;
jump=0;
end
default
begin
regDst=0;
aluSrc=0;
memToReg=0;
regWrite=0;
memRead=0;
memWrite=0;
branch=0;
aluOp=2'b00;
jump=0;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//-----------------------------------------------
// Company: agh
// Engineer: komorkiewicz
// Create Date: 11:41:13 05/10/2011
// Description: log image to ppm file
//-----------------------------------------------
module hdmi_out
(
input hdmi_clk,
input hdmi_vs,
input hdmi_de,
input [31:0] hdmi_data
);
//-----------------------------------------------
integer fm1=0;
reg [7:0]vsc=8'h0;
reg vse=1;
//-----------------------------------------------
initial
begin
//fm1 = $fopen("outA.ppm","wb");
end
//-----------------------------------------------
always @(posedge hdmi_clk)
begin
vse<=hdmi_vs;
if((hdmi_vs==1'b0)&&(vse==1'b1))
begin
$fclose(fm1);
//$stop;
end
if((hdmi_vs==1'b1)&&(vse==1'b0))
begin
fm1 = $fopen({"out/out_",vsc[5:0]/10+8'h30,vsc[5:0]%10+8'h30,".ppm"},"wb");
$display("out%d.ppm saved",vsc);
$fwrite(fm1,"P6%c64 64%c255\n",10,10);
vsc<=vsc+1;
end else
begin
if(hdmi_de)
begin
//just for good debugging
$fwrite(fm1,"%c",{hdmi_data[23:16]});
$fwrite(fm1,"%c",{hdmi_data[15:8]});
$fwrite(fm1,"%c",{hdmi_data[7:0]});
end
end
end
//-----------------------------------------------
endmodule
//-----------------------------------------------
|
#include <bits/stdc++.h> using namespace std; const int kMod = 10007; char buf[222]; int m, n, l; int dp[222][222][222]; int f[222]; int s; struct Matrix { int v[444][444]; void clear() { memset(v, 0, sizeof(v)); } } I, A, F; Matrix operator*(const Matrix &a, const Matrix &b) { Matrix c; c.clear(); for (int i = 0; i < s; ++i) for (int k = 0; k <= i; ++k) if (a.v[i][k]) for (int j = 0; j <= k; ++j) if (b.v[k][j]) c.v[i][j] = (c.v[i][j] + a.v[i][k] * b.v[k][j]) % kMod; return c; } Matrix powMod(const Matrix &a, int b) { Matrix res = I, tmp = a; while (b) { if (b & 1) res = res * tmp; b >>= 1; tmp = tmp * tmp; } return res; } int main() { scanf( %s , buf + 1); m = strlen(buf + 1); scanf( %d , &n); l = m + n; if (buf[1] != buf[m]) { dp[0][0][1] = 1; } else { dp[0][0][0] = 1; } for (int l = 0; l < m; ++l) { for (int r = 0; r < m - l; ++r) { for (int k = 0; k < 222; ++k) if (dp[l][r][k]) { if (buf[l + 1] != buf[m - r]) { int i, j; i = l + 1, j = r; if (buf[i + 1] != buf[m - j]) { dp[i][j][k + 1] += dp[l][r][k]; dp[i][j][k + 1] %= kMod; } else { dp[i][j][k] += dp[l][r][k]; dp[i][j][k] %= kMod; } i = l, j = r + 1; if (buf[i + 1] != buf[m - j]) { dp[i][j][k + 1] += dp[l][r][k]; dp[i][j][k + 1] %= kMod; } else { dp[i][j][k] += dp[l][r][k]; dp[i][j][k] %= kMod; } } else { int i, j; i = l + 1, j = r + 1; if (i + j >= m) { f[k] += dp[l][r][k]; f[k] %= kMod; } else { if (buf[i + 1] != buf[m - j]) { dp[i][j][k + 1] += dp[l][r][k]; dp[i][j][k + 1] %= kMod; } else { dp[i][j][k] += dp[l][r][k]; dp[i][j][k] %= kMod; } } } } } } s = (m - 1) + ((m - 1) / 2 + 1) * 2; for (int i = 0; i < s; ++i) I.v[i][i] = 1; for (int i = 0; i < m - 1; ++i) { A.v[i + 1][i]++; A.v[i][i] += 24; } for (int i = m - 1; i < (m - 1) + ((m - 1) / 2 + 1); ++i) { if (i + 1 < (m - 1) + ((m - 1) / 2) + 1) A.v[i + 1][i]++; A.v[i][i] += 25; A.v[(m - 1) + ((m - 1) / 2 + 1) + (i - (m - 1))][i]++; } for (int i = (m - 1) + ((m - 1) / 2 + 1); i < s; ++i) { A.v[i][i] += 26; } for (int i = 0; i < m; ++i) { F.v[i][i] = 1; } F = powMod(A, (l - 1) / 2 + 1) * F; int ans = 0; for (int k = 0; k < 222; ++k) if (f[k]) { int n24 = k, n25 = (m - k - 1) / 2 + 1; int from = (m - 1) - k; int to = (m - 1) + ((m - 1) / 2 + 1) + n25 - 1; ans = (ans + F.v[to][from] * f[k]) % kMod; } if (l & 1) { F.clear(); for (int i = 0; i < m; ++i) { F.v[i][i] = 1; } F = powMod(A, (l - 1) / 2) * F; for (int k = 0; k < 222; ++k) if (f[k]) { int n24 = k, n25 = (m - k - 1) / 2 + 1; if ((m - n24) % 2 == 0) { int from = (m - 1) - k; int to = (m - 1) + n25 - 1; ans -= F.v[to][from] * f[k] % kMod; if (ans < 0) ans += kMod; } } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int N = 3005; int n, c, a[N], dp[N][N], g[N][N], freq[N], mul[N], imul[N], pw[N], cnt[N]; int dp2[2][N][1 << 12]; int inverse(int n) { if (n == 1) return 1; return inverse(mod % n) * 1LL * (mod - mod / n) % mod; } inline void add(int &x, int y) { x += y; if (x >= mod) x -= mod; } void solve1() { for (int i = 1; i <= n; i++) { a[i]--; } memset(dp2, 0, sizeof(dp2)); int flg = 0; dp2[0][0][0] = 1; for (int i = 1; i <= n; i++) { for (int p = 0; p * c <= i; p++) { for (int mask = 0; mask < (1 << c); mask++) { dp2[flg ^ 1][p][mask] = 0; } } for (int p = 0; p * c <= i; p++) { for (int mask = 0; mask + 1 < (1 << c); mask++) { int nmask = mask | (1 << a[i]); if (nmask + 1 == (1 << c)) { add(dp2[flg ^ 1][p + 1][0], dp2[flg][p][mask]); } else { add(dp2[flg ^ 1][p][nmask], dp2[flg][p][mask]); } add(dp2[flg ^ 1][p][mask], dp2[flg][p][mask]); } } flg ^= 1; } memset(cnt, 0, sizeof(cnt)); for (int p = 0; p <= n; p++) { for (int mask = 0; mask + 1 < (1 << c); mask++) { add(cnt[p], dp2[flg][p][mask]); } } add(cnt[0], mod - 1); for (int i = 0; i <= n; i++) { cout << cnt[i] << ; } cout << n ; } void solve2() { mul[0] = 0; pw[0] = 1; for (int i = 1; i <= n; i++) { mul[i] = mul[i - 1] + mul[i - 1] + 1; if (mul[i] >= mod) mul[i] -= mod; imul[i] = inverse(mul[i]); pw[i] = mul[i] + 1; } memset(g, 0, sizeof(g)); for (int i = 1; i <= n; i++) { int cnt = 0; long long prd = 1; memset(freq, 0, sizeof(freq)); for (int j = i; j <= n; j++) { if (freq[a[j]] == 0) { cnt++; } else { (prd *= imul[freq[a[j]]]) %= mod; } freq[a[j]]++; (prd *= mul[freq[a[j]]]) %= mod; if (cnt == c) { g[i][j] = prd * imul[freq[a[j]]] % mod; } } } memset(dp, 0, sizeof(dp)); for (int i = 1; i <= n; i++) { dp[i][1] = g[1][i]; for (int j = 1; j <= i; j++) { for (int p = 2; p * c <= i; p++) { dp[i][p] += dp[j - 1][p - 1] * 1LL * g[j][i] % mod; if (dp[i][p] >= mod) dp[i][p] -= mod; } } } memset(cnt, 0, sizeof(cnt)); for (int i = 1; i <= n; i++) { for (int p = 1; p * c <= i; p++) { cnt[p] += dp[i][p] * 1LL * pw[n - i] % mod; if (cnt[p] >= mod) cnt[p] -= mod; } } cnt[0] = mul[n] + mod - cnt[1]; if (cnt[0] >= mod) cnt[0] -= mod; for (int p = 1; p <= n; p++) { cnt[p] += mod - cnt[p + 1]; if (cnt[p] >= mod) cnt[p] -= mod; } for (int i = 0; i <= n; i++) { cout << cnt[i] << ; } cout << n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> c; for (int i = 1; i <= n; i++) { cin >> a[i]; } if (c <= 10) { solve1(); } else { solve2(); } return 0; } |
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// A single FFT stage.
// We fill it with values and then empty it.
// This is for QA purposes.
module qa_contents
#(
parameter WIDTH = 32,
parameter MWIDTH = 1
)
(
input wire clk,
input wire rst_n,
input wire [WIDTH-1:0] in_data,
input wire in_nd,
input wire [MWIDTH-1:0] in_m,
input wire [`MSG_WIDTH-1:0] in_msg,
input wire in_msg_nd,
output wire [WIDTH-1:0] out_data,
output wire out_nd,
output wire [MWIDTH-1:0] out_m,
output wire [`MSG_WIDTH-1:0] out_msg,
output wire out_msg_nd,
output wire error
);
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
localparam integer LOG_N = clog2(`N);
localparam integer STAGE_EMPTY = 2'd0;
localparam integer STAGE_WRITING = 2'd1;
localparam integer STAGE_FULL = 2'd2;
localparam integer STAGE_READING = 2'd3;
wire buffer_read_delete;
wire buffer_read_full;
wire [WIDTH+MWIDTH-1:0] buffer_data;
wire buffer_error;
buffer_BB #(WIDTH+MWIDTH, `N) buffer_in
(
.clk(clk),
.rst_n(rst_n),
.write_strobe(in_nd),
.write_data({in_data, in_m}),
.read_delete(buffer_read_delete),
.read_full(buffer_read_full),
.read_data(buffer_data),
.error(buffer_error)
);
reg b2s_start;
wire b2s_active;
wire [LOG_N-1:0] b2s_addr0;
wire [LOG_N-1:0] b2s_addr1;
wire b2s_nd;
wire [WIDTH-1:0] b2s_data0;
wire [WIDTH-1:0] b2s_data1;
wire b2s_mnd;
wire [MWIDTH-1:0] b2s_m;
wire b2s_error;
buffer_BB_to_stage #(`N, LOG_N, WIDTH, MWIDTH) b2s
(
.clk(clk),
.rst_n(rst_n),
.start(b2s_start),
.read_full(buffer_read_full),
.read_data(buffer_data),
.read_delete(buffer_read_delete),
.out_addr0(b2s_addr0),
.out_addr1(b2s_addr1),
.out_nd(b2s_nd),
.out_data0(b2s_data0),
.out_data1(b2s_data1),
.out_mnd(b2s_mnd),
.out_m(b2s_m),
.active(b2s_active),
.error(b2s_error)
);
wire mbuffer_read;
wire mbuffer_error;
wire mbuffer_full;
wire [MWIDTH-1:0] s2o_m;
buffer_BB #(MWIDTH, `N*2) mstore
(
.clk(clk),
.rst_n(rst_n),
.write_strobe(b2s_mnd),
.write_data(b2s_m),
.read_delete(mbuffer_read),
.read_full(mbuffer_full),
.read_data(s2o_m),
.error(mbuffer_error)
);
wire [LOG_N-1:0] s2o_addr0;
wire [LOG_N-1:0] s2o_addr1; // not used
wire [WIDTH-1:0] s2o_data0;
wire [WIDTH-1:0] s2o_data1;
wire error_stage;
wire [1:0] s_state;
wire s2o_active;
stage #(`N, LOG_N, WIDTH) stage_0
(
.clk(clk),
.rst_n(rst_n),
.in_addr0(b2s_addr0),
.in_addr1(b2s_addr1),
.in_nd(b2s_nd),
.in_data0(b2s_data0),
.in_data1(b2s_data1),
.in_active(b2s_active),
.out_addr0(s2o_addr0),
.out_addr1(s2o_addr1),
.out_data0(s2o_data0),
.out_data1(s2o_data1),
.out_active(s2o_active),
.state(s_state),
.error(error_stage)
);
reg s2o_start;
wire s2o_error;
stage_to_out #(`N, LOG_N, WIDTH, MWIDTH) s2o
(
.clk(clk),
.rst_n(rst_n),
.start(s2o_start),
.addr(s2o_addr0),
.in_data(s2o_data0),
.out_mread(mbuffer_read),
.in_m(s2o_m),
.out_nd(out_nd),
.out_data(out_data),
.out_m(out_m),
.active(s2o_active),
.error(s2o_error)
);
reg writing;
assign stage_addr0 = (writing)?b2s_addr0:s2o_addr0;
assign stage_addr1 = b2s_addr1;
// The logic to inititate the reading and writing.
always @ (posedge clk)
if (~rst_n)
begin
writing <= 1'b1;
b2s_start <= 1'b1;
s2o_start <= 1'b0;
end
else
begin
//defaults
b2s_start <= 1'b0;
s2o_start <= 1'b0;
if (s_state == STAGE_EMPTY)
b2s_start <= 1'b1;
else if (s_state == STAGE_FULL)
s2o_start <= 1'b1;
end
assign error = buffer_error | b2s_error | mbuffer_error | error_stage | s2o_error;
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, s, f, add = 0, rund = 1; cin >> n >> m >> s >> f; if (s < f) add = 1; else add = -1; for (int i = 0; i < m; i++) { int t, l, r; cin >> t >> l >> r; while (rund < t) { if (s == f) break; if (add == 1) cout << R ; else if (add == -1) cout << L ; s += add; rund++; } if (s == f) continue; if (t == rund) { rund++; if (s >= l && s <= r || s + add >= l && s + add <= r) cout << X ; else if (add == 1) { cout << R ; s += add; } else if (add == -1) { cout << L ; s += add; } } } while (s != f) { if (add == 1) cout << R ; else if (add == -1) cout << L ; s += add; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int a[n]; for (int i = 0; i < n; i++) a[i] = i + 1; int cnt = (n / 2) * (n / 2); if (n % 2 == 0) cnt -= n / 2; if (cnt < m) { cout << -1; return 0; } int idx = n - 1; while (m < cnt) { if (cnt - (idx / 2) <= m) { a[idx] += 2 * (cnt - m); break; } else { cnt -= idx / 2; if (idx + 1 == n) a[idx] = 1000 * 1000 * 1000; else a[idx] = a[idx + 1] - 2 * n; } idx--; } for (int i = 0; i < n; i++) cout << a[i] << ; } |
#include <bits/stdc++.h> using namespace std; vector<int> gr[300005]; int n, m; int col[300005]; void go(int now) { for (auto to : gr[now]) { if (col[to]) continue; col[to] = 3 - col[now]; go(to); } int cnt = 0; for (auto to : gr[now]) { cnt += (col[to] == col[now]); } if (cnt > 1) col[now] = 3 - col[now]; } int main() { int i, j; scanf( %d , &n); scanf( %d , &m); for (i = 1; i <= m; i++) { int u, v; scanf( %d , &u); scanf( %d , &v); gr[u].push_back(v); gr[v].push_back(u); } for (i = 1; i <= n; i++) { if (col[i]) continue; col[i] = 1; go(i); } for (i = 1; i <= n; i++) printf( %d , col[i] - 1); printf( n ); return 0; } |
#include <bits/stdc++.h> #define Mid ((l + r) >> 1) #define lson (rt << 1) #define rson (rt << 1 | 1) using namespace std; int read(){ char c; int num, f = 1; while(c = getchar(),!isdigit(c)) if(c == - ) f = -1; num = c - 0 ; while(c = getchar(), isdigit(c)) num = num * 10 + c - 0 ; return f * num; } const int N = 2e5 + 1009; int a, b, k; int x[N], y[N]; signed main() { a = read(); b = read(); k = read(); if(k == 0) { printf( Yes n ); for(int i = 1; i <= b; i++) printf( 1 ); for(int i = 1; i <= a; i++) printf( 0 );printf( n ); for(int i = 1; i <= b; i++) printf( 1 ); for(int i = 1; i <= a; i++) printf( 0 );printf( n ); return 0; } if(a + b < k + 2 || (a > 0 && b == 1) || a == 0) { printf( No n ); return 0; } if(a >= k) { y[1] = 1; x[k + 1] = 1; for(int i = a + 2; i <= a + b; i++) x[i] = y[i] = 1; } else { y[1] = 1; x[k + 1] = 1; for(int i = a + 1; i <= k; i++) { x[i] = y[i] = 1; } for(int i = k + 2; i <= a + b; i++) x[i] = y[i] = 1; } reverse(x + 1, x + 1 + a + b); reverse(y + 1, y + 1 + a + b); printf( Yes n ); for(int i = 1; i <= a + b; i++) printf( %d , x[i]); printf( n ); for(int i = 1; i <= a + b; i++) printf( %d , y[i]); printf( n ); return 0; } /* 两个位置都为1 表示这两个位置之间的数都变成1 也就是说只用两个1就可以构造出来了 可以把中间一对0换成1 可以减少0的数量 至少需要2+k */ |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFBUF_SYMBOL_V
`define SKY130_FD_SC_LP__BUFBUF_SYMBOL_V
/**
* bufbuf: Double buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__bufbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFBUF_SYMBOL_V
|
#include <bits/stdc++.h> int n, m, k; std::unordered_set<int> G[100123]; int deg[100123]; inline bool CheckClique(int x) { std::vector<int> V({x}); for (int y : G[x]) V.emplace_back(y); for (int u : V) for (int v : V) if (u < v && (!G[u].count(v))) return false; return true; } inline void Solve() { for (int i = 1; i <= n; ++i) G[i].clear(); memset(deg, 0, sizeof(deg)); scanf( %d%d%d , &n, &m, &k); std::vector<std::pair<int, int>> input; for (int i = 1, u, v; i <= m; ++i) { scanf( %d%d , &u, &v); input.emplace_back(std::make_pair(u, v)); } if ((1LL * k * (k - 1) / 2) > m) return puts( -1 ), void(); for (auto& p : input) { G[p.first].insert(p.second); G[p.second].insert(p.first); ++deg[p.first]; ++deg[p.second]; } int cnt = 0; std::queue<int> q; for (int i = 1; i <= n; ++i) if (deg[i] < k) { if (deg[i] == k - 1 && CheckClique(i)) { puts( 2 ); for (int x : G[i]) printf( %d , x); printf( %d n , i); return; } q.push(i); ++cnt; } while (!q.empty()) { int u = q.front(); q.pop(); for (int v : G[u]) { G[v].erase(u); if ((--deg[v]) == k - 1) { if (CheckClique(v)) { puts( 2 ); for (int x : G[v]) printf( %d , x); printf( %d n , v); return; } q.push(v); ++cnt; } } } if (cnt < n) { std::vector<int> ans; for (int i = 1; i <= n; ++i) if (deg[i] >= k) ans.emplace_back(i); printf( 1 n%d n , static_cast<int>(ans.size())); for (int i : ans) printf( %d , i); puts( ); } else puts( -1 ); } int main() { int T; scanf( %d , &T); while (T--) Solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[200000 + 1]; int main() { long long t; cin >> t; while (t--) { long long n, k; cin >> n >> k; for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); sort(a + 1, a + n + 1); long long mpos = 0, ppos = 0; for (int i = 1; i <= n; i++) { if (a[n - i + 1] > 0) ppos = n - i + 1; if (a[i] < 0) mpos = i; } long long left = a[1], right = a[n]; if (left < 0) left *= -1; long long sum = 0; if (ppos != 0) { long long s = ppos - 1; if ((n - ppos + 1) % k != 0) { s += (n - ppos + 1) % k; sum += a[s] * 2; } for (int i = s + k; i <= n; i += k) sum += a[i] * 2; } if (mpos != 0) { long long s = mpos + 1; if ((mpos) % k != 0) { s -= (mpos % k); sum -= a[s] * 2; } for (long long i = s - k; i >= 1; i -= k) sum -= a[i] * 2; } if (ppos != 0 and mpos == 0) sum -= a[n]; else if (ppos == 0 and mpos != 0) sum += a[1]; else { if (left < right) sum -= a[n]; else sum += a[1]; } printf( %lld n , sum); } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,avx2,fma,tune=native ) using namespace std; int a1, b1, c1, a2, b2, c2; int d1, d2, d3, d4, d5, d6, d7; int f1, f2, f3, f4, f5, f6, f7; bool check() { return f1 <= d1 && f2 <= d2 && f3 <= d3 && f4 <= d4 && f5 <= d5 && f6 <= d6 && f7 <= d7 && (f1 + f2 + f3 + f4 <= a1) && (f1 + f2 + f5 + f6 <= b1) && (f1 + f3 + f5 + f7 <= c1) && (f1 + f2 + f3 + f4 >= d1 + d2 + d3 + d4 - a2) && (f1 + f2 + f5 + f6 >= d1 + d2 + d5 + d6 - b2) && (f1 + f3 + f5 + f7 >= d1 + d3 + d5 + d7 - c2); } void solve() { cin >> a1 >> b1 >> c1 >> a2 >> b2 >> c2; cin >> d1 >> d2 >> d3 >> d4 >> d5 >> d6 >> d7; if (d1 + d2 + d3 + d4 > a1 + a2 || d1 + d2 + d5 + d6 > b1 + b2 || d1 + d3 + d5 + d7 > c1 + c2) { cout << -1 n ; return; } int t = d2 + d3 + d5; for (int A = 0; A <= a1; ++A) { for (int B = 0; B <= t; ++B) { int lf3 = max({0, A + B - b1}); int rf3 = min({d3, A + B + b2 - d1 - d2 - d5}); int lf5 = max({0, A + B - a1}); int rf5 = min({d5, A + B + a2 - d1 - d2 - d3}); int lf3f5 = max({0, B - d2, d1 + d3 + d5 - A - c2}); int rf3f5 = min({d3 + d5, c1 - A, B}); if (rf3 < lf3 || rf5 < lf5 || rf3f5 < lf3f5) continue; f3 = lf3; f5 = lf5; if (f3 + f5 > rf3f5) continue; if (f3 + f5 < lf3f5) { int tmp; int delta = lf3f5 - (f3 + f5); tmp = min(delta, rf3 - f3); f3 += tmp; delta -= tmp; tmp = min(delta, rf5 - f5); f5 += tmp; delta -= tmp; if (delta > 0) continue; } f1 = A; f2 = B - f3 - f5; f4 = max(0, d1 + d2 + d3 + d4 - a2 - A - B + f5); f6 = max(0, d1 + d2 + d5 + d6 - b2 - A - B + f3); f7 = max(0, d1 + d3 + d5 + d7 - c2 - A - B + f2); if (check()) { cout << f1 << << f2 << << f3 << << f4 << << f5 << << f6 << << f7 << n ; return; } } } cout << -1 n ; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int x; cin >> x; if (x % 4 == 0) printf( 1 A ); else if (x % 4 == 1) printf( 0 A ); else if (x % 4 == 2) printf( 1 B ); else if (x % 4 == 3) printf( 2 A ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 2e3; vector<int> e[MAX_N], d; vector<char> flag; void dfs(int v) { if (d[v] != -1) return; d[v] = 1; for (int to : e[v]) { dfs(to); d[v] = max(d[v], d[to] + 1); } } int main() { int n; scanf( %d , &n); d.assign(n, -1); for (int i = 0; i < n; i++) { int x; scanf( %d , &x); if (x != -1) e[x - 1].push_back(i); } for (int i = 0; i < n; i++) if (d[i] == -1) dfs(i); int ans = 1; for (int i : d) ans = max(ans, i); printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int i, j, p, d, n, m, total, k, ok, a, b, c, op, maxi, rasp, m1, m2, p1, p2, rez, modu = 1000000007, mini, mij, ls, ld; pair<long long int, long long int> v[300500]; priority_queue<pair<long long int, long long int> > nxt; priority_queue<long long int> q; string s; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; cin >> a >> b; n--; for (i = 1; i <= n; i++) { cin >> v[i].first >> v[i].second; } sort(v + 1, v + 1 + n); for (i = 1; i <= n; i++) { if (v[i].first > a) q.push((v[i].second - v[i].first + 1) * -1), rez++; else { nxt.push(v[i]); } } mini = rez; while (a && q.size()) { a += q.top(); q.pop(); if (a < 0) break; rez--; while (nxt.size() && nxt.top().first > a) { q.push((nxt.top().second - nxt.top().first + 1) * -1), rez++; nxt.pop(); } mini = min(rez, mini); } cout << mini + 1; return 0; } |
#include <bits/stdc++.h> using namespace std; int customer[1000][1000]; int main() { int n, m, k; cin >> n >> m >> k; deque<int> dq; for (int i = 0; i < k; i++) { int x; cin >> x; dq.push_back(x); } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) cin >> customer[i][j]; } int t = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { int cnt = 0; for (deque<int>::iterator l = dq.begin(); l != dq.end(); l++) { cnt++; if (*l == customer[i][j]) { int x = *l; dq.erase(l); dq.push_front(x); t += cnt; break; } } } } cout << t; return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ba
//
// Generated
// by: wig
// on: Mon Oct 24 15:17:36 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ba.v,v 1.2 2005/10/24 15:50:24 wig Exp $
// $Date: 2005/10/24 15:50:24 $
// $Log: ent_ba.v,v $
// Revision 1.2 2005/10/24 15:50:24 wig
// added 'reg detection to ::out column
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.64 2005/10/20 17:28:26 lutscher Exp
//
// Generator: mix_0.pl Revision: 1.38 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ba
//
// No `defines in this module
module ent_ba
//
// Generated module inst_ba
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ba
//
//
//!End of Module/s
// --------------------------------------------------------------
|
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