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#include <bits/stdc++.h> using namespace std; template <class T> bool uin(T &a, T b) { return a > b ? (a = b, true) : false; } template <class T> bool uax(T &a, T b) { return a < b ? (a = b, true) : false; } long long f[2001], dp[2001][2001], m = 998244353; long long fun(long long i, long long j) { if (i == 0) return (f[j]); else return (f[j] - f[i - 1]); } long long fpow(long long a, long long p) { if (p == 0) return (1); long long b = fpow(a, p / 2); if (p % 2 == 0) return ((b * b) % m); else return ((((b * b) % m) * a) % m); } int main() { string s; cin >> s; if (s[0] == ? ) f[0] = 1; for (long long i = 1; i < s.length(); i++) { if (s[i] == ? ) f[i] += 1; f[i] += f[i - 1]; } for (long long i = 2; i <= s.length(); i++) { for (long long j = 0; j <= (s.length() - i); j++) { if (s[j] != ( ) dp[j][j + i - 1] = (dp[j][j + i - 1] + dp[j + 1][j + i - 1]) % m; if (s[j + i - 1] != ) ) dp[j][j + i - 1] = (dp[j][j + i - 1] + dp[j][j + i - 2]) % m; if ((s[j] != ( ) && (s[j + i - 1] != ) )) dp[j][j + i - 1] = (dp[j][j + i - 1] - dp[j + 1][j + i - 2] + m) % m; if ((s[j] != ) ) && (s[j + i - 1] != ( )) dp[j][j + i - 1] = (dp[j][j + i - 1] + dp[j + 1][j + i - 2] + (long long)fpow(2, fun(j + 1, j + i - 2))) % m; } } cout << dp[0][s.length() - 1]; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A32O_PP_BLACKBOX_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a32o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int dr[] = {-1, 0, 1, 0, -1, 1, 1, -1}; int dc[] = {0, 1, 0, -1, 1, 1, -1, -1}; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; while (cin >> n) { vector<int> arr; int st = 1; int ans = 0; for (int i = (0); i <= (2 * n - 1); i += (1)) { string s; cin >> s; if (s == remove ) { if (arr.empty()) { st++; continue; } if (st == arr[(int)arr.size() - 1]) { st++; arr.pop_back(); } else { arr.clear(); st++; ans++; } } else { int nn; cin >> nn; arr.push_back(nn); } } cout << ans << endl; } return 0; } |
`include "params.v"
`define INCLUDE_PARAMS
`include "ISA.v"
`define INCLUDE_ISA
// include modules
`include "IMem.v"
`define INCLUDE_IF_MOD
`include "IF.v"
`include "IF_ID.v"
`include "Reg.v"
`define INCLUDE_ID_MOD
`include "ID.v"
`include "ID_EXE.v"
`define INCLUDE_EXE_MOD
`include "EXE.v"
`include "EXE_MEM.v"
`include "DMem.v"
`define INCLUDE_MEM_MOD
`include "MEM.v"
`include "MEM_WB.v"
`define INCLUDE_WB_MOD
`include "WB.v"
`include "WB_out.v"
module Proc (
input clk, // Clock
input rst_n, // Asynchronous reset active low
output reg halt
`ifdef TRACE_MEM
,input wire Print
`endif
);
// wires for IF to IF-ID
wire [`WIDTH - 1:0] IR_IF_ID1;
wire [`WIDTH - 3:0] PC_IF_ID1;
// wires for ID to IF-ID
wire [`WIDTH - 1:0] IR_IF_ID2;
wire [`WIDTH - 3:0] PC_IF_ID2;
// wires for IF
wire IsBranch;
wire [`WIDTH - 3:0] BranchAddr;
IF IF(.clk(clk), .rst_n(rst_n), .IR(IR_IF_ID1), .PC(PC_IF_ID1), .IsBranch(IsBranch), .BranchAddr(BranchAddr));
IF_ID IF_ID(.clk(clk), .IR_in(IR_IF_ID1), .PC_in(PC_IF_ID1),
.IR_out(IR_IF_ID2), .PC_out(PC_IF_ID2));
// wires for Reg to ID - Read port 1
wire [`WIDTH - 1:0] Rd1_data;
wire [`REG_ADDR_LEN - 1:0] Rd1_addr;
wire Rd1_en;
wire Rd1_st;
// Read port 2
wire [`WIDTH - 1:0] Rd2_data;
wire [`REG_ADDR_LEN - 1:0] Rd2_addr;
wire Rd2_en;
wire Rd2_st;
// Write port
wire [`WIDTH - 1:0] Wt_data;
wire [`REG_ADDR_LEN - 1:0] Wt_addr;
wire Wt_en;
wire [1:0] w_mode;
Reg Reg(.clk(clk), .ra(Rd1_addr), .dataA(Rd1_data), .r_en_A(Rd1_en), .st_A(Rd1_st),
.rb(Rd2_addr), .dataB(Rd2_data), .r_en_B(Rd2_en), .st_B(Rd2_st),
.rc(Wt_addr), .dataC(Wt_data), .w_en(Wt_en), .w_mode(w_mode));
// wires for ID to ID-EXE
wire [`WIDTH - 3:0] PC_ID_EXE1;
wire [`WIDTH - 1:0] IR_ID_EXE1;
wire [`WIDTH - 1:0] X_ID_EXE1;
wire [`WIDTH - 1:0] Y_ID_EXE1;
// wires for ID-EXE to EXE
wire [`WIDTH - 3:0] PC_ID_EXE2;
wire [`WIDTH - 1:0] IR_ID_EXE2;
wire [`WIDTH - 1:0] X_ID_EXE2;
wire [`WIDTH - 1:0] Y_ID_EXE2;
ID ID(.clk(clk), .PC_in(PC_IF_ID2), .IR_in(IR_IF_ID2), // pipeline in
.Rd1_addr(Rd1_addr), .Rd1_data(Rd1_data), .Rd1_en(Rd1_en), .Rd1_st(Rd1_st), // register ports
.Rd2_addr(Rd2_addr), .Rd2_data(Rd2_data), .Rd2_en(Rd2_en), .Rd2_st(Rd2_st),
.PC_out(PC_ID_EXE1), .IR_out(IR_ID_EXE1), .X(X_ID_EXE1), .Y(Y_ID_EXE1),
.IsFlush(IsBranch)); // pipeline out
ID_EXE ID_EXE(.clk(clk), .PC_in(PC_ID_EXE1), .IR_in(IR_ID_EXE1), .X_in(X_ID_EXE1), .Y_in(Y_ID_EXE1), //pipeline in
.PC_out(PC_ID_EXE2), .IR_out(IR_ID_EXE2), .X_out(X_ID_EXE2), .Y_out(Y_ID_EXE2)); // pipeline out
// wires for EXE to EXE-MEM
wire [`WIDTH - 3:0] PC_EXE_MEM1;
wire [`WIDTH - 1:0] IR_EXE_MEM1;
wire [`WIDTH - 1:0] Z_EXE_MEM1;
wire [`WIDTH - 1:0] Addr_EXE_MEM1;
// wires for EXE-MEM to MEM
wire [`WIDTH - 3:0] PC_EXE_MEM2;
wire [`WIDTH - 1:0] IR_EXE_MEM2;
wire [`WIDTH - 1:0] Z_EXE_MEM2;
wire [`WIDTH - 1:0] Addr_EXE_MEM2;
EXE EXE(.clk(clk), .PC_in(PC_ID_EXE2), .IR_in(IR_ID_EXE2), .X(X_ID_EXE2), .Y(Y_ID_EXE2), // pipeline in
.PC_out(PC_EXE_MEM1), .IR_out(IR_EXE_MEM1), .Z(Z_EXE_MEM1), .Addr(Addr_EXE_MEM1), // pipeline out
.IsBranch(IsBranch), .BranchAddr(BranchAddr));
EXE_MEM EXE_MEM(.clk(clk), .PC_in(PC_EXE_MEM1), .IR_in(IR_EXE_MEM1), .Z_in(Z_EXE_MEM1), .Addr_in(Addr_EXE_MEM1), // pipeline in
.PC_out(PC_EXE_MEM2), .IR_out(IR_EXE_MEM2), .Z_out(Z_EXE_MEM2), .Addr_out(Addr_EXE_MEM2)); // pipeline in
// wires for MEM to MEM-WB
wire [`WIDTH - 3:0] PC_MEM_WB1;
wire [`WIDTH - 1:0] IR_MEM_WB1;
wire [`WIDTH - 1:0] Z_MEM_WB1;
// wires for MEM to MEM-WB
wire [`WIDTH - 3:0] PC_MEM_WB2;
wire [`WIDTH - 1:0] IR_MEM_WB2;
wire [`WIDTH - 1:0] Z_MEM_WB2;
MEM MEM(.clk(clk), .rst_n(rst_n), .PC_in(PC_EXE_MEM2), .IR_in(IR_EXE_MEM2), .Z_in(Z_EXE_MEM2), .Addr(Addr_EXE_MEM2), // pipeline in
.PC_out(PC_MEM_WB1), .IR_out(IR_MEM_WB1), .Z_out(Z_MEM_WB1) // pipeline out
`ifdef TRACE_MEM
,.Print(Print)
`endif
);
MEM_WB MEM_WB(.clk(clk), .PC_in(PC_MEM_WB1), .IR_in(IR_MEM_WB1), .Z_in(Z_MEM_WB1), // pipeline in
.PC_out(PC_MEM_WB2), .IR_out(IR_MEM_WB2), .Z_out(Z_MEM_WB2));
wire halt_out;
`ifdef TRACE_PIPELINE
wire [`WIDTH - 3:0] PC_WB_OUT1;
wire [`WIDTH - 1:0] IR_WB_OUT1;
wire [`WIDTH - 3:0] PC_WB_OUT2;
wire [`WIDTH - 1:0] IR_WB_OUT2;
WB_out WB_out(.clk(clk), .PC_in(PC_WB_OUT1), .IR_in(IR_WB_OUT1));
`endif
WB WB(.clk(clk), .PC_in(PC_MEM_WB2), .IR_in(IR_MEM_WB2), .Z_in(Z_MEM_WB2), // pipeline in
.Addr(Wt_addr), .Data(Wt_data), .wr_en(Wt_en), .w_mode(w_mode), // register
.Halt(halt_out)
`ifdef TRACE_PIPELINE
,.IR_out(IR_WB_OUT1), .PC_out(PC_WB_OUT1)
`endif
);
always @(halt_out) begin
halt = halt_out;
end
`ifdef TRACE_PIPELINE
always @(posedge clk) begin
/*$display($time, " IF IR=%h, PC=%h", IR_IF_ID1, PC_IF_ID1);
$display($time, " ID IR=%h, PC=%h", IR_ID_EXE1, PC_ID_EXE1);
$display($time, " EXE IR=%h, PC=%h", IR_EXE_MEM1, PC_EXE_MEM1);
$display($time, " MEM IR=%h, PC=%h", IR_MEM_WB1, PC_MEM_WB1);*/
$display($time, " %h \t %h \t %h \t %h \t %h", IR_IF_ID1, IR_ID_EXE1, IR_EXE_MEM1, IR_MEM_WB1, IR_WB_OUT1);
end
`endif
endmodule |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; const int mod = 1e9 + 7; const int inf = 0x3f3f3f3f; int a1[maxn], a2[maxn]; int main() { ios::sync_with_stdio(false); cin.tie(0); long long n, k; cin >> n >> k; long long ans = (n + 1) * n / 2; for (int i = 1; i <= n; i++) a1[i] = i; for (int i = 1; i <= n; i++) a2[i] = i; if (ans > k) { cout << -1 << n ; return 0; } long long up = n / 2; long long now = n - 1; for (int i = 1; i <= up; i++) { if (ans + now <= k) { ans += now; swap(a2[i], a2[i + now]); } else { swap(a2[i], a2[i + k - ans]); ans = k; break; } now -= 2; } cout << ans << n ; for (int i = 1; i <= n; i++) cout << a1[i] << (i == n ? n : ); for (int i = 1; i <= n; i++) cout << a2[i] << (i == n ? n : ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long n, long long m) { return m == 0 ? n : gcd(m, n % m); } long long lcm(long long n, long long m) { return (m * n) / gcd(n, m); } long long dx[] = {1, 0}; long long dy[] = {0, 1}; const long long inf = 1e9 + 10; const long long INF = 1e18; long long const N = 2e5 + 10; long long const M = 5100; double const PI = acos(-1); long long const MOD = 998244353; long long Check(long long n, long long pos) { return n & (1 << pos); } long long Set(long long n, long long pos) { return n |= (1 << pos); } long long n, m; vector<pair<long long, long long> > store; vector<long long> k; long long visit[N]; bool check(long long now) { memset(visit, 0, sizeof(visit)); pair<long long, long long> pt = {now, n}; auto it = upper_bound((store.begin()), (store.end()), pt); it--; long long pos = it - store.begin(); vector<pair<long long, long long> > apes; for (long long i = pos; i >= 0; i--) { long long day = store[i].first; long long type = store[i].second; if (visit[type] == 0) { apes.push_back({day, type}); visit[type] = 1; } } reverse((apes.begin()), (apes.end())); long long taka = 0; long long extra = 0; long long lastDay = 0; for (long long i = 0; i < (long long)apes.size(); i++) { long long day = apes[i].first; lastDay = day; long long type = apes[i].second; if (i == 0) taka += day; else taka += day - apes[i - 1].first; if (k[type] <= taka) taka -= k[type]; else { extra += k[type] - taka; taka = 0; } } taka += now - lastDay; for (long long i = 0; i < n; i++) { if (visit[i] == 0) extra += k[i]; } extra <<= 1; if (taka >= extra) return true; else return false; } int32_t main() { cin >> n >> m; k.resize(n); for (long long i = 0; i < n; i++) { cin >> k[i]; } for (long long i = 0; i < m; i++) { long long day, type; cin >> day >> type; type--; store.push_back({day, type}); } sort((store.begin()), (store.end())); long long res = 1; long long left = 1, right = 1e11; while (left <= right) { long long mid = (left + right) >> 1; if (check(mid)) { res = mid; right = mid - 1; } else { left = mid + 1; } } cout << res << n ; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e5 + 10; const long long mod = 1e9 + 7; struct node { int s, e, next; } edge[maxn]; int head[maxn], len; void add(int s, int e) { edge[len].e = e; edge[len].next = head[s]; head[s] = len++; } void init() { memset(head, -1, sizeof(head)); len = 0; } double dp[maxn]; void dfs(int x, int fa) { dp[x] = 0; int ans = 0; for (int i = head[x]; i != -1; i = edge[i].next) { int y = edge[i].e; if (y == fa) continue; dfs(y, x); dp[x] += dp[y]; ans++; } if (ans == 0) dp[x] = 0; else dp[x] = dp[x] / ans + 1; } int main() { int n; while (scanf( %d , &n) != EOF) { init(); int x, y; for (int i = 1; i < n; i++) { scanf( %d%d , &x, &y); add(x, y); add(y, x); } dfs(1, -1); printf( %.8f n , dp[1]); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__TAPVGND_BEHAVIORAL_PP_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tapvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__INV_BEHAVIORAL_V
`define SKY130_FD_SC_HS__INV_BEHAVIORAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__inv (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__INV_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int n, p; int sum, mx; vector<int> ans; int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (int i = (1); i <= (n); i++) { if (i == 1) { cin >> p; ans.push_back(1); sum += p; mx += p; } else { int x; cin >> x; mx += x; if (x <= p / 2) { ans.push_back(i); sum += x; } } } if (sum <= mx / 2) cout << 0; else { cout << (int)ans.size() << n ; for (int x : ans) cout << x << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; using LL = long long; int main() { cin.tie(nullptr)->sync_with_stdio(false); int T; vector<int> f(3e5 + 5); f[0] = 0; for (int i = 1; i < 3e5 + 5; i++) f[i] = f[i - 1] ^ i; for (cin >> T; T; T--) { int a, b; cin >> a >> b; int ans = a; if (f[a - 1] == 0) { if (f[a - 1] == b) ans = ans; else if (a == b) ans += 2; else ans++; } else { if (f[a - 1] == b) ans = ans; else if ((f[a - 1] ^ b) != a) ans++; else ans += 2; } cout << ans << n ; } return 0; } |
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
compareRecFN#(parameter expWidth = 3, parameter sigWidth = 3) (
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
input signaling,
output lt,
output eq,
output gt,
output unordered,
output [4:0] exceptionFlags
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaNA, isInfA, isZeroA, signA;
wire signed [(expWidth + 1):0] sExpA;
wire [sigWidth:0] sigA;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_a(a, isNaNA, isInfA, isZeroA, signA, sExpA, sigA);
wire isSigNaNA;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA);
wire isNaNB, isInfB, isZeroB, signB;
wire signed [(expWidth + 1):0] sExpB;
wire [sigWidth:0] sigB;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_b(b, isNaNB, isInfB, isZeroB, signB, sExpB, sigB);
wire isSigNaNB;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire ordered = !isNaNA && !isNaNB;
wire bothInfs = isInfA && isInfB;
wire bothZeros = isZeroA && isZeroB;
wire eqExps = (sExpA == sExpB);
wire common_ltMags = (sExpA < sExpB) || (eqExps && (sigA < sigB));
wire common_eqMags = eqExps && (sigA == sigB);
wire ordered_lt =
!bothZeros
&& ((signA && !signB)
|| (!bothInfs
&& ((signA && !common_ltMags && !common_eqMags)
|| (!signB && common_ltMags))));
wire ordered_eq =
bothZeros || ((signA == signB) && (bothInfs || common_eqMags));
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire invalid = isSigNaNA || isSigNaNB || (signaling && !ordered);
assign lt = ordered && ordered_lt;
assign eq = ordered && ordered_eq;
assign gt = ordered && !ordered_lt && !ordered_eq;
assign unordered = !ordered;
assign exceptionFlags = {invalid, 4'b0};
endmodule
|
#include <bits/stdc++.h> using namespace std; ifstream F( p.in ); const int M = 1000000007; const int K = 110; const int N = 100100; int dp[K][N], b[N], c[N][K]; int n, m; void add(int &x, int y) { x = ((x + y) % M + M) % M; } int main() { ios::sync_with_stdio(0); for (int n = 0; n < N; ++n) { c[n][0] = 1; for (int k = 1; k <= min(n, K - 1); ++k) c[n][k] = (c[n - 1][k - 1] + c[n - 1][k]) % M; } cin >> n >> m; for (int i = 1; i <= n; ++i) cin >> b[i]; for (int tt = 1, l, r, k; tt <= m; ++tt) { cin >> l >> r >> k; add(dp[k][l], 1); for (int i = 0; i <= k; ++i) add(dp[i][r + i + 1], -c[r - l + k + 1][k - i]); } for (int k = 100; k >= 0; --k) for (int i = 1; i <= n; ++i) { if (k > 0) add(dp[k - 1][i], dp[k][i]); add(dp[k][i + 1], dp[k][i]); } for (int i = 1; i <= n; ++i) cout << (dp[0][i] + b[i]) % M << ; cout << n ; } |
`timescale 1ns/1ns
module udp_rx_joint_cmd
(input c,
input [7:0] rxd,
input rxdv,
output [7:0] mode,
output [31:0] tgt_0,
output [31:0] tgt_1,
output [31:0] tgt_2,
output [31:0] control_id,
output cmd_valid);
// by the time the data stream gets here, it is already known-valid.
// register it again to help timing
wire [7:0] rxd_i;
d1 #(8) rxd_d1_r(.c(c), .d(rxd), .q(rxd_i));
wire rxdv_i;
d1 rxdv_d1_r(.c(c), .d(rxdv), .q(rxdv_i));
wire rxe;
d1 rxe_r(.c(c), .d(rxdv_i & ~rxdv), .q(rxe));
wire [11:0] cnt;
r #(12) cnt_r(.c(c), .rst(~rxdv_i), .en(1'b1), .d(cnt + 1'b1), .q(cnt));
wire [7:0] reg_cmd;
r #(8) reg_cmd_r(.c(c), .rst(~rxdv_i), .en(cnt == 12'd0),
.d(rxd_i), .q(reg_cmd));
wire [7:0] reg_subcmd;
r #(8) reg_subcmd_r(.c(c), .rst(~rxdv_i), .en(cnt == 12'd1),
.d(rxd_i), .q(reg_subcmd));
wire rx_valid = (reg_cmd == 8'h4) & (reg_subcmd == 8'h0) & (cnt == 11'd19);
wire [31:0] rx_shift;
r #(32) rx_shift_r
(.c(c), .rst(1'b0), .en(1'b1),
.d({rx_shift[23:0], rxd}), .q(rx_shift));
wire [7:0] mode;
r #(8) mode_r(.c(c), .rst(1'b0), .en(cnt == 11'd2), .d(rxd), .q(mode));
r #(32) tgt_0_r(.c(c), .rst(1'b0), .en(cnt == 11'd07), .d(rx_shift), .q(tgt_0));
r #(32) tgt_1_r(.c(c), .rst(1'b0), .en(cnt == 11'd11), .d(rx_shift), .q(tgt_1));
r #(32) tgt_2_r(.c(c), .rst(1'b0), .en(cnt == 11'd15), .d(rx_shift), .q(tgt_2));
r #(32) control_id_r(.c(c), .rst(1'b0), .en(cnt == 11'd19),
.d(rx_shift), .q(control_id));
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
// $Revision: #8 $
// $Date: 2009/02/18 $
// $Author: pscheidt $
//-----------------------------------------------------------------------------
//
// File: altera_std_synchronizer_nocut.v
//
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
// as altera_std_synchronizer.v, except that the embedded false
// path constraint is removed in this module. If you use this
// module, you will have to apply the appropriate timing
// constraints.
//
// We expect to make this a standard Quartus atom eventually.
//
// Composed of two or more flip flops connected in series.
// Random metastable condition is simulated when the
// __ALTERA_STD__METASTABLE_SIM macro is defined.
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
// on the Verilog simulator compiler command line to
// enable this mode. In addition, define the macro
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
// with every metastable event generated in the synchronizer.
//
// Copyright (C) Altera Corporation 2009, All Rights Reserved
//-----------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_std_synchronizer_nocut (
clk,
reset_n,
din,
dout
);
parameter depth = 3; // This value must be >= 2 !
input clk;
input reset_n;
input din;
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip-flops with synchronizer flip-flops.
// QuartusII TimeQuest directives:
// 1. Identify all flip-flops in this module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name SYNCHRONIZER_IDENTIFICATION FORCED; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name ADV_NETLIST_OPT_ALLOWED NEVER_ALLOW; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= 1'b0;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string cad; int cnt = 0, ans = 0; cin >> cnt >> cad; cnt = 0; for (int i = 0; i < cad.size(); i++) { if (cad[i] == x ) { cnt++; } else { ans += max(0, cnt - 2); cnt = 0; } } ans += max(0, cnt - 2); cout << ans; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const double eps = 1e-6; const int inf = 1e9; const long long llf = 1e18; const int mod = 1e9 + 7; const int maxn = 1e5 + 10; char s[110]; int f[310]; int main() { int tc; cin >> tc; while (tc--) { cin >> s + 1; int n = strlen(s + 1); sort(s + 1, s + n + 1); string s1 = , s2 = ; for (int i = 1; i <= n; i++) { f[s[i]]++; } for (int i = a ; i <= z ; i++) { if (i & 1) { while (f[i]) { s1 += i; f[i]--; } } else { while (f[i]) { s2 += i; f[i]--; } } } string t = s1 + s2; int flag = 1; for (int i = 1; i < t.size(); i++) { if (abs(t[i] - t[i - 1]) == 1) { flag = 0; break; } } if (flag) { cout << t << endl; continue; } t = s2 + s1; flag = 1; for (int i = 1; i < t.size(); i++) { if (abs(t[i] - t[i - 1]) == 1) { flag = 0; break; } } if (flag) { cout << t << endl; } else { cout << No answer << endl; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_TB_V
`define SKY130_FD_SC_MS__OR4B_TB_V
/**
* or4b: 4-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or4b.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D_N = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D_N = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D_N = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D_N = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D_N = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ms__or4b dut (.A(A), .B(B), .C(C), .D_N(D_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_TB_V
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always reg_lvalue <= @ event_identifier boolean_expression
// D: There is a dependency here between this and event keyword and ->
module main ;
reg [3:0] value1 ;
event event_ident ;
initial
begin
# 5 -> event_ident ;
end
initial
begin
if(value1 !== 4'bxxxx)
$display("FAILED - always reg_lvalue <= @ event_identifier boolean_expression\n");
#10 ;
if(value1 != 4'b1)
$display("FAILED - always reg_lvalue <= @ event_identifier boolean_expression\n");
else
begin
$display("PASSED\n");
$finish ;
end
end
always value1 <= @ event_ident 1'b1 && 1'b1 ;
endmodule
|
#include <bits/stdc++.h> using namespace std; double mar[100000]; int main() { double ml, rl; cin >> ml >> rl; double m = ml, r = rl; double save = 0; if (ml >= 3) save += 2 * m * (m - 3) + 2 * (m - 2) + 6; else if (ml == 2) save += 2; save *= (sqrt(2) - 2); double ans = m * (m + 1) + m * (m + 1) * (2 * m + 1) / 3 - 2 * (m); ans += save; ans *= r; ans /= (m * m); printf( %.10f n , ans); return 0; } |
#include <bits/stdc++.h> template <typename T> inline T max(T a, T b) { return a > b ? a : b; } template <typename T> inline T min(T a, T b) { return a < b ? a : b; } template <typename T> inline T abs(T a) { return a > 0 ? a : -a; } template <typename T> inline void repr(T &a, T b) { if (a < b) a = b; } template <typename T> inline void repl(T &a, T b) { if (a > b) a = b; } int n, x, y, a[3001], f[3001][3001], fa[3001][3001][2], a1[3000], a2[3000], m1, m2; struct B { int v, id; bool operator<(const B &x) const { return v > x.v; } } b[3001]; int main() { scanf( %d%d%d , &n, &x, &y); for (int i = 1; i <= n; i++) scanf( %d , a + i), f[0][0] += a[i]; for (int i = 1; i <= n; i++) scanf( %d , &b[i].v), b[i].v -= a[i], b[i].id = i; std::sort(b + 1, b + n + 1); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { if (f[i - 1][j] - a[b[i].id] > f[i][j]) f[i][j] = f[i - 1][j] - a[b[i].id], fa[i][j][0] = i - 1, fa[i][j][1] = j; if (j <= y) { if (f[i - 1][j - 1] + b[i].v > f[i][j]) f[i][j] = f[i - 1][j - 1] + b[i].v, fa[i][j][0] = i - 1, fa[i][j][1] = j - 1; } else { if (f[i - 1][j - 1] > f[i][j]) f[i][j] = f[i - 1][j - 1], fa[i][j][0] = i - 1, fa[i][j][1] = j - 1; } } f[i][0] = f[i - 1][0] - a[b[i].id]; } printf( %d n , f[n][x + y]); for (int i = n, j = x + y; j;) { while (fa[i][j][1] == j) { i = fa[i][j][0]; } if (j <= y) a2[m2++] = b[i].id; else a1[m1++] = b[i].id; i = fa[i][j][0]; j--; } std::sort(a1, a1 + m1); std::sort(a2, a2 + m2); for (int i = 0; i < m1; i++) printf( %d , a1[i]); printf( n ); for (int i = 0; i < m2; i++) printf( %d , a2[i]); printf( n ); } |
#include <bits/stdc++.h> using namespace std; const int LEN = (int)1e5; int n; long long a[LEN]; vector<int> g[60]; int bfs(int r, int t) { queue<int> q; static int d[LEN]; memset(d, 0, sizeof d); q.push(r); d[r] = 1; while (!q.empty()) { int u = q.front(); q.pop(); for (int j = 0; (1ll << j) <= a[u]; j++) if ((1ll << j) & a[u]) for (auto v : g[j]) if (!d[v] && !(v == t && u == r)) { d[v] = d[u] + 1; if (v == t) return d[v] > 2 ? d[v] : INT_MAX; q.push(v); } } return INT_MAX; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; for (int j = 0; (1ll << j) <= a[i]; j++) if ((1ll << j) & a[i]) g[j].push_back(i); ; ; } for (int i = 0; i < 60; i++) if ((int)(g[i]).size() >= 3) { cout << 3; return 0; } int ans = INT_MAX; for (int i = 0; i < 60; i++) if ((int)(g[i]).size() > 1) { a[g[i][0]] &= ~(1ll << i); ans = min(ans, bfs(g[i][0], g[i][1])); a[g[i][0]] |= 1ll << i; } cout << (ans < INT_MAX ? ans : -1); return 0; } |
#include <bits/stdc++.h> using namespace std; signed main() { std::ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); ; long long CASE = 1; while (CASE--) { long long n; cin >> n; vector<std::pair<long long, long long> > c; for (long long i = 0; i < n; ++i) { long long x, y; cin >> x >> y; c.push_back({x, y}); } double ans = 0; for (long long i = 0; i < n; ++i) { for (long long j = i + 1; j < n; ++j) { double mx = INT_MIN, mn = INT_MAX; for (long long k = 0; k < n; ++k) { if (i == k || j == k) continue; double area = (c[k].first * (c[i].second - c[j].second) + c[i].first * (c[j].second - c[k].second) + c[j].first * (c[k].second - c[i].second)) * 0.5; mx = max(mx, area); mn = min(mn, area); } ans = max(ans, mx - mn); } } cout << setprecision(10) << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; string s; cin >> s; stack<char> stack; int left = 0, right = 0, size = 0; for (int i = 0; i < s.length(); i++) { stack.push(s[i]); if (s[i] == ( ) { left++; continue; } if (s[i] == ) && left != 0) { left--; stack.pop(); continue; } if (s[i] == ) && left == 0) { right++; continue; } } cout << left << n ; } int main() { int t; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; int lens = s.length(); s = + s; s = s + ; int minn = -1; int a[10000] = {0}; a[0] = 0; int p = 1; for (int i = 0; i <= lens + 1; i++) { if (s[i] == A || s[i] == E || s[i] == I || s[i] == O || s[i] == U || s[i] == Y ) { a[p++] = i; } } a[p++] = lens + 1; for (int i = 0; i < p; i++) { a[i] = a[i + 1] - a[i]; minn = max(a[i], minn); } cout << minn << endl; } |
#include <bits/stdc++.h> using namespace std; const long long INF = (long long)1e18; const int mod = (int)1e9 + 7; const int MAXN = (int)4e5 + 5; long long n, ans[MAXN], ext[MAXN]; vector<pair<int, pair<int, int>>> sorg[MAXN]; vector<pair<int, int>> adj[MAXN]; int a[MAXN]; const int L = 20; int geri[MAXN]; int par[MAXN][L], dep[MAXN]; int tin[MAXN], tout[MAXN]; int Gt = 1; void dfs0(int v, int pr) { tin[v] = Gt++; if (pr == -1) { dep[v] = 0; par[v][0] = v; } else { dep[v] = dep[pr] + 1; par[v][0] = pr; } for (int j = 1; j < L; j++) par[v][j] = par[par[v][j - 1]][j - 1]; ext[v] = a[v]; for (pair<int, int> j : adj[v]) { if (j.first == pr) continue; geri[j.first] = j.second; dfs0(j.first, v); ext[v] += max(0LL, -2LL * j.second + ext[j.first]); } tout[v] = Gt - 1; } int gtp(int v, int dd) { for (int i = L - 1; i >= 0; i--) { if ((1 << i) <= dd) { v = par[v][i]; dd -= (1 << i); } } return v; } int find_lca(int a, int b) { if (dep[a] > dep[b]) swap(a, b); for (int i = L - 1; i >= 0; i--) { if (dep[a] + (1 << i) <= dep[b]) b = par[b][i]; } if (a == b) return a; for (int i = L - 1; i >= 0; i--) { if (par[a][i] != par[b][i]) { a = par[a][i]; b = par[b][i]; } } return par[a][0]; } long long t[MAXN]; void upd(int l, int r, long long val) { r++; for (; l < MAXN; l += (l & -l)) t[l] += val; for (; r < MAXN; r += (r & -r)) t[r] -= val; } long long gt(int v) { long long res = 0; for (; v; v -= (v & -v)) res += t[v]; return res; } void dfs1(int v, int pr, long long sum) { upd(tin[v], tin[v], ext[v]); long long nS = sum + a[v]; for (pair<int, int> u : adj[v]) { if (u.first == pr) continue; nS += max(0LL, -2 * u.second + ext[u.first]); } for (pair<int, int> u : adj[v]) { if (u.first == pr) continue; nS -= max(0LL, -2 * u.second + ext[u.first]); dfs1(u.first, v, max(0LL, nS - 2 * u.second)); nS += max(0LL, -2 * u.second + ext[u.first]); } unordered_map<int, long long> mp; for (pair<int, int> u : adj[v]) { if (u.first == pr) continue; long long dg = max(0LL, -2 * u.second + ext[u.first]); mp[u.first] = dg; } for (auto u : sorg[v]) { int a = u.second.first, b = u.second.second; if (b == v) swap(a, b); if (a == v && b == v) { ans[u.first] = sum + ext[v]; } else if (a == v) { int r1 = gtp(b, dep[b] - dep[v] - 1); ans[u.first] = sum + ext[v] + gt(tin[b]) - mp[r1] - geri[r1]; } else { int r1 = gtp(b, dep[b] - dep[v] - 1), r2 = gtp(a, dep[a] - dep[v] - 1); ans[u.first] = sum + ext[v] + gt(tin[b]) + gt(tin[a]) - mp[r1] - mp[r2] - geri[r1] - geri[r2]; } } for (pair<int, int> u : adj[v]) { if (u.first == pr) continue; upd(tin[u.first], tout[u.first], ext[v] - mp[u.first] - u.second); } } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int q; cin >> n >> q; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 0; i < n - 1; i++) { int u, v, w; cin >> u >> v >> w; adj[u].push_back({v, w}); adj[v].push_back({u, w}); } dfs0(1, -1); for (int i = 0; i < q; i++) { int u, v; cin >> u >> v; sorg[find_lca(u, v)].push_back({i, {u, v}}); } dfs1(1, -1, 0); for (int i = 0; i < q; i++) cout << ans[i] << n ; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// A test case for struct signal bit selection.
//
// This test is to check that bit selection of multi-dimensional signal inside
// of a packed struct works. Currently +: and -: blow up with packed structs.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty, 2013 by Jie Xu.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef struct packed {
logic [15:0] channel;
logic [15:0] others;
} buss_t;
buss_t b;
reg [7:0] a;
reg [7:0] c;
reg [7:0] d;
union packed {
logic [31:0] [7:0] idx;
struct packed {
logic [15:0] z, y, x;
logic [25:0] [7:0] r;
} nam;
} gpr;
reg [14:0] gpr_a;
initial begin
b = {16'h8765,16'h4321};
a = b[19:12]; // This works
c = b[8+:8]; // This fails
d = b[11-:8]; // This fails
`checkh(a, 8'h54);
`checkh(c, 8'h43);
`checkh(d, 8'h32);
gpr = 256'h12346789_abcdef12_3456789a_bcdef123_456789ab_cdef1234_56789abc_def12345;
`checkh (gpr[255:255-14], 15'h091a);
gpr_a = gpr.nam.z[15:1];
`checkh (gpr_a, 15'h091a);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[5], r[5] = {0, 2, 3, 4, 1}; int main() { for (int i = 1; i <= 4; i++) scanf( %d , &a[i]); for (; a[1] != 1 || a[2] != 1 || a[3] != 1 || a[4] != 1;) { int x = rand() % 4 + 1; if (a[x] == 1 && a[r[x]] == 1) continue; if ((a[x] % 2 == 0) && (a[r[x]] % 2 == 0)) printf( /%d n , x), a[x] /= 2, a[r[x]] /= 2; else if (a[x] % 2 == 1) printf( +%d n , x), a[x]++, a[r[x]]++; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long a[3], d, ans = 0; cin >> a[0] >> a[1] >> a[2] >> d; sort(a, a + 3); if (a[1] - a[0] < d) ans += (d - (a[1] - a[0])); if (a[2] - a[1] < d) ans += (d - (a[2] - a[1])); cout << ans << n ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S50KAPWR_SYMBOL_V
`define SKY130_FD_SC_LP__DLYBUF4S50KAPWR_SYMBOL_V
/**
* dlybuf4s50kapwr: Delay Buffer 4-stage 0.50um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s50kapwr (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S50KAPWR_SYMBOL_V
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Channel Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module lab3_master_0_p2b_adapter (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
output reg [ 7: 0] out_channel
);
reg in_channel = 0;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_channel = 0;
out_channel = in_channel;
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:64000000 ) using namespace std; const int infi = 1e9 + 7; const long long infl = 1e18 + 7; int ar[101]; bitset<101> dp0[10500]; bitset<101> dp[10500]; bitset<101> ndp[10500]; int main() { cin.sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (int i = 0; i < (n); ++i) cin >> ar[i]; vector<pair<int, int> > tmp; sort(ar, ar + n); int lst = ar[0]; int sum = ar[0]; int cnt = 1; for (int i = 1; i < n; ++i) { sum += ar[i]; if (lst == ar[i]) ++cnt; else { tmp.emplace_back(lst, cnt); lst = ar[i]; cnt = 1; } } tmp.emplace_back(lst, cnt); if (tmp.size() <= 2) { cout << n; return 0; } for (auto cur : tmp) { for (int cnt = 1; cnt <= cur.second; ++cnt) { int second = cnt * cur.first; for (int w = 0; w < (10500); ++w) { ndp[w + second] |= dp0[w] << cnt; ndp[w + second] |= dp[w] << cnt; } } for (int cnt = 1; cnt <= cur.second; ++cnt) { dp0[cnt * cur.first][cnt] = 1; } for (int i = 0; i < (10500); ++i) dp[i] |= ndp[i]; } int ans = 0; for (auto cur : tmp) { for (int cnt = 1; cnt <= cur.second; ++cnt) { int second = cnt * cur.first; if (dp[second][cnt]) continue; ans = max(ans, cnt); if (tmp.size() == 2 && cnt == cur.second) ans = n; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k; char s[1000111]; pair<int, int> q[33]; int a[33]; int main() { scanf( %d%d n , &n, &k); gets(s); int l = strlen(s); for (int i = 0; i < k; i++) q[i].second = i; long long sum = 1; for (int i = 0; i < l; i++) { int u = s[i] - a ; q[u].first = i + 1; long long t = (sum - a[u] + 1000000007) % 1000000007; sum = (sum + t) % 1000000007; a[u] = (a[u] + t) % 1000000007; } sort(q, q + k); for (int i = 0; i < n; i++) { int u = q[i % k].second; long long t = (sum - a[u] + 1000000007) % 1000000007; sum = (sum + t) % 1000000007; a[u] = (a[u] + t) % 1000000007; } cout << sum << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); unordered_map<int, int> ma; int x, y, z, l; cin >> x >> y; vector<int> vec(x); vector<int> vec1(x); for (int i = 0; i < x; i++) cin >> vec[i]; vec1 = vec; for (int i = 0; i < y; i++) { cin >> z >> l; if (vec[z - 1] > vec[l - 1]) ma[z - 1]++; else if (vec[l - 1] > vec[z - 1]) ma[l - 1]++; } sort(vec1.begin(), vec1.end()); for (int i = 0; i < x; i++) { int r = lower_bound(vec1.begin(), vec1.end(), vec[i]) - vec1.begin(); cout << r - ma[i] << ; } } |
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build Wed Nov 18 09:44:32 MST 2015
// Date : Sat Aug 27 18:41:24 2016
// Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
// Command : write_verilog -force -mode synth_stub
// /home/kobayashi/PCIe_test/branches/IEICE/data_compression/8-way_2-tree/src/ip_pcie/PCIeGen2x8If128_stub.v
// Design : PCIeGen2x8If128
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "PCIeGen2x8If128_pcie2_top,Vivado 2015.4" *)
module PCIeGen2x8If128(pci_exp_txp, pci_exp_txn, pci_exp_rxp, pci_exp_rxn, user_clk_out, user_reset_out, user_lnk_up, user_app_rdy, tx_buf_av, tx_cfg_req, tx_err_drop, s_axis_tx_tready, s_axis_tx_tdata, s_axis_tx_tkeep, s_axis_tx_tlast, s_axis_tx_tvalid, s_axis_tx_tuser, tx_cfg_gnt, m_axis_rx_tdata, m_axis_rx_tkeep, m_axis_rx_tlast, m_axis_rx_tvalid, m_axis_rx_tready, m_axis_rx_tuser, rx_np_ok, rx_np_req, fc_cpld, fc_cplh, fc_npd, fc_nph, fc_pd, fc_ph, fc_sel, cfg_status, cfg_command, cfg_dstatus, cfg_dcommand, cfg_lstatus, cfg_lcommand, cfg_dcommand2, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_powerstate, cfg_pmcsr_pme_status, cfg_received_func_lvl_rst, cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_dsn, cfg_interrupt, cfg_interrupt_rdy, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_do, cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum, cfg_to_turnoff, cfg_turnoff_ok, cfg_bus_number, cfg_device_number, cfg_function_number, cfg_pm_wake, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number, cfg_bridge_serr_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_pme_int_en, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_fatal_err_received, cfg_vc_tcvc_map, sys_clk, sys_rst_n)
/* synthesis syn_black_box black_box_pad_pin="pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n" */;
output [7:0]pci_exp_txp;
output [7:0]pci_exp_txn;
input [7:0]pci_exp_rxp;
input [7:0]pci_exp_rxn;
output user_clk_out;
output user_reset_out;
output user_lnk_up;
output user_app_rdy;
output [5:0]tx_buf_av;
output tx_cfg_req;
output tx_err_drop;
output s_axis_tx_tready;
input [127:0]s_axis_tx_tdata;
input [15:0]s_axis_tx_tkeep;
input s_axis_tx_tlast;
input s_axis_tx_tvalid;
input [3:0]s_axis_tx_tuser;
input tx_cfg_gnt;
output [127:0]m_axis_rx_tdata;
output [15:0]m_axis_rx_tkeep;
output m_axis_rx_tlast;
output m_axis_rx_tvalid;
input m_axis_rx_tready;
output [21:0]m_axis_rx_tuser;
input rx_np_ok;
input rx_np_req;
output [11:0]fc_cpld;
output [7:0]fc_cplh;
output [11:0]fc_npd;
output [7:0]fc_nph;
output [11:0]fc_pd;
output [7:0]fc_ph;
input [2:0]fc_sel;
output [15:0]cfg_status;
output [15:0]cfg_command;
output [15:0]cfg_dstatus;
output [15:0]cfg_dcommand;
output [15:0]cfg_lstatus;
output [15:0]cfg_lcommand;
output [15:0]cfg_dcommand2;
output [2:0]cfg_pcie_link_state;
output cfg_pmcsr_pme_en;
output [1:0]cfg_pmcsr_powerstate;
output cfg_pmcsr_pme_status;
output cfg_received_func_lvl_rst;
input cfg_trn_pending;
input cfg_pm_halt_aspm_l0s;
input cfg_pm_halt_aspm_l1;
input cfg_pm_force_state_en;
input [1:0]cfg_pm_force_state;
input [63:0]cfg_dsn;
input cfg_interrupt;
output cfg_interrupt_rdy;
input cfg_interrupt_assert;
input [7:0]cfg_interrupt_di;
output [7:0]cfg_interrupt_do;
output [2:0]cfg_interrupt_mmenable;
output cfg_interrupt_msienable;
output cfg_interrupt_msixenable;
output cfg_interrupt_msixfm;
input cfg_interrupt_stat;
input [4:0]cfg_pciecap_interrupt_msgnum;
output cfg_to_turnoff;
input cfg_turnoff_ok;
output [7:0]cfg_bus_number;
output [4:0]cfg_device_number;
output [2:0]cfg_function_number;
input cfg_pm_wake;
input cfg_pm_send_pme_to;
input [7:0]cfg_ds_bus_number;
input [4:0]cfg_ds_device_number;
input [2:0]cfg_ds_function_number;
output cfg_bridge_serr_en;
output cfg_slot_control_electromech_il_ctl_pulse;
output cfg_root_control_syserr_corr_err_en;
output cfg_root_control_syserr_non_fatal_err_en;
output cfg_root_control_syserr_fatal_err_en;
output cfg_root_control_pme_int_en;
output cfg_aer_rooterr_corr_err_reporting_en;
output cfg_aer_rooterr_non_fatal_err_reporting_en;
output cfg_aer_rooterr_fatal_err_reporting_en;
output cfg_aer_rooterr_corr_err_received;
output cfg_aer_rooterr_non_fatal_err_received;
output cfg_aer_rooterr_fatal_err_received;
output [6:0]cfg_vc_tcvc_map;
input sys_clk;
input sys_rst_n;
endmodule
|
#include <bits/stdc++.h> using namespace std; int solve(string &s) { int len = s.length(); int ret = 0; for (int i = 0; i < len; ++i) { if (s[i] == V && i + 1 < len && s[i + 1] == K ) { ++ret; } } return ret; } int main() { string s; while (cin >> s) { int ans = solve(s); int len = s.length(); char c; for (int i = 0; i < len; ++i) { c = s[i]; if (s[i] == V ) { s[i] = K ; } else { s[i] = V ; } ans = max(ans, solve(s)); s[i] = c; } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long s[100007]; long long l[100007]; int main() { long long n, k, r = 0; cin >> n >> k; map<int, int> m; map<int, int> e[10]; long long ki = 0; for (int i = 0; i < n; i++) { scanf( %I64d , &s[i]); r += s[i] / 10; if (s[i] != 100) { m[10 - (s[i] % 10)]++; } if ((s[i] % 10) == 0) { ki += (10 - s[i] / 10); } if (s[i] / 10 <= 9) { e[s[i] / 10][10 - (s[i] % 10)]++; } } map<int, int>::iterator it; for (it = m.begin(); it != m.end() && k > 0; it++) { long long gap = it->first; if (gap == 10) { break; } long long tot = it->second; if (gap * tot <= k) { if (gap < 10) { k -= gap * tot; r += tot; m[10] += tot; m[gap] = 0; for (int i = 9; i > 0; i--) { e[i][10] += e[i - 1][gap]; ki += (10 - i) * e[i - 1][gap]; } m[10] -= e[9][gap]; } else if (gap == 10) { r += tot; } } else { r += (k / gap); m[10] += (k / gap); k = 0; } } if (it != m.end() && k > 0) { long long gap = it->first; long long tot = it->second; if (gap * ki <= k) { r += ki; } else { r += (k / gap); } } cout << r; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mxN = 1e6 + 5; vector<int> adj[mxN]; int n, m, sz[mxN], dp[mxN], dpb[mxN], mn[mxN]; bool bad[mxN]; int ans = 1e9 + 7, V; void dfs1(int v, int par = -1) { sz[v] += bad[v]; for (auto to : adj[v]) { if (par != to) { dfs1(to, v); sz[v] += sz[to]; if (sz[to]) { dpb[v] += dpb[to] + 2; mn[v] = min(mn[v], (dp[to] + 1) - (dpb[to] + 2)); } } } dp[v] = dpb[v] + mn[v]; } void dfs2(int v, int par = -1) { if (dp[v] < ans) ans = dp[v], V = v; else if (dp[v] == ans) V = min(V, v); multiset<pair<int, int> > mt; for (auto to : adj[v]) { if (sz[to]) mt.insert({min(0, (dp[to] + 1) - (dpb[to] + 2)), to}); } for (auto to : adj[v]) { if (to != par) { int dpB = dp[v], dpbB = dpb[v]; int mnB = mn[to]; int subdpB = dp[to], subdpbB = dpb[to]; dp[v] -= mt.begin()->first; if (sz[to]) mt.erase({min(0, (dp[to] + 1) - (dpb[to] + 2)), to}); if (!mt.empty()) dp[v] += mt.begin()->first; if (sz[to]) { dp[v] -= dpb[to] + 2; dpb[v] -= dpb[to] + 2; } sz[v] -= sz[to]; sz[to] += sz[v]; if (sz[v]) { dpb[to] += dpb[v] + 2; dp[to] += dpb[v] + 2; if (mn[to] > (dp[v] + 1) - (dpb[v] + 2)) { dp[to] -= mn[to]; mn[to] = (dp[v] + 1) - (dpb[v] + 2); dp[to] += mn[to]; } } dfs2(to, v); sz[to] -= sz[v]; sz[v] += sz[to]; dp[v] = dpB, dpb[v] = dpbB; mn[to] = mnB; dp[to] = subdpB, dpb[to] = subdpbB; if (sz[to]) mt.insert({min(0, (dp[to] + 1) - (dpb[to] + 2)), to}); } } } int main() { ios ::sync_with_stdio(false), cin.tie(nullptr); cin >> n >> m; for (int i = 1; i < n; ++i) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } for (int i = 1; i <= m; ++i) { int v; cin >> v; bad[v] = 1; } dfs1(1); dfs2(1); cout << V << n << ans; return 0; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
//
// SDW - Simple parameter declaration
//
// D: Declare a parameter value, then assign it to a variable.
// D: Check the value of the variable.
//
module main();
parameter VAL_1 = 16'h0001;
parameter VAL_2 = 16'h5432;
reg [15:0] test_var;
initial // Excitation block
begin
test_var = VAL_1 ;
#5 ;
test_var = VAL_2 ;
#5 ;
end
initial // Validation block
begin
#1 ;
if(test_var != 16'h0001)
begin
$display("FAILED - param 1st assign didn't work\n");
$finish ;
end
#5 ;
if(test_var != 16'h5432)
begin
$display("FAILED - param 2nd assign didn't work\n");
$finish ;
end
$display("PASSED\n");
$finish ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k, v[105], frec[105]; vector<int> ans; int main() { cin >> n >> k; for (int i = 1; i <= n; i++) cin >> v[i]; for (int i = 1; i <= n; i++) if (!frec[v[i]]) { frec[v[i]] = 1; ans.push_back(i); if (ans.size() == k) break; } if (ans.size() == k) { cout << YES << n ; for (int i = 0; i < ans.size(); i++) cout << ans[i] << ; cout << n ; } else cout << NO << n ; return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.8
//
// Date: $Date: 2007/09/28 12:50:36 $
// Tag: $Name: i+HEAD+134158 $
// File: $RCSfile: standard_cc_module.ejava,v $
// Rev: $Revision: 1.2 $
//
// Company: Xilinx
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// STANDARD CC MODULE
//
//
// Description: This module drives the Aurora module's Clock Compensation
// interface. Clock Compensation sequences are generated according
// to the requirements in the Aurora Protocol specification.
//
// This module supports Aurora Modules with any number of
// 2-byte lanes and no User Flow Control.
//
//
`timescale 1 ns / 10 ps
module aurora_201_STANDARD_CC_MODULE
(
//Clock Compensation Control Interface
WARN_CC,
DO_CC,
//System Interface
DCM_NOT_LOCKED,
USER_CLK,
CHANNEL_UP
);
`define DLY #1
//***********************************Port Declarations*******************************
//Clock Compensation Control Interface
output WARN_CC;
output DO_CC;
//System Interface
input DCM_NOT_LOCKED;
input USER_CLK;
input CHANNEL_UP;
//**************************** External Register Declarations*************************
reg WARN_CC;
reg DO_CC;
//************************** Internal Register Declarations **************************
reg [0:9] prepare_count_r;
reg [0:5] cc_count_r;
reg reset_r;
reg [0:11] count_13d_srl_r;
reg count_13d_flop_r;
reg [0:14] count_16d_srl_r;
reg count_16d_flop_r;
reg [0:22] count_24d_srl_r;
reg count_24d_flop_r;
//*********************************Wire Declarations**********************************
wire start_cc_c;
wire inner_count_done_r;
wire middle_count_done_c;
wire cc_idle_count_done_c;
//*********************************Main Body of Code**********************************
//________________________Clock Correction State Machine__________________________
// The clock correction state machine is a counter with three sections. The first
// section counts out the idle period before a clock correction occurs. The second
// section counts out a period when NFC and UFC operations should not be attempted
// because they will not be completed. The last section counts out the cycles of
// the clock correction sequence.
// The inner count for the CC counter counts to 13. It is implemented using
// an SRL16 and a flop
// The SRL counts 12 bits of the count
always @(posedge USER_CLK)
count_13d_srl_r <= `DLY {count_13d_flop_r, count_13d_srl_r[0:10]};
// The inner count is done when a 1 reaches the end of the SRL
assign inner_count_done_r = count_13d_srl_r[11];
// The flop extends the shift register to 13 bits for counting. It is held at
// zero while channel up is low to clear the register, and is seeded with a
// single 1 when channel up transitions from 0 to 1
always @(posedge USER_CLK)
if(~CHANNEL_UP)
count_13d_flop_r <= `DLY 1'b0;
else if(CHANNEL_UP && reset_r)
count_13d_flop_r <= `DLY 1'b1;
else
count_13d_flop_r <= `DLY inner_count_done_r;
// The middle count for the CC counter counts to 16. Its count increments only
// when the inner count is done. It is implemented using an SRL16 and a flop
// The SRL counts 15 bits of the count. It is enabled only when the inner count
// is done
always @(posedge USER_CLK)
if(inner_count_done_r|| !CHANNEL_UP)
count_16d_srl_r <= `DLY {count_16d_flop_r, count_16d_srl_r[0:13]};
// The middle count is done when a 1 reaches the end of the SRL and the inner
// count finishes
assign middle_count_done_c = inner_count_done_r && count_16d_srl_r[14];
// The flop extends the shift register to 16 bits for counting. It is held at
// zero while channel up is low to clear the register, and is seeded with a
// single 1 when channel up transitions from 0 to 1
always @(posedge USER_CLK)
if(~CHANNEL_UP)
count_16d_flop_r <= `DLY 1'b0;
else if(CHANNEL_UP && reset_r)
count_16d_flop_r <= `DLY 1'b1;
else if(inner_count_done_r)
count_16d_flop_r <= `DLY middle_count_done_c;
// The outer count (aka the cc idle count) is done when it reaches 24. Its count
// increments only when the middle count is done. It is implemented with 2 SRL16s
// and a flop
// The SRL counts 23 bits of the count. It is enabled only when the middle count is
// done
always @(posedge USER_CLK)
if(middle_count_done_c || !CHANNEL_UP)
count_24d_srl_r <= `DLY {count_24d_flop_r, count_24d_srl_r[0:21]};
// The cc idle count is done when a 1 reaches the end of the SRL and the middle count finishes
assign cc_idle_count_done_c = middle_count_done_c & count_24d_srl_r[22];
// The flop extends the shift register to 24 bits for counting. It is held at
// zero while channel up is low to clear the register, and is seeded with a single
// 1 when channel up transitions from 0 to 1
always @(posedge USER_CLK)
if(~CHANNEL_UP)
count_24d_flop_r <= `DLY 1'b0;
else if(CHANNEL_UP && reset_r)
count_24d_flop_r <= `DLY 1'b1;
else if(middle_count_done_c)
count_24d_flop_r <= `DLY cc_idle_count_done_c;
// For simulation, initialize prepare count to all zeros to simulate an SRL16
// after configuration. The circuit will also work is the init value includes
// ones.
initial
prepare_count_r = 10'b0000000000;
// Because UFC and CC sequences are not allowed to preempt one another, there
// there is a warning signal to indicate an impending CC sequence. This signal
// is used to prevent UFC messages from starting.
// For 1 lane, we need an 10-cycle count.
always @(posedge USER_CLK)
prepare_count_r <= `DLY {cc_idle_count_done_c,prepare_count_r[0:8]};
// The state machine stays in the prepare_cc state from when the cc idle
// count finishes, to when the prepare count has finished. While in this
// state, UFC operations cannot start, which prevents them from having to
// be pre-empted by CC sequences.
always @(posedge USER_CLK)
if(!CHANNEL_UP) WARN_CC <= `DLY 1'b0;
else if(cc_idle_count_done_c) WARN_CC <= `DLY 1'b1;
else if(prepare_count_r[9]) WARN_CC <= `DLY 1'b0;
// For simulation, init to zeros, to simulate an SRL after configuration. The circuit
// will also operate if the SRL is not initialized to all zeros
initial
cc_count_r = 6'b000000;
// Track the state of channel up on the previous cycle. We use this signal to determine
// when to seed the shift register counters with ones
always @(posedge USER_CLK)
reset_r <= `DLY !CHANNEL_UP;
//Do a CC after CHANNEL_UP is asserted or CC_warning is complete.
assign start_cc_c = prepare_count_r[9] || (CHANNEL_UP && reset_r);
// This SRL counter keeps track of the number of cycles spent in the CC
// sequence. It starts counting when the prepare_cc state ends, and
// finishes counting after 6 cycles have passed.
always @(posedge USER_CLK)
cc_count_r <= `DLY {(!CHANNEL_UP|prepare_count_r[9]),cc_count_r[0:4]};
// The TX_LL module stays in the do_cc state for 6 cycles. It starts
// when the prepare_cc state ends.
always @(posedge USER_CLK)
if(!CHANNEL_UP) DO_CC <= `DLY 1'b0;
else if(start_cc_c) DO_CC <= `DLY 1'b1;
else if(cc_count_r[5]) DO_CC <= `DLY 1'b0;
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long getint() { long long num = 0, flag = 1; char c; while ((c = getchar()) < 0 || c > 9 ) if (c == - ) flag = -1; while (c >= 0 && c <= 9 ) num = num * 10 + c - 48, c = getchar(); return num * flag; } int n, m, q, R; int fir[600005], nxt[600005], to[600005], cnt; int sz[600005], tp[600005], fa[600005], son[600005], dpt[600005], pos[600005], cur; map<pair<int, int>, int> M; int p[600005], V[600005]; int P_stk[600005], P_Tp; inline int rotate(int x) { x = (x + R) % n; return x ? x : x + n; } inline bool cmp(int x, int y) { return pos[x] < pos[y]; } inline void newnode(int u, int v) { to[++cnt] = v, nxt[cnt] = fir[u], fir[u] = cnt; } inline void dfs1(int u) { sz[u] = 1; pos[u] = ++cur; for (int i = fir[u]; i; i = nxt[i]) if (to[i] != fa[u]) { fa[to[i]] = u, dpt[to[i]] = dpt[u] + 1; dfs1(to[i]), sz[u] += sz[to[i]]; if (sz[to[i]] > sz[son[u]]) son[u] = to[i]; } } inline void dfs2(int u, int ac) { tp[u] = ac; if (son[u]) dfs2(son[u], ac); for (int i = fir[u]; i; i = nxt[i]) if (to[i] != fa[u] && to[i] != son[u]) dfs2(to[i], to[i]); } inline int LCA(int u, int v) { for (; tp[u] != tp[v] && u && v; u = fa[tp[u]]) if (dpt[tp[u]] < dpt[tp[v]]) swap(u, v); if (!u || !v) return 0; return dpt[u] < dpt[v] ? u : v; } struct node { vector<int> G[600005], Id[600005]; int dfn[600005], low[600005], tim, vis[600005], sccno[600005], scccnt; int stk[600005], Tp; inline void tarjan(int u) { dfn[u] = low[u] = ++tim; stk[++Tp] = u; for (int i = 0, v; i < G[u].size(); i++) if (!vis[Id[u][i]]) { vis[Id[u][i]] = 1; if (!dfn[v = G[u][i]]) tarjan(v), low[u] = min(low[u], low[v]); else if (!sccno[v]) low[u] = min(low[u], dfn[v]); } if (dfn[u] == low[u]) { scccnt++; while (1) { sccno[stk[Tp]] = scccnt; if (stk[Tp--] == u) break; } } } inline void init() { for (int i = 1; i <= m; i++) { int u = getint(), v = getint(); G[u].push_back(v), G[v].push_back(u); Id[u].push_back(i), Id[v].push_back(i); } for (int i = 1; i <= n; i++) if (!dfn[i]) tarjan(i); for (int u = 1; u <= n; u++) for (int i = 0; i < G[u].size(); i++) if (sccno[G[u][i]] != sccno[u]) { int x = min(sccno[u], sccno[G[u][i]]), y = max(sccno[u], sccno[G[u][i]]); if (!M[make_pair(x, y)]) newnode(x, y), newnode(y, x), M[make_pair(x, y)] = 1; } } } G, H; int main() { n = getint(), m = getint(), q = getint(); G.init(); for (int i = 1; i <= G.scccnt; i++) if (!sz[i]) dfs1(i), dfs2(i, i); for (int t = 1; t <= q; t++) { int N = getint(), M = getint(), K = 0, tmp = 0; P_Tp = 0; for (int i = 1; i <= N; i++) { int x = G.sccno[rotate(getint())]; p[++K] = x, V[x] = 1; } for (int i = 1; i <= M; i++) { int x = G.sccno[rotate(getint())], y = G.sccno[rotate(getint())]; if (x == y) continue; p[++K] = x, p[++K] = y, tmp++; H.G[x].push_back(y), H.G[y].push_back(x); H.Id[x].push_back(tmp), H.Id[y].push_back(tmp); } sort(p + 1, p + K + 1, cmp), K = unique(p + 1, p + K + 1) - p - 1; for (int i = K - 1; i; i--) { int x = LCA(p[i], p[i + 1]); if (x) p[++K] = x; } sort(p + 1, p + K + 1, cmp), K = unique(p + 1, p + K + 1) - p - 1; for (int i = 1; i <= K; i++) { while (P_Tp && pos[P_stk[P_Tp]] + sz[P_stk[P_Tp]] <= pos[p[i]]) P_Tp--; if (P_Tp) { int x = P_stk[P_Tp], y = p[i]; tmp++; H.G[x].push_back(y), H.G[y].push_back(x); H.Id[x].push_back(tmp), H.Id[y].push_back(tmp); } P_stk[++P_Tp] = p[i]; } for (int i = 1; i <= K; i++) if (!H.dfn[p[i]]) H.tarjan(p[i]); int pp = 0; bool flg = 1; for (int i = 1; i <= K; i++) if (V[p[i]]) { if (!pp) pp = H.sccno[p[i]]; else if (pp != H.sccno[p[i]]) { flg = 0; break; } } for (int i = 1; i <= K; i++) { H.G[p[i]].clear(), H.Id[p[i]].clear(); H.dfn[p[i]] = H.low[p[i]] = H.sccno[p[i]] = V[p[i]] = 0; } for (int i = 1; i <= tmp; i++) H.vis[i] = 0; H.scccnt = H.tim = H.Tp = 0; R = (R + t * flg) % n; puts(flg ? YES : NO ); } } |
`include "riscv_functions.vh"
module riscv_mem (
input clk,
input rstn,
//EX input
input ex_mem_rdy,
output ex_mem_ack,
input ex_mem_alu_op,
input [31:0] ex_mem_st_data,
input [`LD_FUNCT_W-1:0] ex_mem_ld_funct,
input [`ST_FUNCT_W-1:0] ex_mem_st_funct,
input [31:0] ex_mem_data,
//Data bif
output [31:0] data_bif_addr,
output data_bif_rnw,
output data_bif_rdy,
input data_bif_ack,
input [31:0] data_bif_rdata,
output [31:0] data_bif_wdata,
output [3:0] data_bif_wmask,
//RF output
output mem_rf_rdy,
output [31:0] mem_rf_data
);
//Outputs
reg ex_mem_ack;
reg data_bif_rdy;
reg data_bif_rnw;
reg [31:0] data_bif_addr;
reg [3:0] data_bif_wmask;
reg [31:0] data_bif_wdata;
reg [31:0] mem_rf_data_n;
reg mem_rf_rdy_n;
reg [31:0] mem_rf_data;
reg mem_rf_rdy;
reg ld_op;
reg st_op;
//Set data bif controls
always @ (*) begin
if (ex_mem_ld_funct != `LD_NOP) begin
ld_op = 1'b1;
st_op = 1'b0;
data_bif_rdy = 1'b1;
data_bif_rnw = 1'b1;
end
else if (ex_mem_st_funct != `ST_NOP) begin
ld_op = 1'b0;
st_op = 1'b1;
data_bif_rdy = 1'b1;
data_bif_rnw = 1'b0;
end
else begin
ld_op = 1'b0;
st_op = 1'b0;
data_bif_rnw = 1'b1;
data_bif_rdy = 1'b0;
end
end
//Assign wmask
always @ (*) begin
case (ex_mem_st_funct)
`ST_B : data_bif_wmask = 4'b0001;
`ST_H : data_bif_wmask = 4'b0011;
`ST_W : data_bif_wmask = 4'b1111;
default: data_bif_wmask = 4'b0000;
endcase
end
//Assign read data
always @ (*) begin
case (ex_mem_ld_funct)
`LD_B : mem_rf_data_n = {{24{data_bif_rdata[7]}} , data_bif_rdata[7:0]};
`LD_H : mem_rf_data_n = {{16{data_bif_rdata[15]}}, data_bif_rdata[15:0]};
`LD_W : mem_rf_data_n = data_bif_rdata;
`LD_BU : mem_rf_data_n = {24'b0, data_bif_rdata[7:0]};
`LD_HU : mem_rf_data_n = {16'b0, data_bif_rdata[15:0]};
default: mem_rf_data_n = ex_mem_data;
endcase
end
//Ack the incoming rdy
always @ (*) begin
if (data_bif_rdy) begin
//Only ack if are bus transfer is accepted
ex_mem_ack = data_bif_ack;
end
else begin
ex_mem_ack = 1'b1;
end
end
//Do we have write data going to the RF
always @ (*) begin
mem_rf_rdy_n = 1'b0;
if (ex_mem_rdy && ex_mem_ack) begin
if (ld_op || !st_op) begin
//Must be an ALU op
mem_rf_rdy_n = ex_mem_alu_op;
end
end
end
always @ (posedge clk, negedge rstn) begin
if (!rstn) begin
mem_rf_rdy <= 1'b0;
mem_rf_data <= 1'b0;
end
else begin
mem_rf_rdy <= mem_rf_rdy_n;
mem_rf_data <= mem_rf_data_n;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2e4 + 42; int n, m, k; int d[55][maxn], dp[55][maxn], s[55][maxn]; int val[maxn << 2], tag[maxn << 2]; int g; void build(int day, int l, int r, int rt) { if (l == r) { val[rt] = dp[day][l] + s[day + 1][l + k - 1] - s[day + 1][l - 1]; return; } int mid = l + r >> 1; build(day, l, mid, rt << 1); build(day, mid + 1, r, rt << 1 | 1); val[rt] = max(val[rt << 1], val[rt << 1 | 1]); } void pushd(int rt) { if (!tag[rt]) return; val[rt << 1] += tag[rt]; val[rt << 1 | 1] += tag[rt]; tag[rt << 1] += tag[rt]; tag[rt << 1 | 1] += tag[rt]; tag[rt] = 0; } void upd(int a, int b, int l, int r, int rt, int v) { if (a <= l && r <= b) { val[rt] += v, tag[rt] += v; return; } pushd(rt); int mid = l + r >> 1; if (a <= mid) upd(a, b, l, mid, rt << 1, v); if (b > mid) upd(a, b, mid + 1, r, rt << 1 | 1, v); val[rt] = max(val[rt << 1], val[rt << 1 | 1]); } void upd(int day, int pos) { if (pos) upd(max(1, pos - k + 1), min(g, pos), 1, g, 1, -d[day][pos]); } void del(int day, int pos) { if (pos) upd(max(1, pos - k + 1), min(g, pos), 1, g, 1, d[day][pos]); } signed main() { ios ::sync_with_stdio(false); cin.tie(nullptr), cout.tie(nullptr); cin >> n >> m >> k; g = m - k + 1; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { cin >> d[i][j]; s[i][j] = s[i][j - 1] + d[i][j]; } for (int i = 1; i <= n; i++) { if (i > 1) { for (int j = 1; j < k; j++) upd(i, j); } for (int j = 1; j + k - 1 <= m; j++) { int l = j, r = j + k - 1; if (i == 1) dp[1][j] = s[1][r] - s[1][l - 1]; else { del(i, l - 1); upd(i, r); dp[i][j] = s[i][r] - s[i][l - 1] + val[1]; } } memset(val, 0, sizeof(val)); memset(tag, 0, sizeof(tag)); if (i < n) build(i, 1, g, 1); } int ans = 0; for (int i = 1; i <= g; i++) ans = max(ans, dp[n][i]); cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const double pi = acos(-1); const int maxn = 20005; const long long Mod = 998244353; using namespace std; int n, m, k; int a[60][maxn], sum[60][maxn], dp[60][maxn]; int mx[maxn << 2], lazy[maxn << 2]; void pushup(int rt) { mx[rt] = max(mx[rt << 1], mx[rt << 1 | 1]); } void pushdown(int rt) { if (lazy[rt]) { mx[rt << 1] += lazy[rt]; mx[rt << 1 | 1] += lazy[rt]; lazy[rt << 1] += lazy[rt]; lazy[rt << 1 | 1] += lazy[rt]; lazy[rt] = 0; } } void build(int rt, int l, int r) { lazy[rt] = 0; mx[rt] = 0; if (l == r) return; int mid = (l + r) / 2; build(rt << 1, l, mid); build(rt << 1 | 1, mid + 1, r); } void update(int rt, int l, int r, int L, int R, int val) { if (l > R || r < L) { return; } if (l >= L && r <= R) { lazy[rt] += val; mx[rt] += val; return; } pushdown(rt); int mid = (l + r) / 2; update(rt << 1, l, mid, L, R, val); update(rt << 1 | 1, mid + 1, r, L, R, val); pushup(rt); return; } int query(int rt, int l, int r, int L, int R) { if (l > R || r < L) return 0; if (l >= L && r <= R) { return mx[rt]; } pushdown(rt); int mid = (l + r) / 2; return max(query(rt << 1, l, mid, L, R), query(rt << 1 | 1, mid + 1, r, L, R)); } int getsum(int i, int j) { int ret = sum[i][j + k - 1] - sum[i][j - 1]; if (i != n) { ret += sum[i + 1][j + k - 1] - sum[i + 1][j - 1]; } return ret; } int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); ; cin >> n >> m >> k; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) cin >> a[i][j]; for (int j = 1; j <= m; j++) sum[i][j] = sum[i][j - 1] + a[i][j]; } for (int i = 1; i <= m - k + 1; i++) dp[1][i] = getsum(1, i); for (int i = 2; i <= n; i++) { build(1, 1, m - k + 1); for (int j = 1; j <= m - k + 1; j++) update(1, 1, m - k + 1, j, j, dp[i - 1][j]); for (int j = 1; j <= m - k + 1; j++) { int l = max(j, 1), r = min(j + k - 1, k); if (l <= r) update(1, 1, m - k + 1, j, j, -(sum[i][r] - sum[i][l - 1])); } for (int j = 1; j <= m - k + 1; j++) { dp[i][j] = mx[1] + getsum(i, j); int L = max(1, j - k + 1); int R = min(m - k + 1, j); update(1, 1, m - k + 1, L, R, a[i][j]); if (j != m - k + 1) { int L = max(1, j + 1); int R = min(m - k + 1, j + k); update(1, 1, m - k + 1, L, R, -a[i][j + k]); } } } int ans = 0; for (int i = 1; i <= m - k + 1; i++) ans = max(ans, dp[n][i]); cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFBUF_FUNCTIONAL_V
`define SKY130_FD_SC_MS__BUFBUF_FUNCTIONAL_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__bufbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFBUF_FUNCTIONAL_V |
`default_nettype none
module \$alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
parameter _TECHMAP_CONSTMSK_CI_ = 0;
parameter _TECHMAP_CONSTVAL_CI_ = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
input CI, BI;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y, CO;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BX = B_buf;
wire [Y_WIDTH:0] ALM_CARRY;
// Start of carry chain
generate
if (_TECHMAP_CONSTMSK_CI_ == 1) begin
assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
end else begin
MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // Q = A
.LUT1(16'b0000_0000_0000_0000), // Q = 0 (LUT1's input to the adder is inverted)
) alm_start (
.A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
.CI(1'b0),
.CO(ALM_CARRY[0])
);
end
endgenerate
// Carry chain
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
// TODO: mwk suggests that a pass could merge pre-adder logic into this.
MISTRAL_ALUT_ARITH #(
.LUT0(16'b1010_1010_1010_1010), // Q = A
.LUT1(16'b1100_0011_1100_0011), // Q = C ? B : ~B (LUT1's input to the adder is inverted)
) alm_i (
.A(AA[i]), .B(BX[i]), .C(BI), .D0(1'b1), .D1(1'b1),
.CI(ALM_CARRY[i]),
.SO(Y[i]),
.CO(ALM_CARRY[i+1])
);
// ALM carry chain is not directly accessible, so calculate the carry through soft logic if really needed.
assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
end endgenerate
assign X = AA ^ BB;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, a, b, ans; vector<long long> v[100005]; vector<long long> res; long long cost(long long num) { res.clear(); long long sum = 0; long long need = num - v[0].size(); for (long long i = 1; i <= 100000; i++) { for (long long j = 0; j < v[i].size(); j++) { if (v[i].size() - j >= num) { need--; sum += v[i][j]; } else res.push_back(v[i][j]); } } sort(res.begin(), res.end()); for (long long i = 1; i <= need; i++) { sum += res[i - 1]; } return sum; } int main() { scanf( %lld , &n); for (long long i = 1; i <= n; i++) { scanf( %lld%lld , &a, &b); v[a].push_back(b); } for (long long i = 1; i <= 100000; i++) sort(v[i].begin(), v[i].end()); long long l = v[0].size(), r = n, m1, m2; ans = min(cost(l), cost(r)); while (l + 2 < r) { m1 = l + (r - l) / 3; m2 = r - (r - l) / 3; long long a1 = cost(m1); long long a2 = cost(m2); if (a1 > a2) l = m1, ans = min(ans, a2); else r = m2, ans = min(ans, a1); } printf( %lld n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221O_SYMBOL_V
`define SKY130_FD_SC_HD__A221O_SYMBOL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a221o (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221O_SYMBOL_V
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_length_counter.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU length counter; building block used by several other APU components. Provides automatic
* duration control for the NES APU waveform channels. Once loaded with a value, it can optionally
* count down and silence the channel when it reaches zero.
***************************************************************************************************/
`timescale 1ps / 1ps
module apu_length_counter
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire en_in, // enable signal (from $4015)
input wire halt_in, // disable length decrement
input wire length_pulse_in, // length pulse from frame counter
input wire [4:0] length_in, // new length value
input wire length_wr_in, // update length to length_in
output wire en_out // length counter is non-0
);
reg [7:0] q_length, d_length;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_length <= 8'h00;
end
else
begin
q_length <= d_length;
end
end
always @*
begin
d_length = q_length;
if (!en_in)
begin
d_length = 8'h00;
end
else if (length_wr_in)
begin
case (length_in)
5'h00: d_length = 8'h0A;
5'h01: d_length = 8'hFE;
5'h02: d_length = 8'h14;
5'h03: d_length = 8'h02;
5'h04: d_length = 8'h28;
5'h05: d_length = 8'h04;
5'h06: d_length = 8'h50;
5'h07: d_length = 8'h06;
5'h08: d_length = 8'hA0;
5'h09: d_length = 8'h08;
5'h0A: d_length = 8'h3C;
5'h0B: d_length = 8'h0A;
5'h0C: d_length = 8'h0E;
5'h0D: d_length = 8'h0C;
5'h0E: d_length = 8'h1A;
5'h0F: d_length = 8'h0E;
5'h10: d_length = 8'h0C;
5'h11: d_length = 8'h10;
5'h12: d_length = 8'h18;
5'h13: d_length = 8'h12;
5'h14: d_length = 8'h30;
5'h15: d_length = 8'h14;
5'h16: d_length = 8'h60;
5'h17: d_length = 8'h16;
5'h18: d_length = 8'hC0;
5'h19: d_length = 8'h18;
5'h1A: d_length = 8'h48;
5'h1B: d_length = 8'h1A;
5'h1C: d_length = 8'h10;
5'h1D: d_length = 8'h1C;
5'h1E: d_length = 8'h20;
5'h1F: d_length = 8'h1E;
endcase
end
else if (length_pulse_in && !halt_in && (q_length != 8'h00))
begin
d_length = q_length - 8'h01;
end
end
assign en_out = (q_length != 8'h00);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a, s, d[10004][2], f, g, h, j, k, l, i, n, m; string x, z; set<string> q; bool chk(int idx, int dis) { for (int i = idx; i < idx + dis; i++) { if (x[i] != x[i + dis]) return true; } return false; } int main() { cin >> x; n = x.size(); if (n >= 7) { d[n - 2][0] = 1; z = z + x[n - 2] + x[n - 1]; q.insert(z); } if (n >= 8) { d[n - 3][1] = 1; z = x[n - 3] + z; q.insert(z); } for (i = n - 4; i >= 5; i--) { d[i][0] = d[i + 2][1]; if (chk(i, 2)) d[i][0] |= d[i + 2][0]; if (d[i][0]) { z = ; z = z + x[i] + x[i + 1]; q.insert(z); } d[i][1] = d[i + 3][0]; if (chk(i, 3)) d[i][1] |= d[i + 3][1]; if (d[i][1]) { z = ; z = z + x[i] + x[i + 1] + x[i + 2]; q.insert(z); } } cout << q.size() << endl; for (set<string>::iterator it = q.begin(); it != q.end(); it++) { cout << *it << endl; } } |
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_b_channel.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] s_bid,
output wire [1:0] s_bresp,
output wire s_bvalid,
input wire s_bready,
input wire [1:0] m_bresp,
input wire m_bvalid,
output wire m_bready,
// Signals to/from the axi_protocol_converter_v2_1_b2s_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
input wire [7:0] b_awlen,
input wire b_resp_rdy,
output wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXI protocol responses:
localparam [1:0] LP_RESP_OKAY = 2'b00;
localparam [1:0] LP_RESP_EXOKAY = 2'b01;
localparam [1:0] LP_RESP_SLVERROR = 2'b10;
localparam [1:0] LP_RESP_DECERR = 2'b11;
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH + 8;
localparam P_DEPTH = 4;
localparam P_AWIDTH = 2;
localparam P_RWIDTH = 2;
localparam P_RDEPTH = 4;
localparam P_RAWIDTH = 2;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg bvalid_i;
wire [C_ID_WIDTH-1:0] bid_i;
wire shandshake;
reg shandshake_r;
wire mhandshake;
reg mhandshake_r;
wire b_empty;
wire bresp_full;
wire bresp_empty;
wire [7:0] b_awlen_i;
reg [7:0] bresp_cnt;
reg [1:0] s_bresp_acc;
wire [1:0] s_bresp_acc_r;
reg [1:0] s_bresp_i;
wire need_to_update_bresp;
wire bresp_push;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// assign AXI outputs
assign s_bid = bid_i;
assign s_bresp = s_bresp_acc_r;
assign s_bvalid = bvalid_i;
assign shandshake = s_bvalid & s_bready;
assign mhandshake = m_bvalid & m_bready;
always @(posedge clk) begin
if (reset | shandshake) begin
bvalid_i <= 1'b0;
end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin
bvalid_i <= 1'b1;
end
end
always @(posedge clk) begin
shandshake_r <= shandshake;
mhandshake_r <= mhandshake;
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( shandshake_r ) ,
.din ( {b_awid, b_awlen} ) ,
.dout ( {bid_i, b_awlen_i}) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( b_empty )
);
assign m_bready = ~mhandshake_r & bresp_empty;
/////////////////////////////////////////////////////////////////////////////
// Update if more critical.
assign need_to_update_bresp = ( m_bresp > s_bresp_acc );
// Select accumultated or direct depending on setting.
always @( * ) begin
if ( need_to_update_bresp ) begin
s_bresp_i = m_bresp;
end else begin
s_bresp_i = s_bresp_acc;
end
end
/////////////////////////////////////////////////////////////////////////////
// Accumulate MI-side BRESP.
always @ (posedge clk) begin
if (reset | bresp_push ) begin
s_bresp_acc <= LP_RESP_OKAY;
end else if ( mhandshake ) begin
s_bresp_acc <= s_bresp_i;
end
end
assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty;
always @ (posedge clk) begin
if (reset | bresp_push ) begin
bresp_cnt <= 8'h00;
end else if ( mhandshake_r ) begin
bresp_cnt <= bresp_cnt + 1'b1;
end
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_RWIDTH),
.C_AWIDTH (P_RAWIDTH),
.C_DEPTH (P_RDEPTH)
)
bresp_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( bresp_push ) ,
.rd_en ( shandshake_r ) ,
.din ( s_bresp_acc ) ,
.dout ( s_bresp_acc_r) ,
.a_full ( ) ,
.full ( bresp_full ) ,
.a_empty ( ) ,
.empty ( bresp_empty )
);
endmodule
`default_nettype wire
|
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
`default_nettype none
//
// This module implements a complete brushed DC motor channel with 16 bit quadrature tach counter,
// tach filtering, tach phase inversion, 8 bit pwm with current limit, and pwm output polarity selection.
module bdcmotorchannel(
// Tach counter low byte
output [7:0] countl,
// Tach counter high byte
output [7:0] counth,
// Complmentary pwm signals out
output [1:0] pwmout,
// 4 bit pwm signals out
output [3:0] pwmout4,
// System clock in
input clk,
// Clock enable for tach filter shift register
input filterce,
// Freeze tach counter ( used during reads)
input freeze,
// Invert tach counter phase
input invphase,
// PWM count enable (used to control PWM frequency)
input pwmcntce,
// Load a PWM value on the wrtdata bus into the PWM logic
input pwmldce,
// Invert the PWM outputs
input invertpwm,
// Enable the PWM outputs
input enablepwm,
// Run or send the brake signal to the pwm outputs
input run,
// Force early termination of the PWM cycle
input currentlimit,
// Quadrature tach inputs
input [1:0] tach,
// Write data bus
input [7:0] wrtdata);
tachcounter tc(
.clk(clk),
.tach(tach),
.filterce(filterce),
.freeze(freeze),
.invphase(invphase),
.countl(countl),
.counth(counth));
pwm8 pwm(
.clk(clk),
.pwmcntce(pwmcntce),
.pwmldce(pwmldce),
.invertpwm(invertpwm),
.enablepwm(enablepwm),
.run(run),
.currentlimit(currentlimit),
.wrtdata(wrtdata),
.pwmout(pwmout),
.pwmout4(pwmout4));
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> v; int main() { long long p, k; cin >> p >> k; while (p) { long long y = p % k; if (y < 0) y += k; v.push_back(y); p -= y; p /= k; p *= -1; } cout << v.size() << endl; for (int i = 0; i < v.size(); i++) { cout << v[i] << ; } cout << endl; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: FIFO_16_256.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module FIFO_16_256 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrfull);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output wrfull;
wire sub_wire0;
wire [15:0] sub_wire1;
wire wrfull = sub_wire0;
wire [15:0] q = sub_wire1[15:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.wrfull (sub_wire0),
.q (sub_wire1)
// synopsys translate_off
,
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256_wave*.jpg FALSE
|
#include <bits/stdc++.h> using namespace std; using LL = long long; const int maxn = 3000010; int n, b; int pre[maxn], vis[maxn]; vector<int> prime; struct init { init() { memset(pre, 0, sizeof pre); prime.clear(); for (int i = 2; i < maxn; i++) { if (pre[i] == 0) { pre[i] = i; prime.emplace_back(i); } for (int j = 0; j < prime.size() && i * prime[j] < maxn; j++) { if (prime[j] > pre[i]) break; pre[i * prime[j]] = prime[j]; } } } } init_; bool ok(int x) { if (x == 1) return 0; return pre[x] == 0; } signed main() { while (cin >> n) { memset(vis, 0, sizeof vis); for (int i = 1; i <= 2 * n; i++) { scanf( %d , &b); vis[b]++; } for (int i = maxn - 1; i > 1; i--) { if (pre[i] == i) continue; while (vis[i] > 0) { printf( %d , i); vis[i]--; vis[i / pre[i]]--; } } for (int i = 2; i < maxn; i++) { while (vis[i] > 0) { printf( %d , i); vis[i]--; vis[prime[i - 1]]--; } } printf( n ); } return 0; } |
// megafunction wizard: %LPM_COUNTER%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COUNTER
// ============================================================
// File Name: twentyonecounter.v
// Megafunction Name(s):
// LPM_COUNTER
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module twentyonecounter (
clock,
cnt_en,
sclr,
q);
input clock;
input cnt_en;
input sclr;
output [20:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: Direction NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
// Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
// Retrieval info: PRIVATE: SCLR NUMERIC "1"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: nBit NUMERIC "21"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
// Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "21"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL "cnt_en"
// Retrieval info: USED_PORT: q 0 0 21 0 OUTPUT NODEFVAL "q[20..0]"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: q 0 0 21 0 @q 0 0 21 0
// Retrieval info: GEN_FILE: TYPE_NORMAL twentyonecounter.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL twentyonecounter.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL twentyonecounter.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL twentyonecounter.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL twentyonecounter_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL twentyonecounter_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 11; int n, m; int cha[N], fa[N]; int dfn[N], tot, sz[N]; int U, V; int head[N], nex[N << 1], to[N << 1], size = 1; bool vis[N << 1]; int fr[N]; int dl[N], zh[N], tp; void add(int x, int y) { to[++size] = y; nex[size] = head[x]; head[x] = size; } void dfs(int u) { dfn[u] = ++tot; sz[u] = 1; for (int i = head[u]; i; i = nex[i]) { int v = to[i]; if (v == fa[u]) continue; if (!dfn[v]) { fa[v] = u; dfs(v); sz[u] += sz[v]; cha[u] += cha[v]; } else if (dfn[v] < dfn[u]) { cha[u]++; cha[v]--; } } if (!U && cha[u] > 1) { U = u; return; } } void bfs(int x, int id) { int hd = 0, tl = 1; dl[1] = x; for (int i = 1; i <= n; i++) fr[i] = 0; fr[x] = -1; while (hd < tl) { int u = dl[++hd]; for (int i = head[u]; i; i = nex[i]) { int v = to[i]; if (fr[v] != 0 || vis[i]) continue; fr[v] = i; if (v == V) break; dl[++tl] = v; } } for (int v = V; v != U; v = to[fr[v] ^ 1]) { zh[++tp] = v; vis[fr[v]] = vis[fr[v] ^ 1] = 1; } zh[++tp] = U; } void get_V() { for (int u = fa[U]; u; u = fa[u]) { int cnt = 0; for (int i = head[u]; i; i = nex[i]) { int v = to[i]; if (dfn[v] >= dfn[U] + (u == fa[U]) && dfn[v] <= dfn[U] + sz[U] - 1) { cnt++; } } if (cnt >= 1) { V = u; return; } } } int main() { cin >> n >> m; int u, v; for (int i = 1; i <= m; i++) { scanf( %d%d , &u, &v); add(u, v); add(v, u); } for (int i = 1; i <= n; i++) { if (!dfn[i]) dfs(i); } if (!U) { puts( NO ); } else { puts( YES ); get_V(); for (int i = 1; i <= 3; i++) { bfs(U, i); printf( %d , tp); while (tp) { printf( %d , zh[tp]); tp--; } puts( ); } } return 0; } |
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
Require Export Intervals.
(**
* Metric Spaces (traditional)
*)
Section Relations.
(**
** Relations necessary for Pseudo Metric Spaces and Metric Spaces
%\begin{convention}%
Let [A : CSetoid], [d : (CSetoid_bin_fun A A IR)].
%\end{convention}%
*)
Variable A : CSetoid.
Variable d : CSetoid_bin_fun A A IR.
Set Implicit Arguments.
Unset Strict Implicit.
Definition com : Prop := forall x y : A, d x y[=]d y x.
Definition nneg : Prop := forall x y : A, [0][<=]d x y.
Definition pos_imp_ap : CProp := forall x y : A, [0][<]d x y -> x[#]y.
Definition tri_ineq : Prop := forall x y z : A, d x z[<=]d x y[+]d y z.
Set Strict Implicit.
Unset Implicit Arguments.
Definition diag_zero (X : CSetoid) (d : CSetoid_bin_fun X X IR) : Prop :=
forall x : X, d x x[=][0].
Definition apdiag_imp_grzero (X : CSetoid) (d : CSetoid_bin_fun X X IR) :
CProp := forall x y : X, x[#]y -> [0][<]d x y.
End Relations.
Section Definition_PsMS0.
(**
** Definition of Pseudo Metric Space
*)
(**
A pseudo metric space consists of a setoid and a %''pseudo metric''% #"pseudo metric"#, also called
%''distance''% #"distance"#, a binairy function that fulfils certain properties.
*)
Record is_CPsMetricSpace (A : CSetoid) (d : CSetoid_bin_fun A A IR) :
Type :=
{ax_d_com : com d;
ax_d_nneg : nneg d;
ax_d_pos_imp_ap : pos_imp_ap d;
ax_d_tri_ineq : tri_ineq d}.
Record CPsMetricSpace : Type :=
{cms_crr :> CSetoid;
cms_d : CSetoid_bin_fun cms_crr cms_crr IR;
cms_proof : is_CPsMetricSpace cms_crr cms_d}.
End Definition_PsMS0.
Implicit Arguments cms_d [c].
Infix "[-d]" := cms_d (at level 68, left associativity).
Section PsMS_axioms.
(**
** Pseudo Metric Space axioms
%\begin{convention}%
Let [A] be a pseudo metric space.
%\end{convention}%
*)
Variable A : CPsMetricSpace.
Lemma CPsMetricSpace_is_CPsMetricSpace : is_CPsMetricSpace A cms_d.
Proof cms_proof A.
Lemma d_com : com (cms_d (c:=A)).
Proof.
elim CPsMetricSpace_is_CPsMetricSpace.
auto.
Qed.
Lemma d_nneg : nneg (cms_d (c:=A)).
Proof.
elim CPsMetricSpace_is_CPsMetricSpace.
auto.
Qed.
Lemma d_pos_imp_ap : pos_imp_ap (cms_d (c:=A)).
Proof.
elim CPsMetricSpace_is_CPsMetricSpace.
auto.
Qed.
Lemma d_tri_ineq : tri_ineq (cms_d (c:=A)).
Proof.
elim CPsMetricSpace_is_CPsMetricSpace.
auto.
Qed.
End PsMS_axioms.
Section PsMS_basics.
(**
** Pseudo Metric Space basics
%\begin{convention}%
Let [Y] be a pseudo metric space.
%\end{convention}%
*)
Variable Y : CPsMetricSpace.
Lemma rev_tri_ineq :
forall a b c : cms_crr Y, AbsSmall (b[-d]c) ((a[-d]b)[-](a[-d]c)).
Proof.
intros.
unfold AbsSmall in |- *.
split.
apply shift_leEq_minus.
apply shift_plus_leEq'.
unfold cg_minus in |- *.
cut ([--][--](b[-d]c)[=]b[-d]c).
intros.
apply leEq_wdr with ((a[-d]b)[+](b[-d]c)).
apply ax_d_tri_ineq.
apply CPsMetricSpace_is_CPsMetricSpace.
apply eq_symmetric_unfolded.
apply bin_op_wd_unfolded.
apply eq_reflexive_unfolded.
exact H.
apply cg_inv_inv.
astepr (c[-d]b).
apply shift_minus_leEq.
apply shift_leEq_plus'.
apply shift_minus_leEq.
apply ax_d_tri_ineq.
apply CPsMetricSpace_is_CPsMetricSpace.
apply ax_d_com.
apply CPsMetricSpace_is_CPsMetricSpace.
Qed.
(**
Instead of taking [pos_imp_ap] as axiom,
we could as well have taken [diag_zero].
*)
Lemma diag_zero_imp_pos_imp_ap :
forall (X : CSetoid) (d : CSetoid_bin_fun X X IR),
diag_zero X d -> pos_imp_ap d.
Proof.
intros X d.
unfold diag_zero in |- *.
unfold pos_imp_ap in |- *.
intros H.
intros x y H0.
cut (x[#]x or x[#]y).
intro H1.
elim H1.
cut (Not (x[#]x)).
intros H3 H4.
set (H5 := H3 H4) in *.
intuition.
apply ap_irreflexive_unfolded.
intro H2.
exact H2.
apply (csbf_strext X X IR d).
astepl ZeroR.
apply less_imp_ap.
exact H0.
Qed.
Lemma pos_imp_ap_imp_diag_zero :
forall (X : CSetoid) (d : CSetoid_bin_fun X X IR),
pos_imp_ap d -> nneg d -> diag_zero X d.
Proof.
intros X d.
unfold pos_imp_ap in |- *.
unfold nneg in |- *.
intros H H6.
unfold diag_zero in |- *.
intro x.
apply not_ap_imp_eq.
red in |- *.
intro H0.
set (H1 := less_conf_ap IR (d x x) [0]) in *.
generalize H1.
unfold Iff in |- *.
intro H2.
elim H2.
intros H3 H4.
set (H5 := H3 H0) in *.
elim H5.
generalize H6.
intros H7 H8.
set (H9 := H7 x x) in *.
rewrite -> leEq_def in H9.
set (H10 := H9 H8) in *.
exact H10.
intro H7.
set (H8 := H x x) in *.
set (H9 := H8 H7) in *.
set (H10 := ap_irreflexive_unfolded X x H9) in *.
exact H10.
Qed.
Lemma is_CPsMetricSpace_diag_zero :
forall (X : CSetoid) (d : CSetoid_bin_fun X X IR),
com d /\ tri_ineq d /\ nneg d /\ diag_zero X d -> is_CPsMetricSpace X d.
Proof.
intros X d H.
elim H.
intros H1 H2.
elim H2.
intros H3 H4.
elim H4.
intros H5 H6.
apply (Build_is_CPsMetricSpace X d H1 H5 (diag_zero_imp_pos_imp_ap X d H6) H3).
Qed.
End PsMS_basics.
Section Zerof.
(**
** Zero function
*)
(**
Every setoid forms with the binary function that always returns zero,
a pseudo metric space.
*)
Definition zero_fun (X : CSetoid) (x y : X) : IR := ZeroR.
Lemma zero_fun_strext :
forall X : CSetoid, bin_fun_strext X X IR (zero_fun X).
Proof.
intro X.
unfold bin_fun_strext in |- *.
unfold zero_fun in |- *.
intros x1 x2 y1 y2 Z.
set (H := ap_irreflexive_unfolded IR [0] Z) in *.
intuition.
Qed.
Definition Zero_fun (X : CSetoid) :=
Build_CSetoid_bin_fun X X IR (zero_fun X) (zero_fun_strext X).
Lemma zero_fun_com : forall X : CSetoid, com (Zero_fun X).
Proof.
intro X.
unfold com in |- *.
intros x y.
unfold Zero_fun in |- *.
simpl in |- *.
unfold zero_fun in |- *.
intuition.
Qed.
Lemma zero_fun_nneg : forall X : CSetoid, nneg (Zero_fun X).
Proof.
intro X.
unfold nneg in |- *.
intros x y.
unfold Zero_fun in |- *.
simpl in |- *.
unfold zero_fun in |- *.
apply eq_imp_leEq.
intuition.
Qed.
Lemma zero_fun_pos_imp_ap : forall X : CSetoid, pos_imp_ap (Zero_fun X).
Proof.
intro X.
unfold pos_imp_ap in |- *.
intros x y.
unfold Zero_fun in |- *.
simpl in |- *.
unfold zero_fun in |- *.
intro Z.
set (H := less_irreflexive IR [0] Z) in *.
intuition.
Qed.
Lemma zero_fun_tri_ineq : forall X : CSetoid, tri_ineq (Zero_fun X).
Proof.
intro X.
unfold tri_ineq in |- *.
intros x y z.
unfold Zero_fun in |- *.
simpl in |- *.
unfold zero_fun in |- *.
apply eq_imp_leEq.
rational.
Qed.
Definition zf_is_CPsMetricSpace (X : CSetoid) :=
Build_is_CPsMetricSpace X (Zero_fun X) (zero_fun_com X) (
zero_fun_nneg X) (zero_fun_pos_imp_ap X) (zero_fun_tri_ineq X).
Definition zf_as_CPsMetricSpace (X : CSetoid) :=
Build_CPsMetricSpace X (Zero_fun X) (zf_is_CPsMetricSpace X).
End Zerof.
|
module io1_sub(
/*AUTOARG*/);
wire [42:0] bscan_data; // boundary scan stitch
parameter bscan_count = 0;
assign bscan_data[0] = bscan_in;
/*
* Emacs template to auto instaniate MD[31:0] pads
*/
/*
autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@]),
.pin_in({SDRAM_DQ_in[@],SDRAM_DQ_in[@]}),
.pin_out(SDRAM_DQ_out[@]),
.pin_outen(SDRAM_DQ_outen),
.sdrmode(SDRAM_single_rate),
.hw_enb(SDRAM_upper_word_enb),
.ff_rptr(SDRAM_ddr_inff_sel),
.ff_wptr(ddr_inff_enbH),
.clk(data_strobeH),
.bscan_so(bscan_data[@ + 1]),
.bscan_si(bscan_data[@]),
.bscan_shift(BScanShift),
.bscan_clock(BScanClock),
.bscan_mode(BScanMode),
.bscan_update(BScanUpdate),
.bscan_outen(SDRAM_DQ_bscan_outen),
);
*/
autoinst_lopaz_srpad MD31_pad (/*AUTOINST*/
// Outputs
.pin_in ({SDRAM_DQ_in[31],SDRAM_DQ_in[31]}), // Templated
// Inouts
.pin (MD[31]), // Templated
// Inputs
.clk (data_strobeH), // Templated
.pin_out (SDRAM_DQ_out[31]), // Templated
.pin_outen (SDRAM_DQ_outen)); // Templated
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@"num"]),
);
*/
/*AUTO_LISP(setq num 1)*/
autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/
// Outputs
.pin_in (pin_in[2*w-1:0]),
// Inouts
.pin (MD[1]), // Templated
// Inputs
.clk (clk),
.pin_out (pin_out[w-1:0]),
.pin_outen (pin_outen));
/* autoinst_lopaz_srpad AUTO_TEMPLATE (
.pin(MD[@"num"]),
);
*/
/*AUTO_LISP(setq num 2)*/
autoinst_lopaz_srpad MD31_pad11 (/*AUTOINST*/
// Outputs
.pin_in (pin_in[2*w-1:0]),
// Inouts
.pin (MD[2]), // Templated
// Inputs
.clk (clk),
.pin_out (pin_out[w-1:0]),
.pin_outen (pin_outen));
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, q; int p[200001]; int a[200001]; vector<int> cur[200001]; int pos[200001]; int par[200001][21]; struct cmp { bool operator()(pair<int, int> a, pair<int, int> b) { return a.second > b.second; } }; priority_queue<pair<int, int>, vector<pair<int, int> >, cmp> h; struct Q { int l, r, id; }; vector<Q> Query; bool cmp(Q a, Q b) { return a.l < b.l; } int ans[200001]; int Process(int pos) { int k = n - 1; for (int i = 20; i >= 0; i--) { if (k & (1 << i)) { if (par[pos][i] == -1) return -1; pos = par[pos][i]; } } return pos; } int main() { cin >> n >> m >> q; for (int i = 1; i <= n; i++) { cin >> p[i]; pos[p[i]] = i; } for (int i = 1; i <= m; i++) { cin >> a[i]; } memset(par, -1, sizeof par); for (int i = 1; i <= m; i++) { int x = pos[a[i]]; int y; if (x == 1) y = p[n]; else y = p[x - 1]; for (auto k : cur[y]) { par[k][0] = i; } cur[y].clear(); cur[a[i]].push_back(i); } for (int j = 1; j <= 20; j++) { for (int i = 1; i <= m; i++) { if (par[i][j - 1] != -1) par[i][j] = par[par[i][j - 1]][j - 1]; } } for (int i = 1; i <= q; i++) { int l, r; cin >> l >> r; Query.push_back({l, r, i}); } sort(Query.begin(), Query.end(), cmp); for (int i = 1; i <= m; i++) { int r = Process(i); if (r != -1) h.push({i, r}); } for (auto x : Query) { int id = x.id; while (!h.empty() && h.top().first < x.l) h.pop(); if (h.empty() || h.top().second > x.r) ans[id] = 0; else ans[id] = 1; } for (int i = 1; i <= q; i++) cout << ans[i]; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A22O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A22O_FUNCTIONAL_PP_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a22o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X , and1_out, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A22O_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 10; int awsl[maxn]; int main() { int n; scanf( %d , &n); string s; cin >> s; vector<int> sum(n); vector<int> m(n); for (int i = 0; i < n; ++i) { if (s[i] == ( ) awsl[i] = 1; else awsl[i] = -1; } sum[0] = awsl[0]; for (int i = 1; i < n; ++i) { sum[i] = sum[i - 1] + awsl[i]; } m.back() = sum.back(); for (int i = n - 2; i >= 0; i--) { m[i] = min(sum[i], m[i + 1]); } int cnt = 0; for (int i = 0; i < n; ++i) { int v = 2 * awsl[i]; if (m[i] - v >= 0 && sum.back() - v == 0) cnt++; if (sum[i] < 0) break; } cout << cnt << n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_ground_lvc_wpad ( G_PAD, AMUXBUS_A, AMUXBUS_B
, G_CORE, BDY2_B2B, DRN_LVC1, DRN_LVC2, OGC_LVC, SRC_BDY_LVC1, SRC_BDY_LVC2, VSSA, VDDA, VSWITCH, VDDIO_Q, VCCHIB, VDDIO, VCCD, VSSIO, VSSD, VSSIO_Q
);
inout G_PAD;
inout AMUXBUS_A;
inout AMUXBUS_B;
inout SRC_BDY_LVC1;
inout SRC_BDY_LVC2;
inout OGC_LVC;
inout DRN_LVC1;
inout BDY2_B2B;
inout DRN_LVC2;
inout G_CORE;
inout VDDIO;
inout VDDIO_Q;
inout VDDA;
inout VCCD;
inout VSWITCH;
inout VCCHIB;
inout VSSA;
inout VSSD;
inout VSSIO_Q;
inout VSSIO;
assign G_CORE = G_PAD;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Host Bus Data Out stage
// File : hbi_dout_stage.v
// Author : Frank Bruno
// Created : 30-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// module to generates output blackbird data to the output pins & the module
// also generates parity for the data bus & the byte enables bus
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/10ps
module hbi_dout_stage
(
input hb_clk, // host bus clock
input [31:0] hb_regs_dout, // all HBI registers bus output
input [31:0] hb_rcache_dout, /* host bus data cache output
* (either data cache or WID cache
* output) */
input [31:0] hdat_out_crt_vga, // all CRT registers bus output
input [31:0] draw_engine_a_dout,// 2D cache readback
input [31:0] draw_engine_reg, // all DE registers bus output
input cs_global_regs_n, // global register is addressed.
input cs_hbi_regs_n, // HBI regsiters is been addressed.
input cs_xyw_a_n, // 2D cache accessed
input decoder_cs_windows_n, // memory windows is asserted
input hb_lached_rdwr, /* host bus read cycle in progress
* signal when asserted, it
* indicates that a host bus read
* cycle is in progress (active low)
*/
input hbi_addr_in, // host bus address bit
input [3:0] hb_byte_ens, /* HBI UNLATCHED byte enables
* directly from the PCI bus. */
input irdy_n, // host bus initiator ready signal
input sys_reset_n, // host bus system reset
input trdy_n, /* (BLACKBIRD) is ready to accept new
* data if the cycle is write, or
* target is ready to provide data
* if the cycle is read */
input [31:0] perph_rd_dbus, // read back perhpial data bus
input cs_eprom_n, /* chip select EPROM (the EPROM
* present on the graphics board) */
input cs_dac_space_n, /* chip select VGA registers in
* either I/O or MEM mode */
input cs_vga_space_n, /* chip select VGA space whenever
* BLK board has VGA on board
* (determined from the PCI class
* configuration bits) */
input [2:0] swizzler_ctrl,
input any_trdy_async, /* an "or" of all the async trdy
* sources */
input [31:0] pci_ad_out, // pci ad request data
input pci_ad_oe, // pci oe for write data
input [3:0] c_be_out,
output reg [31:0] blkbird_dout, // data output bus to the outside
output reg par32 /* even parity for the lower half of
* the data output bus */
);
reg pci_ad_oe_reg;
reg [31:0] hb_data_swizzled;
wire [31:0] hb_regblock_dout;
wire [31:0] hb_read_data;
wire [7:0] hb_dat_b3, hb_dat_b2, hb_dat_b1, hb_dat_b0;
wire [7:0] hb_dat_b7, hb_dat_b6, hb_dat_b5, hb_dat_b4;
wire be_par32;
wire bkbrd_par32;
wire lower_level_parity32;
wire be_out_par32;
wire pci_master_par32;
parameter
READ = 1'b0,
WRITE = 1'b1;
// DOUT_MUX
// Block to multiplex data from all Blackbird modules into the data bus
// OUTPUT MUX SELECTING OUTPUT DATA BETWEEN BLKBIRD MODULES
assign hb_read_data =
// PERPH
(!cs_eprom_n || !cs_dac_space_n) ? perph_rd_dbus :
// VGA & crt & video regsiters
(!cs_vga_space_n || !cs_global_regs_n) ? hdat_out_crt_vga :
// hb registers
(!cs_hbi_regs_n) ? hb_regs_dout :
// hb data cache
(!decoder_cs_windows_n) ? hb_rcache_dout :
// 2D DE cache
(!cs_xyw_a_n) ? draw_engine_a_dout :
// Drawing Engine registers
draw_engine_reg;
// SWIZZLER FOR THE READ DATA PATH
assign hb_dat_b3 =
(swizzler_ctrl[0]) ?
{hb_read_data[24], hb_read_data[25], hb_read_data[26],
hb_read_data[27], hb_read_data[28], hb_read_data[29],
hb_read_data[30], hb_read_data[31]} :
hb_read_data[31:24];
assign hb_dat_b2 =
(swizzler_ctrl[0]) ?
{hb_read_data[16], hb_read_data[17], hb_read_data[18],
hb_read_data[19], hb_read_data[20], hb_read_data[21],
hb_read_data[22], hb_read_data[23]} :
hb_read_data[23:16];
assign hb_dat_b1 =
(swizzler_ctrl[0]) ?
{hb_read_data[8], hb_read_data[9], hb_read_data[10],
hb_read_data[11], hb_read_data[12] ,hb_read_data[13],
hb_read_data[14], hb_read_data[15]} :
hb_read_data[15:8];
assign hb_dat_b0 =
(swizzler_ctrl[0]) ?
{hb_read_data[0], hb_read_data[1], hb_read_data[2],
hb_read_data[3], hb_read_data[4], hb_read_data[5],
hb_read_data[6],hb_read_data[7]} :
hb_read_data[7:0];
always @*
case (swizzler_ctrl[2:1])
2'b00:
hb_data_swizzled = { hb_dat_b3, hb_dat_b2, hb_dat_b1, hb_dat_b0};
2'b01:
hb_data_swizzled = { hb_dat_b2, hb_dat_b3, hb_dat_b0, hb_dat_b1};
2'b10:
hb_data_swizzled = { hb_dat_b1, hb_dat_b0, hb_dat_b3, hb_dat_b2};
2'b11:
hb_data_swizzled = { hb_dat_b0, hb_dat_b1, hb_dat_b2, hb_dat_b3};
endcase // case(swizzler_ctrl[2:0])
// PIPELINE THE OUTPUT DATA
always @ (posedge hb_clk) begin
//read cycle is active (in progress) thus allow data to flow through
//if (hb_lached_rdwr==READ && ((any_trdy_async && trdy_n) ||
// (!trdy_n && !irdy_n)))
if (any_trdy_async && (trdy_n || (!trdy_n && !irdy_n)))
blkbird_dout <= hb_data_swizzled;
else if (pci_ad_oe)
blkbird_dout <= pci_ad_out;
end
/*******************************************************************************
* PARITY_GENERATOR
* Block to generate EVEN PARITY for the the host bus read cycles & the
* PCI master's write cycles as required by the PCI spec.
*******************************************************************************/
always @(posedge hb_clk) pci_ad_oe_reg <= pci_ad_oe;
assign be_par32 = ^hb_byte_ens[3:0];
assign be_out_par32 = ^c_be_out[3:0]; //PCI master's CBEs
assign bkbrd_par32 = ^blkbird_dout;
assign lower_level_parity32 = bkbrd_par32 ^ be_par32;//Parity for PCI slave
assign pci_master_par32 = bkbrd_par32 ^ be_out_par32;//Parity for PCI master
//Parity is clocked at the end of every beat(and that would delay
//parity by one clock to comply with PCI spec.)
always @(posedge hb_clk or negedge sys_reset_n) begin
if (!sys_reset_n) begin
par32 <= 1'b0;
end else if (pci_ad_oe_reg) begin
par32 <= pci_master_par32;
end else if (!trdy_n && !irdy_n) begin
par32 <= lower_level_parity32; //current beat is done
end
end
endmodule // HBI_DOUT_STAGE
|
#include <bits/stdc++.h> #pragma GCC optimize(3, Ofast , inline ) #pragma GCC target( avx,avx2 ) using namespace std; template <class t> inline t read(t &x) { char c = getchar(); bool f = 0; x = 0; while (!isdigit(c)) f |= c == - , c = getchar(); while (isdigit(c)) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); if (f) x = -x; return x; } template <class t> inline void write(t x) { if (x < 0) putchar( - ), write(-x); else { if (x > 9) write(x / 10); putchar( 0 + x % 10); } } const long long N = 1005, mod = 1e9 + 7; long long f[N][N][2][2], g[N], ans[N], n, m, fac[N], inv[N]; long long C(long long n, long long m) { return fac[n] * inv[m] % mod * inv[n - m] % mod; } signed main() { read(n); read(m); fac[0] = inv[0] = inv[1] = 1; for (long long i = 1; i <= n; i++) fac[i] = fac[i - 1] * i % mod; for (long long i = 2; i <= n; i++) inv[i] = inv[mod % i] * (mod - mod / i) % mod; for (long long i = 1; i <= n; i++) inv[i] = inv[i] * inv[i - 1] % mod; f[1][0][0][0] = f[1][1][0][1] = 1; for (long long i = 2; i <= n; i++) for (long long j = 0; j < i; j++) { f[i][j][0][0] = (f[i][j][0][0] + f[i - 1][j][0][0] + f[i - 1][j][1][0]) % mod; f[i][j][1][0] = (f[i][j][1][0] + f[i - 1][j][0][1] + f[i - 1][j][1][1]) % mod; f[i][j + 1][0][0] = f[i - 1][j][0][0]; f[i][j + 1][0][1] = (f[i - 1][j][0][0] + f[i - 1][j][1][0]) % mod; f[i][j + 1][1][0] = f[i - 1][j][0][1]; f[i][j + 1][1][1] = (f[i - 1][j][0][1] + f[i - 1][j][1][1]) % mod; } for (long long i = 0; i <= n; i++) g[i] = (f[n][i][0][0] + f[n][i][1][0]) * fac[n - i] % mod; for (long long i = 0; i <= n; i++) for (long long j = i, op = 1; j <= n; j++, op *= -1) ans[i] = (ans[i] + mod + op * C(j, i) * g[j] % mod) % mod; write(ans[m]); } |
#include <bits/stdc++.h> using namespace std; int n, t, k, x; string s; int main() { cin >> s; n = s.size(); for (int k = 0;; k++) { if (s[k] == . ) { t = k; break; } } if (s[t - 1] == 9 + 0 ) cout << GOTO Vasilisa. ; else if (s[t + 1] < 5 + 0 ) { for (int i = 0; i < t; i++) cout << s[i]; } else if (s[t + 1] >= 5 + 0 ) { for (int i = 0; i < t - 1; i++) cout << s[i]; cout << s[t - 1] - 0 + 1; } return 0; } |
#include <bits/stdc++.h> using namespace std; bool judge(char c) { if (c == a || c == e || c == i || c == o || c == u || c == y ) return false; else return true; } int main() { char a[110]; int n, m = 0; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { if (judge(a[i])) { cout << a[i]; m = 0; } else if (m == 1) continue; else if (!judge(a[i])) cout << a[i], m = 1; } } |
#include <bits/stdc++.h> using namespace std; string gd, str, ask; int q, n, t, ans, tmp, cnt, ara[1000]; int main() { cin >> gd >> str >> n; for (int i = 0; i < gd.size(); i++) ara[gd[i] - a ] = 1; while (n--) { cin >> ask; int in = -1, fin = -1; ans = 0; for (int i = 0; i < max(str.size(), ask.size()); i++) { if (str[i] == ? ) { if (ara[ask[i] - a ] != 1) { ans = 2; break; } } else if (str[i] == * ) { in = i; break; } else { if (str[i] != ask[i]) { ans = 2; break; } } } if (ans == 2) { printf( NO n ); continue; } else if (in == -1) { printf( YES n ); continue; } else { for (int i = str.size() - 1, j = ask.size() - 1; i >= 0; i--, j--) { if (str[i] == ? ) { if (ara[ask[j] - a ] != 1) { ans = 2; break; } } else if (str[i] == * ) { fin = j + 1; break; } else { if (str[i] != ask[j]) { ans = 2; break; } } } } if (ans == 2 || fin == -1 || in > fin) { printf( NO n ); continue; } else { for (int i = in; i < fin; i++) { if (ara[ask[i] - a ] == 1) { ans = 2; break; } } } if (ans == 2) { printf( NO n ); } else printf( YES n ); } return 0; } |
//-----------------------------------------------------
// This is FSM demo program using always block
// Design Name : fsm_using_always
// File Name : fsm_using_always.v
//-----------------------------------------------------
module fsm_using_always (
clock , // clock
reset , // Active high, syn reset
req_0 , // Request 0
req_1 , // Request 1
gnt_0 , // Grant 0
gnt_1
);
//-------------Input Ports-----------------------------
input clock,reset,req_0,req_1;
//-------------Output Ports----------------------------
output gnt_0,gnt_1;
//-------------Input ports Data Type-------------------
wire clock,reset,req_0,req_1;
//-------------Output Ports Data Type------------------
reg gnt_0,gnt_1;
//-------------Internal Constants--------------------------
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
//-------------Internal Variables---------------------------
reg [SIZE-1:0] state ;// Seq part of the FSM
reg [SIZE-1:0] next_state ;// combo part of FSM
//----------Code startes Here------------------------
always @ (state or req_0 or req_1)
begin : FSM_COMBO
next_state = 3'b000;
case(state)
IDLE : if (req_0 == 1'b1) begin
next_state = GNT0;
end else if (req_1 == 1'b1) begin
next_state= GNT1;
end else begin
next_state = IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
next_state = GNT0;
end else begin
next_state = IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
next_state = GNT1;
end else begin
next_state = IDLE;
end
default : next_state = IDLE;
endcase
end
//----------Seq Logic-----------------------------
always @ (posedge clock)
begin : FSM_SEQ
if (reset == 1'b1) begin
state <= #1 IDLE;
end else begin
state <= #1 next_state;
end
end
//----------Output Logic-----------------------------
always @ (posedge clock)
begin : OUTPUT_LOGIC
if (reset == 1'b1) begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b0;
end
else begin
case(state)
IDLE : begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b0;
end
GNT0 : begin
gnt_0 <= #1 1'b1;
gnt_1 <= #1 1'b0;
end
GNT1 : begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b1;
end
default : begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b0;
end
endcase
end
end // End Of Block OUTPUT_LOGIC
endmodule // End of Module arbiter
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_1_V
`define SKY130_FD_SC_LS__XOR2_1_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xor2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xor2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_1_V
|
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int mod = 1e9 + 7; int n, a[500010], b[500010], c[500010], bit[500010]; void init() { for (int i = 1; i <= n; i++) { bit[i] = 0; } } int lowbit(int x) { return x & (-x); } void add(int u, int x) { for (; u <= n; u += lowbit(u)) { bit[u] = (bit[u] + x) % mod; } } int sum(int u) { int res = 0; for (; u >= 1; u -= lowbit(u)) { res = (res + bit[u]) % mod; } return res; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); b[i] = a[i]; } sort(b + 1, b + n + 1); for (int i = 1; i <= n; i++) { a[i] = lower_bound(b + 1, b + n + 1, a[i]) - b; } int ans = 0; init(); for (int i = 1; i <= n; i++) { ans = (ans + 1LL * b[a[i]] * sum(a[i]) % mod * (n - i + 1) % mod) % mod; c[a[i]] += sum(a[i]) * (n - i + 1); add(a[i], i); } init(); for (int i = n; i >= 1; i--) { ans = (ans + 1LL * b[a[i]] * sum(a[i]) % mod * i % mod) % mod; c[a[i]] += sum(a[i]) * i; add(a[i], n - i + 1); } for (int i = 1; i <= n; i++) { ans = (ans + 1LL * b[a[i]] * i % mod * (n - i + 1) % mod) % mod; c[a[i]] += i * (n - i + 1); } printf( %d n , ans); return 0; } |
module scaler_spliter # (
parameter integer C_S_WIDTH = 12,
parameter integer C_M_WIDTH = 12,
parameter integer C_S_BMP = 0 ,
parameter integer C_S_BID = 0 ,
parameter integer C_S_IDX = 0 , /// C_S_WIDTH or 0
parameter integer C_SPLIT_ID_WIDTH = 2,
parameter integer C_TEST = 0
) (
input wire clk,
input wire resetn,
///input [C_S_WIDTH-1:0] s_nbr,
input [C_M_WIDTH-1:0] m_nbr,
input wire enable,
input wire i_valid ,
input wire i_s_advance ,
input wire i_s_last ,
input wire [C_S_WIDTH + C_M_WIDTH :0] i_s_c ,
input wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] i_s_bmp_bid_idx0,
input wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] i_s_bmp_bid_idx1,
input wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] i_s_bmp_bid_idx2,
input wire i_m_advance ,
input wire i_m_first ,
input wire i_m_last ,
input wire [C_S_WIDTH + C_M_WIDTH :0] i_m_c ,
input wire i_a_last ,
input wire i_d_valid ,
output wire o_valid ,
output wire o_s_advance ,
output wire o_s_last ,
output wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] o_s_bmp_bid_idx0,
output wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] o_s_bmp_bid_idx1,
output wire [C_S_BMP + C_S_BID + C_S_IDX - 1 : 0] o_s_bmp_bid_idx2,
output wire o_m_advance ,
output wire o_m_first ,
output wire o_m_last ,
output wire o_a_last ,
output wire o_d_valid ,
output wire [C_SPLIT_ID_WIDTH : 0] o_split_id
);
localparam integer C_SPLITERN = (1 << C_SPLIT_ID_WIDTH);
///////////////////////////////////// spliter //////////////////////////////////
reg[C_M_WIDTH:0] spliter[C_SPLITERN-1:0];
always @ (posedge clk) begin
spliter[0] <= (m_nbr * 1 + m_nbr * 0) / 4;
spliter[1] <= (m_nbr * 2 + m_nbr * 1) / 4;
spliter[2] <= (m_nbr * 4 + m_nbr * 1) / 4;
spliter[3] <= (m_nbr * 8 - m_nbr * 1) / 4;
end
///////////////////////////////////// input ////////////////////////////////////
wire input_same01;
generate
if (C_S_BID) begin
wire [C_S_BID-1:0] bid0;
wire [C_S_BID-1:0] bid1;
assign bid0 = i_s_bmp_bid_idx0[C_S_BID+C_S_IDX-1:C_S_IDX];
assign bid1 = i_s_bmp_bid_idx1[C_S_BID+C_S_IDX-1:C_S_IDX];
assign input_same01 = (bid0 == bid1);
end
else if (C_S_BMP) begin
wire [C_S_BMP-1:0] bmp0;
wire [C_S_BMP-1:0] bmp1;
assign bmp0 = i_s_bmp_bid_idx0[C_S_BMP+C_S_BID+C_S_IDX-1:C_S_BID+C_S_IDX];
assign bmp1 = i_s_bmp_bid_idx1[C_S_BMP+C_S_BID+C_S_IDX-1:C_S_BID+C_S_IDX];
assign input_same01 = (bmp0 == bmp1);
end
else if (C_S_IDX) begin
wire [C_S_WIDTH-1:0] idx0;
wire [C_S_WIDTH-1:0] idx1;
assign idx0 = i_s_bmp_bid_idx0[C_S_IDX-1:0];
assign idx1 = i_s_bmp_bid_idx1[C_S_IDX-1:0];
assign input_same01 = (idx0 == idx1);
end
else begin
assign input_same01 = 1;
end
endgenerate
////////////////////////////////////// delay 0 /////////////////////////////////
reg dly0_valid ;
reg dly0_s_advance ;
reg dly0_s_last ;
reg [C_S_BMP + C_S_BID + C_S_WIDTH - 1 : 0] dly0_s_bmp_bid_idx0;
reg [C_S_BMP + C_S_BID + C_S_WIDTH - 1 : 0] dly0_s_bmp_bid_idx1;
reg [C_S_BMP + C_S_BID + C_S_WIDTH - 1 : 0] dly0_s_bmp_bid_idx2;
reg dly0_m_advance ;
reg dly0_m_first ;
reg dly0_m_last ;
reg dly0_a_last ;
reg dly0_d_valid ;
reg [C_M_WIDTH :0] dly0_diff ;
always @ (posedge clk) begin
if (resetn == 1'b0)
dly0_valid <= 0 ;
else if (enable) begin
dly0_valid <= i_valid ;
dly0_s_advance <= i_s_advance ;
dly0_s_last <= i_s_last ;
dly0_s_bmp_bid_idx0 <= i_s_bmp_bid_idx0;
dly0_s_bmp_bid_idx1 <= i_s_bmp_bid_idx1;
dly0_s_bmp_bid_idx2 <= i_s_bmp_bid_idx2;
dly0_m_advance <= i_m_advance ;
dly0_m_first <= i_m_first ;
dly0_m_last <= i_m_last ;
dly0_a_last <= i_a_last ;
dly0_d_valid <= i_d_valid ;
dly0_diff <= (input_same01 ? 0 : (i_s_c - i_m_c));
end
end
wire[C_SPLITERN-1:0] dly0_cmp ;
generate
genvar i;
for (i = 0; i < C_SPLITERN; i=i+1) begin: single_cmp
assign dly0_cmp[i] = (dly0_diff <= spliter[i]);
end
endgenerate
////////////////////////////////////// delay 1 /////////////////////////////////
reg dly1_valid ;
reg dly1_s_advance ;
reg dly1_s_last ;
reg [C_S_BMP + C_S_BID + C_S_WIDTH - 1 : 0] dly1_s_bmp_bid_idx0;
reg [C_S_BMP + C_S_BID + C_S_WIDTH - 1 : 0] dly1_s_bmp_bid_idx1;
reg [C_S_BMP + C_S_BID + C_S_WIDTH - 1 : 0] dly1_s_bmp_bid_idx2;
reg dly1_m_advance ;
reg dly1_m_first ;
reg dly1_m_last ;
reg dly1_a_last ;
reg dly1_d_valid ;
reg [C_SPLIT_ID_WIDTH : 0] dly1_split_id ;
always @ (posedge clk) begin
if (resetn == 1'b0)
dly1_valid <= 0 ;
else if (enable) begin
dly1_valid <= dly0_valid ;
dly1_s_advance <= dly0_s_advance ;
dly1_s_last <= dly0_s_last ;
dly1_s_bmp_bid_idx0 <= dly0_s_bmp_bid_idx0;
dly1_s_bmp_bid_idx1 <= dly0_s_bmp_bid_idx1;
dly1_s_bmp_bid_idx2 <= dly0_s_bmp_bid_idx2;
dly1_m_advance <= dly0_m_advance ;
dly1_m_first <= dly0_m_first ;
dly1_m_last <= dly0_m_last ;
dly1_a_last <= dly0_a_last ;
dly1_d_valid <= dly0_d_valid ;
case (dly0_cmp)
4'b1111: dly1_split_id <= 0;
4'b1110: dly1_split_id <= 1;
4'b1100: dly1_split_id <= 2;
4'b1000: dly1_split_id <= 3;
default: dly1_split_id <= 4;
endcase
end
end
assign o_valid = dly1_valid ;
assign o_s_advance = dly1_s_advance ;
assign o_s_last = dly1_s_last ;
assign o_s_bmp_bid_idx0 = dly1_s_bmp_bid_idx0;
assign o_s_bmp_bid_idx1 = dly1_s_bmp_bid_idx1;
assign o_s_bmp_bid_idx2 = dly1_s_bmp_bid_idx2;
assign o_m_advance = dly1_m_advance ;
assign o_m_first = dly1_m_first ;
assign o_m_last = dly1_m_last ;
assign o_a_last = dly1_a_last ;
assign o_d_valid = dly1_d_valid ;
assign o_split_id = dly1_split_id ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; scanf( %d%d , &n, &m); queue<int> x, y; for (int i = 0; i < n; ++i) { int tmp; scanf( %d , &tmp); x.push(tmp); } for (int i = 0; i < m; ++i) { int tmp; scanf( %d , &tmp); y.push(tmp); } int ans = 0, xSum = x.front(), ySum = y.front(); x.pop(), y.pop(); while (!x.empty() && !y.empty()) { if (xSum == ySum) { ++ans; xSum = x.front(); x.pop(); ySum = y.front(); y.pop(); } else { if (xSum < ySum) { xSum += x.front(); x.pop(); } else { ySum += y.front(); y.pop(); } } } cout << ans + 1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long int> a, v, val; long long int n, x; long long int eval(long long int d, long long int i) { if ((d + x - 1) <= a[i]) { long long int ans = ((d + x - 1) * (d + x)) / 2 - ((d - 1) * (d)) / 2; return ans; } else { long long int c = x - (a[i] - d + 1); long long int l, r, mid, m, ans = 0; l = i + 1; r = 2 * n; while (l <= r) { mid = l + (r - l) / 2; if ((v[mid] - v[i]) >= c) { m = mid; r = mid - 1; } else l = mid + 1; } ans += ((a[i]) * (a[i] + 1)) / 2 - ((d - 1) * (d)) / 2; ans += val[m - 1] - val[i]; c -= v[m - 1] - v[i]; ans += c * (c + 1) / 2; return ans; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int i, ans = 0, l, r, m1, m2, c, b; cin >> n >> x; a.resize(2 * n + 2); v.resize(2 * n + 2); val.resize(2 * n + 2); for (i = 1; i <= n; i++) { cin >> a[i]; a[i + n] = a[i]; } for (i = 1; i <= 2 * n; i++) { v[i] = v[i - 1] + a[i]; val[i] = val[i - 1] + (a[i] * (a[i] + 1)) / 2; } for (i = 1; i <= n; i++) { l = 1; r = a[i]; m1 = l; while (l <= r) { m1 = l + (r - l) / 3; m2 = r - (r - l) / 3; c = eval(m1, i); b = eval(m2, i); ans = max(ans, c); ans = max(ans, b); if (c >= b) r = m2 - 1; else l = m1 + 1; } ans = max(ans, eval(m1, i)); } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, x, y, m, nr, nr1, st, dr, i, j, z, p1, p2, aux, a[1004], b[1004], s[1004], d[1004]; bool ok, c[1004]; int main() { scanf( %d %d %d , &n, &x, &y); ok = true; y = 1; s[1] = 1; d[1] = n; while (ok == true) { nr1 = 0; nr = 0; for (i = 1; i <= y; i++) { if (s[i] != d[i]) { for (j = s[i]; j <= ((s[i] + d[i]) / 2); j++) b[++nr1] = j; for (j = ((s[i] + d[i]) / 2 + 1); j <= d[i]; j++) a[++nr] = j; } } printf( ? %d , nr1); for (i = 1; i <= nr1; i++) printf( %d , b[i]); printf( n ); fflush(stdout); scanf( %d , &z); if (z != 0 && z != x) break; for (i = y; i >= 1; i--) { s[2 * i] = (s[i] + d[i]) / 2 + 1; d[2 * i] = d[i]; s[2 * i - 1] = s[i]; d[2 * i - 1] = (s[i] + d[i]) / 2; } y *= 2; } st = 1; dr = nr1; while (st <= dr) { m = (st + dr) / 2; printf( ? %d , m); for (i = 1; i <= m; i++) printf( %d , b[i]); printf( n ); fflush(stdout); scanf( %d , &z); if (z != 0 && z != x) dr = m - 1; else st = m + 1; } p1 = b[st]; for (i = 1; i <= n; i++) c[i] = false; for (i = 1; i <= nr1; i++) c[b[i]] = true; if (y > 1) { for (i = 1; i <= y; i++) { if (s[i] <= p1 && p1 <= d[i]) break; } nr = 0; for (j = s[i]; j < p1; j++) { if (c[j] == false) a[++nr] = j; } for (j = (p1 + 1); j <= d[i]; j++) { if (c[j] == false) a[++nr] = j; } } st = 1; dr = nr; if (st < dr) { while (st <= dr) { m = (st + dr) / 2; printf( ? %d , m); for (i = 1; i <= m; i++) printf( %d , a[i]); printf( n ); fflush(stdout); scanf( %d , &z); if (z != 0 && z != x) dr = m - 1; else st = m + 1; } } p2 = a[st]; if (p1 > p2) { aux = p1; p1 = p2; p2 = aux; } printf( ! %d %d n , p1, p2); fflush(stdout); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> g[100000 + 10]; map<pair<long long, long long>, long long> mp; map<long long, pair<long long, long long> > road; long long cnt[100000 + 10]; long long ans = 0; int visited[100000 + 10]; int L[100000 + 100]; long long n; void dfs(long long u) { visited[u] = 1; long long l = g[u].size(); cnt[u] = 1; for (int i = 0; i < l; i++) { long long v = g[u][i]; if (visited[v] == 0) { L[v] = L[u] + 1; visited[v] = 1; dfs(v); cnt[u] += cnt[v]; ans += mp[make_pair(u, v)] * cnt[v] * (n - cnt[v]); } } } int main() { scanf( %lld , &(n)); for (int i = 1; i < n; i++) { long long u, v, w; scanf( %lld , &(u)); scanf( %lld , &(v)); scanf( %lld , &(w)); g[u].push_back(v); g[v].push_back(u); mp[make_pair(u, v)] = w; mp[make_pair(v, u)] = w; road[i] = make_pair(u, v); } L[1] = 1; dfs(1); int q; scanf( %d , &(q)); while (q--) { long long r; long long w; scanf( %lld , &(r)); scanf( %lld , &(w)); pair<long long, long long> x; x = road[r]; if (L[x.first] > L[x.second]) { long long tmp = x.first; x.first = x.second; x.second = tmp; } ans += (cnt[x.second]) * (n - cnt[x.second]) * (w - mp[x]); mp[x] = w; mp[make_pair(x.second, x.first)] = w; double num = ans * 6.0 / (n * (n - 1)); printf( %.10f n , num); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BAI_BLACKBOX_V
`define SKY130_FD_SC_HS__O21BAI_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BAI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, maxi[((int)101 * 1000) / ((int)350) + 1000], fnsh, id[((int)101 * 1000)], ex[((int)101 * 1000)]; vector<int> v[((int)101 * 1000) / ((int)350) + 1000]; void reset() { int num = 0; for (int i = 0; i < fnsh; v[i].clear(), v[i].resize(0), i++) for (auto u : v[i]) ex[num++] = u; fnsh = 0; maxi[0] = 0; for (int i = 0; i < num; i++) { v[fnsh].push_back(ex[i]); maxi[fnsh] = max(maxi[fnsh], ex[i]); if (i % ((int)350) == ((int)350) - 1 || i == num - 1) fnsh++, maxi[fnsh] = 0; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 0; i < n; i++) { int a, c; cin >> a >> c; id[a] = i + 1; bool flg = 0; for (int j = 0, num = 0; j < fnsh && !flg; num += (int)v[j].size(), j++) if (num + (int)v[j].size() > c || maxi[j] > a) { flg = 1; for (int k = 0; k < v[j].size(); k++) { if (v[j][k] > a) { v[j].insert(v[j].begin() + k, a); break; } if (k + num == c) { v[j].insert(v[j].begin() + k, a); maxi[j] = max(maxi[j], a); break; } } } if (!flg) { v[fnsh].push_back(a); maxi[fnsh] = a; fnsh++; } if (i % ((int)350) == ((int)350) - 1) reset(); } for (int i = fnsh - 1; i >= 0; i--) for (int j = (int)v[i].size() - 1; j >= 0; j--) cout << id[v[i][j]] << ; return 0; } |
#include<bits/stdc++.h> using namespace std; #ifdef LOCAL #include debug.h #endif #ifdef LOCAL #define debug(...) cerr << [ << #__VA_ARGS__ << ]: , debug_out(__VA_ARGS__) #else #define debug(...) 42 #endif #define endl n typedef long long ll; typedef long double ld; typedef vector<int> vi; typedef std::vector<vector<int> > vvi; typedef pair<int, int> pi; typedef pair<ll, ll> pll; typedef vector<ll> vll; typedef vector<pi> vpi; typedef vector<pll> vpll; typedef vector<vll> vvll; typedef vector<vi> vvi; typedef vector<double> vd; typedef vector<vector<double>> vvd; typedef vector<ld> vld; typedef vector<vld> vvld; typedef vector<bool> vb; typedef vector<vb> vvb; typedef vector<char> vch; typedef vector<vch> vvch; #define rep(i, a, b) for (int i = (int)(a); i < (int)(b); i++) #define repi(i, a, b) for (int i = (int)(a); i >= (int)(b); i--) #define pb push_back #define fi first #define se second #define all(a) a.begin(), a.end() #define sz(a) (int)(a.size()) template<typename T> void umin(T &a, T b) { a = min(a, b); } template<typename T> void umax(T &a, T b) { a = max(a, b); } ll nxt() { ll x; cin >> x; return x; } void setIO(string s) { #ifndef LOCAL ios_base::sync_with_stdio(0); cin.tie(0); freopen((s+ .in ).c_str(), r ,stdin); freopen((s+ .out ).c_str(), w ,stdout); #endif } void yes() { cout << yes n ; } void no() { cout << no n ; } void flush() { debug( ################# ); } const ll mod = 1e9 + 7; const ll INF = 1e9; void solve() { int m, k; cin >> m >> k; vi cnt(k + 1); rep(i, 1, k + 1) { cnt[i] = nxt(); } int mx = *max_element(all(cnt)); int mxid = -1; rep(i, 1, k + 1) if (cnt[i] == mx) mxid = i; int lo = 1, hi = 200005; while (lo < hi) { int mid = (lo + hi) / 2; ll one = 1LL * mid * mid - 1LL * (mid / 2) * (mid / 2); ll two = 1LL * mid * ((mid + 1) / 2); if (one >= m && two >= mx) { hi = mid; } else { lo = mid + 1; } } int n = lo; vvi a(n + 1, vi(n + 1)); vpi filling_order; rep(i, 1, k + 1) filling_order.pb({cnt[i], i}); sort(all(filling_order)); reverse(all(filling_order)); vi order; for (auto it : filling_order) { rep(i, 0, it.fi) order.pb(it.se); } assert(sz(order) == m); int ptr = 0; int done = 0; for (int row = 2; row <= n; row += 2) { for (int col = 1; col <= n; col += 2) { if (done >= mx) break; a[row][col] = order[ptr++]; done++; } } if (done < mx) { for (int row = 1; row <= n; row += 2) { for (int col = 1; col <= n; col += 2) { if (done >= mx) break; a[row][col] = order[ptr++]; done++; } } } else { for (int row = 2; row <= n; row += 2) for (int col = 1; col <= n; col += 2) { if (ptr >= m) break; if (a[row][col] == 0) a[row][col] = order[ptr++]; } } //all reds are filled //fill all non-filled for (int row = 1; row <= n; row++) { int add = 2; if (row % 2 == 1) { add = 1; } for (int col = 1; col <= n; col += add) { if (a[row][col] == 0 && ptr < m) { a[row][col] = order[ptr++]; } } } cout << n << endl; for (int row = 1; row <= n; row++) { for (int col = 1; col <= n; col++) { cout << a[row][col] << ; } cout << endl; } flush(); for (int row = 1; row <= n; row++) for (int col = 1; col <= n; col++) { debug(row, col); if (row + 1 <= n && col + 1 <= n && a[row][col] != 0 && a[row + 1][col + 1] != 0) assert(a[row][col] != a[row + 1][col + 1]); if (row + 1 <= n && col - 1 >= 1 && a[row][col] != 0 && a[row + 1][col - 1] != 0) assert(a[row][col] != a[row + 1][col - 1]); if (row + 1 <= n && col + 1 <= n) assert(a[row][col] == 0 or a[row][col + 1] == 0 or a[row + 1][col] == 0 or a[row + 1][col + 1] == 0); } } int32_t main(){ // setIO( trapped ); ios_base::sync_with_stdio(false); cin.tie(NULL); cout << fixed << setprecision(10); int T = 1; cin >> T; for (int tc = 1; tc <= T; tc++) { // cout << Case # << tc << : ; solve(); } } |
#include <bits/stdc++.h> using namespace std; mt19937_64 random_num( chrono::high_resolution_clock::now().time_since_epoch().count()); const int MOD = 1000000007; const int inf = 2000000000; const int mod = 1007050321; const double e = 0.000001; const int N = 200005; const bool aut = 788480; const int base = 521; int n, m, p, b[N], a[N]; int poww(int n, int a) { if (n == 1) return a; if (n == 0) return 0; int t = poww(n / 2, a); t = 1LL * t * t % MOD; if (n & 1) t = 1LL * t * a % MOD; return t; } int main() { ios_base ::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m >> p; vector<int> pack; for (int i = 1; i <= n; ++i) cin >> a[i], pack.push_back(a[i]); for (int i = 1; i <= m; ++i) cin >> b[i], pack.push_back(b[i]); sort((pack).begin(), (pack).end()); for (int i = 1; i <= n; ++i) a[i] = lower_bound((pack).begin(), (pack).end(), a[i]) - pack.begin() + 1; for (int i = 1; i <= m; ++i) b[i] = lower_bound((pack).begin(), (pack).end(), b[i]) - pack.begin() + 1; vector<int> ans; long long S = 0, T = 1; for (int i = 1; i <= m; ++i) S += b[i], T = 1LL * T * b[i] % MOD; for (int i = 1; i <= p; ++i) { long long sum = 0; int mul = 1; if ((n - i) / p < m - 1) break; for (int j = 0; j <= m - 1; ++j) { sum += a[i + j * p]; mul = 1LL * mul * a[i + j * p] % MOD; } if (sum == S && mul == T) ans.push_back(i); for (int j = m; i + j * p <= n; ++j) { sum += a[i + j * p] - a[i + (j - m) * p]; mul = 1LL * mul * poww(MOD - 2, a[i + (j - m) * p]) % MOD * a[i + j * p] % MOD; if (mul == T && sum == S) ans.push_back(i + (j - m + 1) * p); } } sort((ans).begin(), (ans).end()); cout << ans.size() << n ; for (int v : ans) cout << v << ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; vector<long long> t(n), x(n); for (int i = 0; i < n; i++) { cin >> t[i] >> x[i]; } long long start = 0, end = 0, from = 0, to = 0, ans = 0; for (int i = 0; i < n; i++) { if (end <= t[i]) { start = t[i]; end = t[i] + llabs(to - x[i]); from = to; to = x[i]; } if (min(from, to) <= x[i] && max(from, to) >= x[i]) { long long arrival = start + abs(from - x[i]); if (t[i] <= arrival && (i == n - 1 ? true : (arrival <= t[i + 1]))) { ans++; } } } cout << ans << n ; } return 0; } |
module opicorv32_memif_wrap (
mem_do_wdata,
mem_do_rdata,
mem_do_prefetch,
mem_wordsize,
mem_rdata,
mem_do_rinst,
mem_ready,
next_pc,
reg_op2,
reg_op1,
resetn,
clk,
mem_done,
mem_valid,
mem_instr,
mem_addr,
mem_wdata,
mem_wstrb,
mem_rdata_latched,
mem_rdata_q,
mem_rdata_word,
mem_la_read,
mem_la_write,
mem_la_addr,
mem_la_wdata,
mem_la_wstrb
);
input mem_do_wdata;
input mem_do_rdata;
input mem_do_prefetch;
input [1:0] mem_wordsize;
input [31:0] mem_rdata;
input mem_do_rinst;
input mem_ready;
input [31:0] next_pc;
input [31:0] reg_op2;
input [31:0] reg_op1;
input resetn;
input clk;
output mem_done;
output mem_valid;
output mem_instr;
output [31:0] mem_addr;
output [31:0] mem_wdata;
output [3:0] mem_wstrb;
output [31:0] mem_rdata_latched;
output [31:0] mem_rdata_q;
output [31:0] mem_rdata_word;
output mem_la_read;
output mem_la_write;
output [31:0] mem_la_addr;
output [31:0] mem_la_wdata;
output [3:0] mem_la_wstrb;
/* signal declarations */
wire [3:0] _1515;
wire [3:0] _1501;
wire [3:0] compare_mem_la_wstrb;
wire [3:0] _1517;
wire [31:0] _1518;
wire [31:0] _1502;
wire [31:0] compare_mem_la_wdata;
wire [31:0] _1520;
wire [31:0] _1521;
wire [31:0] _1503;
wire [31:0] compare_mem_la_addr;
wire [31:0] _1523;
wire _1524;
wire _1504;
wire compare_mem_la_write;
wire _1526;
wire _1527;
wire _1505;
wire compare_mem_la_read;
wire _1529;
wire [31:0] _1530;
wire [31:0] _1506;
wire [31:0] compare_mem_rdata_word;
wire [31:0] _1532;
wire [31:0] _1533;
wire [31:0] _1507;
wire [31:0] compare_mem_rdata_q;
wire [31:0] _1535;
wire [31:0] _1536;
wire [31:0] _1508;
wire [31:0] compare_mem_rdata_latched;
wire [31:0] _1538;
wire [3:0] _1539;
wire [3:0] _1509;
wire [3:0] compare_mem_wstrb;
wire [3:0] _1541;
wire [31:0] _1542;
wire [31:0] _1510;
wire [31:0] compare_mem_wdata;
wire [31:0] _1544;
wire [31:0] _1545;
wire [31:0] _1511;
wire [31:0] compare_mem_addr;
wire [31:0] _1547;
wire _1548;
wire _1512;
wire compare_mem_instr;
wire _1550;
wire _1551;
wire _1513;
wire compare_mem_valid;
wire _1553;
wire [236:0] _1498;
wire _1554;
wire [236:0] _1500;
wire _1514;
wire compare_mem_done;
wire _1556;
/* logic */
assign _1515 = _1498[236:233];
assign _1501 = _1500[236:233];
assign compare_mem_la_wstrb = _1501 ^ _1515;
assign _1517 = compare_mem_la_wstrb ^ _1515;
assign _1518 = _1498[232:201];
assign _1502 = _1500[232:201];
assign compare_mem_la_wdata = _1502 ^ _1518;
assign _1520 = compare_mem_la_wdata ^ _1518;
assign _1521 = _1498[200:169];
assign _1503 = _1500[200:169];
assign compare_mem_la_addr = _1503 ^ _1521;
assign _1523 = compare_mem_la_addr ^ _1521;
assign _1524 = _1498[168:168];
assign _1504 = _1500[168:168];
assign compare_mem_la_write = _1504 ^ _1524;
assign _1526 = compare_mem_la_write ^ _1524;
assign _1527 = _1498[167:167];
assign _1505 = _1500[167:167];
assign compare_mem_la_read = _1505 ^ _1527;
assign _1529 = compare_mem_la_read ^ _1527;
assign _1530 = _1498[166:135];
assign _1506 = _1500[166:135];
assign compare_mem_rdata_word = _1506 ^ _1530;
assign _1532 = compare_mem_rdata_word ^ _1530;
assign _1533 = _1498[134:103];
assign _1507 = _1500[134:103];
assign compare_mem_rdata_q = _1507 ^ _1533;
assign _1535 = compare_mem_rdata_q ^ _1533;
assign _1536 = _1498[102:71];
assign _1508 = _1500[102:71];
assign compare_mem_rdata_latched = _1508 ^ _1536;
assign _1538 = compare_mem_rdata_latched ^ _1536;
assign _1539 = _1498[70:67];
assign _1509 = _1500[70:67];
assign compare_mem_wstrb = _1509 ^ _1539;
assign _1541 = compare_mem_wstrb ^ _1539;
assign _1542 = _1498[66:35];
assign _1510 = _1500[66:35];
assign compare_mem_wdata = _1510 ^ _1542;
assign _1544 = compare_mem_wdata ^ _1542;
assign _1545 = _1498[34:3];
assign _1511 = _1500[34:3];
assign compare_mem_addr = _1511 ^ _1545;
assign _1547 = compare_mem_addr ^ _1545;
assign _1548 = _1498[2:2];
assign _1512 = _1500[2:2];
assign compare_mem_instr = _1512 ^ _1548;
assign _1550 = compare_mem_instr ^ _1548;
assign _1551 = _1498[1:1];
assign _1513 = _1500[1:1];
assign compare_mem_valid = _1513 ^ _1551;
assign _1553 = compare_mem_valid ^ _1551;
picorv32_memif
the_picorv32_memif
( .clk(clk), .resetn(resetn), .reg_op1(reg_op1), .reg_op2(reg_op2), .next_pc(next_pc), .mem_ready(mem_ready), .mem_do_rinst(mem_do_rinst), .mem_rdata(mem_rdata), .mem_wordsize(mem_wordsize), .mem_do_prefetch(mem_do_prefetch), .mem_do_rdata(mem_do_rdata), .mem_do_wdata(mem_do_wdata), .mem_la_wstrb(_1498[236:233]), .mem_la_wdata(_1498[232:201]), .mem_la_addr(_1498[200:169]), .mem_la_write(_1498[168:168]), .mem_la_read(_1498[167:167]), .mem_rdata_word(_1498[166:135]), .mem_rdata_q(_1498[134:103]), .mem_rdata_latched(_1498[102:71]), .mem_wstrb(_1498[70:67]), .mem_wdata(_1498[66:35]), .mem_addr(_1498[34:3]), .mem_instr(_1498[2:2]), .mem_valid(_1498[1:1]), .mem_done(_1498[0:0]) );
assign _1554 = _1498[0:0];
opicorv32_memif
the_opicorv32_memif
( .clk(clk), .resetn(resetn), .reg_op1(reg_op1), .reg_op2(reg_op2), .next_pc(next_pc), .mem_ready(mem_ready), .mem_do_rinst(mem_do_rinst), .mem_rdata(mem_rdata), .mem_wordsize(mem_wordsize), .mem_do_prefetch(mem_do_prefetch), .mem_do_rdata(mem_do_rdata), .mem_do_wdata(mem_do_wdata), .mem_la_wstrb(_1500[236:233]), .mem_la_wdata(_1500[232:201]), .mem_la_addr(_1500[200:169]), .mem_la_write(_1500[168:168]), .mem_la_read(_1500[167:167]), .mem_rdata_word(_1500[166:135]), .mem_rdata_q(_1500[134:103]), .mem_rdata_latched(_1500[102:71]), .mem_wstrb(_1500[70:67]), .mem_wdata(_1500[66:35]), .mem_addr(_1500[34:3]), .mem_instr(_1500[2:2]), .mem_valid(_1500[1:1]), .mem_done(_1500[0:0]) );
assign _1514 = _1500[0:0];
assign compare_mem_done = _1514 ^ _1554;
assign _1556 = compare_mem_done ^ _1554;
/* aliases */
/* output assignments */
assign mem_done = _1556;
assign mem_valid = _1553;
assign mem_instr = _1550;
assign mem_addr = _1547;
assign mem_wdata = _1544;
assign mem_wstrb = _1541;
assign mem_rdata_latched = _1538;
assign mem_rdata_q = _1535;
assign mem_rdata_word = _1532;
assign mem_la_read = _1529;
assign mem_la_write = _1526;
assign mem_la_addr = _1523;
assign mem_la_wdata = _1520;
assign mem_la_wstrb = _1517;
endmodule
|
#include <bits/stdc++.h> template <typename T> inline void read(T &x) { x = 0; register char ch; register bool fl = 0; while (ch = getchar(), ch < 48 || 57 < ch) fl ^= ch == - ; x = (ch & 15); while (ch = getchar(), 47 < ch && ch < 58) x = (x << 1) + (x << 3) + (ch & 15); if (fl) x = -x; } template <typename T> inline void readc(T &x) { while (x = getchar(), !islower(x) && !isupper(x)) ; } template <typename T> inline void print(T x, char c = ) { static int buf[40]; if (x == 0) { putchar( 0 ); putchar(c); return; } if (x < 0) putchar( - ), x = -x; for (buf[0] = 0; x; x /= 10) buf[++buf[0]] = x % 10 + 48; while (buf[0]) putchar((char)buf[buf[0]--]); putchar(c); } const int maxn = 100010; int n, m, x, ans; int c[maxn], f[maxn][20], cnt[maxn], dp[maxn]; long long s, a[maxn], g[maxn][20], sum[maxn]; int tot = 2, hed[maxn], to[maxn << 1], nxt[maxn << 1]; inline void add_edge(int u, int v) { nxt[tot] = hed[u], to[tot] = v, hed[u] = tot++; nxt[tot] = hed[v], to[tot] = u, hed[v] = tot++; } void dfs1(int u) { for (int i = hed[u], v = to[i]; i; i = nxt[i], v = to[i]) if (v ^ f[u][0]) { f[v][0] = u; g[v][0] = a[u]; dfs1(v); } } int dfs2(int u) { int max = 0; for (int i = hed[u], v = to[i]; i; i = nxt[i], v = to[i]) if (v ^ f[u][0]) { max = std::max(max, dfs2(v)); } if (!max) { ans++; max = dp[u]; } return max - 1; } int main() { read(n), read(m), read(s); for (int i = 1; i <= n; i++) { read(a[i]); if (a[i] > s) { puts( -1 ); return 0; } } for (int i = 2; i <= n; i++) { read(x); add_edge(x, i); } dfs1(1); for (int i = 1; i < 20; i++) for (int j = 1; j <= n; j++) { f[j][i] = f[f[j][i - 1]][i - 1]; g[j][i] = g[f[j][i - 1]][i - 1] + g[j][i - 1]; } for (int k = 1, u = k; k <= n; k++, u = k) { int stp = 1, sum = a[u]; for (int i = 19; i >= 0; i--) if ((stp + (1 << i)) <= m && (sum + g[u][i]) <= s && f[u][i]) { stp += 1 << i; sum += g[u][i]; u = f[u][i]; } dp[k] = stp; } dfs2(1); print(ans, n ); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02/12/2015 03:26:51 PM
// Design Name:
// Module Name: // Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module XADCdemo(
input CLK100MHZ,
input vauxp2,
input vauxn2,
input vauxp3,
input vauxn3,
input vauxp10,
input vauxn10,
input vauxp11,
input vauxn11,
input [1:0] sw,
output reg [15:0] LED,
output [7:0] an,
output dp,
output [6:0] seg
);
wire enable;
wire ready;
wire [15:0] data;
reg [6:0] Address_in;
reg [32:0] decimal;
reg [3:0] dig0;
reg [3:0] dig1;
reg [3:0] dig2;
reg [3:0] dig3;
reg [3:0] dig4;
reg [3:0] dig5;
reg [3:0] dig6;
//xadc instantiation connect the eoc_out .den_in to get continuous conversion
xadc_wiz_0 XLXI_7 (.daddr_in(Address_in), //addresses can be found in the artix 7 XADC user guide DRP register space
.dclk_in(CLK100MHZ),
.den_in(enable),
.di_in(),
.dwe_in(),
.busy_out(),
.vauxp2(vauxp2),
.vauxn2(vauxn2),
.vauxp3(vauxp3),
.vauxn3(vauxn3),
.vauxp10(vauxp10),
.vauxn10(vauxn10),
.vauxp11(vauxp11),
.vauxn11(vauxn11),
.vn_in(),
.vp_in(),
.alarm_out(),
.do_out(data),
.reset_in(),
.eoc_out(enable),
.channel_out(),
.drdy_out(ready));
//led visual dmm
always @( posedge(CLK100MHZ))
begin
if(ready == 1'b1)
begin
case (data[15:12])
1: LED <= 16'b11;
2: LED <= 16'b111;
3: LED <= 16'b1111;
4: LED <= 16'b11111;
5: LED <= 16'b111111;
6: LED <= 16'b1111111;
7: LED <= 16'b11111111;
8: LED <= 16'b111111111;
9: LED <= 16'b1111111111;
10: LED <= 16'b11111111111;
11: LED <= 16'b111111111111;
12: LED <= 16'b1111111111111;
13: LED <= 16'b11111111111111;
14: LED <= 16'b111111111111111;
15: LED <= 16'b1111111111111111;
default: LED <= 16'b1;
endcase
end
end
reg [32:0] count;
//binary to decimal conversion
always @ (posedge(CLK100MHZ))
begin
if(count == 10000000)begin
decimal = data >> 4;
//looks nicer if our max value is 1V instead of .999755
if(decimal >= 4093)
begin
dig0 = 0;
dig1 = 0;
dig2 = 0;
dig3 = 0;
dig4 = 0;
dig5 = 0;
dig6 = 1;
count = 0;
end
else
begin
decimal = decimal * 250000;
decimal = decimal >> 10;
dig0 = decimal % 10;
decimal = decimal / 10;
dig1 = decimal % 10;
decimal = decimal / 10;
dig2 = decimal % 10;
decimal = decimal / 10;
dig3 = decimal % 10;
decimal = decimal / 10;
dig4 = decimal % 10;
decimal = decimal / 10;
dig5 = decimal % 10;
decimal = decimal / 10;
dig6 = decimal % 10;
decimal = decimal / 10;
count = 0;
end
end
count = count + 1;
end
always @(posedge(CLK100MHZ))
begin
case(sw)
0: Address_in <= 8'h12;
1: Address_in <= 8'h13;
2: Address_in <= 8'h1a;
3: Address_in <= 8'h1b;
endcase
end
DigitToSeg segment1(.in1(dig0),
.in2(dig1),
.in3(dig2),
.in4(dig3),
.in5(dig4),
.in6(dig5),
.in7(dig6),
.in8(),
.mclk(CLK100MHZ),
.an(an),
.dp(dp),
.seg(seg));
endmodule
|
#include <bits/stdc++.h> template <typename T> void rd(T& x) { long long f = 0, c; while ((c = getchar()) < 48 || 57 < c) f ^= !(c ^ 45); x = (c & 15); while (47 < (c = getchar()) && c < 58) x = x * 10 + (c & 15); if (f) x = -x; } template <typename T> inline void pt(T x) { if (x < 0) x = -x, putchar( - ); if (x > 9) pt(x / 10); putchar(x % 10 + 48); } template <typename T> inline void pt(T x, long long c) { pt(x), putchar(c); } template <typename T> inline T max(const T& x, const T& y) { return x < y ? y : x; } template <typename T> inline T min(const T& x, const T& y) { return x < y ? x : y; } const long long N = 2005, P = 1000000007; long long n, m, f[2][N][N], sum[N][N]; char s[N][N]; long long getsum(long long a, long long b, long long c, long long d) { if (a > c || b > d) return 0; return sum[c][d] - sum[c][b - 1] - sum[a - 1][d] + sum[a - 1][b - 1]; } long long getf0(long long a, long long b, long long c, long long d) { if (a > c || b > d) return 0; return f[0][c][d] - f[0][c][b - 1] - f[0][a - 1][d] + f[0][a - 1][b - 1]; } long long getf1(long long a, long long b, long long c, long long d) { if (a > c || b > d) return 0; return f[1][c][d] - f[1][c][b - 1] - f[1][a - 1][d] + f[1][a - 1][b - 1]; } signed main() { rd(n), rd(m); for (long long i = (1); i <= (n); ++i) scanf( %s , s[i] + 1); if (s[n][m] == R ) { puts( 0 ); return 0; } if (n == 1 && m == 1) { puts( 1 ); return 0; } for (long long i = (1); i <= (n); ++i) for (long long j = (1); j <= (m); ++j) sum[i][j] = sum[i][j - 1] + sum[i - 1][j] - sum[i - 1][j - 1] + (s[i][j] == R ); f[0][1][1] = 1; f[1][1][1] = 1; for (long long i = (1); i <= (n); ++i) for (long long j = (1); j <= (m); ++j) { long long l = 1, r = i, ans = i; while (l <= r) { long long mid = (l + r) >> 1; if (getsum(mid + 1, j, n, j) <= n - i) ans = mid, r = mid - 1; else l = mid + 1; } (f[1][i][j] += getf0(ans, j, i - 1, j)) %= P; l = 1, r = j, ans = j; while (l <= r) { long long mid = (l + r) >> 1; if (getsum(i, mid + 1, i, m) <= m - j) ans = mid, r = mid - 1; else l = mid + 1; } (f[0][i][j] += getf1(i, ans, i, j - 1)) %= P; (f[0][i][j] += f[0][i][j - 1] + f[0][i - 1][j] - f[0][i - 1][j - 1]) %= P; (f[1][i][j] += f[1][i][j - 1] + f[1][i - 1][j] - f[1][i - 1][j - 1]) %= P; } pt(((getf0(n, m, n, m) + getf1(n, m, n, m)) % P + P) % P, n ); return 0; } |
#include <bits/stdc++.h> int ex[] = {1, -1, 0, 0}; int wye[] = {0, 0, 1, -1}; using namespace std; vector<int> vt[10005]; bool visit[10005]; int n, x, y, an; void dfs(int node) { if (visit[node]) return; visit[node] = true; int siz = vt[node].size(); int tmp; for (int i = 0; i < siz; i++) { tmp = vt[node][i]; if (visit[tmp]) continue; dfs(tmp); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &x); vt[i].push_back(x); vt[x].push_back(i); } for (int i = 1; i <= n; i++) { if (visit[i]) continue; dfs(i); an++; } printf( %d n , an); return 0; } |
#include <bits/stdc++.h> using namespace std; int n; pair<int, int> arr[100000 + 5]; int main() { cin >> n; int L = 0, R = 0; for (int i = 1; i <= n; i++) { cin >> arr[i].first >> arr[i].second; L += arr[i].first; R += arr[i].second; } int ans = abs(L - R); int id = 0; for (int i = 1; i <= n; i++) { if (ans < abs(L - R + 2 * (arr[i].second - arr[i].first))) { ans = abs(L - R + 2 * (arr[i].second - arr[i].first)); id = i; } } cout << id << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_BEHAVIORAL_V
`define SKY130_FD_SC_LP__NOR2_BEHAVIORAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int n, k, num[100001], mxn, contador; int main() { cin >> n; for (int i = 0; i < n; i++) { cin >> num[i]; } if (n == 1) { cout << 1; return 0; } for (int i = 2; i < n; i++) { if (num[i] == num[i - 1] + num[i - 2]) contador++; else { mxn = max(mxn, contador); contador = 0; } } if (contador < mxn) cout << mxn + 2; else cout << contador + 2; } |
#include <bits/stdc++.h> using namespace std; map<long long, int> mp; int n; int main() { scanf( %d , &n); int t; long long s = 0; for (int i = 1; i <= n; i++) { scanf( %d , &t); s += t; mp[s]++; } int ans = 0; map<long long, int>::iterator it; for (it = mp.begin(); it != mp.end(); it++) { ans = max(ans, it->second); } printf( %d n , n - ans); return 0; } |
#include <bits/stdc++.h> using namespace std; static const double EPS = 1e-5; bool board[8][8]; const int dx[8] = {1, 2, 2, 1, -1, -2, -2, -1}; const int dy[8] = {2, 1, -1, -2, -2, -1, 1, 2}; void check(int x, int y, int n) { board[x][y] = true; if (n == 1) { for (int i = (0); i < (int)(8); ++i) { board[i][y] = true; board[x][i] = true; } } for (int r = (0); r < (int)(8); ++r) { if (x + dx[r] < 8 && x + dx[r] >= 0) { if (y + dy[r] < 8 && y + dy[r] >= 0) { board[x + dx[r]][y + dy[r]] = true; } } } } int main(void) { int x, y, count = 0; string line; cin >> line; x = line[0] - a ; y = line[1] - 1 ; check(x, y, 1); cin >> line; x = line[0] - a ; y = line[1] - 1 ; check(x, y, 2); for (int x = (0); x < (int)(8); ++x) { for (int y = (0); y < (int)(8); ++y) { if (board[x][y]) count++; } } cout << 64 - count << endl; return 0; } |
/*
* Copyright 2020-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
// A model of a clock multiplexer with two clock inputs, one clock output and
// a select input.
(* whitebox *)
module GMUX (IP, IC, IS0, IZ);
// 1st clock input
(* CLOCK *)
input wire IP;
// 2nd clock input
(* CLOCK *)
input wire IC;
// Select input
input wire IS0;
// Clock output (has to be defined as a regular output port)
(* DELAY_CONST_IP="1e-10" *)
(* DELAY_CONST_IC="2e-10" *)
(* DELAY_CONST_IS0="3e-10" *)
(* COMB_INCLUDE_CLOCKS *)
output wire IZ;
// Behavioral model:
assign IZ = IS0 ? IC : IP;
endmodule
|
`timescale 1 ps / 1 ps
module daala_zynq_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
daala_zynq daala_zynq_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2017/11/29 22:40:09
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_adder(
input clk,
input button,
output [1:0] C,
output [3:0] Q
);
reg [3:0]Q;
reg [1:0]C;
reg before;
wire D;
wire [3:0]inD;
wire [3:0]tempQ;
wire [1:0]tempC;
always@(posedge clk)
begin
if(~before&button)
C[1:0]<=tempC[1:0];
else
Q[3:0]<=tempQ[3:0];
before<=button;
end
assign inD[0]=~(Q[0]|Q[1]|Q[2]);
assign inD[1]=~(Q[3])|(Q[3]&~Q[2]&~Q[1]&Q[0]);
assign inD[2]=~(Q[3])|(Q[3]&Q[2]&~Q[1]&~Q[0]);
assign inD[3]=(Q[0]^Q[3])|(~Q[0]&~Q[1]&~Q[2]&~Q[3]);
assign D=(inD[0]&~C[0]&~C[1])|(inD[1]&C[0]&~C[1])|(inD[2]&~C[0]&C[1])|(inD[3]&C[0]&C[1]);
assign tempQ[0]=D;
assign tempQ[1]=Q[0];
assign tempQ[2]=Q[1];
assign tempQ[3]=Q[2];
assign tempC[0]=~C[0];
assign tempC[1]=C[0]^C[1];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:27:42 05/05/2015
// Design Name:
// Module Name: key_Processor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module key_Processor(
select,
lefto,
righto,
key
);
input select;
output [28:1] lefto;
output [28:1] righto;
wire select;
//wire [28:1] lefto;
//wire [28:1] righto;
reg [56:1] output_permutation;
input [64:1] key;
assign righto= output_permutation[28:1];
assign lefto = output_permutation[56:29];
always@(select or key)
begin
if(select == 1)
begin
output_permutation[1] <= key[57];
output_permutation[2] <= key[49];
output_permutation[3] <= key[41];
output_permutation[4] <= key[33];
output_permutation[5] <= key[25];
output_permutation[6] <= key[17];
output_permutation[7] <= key[9];
output_permutation[8] <= key[1];
output_permutation[9] <= key[58];
output_permutation[10] <= key[50];
output_permutation[11] <= key[42];
output_permutation[12] <= key[34];
output_permutation[13] <= key[26];
output_permutation[14] <= key[18];
output_permutation[15] <= key[10];
output_permutation[16] <= key[2];
output_permutation[17] <= key[59];
output_permutation[18] <= key[51];
output_permutation[19] <= key[43];
output_permutation[20] <= key[35];
output_permutation[21] <= key[27];
output_permutation[22] <= key[19];
output_permutation[23] <= key[11];
output_permutation[24] <= key[3];
output_permutation[25] <= key[60];
output_permutation[26] <= key[52];
output_permutation[27] <= key[44];
output_permutation[28] <= key[36];
output_permutation[29] <= key[63];
output_permutation[30] <= key[55];
output_permutation[31] <= key[47];
output_permutation[32] <= key[39];
output_permutation[33] <= key[31];
output_permutation[34] <= key[23];
output_permutation[35] <= key[15];
output_permutation[36] <= key[7];
output_permutation[37] <= key[62];
output_permutation[38] <= key[54];
output_permutation[39] <= key[46];
output_permutation[40] <= key[38];
output_permutation[41] <= key[30];
output_permutation[42] <= key[22];
output_permutation[43] <= key[14];
output_permutation[44] <= key[6];
output_permutation[45] <= key[61];
output_permutation[46] <= key[53];
output_permutation[47] <= key[45];
output_permutation[48] <= key[37];
output_permutation[49] <= key[29];
output_permutation[50] <= key[21];
output_permutation[51] <= key[13];
output_permutation[52] <= key[5];
output_permutation[53] <= key[28];
output_permutation[54] <= key[20];
output_permutation[55] <= key[12];
output_permutation[56] <= key[4];
end
else
begin
output_permutation <= 64'bx;
end
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_sram_data (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
)
;
inout [ 15: 0] bidir_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire [ 15: 0] bidir_port;
wire clk_en;
reg [ 15: 0] data_dir;
wire [ 15: 0] data_in;
reg [ 15: 0] data_out;
wire [ 15: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 0)}} & data_in) |
({16 {(address == 1)}} & data_dir);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[15 : 0];
end
assign bidir_port[0] = data_dir[0] ? data_out[0] : 1'bZ;
assign bidir_port[1] = data_dir[1] ? data_out[1] : 1'bZ;
assign bidir_port[2] = data_dir[2] ? data_out[2] : 1'bZ;
assign bidir_port[3] = data_dir[3] ? data_out[3] : 1'bZ;
assign bidir_port[4] = data_dir[4] ? data_out[4] : 1'bZ;
assign bidir_port[5] = data_dir[5] ? data_out[5] : 1'bZ;
assign bidir_port[6] = data_dir[6] ? data_out[6] : 1'bZ;
assign bidir_port[7] = data_dir[7] ? data_out[7] : 1'bZ;
assign bidir_port[8] = data_dir[8] ? data_out[8] : 1'bZ;
assign bidir_port[9] = data_dir[9] ? data_out[9] : 1'bZ;
assign bidir_port[10] = data_dir[10] ? data_out[10] : 1'bZ;
assign bidir_port[11] = data_dir[11] ? data_out[11] : 1'bZ;
assign bidir_port[12] = data_dir[12] ? data_out[12] : 1'bZ;
assign bidir_port[13] = data_dir[13] ? data_out[13] : 1'bZ;
assign bidir_port[14] = data_dir[14] ? data_out[14] : 1'bZ;
assign bidir_port[15] = data_dir[15] ? data_out[15] : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_dir <= 0;
else if (chipselect && ~write_n && (address == 1))
data_dir <= writedata[15 : 0];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, flag = 0; cin >> n >> m; char c; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> c; if (c == B || c == W || c == G ) continue; else flag = 1; } } if (flag == 0) cout << #Black&White << endl; else cout << #Color << endl; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_async_fifo
*/
module test_axis_async_frame_fifo;
// Parameters
parameter DEPTH = 512;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter LAST_ENABLE = 1;
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter PIPELINE_OUTPUT = 2;
parameter FRAME_FIFO = 1;
parameter USER_BAD_FRAME_VALUE = 1'b1;
parameter USER_BAD_FRAME_MASK = 1'b1;
parameter DROP_BAD_FRAME = 1;
parameter DROP_WHEN_FULL = 0;
// Inputs
reg async_rst = 0;
reg s_clk = 0;
reg m_clk = 0;
reg [7:0] current_test = 0;
reg [DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg [ID_WIDTH-1:0] s_axis_tid = 0;
reg [DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
wire s_status_overflow;
wire s_status_bad_frame;
wire s_status_good_frame;
wire m_status_overflow;
wire m_status_bad_frame;
wire m_status_good_frame;
initial begin
// myhdl integration
$from_myhdl(
async_rst,
s_clk,
m_clk,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
s_status_overflow,
s_status_bad_frame,
s_status_good_frame,
m_status_overflow,
m_status_bad_frame,
m_status_good_frame
);
// dump file
$dumpfile("test_axis_async_frame_fifo.lxt");
$dumpvars(0, test_axis_async_frame_fifo);
end
axis_async_fifo #(
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.LAST_ENABLE(LAST_ENABLE),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.PIPELINE_OUTPUT(PIPELINE_OUTPUT),
.FRAME_FIFO(FRAME_FIFO),
.USER_BAD_FRAME_VALUE(USER_BAD_FRAME_VALUE),
.USER_BAD_FRAME_MASK(USER_BAD_FRAME_MASK),
.DROP_BAD_FRAME(DROP_BAD_FRAME),
.DROP_WHEN_FULL(DROP_WHEN_FULL)
)
UUT (
// Common reset
.async_rst(async_rst),
// AXI input
.s_clk(s_clk),
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_clk(m_clk),
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser),
// Status
.s_status_overflow(s_status_overflow),
.s_status_bad_frame(s_status_bad_frame),
.s_status_good_frame(s_status_good_frame),
.m_status_overflow(m_status_overflow),
.m_status_bad_frame(m_status_bad_frame),
.m_status_good_frame(m_status_good_frame)
);
endmodule
|
module fifo # (parameter abits = 400, dbits = 1)(
input reset, clock,
input rd, wr,
input [dbits-1:0] din,
output [dbits-1:0] dout,
output empty,
output full,
output reg ledres
);
wire db_wr;
wire db_rd;
reg dffw1, dffr1;
reg [dbits-1:0] out;
initial ledres = 0;
reg [1:0] count;
reg [1:0] count1;
//always @ (posedge clock) dffw1 <= ~wr;
//always @ (posedge clock) dffw2 <= rd;
assign db_wr = dffw1; //monostable multivibrator to detect only one pulse of the button
//always @ (posedge clock) dffr1 <= rd;
//always @ (posedge clock) dffr2 <= dffr1;
assign db_rd = dffr1; //monostable multivibrator to detect only one pulse of the button
reg [dbits-1:0] regarray[2**abits-1:0]; //number of words in fifo = 2^(number of address bits)
reg [abits-1:0] wr_reg, wr_next, wr_succ; //points to the register that needs to be written to
reg [abits-1:0] rd_reg, rd_next, rd_succ; //points to the register that needs to be read from
reg full_reg, empty_reg, full_next, empty_next;
assign wr_en = db_wr & ~full; //only write if write signal is high and fifo is not full
always @ (posedge clock)//only write
begin
if(wr && ~rd)
begin
if(count)
begin
//dffr1<=0;
dffw1<=0;
count<=count+1;
end
else
begin
//dffr1<=0;
dffw1<=1;
count<=0;
end
end
else dffw1<=0;
end
always @ (posedge clock)//only read
begin
if(rd && ~wr)
begin
if(count1)
begin
//dffw1<=0;
dffr1<=0;
count1<=count1+1;
end
else
begin
//dffw1<=0;
dffr1<=1;
count1<=0;
end
end
else dffr1<=0;
end
//always block for write operation
always @ (posedge clock)
begin
if(wr_en)
regarray[wr_reg] <= din; //at wr_reg location of regarray store what is given at din
end
//always block for read operation
always @ (posedge clock)
begin
if(db_rd)
out <= regarray[rd_reg];
end
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
wr_reg <= 0;
rd_reg <= 0;
full_reg <= 1'b0;
empty_reg <= 1'b1;
ledres=0;
end
else
begin
wr_reg <= wr_next; //created the next registers to avoid the error of mixing blocking and non blocking assignment to the same signal
rd_reg <= rd_next;
full_reg <= full_next;
empty_reg <= empty_next;
ledres=1;
end
end
always @(clock)
begin
wr_succ = wr_reg + 1; //assigned to new value as wr_next cannot be tested for in same always block
rd_succ = rd_reg + 1; //assigned to new value as rd_next cannot be tested for in same always block
wr_next = wr_reg; //defaults state stays the same
rd_next = rd_reg; //defaults state stays the same
full_next = full_reg; //defaults state stays the same
empty_next = empty_reg; //defaults state stays the same
case({db_wr,db_rd})
//2'b00: do nothing LOL..
2'b01: //read
begin
if(~empty) //if fifo is not empty continue
begin
rd_next = rd_succ;
full_next = 1'b0;
if(rd_succ == wr_reg) //all data has been read
empty_next = 1'b1; //its empty again
end
end
2'b10: //write
begin
if(~full) //if fifo is not full continue
begin
wr_next = wr_succ;
empty_next = 1'b0;
if(wr_succ == (2**abits-1)) //all registers have been written to
full_next = 1'b1; //its full now
end
end
2'b11: //read and write
begin
wr_next = wr_succ;
rd_next = rd_succ;
end
//no empty or full flag will be checked for or asserted in this state since data is being written to and read from together it can not get full in this state.
endcase
end
assign full = full_reg;
assign empty = empty_reg;
assign dout = out;
endmodule
|
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