text stringlengths 59 71.4k |
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#include <bits/stdc++.h> using namespace std; int main() { pair<long long, long long> a[1001]; a[0].second = 1; for (long long i = 1; i < 1001; i++) { a[i].first = i; if (i < 10) a[i].second = 1; else if (i < 100) a[i].second = 2; else if (i < 1000) a[i].second = 3; } long long n; cin >> n; long long count = 1; long long i = 1; while (count < n) { count += a[i].second; i++; } if (count == n) { long long temp = i; long long ans; while (temp != 0) { ans = temp % 10; temp = temp / 10; } cout << ans << endl; } else if (count > n) { i--; long long temp = a[i].first; long long flag = count - n - 1; while (flag > 0) { temp = temp / 10; flag--; } cout << temp % 10 << endl; } } |
#include <bits/stdc++.h> using namespace std; struct Act { int l, r; int mx; double pb; vector<Act *> son; static int dp_size; double dp[5005]; bool operator<(const Act &act) const { if (l < act.l) { return true; } else if (l > act.l) { return false; } else if (r > act.r) { return true; } return false; } bool contains(Act &act) { return act.l >= l && act.r <= r; } double p(int profit) { if (profit < 0) return 0.0; if (profit > dp_size) return 1.0; return dp[profit]; } }; int Act::dp_size = 0; int n, q; int *a; int **m; int *lg; Act act[5005]; void dfs(Act &act) { for (int i = 0; i < act.son.size(); i++) { dfs(*act.son[i]); } for (int i = 0; i <= Act::dp_size; i++) { act.dp[i] = 0.0; } for (int i = 0; i <= Act::dp_size; i++) { double p = (i == 0 ? 0.0 : act.pb); double np = 1.0 - act.pb; for (int j = 0; j < act.son.size(); j++) { Act *son = act.son[j]; p *= son->p(act.mx - son->mx + i - 1); np *= son->p(act.mx - son->mx + i); } act.dp[i] = p + np; } } int main() { cin >> n >> q; a = new int[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } lg = new int[n + 1]; lg[1] = 0; for (int i = 2; i <= n; i++) { lg[i] = lg[i / 2] + 1; } m = new int *[lg[n] + 1]; for (int i = 0; i <= lg[n]; i++) { m[i] = new int[n]; } for (int i = 0; i < n; i++) { m[0][i] = a[i]; } for (int i = 1; i <= lg[n]; i++) { int psz = 1 << (i - 1); int nsz = 1 << i; for (int j = 0; j + nsz <= n; j++) { m[i][j] = max(m[i - 1][j], m[i - 1][j + psz]); } } q++; for (int i = 0; i < q; i++) { if (i == q - 1) { act[i].l = 1; act[i].r = n; act[i].pb = 0.0; } else { cin >> act[i].l >> act[i].r >> act[i].pb; } act[i].l--, act[i].r--; int tlg = lg[act[i].r - act[i].l + 1]; int tsz = 1 << tlg; act[i].mx = max(m[tlg][act[i].l], m[tlg][act[i].r - tsz + 1]); } sort(act, act + q); Act::dp_size = q; for (int i = 1; i < q; i++) { int j = i - 1; while (!act[j].contains(act[i])) j--; act[j].son.push_back(act + i); } dfs(act[0]); double ans = 0.0; for (int i = 0; i <= Act::dp_size; i++) { ans += (act[0].mx + i) * (act[0].p(i) - act[0].p(i - 1)); } printf( %.8lf , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { int t, h, g; cin >> t; while (t--) { scanf( %d %d , &h, &g); int n = (1 << h) - 1, m = (1 << g) - 1; std::vector<pair<int, int> > a(1 << h); for (int i = 0; i < n; i++) { scanf( %d , &a[i].first); a[i].second = i + 1; } sort(a.begin(), a.end()); std::vector<int> notFree(n + 1, 0), taken(n + 1, 0); ll ans = 0LL; for (int i = 0; i < n; i++) { int where = a[i].second; while (where > m or notFree[where]) where = where >> 1; if (!where) continue; if (notFree[where << 1] == notFree[where << 1 | 1]) { notFree[where] = 1; ans += a[i].first; taken[a[i].second] = 1; } } printf( %lld n , ans); for (int i = n; i >= 1; i--) { if (!taken[i]) printf( %d , i); ; } puts( ); } return 0; } |
#include <bits/stdc++.h> const int mxn = 1e5; int cost[mxn][3], go[mxn][2], deg[mxn], path[mxn]; int color[mxn]; long long cc[3][3]; int main() { int n, u, a, b, c = 0; scanf( %d , &n); for (int j = 0; j < 3; ++j) for (int i = 1; i <= n; ++i) scanf( %d , &cost[i][j]); for (int i = 1; i < n; ++i) { scanf( %d%d , &a, &b); ++deg[a], ++deg[b]; go[a][0] ? go[a][1] = b : go[a][0] = b; go[b][0] ? go[b][1] = a : go[b][0] = a; } for (int i = 1; i <= n; ++i) { if (deg[i] == 1) ++c, u = i; if (deg[i] > 2) return 0 * printf( -1 ); } if (c != 2) return 0 * printf( -1 ); for (int i = 1, v = u, p = 0, pa; p != v; ++i, p = pa) { path[i] = pa = v; if (go[v][0] != p && go[v][0]) v = go[v][0]; else if (go[v][1] != p && go[v][1]) v = go[v][1]; } for (int i = 0; i < 3; ++i) { for (int j = 0; j < 3; ++j) if (i != j) { a = i, b = j; cc[i][j] = cost[path[1]][i] + cost[path[2]][j]; for (int k = 3; k <= n; ++k) { c = (3 - a - b) % 3; cc[i][j] += cost[path[k]][c]; a = b, b = c; } } } long long min_cost = (long long)1e18; for (int i = 0; i < 3; ++i) for (int j = 0; j < 3; ++j) if (i != j) if (min_cost > cc[i][j]) a = i, b = j, min_cost = cc[i][j]; color[path[1]] = a, color[path[2]] = b; for (int k = 3; k <= n; ++k) { c = (3 - a - b) % 3; color[path[k]] = c; a = b, b = c; } printf( %lld n , min_cost); for (int i = 1; i <= n; ++i) printf( %d , color[i] + 1); } |
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/13.0sp1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2013/03/07 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int a[200010], b[200010]; int nxt[200010]; void make_next() { int i = 0, j = -1; nxt[0] = -1; while (i < m) { if (j == -1 || b[i] == b[j]) { i++; j++; if (b[i] == b[j]) nxt[i] = nxt[j]; else nxt[i] = j; } else j = nxt[j]; } } int kmp() { int i = 0, j = 0; int cnt = 0; while (i < n) { if (a[i] == b[j]) { i++; j++; if (j == m) { cnt++; } } else { j = nxt[j]; if (j == -1) { i++; j = 0; } } } return cnt; } int main() { int i, j; while (cin >> n >> m) { for (i = 0; i < n; i++) cin >> a[i]; for (i = 0; i < m; i++) cin >> b[i]; if (n < m) { cout << 0 n ; continue; } else if (m == 1) { cout << n << endl; continue; } for (i = 0; i < n - 1; i++) a[i] = a[i + 1] - a[i]; for (i = 0; i < m - 1; i++) b[i] = b[i + 1] - b[i]; m--; n--; make_next(); cout << kmp() << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; using bigint = long long int; using vi = vector<int>; using vll = vector<long long int>; int cnt[200001]; int main() { int N, A; cin >> N >> A; for (int i = 0; i < N; i++) { int x; cin >> x; cnt[x]++; } int ans = 0; if (cnt[A] == 0) { ans++; cnt[A] = 1; } int left = 0, right = 0; for (int i = 1; i < A; i++) left += cnt[i]; for (int i = A + 1; i < 100001; i++) right += cnt[i]; if (left == right) { cout << ans << n ; return 0; } if (left > right) { if (right + cnt[A] - 1 >= left) cout << ans << n ; else cout << ans + left - (right + cnt[A] - 1) << n ; } else if (right > left) { if (left + cnt[A] - 1 >= right - 1) cout << ans << n ; else cout << ans + (right - 1) - (left + cnt[A] - 1) << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int ans, cnt; struct Node { Node *Left = NULL, *Right = NULL; int value, fix, sz = 1; long long sum[5] = {}; }; typedef Node *PNode; PNode root = NULL; inline int gts(PNode &cur) { if (cur == NULL) return 0; return cur->sz; } Node nodes[111111]; inline void Init(PNode &cur) { if (cur) { cur->sz = gts(cur->Left) + gts(cur->Right) + 1; int t = 0; if (cur->Left) { for (int i = 0; i < 5; ++i) cur->sum[i] = cur->Left->sum[i]; t = cur->Left->sz % 5; } else { for (int i = 0; i < 5; ++i) cur->sum[i] = 0; } cur->sum[t] += cur->value; t++; t %= 5; if (cur->Right) { for (int i = 0; i < 5; ++i) { int T = i + t; T %= 5; cur->sum[T] += cur->Right->sum[i]; } } } } inline void make(PNode a, PNode b, PNode &c) { if (!b or !a) { c = b ? b : a; return; } if (a->fix > b->fix) { make(a->Right, b, a->Right); c = a; } else { make(a, b->Left, b->Left); c = b; } Init(c); } inline void split(PNode t, PNode &a, PNode &b, int f) { if (!t) { a = b = NULL; return; } if (f < t->value) { split(t->Left, a, t->Left, f); b = t; } else { split(t->Right, t->Right, b, f); a = t; } Init(t); } inline void Insert(int val) { PNode a, b, c; split(root, a, c, val); nodes[cnt].value = val; nodes[cnt].fix = rand(); b = nodes + cnt++; Init(b); make(a, b, root); make(root, c, root); } inline void Delete(PNode &cur, int val) { if (cur->value == val) { make(cur->Left, cur->Right, cur); } else if (val < cur->value) { Delete(cur->Left, val); } else Delete(cur->Right, val); Init(cur); } inline int Find_Min(PNode cur) { while (cur->Left) cur = cur->Left; return cur->value; } inline int Find_Max(PNode cur) { while (cur->Right) cur = cur->Right; return cur->value; } int main() { ios_base::sync_with_stdio(false); int n, x, y, i, count = 0; string s; cin >> n; for (i = 0; i < n; ++i) { cin >> s; if (s == add ) { cin >> x; count++; Insert(x); } else if (s == del ) { cin >> x; count--; Delete(root, x); } else { if (!count) printf( %d n , 0); else printf( %I64d n , root->sum[2]); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int x, n, m, temp = 0; cin >> x >> n >> m; for (int i = 0; i <= n; i++) { if (x <= 10 * m) { temp = 1; break; } else x = x / 2 + 10; } if (temp == 1) cout << YES << endl; else cout << NO << endl; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__NOR4_BEHAVIORAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_BLACKBOX_V
`define SKY130_FD_SC_LS__INV_BLACKBOX_V
/**
* inv: Inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__inv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; set<pair<long long, long long> > S; set<pair<long long, long long> >::iterator it; set<pair<long long, long long> >::iterator it2; pair<long long, long long> temp; void intersect_yes(long long s, long long e) { if (S.empty()) return; for (it = S.begin(); it != S.end();) { if (it->first < s && it->second < s) S.erase(it++); else break; } if (S.empty()) return; bool finish = 0; for (it = --S.end(); !finish;) { if (it == S.begin()) finish = true; if (it->first > e) S.erase(it--); else break; } if (S.empty()) return; temp = *S.begin(); S.erase(temp); temp.first = max(s, temp.first); S.insert(temp); temp = *(--S.end()); S.erase(temp); temp.second = min(temp.second, e); S.insert(temp); } const long long big = 1LL << 55; void intersect_no(long long s, long long e) { it = S.lower_bound(make_pair(s, big)); if (it != S.begin()) it--; it2 = S.upper_bound(make_pair(e, big)); while (it != it2) { if (it->second < s) it++; else if (it->first < s) { if (it->second >= s && it->second <= e) { temp = *it; it++; S.erase(temp); S.insert(make_pair(temp.first, s - 1)); } else if (it->second > e) { temp = *it; it++; S.erase(temp); S.insert(make_pair(temp.first, s - 1)); S.insert(make_pair(e + 1, temp.second)); } } else if (it->first >= s && it->first <= e) { if (it->second <= e) { S.erase(it++); } else if (it->second > e) { temp = *it; it++; S.erase(temp); S.insert(make_pair(e + 1, temp.second)); } } } } int main() { int h, q, lvl, ans; long long l, r; scanf( %d%d , &h, &q); long long begining = 1LL << (h - 1), ending = (1LL << h) - 1; S.insert(make_pair(begining, ending)); for (int i = 0; i < q; i++) { scanf( %d%I64d%I64d%d , &lvl, &l, &r, &ans); long long left = l * (1LL << (h - lvl)), right = (r + 1) * (1LL << (h - lvl)) - 1; if (S.empty()) { printf( Game cheated! n ); return 0; } if (ans) intersect_yes(left, right); else intersect_no(left, right); } if (S.empty()) printf( Game cheated! n ); else if (S.size() == 1 && (*S.begin()).first == (*S.begin()).second) printf( %I64d n , (*S.begin()).first); else printf( Data not sufficient! n ); } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; char a[2 * n - 1][2 * n - 1]; int v = 0, k = n; for (int i = 0; i < n; i++, k--, v++) { for (int j = 0; j < k; j++) printf( ); for (int j = 0; j < v; j++) printf( %d , j); printf( %d , v); for (int j = v - 1; j >= 0; j--) printf( %d , j); printf( n ); } for (int i = 0; i < n; i++) printf( %d , i); printf( %d , n); for (int i = n - 1; i >= 0; i--) printf( %d , i); for (int i = 0, k = 1, v = n - 1; i < n; i++, k++, v--) { printf( n ); for (int j = 0; j < k; j++) printf( ); for (int j = 0; j < v; j++) printf( %d , j); printf( %d , v); for (int j = v - 1; j >= 0; j--) printf( %d , j); } return 0; } |
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/addsubcmp.v:1" *)
module AddSubCmp(AddOrSub_i, A_i, B_i, D_o, Carry_i, Carry_o, Zero_o, Sign_o, Overflow_o);
(* src = "../../verilog/addsubcmp.v:33" *)
wire [16:0] \$add$../../verilog/addsubcmp.v:33$7_Y ;
(* src = "../../verilog/addsubcmp.v:42" *)
wire \$eq$../../verilog/addsubcmp.v:42$11_Y ;
(* src = "../../verilog/addsubcmp.v:42" *)
wire \$ne$../../verilog/addsubcmp.v:42$12_Y ;
(* src = "../../verilog/addsubcmp.v:30" *)
wire [15:0] \$not$../../verilog/addsubcmp.v:30$2_Y ;
(* src = "../../verilog/addsubcmp.v:31" *)
wire \$not$../../verilog/addsubcmp.v:31$5_Y ;
(* src = "../../verilog/addsubcmp.v:23" *)
wire [16:0] A;
(* intersynth_conntype = "Word" *)
(* src = "../../verilog/addsubcmp.v:7" *)
input [15:0] A_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/addsubcmp.v:5" *)
input AddOrSub_i;
(* src = "../../verilog/addsubcmp.v:24" *)
wire [16:0] B;
(* intersynth_conntype = "Word" *)
(* src = "../../verilog/addsubcmp.v:9" *)
input [15:0] B_i;
(* src = "../../verilog/addsubcmp.v:26" *)
wire Carry;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/addsubcmp.v:13" *)
input Carry_i;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/addsubcmp.v:15" *)
output Carry_o;
(* src = "../../verilog/addsubcmp.v:27" *)
wire [15:0] D;
(* intersynth_conntype = "Word" *)
(* src = "../../verilog/addsubcmp.v:11" *)
output [15:0] D_o;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/addsubcmp.v:21" *)
output Overflow_o;
(* src = "../../verilog/addsubcmp.v:25" *)
wire [16:0] Result;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/addsubcmp.v:19" *)
output Sign_o;
(* intersynth_conntype = "Bit" *)
(* src = "../../verilog/addsubcmp.v:17" *)
output Zero_o;
(* src = "../../verilog/addsubcmp.v:33" *)
\$add #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010001),
.Y_WIDTH(32'b00000000000000000000000000010001)
) \$add$../../verilog/addsubcmp.v:33$7 (
.A({ 1'b0, A_i }),
.B(B),
.Y(\$add$../../verilog/addsubcmp.v:33$7_Y )
);
(* src = "../../verilog/addsubcmp.v:33" *)
\$add #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000010001)
) \$add$../../verilog/addsubcmp.v:33$8 (
.A(\$add$../../verilog/addsubcmp.v:33$7_Y ),
.B(Carry),
.Y({ Carry_o, D })
);
(* src = "../../verilog/addsubcmp.v:39" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/addsubcmp.v:39$9 (
.A(D),
.B(16'b0000000000000000),
.Y(Zero_o)
);
(* src = "../../verilog/addsubcmp.v:42" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/addsubcmp.v:42$11 (
.A(A_i[15]),
.B(B[15]),
.Y(\$eq$../../verilog/addsubcmp.v:42$11_Y )
);
(* src = "../../verilog/addsubcmp.v:42" *)
\$logic_and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$logic_and$../../verilog/addsubcmp.v:42$13 (
.A(\$eq$../../verilog/addsubcmp.v:42$11_Y ),
.B(\$ne$../../verilog/addsubcmp.v:42$12_Y ),
.Y(Overflow_o)
);
(* src = "../../verilog/addsubcmp.v:42" *)
\$ne #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$ne$../../verilog/addsubcmp.v:42$12 (
.A(D[15]),
.B(A_i[15]),
.Y(\$ne$../../verilog/addsubcmp.v:42$12_Y )
);
(* src = "../../verilog/addsubcmp.v:30" *)
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$not$../../verilog/addsubcmp.v:30$2 (
.A(B_i),
.Y(\$not$../../verilog/addsubcmp.v:30$2_Y )
);
(* src = "../../verilog/addsubcmp.v:31" *)
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$not$../../verilog/addsubcmp.v:31$5 (
.A(Carry_i),
.Y(\$not$../../verilog/addsubcmp.v:31$5_Y )
);
(* src = "../../verilog/addsubcmp.v:30" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000010001)
) \$ternary$../../verilog/addsubcmp.v:30$3 (
.A({ 1'b0, B_i }),
.B({ 1'b0, \$not$../../verilog/addsubcmp.v:30$2_Y }),
.S(AddOrSub_i),
.Y(B)
);
(* src = "../../verilog/addsubcmp.v:31" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$ternary$../../verilog/addsubcmp.v:31$6 (
.A(Carry_i),
.B(\$not$../../verilog/addsubcmp.v:31$5_Y ),
.S(AddOrSub_i),
.Y(Carry)
);
assign A = { 1'b0, A_i };
assign D_o = D;
assign Result = { Carry_o, D };
assign Sign_o = D[15];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int x; cin >> x; vector<int> used(1000000, 0); vector<int> len(1000000, 5); queue<int> q; q.push(x); used[x] = 1; len[x] = 0; while (!q.empty()) { int v = q.front(), v1 = v; q.pop(); vector<int> res(6); for (int i = 5; i >= 0; i--) { res[i] = v1 % 10; v1 /= 10; } if (res[0] + res[1] + res[2] == res[3] + res[4] + res[5]) { cout << len[v]; return 0; } for (int i = 0; i < 6; ++i) { for (int j = 0; j <= 9; ++j) { if (j != res[i]) { int to = 0; for (int i1 = 0; i1 < 6; ++i1) { if (i1 != i) to = to * 10 + res[i1]; else to = to * 10 + j; } if (used[to] == 0) { used[to] = 1; q.push(to); len[to] = len[v] + 1; } } } } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long ans, cr[40002], ar[40005], br[40005], nd[40005]; void build(int id, int l, int r) { if (l == r) { nd[id] = cr[l]; return; } int md = (l + r) >> 1; build(id * 2, l, md); build(id * 2 + 1, md + 1, r); nd[id] = min(nd[2 * id], nd[2 * id + 1]); ans -= nd[id]; } int main() { long long i, j, k, n, m, x, mx; cin >> n; queue<long long> Q; m = (1 << (n + 1)) - 2; Q.push(2); Q.push(3); mx = 0; k = 0; for (i = 1; i <= m; i++) { cin >> x; long long tp = Q.front(); Q.pop(); if (tp >= (1 << (n))) cr[k++] = x; ar[tp] = x; br[tp] = x + br[tp / 2]; mx = max(mx, br[tp]); Q.push(2 * tp); Q.push(2 * tp + 1); } ans = 0; int p = (1 << n); k = 1; while (1) { cr[k] = mx - br[p]; ans += cr[k]; k++; p++; if (p > (m + 1)) break; } build(1, 1, (m + 2)); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, k; long long read() { long long s = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { s = s * 10 + ch - 0 ; ch = getchar(); } return s * f; } inline void print(long long *f, long long len) { for (long long i = 0; i < len; i++) printf( %lld , f[i]); puts( ); } long long a[101010]; long long pw[101010]; long long cnt[101010]; long long dp[101010]; const long long mod = 1e9 + 7; signed main() { n = read(); pw[0] = 1; for (long long i = 1, iend = n; i <= iend; ++i) a[i] = read(), pw[i] = (pw[i - 1] * 2) % mod, cnt[a[i]]++; for (long long i = 100000, iend = 1; i >= iend; --i) { long long sum = 0; for (long long j = i; j <= 100000; j += i) sum += cnt[j]; dp[i] = pw[sum] - 1; for (long long j = i * 2; j <= 100000; j += i) dp[i] += mod, dp[i] -= dp[j], dp[i] %= mod; } cout << dp[1]; } |
module ultrasonic #( parameter N = 16 , CONSTANT = 20'd588 ) (
input clk,
input signal,
input rst_n,
output reg [N-1:0] value ,
output reg done
);
reg [1:0] state ;
reg [N-1:0] count_1 ;
// El modulo tiene 3 estados, el primero mantiene los valores en cero y se llega a el por medio del rst_n
// El segundo estado inicia cuando el ultrasónico recibe la señal del modulo fisico y cuenta la duración
// El tercer estado inicia cuando la señal del físico se apaga, enviando un "Done" al controlador
// El rst_n devuelve al estado inicia el módulo
// States assignation
parameter S0 = 2'b00 ;
parameter S1 = 2'b01 ;
parameter S2 = 2'b10 ;
// Nextstate logic
always @ ( negedge clk )
if ( ~rst_n )
state <= S0 ;
else
case ( state )
S0 :
if ( signal )
state <= S1 ;
else
state <= S0 ;
S1 :
if ( ~signal )
state <= S2 ;
else
state <= S1 ;
endcase
// State logic
always @( posedge clk )
case ( state )
S0 : begin
count_1 <= 0 ;
value <= 0 ;
done <= 0 ;
end S1 : begin
if ( CONSTANT == count_1 ) begin
count_1 <= 1 ;
value <= value + 1'b1 ;
done <= 0 ;
end else begin
count_1 <= count_1 + 1'b1 ;
value <= value ;
done <= 0 ;
end
end S2 : begin
count_1 <= 0 ;
value <= value ;
done <= 1 ;
end
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1010; int c1, c2; char str[maxn]; int main() { scanf( %s , str); int len = int(strlen(str)); for (int i = 0; i < len; i++) { int t = str[i] - 0 ; if (t == 0) { if (!c1) { puts( 1 1 ); } else puts( 3 1 ); c1 ^= 1; } else { if (!c2) { puts( 4 3 ); } else puts( 4 1 ); c2 ^= 1; } } return 0; } |
`timescale 1ns/1ns
module hct74245(
input dir,
input nOE,
inout [7:0] A,
inout [7:0] B,
output [7:0] C // Added to demonstrate that a straight dependency timing works correctly
);
// HCT typical @ 5v according to https://assets.nexperia.com/documents/data-sheet/74HC_HCT245.pdf
specify
(A *> C) = 100; // This delay works OK
(A *> B) = 10; // The rest of these delays do not work
(B *> A) = 10; // not respected
(dir *> A) = 16;// not respected
(dir *> B) = 16;// not respected
(nOE *> A) = 16;// not respected
(nOE *> B) = 16;// not respected
endspecify
assign A=nOE? 8'bzzzzzzzz : dir?8'bzzzzzzzz:B;
assign B=nOE? 8'bzzzzzzzz : dir?A:8'bzzzzzzzz;
assign C=A; // THIS IS DELAYED BY 100
// HAVE TO USE THIS APPROACH TO MAKE TIMINGS WORK AT ALL
// assign #16 A=nOE? 8'bzzzzzzzz :dir?8'bzzzzzzzz:B;
// assign #16 B=nOE? 8'bzzzzzzzz :dir?A: 8'bzzzzzzzz;
endmodule
module tb();
tri [7:0]A;
tri [7:0]B;
tri [7:0]C; // 'C' IS NOT PART OF ORIGINAL DESIGN - HOWEVER THIS TIMING IS RESPECTED COS THERE ARE NO CONDITIONALS IN THE ASSIGNMENT
reg [7:0] Vb=8'b00000000;
reg [7:0] Va=8'b11111111;
reg dir;
reg nOE;
assign B=Vb;
assign A=Va;
hct74245 buf245(.A, .B, .dir, .nOE);
integer timer;
reg failed = 0;
initial begin
$display("disable output , set dir a->b");
dir <= 1; // A->B
nOE <= 1;
Va=8'b11111111;
Vb=8'bzzzzzzzz;
#50 // time to settle
// NOW throw outputs on and time how long it takes for expected output to appear.
// It should take 16 to propagate from nOE -> B but the change is instantaneous
$display("enable output - B will change immediately");
timer=$time;
nOE <= 0;
wait(B === 8'b11111111);
if ($time - timer < 16) begin
$display("%6d", $time, " ERROR TOO QUICK - EXPECTED nOE->B = 16ns - BUT TOOK %-d", ($time - timer));
failed = 1;
end
else
$display("%6d", $time, " OK - TOOK %-d", ($time - timer));
#50 // settle
// Change data in - This should take 10 to propagate A->B but is instantaneous
$display("change A - B will change immediately (but C is delayed as expected by 100)");
Va=8'b00000000;
timer=$time;
nOE <= 0;
wait(B === 8'b00000000);
if ($time - timer < 10) begin
$display("%6d", $time, " ERROR TOO QUICK - EXPECTED A->B = 10ns - BUT TOOK %-d", ($time - timer));
failed = 1;
end
else
$display("%6d", $time, " OK - TOOK %-d", ($time - timer));
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000000 + 20; int xor_n[maxn]; int p[maxn]; int n; int q; void init() { xor_n[0] = 0; for (int i = 1; i < maxn; i++) { xor_n[i] = i ^ xor_n[i - 1]; } } int main() { init(); while (~scanf( %d , &n)) { q = 0; for (int i = 1; i <= n; i++) { scanf( %d , &p[i]); q = q ^ p[i]; } for (int i = 1; i <= n; i++) { int tmp = n / i; if (n % i == 0) { if (tmp & 1) q = q ^ xor_n[i - 1]; } else { if (tmp & 1) q = q ^ xor_n[i - 1] ^ xor_n[n % i]; else q = q ^ xor_n[n % i]; } } printf( %d n , q); } return 0; } |
/*
* Copyright (C) 2015 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
*/
`timescale 1ns / 1ps
// p = p + (a*b / 2^17)
// if r p = (a*b / 2^17)
module mac_24x18
(
input c,
input r, // 2 cycles after a, b
input signed [23:0] a,
input signed [17:0] b,
output signed [23:0] p);
dsp48_wrap #(.NBA(24), .NBB(18), .NBP(24), .S(18), .AREG(1), .BREG(1)) mac_i
(
.clock(c),
.ce1(1'b1),
.ce2(1'b1),
.cem(1'b1),
.cep(1'b1),
.a(a),
.b(b),
.c(24'd131072), // convergent rounding
.d(24'h0),
.mode(r ? 5'b01100 : 5'b01000),
.acin(30'h0),
.bcin(18'h0),
.pcin(48'h0),
.acout(),
.bcout(),
.pcout(),
.p(p)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long b, d, s, x, y, z, m, t; x = y = z = 0; cin >> b >> d >> s; long long a[3] = {b, d, s}; sort(a, a + 3); if (a[0] == a[2]) { cout << 0; } else if (a[1] == a[2]) { cout << a[2] - a[0] - 1; } else { cout << 2 * a[2] - a[0] - a[1] - 2; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> g[100100]; int a[100100], b[100100], s[100100]; int n, sa, sb; double ans; void dfs(int v, int p) { s[v] = 1; for (int i = 0; i < g[v].size(); i++) { int u = g[v][i]; if (u == p) continue; dfs(u, v); s[v] += s[u]; a[v] += a[u]; ans += 1.0 * b[v] * s[u] * a[u]; } ans += 1.0 * b[v] * (n - s[v]) * (sa - a[v]); } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); g[u].push_back(v); g[v].push_back(u); } for (int i = 1; i <= n; i++) scanf( %d%d , a + i, b + i); for (int i = 1; i <= n; i++) { sa += a[i]; sb += b[i]; } dfs(1, 0); printf( %.12lf n , ans / sa / sb); return 0; } |
module nios_system (
alu_a_export,
alu_b_export,
alu_carry_out_export,
alu_control_export,
alu_negative_export,
alu_out_export,
alu_overflow_export,
alu_zero_export,
clk_clk,
hex_0_export,
hex_1_export,
hex_2_export,
hex_3_export,
hex_4_export,
hex_5_export,
leds_export,
regfile_data_export,
regfile_r1sel_export,
regfile_r2sel_export,
regfile_reg1_export,
regfile_reg2_export,
regfile_we_export,
regfile_wsel_export,
reset_reset_n,
sram_addr_export,
sram_cs_export,
sram_data_in_export,
sram_oe_export,
sram_read_write_export,
switches_export,
keys_export);
output [31:0] alu_a_export;
output [31:0] alu_b_export;
input alu_carry_out_export;
output [2:0] alu_control_export;
input alu_negative_export;
input [31:0] alu_out_export;
input alu_overflow_export;
input alu_zero_export;
input clk_clk;
output [3:0] hex_0_export;
output [3:0] hex_1_export;
output [3:0] hex_2_export;
output [3:0] hex_3_export;
output [3:0] hex_4_export;
output [3:0] hex_5_export;
output [9:0] leds_export;
output [31:0] regfile_data_export;
output [5:0] regfile_r1sel_export;
output [5:0] regfile_r2sel_export;
input [31:0] regfile_reg1_export;
input [31:0] regfile_reg2_export;
output regfile_we_export;
output [5:0] regfile_wsel_export;
input reset_reset_n;
output [10:0] sram_addr_export;
output sram_cs_export;
inout [15:0] sram_data_in_export;
output sram_oe_export;
output sram_read_write_export;
input [9:0] switches_export;
input [3:0] keys_export;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> ostream &operator<<(ostream &os, vector<T> &vec) { os << { ; for (int i = (0), __i = (((int)(vec).size())); i < __i; i++) { os << vec[i]; if (i + 1 != ((int)(vec).size())) os << , ; } os << } ; return os; } template <class T1, class T2> ostream &operator<<(ostream &os, pair<T1, T2> &par) { os << ( << par.first << , << par.second << ) ; return os; } const int dim = 110000; char s[dim]; char s1[dim]; int p[dim]; int a[dim]; int a1[dim]; long long r1[dim]; long long r2[dim]; long long r3[dim]; int main() { scanf( %s , s); int n = strlen(s); for (int i = (0), __i = (n); i < __i; i++) s1[i] = s[n - 1 - i]; s1[n] = 0; p[0] = -1; int g = -1; for (int i = (1), __i = (n); i < __i; i++) { while (g != -1 && s1[g + 1] != s1[i]) { g = p[g]; } if (s1[g + 1] == s1[i]) ++g; p[i] = g; } g = -1; a[0] = 0; a1[0] = 0; for (int i = (0), __i = (n); i < __i; i++) { while (g != -1 && s1[g + 1] != s[i]) { g = p[g]; } if (s1[g + 1] == s[i]) ++g; if (a[i] > g + 1) { a1[i + 1] = a1[i]; } else { a1[i + 1] = i - g; } a[i + 1] = max(a[i], g + 1); } r1[0] = 0; r2[0] = 0; r3[0] = 1; long long cc = 52152551; for (int i = (0), __i = (n); i < __i; i++) { r1[i + 1] = r1[i] + s[i] * r3[i]; r2[i + 1] = r2[i] + s1[i] * r3[i]; r3[i + 1] = r3[i] * cc; } int ans = 0; int i1, j1; int i2, j2; for (int i = (0), __i = (n); i < __i; i++) { int l = 0, r = n; while (r - l > 1) { int mid = (l + r) / 2; if (i - mid >= 0 && i + mid < n && (r1[i + 1] - r1[i - mid]) * r3[n - i - mid - 1] == (r2[n - i] - r2[n - i - mid - 1]) * r3[i - mid]) { l = mid; } else { r = mid; } } int t = min(a[i - l], n - i - l - 1); int ans1 = t * 2 + l * 2 + 1; if (ans < ans1) { ans = ans1; i1 = a1[i - l]; j1 = t; i2 = i - l; j2 = l * 2 + 1; } } if (j1 == 0) { printf( 1 n ); printf( %d %d n , i2 + 1, j2); } else { printf( 3 n ); printf( %d %d n , i1 + 1, j1); printf( %d %d n , i2 + 1, j2); printf( %d %d n , n - j1 + 1, j1); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4B_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__OR4B_BEHAVIORAL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__or4b (
X ,
A ,
B ,
C ,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X, not0_out, C, B, A);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4B_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; vector<int> V[1005]; int dis[1005], rdis[1005], G[1005][1005]; void spfa(int s, int e) { queue<int> Q; memset(dis, 0x3f, sizeof(dis)); memset(rdis, 0x3f, sizeof(rdis)); Q.push(s); dis[s] = 0; while (!Q.empty()) { int f = Q.front(); for (int i = (0); i < ((int)(V[f]).size()); i++) { int nex = V[f][i]; if (dis[nex] > dis[f] + 1) { dis[nex] = dis[f] + 1; Q.push(nex); } } Q.pop(); } Q.push(e); rdis[e] = 0; while (!Q.empty()) { int f = Q.front(); for (int i = (0); i < ((int)(V[f]).size()); i++) { int nex = V[f][i]; if (rdis[nex] > rdis[f] + 1) { rdis[nex] = rdis[f] + 1; Q.push(nex); } } Q.pop(); } } int main() { int n, m, s, e; scanf( %d%d%d%d , &n, &m, &s, &e); while (m--) { int a, b; scanf( %d%d , &a, &b); V[a].push_back(b); V[b].push_back(a); G[a][b] = G[b][a] = 1; } int ans = 0; spfa(s, e); for (int i = (1); i < (n + 1); i++) for (int j = (i + 1); j < (n + 1); j++) if (dis[i] + 1 + rdis[j] >= dis[e] && dis[j] + 1 + rdis[i] >= dis[e] && !G[i][j]) ans++; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; const int MAX = 400005; const int MAX1 = 2007; const int MAX2 = 4007; const int LEN = 21; const int BASE = 1000000000; const double EPS = 1e-7; const int MOD = 1234567891; vector<pair<char, int> > vec; int main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); ifstream in( ); ofstream out( ); int n, k; cin >> n >> k; string s; cin >> s; for (int i = (0); i < ((int)s.size()); ++i) { vec.push_back(make_pair(s[i], i)); } sort(vec.begin(), vec.end()); char ans[MAX]; memset(ans, 0 , sizeof(ans)); for (int i = (k); i < ((int)vec.size()); ++i) { ans[vec[i].second] = vec[i].first; } for (int i = (0); i < (n); ++i) { if (ans[i] != 0 ) cout << ans[i]; } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; bool can(int x, int y, int a, int b) { cout << ? << x << << y << << a << << b << endl; string ans; cin >> ans; if (ans == BAD ) exit(0); return ans == YES ; } int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; int x = 1, y = 1; string ord1(n - 1, ), ord2(n - 1, ); int i = 0; while (i < n - 1) { if (can(x + 1, y, n, n)) { ++x; ord1[i] = D ; } else { ord1[i] = R ; ++y; } ++i; } x = n; y = n; i = 0; while (i < n - 1) { if (can(1, 1, x, y - 1)) { ord2[i] = R ; --y; } else { --x; ord2[i] = D ; } ++i; } reverse(ord2.begin(), ord2.end()); cout << ! << ord1 << ord2 << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__XOR3_BEHAVIORAL_PP_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__xor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , A, B, C );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR3_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int a[55], b[55]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= m; i++) scanf( %d , b + i); long long ans = 1ll << 62; for (int x = 1; x <= n; x++) { long long maxv = -(1ll << 62); for (int y = 1; y <= n; y++) { if (x == y) continue; for (int z = 1; z <= m; z++) { maxv = max(maxv, (long long)a[y] * b[z]); } } ans = min(ans, maxv); } printf( %lld n , ans); return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: asy_256_139.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module asy_256_139 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw);
input aclr;
input [138:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [138:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [138:0] sub_wire0;
wire [7:0] sub_wire1;
wire [138:0] q = sub_wire0[138:0];
wire [7:0] wrusedw = sub_wire1[7:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.wrusedw (sub_wire1),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 139,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "139"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "139"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "139"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 139 0 INPUT NODEFVAL "data[138..0]"
// Retrieval info: USED_PORT: q 0 0 139 0 OUTPUT NODEFVAL "q[138..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL "wrusedw[7..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 139 0 data 0 0 139 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 139 0 @q 0 0 139 0
// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_256_139.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_256_139.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_256_139.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_256_139.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_256_139_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_256_139_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_256_139_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asy_256_139_wave*.jpg FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S6S_1_V
`define SKY130_FD_SC_LP__DLYMETAL6S6S_1_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog wrapper for dlymetal6s6s with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlymetal6s6s.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlymetal6s6s_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlymetal6s6s base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlymetal6s6s_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlymetal6s6s base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S6S_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int s, x1, x2, t1, t2, p, d; cin >> s >> x1 >> x2 >> t1 >> t2 >> p >> d; int cnt = 0, initial_position = p; while (initial_position != x1) { if (initial_position == s) d = -1; if (initial_position == 0) d = 1; initial_position += d; cnt++; } while (initial_position != x2) { if (initial_position == s) d = -1; if (initial_position == 0) d = 1; initial_position += d; cnt++; } int ans = min(abs(x1 - x2) * t2, cnt * t1); cout << ans; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 21:01:02 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_sim_netlist.v
// Design : system_clock_splitter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_clock_splitter_0_0,clock_splitter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "clock_splitter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_clock_splitter_0_0
(clk_in,
latch_edge,
clk_out);
input clk_in;
input latch_edge;
output clk_out;
wire clk_in;
wire clk_out;
wire latch_edge;
system_clock_splitter_0_0_clock_splitter U0
(.clk_in(clk_in),
.clk_out(clk_out),
.latch_edge(latch_edge));
endmodule
(* ORIG_REF_NAME = "clock_splitter" *)
module system_clock_splitter_0_0_clock_splitter
(clk_out,
latch_edge,
clk_in);
output clk_out;
input latch_edge;
input clk_in;
wire clk_i_1_n_0;
wire clk_in;
wire clk_out;
wire last_edge;
wire latch_edge;
LUT3 #(
.INIT(8'h6F))
clk_i_1
(.I0(latch_edge),
.I1(last_edge),
.I2(clk_out),
.O(clk_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_reg
(.C(clk_in),
.CE(1'b1),
.D(clk_i_1_n_0),
.Q(clk_out),
.R(1'b0));
FDRE #(
.INIT(1'b0))
last_edge_reg
(.C(clk_in),
.CE(1'b1),
.D(latch_edge),
.Q(last_edge),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int m, n; cin >> m; int a[m]; for (int i = 0; i < m; i++) { a[i] = 0; } cin >> n; int p = 0, q = 0, r = 0; for (int i = 0; i < n; i++) { cin >> p; cin >> q; cin >> r; a[p - 1] -= r; a[q - 1] += r; } int res = 0; for (int i = 0; i < m; i++) { if (a[i] > 0) res += a[i]; } cout << res; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FILL_TB_V
`define SKY130_FD_SC_LP__FILL_TB_V
/**
* fill: Fill cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fill.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_lp__fill dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FILL_TB_V
|
`include "hrfp_defs.vh"
module hrfp_mult_round_final(
input wire clk,
input wire expdiff,
input wire sign5,
input wire rounding_overflowed,answer_is_zero, res_is_inf, res_is_nan,
input wire [53:0] rounded_mantissa_expdiff0, rounded_mantissa_expdiff1,
input wire [`MANTISSABITS-1:0] roundoverflow_mantissa,
input wire [`EXPONENTBITS-1:0] roundoverflow_exponent,
input wire [53:0] final_hrfp_round_mask_expdiff0,final_hrfp_round_mask_expdiff1,
input wire [`EXPONENTBITS-1+1:0] exponent_post_round_expdiff0, exponent_post_round_expdiff1,
output wire [`MSBBIT:0] result);
parameter PARALLELL_ROUNDING = 0;
reg [53:0] final_rounded_mantissa, final_hrfp_round_mask;
reg [`EXPONENTBITS-1+1:0] final_exponent_post_round;
always @* begin
// Default behavior: (expdiff == 0)
final_rounded_mantissa = rounded_mantissa_expdiff0;
final_hrfp_round_mask = final_hrfp_round_mask_expdiff0;
final_exponent_post_round = exponent_post_round_expdiff0;
if(PARALLELL_ROUNDING && (expdiff == 1)) begin
final_rounded_mantissa = rounded_mantissa_expdiff1;
final_hrfp_round_mask = final_hrfp_round_mask_expdiff1;
final_exponent_post_round = exponent_post_round_expdiff1;
end
end
reg [`MSBBIT:0] theresult;
always @* begin
theresult`SIGN <= sign5;
// Conversion between decimal, ieee754 and HRFP
// Decimal: 1.0
// IEEE754: 0x3f800000 (0 01111111 00000000000000000000000)
// HRFP: 8.0*16^(31 - bias)/8 1000.0000000000000000000 * 16^(31 - bias)
// Hence bias should be 31 and the mantissa shifted accordingly
theresult`EXPONENT <= final_exponent_post_round;
// Normalization:
theresult`MANTISSA <= final_rounded_mantissa[53:27] & final_hrfp_round_mask[53:27];
// FIXME - Precalculate this difference for each expdiff case to simplify this expression...
// Actually, we might not need to do this, as we might be able to precalculate hrfp_round_mask
// so that at least the mantissa is always zero.
// if(final_exponent_post_round < 58) begin
// theresult`EXPONENT <= 0;
// theresult`MANTISSA <= 0;
// end
if(rounding_overflowed) begin
theresult`EXPONENT <= roundoverflow_exponent;
end
if(answer_is_zero) begin
// The following is not needed here as it is handled below (using the RESET input of flip-flops)
// theresult`EXPONENT <= 0;
// theresult`MANTISSA <= 0;
// However, these bits of the exponent are not reset below using answer_is_zero,
// zero them here instead!
theresult`IS_NAN_OR_INF <= 0;
theresult`HRFP_IS_NAN <= 0;
end
if(res_is_inf) begin
theresult`IS_NAN_OR_INF <= 1;
theresult`HRFP_IS_NAN <= 0;
end
if(res_is_nan) begin
theresult`IS_NAN_OR_INF <= 1;
theresult`HRFP_IS_NAN <= 1;
end
if(rounding_overflowed) begin
// Handled using reset inputs below!
// theresult`MANTISSA <= 27'b000100000000000000000000000;
// Except this one which isn't!
theresult[23] <= 1;
end
end
initial begin
if(`MSBBIT != 35) $stop;
if(`EXPONENTBITS != 8) $stop;
if(`MANTISSABITS != 27) $stop;
end
// Instantiate the flip-flops manually to ensure that a suitable
// signal is used for the D and R input of the flip-flops. (As the
// synthesis tool will often make a fairly suboptimal choice here.)
FDRE ff35(.C(clk), .Q(result[35]), .CE(1'b1), .R(1'b0), .D(theresult[35]));
FDRE ff34(.C(clk), .Q(result[34]), .CE(1'b1), .R(1'b0), .D(theresult[34]));
FDRE ff33(.C(clk), .Q(result[33]), .CE(1'b1), .R(1'b0), .D(theresult[33])); // These bits also contain IS_NAN_OR_INF and HRFP_IS_NAN
FDRE ff32(.C(clk), .Q(result[32]), .CE(1'b1), .R(answer_is_zero), .D(theresult[32]));
FDRE ff31(.C(clk), .Q(result[31]), .CE(1'b1), .R(answer_is_zero), .D(theresult[31]));
FDRE ff30(.C(clk), .Q(result[30]), .CE(1'b1), .R(answer_is_zero), .D(theresult[30]));
FDRE ff29(.C(clk), .Q(result[29]), .CE(1'b1), .R(answer_is_zero), .D(theresult[29]));
FDRE ff28(.C(clk), .Q(result[28]), .CE(1'b1), .R(answer_is_zero), .D(theresult[28]));
FDRE ff27(.C(clk), .Q(result[27]), .CE(1'b1), .R(answer_is_zero), .D(theresult[27]));
FDRE ff26(.C(clk), .Q(result[26]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[26]));
FDRE ff25(.C(clk), .Q(result[25]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[25]));
FDRE ff24(.C(clk), .Q(result[24]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[24]));
FDRE ff23(.C(clk), .Q(result[23]), .CE(1'b1), .R(answer_is_zero), .D(theresult[23]));
FDRE ff22(.C(clk), .Q(result[22]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[22]));
FDRE ff21(.C(clk), .Q(result[21]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[21]));
FDRE ff20(.C(clk), .Q(result[20]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[20]));
FDRE ff19(.C(clk), .Q(result[19]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[19]));
FDRE ff18(.C(clk), .Q(result[18]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[18]));
FDRE ff17(.C(clk), .Q(result[17]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[17]));
FDRE ff16(.C(clk), .Q(result[16]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[16]));
FDRE ff15(.C(clk), .Q(result[15]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[15]));
FDRE ff14(.C(clk), .Q(result[14]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[14]));
FDRE ff13(.C(clk), .Q(result[13]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[13]));
FDRE ff12(.C(clk), .Q(result[12]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[12]));
FDRE ff11(.C(clk), .Q(result[11]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[11]));
FDRE ff10(.C(clk), .Q(result[10]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[10]));
FDRE ff9(.C(clk), .Q(result[9]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[9]));
FDRE ff8(.C(clk), .Q(result[8]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[8]));
FDRE ff7(.C(clk), .Q(result[7]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[7]));
FDRE ff6(.C(clk), .Q(result[6]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[6]));
FDRE ff5(.C(clk), .Q(result[5]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[5]));
FDRE ff4(.C(clk), .Q(result[4]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[4]));
FDRE ff3(.C(clk), .Q(result[3]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[3]));
FDRE ff2(.C(clk), .Q(result[2]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[2]));
FDRE ff1(.C(clk), .Q(result[1]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[1]));
FDRE ff0(.C(clk), .Q(result[0]), .CE(1'b1), .R(answer_is_zero || rounding_overflowed), .D(theresult[0]));
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; long long MOD = 1e9 + 7; long long dp[4000][4000]; long long mn[4000][4000]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; set<long long> uss; long long a[n]; long long b[n]; long long sm = 0; for (int i = 0; i < n; i++) { cin >> a[i]; a[i] = a[i] - i; uss.insert(a[i]); } vector<long long> us; for (auto i : uss) { us.push_back(i); } for (int i = 0; i < n; i++) { for (int j = 0; j < us.size(); j++) { dp[i + 1][j] = mn[i][j] + abs(us[j] - a[i]); mn[i + 1][j] = dp[i + 1][j]; if (j) mn[i + 1][j] = min(mn[i + 1][j], mn[i + 1][j - 1]); } } cout << mn[n][us.size() - 1]; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = (long long)1e9 + 7; const long long MOD1 = 2286661337; const long long MOD2 = 998244353; const int INF = (int)1e9 + 7; const double EPS = 1e-7; const int N = (int)2e5; int n; long long a[N], b[N]; bool is_same_() { for (int i = 0; i < n; ++i) { if (a[i] != b[i]) { return false; } } return true; } bool is_up() { for (int i = 1; i < n; ++i) { if (b[i] <= b[i - 1]) { return false; } } return true; } bool is_down() { for (int i = 1; i < n; ++i) { if (b[i] >= b[i - 1]) { return false; } } return true; } bool is_bad() { for (int i = 0; i < n; ++i) { if (b[i] <= 0) { return true; } } return false; } bool is_rev_same() { for (int i = 0; i < n; ++i) { if (a[i] != b[n - 1 - i]) { return false; } } return true; } bool is_uncomp() { for (int i = 0; i < n; ++i) { if (a[i] > b[i]) { return true; } } return false; } void solve() { int cnt = 0; string ans; int prev_ = -1; while (!is_same_()) { if (is_rev_same()) { ans.push_back( R ); break; } if (is_bad()) { cnt = -1; break; } if (is_up()) { for (int i = n - 1; i >= 0; --i) { b[i] = (i ? b[i] - b[i - 1] : b[i]); } if (prev_ != 0) { if (prev_ != -1) { ans.push_back( R ); } prev_ = 0; } ans.push_back( P ); } else if (is_down()) { for (int i = 0; i < n; ++i) { b[i] = (i == n - 1 ? b[i] : b[i] - b[i + 1]); } if (prev_ != 1) { ans.push_back( R ); prev_ = 1; } ans.push_back( P ); } else { cnt = -1; break; } ++cnt; } if (prev_ == 1) { ans.push_back( R ); } reverse(ans.begin(), ans.end()); if (cnt == -1) { printf( IMPOSSIBLE ); } else if (cnt > N) { printf( BIG n%d , cnt); } else { printf( SMALL n%d n%s , ans.size(), ans.c_str()); } } signed main() { scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %lld , &a[i]); } for (int i = 0; i < n; ++i) { scanf( %lld , &b[i]); } if (n == 1) { if (a[0] == b[0]) { printf( SMALL n0 ); } else { printf( IMPOSSIBLE ); } } else if (n == 2) { long long cnt = 0; int prev_ = -1; string ans = ; while (!is_same_()) { if (is_rev_same()) { ans.push_back( R ); break; } if (is_uncomp()) { ans.push_back( R ); reverse(b, b + n); if (is_uncomp()) { cnt = -1; break; } } long long x = b[0], y = b[1]; if (x <= 0 || y <= 0) { cnt = -1; break; } if (x < y) { if (prev_ != 0) { if (prev_ != -1) { ans.push_back( R ); } prev_ = 0; } long long cur_cnt = y / x; if (x == a[0]) { cur_cnt = min(cur_cnt, (y - a[1] + x - 1) / x); } if (ans.size() + cur_cnt <= N) { for (int i = 0; i < cur_cnt; ++i) { ans.push_back( P ); } } cnt += cur_cnt; y -= x * cur_cnt; } else if (x > y) { if (prev_ != 1) { ans.push_back( R ); prev_ = 1; } long long cur_cnt = x / y; if (y == a[1]) { cur_cnt = min(cur_cnt, (x - a[0] + y - 1) / y); } if (ans.size() + cur_cnt <= N) { for (int i = 0; i < cur_cnt; ++i) { ans.push_back( P ); } } cnt += cur_cnt; x -= y * cur_cnt; } else { cnt = -1; break; } b[0] = x, b[1] = y; } if (prev_ == 1) { ans.push_back( R ); } reverse(ans.begin(), ans.end()); if (cnt == -1) { printf( IMPOSSIBLE ); } else if (cnt > N) { printf( BIG n%lld , cnt); } else { printf( SMALL n%d n%s , ans.size(), ans.c_str()); } } else { solve(); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef enum {
E01 = 'h1,
ELARGE = 'hf00d
} my_t;
integer cyc=0;
my_t e;
string all;
// Check runtime
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
e <= E01;
end
else if (cyc==1) begin
`checks(e.name, "E01");
`checkh(e.next, ELARGE);
e <= ELARGE;
end
else if (cyc==3) begin
`checks(e.name, "ELARGE");
`checkh(e.next, E01);
`checkh(e.prev, E01);
e <= E01;
end
else if (cyc==20) begin
e <= 'h11; // Unknown
end
else if (cyc==20) begin
`checks(e.name, ""); // Unknown
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module converts video streams between RGB color formats. *
* *
******************************************************************************/
module Video_System_Pixel_RGB_Resampler (
// Inputs
clk,
reset,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bidirectional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter IDW = 15;
parameter ODW = 29;
parameter IEW = 0;
parameter OEW = 1;
parameter ALPHA = 10'h3FF;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [IDW:0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [IEW:0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bidirectional
// Outputs
output stream_in_ready;
output reg [ODW:0] stream_out_data;
output reg stream_out_startofpacket;
output reg stream_out_endofpacket;
output reg [OEW:0] stream_out_empty;
output reg stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 9: 0] r;
wire [ 9: 0] g;
wire [ 9: 0] b;
wire [ 9: 0] a;
wire [ODW:0] converted_data;
// Internal Registers
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
begin
stream_out_data <= 'b0;
stream_out_startofpacket <= 1'b0;
stream_out_endofpacket <= 1'b0;
stream_out_empty <= 'b0;
stream_out_valid <= 1'b0;
end
else if (stream_out_ready | ~stream_out_valid)
begin
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
stream_out_empty <= stream_in_empty;
stream_out_valid <= stream_in_valid;
end
end
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_in_ready = stream_out_ready | ~stream_out_valid;
// Internal Assignments
assign r = {stream_in_data[15:11], stream_in_data[15:11]};
assign g = {stream_in_data[10: 5], stream_in_data[10: 7]};
assign b = {stream_in_data[ 4: 0], stream_in_data[ 4: 0]};
assign a = ALPHA;
assign converted_data[29:20] = r[ 9: 0];
assign converted_data[19:10] = g[ 9: 0];
assign converted_data[ 9: 0] = b[ 9: 0];
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_FUNCTIONAL_V
`define SKY130_FD_SC_MS__INV_FUNCTIONAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; void solve() { long long n, m; cin >> n >> m; set<long long> s; vector<long long> ar(n + 1, 0); for (long long i = 0; i < n; i++) { s.insert(i + 1); } for (long long i = 1; i <= m; i++) { long long li, ri, xi; vector<long long> temp; cin >> li >> ri >> xi; auto itl = s.lower_bound(li); auto itr = s.upper_bound(ri); for (auto it = itl; it != itr && (*it) <= ri; it++) temp.push_back(*it); for (auto i : temp) { if (i != xi) { s.erase(i); ar[i] = xi; } } } for (long long i = 1; i <= n; i++) cout << ar[i] << ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t = 1; while (t--) solve(); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:52:54 10/17/2015
// Design Name:
// Module Name: tx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx
#(
parameter DBIT = 8, // cantidad de bits de datos
SB_TICK = 16 // cantidad de ticks para enviar un bit fuera del shift register
)
(
input wire clk, reset,
input wire tx_start, s_tick,
input wire [DBIT-1:0] data_in,
output reg tx_done_tick,
output wire tx
);
//Declaracin de estados simblicos
localparam [1:0]
idle = 2'b00,
start = 2'b01,
data = 2'b10,
stop = 2'b11;
//Declaracin de seales
reg [1:0] state_reg, state_next;
reg [3:0] s_reg, s_next; //Numero de sampling ticks para hacer el oversampling
reg [2:0] n_reg, n_next; //Numero de bits de datos recibidos en el estado data.
reg [DBIT-1:0] b_reg, b_next;
reg tx_reg, tx_next; //Buffer de un bit para filtrar posibles fallos
//Cuerpo
//Registros de datos y Estado de la FSMD
always @(posedge clk, posedge reset)
if(reset)
begin
state_reg <= idle;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0;
tx_reg <= 1'b1;
end
else
begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
tx_reg <= tx_next;
end
// FSMD next-state logic y unidades funcionales
always @*
begin
state_next = state_reg;
tx_done_tick = 1'b0;
s_next = s_reg;
n_next = n_reg;
b_next = b_reg;
tx_next = tx_reg;
case (state_reg)
idle:
begin
tx_next = 1'b1;
if(tx_start)
begin
state_next = start;
s_next = 0;
b_next = data_in;
end
end
start:
begin
tx_next = 1'b0;
if(s_tick)
if(s_reg == 15)
begin
state_next = data;
s_next = 0;
n_next = 0;
end
else
s_next = s_reg + 4'b0001;
end
data:
begin
tx_next = b_reg[0];
if(s_tick)
if(s_reg == 15)
begin
s_next = 0;
b_next = b_reg >> 1;
if(n_reg == (DBIT - 1))
state_next = stop;
else
n_next = n_reg + 3'b001;
end
else
s_next = s_reg + 4'b0001;
end
stop:
begin
tx_next = 1'b1;
if(s_tick)
if(s_reg == (SB_TICK - 1))
begin
state_next = idle;
tx_done_tick = 1'b1;
end
else
s_next = s_reg + 4'b0001;
end
endcase
end
//Salida
assign tx = tx_reg;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__EDFXTP_BEHAVIORAL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__edfxtp (
Q ,
CLK,
D ,
DE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXTP_BEHAVIORAL_V |
#pragma GCC optimize( Ofast ) #include<bits/stdc++.h> using namespace std; #define int long long int #define double long double #define all(x) begin(x), end(x) #define Done(x) cout<<x<<endl; return; #define endl n void solve(){ int q; cin>>q; for(int i=0;i<q;i++){ int u; cin>>u; int v; cin>>v; if(v<u){ cout<< NO <<endl; }else if(v==u){ cout<< YES <<endl; }else{ vector<int>cnt(31); for(int i=0;i<30;i++){ if(u&(1<<i)){ cnt[i]++; } } bool can=true; for(int i=0;i<30;i++){ int val=(1<<i); if(v&val){ if(cnt[i]==0){ can=false; break; }else{ cnt[i]-=1; cnt[i+1]+=cnt[i]; } }else{ cnt[i+1]+=cnt[i]; } } if(can){ cout<< YES <<endl; }else{ cout<< NO <<endl; } } } } int32_t main(){ // Remove for Interactive Problems ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(); cerr<< Time : <<1000*((double)clock())/(double)CLOCKS_PER_SEC<< ms n ; return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_dadd_64ns_64ns_64_5_full_dsp
#(parameter
ID = 6,
NUM_STAGE = 5,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
ANN_ap_dadd_3_full_dsp_64 ANN_ap_dadd_3_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> arr; pair<int, long long> doit(long long n) { if (n <= 7) return make_pair(n, n); vector<long long>::iterator ite = upper_bound(arr.begin(), arr.end(), n); int ind = (ite - arr.begin()); ind--; pair<int, long long> te1 = doit(n - arr[ind]); pair<int, long long> te2 = doit(arr[ind] - 1 - arr[ind - 1]); if (te1.first > te2.first) return make_pair(te1.first + 1, te1.second + arr[ind]); if (te1.first < te2.first) return make_pair(te2.first + 1, te2.second + arr[ind - 1]); if (te1.second + arr[ind] > te2.second + arr[ind - 1]) return make_pair(te1.first + 1, te1.second + arr[ind]); return make_pair(te2.first + 1, te2.second + arr[ind - 1]); } int main() { for (long long i = 0; i <= 100001; i++) { arr.push_back(i * i * i); } long long m; cin >> m; pair<int, long long> temp = doit(m); cout << temp.first << << temp.second; return 0; } |
#include <bits/stdc++.h> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); using ll = long long; template <typename T> void DEBUG(string label, T value) { cerr << [ << label << = << value << ] n ; } const int oo = 1 << 30; void solve() { int n; cin >> n; int bsize; cin >> bsize; vector<int> arr(n + 2); for (int i = 1; i <= n; ++i) { cin >> arr[i]; arr[i] -= i; } arr[0] = -oo; arr[n + 1] = oo; vector<int> b(bsize + 2); for (int i = 1; i <= bsize; ++i) { cin >> b[i]; } b[0] = 0; b[bsize + 1] = n + 1; bsize += 2; n += 2; int ans = 0; for (int i = 0; i < bsize - 1; ++i) { if (arr[b[i]] > arr[b[i + 1]]) { cout << -1 << n ; return; } vector<int> dp; for (int j = b[i] + 1; j < b[i + 1]; ++j) { auto u = upper_bound(dp.begin(), dp.end(), arr[j]); if (arr[j] >= arr[b[i]] && arr[j] <= arr[b[i + 1]]) { if (u == dp.end()) { dp.push_back(arr[j]); } else { *u = arr[j]; } } } ans += b[i + 1] - b[i] - 1 - (int)dp.size(); } cout << ans << n ; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int t = 1; while (t--) solve(); } |
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_rd.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 2 read requests from 2 ports.
*
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_rd(
rstn,
sw_clk,
qos1,
qos2,
prt_req1,
prt_req2,
prt_bytes1,
prt_bytes2,
prt_addr1,
prt_addr2,
prt_data1,
prt_data2,
prt_dv1,
prt_dv2,
prt_req,
prt_qos,
prt_addr,
prt_bytes,
prt_data,
prt_dv
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input prt_req1, prt_req2;
input [addr_width-1:0] prt_addr1, prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2;
output reg prt_dv1, prt_dv2;
output reg [max_burst_bits-1:0] prt_data1,prt_data2;
output reg prt_req;
output reg [axi_qos_width-1:0] prt_qos;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
input [max_burst_bits-1:0] prt_data;
input prt_dv;
parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_dv_low = 2'b11;
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_req = 0;
if(prt_req1 && !prt_req2) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(!prt_req1 && prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req1 && prt_req2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_addr = prt_addr2;
prt_qos = qos2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1'b0;
if(prt_dv) begin
prt_dv1 = 1'b1;
prt_data1 = prt_data;
prt_req = 0;
if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
state = wait_dv_low;
//state = wait_req;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1'b0;
if(prt_dv) begin
prt_dv2 = 1'b1;
prt_data2 = prt_data;
prt_req = 0;
if(prt_req1) begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_dv_low;
//state = wait_req;
end
end
end
wait_dv_low:begin
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
state = wait_dv_low;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21O_1_V
`define SKY130_FD_SC_MS__A21O_1_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog wrapper for a21o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a21o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21o_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21o_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a21o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21O_1_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
iic_scl,
iic_sda,
adc_clk_p,
adc_clk_n,
adc_data_p,
adc_data_n,
adc_or_p,
adc_or_n,
spi_csn_clk,
spi_csn_adc,
spi_sclk,
spi_dio);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
inout iic_scl;
inout iic_sda;
input adc_clk_p;
input adc_clk_n;
input [11:0] adc_data_p;
input [11:0] adc_data_n;
input adc_or_p;
input adc_or_n;
output spi_csn_clk;
output spi_csn_adc;
output spi_sclk;
inout spi_dio;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire spi_miso;
wire spi_mosi;
wire spi_csn_adc;
wire spi_csn_clk;
// instantiations
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_gpio (
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_t (gpio_t[14:0]),
.dio_p (gpio_bd));
ad9434_spi i_spi (
.spi_csn({spi_csn_clk, spi_csn_adc}),
.spi_clk(spi_sclk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_dio)
);
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.spdif (spdif),
.adc_clk_p(adc_clk_p),
.adc_clk_n(adc_clk_n),
.adc_data_p(adc_data_p),
.adc_data_n(adc_data_n),
.adc_or_p(adc_or_p),
.adc_or_n(adc_or_n),
.spi0_clk_i (1'b0),
.spi0_clk_o (spi_sclk),
.spi0_csn_0_o (spi_csn_adc),
.spi0_csn_1_o (spi_csn_clk),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi_miso),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (spi_mosi));
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long int; ll ara[300005], ans_ara[300005]; set<ll> st; vector<pair<ll, ll> > vv; int main() { ll n, k, i, j, ans = 0; scanf( %I64d %I64d , &n, &k); for (i = 1; i <= n; i++) { scanf( %I64d , &ara[i]); ans -= (ara[i] * i); st.insert(i + k); vv.push_back({ara[i], i}); } sort(vv.rbegin(), vv.rend()); for (pair<ll, ll> u : vv) { ll num = *st.lower_bound(u.second); ans += (num * u.first); st.erase(st.lower_bound(u.second)); ans_ara[u.second] = num; } printf( %I64d n , ans); for (i = 1; i <= n; i++) { printf( %I64d , ans_ara[i]); } printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int nax = 505; int n; char grid[nax][nax]; int cc[nax][nax]; int cc_size[nax * nax]; int when_added[nax * nax]; const int dx[4] = {-1, 1, 0, 0}; const int dy[4] = {0, 0, -1, 1}; const char EMPTY = . ; bool inside(int x, int y) { return 0 <= min(x, y) && max(x, y) < n; } void dfs(int x, int y, int which_cc) { cc[x][y] = which_cc; ++cc_size[which_cc]; for (int i = 0; i < 4; ++i) { int x2 = x + dx[i]; int y2 = y + dy[i]; if (inside(x2, y2) && grid[x2][y2] == EMPTY && cc[x2][y2] == 0) dfs(x2, y2, which_cc); } } void add(int x, int y, int& answer, int current_time) { if (inside(x, y) && grid[x][y] == EMPTY) { int id = cc[x][y]; if (when_added[id] != current_time) { when_added[id] = current_time; answer += cc_size[id]; } } } int main() { int k; scanf( %d%d , &n, &k); for (int i = 0; i < n; ++i) scanf( %s , grid[i]); int how_many_cc = 0; for (int x = 0; x < n; ++x) for (int y = 0; y < n; ++y) if (grid[x][y] == EMPTY && cc[x][y] == 0) dfs(x, y, ++how_many_cc); int cur_time = 1; int best_answer = 0; for (int y_low = 0; y_low + k <= n; ++y_low) { for (int x = 0; x < k; ++x) for (int y = y_low; y < y_low + k; ++y) --cc_size[cc[x][y]]; for (int x_low = 0; x_low + k <= n; ++x_low) { int answer = k * k; for (int x = x_low; x < x_low + k; ++x) { add(x, y_low - 1, answer, cur_time); add(x, y_low + k, answer, cur_time); } for (int y = y_low; y < y_low + k; ++y) { add(x_low - 1, y, answer, cur_time); add(x_low + k, y, answer, cur_time); } ++cur_time; best_answer = max(best_answer, answer); if (x_low + k != n) { for (int y = y_low; y < y_low + k; ++y) { ++cc_size[cc[x_low][y]]; --cc_size[cc[x_low + k][y]]; } } } for (int x = n - k; x < n; ++x) for (int y = y_low; y < y_low + k; ++y) ++cc_size[cc[x][y]]; } printf( %d , best_answer); return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 15:51:43 09/10/2015
// Design Name: SN74LS195Agates and SN74LS195Abehavior
// Module Name: C:/Users/adam/Documents/GitHub/Lab1SN74LS195A/SN74LS195ARelativeTime.v
// Project Name: Lab1SN74LS195A
////////////////////////////////////////////////////////////////////////////////
module SN74LS195ARelativeTime;
reg [3:0] P;
reg PE, J, K, CP, MR;
wire Q3not_gate, Q3not_behavior;
wire [3:0] Qbehavior, Qgates;
SN74LS195Agates GatesChip (Qgates, P, Q3not_gate, PE, J, K, CP, MR);
SN74LS195Abehavior BehaviorChip (Qbehavior, P, Q3not_behavior, PE, J, K, CP, MR);
initial begin P = 0; PE = 0; J = 0; K = 0; CP = 0; MR = 0; end
always #5 CP = ~CP;
initial begin
MR = 1; P = 4'b1010; PE=0; J = 0; K = 0; #5; //reset
MR = 0; P = 4'b1010; PE=0; J = 0; K = 0; #18; //reset
MR = 1; P = 4'b1010; PE=0; J = 1; K = 1; #18; //parallel load
MR = 1; P = 4'b1010; PE=1; J = 1; K = 1; #18; //shift, set first stage
MR = 1; P = 4'b1010; PE=1; J = 0; K = 0; #18; //shift, reset first
MR = 1; P = 4'b1010; PE=1; J = 1; K = 0; #26; //shift, toggle first stage
MR = 1; P = 4'b1010; PE=1; J = 0; K = 1; #50; //shift, retain first stage
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; int pos[100005]; pair<int, long long> ai[4 * 100005]; void update_ai(int node, int l, int r, int pos, pair<int, long long> val) { if (l == r) { ai[node] = val; return; } int mid = (l + r) >> 1; if (pos <= mid) update_ai(2 * node, l, mid, pos, val); else update_ai(2 * node + 1, mid + 1, r, pos, val); ai[node].first = ai[2 * node].first + ai[2 * node + 1].first; ai[node].second = ai[2 * node].second + ai[2 * node + 1].second; } void query_ai(int node, int l, int r, int lq, int rq, pair<int, long long> &ans) { if (lq <= l && r <= rq) { ans.first += ai[node].first; ans.second += ai[node].second; return; } int mid = (l + r) >> 1; if (lq <= mid) query_ai(2 * node, l, mid, lq, rq, ans); if (mid + 1 <= rq) query_ai(2 * node + 1, mid + 1, r, lq, rq, ans); } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) { int x; scanf( %d , &x); pos[x] = i; } double sol = 0; for (int i = 1; i <= n; ++i) { pair<int, long long> x = make_pair(0, 0); query_ai(1, 1, n, 1, pos[i], x); sol += ((double)(n - pos[i] + 1)) / n * (((double)x.second) / (n + 1)); x = make_pair(0, 0); query_ai(1, 1, n, pos[i], n, x); sol += x.first - ((double)pos[i]) / n * (x.first - ((double)x.second) / (n + 1)); update_ai(1, 1, n, pos[i], make_pair(1, pos[i])); } printf( %.20f n , sol); return 0; } |
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: VgaPll.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module vga_pll (
clock_in,
clock_out);
input clock_in;
output clock_out;
wire [5:0] clock_output_bus;
wire [1:0] clock_input_bus;
wire gnd;
assign gnd = 1'b0;
assign clock_input_bus = { gnd, clock_in };
altpll altpll_component (
.inclk (clock_input_bus),
.clk (clock_output_bus)
);
defparam
altpll_component.operation_mode = "NORMAL",
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_type = "altpll",
altpll_component.pll_type = "FAST",
/* Specify the input clock to be a 50MHz clock. A 50 MHz clock is present
* on PIN_N2 on the DE2 board. We need to specify the input clock frequency
* in order to set up the PLL correctly. To do this we must put the input clock
* period measured in picoseconds in the inclk0_input_frequency parameter.
* 1/(20000 ps) = 0.5 * 10^(5) Hz = 50 * 10^(6) Hz = 50 MHz. */
altpll_component.inclk0_input_frequency = 20000,
altpll_component.primary_clock = "INCLK0",
/* Specify output clock parameters. The output clock should have a
* frequency of 25 MHz, with 50% duty cycle. */
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0",
altpll_component.clk0_divide_by = 2,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_duty_cycle = 50;
assign clock_out = clock_output_bus[0];
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC ""
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: PLL_TYPE STRING "FAST"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VgaPll_bb.v FALSE FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4B_4_V
`define SKY130_FD_SC_HD__NAND4B_4_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4b_4 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nand4b_4 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4B_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, x, y; cin >> n >> m >> x >> y; vector<vector<int>> chessboard(n, vector<int>(m)); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) chessboard[i][j] = 0; cout << x << << y << endl; chessboard[x - 1][y - 1] = 1; if (chessboard[0][y - 1] == 0) cout << 1 << << y << endl; chessboard[0][y - 1] = 1; if (chessboard[0][0] == 0) cout << 1 << << 1 << endl; chessboard[0][0] = 1; int j = 0; for (int i = 0; i < n; i++) { if (j == m) j--; if (j < 0) j++; bool plus = (j == 0); while (j >= 0 && j < m) { if (chessboard[i][j] == 0) { cout << i + 1 << << j + 1 << endl; chessboard[i][j] = 1; } (plus) ? j++ : j--; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211AI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O211AI_BEHAVIORAL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o211ai (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211AI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32AI_4_V
`define SKY130_FD_SC_HS__O32AI_4_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o32ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o32ai_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32AI_4_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n = 1000 + 1000 + 1; printf( %d n , n); for (int i = (int)(1); i <= (int)(1000); ++i) printf( %d %d %d %d n , i, 1, i, 2); puts( 1 1 1 2 ); for (int i = (int)(1); i <= (int)(1000); ++i) printf( %d %d %d %d n , i, 1, i, 2); return 0; } |
#include <bits/stdc++.h> using namespace std; const double pi = acos((double)(-1)); const int maxn = 100010; const int mod = 1e9 + 7; int moven2[10][5] = {{1, 0, 0}, {-1, 0, 0}, {0, 1, 0}, {0, -1, 0}, {0, 0, 1}, {0, 0, -1}}; int moven1[10][5] = {{1, 0}, {-1, 0}, {0, 1}, {0, -1}}; int n, m, q, f[2 * maxn]; map<string, int> mp; string a, b; int find(int x) { return f[x] == x ? x : f[x] = find(f[x]); } void Union(int x, int y) { int fx = find(x); int fy = find(y); f[fx] = fy; } int main() { cin >> n >> m >> q; for (int i = 1; i <= n; i++) { cin >> a; mp[a] = i; } for (int i = 1; i <= 2 * n; i++) f[i] = i; for (int i = 1, t; i <= m; i++) { cin >> t >> a >> b; int x = mp[a]; int y = mp[b]; if (t == 1) { if (find(x) == find(y + n) || find(y) == find(x + n)) cout << NO << n ; else { cout << YES << n ; Union(x, y); Union(x + n, y + n); } } else { if (find(x) == find(y) || find(x + n) == find(y + n)) cout << NO << n ; else { cout << YES << n ; Union(x + n, y); Union(x, y + n); } } } for (int i = 1; i <= q; i++) { cin >> a >> b; int x = mp[a]; int y = mp[b]; if (find(x) == find(y) || find(x + n) == find(y + n)) cout << 1 << n ; else if (find(x + n) == find(y) || find(x) == find(y + n)) cout << 2 << n ; else cout << 3 << n ; } return 0; } |
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
module small_fifo
#(parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1
)
(
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output empty,
input reset,
input clk
);
parameter MAX_DEPTH = 2 ** MAX_DEPTH_BITS;
reg [WIDTH-1:0] queue [MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
reg [MAX_DEPTH_BITS : 0] depth;
// Sample the data
always @(posedge clk)
begin
if (wr_en)
queue[wr_ptr] <= din;
if (rd_en)
dout <=
// synthesis translate_off
#1
// synthesis translate_on
queue[rd_ptr];
end
always @(posedge clk)
begin
if (reset) begin
rd_ptr <= 'h0;
wr_ptr <= 'h0;
depth <= 'h0;
end
else begin
if (wr_en) wr_ptr <= wr_ptr + 'h1;
if (rd_en) rd_ptr <= rd_ptr + 'h1;
if (wr_en & ~rd_en) depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth + 'h1;
else if (~wr_en & rd_en) depth <=
// synthesis translate_off
#1
// synthesis translate_on
depth - 'h1;
end
end
//assign dout = queue[rd_ptr];
assign full = depth == MAX_DEPTH;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= MAX_DEPTH-1;
assign empty = depth == 'h0;
// synthesis translate_off
always @(posedge clk)
begin
if (wr_en && depth == MAX_DEPTH && !rd_en)
$display($time, " ERROR: Attempt to write to full FIFO: %m");
if (rd_en && depth == 'h0)
$display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
endmodule // small_fifo
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
#include <bits/stdc++.h> using namespace std; const int fx[] = {+0, +0, +1, -1, -1, +1, -1, +1}; const int fy[] = {-1, +1, +0, +0, +1, +1, -1, -1}; long long dp[1005][1005][2]; string s; int k; int ar[1026]; long long Dance_of_Death(int x, int rem, int f) { if (x == s.size()) { if (ar[rem] + 1 == k) { return 1; } else { return 0; } } if (dp[x][rem][f] != -1) { return dp[x][rem][f]; } long long y = 0; if (!f && s[x] == 0 ) { y = Dance_of_Death(x + 1, rem, 0) % 1000000007; } if (f) { y = Dance_of_Death(x + 1, rem, f) % 1000000007; y = (y + Dance_of_Death(x + 1, rem + 1, f)) % 1000000007; } if (f == 0 && s[x] == 1 ) { y = Dance_of_Death(x + 1, rem, 1) % 1000000007; y = (y + Dance_of_Death(x + 1, rem + 1, f)) % 1000000007; } return dp[x][rem][f] = y; } void build() { ar[1] = 0; for (int i = 2; i < 1026; i++) { int x = i; int c = 0; while (x) { if (x % 2) { c++; } x /= 2; } ar[i] = ar[c] + 1; } ar[0] = 10000; } int main() { build(); cin >> s; cin >> k; memset(dp, -1, sizeof(dp)); if (k == 0) { cout << 1 << endl; return 0; } int f = 0; if (k == 1) { f = 1; } cout << Dance_of_Death(0, 0, 0) - f << endl; } |
#include <bits/stdc++.h> using namespace std; #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) const int tam = 100010; const int MOD = 1000000007; const int MOD1 = 998244353; const double DINF = 1e100; const double EPS = 1e-9; const double PI = acos(-1); void solve() { int n; cin >> n; vector<int> ar(n); bool bo = true; for (int i = 0; i < n; i++) { cin >> ar[i]; bo &= ar[i] & 1 ^ i; } if (!bo) { cout << -1 << n ; return; } int a, b; vector<int> res; for (int i = n; i > 1; i -= 2) { for (int j = 0; j < i; j++) { if (ar[j] == i) a = j + 1; if (ar[j] == i - 1) b = j + 1; } if (a == i && b == i - 1) { continue; } if (a != 1) { res.push_back(a); reverse(ar.begin(), ar.begin() + a); for (int j = 0; j < i; j++) if (ar[j] == i - 1) b = j + 1; } if (b != 2) { res.push_back(b - 1); reverse(ar.begin(), ar.begin() + b - 1); res.push_back(b + 1); reverse(ar.begin(), ar.begin() + b + 1); res.push_back(3); reverse(ar.begin(), ar.begin() + 3); } res.push_back(i); reverse(ar.begin(), ar.begin() + i); } cout << res.size() << n ; for (int x : res) cout << x << ; if (res.size()) cout << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 5; long long R = 1, n, q, arr[N]; vector<long long> a[N]; long long h[N], p[N][20]; long long cnt = 0, st[N], en[N], pos[2 * N]; long long it[8 * N], lz[8 * N]; void dfs(long long u) { st[u] = ++cnt; pos[cnt] = arr[u]; for (long long i = 1; i < 17; ++i) p[u][i] = p[p[u][i - 1]][i - 1]; for (long long i = 0; i < a[u].size(); ++i) { long long v = a[u][i]; if (v == p[u][0]) continue; h[v] = h[u] + 1; p[v][0] = u; dfs(v); } en[u] = ++cnt; pos[cnt] = arr[u]; } long long par(long long u, long long d) { for (long long i = 0; i < 17; ++i) if ((d >> i & 1)) u = p[u][i]; return u; } long long lca(long long u, long long v) { if (h[u] != h[v]) { if (h[u] < h[v]) swap(u, v); u = par(u, h[u] - h[v]); } if (u == v) return u; for (long long i = 16; i >= 0; --i) if (p[u][i] != p[v][i]) { u = p[u][i]; v = p[v][i]; } return p[u][0]; } void build_IT(long long i, long long l, long long r) { if (l == r) { it[i] = pos[l]; return; } long long m = (l + r) / 2; build_IT(i * 2, l, m); build_IT(i * 2 + 1, m + 1, r); it[i] = it[i * 2] + it[i * 2 + 1]; } void true_val(long long i, long long l, long long r) { if (lz[i] == 0) return; it[i] += (r - l + 1) * lz[i]; if (l != r) { lz[i * 2] += lz[i]; lz[i * 2 + 1] += lz[i]; } lz[i] = 0; } void update(long long i, long long l, long long r, long long a, long long b, long long val) { true_val(i, l, r); if (l > b || r < a || l > r) return; if (a <= l && r <= b) { it[i] += (r - l + 1) * val; if (l != r) { lz[i * 2] += val; lz[i * 2 + 1] += val; } return; } long long m = (l + r) / 2; update(i * 2, l, m, a, b, val); update(i * 2 + 1, m + 1, r, a, b, val); it[i] = it[i * 2] + it[i * 2 + 1]; } long long get(long long i, long long l, long long r, long long a, long long b) { true_val(i, l, r); if (l > b || r < a || l > r) return 0; if (a <= l && r <= b) return it[i]; long long m = (l + r) / 2; return get(i * 2, l, m, a, b) + get(i * 2 + 1, m + 1, r, a, b); } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); scanf( %lld%lld , &n, &q); for (long long i = 1; i <= n; ++i) scanf( %lld , &arr[i]); for (long long i = 1; i < n; ++i) { long long x, y; scanf( %lld%lld , &x, &y); a[x].push_back(y); a[y].push_back(x); } dfs(1); n *= 2; build_IT(1, 1, n); while (q--) { long long t; scanf( %lld , &t); if (t == 1) { scanf( %lld , &R); continue; } if (t == 3) { long long u, ans = 0; scanf( %lld , &u); if (lca(R, u) != u) ans = get(1, 1, n, st[u], en[u]); else if (R == u) ans = it[1]; else { long long z = par(R, h[R] - h[u] - 1); ans = it[1] - get(1, 1, n, st[z], en[z]); } printf( %lld n , ans / 2); continue; } long long u, v, val; scanf( %lld%lld%lld , &u, &v, &val); long long x = lca(u, v); if (lca(x, R) != x) update(1, 1, n, st[x], en[x], val); else { long long a = lca(u, R), b = lca(v, R); long long w = (a == x ? b : a); update(1, 1, n, 1, n, val); if (w != R) { long long z = par(R, h[R] - h[w] - 1); update(1, 1, n, st[z], en[z], -val); } } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_4_V
`define SKY130_FD_SC_LP__NAND2_4_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_4_V
|
module ds8dac1(clk, PWM_in, PWM_out);
input clk;
input [7:0] PWM_in;
output reg PWM_out;
reg [8:0] PWM_accumulator;
reg [7:0] PWM_add;
initial
begin
PWM_accumulator <= 0;
PWM_add <=0;
end
always @(posedge clk) begin
PWM_accumulator <= PWM_accumulator[7:0] + PWM_add;
PWM_add <= PWM_in;
end
always @(negedge clk) begin
PWM_out <= PWM_accumulator[8];
end
endmodule
/*
// Delta-Sigma DAC
module ds8dac1(clk, DACin, DACout);
output DACout; // This is the average output that feeds low pass filter
reg DACout; // for optimum performance, ensure that this ff is in IOB
input [7:0] DACin; // DAC input
input clk;
reg [9:0] DeltaAdder; // Output of Delta adder
reg [9:0] SigmaAdder; // Output of Sigma adder
reg [9:0] SigmaLatch; // Latches output of Sigma adder
reg [9:0] DeltaB; // B input of Delta adder
initial
begin
DeltaAdder = 10'd0;
SigmaAdder = 10'd0;
SigmaLatch = 10'd0;
DeltaB = 10'd0;
end
always @(SigmaLatch) DeltaB = {SigmaLatch[9], SigmaLatch[9]} << (8);
always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge clk)
begin
SigmaLatch <= SigmaAdder;
DACout <= SigmaLatch[9];
end
endmodule*/ |
//-----------------------------------------------------------------------------
//-- Secuenciador de notas
//-- Se tocan por el mismo canal las notas DO, RE, MI, (silencio) repetidamente
//-----------------------------------------------------------------------------
//-- (C) BQ. August 2015. Written by Juan Gonzalez
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
//-- Incluir las constantes del modulo del divisor
`include "divider.vh"
//-- Parameteros:
//-- clk: Reloj de entrada de la placa iCEstick
//-- ch_out: Canal de salida
module secnotas(input wire clk, output reg ch_out);
//-- Parametros: notas a tocar
//-- Se define como parametro para poder modificarlas desde el testbench
//-- para hacer pruebas
parameter N0 = `DO_4;
parameter N1 = `RE_4;
parameter N2 = `MI_4;
parameter DUR = `T_250ms;
//-- Cables de salida de los canales
wire ch0, ch1, ch2;
//-- Selección del canal del multiplexor
reg [1:0] sel = 0;
//-- Reloj con la duracion de la nota
wire clk_dur;
//-- Canal 0
divider #(N0)
CH0 (
.clk_in(clk),
.clk_out(ch0)
);
//-- Canal 1
divider #(N1)
CH1 (
.clk_in(clk),
.clk_out(ch1)
);
//-- canal 2
divider #(N2)
CH2 (
.clk_in(clk),
.clk_out(ch2)
);
//-- Multiplexor de seleccion del canal de salida
always @*
case (sel)
0 : ch_out <= ch0;
1 : ch_out <= ch1;
2 : ch_out <= ch2;
3 : ch_out <= 0;
default : ch_out <= 0;
endcase
//-- Contador para seleccion de nota
always @(posedge clk_dur)
sel <= sel + 1;
//-- Divisor para marcar la duración de cada nota
divider #(DUR)
TIMER0 (
.clk_in(clk),
.clk_out(clk_dur)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2010, mod = 998244353; int sm[2][N], n, f[N][N], a[N][N], ans; void add(int x, int y, int z) { for (; x <= n; x += x & -x) sm[z][x] += y; } int query(int x, int z) { int ret = 0; for (; x; x -= x & -x) ret += sm[z][x]; return ret; } void Init() { f[0][0] = 1; for (int i = 1; i <= n; ++i) { f[i][0] = (long long)f[i - 1][0] * i % mod; for (int j = 1; j <= i; ++j) f[i][j] = (f[i][j - 1] - f[i - 1][j - 1] + mod) % mod; } } int p[N], q[N]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; Init(); for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) cin >> a[i][j]; for (int i = 1; i <= n; ++i) { int les = n; ans = (long long)ans * f[n][n] % mod; memset(sm, 0, sizeof sm); memset(p, 0, sizeof p); memset(q, 0, sizeof q); for (int j = 1; j <= n; ++j) { int u = query(a[i][j] - 1, 0); p[a[i - 1][j]] = 1; if (q[a[i - 1][j]]) ++les; else if (a[i - 1][j]) add(a[i - 1][j], 1, 0), add(a[i - 1][j], 1, 1); int v = a[i][j] - 1 - query(a[i][j] - 1, 1); les -= 2; if (i == 1) ans = (ans + (long long)v * f[n - j][0]) % mod; else ans = (ans + (long long)u * f[n - j][les + 1] + (long long)v * f[n - j][les]) % mod; q[a[i][j]] = 1; if (p[a[i][j]]) add(a[i][j], -1, 0), ++les; else add(a[i][j], 1, 1); } } cout << ans << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4B_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__AND4B_PP_BLACKBOX_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4B_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND2_SYMBOL_V
`define SKY130_FD_SC_HD__TAPVGND2_SYMBOL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvgnd2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND2_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, i, j; string s1, s2; cin >> n >> s1 >> s2; if (s2 == week ) { if (n == 5 || n == 6) { cout << 53 << endl; } else { cout << 52 << endl; } } else { if (n <= 29) { cout << 12 << endl; } else if (n == 30) { cout << 11 << endl; } else if (n == 31) { cout << 7 << endl; } } } |
#include <bits/stdc++.h> const long long int M = 1e9 + 7; using namespace std; bool visit[100000]; vector<int> G[100000]; void dfs1(int v, stack<int> &s) { visit[v] = true; for (int i = 0; i < G[v].size(); i++) { int c = G[v][i]; if (!visit[c]) dfs1(c, s); } s.push(v); } void dfs(int n) { stack<int> s; for (int i = 1; i <= n; i++) if (!visit[i]) dfs1(i, s); while (!s.empty()) { cout << s.top() << ; s.pop(); } } int main() { ios::sync_with_stdio(false); int n, m, i, a, b; cin >> n >> m; for (i = 0; i < m; i++) { cin >> a >> b; G[b].push_back(a); } dfs(n); return 0; } |
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 15.1 cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module hps_sdram_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //hps_sdram_p0_clock_pair_generator
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; long long n, k, s[30][105], cnt[105]; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> k; string t; cin >> t; s[t[0] - a ][1] = 1; for (int i = 1; i < t.size(); i++) { int u = t[i] - a ; for (int j = i + 1; j >= 2; j--) { s[u][j] = 0; for (int k = 0; k < 26; k++) { s[u][j] += s[k][j - 1]; } } s[u][1] = 1; } for (int i = 0; i < 26; i++) { for (int j = 1; j <= t.size(); j++) { cnt[j] += s[i][j]; } } cnt[0] = 1; long long res = 0, id = t.size(); while (k > 0) { long long u = min(k, cnt[id]); k -= u; res += (n - id) * u; id--; if (id < 0) break; } if (k > 0) return cout << -1, 0; cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long int pwr(long long int a, long long int n, long long int m) { long long int p = 1; while (n > 0) { if (n % 2 == 1) p = (p * a) % m; a = (a * a) % m; n = n / 2; } return p; } char str[1000000]; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int n, a, b, k, s = 0, i, j; cin >> n >> a >> b >> k; long long int f = pwr(b, k, (long long int)(1e9 + 9)); long long int g = pwr(a, k, (long long int)(1e9 + 9)); long long int r = (f * pwr(g, (long long int)(1e9 + 9) - 2, (long long int)(1e9 + 9))) % (long long int)(1e9 + 9); r = ((pwr(r, (n + 1) / k, (long long int)(1e9 + 9)) - 1 + (long long int)(1e9 + 9)) % (long long int)(1e9 + 9) * pwr(r - 1, (long long int)(1e9 + 9) - 2, (long long int)(1e9 + 9))) % (long long int)(1e9 + 9); if (r == 0) r = (n + 1) / k; cin >> str; for (i = 0; i < k; i++) { if (str[i] == + ) s = (s + (pwr(a, n - i, (long long int)(1e9 + 9)) * pwr(b, i, (long long int)(1e9 + 9))) % (long long int)(1e9 + 9) + (long long int)(1e9 + 9)) % (long long int)(1e9 + 9); else s = (s - (pwr(a, n - i, (long long int)(1e9 + 9)) * pwr(b, i, (long long int)(1e9 + 9))) % (long long int)(1e9 + 9) + (long long int)(1e9 + 9)) % (long long int)(1e9 + 9); } cout << ((s * r) % (long long int)(1e9 + 9) + (long long int)(1e9 + 9)) % (long long int)(1e9 + 9) << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31AI_TB_V
`define SKY130_FD_SC_HD__O31AI_TB_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o31ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hd__o31ai dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31AI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__AND3_PP_BLACKBOX_V
/**
* and3: 3-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3_PP_BLACKBOX_V
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [15:0] featurebits,
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // want to access RAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output cx4_enable,
output cx4_vect_enable,
output r213f_enable,
output r2100_hit,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable,
output branch3_enable
);
parameter [2:0]
FEAT_MSU1 = 3,
FEAT_213F = 4,
FEAT_2100 = 6
;
wire [23:0] SRAM_SNES_ADDR;
/* Cx4 mapper:
- LoROM (extended to 00-7d, 80-ff)
- MMIO @ 6000-7fff
- SRAM @ 70-77:0000-7fff
*/
assign IS_ROM = ~SNES_ROMSEL;
assign IS_SAVERAM = |SAVERAM_MASK & (~SNES_ADDR[23] & &SNES_ADDR[22:20] & ~SNES_ADDR[19] & ~SNES_ADDR[15]);
assign SRAM_SNES_ADDR = IS_SAVERAM
? (24'hE00000 | ({SNES_ADDR[19:16], SNES_ADDR[14:0]}
& SAVERAM_MASK))
: ({2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]}
& ROM_MASK);
assign ROM_ADDR = SRAM_SNES_ADDR;
assign IS_WRITABLE = IS_SAVERAM;
assign ROM_HIT = IS_ROM | IS_WRITABLE;
wire msu_enable_w = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
assign msu_enable = msu_enable_w;
wire cx4_enable_w = (!SNES_ADDR[22] && (SNES_ADDR[15:13] == 3'b011));
assign cx4_enable = cx4_enable_w;
assign cx4_vect_enable = &SNES_ADDR[15:5];
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign r2100_hit = (SNES_PA == 8'h00);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A6C);
assign branch1_enable = (SNES_ADDR == 24'h002A1F);
assign branch2_enable = (SNES_ADDR == 24'h002A59);
assign branch3_enable = (SNES_ADDR == 24'h002A5E);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:10:36 04/11/2015
// Design Name:
// Module Name: MEMWB_Voter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Processor_Voter(
input [1853:0] Vote_0_in,
input [1853:0] Vote_1_in,
input [1853:0] Vote_2_in,
output [1853:0] Vote_out
);
Voter #(.WIDTH(2)) InstructionInterface_VOTER (
.A (Vote_0_in[1:0]),
.B (Vote_1_in[1:0]),
.C (Vote_2_in[1:0]),
.True (Vote_out[1:0])
);
Voter #(.WIDTH(193)) CP0_VOTER (
.A (Vote_0_in[194:2]),
.B (Vote_1_in[194:2]),
.C (Vote_2_in[194:2]),
.True (Vote_out[194:2])
);
Voter #(.WIDTH(32)) PC_VOTER (
.A (Vote_0_in[226:195]),
.B (Vote_1_in[226:195]),
.C (Vote_2_in[226:195]),
.True (Vote_out[226:195])
);
Voter #(.WIDTH(98)) IFID_VOTER (
.A (Vote_0_in[324:227]),
.B (Vote_1_in[324:227]),
.C (Vote_2_in[324:227]),
.True (Vote_out[324:227])
);
Voter #(.WIDTH(992)) RegisterFile_VOTER (
.A (Vote_0_in[1316:325]),
.B (Vote_1_in[1316:325]),
.C (Vote_2_in[1316:325]),
.True (Vote_out[1316:325])
);
Voter #(.WIDTH(154)) IDEX_VOTER (
.A (Vote_0_in[1470:1317]),
.B (Vote_1_in[1470:1317]),
.C (Vote_2_in[1470:1317]),
.True (Vote_out[1470:1317])
);
Voter #(.WIDTH(65)) ALU_VOTER (
.A (Vote_0_in[1535:1471]),
.B (Vote_1_in[1535:1471]),
.C (Vote_2_in[1535:1471]),
.True (Vote_out[1535:1471])
);
Voter #(.WIDTH(98)) Divider_VOTER (
.A (Vote_0_in[1633:1536]),
.B (Vote_1_in[1633:1536]),
.C (Vote_2_in[1633:1536]),
.True (Vote_out[1633:1536])
);
Voter #(.WIDTH(117)) EXMEM_VOTER (
.A (Vote_0_in[1750:1634]),
.B (Vote_1_in[1750:1634]),
.C (Vote_2_in[1750:1634]),
.True (Vote_out[1750:1634])
);
Voter #(.WIDTH(32)) DataInterface_VOTER (
.A (Vote_0_in[1782:1751]),
.B (Vote_1_in[1782:1751]),
.C (Vote_2_in[1782:1751]),
.True (Vote_out[1782:1751])
);
Voter #(.WIDTH(71)) MEMWB_VOTER (
.A (Vote_0_in[1853:1783]),
.B (Vote_1_in[1853:1783]),
.C (Vote_2_in[1853:1783]),
.True (Vote_out[1853:1783])
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_TB_V
`define SKY130_FD_SC_HDLL__CLKBUF_TB_V
/**
* clkbuf: Clock tree buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkbuf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hdll__clkbuf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_TB_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module sp_mux_5to1_sel3_4_1 #(
parameter
ID = 0,
NUM_STAGE = 1,
din1_WIDTH = 32,
din2_WIDTH = 32,
din3_WIDTH = 32,
din4_WIDTH = 32,
din5_WIDTH = 32,
din6_WIDTH = 32,
dout_WIDTH = 32
)(
input [3 : 0] din1,
input [3 : 0] din2,
input [3 : 0] din3,
input [3 : 0] din4,
input [3 : 0] din5,
input [2 : 0] din6,
output [3 : 0] dout);
// puts internal signals
wire [2 : 0] sel;
// level 1 signals
wire [3 : 0] mux_1_0;
wire [3 : 0] mux_1_1;
wire [3 : 0] mux_1_2;
// level 2 signals
wire [3 : 0] mux_2_0;
wire [3 : 0] mux_2_1;
// level 3 signals
wire [3 : 0] mux_3_0;
assign sel = din6;
// Generate level 1 logic
assign mux_1_0 = (sel[0] == 0)? din1 : din2;
assign mux_1_1 = (sel[0] == 0)? din3 : din4;
assign mux_1_2 = din5;
// Generate level 2 logic
assign mux_2_0 = (sel[1] == 0)? mux_1_0 : mux_1_1;
assign mux_2_1 = mux_1_2;
// Generate level 3 logic
assign mux_3_0 = (sel[2] == 0)? mux_2_0 : mux_2_1;
// output logic
assign dout = mux_3_0;
endmodule
|
#include <bits/stdc++.h> using namespace std; void __print(unsigned x) { cerr << x; } void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } void __print(char x) { cerr << << x << ; } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } int n, x; vector<int> visited; vector<int> g[20000]; void dfs(int u, int deep) { visited[u] = deep; for (int v : g[u]) { if (!visited[v]) { dfs(v, deep + 1); } } } void solve() { cin >> n >> x; x--; for (int i = 0; i < n; i += 1) g[i].clear(); visited.clear(); visited.resize(n); int e = n - 1; while (e--) { int u, v; cin >> u >> v; u--; v--; g[u].emplace_back(v); g[v].emplace_back(u); }; if (g[x].size() <= 1) { cout << Ayush n ; return; } int ans = 0; dfs(x, 1); for (int &x : visited) x--; vector<int> dis = visited; sort(dis.begin(), dis.end()); ans = dis[n - 1] + dis[n - 2]; int t = n - ans - 1; if (ans & 1) { if (t & 1) { cout << Ashish n ; } else cout << Ayush n ; } else { if (t & 1) cout << Ayush n ; else cout << Ashish n ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tc; cin >> tc; while (tc--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } template <class T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T, class T1> inline void gn(T &first, T1 &second) { gn(first); gn(second); } template <class T, class T1, class T2> inline void gn(T &first, T1 &second, T2 &z) { gn(first); gn(second); gn(z); } template <class T> inline void print(T first) { if (first < 0) { putchar( - ); return print(-first); } if (first < 10) { putchar( 0 + first); return; } print(first / 10); putchar(first % 10 + 0 ); } template <class T> inline void printsp(T first) { print(first); putchar( ); } template <class T> inline void println(T first) { print(first); putchar( n ); } template <class T, class U> inline void print(T first, U second) { printsp(first); println(second); } template <class T, class U, class V> inline void print(T first, U second, V z) { printsp(first); printsp(second); println(z); } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } const int C = 333333; vector<int> adj[C]; int root[C], sz[C], d[C], src; pair<int, int> f; int find_root(int u) { return (root[u] == u ? u : root[u] = find_root(root[u])); } void add(int u, int v) { int uu = find_root(u), vv = find_root(v); if (uu == vv) return; sz[vv] += sz[uu]; root[uu] = vv; smax(d[vv], max(d[uu], (1 + d[uu]) / 2 + (1 + d[vv]) / 2 + 1)); } void dfs(int u, int dp = 0) { root[u] = src; sz[src]++; if (dp > f.second) { f.second = dp; f.first = u; } for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (root[v]) continue; dfs(v, dp + 1); } } void rdfs(int u, int dp = 0, int fa = 0) { smax(d[src], dp); for (int i = 0; i < adj[u].size(); i++) { int v = adj[u][i]; if (v == fa) continue; rdfs(v, dp + 1, u); } } void solve_C() { int n, m, q, u, v; gn(n, m, q); for (int i = 0; i < m; i++) { gn(u, v); adj[u].push_back(v); adj[v].push_back(u); } for (int i = 1; i <= n; i++) if (!root[i]) { f.first = i; f.second = 0; src = i; dfs(i); rdfs(f.first); } while (q--) { int t; gn(t); if (t == 1) { gn(u); u = find_root(u); println(d[u]); } else { gn(u, v); add(u, v); } } exit(0); } int main() { solve_C(); return 0; } |
#include <bits/stdc++.h> using namespace std; int a[101], k, i, n, check[101][101], j = 0, kil1, kil2, ans; int main() { cin >> n >> k; for (i = 1; i <= n; i++) { cin >> a[i]; } for (i = 1; i <= k; i++) { kil1 = 0; kil2 = 0; for (j = i; j <= n; j += k) { if (a[j] == 1) kil1++; else kil2++; } ans += min(kil1, kil2); } cout << ans << endl; return 0; } |
module register_file_testbench;
reg[1:0] read_register_port_0;
reg[1:0] read_register_port_1;
reg[1:0] write_register;
reg[31:0] write_data;
reg write_enable;
wire[31:0] read_data_port_0;
wire[31:0] read_data_port_1;
register_file rf(read_register_port_0, read_register_port_1,
write_register, write_data, write_enable,
read_data_port_0, read_data_port_1);
initial
begin
$dumpfile("register-file-test.vcd");
$dumpvars(0, register_file_testbench);
$monitor("read_register_port_0=%d write_register=%d write_data=%d write_enable=%d read_data_port_0=%d",
read_register_port_0, write_register, write_data,
write_enable, read_data_port_0);
#0 write_enable = 'b0;
#0 write_data = 'd21;
#0 write_register = 'b00;
#1 write_enable = 'b1;
#1 write_enable = 'b0;
#0 write_register = 'b01;
#0 write_data = 'd42;
#1 write_enable = 'b1;
#1 write_enable = 'b0;
#0 write_register = 'b10;
#0 write_data = 'd84;
#1 write_enable = 'b1;
#1 write_enable = 'b0;
#0 write_register = 'b11;
#0 write_data = 'd168;
#1 write_enable = 'b1;
#1 write_enable = 'b0;
#1 read_register_port_0 = 'b00;
#1 read_register_port_0 = 'b01;
#1 read_register_port_0 = 'b10;
#1 read_register_port_0 = 'b11;
end
endmodule
|
module top;
typedef reg [4:0] T1;
typedef T1 [7:0] T2;
T2 q_tst [$:2];
T2 q_tmp [$];
bit passed;
task automatic check_size(integer size,
string fname,
integer lineno);
if (q_tst.size !== size) begin
$display("%s:%0d: Failed: queue size != %0d (%0d)",
fname, lineno, size, q_tst.size);
passed = 1'b0;
end
endtask
task automatic check_idx_value(integer idx,
T2 expected,
string fname,
integer lineno);
if (q_tst[idx] != expected) begin
$display("%s:%0d: Failed: element [%0d] != %0d (%0d)",
fname, lineno, idx, expected, q_tst[idx]);
passed = 1'b0;
end
endtask
initial begin
passed = 1'b1;
check_size(0, `__FILE__, `__LINE__);
q_tst.push_back(2);
q_tst.push_front(1);
q_tst.push_back(3);
q_tst.push_back(100); // Warning: item not added.
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 1, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
check_idx_value(2, 3, `__FILE__, `__LINE__);
q_tst.push_front(5); // Warning: back item removed.
q_tst[3] = 3; // Warning: item not added.
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 5, `__FILE__, `__LINE__);
check_idx_value(1, 1, `__FILE__, `__LINE__);
check_idx_value(2, 2, `__FILE__, `__LINE__);
q_tst.insert(3, 10); // Warning: item not added.
q_tst.insert(1, 2); // Warning: back item removed.
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 5, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
check_idx_value(2, 1, `__FILE__, `__LINE__);
q_tst = '{1, 2, 3, 4}; // Warning: items not added.
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 1, `__FILE__, `__LINE__);
check_idx_value(1, 2, `__FILE__, `__LINE__);
check_idx_value(2, 3, `__FILE__, `__LINE__);
q_tmp = '{4, 3, 2, 1};
q_tst = q_tmp; // Warning not all items copied
q_tmp[0] = 5;
check_size(3, `__FILE__, `__LINE__);
check_idx_value(0, 4, `__FILE__, `__LINE__);
check_idx_value(1, 3, `__FILE__, `__LINE__);
check_idx_value(2, 2, `__FILE__, `__LINE__);
if (passed) $display("PASSED");
end
endmodule : top
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__DECAP_FUNCTIONAL_PP_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__decap (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAP_FUNCTIONAL_PP_V |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_start_event;
wire valid_test_expr;
assign valid_start_event = ~(start_event ^ start_event);
assign valid_test_expr = ~(test_expr ^ test_expr);
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_ASSERT_ON
// local parameters
parameter num_cks = (max_cks>min_cks)?max_cks:min_cks;
parameter FRAME_START = 1'b0;
parameter FRAME_CHECK = 1'b1;
reg r_state;
reg r_start_event;
integer ii;
always @(posedge clk)
if (`OVL_RESET_SIGNAL == 1'b0) // active low reset
r_start_event <= 1'b1; // reset high to avoid fail straight out of reset
else
r_start_event <= start_event;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
case (r_state)
FRAME_START: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
// assert_frame() behaves like assert_implication()
// when min_cks==0 and max_cks==0
if ((min_cks==0) && (max_cks==0)) begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if ( (r_start_event == 1'b0) && (start_event == 1'b1) )
begin
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if ((r_start_event == 1'b0) && (start_event==1'b1) &&
(test_expr==1'b0)) begin
// FAIL, it does not behave like assert_implication()
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not TRUE while start event is asserted when both parameters min_cks and max_cks are set to 0");
end
end
// wait for start_event (0->1)
else if ((r_start_event == 1'b0) && (start_event == 1'b1)) begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if ((min_cks != 0) && (test_expr==1'b1)) begin
// FAIL, test_expr should not happen before min_cks
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is TRUE before elapse of specified minimum min_cks cycles from start event");
end
else if (!(min_cks == 0 && test_expr == 1'b1)) begin
r_state <= FRAME_CHECK;
ii <= 1;
end
end
end
FRAME_CHECK:
// start_event (0->1) has occurred
// start checking
begin
// Count clock ticks
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if (action_on_new_start != `OVL_IGNORE_NEW_START)
begin
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if ((r_start_event == 1'b0) && (start_event == 1'b1)) begin
if ((min_cks != 0) && (test_expr==1'b1) &&
(action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
// FAIL, test_expr should not happen before min_cks
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is TRUE before elapse of specified minimum min_cks cycles from start event");
r_state <= FRAME_START;
end
// start_event (0->1) happens again -- re-started!!!
else if (action_on_new_start == `OVL_IGNORE_NEW_START) begin
if (max_cks) ii <= ii + 1;
else if (ii < min_cks) ii <= ii + 1;
end
else if (action_on_new_start == `OVL_RESET_ON_NEW_START)
ii <= 1;
else if (action_on_new_start == `OVL_ERROR_ON_NEW_START) begin
ovl_error_t(`OVL_FIRE_2STATE,"Illegal start event which has reoccured before completion of current window");
if (max_cks) ii <= ii + 1;
else if (ii < min_cks) ii <= ii + 1;
end
end
else begin
if (max_cks) ii <= ii + 1;
else if (ii < min_cks) ii <= ii + 1;
end
// Check for (0,0), (0,M), (m,0), (m,M) conditions
if (min_cks == 0) begin
if (max_cks == 0) begin
// (0,0): (min_cks==0, max_cks==0)
// This condition is UN-REACHABLE!!!
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not TRUE while start event is asserted when both parameters min_cks and max_cks are set to 0");
r_state <= FRAME_START;
end
else begin // max_cks > 0
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
// (0,M): (min_cks==0, max_cks>0)
if (test_expr == 1'b1) begin
// OK, ckeck is done. Go to FRAME_START state for next check.
r_state <= FRAME_START;
end
else begin
if (ii == max_cks &&
!(r_start_event == 1'b0 && start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)
) begin
// FAIL, test_expr does not happen at/before max_cks
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not TRUE within specified maximum max_cks cycles from start event");
r_state <= FRAME_START;
end
end
end
end
else begin // min_cks > 0
if (max_cks == 0) begin
// (m,0): (min_cks>0, max_cks==0)
if (ii == min_cks) begin
// OK, test_expr does not happen before min_cks
r_state <= FRAME_START;
end
else begin
if ((test_expr == 1'b1) &&
!(r_start_event == 1'b0 && start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)
) begin
// FAIL, test_expr should not happen before min_cks
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is TRUE before elapse of specified minimum min_cks cycles from start event");
r_state <= FRAME_START;
end
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end
end
else begin // max_cks > 0
// (m,M): (min_cks>0, max_cks>0)
if (test_expr == 1'b1) begin
r_state <= FRAME_START;
if (ii < min_cks &&
!(r_start_event == 1'b0 && start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)
) begin
// FAIL, test_expr should not happen before min_cks
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is TRUE before elapse of specified minimum min_cks cycles from start event");
end
// else OK, we are done!!!
end
else begin
if (ii == max_cks &&
!(r_start_event == 1'b0 && start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)
) begin
// FAIL, test_expr does not happen at/before max_cks
ovl_error_t(`OVL_FIRE_2STATE,"Test expression is not TRUE within specified maximum max_cks cycles from start event");
r_state <= FRAME_START;
end
end
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
// Do the x/z checking
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end
end
end
endcase
end
else begin
r_state <= FRAME_START;
ii <= 0;
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_COVER_ON
reg prev_start_event;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
if ((start_event != prev_start_event) && (prev_start_event == 1'b0)) begin
ovl_cover_t("start_event covered");
end
prev_start_event <= start_event;
end //basic coverage
end // OVL_COVER_NONE
end
else begin
prev_start_event <= 1'b0;
end
end //always
`endif // OVL_COVER_ON
|
#include <bits/stdc++.h> using namespace std; int main() { int n; long long l; cin >> n >> l; long long *lanterns = new long long[n]; for (long long i = 0; i < n; i++) cin >> lanterns[i]; double maxDistance = 0; sort(lanterns, lanterns + n); for (long long i = 0; i < n - 1; i++) if (lanterns[i + 1] - lanterns[i] > maxDistance) maxDistance = lanterns[i + 1] - lanterns[i]; if (maxDistance < lanterns[0] * 2) maxDistance = lanterns[0] * 2; if (maxDistance < (l - lanterns[n - 1]) * 2) maxDistance = (l - lanterns[n - 1]) * 2; cout << fixed; cout << maxDistance / 2; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; int trie[5000005][2]; int n, cnt; inline int read() { int t = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { ch = getchar(); } while (ch >= 0 && ch <= 9 ) { t = (t << 3) + (t << 1) + (ch ^ 48); ch = getchar(); } return t; } inline void write(int t) { if (t > 9) { write(t / 10); } putchar(t % 10 + 0 ); } inline void insert(int t) { int pos = 0; for (int i = 29; i >= 0; i--) { int x = (t >> i) & 1; if (!trie[pos][x]) { trie[pos][x] = ++cnt; } pos = trie[pos][x]; } } inline int solve(int t, int cur) { if (t == -1) { return 0; } if (!trie[cur][0]) { return solve(t - 1, trie[cur][1]); } else if (!trie[cur][1]) { return solve(t - 1, trie[cur][0]); } else { return (1 << t) + min(solve(t - 1, trie[cur][0]), solve(t - 1, trie[cur][1])); } } int main() { n = read(); while (n--) { insert(read()); } write(solve(29, 0)); putchar(10); return 0; } |
/////////////////////////////////////////////////////////////////////
//// ////
//// FFT/IFFT 256 points transform ////
//// ////
//// Authors: Anatoliy Sergienko, Volodya Lepeha ////
//// Company: Unicore Systems http://unicore.co.ua ////
//// ////
//// Downloaded from: http://www.opencores.org ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006-2010 Unicore Systems LTD ////
//// www.unicore.co.ua ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED "AS IS" ////
//// AND ANY EXPRESSED OR IMPLIED WARRANTIES, ////
//// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ////
//// WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT ////
//// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ////
//// IN NO EVENT SHALL THE UNICORE SYSTEMS OR ITS ////
//// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ////
//// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT ////
//// OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ////
//// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) ////
//// HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ////
//// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING ////
//// IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, ////
//// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DESCRIPTION : 1-port synchronous RAM
// FUNCTION: 1-port synchronous RAM
// FILES: RAM256.v -single ported synchronous RAM
// PROPERTIES: 1) Has the volume of 256 data
// 2) RAM is synchronous one, the read datum is outputted in 2 cycles after the address setting
// 3) Can be substituted to any 2-port synchronous RAM
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
`timescale 1 ns / 1 ps
`include "FFT256_CONFIG.inc"
module RAM256 ( CLK, ED,WE ,ADDR ,DI ,DO );
`FFT256paramnb
output [nb-1:0] DO ;
reg [nb-1:0] DO ;
input CLK ;
wire CLK ;
input ED;
input WE ;
wire WE ;
input [7:0] ADDR ;
wire [7:0] ADDR ;
input [nb-1:0] DI ;
wire [nb-1:0] DI ;
reg [nb-1:0] mem [255:0];
reg [7:0] addrrd;
always @(posedge CLK) begin
if (ED) begin
if (WE) mem[ADDR] <= DI;
addrrd <= ADDR; //storing the address
DO <= mem[addrrd]; // registering the read datum
end
end
endmodule
|
#include <bits/stdc++.h> const double eps = 1e-7, PI = 3.1415926; const int N = 2e5 + 10; using namespace std; int n, q, m, k, x, y, a[N], mx = -1, mn = 1e9, sum, t; char c[N]; string s, s1, s2; map<pair<int, char>, int> mp; vector<int> vec; int main() { cin >> q; while (q--) { cin >> n; cin >> s1 >> s2; y = 0; mp.clear(); sum = 0; for (int i = 0; i < 20; i++) { char v = a + i; mn = 1e9; int hg = 20; while (hg--) { mn = 1e9; for (int j = 0; j < n; j++) { if (s1[j] == v && s2[j] != s1[j]) { mn = min(mn, s2[j] - s1[j]); } } for (int j = 0; j < n; j++) { if (s1[j] == v && s2[j] != s1[j]) { s1[j] += mn; } } if (mn < 0) y = 1; if (mn == 1e9) break; else sum++; } } if (!y) cout << sum << endl; else cout << -1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int col[501]; int tcol[501]; int edge[501][501]; void docol(int v, int c) { col[v] = c; for (int i = 1; i <= v; ++i) { if (edge[v][i] && col[i] == -1) { docol(i, c); } } } int main(void) { ios_base::sync_with_stdio(false); int n; cin >> n; int k; cin >> k; memset(tcol, -1, sizeof(tcol)); memset(col, -1, sizeof(col)); memset(edge, 0, sizeof(edge)); for (int i = 1; i <= k; ++i) { int a, b; cin >> a >> b; edge[a][b] = 1; edge[b][a] = 1; } int b = 0; for (int i = 1; i <= n; ++i) { bool flag = true; for (int j = 1; j <= n; ++j) { if (i == j) continue; if (edge[i][j] == 0) { flag = false; break; } } if (flag) { tcol[i] = 1; b++; } } if (b == n) { cout << Yes n ; for (int i = 1; i <= n; ++i) cout << b ; return 0; } for (int i = 1; i <= n; ++i) { if (tcol[i] != -1) continue; memset(col, -1, sizeof(col)); for (int j = 1; j <= n; ++j) col[j] = tcol[j]; docol(i, 0); for (int j = 1; j <= n; ++j) { if (col[j] == -1) col[j] = 2; } bool flag = false; for (int ii = 1; ii <= n && !flag; ++ii) { for (int j = 1; j <= n && !flag; ++j) { if (ii == j) continue; if (edge[ii][j] == 0) { if ((col[ii] == 0 && col[j] == 2) || (col[ii] == 2 && col[j] == 0)) continue; else { flag = true; break; } } if (col[ii] == 1 || col[j] == 1) continue; if (col[ii] == 0 && (col[j] == 0 || col[j] == 1)) continue; if (col[ii] == 2 && (col[j] == 2 || col[j] == 1)) continue; flag = true; break; } } if (flag) continue; cout << Yes n ; for (int ii = 1; ii <= n; ++ii) cout << (col[ii] == 0 ? a : col[ii] == 1 ? b : c ); return 0; } cout << No ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 1100100; long long N, l, r; long long L[MAX], R[MAX], d, sol; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> N; for (int I = 0; I < N; I++) { cin >> L[I] >> R[I]; l += L[I]; r += R[I]; } d = abs(l - r); for (int I = 0; I < N; I++) { l += +R[I] - L[I]; r += -R[I] + L[I]; if (abs(l - r) > d) { d = abs(l - r); sol = I + 1; } l -= +R[I] - L[I]; r -= -R[I] + L[I]; } cout << sol << endl; } |
#include <bits/stdc++.h> using namespace std; int n, m, p, q, c, x, y, mod, lo[100000], z[3005][3005]; long long ans; struct segment_tree { int a[3005][13]; void update(int x, int y) { a[x][0] = y; } void build(int n) { for (int i = 1; i <= lo[n]; i++) for (int j = 1; j + (1 << i) - 1 <= n; j++) a[j][i] = min(a[j][i - 1], a[j + (1 << (i - 1))][i - 1]); } long long find(int x, int y) { int len = lo[y - x + 1]; return min(a[x][len], a[y - (1 << len) + 1][len]); } } a; int main() { scanf( %d%d%d%d , &n, &m, &p, &q); scanf( %d%d%d%d , &c, &x, &y, &mod); a.update(1, c); for (int i = 2; i <= 10000; i++) lo[i] = lo[i >> 1] + 1; for (int i = 2; i <= m; i++) c = (1ll * c * x + y) % mod, a.update(i, c); a.build(m); for (int i = 1; i <= m - q + 1; i++) z[1][i] = a.find(i, i + q - 1); for (int i = 2; i <= n; i++) { for (int j = 1; j <= m; j++) c = (1ll * c * x + y) % mod, a.update(j, c); a.build(m); for (int j = 1; j <= m - q + 1; j++) z[i][j] = a.find(j, j + q - 1); } for (int i = 1; i <= m - q + 1; i++) { for (int j = 1; j <= n; j++) a.update(j, z[j][i]); a.build(n); for (int j = 1; j <= n - p + 1; j++) ans = ans + a.find(j, j + p - 1); } printf( %lld , ans); } |
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