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#include <bits/stdc++.h> using namespace std; using Int = long long; template <class T1, class T2> ostream &operator<<(ostream &os, const pair<T1, T2> &a) { return os << ( << a.first << , << a.second << ) ; }; template <class T> void pv(T a, T b) { for (T i = a; i != b; ++i) cerr << *i << ; cerr << endl; } template <class T> bool chmin(T &t, const T &f) { if (t > f) { t = f; return true; } return false; } template <class T> bool chmax(T &t, const T &f) { if (t < f) { t = f; return true; } return false; } constexpr int MAX_N = 1010; constexpr int MAX_K = 1010; constexpr int MUL[4][4] = { {0, 0, 0, 0}, {0, 1, 2, 3}, {0, 2, 3, 1}, {0, 3, 1, 2}, }; int N, K; char typ[MAX_K][10], mix[MAX_K][10]; int M[MAX_K], J[MAX_K][MAX_N]; int fs[MAX_N], gs[MAX_N]; int aLen; vector<bitset<2 * MAX_N>> a; int main() { for (; ~scanf( %d%d , &N, &K);) { for (int k = 0; k < K; ++k) { scanf( %s%d , typ[k], &M[k]); for (int m = 0; m < M[k]; ++m) { scanf( %d , &J[k][m]); --J[k][m]; } if (!strcmp(typ[k], mix )) { scanf( %s , mix[k]); } } fill(fs, fs + N, 1); fill(gs, gs + N, 0); aLen = 0; a.assign(2 * K, bitset<2 * MAX_N>()); for (int k = 0; k < K; ++k) { if (!strcmp(typ[k], mix )) { const int num = string( WRYB ).find(mix[k]); for (int m = 0; m < M[k]; ++m) { const int i = J[k][m]; switch (gs[i]) { case 0: { const int p = (fs[i] >> 0) & 1; const int q = (fs[i] >> 1) & 1; a[aLen + 0][i << 1 | 0] = p; a[aLen + 0][i << 1 | 1] = q; a[aLen + 1][i << 1 | 0] = q; a[aLen + 1][i << 1 | 1] = p ^ q; } break; case 1: { const int p = (fs[i] >> 0) & 1; const int q = (fs[i] >> 1) & 1; a[aLen + 0][i << 1 | 0] = p; a[aLen + 0][i << 1 | 1] = p ^ q; a[aLen + 1][i << 1 | 0] = q; a[aLen + 1][i << 1 | 1] = p; } break; default: assert(false); } } a[aLen + 0][N << 1] = (num >> 0) & 1; a[aLen + 1][N << 1] = (num >> 1) & 1; aLen += 2; } else if (!strcmp(typ[k], RY )) { for (int m = 0; m < M[k]; ++m) { const int i = J[k][m]; fs[i] = MUL[2][MUL[fs[i]][fs[i]]]; gs[i] ^= 1; } } else if (!strcmp(typ[k], RB )) { for (int m = 0; m < M[k]; ++m) { const int i = J[k][m]; fs[i] = MUL[3][MUL[fs[i]][fs[i]]]; gs[i] ^= 1; } } else if (!strcmp(typ[k], YB )) { for (int m = 0; m < M[k]; ++m) { const int i = J[k][m]; fs[i] = MUL[1][MUL[fs[i]][fs[i]]]; gs[i] ^= 1; } } else { assert(false); } } a.resize(aLen); int r = 0; vector<int> hs; for (int h = 0; h < N << 1; ++h) { for (int i = r; i < aLen; ++i) { if (a[i][h]) { swap(a[r], a[i]); break; } } if (a[r][h]) { for (int i = r + 1; i < aLen; ++i) { if (a[i][h]) { a[i] ^= a[r]; } } ++r; hs.push_back(h); } } bool ok = true; for (int i = r; i < aLen; ++i) { ok = ok && !a[i][N << 1]; } if (ok) { bitset<2 * MAX_N> sol; for (int i = r; i--;) { sol[hs[i]] = (int)a[i][N << 1] ^ ((a[i] & sol).count() & 1); } puts( YES ); for (int i = 0; i < N; ++i) { putchar( .RYB [(int)sol[i << 1 | 0] << 0 | (int)sol[i << 1 | 1] << 1]); } puts( ); } else { puts( NO ); } } return 0; } |
#include <bits/stdc++.h> long long read() { long long x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } using namespace std; const long long maxn = 1e5 + 7; const double eps = 1e-10; const long long mod = 1e9 + 7; long long n; long long totA = 0, totB = 0; long long casA[maxn * 2], casB[maxn * 2]; long long tot = 0; struct Node { long long set, score; }; Node node[maxn]; bool cmp(Node a, Node b) { if (a.set < b.set) return 1; if (a.set == b.set && a.score < b.score) return 1; return 0; } int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (long long i = 1; i < 2 * maxn; i++) casA[i] = casB[i] = 9223372036854775807; bool flagA = 0, flagB = 0; for (long long i = 1; i <= n; i++) { long long x; cin >> x; if (x == 1) casA[++totA] = i; else casB[++totB] = i; if (i == n) { if (x == 1) flagA = 1; else flagB = 1; } } for (long long i = n; i >= 1; i--) { long long winA = 0, winB = 0, tarA = 0, tarB = 0; long long now = 1; bool flag = 1; while (now <= n) { if (casA[tarA + i] == 9223372036854775807 && casB[tarB + i] == 9223372036854775807) { flag = 0; break; } if (casA[tarA + i] < casB[tarB + i]) { winA++; tarA += i; tarB = casA[tarA] - tarA; now = casA[tarA] + 1; } else { winB++; tarB += i; tarA = casB[tarB] - tarB; now = casB[tarB] + 1; } } if (winA == winB) flag = 0; if (winA > winB && flagB) flag = 0; if (winA < winB && flagA) flag = 0; if (flag) { node[++tot].set = max(winA, winB); node[tot].score = i; } } sort(node, node + tot, cmp); cout << tot << n ; if (tot) { for (long long i = 1; i <= tot; i++) cout << node[i].set << << node[i].score << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLCLKP_1_V
`define SKY130_FD_SC_HS__DLCLKP_1_V
/**
* dlclkp: Clock gate.
*
* Verilog wrapper for dlclkp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlclkp_1 (
GCLK,
GATE,
CLK ,
VPWR,
VGND
);
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
sky130_fd_sc_hs__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlclkp_1 (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLCLKP_1_V
|
#include <bits/stdc++.h> using namespace std; void debug(int* a, int n, bool flag = false) { if (!flag) printf( array ); for (int i = 1; i <= n; i++) printf( %d , a[i]); printf( n ); } void debug(vector<int>& E, bool flag = false) { if (!flag) printf( vector ); for (auto it : E) printf( %d , it); printf( n ); } const int maxn = 2e5 + 5; int a[maxn]; set<pair<int, int> > s; int n, m; map<int, bool> Map; vector<int> res; int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); Map[a[i]] = true; s.insert(make_pair(i, -1)); s.insert(make_pair(i, 1)); } sort(a + 1, a + 1 + n); long long ans = 0; long long k = 1; while (m) { auto it = s.begin(); while (it != s.end()) { long long val = a[it->first] + k * it->second; if (!Map.count(val)) { res.push_back(val); ans += k; it++; m--; Map[val] = true; if (!m) break; } else s.erase(it++); } k++; } printf( %I64d n , ans); debug(res, true); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31OI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A31OI_FUNCTIONAL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a31oi (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31OI_FUNCTIONAL_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:25:26 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_0_stub.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_bram_ctrl,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid,
s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arlen,
s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, bram_rst_a,
bram_clk_a, bram_en_a, bram_we_a, bram_addr_a, bram_wrdata_a, bram_rddata_a, bram_rst_b,
bram_clk_b, bram_en_b, bram_we_b, bram_addr_b, bram_wrdata_b, bram_rddata_b)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[15:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[15:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[15:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[15:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [15:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [15:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [15:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [15:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
endmodule
|
#include <bits/stdc++.h> using namespace std; int dx[4] = {1, 0, -1, 0}; int dy[4] = {0, 1, 0, -1}; int ddx[8] = {-1, -1, 0, 1, 1, 1, 0, -1}; int ddy[8] = {0, 1, 1, 1, 0, -1, -1, -1}; bool debug = false; int main() { int n, L, a; cin >> n >> L >> a; int ans = 0, now = 0; for (int i = 0; i < n; i++) { int t, l; cin >> t >> l; ans += (t - now) / a; now = t + l; } ans += (L - now) / a; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int x, y, next; } a[1010000]; int len, last[510000]; inline void ins(int x, int y) { len++; a[len].x = x; a[len].y = y; a[len].next = last[x]; last[x] = len; } int tt[510000]; int col[510000]; int cnt, belong[510000]; bool dfs(int x, int c) { if (col[x] != -1) return col[x] == c; col[x] = c; belong[x] = cnt; for (int k = last[x]; k > 0; k = a[k].next) { int y = a[k].y; if (tt[x] != tt[y]) continue; if (!dfs(y, 1 - c)) return false; } return true; } bool b[510000]; int tg[510000]; struct edge { int x, y, c, next; bool bk; } e[1010000]; map<int, map<int, int>> east; inline void ins(int x, int y, int c) { len++; e[len].x = x; e[len].y = y; e[len].c = c; e[len].next = east[x][tg[y]]; east[x][tg[y]] = len; e[len].bk = true; } int Al, Be, Ga; bool De; void color(int x, int c) { if (col[x] < Ga) { col[x] = c; int ty = tg[x] == Al ? Be : Al; for (int k = east[x][ty]; k > 0; k = e[k].next) { int y = e[k].y; e[k].bk = false; color(y, c ^ e[k].c); } } else if (col[x] == (c ^ 1)) De = false; } set<pair<int, int>> S; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) scanf( %d , &tt[i]); len = 0; memset(last, 0, sizeof(last)); for (int i = 1; i <= m; i++) { int x, y; scanf( %d%d , &x, &y); ins(x, y); ins(y, x); } memset(col, -1, sizeof(col)); memset(b, true, sizeof(b)); cnt = 0; for (int i = 1; i <= n; i++) { if (col[i] == -1 && b[tt[i]]) { cnt++; if (!dfs(i, 0)) { k--; b[tt[i]] = false; } } } for (int i = 1; i <= n; i++) tg[belong[i]] = tt[i]; len = 0; for (int i = 1; i <= m; i++) { int x = a[i * 2].x, y = a[i * 2].y; if (b[tt[x]] && b[tt[y]] && tt[x] != tt[y]) { ins(belong[x], belong[y], col[x] ^ col[y]); ins(belong[y], belong[x], col[x] ^ col[y]); } } memset(col, -1, sizeof(col)); Ga = 0; for (int i = 1; i <= len; i += 2) { int x = e[i].x, y = e[i].y; if (tg[x] > tg[y]) x ^= y ^= x ^= y; if (e[i].bk) { Al = tg[x]; Be = tg[y]; De = true; color(x, Ga); if (!De) S.insert({tg[x], tg[y]}); Ga += 2; } } printf( %lld n , 1ll * k * (k - 1) / 2 - S.size()); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, pay = 0, kd; int U = 0, R = 0; char c; cin >> n; cin >> c; if (c == U ) { kd = 1; U++; } else { kd = 0; R++; } for (int i = 1; i < n; i++) { cin >> c; if (c == U ) U++; else if (c == R ) R++; if (kd == 0 && R < U) { pay++; kd = 1; } else if (kd && R > U) { pay++; kd = 0; } } cout << pay; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_4_V
`define SKY130_FD_SC_HD__A31OI_4_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a31oi_4 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_4_V
|
#include <bits/stdc++.h> using namespace std; struct data { int idx, val; bool operator<(const data &a1) const { if (a1.val == val) { return a1.idx < idx; } return val > a1.val; } data(int t, int w) : idx(t), val(w) {} }; set<data> coastline; set<data>::iterator it, it2; int main() { int N; scanf( %d , &N); string ans[N]; int a; for (int i = 0; i < N; i++) { scanf( %d , &a); if (a == 0) { int sz = coastline.size(); if (sz == 0) { ans[i] = 0 ; } else if (sz == 1) { ans[i] = 1 popStack ; it = coastline.begin(); ans[it->idx] = pushStack ; } else if (sz == 2) { ans[i] = 2 popStack popQueue ; it = coastline.begin(); ans[it->idx] = pushQueue ; it++; ans[it->idx] = pushStack ; it++; } else { ans[i] = 3 popStack popQueue popFront ; it = coastline.begin(); ans[it->idx] = pushFront ; it++; ans[it->idx] = pushQueue ; it++; ans[it->idx] = pushStack ; it++; } coastline.clear(); } else { coastline.insert(data(i, a)); } } for (int i = 0; i < N; i++) { if (ans[i].size() == 0) { cout << pushBack << endl; } else cout << ans[i] << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111AI_SYMBOL_V
`define SKY130_FD_SC_MS__O2111AI_SYMBOL_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o2111ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111AI_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int* m = new int[n]; int* r = new int[n]; for (int i = 0; i < n; i++) { cin >> m[i]; } for (int i = 0; i < n; i++) { cin >> r[i]; } double total = 0; for (int i = 0; i < 1000000; i++) { for (int j = 0; j < n; j++) { if (i % m[j] == r[j]) { total++; break; } } } double percentage = total / 1000000; cout << fixed << setprecision(6) << percentage << endl; } |
//----------------------------------------------------------------------------
// TFT INTERFACE - Sub Level Module
//-----------------------------------------------------------------------------
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
//----------------------------------------------------------------------------
// Filename: tft_if.v
//
// Description:
// This module takes as input, the TFT input signals and registers them.
// Therefore all signals going to the TFT hardware is registered in the
// IOBs.
//
// Design Notes:
// Wrapper type file to register all the inputs to the TFT hardware.
//
//-----------------------------------------------------------------------------
// Structure:
// -- tft_if.v
//-----------------------------------------------------------------------------
// Author: CJN
// History:
// CJN, MM 3/02 -- First Release
// CJN -- Second Release
//
//
//
//-----------------------------------------------------------------------------
///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 100 ps
module tft_if(
clk, // I
rst, // I
HSYNC, // I
VSYNC, // I
DE, // I
R0, // I
R1, // I
R2, // I
R3, // I
R4, // I
R5, // I
G0, // I
G1, // I
G2, // I
G3, // I
G4, // I
G5, // I
B0, // I
B1, // I
B2, // I
B3, // I
B4, // I
B5, // I
TFT_LCD_HSYNC, // O
TFT_LCD_VSYNC, // O
TFT_LCD_DE, // O
TFT_LCD_CLK, // O
TFT_LCD_R0, // O
TFT_LCD_R1, // O
TFT_LCD_R2, // O
TFT_LCD_R3, // O
TFT_LCD_R4, // O
TFT_LCD_R5, // O
TFT_LCD_G0, // O
TFT_LCD_G1, // O
TFT_LCD_G2, // O
TFT_LCD_G3, // O
TFT_LCD_G4, // O
TFT_LCD_G5, // O
TFT_LCD_B0, // O
TFT_LCD_B1, // O
TFT_LCD_B2, // O
TFT_LCD_B3, // O
TFT_LCD_B4, // O
TFT_LCD_B5 // O
);
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input clk;
input rst;
input HSYNC;
input VSYNC;
input DE;
input R0;
input R1;
input R2;
input R3;
input R4;
input R5;
input G0;
input G1;
input G2;
input G3;
input G4;
input G5;
input B0;
input B1;
input B2;
input B3;
input B4;
input B5;
output TFT_LCD_HSYNC;
output TFT_LCD_VSYNC;
output TFT_LCD_DE;
output TFT_LCD_CLK;
output TFT_LCD_R0;
output TFT_LCD_R1;
output TFT_LCD_R2;
output TFT_LCD_R3;
output TFT_LCD_R4;
output TFT_LCD_R5;
output TFT_LCD_G0;
output TFT_LCD_G1;
output TFT_LCD_G2;
output TFT_LCD_G3;
output TFT_LCD_G4;
output TFT_LCD_G5;
output TFT_LCD_B0;
output TFT_LCD_B1;
output TFT_LCD_B2;
output TFT_LCD_B3;
output TFT_LCD_B4;
output TFT_LCD_B5;
///////////////////////////////////////////////////////////////////////////////
// Signal Declaration
///////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// FDRE COMPONENT INSTANTIATION FOR IOB OUTPUT REGISTERS
// -- All output to TFT/tft are registered
////////////////////////////////////////////////////////////////////////////
FDRE FDRE_HSYNC (.Q(TFT_LCD_HSYNC), .C(clk), .CE(1'b1), .R(rst), .D(HSYNC)) /* synthesis syn_useioff = 1 */;
FDRE FDRE_VSYNC (.Q(TFT_LCD_VSYNC), .C(clk), .CE(1'b1), .R(rst), .D(VSYNC)) /* synthesis syn_useioff = 1 */;
FDRE FDRE_DE (.Q(TFT_LCD_DE), .C(clk), .CE(1'b1), .R(rst), .D(DE)) /* synthesis syn_useioff = 1 */;
assign TFT_LCD_CLK = clk;
// ODDR TFT_CLK_ODDR (.Q(TFT_LCD_CLK), .C(clk), .CE(1'b1), .R(1'b0), .D1(1'b0), .D2(1'b1), .S(1'b0));
FD FD_R0 (.Q(TFT_LCD_R0), .C(clk), .D(R0)) /* synthesis syn_useioff = 1 */;
FD FD_R1 (.Q(TFT_LCD_R1), .C(clk), .D(R1)) /* synthesis syn_useioff = 1 */;
FD FD_R2 (.Q(TFT_LCD_R2), .C(clk), .D(R2)) /* synthesis syn_useioff = 1 */;
FD FD_R3 (.Q(TFT_LCD_R3), .C(clk), .D(R3)) /* synthesis syn_useioff = 1 */;
FD FD_R4 (.Q(TFT_LCD_R4), .C(clk), .D(R4)) /* synthesis syn_useioff = 1 */;
FD FD_R5 (.Q(TFT_LCD_R5), .C(clk), .D(R5)) /* synthesis syn_useioff = 1 */;
FD FD_G0 (.Q(TFT_LCD_G0), .C(clk), .D(G0)) /* synthesis syn_useioff = 1 */;
FD FD_G1 (.Q(TFT_LCD_G1), .C(clk), .D(G1)) /* synthesis syn_useioff = 1 */;
FD FD_G2 (.Q(TFT_LCD_G2), .C(clk), .D(G2)) /* synthesis syn_useioff = 1 */;
FD FD_G3 (.Q(TFT_LCD_G3), .C(clk), .D(G3)) /* synthesis syn_useioff = 1 */;
FD FD_G4 (.Q(TFT_LCD_G4), .C(clk), .D(G4)) /* synthesis syn_useioff = 1 */;
FD FD_G5 (.Q(TFT_LCD_G5), .C(clk), .D(G5)) /* synthesis syn_useioff = 1 */;
FD FD_B0 (.Q(TFT_LCD_B0), .C(clk), .D(B0)) /* synthesis syn_useioff = 1 */;
FD FD_B1 (.Q(TFT_LCD_B1), .C(clk), .D(B1)) /* synthesis syn_useioff = 1 */;
FD FD_B2 (.Q(TFT_LCD_B2), .C(clk), .D(B2)) /* synthesis syn_useioff = 1 */;
FD FD_B3 (.Q(TFT_LCD_B3), .C(clk), .D(B3)) /* synthesis syn_useioff = 1 */;
FD FD_B4 (.Q(TFT_LCD_B4), .C(clk), .D(B4)) /* synthesis syn_useioff = 1 */;
FD FD_B5 (.Q(TFT_LCD_B5), .C(clk), .D(B5)) /* synthesis syn_useioff = 1 */;
endmodule
|
#include <bits/stdc++.h> int main(void) { int n, sum = 0; scanf( %d , &n); getchar(); char str[n]; gets(str); for (int i = 0; i < n; i++) { if (str[i] == + ) sum++; else if (str[i] == - && sum != 0) sum--; } printf( %d n , sum); return 0; } |
/*****************************************************************************
* *
* Module: Altera_UP_PS2_Data_In *
* Description: *
* This module accepts incoming data from a PS2 core. *
* *
*****************************************************************************/
module Altera_UP_PS2_Data_In (
// Inputs
clk,
reset,
wait_for_incoming_data,
start_receiving_data,
ps2_clk_posedge,
ps2_clk_negedge,
ps2_data,
// Bidirectionals
// Outputs
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input wait_for_incoming_data;
input start_receiving_data;
input ps2_clk_posedge;
input ps2_clk_negedge;
input ps2_data;
// Bidirectionals
// Outputs
output reg [7:0] received_data;
output reg received_data_en;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_WAIT_FOR_DATA = 3'h1,
PS2_STATE_2_DATA_IN = 3'h2,
PS2_STATE_3_PARITY_IN = 3'h3,
PS2_STATE_4_STOP_IN = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
reg [3:0] data_count;
reg [7:0] data_shift_reg;
// State Machine Registers
reg [2:0] ns_ps2_receiver;
reg [2:0] s_ps2_receiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_ps2_receiver <= PS2_STATE_0_IDLE;
else
s_ps2_receiver <= ns_ps2_receiver;
end
always @(*)
begin
// Defaults
ns_ps2_receiver = PS2_STATE_0_IDLE;
case (s_ps2_receiver)
PS2_STATE_0_IDLE:
begin
if ((wait_for_incoming_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
else if ((start_receiving_data == 1'b1) &&
(received_data_en == 1'b0))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_WAIT_FOR_DATA:
begin
if ((ps2_data == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
else if (wait_for_incoming_data == 1'b0)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_1_WAIT_FOR_DATA;
end
PS2_STATE_2_DATA_IN:
begin
if ((data_count == 3'h7) && (ps2_clk_posedge == 1'b1))
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
else
ns_ps2_receiver = PS2_STATE_2_DATA_IN;
end
PS2_STATE_3_PARITY_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
else
ns_ps2_receiver = PS2_STATE_3_PARITY_IN;
end
PS2_STATE_4_STOP_IN:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_receiver = PS2_STATE_0_IDLE;
else
ns_ps2_receiver = PS2_STATE_4_STOP_IN;
end
default:
begin
ns_ps2_receiver = PS2_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
data_count <= 3'h0;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_count <= data_count + 3'h1;
else if (s_ps2_receiver != PS2_STATE_2_DATA_IN)
data_count <= 3'h0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
data_shift_reg <= 8'h00;
else if ((s_ps2_receiver == PS2_STATE_2_DATA_IN) &&
(ps2_clk_posedge == 1'b1))
data_shift_reg <= {ps2_data, data_shift_reg[7:1]};
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data <= 8'h00;
else if (s_ps2_receiver == PS2_STATE_4_STOP_IN)
received_data <= data_shift_reg;
end
always @(posedge clk)
begin
if (reset == 1'b1)
received_data_en <= 1'b0;
else if ((s_ps2_receiver == PS2_STATE_4_STOP_IN) &&
(ps2_clk_posedge == 1'b1))
received_data_en <= 1'b1;
else
received_data_en <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 0; char ch = getchar(); while (!isdigit(ch)) f |= ch == - , ch = getchar(); while (isdigit(ch)) x = (x << 1) + (x << 3) + (ch ^ 0 ), ch = getchar(); return f ? -x : x; } inline void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x > 9) write(x / 10); putchar(x % 10 + 48); } inline void writebl(long long x) { write(x); putchar( ); } inline void writeln(long long x) { write(x); putchar( n ); } const long long N = 4e6 + 5; long long ch[N][3], cnt = 1, val[N]; void ins(long long x) { long long u = 1; for (long long i = (30); i >= (0); --i) { long long v = (x >> i) & 1; if (!ch[u][v]) ch[u][v] = ++cnt; u = ch[u][v]; } } long long n, a[N]; long long dfs(long long u) { long long r1 = 0, r2 = 0; if (!ch[u][0] && !ch[u][1]) return 1; if (!ch[u][0]) return dfs(ch[u][1]); if (!ch[u][1]) return dfs(ch[u][0]); return max(dfs(ch[u][0]), dfs(ch[u][1])) + 1; } signed main() { n = read(); for (long long i = (1); i <= (n); ++i) a[i] = read(), ins(a[i]); writeln(n - dfs(1)); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__HA_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__HA_PP_BLACKBOX_V
/**
* ha: Half adder.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__HA_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; struct inf { long long v; long long b; }; bool cmp(struct inf a, struct inf c) { return a.b > c.b; } int main() { struct inf a[300005]; long long n, k, i, j, sum = 0, ans = -1, temp; cin >> n >> k; for (i = 0; i < n; i++) { cin >> a[i].v >> a[i].b; } sort(a, a + n, cmp); priority_queue<long long, vector<long long>, greater<long long>> q; for (i = 0; i < n; i++) { if (i < k) { sum += a[i].v; q.push(a[i].v); ans = max(ans, sum * a[i].b); } else { temp = q.top(); if (temp < a[i].v) { sum -= temp; q.pop(); q.push(a[i].v); sum += a[i].v; ans = max(ans, sum * a[i].b); } } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, t; cin >> n >> t; if (n == 1 && t == 10) cout << -1 << endl; else { cout << t; if (t == 10) n--; for (int i = 0; i < n - 1; i++) cout << 0; cout << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_2_V
`define SKY130_FD_SC_HD__O21BAI_2_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21bai_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_2_V
|
#include <bits/stdc++.h> using namespace std; pair<int, int> tc[30]; bool dp[5][110][505]; int vis[5][110][505], n, k, Trow[30], kase, stx, sty; char mp[5][110]; bool solve(int x, int y, int mv) { if (x < 1 || x > 3 || y < 1) return 0; if (y > n) return 1; bool oc1 = 0, oc2 = 0, oc3 = 0; if (vis[x][y][mv] == kase) return dp[x][y][mv]; for (int i = 1; i <= k; i++) { if (x == Trow[i]) { if (y >= (tc[i].first - mv * 2) && y <= (tc[i].second - mv * 2)) return 0; if (y + 1 >= (tc[i].first - mv * 2) && y + 1 <= (tc[i].second - mv * 2)) oc1 = 1; } else if (x - Trow[i] == 1) { if (y + 1 >= (tc[i].first - mv * 2) && y + 1 <= (tc[i].second - mv * 2)) oc2 = 1; } else if (Trow[i] - x == 1) { if (y + 1 >= (tc[i].first - mv * 2) && y + 1 <= (tc[i].second - mv * 2)) oc3 = 1; } } bool op1 = 0, op2 = 0, op3 = 0; if (!oc1) op1 = solve(x, y + 1, mv + 1); if (!oc1 && !oc2) op2 = solve(x - 1, y + 1, mv + 1); if (!oc1 && !oc3) op3 = solve(x + 1, y + 1, mv + 1); vis[x][y][mv] = kase; return dp[x][y][mv] = (op1 || op2 || op3); } int main() { int ks; scanf( %d , &ks); for (kase = 1; kase <= ks; kase++) { scanf( %d %d , &n, &k); for (int i = 1; i <= 3; i++) scanf( %s , &mp[i][1]); int cnt = 1; for (int i = 1; i <= 3; i++) { for (int j = 1; j <= n; j++) { if (mp[i][j] == s ) stx = i, sty = j; else if (mp[i][j] != . ) { char S = mp[i][j]; int kk = j; while (kk <= n && mp[i][kk] == S) mp[i][kk] = . , kk++; Trow[cnt] = i; tc[cnt].first = j; tc[cnt].second = kk - 1; cnt++; } } } printf( %s n , solve(stx, sty, 0) ? YES : NO ); } } |
#include <bits/stdc++.h> using namespace std; void solve() { long long n; cin >> n; vector<long long> v(n + 1); long long xr = 0; for (long long i = 1; i <= n; i++) { cin >> v[i]; xr ^= v[i]; } if (xr == 0) { cout << DRAW << n ; return; } long long msb; for (long long i = 32; ~i; i--) { if (xr & (1ll << i)) { msb = i; break; } } long long count = 0; for (long long i = 1; i <= n; i++) { count += ((v[i] & (1ll << msb)) > 0); } bool win = (count % 4 == 1 or ((n - count) & 1)); cout << (win ? WIN : LOSE ) << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; long long pow1(long long b, long long expo, long long md) { if (!expo) return 1; long long tmp = pow1(b, expo / 2, md); tmp = (tmp * tmp) % md; if (expo % 2) tmp = (tmp * b) % md; return tmp; } long long w[1000005] = {}; long long apow[1000005] = {}; long long inv[1000005] = {}; vector<long long> v[1000005] = {}; long long get(long long a, long long m1, long long b, long long m2, long long x) { long long ret = 0; long long first, k; k = (a - b) * inv[m2]; k %= m1; k += m1; k %= m1; first = k * m2 + b; first %= m1 * m2; x -= first; if (x >= 0) { ret += 1 + x / (m1 * m2); } return ret; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed << setprecision(15); long long md, a, b, x, per; long long ans = 0; cin >> a >> b >> md >> x; apow[0] = 1; v[1].push_back(0); if (a != 1) { apow[1] = a; v[a].push_back(1); for (long long f = (long long)2; f <= (long long)md; ++f) { apow[f] = a * apow[f - 1]; apow[f] %= md; if (apow[f] == 1) { per = f; break; } v[apow[f]].push_back(f); } } else { per = 1; } for (long long f = (long long)1; f <= (long long)md - 1; ++f) { inv[f] = pow1(f, md - 2, md); } for (long long f = (long long)1; f <= (long long)md - 1; ++f) { w[f] = (inv[f] * b) % md; } for (long long f = (long long)1; f <= (long long)md - 1; ++f) { if ((long)v[w[f]].size()) { for (long long ff = (long long)0; ff <= (long long)(long)v[w[f]].size() - 1; ++ff) { ans += get(f, md, v[w[f]][ff], per, x); } } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; vector<pair<pair<int, int>, int> > a(2 * n - 1); for (int i = 0; i < 2 * n - 1; i++) { cin >> a[i].first.first; cin >> a[i].first.second; a[i].second = i + 1; } sort(a.begin(), a.end()); long long s = 0, s1 = 0, tt = 0, tt1 = 0; for (int i = 0; i < 2 * n - 1; i++) { if (i % 2 == 0) { s += a[i].first.first; s1 += a[i].first.second; } tt += a[i].first.first; tt1 += a[i].first.second; } tt++; tt1++; tt /= 2; tt1 /= 2; cout << YES << endl; if (s >= tt && s1 >= tt1) { for (int i = 0; i < 2 * n - 1; i++) { if (i % 2 == 0) cout << a[i].second << ; } cout << endl; } else { for (int i = 0; i < 2 * n - 1; i++) { if (i % 2 == 1) { cout << a[i].second << ; } } cout << a[2 * n - 2].second << endl; } } return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_out.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// FPU result output.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_out (
d8stg_fdiv_in,
m6stg_fmul_in,
a6stg_fadd_in,
div_id_out_in,
m6stg_id_in,
add_id_out_in,
div_exc_out,
d8stg_fdivd,
d8stg_fdivs,
div_sign_out,
div_exp_out,
div_frac_out,
mul_exc_out,
m6stg_fmul_dbl_dst,
m6stg_fmuls,
mul_sign_out,
mul_exp_out,
mul_frac_out,
add_exc_out,
a6stg_fcmpop,
add_cc_out,
add_fcc_out,
a6stg_dbl_dst,
a6stg_sng_dst,
a6stg_long_dst,
a6stg_int_dst,
add_sign_out,
add_exp_out,
add_frac_out,
arst_l,
grst_l,
rclk,
fp_cpx_req_cq,
add_dest_rdy,
mul_dest_rdy,
div_dest_rdy,
fp_cpx_data_ca,
se,
si,
so
);
input d8stg_fdiv_in; // div pipe output request next cycle
input m6stg_fmul_in; // mul pipe output request next cycle
input a6stg_fadd_in; // add pipe output request next cycle
input [9:0] div_id_out_in; // div pipe output ID next cycle
input [9:0] m6stg_id_in; // mul pipe output ID next cycle
input [9:0] add_id_out_in; // add pipe output ID next cycle
input [4:0] div_exc_out; // divide pipe result- exception flags
input d8stg_fdivd; // divide double- divide stage 8
input d8stg_fdivs; // divide single- divide stage 8
input div_sign_out; // divide sign output
input [10:0] div_exp_out; // divide exponent output
input [51:0] div_frac_out; // divide fraction output
input [4:0] mul_exc_out; // multiply pipe result- exception flags
input m6stg_fmul_dbl_dst; // double precision multiply result
input m6stg_fmuls; // fmuls- multiply 6 stage
input mul_sign_out; // multiply sign output
input [10:0] mul_exp_out; // multiply exponent output
input [51:0] mul_frac_out; // multiply fraction output
input [4:0] add_exc_out; // add pipe result- exception flags
input a6stg_fcmpop; // compare- add 6 stage
input [1:0] add_cc_out; // add pipe result- condition
input [1:0] add_fcc_out; // add pipe input fcc passed through
input a6stg_dbl_dst; // float double result- add 6 stage
input a6stg_sng_dst; // float single result- add 6 stage
input a6stg_long_dst; // 64bit integer result- add 6 stage
input a6stg_int_dst; // 32bit integer result- add 6 stage
input add_sign_out; // add sign output
input [10:0] add_exp_out; // add exponent output
input [63:0] add_frac_out; // add fraction output
input arst_l; // global async. reset- asserted low
input grst_l; // global sync. reset- asserted low
input rclk; // global clock
output [7:0] fp_cpx_req_cq; // FPU result request to CPX
output add_dest_rdy; // add pipe result request this cycle
output mul_dest_rdy; // mul pipe result request this cycle
output div_dest_rdy; // div pipe result request this cycle
output [144:0] fp_cpx_data_ca; // FPU result to CPX
input se; // scan_enable
input si; // scan in
output so; // scan out
///////////////////////////////////////////////////////////////////////////////
//
// Outputs of fpu_out_ctl.
//
///////////////////////////////////////////////////////////////////////////////
wire [7:0] fp_cpx_req_cq; // FPU result request to CPX
wire [1:0] req_thread; // thread ID of result req this cycle
wire [2:0] dest_rdy; // pipe with result request this cycle
wire add_dest_rdy; // add pipe result request this cycle
wire mul_dest_rdy; // mul pipe result request this cycle
wire div_dest_rdy; // div pipe result request this cycle
///////////////////////////////////////////////////////////////////////////////
//
// Outputs of fpu_out_dp.
//
///////////////////////////////////////////////////////////////////////////////
wire [144:0] fp_cpx_data_ca; // FPU result to CPX
///////////////////////////////////////////////////////////////////////////////
//
// Instantiations.
//
///////////////////////////////////////////////////////////////////////////////
fpu_out_ctl fpu_out_ctl (
.d8stg_fdiv_in (d8stg_fdiv_in),
.m6stg_fmul_in (m6stg_fmul_in),
.a6stg_fadd_in (a6stg_fadd_in),
.div_id_out_in (div_id_out_in[9:0]),
.m6stg_id_in (m6stg_id_in[9:0]),
.add_id_out_in (add_id_out_in[9:0]),
.arst_l (arst_l),
.grst_l (grst_l),
.rclk (rclk),
.fp_cpx_req_cq (fp_cpx_req_cq[7:0]),
.req_thread (req_thread[1:0]),
.dest_rdy (dest_rdy[2:0]),
.add_dest_rdy (add_dest_rdy),
.mul_dest_rdy (mul_dest_rdy),
.div_dest_rdy (div_dest_rdy),
.se (se),
.si (si),
.so (scan_out_fpu_out_ctl)
);
fpu_out_dp fpu_out_dp (
.dest_rdy (dest_rdy[2:0]),
.req_thread (req_thread[1:0]),
.div_exc_out (div_exc_out[4:0]),
.d8stg_fdivd (d8stg_fdivd),
.d8stg_fdivs (d8stg_fdivs),
.div_sign_out (div_sign_out),
.div_exp_out (div_exp_out[10:0]),
.div_frac_out (div_frac_out[51:0]),
.mul_exc_out (mul_exc_out[4:0]),
.m6stg_fmul_dbl_dst (m6stg_fmul_dbl_dst),
.m6stg_fmuls (m6stg_fmuls),
.mul_sign_out (mul_sign_out),
.mul_exp_out (mul_exp_out[10:0]),
.mul_frac_out (mul_frac_out[51:0]),
.add_exc_out (add_exc_out[4:0]),
.a6stg_fcmpop (a6stg_fcmpop),
.add_cc_out (add_cc_out[1:0]),
.add_fcc_out (add_fcc_out[1:0]),
.a6stg_dbl_dst (a6stg_dbl_dst),
.a6stg_sng_dst (a6stg_sng_dst),
.a6stg_long_dst (a6stg_long_dst),
.a6stg_int_dst (a6stg_int_dst),
.add_sign_out (add_sign_out),
.add_exp_out (add_exp_out[10:0]),
.add_frac_out (add_frac_out[63:0]),
.rclk (rclk),
.fp_cpx_data_ca (fp_cpx_data_ca[144:0]),
.se (se),
.si (scan_out_fpu_out_ctl),
.so (so)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, a, b, ans[400]; string s[400]; long long calc(int pos, int res) { for (int i = res + 1; i <= 10; i++) { for (int j = 0; j < 1 << i; j++) { string t = ; for (int k = 0; k < i; k++) t = t + (char)(((j >> k) & 1) + 0 ); if (s[pos].find(t) == -1) { ans[pos] = i - 1; return i - 1; } } } } int main() { ios_base::sync_with_stdio(false); cin >> n; for (int i = 1; i <= n; i++) cin >> s[i]; cin >> m; for (int i = 1; i <= m; i++) { cin >> a >> b; s[n + i] = s[a] + s[b]; if (s[n + i].length() > 1000) s[n + i] = s[n + i].substr(0, 500) + s[n + i].substr(s[n + i].length() - 500, 500); cout << calc(n + i, max(ans[a], ans[b])) << endl; } return 0; } |
//---------------------------------------------------------------------------------------
// uart transmit module
//
//---------------------------------------------------------------------------------------
module uart_tx
(
clock, reset,
ce_16, tx_data, new_tx_data,
ser_out, tx_busy
);
//---------------------------------------------------------------------------------------
// modules inputs and outputs
input clock; // global clock input
input reset; // global reset input
input ce_16; // baud rate multiplyed by 16 - generated by baud module
input [7:0] tx_data; // data byte to transmit
input new_tx_data; // asserted to indicate that there is a new data byte for transmission
output ser_out; // serial data output
output tx_busy; // signs that transmitter is busy
// internal wires
wire ce_1; // clock enable at bit rate
// internal registers
reg ser_out;
reg tx_busy;
reg [3:0] count16;
reg [3:0] bit_count;
reg [8:0] data_buf;
//---------------------------------------------------------------------------------------
// module implementation
// a counter to count 16 pulses of ce_16 to generate the ce_1 pulse
always @ (posedge clock or posedge reset)
begin
if (reset)
count16 <= 4'b0;
else if (tx_busy & ce_16)
count16 <= count16 + 4'b1;
else if (~tx_busy)
count16 <= 4'b0;
end
// ce_1 pulse indicating output data bit should be updated
assign ce_1 = (count16 == 4'b1111) & ce_16;
// tx_busy flag
always @ (posedge clock or posedge reset)
begin
if (reset)
tx_busy <= 1'b0;
else if (~tx_busy & new_tx_data)
tx_busy <= 1'b1;
else if (tx_busy & (bit_count == 4'h9) & ce_1)
tx_busy <= 1'b0;
end
// output bit counter
always @ (posedge clock or posedge reset)
begin
if (reset)
bit_count <= 4'h0;
else if (tx_busy & ce_1)
bit_count <= bit_count + 4'h1;
else if (~tx_busy)
bit_count <= 4'h0;
end
// data shift register
always @ (posedge clock or posedge reset)
begin
if (reset)
data_buf <= 9'b0;
else if (~tx_busy)
data_buf <= {tx_data, 1'b0};
else if (tx_busy & ce_1)
data_buf <= {1'b1, data_buf[8:1]};
end
// output data bit
always @ (posedge clock or posedge reset)
begin
if (reset)
ser_out <= 1'b1;
else if (tx_busy)
ser_out <= data_buf[0];
else
ser_out <= 1'b1;
end
endmodule
//---------------------------------------------------------------------------------------
// Th.. Th.. Th.. Thats all folks !!!
//---------------------------------------------------------------------------------------
|
// hub_mem
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module hub_mem
(
input clk_cog,
input ena_bus,
input w,
input [3:0] wb,
input [13:0] a,
input [31:0] d,
output [31:0] q
);
// 8192 x 32 ram with byte-write enables ($0000..$7FFF)
reg [7:0] ram3 [8191:0];
reg [7:0] ram2 [8191:0];
reg [7:0] ram1 [8191:0];
reg [7:0] ram0 [8191:0];
reg [7:0] ram_q3;
reg [7:0] ram_q2;
reg [7:0] ram_q1;
reg [7:0] ram_q0;
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[3])
ram3[a[12:0]] <= d[31:24];
if (ena_bus && !a[13])
ram_q3 <= ram3[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[2])
ram2[a[12:0]] <= d[23:16];
if (ena_bus && !a[13])
ram_q2 <= ram2[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[1])
ram1[a[12:0]] <= d[15:8];
if (ena_bus && !a[13])
ram_q1 <= ram1[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[0])
ram0[a[12:0]] <= d[7:0];
if (ena_bus && !a[13])
ram_q0 <= ram0[a[12:0]];
end
// 4096 x 32 rom containing character definitions ($8000..$BFFF)
(* ram_init_file = "hub_rom_low.hex" *) reg [31:0] rom_low [4095:0];
reg [31:0] rom_low_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b10)
rom_low_q <= rom_low[a[11:0]];
// 4096 x 32 rom containing sin table, log table, booter, and interpreter ($C000..$FFFF)
(* ram_init_file = "hub_rom_high.hex" *) reg [31:0] rom_high [4095:0];
reg [31:0] rom_high_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b11)
rom_high_q <= rom_high[a[11:0]];
// memory output mux
reg [1:0] mem;
always @(posedge clk_cog)
if (ena_bus)
mem <= a[13:12];
assign q = !mem[1] ? {ram_q3, ram_q2, ram_q1, ram_q0}
// : !mem[0] ? rom_low_q // comment out this line for DE0-Nano (sacrifices character rom to fit device)
: rom_high_q;
endmodule
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module regfile (
input clk,
input reset,
output [31:0] rd1,
output [31:0] rd2,
input [4:0] rs1,
input [4:0] rs2,
input [4:0] wd,
input [31:0] w_data,
input w_enable,
input stall);
/* Registers */
reg [31:0] registers[31:0];
always @ (posedge clk) begin
if (w_enable & !stall & wd != 0)
registers[wd] <= w_data;
end
/* Outputs */
assign rd1 = rs1 == 0 ? 32'b0 : registers[rs1];
assign rd2 = rs2 == 0 ? 32'b0 : registers[rs2];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1005; double dis(long u, long v, long p, long q) { return sqrt(((double)u - p) * (u - p) + ((double)q - v) * (q - v)); } struct point { int x; int y; }; int main() { int n, m; cin >> n >> m; if (n == 0) { cout << 0 << << 1 << endl; cout << 0 << << m << endl; cout << 0 << << 0 << endl; cout << 0 << << m - 1 << endl; return 0; } if (m == 0) { cout << 1 << << 0 << endl; cout << n << << 0 << endl; cout << 0 << << 0 << endl; cout << n - 1 << << 0 << endl; return 0; } double tam1 = 2 * dis(0, 0, n - 1, m); double tam2 = 2 * dis(0, 0, n, m - 1); double tam3 = sqrt(double(m) * m + double(n) * n) + max(m, n); if (tam3 >= tam1 && tam3 >= tam2) { cout << 0 << << 0 << endl; cout << n << << m << endl; if (n > m) { cout << 0 << << m << endl; cout << n << << 0 << endl; } else { cout << n << << 0 << endl; cout << 0 << << m << endl; } return 0; } if (n <= m) { cout << n - 1 << << m << endl; cout << 0 << << 0 << endl; cout << n << << m << endl; cout << 1 << << 0 << endl; } else { cout << n << << m - 1 << endl; cout << 0 << << 0 << endl; cout << n << << m << endl; cout << 0 << << 1 << endl; } } |
#include <bits/stdc++.h> const int N = (int)2e5 + 5; const int MOD = (int)1e9 + 7; const bool MULTI_TEST = true; const double PI = acos(-1.0); using namespace std; void solve() { int n; cin >> n; int a[n]; int max = 0, index = -1; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] > max) { max = a[i]; } } if (*min_element(a, a + n) == max) cout << -1 n ; else { for (int i = 0; i < n - 1; i++) { if (a[i] == max && a[i] > a[i + 1]) index = i + 1; } if (index != -1) { cout << index << n ; return; } else { for (int i = 1; i < n; i++) { if (a[i] == max && a[i] > a[i - 1]) index = i + 1; } } cout << index << endl; } } int main() { ios_base::sync_with_stdio(false); int t = 1; if (MULTI_TEST) cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k; int a[100010]; int tot[200010]; int dis[200010]; int main() { queue<int> q; scanf( %d%d , &n, &k); for (int i = 0; i <= 4000; ++i) dis[i] = 1e9; for (int i = 1; i <= k; ++i) { scanf( %d , &a[i]); a[i] -= n; ++tot[a[i] + 2000]; if (dis[tot[a[i] + 2000]] == 1e9) q.push(a[i]); dis[a[i] + 2000] = 1; } while (!q.empty()) { int now = q.front(); q.pop(); for (int i = -2000; i <= 2000; ++i) { if (dis[i + 2000] == 1 && dis[i + now + 2000] == 1e9) { dis[i + now + 2000] = dis[now + 2000] + 1; q.push(i + now); } } } if (dis[2000] == 1e9) dis[2000] = -1; printf( %d n , dis[2000]); } |
#include <bits/stdc++.h> //#include <bits/extc++.h> #define ll long long #define endl n #define pb push_back #define ms(v,x) memset(v,x,sizeof(v)) #define ff first #define ss second #define td(v) v.begin(),v.end() #define rep(i,a,n) for (int i=(a);i<(n);i++) #define per(i,a,n) for (int i=(n-1);i>=a;i--) #define trav(a, x) for(auto& a : x) #define re(v) {for(auto &_re : v) cin >> _re;} #define pr(v) {for(auto _pr : v) cout << _pr << ; cout << endl;} #define sz(x) (int)(x).size() #define all(x) x.begin(), x.end() #define pii pair<int,int> #define pll pair<ll,ll> #define vi vector<int> #define vl vector<ll> #define eb emplace_back using namespace std; using vvi = vector<vi>; using vvl = vector<vl>; const ll M = 1e9 + 7; //const ll M = 998244353; //const ll M = 1e6; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); ll binpow(ll a, ll b){ ll res = (a!=0); while(b > 0){ if(b&1) res = res * a % M; a = a * a % M; b>>=1; } return res; } //#define double long double //#define int long long //#define tiii tuple<int,int,int> //#define uint unsigned int void solve(){ int n; cin >> n; vi a(n), c(n + 1); re(a); for(int i=0;i<n;i++){ int j = i; while(j+1 < n && a[j + 1] == a[i]){ j++; } c[a[i]]++; i = j; } int ans = n + 1; for(int i=0;i<n;i++){ ans = min(ans, c[a[i]] + 1 - (a[i] == a[0]) - (a[i] == a.back())); } cout << ans << endl; } int32_t main(){ ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); //freopen( .in , r , stdin); //freopen( .out , w , stdout); int t = 1; cin >> t; while(t--){ solve(); } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Sub sub1 (.*);
Sub sub2 (.*);
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Simple cover
cover property (@(posedge clk) cyc==3);
// With statement, in generate
generate if (1) begin
cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4");
end
endgenerate
// Labeled cover
cyc_eq_5:
cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
// Using default clock
default clocking @(posedge clk); endclocking
cover property (cyc==6) $display("*COVER: Cyc==6");
// Disable statement
// Note () after disable are required
cover property (@(posedge clk) disable iff (toggle) cyc==8)
$display("*COVER: Cyc==8");
cover property (@(posedge clk) disable iff (!toggle) cyc==8)
$stop;
always_ff @ (posedge clk) begin
labeled_icov: cover (cyc==3 || cyc==4);
end
// Immediate cover
labeled_imm0: cover #0 (cyc == 0);
labeled_immf: cover final (cyc == 0);
// Immediate assert
labeled_imas: assert #0 (1);
assert final (1);
//============================================================
// Using a macro and generate
wire reset = (cyc < 2);
`define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn))
genvar i;
generate
for (i=0; i<32; i=i+1)
begin: cycval
CycCover_i: `covclk( cyc[i] );
end
endgenerate
`ifndef verilator // Unsupported
//============================================================
// Using a more complicated property
property C1;
@(posedge clk)
disable iff (!toggle)
cyc==5;
endproperty
cover property (C1) $display("*COVER: Cyc==5");
// Using covergroup
// Note a covergroup is really inheritance of a special system "covergroup" class.
covergroup counter1 @ (posedge cyc);
// Automatic methods: stop(), start(), sample(), set_inst_name()
// Each bin value must be <= 32 bits. Strange.
cyc_value : coverpoint cyc {
}
cyc_bined : coverpoint cyc {
bins zero = {0};
bins low = {1,5};
// Note 5 is also in the bin above. Only the first bin matching is counted.
bins mid = {[5:$]};
// illegal_bins // Has precidence over "first matching bin", creates assertion
// ignore_bins // Not counted, and not part of total
}
toggle : coverpoint (toggle) {
bins off = {0};
bins on = {1};
}
cyc5 : coverpoint (cyc==5) {
bins five = {1};
}
// option.at_least = {number}; // Default 1 - Hits to be considered covered
// option.auto_bin_max = {number}; // Default 64
// option.comment = {string}
// option.goal = {number}; // Default 90%
// option.name = {string}
// option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1)
// option.weight = {number}; // Default 1
// CROSS
value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n>
cross cyc_value, toggle;
endgroup
counter1 c1 = new();
`endif
endmodule
module Sub
(
input clk,
input integer cyc
);
// Simple cover, per-instance
pi_sub:
cover property (@(posedge clk) cyc == 3);
endmodule
|
#include <bits/stdc++.h> using namespace std; int v[11][100010]; int vmap[11][100010]; int pointer[11]; int main() { int n, m; scanf( %d %d , &n, &m); long long ans = 0; for (int j = 0; j < m; j++) { for (int i = 0; i < n; i++) { scanf( %d , &v[j][i]); v[j][i]--; vmap[j][v[j][i]] = i; } } bool isNew = true; long long sz; for (int i = 0; i < n; i++) { if (isNew) { for (int j = 1; j < m; j++) pointer[j] = vmap[j][v[0][i]]; sz = 1; ans += 1; isNew = false; } else { bool check = true; sz++; for (int j = 1; j < m && check; j++) { pointer[j]++; if (pointer[j] >= n || v[j][pointer[j]] != v[0][i]) check = false; } if (check) ans += sz; else { isNew = true; i--; } } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> bool chkmax(T &x, T y) { return x < y ? x = y, true : false; } template <typename T> bool chkmin(T &x, T y) { return x > y ? x = y, true : false; } int readint() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, m, rt; long long a[4005], rmq[4005][20], ch[4005][2], lg2[4005], siz[4005]; long long d[4005][4005]; int getmin(int l, int r) { int k = lg2[r - l + 1]; return a[rmq[l][k]] < a[rmq[r - (1 << k) + 1][k]] ? rmq[l][k] : rmq[r - (1 << k) + 1][k]; } int build(int l, int r) { int mid = getmin(l, r); if (l != mid) ch[mid][0] = build(l, mid - 1); if (r != mid) ch[mid][1] = build(mid + 1, r); return mid; } void dfs(int u) { if (!u) return; siz[u] = 1; dfs(ch[u][0]), dfs(ch[u][1]); siz[u] += siz[ch[u][0]] + siz[ch[u][1]]; for (int i = 0; i <= siz[ch[u][0]]; i++) { for (int j = 0; j <= siz[ch[u][1]]; j++) { chkmax(d[u][i + j], d[ch[u][0]][i] + d[ch[u][1]][j] - 2ll * i * j * a[u]); chkmax(d[u][i + j + 1], d[ch[u][0]][i] + d[ch[u][1]][j] - 2ll * i * j * a[u] + 1ll * (m - 1) * a[u] - 2ll * (i + j) * a[u]); } } } int main() { n = readint(); m = readint(); for (int i = 1; i <= n; i++) a[i] = readint(); for (int i = 2; i <= n; i++) lg2[i] = lg2[i >> 1] + 1; for (int i = 1; i <= n; i++) rmq[i][0] = i; for (int i = 1; (1 << i) <= n; i++) for (int j = 1; j + (1 << i) - 1 <= n; j++) rmq[j][i] = a[rmq[j][i - 1]] < a[rmq[j + (1 << (i - 1))][i - 1]] ? rmq[j][i - 1] : rmq[j + (1 << (i - 1))][i - 1]; rt = build(1, n); for (int i = 0; i <= n; i++) for (int j = 0; j <= n; j++) d[i][j] = -(1ll << 60); d[0][0] = 0; dfs(rt); printf( %lld n , d[rt][m]); return 0; } |
(** * Gen: Generalizing Induction Hypotheses *)
(* $Date: 2011-06-07 16:49:17 -0400 (Tue, 07 Jun 2011) $ *)
Require Export Poly.
(** In the previous chapter, we noticed the importance of
controlling the exact form of the induction hypothesis when
carrying out inductive proofs in Coq. In particular, we need to
be careful about which of the assumptions we move (using [intros])
from the goal to the context before invoking the [induction]
tactic. In this short chapter, we consider this point in a little
more depth and introduce one new tactic, called [generalize
dependent], that is sometimes useful in helping massage the
induction hypothesis into the required form.
First, let's review the basic issue. Suppose we want to show that
the [double] function is injective -- i.e., that it always maps
different arguments to different results. The way we _start_ this
proof is a little bit delicate: if we begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'".
assert (n' = m') as H.
SSCase "Proof of assertion".
(* Here we are stuck. We need the assertion in order to
rewrite the final goal (subgoal 2 at this point) to an
identity. But the induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the assertion is not provable. *)
Admitted.
(** What went wrong?
The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context
-- intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we can prove
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.)
To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective' : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for *every* [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O". inversion eq. (* The 0 case is trivial *)
SCase "m = S m'".
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
assert (n' = m') as H.
SSCase "Proof of assertion". apply IHn'.
inversion eq. reflexivity.
rewrite -> H. reflexivity. Qed.
(** What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** However, this strategy doesn't always apply directly; sometimes a
little rearrangement is needed. Suppose, for example, that we had
decided we wanted to prove [double_injective] by induction on [m]
instead of [n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'".
assert (n' = m') as H.
SSCase "Proof of assertion".
(* Here we are stuck again, just like before. *)
Admitted.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'".
assert (n' = m') as H.
SSCase "Proof of assertion".
apply IHm'. inversion eq. reflexivity.
rewrite -> H. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** **** Exercise: 3 stars, recommended (gen_dep_practice) *)
(** Carry out this proof by induction on [m]. *)
Theorem plus_n_n_injective_take2 : forall n m,
n + n = m + m ->
n = m.
Proof.
(* FILL IN HERE *) Admitted.
(** Now prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index (S n) l = None.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars (gen_dep_practice_opt) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DFSBP_FUNCTIONAL_PP_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSBP_FUNCTIONAL_PP_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 08 17:42:47 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_rgb888_to_rgb565_0_0 -prefix
// system_rgb888_to_rgb565_0_0_ system_rgb888_to_rgb565_0_0_stub.v
// Design : system_rgb888_to_rgb565_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb888_to_rgb565,Vivado 2016.4" *)
module system_rgb888_to_rgb565_0_0(rgb_888, rgb_565)
/* synthesis syn_black_box black_box_pad_pin="rgb_888[23:0],rgb_565[15:0]" */;
input [23:0]rgb_888;
output [15:0]rgb_565;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> T gcd(T a, T b) { T r; while (b != 0) { r = a % b; a = b; b = r; } return a; } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } template <class T> int getbit(T s, int i) { return (s >> i) & 1; } template <class T> T onbit(T s, int i) { return s | (T(1) << i); } template <class T> T offbit(T s, int i) { return s & (~(T(1) << i)); } const double PI = 2 * acos(0.0); const double eps = 1e-9; const int infi = 1e9; const long long Linfi = (long long)1e18; const long long MOD = 1000000007; const int c1 = 11; const int c2 = 13; int n, m, dx, dy; int a[100005], b[100005]; map<int, int> M; long long power(int a, int p, int M) { if (p == 0) return 1; if (p == 1) return a % M; long long ans = power(a, p / 2, M); ans = (ans * ans) % M; if (p % 2 == 1) ans = (ans * a) % M; return ans; } int phiEuler(int n) { int res = n; for (int i = 2; i * i <= n; i++) { if (n % i == 0) res -= res / i; while (n % i == 0) n /= i; } if (n > 1) res -= res / n; return res; } void solve() { int phi = phiEuler(n); for (int i = 1; i <= m; i++) { long long inver = power(dx, phi - 1, n); long long k = inver * (n - a[i]); k %= n; long long tmp = (b[i] + k * dy) % n; M[tmp]++; } int maxx = 0, val = -1; for (typeof(M.begin()) i = M.begin(); i != M.end(); i++) { if (i->second > maxx) { maxx = i->second; val = i->first; } } cout << 0 << << val << endl; } int main() { ios::sync_with_stdio(false); cin >> n >> m >> dx >> dy; for (int i = 1; i <= m; i++) { cin >> a[i] >> b[i]; } solve(); return 0; } |
`timescale 1ns / 1ps
module nkmd_ddr3_mig_if_t;
// ins
reg clk;
parameter TCLK = 20;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg rst;
reg [31:0] nkmd_data_i;
wire [31:0] nkmd_data_o;
reg [15:0] nkmd_addr;
reg nkmd_we;
reg [31:0] mig_rd_data;
reg [6:0] mig_rd_count;
nkmd_ddr3_mig_if uut(
.clk(clk),
.rst(rst),
.mig_cmd_empty(1'b1),
.mig_cmd_full(1'b0),
.mig_wr_full(1'b1),
.mig_wr_empty(1'b0),
// .mig_wr_count,
// .mig_wr_underrun,
// .mig_wr_error,
.mig_rd_data(mig_rd_data),
// .mig_rd_full,
// .mig_rd_empty,
.mig_rd_count(mig_rd_count),
// .mig_rd_overflow,
// .mig_rd_error,
.data_i(nkmd_data_i),
.data_o(nkmd_data_o),
.addr_i(nkmd_addr),
.we_i(nkmd_we));
task nkmd_write;
input [15:0] addr;
input [31:0] data;
begin
nkmd_addr = addr;
nkmd_data_i = data;
nkmd_we = 1'b1;
#(TCLK);
nkmd_we = 1'b0;
end
endtask
task nkmd_read;
input [15:0] addr;
begin
nkmd_addr = addr;
#(TCLK);
$display("read addr: %x data: %x", nkmd_addr, nkmd_data_o);
end
endtask
reg [31:0] i;
initial begin
$dumpfile("nkmd_ddr3_mig_if_t.lxt");
$dumpvars(0, nkmd_ddr3_mig_if_t);
nkmd_data_i = 32'h0;
nkmd_addr = 16'h0;
nkmd_we = 1'b0;
mig_rd_data = 32'hdeadbeef;
mig_rd_count = 6'h00;
rst = 1'b1;
#(TCLK);
rst = 1'b0;
#(TCLK*10);
nkmd_write(16'h1080, 32'h00000001);
nkmd_write(16'h1081, 32'h00000002);
nkmd_write(16'h1082, 32'h00000003);
nkmd_write(16'h1083, 32'h00000004);
nkmd_write(16'h1084, 32'h00000005);
nkmd_write(16'h1085, 32'h00000006);
nkmd_write(16'h1086, 32'h00000007);
nkmd_write(16'h1087, 32'h00000008);
nkmd_write(16'hc100, 32'h0abcdefc);
nkmd_write(16'hc101, 32'h00000080);
nkmd_write(16'hc102, 32'h00000003);
nkmd_write(16'hc103, 32'h00000001);
#(TCLK*32);
nkmd_write(16'hc100, 32'hadadadad);
nkmd_write(16'hc101, 32'h000000c0);
nkmd_write(16'hc102, 32'h00000001);
nkmd_write(16'hc103, 32'h00000000);
#(TCLK*10);
mig_rd_count = 6'h02;
#(TCLK);
mig_rd_count = 6'h01;
mig_rd_data = 32'hcafebabe;
#(TCLK);
mig_rd_count = 6'h00;
#(TCLK*10);
nkmd_read(16'h10c0);
nkmd_read(16'h10c1);
nkmd_read(16'h10c2);
$finish(2);
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[25] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 4, 9, 25, 49}; int main() { string s; int num = 0; for (int i = 0; i < 19; i++) { printf( %d n , a[i]); fflush(stdout); cin >> s; if (s == yes ) num++; } if (num <= 1) printf( prime n ); else printf( composite n ); fflush(stdout); } |
`timescale 1ns / 1ns
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:28:18 02/06/2014
// Design Name:
// Module Name: test1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tld_zxuno (
input wire clk50mhz,
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire csync,
output wire stdn,
output wire stdnb
);
assign stdn = 1'b0;
assign stdnb = 1'b1;
// Generación de relojes
reg [1:0] divs = 2'b00;
wire wssclk,sysclk;
wire clk14 = divs[0];
wire clk7 = divs[1];
always @(posedge sysclk)
divs <= divs + 1;
relojes los_relojes_del_sistema (
.CLKIN_IN(clk50mhz),
.CLKDV_OUT(wssclk),
.CLKFX_OUT(sysclk),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT(),
.LOCKED_OUT()
);
// Instanciación del sistema
zxuno la_maquina (
.clk(clk7),
.wssclk(wssclk),
.r(r),
.g(g),
.b(b),
.csync(csync)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int x; int dfs(int xx, int yy, int cc) { if (cc == 0) { if (xx == 1 || yy == 1) { int tt = xx * yy; if (tt % 2 == 0) return tt / 2; else return tt / 2 + 1; } else return ((xx + yy) * 2 - 4) / 2; } if (xx <= 2 || yy <= 2) { if (cc >= 1) return 0; int k = xx * yy; if (k % 2 == 0) return k / 2; return k / 2 + 1; } int g = dfs(xx - 2, yy - 2, cc - 1); return g; } int main() { while (cin >> n >> m >> x) { int t = dfs(n, m, x - 1); cout << t << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d, e, f; cin >> a >> b >> c >> d >> e >> f; cout << (a + b + f) * (a + b + f) - b * b - d * d - f * f << endl; return 0; } |
// DESCRIPTION: Verilator: Test of gated clock detection
//
// The code as shown generates a result by a delayed assignment from PC. The
// creation of the result is from a clock gated from the clock that sets
// PC. Howevever since they are essentially the same clock, the result should
// be delayed by one cycle.
//
// Standard Verilator treats them as different clocks, so the result stays in
// step with the PC. An event drive simulator always allows the clock to win.
//
// The problem is caused by the extra loop added by Verilator to the
// evaluation of all internally generated clocks (effectively removed by
// marking the clock enable).
//
// This test is added to facilitate experiments with solutions.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jeremy Bennett <>.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg gated_clk_en = 1'b0 ;
reg [1:0] pc = 2'b0;
reg [1:0] res = 2'b0;
wire gated_clk = gated_clk_en & clk;
always @(posedge clk) begin
pc <= pc + 1;
gated_clk_en <= 1'b1;
end
always @(posedge gated_clk) begin
res <= pc;
end
always @(posedge clk) begin
if (pc == 2'b11) begin
// Correct behaviour is that res should be lagging pc in the count
// by one cycle
if (res == 2'b10) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$stop;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long N; long long x, y, x2, y2; pair<int, int> v[100010]; bool Can(long long n) { long long Rem = n % N; long long Count = n / N; long long X = v[Rem].first + (v[N].first * Count); long long Y = v[Rem].second + (v[N].second * Count); return ((abs(x2 - (X + x)) + abs(y2 - (Y + y))) <= n); } void Solve() { cin >> x >> y; cin >> x2 >> y2; cin >> N; string s; cin >> s; long long X = 0, Y = 0; for (long long i = 0; i < N; ++i) { if (s[i] == U ) { Y++; } else if (s[i] == D ) { Y--; } else if (s[i] == L ) { X--; } else if (s[i] == R ) { X++; } v[i + 1] = make_pair(X, Y); } long long ans = -1; long long low = 0, high = (1100000000000000000ll); while (low <= high) { long long mid = (low + high) / 2; if (Can(mid)) { high = mid - 1; ans = mid; } else { low = mid + 1; } } cout << ans << endl; } int main() { ios::sync_with_stdio(NULL); cin.tie(NULL); cout.tie(NULL); int t = 1; while (t--) Solve(); return 0; } |
#include <bits/stdc++.h> using std::pair; using std::string; using std::vector; template <typename T> bool chkmax(T& a, T b) { return a < b ? a = b, 1 : 0; } template <typename T> bool chkmin(T& a, T b) { return a > b ? a = b, 1 : 0; } const int oo = 0x3f3f3f3f; string procStatus() { std::ifstream t( /proc/self/status ); return string(std::istreambuf_iterator<char>(t), std::istreambuf_iterator<char>()); } template <typename T> T read(T& x) { int f = 1; x = 0; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -1; for (; isdigit(ch); ch = getchar()) x = x * 10 + ch - 48; return x *= f; } const int N = 10000; struct point { int x, y; point(int _x = 0, int _y = 0) : x(_x), y(_y) {} point operator+(const point& rhs) const { return point(x + rhs.x, y + rhs.y); } point operator-(const point& rhs) const { return point(x - rhs.x, y - rhs.y); } bool operator<(const point& rhs) const { return x < rhs.x || (x == rhs.x && y < rhs.y); } }; inline int dot(const point& a, const point& b) { return a.x * b.x + a.y * b.y; } inline int cross(const point& a, const point& b) { return a.x * b.y - a.y * b.x; } vector<point> convex_hull(vector<point> a) { vector<point> h; std::sort(a.begin(), a.end()); for (auto p : a) { while ((int)h.size() > 1 && cross(p - *h.rbegin(), p - *(h.rbegin() + 1)) >= 0) { h.pop_back(); } h.push_back(p); } int m = h.size(); h.pop_back(); std::reverse(a.begin(), a.end()); for (auto p : a) { while ((int)h.size() > m && cross(p - *h.rbegin(), p - *(h.rbegin() + 1)) >= 0) { h.pop_back(); } h.push_back(p); } h.pop_back(); return h; } bool solve(vector<point> a, vector<point> b) { vector<pair<int, int> > edge; std::function<void(int, int)> get = [&](int l, int r) { edge.push_back(std::make_pair(l, r)); if (r - l < 2) return; int p = -1; double mx = -DBL_MAX; for (int i = l + 1; i < r; ++i) { double temp = 1. * dot(a[r] - a[i], a[l] - a[i]) / cross(a[r] - a[i], a[l] - a[i]); if (chkmax(mx, temp)) p = i; } get(l, p); get(p, r); }; a = convex_hull(a); get(0, a.size() - 1); for (auto e : edge) { int x = e.first, y = e.second; double l = -DBL_MAX, r = DBL_MAX; for (int i = 0; i < (int)a.size() && l < r; ++i) { int p = dot(a[y] - a[i], a[x] - a[i]); int q = cross(a[y] - a[i], a[x] - a[i]); if (!q) continue; if (q < 0) { chkmin(r, double(p) / q); } else { chkmax(l, double(p) / q); } } for (int i = 0; i < (int)b.size() && l < r; ++i) { int p = dot(a[y] - b[i], a[x] - b[i]); int q = cross(a[y] - b[i], a[x] - b[i]); if (!q) { if (p > 0) continue; l = DBL_MAX; break; } if (q < 0) { chkmax(l, double(p) / q); } else { chkmin(r, double(p) / q); } } if (l < r) return true; } return false; } int n, m; vector<point> a, b; int main() { read(n), read(m); for (int i = 0, x, y; i < n; ++i) read(x), read(y), a.push_back(point(x, y)); for (int i = 0, x, y; i < m; ++i) read(x), read(y), b.push_back(point(x, y)); if (n == 1 || m == 1) return puts( YES ), 0; puts((solve(a, b) || solve(b, a)) ? YES : NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; double x[1005], y[1005], z[1005], r[1005]; long long int n, m; int main() { double res = (1ll << (long long int)(60)), ax, ay, az, vx, vy, vz, R; cin >> ax >> ay >> az >> vx >> vy >> vz >> R >> n; for (long long int i = 0; i < ((long long int)(n)); i++) { cin >> x[0] >> y[0] >> z[0] >> r[0] >> m; for (long long int j = 0; j < ((long long int)(m)); j++) cin >> x[j + 1] >> y[j + 1] >> z[j + 1]; for (long long int j = 0; j < ((long long int)(m)); j++) x[j + 1] += x[0], y[j + 1] += y[0], z[j + 1] += z[0]; for (long long int j = 0; j < ((long long int)(m + 1)); j++) { double t = -(vx * (ax - x[j]) + vy * (ay - y[j]) + vz * (az - z[j])) / ((vx) * (vx) + (vy) * (vy) + (vz) * (vz)); if (t < 0) continue; if (((vx * t + ax - x[j]) * (vx * t + ax - x[j]) + (vy * t + ay - y[j]) * (vy * t + ay - y[j]) + (vz * t + az - z[j]) * (vz * t + az - z[j])) < (R + r[j]) * (R + r[j]) + 0.0000001) { double low = 0, high = t; for (long long int k = 0; k < ((long long int)(100)); k++) { double mid = (low + high) / 2.0; if (((vx * mid + ax - x[j]) * (vx * mid + ax - x[j]) + (vy * mid + ay - y[j]) * (vy * mid + ay - y[j]) + (vz * mid + az - z[j]) * (vz * mid + az - z[j])) < (R + r[j]) * (R + r[j])) high = mid; else low = mid; } res = min(res, low); } } } if (res == (1ll << (long long int)(60))) cout << -1 << endl; else printf( %0.20lf n , res); } |
#include <bits/stdc++.h> using namespace std; int a, b, c; vector<int> ans; int sum(int curr) { int sum = 0; while (curr > 0) { sum += curr % 10; curr = curr / 10; } return sum; } long long go(long long x, int n) { long long ans = 1; for (int i = 0; i < n; i++) { ans = ans * x; } return ans; } int main() { scanf( %d %d %d , &a, &b, &c); for (int i = 0; i <= 81; i++) { long long curr = go(i, a) * b + c; if (curr > 1000000000LL || curr <= 0) continue; if (sum(curr) == i) ans.push_back(curr); } printf( %d n , ans.size()); for (int i = 0; i < ans.size(); i++) { printf( %d , ans[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[500009], posin[500009]; vector<int> pairs[500009]; int main() { int n, m, x, y, c = 0; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); posin[a[i]] = i; } for (int i = 0; i < m; i++) { scanf( %d %d , &x, &y); pairs[x].push_back(posin[y]); pairs[y].push_back(posin[x]); } x = -1, y = 0; long long int sol = 0; while (y < n && x < y) { if (c) { x++; for (int i = 0; i < pairs[a[x]].size(); i++) if (pairs[a[x]][i] > x && pairs[a[x]][i] <= y) { c--; } } else { sol += (y - x); y++; for (int i = 0; i < pairs[a[y]].size(); i++) if (pairs[a[y]][i] > x && pairs[a[y]][i] <= y) { c++; } } } printf( %I64d n , sol); } |
// Automatically generated: write_netlist -wrapapp -verilog -module reconflogic-wrapmax6682.v
module MyReconfigLogic (
input Reset_n_i,
input Clk_i,
input AdcConvComplete_i,
output AdcDoConvert_o,
input[9:0] AdcValue_i,
input I2C_Busy_i,
output[7:0] I2C_DataIn_o,
input[7:0] I2C_DataOut_i,
output[15:0] I2C_Divider800_o,
output I2C_ErrAckParam_o,
input I2C_Error_i,
output I2C_F100_400_n_o,
input I2C_FIFOEmpty_i,
input I2C_FIFOFull_i,
output I2C_FIFOReadNext_o,
output I2C_FIFOWrite_o,
output[3:0] I2C_ReadCount_o,
output I2C_ReceiveSend_n_o,
output I2C_StartProcess_o,
input[7:0] Inputs_i,
output[7:0] Outputs_o,
output[4:0] ReconfModuleIRQs_o,
output SPI_CPHA_o,
output SPI_CPOL_o,
output[7:0] SPI_DataIn_o,
input[7:0] SPI_DataOut_i,
input SPI_FIFOEmpty_i,
input SPI_FIFOFull_i,
output SPI_LSBFE_o,
output SPI_ReadNext_o,
output[7:0] SPI_SPPR_SPR_o,
input SPI_Transmission_i,
output SPI_Write_o,
input[7:0] ReconfModuleIn_i,
output[7:0] ReconfModuleOut_o,
input[7:0] I2C_Errors_i,
input[13:0] PerAddr_i,
input[15:0] PerDIn_i,
input[1:0] PerWr_i,
input PerEn_i,
output[15:0] CfgIntfDOut_o,
output[15:0] ParamIntfDOut_o
);
wire [15:0] PeriodCounterPresetH_s;
wire [15:0] PeriodCounterPresetL_s;
wire [15:0] SensorValue_s;
wire [15:0] Threshold_s;
wire [0:0] CfgClk_s;
wire CfgMode_s;
wire [0:0] CfgShift_s;
wire CfgDataOut_s;
wire [0:0] CfgDataIn_s;
wire [2:0] ParamWrAddr_s;
wire [15:0] ParamWrData_s;
wire ParamWr_s;
wire [0:0] ParamRdAddr_s;
wire [15:0] ParamRdData_s;
TODO: implement
wire Params_s;
wire [0:0] I2C_ErrAckParam_s;
wire ParamI2C_Divider800Enable_s;
wire ParamI2C_ErrAckParamEnable_s;
wire ParamPeriodCounterPresetHEnable_s;
wire ParamPeriodCounterPresetLEnable_s;
wire ParamThresholdEnable_s;
// Configuration Interface
CfgIntf #(
.BaseAddr('h0180),
.NumCfgs(1)
) CfgIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(CfgIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.CfgClk_o(CfgClk_s),
.CfgMode_o(CfgMode_s),
.CfgShift_o(CfgShift_s),
.CfgDataOut_o(CfgDataOut_s),
.CfgDataIn_i(CfgDataIn_s)
);
// Parameterization Interface: 5 write addresses, 2 read addresses
ParamIntf #(
.BaseAddr('h0188),
.WrAddrWidth(3),
.RdAddrWidth(1)
) ParamIntf_0 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.PerAddr_i(PerAddr_i),
.PerDIn_i(PerDIn_i),
.PerDOut_o(ParamIntfDOut_o),
.PerWr_i(PerWr_i),
.PerEn_i(PerEn_i),
.ParamWrAddr_o(ParamWrAddr_s),
.ParamWrData_o(ParamWrData_s),
.ParamWr_o(ParamWr_s),
.ParamRdAddr_o(ParamRdAddr_s),
.ParamRdData_i(ParamRdData_s)
);
MAX6682 MAX6682_0 (
.MAX6682CS_n_o(Outputs_o[0]),
.CpuIntr_o(ReconfModuleIRQs_o[0]),
.SPI_Data_o(SPI_DataIn_o),
.SPI_Data_i(SPI_DataOut_i),
.SPI_FIFOEmpty_i(SPI_FIFOEmpty_i),
.SPI_FIFOFull_i(SPI_FIFOFull_i),
.SPI_ReadNext_o(SPI_ReadNext_o),
.SPI_Transmission_i(SPI_Transmission_i),
.SPI_Write_o(SPI_Write_o),
.Enable_i(ReconfModuleIn_i[0]),
.Clk_i(Clk_i),
.Reset_n_i(Reset_n_i),
.PeriodCounterPresetH_i(PeriodCounterPresetH_s),
.PeriodCounterPresetL_i(PeriodCounterPresetL_s),
.SensorValue_o(SensorValue_s),
.Threshold_i(Threshold_s)
);
assign AdcDoConvert_o = 1'b0;
assign I2C_DataIn_o = 8'b00000000;
assign I2C_F100_400_n_o = 1'b0;
assign I2C_FIFOReadNext_o = 1'b0;
assign I2C_FIFOWrite_o = 1'b0;
assign I2C_ReadCount_o = 4'b0000;
assign I2C_ReceiveSend_n_o = 1'b0;
assign I2C_StartProcess_o = 1'b0;
assign Outputs_o[1] = 1'b0;
assign Outputs_o[2] = 1'b0;
assign Outputs_o[3] = 1'b0;
assign Outputs_o[4] = 1'b0;
assign Outputs_o[5] = 1'b0;
assign Outputs_o[6] = 1'b0;
assign Outputs_o[7] = 1'b0;
assign ReconfModuleIRQs_o[1] = 1'b0;
assign ReconfModuleIRQs_o[2] = 1'b0;
assign ReconfModuleIRQs_o[3] = 1'b0;
assign ReconfModuleIRQs_o[4] = 1'b0;
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_LSBFE_o = 1'b0;
assign SPI_SPPR_SPR_o = 8'b00000000;
assign ReconfModuleOut_o[0] = 1'b0;
assign ReconfModuleOut_o[1] = 1'b0;
assign ReconfModuleOut_o[2] = 1'b0;
assign ReconfModuleOut_o[3] = 1'b0;
assign ReconfModuleOut_o[4] = 1'b0;
assign ReconfModuleOut_o[5] = 1'b0;
assign ReconfModuleOut_o[6] = 1'b0;
assign ReconfModuleOut_o[7] = 1'b0;
/* just a fixed value for the config interface */
assign CfgDataIn_s = 1'b0;
/* Param read address decoder
Synthesis: Accept undefined behavior if ParamRdAddr_s >= NumParams and
hope that the synthesis optimizes the MUX
Simulation: ModelSim complains "Fatal: (vsim-3421) Value x is out of range
0 to n.", even during param write cycles, because ParamRdAddr has the
source as ParamWrAddr. Use the parameter "-noindexcheck" during
compilation ("vcom"). Simulation works fine then, but ModelSim generates
numerous "INTERNAL ERROR"s to stdout, which seem harmless. */
assign ParamRdData_s = Params_s[to_integer(unsigned(ParamRdAddr_s))];
ParamOutReg #(
.Width(16)
) ParamOutReg_I2C_Divider800 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_Divider800_o),
.Enable_i(ParamI2C_Divider800Enable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(1)
) ParamOutReg_I2C_ErrAckParam (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(I2C_ErrAckParam_s),
.Enable_i(ParamI2C_ErrAckParamEnable_s),
.ParamWrData_i(ParamWrData_s[0:0])
);
ParamOutReg #(
.Width(16)
) ParamOutReg_PeriodCounterPresetH (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(PeriodCounterPresetH_s),
.Enable_i(ParamPeriodCounterPresetHEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_PeriodCounterPresetL (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(PeriodCounterPresetL_s),
.Enable_i(ParamPeriodCounterPresetLEnable_s),
.ParamWrData_i(ParamWrData_s)
);
ParamOutReg #(
.Width(16)
) ParamOutReg_Threshold (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Param_o(Threshold_s),
.Enable_i(ParamThresholdEnable_s),
.ParamWrData_i(ParamWrData_s)
);
assign I2C_ErrAckParam_o = I2C_ErrAckParam_s[0];
/* Address $00 */
assign Params_s[0] = { 8'b00000000, I2C_Errors_i };
/* Address $01 */
assign Params_s[1] = SensorValue_s;
/* Address $00 */
assign ParamI2C_Divider800Enable_s = TODO: implement;
/* Address $01 */
assign ParamI2C_ErrAckParamEnable_s = TODO: implement;
/* Address $02 */
assign ParamPeriodCounterPresetHEnable_s = TODO: implement;
/* Address $03 */
assign ParamPeriodCounterPresetLEnable_s = TODO: implement;
/* Address $04 */
assign ParamThresholdEnable_s = TODO: implement;
endmodule
|
module grid_AD7490(
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output [31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_address,
input [3:0] avs_ctrl_byteenable,
input avs_ctrl_write,
input avs_ctrl_read,
output avs_ctrl_waitrequest,
input csi_ADCCLK_clk,
output [3:0] aso_adc_channel,
output [15:0] aso_adc_data,
output aso_adc_valid,
input aso_adc_ready,
output coe_DIN,
input coe_DOUT,
output coe_SCLK,
output coe_CSN
);
assign avs_ctrl_readdata = read_data;
assign avs_ctrl_waitrequest = 1'b0;
assign aso_adc_channel = adc_aso_ch;
assign aso_adc_data = {adc_aso_data, 4'b0};
assign aso_adc_valid = adc_aso_valid;
assign coe_DIN = spi_din;
assign spi_dout = coe_DOUT;
assign coe_SCLK = spi_clk;
assign coe_CSN = spi_cs;
reg [31:0] read_data = 0;
reg spi_din = 0, spi_cs = 1, spi_clk = 1;
wire spi_dout;
reg [7:0] state = 0;
reg [7:0] delay = 0;
reg adc_range = 0;
reg adc_coding = 1;
reg adc_reset = 1;
reg [7:0] cnv_delay = 255;
reg [11:0] adc_ch[0:15] = 0;
reg [3:0] adc_addr = 0;
reg [3:0] adc_aso_ch = 0;
reg [11:0] adc_aso_data = 0;
reg adc_aso_valid = 0;
/*
* GRID_MOD_SIZE 0x0
* GRID_MOD_ID 0x4
* ADC_CTRL 0x8
* CNV_DELAY 0xC
* ADC_CH0 0x20
* ADC_CH1 0x22
* ADC_CH2 0x24
* ADC_CH3 0x26
* ADC_CH4 0x28
* ADC_CH5 0x2A
* ADC_CH6 0x2C
* ADC_CH7 0x2E
* ADC_CH8 0x30
* ADC_CH9 0x32
* ADC_CH10 0x34
* ADC_CH11 0x36
* ADC_CH12 0x38
* ADC_CH13 0x3A
* ADC_CH14 0x3C
* ADC_CH15 0x3E
*/
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
read_data <= 0;
end
else begin
case(avs_ctrl_address)
0: read_data <= 64;
1: read_data <= 32'hEA680003;
2: read_data <= {4'b0, adc_addr, 7'b0, adc_range, 7'b0, adc_coding, 7'b0, adc_reset};
3: read_data <= {24'b0, cnv_delay};
8: read_data <= {adc_ch[1], 4'b0, adc_ch[0], 4'b0};
9: read_data <= {adc_ch[3], 4'b0, adc_ch[2], 4'b0};
10: read_data <= {adc_ch[5], 4'b0, adc_ch[4], 4'b0};
11: read_data <= {adc_ch[7], 4'b0, adc_ch[6], 4'b0};
12: read_data <= {adc_ch[9], 4'b0, adc_ch[8], 4'b0};
13: read_data <= {adc_ch[11], 4'b0, adc_ch[10], 4'b0};
14: read_data <= {adc_ch[13], 4'b0, adc_ch[12], 4'b0};
15: read_data <= {adc_ch[15], 4'b0, adc_ch[14], 4'b0};
default: read_data <= 0;
endcase
end
end
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if(rsi_MRST_reset) begin
adc_range <= 0;
adc_coding <= 1;
adc_reset <= 1;
cnv_delay <= 255;
end
else begin
if(avs_ctrl_write) begin
case(avs_ctrl_address)
2: begin
if(avs_ctrl_byteenable[2]) adc_range <= avs_ctrl_writedata[16];
if(avs_ctrl_byteenable[1]) adc_coding <= avs_ctrl_writedata[8];
if(avs_ctrl_byteenable[0]) adc_reset <= avs_ctrl_writedata[0];
end
3: begin
if(avs_ctrl_byteenable[0]) cnv_delay <= avs_ctrl_writedata[7:0];
end
default: begin end
endcase
end
end
end
wire rWRITE = 1;
wire rSEQ = 0;
wire rPM1 = 1;
wire rPM0 = 1;
wire rSHADOW = 0;
wire rWEAKTRI = 0;
always@(posedge csi_ADCCLK_clk or posedge adc_reset)
begin
if(adc_reset) begin
adc_ch[0] <= 0;
adc_ch[1] <= 0;
adc_ch[2] <= 0;
adc_ch[3] <= 0;
adc_ch[4] <= 0;
adc_ch[5] <= 0;
adc_ch[6] <= 0;
adc_ch[7] <= 0;
adc_ch[8] <= 0;
adc_ch[9] <= 0;
adc_ch[10] <= 0;
adc_ch[11] <= 0;
adc_ch[12] <= 0;
adc_ch[13] <= 0;
adc_ch[14] <= 0;
adc_ch[15] <= 0;
adc_addr <= 0;
adc_aso_ch <= 0;
adc_aso_data <= 0;
adc_aso_valid <= 0;
spi_din <= 0;
spi_cs <= 1;
spi_clk <= 1;
state <= 0;
delay <= 0;
end
else begin
case(state)
0: begin state <= state + 1; spi_clk <= 1; spi_din <= rWRITE; spi_cs <= 1; delay <= 0; end
1: begin if(delay > cnv_delay) begin delay <= 0; state <= state + 1; end else delay <= delay + 1; end
2: begin state <= state + 1; spi_clk <= 1; spi_din <= rWRITE; spi_cs <= 0; end
3: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[3] <= spi_dout; end
4: begin state <= state + 1; spi_clk <= 1; spi_din <= rSEQ; end
5: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[2] <= spi_dout; end
6: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[3]; end
7: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[1] <= spi_dout; end
8: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[2]; end
9: begin state <= state + 1; spi_clk <= 0; adc_aso_ch[0] <= spi_dout; end
10: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[1]; end
11: begin state <= state + 1; spi_clk <= 0; adc_aso_data[11] <= spi_dout; end
12: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_addr[0]; end
13: begin state <= state + 1; spi_clk <= 0; adc_aso_data[10] <= spi_dout; end
14: begin state <= state + 1; spi_clk <= 1; spi_din <= rPM1; end
15: begin state <= state + 1; spi_clk <= 0; adc_aso_data[9] <= spi_dout; end
16: begin state <= state + 1; spi_clk <= 1; spi_din <= rPM0; end
17: begin state <= state + 1; spi_clk <= 0; adc_aso_data[8] <= spi_dout; end
18: begin state <= state + 1; spi_clk <= 1; spi_din <= rSHADOW; end
19: begin state <= state + 1; spi_clk <= 0; adc_aso_data[7] <= spi_dout; end
20: begin state <= state + 1; spi_clk <= 1; spi_din <= rWEAKTRI; end
21: begin state <= state + 1; spi_clk <= 0; adc_aso_data[6] <= spi_dout; end
22: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_range; end
23: begin state <= state + 1; spi_clk <= 0; adc_aso_data[5] <= spi_dout; end
24: begin state <= state + 1; spi_clk <= 1; spi_din <= adc_coding; end
25: begin state <= state + 1; spi_clk <= 0; adc_aso_data[4] <= spi_dout; end
26: begin state <= state + 1; spi_clk <= 1; spi_din <= 0; end
27: begin state <= state + 1; spi_clk <= 0; adc_aso_data[3] <= spi_dout; end
28: begin state <= state + 1; spi_clk <= 1; end
29: begin state <= state + 1; spi_clk <= 0; adc_aso_data[2] <= spi_dout; end
30: begin state <= state + 1; spi_clk <= 1; end
31: begin state <= state + 1; spi_clk <= 0; adc_aso_data[1] <= spi_dout; end
32: begin state <= state + 1; spi_clk <= 1; end
33: begin state <= state + 1; spi_clk <= 0; adc_aso_data[0] <= spi_dout; end
34: begin state <= state + 1; spi_clk <= 1; adc_ch[adc_aso_ch] <= adc_aso_data; adc_aso_valid <= 1; end
35: begin state <= 0; spi_cs <= 1; adc_aso_valid <= 0; adc_addr <= adc_addr + 1; end
default: begin
adc_ch[0] <= 0;
adc_ch[1] <= 0;
adc_ch[2] <= 0;
adc_ch[3] <= 0;
adc_ch[4] <= 0;
adc_ch[5] <= 0;
adc_ch[6] <= 0;
adc_ch[7] <= 0;
adc_ch[8] <= 0;
adc_ch[9] <= 0;
adc_ch[10] <= 0;
adc_ch[11] <= 0;
adc_ch[12] <= 0;
adc_ch[13] <= 0;
adc_ch[14] <= 0;
adc_ch[15] <= 0;
adc_addr <= 0;
adc_aso_ch <= 0;
adc_aso_data <= 0;
adc_aso_valid <= 0;
spi_din <= 0;
spi_cs <= 1;
spi_clk <= 1;
state <= 0;
delay <= 0;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFXTP_SYMBOL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_SYMBOL_V
|
#include <bits/stdc++.h> struct node { double x, y, z; } p[5005]; double d[5005]; double getlen(node a, node b) { double len; len = (a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y) + (a.z - b.z) * (a.z - b.z); return sqrt(len); } int main() { int n, i, j, a, b, c; while (scanf( %d , &n) != EOF) { for (i = 0; i < n; i++) { scanf( %d %d %d , &a, &b, &c); p[i].x = a * 1.0; p[i].y = b * 1.0; p[i].z = c * 1.0; } for (i = 1; i < n; i++) { d[i] = getlen(p[0], p[i]); } double lenn; double max = 9999999.0; for (i = 1; i < n; i++) { for (j = 1; j <= i; j++) { if (j == i) continue; lenn = d[i] + d[j] + getlen(p[i], p[j]); if (max - lenn > 1e-6) max = lenn; } } printf( %.10f n , max * 1.0 / 2.0); } return 0; } |
// Based on US Patent # 4,486,739 (expired)
// Byte Oriented DC Balanced 8B/10B Partitioned Block Transmission Code
// Author: Franaszek et al.
//
// https://patentimages.storage.googleapis.com/67/2d/ad/0258c2f0d807bf/US4486739.pdf
//
`include "bsg_defines.v"
module bsg_8b10b_encode_comb
( input [7:0] data_i
, input k_i
, input rd_i
, output logic [9:0] data_o
, output logic rd_o
, output logic kerr_o
);
wire A = data_i[0];
wire B = data_i[1];
wire C = data_i[2];
wire D = data_i[3];
wire E = data_i[4];
wire F = data_i[5];
wire G = data_i[6];
wire H = data_i[7];
// From FIG. 3
wire AxorB = A ^ B;
wire CxorD = C ^ D;
wire AandB = A & B;
wire CandD = C & D;
wire NAandNB = ~A & ~B;
wire NCandND = ~C & ~D;
wire L22 = (AandB & NCandND) | (CandD & NAandNB) | (AxorB & CxorD);
wire L40 = AandB & CandD;
wire L04 = NAandNB & NCandND;
wire L13 = (AxorB & NCandND) | (CxorD & NAandNB);
wire L31 = (AxorB & CandD) | (CxorD & AandB);
// From FIG. 4
wire FxorG = F ^ G;
wire FandG = F & G;
wire NFandNG = ~F & ~G;
wire NFandNGandNH = NFandNG & ~H;
wire FxorGandK = FxorG & k_i;
wire FxorGandNH = FxorG & ~H;
wire FandGandH = FandG & H;
wire S = (rd_i & L31 & D & ~E) | (~rd_i & L13 & ~D & E);
// Form FIG. 5
wire T0 = L13 & D & E; // Intermediate net
wire PDM1S6 = T0 | (~L22 & ~L31 & ~E);
wire ND0S6 = PDM1S6;
wire PD0S6 = (E & ~L22 & ~L13) | k_i;
wire NDM1S6 = (L31 & ~D & ~E) | PD0S6;
wire NDM1S4 = FandG;
wire ND0S4 = NFandNG;
wire PDM1S4 = NFandNG | FxorGandK;
wire PD0S4 = FandGandH;
// From FIG. 6
wire COMPLS6 = (NDM1S6 & rd_i) | (~rd_i & PDM1S6);
wire NDL6 = (PD0S6 & ~COMPLS6) | (COMPLS6 & ND0S6) | (~ND0S6 & ~PD0S6 & rd_i);
wire COMPLS4 = (NDM1S4 & NDL6) | (~NDL6 & PDM1S4 );
assign rd_o = (NDL6 & ~PD0S4 & ~ND0S4) | (ND0S4 & COMPLS4) | (~COMPLS4 & PD0S4);
// From FIG. 7
wire N0 = A;
wire N1 = (~L40 & B) | L04;
wire N2 = (L04 | C) | T0;
wire N3 = D & ~L40;
wire N4 = (~T0 & E) | (~E & L13);
wire N5 = (~E & L22) | (L22 & k_i) | (L04 & E) | (E & L40) | (E & L13 & ~D);
assign data_o[0] = N0 ^ COMPLS6;
assign data_o[1] = N1 ^ COMPLS6;
assign data_o[2] = N2 ^ COMPLS6;
assign data_o[3] = N3 ^ COMPLS6;
assign data_o[4] = N4 ^ COMPLS6;
assign data_o[5] = N5 ^ COMPLS6;
// From FIG. 8
wire T1 = (S & FandGandH) | (FandGandH & k_i); // Intermediate net
wire N6 = ~(~F | T1);
wire N7 = G | NFandNGandNH;
wire N8 = H;
wire N9 = T1 | FxorGandNH;
assign data_o[6] = N6 ^ COMPLS4;
assign data_o[7] = N7 ^ COMPLS4;
assign data_o[8] = N8 ^ COMPLS4;
assign data_o[9] = N9 ^ COMPLS4;
// Not in patent
assign kerr_o = k_i & ~(NAandNB & CandD & E) & ~(FandGandH & E & L31) ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DFXTP_FUNCTIONAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p/sky130_fd_sc_lp__udp_dff_p.v"
`celldefine
module sky130_fd_sc_lp__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; long long data[4 * 150005], lazy[4 * 150005], ret; int ll, rr, n, m; void change(int t, long long d) { data[t] = lazy[t] = d; } void down(int t) { if (lazy[t]) { change(t * 2, lazy[t]); change(t * 2 + 1, lazy[t]); lazy[t] = 0; } } void modify(int t, int l, int r) { if (ll <= l && r <= rr) { change(t, ret); return; } int mid = (l + r) >> 1; down(t); if (ll <= mid) modify(t * 2, l, mid); if (rr > mid) modify(t * 2 + 1, mid + 1, r); data[t] = max(data[t * 2], data[t * 2 + 1]); } void query(int t, int l, int r) { if (ll <= l && r <= rr) { ret = max(ret, data[t]); return; } int mid = (l + r) >> 1; down(t); if (ll <= mid) query(t * 2, l, mid); if (rr > mid) query(t * 2 + 1, mid + 1, r); } void build(int t, int l, int r) { if (l == r) { scanf( %I64d , &data[t]); return; } int mid = (l + r) >> 1; build(t * 2, l, mid); build(t * 2 + 1, mid + 1, r); data[t] = max(data[t * 2], data[t * 2 + 1]); } int main() { scanf( %d , &n); build(1, 1, n); scanf( %d , &m); while (m--) { int h; scanf( %d%d , &rr, &h); ll = 1; ret = 0; query(1, 1, n); printf( %I64d n , ret); ret += h; modify(1, 1, n); } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07/07/2016 09:24:55 AM
// Design Name:
// Module Name: Deslinealizador
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DESLINEALIZADOR#(parameter P = 32)(
input wire CLK, //system clock
input wire [P-1:0] T, //VALOR DEL ARGUMENTO DEL EXPONENCIAL QUE SE DESEA CALCULAR
input wire RST_EX, //system reset
input wire Begin_FSM_EX, //INICIAL EL CALCULO
output wire ACK_EX, //INDICA QUE EL CALCULO FUE REALIZADO
output wire ACK_SUMX,
output wire ACK_SUMY,
output wire ACK_SUMZ,
output wire O_FX, //BANDERA DE OVER FLOW X
output wire O_FY, //BANDERA DE OVER FLOW Y
output wire O_FZ, //BANDERA DE OVER FLOW Z
output wire U_FX, //BANDERA DE UNDER FLOW X
output wire U_FY, //BANDERA DE UNDER FLOW Y
output wire U_FZ, //BANDERA DE UNDER FLOW Z
output wire [P-1:0] RESULT //RESULTADO FINAL
);
wire [4:0] CONT_ITERA;
wire RST;
wire MS_1;
wire EN_REG3;
//wire EN_REGMult;
wire ADD_SUBT;
wire Begin_SUMX;
wire Begin_SUMY;
wire Begin_SUMZ;
wire EN_REG1X;
wire EN_REG1Y;
wire EN_REG1Z;
wire MS_2;
wire EN_REG2;
wire CLK_CDIR;
wire EN_REG2XYZ;
// wire ACK_SUMX;
// wire ACK_SUMY;
// wire ACK_SUMZ;
// wire ACK_MULTX,
// wire ACK_MULTY,
wire EN_MS1;
wire EN_MS2;
wire EN_ADDSUBT;
wire MS_1_reg;
wire MS_2_reg;
wire ADD_SUBT_reg;
assign BeginSUMX = Begin_SUMX;
assign BeginSUMY = Begin_SUMY;
assign BeginSUMZ = Begin_SUMZ;
Coprocesador_CORDIC C_CORDIC_EX (
.T(T),
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST),
.MS_1(MS_1_reg),
.EN_REG3(EN_REG3),
//.EN_REGMult(EN_REGMult),
.ADD_SUBT(ADD_SUBT_reg),
.Begin_SUMX(Begin_SUMX),
.Begin_SUMY(Begin_SUMY),
.Begin_SUMZ(Begin_SUMZ),
.EN_REG1X(EN_REG1X),
.EN_REG1Y(EN_REG1Y),
.EN_REG1Z(EN_REG1Z),
.MS_2(MS_2_reg),
.EN_REG2(EN_REG2),
.CLK_CDIR(CLK_CDIR),
.EN_REG2XYZ(EN_REG2XYZ),
.ACK_SUMX(ACK_SUMX),
.ACK_SUMY(ACK_SUMY),
.ACK_SUMZ(ACK_SUMZ),
.O_FX(O_FX),
.U_FX(U_FX),
.O_FY(O_FY),
.U_FY(U_FY),
.O_FZ(O_FZ),
.U_FZ(U_FZ),
.RESULT(RESULT),
.CONT_ITERA(CONT_ITERA)
);
FF_D #(.P(1)) REG_ADDSUBTL( //#(.P(1))
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_ADDSUBT), //ENABLE
.D(ADD_SUBT), //ENTRADA
.Q(ADD_SUBT_reg) //SALIDA
);
FF_D #(.P(1)) REG_MS_1(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS1), //ENABLE
.D(MS_1), //ENTRADA
.Q(MS_1_reg) //SALIDA
);
FF_D #(.P(1)) REG_MS_2(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS2), //ENABLE
.D(MS_2), //ENTRADA
.Q(MS_2_reg) //SALIDA
);
FSM_C_CORDIC M_E_EX (
.CLK(CLK), //RELOJ DEL SISTEMA
.RST_EX(RST_EX), //system reset
.ACK_ADD_SUBTX(ACK_SUMX),
.ACK_ADD_SUBTY(ACK_SUMY),
.ACK_ADD_SUBTZ(ACK_SUMZ),
.Begin_FSM_EX(Begin_FSM_EX),
.CONT_ITER(CONT_ITERA),
.RST(RST),
.MS_1(MS_1),
.EN_REG3(EN_REG3),
//.EN_REGMult(EN_REGMult),
.ADD_SUBT(ADD_SUBT),
.Begin_SUMX(Begin_SUMX),
.Begin_SUMY(Begin_SUMY),
.Begin_SUMZ(Begin_SUMZ),
.EN_REG1X(EN_REG1X),
.EN_REG1Y(EN_REG1Y),
.EN_REG1Z(EN_REG1Z),
.MS_2(MS_2),
.EN_REG2(EN_REG2),
.CLK_CDIR(CLK_CDIR),
.EN_REG2XYZ(EN_REG2XYZ),
.ACK_EX(ACK_EX),
.EN_ADDSUBT(EN_ADDSUBT),
.EN_MS1(EN_MS1),
.EN_MS2(EN_MS2)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void bringToTen(int &k, int &rating, vector<int> &bucket) { for (int i = 9; i > 0; i--) { int x = 0; while (x < 100) { int h = min(k / (10 - i), bucket[x + i]); k -= h * (10 - i); bucket[x + 10] += h; rating += h; bucket[x + i] -= h; x += 10; } } } void addToTen(int &k, int &rating, vector<int> &bucket) { int x = 0; while (x < 100) { int h = min(k / 10, bucket[x]); rating += h; bucket[x + 10] += h; bucket[x] -= h; k -= 10 * h; x += 10; } } int main(void) { int n, k, rating = 0, h; scanf( %d %d , &n, &k); vector<int> a(n); for (int(i) = (0); i < (n); i++) scanf( %d , &a[i]); vector<int> num(101, 0); for (int(i) = (0); i < (n); i++) { num[a[i]]++; rating += a[i] / 10; } bringToTen(k, rating, num); addToTen(k, rating, num); printf( %d n , rating); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V
`define SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__and3b (
X ,
A_N,
B ,
C
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND3B_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int size = 1e5 + 7; long long a[size], ans = 2e9, res, val, n, k, i; int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; for (i = 0; i < n; i++) { cin >> a[i]; if (!i) val = a[i] % k; else if (val != a[i] % k) { cout << -1; return 0; } ans = min(a[i], ans); } for (i = 0; i < n; i++) { val = a[i] - ans; res += val / k; } cout << res; return 0; } |
`timescale 1ns/10ps
module pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(1),
.output_clock_frequency0("40.0 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.rst (rst),
.refclk (refclk)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[3], b[3]; int main() { int n, m; ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> m; for (int i = 1; i <= n; ++i) { int c; cin >> c; a[c % 2]++; } for (int j = 1; j <= m; ++j) { int c; cin >> c; b[c % 2]++; } cout << min(a[1], b[0]) + min(b[1], a[0]) << n ; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: top_nto1_ddr_diff_rx.v
// / / Date Last Modified: November 5 2009
// /___/ /\ Date Created: June 1 2009
// \ \ / \
// \___\/\___\
//
//Device: Spartan 6
//Purpose: Example differential input receiver for DDR clock and data using 2 x BUFIO2
// Serdes factor and number of data lines are set by constants in the code
//Reference:
//
//Revision History:
// Rev 1.0 - First created (nicks)
//
///////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
//
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to you
// by Xilinx, and to the maximum extent permitted by applicable law:
// (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
// AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
// FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
// or tort, including negligence, or under any other theory of liability) for any loss or damage
// of any kind or nature related to, arising under or in connection with these materials,
// including for any direct, or any indirect, special, incidental, or consequential loss
// or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
// as a result of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// Critical Applications:
//
// Xilinx products are not designed or intended to be fail-safe, or for use in any application
// requiring fail-safe performance, such as life-support or safety devices or systems,
// Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
// or any other applications that could lead to death, personal injury, or severe property or
// environmental damage (individually and collectively, "Critical Applications"). Customer assumes
// the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
// to applicable laws and regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
module top_nto1_ddr_diff_rx (
input reset, // reset (active high)
input [7:0] datain_p, datain_n, // lvds data inputs
input clkin_p, clkin_n, // lvds clock input
output [63:0] dummy_out) ; // dummy outputs
// Parameters for serdes factor and number of IO pins
parameter integer S = 8 ; // Set the serdes factor to 8
parameter integer D = 8 ; // Set the number of inputs and outputs
parameter integer DS = (D*S)-1 ; // Used for bus widths = serdes factor * number of inputs - 1
wire rst ;
wire [DS:0] rxd ; // Data from serdeses
reg [DS:0] rxr ; // Registered Data from serdeses
reg state ;
reg bslip ;
reg [3:0] count ;
assign rst = reset ; // active high reset pin
assign dummy_out = rxr ;
// Clock Input. Generate ioclocks via BUFIO2
serdes_1_to_n_clk_ddr_s8_diff #(
.S (S),
.DIFF_TERM ("TRUE")) // Enable or disable diff termination
inst_clkin (
.clkin_p (clkin_p),
.clkin_n (clkin_n),
.rxioclkp (rxioclkp),
.rxioclkn (rxioclkn),
.rx_serdesstrobe (rx_serdesstrobe),
.rx_bufg_x1 (rx_bufg_x1));
// Data Inputs
serdes_1_to_n_data_ddr_s8_diff #(
.S (S),
.D (D),
.DIFF_TERM ("TRUE")) // Enable or disable diff termination
inst_datain (
.use_phase_detector (1'b1), // '1' enables the phase detector logic
.datain_p (datain_p),
.datain_n (datain_n),
.rxioclkp (rxioclkp),
.rxioclkn (rxioclkn),
.rxserdesstrobe (rx_serdesstrobe),
.gclk (rx_bufg_x1),
.bitslip (bslip),
.reset (rst),
.data_out (rxd),
.debug_in (2'b00),
.debug ());
always @ (posedge rx_bufg_x1 or posedge rst) // example bitslip logic, if required
begin
if (rst == 1'b1) begin
state <= 0 ;
bslip <= 1'b0 ;
count <= 4'b0000 ;
end
else begin
if (state == 0) begin
if (rxd[63:60] != 4'h3) begin
bslip <= 1'b1 ; // bitslip needed
state <= 1 ;
count <= 4'b0000 ;
end
end
else if (state == 1) begin
bslip <= 1'b0 ; // bitslip low
count <= count + 4'b0001 ;
if (count == 4'b1111) begin
state <= 0;
end
end
end
end
always @ (posedge rx_bufg_x1) // process received data
begin
rxr <= rxd ;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD1_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DLYGATE4SD1_BEHAVIORAL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__dlygate4sd1 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD1_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; using ll = long long; using db = double; using pii = pair<int, int>; using vi = vector<int>; const int N = 1e5 + 100; int n, d[N], f[N][2], ans; vi G[N]; void dfs(int x, int fz) { f[x][0] = 0, f[x][1] = 1; for (int y : G[x]) if (y != fz) { dfs(y, x); ans = max({ans, f[x][0] + f[y][0], f[x][0] + f[y][1], f[x][1] + f[y][0]}); f[x][0] = max({f[x][0], f[y][0] + d[x] - 2, f[y][1] + d[x] - 2}); f[x][1] = max({f[x][1], f[y][0] + 1}); } ans = max(ans, f[x][1]); } signed main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int x, y; scanf( %d %d , &x, &y); G[x].push_back(y), G[y].push_back(x); d[x]++, d[y]++; } dfs(1, 0); printf( %d n , ans); fprintf(stderr, time=%.4f n , (db)clock() / CLOCKS_PER_SEC); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 15; vector<int> g[N]; int n, m, b[N], r[N], a[N], res; void dfs(int v, int pa) { if (a[v] == 1) r[v]++; else if (a[v] == 2) b[v]++; for (int i : g[v]) { if (i == pa) continue; dfs(i, v); b[v] += b[i]; r[v] += r[i]; } } int main() { ios::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n - 1; i++) { int x, y; cin >> x >> y; x--, y--; g[x].push_back(y); g[y].push_back(x); } dfs(0, -1); for (int i = 1; i < n; i++) { if (b[i] && r[i]) continue; int blue = b[0] - b[i], red = r[0] - r[i]; if (((!blue) && red) || (blue && (!red))) { res++; } } cout << res << endl; } |
#include <bits/stdc++.h> using namespace std; template <class T> ostream& operator<<(ostream& os, vector<T> V) { os << [ ; for (auto v : V) os << v << ; os << ] ; return os; } template <class T> ostream& operator<<(ostream& os, set<T> second) { os << { ; for (auto s : second) os << s << ; return os << } ; } template <class T> ostream& operator<<(ostream& os, multiset<T> second) { os << { ; for (auto s : second) os << s << ; return os << } ; } template <class L, class R> ostream& operator<<(ostream& os, pair<L, R> P) { return os << ( << P.first << , << P.second << ) ; } template <class L, class R> ostream& operator<<(ostream& os, map<L, R> M) { os << { ; for (auto m : M) os << ( << m.first << : << m.second << ) ; return os << } ; } template <class L, class R> ostream& operator<<(ostream& os, unordered_map<L, R> M) { os << { ; for (auto m : M) os << ( << m.first << : << m.second << ) ; return os << } ; } const long long N = 2010, M = 1e9 + 7; long long n, a[N][N], dp1[N][N], dp2[N][N], dp3[N][N]; void solve() { cin >> n; for (long long i = (0); i <= n - 1; i++) for (long long j = (0); j <= n - 1; j++) cin >> a[i][j]; for (long long i = (0); i <= n - 1; i++) dp1[i][0] = a[i][0], dp1[0][i] = a[0][i], dp2[i][n - 1] = a[i][n - 1], dp2[0][n - i - 1] = a[0][n - i - 1]; for (long long i = (1); i <= n - 1; i++) for (long long j = (1); j <= n - 1; j++) dp1[i][j] = a[i][j] + dp1[i - 1][j - 1]; for (long long i = (1); i <= n - 1; i++) for (long long j = (0); j <= n - 2; j++) dp2[i][j] = a[i][j] + dp2[i - 1][j + 1]; for (long long i = (0); i <= n - 1; i++) for (long long j = (0); j <= n - 1; j++) { long long i1 = i + min(n - i - 1, n - j - 1); long long j1 = j + min(n - i - 1, n - j - 1); long long i2 = i + min(n - i - 1, j); long long j2 = j - min(n - i - 1, j); dp3[i][j] = dp1[i1][j1] + dp2[i2][j2] - a[i][j]; } long long ans1 = LLONG_MIN, ans2 = LLONG_MIN, posx1, posy1, posx2, posy2; for (long long i = (0); i <= n - 1; i++) for (long long j = (0); j <= n - 1; j++) { if ((i + j) % 2 == 0 && dp3[i][j] > ans1) { ans1 = max(ans1, dp3[i][j]); posx1 = i + 1; posy1 = j + 1; } else if ((i + j) % 2 == 1 && dp3[i][j] > ans2) { ans2 = max(ans2, dp3[i][j]); posx2 = i + 1; posy2 = j + 1; } } cout << ans1 + ans2 << n ; cout << posx1 << << posy1 << << posx2 << << posy2 << n ; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(0); solve(); return 0; } |
`default_nettype none
package testcase_pkg;
typedef int unsigned uint;
localparam uint SIZE = 8;
typedef enum {ENUM1, ENUM2} enum_t;
endpackage
module testcase_top
(
input testcase_pkg::enum_t top_enum,
input logic [testcase_pkg::SIZE-1:0] top_in,
output logic [testcase_pkg::SIZE-1:0] top_out
);
import testcase_pkg::*;
//enum_t sub_enum; // is not declared by AUTOWIRE
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
testcase_pkg::enum_t sub_enum; // From testcase_sub1 of testcase_sub1.v
logic [testcase_pkg::SIZE-1:0] sub_in; // From testcase_sub1 of testcase_sub1.v
logic [testcase_pkg::SIZE-1:0] sub_out; // From testcase_sub2 of testcase_sub2.v
// End of automatics
assign top_out = sub_out;
testcase_sub1 testcase_sub1 (.*,
// Outputs
.sub_enum (sub_enum), // Implicit .*
.sub_in (sub_in[testcase_pkg::SIZE-1:0]), // Implicit .*
// Inputs
.top_enum (top_enum)); // Implicit .*
testcase_sub2 testcase_sub2 (.*,
// Outputs
.sub_out (sub_out[testcase_pkg::SIZE-1:0]), // Implicit .*
// Inputs
.sub_enum (sub_enum), // Implicit .*
.sub_in (sub_in[testcase_pkg::SIZE-1:0])); // Implicit .*
endmodule
module testcase_sub1
(
input testcase_pkg::enum_t top_enum,
output testcase_pkg::enum_t sub_enum,
output logic [testcase_pkg::SIZE-1:0] sub_in
);
import testcase_pkg::*;
assign sub_enum = top_enum;
assign sub_in = '1;
endmodule
module testcase_sub2
(
input testcase_pkg::enum_t sub_enum,
input logic [testcase_pkg::SIZE-1:0] sub_in,
output logic [testcase_pkg::SIZE-1:0] sub_out
);
import testcase_pkg::*;
assign sub_out = (sub_enum==ENUM1) ? ~sub_in : sub_in;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// verilog-auto-star-save: t
// End:
|
module main;
wire out;
reg [1:0] A, B;
ge2 dut(.out(out), .A(A), .B(B));
initial begin
A = 0;
B = 0;
#1 $display("%b >= %b: %b", A, B, out);
B = 1;
#1 $display("%b >= %b: %b", A, B, out);
B = 2;
#1 $display("%b >= %b: %b", A, B, out);
B = 3;
#1 $display("%b >= %b: %b", A, B, out);
A = 1;
B = 0;
#1 $display("%b >= %b: %b", A, B, out);
B = 1;
#1 $display("%b >= %b: %b", A, B, out);
B = 2;
#1 $display("%b >= %b: %b", A, B, out);
B = 3;
#1 $display("%b >= %b: %b", A, B, out);
A = 2;
B = 0;
#1 $display("%b >= %b: %b", A, B, out);
B = 1;
#1 $display("%b >= %b: %b", A, B, out);
B = 2;
#1 $display("%b >= %b: %b", A, B, out);
B = 3;
#1 $display("%b >= %b: %b", A, B, out);
A = 3;
B = 0;
#1 $display("%b >= %b: %b", A, B, out);
B = 1;
#1 $display("%b >= %b: %b", A, B, out);
B = 2;
#1 $display("%b >= %b: %b", A, B, out);
B = 3;
#1 $display("%b >= %b: %b", A, B, out);
end // initial begin
endmodule // main
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BAI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O21BAI_BEHAVIORAL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, b, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BAI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2B_TB_V
`define SKY130_FD_SC_HDLL__AND2B_TB_V
/**
* and2b: 2-input AND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and2b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A_N = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A_N = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A_N = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A_N = 1'bx;
end
sky130_fd_sc_hdll__and2b dut (.A_N(A_N), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2B_TB_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; const unsigned long long base = 311; unsigned long long TH[maxn][3], L[3], P[maxn]; int Sol, lona, lonb; void calc_Hash(string& a, int id) { int lon = L[id]; for (int i = (1); i <= (lon); i += (1)) { TH[i][id] = TH[i - 1][id] * base + (unsigned long long)(a[i] - 0 ); } return; } void calc_pot(int N) { P[0] = 1; for (int i = (1); i <= (N); i += (1)) { P[i] = P[i - 1] * base; } return; } bool completa(int tam, int id) { int lon = L[id]; unsigned long long H = TH[tam][1]; bool flag = true; for (int i = (tam); i <= (lon); i += (tam)) { if (TH[i][id] - TH[i - tam][id] * P[tam] != H) { flag = false; break; } } return flag; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); string A, B; cin >> A >> B; lona = A.size(); lonb = B.size(); L[1] = lona; L[2] = lonb; A = + A; B = + B; calc_pot(((lona) > (lonb) ? (lona) : (lonb))); calc_Hash(A, 1); calc_Hash(B, 2); int l = ((lona) < (lonb) ? (lona) : (lonb)); for (int i = (1); i <= (l); i += (1)) { if (!(lona % i) && !(lonb % i)) { if (completa(i, 1) && completa(i, 2)) { Sol++; } } } cout << Sol << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int M = 400005; int read() { int x = 0, flag = 1; char c; while ((c = getchar()) < 0 || c > 9 ) if (c == - ) flag = -1; while (c >= 0 && c <= 9 ) x = (x << 3) + (x << 1) + (c ^ 48), c = getchar(); return x * flag; } int n, m, a[M], b[M], s[M], f[M]; vector<int> t; void manacher() { for (int i = 1; i <= n; i++) s[i * 2] = b[i]; for (int i = 1; i <= n; i++) s[i * 2 - 1] = -1; s[2 * n + 1] = -1; int r = 0, c = 0; for (int i = 1; i <= 2 * n + 1; i++) { f[i] = r > i ? min(r - i + 1, f[2 * c - i]) : 1; while (i + f[i] <= 2 * n + 1 && i - f[i] >= 1 && s[i - f[i]] == s[i + f[i]]) f[i]++; if (i + f[i] - 1 > r) { r = i + f[i] - 1; c = i; } } } int chk(int l, int r) { if (l >= r) return 1; int p = l + r; int ll = p - f[p] + 1, rr = p + f[p] - 1; return ll <= 2 * l && rr >= 2 * r; } int main() { n = read(); m = read(); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 1; i <= n; i++) b[i] = a[i] - a[i - 1]; if (n == 1) { printf( 1 n%d n , (a[1] + a[1]) % m); return 0; } manacher(); for (int i = 1; i < n; i++) { if ((a[1] + a[i]) % m == (a[i + 1] + a[n]) % m) if (chk(2, i) && chk(i + 2, n)) t.push_back((a[1] + a[i]) % m); } if (chk(2, n)) t.push_back((a[1] + a[n]) % m); sort(t.begin(), t.end()); printf( %d n , t.size()); for (int i = 0; i < t.size(); i++) printf( %d , t[i]); } |
/*******************************************************************************
*
* NetFPGA-10G http://www.netfpga.org
*
* File:
* generate_stream.v
*
* Library:
* hw/osnt/pcores/osnt_10g_interface_v1_11_a
*
* Module:
* rx_queue
*
* Author:
* Mario Ruiz
*
*
* Copyright (C) 2015 - HPCN-UAM High Performance Computing and Networking
*
* Licence:
* This file is part of the HPCN-NetFPGA 10G development base package.
*
* This file is free code: you can redistribute it and/or modify it under
* the terms of the GNU Lesser General Public License version 2.0 as
* published by the Free Software Foundation.
*
* This package is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with the NetFPGA source package. If not, see
* http://www.gnu.org/licenses/.
*
*/
#(
parameter AXI_CALCULATIONS_DATA_WIDTH = 160,
parameter C_DEFAULT_SRC_PORT = 0
)
(
input clk,
input reset,
input [AXI_CALCULATIONS_DATA_WIDTH-1:0] data,
input valid,
output reg ack,
// AXI stream for hardware calculations
output reg [AXI_CALCULATIONS_DATA_WIDTH-1:0] tdata_calculations,
output reg [(AXI_CALCULATIONS_DATA_WIDTH/8)-1:0] tstrb_calculations,
output reg tvalid_calculations,
output reg tlast_calculations,
input tready_calculations
);
localparam WAIT=0;
localparam SND=1;
reg wr_en,rd_en;
wire fifo_empty,fifo_info_empty,fifo_rx_empty,fifo_tx_empty;
wire [63:0] rx_1,rx,pkt_info;
reg state;
reg [1:0] state_wr_fifo;
localparam WAIT_DATA=0;
localparam SND_ACK=1;
localparam WRITE=2;
wire [35:0] CONTROL0;
generate
begin
if(C_DEFAULT_SRC_PORT == 8'h10)
begin
chipscope_icon ICON (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
chipscope_ila ILA(
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(clk), // IN
.TRIG0(tdata_calculations), // IN BUS [160:0]
.TRIG1(tstrb_calculations), // IN BUS [20:0]
.TRIG2(tvalid_calculations), // IN BUS
.TRIG3(tlast_calculations), // IN BUS
.TRIG4(tready_calculations), // OUT BUS
.TRIG5(data), // IN BUS [159:0]
.TRIG6(valid), // IN BUS
.TRIG7(ack) // OUT BUS
);
end
end
endgenerate
/* save data in fifo */
always @(posedge clk) begin
if (reset == 1'b1) begin
wr_en <= 1'b0;
state_wr_fifo <= WAIT_DATA;
ack <=1'b0;
end
case (state_wr_fifo)
WAIT_DATA: begin
wr_en <= 1'b0;
if(valid==1'b1) begin
state_wr_fifo <= SND_ACK;
ack <=1'b1;
end
end
SND_ACK: begin
if(valid==1'b0) begin
state_wr_fifo <= WRITE;
ack <=1'b0;
end
end
WRITE: begin
wr_en <= 1'b1;
state_wr_fifo <= WAIT_DATA;
end
default: begin
wr_en <= 1'b0;
state_wr_fifo <= WAIT_DATA;
end
endcase
end
/* write data in stream */
assign fifo_empty = fifo_info_empty || fifo_rx_empty || fifo_tx_empty;
always @(posedge clk) begin
if (reset==1'b1) begin
state <= WAIT;
rd_en <= 1'b0;
tvalid_calculations <= 1'b0;
tlast_calculations <= 1'b0;
end
case (state)
WAIT: begin
tdata_calculations <= {160{1'b0}};
tstrb_calculations <= {20{1'b0}};
tvalid_calculations <= 1'b0;
tlast_calculations <= 1'b0;
if (fifo_empty == 1'b0 && tready_calculations==1'b1) begin
rd_en <= 1'b1;
state <= SND;
end
end
SND: begin
//if (tready_calculations==1'b1) begin
tdata_calculations <= {pkt_info[31:0],rx_1,rx};
tstrb_calculations <= {20{1'b1}};
tvalid_calculations <= 1'b1;
tlast_calculations <= 1'b1;
state <= WAIT;
//end
rd_en <= 1'b0;
end
default:
begin
tdata_calculations <= {160{1'b0}};
tstrb_calculations <= {20{1'b0}};
tvalid_calculations <= 1'b0;
tlast_calculations <= 1'b0;
rd_en <= 1'b0;
state <= WAIT;
end
endcase
end
// Instantiate clock domain crossing FIFO
FIFO36_72 #(
.SIM_MODE("FAST"),
.ALMOST_FULL_OFFSET(9'd300), // > Ethernet MAX length / 6 = 1516Byte/6 = 252
.ALMOST_EMPTY_OFFSET(9'hA),
.DO_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.EN_SYN("FALSE"),
.FIRST_WORD_FALL_THROUGH("TRUE")
) info_fifo (
.ALMOSTEMPTY(),
.ALMOSTFULL(),
.DBITERR(),
.DO(pkt_info),
.DOP(),
.ECCPARITY(),
.EMPTY(fifo_info_empty),
.FULL(),
.RDCOUNT(),
.RDERR(),
.SBITERR(),
.WRCOUNT(),
.WRERR(),
.DI({{32 {1'b0}} , data[159:128]}),
.DIP(8'h0000FFFF),
.RDCLK(clk),
.RDEN(rd_en),
.RST(reset),
.WRCLK(clk),
.WREN(wr_en)
);
FIFO36_72 #(
.SIM_MODE("FAST"),
.ALMOST_FULL_OFFSET(9'd300), // > Ethernet MAX length / 6 = 1516Byte/6 = 252
.ALMOST_EMPTY_OFFSET(9'hA),
.DO_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.EN_SYN("FALSE"),
.FIRST_WORD_FALL_THROUGH("TRUE")
) rx_fifo (
.ALMOSTEMPTY(),
.ALMOSTFULL(),
.DBITERR(),
.DO(rx_1),
.DOP(),
.ECCPARITY(),
.EMPTY(fifo_tx_empty),
.FULL(),
.RDCOUNT(),
.RDERR(),
.SBITERR(),
.WRCOUNT(),
.WRERR(),
.DI(data[127:64]),
.DIP(8'hFFFFFFFF),
.RDCLK(clk),
.RDEN(rd_en),
.RST(reset),
.WRCLK(clk),
.WREN(wr_en)
);
FIFO36_72 #(
.SIM_MODE("FAST"),
.ALMOST_FULL_OFFSET(9'd300), // > Ethernet MAX length / 6 = 1516Byte/6 = 252
.ALMOST_EMPTY_OFFSET(9'hA),
.DO_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.EN_SYN("FALSE"),
.FIRST_WORD_FALL_THROUGH("TRUE")
) rx_1_fifo (
.ALMOSTEMPTY(),
.ALMOSTFULL(),
.DBITERR(),
.DO(rx),
.DOP(),
.ECCPARITY(),
.EMPTY(fifo_rx_empty),
.FULL(),
.RDCOUNT(),
.RDERR(),
.SBITERR(),
.WRCOUNT(),
.WRERR(),
.DI(data[63:0]),
.DIP(8'hFFFFFFFF),
.RDCLK(clk),
.RDEN(rd_en),
.RST(reset),
.WRCLK(clk),
.WREN(wr_en)
);
endmodule |
//
//////////////////////////////////////////////////////////////////////////////////
// Copyright © 2010, Xilinx, Inc.
// This file contains confidential and proprietary information of Xilinx, Inc. and is
// protected under U.S. and international copyright and other intellectual property laws.
//////////////////////////////////////////////////////////////////////////////////
//
// Disclaimer:
// This disclaimer is not a license and does not grant any rights to the materials
// distributed herewith. Except as otherwise provided in a valid license issued to
// you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
// MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
// DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
// INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
// OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
// (whether in contract or tort, including negligence, or under any other theory
// of liability) for any loss or damage of any kind or nature related to, arising
// under or in connection with these materials, including for any direct, or any
// indirect, special, incidental, or consequential loss or damage (including loss
// of data, profits, goodwill, or any type of loss or damage suffered as a result
// of any action brought by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-safe, or for use in any
// application requiring fail-safe performance, such as life-support or safety
// devices or systems, Class III medical devices, nuclear facilities, applications
// related to the deployment of airbags, or any other applications that could lead
// to death, personal injury, or severe property or environmental damage
// (individually and collectively, "Critical Applications"). Customer assumes the
// sole risk and liability of any use of Xilinx products in Critical Applications,
// subject only to applicable laws and regulations governing limitations on product
// liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//////////////////////////////////////////////////////////////////////////////////
//
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 2.10
// \ \ Filename: bbfifo_16x8.v
// / / Date Last Modified: March 19 2010
// /___/ /\ Date Created: October 14 2002
// \ \ / \
// \___\/\___\
//
// Device: Xilinx
// Purpose: 'Bucket Brigade' FIFO, 16 deep, 8-bit data
//
//
// This module was made for use with Spartan-3 Generation Devices and is also ideally
// suited for use with Virtex-II(PRO) and Virtex-4 devices. Will also work in Virtex-5,
// Virtex-6 and Spartan-6 devices but it is not specifically optimised for these
// architectures.
//
//
// Contact: e-mail
//
//
// Revision History:
// Rev 1.00 - kc - Start of design entry in VHDL, October 14 2002.
// Rev 1.01 - sus - Converted to verilog, August 4 2004.
// Rev 1.02 - njs - Synplicity attributes added, September 6 2004.
// Rev 1.03 - njs - defparam values corrected, December 1 2005.
// Rev 1.04 - njs - INIT values specified using Verilog 2001 format, July 6 2005.
// Rev 1.03 - kc - Minor format changes, January 17 2007.
// Rev 2.10 - njs - March 19 2010.
// The Verilog coding style adjusted to be compatible with XST provided
// as part of the ISE v12.1i tools when targeting Spartan-6 and Virtex-6
// devices. No functional changes.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Format of this file.
//
// The module defines the implementation of the logic using Xilinx primitives.
// These ensure predictable synthesis results and maximise the density of the
// implementation. The Unisim Library is used to define Xilinx primitives.
// The source can be viewed at %XILINX%\verilog\src\unisims.
//
//////////////////////////////////////////////////////////////////////////////////
//
`timescale 1 ps / 1ps
module bbfifo_16x8(
input [7:0] data_in,
output [7:0] data_out,
input reset,
input write,
input read,
output full,
output half_full,
output data_present,
input clk);
//
//////////////////////////////////////////////////////////////////////////////////
//
// Signals used in BBFIFO_16x8
//
//////////////////////////////////////////////////////////////////////////////////
//
wire [3:0] pointer;
wire [3:0] next_count;
wire [3:0] half_count;
wire [2:0] count_carry;
wire pointer_zero;
wire pointer_full;
wire decode_data_present;
wire data_present_int;
wire valid_write;
//
//////////////////////////////////////////////////////////////////////////////////
//
// Start of BBFIFO_16x8 circuit description
//
//////////////////////////////////////////////////////////////////////////////////
//
// SRL16E data storage
genvar i ;
generate
for (i = 0; i <= 7; i = i + 1)
begin : data_width_loop
SRL16E #(
.INIT (16'h0000))
data_srl (
.D (data_in[i]),
.CE (valid_write),
.CLK (clk),
.A0 (pointer[0]),
.A1 (pointer[1]),
.A2 (pointer[2]),
.A3 (pointer[3]),
.Q (data_out[i])) ;
end
endgenerate
// 4-bit counter to act as data pointer
// Counter is clock enabled by 'data_present'
// Counter will be reset when 'reset' is active
// Counter will increment when 'valid_write' is active
generate
for (i = 0; i <= 3; i = i + 1)
begin : count_width_loop
FDRE register_bit(
.D (next_count[i]),
.Q (pointer[i]),
.CE (data_present_int),
.R (reset),
.C (clk));
LUT4 #(
.INIT (16'h6606))
count_lut(
.I0 (pointer[i]),
.I1 (read),
.I2 (pointer_zero),
.I3 (write),
.O (half_count[i])) ;
if (i == 0) begin : lsb_count
MUXCY count_muxcy_0(
.DI (pointer[i]),
.CI (valid_write),
.S (half_count[i]),
.O (count_carry[i]) );
XORCY count_xor_0(
.LI (half_count[i]),
.CI (valid_write),
.O (next_count[i]));
end
if (i > 0 && i < 3) begin : mid_count
MUXCY count_muxcy (
.DI (pointer[i]),
.CI (count_carry[i-1]),
.S (half_count[i]),
.O (count_carry[i]));
XORCY count_xor(
.LI (half_count[i]),
.CI (count_carry[i-1]),
.O (next_count[i]));
end
if (i == 3) begin : msb_count
XORCY count_xor(
.LI (half_count[i]),
.CI (count_carry[i-1]),
.O (next_count[i]));
end
end
endgenerate
// Detect when pointer is zero and maximum
LUT4 #(
.INIT (16'h0001))
zero_lut(
.I0 (pointer[0]),
.I1 (pointer[1]),
.I2 (pointer[2]),
.I3 (pointer[3]),
.O (pointer_zero)) ;
LUT4 #(
.INIT (16'h8000))
full_lut(
.I0 (pointer[0]),
.I1 (pointer[1]),
.I2 (pointer[2]),
.I3 (pointer[3]),
.O (pointer_full)) ;
// Data Present status
LUT4 #(
.INIT (16'hBFA0))
dp_lut(
.I0 (write),
.I1 (read),
.I2 (pointer_zero),
.I3 (data_present_int),
.O (decode_data_present)) ;
FDR dp_flop(
.D (decode_data_present),
.Q (data_present_int),
.R (reset),
.C (clk));
// Valid write wire
LUT3 #(
.INIT (8'hC4))
valid_lut(
.I0 (pointer_full),
.I1 (write),
.I2 (read),
.O (valid_write)) ;
// assign internal wires to outputs
assign full = pointer_full;
assign half_full = pointer[3];
assign data_present = data_present_int;
endmodule
//
//////////////////////////////////////////////////////////////////////////////////
//
// END OF FILE BBFIFO_16x8.V
//
//////////////////////////////////////////////////////////////////////////////////
//
|
// MBT 11/26/2014
//
// bsg_nonsynth_fsb_node_trace_replay
//
// note: generally it is better to use
// bsg_fsb_node_trace_replay
// than this module, because 1)
// it is synthesizeable, and 2)
// it may have races (see fixme)
//
// trace format
//
//
// 0: wait one cycle
// 1: send data
// 2: receive data
// 3: assert done_o; test complete.
// 4: end test; call $finish
`include "bsg_defines.v"
module bsg_nonsynth_fsb_node_trace_replay
#(parameter ring_width_p=80
, parameter `BSG_INV_PARAM(master_id_p)
, parameter `BSG_INV_PARAM(slave_id_p)
, parameter filename_p="trace.in"
)
(input clk_i
, input reset_i
, input en_i
// input channel
, input v_i
, input [ring_width_p-1:0] data_i
, output ready_o
// output channel
, output v_o
, output [ring_width_p-1:0] data_o
, input yumi_i
, output reg done_o
);
integer data_file, result_code;
//logic [7:0] read_line[255:0];
string read_line;
logic [ring_width_p-1:0] data_r;
logic [3:0] op_r;
logic eof;
logic next_line_r;
logic [$bits(byte) * 1000-1:0] filename_string;
string filename_path = filename_p;
initial
begin
// check for command line argument; otherwise use default.
if ($test$plusargs("fsb_trace"))
begin
if ($value$plusargs("fsb_trace=%s", filename_string))
begin
// make it prettier when we print it out
filename_path = string ' (filename_string);
$display("### %m using filename %s", filename_path);
end
end
data_file = $fopen(filename_path,"r");
if (data_file == 0)
begin
$display("############################################################################");
$display("### %m Failed to open file %s", filename_path);
$display("############################################################################");
$finish;
end
else
begin
$display("############################################################################");
$display("### %m OPENED FILE %s", filename_path);
$display("############################################################################");
end
next_line_r = 1;
eof = 0;
op_r = 0;
done_o = 0;
end
assign v_o = ~reset_i & ~eof & (op_r == 1) & en_i;
assign data_o = data_r;
wire receive_op = (op_r == 2);
// we absorb data if we are receiving or if we are done.
assign ready_o = receive_op | done_o;
// mbt fixme: I suspect this should actually
// be done on the negative edge of the clock
// to avoid races.
always @(posedge clk_i)
begin
if (!done_o)
begin
case (op_r)
0: next_line_r = 1;
1:
// send data
if (v_o & yumi_i)
begin
next_line_r = 1;
// for now we just print out the data
$display("### trace %s sent %h", filename_p, data_r);
end
2:
// receive and check
if (v_i)
begin
if (data_i != data_r)
begin
$display("############################################################################");
$display("### %m ");
$display("### ");
$display("### FAIL (trace mismatch) = %h", data_i);
$display("### expected = %h\n", data_r);
$display("############################################################################");
$finish();
end
else
begin
$display("### %m trace %s matched %h", filename_p, data_r);
next_line_r = 1;
end // else: !if(data_i != data_r)
end // if (v_i)
3:
begin
$display("############################################################################");
$display("###### done_o=1 (trace %s finished) (%m)", filename_p);
$display("############################################################################");
done_o = 1;
end
4:
begin
$display("############################################################################");
$display("###### DONE (trace %s finished; CALLING $finish) (%m)", filename_p);
$display("############################################################################");
$finish;
end
default:
$display("%m unknown op %x\n", op_r);
endcase
if (next_line_r)
begin
next_line_r = 0;
result_code = $fgets (read_line, data_file);
if (result_code == 0)
eof = 1;
// skip comments
while (!eof & ((read_line[0] == "\n") || (read_line[0] == " ") || (read_line[0] == "") || (read_line[0] == "#")))
begin
result_code = $fgets (read_line, data_file);
if (result_code == 0)
eof = 1;
end
if (eof)
begin
$display("############################################################################");
$display("###### End of Trace (trace %s finished) (%m)", filename_p);
$display("############################################################################");
end
else
begin
result_code = $sscanf(read_line, "%b\n", {op_r, data_r});
if (result_code == 0)
begin
$display("### error reading file %s:\n", read_line);
$finish();
end
end
end // if (next_line_r)
end // if (!done_o)
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_fsb_node_trace_replay)
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_debug_if.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core debug interface. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// ////
//// Created: 2001/12/02 ////
//// (See log for the revision history) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_debug_if.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.5 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.4 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.3 2001/12/19 08:40:03 mohor
// Warnings fixed (unused signals removed).
//
// Revision 1.2 2001/12/12 22:17:30 gorban
// some synthesis bugs fixed
//
// Revision 1.1 2001/12/04 21:14:16 gorban
// committed the debug interface file
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_debug_if (/*AUTOARG*/
// Outputs
wb_dat32_o,
// Inputs
wb_adr_i, ier, iir, fcr, mcr, lcr, msr,
lsr, rf_count, tf_count, tstate, rstate
) ;
input [`UART_ADDR_WIDTH-1:0] wb_adr_i;
output [31:0] wb_dat32_o;
input [3:0] ier;
input [3:0] iir;
input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
input [4:0] mcr;
input [7:0] lcr;
input [7:0] msr;
input [7:0] lsr;
input [`UART_FIFO_COUNTER_W-1:0] rf_count;
input [`UART_FIFO_COUNTER_W-1:0] tf_count;
input [2:0] tstate;
input [3:0] rstate;
wire [`UART_ADDR_WIDTH-1:0] wb_adr_i;
reg [31:0] wb_dat32_o;
always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr
or rf_count or rstate or tf_count or tstate or wb_adr_i)
case (wb_adr_i)
// 8 + 8 + 4 + 4 + 8
5'b01000: wb_dat32_o = {msr,lcr,iir,ier,lsr};
// 5 + 2 + 5 + 4 + 5 + 3
5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate};
default: wb_dat32_o = 0;
endcase // case(wb_adr_i)
endmodule // uart_debug_if
|
#include <bits/stdc++.h> using namespace std; int tux, foo, bar, baz, quz = 1; int main() { scanf( %d , &tux); for (int i = 1; i <= tux; ++i) { int pur; scanf( %d , &pur); foo += pur, bar++; if (foo * quz > baz * bar) baz = foo, quz = bar; } printf( %.6lf , baz * 1.0 / quz); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } vector<pair<int, int>> dec; vector<pair<int, int>> inc; dec.push_back({1e7, 0}); inc.push_back({-1e7, 0}); for (int i = 0; i < n; i++) { if (a[i] >= dec[dec.size() - 1].first and a[i] <= inc[inc.size() - 1].first) { cout << NO ; return 0; } else if (a[i] < dec[dec.size() - 1].first and a[i] <= inc[inc.size() - 1].first) { dec.push_back({a[i], i}); } else if (a[i] >= dec[dec.size() - 1].first and a[i] > inc[inc.size() - 1].first) { inc.push_back({a[i], i}); } else { if (i < n - 1) { if (a[i] > a[i + 1]) { dec.push_back({a[i], i}); } else { inc.push_back({a[i], i}); } } else { inc.push_back({a[i], i}); } } } cout << YES n ; vector<int> ans(n, 1); for (int i = 1; i < inc.size(); i++) { ans[inc[i].second] = 0; } for (int i = 0; i < n; i++) { cout << ans[i] << ; } return 0; } |
#include <bits/stdc++.h> const long long mod = (long long)1e9 + 7; const int maxn = (int)1e5 + 1; long long inf = 1LL << 60; using namespace std; inline void read(int &n) { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = 10 * x + ch - 0 ; ch = getchar(); } n = x * f; } inline void read(long long &n) { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = 10ll * x + ch - 0 ; ch = getchar(); } n = x * f; } int a[20]; int rule[20][20]; long long dp[1 << 19][19]; int bitCount(int n) { int count = 0; while (n) { count++; n &= (n - 1); } return count; } int main() { setlocale(LC_ALL, Russian ); ios_base::sync_with_stdio(0); int n, m, k; cin >> n >> m >> k; long long ans = 0; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < k; i++) { int u, v, d; cin >> u >> v >> d; u--, v--; rule[u][v] = d; } for (int i = 0; i < n; i++) dp[1 << i][i] = a[i]; for (int mask = 0; mask < 1 << n; mask++) { for (int i = 0; i < n; i++) { if (mask & (1 << i)) { for (int j = 0; j < n; j++) { if (!(mask & (1 << j))) { int nmask = mask | (1 << j); dp[nmask][j] = max(dp[nmask][j], dp[mask][i] + a[j] + rule[i][j]); } } } } } for (int mask = 0; mask < 1 << n; mask++) { for (int i = 0; i < n; i++) { if (bitCount(mask) == m) { ans = max(ans, dp[mask][i]); } } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 200; int n, a[N], m; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); scanf( %d , &m); for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); x--; if (x - 1 >= 0) a[x - 1] += y - 1; if (x + 1 < n) a[x + 1] += a[x] - y; a[x] = 0; } for (int i = 0; i < n; i++) printf( %d n , a[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e3 + 20; const int MOD = 1e9 + 7; const int INF = 0x3f3f3f3f; const long long LLINF = 0x3f3f3f3f3f3f3f3f; const double PI = acos(-1.0); const double RATE = 0.995; const double eps = 1e-4; int arr[MAXN][MAXN]; signed main() { int n; scanf( %d , &n); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { scanf( %d , &arr[i][j]); } } int a1a2 = arr[1][2]; int a2 = sqrt(1ll * a1a2 * arr[2][3] / arr[1][3]); printf( %d , arr[1][2] / a2); printf( %d , a2); for (int i = 3; i <= n; ++i) printf( %d , arr[2][i] / a2); puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string A; cin >> A; if (A.size() > 1 and A.size() % 2 == 0) { int x = (A.size() / 2) - 1; cout << A[x]; for (int i = 1; i <= x; i++) { cout << A[x + i] << A[x - i]; } cout << A[2 * x + 1]; } else if (A.size() % 2 != 0 and A.size() > 1) { int x = (A.size() / 2); cout << A[x]; for (int i = 1; i <= x; i++) { cout << A[x + i] << A[x - i]; } } else { cout << A[0]; } } |
#include <bits/stdc++.h> using namespace std; int n; int p[300]; int main() { int i, k, j, l; ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (i = 0; i < 2 * n; i++) { cin >> p[i]; } n *= 2; int result = 200000000; for (i = 0; i < n; i++) { for (j = i + 1; j < n; j++) { vector<int> V; for (k = 0; k < n; k++) { if (k != i && k != j) { V.push_back(p[k]); } } sort(V.begin(), V.end()); int sum = 0; for (l = 0; l < V.size(); l = l + 2) { sum += (V[l + 1] - V[l]); } result = min(result, sum); } } cout << result << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 7; int a[maxn]; int n, s; int main() { scanf( %d%d , &n, &s); if (s >= 2 * n) { s -= 2 * n; puts( YES ); printf( %d , 2 + s); for (int i = 1; i < n; ++i) printf( %d , 2); puts( ); puts( 1 ); } else puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, h, a, road_width = 0; cin >> n >> h; for (int i = 0; i < n; i++) { cin >> a; if (a > h) road_width += 2; else road_width++; } cout << road_width << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( O3 ) #pragma GCC target( avx ) #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) const int MOD = 1000000007; const int INF = 1000000009; const int MAXN = 1000005; vector<string> split(const string& s, char c) { vector<string> v; stringstream ss(s); string x; while (getline(ss, x, c)) v.emplace_back(x); return move(v); } template <typename T, typename... Args> inline string arrStr(T arr, int n) { stringstream s; s << [ ; for (int i = 0; i < n - 1; i++) s << arr[i] << , ; s << arr[n - 1] << ] ; return s.str(); } bool is_prime(long long n) { if (n < 2) return false; for (long long x = 2; x * x <= n; x++) { if (n % x == 0) return false; } return true; } vector<long long> get_prime_factors(long long n) { vector<long long> f; for (long long x = 2; x * x <= n; x++) { while (n % x == 0) { f.push_back(x); n /= x; } } if (n > 1) f.push_back(n); return f; } long long fpow(long long x, long long n) { long long res = 1; while (n) { if (n & 1) { res = (1LL * res * x) % MOD; } x = (1LL * x * x) % MOD; n >>= 1; } return (res % MOD); } vector<long long> fac, inv; void create_fac(long long n = MAXN) { fac.resize(n + 5); inv.resize(n + 5); fac[0] = 1; inv[0] = fpow(fac[0], MOD - 2); for (long long i = 1; i <= n; i++) { fac[i] = (fac[i - 1] % MOD * i % MOD) % MOD; inv[i] = fpow(fac[i], MOD - 2); } } long long binomial_coefficient(long long n, long long r) { long long res = 1; res = (res * (fac[n] % MOD)) % MOD; res = (res * (inv[r] % MOD)) % MOD; res = (res * (inv[n - r] % MOD)) % MOD; return res; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return a * (b / gcd(a, b)); } long long sceil(long long a, long long b) { return (a + b - 1) / b; } vector<long long> lp; vector<long long> pr; void sieve(long long n = MAXN) { lp.resize(n + 1); pr.clear(); for (long long i = 2; i <= n; ++i) { if (lp[i] == 0) { lp[i] = i; pr.push_back(i); } for (long long j = 0; j < (long long)pr.size() && pr[j] <= lp[i] && i * pr[j] <= n; ++j) lp[i * pr[j]] = pr[j]; } } long long extended_euclidean(long long a, long long b, long long& x, long long& y) { if (b == 0) { x = 1; y = 0; return a; } long long x1, y1; long long d = extended_euclidean(b, a % b, x1, y1); x = y1; y = x1 - y1 * (a / b); return d; } int mod_inv(long long a, long long m) { long long x, y; long long g = extended_euclidean(a, m, x, y); if (g != 1) { return -1; } else { x = (x % m + m) % m; return x; } } long long solution() { long long n, k; cin >> n >> k; string s; cin >> s; long long ans = 0; if (k <= n) ans = k; vector<long long> f(26, 0); for (auto c : s) { f[c - a ]++; } long long MX = *max_element(f.begin(), f.end()); vector<long long> v(MX, 0); for (int times = MX; times > 0; times--) { for (int i = 0; i < 26; i++) { v[times - 1] += f[i] / times; } } reverse(v.begin(), v.end()); 42; for (long long i = 1; i <= k && i <= n; i++) { if (k % i == 0) { long long times = MX - (lower_bound(v.begin(), v.end(), i) - v.begin()); 42; 42; ans = max(ans, times * i); } } return ans; } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); int tt = 1; cin >> tt; while (tt--) { cout << solution() << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; unsigned long long F(unsigned long long n) { if (n < 10) return n; unsigned long long nn = n; int firstDig = 0; while (n) { firstDig = n % 10; n /= 10; } return (nn / 10) + 9 - (firstDig > (nn % 10)); } int main() { unsigned long long x, y; while (cin >> x >> y) cout << F(y) - F(x - 1) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string name; ostringstream convert; for (int i = 1; i <= n; i++) { convert << i; name = convert.str(); } cout << name[n - 1]; return 0; } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Reset_Delay_block1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Reset_Delay_block1
// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/Reset_Delay
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Reset_Delay_block1
(
CLK_IN,
reset,
enb_1_2000_0,
Reset_1,
In,
Out
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input Reset_1;
input signed [31:0] In; // sfix32_En28
output signed [31:0] Out; // sfix32_En28
wire signed [31:0] Constant1_out1; // sfix32_En28
wire signed [31:0] Reset_Switch1_out1; // sfix32_En28
reg signed [31:0] In_Delay_out1; // sfix32_En28
wire signed [31:0] Constant_out1; // sfix32_En28
wire signed [31:0] Reset_Switch_out1; // sfix32_En28
// <S30>/Constant1
assign Constant1_out1 = 32'sb00000000000000000000000000000000;
// <S30>/Reset_Switch1
assign Reset_Switch1_out1 = (Reset_1 == 1'b0 ? In :
Constant1_out1);
// <S30>/In_Delay
always @(posedge CLK_IN)
begin : In_Delay_process
if (reset == 1'b1) begin
In_Delay_out1 <= 32'sb00000000000000000000000000000000;
end
else if (enb_1_2000_0) begin
In_Delay_out1 <= Reset_Switch1_out1;
end
end
// <S30>/Constant
assign Constant_out1 = 32'sb00000000000000000000000000000000;
// <S30>/Reset_Switch
assign Reset_Switch_out1 = (Reset_1 == 1'b0 ? In_Delay_out1 :
Constant_out1);
assign Out = Reset_Switch_out1;
endmodule // velocityControlHdl_Reset_Delay_block1
|
#include <bits/stdc++.h> using namespace std; const int N = 1e9; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; int a[n + 5]; long long ans = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; ans += a[i] * a[i]; } sort(a + 1, a + n + 1); for (int i = 1; i <= n / 2; i++) { ans += 2 * a[i] * a[n - i + 1]; } cout << ans; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND2_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__NAND2_FUNCTIONAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nand2 (
Y,
A,
B
);
// Module ports
output Y;
input A;
input B;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND2_FUNCTIONAL_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [31:0] in_a;
reg [31:0] in_b;
reg [31:0] e,f,g,h;
always @ (/*AS*/in_a) begin
e = in_a;
f = {e[15:0], e[31:16]};
g = {f[15:0], f[31:16]};
h = {g[15:0], g[31:16]};
end
// verilator lint_off UNOPTFLAT
reg [31:0] e2,f2,g2,h2;
always @ (/*AS*/f2) begin
h2 = {g2[15:0], g2[31:16]};
g2 = {f2[15:0], f2[31:16]};
end
always @ (/*AS*/in_a) begin
f2 = {e2[15:0], e2[31:16]};
e2 = in_a;
end
// verilator lint_on UNOPTFLAT
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d %x %x\n", cyc, h, h2);
if (h != h2) $stop;
if (cyc==1) begin
in_a <= 32'h89a14fab;
in_b <= 32'h7ab512fa;
end
if (cyc==2) begin
in_a <= 32'hf4c11a42;
in_b <= 32'h359967c6;
if (h != 32'h4fab89a1) $stop;
end
if (cyc==3) begin
if (h != 32'h1a42f4c1) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 7; const int MOD = 1e9 + 7; vector<int> Gimp[MAXN]; vector<int> Gcrew[MAXN]; vector<int> G[MAXN]; int comp[MAXN]; int compSize[MAXN]; bool vis[MAXN]; bool col[MAXN]; bool ans; int res; int allSize; void DFScomp(int v, int nr) { comp[v] = nr; ++compSize[nr]; for (auto u : Gcrew[v]) { if (comp[u] > 0) continue; DFScomp(u, nr); } } void DFScolor(int v, bool c) { vis[v] = true; col[v] = c; if (c) res += compSize[v]; allSize += compSize[v]; for (auto u : G[v]) { if (vis[u]) { if (col[u] == c) ans = false; continue; } DFScolor(u, !c); } } void solve() { int n, m; cin >> n >> m; for (int i = 1; i <= m; ++i) { int u, v; string c; cin >> u >> v >> c; if (c == imposter ) { Gimp[v].push_back(u); Gimp[u].push_back(v); } else { Gcrew[v].push_back(u); Gcrew[u].push_back(v); } } int c = 1; for (int i = 1; i <= n; ++i) { if (comp[i] == 0) { DFScomp(i, c); ++c; } } for (int v = 1; v <= n; ++v) { for (auto u : Gimp[v]) { G[comp[u]].push_back(comp[v]); G[comp[v]].push_back(comp[u]); } } int best = 0; ans = true; for (int i = 1; i < c; ++i) { if (!vis[i]) { res = 0; allSize = 0; DFScolor(i, 0); best += max(res, allSize - res); } } if (!ans) best = -1; cout << best << n ; for (int i = 1; i <= n; ++i) { Gimp[i].clear(); Gcrew[i].clear(); G[i].clear(); col[i] = 0; comp[i] = 0; compSize[i] = 0; vis[i] = false; } } int main() { ios_base::sync_with_stdio(0), cin.tie(0); int T; cin >> T; while (T--) solve(); return 0; } |
#include <bits/stdc++.h> const long long mod = (long long)1e9 + 7; using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, m; cin >> n >> m; vector<long long> v(m); bool valid = true; for (long long i = 0; i < m; i++) { cin >> v[i]; if (v[i] == n or v[i] == 1) valid = 0; } if (!valid) { cout << NO << n ; return 0; } sort(v.begin(), v.end()); for (long long i = 2; i < m; i++) { if (v[i] - 1 == v[i - 1] and v[i] - 2 == v[i - 2]) { valid = 0; break; } } if (valid) cout << YES << n ; else cout << NO << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21OI_SYMBOL_V
`define SKY130_FD_SC_LS__A21OI_SYMBOL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a21oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21OI_SYMBOL_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module m26_rx #(
parameter BASEADDR = 16'h0000,
parameter HIGHADDR = 16'h0000,
parameter ABUSWIDTH = 16,
parameter HEADER = 0,
parameter IDENTIFIER = 0
) (
input wire BUS_CLK,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
input wire BUS_RST,
input wire BUS_WR,
input wire BUS_RD,
input wire CLK_RX,
input wire MKD_RX,
input wire [1:0] DATA_RX,
input wire FIFO_READ,
output wire FIFO_EMPTY,
output wire [31:0] FIFO_DATA,
input wire [31:0] TIMESTAMP,
output wire LOST_ERROR,
output wire INVALID,
output wire INVALID_FLAG
);
wire IP_RD, IP_WR;
wire [ABUSWIDTH-1:0] IP_ADD;
wire [7:0] IP_DATA_IN;
wire [7:0] IP_DATA_OUT;
bus_to_ip #(
.BASEADDR(BASEADDR),
.HIGHADDR(HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_bus_to_ip (
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.IP_RD(IP_RD),
.IP_WR(IP_WR),
.IP_ADD(IP_ADD),
.IP_DATA_IN(IP_DATA_IN),
.IP_DATA_OUT(IP_DATA_OUT)
);
m26_rx_core #(
.ABUSWIDTH(ABUSWIDTH),
.IDENTIFIER(IDENTIFIER),
.HEADER(HEADER)
) i_m26_rx_core (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(IP_ADD),
.BUS_DATA_IN(IP_DATA_IN),
.BUS_RD(IP_RD),
.BUS_WR(IP_WR),
.BUS_DATA_OUT(IP_DATA_OUT),
.CLK_RX(CLK_RX),
.MKD_RX(MKD_RX),
.DATA_RX(DATA_RX),
.FIFO_READ(FIFO_READ),
.FIFO_EMPTY(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.TIMESTAMP(TIMESTAMP),
.LOST_ERROR(LOST_ERROR),
.INVALID(INVALID),
.INVALID_FLAG(INVALID_FLAG)
);
endmodule
|
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