text stringlengths 59 71.4k |
|---|
#include <bits/stdc++.h> using namespace std; int pct(int x) { return __builtin_popcount(x); } int pct(long long x) { return __builtin_popcountll(x); } int bt(int x) { return 31 - __builtin_clz(x); } int bt(long long x) { return 63 - __builtin_clzll(x); } int cdiv(int a, int b) { return a / b + !(a < 0 || a % b == 0); } long long cdiv(long long a, long long b) { return a / b + !(a < 0 || a % b == 0); } int nxt_C(int x) { int c = x & -x, r = x + c; return (((r ^ x) >> 2) / c) | r; } long long nxt_C(long long x) { long long c = x & -x, r = x + c; return (((r ^ x) >> 2) / c) | r; } vector<int> get_bits(int mask) { vector<int> bb; while (mask) { int b = bt(mask); bb.push_back(b); mask ^= (1 << b); } reverse(bb.begin(), bb.end()); return bb; } int get_mask(vector<int> v) { int mask = 0; for (int x : v) { mask ^= (1 << x); } return mask; } template <typename T> void uniq(vector<T> &v) { sort(v.begin(), v.end()); v.resize(unique(v.begin(), v.end()) - v.begin()); } mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); long long rand(long long l, long long r) { uniform_int_distribution<long long> uid(l, r); return uid(rng); } void sc() {} template <typename Head, typename... Tail> void sc(Head &H, Tail &...T) { cin >> H; sc(T...); } const int mod = 1e9 + 7; int pwr(int a, long long b) { int ans = 1; while (b) { if (b & 1) ans = (ans * 1LL * a) % mod; a = (a * 1LL * a) % mod; b >>= 1; } return ans; } const int N = 2e5 + 5; int a[N]; int dp[N][2]; int n, k; bool f(int x) { dp[0][0] = 0; dp[0][1] = 0; for (int i = 1; i <= n; i++) { dp[i][0] = dp[i][1] = 0; } for (int i = 0; i <= n - 1; i++) { for (int j = 0; j <= 1; j++) { dp[i + 1][j] = max(dp[i + 1][j], dp[i][j]); if (a[i + 1] > x && !j) continue; dp[i + 1][j ^ 1] = max(dp[i + 1][j ^ 1], dp[i][j] + 1); } } return max(dp[n][0], dp[n][1]) >= k; } void solve() { sc(n, k); for (int i = 1; i <= n; i++) { sc(a[i]); } int l = 0, r = 1e9 + 5; while (r - l > 1) { int m = (l + r) >> 1; if (f(m)) r = m; else l = m; } cout << r; } int main() { ios ::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; for (int tt = 1; tt <= t; tt++) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int inf = 1000000000; const long long int mod = 1000000000 + 7; inline void IO() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } inline int dcmp(long double x) { return x < -1e-12 ? -1 : (x > 1e-12); } template <class T> inline int CHECK(T MASK, int i) { return (MASK >> i) & 1; } template <class T> inline T ON(T MASK, int i) { return MASK | (T(1) << i); } template <class T> inline T OFF(T MASK, int i) { return MASK & (~(T(1) << i)); } template <typename T> inline int CNT(T MASK) { if (numeric_limits<T>::digits <= numeric_limits<unsigned int>::digits) return __builtin_popcount(MASK); else return __builtin_popcountll(MASK); } template <class T> inline int RIGHT(T MASK) { return log2(MASK & -MASK); } int dx4[] = {0, 0, -1, +1}; int dy4[] = {+1, -1, 0, 0}; int dx8[] = {1, 1, 0, -1, -1, -1, 0, 1, 0}; int dy8[] = {0, 1, 1, 1, 0, -1, -1, -1, 0}; inline void I(int& a) { scanf( %d , &a); } inline void I(long long int& a) { scanf( %I64d , &a); } inline void I(unsigned long long int& a) { scanf( %I64u , &a); } inline void I(char* a) { scanf( %s , a); } char Iarr[2000010]; inline void I(string& a) { scanf( %s , Iarr); a = Iarr; } template <typename T, typename... Args> void I(T& a, Args&... args) { I(a); I(args...); } inline void OUT(int a) { printf( %d , a); } inline void OUT(long long int a) { printf( %I64d , a); } inline void OUT(const char* a) { printf( %s , a); } inline void OUT(char* a) { printf( %s , a); } inline void OUT(bool a) { printf( %d , a); } inline void OUT(string a) { for (__typeof(a.end()) it = (a.begin()) - ((a.begin()) > (a.end())); it != (a.end()) - ((a.begin()) > (a.end())); it += 1 - 2 * ((a.begin()) > (a.end()))) printf( %c , *it); } inline void OUT(unsigned long long int a) { printf( %I64u , a); } template <typename T, typename... Args> void OUT(T a, Args... args) { OUT(a); OUT( ); OUT(args...); } template <typename... Args> void O(Args... args) { OUT(args...); OUT( n ); } template <typename T1, typename T2> inline ostream& operator<<(ostream& os, pair<T1, T2> p) { os << { << p.first << , << p.second << } ; return os; } template <typename T> inline ostream& operator<<(ostream& os, vector<T>& a) { os << [ ; for (int i = 0; i < (int)a.size(); i++) { if (i) os << , ; os << a[i]; } os << ] ; return os; } void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cout << *it << = << a << endl; err(++it, args...); } const int M = 1000010; bool dp[500001]; int main() { int n, d; I(n, d); dp[0] = 1; for (int i = 0; i < n; i++) { int x; I(x); for (int j = 500000; j >= 0; j--) { if (dp[j]) { if (j + x <= 500000) dp[j + x] = 1; } } } vector<int> v; for (int i = 0; i <= 500000; i++) { if (dp[i]) v.push_back(i); } int in = 0; int days = 0; while (1) { int low = in + 1, high = (int)v.size() - 1; if (low > high) break; while (low < high) { int mid = (low + high + 1) / 2; if (v[mid] - v[in] <= d) { low = mid; } else { high = mid - 1; } } if (v[low] - v[in] <= d) { days++; in = low; } else { break; } } O(v[in], days); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 2e5 + 5; long long res = 0, mx = 0; long long sub[MAX_N]; int custo[MAX_N]; vector<vector<int> > g(MAX_N); void dfs(int node, int p = -1, int d = 0) { res += 1LL * d * custo[node]; sub[node] = custo[node]; for (auto to : g[node]) { if (to != p) { dfs(to, node, d + 1); sub[node] += sub[to]; } } } void root(int node, int p = -1) { mx = max(mx, res); for (auto to : g[node]) { if (to != p) { long long old_res = res; long long old_node = sub[node]; long long old_to = sub[to]; res -= sub[to]; sub[node] -= sub[to]; res += sub[node]; sub[to] += sub[node]; root(to, node); res = old_res; sub[node] = old_node; sub[to] = old_to; } } } int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) cin >> custo[i]; for (int i = 0; i < n - 1; i++) { int st, et; cin >> st >> et; --st; --et; g[st].emplace_back(et); g[et].emplace_back(st); } dfs(0); root(0); cout << mx << n ; return 0; } |
/* I expected that p1=p2. But the generated output looks like:
Icarus Verilog version 0.7
Copyright 1998-2003 Stephen Williams
$Name: $
0 p1=x p2=StX
5 p1=1 p2=StX
10 p1=0 p2=St0
15 p1=1 p2=St0
20 p1=0 p2=St0
25 p1=1 p2=St0
30 p1=0 p2=St0
35 p1=1 p2=St0
40 p1=0 p2=St0
45 p1=1 p2=St0
50 p1=0 p2=St0
55 p1=1 p2=St0
60 p1=0 p2=St0
65 p1=1 p2=St0
70 p1=0 p2=St0
75 p1=1 p2=St0
80 p1=0 p2=St0
85 p1=1 p2=St0
90 p1=0 p2=St0
95 p1=1 p2=St0
Model Technology ModelSim SE vsim 5.7c Simulator 2003.03 Mar 13 2003
# 0 p1=x p2=StX
# 5 p1=1 p2=StX
# 10 p1=0 p2=St0
# 15 p1=1 p2=St0
# 20 p1=0 p2=St0
# 25 p1=1 p2=St0
# 30 p1=0 p2=St0
# 35 p1=1 p2=St0
# 40 p1=0 p2=St0
# 45 p1=1 p2=St0
# 50 p1=0 p2=St0
# 55 p1=1 p2=St0
# 60 p1=0 p2=St0
# 65 p1=1 p2=St0
# 70 p1=0 p2=St0
# 75 p1=1 p2=St0
# 80 p1=0 p2=St0
# 85 p1=1 p2=St0
# 90 p1=0 p2=St0
# 95 p1=1 p2=St0
#
*/
`timescale 1 ns / 1 ns
module pulse;
reg p1,p2;
initial
begin
$monitor("%t p1=%b p2=%v",$time,p1,p2);
#101 $finish;
end
initial
repeat(10)
begin
#5 p1=1'b1;
#5 p1=1'b0;
end
initial
repeat(10) single_pulse(p2);
task single_pulse;
output p;
begin
#5 p=1'b1;
#5 p=1'b0;
end
endtask
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A221OI_FUNCTIONAL_PP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a221oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221OI_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; inline int read() { int x = 0, w = 1; char ch = 0; while (ch < 0 || ch > 9 ) { ch = getchar(); if (ch == - ) w = -1; } while (ch <= 9 && ch >= 0 ) { x = (x << 1) + (x << 3) + ch - 0 ; ch = getchar(); } return x * w; } int p[10]; int k1[10], k2[10], ans1[10], ans2[10]; int a, b, p1, p2, flag; inline void chk(int n, int c1, int c2) { int cnt1 = 0, cnt2 = 0; memset(k1, 0, sizeof(k1)); memset(k2, 0, sizeof(k2)); if ((c1 - c2 <= p1 - p2)) return; for (int i = 1; i <= n; ++i) { if (p[i] == 1) cnt1 += (k1[i] = (i == 5) ? 15 : 25); else cnt2 += (k2[i] = (i == 5) ? 15 : 25); } if (cnt1 > a || cnt2 > b) return; if (n == 5) { if (p[5]) { if (cnt2 + 13 <= b) { cnt2 += 13; k2[5] = 13; int now = min(a - cnt1, b - cnt2); cnt1 += now, cnt2 += now; k1[5] += now, k2[5] += now; } } else { if (cnt1 + 13 <= a) { cnt1 += 13; k1[5] = 13; int now = min(a - cnt1, b - cnt2); cnt1 += now, cnt2 += now; k1[5] += now, k2[5] += now; } } for (int i = 1; i <= n; ++i) { int k = (i == 5) ? 13 : 23; if (!p[i]) { if (k1[i]) continue; if (cnt1 + k > a) k1[i] = a - cnt1; else k1[i] = k; cnt1 += k1[i]; } else { if (k2[i]) continue; if (cnt2 + k > b) k2[i] = b - cnt2; else k2[i] = k; cnt2 += k2[i]; } } if (cnt1 == a && cnt2 == b && c1 - c2 > p1 - p2) { p1 = c1, p2 = c2; flag = 1; for (int i = 1; i <= n; ++i) ans1[i] = k1[i], ans2[i] = k2[i]; return; } } cnt1 = 0, cnt2 = 0; memset(k1, 0, sizeof(k1)); memset(k2, 0, sizeof(k2)); for (int i = 1; i <= n; ++i) { if (p[i] == 1) cnt1 += (k1[i] = (i == 5) ? 15 : 25); else cnt2 += (k2[i] = (i == 5) ? 15 : 25); } if (p[1]) { if (cnt2 + 23 <= b) { cnt2 += 23; k2[1] = 23; int now = min(a - cnt1, b - cnt2); cnt1 += now, cnt2 += now; k1[1] += now, k2[1] += now; } } else { if (cnt1 + 23 <= a) { cnt1 += 23; k1[1] = 23; int now = min(a - cnt1, b - cnt2); cnt1 += now, cnt2 += now; k1[1] += now, k2[1] += now; } } for (int i = 1; i <= n; ++i) { int k = (i == 5) ? 13 : 23; if (!p[i]) { if (k1[i]) continue; if (cnt1 + k > a) k1[i] = a - cnt1; else k1[i] = k; cnt1 += k1[i]; } else { if (k2[i]) continue; if (cnt2 + k > b) k2[i] = b - cnt2; else k2[i] = k; cnt2 += k2[i]; } } if (cnt1 != a || cnt2 != b) return; if (c1 - c2 > p1 - p2) { p1 = c1, p2 = c2; flag = 1; for (int i = 1; i <= n; ++i) ans1[i] = k1[i], ans2[i] = k2[i]; } } void dfs(int x, int c1, int c2) { if (c1 >= 3 || c2 >= 3) { chk(x - 1, c1, c2); return; } p[x] = 1; dfs(x + 1, c1 + 1, c2); p[x] = 0; dfs(x + 1, c1, c2 + 1); } int main() { int T = read(); while (T--) { a = read(); b = read(); flag = 0; p1 = 0, p2 = 5; dfs(1, 0, 0); if (!flag) { printf( Impossible n ); continue; } printf( %d:%d n , p1, p2); for (int i = 1; i <= p1 + p2; ++i) printf( %d:%d , ans1[i], ans2[i]); printf( n ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DFRTN_BEHAVIORAL_PP_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFRTN_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 2; int t, n, m, U, V, sum, ans1, ans2; bool kt[maxn], ch[maxn]; struct T { int c, id; }; vector<T> a[maxn]; vector<int> s[maxn]; void Enter() { cin >> m >> n; for (int i = 1; i <= m; i++) { a[i].clear(); s[i].clear(); a[i].push_back({ a , 0}); s[i].push_back(0); } for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) { char u; cin >> u; s[i].push_back(u - 0 ); } for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) { char c; cin >> c; a[i].push_back({c, -1}); } } void Findcir(int u, int v, int id) { if (a[u][v].id != -1) { U = u; V = v; sum = id - a[u][v].id; return; } a[u][v].id = id; char c = a[u][v].c; if (c == U ) Findcir(u - 1, v, id + 1); if (c == D ) Findcir(u + 1, v, id + 1); if (c == L ) Findcir(u, v - 1, id + 1); if (c == R ) Findcir(u, v + 1, id + 1); a[u][v].id = -1; } void DFS(int u, int v, int id) { a[u][v].id = id; if (s[u][v] == 0) { if (!kt[id % sum]) { kt[id % sum] = true; ans2++; ans1 -= ch[id % sum]; } } else { if (!ch[id % sum] && !kt[id % sum]) { ch[id % sum] = true; ans1++; } } if (u > 1 && a[u - 1][v].id == -1 && a[u - 1][v].c == D ) DFS(u - 1, v, id + 1); if (u < m && a[u + 1][v].id == -1 && a[u + 1][v].c == U ) DFS(u + 1, v, id + 1); if (v > 1 && a[u][v - 1].id == -1 && a[u][v - 1].c == R ) DFS(u, v - 1, id + 1); if (v < n && a[u][v + 1].id == -1 && a[u][v + 1].c == L ) DFS(u, v + 1, id + 1); } void Solve() { ans1 = ans2 = 0; for (int i = 1; i <= m; i++) for (int j = 1; j <= n; j++) if (a[i][j].id == -1) { Findcir(i, j, 0); fill_n(kt, sum + 1, false); fill_n(ch, sum + 1, false); DFS(U, V, 0); } cout << ans1 + ans2 << << ans2 << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> t; while (t--) { Enter(); Solve(); } } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module finalproject_cpu_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: LOG_Table.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module LOG_Table (
address,
clock,
q);
input [12:0] address;
input clock;
output [7:0] q;
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.clock0 (clock),
.address_a (address),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "LOG_Table.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=log",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 13,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "log"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "LOG_Table.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "LOG_Table.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=log"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL address[12..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LOG_Table_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module fmcadc4_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio);
// 4 wire
input [ 2:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const int N = 4e5 + 10; vector<int> ans[N]; vector<int> v[N]; int tot; int vis[N]; int cnt = 0; void dfs(int x) { vis[x] = 1; ans[cnt++ / tot].push_back(x); for (auto &y : v[x]) { if (vis[y]) continue; dfs(y); ans[cnt++ / tot].push_back(x); } } int main() { int n, m, k; cin >> n >> m >> k; tot = (2 * n + k - 1) / k; while (m--) { int x, y; cin >> x >> y; v[x].push_back(y); v[y].push_back(x); } for (int i = 1; i <= n; i++) { if (vis[i]) continue; cnt = (cnt + tot - 1) / tot * tot; dfs(i); } for (int i = 0; i < k; i++) { if (ans[i].empty()) ans[i].push_back(1); printf( %d , ans[i].size()); for (auto &x : ans[i]) printf( %d , x); puts( ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX = 105; int main() { ios::sync_with_stdio(false); int n; cin >> n; int x; cin >> x; for (int i = 0; i < n; i++) { x = 7 - x; int a, b; cin >> a >> b; if (a == x || b == x || 7 - a == x || 7 - b == x) { cout << NO n ; return 0; } for (int j = 1; j <= 6; j++) if (a != j && b != j && 7 - a != j && 7 - b != j) x = j; } cout << YES n ; return 0; } |
//Instruction decoder
`include "verilog/mips_instr_defines.v"
module decode
(
input wire[31:0] instr_dec_i,
input wire sign_ext_i,
output wire[4:0] rt_dec_o,
output wire[4:0] rs_dec_o,
output wire[4:0] rd_dec_o,
output wire[5:0] op_dec_o,
output wire[5:0] funct_dec_o,
output wire[4:0] shamt_dec_o,
output wire[25:0] target_dec_o,
output wire[31:0] sign_imm_dec_o,
output wire is_r_type_dec_o,
output wire is_i_type_dec_o,
output wire is_j_type_dec_o,
output wire is_lw_dec_o,
output wire use_link_reg_dec_o
);
//Populate the output fields using the input instruction
wire[4:0] rt_dec;
wire[4:0] rs_dec;
wire[4:0] rd_dec;
wire[5:0] op_dec;
wire[5:0] funct_dec;
wire[4:0] shamt_dec;
wire[25:0] target_dec;
wire[31:0] sign_imm_dec;
wire is_r_type_dec;
wire is_i_type_dec;
wire is_j_type_dec;
wire is_lw_dec;
wire use_link_reg_dec;
assign rt_dec_o = rt_dec;
assign rs_dec_o = rs_dec;
assign rd_dec_o = rd_dec;
assign op_dec_o = op_dec;
assign funct_dec_o = funct_dec;
assign shamt_dec_o = shamt_dec;
assign target_dec_o = target_dec;
assign sign_imm_dec_o = sign_imm_dec;
assign is_r_type_dec_o = is_r_type_dec;
assign is_i_type_dec_o = is_i_type_dec;
assign is_j_type_dec_o = is_j_type_dec;
assign is_lw_dec_o = is_lw_dec;
assign use_link_reg_dec_o = use_link_reg_dec;
assign sign_imm_dec = (sign_ext_i) ? {{16{instr_dec_i[15]}},instr_dec_i[15:0]} :
{16'b0, instr_dec_i[15:0]};
assign rd_dec = instr_dec_i[15:11];
assign rt_dec = instr_dec_i[20:16];
assign rs_dec = instr_dec_i[25:21];
assign op_dec = instr_dec_i[31:26];
assign target_dec = instr_dec_i[25:0];
assign funct_dec = instr_dec_i[5:0];
assign shamt_dec = instr_dec_i[10:6];
assign is_r_type_dec = (op_dec == 6'h0) &
~((funct_dec == 6'h0) & (shamt_dec == 6'h0) &
(rt_dec == 5'h0) & (rd_dec == 5'h0));
assign is_i_type_dec = ((op_dec != 6'h0) && ((op_dec != `J) && (op_dec != `JAL)));
assign is_j_type_dec = ((op_dec == `J) || (op_dec == `JAL));
assign use_link_reg_dec = (((op_dec == `BVAR) && ((rt_dec == `BLTZAL) || (rt_dec == `BGEZAL))) ||
((is_r_type_dec) && ((funct_dec == `JALR))) ||
((is_j_type_dec) && ((op_dec == `JAL))));
assign is_lw_dec = is_i_type_dec & (op_dec == `LW);
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast , unroll-loops ) using namespace std; const int max_n = 100011, inf = 1000111222; const int mod = 1000000007; int n, m, fenv[333][333]; map<int, vector<pair<int, int>>> mp; pair<int, int> a[max_n]; int sum(int tt[], int r) { int result = 0; for (; r >= 0; r = (r & (r + 1)) - 1) result += tt[r]; return result; } void inc(int t[], int i, int delta) { for (; i < m; i = (i | (i + 1))) t[i] += delta; } bool cmp(pair<int, int> a, pair<int, int> b) { if (a.second == b.second) { return a.first > b.first; } return a.second < b.second; } int main() { int t; cin >> t; while (t--) { cin >> n >> m; mp.clear(); for (int i = 0; i < n; ++i) { for (int q = 0; q < m; ++q) { fenv[i][q] = 0; } } for (int i = 0; i < n * m; ++i) { cin >> a[i].first; a[i].second = i; } sort(a, a + n * m); int pos = 0; for (int i = 0; i < n * m; ++i) { mp[a[i].first].push_back({pos % m, pos / m}); ++pos; swap(a[i].first, a[i].second); } for (auto& a : mp) { sort(a.second.begin(), a.second.end(), cmp); reverse(a.second.begin(), a.second.end()); } sort(a, a + n * m); int ans = 0; for (int i = 0; i < n * m; ++i) { int x = mp[a[i].second].back().second; int y = mp[a[i].second].back().first; mp[a[i].second].pop_back(); ans += sum(fenv[x], y); inc(fenv[x], y, 1); } cout << ans << n ; } return 0; } |
`timescale 1ns / 1ps
`define SIMULATION
module peripheral_pwm_TB;
reg clk;
reg rst;
reg reset;
reg start;
reg [15:0]d_in;
reg cs;
reg [1:0]addr;
reg rd;
reg wr;
wire [15:0]d_out;
reg micData;
peripheral_pwm uut (.clk(clk) , .rst(reset) , .d_in(d_in) , .cs(cs) , .addr(addr) , .rd(rd) , .wr(wr), .d_out(d_out),.micData(micData) );
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
reg [20:0] i;
event reset_trigger;
reg d;
initial begin // Initialize Inputs
clk = 0; reset = 1; start = 0; d_in = 16'd0035; addr = 16'h0000; cs=1; rd=0; wr=1;
end
initial begin // Process for clk
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
micData = 1'b0;#75;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b0;#450;
micData = 1'b1;#100;
micData = 1'b0;#64;
micData = 1'b1;#80;
micData = 1'b0;#75;
micData = 1'b1;#34;
end
initial begin // Reset the system, Start the image capture process
forever begin
@ (reset_trigger);
@ (posedge clk);
start = 0;
@ (posedge clk);
start = 1;
for(i=0; i<2; i=i+1) begin
@ (posedge clk);
end
start = 0;
#4 reset=0;
// stimulus here
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
//d_in = 16'h0001; //envio 1
addr = 16'h0000;
cs=1; rd=0; wr=1;
addr = 16'h0002;
cs=1; rd=1; wr=0;
for(i=0; i<40000; i=i+1) begin
@ (posedge clk);
end
//d_in = 16'h0002; //envio 1
addr = 16'h0000;
cs=1; rd=0; wr=1;
end
end
initial begin: TEST_CASE
$dumpfile("peripheral_pwm_TB.vcd");
$dumpvars(-1, uut);
#10 -> reset_trigger;
#((PERIOD*DUTY_CYCLE)*200000) $finish;
end
endmodule
|
#include <bits/stdc++.h> using std::cin; using std::cout; using std::deque; using std::endl; using std::map; using std::max; using std::min; using std::multiset; using std::pair; using std::queue; using std::set; using std::sort; using std::stack; using std::string; using std::vector; int n, k, s, t; int c[200005] = { 0, }; int v[200005] = { 0, }; int g[200005] = { 0, }; bool isGood(int middle) { int time = 0; for (int i = 1; i <= k + 1; i++) { int len = g[i] - g[i - 1]; if (len > middle) { return false; } if (middle >= len * 2) { time += len; } else { time += (len * 2 - middle) * 2 + (middle - len); } } if (time <= t) return true; return false; } int main() { cin >> n >> k >> s >> t; for (int i = 0; i < n; i++) { scanf( %d%d , c + i, v + i); } g[0] = 0; g[k + 1] = s; for (int i = 1; i <= k; i++) { scanf( %d , g + i); } sort(g, g + k + 2); const int up = 2123456789; int badBak = 0; int goodBak = up; while (badBak + 1 != goodBak) { int middle = (int)((1LL * badBak + goodBak) / 2); if (isGood(middle)) { goodBak = middle; } else { badBak = middle; } } if (goodBak == up) { cout << -1; return 0; } int cheap = up; for (int i = 0; i < n; i++) { if (v[i] >= goodBak && c[i] < cheap) { cheap = c[i]; } } if (cheap == up) { cout << -1; return 0; } cout << cheap; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jorge Sequeira Rojas
//
// Create Date: 08/31/2016 04:06:16 PM
// Design Name: Recursive Parameterized KOA
// Module Name: RecursiveKOA
// Project Name: FPU
// Target Devices: Artix 7
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RecursiveKOA
#(parameter SW = 24,
//#(parameter SW = 56,
parameter Opt_FPGA_ASIC=0) //Se está optimizando el modulo para FPGA o para un ASIC
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
//genvar precision = 1;
////////////////////WIRE DECLARATIONS
wire [2*SW-1:0] Result;
///////////////////////////INSTANCIATIONS//////////////////
/////////////////////FIRST KOA MULTIPLIER//////////////////
generate
if (Opt_FPGA_ASIC) begin //Opt_FPGA_ASIC=0 Optimizations for ASIC
KOA_FPGA #(.SW(SW)/*,.level(level1)*/) main_KOA(
.Data_A_i(Data_A_i[SW-1:0]/*P=SW*/),
.Data_B_i(Data_B_i[SW-1:0]/*P=SW*/),
.sgf_result_o(Result[2*SW-1:0]) /*P=SW*/
);
end else begin //Opt_FPGA_ASIC=1 Optimizations for FPGA
KOA_c #(.SW(SW), .precision(1)/*,.level(level1)*/) main_KOA(
.Data_A_i(Data_A_i[SW-1:0]/*P=SW*/),
.Data_B_i(Data_B_i[SW-1:0]/*P=SW*/),
.sgf_result_o(Result[2*SW-1:0]) /*P=SW*/
);
// KOA_c_2 #(.SW(SW), .precision(0)/*,.level(level1)*/) main_KOA(
// .Data_A_i(Data_A_i[SW-1:0]/*P=SW*/),
// .Data_B_i(Data_B_i[SW-1:0]/*P=SW*/),
// .sgf_result_o(Result[2*SW-1:0]) /*P=SW*/
// );
end
endgenerate
//////////////////////Following REG///////////////////
RegisterAdd #(.W(2*SW)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]/*P=2*SW*/),
.Q({sgf_result_o[2*SW-1:0]})
);
///////////////////////END OF CODE////////////////////
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 3e5 + 5; struct Ans { long long a, b, c; }; void solve() { long long a, b, c; cin >> a >> b >> c; long long ans = 1e9; auto x = Ans{a, b, c}; for (long long aa = 1; aa <= 2 * a; aa++) { for (long long bb = aa; bb <= 2 * b; bb += aa) { long long op1 = bb * (c / bb); long long op2 = op1 + bb; long long diff = abs(a - aa) + abs(b - bb); long long y = diff + abs(c - op1); long long z = diff + abs(c - op2); if (y < ans) { ans = y; x.a = aa; x.b = bb; x.c = op1; } if (z < ans) { ans = z; x.a = aa; x.b = bb; x.c = op2; } } } cout << ans << n ; cout << x.a << << x.b << << x.c << n ; } int main(int argc, char *argv[]) { long long t; ios::sync_with_stdio(0); cin.tie(0); std::cout << std::fixed; std::cout << std::setprecision(15); cin >> t; for (long long z = 0; z < (long long)t; ++z) solve(); return 0; } |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response AXI3 Slave Converter
// Forwards and re-assembles split transactions.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_8_r_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
output wire cmd_ready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Throttling help signals.
wire cmd_ready_i;
wire pop_si_data;
wire si_stalling;
// Internal MI-side control signals.
wire M_AXI_RREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
wire [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from MI-Side to SI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign M_AXI_RREADY_I = ~si_stalling & cmd_valid;
assign M_AXI_RREADY = M_AXI_RREADY_I;
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_si_data & M_AXI_RLAST;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple AXI signal forwarding:
//
// USER, ID, DATA and RRESP passes through untouched.
//
// LAST has to be filtered to remove any intermediate LAST (due to split
// trasactions). LAST is only removed for the first parts of a split
// transaction. When splitting is unsupported is the LAST filtering completely
// completely removed.
//
/////////////////////////////////////////////////////////////////////////////
// Calculate last, i.e. mask from split transactions.
assign S_AXI_RLAST_I = M_AXI_RLAST &
( ~cmd_split | ( C_SUPPORT_SPLITTING == 0 ) );
// Data is passed through.
assign S_AXI_RID_I = M_AXI_RID;
assign S_AXI_RUSER_I = M_AXI_RUSER;
assign S_AXI_RDATA_I = M_AXI_RDATA;
assign S_AXI_RRESP_I = M_AXI_RRESP;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
assign S_AXI_RUSER = S_AXI_RUSER_I;
endmodule
|
/*
* Attributes:
* REFCLOCK_SECOND_COUNTER: Number of clock_ref perioss in a second
* By default it is set for 100MHz
*
* Ports:
* clock_ref: (Input): Known Clock (For Example 100 MHz)
* rst (Input): Reset
* clock_input (Output): Clock To Measure
* value (Output): Number of clock cycles per second
*/
`include "project_defines.v"
module clock_counter #(
parameter REFCLK_SECOND_COUNTER = `CLOCK_RATE
)(
input clock_ref,
input rst,
input clock_input,
output reg [31:0] value
);
//Local Parameters
//Registers/Wires
reg [31:0] ref_count;
reg capture;
wire cc_capture;
reg [31:0] counter;
reg data_ready_strobe;
wire ref_data_ready;
reg [31:0] input_value;
//Submodules
cross_clock_strobe ccc(
.rst (rst ),
.in_clk (clock_ref ),
.in_stb (capture ),
.out_clk (clock_input ),
.out_stb (cc_strobe )
);
cross_clock_strobe ccd(
.rst (rst ),
.in_clk (clock_input ),
.in_stb (data_ready_strobe ),
.out_clk (clock_ref ),
.out_stb (ref_data_ready )
);
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clock_ref) begin
if (rst) begin
capture <= 0;
ref_count <= 0;
value <= 0;
end
else begin
capture <= 0;
if (ref_count < REFCLK_SECOND_COUNTER) begin
ref_count <= ref_count + 32'h01;
end
else begin
ref_count <= 0;
capture <= 1;
end
if (ref_data_ready) begin
value <= input_value;
end
end
end
always @ (posedge clock_input) begin
if (rst) begin
counter <= 0;
input_value <= 0;
data_ready_strobe <= 0;
end
else begin
data_ready_strobe <= 0;
counter <= counter + 1;
if (cc_strobe) begin
input_value <= counter;
data_ready_strobe <= 1;
counter <= 0;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__SEDFXTP_PP_BLACKBOX_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXTP_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e2 + 7; const long long mod = 1e9 + 7; int a[N]; int main() { int n; cin >> n; for (int i = (1); i < (n + 1); ++i) scanf( %d , a + i); sort(a + 1, a + 1 + n); if (n == 0) { cout << YES n1 n1 n3 n3 n ; } else if (n == 1) { printf( YES n%d n%d n%d , a[1], 3 * a[1], 3 * a[1]); } else if (n == 2) { a[3] = 4 * a[1] - a[2]; a[4] = a[2] + a[3] - a[1]; if (a[3] < a[1] || a[4] < a[2] || a[4] < a[3]) { cout << NO ; return 0; } printf( YES n%d n%d , a[3], a[4]); } else if (n == 3) { a[4] = a[2] + a[3] - a[1]; if (2 * (a[4] - a[1]) == a[2] + a[3]) { printf( YES n%d , a[4]); return 0; } a[4] = a[1] + a[3] - a[2]; if (2 * (a[3] - a[1]) == a[2] + a[4]) { printf( YES n%d , a[4]); return 0; } a[4] = a[1] + a[2] - a[3]; if (2 * (a[3] - a[4]) == a[1] + a[2]) { printf( YES n%d , a[4]); return 0; } cout << NO ; } else if (n == 4) { if (2 * (a[2] + a[3]) == (a[1] + a[2] + a[3] + a[4]) && (a[2] + a[3]) == 2 * (a[4] - a[1])) cout << YES << endl; else cout << NO ; } } |
#include <bits/stdc++.h> using namespace std; string a, b; int ans = 0; vector<int> A, B; string cp(string s, int n) { string ans = s; for (int i = 1; i < n; i++) ans += s; return ans; } int main() { cin >> a >> b; for (int i = 1; i <= a.size(); i++) if (a.size() % i == 0 && cp(a.substr(0, i), a.size() / i) == a) A.push_back(i); for (int i = 1; i <= b.size(); i++) if (b.size() % i == 0 && cp(b.substr(0, i), b.size() / i) == b) B.push_back(i); for (int i = 0; i < A.size(); i++) for (int j = 0; j < B.size(); j++) if (A[i] == B[j] && a.substr(0, A[i]) == b.substr(0, B[j])) ans++; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long t, x, y, p, q; bool check(long long mid) { long long pp = p * mid; long long qq = q * mid; if (pp - x < 0 || qq - y < 0) return false; return (pp - x <= qq - y); } int main() { scanf( %lld , &t); while (t--) { scanf( %lld %lld %lld %lld , &x, &y, &p, &q); if (x * q == p * y) { printf( 0 n ); continue; } long long lo = 1, hi = 2000000000; while (lo + 1 < hi) { long long mid = (lo + hi) / 2LL; if (check(mid)) hi = mid; else lo = mid; } if (check(lo)) hi = lo; if (check(hi)) printf( %lld n , hi * q - y); else printf( -1 n ); } return 0; } |
`timescale 1ns / 1ns
`define HALT 10'b00_0000_0000
`define EXEC 3'b100
module opc5lstb();
reg [15:0] mem [ 65535:0 ];
reg clk, reset_b, interrupt_b, int_clk, m1, clken;
wire [15:0] addr, data1;
wire rnw, vda, vpa;
wire ceb = 1'b0;
wire oeb = !rnw;
reg [15:0] data0 ;
wire mreq_b = !(vda||vpa);
integer seed = 10;
// OPC CPU instantiation
opc5lscpu dut0_u (.address(addr), .din(data0), .dout(data1), .rnw(rnw), .clk(clk), .reset_b(reset_b), .int_b(interrupt_b), .clken(clken), .vpa(vpa), .vda(vda));
initial begin
$dumpvars;
$readmemh("test.hex", mem); // Problems with readmemb - use readmemh for now
{ clk, int_clk, reset_b} = 0;
`ifndef POSEDGE_MEMORY
clken = 1'b1;
`endif
interrupt_b = 1;
#3005 reset_b = 1;
#50000000000 $finish;
end
always @ (posedge clk or negedge reset_b)
if ( !reset_b)
m1 = 1'b0;
else if (mreq_b == 1)
m1 <= 0;
else
m1 <= !m1;
`ifdef POSEDGE_MEMORY
always @ (negedge clk or negedge reset_b)
if ( !reset_b)
clken = 1'b1;
else
clken <= (mreq_b | m1 | !reset_b) ;
always @ (posedge clk) begin
`else // Negedge memory
always @ (negedge clk) begin
`endif
if (!rnw && !ceb && oeb && reset_b)
mem[addr] <= data1;
data0 <= mem[addr];
end
always @ (posedge int_clk)
if ( (($random(seed) %100)> 85) && interrupt_b ==1'b1)
interrupt_b = 1'b0;
else
interrupt_b = 1'b1;
always begin
#273 int_clk = !int_clk;
#5000 int_clk = !int_clk;
end
always begin
#500 clk = !clk;
end
// Always stop simulation on encountering the halt pseudo instruction
always @ (negedge clk)
if (dut0_u.IR_q[10:0]== `HALT && dut0_u.FSM_q==`EXEC) begin
$display("Simulation terminated with halt instruction at time", $time);
$writememh("test.vdump",mem);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long mod(long long n, long long m) { long long ret = n % m; if (ret < 0) ret += m; return ret; } long long gcd(long long a, long long b) { return (b == 0LL ? a : gcd(b, a % b)); } long long exp(long long a, long long b, long long m) { if (b == 0LL) return 1LL; if (b == 1LL) return mod(a, m); long long k = mod(exp(a, b / 2, m), m); if (b & 1LL) { return mod(a * mod(k * k, m), m); } else return mod(k * k, m); } const int N = 660; vector<int> g[N]; vector<int> nada; map<vector<int>, int> cache; int ask(vector<int> v) { sort(v.begin(), v.end()); int k = (int)v.size(); if ((int)v.size() == 1) return 0; if (cache.count(v)) return cache[v]; cout << ? << k << n ; for (int x : v) cout << x << ; cout << n ; cout.flush(); int m; cin >> m; if (m == -1) { exit(0); } return cache[v] = m; } int vis[N]; int ed; int n; struct dsu { vector<int> p, ps; dsu(int n) { p = vector<int>(n + 1), ps = vector<int>(n + 1, 1); for (int i = 0; i < (n + 1); ++i) p[i] = i; } int find(int x) { return p[x] == x ? x : p[x] = find(p[x]); } bool join(int x, int y) { x = find(x), y = find(y); if (x == y) return 0; if (ps[x] > ps[y]) swap(x, y); p[x] = y, ps[y] += ps[x]; return 1; } }; dsu D(N); void addEdge(int a, int b) { g[a].push_back(b); g[b].push_back(a); ed++; assert(ed < n); } void go(int id, vector<int> cur) { int tam = (int)cur.size(); if (tam == 0) return; if (tam == 1) { if (D.find(id) == D.find(cur[0])) return; cur.push_back(id); int m = ask(cur); if (m == 1) { D.join(id, cur[0]); addEdge(id, cur[0]); } return; } vector<int> L, R; for (int i = 0; i < tam / 2; i++) { L.push_back(cur[i]); } if ((int)L.size()) { int m1 = ask(L); vector<int> aux = L; aux.push_back(id); int m11 = ask(aux); if (m1 != m11) { go(id, L); } } for (int i = tam / 2; i < (int)cur.size(); i++) { R.push_back(cur[i]); } cur.clear(); if ((int)R.size()) { int m1 = ask(R); vector<int> aux = R; aux.push_back(id); int m11 = ask(aux); if (m1 != m11) { go(id, R); } } return; } vector<int> cor[2]; int pai[N]; int H[N]; vector<int> path(int a, int b) { vector<int> vL, vR; while (a != b) { if (H[a] > H[b]) { vL.push_back(a); a = pai[a]; } else if (H[b] > H[a]) { vR.push_back(b); b = pai[b]; } else { vL.push_back(a); a = pai[a]; } } vector<int> ans; vL.push_back(a); for (int x : vL) ans.push_back(x); reverse(vR.begin(), vR.end()); for (int x : vR) ans.push_back(x); return ans; } void vai(vector<int> v, int tot) { if ((int)v.size() <= 1 or tot == 0) return; vector<int> L, R; int tam = (int)v.size(); for (int i = 0; i < tam / 2; i++) { L.push_back(v[i]); } for (int i = tam / 2; i < tam; i++) { R.push_back(v[i]); } v.clear(); int m1 = ask(L); int m2 = ask(R); if (m1 + m2 == tot) { vai(L, m1); vai(R, m2); return; } assert((int)R.size() > 0); for (int x : L) { vector<int> aux = R; aux.push_back(x); int mn = ask(aux); if (mn == m2) continue; while ((int)R.size() > 1) { int mid = (int)R.size() / 2; vector<int> v1, v2; for (int i = 0; i < mid; i++) { v1.push_back(R[i]); } for (int i = mid; i < (int)R.size(); i++) { v2.push_back(R[i]); } aux = v1; aux.push_back(x); int t1 = ask(v1); int t2 = ask(aux); if (t1 < t2) { R = v1; } else R = v2; } int ca = x, cb = R[0]; assert(D.find(ca) == D.find(cb)); vector<int> cic = path(ca, cb); cout << N << (int)cic.size() << n ; for (int y : cic) cout << y << ; cout << n ; exit(0); } } void tenta(int c) { if ((int)cor[c].size() == 0) return; int m = ask(cor[c]); if (m == 0) return; vai(cor[c], m); } int tt = 0; vector<int> vec; int comp = 0; void dfs(int v, int c, int p) { cor[c].push_back(v); tt++; vec.push_back(v); vis[v] = 1; if (tt > N) exit(0); for (int to : g[v]) { if (to != p) { pai[to] = v; H[to] = H[v] + 1; dfs(to, 1 - c, v); } } } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n; for (int i = 1; i <= n; i++) { nada.clear(); for (int j = 1; j <= n; j++) if (D.find(i) != D.find(j)) nada.push_back(j); go(i, nada); } for (int i = 1; i <= n; i++) { vis[i] = 0; } for (int i = 1; i <= n; i++) { if (!vis[i]) { H[i] = 1; pai[i] = 0; vec.clear(); dfs(i, 0, i); int cnt = 0; for (int x : vec) cnt += (H[x] == 1); assert(cnt == 1); vector<int> mark(n + 1, 0); int aqui = i; for (int x : vec) { mark[x] = 1; assert(D.find(aqui) == D.find(i)); } for (int j = 1; j <= n; j++) { if (!mark[j]) { assert(D.find(j) != D.find(i)); } } for (int x : vec) { int cur = x; while (cur != i and cur > 0) cur = pai[cur]; assert(cur == i); } } } for (int i = 1; i <= n; i++) { assert(H[i] == H[pai[i]] + 1); } tenta(0); tenta(1); if ((int)cor[0].size() < (int)cor[1].size()) swap(cor[0], cor[1]); cout << Y << (int)cor[0].size() << n ; for (int x : cor[0]) cout << x << ; cout << n ; } |
#include <bits/stdc++.h> using namespace std; int A[26]; int main() { int n; cin >> n; string s; cin >> s; int cnt = 0; for (int i = 0; i < n; i++) s[i] = tolower(s[i]); for (int i = 0; i < n; i++) { if (!A[s[i] - a ]) { A[s[i] - a ] = 1; ++cnt; } } if (cnt == 26) cout << YES ; else cout << NO ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__CONB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__CONB_FUNCTIONAL_PP_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_g/sky130_fd_sc_hvl__udp_pwrgood_pp_g.v"
`include "../../models/udp_pwrgood_pp_p/sky130_fd_sc_hvl__udp_pwrgood_pp_p.v"
`celldefine
module sky130_fd_sc_hvl__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_hvl__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_hvl__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__CONB_FUNCTIONAL_PP_V |
module inflight_instr_counter
(/*AUTOARG*/
// Outputs
no_inflight_instr_flag, max_inflight_instr_flag,
// Inputs
clk, rst, retire_vgpr_1_en, retire_branch_en, retire_sgpr_en,
issued_en
);
// Inputs and outputs
input clk,rst, retire_vgpr_1_en,
retire_branch_en, retire_sgpr_en,
issued_en;
output no_inflight_instr_flag, max_inflight_instr_flag;
wire wr_en;
// For now, allow only 16 inflight instructions
wire [3:0] inflight_instr_counter;
// This will be used to calculate the total number of retired instructions
wire [1:0] total_retired_instr;
wire [2:0] total_counter_summed_value;
// Next counter value
wire [3:0] counter_value;
wire [3:0] next_counter_value;
// Find the number of retired instructions
adder1bit adder_retired
(
total_retired_instr[0],
total_retired_instr[1],
retire_vgpr_1_en,
retire_branch_en,
retire_sgpr_en
);
// Calculates:
// total_counter_summed_value = (issued_en? 1 : 0) - total_retired_instr
adder_param #(3) adder_issued
(
.in1({{2{1'b0}},issued_en}),
.in2({1'b1,~total_retired_instr}),
.cin(1'b1),
.sum(total_counter_summed_value),
.cout()
);
// Calculates the next counter value
adder_param #(4) adder_next_counter
(
.in1({total_counter_summed_value[2],total_counter_summed_value}),
.in2(counter_value),
.cin(1'b0),
.sum(next_counter_value),
.cout()
);
// Register for the counter value
register #(4) counter_reg
(
.out(counter_value),
.in(next_counter_value),
.wr_en(wr_en),
.clk(clk),
.rst(rst)
);
// Finds out when to write the counter
assign wr_en = retire_vgpr_1_en | retire_branch_en |retire_sgpr_en | issued_en;
// Calculate the no_inflight_instr bit or the max_inflight_instr_bit
assign no_inflight_instr_flag = ~(|counter_value);
assign max_inflight_instr_flag = &counter_value;
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 21-03-2019
Each channel can use the full range of the DAC as they do not
get summed in the real chip.
Operator data is summed up without adding extra bits. This is
the case of real YM3438, which was used on Megadrive 2 models.
*/
// YM2610
// ADPCM inputs
// Full OP resolution
// No PCM
// 4 OP channels
// ADPCM-A input is added for the time assigned to FM channel 0_10 (i.e. 3)
module jt10_acc(
input clk,
input clk_en /* synthesis direct_enable */,
input signed [13:0] op_result,
input [ 1:0] rl,
input zero,
input s1_enters,
input s2_enters,
input s3_enters,
input s4_enters,
input [2:0] cur_ch,
input [1:0] cur_op,
input [2:0] alg,
input signed [15:0] adpcmA_l,
input signed [15:0] adpcmA_r,
input signed [15:0] adpcmB_l,
input signed [15:0] adpcmB_r,
// combined output
output signed [15:0] left,
output signed [15:0] right
);
reg sum_en;
always @(*) begin
case ( alg )
default: sum_en = s4_enters;
3'd4: sum_en = s2_enters | s4_enters;
3'd5,3'd6: sum_en = ~s1_enters;
3'd7: sum_en = 1'b1;
endcase
end
wire left_en = rl[1];
wire right_en= rl[0];
wire signed [15:0] opext = { {2{op_result[13]}}, op_result };
reg signed [15:0] acc_input_l, acc_input_r;
reg acc_en_l, acc_en_r;
// YM2610 mode:
// uses channels 0 and 4 for ADPCM data, throwing away FM data for those channels
// reference: YM2610 Application Notes.
always @(*)
case( {cur_op,cur_ch} )
{2'd0,3'd0}: begin // ADPCM-A:
acc_input_l = (adpcmA_l <<< 2) + (adpcmA_l <<< 1);
acc_input_r = (adpcmA_r <<< 2) + (adpcmA_r <<< 1);
`ifndef NOMIX
acc_en_l = 1'b1;
acc_en_r = 1'b1;
`else
acc_en_l = 1'b0;
acc_en_r = 1'b0;
`endif
end
{2'd0,3'd4}: begin // ADPCM-B:
acc_input_l = adpcmB_l >>> 1; // Operator width is 14 bit, ADPCM-B is 16 bit
acc_input_r = adpcmB_r >>> 1; // accumulator width per input channel is 14 bit
`ifndef NOMIX
acc_en_l = 1'b1;
acc_en_r = 1'b1;
`else
acc_en_l = 1'b0;
acc_en_r = 1'b0;
`endif
end
default: begin
// Note by Jose Tejada:
// I don't think we should divide down the FM output
// but someone was looking at the balance of the different
// channels and made this arrangement
// I suppose ADPCM-A would saturate if taken up a factor of 8 instead of 4
// I'll leave it as it is but I think it is worth revisiting this:
acc_input_l = opext >>> 1;
acc_input_r = opext >>> 1;
acc_en_l = sum_en & left_en;
acc_en_r = sum_en & right_en;
end
endcase
// Continuous output
jt12_single_acc #(.win(16),.wout(16)) u_left(
.clk ( clk ),
.clk_en ( clk_en ),
.op_result ( acc_input_l ),
.sum_en ( acc_en_l ),
.zero ( zero ),
.snd ( left )
);
jt12_single_acc #(.win(16),.wout(16)) u_right(
.clk ( clk ),
.clk_en ( clk_en ),
.op_result ( acc_input_r ),
.sum_en ( acc_en_r ),
.zero ( zero ),
.snd ( right )
);
`ifdef SIMULATION
// Dump each channel independently
// It dumps values in decimal, left and right
integer f0,f1,f2,f4,f5,f6;
reg signed [15:0] sum_l[7], sum_r[7];
initial begin
f0=$fopen("fm0.raw","w");
f1=$fopen("fm1.raw","w");
f2=$fopen("fm2.raw","w");
f4=$fopen("fm4.raw","w");
f5=$fopen("fm5.raw","w");
f6=$fopen("fm6.raw","w");
end
always @(posedge clk) begin
if(cur_op==2'b0) begin
sum_l[cur_ch] <= acc_en_l ? acc_input_l : 16'd0;
sum_r[cur_ch] <= acc_en_r ? acc_input_r : 16'd0;
end else begin
sum_l[cur_ch] <= sum_l[cur_ch] + (acc_en_l ? acc_input_l : 16'd0);
sum_r[cur_ch] <= sum_r[cur_ch] + (acc_en_r ? acc_input_r : 16'd0);
end
end
always @(posedge zero) begin
$fwrite(f0,"%d,%d\n", sum_l[0], sum_r[0]);
$fwrite(f1,"%d,%d\n", sum_l[1], sum_r[1]);
$fwrite(f2,"%d,%d\n", sum_l[2], sum_r[2]);
$fwrite(f4,"%d,%d\n", sum_l[4], sum_r[4]);
$fwrite(f5,"%d,%d\n", sum_l[5], sum_r[5]);
$fwrite(f6,"%d,%d\n", sum_l[6], sum_r[6]);
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSTP_2_V
`define SKY130_FD_SC_MS__SDFSTP_2_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfstp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfstp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSTP_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t = 1; while (t--) { long long l, r, i, sum = 0; deque<long long> a; a.push_back(4); a.push_back(7); cin >> l >> r; for (i = l; i <= r;) { if (i <= a.front()) { sum += a.front(); i++; } else { a.push_back(a.front() * 10 + 4); a.push_back(a.front() * 10 + 7); a.pop_front(); } } cout << sum << ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BAI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__O21BAI_FUNCTIONAL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o21bai (
Y ,
A1 ,
A2 ,
B1_N
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Local signals
wire b ;
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, b, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BAI_FUNCTIONAL_V |
// Created by aadi // Never give up , Miracles never happen in real life. #include<bits/stdc++.h> using namespace std ; #define FAST ios_base::sync_with_stdio(false);cin.tie(NULL); #define int long long int #define MIN LLONG_MIN #define MAX LLONG_MAX #define set1D(a,val,n) { for(int i=0;i<n;i++) a[i]=val; } #define set2D(a,val,n,m) { for(int i=0;i<n;i++) for(int j=0;j<m;j++)a[i][j]=val; } const double pi = 3.14159265358979323846; #define endl n #define db1(x) cout<<#x<< = <<x<< n #define db2(x,y) cout<<#x<< = <<x<< , <<#y<< = <<y<< n #define db3(x,y,z) cout<<#x<< = <<x<< , <<#y<< = <<y<< , <<#z<< = <<z<< n #define all(x) x.begin(),x.end() int32_t main() { //code; FAST int tt; cin >> tt; while (tt--) { //write code int n; cin >> n; string a, b; cin >> a >> b; int red = 0; int blue = 0; for (int i = 0; i < n; i++) { if (a[i] - 0 > b[i] - 0 ) { red++; } else if (a[i] - 0 < b[i] - 0 ) { blue++; } } if (red > blue) { cout << RED ; } else if (blue > red) { cout << BLUE ; } else { cout << EQUAL ; } cout << endl; } return 0; } |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the program counter
// Import the modules that will be tested for in this testbench
`include "prog_counter2.v"
// IMPORTANT: To run this, try: ncverilog -f prog_counter.f +gui
module prog_counter2tb();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the prog_counter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// next_pc output signal
wire [0:31] n_pc;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, rst
reg clock,reset;
// cur_pc
//reg [0:31] c_pc;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
prog_counter2 pc (
// instance_name(signal name),
// Signal name can be the same as the instance name
// next_pc,cur_pc,rst,clk
n_pc,reset,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
//c_pc=$random;
reset=1'b1;
#19
//c_pc=200;
reset=1'b0;
// Write to 8 data locations
for(count=200; count<216; count=count+1)
begin
#10
//c_pc=count;
//c_pc=n_pc;
reset=1'b0;
end
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
module usb_packet_fifo
( input reset,
input clock_in,
input clock_out,
input [15:0]ram_data_in,
input write_enable,
output reg [15:0]ram_data_out,
output reg pkt_waiting,
output reg have_space,
input read_enable,
input skip_packet ) ;
/* Some parameters for usage later on */
parameter DATA_WIDTH = 16 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
/* Create the address signals */
reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
reg [7:0] usb_ram_offset ;
reg [1:0] usb_ram_packet ;
wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
reg isfull;
assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
// Check if there is one full packet to process
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
pkt_waiting <= 0;
else if (usb_ram_ain == usb_ram_aout)
pkt_waiting <= isfull;
else if (usb_ram_ain > usb_ram_aout)
pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
else
pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
end
// Check if there is room
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
have_space <= 1;
else if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
else
have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
end
/* RAM Write Address process */
always @(posedge clock_in)
begin
if( reset )
usb_ram_ain <= 0 ;
else
if( write_enable )
begin
usb_ram_ain <= usb_ram_ain + 1 ;
if (usb_ram_ain + 1 == usb_ram_aout)
isfull <= 1;
end
end
/* RAM Writing process */
always @(posedge clock_in)
begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
end
/* RAM Read Address process */
always @(posedge clock_out)
begin
if( reset )
begin
usb_ram_packet <= 0 ;
usb_ram_offset <= 0 ;
isfull <= 0;
end
else
if( skip_packet )
begin
usb_ram_packet <= usb_ram_packet + 1 ;
usb_ram_offset <= 0 ;
end
else if(read_enable)
if( usb_ram_offset == 8'b11111111 )
begin
usb_ram_offset <= 0 ;
usb_ram_packet <= usb_ram_packet + 1 ;
end
else
usb_ram_offset <= usb_ram_offset + 1 ;
if (usb_ram_ain == usb_ram_aout)
isfull <= 0;
end
/* RAM Reading Process */
always @(posedge clock_out)
begin
ram_data_out <= usb_ram[usb_ram_aout] ;
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a, b; if (n == 2) { cout << 2 << endl; } else cout << 1 << endl; return 0; } |
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.91
// \ \ Application : MIG
// / / Filename : round_robin_arb.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// A simple round robin arbiter implemented in a not so simple
// way. Two things make this special. First, it takes width as
// a parameter and secondly it's constructed in a way to work with
// restrictions synthesis programs.
//
// Consider each req/grant pair to be a
// "channel". The arbiter computes a grant response to a request
// on a channel by channel basis.
//
// The arbiter implementes a "round robin" algorithm. Ie, the granting
// process is totally fair and symmetric. Each requester is given
// equal priority. If all requests are asserted, the arbiter will
// work sequentially around the list of requesters, giving each a grant.
//
// Grant priority is based on the "last_master". The last_master
// vector stores the channel receiving the most recent grant. The
// next higher numbered channel (wrapping around to zero) has highest
// priority in subsequent cycles. Relative priority wraps around
// the request vector with the last_master channel having lowest priority.
//
// At the highest implementation level, a per channel inhibit signal is computed.
// This inhibit is bit-wise AND'ed with the incoming requests to
// generate the grant.
//
// There will be at most a single grant per state. The logic
// of the arbiter depends on this.
//
// Once a grant is given, it is stored as the last_master. The
// last_master vector is initialized at reset to the zero'th channel.
// Although the particular channel doesn't matter, it does matter
// that the last_master contains a valid grant pattern.
//
// The heavy lifting is in computing the per channel inhibit signals.
// This is accomplished in the generate statement.
//
// The first "for" loop in the generate statement steps through the channels.
//
// The second "for" loop steps through the last mast_master vector
// for each channel. For each last_master bit, an inh_group is generated.
// Following the end of the second "for" loop, the inh_group signals are OR'ed
// together to generate the overall inhibit bit for the channel.
//
// For a four bit wide arbiter, this is what's generated for channel zero:
//
// inh_group[1] = last_master[0] && |req[3:1]; // any other req inhibits
// inh_group[2] = last_master[1] && |req[3:2]; // req[3], or req[2] inhibit
// inh_group[3] = last_master[2] && |req[3:3]; // only req[3] inhibits
//
// For req[0], last_master[3] is ignored because channel zero is highest priority
// if last_master[3] is true.
//
`timescale 1ps/1ps
module round_robin_arb
#(
parameter TCQ = 100,
parameter WIDTH = 3
)
(
/*AUTOARG*/
// Outputs
grant_ns, grant_r,
// Inputs
clk, rst, req, disable_grant, current_master, upd_last_master
);
input clk;
input rst;
input [WIDTH-1:0] req;
wire [WIDTH-1:0] last_master_ns;
reg [WIDTH*2-1:0] dbl_last_master_ns;
always @(/*AS*/last_master_ns)
dbl_last_master_ns = {last_master_ns, last_master_ns};
reg [WIDTH*2-1:0] dbl_req;
always @(/*AS*/req) dbl_req = {req, req};
reg [WIDTH-1:0] inhibit = {WIDTH{1'b0}};
genvar i;
genvar j;
generate
for (i = 0; i < WIDTH; i = i + 1) begin : channel
wire [WIDTH-1:1] inh_group;
for (j = 0; j < (WIDTH-1); j = j + 1) begin : last_master
assign inh_group[j+1] =
dbl_last_master_ns[i+j] && |dbl_req[i+WIDTH-1:i+j+1];
end
always @(/*AS*/inh_group) inhibit[i] = |inh_group;
end
endgenerate
input disable_grant;
output wire [WIDTH-1:0] grant_ns;
assign grant_ns = req & ~inhibit & {WIDTH{~disable_grant}};
output reg [WIDTH-1:0] grant_r;
always @(posedge clk) grant_r <= #TCQ grant_ns;
input [WIDTH-1:0] current_master;
input upd_last_master;
reg [WIDTH-1:0] last_master_r;
localparam ONE = 1 << (WIDTH - 1); //Changed form '1' to fix the CR #544024
//A '1' in the LSB of the last_master_r
//signal gives a low priority to req[0]
//after reset. To avoid this made MSB as
//'1' at reset.
assign last_master_ns = rst
? ONE[0+:WIDTH]
: upd_last_master
? current_master
: last_master_r;
always @(posedge clk) last_master_r <= #TCQ last_master_ns;
`ifdef MC_SVA
grant_is_one_hot_zero:
assert property (@(posedge clk) (rst || $onehot0(grant_ns)));
last_master_r_is_one_hot:
assert property (@(posedge clk) (rst || $onehot(last_master_r)));
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int a, b; stack<long long int> st; bool dfs(long long int n) { if (n > b) { return false; } if (n == b) { return true; } bool a1, a2; a1 = dfs(n * 2); if (a1) { st.push(n * 2); return true; } a2 = dfs((n * 10) + 1); if (a2) { st.push((n * 10) + 1); return true; } return false; } int main() { cin >> a >> b; if (dfs(a)) { cout << YES n ; cout << st.size() + 1 << n ; cout << a << ; while (!st.empty()) { cout << st.top() << ; st.pop(); } } else { cout << NO ; } return 0; } |
#include <bits/stdc++.h> const int INF = 107374182; using namespace std; int n, k; int ans[100005][2]; struct sa { int ma, mi; } segTree[1000000]; void build(int l, int r, int root) { if (l == r) { if (l != n + 1) { scanf( %d , &segTree[root].ma); segTree[root].mi = segTree[root].ma; } else { segTree[root].ma = 0; segTree[root].mi = INF; } return; } int mid = (l + r) >> 1; build(l, mid, root << 1); build(mid + 1, r, (root << 1) | 1); segTree[root].ma = max(segTree[root << 1].ma, segTree[(root << 1) | 1].ma); segTree[root].mi = min(segTree[root << 1].mi, segTree[(root << 1) | 1].mi); } sa query(int L, int R, int l, int r, int root) { if (L <= l && r <= R) { return segTree[root]; } sa ans, temp; if (l == r) { temp.ma = 0; temp.mi = INF; return temp; } int mid = (l + r) >> 1; ans.ma = 0; ans.mi = INF; if (L <= mid) { temp = query(L, R, l, mid, root << 1); ans.ma = max(ans.ma, temp.ma); ans.mi = min(ans.mi, temp.mi); } if (R > mid) { temp = query(L, R, mid + 1, r, (root << 1) | 1); ans.ma = max(ans.ma, temp.ma); ans.mi = min(ans.mi, temp.mi); } return ans; } int main() { scanf( %d%d , &n, &k); { build(1, n, 1); int maxlength = 0, cnt = 0; sa tempx, tempy; for (int i = 1; i <= n; i++) { int l = i, r = n + 1; while (r > l + 1) { int mid = (l + r) >> 1; tempx = query(i, mid + 1, 1, n, 1); if (tempx.ma - tempx.mi > k) r = mid; else l = mid; } tempx = query(i, l, 1, n, 1); tempy = query(i, r, 1, n, 1); if (tempx.ma - tempx.mi <= tempy.ma - tempy.mi && tempy.ma - tempy.mi <= k && l < n) l++; if (maxlength < l - i + 1) { maxlength = l - i + 1; ans[0][0] = i; ans[0][1] = l; cnt = 1; } else if (maxlength == l - i + 1) { ans[cnt][0] = i; ans[cnt++][1] = l; } } printf( %d %d n , maxlength, cnt); for (int i = 0; i < cnt; i++) { printf( %d %d n , ans[i][0], ans[i][1]); } } return 0; } |
module latch_id_ex(
input clock ,
input reset ,
input [ 5:0] stall ,
input [31:0] id_instruction ,
output reg [31:0] ex_instruction ,
input [ 7:0] id_operator ,
output reg [ 7:0] ex_operator ,
input [ 2:0] id_category ,
output reg [ 2:0] ex_category ,
input [31:0] id_operand_a ,
output reg [31:0] ex_operand_a ,
input [31:0] id_operand_b ,
output reg [31:0] ex_operand_b ,
input id_register_write_enable ,
output reg ex_register_write_enable ,
input [ 4:0] id_register_write_address,
output reg [ 4:0] ex_register_write_address,
input [31:0] id_register_write_data ,
output reg [31:0] ex_register_write_data
);
always @ (posedge clock) begin
if (reset == `RESET_ENABLE || (stall[2] == `STALL_ENABLE && stall[3] == `STALL_DISABLE)) begin
ex_instruction <= 32'b0 ;
ex_operator <= `OPERATOR_NOP ;
ex_category <= `CATEGORY_NONE;
ex_operand_a <= 32'b0 ;
ex_operand_b <= 32'b0 ;
ex_register_write_enable <= `WRITE_DISABLE;
ex_register_write_address <= 32'b0 ;
ex_register_write_data <= 32'b0 ;
end
else if (stall[2] == `STALL_DISABLE) begin
ex_instruction <= id_instruction ;
ex_operator <= id_operator ;
ex_category <= id_category ;
ex_operand_a <= id_operand_a ;
ex_operand_b <= id_operand_b ;
ex_register_write_enable <= id_register_write_enable ;
ex_register_write_address <= id_register_write_address;
ex_register_write_data <= id_register_write_data ;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { long long int l, r; cin >> l >> r; if (r - l < 2) { printf( -1 ); return 0; } if (l & 1) l++; if (l + 2 > r) { printf( -1 ); return 0; } cout << l << << l + 1 << << l + 2 << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_SYMBOL_V
`define SKY130_FD_SC_HVL__A21OI_SYMBOL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__a21oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_SYMBOL_V
|
#include <bits/stdc++.h> long long res; int max; const int N = 205; int f[N], tt[N], cnt, next[N]; long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return a / gcd(a, b) * b; } void dfs(int u) { cnt++; f[u] = -2; tt[u] = cnt; if (next[u] != u) { if (f[next[u]] == -2) { int tmp = tt[u] - tt[next[u]] + 1; res = lcm(res, tmp); cnt = tt[next[u]] - 1; } else { if (f[next[u]] == -1) { f[u] = 1; } else { if (f[next[u]] > 0) { f[u] = f[next[u]] + 1; } else { dfs(next[u]); if (tt[next[u]] <= cnt) { f[u] = f[next[u]] + 1; } else { if (tt[u] <= cnt) f[u] = 1; else f[u] = -1; } } } } } else { f[u] = -1; cnt--; } if (f[u] > max) max = f[u]; if (f[u] == -2) f[u] = -1; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &next[i]); for (int i = 1; i <= n; i++) f[i] = 0; max = 0; res = 1; for (int i = 1; i <= n; i++) if (f[i] == 0) { cnt = 0; dfs(i); } if (max > 0) { if (max % res == 0) res = max; else res *= max / res + 1; } printf( %I64d , res); return 0; } |
#include <bits/stdc++.h> using namespace std; void fre() { freopen( c://test//input.in , r , stdin); freopen( c://test//output.out , w , stdout); } template <class T1, class T2> inline void gmax(T1 &a, T2 b) { if (b > a) a = b; } template <class T1, class T2> inline void gmin(T1 &a, T2 b) { if (b < a) a = b; } const int N = 4040, M = 0, Z = 1e9 + 7, ms63 = 0x3f3f3f3f; int n, m; int y, x; int ln[1010], ls[1010]; vector<int> a[N]; int p[N]; bool e[N]; int hungary(int x) { e[x] = 1; for (int i = a[x].size() - 1; ~i; i--) { int y = a[x][i]; if (p[y] == -1) { p[y] = x; return 1; } } for (int i = a[x].size() - 1; ~i; i--) { int y = a[x][i]; if (!e[p[y]] && hungary(p[y])) { p[y] = x; return 1; } } return 0; } void ins(int x, int y) { a[x].push_back(y); } int main() { while (~scanf( %d%d , &n, &m)) { memset(ln, 1, sizeof(ln)); memset(ls, 1, sizeof(ls)); int n2 = n * 2; int n3 = n * 3; int n4 = n * 4; for (int i = 1; i <= n4; ++i) a[i].clear(); for (int i = 1; i <= m; ++i) { scanf( %d%d , &y, &x); ln[y] = 0; ls[x] = 0; } for (int i = 2; i < n; ++i) if (ln[i]) { ins(i, i + n); ins(i + n, i); if (ls[i]) { ins(i, i + n2); ins(i + n2, i); } if (ls[n + 1 - i]) { ins(i, i + n3); ins(i + n3, i); } if (ls[n + 1 - i]) { ins(i + n, i + n3); ins(i + n3, i + n); } if (ls[n + 1 - i]) { ins(i + n, n + 1 - i + n2); ins(n + 1 - i + n2, i + n); } } for (int j = 2; j < n; ++j) if (ls[j]) { ins(n + n + j, n + n + n + j); ins(n + n + n + j, n + n + j); } memset(p, -1, sizeof(p)); int ans = 0; for (int i = 1; i <= n4; i++) { memset(e, 0, sizeof(e)); if (hungary(i)) ans++; } ans /= 2; if (n & 1) { if (ln[n / 2 + 1] && ls[n / 2 + 1]) --ans; } printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long max(long long a, long long b) { if (a < b) return b; return a; } long long min(long long a, long long b) { if (a < b) return a; return b; } bool okay(vector<long long> &v, long long d, long long k) { long long sum = 0; priority_queue<long long, vector<long long>, greater<long long>> pq; for (int i = 0; i < d; i++) pq.push(0); for (auto x : v) { long long ind = pq.top(); pq.pop(); sum += max(0, x - ind); pq.push(ind + 1); } return sum >= k; } void solve() { long long n, m; cin >> n >> m; vector<long long> v(n); for (int i = 0; i < n; i++) cin >> v[i]; sort(v.rbegin(), v.rend()); long long low = 1, high = n, ans = -1; while (low <= high) { long long mid = low + (high - low) / 2; if (okay(v, mid, m)) { ans = mid; high = mid - 1; } else low = mid + 1; } cout << ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; } |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:49:29 2016
/////////////////////////////////////////////////////////////
module ACA_I_N16_Q4 ( in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
wire n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82,
n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96,
n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108,
n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119,
n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130,
n131, n132, n133;
CLKAND2X2TS U83 ( .A(in1[4]), .B(in2[4]), .Y(n120) );
CLKAND2X2TS U84 ( .A(in1[8]), .B(in2[8]), .Y(n99) );
CLKAND2X2TS U85 ( .A(in1[0]), .B(in2[0]), .Y(n127) );
OAI21XLTS U86 ( .A0(n120), .A1(n121), .B0(n112), .Y(n111) );
AOI2BB1XLTS U87 ( .A0N(n122), .A1N(n121), .B0(n120), .Y(n126) );
OAI21XLTS U88 ( .A0(n86), .A1(n94), .B0(n85), .Y(n84) );
OAI21XLTS U89 ( .A0(n99), .A1(n97), .B0(n98), .Y(n96) );
AOI2BB1XLTS U90 ( .A0N(n93), .A1N(n97), .B0(n99), .Y(n72) );
OAI21XLTS U91 ( .A0(n92), .A1(n102), .B0(n91), .Y(n90) );
OAI21XLTS U92 ( .A0(n106), .A1(n116), .B0(n105), .Y(n104) );
CLKAND2X2TS U93 ( .A(in2[12]), .B(in1[12]), .Y(n106) );
AOI2BB2XLTS U94 ( .B0(in2[12]), .B1(in1[12]), .A0N(n117), .A1N(n116), .Y(
n119) );
OAI211XLTS U95 ( .A0(in1[2]), .A1(in2[2]), .B0(in1[1]), .C0(in2[1]), .Y(n109) );
OAI21XLTS U96 ( .A0(n107), .A1(n110), .B0(n70), .Y(n69) );
OAI21XLTS U97 ( .A0(n75), .A1(n95), .B0(n74), .Y(n73) );
OAI21XLTS U98 ( .A0(n79), .A1(n103), .B0(n78), .Y(n77) );
AOI2BB1XLTS U99 ( .A0N(in1[0]), .A1N(in2[0]), .B0(n127), .Y(res[0]) );
NAND2X1TS U100 ( .A(in1[3]), .B(in2[3]), .Y(n82) );
INVX2TS U101 ( .A(n82), .Y(n107) );
NOR2X2TS U102 ( .A(in1[3]), .B(in2[3]), .Y(n110) );
OAI31X1TS U103 ( .A0(n107), .A1(n70), .A2(n110), .B0(n69), .Y(res[3]) );
NOR2X2TS U104 ( .A(in1[7]), .B(in2[7]), .Y(n95) );
NAND2X1TS U105 ( .A(in1[6]), .B(in2[6]), .Y(n80) );
NAND2X1TS U106 ( .A(in1[7]), .B(in2[7]), .Y(n88) );
OA21XLTS U107 ( .A0(n95), .A1(n80), .B0(n88), .Y(n93) );
NOR2X2TS U108 ( .A(in1[8]), .B(in2[8]), .Y(n97) );
NOR2X1TS U109 ( .A(in1[9]), .B(in2[9]), .Y(n89) );
INVX2TS U110 ( .A(n89), .Y(n76) );
NAND2X1TS U111 ( .A(in1[9]), .B(in2[9]), .Y(n101) );
NAND2X1TS U112 ( .A(n76), .B(n101), .Y(n71) );
XOR2XLTS U113 ( .A(n72), .B(n71), .Y(res[9]) );
INVX2TS U114 ( .A(n88), .Y(n75) );
NOR2X1TS U115 ( .A(in1[5]), .B(in2[5]), .Y(n83) );
INVX2TS U116 ( .A(n83), .Y(n124) );
AOI22X1TS U117 ( .A0(in1[5]), .A1(in2[5]), .B0(n120), .B1(n124), .Y(n81) );
NOR2X2TS U118 ( .A(in1[6]), .B(in2[6]), .Y(n94) );
OAI21X1TS U119 ( .A0(n81), .A1(n94), .B0(n80), .Y(n74) );
OAI31X1TS U120 ( .A0(n75), .A1(n74), .A2(n95), .B0(n73), .Y(res[7]) );
NAND2X1TS U121 ( .A(in1[11]), .B(in2[11]), .Y(n113) );
INVX2TS U122 ( .A(n113), .Y(n79) );
AOI22X1TS U123 ( .A0(in1[9]), .A1(in2[9]), .B0(n99), .B1(n76), .Y(n87) );
NOR2X2TS U124 ( .A(in1[10]), .B(in2[10]), .Y(n102) );
NAND2X1TS U125 ( .A(in1[10]), .B(in2[10]), .Y(n100) );
OAI21X1TS U126 ( .A0(n87), .A1(n102), .B0(n100), .Y(n78) );
NOR2X2TS U127 ( .A(in1[11]), .B(in2[11]), .Y(n103) );
OAI31X1TS U128 ( .A0(n79), .A1(n78), .A2(n103), .B0(n77), .Y(res[11]) );
INVX2TS U129 ( .A(n80), .Y(n86) );
NOR2X2TS U130 ( .A(in1[4]), .B(in2[4]), .Y(n121) );
OAI31X1TS U131 ( .A0(n83), .A1(n121), .A2(n82), .B0(n81), .Y(n85) );
OAI31X1TS U132 ( .A0(n86), .A1(n85), .A2(n94), .B0(n84), .Y(res[6]) );
INVX2TS U133 ( .A(n100), .Y(n92) );
OAI31X1TS U134 ( .A0(n89), .A1(n97), .A2(n88), .B0(n87), .Y(n91) );
OAI31X1TS U135 ( .A0(n92), .A1(n91), .A2(n102), .B0(n90), .Y(res[10]) );
NAND2X1TS U136 ( .A(in1[5]), .B(in2[5]), .Y(n123) );
OAI31X1TS U137 ( .A0(n95), .A1(n94), .A2(n123), .B0(n93), .Y(n98) );
OAI31X1TS U138 ( .A0(n99), .A1(n98), .A2(n97), .B0(n96), .Y(res[8]) );
OA21XLTS U139 ( .A0(n103), .A1(n100), .B0(n113), .Y(n117) );
OAI31X1TS U140 ( .A0(n103), .A1(n102), .A2(n101), .B0(n117), .Y(n105) );
NOR2X2TS U141 ( .A(in2[12]), .B(in1[12]), .Y(n116) );
OAI31X1TS U142 ( .A0(n106), .A1(n105), .A2(n116), .B0(n104), .Y(res[12]) );
INVX2TS U143 ( .A(n110), .Y(n108) );
AOI31X1TS U144 ( .A0(in1[2]), .A1(in2[2]), .A2(n108), .B0(n107), .Y(n122) );
OAI21X1TS U145 ( .A0(n110), .A1(n109), .B0(n122), .Y(n112) );
OAI31X1TS U146 ( .A0(n120), .A1(n112), .A2(n121), .B0(n111), .Y(res[4]) );
NOR2X1TS U147 ( .A(in1[14]), .B(in2[14]), .Y(n130) );
AOI21X1TS U148 ( .A0(in1[14]), .A1(in2[14]), .B0(n130), .Y(n115) );
NOR2X2TS U149 ( .A(in2[13]), .B(in1[13]), .Y(n132) );
AOI22X1TS U150 ( .A0(in2[12]), .A1(in1[12]), .B0(in2[13]), .B1(in1[13]), .Y(
n131) );
OAI32X1TS U151 ( .A0(n132), .A1(n116), .A2(n113), .B0(n131), .B1(n132), .Y(
n114) );
XOR2XLTS U152 ( .A(n115), .B(n114), .Y(res[14]) );
AOI21X1TS U153 ( .A0(in1[13]), .A1(in2[13]), .B0(n132), .Y(n118) );
XNOR2X1TS U154 ( .A(n119), .B(n118), .Y(res[13]) );
NAND2X1TS U155 ( .A(n124), .B(n123), .Y(n125) );
XOR2XLTS U156 ( .A(n126), .B(n125), .Y(res[5]) );
CMPR32X2TS U157 ( .A(in2[1]), .B(in1[1]), .C(n127), .CO(n128), .S(res[1]) );
CMPR32X2TS U158 ( .A(in1[2]), .B(in2[2]), .C(n128), .CO(n70), .S(res[2]) );
NAND2X1TS U159 ( .A(in1[14]), .B(in2[14]), .Y(n129) );
OAI31X1TS U160 ( .A0(n132), .A1(n131), .A2(n130), .B0(n129), .Y(n133) );
CMPR32X2TS U161 ( .A(in1[15]), .B(in2[15]), .C(n133), .CO(res[16]), .S(
res[15]) );
initial $sdf_annotate("ACA_I_N16_Q4_syn.sdf");
endmodule
|
#pragma comment(linker, /STACK:256777216 ) #define _USE_MATH_DEFINES #define _CRT_SECURE_NO_WARNINGS #include <iostream> #include <string> #include <cstring> #include <vector> #include <queue> #include <bitset> #include <stack> #include <deque> #include <set> #include <unordered_set> #include <map> #include <unordered_map> #include <algorithm> #include <math.h> #include <chrono> #include <cmath> #include <climits> #include <ctime> #include <random> #include <iostream> #include <cstdio> #include <iomanip> using namespace std; #define forx(_name,_from, to, value) for (int name = from; name < to; name += value) #define rforx(_name, from, to, value) for (int name = from; name > to; name -= _value) #define all(_STL_NAME) _STL_NAME.begin(), _STL_NAME.end() #define rall(_STL_NAME) _STL_NAME.rbegin(), _STL_NAME.rend() #define mp(_FIRST,_SECOND) make_pair(_FIRST,_SECOND) typedef long long ll; typedef unsigned long long llu; typedef long double ld; const ld eps = 1e-9; mt19937 rndm; void start() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << setprecision(5); cout.setf(ios::fixed); string FILENAME = dice ; rndm.seed(time(0)); #ifdef _DEBUG freopen( input.txt , rt , stdin); freopen( output.txt , wt , stdout); #else /*freopen((FILENAME + .in ).c_str(), rt , stdin); freopen((FILENAME + .out ).c_str(), wt , stdout);*/ #endif } const int MAX_N = 5e3 + 5; const int INF = 1e9 + 7; const int MOD = 1e9 + 7; int a[MAX_N]; ll cnt[MAX_N]; ll dp1[MAX_N][MAX_N]; ll dp2[MAX_N][MAX_N]; void CalcCnt(int n, int k) { for (int i = 0; i < n; ++i) { dp1[i][0] = 1; } for (int j = 1; j <= k; ++j) { for (int i = 0; i < n; ++i) { if (i > 0) { dp1[i][j] = (dp1[i][j] + dp1[i - 1][j - 1]) % MOD; } if (i < n - 1) { dp1[i][j] = (dp1[i][j] + dp1[i + 1][j - 1]) % MOD; } } } for (int i = 0; i < n; ++i) { for (int j = 0; j <= k; ++j) { dp2[i][j] = (dp1[i][j] * dp1[i][k - j]) % MOD; } } for (int i = 0; i < n; ++i) { for (int j = 0; j <= k; ++j) { cnt[i] = (cnt[i] + dp2[i][j]) % MOD; } } } void solve() { int n, k, q; cin >> n >> k >> q; CalcCnt(n, k); for (int i = 0; i < n; ++i) { cin >> a[i]; } ll ans = 0; for (int i = 0; i < n; ++i) { ans = (ans + (a[i] * cnt[i]) % MOD) % MOD; } for (int i = 0; i < q; ++i) { int ii, x; cin >> ii >> x; --ii; ans = (ans - (a[ii] * cnt[ii]) % MOD + MOD) % MOD; a[ii] = x; ans = (ans + (a[ii] * cnt[ii]) % MOD) % MOD; cout << ans << n ; } } void multitest() { int t; cin >> t; for (int i = 0; i < t; ++i) { solve(); } } int main() { start(); //multitest(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& a) { in >> a.first >> a.second; return in; } template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2> a) { out << a.first << << a.second; return out; } template <typename T, typename T1> T amax(T& a, T1 b) { if (b > a) a = b; return a; } template <typename T, typename T1> T amin(T& a, T1 b) { if (b < a) a = b; return a; } const long long INF = 1e18; const int32_t M = 1e9 + 7; const int32_t MM = 998244353; const long long N = 2 * 100005; struct node { long long mn, sum; bool lazyset; long long lazyval; void assign(long long val) { mn = val; sum = val; } void merge(node& a, node& b) { mn = min(a.mn, b.mn); sum = a.sum + b.sum; } }; struct segtree { node t[4 * N]; void pushdown(long long v, long long tl, long long tr) { long long tm = (tl + tr) / 2; if (t[v].lazyset) { apply(v * 2, tl, tm, t[v].lazyval); apply(v * 2 + 1, tm + 1, tr, t[v].lazyval); t[v].lazyset = 0; } } void apply(long long v, long long tl, long long tr, long long val) { t[v].mn = val; t[v].sum = val * (tr - tl + 1); t[v].lazyset = 1; t[v].lazyval = val; } void build(long long a[], long long v, long long tl, long long tr) { if (tl == tr) { t[v].assign(a[tl]); } else { long long tm = (tl + tr) / 2; build(a, v * 2, tl, tm); build(a, v * 2 + 1, tm + 1, tr); t[v].merge(t[v * 2], t[v * 2 + 1]); } t[v].lazyset = 0; } long long query(long long v, long long tl, long long tr, long long l, long long r) { if (tl > r || tr < l) return 0; if (l <= tl && tr <= r) { return t[v].sum; } pushdown(v, tl, tr); long long tm = (tl + tr) / 2; return query(v * 2, tl, tm, l, r) + query(v * 2 + 1, tm + 1, tr, l, r); } long long sumdescent(long long v, long long tl, long long tr, long long val) { if (tl == tr) return t[v].sum > val ? tl : N; pushdown(v, tl, tr); long long tm = (tl + tr) / 2; if (t[v * 2].sum > val) return sumdescent(v * 2, tl, tm, val); return sumdescent(v * 2 + 1, tm + 1, tr, val - t[v * 2].sum); } long long descent(long long v, long long tl, long long tr, long long val) { if (t[v].mn >= val) return tr + 1; if (tl == tr) return tl; pushdown(v, tl, tr); long long tm = (tl + tr) / 2; if (t[v * 2].mn < val) return descent(v * 2, tl, tm, val); return descent(v * 2 + 1, tm + 1, tr, val); } void rupd(long long v, long long tl, long long tr, long long l, long long r, long long val) { if (tl > r || tr < l) return; if (l <= tl && tr <= r) { apply(v, tl, tr, val); return; } pushdown(v, tl, tr); long long tm = (tl + tr) / 2; rupd(v * 2, tl, tm, l, r, val); rupd(v * 2 + 1, tm + 1, tr, l, r, val); t[v].merge(t[v * 2], t[v * 2 + 1]); } } st; void solve() { long long n, q; cin >> n >> q; long long a[n]; for (long long i = 0; i < n; ++i) { cin >> a[i]; } st.build(a, 1, 0, n - 1); for (long long i = 0; i < q; ++i) { long long t, x, y; cin >> t >> x >> y; if (t == 1) { long long l = st.descent(1, 0, n - 1, y); long long r = x - 1; if (l <= r) st.rupd(1, 0, n - 1, l, r, y); } else { long long cur = y; long long idx = x - 1; long long ans = 0; while (idx < n) { long long nxtidx = st.descent(1, 0, n - 1, cur + 1); amax(idx, nxtidx); long long sumidx = st.sumdescent(1, 0, n - 1, cur + st.query(1, 0, n - 1, 0, idx - 1)) - 1; amin(sumidx, n - 1); ans += sumidx - idx + 1; cur -= st.query(1, 0, n - 1, idx, sumidx); idx = sumidx + 1; } cout << ans << n ; } } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t = 1; while (t--) solve(); return 0; } |
module TailLight(
input reset, left, right, clk,
output LC, LB, LA, RA, RB, RC
);
parameter ST_IDLE = 3'b000;
parameter ST_L1 = 3'b001;
parameter ST_L2 = 3'b010;
parameter ST_L3 = 3'b011;
parameter ST_R1 = 3'b100;
parameter ST_R2 = 3'b101;
parameter ST_R3 = 3'b110;
reg [2:0] state, next_state;
always @(posedge clk)
if (reset)
state <= ST_IDLE;
else
state <= next_state;
always @*
begin
case (state)
ST_IDLE: begin
if (left && ~right)
next_state = ST_L1;
else if (~left && right)
next_state = ST_R1;
else
next_state = ST_IDLE;
end
ST_L1: next_state = ST_L2;
ST_L2: next_state = ST_L3;
ST_R1: next_state = ST_R2;
ST_R2: next_state = ST_R3;
default: next_state = ST_IDLE;
endcase
if (left && right)
next_state = ST_IDLE;
end
assign LA = state == ST_L1 || state == ST_L2 || state == ST_L3;
assign LB = state == ST_L2 || state == ST_L3;
assign LC = state == ST_L3;
assign RA = state == ST_R1 || state == ST_R2 || state == ST_R3;
assign RB = state == ST_R2 || state == ST_R3;
assign RC = state == ST_R3;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DFBBP_PP_SYMBOL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long head[200010], cnt; class littlestar { public: long long to, nxt; void add(long long u, long long v) { to = v; nxt = head[u]; head[u] = cnt; } } star[400010]; long long n, f[200010], g[200010], h[200010]; void dfs(long long u, long long fa) { for (long long i = head[u]; i; i = star[i].nxt) { long long v = star[i].to; if (v == fa) continue; dfs(v, u); f[fa] = f[fa] + f[v] + 1; g[u] = g[u] + f[v] + 1; } } void dp(long long u, long long fa) { for (long long i = head[u]; i; i = star[i].nxt) { long long v = star[i].to; if (v == fa) continue; h[v] = g[u] - 1; if (fa) h[v] = h[fa]; dp(v, u); } } signed main() { cin >> n; for (register long long i = 1; i <= n - 1; i++) { long long x, y; scanf( %lld%lld , &x, &y); star[++cnt].add(x, y); star[++cnt].add(y, x); } dfs(1, 0); h[1] = f[1]; dp(1, 0); long long ans = LLONG_MAX; for (register long long i = 1; i <= n; i++) ans = min(ans, h[i]); cout << ans; } |
#include <bits/stdc++.h> using namespace std; void solve() { int n, d = 0; long long x, amount; char sign; int quantity; cin >> n >> amount; for (int i = 0; i < n; i++) { cin >> sign >> quantity; if (sign == + ) amount += quantity; else if (amount < quantity) d++; else amount -= quantity; } cout << amount << << d; } int main() { solve(); return 0; } |
// DEFINES
`define BITS 2 // Bit width of the operands
module bm_if_collapse(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out2,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output [`BITS-1:0] out2;
output out1;
reg [`BITS-1:0] out0;
reg [`BITS-1:0] out2;
reg out1;
wire [`BITS-1:0] temp_a;
a top_a(clock, a_in, b_in, temp_a);
always @(posedge clock)
begin
if (c_in == 1'b0)
begin
out0 <= 2'b00;
out1 <= 1'b0;
end
else
begin
if (d_in == 1'b1)
begin
out0 <= a_in & b_in;
out1 <= c_in & d_in;
end
end
out2 <= temp_a;
end
endmodule
/*---------------------------------------------------------*/
module a(clock,
a_in,
b_in,
out);
input clock;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] out1;
reg [`BITS-1:0] out2;
always @(posedge clock)
begin
case (a_in)
2'b00:
begin
if (b_in != 2'b01)
begin
out2 <= 2'b11 ;
end
end
2'b01: out1 <= 2'b10 ;
2'b10: out1 <= 2'b01 ;
2'b11: out1 <= 2'b00 ;
endcase
out <= out1 & out2;
end
endmodule
|
#include <bits/stdc++.h> int main() { int i, j, k, l, y, m, n; char s[101], t[101]; scanf( %d , &y); for (i = y + 1;; i++) { n = i; j = n % 10; n = n / 10; k = n % 10; n = n / 10; l = n % 10; n = n / 10; if (n != l && n != k && n != j && l != k && l != j && k != j) { printf( %d n , i); return 0; } } return 0; } |
module TrafficLight(
input x, clock, clear,
output reg [1:0] MainStreet, SideStreet
);
localparam S0 = 3'd0;
localparam S1 = 3'd1;
localparam S2 = 3'd2;
localparam S3 = 3'd3;
localparam S4 = 3'd4;
localparam RED = 2'd0;
localparam YELLOW = 2'd1;
localparam GREEN = 2'd2;
reg [2:0] state, next_state;
always @(posedge clock)
begin
if (clear)
state <= S0;
else
state <= next_state;
end
always @(posedge clock)
begin
if (clear) begin
MainStreet <= GREEN;
SideStreet <= RED;
end else begin
case (next_state)
S4: begin
MainStreet <= RED;
SideStreet <= YELLOW;
end
S3: begin
MainStreet <= RED;
SideStreet <= GREEN;
end
S2: begin
MainStreet <= RED;
SideStreet <= RED;
end
S1: begin
MainStreet <= YELLOW;
SideStreet <= RED;
end
default: begin
MainStreet <= GREEN;
SideStreet <= RED;
end
endcase
end
end
always @(*)
begin
case (state)
S0:
if (x)
next_state = S1;
else
next_state = S0;
S1: next_state = S2;
S2: next_state = S3;
S3:
if (x)
next_state = S3;
else
next_state = S4;
default: next_state = S0;
endcase
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_dds (
// interface
clk,
dds_format,
dds_phase_0,
dds_scale_0,
dds_phase_1,
dds_scale_1,
dds_data);
// interface
input clk;
input dds_format;
input [15:0] dds_phase_0;
input [15:0] dds_scale_0;
input [15:0] dds_phase_1;
input [15:0] dds_scale_1;
output [15:0] dds_data;
// internal registers
reg [15:0] dds_data_int = 'd0;
reg [15:0] dds_data = 'd0;
reg [15:0] dds_scale_0_r = 'd0;
reg [15:0] dds_scale_1_r = 'd0;
// internal signals
wire [15:0] dds_data_0_s;
wire [15:0] dds_data_1_s;
// dds channel output
always @(posedge clk) begin
dds_data_int <= dds_data_0_s + dds_data_1_s;
dds_data[15:15] <= dds_data_int[15] ^ dds_format;
dds_data[14: 0] <= dds_data_int[14:0];
end
always @(posedge clk) begin
dds_scale_0_r <= dds_scale_0;
dds_scale_1_r <= dds_scale_1;
end
// dds-1
ad_dds_1 i_dds_1_0 (
.clk (clk),
.angle (dds_phase_0),
.scale (dds_scale_0_r),
.dds_data (dds_data_0_s));
// dds-2
ad_dds_1 i_dds_1_1 (
.clk (clk),
.angle (dds_phase_1),
.scale (dds_scale_1_r),
.dds_data (dds_data_1_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse4 ) using namespace std; template <typename T> void etch(T V) { for (auto x : V) cout << x << ; cout << n ; } vector<string> vec_splitter(string s) { s += , ; vector<string> res; while (!s.empty()) { res.push_back(s.substr(0, s.find( , ))); s = s.substr(s.find( , ) + 1); } return res; } void debug_out(vector<string> __attribute__((unused)) args, __attribute__((unused)) long long int idx, __attribute__((unused)) long long int LINE_NUM) { cerr << endl; } template <typename Head, typename... Tail> void debug_out(vector<string> args, long long int idx, long long int LINE_NUM, Head H, Tail... T) { if (idx > 0) cerr << , ; else cerr << Line( << LINE_NUM << ) ; stringstream ss; ss << H; cerr << args[idx] << = << ss.str(); debug_out(args, idx + 1, LINE_NUM, T...); } const long long int MOD = 1e9 + 7; const long long int MOD1 = 998244353; const long long int N = 2e5 + 5; const long long int INF = 1000111000111000111LL; const long double EPS = 1e-12; const long double PI = 3.141592653589793116; long long int d[3005][3005], p[3005][3005]; void solve() { long long int n; cin >> n; long long int a[n + 5]; for (long long int i = 1; i <= n; i++) cin >> a[i]; for (long long int i = 0; i <= n + 2; i++) { for (long long int j = 0; j <= n + 2; j++) { d[i][j] = p[i][j] = 0; } } for (long long int i = 1; i <= n; i++) { d[i][a[i]]++; for (long long int j = 0; j <= n; j++) { d[i][j] += d[i - 1][j]; } } for (long long int i = n; i >= 1; i--) { p[i][a[i]]++; for (long long int j = 0; j <= n; j++) { p[i][j] += p[i + 1][j]; } } long long int ans = 0; for (long long int i = 1; i <= n; i++) { for (long long int j = i + 1; j <= n; j++) { ans += (d[i - 1][a[j]] * p[j + 1][a[i]]); } } cout << ans << n ; } int32_t main() { std::ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); long long int T; cin >> T; while (T--) { solve(); } return 0; } |
module main;
reg enable, bar_a, bar_b, val_in;
reg [7:0] scon;
reg val;
//(* ivl_synthesis_on *)
always @(val_in or bar_a or bar_b or scon[7:6] or enable)
begin
if (scon[7:6]==2'b10) begin
val = 1'b1;
end else if (enable) begin
val = val_in;
end else begin
val = !bar_b & bar_a;
end
end
(* ivl_synthesis_off *)
initial begin
val_in = 0;
enable = 0;
bar_b = 0;
bar_a = 0;
scon = 8'b10_000000;
#1 if (val !== 1'b1) begin
$display("FAILED -- scon=%b, val=%b", scon, val);
$finish;
end
scon = 0;
enable = 1;
#1 if (val !== 1'b0) begin
$display("FAILED -- scon=%b, enable=%b, val=%b", scon, enable, val);
$finish;
end
val_in = 1;
#1 if (val !== 1'b1) begin
$display("FAILED -- scon=%b, enable=%b, val_in=%b, val=%b",
scon, enable, val_in, val);
$finish;
end
enable = 0;
#1 if (val !== 1'b0) begin
$display("FAILED -- scon=%b, enable=%b, val=%b", scon, enable, val);
$finish;
end
bar_a = 1;
#1 if (val !== 1'b1) begin
$display("FAILED -- scon=%b, enable=%b, bar_a==%b, bar_b=%b, val=%b",
scon, enable, bar_a, bar_b, val);
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const int __ = 1000000; bool pri[__ + 5]; int num[__ + 5]; void era() { int x = (int)sqrt(__ + 0.01); for (int i = 2; i <= x; i++) if (!pri[i]) { num[++num[0]] = i; for (int j = i * i; j <= __; j += i) pri[j] = true; } for (int i = x + 1; i <= __; i++) if (!pri[i]) num[++num[0]] = i; } int main() { era(); int n; scanf( %d , &n); int m = n, maxx = 0; for (int i = 2; i * i <= m; i++) if (m % i == 0) for (maxx = i; m % i == 0; m /= i) ; if (m != 1) maxx = m; int x1 = n - maxx + 1, ans = INT_MAX; for (int i = (1); i <= (num[0]); i++) { int p = num[i]; int x0 = (x1 + p - 1) / p * p - (p - 1); int x = (x0 + p - 1) / p * p; if (x0 > p && x0 >= 3 && x <= n) ans = min(ans, x0); } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { vector<pair<long long int, long long int> > v; long long int n, x, c = 0; cin >> n; for (int i = 0; i < n; i++) { long long int a, b; cin >> a >> b; v.push_back(make_pair(a, b)); } sort(v.begin(), v.end()); long long int i = 0; x = v[0].second; while (i < n) { if (v[i].first <= x) i++; if (v[i].second < x) x = v[i].second; if (v[i].first > x || i >= n) { c++; x = v[i].second; } } cout << c; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module vgafb_pixelfeed #(
parameter fml_depth = 26
) (
input sys_clk,
/* We must take into account both resets :
* VGA reset should not interrupt a pending FML request
* but system reset should.
*/
input sys_rst,
input vga_rst,
input [17:0] nbursts,
input [fml_depth-1:0] baseaddress,
output baseaddress_ack,
output reg [fml_depth-1:0] fml_adr,
output reg fml_stb,
input fml_ack,
input [63:0] fml_di,
output reg dcb_stb,
output [fml_depth-1:0] dcb_adr,
input [63:0] dcb_dat,
input dcb_hit,
output pixel_valid,
output [15:0] pixel,
input pixel_ack
);
/* FIFO that stores the 64-bit bursts and slices it in 16-bit words */
reg fifo_source_cache;
reg fifo_stb;
wire can_burst;
wire fifo_valid;
vgafb_fifo64to16 fifo64to16(
.sys_clk(sys_clk),
.vga_rst(vga_rst),
.stb(fifo_stb),
.di(fifo_source_cache ? dcb_dat : fml_di),
.can_burst(can_burst),
.do_valid(fifo_valid),
.do(pixel),
.next(pixel_ack)
);
assign pixel_valid = fifo_valid;
/* BURST COUNTER */
reg sof;
wire counter_en;
reg [17:0] bcounter;
always @(posedge sys_clk) begin
if(vga_rst) begin
bcounter <= 18'd1;
sof <= 1'b1;
end else begin
if(counter_en) begin
if(bcounter == nbursts) begin
bcounter <= 18'd1;
sof <= 1'b1;
end else begin
bcounter <= bcounter + 18'd1;
sof <= 1'b0;
end
end
end
end
/* FML ADDRESS GENERATOR */
wire next_address;
assign baseaddress_ack = sof & next_address;
always @(posedge sys_clk) begin
if(sys_rst) begin
fml_adr <= {fml_depth{1'b0}};
end else begin
if(next_address) begin
if(sof)
fml_adr <= baseaddress;
else
fml_adr <= fml_adr + {{fml_depth-6{1'b0}}, 6'd32};
end
end
end
/* DCB ADDRESS GENERATOR */
reg [1:0] dcb_index;
always @(posedge sys_clk) begin
if(dcb_stb)
dcb_index <= dcb_index + 2'd1;
else
dcb_index <= 2'd0;
end
assign dcb_adr = {fml_adr[fml_depth-1:5], dcb_index, 3'b000};
/* CONTROLLER */
reg [3:0] state;
reg [3:0] next_state;
parameter IDLE = 4'd0;
parameter TRYCACHE = 4'd1;
parameter CACHE1 = 4'd2;
parameter CACHE2 = 4'd3;
parameter CACHE3 = 4'd4;
parameter CACHE4 = 4'd5;
parameter FML1 = 4'd6;
parameter FML2 = 4'd7;
parameter FML3 = 4'd8;
parameter FML4 = 4'd9;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
/*
* Do not put spurious data into the FIFO if the VGA reset
* is asserted and released during the FML access. Getting
* the FIFO out of sync would result in distorted pictures
* we really want to avoid.
*/
reg ignore;
reg ignore_clear;
always @(posedge sys_clk) begin
if(vga_rst)
ignore <= 1'b1;
else if(ignore_clear)
ignore <= 1'b0;
end
reg next_burst;
assign counter_en = next_burst;
assign next_address = next_burst;
always @(*) begin
next_state = state;
fifo_stb = 1'b0;
next_burst = 1'b0;
fml_stb = 1'b0;
ignore_clear = 1'b0;
dcb_stb = 1'b0;
fifo_source_cache = 1'b0;
case(state)
IDLE: begin
if(can_burst & ~vga_rst) begin
/* We're in need of pixels ! */
next_burst = 1'b1;
ignore_clear = 1'b1;
next_state = TRYCACHE;
end
end
/* Try to fetch from L2 first */
TRYCACHE: begin
dcb_stb = 1'b1;
next_state = CACHE1;
end
CACHE1: begin
fifo_source_cache = 1'b1;
if(dcb_hit) begin
dcb_stb = 1'b1;
if(~ignore) fifo_stb = 1'b1;
next_state = CACHE2;
end else
next_state = FML1; /* Not in L2 cache, fetch from DRAM */
end
/* No need to check for cache hits anymore:
* - we fetched from the beginning of a line
* - we fetch exactly a line
* - we do not release dcb_stb so the cache controller locks the line
* Therefore, next 3 fetchs always are cache hits.
*/
CACHE2: begin
dcb_stb = 1'b1;
fifo_source_cache = 1'b1;
if(~ignore) fifo_stb = 1'b1;
next_state = CACHE3;
end
CACHE3: begin
dcb_stb = 1'b1;
fifo_source_cache = 1'b1;
if(~ignore) fifo_stb = 1'b1;
next_state = CACHE4;
end
CACHE4: begin
fifo_source_cache = 1'b1;
if(~ignore) fifo_stb = 1'b1;
next_state = IDLE;
end
FML1: begin
fml_stb = 1'b1;
if(fml_ack) begin
if(~ignore) fifo_stb = 1'b1;
next_state = FML2;
end
end
FML2: begin
if(~ignore) fifo_stb = 1'b1;
next_state = FML3;
end
FML3: begin
if(~ignore) fifo_stb = 1'b1;
next_state = FML4;
end
FML4: begin
if(~ignore) fifo_stb = 1'b1;
next_state = IDLE;
end
endcase
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Generic single-channel AXI FIFO
// Synchronous FIFO is implemented using either LUTs (SRL) or BRAM.
// Transfers received on the AXI slave port are pushed onto the FIFO.
// FIFO output, when available, is presented on the AXI master port and
// popped when the master port responds (M_READY).
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Structure:
// axic_fifo
// fifo_gen
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_6_axic_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [5:9] when TYPE="lut",
// Range = [5:12] when TYPE="bram",
parameter integer C_FIFO_WIDTH = 64, // Width of payload [1:512]
parameter C_FIFO_TYPE = "lut" // "lut" = LUT (SRL) based,
// "bram" = BRAM based
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
axi_data_fifo_v2_1_6_fifo_gen #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(1),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_FIFO_WIDTH),
.C_FIFO_TYPE(C_FIFO_TYPE))
inst (
.clk(ACLK),
.rst(ARESET),
.wr_clk(1'b0),
.wr_en(S_VALID),
.wr_ready(S_READY),
.wr_data(S_MESG),
.rd_clk(1'b0),
.rd_en(M_READY),
.rd_valid(M_VALID),
.rd_data(M_MESG));
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } const int mod = int(1e9) + 7; const int N = int(1e6) + 7; long long int two[N]; void pre() { two[0] = 1; for (int i = (int)1; i < (int)N; i++) { two[i] = (two[i - 1] * 2) % mod; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); pre(); string s; cin >> s; int cnt = 0; long long int ans = 0; for (int i = (int)0; i < (int)(int)(s.size()); i++) { if (s[i] == b ) { ans = (ans + (two[cnt] - 1)) % mod; continue; } cnt++; } cout << ans << endl; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:52:03 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_util_vector_logic_1_0/system_util_vector_logic_1_0_sim_netlist.v
// Design : system_util_vector_logic_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_util_vector_logic_1_0,util_vector_logic,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "util_vector_logic,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_util_vector_logic_1_0
(Op1,
Op2,
Res);
input [0:0]Op1;
input [0:0]Op2;
output [0:0]Res;
wire [0:0]Op1;
wire [0:0]Op2;
wire [0:0]Res;
LUT2 #(
.INIT(4'hE))
\Res[0]_INST_0
(.I0(Op1),
.I1(Op2),
.O(Res));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, k; scanf( %d%d%d , &n, &m, &k); vector<vector<int>> sum_points(n + m), diff_points(n + m); vector<int> x(k), y(k); for (int i = 0; i < k; ++i) { scanf( %d%d , &x[i], &y[i]); sum_points[x[i] + y[i]].push_back(i); diff_points[x[i] - y[i] + m].push_back(i); } vector<long long> ans(k, -1); long long time = 0; int px = 0, py = 0, nx = 0, ny = 0; int dx = 1, dy = 1; while (dx) { int xdiff = (dx > 0) ? n - px : px; int ydiff = (dy > 0) ? m - py : py; int diff = min(xdiff, ydiff); nx = px + diff * dx; ny = py + diff * dy; if (dx * dy > 0) { for (int i : diff_points[nx - ny + m]) if (ans[i] == -1) ans[i] = time + abs(x[i] - px); } else { for (int i : sum_points[nx + ny]) if (ans[i] == -1) ans[i] = time + abs(x[i] - px); } if (xdiff < ydiff) dx *= -1; if (xdiff > ydiff) dy *= -1; if (xdiff == ydiff) dx = 0; px = nx; py = ny; time += diff; } for (long long t : ans) printf( %lld n , t); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 3; long long n, ans, sz[N], up[N], down[N]; vector<long long> q[N]; void dfs1(long long v, long long p) { sz[v] = 1; for (auto i : q[v]) { if (i != p) { dfs1(i, v); sz[v] += sz[i]; down[v] += down[i] + sz[i]; } } } void dfs2(long long v, long long p) { if (p != -1) { up[v] = down[p] + up[p] - (down[v] + sz[v]) + (sz[1] - sz[v]); } ans = max(ans, down[v] + up[v] + n); for (auto i : q[v]) { if (i != p) { dfs2(i, v); } } } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n; for (long long i = 1; i < n; i++) { long long x, y; cin >> x >> y; q[x].push_back(y); q[y].push_back(x); } dfs1(1, -1); dfs2(1, -1); cout << ans; } |
#include <bits/stdc++.h> const int inf = 0x3f3f3f3f; using namespace std; int yh() { int ret = 0; bool f = 0; char c = getchar(); while (!isdigit(c)) { if (c == EOF) return -1; if (c == - ) f = 1; c = getchar(); } while (isdigit(c)) ret = (ret << 3) + (ret << 1) + (c ^ 48), c = getchar(); return f ? -ret : ret; } template <typename T> void yh(T& ret) { ret = 0; bool f = 0; char c = getchar(); while (!isdigit(c)) { if (c == EOF) return ret = -1, void(); if (c == - ) f = 1; c = getchar(); } while (isdigit(c)) ret = (ret << 3) + (ret << 1) + (c ^ 48), c = getchar(); ret = f ? -ret : ret; } char s[200005]; int main() { for (register int _ = (yh()); _ >= (1); _--) { int n = yh(); queue<int> q; scanf( %s , s + 1); int bloc = 0; for (register int i = (1); i <= (n); i++) { if (s[i] == s[i - 1]) { q.push(bloc); } else bloc++; } int opts = 0, dlt = 0; for (register int i = (1); i <= (n); i++) { if (q.empty()) break; q.pop(); opts++; dlt++; while (!q.empty() && q.front() == i) { q.pop(); dlt++; } dlt++; } opts += (n - dlt + 1) / 2; cout << opts << n ; } return 0; } |
#include <bits/stdc++.h> const int inf = 1e9 + 7; const int mod = 1e9 + 7; using namespace std; int main() { long long N; cin >> N; long long cnt = 1; long long now = 10; while (now <= N) { now *= 10; cnt++; } long long ans = (cnt - 1) * 9; long long n = cnt - 1; long long sum = 0; while (n--) { sum = sum * 10 + 9; } sum = N - sum; while (sum) { ans += sum % 10; sum /= 10; } cout << ans << endl; return 0; } |
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code for ZTEX USB-FPGA Module 1.15b (one double hash pipe)
Copyright (C) 2011-2012 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
module ztex_ufm1_15d4 (fxclk_in, reset, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start, read, write);
input fxclk_in, reset, clk_reset, pll_stop, dcm_progclk, dcm_progdata, dcm_progen, rd_clk, wr_clk, wr_start;
input [7:0] read;
output [7:0] write;
reg [3:0] rd_clk_b, wr_clk_b;
reg wr_start_b1, wr_start_b2, reset_buf;
reg dcm_progclk_buf, dcm_progdata_buf, dcm_progen_buf;
reg [4:0] wr_delay;
reg [351:0] inbuf, inbuf_tmp;
reg [127:0] outbuf;
reg [7:0] read_buf, write_buf;
reg [31:0] golden_nonce1, golden_nonce2;
wire fxclk, clk, dcm_clk, pll_fb, pll_clk0, dcm_locked, pll_reset;
wire [2:1] dcm_status;
wire [31:0] golden_nonce, nonce2, hash2;
miner253 m (
.clk(clk),
.reset(reset_buf),
.midstate(inbuf[351:96]),
.data(inbuf[95:0]),
.golden_nonce(golden_nonce),
.nonce2(nonce2),
.hash2(hash2)
);
BUFG bufg_fxclk (
.I(fxclk_in),
.O(fxclk)
);
BUFG bufg_clk (
.I(pll_clk0),
.O(clk)
);
DCM_CLKGEN #(
.CLKFX_DIVIDE(4.0),
.CLKFX_MULTIPLY(32),
.CLKFXDV_DIVIDE(2),
.CLKIN_PERIOD(20.8333)
)
dcm0 (
.CLKIN(fxclk),
.CLKFXDV(dcm_clk),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata_buf),
.PROGEN(dcm_progen_buf),
.LOCKED(dcm_locked),
.STATUS(dcm_status),
.RST(clk_reset)
);
PLL_BASE #(
.BANDWIDTH("LOW"),
.CLKFBOUT_MULT(4),
.CLKOUT0_DIVIDE(4),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLK_FEEDBACK("CLKFBOUT"),
.COMPENSATION("INTERNAL"),
.DIVCLK_DIVIDE(1),
.REF_JITTER(0.10),
.RESET_ON_LOSS_OF_LOCK("FALSE")
)
pll0 (
.CLKFBOUT(pll_fb),
.CLKOUT0(pll_clk0),
.CLKFBIN(pll_fb),
.CLKIN(dcm_clk),
.RST(pll_reset)
);
assign write = write_buf;
assign pll_reset = pll_stop | ~dcm_locked | clk_reset | dcm_status[2];
always @ (posedge clk)
begin
if ( (rd_clk_b[3] == rd_clk_b[2]) && (rd_clk_b[2] == rd_clk_b[1]) && (rd_clk_b[1] != rd_clk_b[0]) )
begin
inbuf_tmp[351:344] <= read_buf;
inbuf_tmp[343:0] <= inbuf_tmp[351:8];
end;
inbuf <= inbuf_tmp;
if ( wr_start_b1 && wr_start_b2 )
begin
wr_delay <= 5'd0;
end else
begin
wr_delay[0] <= 1'b1;
wr_delay[4:1] <= wr_delay[3:0];
end
if ( ! wr_delay[4] )
begin
outbuf <= { golden_nonce2, hash2, nonce2, golden_nonce1 };
end else
begin
if ( (wr_clk_b[3] == wr_clk_b[2]) && (wr_clk_b[2] == wr_clk_b[1]) && (wr_clk_b[1] != wr_clk_b[0]) )
outbuf[119:0] <= outbuf[127:8];
end
if ( reset_buf )
begin
golden_nonce2 <= 32'd0;
golden_nonce1 <= 32'd0;
end else if ( golden_nonce != golden_nonce1 )
begin
golden_nonce2 <= golden_nonce1;
golden_nonce1 <= golden_nonce;
end
read_buf <= read;
write_buf <= outbuf[7:0];
rd_clk_b[0] <= rd_clk;
rd_clk_b[3:1] <= rd_clk_b[2:0];
wr_clk_b[0] <= wr_clk;
wr_clk_b[3:1] <= wr_clk_b[2:0];
wr_start_b1 <= wr_start;
wr_start_b2 <= wr_start_b1;
reset_buf <= reset;
end
always @ (posedge fxclk)
begin
dcm_progclk_buf <= dcm_progclk;
dcm_progdata_buf <= dcm_progdata;
dcm_progen_buf <= dcm_progen;
end
endmodule
|
module autolisp_top (/*AUTOARG*/);
/* autolisp_inst AUTO_TEMPLATE (
.\(.*\)A (\1_@"(eval tense)"_A),
.\(.*\)B (\1_@"(eval tense)"_B),
);
*/
/* AUTO_LISP(setq tense "is") */
autolisp_inst AUTOLISP_INST_I0
(/*AUTOINST*/
// Outputs
.result (result),
// Inputs
.portA (port_is_A), // Templated
.busA (bus_is_A), // Templated
.portB (port_is_B), // Templated
.busB (bus_is_B)); // Templated
/* AUTO_LISP(setq tense "was") */
autolisp_inst AUTOLISP_INST_I1
(/*AUTOINST*/
// Outputs
.result (result),
// Inputs
.portA (port_was_A), // Templated
.busA (bus_was_A), // Templated
.portB (port_was_B), // Templated
.busB (bus_was_B)); // Templated
endmodule
module autolisp_inst (/*AUTOARG*/
// Outputs
result,
// Inputs
portA, busA, portB, busB
);
input portA;
input [3:0] busA;
input portB;
input [1:0] busB;
output result;
endmodule
|
(** Extraction : tests of optimizations of pattern matching *)
(** First, a few basic tests *)
Definition test1 b :=
match b with
| true => true
| false => false
end.
Extraction test1. (** should be seen as the identity *)
Definition test2 b :=
match b with
| true => false
| false => false
end.
Extraction test2. (** should be seen a the always-false constant function *)
Inductive hole (A:Set) : Set := Hole | Hole2.
Definition wrong_id (A B : Set) (x:hole A) : hole B :=
match x with
| Hole _ => @Hole _
| Hole2 _ => @Hole2 _
end.
Extraction wrong_id. (** should _not_ be optimized as an identity *)
Definition test3 (A:Type)(o : option A) :=
match o with
| Some x => Some x
| None => None
end.
Extraction test3. (** Even with type parameters, should be seen as identity *)
Inductive indu : Type := A : nat -> indu | B | C.
Definition test4 n :=
match n with
| A m => A (S m)
| B => B
| C => C
end.
Extraction test4. (** should merge branchs B C into a x->x *)
Definition test5 n :=
match n with
| A m => A (S m)
| B => B
| C => B
end.
Extraction test5. (** should merge branches B C into _->B *)
Inductive indu' : Type := A' : nat -> indu' | B' | C' | D' | E' | F'.
Definition test6 n :=
match n with
| A' m => A' (S m)
| B' => C'
| C' => C'
| D' => C'
| E' => B'
| F' => B'
end.
Extraction test6. (** should merge some branches into a _->C' *)
(** NB : In Coq, "| a => a" corresponds to n, hence some "| _ -> n" are
extracted *)
Definition test7 n :=
match n with
| A m => Some m
| B => None
| C => None
end.
Extraction test7. (** should merge branches B,C into a _->None *)
(** Script from bug #2413 *)
Set Implicit Arguments.
Section S.
Definition message := nat.
Definition word := nat.
Definition mode := nat.
Definition opcode := nat.
Variable condition : word -> option opcode.
Section decoder_result.
Variable inst : Type.
Inductive decoder_result : Type :=
| DecUndefined : decoder_result
| DecUnpredictable : decoder_result
| DecInst : inst -> decoder_result
| DecError : message -> decoder_result.
End decoder_result.
Definition decode_cond_mode (mode : Type) (f : word -> decoder_result mode)
(w : word) (inst : Type) (g : mode -> opcode -> inst) :
decoder_result inst :=
match condition w with
| Some oc =>
match f w with
| DecInst i => DecInst (g i oc)
| DecError _ m => @DecError inst m
| DecUndefined _ => @DecUndefined inst
| DecUnpredictable _ => @DecUnpredictable inst
end
| None => @DecUndefined inst
end.
End S.
Extraction decode_cond_mode.
(** inner match should not be factorized with a partial x->x (different type) *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DLXTP_BEHAVIORAL_PP_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlxtp (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 10000; const long double pi = acos(-1.0); int n, sum[2020]; long long bin[2020], f[2020][2020]; char s[2020]; int read() { int x = 0, f = 1; char ch = getchar(); while ((ch < 0 ) || (ch > 9 )) { if (ch == - ) f = -1; ch = getchar(); } while ((ch >= 0 ) && (ch <= 9 )) { x = x * 10 + (ch - 0 ); ch = getchar(); } return x * f; } int main() { scanf( %s , s + 1); n = strlen(s + 1); for (register int i = 2; i <= n; i++) sum[i] = sum[i - 1] + (s[i] == ? ); bin[0] = 1; for (register int i = 1; i <= n; i++) bin[i] = (bin[i - 1] * 2) % 998244353; for (register int len = 2; len <= n; len++) { for (int i = 1; i + len - 1 <= n; i++) { int j = i + len - 1; if (s[i] != ( ) f[i][j] = (f[i][j] + f[i + 1][j]) % 998244353; if (s[j] != ) ) f[i][j] = (f[i][j] + f[i][j - 1]) % 998244353; if ((s[i] != ( ) && (s[j] != ) )) f[i][j] = (f[i][j] - f[i + 1][j - 1] + 998244353) % 998244353; if ((s[i] != ) ) && (s[j] != ( )) f[i][j] = (f[i][j] + f[i + 1][j - 1] + bin[sum[j - 1] - sum[i]]) % 998244353; } } printf( %lld , f[1][n]); return 0; } |
module IDEX_Reg (
input clk,
input flush,
input stall,
input [5-1:0] EX_ctrl_i,
output [5-1:0] EX_ctrl_o,
input [2-1:0] MEM_ctrl_i,
output [2-1:0] MEM_ctrl_o,
input [2-1:0] WB_ctrl_i,
output [2-1:0] WB_ctrl_o,
input [32-1:0] Rs_data_i,
output [32-1:0] Rs_data_o,
input [32-1:0] Rt_data_i,
output [32-1:0] Rt_data_o,
input [32-1:0] imm_data_i,
output [32-1:0] imm_data_o,
input [5-1:0] Rs_i,
output [5-1:0] Rs_o,
input [5-1:0] Rt_i,
output [5-1:0] Rt_o,
input [5-1:0] Rd_i,
output [5-1:0] Rd_o
);
Latch #(.width(5)) IDEX_EX_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (EX_ctrl_i),
.data_o (EX_ctrl_o)
);
Latch #(.width(2)) IDEX_MEM_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (MEM_ctrl_i),
.data_o (MEM_ctrl_o)
);
Latch #(.width(2)) IDEX_WB_ctrl (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (WB_ctrl_i),
.data_o (WB_ctrl_o)
);
Latch IDEX_Rs_data (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rs_data_i),
.data_o (Rs_data_o)
);
Latch IDEX_Rt_data (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rt_data_i),
.data_o (Rt_data_o)
);
Latch IDEX_imm_data (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (imm_data_i),
.data_o (imm_data_o)
);
Latch #(.width(5)) IDEX_Rs (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rs_i),
.data_o (Rs_o)
);
Latch #(.width(5)) IDEX_Rt (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rt_i),
.data_o (Rt_o)
);
Latch #(.width(5)) IDEX_Rd (
.clk (clk),
.rst (~flush),
.we (~stall),
.data_i (Rd_i),
.data_o (Rd_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long int n; cin >> n; if (n & 1) cout << ((n / 2) + 1) << n ; else cout << (n / 2) << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; char str[100050]; char a[5000], b[5000]; int len1, len2, len3; bool pp(int s1, int s2) { while (s2 <= len2) { if (str[s1] != a[s2]) return false; s1++, s2++; } return true; } bool pp2(int s1, int s2) { while (s2 <= len3) { if (str[s1] != b[s2]) return false; s1++, s2++; } return true; } bool rp(int s1, int s2) { while (s2 <= len2) { if (str[s1] != a[s2]) return false; s1--, s2++; } return true; } bool rp2(int s1, int s2) { while (s2 <= len3) { if (str[s1] != b[s2]) return false; s1--, s2++; } return true; } int main() { printf( Even n ); } |
#include <bits/stdc++.h> int main() { char a[21]; char b[21]; int s1[21]; int s2[21]; int lena; int lenb; while (scanf( %s%s , &a, &b) != EOF) { lena = strlen(a); for (int i = 0; i < lena; i += 2) { if (a[i] == [ && a[i + 1] == ] ) s1[i / 2] = 2; else if (a[i] == ( && a[i + 1] == ) ) s1[i / 2] = 1; else if (a[i] == 8 && a[i + 1] == < ) s1[i / 2] = 0; if (b[i] == [ && b[i + 1] == ] ) s2[i / 2] = 2; else if (b[i] == ( && b[i + 1] == ) ) s2[i / 2] = 1; else if (b[i] == 8 && b[i + 1] == < ) s2[i / 2] = 0; } int sum = 0; for (int i = 0; i < lena / 2; i++) { if (s1[i] - s2[i] == 1 || (s1[i] - s2[i] == -2)) sum += 1; else if ((s1[i] - s2[i] == -1) || (s1[i] - s2[i] == 2)) sum -= 1; } if (sum > 0) printf( TEAM 1 WINS n ); else if (sum < 0) printf( TEAM 2 WINS n ); else printf( TIE n ); } return 0; } |
#include <bits/stdc++.h> #define ll long long #define mod 1000000007 using namespace std; ll dp[10][200001]; string s = abcdefghijklmnopqrstuvwxyz ; ll findgcd(ll a, ll b) { if (b == 0) { return a; } return findgcd(b, a % b); } bool ispalindrome(string s) { int n = s.length(); bool flag = true; for (int i = 0; i < n / 2; i++) { if (s[i] != s[n - 1 - i]) { flag = false; break; } } return flag; } ll factorial(ll n) { vector<ll> v(n + 1); for (ll i = 0; i <= n; i++) { if (i == 0 || i == 1) { v[i] = 1; } else { v[i] = (i * v[i - 1]) % mod; } } return v[n]; } void calculatedp() { for (ll i = 0; i <= 9; i++) { ll temp = 10 - i; for (ll j = 0; j <= 200000; j++) { if (j < temp) { dp[i][j] = 1; } else if (j == temp) { dp[i][j] = 2; } else { break; } } } dp[1][10] = 2; for (ll i = 11; i <= 200000; i++) { int temp1 = i - 10; int temp2 = i - 9; dp[0][i] = (dp[0][temp1] + dp[1][temp1]) % mod; dp[1][i] = (dp[0][temp2] + dp[1][temp2]) % mod; } for (ll i = 2; i <= 9; i++) { ll temp = 10 - i; for (ll j = temp + 1; j <= 200000; j++) { dp[i][j] = (dp[0][j - temp] + dp[1][j - temp]) % mod; } } } void solve() { // ll m; // cin >> s; // cin >> m; // ll ans = 0; // for (int i = 0; i < s.length(); i++) { // ans = (ans + (dp[s[i] - 0 ][m])) % mod; // } // cout << ans << n ; int n, k; cin >> n >> k; string ans = ; for (int i = 0 ; i < k ; i++) { ans += s[i]; for (int j = i + 1 ; j < k ; j++) { ans += s[i]; ans += s[j]; } } if (n < ans.size()) { cout << ans.substr(0, n) << endl; } else { int j = ans.length(); int i = 0; while (j < n) { ans += ans[i]; i++; j++; } cout << ans << endl; } } int main() { #ifndef ONLINE_JUDGE //for getting input from input.txt freopen( input.txt , r , stdin); //for writing output to output.txt freopen( output.txt , w , stdout); #endif ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); // calculatedp(); // for (int i = 0; i <= 10; i++) { // for (int j = 0; j <= 10; j++) { // cout << dp[i][j] << ; // } // cout << n ; // } int t; t = 1; // cin >> t; while (t--) { solve(); } } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_alu(
input sys_clk,
input alu_rst,
input [31:0] a,
input [31:0] b,
input ifb,
input [3:0] opcode,
output [31:0] r,
output r_valid,
output reg dma_en,
output err_collision
);
/* Compensate for the latency cycle of the register file SRAM. */
reg [3:0] opcode_r;
always @(posedge sys_clk) begin
if(alu_rst)
opcode_r <= 4'd0;
else
opcode_r <= opcode;
end
/* Detect VECTOUT opcodes and trigger DMA */
always @(posedge sys_clk) begin
if(alu_rst)
dma_en <= 1'b0;
else
dma_en <= opcode == 4'h7;
end
/* Computation units */
wire faddsub_valid;
wire [31:0] r_faddsub;
pfpu_faddsub u_faddsub(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.b(b),
.sub(~opcode_r[0]),
.valid_i((opcode_r == 4'h1) | (opcode_r == 4'h2)),
.r(r_faddsub),
.valid_o(faddsub_valid)
);
wire fmul_valid;
wire [31:0] r_fmul;
pfpu_fmul u_fmul(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.b(b),
.valid_i(opcode_r == 4'h3),
.r(r_fmul),
.valid_o(fmul_valid)
);
wire tsign_valid;
wire [31:0] r_tsign;
pfpu_tsign u_tsign(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.b(b),
.tsign(opcode_r[3]),
.valid_i((opcode_r == 4'h4) | (opcode_r == 4'he)),
.r(r_tsign),
.valid_o(tsign_valid)
);
wire f2i_valid;
wire [31:0] r_f2i;
pfpu_f2i u_f2i(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.valid_i(opcode_r == 4'h5),
.r(r_f2i),
.valid_o(f2i_valid)
);
wire i2f_valid;
wire [31:0] r_i2f;
pfpu_i2f u_i2f(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.valid_i(opcode_r == 4'h6),
.r(r_i2f),
.valid_o(i2f_valid)
);
wire sincos_valid;
wire [31:0] r_sincos;
pfpu_sincos u_sincos(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.cos(opcode_r[0]),
.valid_i((opcode_r == 4'h8) | (opcode_r == 4'h9)),
.r(r_sincos),
.valid_o(sincos_valid)
);
wire above_valid;
wire [31:0] r_above;
pfpu_above u_above(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.b(b),
.valid_i(opcode_r == 4'ha),
.r(r_above),
.valid_o(above_valid)
);
wire equal_valid;
wire [31:0] r_equal;
pfpu_equal u_equal(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.b(b),
.valid_i(opcode_r == 4'hb),
.r(r_equal),
.valid_o(equal_valid)
);
wire copy_valid;
wire [31:0] r_copy;
pfpu_copy u_copy(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.valid_i(opcode_r == 4'hc),
.r(r_copy),
.valid_o(copy_valid)
);
wire if_valid;
wire [31:0] r_if;
pfpu_if u_if(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.b(b),
.ifb(ifb),
.valid_i(opcode_r == 4'hd),
.r(r_if),
.valid_o(if_valid)
);
wire quake_valid;
wire [31:0] r_quake;
pfpu_quake u_quake(
.sys_clk(sys_clk),
.alu_rst(alu_rst),
.a(a),
.valid_i(opcode_r == 4'hf),
.r(r_quake),
.valid_o(quake_valid)
);
/* Generate output */
assign r =
({32{faddsub_valid}} & r_faddsub)
|({32{fmul_valid}} & r_fmul)
|({32{tsign_valid}} & r_tsign)
|({32{f2i_valid}} & r_f2i)
|({32{i2f_valid}} & r_i2f)
|({32{sincos_valid}} & r_sincos)
|({32{above_valid}} & r_above)
|({32{equal_valid}} & r_equal)
|({32{copy_valid}} & r_copy)
|({32{if_valid}} & r_if)
|({32{quake_valid}} & r_quake);
assign r_valid =
faddsub_valid
|fmul_valid
|tsign_valid
|f2i_valid
|i2f_valid
|sincos_valid
|above_valid
|equal_valid
|copy_valid
|if_valid
|quake_valid;
assign err_collision =
(faddsub_valid & (fmul_valid|tsign_valid|f2i_valid|i2f_valid|sincos_valid|above_valid|equal_valid|copy_valid|if_valid|quake_valid))
|(fmul_valid & (tsign_valid|f2i_valid|i2f_valid|sincos_valid|above_valid|equal_valid|copy_valid|if_valid|quake_valid))
|(tsign_valid & (f2i_valid|i2f_valid|sincos_valid|above_valid|equal_valid|copy_valid|if_valid|quake_valid))
|(f2i_valid & (i2f_valid|sincos_valid|above_valid|equal_valid|copy_valid|if_valid|quake_valid))
|(i2f_valid & (sincos_valid|above_valid|equal_valid|copy_valid|if_valid|quake_valid))
|(sincos_valid & (above_valid|equal_valid|copy_valid|if_valid|quake_valid))
|(above_valid & (equal_valid|copy_valid|if_valid|quake_valid))
|(equal_valid & (copy_valid|if_valid|quake_valid))
|(copy_valid & (if_valid|quake_valid))
|(if_valid & (quake_valid));
endmodule
|
#include <bits/stdc++.h> int len, p; char s[111111], buf[111111]; void add(char ch) { buf[len++] = ch; } void out() { printf( < ); for (int i = 0; i < len; i++) printf( %c , buf[i]); printf( > n ); len = 0; } int main() { gets(s); len = p = 0; for (p = 0; s[p]; p++) { if (s[p] == ) { p++; while (s[p] != ) { add(s[p]); p++; } out(); } else if (s[p] == ) { if (len) out(); } else add(s[p]); } if (len) out(); return 0; } |
#include <bits/stdc++.h> const int p = 998244353; const int inv2 = 499122177; const int MAXN = 140000; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch > 9 || ch < 0 ) { if (ch == - ) f = -1; ch = getchar(); } do x = (x * 10 + ch - 48) % p, ch = getchar(); while (ch >= 0 && ch <= 9 ); return (x * f % p + p) % p; } int n, k, r[MAXN]; long long c[MAXN] = {1, 6, 1}; long long s[MAXN], f[MAXN], g[MAXN]; long long fastpow(long long a, int b) { long long res = 1; a %= p; while (b) { if (b & 1) res = res * a % p; a = a * a % p; b >>= 1; } return res; } void NTT(long long *a, int N) { for (int i = 0; i < N; i++) if (i < r[i]) std::swap(a[i], a[r[i]]); for (int n = 2, m = 1; n <= N; m = n, n <<= 1) { long long g1 = fastpow(3, (p - 1) / n); for (int l = 0; l < N; l += n) { long long g = 1, t1, t2; for (int i = l; i < l + m; i++) { t1 = a[i], t2 = g * a[i + m] % p; a[i] = (t1 + t2) % p; a[i + m] = (t1 - t2 + p) % p; g = g * g1 % p; } } } return; } void INTT(long long *a, int N) { NTT(a, N); std::reverse(a + 1, a + N); int invN = fastpow(N, p - 2); for (int i = 0; i < N; i++) a[i] = a[i] * invN % p; } long long a1[MAXN], b1[MAXN]; void Inv(long long *a, long long *b, int n) { if (n == 1) return void(b[0] = fastpow(a[0], p - 2)); Inv(a, b, (n + 1) >> 1); int N = 1, l = -1; while (N <= n << 1) N <<= 1, l++; for (int i = 1; i < N; i++) r[i] = (r[i >> 1] >> 1) | ((i & 1) << l); for (int i = 0; i < n; i++) a1[i] = a[i]; for (int i = n; i < N; i++) a1[i] = 0; NTT(a1, N); NTT(b, N); for (int i = 0; i < N; i++) b[i] = ((b[i] << 1) % p + p - a1[i] * b[i] % p * b[i] % p) % p; INTT(b, N); for (int i = n; i < N; i++) b[i] = 0; return; } void Dervt(long long *a, long long *b, int n) { for (int i = 1; i < n; i++) b[i - 1] = a[i] * i % p; b[n - 1] = 0; } void Integ(long long *a, long long *b, int n) { for (int i = 1; i < n; i++) b[i] = a[i - 1] * fastpow(i, p - 2) % p; b[0] = 0; } long long f1[MAXN], f2[MAXN]; void Ln(long long *f, long long *g, int n) { memset(f1, 0, sizeof(f1)); memset(f2, 0, sizeof(f2)); Dervt(f, f1, n); Inv(f, f2, n); int N = 1, l = -1; while (N <= n << 1) N <<= 1, l++; for (int i = 1; i < N; i++) r[i] = (r[i >> 1] >> 1) | ((i & 1) << l); NTT(f1, N); NTT(f2, N); for (int i = 0; i < N; i++) f1[i] = f1[i] * f2[i] % p; INTT(f1, N); Integ(f1, g, n); return; } long long g1[MAXN]; void Exp(long long *f, long long *g, int n) { if (n == 1) return void(g[0] = 1); Exp(f, g, (n + 1) >> 1); Ln(g, g1, n); int N = 1, l = -1; while (N <= n << 1) N <<= 1, l++; for (int i = 1; i < N; i++) r[i] = (r[i >> 1] >> 1) | ((i & 1) << l); for (int i = 0; i < n; i++) f1[i] = f[i]; for (int i = n; i < N; i++) g1[i] = f1[i] = 0; for (int i = 0; i < N; i++) f1[i] = ((f1[i] - g1[i]) % p + p) % p; f1[0] = (f1[0] + 1) % p; NTT(f1, N); NTT(g, N); for (int i = 0; i < N; i++) g[i] = f1[i] * g[i] % p; INTT(g, N); for (int i = n; i < N; i++) g[i] = 0; return; } long long lnf[MAXN]; void Pow(long long *f, long long *g, int n, int k) { Ln(f, lnf, n); for (int i = 0; i < n; i++) lnf[i] = lnf[i] * k % p; memset(g, 0, sizeof(g1)); Exp(lnf, g, n); return; } int main() { n = read(); int t = read(); k = std::min(n, t); int N = 1, l = -1; while (N <= (k + 1) << 1) N <<= 1, l++; for (int i = 1; i < N; i++) r[i] = (r[i >> 1] >> 1) | ((i & 1) << l); Pow(c, s, k + 1, inv2 - 1); Pow(c, f, k + 1, inv2); f[0]++, f[1]++; for (int i = 0; i <= k; i++) f[i] = f[i] * inv2 % p; Pow(f, g, k + 1, n + 1); NTT(s, N); NTT(g, N); for (int i = 0; i < N; i++) s[i] = s[i] * g[i] % p; INTT(s, N); for (int i = 1; i <= k; i++) std::printf( %lld , s[i]); for (int i = k + 1; i <= t; i++) std::printf( 0 ); std::putchar( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; inline void Fail() { printf( 0 ); exit(0); } const int maxn = 100005; int n, l, r, mn, id, ans, from, to, cnt, clen, mxdep, mid; vector<pair<int, int> > edge[maxn]; pair<int, pair<int, int> > cur[maxn]; vector<int> beauty; int sz[maxn], u[maxn], v[maxn], c[maxn], cen[maxn][25], total[maxn][25]; bool centroid[maxn], debug; class segtree { public: pair<int, int> tree[maxn * 4]; int sz; void _init(int tot) { for (sz = 1; sz < tot; sz <<= 1) ; for (int(i) = 0; (i) < sz << 1; i++) tree[i] = make_pair(-1e9, -1); } void upd(int pos, int val, int id) { pos += sz - 1; tree[pos] = max(tree[pos], make_pair(val, id)); while (pos) { pos >>= 1; if (!pos) break; tree[pos] = max(tree[pos << 1], tree[pos << 1 | 1]); } } void clr(int pos) { pos += sz - 1; tree[pos] = make_pair(-1e9, -1); while (pos) { pos >>= 1; if (!pos) break; tree[pos] = max(tree[pos << 1], tree[pos << 1 | 1]); } } pair<int, int> qry(int l, int r) { if (r < 1) return make_pair(-1e9, -1); l = max(l, 1); r = min(r, sz); l += sz - 1; r += sz - 1; pair<int, int> res = make_pair(-1e9, -1); for (; l <= r; l >>= 1, r >>= 1) { if (l & 1) res = max(res, tree[l++]); if ((r - 1) & 1) res = max(res, tree[r--]); } return res; } } T; void get_sz(int x, int p) { sz[x] = 1; for (int(i) = 0; (i) < edge[x].size(); i++) { pair<int, int> y = edge[x][i]; if (centroid[y.first] || y.first == p) continue; get_sz(y.first, x); sz[x] += sz[y.first]; } } void get_centroid(int x, int p, int tot) { int mx = tot - sz[x]; for (int(i) = 0; (i) < edge[x].size(); i++) { pair<int, int> y = edge[x][i]; if (centroid[y.first] || y.first == p) continue; get_centroid(y.first, x, tot); mx = max(mx, sz[y.first]); } if (mx < mn) { mn = mx; id = x; } } void get_dis(int x, int p, int dep, int dis, int s) { mxdep = max(mxdep, dep); cur[clen++] = make_pair(dep, make_pair(dis, x)); pair<int, int> mx = T.qry(l - dep + 1, r - dep + 1); if (dis + mx.first > ans) { ans = dis + mx.first; from = x; to = mx.second; } for (int(i) = 0; (i) < edge[x].size(); i++) { pair<int, int> y = edge[x][i]; if (centroid[y.first] || y.first == p) continue; get_dis(y.first, x, dep + 1, dis + (y.second >= mid ? 1 : -1), s); } } void solve(int t, int dep) { int s = cen[t][dep]; if (s < 0) { mn = 1e9; get_sz(t, -1); get_centroid(t, -1, sz[t]); s = id; cen[t][dep] = s; total[t][dep] = sz[t]; } centroid[s] = true; T._init(total[t][dep] + 1); T.upd(1, 0, s); for (int(i) = 0; (i) < edge[s].size(); i++) { if (centroid[edge[s][i].first]) continue; clen = 0; get_dis(edge[s][i].first, s, 1, edge[s][i].second >= mid ? 1 : -1, s); for (int(j) = 0; (j) < clen; j++) { T.upd(cur[j].first + 1, cur[j].second.first, cur[j].second.second); } } for (int(i) = 0; (i) < edge[s].size(); i++) if (!centroid[edge[s][i].first]) solve(edge[s][i].first, dep + 1); centroid[s] = false; } void add_edge(int x, int y, int z) { edge[x].push_back(make_pair(y, z)); edge[y].push_back(make_pair(x, z)); } bool check() { ans = -1e9; solve(0, 0); return ans >= 0; } int main() { memset(cen, -1, sizeof(cen)); scanf( %d%d%d , &n, &l, &r); for (int(i) = 0; (i) < n - 1; i++) { scanf( %d%d%d , &u[i], &v[i], &c[i]); u[i]--, v[i]--; add_edge(u[i], v[i], c[i]); beauty.push_back(c[i]); } sort(beauty.begin(), beauty.end()); beauty.resize(unique(beauty.begin(), beauty.end()) - beauty.begin()); int L = 0, R = beauty.size(); while (R - L > 1) { int Mid = (L + R) >> 1; mid = beauty[Mid]; if (check()) L = Mid; else R = Mid; } debug = true; mid = beauty[L]; check(); printf( %d %d , from + 1, to + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, d[1002], s[1002], t, f, sum, k; int main() { cin >> m >> k; for (int i = 2; i <= m + 1; i++) { cin >> d[i]; } for (int i = 1; i <= m; i++) { cin >> s[i]; } for (int i = 1; i <= m; i++) { f += s[i]; t = max(t, s[i]); while (f < d[i + 1]) { sum += k, f += t; } sum += d[i + 1], f -= d[i + 1]; } cout << sum; } |
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } long long dx[4] = {0, 0, -1, 1}; long long dy[4] = {1, -1, 0, 0}; int n, m, q; char s[11]; long long bz[100010 << 1][52]; int pos[100010 << 1][52]; int head[100010 << 1], nex[100010 << 1], val[100010 << 1], op[100010 << 1], tot; int T[100010 << 2]; void pushdown(int rt) { if (T[rt]) { T[rt << 1] = T[rt << 1 | 1] = T[rt]; T[rt] = 0; } } void insert(int l, int r, int rt, int x, int y, int v) { if (x <= l && r <= y) { T[rt] = v; return; } int mid = l + r >> 1; pushdown(rt); if (mid >= x) insert(l, mid, rt << 1, x, y, v); if (mid < y) insert(mid + 1, r, rt << 1 | 1, x, y, v); } int query(int l, int r, int rt, int v) { if (l == r) return T[rt]; int mid = l + r >> 1; pushdown(rt); if (mid >= v) return query(l, mid, rt << 1, v); else return query(mid + 1, r, rt << 1 | 1, v); } void add(long long x, long long y, int tp) { tot++; nex[tot] = head[x]; head[x] = tot; val[tot] = y; op[tot] = tp; } struct vec { long long x1, x2, y1, y2; int op; void read() { scanf( %I64d%I64d%I64d%I64d , &x1, &y1, &x2, &y2); if (y1 < y2) op = 0; if (y1 > y2) op = 1; if (x1 > x2) op = 2; if (x1 < x2) op = 3; } } a[100010]; struct node { int op; long long len, x, y; void read() { scanf( %I64d%I64d%s%I64d , &x, &y, s, &len); if (s[0] == U ) op = 0; if (s[0] == D ) op = 1; if (s[0] == L ) op = 2; if (s[0] == R ) op = 3; } } b[100010]; pair<long long, long long> cal(long long x, long long y, int p) { if (a[p].x1 == a[p].x2) { if (a[p].x1 == x) { if (min(a[p].y1, a[p].y2) <= y && y <= max(a[p].y1, a[p].y2)) return make_pair(x, y); if (y < min(a[p].y1, a[p].y2)) return make_pair(x, min(a[p].y1, a[p].y2)); else return make_pair(x, max(a[p].y1, a[p].y2)); } else return make_pair(a[p].x1, y); } else { if (a[p].y1 == y) { if (min(a[p].x1, a[p].x2) <= x && x <= max(a[p].x1, a[p].x2)) return make_pair(x, y); if (x < min(a[p].x1, a[p].x2)) return make_pair(min(a[p].x1, a[p].x2), y); else return make_pair(max(a[p].x1, a[p].x2), y); } else return make_pair(x, a[p].y1); } } int dis(long long x1, long long y1, long long x2, long long y2) { return abs(x1 - x2) + abs(y1 - y2); } pair<long long, long long> find(long long x, long long y, int tp, long long step) { return make_pair(x + step * dx[tp], y + step * dy[tp]); } void print(pair<long long, long long> p) { long long x = p.first, y = p.second; x = max(x, 0ll); x = min(x, (long long)m); y = max(y, 0ll); y = min(y, (long long)m); printf( %I64d %I64d n , x, y); } int main() { n = read(); m = read(); for (int i = 1; i <= n; i++) a[i].read(); q = read(); for (int i = 1; i <= q; i++) b[i].read(); for (int i = 0; i <= 3; i++) { tot = 0; memset(head, 0, sizeof(head)); memset(T, 0, sizeof(T)); for (int j = 1; j <= q; j++) if (b[j].op == i) { if (i < 2) add(b[j].y, j + n, 1); else add(b[j].x, j + n, 1); } for (int j = 1; j <= n; j++) { if (i == 0) add(max(a[j].y1, a[j].y2), j, 0); if (i == 1) add(min(a[j].y1, a[j].y2), j, 0); if (i == 2) add(min(a[j].x1, a[j].x2), j, 0); if (i == 3) add(max(a[j].x1, a[j].x2), j, 0); } for (int j = 1; j <= n; j++) if (a[j].op == i) { if (i < 2) add(a[j].y2, j, 1); else add(a[j].x2, j, 1); } int now = (i == 0 || i == 3) ? m : 0; while (now != -1 && now != m + 1) { for (int j = head[now]; j; j = nex[j]) { if (!op[j]) { if (i < 2) insert(0, m, 1, min(a[val[j]].x1, a[val[j]].x2), max(a[val[j]].x1, a[val[j]].x2), val[j]); else insert(0, m, 1, min(a[val[j]].y1, a[val[j]].y2), max(a[val[j]].y1, a[val[j]].y2), val[j]); } else { int tmp; if (val[j] <= n) { if (i < 2) tmp = query(0, m, 1, a[val[j]].x1); else tmp = query(0, m, 1, a[val[j]].y1); } else { if (i < 2) tmp = query(0, m, 1, b[val[j] - n].x); else tmp = query(0, m, 1, b[val[j] - n].y); } pos[val[j]][0] = tmp; if (tmp) { if (val[j] <= n) bz[val[j]][0] = abs(a[tmp].x2 - a[val[j]].x2) + abs(a[tmp].y2 - a[val[j]].y2); else bz[val[j]][0] = abs(a[tmp].x2 - b[val[j] - n].x) + abs(a[tmp].y2 - b[val[j] - n].y); } else bz[val[j]][0] = 1ll << 50; } } if (i == 0 || i == 3) now--; else now++; } } for (int i = 1; i <= 50; i++) bz[0][i] = 1ll << 50; for (int i = 1; i <= 50; i++) for (int j = 1; j <= n + q; j++) { pos[j][i] = pos[pos[j][i - 1]][i - 1]; bz[j][i] = bz[j][i - 1] + bz[pos[j][i - 1]][i - 1]; bz[j][i] = min(bz[j][i], 1ll << 50); } for (int i = 1; i <= q; i++) { int tmp = i + n; long long t = b[i].len; for (int j = 50; j >= 0; j--) if (bz[tmp][j] <= t) { t -= bz[tmp][j]; tmp = pos[tmp][j]; } if (tmp == i + n) { if (pos[tmp][0]) { pair<long long, long long> tq = cal(b[i].x, b[i].y, pos[tmp][0]); int tw = dis(tq.first, tq.second, b[i].x, b[i].y); if (tw >= t) print(find(b[i].x, b[i].y, b[i].op, t)); else print(find(tq.first, tq.second, a[pos[tmp][0]].op, t - tw)); } else print(find(b[i].x, b[i].y, b[i].op, t)); } else { if (!pos[tmp][0]) print(find(a[tmp].x2, a[tmp].y2, a[tmp].op, t)); else { pair<long long, long long> tq = cal(a[tmp].x2, a[tmp].y2, pos[tmp][0]); int tw = dis(tq.first, tq.second, a[tmp].x2, a[tmp].y2); if (tw >= t) print(find(a[tmp].x2, a[tmp].y2, a[tmp].op, t)); else print(find(tq.first, tq.second, a[pos[tmp][0]].op, t - tw)); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; string a, b, c, d; int pref[123456]; int main() { int n, k; cin >> n >> k; string s; cin >> s; s = . + s; for (int i = 1; i < s.length(); i++) { pref[i] = pref[i - 1]; if (s[i] == 0 ) pref[i]++; } int ans = INT_MAX; for (int i = 1; i < s.length(); i++) { if (s[i] == 0 ) { int lo = k / 2; int hi = s.length() - 1; while (hi - lo > 2) { int mid = (lo + hi) / 2; int lft = max(0, i - mid); int cccc = s.length() - 1; int rt = min(cccc, i + mid); if (pref[rt] - pref[lft - 1] < k + 1) lo = mid; else hi = mid; } while (lo <= hi) { int lft = max(0, i - lo); int cccc = s.length() - 1; int rt = min(cccc, i + lo); if (pref[rt] - pref[lft - 1] < k + 1) lo++; if (pref[rt] - pref[lft - 1] >= k + 1) break; } ans = min(ans, lo); } } cout << ans; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_hstl_pad.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// HSTL PAD
*/
////////////////////////////////////////////////////////////////////////
`include "sys.h"
module bw_io_hstl_pad(so ,obsel ,clock_dr ,vref ,update_dr ,clk ,reset_l
,hiz_l ,shift_dr ,rst_io_l ,rst_val_up ,bso ,bsr_si ,
rst_val_dn ,mode_ctl ,si ,oe ,data ,se ,to_core ,por_l ,pad ,
sel_bypass ,ckd, vddo );
input [5:4] obsel ;
output so ;
output bso ;
output to_core ;
input clock_dr ;
input vref ;
input update_dr ;
input clk ;
input reset_l ;
input hiz_l ;
input shift_dr ;
input rst_io_l ;
input rst_val_up ;
input bsr_si ;
input rst_val_dn ;
input mode_ctl ;
input si ;
input oe ;
input data ;
input se ;
input por_l ;
input sel_bypass ;
input ckd ;
inout pad ;
input vddo ;
supply1 vdd ;
supply0 vss ;
wire cmsi_clk_en_l ;
wire se_buf ;
wire net199 ;
wire q_up_pad ;
wire bsr_dn_l ;
wire q_dn_pad_l ;
wire rcvr_data_to_bsr ;
wire pad_clk_en_l ;
wire por ;
wire bsr_data_to_core ;
wire sel_data_n ;
wire cmsi_l ;
wire pad_up ;
wire bsr_up ;
wire pad_dn_l ;
bw_io_dtlhstl_rcv I1 (
.pad_clk_en_l (pad_clk_en_l ),
.pad (pad ),
.clk (clk ),
.cmsi_l (cmsi_l ),
.ref (vref ),
.cmsi_clk_en_l (cmsi_clk_en_l ),
.so (so ),
.se_buf (se_buf ),
.out (to_core ),
.vddo (vddo) );
bw_io_hstl_edgelogic I2 (
.obsel ({obsel } ),
.ckd (ckd ),
.bsr_up (q_up_pad ),
.bsr_dn_l (q_dn_pad_l ),
.pad_dn_l (pad_dn_l ),
.pad_up (pad_up ),
.oe (oe ),
.data (data ),
.clk (clk ),
.por_l (por_l ),
.se (se ),
.bsr_mode (mode_ctl ),
.sel_bypass (sel_bypass ),
.reset_l (reset_l ),
.por (por ),
.si (si ),
.bsr_data_to_core (bsr_data_to_core ),
.cmsi_clk_en_l (cmsi_clk_en_l ),
.cmsi_l (cmsi_l ),
.pad_clk_en_l (pad_clk_en_l ),
.se_buf (se_buf ) );
bw_io_hstl_drv I3 (
.cbu ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.cbd ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.por (por ),
.bsr_dn_l (bsr_dn_l ),
.bsr_up (bsr_up ),
.pad_dn_l (pad_dn_l ),
.sel_data_n (sel_data_n ),
.pad_up (pad_up ),
.pad (pad ),
.vddo (vddo) );
bw_io_dtl_bscan bscan (
.bsr_data_to_core (bsr_data_to_core ),
.hiz_l (hiz_l ),
.rst_io_l (rst_io_l ),
.rst_val_dn (rst_val_dn ),
.rst_val_up (rst_val_up ),
.shift_dr (shift_dr ),
.clock_dr (clock_dr ),
.update_dr (update_dr ),
.up_open (vdd ),
.bsr_so (bso ),
.se (se ),
.mode_ctl (mode_ctl ),
.bsr_si (bsr_si ),
.q_up_mux (bsr_up ),
.down_25 (vss ),
.sel_data_n (sel_data_n ),
.rcvr_data_to_bsr (rcvr_data_to_bsr ),
.q25_dn_pad_l (vdd ),
.q_dn_pad_l (q_dn_pad_l ),
.q_dn_mux_l (bsr_dn_l ),
.q25_dn_mux_l (net199 ),
.q_up_pad (q_up_pad ),
.serial_out (),
.bypass_enable (vss),
.clk (vss),
.bypass_in (vss),
.serial_in (vss),
.ps_select (vss),
.out_type (vss) );
bw_io_schmitt I41 (
.vddo (vddo ),
.out (rcvr_data_to_bsr ),
.in (pad ) );
endmodule
|
/* Copyright 2005-2006, Technologic Systems
* All Rights Reserved.
*
* Author(s): Jesse Off <>
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License v2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
module wb32_blockram(
wb_clk_i,
wb_rst_i,
wb1_adr_i,
wb1_dat_i,
wb1_dat_o,
wb1_cyc_i,
wb1_stb_i,
wb1_ack_o,
wb1_we_i,
wb1_sel_i,
wb2_adr_i,
wb2_dat_i,
wb2_dat_o,
wb2_cyc_i,
wb2_stb_i,
wb2_ack_o,
wb2_we_i,
wb2_sel_i
);
input wb_clk_i, wb_rst_i;
input [10:0] wb1_adr_i, wb2_adr_i;
input [31:0] wb1_dat_i, wb2_dat_i;
input wb1_cyc_i, wb2_cyc_i, wb1_stb_i, wb2_stb_i, wb1_we_i, wb2_we_i;
input [3:0] wb1_sel_i, wb2_sel_i;
output [31:0] wb1_dat_o, wb2_dat_o;
output reg wb1_ack_o, wb2_ack_o;
/* Set if wb1 and wb2 are opposite endianness */
parameter endian_swap = 1'b0;
reg [31:0] blockram_data_i;
reg [10:0] blockram_rdadr_i, blockram_wradr_i;
wire [31:0] blockram_data_o;
reg [3:0] blockram_wren;
altera_ram blockram0(
.clock(wb_clk_i),
.data(blockram_data_i[7:0]),
.rdaddress(blockram_rdadr_i),
.wraddress(blockram_wradr_i),
.wren(blockram_wren[0]),
.q(blockram_data_o[7:0])
);
altera_ram blockram1(
.clock(wb_clk_i),
.data(blockram_data_i[15:8]),
.rdaddress(blockram_rdadr_i),
.wraddress(blockram_wradr_i),
.wren(blockram_wren[1]),
.q(blockram_data_o[15:8])
);
altera_ram blockram2(
.clock(wb_clk_i),
.data(blockram_data_i[23:16]),
.rdaddress(blockram_rdadr_i),
.wraddress(blockram_wradr_i),
.wren(blockram_wren[2]),
.q(blockram_data_o[23:16])
);
altera_ram blockram3(
.clock(wb_clk_i),
.data(blockram_data_i[31:24]),
.rdaddress(blockram_rdadr_i),
.wraddress(blockram_wradr_i),
.wren(blockram_wren[3]),
.q(blockram_data_o[31:24])
);
reg rdowner = 1'b0;
reg wrowner = 1'b0;
reg wb1_rdreq, wb2_rdreq, wb1_wrreq, wb2_wrreq;
always @(rdowner or wrowner or wb1_adr_i or wb2_adr_i or wb1_dat_i or
wb2_dat_i or wb1_sel_i or wb2_sel_i or rdowner or wrowner or
wb2_wrreq or wb1_wrreq or endian_swap) begin
if (rdowner) blockram_rdadr_i = wb2_adr_i;
else blockram_rdadr_i = wb1_adr_i;
blockram_wren = 4'b0000;
if (wrowner) begin
blockram_wradr_i = wb2_adr_i;
if (endian_swap) begin
blockram_data_i = {wb2_dat_i[7:0], wb2_dat_i[15:8], wb2_dat_i[23:16],
wb2_dat_i[31:24]};
if (wb2_wrreq) blockram_wren = {wb2_sel_i[0], wb2_sel_i[1], wb2_sel_i[2],
wb2_sel_i[3]};
end else begin
blockram_data_i = wb2_dat_i;
if (wb2_wrreq) blockram_wren = wb2_sel_i;
end
end else begin
blockram_wradr_i = wb1_adr_i;
blockram_data_i = wb1_dat_i;
if (wb1_wrreq) blockram_wren = wb1_sel_i;
end
end
assign wb1_dat_o = blockram_data_o;
assign wb2_dat_o = endian_swap ? {blockram_data_o[7:0],
blockram_data_o[15:8], blockram_data_o[23:16], blockram_data_o[31:24]} :
blockram_data_o;
always @(wb1_cyc_i or wb1_stb_i or wb1_we_i or wb_rst_i or
wb2_cyc_i or wb2_stb_i or wb2_we_i or rdowner or wrowner or
wb1_ack_o or wb2_ack_o) begin
wb1_rdreq = wb1_cyc_i && wb1_stb_i && !wb1_we_i && !wb1_ack_o;
wb2_rdreq = wb2_cyc_i && wb2_stb_i && !wb2_we_i && !wb2_ack_o;
wb1_wrreq = wb1_cyc_i && wb1_stb_i && wb1_we_i && !wb1_ack_o;
wb2_wrreq = wb2_cyc_i && wb2_stb_i && wb2_we_i && !wb2_ack_o;
if (rdowner) begin
if (wb1_rdreq && !wb2_rdreq) rdowner = 1'b0;
else rdowner = 1'b1;
end else begin
if (!wb1_rdreq && wb2_rdreq) rdowner = 1'b1;
else rdowner = 1'b0;
end
if (wrowner) begin
if (wb1_wrreq && !wb2_wrreq) wrowner = 1'b0;
else wrowner = 1'b1;
end else begin
if (!wb1_wrreq && wb2_wrreq) wrowner = 1'b1;
else wrowner = 1'b0;
end
if (wb_rst_i) begin
rdowner = 1'b0;
wrowner = 1'b0;
end
end
always @(posedge wb_clk_i) begin
wb1_ack_o <= 1'b0;
wb2_ack_o <= 1'b0;
if (wb1_rdreq && !rdowner && !wb1_ack_o) begin
wb1_ack_o <= 1'b1;
end else if (wb2_rdreq && rdowner && !wb2_ack_o) begin
wb2_ack_o <= 1'b1;
end
if (wb1_wrreq && !wrowner && !wb1_ack_o) begin
wb1_ack_o <= 1'b1;
end else if (wb2_wrreq && wrowner && !wb2_ack_o) begin
wb2_ack_o <= 1'b1;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { long long n; int m; cin >> n >> m; long long cnt = 0; if (m == 1) { cout << n * n << endl; return 0; } if (m < n) { for (int i = 1; i <= m; i++) for (int j = 1; j <= m; j++) if ((i * i + j * j) % m == 0) cnt++; long long mul = n / m; mul = mul * mul; cnt *= mul; long long index = (n / m) * m; index++; if (index <= n) { long long cnt1 = 0; for (long long i = index; i <= n; i++) for (long long j = 1; j <= m; j++) { long long i1 = i % m; long long j1 = j % m; if ((i1 * i1 + j1 * j1) % m == 0) cnt1++; } mul = n / m; mul *= 2; cnt1 *= mul; cnt += cnt1; for (long long i = index; i <= n; i++) for (long long j = index; j <= n; j++) { long long i1 = i % m; long long j1 = j % m; if ((i1 * i1 + j1 * j1) % m == 0) cnt++; } } } else { for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if ((i * i + j * j) % m == 0) cnt++; } cout << cnt << endl; return 0; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire [3:0] sw,
input wire [3:0] btn,
output wire led0_r,
output wire led0_g,
output wire led0_b,
output wire led1_r,
output wire led1_g,
output wire led1_b,
output wire led2_r,
output wire led2_g,
output wire led2_b,
output wire led3_r,
output wire led3_g,
output wire led3_b,
output wire led4,
output wire led5,
output wire led6,
output wire led7,
/*
* Ethernet: 100BASE-T MII
*/
output wire phy_ref_clk,
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
input wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_en,
input wire phy_col,
input wire phy_crs,
output wire phy_reset_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
wire clk_bufg;
wire clk_mmcm_out;
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire mmcm_rst = ~reset_n;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
wire clk_25mhz_mmcm_out;
wire clk_25mhz_int;
// MMCM instance
// 100 MHz in, 125 MHz out
// PFD range: 10 MHz to 550 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
// Divide by 40 to get output frequency of 25 MHz
// 1000 / 5 = 200 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(40),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(10),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(10.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(clk_25mhz_mmcm_out),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
BUFG
clk_25mhz_bufg_inst (
.I(clk_25mhz_mmcm_out),
.O(clk_25mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.out(rst_int)
);
// GPIO
wire [3:0] btn_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(8),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btn,
sw}),
.out({btn_int,
sw_int})
);
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
assign phy_ref_clk = clk_25mhz_int;
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btn(btn_int),
.sw(sw_int),
.led0_r(led0_r),
.led0_g(led0_g),
.led0_b(led0_b),
.led1_r(led1_r),
.led1_g(led1_g),
.led1_b(led1_b),
.led2_r(led2_r),
.led2_g(led2_g),
.led2_b(led2_b),
.led3_r(led3_r),
.led3_g(led3_g),
.led3_b(led3_b),
.led4(led4),
.led5(led5),
.led6(led6),
.led7(led7),
/*
* Ethernet: 100BASE-T MII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd),
.phy_rx_dv(phy_rx_dv),
.phy_rx_er(phy_rx_er),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_en(phy_tx_en),
.phy_col(phy_col),
.phy_crs(phy_crs),
.phy_reset_n(phy_reset_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { if (a < b) swap(a, b); if (b == 0) return a; while ((a = a % b) != 0) { swap(a, b); } return b; } long long mpow(long long x, long long y, long long m) { long long res = 1; while (y > 0) { if (y & 1) res = res * x % m; y = y >> 1; x = x * x % m; } return res; } long long ncr(long long n, long long r) { if (r > n) return 0; long long res = 1; for (long long i = (1); i < (r + 1); i++) res = res * (n - r + i) / i; return res; } long long *sieve(long long n) { long long *lpf = new long long[n + 1]; for (long long i = 1; i <= n; i++) lpf[i] = i; long long rt = (long long)floor(sqrt(n)) + 1; for (long long i = (2); i < (rt); i++) { if (lpf[i] != i) continue; for (long long j = i * i; j <= n; j += i) { if (lpf[j] == j) lpf[j] = i; } } return lpf; } void solve() { long long n; cin >> n; long long a[n]; for (long long i = (0); i < (n); i++) cin >> a[i]; long long mx = *max_element(a, a + n), mn = *min_element(a, a + n); if (mx == mn) { if (mx != 0) cout << NO ; else { cout << YES n ; for (long long i = (0); i < (n); i++) cout << 1 ; } return; } long long k; for (long long i = (0); i < (n); i++) { long long prev = i - 1; if (prev == -1) prev = n - 1; if (a[i] == mx && a[prev] != mx) { k = i; break; } } long long pt = k; long long b[n]; b[pt] = mx; pt--; if (pt == -1) pt = n - 1; if (a[pt] == 0) b[pt] = mx * 2; else b[pt] = mx + a[pt]; pt--; if (pt == -1) pt = n - 1; while (pt != k) { b[pt] = b[(pt + 1) % n] + a[pt]; pt--; if (pt == -1) pt = n - 1; } cout << YES n ; for (long long i = (0); i < (n); i++) cout << b[i] << ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t = 1; for (long long i = (1); i < (t + 1); i++) { solve(); cout << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$NSR_pp$PG$N: Negative edge triggered D flip-flop
* (Q output UDP) with both active high reset and
* set (set dominate). Includes VPWR and VGND
* power pins and notifier pin.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N (
Q ,
SET ,
RESET ,
CLK_N ,
D ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input SET ;
input RESET ;
input CLK_N ;
input D ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_NSR_PP_PG_N_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int flag = 0; char s[6][6]; for (int i = 0; i < 4; i++) for (int j = 0; j < 4; j++) cin >> s[i][j]; for (int i = 0; i < 4; i++) { if (flag) break; for (int j = 0; j < 4; j++) { if (s[i][j] == x && s[i][j + 1] == x && (s[i][j + 2] == . || s[i][j - 1] == . )) { cout << YES ; flag = 1; break; } else if (s[i][j] == x && s[i][j + 1] == . && s[i][j + 2] == x ) { cout << YES ; flag = 1; break; } else if (s[i][j] == x && s[i + 1][j] == x && (s[i + 2][j] == . || s[i - 1][j] == . )) { cout << YES ; flag = 1; break; } else if (s[i][j] == x && s[i + 1][j] == . && s[i + 2][j] == x ) { cout << YES ; flag = 1; break; } else if (s[i][j] == x && s[i + 1][j + 1] == x && (s[i + 2][j + 2] == . || s[i - 1][j - 1] == . )) { cout << YES ; flag = 1; break; } else if (s[i][j] == x && s[i + 1][j + 1] == . && s[i + 2][j + 2] == x ) { cout << YES ; flag = 1; break; } else if (s[i][j] == x && s[i + 1][j - 1] == x && (s[i + 2][j - 2] == . || s[i - 1][j + 1] == . )) { cout << YES ; flag = 1; break; } else if (s[i][j] == x && s[i + 1][j - 1] == . && s[i + 2][j - 2] == x ) { cout << YES ; flag = 1; break; } } } if (!flag) cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, d, a, b; cin >> n >> d >> a >> b; vector<pair<long long, int> > v(n); for (int i = 0; i < n; i++) { long long x, y; cin >> x >> y; v[i].first = x * a + y * b; v[i].second = i + 1; } sort(v.begin(), v.end()); int ans = 0, sum = 0, pos = 0; for (int i = 0; i < n; i++) { if (sum + v[i].first <= d) { sum += v[i].first; ans++; pos = i; } } cout << ans << endl; if (ans) for (int i = 0; i <= pos; i++) cout << v[i].second << ; return 0; } |
#include <bits/stdc++.h> struct Edge { int u, v; int w; }; struct RowEdges { int sum; std::vector<Edge> vs; RowEdges() : sum(0) {} Edge &back() { return vs.back(); } Edge &front() { return vs.front(); } Edge &operator[](int i) { return vs[i]; } int size() { return (int)vs.size(); } void pop_back() { vs.pop_back(); } void push_back(Edge ae) { vs.push_back(ae); } bool operator<(RowEdges ot) const { return sum < ot.sum; } }; struct Graph { Graph(int n) : ves(n), vals(nullptr) {} ~Graph() { if (vals) { delete[] vals; vals = nullptr; } } void addTwoEdge(int a, int b, int awei = 0, int bwei = 0) { int minWei = std::min(awei, bwei); addEdge(a, b, minWei); addEdge(b, a, minWei); } void removeTwoEdge(int a, int b) { removeEdge(a, b); removeEdge(b, a); } void removeEdge(int a, int b) { auto &tv = ves[a]; for (int i = 0; i < (int)tv.size(); i++) { if (tv[i].v == b) { tv.sum -= std::min(vals[a], vals[b]); tv[i] = tv.back(); tv.pop_back(); break; } } } void addEdge(int a, int b, int addWeight = 0) { ves[a].push_back(Edge()); auto &bn = ves[a].back(); bn.u = a, bn.v = b; ves[a].sum += addWeight; } void sort(int off = 0) { std::sort(ves.begin() + off, ves.end()); std::vector<int> oldToNewId(ves.size()); std::vector<int> newToOldId(ves.size()); for (size_t i = off; i < ves.size(); i++) { if (ves[i].size()) { oldToNewId[ves[i].front().u] = i; newToOldId[i] = ves[i].front().u; } } for (size_t i = off; i < ves.size(); i++) { for (int j = 0; j < ves[i].size(); j++) { ves[i][j].u = oldToNewId[ves[i][j].u]; ves[i][j].v = oldToNewId[ves[i][j].v]; } } int n = ves.size(); int *varr = new int[n]; memcpy(varr, vals, n * sizeof(int)); for (int i = off; i < n; i++) { int j = newToOldId[i]; vals[i] = varr[j]; } delete[] varr; } int getAns() { int ans = 0; for (size_t i = 1; i < ves.size(); i++) { sort(i); if (ves[i].size()) { ans += ves[i].sum; while (ves[i].size()) { removeTwoEdge(i, ves[i].front().v); } } } return ans; } std::vector<RowEdges> ves; int *vals; }; int main() { int n = 0, m = 0, n1 = 0; scanf( %d %d , &n, &m); n1 = n + 1; int *v = new int[n1]; v[0] = 0; for (int i = 1; i < n1; i++) { scanf( %d , v + i); } Graph g(n1); g.vals = v; int a = 0, b = 0; for (int i = 0; i < m; i++) { scanf( %d %d , &a, &b); g.addTwoEdge(a, b, v[a], v[b]); } printf( %d , g.getAns()); return 0; } |
//------------------------------------------------------------------------------
// Title : 10/100/1G Ethernet FIFO
// Version : 1.2
// Project : Tri-Mode Ethernet MAC
//------------------------------------------------------------------------------
// File : ten_100_1g_eth_fifo.v
// Author : Xilinx Inc.
// -----------------------------------------------------------------------------
// (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
// Description: This is the top level wrapper for the 10/100/1G Ethernet FIFO.
// The top level wrapper consists of individual FIFOs on the
// transmitter path and on the receiver path.
//
// Each path consists of an 8 bit local link to 8 bit client
// interface FIFO.
//------------------------------------------------------------------------------
`timescale 1ps / 1ps
//------------------------------------------------------------------------------
// The module declaration for the FIFO
//------------------------------------------------------------------------------
module ten_100_1g_eth_fifo #
(
parameter FULL_DUPLEX_ONLY = 0
)
(
input tx_fifo_aclk, // tx fifo clock
input tx_fifo_resetn, // tx fifo clock synchronous reset
// tx fifo AXI-Stream interface
input [7:0] tx_axis_fifo_tdata,
input tx_axis_fifo_tvalid,
input tx_axis_fifo_tlast,
output tx_axis_fifo_tready,
input tx_mac_aclk, // tx_mac clock
input tx_mac_resetn, // tx mac clock synchronous reset
// tx mac AXI-Stream interface
output [7:0] tx_axis_mac_tdata,
output tx_axis_mac_tvalid,
output tx_axis_mac_tlast,
input tx_axis_mac_tready,
output tx_axis_mac_tuser,
// tx FIFO status outputs
output tx_fifo_overflow,
output [3:0] tx_fifo_status,
// tx fifo duplex controls
input tx_collision,
input tx_retransmit,
input rx_fifo_aclk, // rx fifo clock
input rx_fifo_resetn, // rx fifo clock synchronous reset
// rx fifo AXI-Stream interface
output [7:0] rx_axis_fifo_tdata,
output rx_axis_fifo_tvalid,
output rx_axis_fifo_tlast,
input rx_axis_fifo_tready,
input rx_mac_aclk, // rx mac clock
input rx_mac_resetn, // rx mac clock synchronous reset
// rx mac AXI-Stream interface
input [7:0] rx_axis_mac_tdata,
input rx_axis_mac_tvalid,
input rx_axis_mac_tlast,
output rx_axis_mac_tready,
input rx_axis_mac_tuser,
// rx fifo status outputs
output [3:0] rx_fifo_status,
output rx_fifo_overflow
);
//----------------------------------------------------------------------------
// Instantiate the Transmitter FIFO
//----------------------------------------------------------------------------
tx_client_fifo #
(
.FULL_DUPLEX_ONLY (FULL_DUPLEX_ONLY)
)
tx_fifo_i
(
.tx_fifo_aclk (tx_fifo_aclk),
.tx_fifo_resetn (tx_fifo_resetn),
.tx_axis_fifo_tdata (tx_axis_fifo_tdata),
.tx_axis_fifo_tvalid (tx_axis_fifo_tvalid),
.tx_axis_fifo_tlast (tx_axis_fifo_tlast),
.tx_axis_fifo_tready (tx_axis_fifo_tready),
.tx_mac_aclk (tx_mac_aclk),
.tx_mac_resetn (tx_mac_resetn),
.tx_axis_mac_tdata (tx_axis_mac_tdata),
.tx_axis_mac_tvalid (tx_axis_mac_tvalid),
.tx_axis_mac_tlast (tx_axis_mac_tlast),
.tx_axis_mac_tready (tx_axis_mac_tready),
.tx_axis_mac_tuser (tx_axis_mac_tuser),
.fifo_overflow (tx_fifo_overflow),
.fifo_status (tx_fifo_status),
.tx_collision (tx_collision),
.tx_retransmit (tx_retransmit)
);
//----------------------------------------------------------------------------
// Instantiate the Receiver FIFO
//----------------------------------------------------------------------------
rx_client_fifo rx_fifo_i
(
.rx_fifo_aclk (rx_fifo_aclk),
.rx_fifo_resetn (rx_fifo_resetn),
.rx_axis_fifo_tdata (rx_axis_fifo_tdata),
.rx_axis_fifo_tvalid (rx_axis_fifo_tvalid),
.rx_axis_fifo_tlast (rx_axis_fifo_tlast),
.rx_axis_fifo_tready (rx_axis_fifo_tready),
.rx_mac_aclk (rx_mac_aclk),
.rx_mac_resetn (rx_mac_resetn),
.rx_axis_mac_tdata (rx_axis_mac_tdata),
.rx_axis_mac_tvalid (rx_axis_mac_tvalid),
.rx_axis_mac_tlast (rx_axis_mac_tlast),
.rx_axis_mac_tready (rx_axis_mac_tready),
.rx_axis_mac_tuser (rx_axis_mac_tuser),
.fifo_status (rx_fifo_status),
.fifo_overflow (rx_fifo_overflow)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9; const long long MAXN = 2e5 + 1; void faster() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } int prs[1000]; void solve() { int n, k; cin >> n >> k; unsigned long long a[n]; set<int> ms; int s0 = 0; for (int i = 0; i < n; i++) { cin >> a[i]; } int b[65], cnt = 0; for (int i = 0; i <= 60; i++) { b[i] = 0; } for (int i = 0; i < n; i++) { cnt = 0; while (a[i] >= 1) { if (a[i] % k == 0) { cnt++; a[i] /= k; } else if ((a[i] - 1) % k == 0 && a[i] != 1) { if (b[cnt] == 0) { b[cnt] = 1; } else { cout << NO << endl; return; } a[i] -= 1; } else { if (a[i] == 1 && b[cnt] == 0) { b[cnt] = 1; break; } else { cout << NO << endl; return; } } } } cout << YES << endl; } int main() { int n = 1; cin >> n; while (n--) { solve(); } } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:167177216 ) using namespace std; const long long MOD = 1000000000 + 7; int main() { ios::sync_with_stdio(false); string s; cin >> s; long long bcount = 0; long long ans = 0; for (int i = s.size() - 1; i >= 0; --i) { if (s[i] == b ) { bcount++; } if (s[i] == a ) { ans += bcount; bcount *= 2; bcount %= MOD; ans %= MOD; } } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = (1 << 29); int n, k; string str[2505][4], rhy[2505]; int sch[4]; string sub(string s, int k) { string res = ; int t = k; for (int i = s.size() - 1; i >= 0; --i) { res = s[i] + res; if (s[i] == a || s[i] == e || s[i] == i || s[i] == o || s[i] == u ) { --t; if (t == 0) { break; } } } if (t != 0) { return ; } return res; } string find_rhy(int i) { if (str[i][0] == str[i][1] && str[i][1] == str[i][2] && str[i][0] == str[i][3]) { return aaaa ; } if (str[i][0] == str[i][1] && str[i][2] == str[i][3]) { return aabb ; } if (str[i][0] == str[i][2] && str[i][1] == str[i][3]) { return abab ; } if (str[i][0] == str[i][3] && str[i][1] == str[i][2]) { return abba ; } return NO ; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> k; bool f = 1; for (int i = 0; i < n; ++i) { for (int j = 0; j < 4; ++j) { string s; cin >> s; str[i][j] = sub(s, k); if (str[i][j] == ) { f = 0; } } } if (f == 0) { cout << NO n ; exit(0); } for (int i = 0; i < n; ++i) { rhy[i] = find_rhy(i); } string ans = rhy[0]; for (int i = 1; i < n; ++i) { if (ans == aaaa ) { ans = rhy[i]; } else if (ans == rhy[i] || rhy[i] == aaaa ) { ; } else { ans = NO ; } } cout << ans << n ; return 0; } |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.