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#include <bits/stdc++.h> using namespace std; const double eps = 1e-6; const double PI = 3.14159265358979323846264338f; const double pi = acos(-1.0); const int inf = 0x3f3f3f3f; const long long mod = 1e9 + 7; const int MAXN = 1005; inline int read() { int c = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { c = c * 10 + ch - 0 ; ch = getchar(); } return c * f; } struct node { int w, h; } e[MAXN]; int n; int ans = inf; bool vis[MAXN]; int main() { n = read(); for (int i = 1; i <= n; i++) { e[i].w = read(); e[i].h = read(); } auto solve = [](int x) -> void { memset(vis, false, sizeof(vis)); priority_queue<int> q; int tot = 0; int w = 0; for (int i = 1; i <= n; i++) { if (e[i].h > x) { vis[i] = true; tot++; w += e[i].h; if (e[i].w > x) return; } } for (int i = 1; i <= n; i++) { if (!vis[i]) { if (e[i].w <= x) q.push(e[i].w - e[i].h); w += e[i].w; } } while (tot < n / 2 && !q.empty()) { int ww = q.top(); q.pop(); if (ww > 0) { w -= ww; tot++; } else break; } if (tot <= n / 2) ans = min(ans, w * x); }; for (int i = 1; i <= 1000; i++) { solve(i); } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; string arr[12] = { C , C# , D , D# , E , F , F# , G , G# , A , B , H }, a, b, c; int ok(int a1, int a2, int a3) { int dis1, dis2; if (a2 > a1) dis1 = a2 - a1; else dis1 = 12 - a1 + a2; if (a3 > a2) dis2 = a3 - a2; else dis2 = 12 - a2 + a3; if (dis1 == 4 && dis2 == 3) return 1; if (dis1 == 3 && dis2 == 4) return 0; return 2; } int main() { cin >> a >> b >> c; int ind1, ind2, ind3; for (int i = 0; i < 12; i++) { if (arr[i] == a) ind1 = i; if (arr[i] == b) ind2 = i; if (arr[i] == c) ind3 = i; } if (ok(ind1, ind2, ind3) == 1 || ok(ind1, ind3, ind2) == 1 || ok(ind2, ind1, ind3) == 1 || ok(ind2, ind3, ind1) == 1 || ok(ind3, ind1, ind2) == 1 || ok(ind3, ind2, ind1) == 1) cout << major << endl; else { if (ok(ind1, ind2, ind3) == 0 || ok(ind1, ind3, ind2) == 0 || ok(ind2, ind1, ind3) == 0 || ok(ind2, ind3, ind1) == 0 || ok(ind3, ind1, ind2) == 0 || ok(ind3, ind2, ind1) == 0) cout << minor << endl; else cout << strange << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int k; cin >> k; string s; cin >> s; long long tot = 0; int av[11]; memset(av, 0, sizeof(av)); int ans = 0; for (char a : s) tot += a - 0 , av[9 - (a - 0 )]++; for (int i = 10; i; i--) { if (tot >= k) break; if (k - av[i] * i < tot) { while (k > tot) { k -= i; ans++; } break; } else { k -= av[i] * i; ans += av[i]; } } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; const int N = 109; int n, suma, K, sumb, f[10086][N], ans = 0; struct node { int a, b; } c[N]; bool cmp(const node& a, const node& b) { return a.b > b.b; } int main() { scanf( %d , &n); for (register int i = 1; i <= n; i++) scanf( %d , &c[i].a), suma += c[i].a; for (register int i = 1; i <= n; i++) scanf( %d , &c[i].b); sort(c + 1, c + n + 1, cmp); while (sumb < suma) sumb += c[++K].b; printf( %d , K); memset(f, 128, sizeof(f)); f[0][0] = 0; for (register int i = 1; i <= n; i++) for (register int j = sumb; j >= c[i].b; j--) for (register int k = 1; k <= K; k++) f[j][k] = max(f[j][k], f[j - c[i].b][k - 1] + c[i].a); for (register int j = suma; j <= sumb; j++) ans = max(ans, f[j][K]); printf( %d , suma - ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long bigmod(long long a, long long b) { if (b == 0) return 1; if (!(b & 1)) { long long ret = bigmod(a, b / 2); return ((ret % 1000000007) * (ret % 1000000007)) % 1000000007; } else return ((a % 1000000007) * (bigmod(a, b - 1) % 1000000007)) % 1000000007; } bool cmp(pair<int, int> p1, pair<int, int> p2) { if (p1.first != p2.first) return p1.first < p1.first; return p1.second < p2.second; } bool approximatelyEqual(float a, float b, float epsilon) { return fabs(a - b) <= ((fabs(a) < fabs(b) ? fabs(b) : fabs(a)) * epsilon); } bool essentiallyEqual(float a, float b, float epsilon) { return fabs(a - b) <= ((fabs(a) > fabs(b) ? fabs(b) : fabs(a)) * epsilon); } bool definitelyGreaterThan(float a, float b, float epsilon) { return (a - b) > ((fabs(a) < fabs(b) ? fabs(b) : fabs(a)) * epsilon); } bool definitelyLessThan(float a, float b, float epsilon) { return (b - a) > ((fabs(a) < fabs(b) ? fabs(b) : fabs(a)) * epsilon); } bool cmp1(pair<int, int> p1, pair<int, int> p2) { return p1.second < p2.second; } bool cmp2(pair<int, int> p1, pair<int, int> p2) { return p1.second > p2.second; } int main() { int t, tc = 1, a, b, c, m, n, i, j, k, p, q; char s[500000]; vector<pair<int, int> > u, v; scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &c); u.push_back(pair<int, int>(i, c)); v.push_back(pair<int, int>(i, c)); } getchar(); scanf( %s , s); sort(u.begin(), u.end(), cmp1); k = 0, b = 0; vector<int> ans; stack<int> st; int oc[200001] = {0}; int pp; for (i = 0; s[i]; i++) { if (s[i] == 0 ) { ans.push_back(u[k].first + 1); st.push(k); k++; } else { int xx = st.top(); st.pop(); ans.push_back(u[xx].first + 1); } } for (i = 0; i < ans.size(); i++) { i != ans.size() - 1 ? printf( %d , ans[i]) : printf( %d n , ans[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int x, y, z; cin >> x >> y >> z; int x1, y1, z1; cin >> x1 >> y1 >> z1; int a[6]; for (auto &z : a) cin >> z; int sum = 0; if (x < 0) sum += a[4]; else if (x > x1) sum += a[5]; if (y < 0) sum += a[0]; else if (y > y1) sum += a[1]; if (z < 0) sum += a[2]; else if (z > z1) sum += a[3]; cout << sum << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; struct sak { int x, y; sak(int x1, int y1) { x = x1; y = y1; } }; vector<sak> A, B; vector<int> AA, BB; int findA(int k) { int t1 = -1; for (int i = 0; i < A.size(); i++) if (A[i].x <= k && AA[i] == 0 && (t1 == -1 || A[t1].y < A[i].y)) { t1 = i; } return t1; } int findB(int k) { int t1 = -1; for (int i = 0; i < B.size(); i++) if (B[i].x <= k && BB[i] == 0 && (t1 == -1 || B[t1].y < B[i].y)) { t1 = i; } return t1; } int main() { int n, k; while (scanf( %d %d , &n, &k) == 2) { int x, y, z; A.clear(); B.clear(); AA.clear(); BB.clear(); for (int i = 0; i < n; i++) { scanf( %d %d %d , &x, &y, &z); if (x == 0) { A.push_back(sak(y, z)); AA.push_back(0); } else { B.push_back(sak(y, z)); BB.push_back(0); } } int maxi = 0; int sak1 = findA(k); if (A.size() > 0 && sak1 != -1) { int cnt = 1; x = 1; y = 0; int kk = k + A[sak1].y; AA[sak1] = 1; while (1) { sak1 = findB(kk); if (sak1 == -1) break; cnt++; kk += B[sak1].y; BB[sak1] = 1; y++; sak1 = findA(kk); if (sak1 == -1) break; cnt++; kk += A[sak1].y; AA[sak1] = 1; x++; } if (cnt > maxi) maxi = cnt; } for (int i = 0; i < AA.size(); i++) AA[i] = 0; for (int i = 0; i < BB.size(); i++) BB[i] = 0; sak1 = findB(k); if (B.size() > 0 && sak1 != -1) { int cnt = 1; x = 0; y = 1; int kk = k + B[sak1].y; BB[sak1] = 1; while (1) { sak1 = findA(kk); if (sak1 == -1) break; cnt++; kk += A[sak1].y; AA[sak1] = 1; x++; sak1 = findB(kk); if (sak1 == -1) break; cnt++; kk += B[sak1].y; BB[sak1] = 1; y++; } if (cnt > maxi) maxi = cnt; } printf( %d n , maxi); } return 0; } |
#include <bits/stdc++.h> using namespace std; void readi(int &x) { int v = 0, f = 1; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = v * 10 + c - 0 ; while (isdigit(c = getchar())) v = v * 10 + c - 0 ; x = v * f; } void readll(long long &x) { long long v = 0ll, f = 1ll; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = v * 10 + c - 0 ; while (isdigit(c = getchar())) v = v * 10 + c - 0 ; x = v * f; } void readc(char &x) { char c; while ((c = getchar()) == ) ; x = c; } void writes(string s) { puts(s.c_str()); } void writeln() { writes( ); } void writei(int x) { if (!x) putchar( 0 ); char a[25]; int top = 0; while (x) { a[++top] = (x % 10) + 0 ; x /= 10; } while (top) { putchar(a[top]); top--; } } void writell(long long x) { if (!x) putchar( 0 ); char a[25]; int top = 0; while (x) { a[++top] = (x % 10) + 0 ; x /= 10; } while (top) { putchar(a[top]); top--; } } inline long long inc(int &x) { return ++x; } inline long long inc(long long &x) { return ++x; } inline long long inc(int &x, long long y) { return x += y; } inline long long inc(long long &x, long long y) { return x += y; } inline double inc(double &x, double y) { return x += y; } inline long long dec(int &x) { return --x; } inline long long dec(long long &x) { return --x; } inline long long dec(int &x, long long y) { return x -= y; } inline long long dec(long long &x, long long y) { return x -= y; } inline double dec(double &x, double y) { return x -= y; } inline long long mul(int &x) { return x = ((long long)x) * x; } inline long long mul(long long &x) { return x = x * x; } inline long long mul(int &x, long long y) { return x *= y; } inline long long mul(long long &x, long long y) { return x *= y; } inline double mul(double &x, double y) { return x *= y; } inline long long divi(int &x) { return x = sqrt(x); } inline long long divi(long long &x) { return x = sqrt(x); } inline long long divi(int &x, long long y) { return x /= y; } inline long long divi(long long &x, long long y) { return x /= y; } inline double divi(double &x, double y) { return x /= y; } inline long long mod(int &x, long long y) { return x %= y; } inline long long mod(long long &x, long long y) { return x %= y; } long long n, m, i, j, cnt, cas; long long ans; vector<long long> all; struct Scanning_line { long long l, r, h, ad; } s[200005]; struct seg { long long l, r, add; long long sum; } tr[800005]; void build(long long x, long long l, long long r) { if (l == r) { tr[x].l = l; tr[x].r = r; tr[x].add = tr[x].sum = 0; return; } tr[x].l = l; tr[x].r = r; tr[x].add = tr[x].sum = 0; build(x * 2, l, (l + r) / 2); build(x * 2 + 1, (l + r) / 2 + 1, r); } void pushup(long long x) { if (tr[x].add) tr[x].sum = all[tr[x].r] - all[tr[x].l - 1]; else if (tr[x].l == tr[x].r) tr[x].sum = 0; else tr[x].sum = tr[x * 2].sum + tr[x * 2 + 1].sum; } void update(long long x, long long l, long long r, long long c) { if (tr[x].l > r || tr[x].r < l) return; if (l <= tr[x].l && tr[x].r <= r) { tr[x].add += c; pushup(x); return; } update(x * 2, l, r, c); update(x * 2 + 1, l, r, c); pushup(x); } bool cmp(Scanning_line x, Scanning_line y) { return x.h < y.h; } int main() { ios_base::sync_with_stdio(0); cin >> n; cnt = 0; for (i = 1; i <= n; i++) { long long w, x, y, z; cin >> w >> x >> y >> z; if (w > y) swap(w, y); if (x > z) swap(x, z); w--; x--; all.push_back(w); all.push_back(y); s[++cnt] = {w, y, x, 1}; s[++cnt] = {w, y, z, -1}; } stable_sort(all.begin(), all.end()); stable_sort(s + 1, s + cnt + 1, cmp); all.resize(unique(all.begin(), all.end()) - all.begin()); ans = 0; build(1, 0, all.size()); for (i = 1; i <= cnt; i++) { if (i != 1 && s[i].h != s[i - 1].h) { ans += abs(s[i].h - s[i - 1].h) * tr[1].sum; } long long l = upper_bound(all.begin(), all.end(), s[i].l) - all.begin(); long long r = upper_bound(all.begin(), all.end(), s[i].r) - all.begin(); update(1, l, r - 1, s[i].ad); } cout << ans << endl; return 0; } |
//-----------------------------------------------------------------------------
// Title : 10/100/1G Ethernet FIFO for 8-bit Client Interface
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : eth_fifo_8.v
// Version : 1.5
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//------------------------------------------------------------------------
// Description: This is the top-level wrapper for the 10/100/1G Ethernet
// FIFO. The top level wrapper consists of individual FIFOs
// on the transmitter path and on the receiver path.
//
// Each path consists of an 8-bit LocalLink-to-8-bit
// client-interface FIFO.
//------------------------------------------------------------------------
`timescale 1ps / 1ps
module eth_fifo_8 (
// Transmit FIFO MAC TX Interface
tx_clk, // MAC transmit clock
tx_reset, // Synchronous reset (tx_clk)
tx_enable, // Clock enable for tx_clk
tx_data, // Data to MAC transmitter
tx_data_valid, // Valid signal to MAC transmitter
tx_ack, // Ack signal from MAC transmitter
tx_underrun, // Underrun signal to MAC transmitter
tx_collision, // Collsion signal from MAC transmitter
tx_retransmit, // Retransmit signal from MAC transmitter
// Transmit FIFO LocalLink Interface
tx_ll_clock, // Local link write clock
tx_ll_reset, // synchronous reset (tx_ll_clock)
tx_ll_data_in, // Data to Tx FIFO
tx_ll_sof_in_n, // sof indicator to FIFO
tx_ll_eof_in_n, // eof indicator to FIFO
tx_ll_src_rdy_in_n, // src ready indicator to FIFO
tx_ll_dst_rdy_out_n, // dst ready indicator from FIFO
tx_fifo_status, // FIFO memory status
tx_overflow, // FIFO overflow indicator from FIFO
// Receive FIFO MAC RX Interface
rx_clk, // MAC receive clock
rx_reset, // Synchronous reset (rx_clk)
rx_enable, // Clock enable for rx_clk
rx_data, // Data from MAC receiver
rx_data_valid, // Valid signal from MAC receiver
rx_good_frame, // Good frame indicator from MAC receiver
rx_bad_frame, // Bad frame indicator from MAC receiver
rx_overflow, // FIFO overflow indicator from FIFO
// Receive FIFO LocalLink Interface
rx_ll_clock, // Local link read clock
rx_ll_reset, // synchronous reset (rx_ll_clock)
rx_ll_data_out, // Data from Rx FIFO
rx_ll_sof_out_n, // sof indicator from FIFO
rx_ll_eof_out_n, // eof indicator from FIFO
rx_ll_src_rdy_out_n, // src ready indicator from FIFO
rx_ll_dst_rdy_in_n, // dst ready indicator to FIFO
rx_fifo_status // FIFO memory status
);
//---------------------------------------------------------------------------
// Define Interface Signals
//---------------------------------------------------------------------------
parameter FULL_DUPLEX_ONLY = 0;
// Transmit FIFO MAC TX Interface
input tx_clk;
input tx_reset;
input tx_enable;
output [7:0] tx_data;
output tx_data_valid;
input tx_ack;
output tx_underrun;
input tx_collision;
input tx_retransmit;
// Transmit FIFO LocalLink Interface
input tx_ll_clock;
input tx_ll_reset;
input [7:0] tx_ll_data_in;
input tx_ll_sof_in_n;
input tx_ll_eof_in_n;
input tx_ll_src_rdy_in_n;
output tx_ll_dst_rdy_out_n;
output [3:0] tx_fifo_status;
output tx_overflow;
// Receive FIFO MAC RX Interface
input rx_clk;
input rx_reset;
input rx_enable;
input [7:0] rx_data;
input rx_data_valid;
input rx_good_frame;
input rx_bad_frame;
output rx_overflow;
// Receive FIFO LocalLink Interface
input rx_ll_clock;
input rx_ll_reset;
output [7:0] rx_ll_data_out;
output rx_ll_sof_out_n;
output rx_ll_eof_out_n;
output rx_ll_src_rdy_out_n;
input rx_ll_dst_rdy_in_n;
output [3:0] rx_fifo_status;
assign tx_underrun = 1'b0;
// Transmitter FIFO
tx_client_fifo_8 #(
.FULL_DUPLEX_ONLY (FULL_DUPLEX_ONLY)
)
tx_fifo_i (
.rd_clk (tx_clk),
.rd_sreset (tx_reset),
.rd_enable (tx_enable),
.tx_data (tx_data),
.tx_data_valid (tx_data_valid),
.tx_ack (tx_ack),
.tx_collision (tx_collision),
.tx_retransmit (tx_retransmit),
.overflow (tx_overflow),
.wr_clk (tx_ll_clock),
.wr_sreset (tx_ll_reset),
.wr_data (tx_ll_data_in),
.wr_sof_n (tx_ll_sof_in_n),
.wr_eof_n (tx_ll_eof_in_n),
.wr_src_rdy_n (tx_ll_src_rdy_in_n),
.wr_dst_rdy_n (tx_ll_dst_rdy_out_n),
.wr_fifo_status (tx_fifo_status)
);
// Receiver FIFO
rx_client_fifo_8 rx_fifo_i (
.wr_clk (rx_clk),
.wr_enable (rx_enable),
.wr_sreset (rx_reset),
.rx_data (rx_data),
.rx_data_valid (rx_data_valid),
.rx_good_frame (rx_good_frame),
.rx_bad_frame (rx_bad_frame),
.overflow (rx_overflow),
.rd_clk (rx_ll_clock),
.rd_sreset (rx_ll_reset),
.rd_data_out (rx_ll_data_out),
.rd_sof_n (rx_ll_sof_out_n),
.rd_eof_n (rx_ll_eof_out_n),
.rd_src_rdy_n (rx_ll_src_rdy_out_n),
.rd_dst_rdy_n (rx_ll_dst_rdy_in_n),
.rx_fifo_status (rx_fifo_status)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAP_SYMBOL_V
`define SKY130_FD_SC_MS__TAP_SYMBOL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__tap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; vector<long long> graph[300005]; long long col[300005]; long long ans, r, b; pair<long long, long long> dfs(long long x, long long p = -1) { long long a1, b1; a1 = 0; b1 = 0; if (col[x] == 1) a1++; if (col[x] == 2) b1++; for (long long i = 0; i < graph[x].size(); i++) { if (graph[x][i] == p) continue; auto temp = dfs(graph[x][i], x); if (temp.first == r && temp.second == 0) ans++; if (temp.first == 0 && temp.second == b) ans++; a1 += temp.first; b1 += temp.second; } return {a1, b1}; } signed main() { long long t, i, j, a, n, a1, a2, b1, b2; cin >> n; b = 0; r = 0; ans = 0; for (i = 1; i <= n; i++) { cin >> j; col[i] = j; if (j == 1) r++; if (j == 2) b++; } for (i = 0; i < n - 1; i++) { cin >> a1 >> b1; graph[a1].push_back(b1); graph[b1].push_back(a1); } dfs(1); cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1 << 30; typedef struct { long long x, y; } point; priority_queue<pair<int, int>, vector<pair<int, int> >, greater<pair<int, int> > > pq; vector<pair<pair<int, int>, int> > vpp; vector<pair<int, int> > vp; const int N = 1e5 + 5; const int seg = sqrt(N) + 1; int main() { int n, k; cin >> n >> k; vector<pair<int, int> > a(n); vector<int> vi(n, 10); for (int i = 0; i < n; i++) { cin >> a[i].first; a[i].second = i; } sort(a.rbegin(), a.rend()); queue<int> q; for (int i = 0; i < n; i++) { q.push(a[i].second); } set<int> idx; for (int i = 0; i < n; ++i) { idx.insert(i); } string ans(n, c ); int who = 0; while (!idx.empty()) { while (!idx.count(q.front())) { q.pop(); } int pos = q.front(); q.pop(); vector<int> add; auto it = idx.find(pos); for (int i = 0; i <= k; i++) { add.push_back(*it); if (it == idx.begin()) break; it--; } it = next(idx.find(pos)); for (int i = 0; i < k; i++) { if (it == idx.end()) break; add.push_back(*it); it++; } for (auto it : add) { idx.erase(it); ans[it] = 1 + who; } who ^= 1; } cout << ans << endl; return 0; } |
`include "defines.v"
module ctrl (
input wire rst,
input wire stallreq_from_id,
input wire stallreq_from_ex,
input wire[`RegBus] excepttype_i,
input wire[`RegBus] cp0_epc_i,
output reg[5:0] stall,
output reg[`RegBus] new_pc,
output reg flush
);
always @(*) begin
if (rst == `RstEnable) begin
stall <= `StallNone;
new_pc <= `ZeroWord;
flush <= `NotFlush;
end
else if (excepttype_i != `ZeroWord) begin
stall <= `StallNone;
flush <= `Flush;
case (excepttype_i)
`EXCEPTTYPE_INTERRUPT: begin
new_pc <= 32'h00000020;
end
`EXCEPTTYPE_SYSCALL: begin
new_pc <= 32'h00000040;
end
`EXCEPTTYPE_INST_INVALID: begin
new_pc <= 32'h00000040;
end
`EXCEPTTYPE_TRAP: begin
new_pc <= 32'h00000040;
end
`EXCEPTTYPE_OV: begin
new_pc <= 32'h00000040;
end
`EXCEPTTYPE_ERET: begin
new_pc <= cp0_epc_i;
end
default: begin
end
endcase
end
else if (stallreq_from_id == `StallEnable) begin
stall <= `StallFromID;
flush <= `NotFlush;
end
else if (stallreq_from_ex == `StallEnable) begin
stall <= `StallFromEX;
flush <= `NotFlush;
end
else begin
stall <= `StallNone;
flush <= `NotFlush;
new_pc <= `ZeroWord;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 9, inf = 1e18, mod = 1e9 + 7; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int t; cin >> t; while (t--) { int a, b, c, d, k; cin >> a >> b >> c >> d >> k; int x = (a + c - 1) / c; int y = k - x; if (y * d >= b) cout << x << << y << n ; else cout << -1 << n ; } } |
#include <bits/stdc++.h> using namespace std; const int mx = 2e3 + 505; struct node { double x, y; } a[mx]; double pw(double x) { return x * x; } double dist(node a, node b) { return sqrt(pw(a.x - b.x) + pw(a.y - b.y)); } double f[2][mx], g[2][mx]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lf%lf , &a[i].x, &a[i].y); for (int i = 1; i < n; i++) for (int j = 0; j < n; j++) { g[i % 2][j] = max(g[(i + 1) % 2][(j - 1 + n) % n] + dist(a[j], a[(j - 1 + n) % n]), f[(i + 1) % 2][(j - i + n) % n] + dist(a[j], a[(j - i + n) % n])); f[i % 2][j] = max(f[(i + 1) % 2][(j + 1) % n] + dist(a[j], a[(j + 1) % n]), g[(i + 1) % 2][(i + j) % n] + dist(a[j], a[(i + j) % n])); } double ans = 0; for (int i = 0; i < n; i++) ans = max(ans, max(f[(n - 1) % 2][i], g[(n - 1) % 2][i])); printf( %.10f n , ans); return 0; } |
//alt_oct_power CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" device_family="Stratix IV" parallelterminationcontrol rdn rup seriesterminationcontrol
//VERSION_BEGIN 11.0SP1 cbx_alt_oct_power 2011:07:03:21:10:32:SJ cbx_cycloneii 2011:07:03:21:10:33:SJ cbx_lpm_add_sub 2011:07:03:21:10:33:SJ cbx_lpm_compare 2011:07:03:21:10:33:SJ cbx_lpm_counter 2011:07:03:21:10:33:SJ cbx_lpm_decode 2011:07:03:21:10:33:SJ cbx_mgl 2011:07:03:21:11:41:SJ cbx_stratix 2011:07:03:21:10:33:SJ cbx_stratixii 2011:07:03:21:10:33:SJ cbx_stratixiii 2011:07:03:21:10:33:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = stratixiv_termination 1 stratixiv_termination_logic 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module ddr3_s4_uniphy_p0_oct_control
(
parallelterminationcontrol,
rdn,
rup,
seriesterminationcontrol) /* synthesis synthesis_clearbox=1 */;
output [13:0] parallelterminationcontrol;
input [0:0] rdn;
input [0:0] rup;
output [13:0] seriesterminationcontrol;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] rdn;
tri0 [0:0] rup;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] wire_sd1a_serializerenableout;
wire [0:0] wire_sd1a_terminationcontrol;
wire [13:0] wire_sd2a_parallelterminationcontrol;
wire [13:0] wire_sd2a_seriesterminationcontrol;
stratixiv_termination sd1a_0
(
.incrdn(),
.incrup(),
.rdn(rdn),
.rup(rup),
.scanout(),
.serializerenableout(wire_sd1a_serializerenableout[0:0]),
.shiftregisterprobe(),
.terminationcontrol(wire_sd1a_terminationcontrol[0:0]),
.terminationcontrolprobe()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.otherserializerenable({9{1'b0}}),
.scanen(1'b0),
.serializerenable(1'b0),
.terminationclear(1'b0),
.terminationclock(1'b0),
.terminationcontrolin(1'b0),
.terminationenable(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
stratixiv_termination_logic sd2a_0
(
.parallelterminationcontrol(wire_sd2a_parallelterminationcontrol[13:0]),
.serialloadenable(wire_sd1a_serializerenableout),
.seriesterminationcontrol(wire_sd2a_seriesterminationcontrol[13:0]),
.terminationdata(wire_sd1a_terminationcontrol)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.parallelloadenable(1'b0),
.terminationclock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
assign
parallelterminationcontrol = wire_sd2a_parallelterminationcontrol,
seriesterminationcontrol = wire_sd2a_seriesterminationcontrol;
endmodule //ddr3_s4_uniphy_p0_oct_control
//VALID FILE
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
// > Intel FPGA technology mapping. User must first simulate the generated \
// > netlist before going to test it on board.
// Input buffer map
module \$__inpad (input I, output O);
cyclone10lp_io_ibuf _TECHMAP_REPLACE_ (.o(O), .i(I), .ibar(1'b0));
endmodule
// Output buffer map
module \$__outpad (input I, output O);
cyclone10lp_io_obuf _TECHMAP_REPLACE_ (.o(O), .i(I), .oe(1'b1));
endmodule
// LUT Map
/* 0 -> datac
1 -> cin */
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
(* force_downto *)
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
cyclone10lp_lcell_comb #(.lut_mask({4{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(1'b1),
.datad(1'b1));
end else
if(WIDTH == 3) begin
cyclone10lp_lcell_comb #(.lut_mask({2{LUT}}),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(1'b1));
end else
if(WIDTH == 4) begin
cyclone10lp_lcell_comb #(.lut_mask(LUT),
.sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
.dataa(A[0]),
.datab(A[1]),
.datac(A[2]),
.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; long long n, a[N], sum; vector<long long> v; void fact() { if (sum % 2 == 0) { v.push_back(2); while (sum % 2 == 0) sum /= 2; } for (long long i = 3; i * i <= sum; i += 2) { if (sum % i == 0) { v.push_back(i); while (sum % i == 0) sum /= i; } } if (sum > 2) v.push_back(sum); } long long solve(long long p) { long long tmp, tmp2, res = 0; for (int i = 1; i < n; i++) { tmp = a[i] % p, tmp2 = p - tmp; if (tmp < tmp2) res += tmp; else res += tmp2; } return res; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; sum += a[i]; a[i] = a[i - 1] + a[i]; } fact(); if (!v.size()) return cout << -1 n , 0; long long ans = 1e18; for (int i = 0; i < v.size(); i++) { long long p = v[i]; ans = min(ans, solve(p)); } cout << ans << n ; return 0; } |
module mem(
input clk,
input we,
input [ADDR_WIDTH - 1 : 0] waddr,
input [DATA_WIDTH - 1 : 0] d,
input re,
input [ADDR_WIDTH - 1 : 0] raddr,
output [DATA_WIDTH - 1 : 0] q
);
parameter ADDR_WIDTH = 8;
parameter DATA_WIDTH = 16;
localparam DEPTH = 1 << ADDR_WIDTH;
parameter INIT = 0;
parameter SPRITE_FILE_NAME = "";
parameter SPRITE_FILE_WIDTH = 80;
parameter PROGRAM_FILE_NAME = "";
parameter PROGRAM_FILE_WIDTH = 256;
localparam PROGRAM_FILE_START = 512;
initial
begin
if (INIT)
begin
$readmemh(SPRITE_FILE_NAME, mem, 0, SPRITE_FILE_WIDTH - 1);
$readmemh(PROGRAM_FILE_NAME, mem,
PROGRAM_FILE_START, PROGRAM_FILE_START + PROGRAM_FILE_WIDTH - 1);
end
end
reg [DATA_WIDTH - 1 : 0] mem [DEPTH - 1 : 0];
reg [DATA_WIDTH - 1 : 0] _q = 0;
assign q = _q;
always @ (posedge clk)
begin
if (we)
begin
mem[waddr] <= d;
end
if (re)
begin
_q <= mem[raddr];
end
end // always @ (posedge clk)
endmodule // ram
|
#include <bits/stdc++.h> const int MAXN = 1e5 * 5; const int INF = 1e9 + 7; const int N = 5000; using namespace std; int n, m, h[N], c[N], cnt; char a[N][N]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) { cin >> a[i][j]; if (a[i][j] == * ) ++h[i], ++c[j], ++cnt; } for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) if (h[i] + c[j] - (a[i][j] == * ) >= cnt) { cout << YES << n ; cout << i << << j; return 0; } cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 300005; const int maxm = 5005; int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } int main() { int n; scanf( %d , &n); int a[maxn]; bool exist[maxm]; for (int i = 0; i < maxm; ++i) exist[i] = true; int i = 2; while (i < maxm) { int j = i + i; if (exist[i]) { while (j < maxm) { exist[j] = false; j += i; } } i += 1; } vector<int> primes; for (int i = 2; i < maxm; ++i) if (exist[i]) { primes.push_back(i); } for (int i = 0; i < n; ++i) scanf( %d , a + i); int cur_gcd = gcd(a[0], a[1]); for (int i = 2; i < n; ++i) if (cur_gcd != 1) cur_gcd = gcd(cur_gcd, a[i]); for (int i = 0; i < n; ++i) a[i] = a[i] / cur_gcd; vector<int> nums; for (int i = 0; i < n; ++i) { int cur = a[i]; for (int j = 0; j < primes.size(); ++j) if (primes[j] > cur) break; else if (cur % primes[j] == 0) { nums.push_back(primes[j]); while (cur % primes[j] == 0) { cur = cur / primes[j]; } } if (cur > 1) nums.push_back(cur); } sort(nums.begin(), nums.end()); int ans = 0; int left = 0, right = 0; while (right < nums.size()) { while (right < nums.size() && nums[right] == nums[left]) right++; if (right - left > ans) { ans = right - left; } left = right; } if (ans == 0 || ans == n) cout << -1 << endl; else cout << n - ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { long long test; cin >> test; while (test--) { long long b, p, f, h, c; cin >> b >> p >> f >> h >> c; long long profit = 0; if (h > c) { if (b - 2 * p >= 0) { profit += p * h; b = b - 2 * p; if (b - 2 * f >= 0) { profit += f * c; } else { profit += c * (b / 2); } } else { profit += h * (b / 2); } } else { if (b - 2 * f >= 0) { profit += f * c; b = b - 2 * f; if (b - 2 * p >= 0) { profit += p * h; } else { profit += h * (b / 2); } } else { profit += c * (b / 2); } } cout << profit << n ; } } |
#include <bits/stdc++.h> using namespace std; char buf[1 << 21], *p1 = buf, *p2 = buf; inline int qread() { register char c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); register int x = 0, f = 1; while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); } while (c >= 0 && c <= 9 ) { x = (x << 3) + (x << 1) + c - 48; c = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); } return x * f; } inline int Abs(const int& x) { return (x > 0 ? x : -x); } inline int Max(const int& x, const int& y) { return (x > y ? x : y); } inline int Min(const int& x, const int& y) { return (x < y ? x : y); } struct Segtree { long long sumv[800005], sumidx[800005]; inline void Modify(int p, int pl, int pr, int id) { if (pl == pr) { sumv[p]++; sumidx[p] += id; return; } int mid = pl + pr >> 1; if (mid >= id) Modify(p << 1, pl, mid, id); else Modify(p << 1 | 1, mid + 1, pr, id); sumv[p] = sumv[p << 1] + sumv[p << 1 | 1]; sumidx[p] = sumidx[p << 1] + sumidx[p << 1 | 1]; } inline int Kth(int p, int pl, int pr, int k) { if (pl == pr) return pl; int mid = pl + pr >> 1; if (k <= sumv[p << 1]) return Kth(p << 1, pl, mid, k); else return Kth(p << 1 | 1, mid + 1, pr, k - sumv[p << 1]); } inline long long Sumv(int p, int pl, int pr, int l, int r) { if (l > r) return 0; if (pl == l && pr == r) return sumv[p]; int mid = pl + pr >> 1; if (mid >= r) return Sumv(p << 1, pl, mid, l, r); else if (mid + 1 <= l) return Sumv(p << 1 | 1, mid + 1, pr, l, r); else return Sumv(p << 1, pl, mid, l, mid) + Sumv(p << 1 | 1, mid + 1, pr, mid + 1, r); } inline long long Sumidx(int p, int pl, int pr, int l, int r) { if (l > r) return 0; if (pl == l && pr == r) return sumidx[p]; int mid = pl + pr >> 1; if (mid >= r) return Sumidx(p << 1, pl, mid, l, r); else if (mid + 1 <= l) return Sumidx(p << 1 | 1, mid + 1, pr, l, r); else return Sumidx(p << 1, pl, mid, l, mid) + Sumidx(p << 1 | 1, mid + 1, pr, mid + 1, r); } }; Segtree sgt; int n, a[200005], idx[200005]; inline void Read() { n = qread(); for (int i = 1; i <= n; i++) idx[a[i] = qread()] = i; } inline long long Sum(int l, int k) { return 1ll * k * (l + l + k - 1) / 2; } inline void Solve() { long long inv = 0; for (int i = 1; i <= n; i++) { inv += sgt.Sumv(1, 1, n, idx[i] + 1, n); sgt.Modify(1, 1, n, idx[i]); int midv = sgt.Kth(1, 1, n, i + 1 >> 1); long long lsum = sgt.Sumidx(1, 1, n, 1, midv - 1), rsum = sgt.Sumidx(1, 1, n, midv + 1, n); printf( %lld , inv + Sum(midv - (i - 1 >> 1), i - 1 >> 1) - lsum + rsum - Sum(midv + 1, i >> 1)); } } int main() { Read(); Solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; void Debug(vector<int> v) { for (int i : v) { cerr << i << ; } } void Debug(int a[]) { for (int i = 0; i < 5; i++) { cerr << a[i] << ; } } void Debug(int a) { cerr << a; } void Debug(string a) { cerr << a; } void Debug(long long a) { cerr << a; } void Debug(unsigned long long a) { cerr << a; } void Debug(float a) { cerr << a; } void Debug(double a) { cerr << a; } void Debug(char a) { cerr << a; } int32_t main() { int64_t l; cin >> l; int64_t a, b; cin >> a >> b; int64_t speed = a + b; double time = (double)l / speed; cout << time * a; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = (int)2e5 + 5; int n, a[maxn], vis[2 * maxn], mx[maxn]; long long ans; vector<int> slist[maxn]; int gcd(int a, int b) { return b ? gcd(b, a % b) : a; } void doit(int d) { for (int i = 0; i < d; i++) mx[i] = 0; for (int i = 0; i < n; i++) vis[i] = 0; for (int i = 0; i < n; i++) mx[i % d] = max(mx[i % d], a[i]); for (int i = 0; i < n; i++) if (a[i] == mx[i % d]) vis[i] = 1; for (int i = n; i < 2 * n; i++) vis[i] = vis[i - n]; int lst = -1; for (int i = 2 * n - 1; i >= 0; i--) { if (vis[i] && lst == -1) lst = i; else if (!vis[i]) lst = -1; if (lst == -1 || i >= n) continue; int len = lst - i + 1; int idx = upper_bound(slist[d].begin(), slist[d].end(), len) - slist[d].begin(); ans += idx; } } int main() { ios_base::sync_with_stdio(0); cin.clear(); cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 1; i < n; i++) slist[gcd(i, n)].push_back(i); for (int i = 1; i * i <= n; i++) { if (n % i) continue; doit(i); if (n / i != i) doit(n / i); } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int main() { int BIG = 1000000; int n, k; cin >> n >> k; string s; int a[2][n + 2 * k]; int x[2][n + 2 * k]; for (int i = 0; i < 2; i++) { cin >> s; for (int j = k; j < n + k; j++) { if (s[j - k] == - ) a[i][j] = 0; else a[i][j] = 1; } } for (int i = 0; i < 2; i++) for (int j = 0; j < k; j++) { a[i][j] = 1; } for (int i = 0; i < 2; i++) for (int j = n + k; j < n + 2 * k; j++) { a[i][j] = 0; } for (int i = 0; i < 2; i++) { for (int j = 0; j < n + 2 * k; j++) { x[i][j] = BIG; } } x[0][k] = 0; vector<int> v[2][n + 1]; v[0][0].push_back(k); for (int T = 1; T <= n; T++) { for (int i = 0; i < 2; i++) { for (int J = 0; J < v[(i) % 2][T - 1].size(); J++) { int j = v[(i) % 2][T - 1][J]; if (x[i][j - 1] == BIG && (j - 1 - k) >= T) { x[i][j - 1] = (a[i][j - 1] == 1) ? BIG : T; if (!(a[i][j - 1] == 1)) v[(i) % 2][T].push_back(j - 1); } if (x[i][j + 1] == BIG) { x[i][j + 1] = (a[i][j + 1] == 1) ? BIG : T; if (!(a[i][j + 1] == 1)) v[(i) % 2][T].push_back(j + 1); } if (x[(i + 1) % 2][j + k] == BIG) { x[(i + 1) % 2][j + k] = (a[(i + 1) % 2][j + k] == 1) ? BIG : T; if (!(a[(i + 1) % 2][j + k] == 1)) v[(i + 1) % 2][T].push_back(j + k); } } } } for (int i = 0; i < 2; i++) for (int j = n + k; j < n + 2 * k; j++) { if (x[i][j] <= n) { cout << YES ; return 0; } } cout << NO ; } |
#include <bits/stdc++.h> #pragma GCC optimize(2) #pragma GCC optimize(3) #pragma GCC optimize( Ofast ) #pragma GCC optimize( inline ) #pragma GCC optimize( -fgcse ) #pragma GCC optimize( -fgcse-lm ) #pragma GCC optimize( -fipa-sra ) #pragma GCC optimize( -ftree-pre ) #pragma GCC optimize( -ftree-vrp ) #pragma GCC optimize( -fpeephole2 ) #pragma GCC optimize( -ffast-math ) #pragma GCC optimize( -fsched-spec ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( -falign-jumps ) #pragma GCC optimize( -falign-loops ) #pragma GCC optimize( -falign-labels ) #pragma GCC optimize( -fdevirtualize ) #pragma GCC optimize( -fcaller-saves ) #pragma GCC optimize( -fcrossjumping ) #pragma GCC optimize( -fthread-jumps ) #pragma GCC optimize( -funroll-loops ) #pragma GCC optimize( -fwhole-program ) #pragma GCC optimize( -freorder-blocks ) #pragma GCC optimize( -fschedule-insns ) #pragma GCC optimize( inline-functions ) #pragma GCC optimize( -ftree-tail-merge ) #pragma GCC optimize( -fschedule-insns2 ) #pragma GCC optimize( -fstrict-aliasing ) #pragma GCC optimize( -fstrict-overflow ) #pragma GCC optimize( -falign-functions ) #pragma GCC optimize( -fcse-skip-blocks ) #pragma GCC optimize( -fcse-follow-jumps ) #pragma GCC optimize( -fsched-interblock ) #pragma GCC optimize( -fpartial-inlining ) #pragma GCC optimize( no-stack-protector ) #pragma GCC optimize( -freorder-functions ) #pragma GCC optimize( -findirect-inlining ) #pragma GCC optimize( -fhoist-adjacent-loads ) #pragma GCC optimize( -frerun-cse-after-loop ) #pragma GCC optimize( inline-small-functions ) #pragma GCC optimize( -finline-small-functions ) #pragma GCC optimize( -ftree-switch-conversion ) #pragma GCC optimize( -foptimize-sibling-calls ) #pragma GCC optimize( -fexpensive-optimizations ) #pragma GCC optimize( -funsafe-loop-optimizations ) #pragma GCC optimize( inline-functions-called-once ) #pragma GCC optimize( -fdelete-null-pointer-checks ) using namespace std; const int N = 2e5 + 9; int x[N], t, n, k; char buf[1 << 21], *p1 = buf, *p2 = buf; inline int getc() { return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++; } inline int read() { int ret = 0, f = 0; char ch = getc(); while (!isdigit(ch)) { if (ch == - ) f = 1; ch = getc(); } while (isdigit(ch)) { ret = ret * 10 + ch - 48; ch = getc(); } return f ? -ret : ret; } char Buf[1 << 21], out[20]; int P, Size = -1; inline void flush() { fwrite(Buf, 1, Size + 1, stdout); Size = -1; } inline void write(int x, char ch) { if (Size > 1 << 20) flush(); if (x < 0) Buf[++Size] = 45, x = -x; do { out[++P] = x % 10 + 48; } while (x /= 10); do { Buf[++Size] = out[P]; } while (--P); Buf[++Size] = ch; } inline int max(int a, int b) { return a > b ? a : b; } int main() { t = read(); while (t--) { n = read(), k = read(); for (register int i = 0; i < n; i++) *(x + i) = read(); for (register int i = 0; i < n; i++) read(); sort(x, x + n); int maxi = 0, opt = 0, fans = 0; for (register int i = 0; i < n; i++) { int curr = upper_bound(x + i, x + n, *(x + i) + k) - x - i; if (i) opt = x + i - lower_bound(x, x + i - 1, *(x + i - 1) - k); maxi = max(maxi, opt); curr += maxi; fans = max(fans, curr); } write(fans, n ); } flush(); return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:54:34 03/11/2015
// Design Name: Condition
// Module Name: F:/ISE/work/cpu/cpu/Cond_Test.v
// Project Name: cpu
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Condition
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Cond_Test;
// Inputs
reg [1:0] kind;
reg data_in;
// Outputs
wire data_out;
// Instantiate the Unit Under Test (UUT)
Condition uut (
.data_out(data_out),
.kind(kind),
.data_in(data_in)
);
initial begin
// Initialize Inputs
kind = 0;
data_in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
kind = 0;
data_in = 1;
#100;
kind = 1;
data_in = 0;
#100;
kind = 1;
data_in = 1;
#100;
kind = 2;
data_in = 0;
#100;
kind = 2;
data_in = 1;
#100;
kind = 3;
data_in = 0;
#100;
kind = 3;
data_in = 1;
#100;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int mod = 1e9 + 7; long long binpow(long long a, long long b) { long long res = 1; while (b > 0) { if (b & 1) res = (res % mod) * (a % mod), res %= mod; a = (a % mod) * (a % mod); a %= mod; b >>= 1; } return res; } long long divide(long long a, int b) { return ((a % mod) * binpow(b, mod - 2) % mod) % mod; } long long nCr(long long n, long long k) { long long res = 1; if (k > n - k) k = n - k; for (int i = 0; i < k; ++i) { res = ((res % mod) * ((n - i) % mod)) % mod; res = divide(res, i + 1); } return res; } int main() { ios ::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, k; cin >> n; k = n; bool can = (n == 1); multiset<long long> st; for (long long i = 2; i * i <= n; i++) { while (n % i == 0) { n /= i; st.insert(i); } } if (n > 1) st.insert(n); if (n == k) can = 1; if (can) { return cout << 1 n0 n , 0; } if (st.size() == 2) { cout << 2 n ; } else { cout << 1 n ; int cnt = 0; long long mul = 1; for (auto i : st) { mul *= i; cnt++; if (cnt == 2) break; } cout << mul; } } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-9; const double pi = acos(-1.0); const int INF = 0x3f3f3f3f; const long long inf = (((long long)1) << 61) + 5; const int N = 200005; int a[N]; int b[N]; int f1[N]; int f2[N]; int bit[N]; int n; int sum(int i) { int s = 0; while (i > 0) { s += bit[i]; i -= i & -i; } return s; } void add(int i, int x) { while (i <= n + 1) { bit[i] += x; i += i & -i; } } int get(int x) { int ans = n, l = 1, r = n; while (l <= r) { int mid = (l + r) >> 1; if (sum(mid) >= x) { ans = mid; r = mid - 1; } else l = mid + 1; } return ans; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); int x = sum(a[i]); int tmp = a[i] - x; f1[n - i - 1] = tmp; add(a[i] + 1, 1); } memset(bit, 0, sizeof bit); for (int i = 0; i < n; i++) { scanf( %d , &b[i]); int x = sum(b[i]); int tmp = b[i] - x; f2[n - i - 1] = tmp; add(b[i] + 1, 1); } for (int i = 0; i < n; i++) { f1[i] += f2[i]; f1[i + 1] += f1[i] / (i + 1); f1[i] %= (i + 1); } memset(bit, 0, sizeof bit); for (int i = 1; i <= n; i++) add(i, 1); for (int i = n - 1; i >= 0; i--) { int ans = get(f1[i] + 1); printf( %d , ans - 1); add(ans, -1); } puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; cout << (n * n) / 4 << endl; for (int i = 1; i <= n / 2; i++) cout << n << << i << endl; for (int i = 1; i <= n / 2; i++) for (int j = n / 2 + 1; j < n; j++) cout << i << << j << endl; } |
#include <bits/stdc++.h> using namespace std; struct Point { double x, y; Point() : x(0), y(0) {} Point(double _x, double _y) : x(_x), y(_y) {} bool operator<(const Point &b) const { return tie(x, y) < tie(b.x, b.y); } bool operator==(const Point &b) const { return tie(x, y) == tie(b.x, b.y); } Point operator+(const Point &b) const { return Point(x + b.x, y + b.y); } Point operator-(const Point &b) const { return Point(x - b.x, y - b.y); } double operator*(const Point &b) const { return x * b.x + y * b.y; } double operator%(const Point &b) const { return x * b.y - y * b.x; } Point operator*(const double &b) const { return Point(x * b, y * b); } double abs() { return sqrt(abs2()); } double abs2() { return x * x + y * y; } }; long long cross(Point o, Point a, Point b) { return (a - o) % (b - o); } vector<Point> convex_hull(vector<Point> &pt) { sort(pt.begin(), pt.end()); int top = 0; vector<Point> stk(2 * pt.size()); for (int i = 0; i < (int)pt.size(); i++) { while (top >= 2 && cross(stk[top - 2], stk[top - 1], pt[i]) <= 0) top--; stk[top++] = pt[i]; } for (int i = pt.size() - 2, t = top + 1; i >= 0; i--) { while (top >= t && cross(stk[top - 2], stk[top - 1], pt[i]) <= 0) top--; stk[top++] = pt[i]; } stk.resize(top - 1); return stk; } int N, R; int ans; vector<Point> convexP, chp, sol; int dis2(Point a, Point b) { return (a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y); } void DFS(int i, int prv, int val) { if (i >= N) { if (val > ans) { ans = val; sol = chp; } return; } for (int j = prv; j < (int)convexP.size(); j++) { int c = 0; for (auto pt : chp) c += (pt - convexP[j]).abs2(); chp.push_back(convexP[j]); DFS(i + 1, j, val + c); chp.pop_back(); } } int main() { vector<Point> pt; cin >> N >> R; if (N % 2 == 0) { for (int i = 0; i < N / 2; i++) { sol.push_back(Point(R, 0)); sol.push_back(Point(-R, 0)); } for (int i = 0; i < N; i++) for (int j = 0; j < i; j++) ans += (sol[i] - sol[j]).abs2(); } else { for (int i = -R; i <= R; i++) { for (int j = -R; j <= R; j++) { if (i * i + j * j <= R * R) { pt.push_back(Point(i, j)); } } } convexP = convex_hull(pt); ans = 0; DFS(0, 0, 0); } cout << ans << endl; for (auto p : sol) cout << p.x << << p.y << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e3 + 5; const int P = 998244353; template <typename T> void chkmax(T &x, T y) { x = max(x, y); } template <typename T> void chkmin(T &x, T y) { x = min(x, y); } template <typename T> void read(T &x) { x = 0; int f = 1; char c = getchar(); for (; !isdigit(c); c = getchar()) if (c == - ) f = -f; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; x *= f; } template <typename T> void write(T x) { if (x < 0) x = -x, putchar( - ); if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } template <typename T> void writeln(T x) { write(x); puts( ); } struct BinaryIndexTree { int n, a[MAXN]; void init(int x) { n = x; memset(a, 0, sizeof(a)); } void modify(int x, int d) { for (int i = x; i <= n; i += i & -i) a[i] += d; } int query(int x) { int ans = 0; for (int i = x; i >= 1; i -= i & -i) ans += a[i]; return ans; } int query(int l, int r) { int ans = 0; for (int i = r; i >= 1; i -= i & -i) ans += a[i]; for (int i = l - 1; i >= 1; i -= i & -i) ans -= a[i]; return ans; } } BIT[3]; int n, a[MAXN][MAXN], dp[MAXN][MAXN], power[MAXN]; void update(int &x, int y) { x += y; if (x >= P) x -= P; } int main() { read(n), dp[0][0] = 1; for (int i = 1; i <= n; i++) { dp[i][0] = 1ll * i * dp[i - 1][0] % P; for (int j = 1; j <= i; j++) dp[i][j] = (dp[i][j - 1] - dp[i - 1][j - 1] + P) % P; } power[0] = 1; for (int i = 1; i <= n; i++) power[i] = 1ll * power[i - 1] * dp[n][n] % P; for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) read(a[i][j]); int ans = 0; BIT[0].init(n); for (int i = n; i >= 1; i--) { BIT[0].modify(a[1][i], 1); update(ans, 1ll * BIT[0].query(a[1][i] - 1) * dp[n - i][0] % P * power[n - 1] % P); } for (int i = 2; i <= n; i++) { bool visa[MAXN], visb[MAXN]; memset(visa, 0, sizeof(visa)); memset(visb, 0, sizeof(visb)); BIT[0].init(n), BIT[1].init(n); for (int j = n; j >= 1; j--) { visb[a[i][j]] = true; if (!visa[a[i][j]]) BIT[0].modify(a[i][j], 1); else BIT[1].modify(a[i][j], 1); int cnt = BIT[1].query(n); update(ans, 1ll * BIT[0].query(a[i][j] - 1) * dp[n - j][cnt] % P * power[n - i] % P); if (cnt) update(ans, 1ll * BIT[1].query(a[i][j] - 1) * dp[n - j][cnt - 1] % P * power[n - i] % P); if (a[i][j] > a[i - 1][j] && visb[a[i - 1][j]]) { if (visa[a[i - 1][j]]) update(ans, P - 1ll * dp[n - j][cnt - 1] * power[n - i] % P); else update(ans, P - 1ll * dp[n - j][cnt] * power[n - i] % P); } if (!visb[a[i - 1][j]]) visa[a[i - 1][j]] = true; else { visa[a[i - 1][j]] = true; BIT[0].modify(a[i - 1][j], -1); BIT[1].modify(a[i - 1][j], 1); } } } writeln(ans); return 0; } |
#include <bits/stdc++.h> using namespace std; char ch[500005]; bool vis[200]; int n; double f[500005], g[500005]; void init() { vis[ I ] = vis[ E ] = vis[ A ] = vis[ O ] = vis[ U ] = vis[ Y ] = true; int i; n = strlen(ch + 1); f[0] = g[0] = 0.0; for (i = 1; i <= n; i++) { f[i] = f[i - 1] + 1.0 / i; g[i] = g[i - 1] + 1.0 * i / (n - i + 1); } } int main() { scanf( %s , ch + 1); init(); double ans = 0.0; int i, t; for (i = 1; i <= n; i++) { if (!vis[ch[i]]) continue; t = min(i, n - i + 1); ans += t; ans += t * (f[n - t + 1] - f[t]); ans += g[n - (n - t + 1)]; } printf( %.10f n , ans); } |
#include <bits/stdc++.h> using namespace std; int n, m; string a, b, c, d, e; vector<vector<int> > vals; vector<vector<int> > forms(1); map<string, int> getind; int doop(int left, int right, int op) { if (op == 2) return left ^ right; if (op == 3) return left & right; else return left | right; } int main() { ios::sync_with_stdio(false); cin >> n >> m; vals.resize(1, vector<int>(m, 0)); getind[ ? ] = 0; for (int i = 0; i < n; i++) { cin >> a >> b >> c; getind[a] = vals.size(); vals.resize(vals.size() + 1); forms.resize(forms.size() + 1); if (c[0] != 1 && c[0] != 0 ) { cin >> d >> e; int first = getind[c]; int sec = getind[e]; int op = 2; if (d == AND ) op = 3; else if (d == OR ) op = 4; forms[forms.size() - 1].push_back(first); forms[forms.size() - 1].push_back(op); forms[forms.size() - 1].push_back(sec); for (int j = 0; j < m; j++) { vals[vals.size() - 1].push_back(doop(vals[first][j], vals[sec][j], op)); } } else { for (int j = 0; j < m; j++) { if (c[j] == 1 ) vals[vals.size() - 1].push_back(1); else vals[vals.size() - 1].push_back(0); } } } vector<int> best(m, 0); vector<int> worst(m, 0); for (int i = 0; i < m; i++) { int curcnt = 0; int rescnt = 0; for (int j = 1; j <= n; j++) { if (forms[j].size() > 0) { curcnt += vals[j][i]; } } vals[0][i] = 1; for (int j = 1; j <= n; j++) { if (forms[j].size() > 0) { int first = forms[j][0]; int sec = forms[j][2]; int op = forms[j][1]; int res = doop(vals[first][i], vals[sec][i], op); vals[j][i] = res; rescnt += res; } } if (rescnt > curcnt) best[i] = 1; if (rescnt < curcnt) worst[i] = 1; } for (int i = 0; i < m; i++) { cout << worst[i]; } cout << n ; for (int i = 0; i < m; i++) { cout << best[i]; } return 0; } |
/* -------------------------------------------------------------------------------
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
* -------------------------------------------------------------------------------
*
* pl_input_port
*
* - Buffers incoming flits and updates PL ID field with PL allocated for
* packet at current router.
*
* - Determine which port is needed at next router (route packet)
*
* pipelined_pl_switch_alloc = 0 | 1
* =================================
*
* Do we need to consider PLs allocated on this cycle when returning
* currently allocated PL id.?
* If PL/switch allocation is pipelined, current PL will always be
* read from the 'pl_reg' register.
*
*/
module LAG_pl_input_port(push, pop, data_in, data_out, flags,
// currently allocated PLs and valid bits
allocated_pl, allocated_pl_valid,
// incoming newly granted/allocated PLs and valid bits
pl_new, pl_new_valid,
clk, rst_n);
// number of virtual channels
parameter num_pls = 4;
// length of each virtual channel buffer
parameter buffer_length = 8;
input clk, rst_n;
input [num_pls-1:0] push;
input [num_pls-1:0] pop;
input flit_t data_in [num_pls-1:0];
output flit_t data_out [num_pls-1:0];
`include "LAG_functions.v"
output fifov_flags_t flags [num_pls-1:0];
output [num_pls-1:0] allocated_pl [num_pls-1:0];
output [num_pls-1:0] allocated_pl_valid;
input [num_pls-1:0][num_pls-1:0] pl_new;
input [num_pls-1:0] pl_new_valid;
logic [num_pls-1:0] pl_reg [num_pls-1:0];
logic [num_pls-1:0] allocated_pl_valid;
flit_t buffer_data_out [num_pls-1:0];
flit_t routed [num_pls-1:0];
logic sel_allocated_pl_valid;
logic [num_pls-1:0] sel_pl_reg, sel_pl_new;
integer i;
genvar pl;
//
// virtual-channel buffers
//
LAG_pl_buffers #(.size(buffer_length),
.n(num_pls)) pl_bufsi
(.push(push), .pop(pop), .data_in(data_in),
.data_out(buffer_data_out),
.flags(flags), .clk, .rst_n);
generate
for (pl=0; pl<num_pls; pl++) begin:eachpl
//
// if PL and switch allocation are pipelined,
// current PL is always read from register.
//
assign allocated_pl[pl] = pl_reg[pl];
assign data_out[pl] = buffer_data_out[pl];
end
endgenerate
always@(posedge clk) begin
if (!rst_n) begin
for (i=0; i<num_pls; i++) begin
// No allocated PLs on reset
allocated_pl_valid[i]<=1'b0;
end
end else begin
//
// if we have sent the last flit (tail) we don't hold a PL anymore
//
for (i=0; i<num_pls; i++) begin
if (buffer_data_out[i].control.tail && pop[i]) begin
//
// tail has gone, no longer hold a valid PL
//
allocated_pl_valid[i]<=1'b0;
pl_reg[i]<='0;
end else begin
// [may obtain, use and release PL in one cycle (single flit packets), if so
// allocated_pl_valid[] is never set
if (pl_new_valid[i]) begin
//
// receive new PL
//
// $display ("%m: new PL (%b) written to reg. at input PL buffer %1d", pl_new[i], i);
allocated_pl_valid[i]<=1'b1;
pl_reg[i]<=pl_new[i];
assert (pl_new[i]!='0) else begin
$display ("New PL id. is blank?"); $fatal;
end
end
end
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
endmodule // pl_input_port
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 60; const int IN = 0; const int AND = 1; const int OR = 2; const int XOR = 3; const int NOT = 4; struct Node { int val, p1, p2; int op; } node[maxn]; int n, p1, p2; string op; bool change[maxn]; int eval(int cur) { if (node[cur].op == IN) { return node[cur].val; } if (node[cur].op == AND) { return node[cur].val = (eval(node[cur].p1) & eval(node[cur].p2)); } if (node[cur].op == OR) { return node[cur].val = (eval(node[cur].p1) | eval(node[cur].p2)); } if (node[cur].op == XOR) { return node[cur].val = (eval(node[cur].p1) ^ eval(node[cur].p2)); } if (node[cur].op == NOT) { return node[cur].val = (!eval(node[cur].p1)); } } void process(int cur, int now) { int l = node[cur].p1; int r = node[cur].p2; int vl = node[l].val; int vr = node[r].val; if (node[cur].op == IN) { return; } else if (node[cur].op == AND) { if (vl == 0 && vr == 0) { process(l, change[l] = 0); process(r, change[r] = 0); } else if (vl == 0 && vr == 1) { process(l, change[l] = (now & 1)); process(r, change[r] = 0); } else if (vl == 1 && vr == 0) { process(l, change[l] = 0); process(r, change[r] = (now & 1)); } else if (vl == 1 && vr == 1) { process(l, change[l] = (now & 1)); process(r, change[r] = (now & 1)); } } else if (node[cur].op == OR) { if (vl == 0 && vr == 0) { process(l, change[l] = (now & 1)); process(r, change[r] = (now & 1)); } else if (vl == 0 && vr == 1) { process(l, change[l] = 0); process(r, change[r] = (now & 1)); } else if (vl == 1 && vr == 0) { process(l, change[l] = (now & 1)); process(r, change[r] = 0); } else if (vl == 1 && vr == 1) { process(l, change[l] = 0); process(r, change[r] = 0); } } else if (node[cur].op == XOR) { process(l, change[l] = (now & 1)); process(r, change[r] = (now & 1)); } else if (node[cur].op == NOT) { process(l, change[l] = (now & 1)); } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { cin >> op; if (op == IN ) { scanf( %d , &p1); node[i] = {p1, 0, 0, IN}; } else if (op == NOT ) { scanf( %d , &p1); node[i] = {0, p1, 0, NOT}; } else if (op == AND ) { scanf( %d%d , &p1, &p2); node[i] = {0, p1, p2, AND}; } else if (op == OR ) { scanf( %d%d , &p1, &p2); node[i] = {0, p1, p2, OR}; } else if (op == XOR ) { scanf( %d%d , &p1, &p2); node[i] = {0, p1, p2, XOR}; } } eval(1); process(1, 1); for (int i = 1; i <= n; i++) { if (node[i].op == IN) printf( %d , change[i] ^ node[1].val); } } |
#include <bits/stdc++.h> using namespace std; class base { public: long double a, b; base(void) { a = 0; b = 0; } base(long double _a, long double _b) { a = _a; b = _b; } base(long double _a) { a = _a; b = 0; } base operator*(const base& b2) { base ret(a * b2.a - b * b2.b, b * b2.a + a * b2.b); return ret; } base operator+(const base& b2) { base ret(a + b2.a, b + b2.b); return ret; } base operator-(const base& b2) { base ret(a - b2.a, b - b2.b); return ret; } base operator/(const base& b2) { long double c = b2.a, d = b2.b; base ret((a * c + b * d) / (c * c + d * d), (b * c - a * d) / (c * c + d * d)); return ret; } void operator*=(const base& b2) { long double tmp = a * b2.a - b * b2.b; b = b * b2.a + a * b2.b; a = tmp; } void operator/=(const base& b2) { long double c = b2.a, d = b2.b; long double tmp = (a * c + b * d) / (c * c + d * d); b = (b * c - a * d) / (c * c + d * d); a = tmp; } inline long double real(void) { return a; } }; void fft(vector<base>& a, bool invert) { int n = (int)a.size(); for (int i = 1, j = 0; i < n; ++i) { int bit = n >> 1; for (; j >= bit; bit >>= 1) j -= bit; j += bit; if (i < j) swap(a[i], a[j]); } base ww[n]; long double ang = 2 * 3.14159265358979323846l / n * (invert ? -1 : 1); base wi(cos(ang), sin(ang)); ww[0] = 1; for (int i = 1; i < n; i++) { ww[i] = ww[i / 2] * ww[i / 2]; if (i % 2 == 1) ww[i] *= wi; } for (int len = 2; len <= n; len <<= 1) { int k = n / len; for (int i = 0; i < n; i += len) { int wn = 0; for (int j = 0; j < len / 2; ++j) { base u = a[i + j], v = a[i + j + len / 2] * ww[wn]; a[i + j] = u + v; a[i + j + len / 2] = u - v; wn += k; } } } if (invert) for (int i = 0; i < n; ++i) a[i] /= n; } vector<int> multiply(const vector<int>& a, const vector<int>& b) { vector<base> fa(a.begin(), a.end()); size_t n = 1; while (n < (a.size() + b.size())) n <<= 1; fa.resize(n); vector<int> res; fft(fa, false); for (size_t i = 0; i < n; ++i) fa[i] *= fa[i]; fft(fa, true); res.resize(n); long long int carry = 0; for (size_t i = 0; i < n; ++i) { carry += (long long int)(fa[i].real() + 0.5); res[i] = carry % 1000; carry /= 1000; } int i; for (i = n - 1; i > 0; i--) { if (res[i] != 0) break; } res.resize(i + 1); return res; } void small_mult(vector<int>& a, int b) { int carry = 0; for (int i = 0; i < (int)a.size() || carry; i++) { if (i == (int)a.size()) a.push_back(0); int cur = carry + a[i] * b; a[i] = cur % 1000; carry = cur / 1000; } while (a.size() > 1 && !a.back()) a.pop_back(); } void fast_3_pow(long long int k, vector<int>& ans) { ans = {1}; if (k <= 0) return; long long int r = 0, kk = 0; for (long long int t = k; t > 0; t /= 2) { r = (2 * r + t % 2); kk++; } for (long long int i = 0; i < kk; i++) { ans = multiply(ans, ans); if (r % 2) small_mult(ans, 3); r /= 2; } } bool first_is_BE(vector<int>& v1, vector<int>& v2) { if (v1.size() > v2.size()) return 1; if (v1.size() < v2.size()) return 0; for (long long int i = ((long long int)v1.size()) - 1; i >= 0; i--) { if (v1[i] > v2[i]) return 1; if (v1[i] < v2[i]) return 0; } return 1; } int main() { ios::sync_with_stdio(0); string s; cin >> s; if (s == 1 ) { cout << 1 ; return 0; } if (s == 2 ) { cout << 2 ; return 0; } if (s == 3 ) { cout << 3 ; return 0; } if (s == 4 ) { cout << 4 ; return 0; } if (s == 5 ) { cout << 5 ; return 0; } if (s == 6 ) { cout << 5 ; return 0; } if (s == 7 ) { cout << 6 ; return 0; } if (s == 8 ) { cout << 6 ; return 0; } if (s == 9 ) { cout << 6 ; return 0; } vector<int> n; int tmp = 0; while (s.size() % 3 != 0) s = 0 + s; for (int i = 0; i < (int)s.size(); i++) { tmp *= 10; tmp += s[i] - 0 ; if ((i + 1) % 3 == 0) { n.push_back(tmp); tmp = 0; } } reverse(n.begin(), n.end()); vector<int> v1, vt; int k; k = max((int)(s.size() * logl(10) / logl(3) - 8), (int)0); fast_3_pow(k, v1); vt = v1; small_mult(v1, 4); while (1) { if (first_is_BE(v1, n)) { break; } k++; small_mult(v1, 3); } int ans3 = 3 * k + 4; k = max((int)(s.size() * logl(10) / logl(3) - 8), (int)0); v1 = vt; while (1) { if (first_is_BE(v1, n)) { break; } k++; small_mult(v1, 3); } int ans1 = 3 * k; k = max((int)(s.size() * logl(10) / logl(3) - 8), (int)0); v1 = vt; small_mult(v1, 2); while (1) { if (first_is_BE(v1, n)) { break; } k++; small_mult(v1, 3); } int ans2 = 3 * k + 2; cout << min(min(ans1, ans2), ans3); return 0; } |
module user_design(clk, rst, exception, input_timer, input_rs232_rx, input_ps2, input_i2c, input_switches, input_eth_rx, input_buttons, input_timer_stb, input_rs232_rx_stb, input_ps2_stb, input_i2c_stb, input_switches_stb, input_eth_rx_stb, input_buttons_stb, input_timer_ack, input_rs232_rx_ack, input_ps2_ack, input_i2c_ack, input_switches_ack, input_eth_rx_ack, input_buttons_ack, output_seven_segment_annode, output_eth_tx, output_rs232_tx, output_leds, output_audio, output_led_g, output_seven_segment_cathode, output_led_b, output_i2c, output_vga, output_led_r, output_seven_segment_annode_stb, output_eth_tx_stb, output_rs232_tx_stb, output_leds_stb, output_audio_stb, output_led_g_stb, output_seven_segment_cathode_stb, output_led_b_stb, output_i2c_stb, output_vga_stb, output_led_r_stb, output_seven_segment_annode_ack, output_eth_tx_ack, output_rs232_tx_ack, output_leds_ack, output_audio_ack, output_led_g_ack, output_seven_segment_cathode_ack, output_led_b_ack, output_i2c_ack, output_vga_ack, output_led_r_ack);
input clk;
input rst;
output exception;
input [31:0] input_timer;
input input_timer_stb;
output input_timer_ack;
input [31:0] input_rs232_rx;
input input_rs232_rx_stb;
output input_rs232_rx_ack;
input [31:0] input_ps2;
input input_ps2_stb;
output input_ps2_ack;
input [31:0] input_i2c;
input input_i2c_stb;
output input_i2c_ack;
input [31:0] input_switches;
input input_switches_stb;
output input_switches_ack;
input [31:0] input_eth_rx;
input input_eth_rx_stb;
output input_eth_rx_ack;
input [31:0] input_buttons;
input input_buttons_stb;
output input_buttons_ack;
output [31:0] output_seven_segment_annode;
output output_seven_segment_annode_stb;
input output_seven_segment_annode_ack;
output [31:0] output_eth_tx;
output output_eth_tx_stb;
input output_eth_tx_ack;
output [31:0] output_rs232_tx;
output output_rs232_tx_stb;
input output_rs232_tx_ack;
output [31:0] output_leds;
output output_leds_stb;
input output_leds_ack;
output [31:0] output_audio;
output output_audio_stb;
input output_audio_ack;
output [31:0] output_led_g;
output output_led_g_stb;
input output_led_g_ack;
output [31:0] output_seven_segment_cathode;
output output_seven_segment_cathode_stb;
input output_seven_segment_cathode_ack;
output [31:0] output_led_b;
output output_led_b_stb;
input output_led_b_ack;
output [31:0] output_i2c;
output output_i2c_stb;
input output_i2c_ack;
output [31:0] output_vga;
output output_vga_stb;
input output_vga_ack;
output [31:0] output_led_r;
output output_led_r_stb;
input output_led_r_ack;
wire exception_139931285810784;
wire exception_139931284795904;
wire exception_139931280503296;
wire exception_139931285208240;
wire exception_139931285145792;
wire exception_139931283554816;
wire exception_139931285866976;
wire exception_139931283565600;
wire exception_139931281978288;
wire exception_139931284096280;
wire exception_139931285722968;
wire exception_139931282979872;
wire exception_139931282082272;
wire exception_139931280124096;
main_0 main_0_139931285810784(
.clk(clk),
.rst(rst),
.exception(exception_139931285810784),
.input_rs232_rx(input_rs232_rx),
.input_rs232_rx_stb(input_rs232_rx_stb),
.input_rs232_rx_ack(input_rs232_rx_ack),
.output_led_r(output_led_r),
.output_led_r_stb(output_led_r_stb),
.output_led_r_ack(output_led_r_ack),
.output_led_g(output_led_g),
.output_led_g_stb(output_led_g_stb),
.output_led_g_ack(output_led_g_ack),
.output_rs232_tx(output_rs232_tx),
.output_rs232_tx_stb(output_rs232_tx_stb),
.output_rs232_tx_ack(output_rs232_tx_ack),
.output_led_b(output_led_b),
.output_led_b_stb(output_led_b_stb),
.output_led_b_ack(output_led_b_ack));
main_1 main_1_139931284795904(
.clk(clk),
.rst(rst),
.exception(exception_139931284795904),
.input_in(input_timer),
.input_in_stb(input_timer_stb),
.input_in_ack(input_timer_ack));
main_2 main_2_139931280503296(
.clk(clk),
.rst(rst),
.exception(exception_139931280503296),
.input_in(input_ps2),
.input_in_stb(input_ps2_stb),
.input_in_ack(input_ps2_ack));
main_3 main_3_139931285208240(
.clk(clk),
.rst(rst),
.exception(exception_139931285208240),
.input_in(input_i2c),
.input_in_stb(input_i2c_stb),
.input_in_ack(input_i2c_ack));
main_4 main_4_139931285145792(
.clk(clk),
.rst(rst),
.exception(exception_139931285145792),
.input_in(input_switches),
.input_in_stb(input_switches_stb),
.input_in_ack(input_switches_ack));
main_5 main_5_139931283554816(
.clk(clk),
.rst(rst),
.exception(exception_139931283554816),
.input_in(input_eth_rx),
.input_in_stb(input_eth_rx_stb),
.input_in_ack(input_eth_rx_ack));
main_6 main_6_139931285866976(
.clk(clk),
.rst(rst),
.exception(exception_139931285866976),
.input_in(input_buttons),
.input_in_stb(input_buttons_stb),
.input_in_ack(input_buttons_ack));
main_7 main_7_139931283565600(
.clk(clk),
.rst(rst),
.exception(exception_139931283565600),
.output_out(output_seven_segment_annode),
.output_out_stb(output_seven_segment_annode_stb),
.output_out_ack(output_seven_segment_annode_ack));
main_8 main_8_139931281978288(
.clk(clk),
.rst(rst),
.exception(exception_139931281978288),
.output_out(output_eth_tx),
.output_out_stb(output_eth_tx_stb),
.output_out_ack(output_eth_tx_ack));
main_9 main_9_139931284096280(
.clk(clk),
.rst(rst),
.exception(exception_139931284096280),
.output_out(output_leds),
.output_out_stb(output_leds_stb),
.output_out_ack(output_leds_ack));
main_10 main_10_139931285722968(
.clk(clk),
.rst(rst),
.exception(exception_139931285722968),
.output_out(output_audio),
.output_out_stb(output_audio_stb),
.output_out_ack(output_audio_ack));
main_11 main_11_139931282979872(
.clk(clk),
.rst(rst),
.exception(exception_139931282979872),
.output_out(output_seven_segment_cathode),
.output_out_stb(output_seven_segment_cathode_stb),
.output_out_ack(output_seven_segment_cathode_ack));
main_12 main_12_139931282082272(
.clk(clk),
.rst(rst),
.exception(exception_139931282082272),
.output_out(output_i2c),
.output_out_stb(output_i2c_stb),
.output_out_ack(output_i2c_ack));
main_13 main_13_139931280124096(
.clk(clk),
.rst(rst),
.exception(exception_139931280124096),
.output_out(output_vga),
.output_out_stb(output_vga_stb),
.output_out_ack(output_vga_ack));
assign exception = exception_139931285810784 || exception_139931284795904 || exception_139931280503296 || exception_139931285208240 || exception_139931285145792 || exception_139931283554816 || exception_139931285866976 || exception_139931283565600 || exception_139931281978288 || exception_139931284096280 || exception_139931285722968 || exception_139931282979872 || exception_139931282082272 || exception_139931280124096;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long int N = 500010; vector<vector<long long int> > ch, ar; void multiply(vector<vector<long long int> > &a, vector<vector<long long int> > &b) { vector<vector<long long int> > c; c.resize(a.size(), vector<long long int>(b[0].size(), 0)); for (long long int i = 0; i < a.size(); ++i) { for (long long int j = 0; j < b[0].size(); ++j) { c[i][j] = 0; for (long long int k = 0; k < a[0].size(); ++k) { c[i][j] = (c[i][j] + (a[i][k] * b[k][j]) % 1000000007) % 1000000007; } } } a = c; } void power_matrix(long long int n) { if (n == 1) { ar = ch; return; } power_matrix(n / 2); multiply(ar, ar); if (n % 2 == 1) { multiply(ar, ch); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, b, k, x; cin >> n >> b >> k >> x; long long int bh[10] = {0}; for (long long int i = 0; i < n; ++i) { long long int a; cin >> a; bh[a] += 1; } ch.resize(x, vector<long long int>(x, 0)); for (long long int i = 0; i < x; ++i) { for (long long int j = 0; j < 10; ++j) { ch[i][(10 * i + j) % x] += bh[j]; } } power_matrix(b); cout << ar[0][k] << endl; return (0); } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_faddsub(
input sys_clk,
input alu_rst,
input [31:0] a,
input [31:0] b,
input sub,
input valid_i,
output [31:0] r,
output reg valid_o
);
/* Stage 1 */
reg s1_valid;
reg a_sign;
reg [7:0] a_expn;
reg [22:0] a_mant;
reg b_sign;
reg [7:0] b_expn;
reg [22:0] b_mant;
always @(posedge sys_clk) begin
if(alu_rst)
s1_valid <= 1'b0;
else begin
s1_valid <= valid_i;
a_sign <= a[31];
a_expn <= a[30:23];
a_mant <= a[22:0];
b_sign <= b[31] ^ sub;
b_expn <= b[30:23];
b_mant <= b[22:0];
end
end
/* Stage 2 */
reg s2_iszero; /* one or both of the operands is zero */
reg s2_sign; /* sign of the result */
reg s2_issub; /* shall we do a subtraction or an addition */
reg [7:0] s2_expn_max; /* exponent of the bigger number (abs value) */
reg [7:0] s2_expn_diff; /* difference with the exponent of the smaller number (abs value) */
reg [22:0] s2_mant_max; /* mantissa of the bigger number (abs value) */
reg [22:0] s2_mant_min; /* mantissa of the smaller number (abs value) */
reg s2_valid;
/* local signals ; explicitly share the comparators */
wire expn_compare = a_expn > b_expn;
wire expn_equal = a_expn == b_expn;
wire mant_compare = a_mant > b_mant;
always @(posedge sys_clk) begin
if(alu_rst)
s2_valid <= 1'b0;
else
s2_valid <= s1_valid;
s2_issub <= a_sign ^ b_sign;
if(expn_compare)
/* |b| <= |a| */
s2_sign <= a_sign;
else begin
if(expn_equal) begin
if(mant_compare)
/* |b| <= |a| */
s2_sign <= a_sign;
else
/* |b| > |a| */
s2_sign <= b_sign;
end else
/* |b| > |a| */
s2_sign <= b_sign;
end
if(expn_compare) begin
s2_expn_max <= a_expn;
s2_expn_diff <= a_expn - b_expn;
end else begin
s2_expn_max <= b_expn;
s2_expn_diff <= b_expn - a_expn;
end
if(expn_equal) begin
if(mant_compare) begin
s2_mant_max <= a_mant;
s2_mant_min <= b_mant;
end else begin
s2_mant_max <= b_mant;
s2_mant_min <= a_mant;
end
end else begin
if(expn_compare) begin
s2_mant_max <= a_mant;
s2_mant_min <= b_mant;
end else begin
s2_mant_max <= b_mant;
s2_mant_min <= a_mant;
end
end
s2_iszero <= (a_expn == 8'd0)|(b_expn == 8'd0);
end
/* Stage 3 */
reg s3_sign;
reg [7:0] s3_expn;
reg [25:0] s3_mant;
reg s3_valid;
/* local signals */
wire [24:0] max_expanded = {1'b1, s2_mant_max, 1'b0}; /* 1 guard digit */
wire [24:0] min_expanded = {1'b1, s2_mant_min, 1'b0} >> s2_expn_diff;
always @(posedge sys_clk) begin
if(alu_rst)
s3_valid <= 1'b0;
else
s3_valid <= s2_valid;
s3_sign <= s2_sign;
s3_expn <= s2_expn_max;
if(s2_iszero)
s3_mant <= {2'b01, s2_mant_max, 1'b0};
else begin
if(s2_issub)
s3_mant <= max_expanded - min_expanded;
else
s3_mant <= max_expanded + min_expanded;
end
end
/* Stage 4 */
reg s4_sign;
reg [7:0] s4_expn;
reg [25:0] s4_mant;
wire [4:0] clz;
pfpu_clz32 clz32(
.d({s3_mant, 6'bx}),
.clz(clz)
);
always @(posedge sys_clk) begin
if(alu_rst)
valid_o <= 1'b0;
else
valid_o <= s3_valid;
s4_sign <= s3_sign;
s4_mant <= s3_mant << clz;
s4_expn <= s3_expn - clz + 8'd1;
end
assign r = {s4_sign, s4_expn, s4_mant[24:2]};
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 14:40:00 10/31/2016
// Module Name: MEM_WB
// Project Name: MIPS
// Description: The MIPS MEM/WB register (latch) of the MEMORY (MEM) stage.
//
// Dependencies: None.
//
////////////////////////////////////////////////////////////////////////////////
module MEM_WB(
input clk,
input [1:0] control_wb_in,
input [31:0] Read_data_in,
input [31:0] ALU_result_in,
input [4:0] Write_reg_in,
output reg [1:0] mem_control_wb,
output reg [31:0] Read_data,
output reg [31:0] mem_ALU_result,
output reg [4:0] mem_Write_reg);
// Initialize outputs to defaults.
initial
begin
mem_control_wb <= 0;
Read_data <= 0;
mem_ALU_result <= 0;
mem_Write_reg <= 0;
end
// Update outputs.
always @ (posedge clk)
begin
mem_control_wb <= control_wb_in;
Read_data <= Read_data_in;
mem_ALU_result <= ALU_result_in;
mem_Write_reg <= Write_reg_in;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool cmp(pair<int, int> p1, pair<int, int> p2) { return p2.second < p1.second; } vector<pair<int, int> > k; vector<pair<int, int> > c; vector<pair<int, int> > ans; int main() { int n, v; int t, p; cin >> n >> v; for (int i = 0; i < n; i++) { cin >> t >> p; if (t == 1) { k.push_back(make_pair(i + 1, p)); } else { c.push_back(make_pair(i + 1, p)); } } sort(k.begin(), k.end(), cmp); sort(c.begin(), c.end(), cmp); int cur = 0; while (v > 1 && cur < c.size()) { ans.push_back(c[cur]); v -= 2; cur++; } int last = ans.size() - 1; int nowk = 0; while (v > 0 && nowk < k.size()) { ans.push_back(k[nowk]); v -= 1; nowk++; } for (; nowk < k.size() - 1 && last >= 0; nowk += 2) { if (k[nowk].second + k[nowk + 1].second > ans[last].second) { ans.erase(ans.begin() + last); ans.push_back(k[nowk]); ans.push_back(k[nowk + 1]); last--; } } if (last >= 0 && nowk == k.size() - 1) { if (k[nowk].second > ans[last].second) { ans.erase(ans.begin() + last); ans.push_back(k[nowk]); last--; } } if (ans.size() > 0) { int tot = 0; for (int i = 0; i < ans.size(); i++) tot += ans[i].second; cout << tot << endl << ans[0].first << endl; for (int i = 1; i < ans.size(); i++) cout << ans[i].first << ; cout << endl; } else { cout << 0 << endl; } return 0; } |
// Execute-Memory Pipeline Register
module mem_pipe_reg
(
input wire clk,
input wire reset,
input wire clr,
input wire valid_mem_pipe_reg_i,
input wire reg_wr_mem_pipe_reg_i,
input wire mem_to_reg_mem_pipe_reg_i,
input wire mem_wr_mem_pipe_reg_i,
input wire[4:0] rd_mem_pipe_reg_i,
input wire[31:0] res_alu_mem_pipe_reg_i,
input wire[31:0] r_data_p2_mem_pipe_reg_i,
input wire[31:0] next_seq_pc_mem_pipe_reg_i,
input wire is_lw_mem_pipe_reg_i,
input wire use_link_reg_mem_pipe_reg_i,
output wire valid_mem_pipe_reg_o,
output wire reg_wr_mem_pipe_reg_o,
output wire mem_to_reg_mem_pipe_reg_o,
output wire mem_wr_mem_pipe_reg_o,
output wire[4:0] rd_mem_pipe_reg_o,
output wire[31:0] res_alu_mem_pipe_reg_o,
input wire[31:0] r_data_p2_mem_pipe_reg_o,
output wire[31:0] next_seq_pc_mem_pipe_reg_o,
output wire is_lw_mem_pipe_reg_o,
output wire use_link_reg_mem_pipe_reg_o
);
reg valid_mem_pipe_reg;
reg reg_wr_mem_pipe_reg;
reg mem_to_reg_mem_pipe_reg;
reg mem_wr_mem_pipe_reg;
reg[4:0] rd_mem_pipe_reg;
reg[31:0] res_alu_mem_pipe_reg;
reg[31:0] r_data_p2_mem_pipe_reg;
reg[31:0] next_seq_pc_mem_pipe_reg;
reg is_lw_mem_pipe_reg;
reg use_link_reg_mem_pipe_reg;
assign valid_mem_pipe_reg_o = valid_mem_pipe_reg;
assign reg_wr_mem_pipe_reg_o = reg_wr_mem_pipe_reg;
assign mem_to_reg_mem_pipe_reg_o = mem_to_reg_mem_pipe_reg;
assign mem_wr_mem_pipe_reg_o = mem_wr_mem_pipe_reg;
assign rd_mem_pipe_reg_o = rd_mem_pipe_reg;
assign res_alu_mem_pipe_reg_o = res_alu_mem_pipe_reg;
assign r_data_p2_mem_pipe_reg_o = r_data_p2_mem_pipe_reg;
assign next_seq_pc_mem_pipe_reg_o = next_seq_pc_mem_pipe_reg;
assign is_lw_mem_pipe_reg_o = is_lw_mem_pipe_reg;
assign use_link_reg_mem_pipe_reg_o = use_link_reg_mem_pipe_reg;
always @(posedge clk or posedge reset)
if (reset | clr)
begin
valid_mem_pipe_reg <= 0;
reg_wr_mem_pipe_reg <= 0;
mem_to_reg_mem_pipe_reg <= 0;
mem_wr_mem_pipe_reg <= 0;
rd_mem_pipe_reg <= 0;
res_alu_mem_pipe_reg <= 0;
r_data_p2_mem_pipe_reg <= 0;
next_seq_pc_mem_pipe_reg <= 0;
is_lw_mem_pipe_reg <= 0;
use_link_reg_mem_pipe_reg <= 0;
end
else
begin
valid_mem_pipe_reg <= valid_mem_pipe_reg_i;
reg_wr_mem_pipe_reg <= reg_wr_mem_pipe_reg_i;
mem_to_reg_mem_pipe_reg <= mem_to_reg_mem_pipe_reg_i;
mem_wr_mem_pipe_reg <= mem_wr_mem_pipe_reg_i;
rd_mem_pipe_reg <= rd_mem_pipe_reg_i;
res_alu_mem_pipe_reg <= res_alu_mem_pipe_reg_i;
r_data_p2_mem_pipe_reg <= r_data_p2_mem_pipe_reg_i;
next_seq_pc_mem_pipe_reg <= next_seq_pc_mem_pipe_reg_i;
is_lw_mem_pipe_reg <= is_lw_mem_pipe_reg_i;
use_link_reg_mem_pipe_reg <= use_link_reg_mem_pipe_reg_i;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n, p, x; cin >> t; for (int u = 0; u < t; u++) { cin >> n >> p; x = 2 * n + p; for (int i = 0; i < n; i++) { for (int j = i + 1; j < n; j++) { cout << i + 1 << << j + 1 << n ; x--; if (x == 0) { break; } } if (x == 0) { break; } } } return 0; } |
/*TODO:
Test byte masks
Add timeout
Add FIFO mode
*/
module wb_bfm_transactor
#(parameter aw = 32,
parameter dw = 32,
parameter VERBOSE = 0,
parameter MAX_BURST_LEN = 5,
parameter MEM_LOW = 0,
parameter MEM_HIGH = 32'hffffffff)
(input wb_clk_i,
input wb_rst_i,
output [aw-1:0] wb_adr_o,
output [dw-1:0] wb_dat_o,
output [3:0] wb_sel_o,
output wb_we_o,
output wb_cyc_o,
output wb_stb_o,
output [2:0] wb_cti_o,
output [1:0] wb_bte_o,
input [dw-1:0] wb_dat_i,
input wb_ack_i,
input wb_err_i,
input wb_rty_i,
output reg done);
`include "wb_bfm_params.v"
integer SEED = 2;
integer TRANSACTIONS;
initial
if(!$value$plusargs("transactions=%d", TRANSACTIONS))
TRANSACTIONS = 1000;
wb_bfm_master
#(.MAX_BURST_LENGTH (MAX_BURST_LEN))
bfm
(.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_adr_o (wb_adr_o),
.wb_dat_o (wb_dat_o),
.wb_sel_o (wb_sel_o),
.wb_we_o (wb_we_o),
.wb_cyc_o (wb_cyc_o),
.wb_stb_o (wb_stb_o),
.wb_cti_o (wb_cti_o),
.wb_bte_o (wb_bte_o),
.wb_dat_i (wb_dat_i),
.wb_ack_i (wb_ack_i),
.wb_err_i (wb_err_i),
.wb_rty_i (wb_rty_i));
/*Return a 2*aw array with the highest and lowest accessed addresses
based on starting address and burst type
TODO: Account for short wrap bursts. Fix for 8-bit mode*/
function [2*aw-1:0] adr_range;
input [aw-1:0] adr_i;
input [$clog2(MAX_BURST_LEN)-1:0] len_i;
input [2:0] burst_type_i;
parameter bpw = 4; //Bytes per word. Hardcoded to 4 (32-bit)
reg [aw-1:0] adr;
reg [aw-1:0] adr_high;
reg [aw-1:0] adr_low;
begin
if(bpw==4)
adr = adr_i[aw-1:2];
case (burst_type_i)
LINEAR_BURST : begin
adr_high = (adr+len_i)*bpw-1;
adr_low = adr*bpw;
end
WRAP_4_BURST : begin
adr_high = (adr[aw-1:2]*4+4)*bpw-1;
adr_low = adr[aw-1:2]*4*bpw;
end
WRAP_8_BURST : begin
adr_high = (adr[aw-1:3]*8+8)*bpw-1;
adr_low = adr[aw-1:3]*8*bpw;
end
WRAP_16_BURST : begin
adr_high = (adr[aw-1:4]*16+16)*bpw-1;
adr_low = adr[aw-1:4]*16*bpw;
end
CONSTANT_BURST : begin
adr_high = (adr+1)*bpw-1;
adr_low = adr*bpw;
end
default : begin
$error("%d : Illegal burst type (%b)", $time, burst_type);
adr_range = {2*aw{1'bx}};
end
endcase // case (burst_type)
adr_range = {adr_high, adr_low};
end
endfunction
reg [dw*MAX_BURST_LEN-1:0] write_data;
reg [dw*MAX_BURST_LEN-1:0] read_data;
reg [dw*MAX_BURST_LEN-1:0] expected_data;
integer word;
integer burst_length;
reg [2:0] burst_type;
integer transaction;
integer tmp, burst_wrap;
reg err;
reg [aw-1:0] address;
reg [aw-1:0] adr_high;
reg [aw-1:0] adr_low;
initial begin
bfm.reset;
done = 0;
$display("%m : Running %0d transactions", TRANSACTIONS);
$display("Max burst length=%0d", MAX_BURST_LEN);
for(transaction = 0 ; transaction < TRANSACTIONS; transaction = transaction + 1) begin
address = (MEM_LOW + ($random(SEED) % (MEM_HIGH-MEM_LOW))) & {{aw-2{1'b1}},2'b00};
burst_length = ({$random(SEED)} % MAX_BURST_LEN) + 1;
burst_type = ({$random(SEED)} % 4);
{adr_high, adr_low} = adr_range(address, burst_length, burst_type);
while((adr_high > MEM_HIGH) || (adr_low < MEM_LOW)) begin
address = (MEM_LOW + ($random(SEED) % (MEM_HIGH-MEM_LOW))) & {{aw-2{1'b1}},2'b00};
burst_length = ({$random(SEED)} % MAX_BURST_LEN) + 1;
burst_type = ({$random(SEED)} % 4);
{adr_high, adr_low} = adr_range(address, burst_length, burst_type);
end
case (burst_type)
LINEAR_BURST : burst_wrap = burst_length;
WRAP_4_BURST : burst_wrap = 4;
WRAP_8_BURST : burst_wrap = 8;
WRAP_16_BURST : burst_wrap = 16;
CONSTANT_BURST : burst_wrap = 1;
default : $error("%d : Illegal burst type (%b)", $time, burst_type);
endcase
for(word = 0; word < burst_length; word = word + 1)
write_data[dw*word+:dw] = $random;
bfm.write_burst(address, write_data, 4'hf, burst_length, burst_type, err);
@(posedge wb_clk_i);
bfm.read_burst(address, read_data, 4'hf, burst_length, burst_type, err);
@(posedge wb_clk_i);
if(VERBOSE>0)
if(!(transaction%(TRANSACTIONS/10)))
$display("%m : %0d/%0d", transaction, TRANSACTIONS);
tmp = burst_length-1;
for(word = burst_length-1 ; word >= 0 ; word = word - 1) begin
expected_data[dw*word+:dw] = write_data[dw*tmp+:dw];
tmp = tmp - 1;
if(tmp < burst_length - burst_wrap)
tmp = burst_length-1;
end
for(word = 0 ; word < burst_length ; word = word +1)
if(read_data[word*dw+:dw] !== expected_data[word*dw+:dw]) begin
$error("%m : Transaction %0d failed!", transaction);
$error("Read data mismatch on address %h (burst length=%0d, burst_type=%0d, iteration %0d)", address, burst_length, burst_type, word);
$error("Expected %h", expected_data[word*dw+:dw]);
$error("Got %h", read_data[word*dw+:dw]);
#3 $finish;
end
if (VERBOSE>1) $display("Read ok from address %h (burst length=%0d, burst_type=%0d)", address, burst_length, burst_type);
end
done = 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; stack<int> a[27]; stack<int> b[27]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n; cin >> n; string f, s; cin >> f >> s; for (int i = 0; i < f.size(); ++i) { if (f[i] == ? ) { a[26].push(i + 1); } else { a[(int)(f[i] - a )].push(i + 1); } } for (int i = 0; i < s.size(); ++i) { if (s[i] == ? ) { b[26].push(i + 1); } else { b[(int)(s[i] - a )].push(i + 1); } } int ans = 0; vector<pair<int, int> > anss; for (int i = 0; i < 27; ++i) { while ((a[i].size() != 0 && b[i].size() != 0) || (a[i].size() != 0 && b[26].size() != 0) || (a[26].size() != 0 && b[i].size() != 0)) { if (a[i].size() != 0 && b[i].size() != 0) { int c1, c2; c1 = a[i].top(); c2 = b[i].top(); ans++; a[i].pop(); b[i].pop(); anss.push_back({c1, c2}); } else if (a[i].size() != 0 && b[i].size() == 0) { if (b[26].size() != 0) { int c1, c2; c1 = a[i].top(); c2 = b[26].top(); ans++; a[i].pop(); b[26].pop(); anss.push_back({c1, c2}); } } else if (a[i].size() == 0 && b[i].size() != 0) { if (a[26].size() != 0) { int c1, c2; c1 = a[26].top(); c2 = b[i].top(); ans++; a[26].pop(); b[i].pop(); anss.push_back({c1, c2}); } } } } cout << ans << endl; for (int i = 0; i < anss.size(); ++i) { cout << anss[i].first << << anss[i].second << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BOI_BLACKBOX_V
`define SKY130_FD_SC_MS__A21BOI_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BOI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFINV_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__BUFINV_PP_BLACKBOX_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFINV_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 2007; int n, m, a[maxn][maxn]; long long sr[maxn][maxn], sc[maxn][maxn], sumr[maxn], sumc[maxn], allsumr[maxn], allsumc[maxn]; int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &a[i][j]); sumr[i] += a[i][j]; sumc[j] += a[i][j]; } } for (int r = 1; r <= n + 1; r++) { for (int nr = 1; nr <= n; nr++) { int dis; if (nr < r) dis = abs(r - nr - 1) * 4 + 2; else dis = abs(r - nr) * 4 + 2; sr[r][nr] = dis * dis * sumr[nr]; allsumr[r] += sr[r][nr]; } } for (int c = 1; c <= m + 1; c++) { for (int nc = 1; nc <= m; nc++) { int dis; if (nc < c) dis = abs(c - nc - 1) * 4 + 2; else dis = abs(c - nc) * 4 + 2; sc[c][nc] = dis * dis * sumc[nc]; allsumc[c] += sc[c][nc]; } } long long ans = 1e18 + 10; int x, y; for (int r = 1; r <= n + 1; r++) { for (int c = 1; c <= m + 1; c++) { if (allsumr[r] + allsumc[c] < ans) { ans = allsumr[r] + allsumc[c]; x = r, y = c; } } } printf( %lld n%d %d n , ans, x - 1, y - 1); return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; long long int x; long long int k; long long int res; long long int curr; long long int exponentiation(long long int base, long long int power) { long long int ans = 1; while (power > 0) { if (power % 2) ans = (ans * base) % mod; base = (base * base) % mod; power /= 2; } return ans % mod; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; cin >> x >> k; if (x == 0) { res = 0; } else if (k == 0) { res = (2 * x) % mod; } else { curr = (2 * x - 1 - x + mod) % mod; res = (x + ((((curr + x) % mod) * exponentiation(2, k)) % mod - curr) + mod) % mod; } cout << res << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_1_V
`define SKY130_FD_SC_LP__NOR2_1_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_1_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1100; int N, K, L; string S; int nc[26]; vector<char> res[MAXN]; int main() { ios_base::sync_with_stdio(0); for (int i = 0; i < 26; i++) nc[i] = 0; cin >> N >> L >> K >> S; for (int i = 0; i < S.length(); i++) nc[S[i] - a ]++; int nlo = 0, tlen = 0; for (int i = 0; i < 26; i++) { if (tlen == L) break; int ncnt = (K - nlo); int nb = nc[i] / ncnt; nb = min(nb, L - tlen); for (int j = nlo; j < K; j++) { for (int k = 0; k < nb; k++) { res[j].push_back((char) a + i); nc[i]--; } } tlen += nb; if (tlen == L) break; int nleft = nc[i] % ncnt; for (int j = 0; j < nleft; j++) { res[nlo++].push_back((char) a + i); nc[i]--; } } for (int i = 0; i < N; i++) { for (int j = 0; j < 26; j++) { while (nc[j] > 0 && res[i].size() < L) { res[i].push_back((char) a + j); nc[j]--; } } } for (int i = 0; i < N; i++) { for (char c : res[i]) cout << c; cout << n ; } } |
#include <bits/stdc++.h> using namespace std; const int M = 998244353; int main() { long long n; cin >> n; map<long long, long long> mp; long long a[200005]; for (long long i = 0; i < n; i++) { cin >> a[i]; mp[a[i]] = i; } long long ans = 1, w = mp[a[0]]; for (int i = 0; i < n; i++) { if (i > w) { ans = (ans * 2) % M; } w = max(w, mp[a[i]]); } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int n, m, k; struct Lesson { long long a, b; int c, id; bool operator<(const Lesson &t) const { return c < t.c; } } ls[55]; int fstc[110]; long long dp[55][55][110]; pair<int, int> trans[55][55][110]; inline void upd(int x1, int y1, int z1, int y2, int z2, long long val) { if (dp[x1][y1][z1] < val) { dp[x1][y1][z1] = val; trans[x1][y1][z1] = make_pair(y2, z2); } } void Print(int lvl, int od, int ad) { if (lvl == 0) { printf( %d %I64d n , ls[od].id, ls[od].a + ad); return; } Print(lvl - 1, trans[lvl][od][ad].first, trans[lvl][od][ad].second); printf( %d %lld n , ls[od].id, ls[od].a + ad); } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < m; i++) { scanf( %I64d%I64d%d , &ls[i].a, &ls[i].b, &ls[i].c); ls[i].id = i + 1; } sort(ls, ls + m); memset(fstc, -1, sizeof(fstc)); for (int i = 0; i < m; i++) if (fstc[ls[i].c] == -1) fstc[ls[i].c] = i; for (int i = 0; i < m; i++) { for (int j = 0; j <= (int)(ls[i].b - ls[i].a); j++) { dp[0][i][j] = (ls[i].a + j); } } for (int i = 1; i < n; i++) { for (int j = 0; j < m; j++) { int c = ls[j].c; for (int task = 0; task <= 100; task++) if (dp[i - 1][j][task]) { long long val = ls[j].a + task; if (val > ls[j].b) continue; long long knval = val * 1ll * k; long long nvalk = val + 1ll * k; for (int nc = c + 1; nc <= 100; nc++) { if (fstc[nc] == -1) continue; for (int nj = fstc[nc]; nj < m && ls[nj].c == nc; nj++) { if (ls[nj].a <= knval && knval <= ls[nj].b) { int ntask = (int)(knval - ls[nj].a); upd(i, nj, ntask, j, task, dp[i - 1][j][task] + knval); } if (ls[nj].a <= nvalk && nvalk <= ls[nj].b) { int ntask = (int)(nvalk - ls[nj].a); upd(i, nj, ntask, j, task, dp[i - 1][j][task] + nvalk); } } } } } } long long ans = 0; int y = -1, z = -1; for (int i = 0; i < m; i++) for (int j = 0; j <= (int)(ls[i].b - ls[i].a); j++) { if (dp[n - 1][i][j] > ans) { ans = dp[n - 1][i][j]; y = i; z = j; } } if (ans == 0 || y == -1 || z == -1) { printf( NO n ); return 0; } printf( YES n ); Print(n - 1, y, z); return 0; } |
`timescale 1ns/1ps
module fifo_axi_lcl(
input clk ,
input rst_n,
input clr ,
//FIFO status
output reg ovfl ,
output reg udfl ,
//data input ports
input iend , //synced with,or after the last input data
output reg irdy , //stop asserting den when irdy is 0, but with margin
input den ,
input [511:0] din ,
//data output ports
input rdrq , //MUST be deasserted when olast is 1
output olast, //synced with the last output data
output reg ordy , //stop asserting rdrq when ordy is 0, but with margin
output [511:0] dout ,
output dv ,
output empty,
output reg flush
);
reg [04:00] i_cnt ;
reg [04:00] o_cnt ;
wire[04:00] cnt ;
wire full ;
parameter IH_LIM = 5'd26,
IL_LIM = 5'd16,
OH_LIM = 5'd16,
OL_LIM = 5'd4;
//---input data count---
always@(posedge clk or negedge rst_n)
if(~rst_n)
i_cnt <= 5'b0;
else if(clr | olast) //hold the last value, i.e. the number of frame data till they're all read
i_cnt <= 5'b0;
else if(den)
i_cnt <= i_cnt + 5'b1;
//---output data count---
always@(posedge clk or negedge rst_n)
if(~rst_n)
o_cnt <= 5'b0;
else if(clr | olast) //clear the counter when all frame data are read
o_cnt <= 5'b0;
else if(rdrq)
o_cnt <= o_cnt + 5'b1;
//---flush the rest of the frame data out---
always@(posedge clk or negedge rst_n)
if(~rst_n)
flush <= 1'b0;
else if(clr | olast) //deasserted when all frame data are out of the buffer
flush <= 1'b0;
else if(iend) //asserted when all frame data are in the buffer
flush <= 1'b1;
//---input ready, input data allowed to be in when asserted, and forbidden when deasserted---
always@(posedge clk or negedge rst_n)
if(~rst_n)
irdy <= 1'b0;
else if(clr)
irdy <= 1'b0;
else if(flush | iend) //input forbidden during flush
irdy <= 1'b0;
else if((cnt < IL_LIM) | (cnt == IL_LIM))
irdy <= 1'b1;
else if((cnt > IH_LIM) | (cnt == IH_LIM))
irdy <= 1'b0;
//---output ready, output request responded accordingly when asserted, and forbidden when deasserted---
always@(posedge clk or negedge rst_n)
if(~rst_n)
ordy <= 1'b0;
else if(clr)
ordy <= 1'b0;
else if(flush) //output available during flush
begin
if(olast)
ordy <= 1'b0;
else
ordy <= 1'b1;
end
else if((cnt < OL_LIM) | (cnt == OL_LIM))
ordy <= 1'b0;
else if((cnt > OH_LIM) | (cnt == OH_LIM))
ordy <= 1'b1;
//---the last-data output indicator---
assign olast = rdrq & flush & (o_cnt == i_cnt - 5'd1);
//---indicate overflowing---
always@(posedge clk or negedge rst_n)
if(~rst_n)
ovfl <= 1'b0;
else if(clr)
ovfl <= 1'b0;
else if(full & den)
ovfl <= 1'b1;
//---indicate underflowing---
always@(posedge clk or negedge rst_n)
if(~rst_n)
udfl <= 1'b0;
else if(clr)
udfl <= 1'b0;
else if(empty & rdrq)
udfl <= 1'b1;
//---buffering FIFO---
fifo_sync_32_512i512o mfifo_buf (
.clk(clk), // input clk
.rst(~rst_n | clr), // input rst
.din(din), // input [511 : 0] din
.wr_en(den), // input wr_en
.rd_en(rdrq), // input rd_en
.valid(dv), // output dv
.dout(dout), // output [511 : 0] dout
.full(full), // output full
.empty(empty), // output empty
.data_count(cnt) // output [4 : 0] data_count
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSTP_2_V
`define SKY130_FD_SC_HD__SDFSTP_2_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfstp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfstp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSTP_2_V
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { int h1, a1, c1; int h2, a2; cin >> h1 >> a1 >> c1; cin >> h2 >> a2; int th1 = h1; int th2 = h2; int count = 0; while (th2 > 0) { if (th1 > a2 || th2 - a1 <= 0) { count++; th2 = th2 - a1; th1 = th1 - a2; } else { count++; th1 = th1 + c1; th1 = th1 - a2; } } cout << count << n ; while (h2 > 0) { if (h1 > a2 || h2 - a1 <= 0) { h2 = h2 - a1; h1 = h1 - a2; cout << STRIKE n ; } else { h1 = h1 + c1; h1 = h1 - a2; cout << HEAL n ; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_SYMBOL_V
`define SKY130_FD_SC_MS__NOR2B_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long a[1000010]; long long l[1000010], r[1000010]; vector<pair<int, int>> g1[1000010], g2[1000010]; int n, q; long long ans[1000010]; const int N = 1000000; long long sum[N * 4]; long long flag[N * 4]; int cnt_v; void build(int n) { cnt_v = 1; while (cnt_v <= n) { cnt_v <<= 1; } memset(sum, 0, sizeof(sum)); memset(flag, 0, sizeof(flag)); } void push_down(int t, long long l, long long r) { if (flag[t]) { long long mid = (l + r) >> 1; sum[t << 1] += flag[t] * (mid - l + 1); sum[(t << 1) + 1] += flag[t] * (r - mid); flag[t << 1] += flag[t]; flag[(t << 1) + 1] += flag[t]; flag[t] = 0; } } void push_up(int t) { sum[t] = sum[t << 1] + sum[(t << 1) + 1]; } void upd(int x, int lx, int rx, int l, int r) { if (lx > rx) return; if (l > rx || r < lx) return; if (lx >= l && rx <= r) { sum[x] += (rx - lx + 1); flag[x]++; return; } { push_down(x, lx, rx); upd(x * 2, lx, (lx + rx) / 2, l, r); upd(x * 2 + 1, (lx + rx) / 2 + 1, rx, l, r); push_up(x); } } long long get(int x, int lx, int rx, int l, int r) { if (lx > rx) return 0; if (l > rx || r < lx) return 0; if (lx >= l && rx <= r) { return sum[x]; } else { push_down(x, lx, rx); return get(x * 2, lx, (lx + rx) / 2, l, r) + get(x * 2 + 1, (lx + rx) / 2 + 1, rx, l, r); } } void init() { build(n); } void upd(long long l, long long r, long long val) { upd(1, 1, cnt_v, l, r); } long long get_sum(long long l, long long r) { long long t = get(1, 0, cnt_v, l, r); return t; } pair<int, int> st[1000040]; int main() { scanf( %d%d , &n, &q); for (int i = 1; i < n + 1; ++i) { scanf( %lld , &a[i]); } for (int i = 0; i < q; ++i) { scanf( %lld , &l[i]); } for (int i = 0; i < q; ++i) { scanf( %lld , &r[i]); } for (int i = 0; i < q; ++i) { g1[l[i]].push_back(make_pair(r[i], i)); g2[r[i]].push_back(make_pair(l[i], i)); } init(); stack<pair<long long, int>> st; st.push(make_pair(10000000, 0)); for (int i = 1; i < n + 1; ++i) { while (!st.empty() && a[i] > st.top().first) { st.pop(); } long long s = st.top().second + 1; long long e = i; upd(s, e, 1); st.push(make_pair(a[i], i)); for (int j = 0; j < g2[i].size(); ++j) { long long s = g2[i][j].first; int id = g2[i][j].second; ans[id] += get_sum(s, i); } } init(); while (!st.empty()) st.pop(); st.push(make_pair(10000000, n + 1)); for (int i = n; i > 0; --i) { while (!st.empty() && a[i] > st.top().first) { st.pop(); } long long s = i; long long e = st.top().second - 1; upd(s, e, 1); st.push(make_pair(a[i], i)); for (int j = 0; j < g1[i].size(); ++j) { long long e = g1[i][j].first; int id = g1[i][j].second; ans[id] += get_sum(i, e); } } for (int i = 0; i < q; ++i) { printf( %lld , ans[i] - (r[i] - l[i] + 1)); } cout << endl; } |
#include <bits/stdc++.h> using namespace std; long long const M = 2e5 + 10, M2 = 1e5 + 10, mod = 1e9 + 7, inf = 1e9 + 10; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; long long tmp = 1; for (long long i = 1;; i++) { if (tmp - 1 >= n) return cout << i - 1, 0; tmp *= 2; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFINV_BEHAVIORAL_V
`define SKY130_FD_SC_MS__BUFINV_BEHAVIORAL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__bufinv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFINV_BEHAVIORAL_V |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: readmemh function - data file length less than array
//
//
module main ();
reg [7:0] array [0:7];
reg error ;
reg [3:0] count;
initial
begin
error = 0;
/* pre init the array to all zeroes. */
for(count = 0; count <= 7; count = count + 1)
array[count] = 8'h0;
$readmemh("ivltests/readmemh2.dat",array);
for(count = 0; count <= 3; count = count + 1)
begin
if(array[count[2:0]] !== count)
begin
error = 1;
$display("FAILED - array[count] == %h, s/b %h",
array[count],count);
end
end
if(array[4] !== 8'h0)
begin
error = 1;
$display("FAILED - array[4] == %h, s/b 0",
array[count]);
end
if(error == 0)
$display("PASSED\n");
$finish ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int fast_exp(long long int base, long long int exp1) { long long int res = 1; while (exp1 > 0) { if (exp1 & 1) res = (res * base) % 1000000007; base = (base * base) % 1000000007; exp1 /= 2; } return res % 1000000007; } long long int pr[100001] = {0}; void isprime() { pr[0] = 1; pr[1] = 1; for (long long int a = 2; a <= 100001; a++) { if (!pr[a]) { for (long long int b = a; b < 100001; b += a) { pr[b] = a; } } } } long long int comp = 1, tim = 0; struct vertex { vector<long long int> adj; long long int vis = 0; long long int parent = -1; long long int dist = 0; long long int component = 0; long long int in = 0; long long int out = 0; long long int low = 0; long long int child = 0; long long int indeg = 0; long long int outdeg = 0; bool AP = false; }; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); isprime(); long long int n; cin >> n; long long int x[n]; long long int dp[100001] = {0}; for (long long int a = 0; a < n; a++) { long long int b; cin >> b; long long int k = b; while (k > 1) { long long int p = pr[k]; dp[b] = max(dp[b], dp[p] + 1); while (k % p == 0) k /= p; } k = b; while (k > 1) { long long int p = pr[k]; dp[p] = max(dp[p], dp[b]); while (k % p == 0) k /= p; } if (b == 1) dp[1] = 1; } cout << *max_element(dp, dp + 100001) << endl; return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_6_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_6_e.v,v 1.3 2006/06/26 08:39:42 wig Exp $
// $Date: 2006/06/26 08:39:42 $
// $Log: inst_6_e.v,v $
// Revision 1.3 2006/06/26 08:39:42 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_6_e
//
// No `defines in this module
module inst_6_e
//
// Generated Module inst_6
//
(
);
// Module parameters:
parameter FOO = 34;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_6_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <iostream> #include <string> #include <algorithm> #include <map> #include <vector> #include <cmath> #include <queue> #include <set> #include <bitset> using namespace std; typedef long long ll; ll MOD = 1000000007; void solve(int testCase) { ll n; cin >> n; for (int i = 0; i * 2020 <= n; i++) { if ((n - i * 2020) % 2021 == 0) { cout << YES << endl; return; } } cout << NO << endl; } int main() { int t; cin >> t; //t = 1; int i = 1; while (t--) { solve(i++); } return 0; } |
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 1532 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4,
w3,
w384,
w383,
w1532;
assign w1 = i_data0;
assign w1532 = w383 << 2;
assign w3 = w4 - w1;
assign w383 = w384 - w1;
assign w384 = w3 << 7;
assign w4 = w1 << 2;
assign o_data0 = w1532;
//multiplier_block area estimate = 3286.48311563824;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [7:0] crc;
// Build up assignments
wire [7:0] bitrev;
assign bitrev[7] = crc[0];
assign bitrev[6] = crc[1];
assign bitrev[5] = crc[2];
assign bitrev[4] = crc[3];
assign bitrev[0] = crc[7];
assign bitrev[1] = crc[6];
assign bitrev[2] = crc[5];
assign bitrev[3] = crc[4];
// Build up always assignments
reg [7:0] bitrevb;
always @ (/*AS*/crc) begin
bitrevb[7] = crc[0];
bitrevb[6] = crc[1];
bitrevb[5] = crc[2];
bitrevb[4] = crc[3];
bitrevb[0] = crc[7];
bitrevb[1] = crc[6];
bitrevb[2] = crc[5];
bitrevb[3] = crc[4];
end
// Build up always assignments
reg [7:0] bitrevr;
always @ (posedge clk) begin
bitrevr[7] <= crc[0];
bitrevr[6] <= crc[1];
bitrevr[5] <= crc[2];
bitrevr[4] <= crc[3];
bitrevr[0] <= crc[7];
bitrevr[1] <= crc[6];
bitrevr[2] <= crc[5];
bitrevr[3] <= crc[4];
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
//$write("cyc=%0d crc=%x r=%x\n", cyc, crc, bitrev);
crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
if (cyc==1) begin
crc <= 8'hed;
end
if (cyc==2 && bitrev!=8'hb7) $stop;
if (cyc==3 && bitrev!=8'h5b) $stop;
if (cyc==4 && bitrev!=8'h2d) $stop;
if (cyc==5 && bitrev!=8'h16) $stop;
if (cyc==6 && bitrev!=8'h8b) $stop;
if (cyc==7 && bitrev!=8'hc5) $stop;
if (cyc==8 && bitrev!=8'he2) $stop;
if (cyc==9 && bitrev!=8'hf1) $stop;
if (bitrevb != bitrev) $stop;
if (cyc==3 && bitrevr!=8'hb7) $stop;
if (cyc==4 && bitrevr!=8'h5b) $stop;
if (cyc==5 && bitrevr!=8'h2d) $stop;
if (cyc==6 && bitrevr!=8'h16) $stop;
if (cyc==7 && bitrevr!=8'h8b) $stop;
if (cyc==8 && bitrevr!=8'hc5) $stop;
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxk = 999 + 5; int a[maxk]; vector<int> vec; int main() { int n, k, p, x, y; scanf( %d%d%d%d%d , &n, &k, &p, &x, &y); for (int i = 0; i < k; i++) scanf( %d , a + i); if (y > p) { printf( -1 n ); return 0; } sort(a, a + k); for (int one = 0, now = 0; one <= n - k; one++) { now = 0; vec.clear(); for (int i = 0; i < one; i++) { now++; vec.push_back(1); } for (int i = 0; i < k; i++) { now += a[i]; vec.push_back(a[i]); } for (; vec.size() < n;) { vec.push_back(y); now += y; } if (now > x) continue; sort(vec.begin(), vec.end()); if (vec[(n + 1) / 2 - 1] >= y) { vector<int> ans; for (int i = 0; i < one; i++) ans.push_back(1); for (int i = 0; i < n - (one + k); i++) ans.push_back(y); for (int i = 0; i < ans.size(); i++) printf( %d%c , ans[i], i == ans.size() - 1 ? n : ); return 0; } } printf( -1 n ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2510; const int INF = 0x3f3f3f3f; int prime[400]; bool isprime[N]; int k; void init() { k = 0; for (int i = 2; i <= N; i++) { if (!isprime[i]) { prime[k++] = i; for (int j = i + i; j <= N; j += i) isprime[j] = 1; } } } char s[N]; int ma[N * 2][N * 2], pre[N * 2][N * 2]; int main() { init(); memset(pre, 0, sizeof(pre)); int n, m; scanf( %d%d , &n, &m); for (int i = 1; i < 2 * N; i++) { if (i <= n) scanf( %s , s + 1); int tmp = 0; for (int j = 1; j <= m; j++) { if (i > n) ma[i][j] = 0; else { if (s[j] == 0 ) ma[i][j] = 0; else { ma[i][j] = 1; tmp++; } } pre[i][j] = tmp + pre[i - 1][j]; } for (int j = m + 1; j < N * 2; j++) { pre[i][j] = tmp + pre[i - 1][j]; } } int ans = INF; for (int f = 0; f < k; f++) { int p = prime[f]; int res = 0; for (int i = p; i < n + p; i += p) { for (int j = p; j < m + p; j += p) { int ff = pre[i][j] + pre[i - p][j - p] - pre[i][j - p] - pre[i - p][j]; res = res + min(p * p - ff, ff); } } ans = min(ans, res); } printf( %d n , ans); return 0; } |
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream UART
*/
module uart_rx #
(
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
input wire m_axis_tready,
/*
* UART interface
*/
input wire rxd,
/*
* Status
*/
output wire busy,
output wire overrun_error,
output wire frame_error,
/*
* Configuration
*/
input wire [15:0] prescale
);
reg [DATA_WIDTH-1:0] m_axis_tdata_reg = 0;
reg m_axis_tvalid_reg = 0;
reg rxd_reg = 1;
reg busy_reg = 0;
reg overrun_error_reg = 0;
reg frame_error_reg = 0;
reg [DATA_WIDTH-1:0] data_reg = 0;
reg [18:0] prescale_reg = 0;
reg [3:0] bit_cnt = 0;
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tvalid = m_axis_tvalid_reg;
assign busy = busy_reg;
assign overrun_error = overrun_error_reg;
assign frame_error = frame_error_reg;
always @(posedge clk) begin
if (rst) begin
m_axis_tdata_reg <= 0;
m_axis_tvalid_reg <= 0;
rxd_reg <= 1;
prescale_reg <= 0;
bit_cnt <= 0;
busy_reg <= 0;
overrun_error_reg <= 0;
frame_error_reg <= 0;
end else begin
rxd_reg <= rxd;
overrun_error_reg <= 0;
frame_error_reg <= 0;
if (m_axis_tvalid && m_axis_tready) begin
m_axis_tvalid_reg <= 0;
end
if (prescale_reg > 0) begin
prescale_reg <= prescale_reg - 1;
end else if (bit_cnt > 0) begin
if (bit_cnt > DATA_WIDTH+1) begin
if (!rxd_reg) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3)-1;
end else begin
bit_cnt <= 0;
prescale_reg <= 0;
end
end else if (bit_cnt > 1) begin
bit_cnt <= bit_cnt - 1;
prescale_reg <= (prescale << 3)-1;
data_reg <= {rxd_reg, data_reg[DATA_WIDTH-1:1]};
end else if (bit_cnt == 1) begin
bit_cnt <= bit_cnt - 1;
if (rxd_reg) begin
m_axis_tdata_reg <= data_reg;
m_axis_tvalid_reg <= 1;
overrun_error_reg <= m_axis_tvalid_reg;
end else begin
frame_error_reg <= 1;
end
end
end else begin
busy_reg <= 0;
if (!rxd_reg) begin
prescale_reg <= (prescale << 2)-2;
bit_cnt <= DATA_WIDTH+2;
data_reg <= 0;
busy_reg <= 1;
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A221OI_FUNCTIONAL_PP_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a221oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y , and0_out, C1, and1_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221OI_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 6010; int ans, f[maxn], r[maxn], m[maxn][maxn]; void dfs(int x, int y, int p) { int k = lower_bound(f, f + p, r[x]) - f; int t = f[k]; f[k] = r[x]; ans = max(ans, k); p = max(k + 1, p); for (int i = 1; i <= m[x][0]; i++) if (m[x][i] != y) dfs(m[x][i], x, p); f[k] = t; } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , r + i); for (int i = 1; i < n; i++) { int a, b; scanf( %d%d , &a, &b); m[a][++m[a][0]] = b; m[b][++m[b][0]] = a; } for (int i = 1; i <= n; i++) dfs(i, 0, 1); printf( %d n , ans); return 0; } |
#include <stdio.h> // #include <iostream> #include <algorithm> // #include <cmath> // #include <string> // #include <string.h> // #include <vector> // #include <bits/stdc++.h> using namespace std; // const int INF32 = 2000000000; // const int INF64 = 2000000000000000000; // const int MOD17 = 1000000007; int tc, n, arr[200002]; int main(){ //freopen( input.txt , r , stdin); //freopen( output.txt , w , stdout); scanf( %d , &tc); while(tc--){ scanf( %d , &n); for(int i = 0; i < n; i++){ scanf( %d , &arr[i]); } if(n == 1 || n == 2){ printf( 0 n ); continue; } sort(arr, arr+n); int j = 0; long long ans = 0; for(int i = 0; i < n; i++){ if(j < i) j = i; while(j+1 < n && arr[j+1] - arr[i] <= 2) j++; if(j - i > 1){ ans += (long long) (j-i-1)*(j-i)>>1; } } printf( %lld n , ans); } return 0; } |
#include <bits/stdc++.h> int main() { int n, i, j; int a[110][110]; long long ans[150]; while (scanf( %d , &n) != EOF) { for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) scanf( %d , &a[i][j]); memset(ans, 0, sizeof(ans)); for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { if (i == j) continue; if (a[i][j] == -1) continue; ans[i] = ans[i] | a[i][j]; } } for (i = 1; i <= n; i++) if (i == 1) printf( %I64d , ans[i]); else printf( %I64d , ans[i]); printf( n ); } return 0; } |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: offset_flag_to_one_hot.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The offset_flag_to_one_hot module takes a data offset,
// and offset_enable and computes the 1-hot encoding of the offset when enabled
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
module offset_flag_to_one_hot
#(
parameter C_WIDTH = 4
)
(
input [clog2s(C_WIDTH)-1:0] WR_OFFSET,
input WR_FLAG,
output [C_WIDTH-1:0] RD_ONE_HOT
);
`include "functions.vh"
assign RD_ONE_HOT = {{(C_WIDTH-1){1'b0}},WR_FLAG} << WR_OFFSET;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Non-restoring unsigned divider ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: div_uu.v,v 1.3 2003-09-17 13:08:53 rherveille Exp $
//
// $Date: 2003-09-17 13:08:53 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/10/31 13:54:58 rherveille
// Fixed a bug in the remainder output of div_su.v
//
// Revision 1.1.1.1 2002/10/29 20:29:10 rherveille
//
//
//
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
module div_uu(clk, ena, z, d, q, s, div0, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width -1:0] z; // divident
input [d_width -1:0] d; // divisor
output [d_width -1:0] q; // quotient
output [d_width -1:0] s; // remainder
output div0;
output ovf;
reg [d_width-1:0] q;
reg [d_width-1:0] s;
reg div0;
reg ovf;
//
// functions
//
function [z_width:0] gen_s;
input [z_width:0] si;
input [z_width:0] di;
begin
if(si[z_width])
gen_s = {si[z_width-1:0], 1'b0} + di;
else
gen_s = {si[z_width-1:0], 1'b0} - di;
end
endfunction
function [d_width-1:0] gen_q;
input [d_width-1:0] qi;
input [z_width:0] si;
begin
gen_q = {qi[d_width-2:0], ~si[z_width]};
end
endfunction
function [d_width-1:0] assign_s;
input [z_width:0] si;
input [z_width:0] di;
reg [z_width:0] tmp;
begin
if(si[z_width])
tmp = si + di;
else
tmp = si;
assign_s = tmp[z_width-1:z_width-d_width];
end
endfunction
//
// variables
//
reg [d_width-1:0] q_pipe [d_width-1:0];
reg [z_width:0] s_pipe [d_width:0];
reg [z_width:0] d_pipe [d_width:0];
reg [d_width:0] div0_pipe, ovf_pipe;
//
// perform parameter checks
//
// synopsys translate_off
initial
begin
if(d_width !== z_width / 2)
$display("div.v parameter error (d_width != z_width/2).");
end
// synopsys translate_on
integer n0, n1, n2, n3;
// generate divisor (d) pipe
always @(d)
d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
always @(posedge clk)
if(ena)
for(n0=1; n0 <= d_width; n0=n0+1)
d_pipe[n0] <= #1 d_pipe[n0-1];
// generate internal remainder pipe
always @(z)
s_pipe[0] <= z;
always @(posedge clk)
if(ena)
for(n1=1; n1 <= d_width; n1=n1+1)
s_pipe[n1] <= #1 gen_s(s_pipe[n1-1], d_pipe[n1-1]);
// generate quotient pipe
always @(posedge clk)
q_pipe[0] <= #1 0;
always @(posedge clk)
if(ena)
for(n2=1; n2 < d_width; n2=n2+1)
q_pipe[n2] <= #1 gen_q(q_pipe[n2-1], s_pipe[n2]);
// flags (divide_by_zero, overflow)
always @(z or d)
begin
ovf_pipe[0] <= !(z[z_width-1:d_width] < d);
div0_pipe[0] <= ~|d;
end
always @(posedge clk)
if(ena)
for(n3=1; n3 <= d_width; n3=n3+1)
begin
ovf_pipe[n3] <= #1 ovf_pipe[n3-1];
div0_pipe[n3] <= #1 div0_pipe[n3-1];
end
// assign outputs
always @(posedge clk)
if(ena)
ovf <= #1 ovf_pipe[d_width];
always @(posedge clk)
if(ena)
div0 <= #1 div0_pipe[d_width];
always @(posedge clk)
if(ena)
q <= #1 gen_q(q_pipe[d_width-1], s_pipe[d_width]);
always @(posedge clk)
if(ena)
s <= #1 assign_s(s_pipe[d_width], d_pipe[d_width]);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, q, l[N], r[N], level[N], p[N][20], res[N]; int import[N], numCity, numVirus; vector<int> adj[N]; vector<pair<int, int> > newAdj[N]; struct T { int city, speed; }; T virus[N]; pair<pair<int, int>, int> top; struct Less { bool operator()(const pair<pair<int, int>, int>& x, const pair<pair<int, int>, int>& y) { int a = x.first.first / virus[x.first.second].speed, b = y.first.first / virus[y.first.second].speed; if (a != b) return a > b; return x.first.second > y.first.second; } }; priority_queue<pair<pair<int, int>, int>, vector<pair<pair<int, int>, int> >, Less> pq; int T; void dfs(int u) { for (int i = 1; i <= 18; i++) p[u][i] = p[p[u][i - 1]][i - 1]; l[u] = ++T; for (int v : adj[u]) { if (v == p[u][0]) continue; level[v] = level[u] + 1; p[v][0] = u; dfs(v); } r[u] = T; } int lca(int u, int v) { if (level[u] < level[v]) swap(u, v); for (int i = 18; i >= 0; --i) if (level[u] - (1 << i) >= level[v]) u = p[u][i]; if (u == v) return u; for (int i = 18; i >= 0; --i) if (p[u][i] != p[v][i]) u = p[u][i], v = p[v][i]; return p[u][0]; } int dist(int x, int y) { return level[x] + level[y] - 2 * level[lca(x, y)]; } vector<pair<int, int> > all; void compress_tree() { all.clear(); for (int i = 1; i <= numVirus; i++) all.push_back(make_pair(l[virus[i].city], virus[i].city)); for (int i = 1; i <= numCity; i++) all.push_back(make_pair(l[import[i]], import[i])); sort(all.begin(), all.end()); all.erase(unique(all.begin(), all.end()), all.end()); int sz = all.size(); for (int i = 1; i < sz; i++) { int p = lca(all[i].second, all[i - 1].second); all.push_back(make_pair(l[p], p)); } sort(all.begin(), all.end()); all.erase(unique(all.begin(), all.end()), all.end()); vector<int> st; for (auto& u : all) { newAdj[u.second].clear(); while (st.size() && r[st.back()] < u.first) st.pop_back(); if (st.size()) { int dist = level[u.second] - level[st.back()]; newAdj[st.back()].push_back(make_pair(u.second, dist)); newAdj[u.second].push_back(make_pair(st.back(), dist)); } st.push_back(u.second); } } void solve() { for (auto& x : all) res[x.second] = -1; for (int i = 1; i <= numVirus; i++) pq.push({{virus[i].speed - 1, i}, virus[i].city}); while (pq.size()) { top = pq.top(); pq.pop(); if (res[top.second] != -1) continue; res[top.second] = top.first.second; for (auto u : newAdj[top.second]) { if (res[u.first] != -1) continue; pq.push({{top.first.first + u.second, top.first.second}, u.first}); } } for (int i = 1; i <= numCity; i++) cout << res[import[i]] << ; cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dfs(1); cin >> q; while (q--) { cin >> numVirus >> numCity; for (int i = 1; i <= numVirus; i++) cin >> virus[i].city >> virus[i].speed; for (int i = 1; i <= numCity; i++) cin >> import[i]; compress_tree(); solve(); } } |
#include <bits/stdc++.h> using namespace std; const int M = 512; const int T = 101; int n, m; long long a[M][M]; long long b[M][M]; int t; int x[T], y[T]; void solve(int xl, int xr, int yl, int yr) { if (xl == xr && yl == yr) { b[xl][yl] = a[xl][yl]; } else if (xl != xr) { int tm = (xr - xl + 1); int um = (yr - yl + 1); for (int i = xl; i < xl + tm / 2; i++) { for (int j = yl; j <= yr; j++) a[i + tm / 2][j] ^= a[i][j]; } solve(xl + tm / 2, xr, yl, yr); for (int i = xl; i < xl + tm / 2; i++) { for (int j = yl; j <= yr; j++) a[i + tm / 2][j] ^= a[i][j]; } for (int i = xl + tm / 2; i <= xr; i++) { for (int j = yl; j <= yr; j++) { for (int k = 1; k <= t; k++) { if ((i + x[k]) % tm < tm / 2) a[xl + (i + x[k]) % tm][yl + (j + y[k]) % um] ^= b[i][j]; } } } solve(xl, xl + tm / 2 - 1, yl, yr); for (int i = xl + tm / 2; i <= xr; i++) { for (int j = yl; j <= yr; j++) { for (int k = 1; k <= t; k++) { if ((i + x[k]) % tm < tm / 2) a[xl + (i + x[k]) % tm][yl + (j + y[k]) % um] ^= b[i][j]; } b[i][j] ^= b[i - tm / 2][j]; } } } else { int tm = (xr - xl + 1); int um = (yr - yl + 1); for (int i = xl; i <= xr; i++) { for (int j = yl; j < yl + um / 2; j++) a[i][j + um / 2] ^= a[i][j]; } solve(xl, xr, yl + um / 2, yr); for (int i = xl; i <= xr; i++) { for (int j = yl; j < yl + um / 2; j++) a[i][j + um / 2] ^= a[i][j]; } for (int i = xl; i <= xr; i++) { for (int j = yl + um / 2; j <= yr; j++) { for (int k = 1; k <= t; k++) { if ((j + y[k]) % um < um / 2) a[xl + (i + x[k]) % tm][yl + (j + y[k]) % um] ^= b[i][j]; } } } solve(xl, xr, yl, yl + um / 2 - 1); for (int i = xl; i <= xr; i++) { for (int j = yl + um / 2; j <= yr; j++) { for (int k = 1; k <= t; k++) { if ((j + y[k]) % um < um / 2) a[xl + (i + x[k]) % tm][yl + (j + y[k]) % um] ^= b[i][j]; } b[i][j] ^= b[i][j - um / 2]; } } } } int main() { ios::sync_with_stdio(false); cin >> n; m = 1 << n; for (int i = 0; i < m; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } } cin >> t; for (int i = 1; i <= t; i++) { cin >> x[i] >> y[i]; } solve(0, m - 1, 0, m - 1); int ans = 0; for (int i = 0; i < m; i++) { for (int j = 0; j < m; j++) { ans += (b[i][j] != 0); } } cout << ans << n ; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Helper module to handle bursting large sequential blocks of memory to or
// from global memory.
//
/*****************************************************************************/
// Burst read master:
// Keeps a local buffer populated with data from a sequential block of
// global memory. The block of global memory is specified by a base address
// and size.
/*****************************************************************************/
module lsu_burst_read_master (
clk,
reset,
o_active, //Debugging signal
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_go,
control_done,
control_early_done,
// user logic inputs and outputs
user_read_buffer,
user_buffer_data,
user_data_available,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_burstcount,
master_waitrequest
);
/*************
* Parameters *
*************/
parameter DATAWIDTH = 32;
parameter MAXBURSTCOUNT = 4;
parameter BURSTCOUNTWIDTH = 3;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
parameter READTHRESHOLD = FIFODEPTH - MAXBURSTCOUNT - 4;
/********
* Ports *
********/
input clk;
input reset;
output o_active;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
output wire control_done;
output wire control_early_done; // don't use this unless you know what you are doing, it's going to fire when the last read is posted, not when the last data returns!
// user logic inputs and outputs
input user_read_buffer;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
/***************
* Architecture *
***************/
// internal control signals
reg control_fixed_location_d1;
wire fifo_empty;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
reg [FIFODEPTH_LOG2-1:0] reads_pending;
wire increment_address;
wire [BURSTCOUNTWIDTH-1:0] burst_count;
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire first_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire final_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
wire too_many_reads_pending;
wire [FIFODEPTH_LOG2-1:0] fifo_used;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, increment by the burst count presented
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
length <= length - (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, decrement by the burst count presented
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign master_burstcount = burst_count;
assign control_done = (length == 0) & (reads_pending == 0); // need to make sure that the reads have returned before firing the done bit
assign control_early_done = (length == 0); // advanced feature, you should use 'control_done' if you need all the reads to return first
assign master_read = (too_many_reads_pending == 0) & (length != 0);
assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
assign first_short_burst_enable = (burst_boundary_word_address != 0);
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
assign final_short_burst_count = (length / BYTEENABLEWIDTH);
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // this will get the transfer back on a burst boundary,
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address = (too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
assign too_many_reads_pending = (reads_pending + fifo_used) >= READTHRESHOLD; // make sure there are fewer reads posted than room in the FIFO
// tracking FIFO
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
reads_pending <= 0;
end
else
begin
if(increment_address == 1)
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending + burst_count;
end
else
begin
reads_pending <= reads_pending + burst_count - 1; // a burst read was posted, but a word returned
end
end
else
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending; // burst read was not posted and no read returned
end
else
begin
reads_pending <= reads_pending - 1; // burst read was not posted but a word returned
end
end
end
end
assign o_active = |reads_pending;
// read data feeding user logic
assign user_data_available = !fifo_empty;
scfifo the_master_to_user_fifo (
.aclr (reset),
.clock (clk),
.data (master_readdata),
.empty (fifo_empty),
.q (user_buffer_data),
.rdreq (user_read_buffer),
.usedw (fifo_used),
.wrreq (master_readdatavalid),
.almost_empty(),
.almost_full(),
.full(),
.sclr()
);
defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
defparam the_master_to_user_fifo.lpm_widthu = FIFODEPTH_LOG2;
defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
defparam the_master_to_user_fifo.lpm_showahead = "ON";
defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
defparam the_master_to_user_fifo.underflow_checking = "OFF";
defparam the_master_to_user_fifo.overflow_checking = "OFF";
initial
if ( READTHRESHOLD > FIFODEPTH ||
READTHRESHOLD > FIFODEPTH - 4 ||
READTHRESHOLD < 1 )
$error("Invalid FIFODEPTH and MAXBURSTCOUNT comination. Produced READTHRESHOLD = %d\n",READTHRESHOLD);
endmodule
|
/* talu - a verilog test,
* illustrating problems I had in fragments of an ALU from an 8-bit micro
*/
module talu;
reg error;
reg [7:0] a;
reg [7:0] b;
reg cin;
reg [1:0] op;
wire cout;
wire [7:0] aluout;
alu alu_m(a, b, cin, op, aluout, cout);
initial begin
error = 0;
// add
op='b00; cin='b0; a='h0; b='h0;
#2 if({cout, aluout} != 9'h000) begin
$display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout);
error = 1;
end
// add1
op='b01; cin='b0; a='h01; b='h01;
#2 if({cout, aluout} != 9'h103) begin
$display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout);
error = 1;
end
// and
op='b10; cin='b0; a='h16; b='h0F;
#2 if({cout, aluout} != 9'h006) begin
$display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout);
error = 1;
end
op='b10; cin='b0; a='h28; b='hF7;
#2 if({cout, aluout} != 9'h020) begin
$display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout);
error = 1;
end
// genbit
op='b11; cin='b0; a='h00; b='h03;
#2 if({cout, aluout} != 9'h008) begin
$display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout);
error = 1;
end
op='b11; cin='b0; a='h00; b='h00;
#2 if({cout, aluout} != 9'h001) begin
$display($time, " FAILED %b %b %h %h %b %h", op, cin, a, b, cout, aluout);
error = 1;
end
/* tests are incomplete - doesn't compile yet on ivl */
if(error == 0)
$display("PASSED");
$finish;
end
endmodule
/*
* fragments of an ALU from an 8-bit micro
*/
module alu(Aval, Bval, cin, op, ALUout, cout);
input [7:0] Aval;
input [7:0] Bval;
input cin;
input [1:0] op;
output cout;
output [7:0] ALUout;
reg cout;
reg [7:0] ALUout;
always @(Aval or Bval or cin or op) begin
case(op)
2'b00 : {cout, ALUout} = Aval + Bval;
2'b10 : {cout, ALUout} = {1'b0, Aval & Bval};
// C++ compilation troubles with both of these:
2'b01 : {cout, ALUout} = 9'h100 ^ (Aval + Bval + 9'h001);
2'b11 : {cout, ALUout} = {1'b0, 8'b1 << Bval};
// 2'b01 : {cout, ALUout} = 9'h000;
// 2'b11 : {cout, ALUout} = 9'h000;
endcase
end // always @ (Aval or Bval or cin or op)
endmodule
/* Copyright (C) 1999 Stephen G. Tell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
|
#include <bits/stdc++.h> void answer(unsigned long long v) { std::cout << v << n ; } void solve(unsigned n, unsigned k) { const auto s = n * (n - 1ull) / 2; if (k > n / 2) return answer(s); const auto m = n - 2 * k; const auto d = m * (m - 1ull) / 2; answer(s - d); } int main() { unsigned n, k; std::cin >> n >> k; solve(n, k); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int m, k, n, s; cin >> m >> k >> n >> s; int len = m - k * (n - 1); vector<int> a(m); for (auto& i : a) { cin >> i; } int bad = 0; vector<int> cnt(5e5 + 1); for (int i = 0; i < s; ++i) { int b; cin >> b; bad += !cnt[b]; ++cnt[b]; } bool ok = false; vector<int> ans; for (int i = 0; i < m; ++i) { --cnt[a[i]]; bad -= !cnt[a[i]]; int j = i - len + 1; if (j >= 0) { if (!bad && j % k == 0) { for (int l = j; len - int(ans.size()) > k; ++l) { if (cnt[a[l]] < 0) { ans.push_back(l); ++cnt[a[l]]; } } ok = true; break; } bad += !cnt[a[j]]; ++cnt[a[j]]; } } if (!ok) { cout << -1 << n ; } else { cout << ans.size() << n ; for (auto i : ans) { cout << i + 1 << ; } } } |
#include <bits/stdc++.h> using namespace std; long long qk(long long x, long long y) { long long ans = 1; while (y) { if (y & 1) ans = ans * x % 1000000007; y >>= 1; x = x * x % 1000000007; } return ans; } const int dx[8] = {0, -1, 0, 1, -1, -1, 1, 1}, dy[8] = {-1, 0, 1, 0, -1, 1, -1, 1}; const int dxx[8] = {2, 1, -1, -2, -2, -1, 1, 2}, dyy[8] = {1, 2, 2, 1, -1, -2, -2, -1}; long long a[100005], b[100005]; void solve() { long long n, p; scanf( %lld%lld , &n, &p); for (int i = 1; i <= n; i++) { long long x, y; scanf( %lld%lld , &x, &y); a[i] = y / p - (x - 1) / p; b[i] = y - x + 1; } double ans = 0; for (int i = 1; i < n; i++) { double num = a[i] * b[i + 1]; num += a[i + 1] * (b[i] - a[i]); ans += 2000.0 * num / (double)(b[i] * b[i + 1]); } double num = a[n] * b[1]; num += a[1] * (b[n] - a[n]); ans += 2000.0 * num / (double)(b[n] * b[1]); printf( %.7lf n , ans); } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 100; const int MX = 200503; int N, M, k; int arr[MX]; int cnt[MX]; vector<int> G[MX]; int vis[MX]; vector<int> sr; void dfs(int x) { vis[x] = 1; for (int i = 0; i < G[x].size(); i++) { int ch = G[x][i]; if (vis[ch] == 1) { sr.push_back(ch); } else if (!vis[ch]) dfs(ch); } vis[x] = 2; } int get(int x, int p) { int ret = arr[x]; vis[x] = 1; for (int i = 0; i < G[x].size(); i++) { int ch = G[x][i]; if (vis[ch]) continue; ret = min(ret, get(ch, x)); } return ret; } int main() { scanf( %d , &N); for (int i = 1; i <= N; i++) { scanf( %d , &arr[i]); } for (int i = 1; i <= N; i++) { int x; scanf( %d , &x); G[i].push_back(x); } long long an = 0; for (int i = 1; i <= N; i++) if (vis[i] == 0) dfs(i); memset(vis, 0, sizeof vis); for (int i = 0; i < sr.size(); i++) an += get(sr[i], -1); cout << an << n ; return 0; } |
// soc_design_mm_interconnect_0_avalon_st_adapter_001.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_design_mm_interconnect_0_avalon_st_adapter_001_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 5; const int INF = 2e9; const int MOD = 1e9 + 7; int main() { vector<int> RES; string S = ; cin >> S; int N = S.size(), last = -1, depth = 0; for (int i = 0; i < N; i++) { if (S[i] == ( ) depth++; else { if (S[i] == # ) last = i; depth--; } if (depth < 0) return printf( -1 ), 0; } int val = depth; depth = 0; for (int i = 0; i < N; i++) { if (S[i] == ( ) depth++; else { int removeIt = (i == last && S[i] == # ? val : 0) + 1; depth -= removeIt; if (S[i] == # ) RES.push_back(removeIt); } if (depth < 0) return printf( -1 ), 0; } for (int i = 0; i < RES.size(); i++) printf( %i n , RES[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, flag; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; if (n == 2) cout << a[0] + 2 * (a[1] - a[0]); else { for (int i = 0; i < n - 2; i++) { if ((a[i + 2] - a[i + 1]) != (a[1 + i] - a[i])) { flag = 0; break; } else flag = 1; } if (flag) { cout << a[0] + (n) * (a[1] - a[0]); } else cout << a[n - 1]; } } |
#include <bits/stdc++.h> using namespace std; char str[100010]; int dp[26][100010]; int maxP[260][260][260]; int len[3]; int idx[3]; char desc[3][260]; int get(int rel) { int m = maxP[idx[0] - (rel == 0)][idx[1] - (rel == 1)][idx[2] - (rel == 2)]; if (m == 100010) return 100010; return dp[desc[rel][idx[rel] - 1] - a ][m]; } int main(void) { setbuf(stdout, 0); int N, Q; cin >> N >> Q; cin >> str; for (int i = 0; i < 26; i++) dp[i][N] = 100010; for (int i = 0; i < N; i++) { for (int j = 0; j < 26; j++) { if (str[N - 1 - i] == a + j) dp[j][N - 1 - i] = N - i; else dp[j][N - 1 - i] = dp[j][N - i]; } } for (int q = 0; q < Q; q++) { char o, c; int i; cin >> o >> i; i--; if (o == + ) { cin >> c; desc[i][len[i]++] = c; idx[i] = len[i]; if (i == 0) { for (int j = 0; j <= len[1]; j++) { idx[1] = j; for (int k = 0; k <= len[2]; k++) { idx[2] = k; maxP[len[0]][j][k] = get(i); if (j) maxP[len[0]][j][k] = min(maxP[len[0]][j][k], get(1)); if (k) maxP[len[0]][j][k] = min(maxP[len[0]][j][k], get(2)); } } } if (i == 1) { for (int j = 0; j <= len[0]; j++) { idx[0] = j; for (int k = 0; k <= len[2]; k++) { idx[2] = k; maxP[j][len[1]][k] = get(i); if (j) maxP[j][len[1]][k] = min(maxP[j][len[1]][k], get(0)); if (k) maxP[j][len[1]][k] = min(maxP[j][len[1]][k], get(2)); } } } if (i == 2) { for (int j = 0; j <= len[0]; j++) { idx[0] = j; for (int k = 0; k <= len[1]; k++) { idx[1] = k; maxP[j][k][len[2]] = get(i); if (j) maxP[j][k][len[2]] = min(maxP[j][k][len[2]], get(0)); if (k) maxP[j][k][len[2]] = min(maxP[j][k][len[2]], get(1)); } } } } else len[i]--; cout << (maxP[len[0]][len[1]][len[2]] < 100010 ? YES n : NO n ); } return 0; } |
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
module ovl_always_wrapped(
clk,
rst,
enable,
test_expr,
prevConfigInvalid,
out
);
input clk;
input rst;
input enable;
input test_expr;
input prevConfigInvalid;
output out;
wire [2:0] result_3bit;
wire [2:0] result_3bit_comb;
ovl_always ovl_always(
.clock(clk),
.reset(rst),
.enable(enable),
.test_expr(test_expr),
.fire(result_3bit),
.fire_comb(result_3bit_comb)
);
assign out = result_3bit_comb[0] & ~prevConfigInvalid;
endmodule
|
// -*- Mode: Verilog -*-
// Filename : wb_master_interface.v
// Description : Wishbone Bus Master
// Author : Philip Tracton
// Created On : Fri Nov 27 16:22:45 2015
// Last Modified By: Philip Tracton
// Last Modified On: Fri Nov 27 16:22:45 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module wb_master_interface (/*AUTOARG*/
// Outputs
wb_adr_o, wb_dat_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o,
wb_cti_o, wb_bte_o, data_rd, active,
// Inputs
wb_clk, wb_rst, wb_dat_i, wb_ack_i, wb_err_i, wb_rty_i, start,
address, selection, write, data_wr
) ;
parameter dw = 32;
parameter aw = 32;
parameter DEBUG = 0;
input wb_clk;
input wb_rst;
output reg [aw-1:0] wb_adr_o;
output reg [dw-1:0] wb_dat_o;
output reg [3:0] wb_sel_o;
output reg wb_we_o ;
output reg wb_cyc_o;
output reg wb_stb_o;
output reg [2:0] wb_cti_o;
output reg [1:0] wb_bte_o;
input [dw-1:0] wb_dat_i;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
input start;
input [aw-1:0] address;
input [3:0] selection;
input write;
input [dw-1:0] data_wr;
output reg [dw-1:0] data_rd;
output reg active;
reg [1:0] state;
reg [1:0] next_state;
parameter STATE_IDLE = 2'h0;
parameter STATE_WAIT_ACK = 2'h1;
parameter STATE_ERROR = 2'h3;
always @(posedge wb_clk)
if (wb_rst) begin
state <= STATE_IDLE;
end else begin
state <= next_state;
end
always @(*)
if (wb_rst) begin
next_state = STATE_IDLE;
active = 0;
wb_adr_o <= 0;
wb_dat_o <= 0;
wb_sel_o <= 0;
wb_we_o <= 0;
wb_cyc_o <= 0;
wb_stb_o <= 0;
wb_cti_o <= 0;
wb_bte_o <= 0;
data_rd <= 0;
end else begin // if (wb_rst)
case (state)
STATE_IDLE: begin
active = 0;
wb_adr_o = 0;
wb_dat_o = 0;
wb_sel_o = 0;
wb_we_o = 0;
wb_cyc_o = 0;
wb_stb_o = 0;
wb_cti_o = 0;
wb_bte_o = 0;
if (start) begin
next_state = STATE_WAIT_ACK;
wb_adr_o = address;
wb_dat_o = data_wr;
wb_sel_o = selection;
wb_we_o = write;
wb_cyc_o = 1;
wb_stb_o = 1;
wb_cti_o = 0;
wb_bte_o = 0;
active = 1;
data_rd =0;
end else begin
next_state = STATE_IDLE;
end
end // case: STATE_IDLE
STATE_WAIT_ACK: begin
if (wb_err_i || wb_rty_i) begin
next_state = STATE_ERROR;
end else if (wb_ack_i) begin
if (! wb_we_o)
data_rd = wb_dat_i;
next_state = STATE_IDLE;
end else begin
next_state = STATE_WAIT_ACK;
end
end // case: STATE_WAIT_ACK
STATE_ERROR: begin
next_state = STATE_IDLE;
end
default: begin
next_state = STATE_IDLE;
end
endcase // case (state)
end
`ifdef SIM
reg [32*8-1:0] state_name;
always @(*)
case (state)
STATE_IDLE: state_name = "IDLE";
STATE_WAIT_ACK: state_name = "WAIT ACK";
STATE_ERROR:state_name = "ERROR";
default: state_name = "DEFAULT";
endcase // case (state)
`endif
endmodule // testing_wb_master
|
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; int a = 2, b = 3, c = 5, d = 7; int ab = 6, ac = 10, ad = 14, bc = 15, bd = 21, cd = 35; int abc = 30, bcd = 105, abd = 42, acd = 70; int abcd = 210; cout << n - (n / a + n / b + n / c + n / d) + (n / ab + n / ac + n / ad + n / bc + n / bd + n / cd) - (n / abc + n / bcd + n / abd + n / acd) + n / abcd; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const long double PI = 4 * atan((long double)1); const long long mod = 1e9 + 7; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long tt = 1; while ((tt)--) { long long n, m; cin >> n >> m; if (min(n, m) & 1) { cout << Akshat << n ; } else { cout << Malvika << n ; } } } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo64_clock_crossing.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo64_clock_crossing (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdusedw,
wrfull);
input [63:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [63:0] q;
output [12:0] rdusedw;
output wrfull;
wire [63:0] sub_wire0;
wire [12:0] sub_wire1;
wire sub_wire2;
wire [63:0] q = sub_wire0[63:0];
wire [12:0] rdusedw = sub_wire1[12:0];
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdusedw (sub_wire1),
.wrfull (sub_wire2),
.aclr (),
.eccstatus (),
.rdempty (),
.rdfull (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.add_usedw_msb_bit = "ON",
dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 4096,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 64,
dcfifo_component.lpm_widthu = 13,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4096"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "64"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "1"
// Retrieval info: PRIVATE: output_width NUMERIC "64"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_USEDW_MSB_BIT STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "13"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: rdusedw 0 0 13 0 OUTPUT NODEFVAL "rdusedw[12..0]"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: CONNECT: rdusedw 0 0 13 0 @rdusedw 0 0 13 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo64_clock_crossing.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo64_clock_crossing.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo64_clock_crossing.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo64_clock_crossing.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo64_clock_crossing_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo64_clock_crossing_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1 ns / 1 ps
`include "AXI_to_audio_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module AXI_to_audio_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:10000000000 ) #pragma GCC optimize( O3 ) using namespace std; const int MOD = 1000000007; const int INF = 1000000007LL; const long long INF2 = 1LL << 62LL; const long double EPS = 1e-9; const int SIZE = 200010; mt19937 rng(time(0)); uniform_int_distribution<int> uid(-1000000000, 1000000000); int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int tt; cin >> tt; for (int rep_iter = 0; rep_iter < tt; ++rep_iter) { int n, x, y, ost; cin >> n >> x >> y; vector<int> b(n, -1); set<int> used_color; map<int, vector<int> > pos; for (int i2 = 0; i2 < n; ++i2) { int a; cin >> a; used_color.insert(a); pos[a].push_back(i2); } for (int i = 1; i <= n + 1; ++i) { if (!(used_color.find(i) != used_color.end())) { ost = i; break; } } set<pair<int, int> > colors; for (auto& i : pos) colors.insert({i.second.size(), i.first}); for (int rep_iter = 0; rep_iter < x; ++rep_iter) { auto p = *(--colors.end()); colors.erase(--colors.end()); --p.first; int color = p.second; int j = pos[color].back(); pos[color].pop_back(); b[j] = color; if (p.first) colors.insert(p); } y -= x; int m = n - x; int real_y; if (colors.size()) real_y = min(m, (m - (--colors.end())->first) * 2); else real_y = m; if (real_y < y) { cout << NO n ; continue; } cout << YES n ; vector<int> v; int j = -1; for (auto& i : colors) { if (i.first) j = v.size(); for (int rep_iter = 0; rep_iter < i.first; ++rep_iter) v.push_back(i.second); } for (auto& color : v) { if (!y) break; --y; int color_move = v[j]; j = (j + 1) % v.size(); while (color_move == color) { color_move = v[j]; j = (j + 1) % v.size(); } int k = pos[color].back(); pos[color].pop_back(); b[k] = color_move; } for (auto& i : b) { if (i == -1) i = ost; } for (auto& i : b) cout << i << ; cout << n ; } return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_9_b2s_r_channel.v
//
// Description:
// Read data channel module to buffer read data from MC, ignore
// extra data in case of BL8 and send the data to AXI.
// The MC will send out the read data as it is ready and it has to be
// accepted. The read data FIFO in the axi_protocol_converter_v2_1_9_b2s_r_channel module will buffer
// the data before being sent to AXI. The address channel module will
// send the transaction information for every command that is sent to the
// MC. The transaction information will be buffered in a transaction FIFO.
// Based on the transaction FIFO information data will be ignored in
// BL8 mode and the last signal to the AXI will be asserted.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b2s_r_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AXI xDATA and MCB xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire [C_ID_WIDTH-1:0] s_rid ,
output wire [C_DATA_WIDTH-1:0] s_rdata ,
output wire [1:0] s_rresp ,
output wire s_rlast ,
output wire s_rvalid ,
input wire s_rready ,
input wire [C_DATA_WIDTH-1:0] m_rdata ,
input wire [1:0] m_rresp ,
input wire m_rvalid ,
output wire m_rready ,
// Connections to/from axi_protocol_converter_v2_1_9_b2s_ar_channel module
input wire r_push ,
output wire r_full ,
// length not needed. Can be removed.
input wire [C_ID_WIDTH-1:0] r_arid ,
input wire r_rlast
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_WIDTH = 1+C_ID_WIDTH;
localparam P_DEPTH = 32;
localparam P_AWIDTH = 5;
localparam P_D_WIDTH = C_DATA_WIDTH + 2;
// rd data FIFO depth varies based on burst length.
// For Bl8 it is two times the size of transaction FIFO.
// Only in 2:1 mode BL8 transactions will happen which results in
// two beats of read data per read transaction.
localparam P_D_DEPTH = 32;
localparam P_D_AWIDTH = 5;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_ID_WIDTH+1-1:0] trans_in;
wire [C_ID_WIDTH+1-1:0] trans_out;
wire tr_empty;
wire rhandshake;
wire r_valid_i;
wire [P_D_WIDTH-1:0] rd_data_fifo_in;
wire [P_D_WIDTH-1:0] rd_data_fifo_out;
wire rd_en;
wire rd_full;
wire rd_empty;
wire rd_a_full;
wire fifo_a_full;
reg [C_ID_WIDTH-1:0] r_arid_r;
reg r_rlast_r;
reg r_push_r;
wire fifo_full;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign s_rresp = rd_data_fifo_out[P_D_WIDTH-1:C_DATA_WIDTH];
assign s_rid = trans_out[1+:C_ID_WIDTH];
assign s_rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0];
assign s_rlast = trans_out[0];
assign s_rvalid = ~rd_empty & ~tr_empty;
// assign MCB outputs
assign rd_en = rhandshake & (~rd_empty);
assign rhandshake =(s_rvalid & s_rready);
// register for timing
always @(posedge clk) begin
r_arid_r <= r_arid;
r_rlast_r <= r_rlast;
r_push_r <= r_push;
end
assign trans_in[0] = r_rlast_r;
assign trans_in[1+:C_ID_WIDTH] = r_arid_r;
// rd data fifo
axi_protocol_converter_v2_1_9_b2s_simple_fifo #(
.C_WIDTH (P_D_WIDTH),
.C_AWIDTH (P_D_AWIDTH),
.C_DEPTH (P_D_DEPTH)
)
rd_data_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( m_rvalid & m_rready ) ,
.rd_en ( rd_en ) ,
.din ( rd_data_fifo_in ) ,
.dout ( rd_data_fifo_out ) ,
.a_full ( rd_a_full ) ,
.full ( rd_full ) ,
.a_empty ( ) ,
.empty ( rd_empty )
);
assign rd_data_fifo_in = {m_rresp, m_rdata};
axi_protocol_converter_v2_1_9_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
transaction_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( r_push_r ) ,
.rd_en ( rd_en ) ,
.din ( trans_in ) ,
.dout ( trans_out ) ,
.a_full ( fifo_a_full ) ,
.full ( ) ,
.a_empty ( ) ,
.empty ( tr_empty )
);
assign fifo_full = fifo_a_full | rd_a_full ;
assign r_full = fifo_full ;
assign m_rready = ~rd_a_full;
endmodule
`default_nettype wire
|
// Check behaviour with out-of-range and undefined array indices
// on LHS of non-blocking procedural assignment.
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg array1[2:1];
reg array2[1:0];
`ifndef VLOG95
real array3[2:1];
real array4[1:0];
`endif
integer index;
reg failed;
initial begin
failed = 0;
array1[1] <= 1'b0;
array1[2] <= 1'b0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
array1[0] <= 1'b1; // Constant out of bounds select may be an error
`endif
#1 $display("array = %b %b", array1[2], array1[1]);
if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1;
array1[1] <= 1'b0;
array1[2] <= 1'b0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
array1[3] <= 1'b1; // Constant out of bounds select may be an error
`endif
#1 $display("array = %b %b", array1[2], array1[1]);
if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1;
array2[0] <= 1'b0;
array2[1] <= 1'b0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
array2['bx] <= 1'b1; // Constant undefined out of bounds select may be an error
`endif
#1 $display("array = %b %b", array2[1], array2[0]);
if ((array2[0] !== 1'b0) || (array2[1] !== 1'b0)) failed = 1;
index = 0;
array1[1] <= 1'b0;
array1[2] <= 1'b0;
array1[index] <= 1'b1;
#1 $display("array = %b %b", array1[2], array1[1]);
if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1;
index = 3;
array1[1] <= 1'b0;
array1[2] <= 1'b0;
array1[index] <= 1'b1;
#1 $display("array = %b %b", array1[2], array1[1]);
if ((array1[1] !== 1'b0) || (array1[2] !== 1'b0)) failed = 1;
index = 'bx;
array2[0] <= 1'b0;
array2[1] <= 1'b0;
array2[index] <= 1'b1;
#1 $display("array = %b %b", array2[1], array2[0]);
if ((array2[0] !== 1'b0) || (array2[1] !== 1'b0)) failed = 1;
`ifndef VLOG95
array3[1] <= 0.0;
array3[2] <= 0.0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
array3[0] <= 1.0; // Constant out of bounds select may be an error
`endif
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
array3[1] <= 0.0;
array3[2] <= 0.0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
array3[3] <= 1.0; // Constant out of bounds select may be an error
`endif
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
array4[0] <= 0.0;
array4[1] <= 0.0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
array4['bx] <= 1.0; // Constant undefined out of bounds select may be an error
`endif
#1 $display("array = %0g %0g", array4[1], array4[0]);
if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1;
index = 0;
array3[1] <= 0.0;
array3[2] <= 0.0;
array3[index] <= 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
index = 3;
array3[1] <= 0.0;
array3[2] <= 0.0;
array3[index] <= 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
index = 'bx;
array4[0] <= 0.0;
array4[1] <= 0.0;
array4[index] <= 1.0;
#1 $display("array = %0g %0g", array4[1], array4[0]);
if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1;
`endif
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { int n; cin >> n; vector<int> a(n); int psum = 0, msum = 0; int zero = 0; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] > 0) psum += a[i]; if (a[i] < 0) msum += a[i]; } if (psum > abs(msum)) { puts( YES ); sort(a.begin(), a.end(), greater<int>()); for (int i = 0; i < n; i++) { cout << a[i] << ; } cout << n ; } else if (psum < abs(msum)) { puts( YES ); sort(a.begin(), a.end()); for (int i = 0; i < n; i++) { cout << a[i] << ; } cout << n ; } else puts( NO ); } int main() { int tc; cin >> tc; while (tc--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline T read() { register T sum = 0; register char cc = getchar(); int sym = 1; while (cc != - && (cc > 9 || cc < 0 )) cc = getchar(); if (cc == - ) sym = -1, cc = getchar(); sum = sum * 10 + cc - 0 ; cc = getchar(); while (cc >= 0 && cc <= 9 ) sum = sum * 10 + cc - 0 , cc = getchar(); return sym * sum; } template <typename T> inline T read(T& a) { a = read<T>(); return a; } template <typename T, typename... Others> inline void read(T& a, Others&... b) { a = read(a); read(b...); } int n, m, tp1, tp2, cnt, a[200010], L[200010], M[200010], R[200010], pre[200010], nxt[200010]; int sta1[200010], sta2[200010], pop1[200010], pop2[200010], buck[200010], back[200010]; int suf1[200010], suf2[200010], st1[20][200010], st2[20][200010]; set<int> s; int upper(int x) { int l = 1, r = tp1; while (l <= r) { int mid = (l + r) >> 1; if (a[sta1[mid]] > x) l = mid + 1; else r = mid - 1; } if (!r) return n + 1; return sta1[r]; } int lower(int x) { int l = 1, r = tp2; while (l <= r) { int mid = (l + r) >> 1; if (a[sta2[mid]] < x) l = mid + 1; else r = mid - 1; } if (!r) return n + 1; return sta2[r]; } int query1(int l, int r) { int k = log2(r - l + 1); int ls = st1[k][l], rs = st1[k][r - (1 << k) + 1]; if (back[ls] <= back[rs]) return ls; return rs; } int query2(int l, int r) { int k = log2(r - l + 1); int ls = st2[k][l], rs = st2[k][r - (1 << k) + 1]; if (R[ls] <= R[rs]) return ls; return rs; } int main() { read(n, m); for (int i = 1; i <= n; i++) read(a[i]); for (int i = 1; i <= n; i++) { if (a[i - 1] != a[i]) pre[i] = i - 1; else pre[i] = pre[i - 1]; } for (int i = n; i >= 1; i--) { if (a[i + 1] != a[i]) nxt[i] = i + 1; else nxt[i] = nxt[i + 1]; } R[0] = n + 1; for (int i = 1; i <= n; i++) { if (!pre[i] || nxt[i] == n + 1) continue; if (1ll * (a[i] - a[pre[i]]) * (a[i] - a[nxt[i]]) > 0) { cnt += 1; L[cnt] = pre[i]; M[cnt] = i; R[cnt] = nxt[i]; if (nxt[i] < R[st2[0][pre[i]]]) st2[0][pre[i]] = cnt; } } s.insert(n + 1); for (int i = n; i >= 1; i--) { while (tp1 && a[sta1[tp1]] < a[i]) { buck[sta1[tp1]] -= 1; pop1[sta1[tp1]] = i; if (!buck[sta1[tp1]]) s.insert(sta1[tp1]); tp1 -= 1; } sta1[++tp1] = i; buck[i] += 1; while (tp2 && a[sta2[tp2]] > a[i]) { buck[sta2[tp2]] -= 1; pop2[sta2[tp2]] = i; if (!buck[sta2[tp2]]) s.insert(sta2[tp2]); tp2 -= 1; } sta2[++tp2] = i; buck[i] += 1; suf1[i] = upper(a[i]); suf2[i] = lower(a[i]); back[i] = *s.lower_bound(max(suf1[i], suf2[i])); } for (int i = 1; i <= n; i++) st1[0][i] = i; for (int i = 1; (1 << i) <= n; i++) for (int j = 1; j + (1 << i) - 1 <= n; j++) { int ls = st1[i - 1][j], rs = st1[i - 1][j + (1 << (i - 1))]; if (back[ls] <= back[rs]) st1[i][j] = ls; else st1[i][j] = rs; ls = st2[i - 1][j], rs = st2[i - 1][j + (1 << (i - 1))]; if (R[ls] <= R[rs]) st2[i][j] = ls; else st2[i][j] = rs; } for (int i = 1; i <= m; i++) { int l, r; read(l, r); int mn = query1(l, r); if (back[mn] <= r) { int x = pop1[back[mn]], y = pop2[back[mn]]; if (a[mn] < a[back[mn]]) y = suf2[mn]; else x = suf1[mn]; printf( 4 n%d %d %d %d n , mn, min(x, y), max(x, y), back[mn]); } else { int k = query2(l, r); if (R[k] <= r) printf( 3 n%d %d %d n , L[k], M[k], R[k]); else printf( 0 n n ); } } return 0; } |
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