text stringlengths 59 71.4k |
|---|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
module read_cycle_tb;
reg RESET;
reg CLK14M;
wire CLK;
reg AS20;
reg DS20;
reg RW20;
reg [31:0] A;
reg [31:0] D_OUT;
reg [1:0] SIZ;
wire [1:0] DSACK;
wire RAMOE;
wire [1:0] RAS;
wire [3:0] CAS;
wire [31:0] D = RW20 ? {32{1'bz}} : D_OUT;
`include "common.vinc"
// Instantiate the Unit Under Test (UUT)
ramcpld uut (
.CLKCPU(CLK),
.RESET(RESET),
.AS20(AS20),
.DS20(DS20),
.RW20(RW20),
.DSACK(DSACK),
.PUNT (PUNT),
.SIZ(SIZ),
.A(A[23:0]),
.D (D[31:24]),
.IDEINT ( 1'b0 ),
.RAMOE (RAMOE),
.CAS (CAS),
.RAS (RAS),
.RAM_MUX(RAM_MUX)
);
integer i;
initial begin
$dumpfile("read_cycle.vcd");
$dumpvars(0, read_cycle_tb);
RESET = 1;
#10;
// Initialize Inputs
CLK14M = 0;
RESET = 0;
// Wait 100 ns for global reset to finish
#142;
RESET = 1;
#142;
SIZ = 2'b10;
// autoconfig the devices.
write(32'h00E8004a, 32'h9_0000000);
write(32'h00E80048, 32'hE_0000000);
write(32'h00E8004a, 32'h0_0000000);
write(32'h00E80048, 32'h2_0000000);
busidle();
for( i = 32'h200000; i < 32'h00210000; i++ ) begin
read(i);
busidle();
end
#;
$finish;
end
assign CLK = CLK14M;
always begin
#71; CLK14M = ~CLK14M;
end
PULLUP PUNT_pullup (
.O(PUNT) // Pullup output (connect directly to top-level port)
);
PULLUP DSACK0_pullup (
.O(DSACK[0])
);
PULLUP DSACK1_pullup (
.O(DSACK[1])
);
endmodule
|
module decoder (cx,d);
output [6:0] d;
input [10:0] cx;
reg [6:0] d;
reg [6:0] s;
reg [10:0] cx1;
parameter s0 = 7'b1000;
parameter s1 = 7'b0100;
parameter s2 = 7'b0010;
parameter s3 = 7'b0001;
parameter s4 = 7'b0111;
parameter s5 = 7'b0101;
parameter s6 = 7'b0010;
parameter s7 = 7'b1001;
parameter s8 = 7'b0010;
parameter s9 = 7'b0111;
parameter s10 = 7'b0101;
always @(cx)
begin
cx1[0] = cx[0];
cx1[1] = cx[1];
cx1[2] = cx[2];
cx1[3] = cx[3];
cx1[4] = cx[4];
cx1[5] = cx[5];
cx1[6] = cx[6];
cx1[7] = cx[7];
cx1[8] = cx[8];
cx1[9] = cx[9];
cx1[10] = cx[10];
s[0]= cx[0]+ cx[7];
s[1]= cx[1]+ cx[4]+ cx[5]+ cx[9]+ cx[10];
s[2]= cx[2]+ cx[4]+ cx[6]+ cx[8]+ cx[9];
s[3]= cx[3]+ cx[4]+ cx[5]+ cx[7]+ cx[9]+ cx[10];
case(s)
s0:
begin
if(cx[0]==1'b0)
begin
cx1[0]=1'b1;
end
else
begin
cx1[0]=1'b0;
end
end
s1:
begin
if(cx[1]==1'b0)
begin
cx1[1]=1'b1;
end
else
begin
cx1[1]=1'b0;
end
end
s2:
begin
if(cx[2]==1'b0)
begin
cx1[2]=1'b1;
end
else
begin
cx1[2]=1'b0;
end
end
s3:
begin
if(cx[3]==1'b0)
begin
cx1[3]=1'b1;
end
else
begin
cx1[3]=1'b0;
end
end
s4:
begin
if(cx[4]==1'b0)
begin
cx1[4]=1'b1;
end
else
begin
cx1[4]=1'b0;
end
end
s5:
begin
if(cx[5]==1'b0)
begin
cx1[5]=1'b1;
end
else
begin
cx1[5]=1'b0;
end
end
s6:
begin
if(cx[6]==1'b0)
begin
cx1[6]=1'b1;
end
else
begin
cx1[6]=1'b0;
end
end
s7:
begin
if(cx[7]==1'b0)
begin
cx1[7]=1'b1;
end
else
begin
cx1[7]=1'b0;
end
end
s8:
begin
if(cx[8]==1'b0)
begin
cx1[8]=1'b1;
end
else
begin
cx1[8]=1'b0;
end
end
s9:
begin
if(cx[9]==1'b0)
begin
cx1[9]=1'b1;
end
else
begin
cx1[9]=1'b0;
end
end
s10:
begin
if(cx[10]==1'b0)
begin
cx1[10]=1'b1;
end
else
begin
cx1[10]=1'b0;
end
end
default:
begin
cx1[0]=cx[0];
cx1[1]=cx[1];
cx1[2]=cx[2];
cx1[3]=cx[3];
cx1[4]=cx[4];
cx1[5]=cx[5];
cx1[6]=cx[6];
cx1[7]=cx[7];
cx1[8]=cx[8];
cx1[9]=cx[9];
cx1[10]=cx[10];
end
endcase
d[0] = cx1[4];
d[1] = cx1[5];
d[2] = cx1[6];
d[3] = cx1[7];
d[4] = cx1[8];
d[5] = cx1[9];
d[6] = cx1[10];
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_dipsw_pio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 9: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 9: 0] d1_data_in;
reg [ 9: 0] d2_data_in;
wire [ 9: 0] data_in;
reg [ 9: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 9: 0] edge_detect;
wire irq;
reg [ 9: 0] irq_mask;
wire [ 9: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({10 {(address == 0)}} & data_in) |
({10 {(address == 2)}} & irq_mask) |
({10 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[9 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[0])
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[1])
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[2])
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[3])
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[4] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[4])
edge_capture[4] <= 0;
else if (edge_detect[4])
edge_capture[4] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[5] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[5])
edge_capture[5] <= 0;
else if (edge_detect[5])
edge_capture[5] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[6] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[6])
edge_capture[6] <= 0;
else if (edge_detect[6])
edge_capture[6] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[7] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[7])
edge_capture[7] <= 0;
else if (edge_detect[7])
edge_capture[7] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[8] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[8])
edge_capture[8] <= 0;
else if (edge_detect[8])
edge_capture[8] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[9] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe && writedata[9])
edge_capture[9] <= 0;
else if (edge_detect[9])
edge_capture[9] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool BeauYear(int y) { int a = y % 10; int b = (y / 10) % 10; int c = (y / 100) % 10; int d = (y / 1000) % 10; if (a != b && a != c && a != d && b != c && b != d && c != d) return true; return false; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int year; cin >> year; for (int i = year + 1; i <= 9012; i++) { if (BeauYear(i) == true) { cout << i; i = 9013; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4BB_SYMBOL_V
`define SKY130_FD_SC_HS__NOR4BB_SYMBOL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4BB_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S15_SYMBOL_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S15_SYMBOL_V
/**
* clkdlybuf4s15: Clock Delay Buffer 4-stage 0.15um length inner stage
* gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkdlybuf4s15 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S15_SYMBOL_V
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module mi_nios_cpu_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
`timescale 1 ns / 1 ps
// Simple counter for BRAM addressing
//
// Write enable is set to 1 for one cycle
// after a rising edge is detected on the trigger
module address_counter #
(
parameter integer COUNT_WIDTH = 13
)
(
input wire clken, // Clock enable
input wire trig, // Trigger
input wire clk,
output wire [31:0] address,
output wire [3:0] wen // Write enable
);
localparam count_max = (1 << COUNT_WIDTH) - 1;
reg trig_reg;
reg trig_detected;
reg wen_reg;
reg [COUNT_WIDTH-1:0] count;
initial count = 0;
initial trig_detected = 0;
initial wen_reg = 0;
always @(posedge clk) begin
trig_reg <= trig;
// Rising edge detection
if (trig & ~trig_reg) begin
trig_detected <= 1;
end else if (count == count_max) begin
trig_detected <= 0;
end
end
always @(posedge clk) begin
if (clken) begin
count <= count + 1;
if (count == count_max) begin
wen_reg <= trig_detected;
end
end
end
assign address = count << 2;
assign wen = {4{wen_reg}};
endmodule
|
//alt_oct_power CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" device_family="Stratix IV" parallelterminationcontrol rdn rup seriesterminationcontrol
//VERSION_BEGIN 11.0SP1 cbx_alt_oct_power 2011:07:03:21:10:32:SJ cbx_cycloneii 2011:07:03:21:10:33:SJ cbx_lpm_add_sub 2011:07:03:21:10:33:SJ cbx_lpm_compare 2011:07:03:21:10:33:SJ cbx_lpm_counter 2011:07:03:21:10:33:SJ cbx_lpm_decode 2011:07:03:21:10:33:SJ cbx_mgl 2011:07:03:21:11:41:SJ cbx_stratix 2011:07:03:21:10:33:SJ cbx_stratixii 2011:07:03:21:10:33:SJ cbx_stratixiii 2011:07:03:21:10:33:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//synthesis_resources = stratixiv_termination 1 stratixiv_termination_logic 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_oct_control
(
parallelterminationcontrol,
rdn,
rup,
seriesterminationcontrol) /* synthesis synthesis_clearbox=1 */;
output [13:0] parallelterminationcontrol;
input [0:0] rdn;
input [0:0] rup;
output [13:0] seriesterminationcontrol;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] rdn;
tri0 [0:0] rup;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] wire_sd1a_serializerenableout;
wire [0:0] wire_sd1a_terminationcontrol;
wire [13:0] wire_sd2a_parallelterminationcontrol;
wire [13:0] wire_sd2a_seriesterminationcontrol;
stratixiv_termination sd1a_0
(
.incrdn(),
.incrup(),
.rdn(rdn),
.rup(rup),
.scanout(),
.serializerenableout(wire_sd1a_serializerenableout[0:0]),
.shiftregisterprobe(),
.terminationcontrol(wire_sd1a_terminationcontrol[0:0]),
.terminationcontrolprobe()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.otherserializerenable({9{1'b0}}),
.scanen(1'b0),
.serializerenable(1'b0),
.terminationclear(1'b0),
.terminationclock(1'b0),
.terminationcontrolin(1'b0),
.terminationenable(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
stratixiv_termination_logic sd2a_0
(
.parallelterminationcontrol(wire_sd2a_parallelterminationcontrol[13:0]),
.serialloadenable(wire_sd1a_serializerenableout),
.seriesterminationcontrol(wire_sd2a_seriesterminationcontrol[13:0]),
.terminationdata(wire_sd1a_terminationcontrol)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.parallelloadenable(1'b0),
.terminationclock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
assign
parallelterminationcontrol = wire_sd2a_parallelterminationcontrol,
seriesterminationcontrol = wire_sd2a_seriesterminationcontrol;
endmodule //ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_oct_control
//VALID FILE
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1.1e5; queue<int> Q[2]; vector<int> E[maxn]; int n, m, cnt, in[maxn], f[maxn]; signed main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) scanf( %d , f + i); for (int i = 1, x, y; i <= m; ++i) scanf( %d%d , &x, &y), ++in[x], E[y].push_back(x); for (int i = 0; i < n; ++i) if (!in[i]) Q[f[i]].push(i); while (!(Q[1].empty() && Q[0].empty())) { while (!Q[0].empty()) { int u = Q[0].front(); Q[0].pop(); for (auto v : E[u]) if (!--in[v]) Q[f[v]].push(v); } if (!Q[1].empty()) ++cnt; while (!Q[1].empty()) { int u = Q[1].front(); Q[1].pop(); for (auto v : E[u]) if (!--in[v]) Q[f[v]].push(v); } } printf( %d , cnt); return 0; } |
#include <bits/stdc++.h> using namespace std; long long int p, pre, k, cnt; vector<long long int> ans; int main() { scanf( %lld %lld , &p, &k); if (p < k) { printf( 1 n%lld n , p); return 0; } pre = p; while (1) { cnt = (k - pre); if (cnt <= 0) { cnt = cnt / k; cnt -= 1; } else { cnt = cnt / k; if (cnt * k == (k - pre)) { cnt -= 1; } } pre = cnt; if (pre == 0) { printf( -1 n ); return 0; } ans.push_back(pre); if (pre > 0 && pre < k) { break; } } reverse(ans.begin(), ans.end()); pre = p; for (int i = ans.size() - 1; i >= 0; i--) { long long int temp = ans[i] * k + pre; pre = ans[i]; ans[i] = temp; } reverse(ans.begin(), ans.end()); ans.push_back(pre); cout << ans.size() << n ; for (int i = 0; i < ans.size(); i++) { cout << ans[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n; long long a[100005]; int main() { { cin >> n; for (int i = 0; i < n; i++) scanf( %lld , &a[i]); sort(a, a + n); long long ans = LLONG_MAX; for (int c = 1;; c++) { long long now = 1; long long tot = 0; bool ok = 1; for (int i = 0; i < n; i++) { tot += abs(now - a[i]); now = now * c; if (now > 1e14) { ok = 0; break; } } if (!ok) break; ans = min(ans, tot); } printf( %lld n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int solve(); int main() { solve(); } int solve() { string s; vector<int> cnt(26); cin >> s; int ncnt = 0; for (int i = 0; i < s.size(); ++i) ++cnt[s[i] - a ]; for (int i = 0; i < 26; ++i) ncnt += (cnt[i] & 1); while (ncnt > 1) { for (int i = 25; i >= 0; --i) { for (int j = 0; j < i; ++j) { if ((cnt[i] & 1) && (cnt[j] & 1)) { ncnt -= 2; ++cnt[j]; --cnt[i]; break; } } } } for (int i = 0; i < 26; ++i) { for (int j = 0; j < cnt[i] / 2; ++j) { cout << (char)(i + a ); } } if (ncnt) { for (int i = 0; i < 26; ++i) { if (cnt[i] & 1) cout << (char)(i + a ); } } for (int i = 25; i >= 0; --i) { for (int j = 0; j < cnt[i] / 2; ++j) { cout << (char)(i + a ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long pw(long long base, long long e) { return e ? pw(base * base, e / 2) * (e % 2 ? base : 1) : 1; } long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long to_int(string s) { long long ret = 0; for (int i = 0; i <= s.size(); i++) { ret += pw(10, s.size() - i - 1) * (long long)(s[i] - 0 ); } return ret; } const int maxn = 1e5 + 10, mod = 1e9 + 7; const long long INF = 1e9; long long n; long long f(long long x) { return (n - x) / (2 * x); } int main() { cin >> n; n--; long long ans = 0; for (int i = 0; i <= log2(n); i++) { ans += pw(2, i) * (f(pw(2, i)) + 1); } return cout << ans << n , 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = 3.141592653589793238463; void printVec(vector<int> v1) { for (int i = 0; i < v1.size(); i++) cout << v1[i] << ; cout << endl; } int main() { ios::sync_with_stdio(false); cout.tie(NULL); cin.tie(NULL); priority_queue<long long, vector<long long>, greater<long long>> pQ; long long n; cin >> n; string s; long long opr; vector<string> vec; vector<long long> operations; for (long long i = 0; i < n; i++) { cin >> s; vec.push_back(s); if (s == removeMin ) { operations.push_back(-1); continue; } cin >> opr; operations.push_back(opr); } vector<string> vec_Out; vector<long long> operations_Out; for (long long i = 0; i < n; i++) { if (vec[i] == removeMin ) { if (pQ.empty()) { pQ.push(0); vec_Out.push_back( insert ); operations_Out.push_back(0); } pQ.pop(); vec_Out.push_back( removeMin ); operations_Out.push_back(-1); } else if (vec[i][0] == i ) { vec_Out.push_back( insert ); operations_Out.push_back(operations[i]); pQ.push(operations[i]); } else { opr = operations[i]; long long MIN = -2; if (!pQ.empty()) { MIN = pQ.top(); } while (opr != MIN && !pQ.empty() && opr > MIN) { pQ.pop(); if (!pQ.empty()) { MIN = pQ.top(); } vec_Out.push_back( removeMin ); operations_Out.push_back(-1); } if (pQ.empty() || opr < MIN) { pQ.push(opr); vec_Out.push_back( insert ); operations_Out.push_back(opr); } vec_Out.push_back( getMin ); operations_Out.push_back(opr); } } cout << vec_Out.size() << endl; for (long long i = 0; i < vec_Out.size(); i++) { if (vec_Out[i] == removeMin ) { cout << vec_Out[i] << endl; continue; } cout << vec_Out[i] << operations_Out[i] << endl; } vec_Out.clear(); vec.clear(); operations.clear(); operations_Out.clear(); return 0; } |
#include <bits/stdc++.h> using namespace std; int n; vector<int> x; int ax[3]; int main() { ax[0] = ax[1] = ax[2] = 0; cin >> n; for (int i = 0; i < n; ++i) { string s; cin >> s; int cc = 0; for (int i = 0; i < s.size(); ++i) cc += s[i] - 0 ; x.push_back(cc % 3); ax[cc % 3]++; } int res = ax[0] / 2 + min(ax[1], ax[2]); cout << res; return 0; } |
module node_noc(clk, rst, data_in, data_in_ready, fifo_in_ready, data_out, data_out_ready);
parameter IDLE = 4'b0000;
parameter IDLE1 = 4'b1111;
parameter KEYWORD = 4'b0001;
parameter TEXTFILE = 4'b0010;
parameter TEXTFILE_1 = 4'b0011;
parameter PAIR_NUM = 10;
input clk;
input rst;
input [31:0] data_in;
input data_in_ready;
input fifo_in_ready; // mapper can write to router when fifo_in_ready==1
output reg [31:0] data_out;
output reg data_out_ready;
reg [31:0] text_in;
wire [31:0] keyword_in;
reg [31:0] keyword_in_reg;
wire [31:0] pair;
wire pair_out;
reg pair_out_reg;
reg [127:0] pair_reg [PAIR_NUM-1:0]; // Store at most 10 pairs now.
reg [4:0] i; // Index the pair_reg
reg [4:0] pair_reg_index;
reg [4:0] pair_reg_index_1;
reg [2:0] pair_reg_counter;
reg [2:0] pair_reg_counter_1;
reg [3:0] current_state;
reg [3:0] next_state;
reg [2:0] key_counter; // Counter keyword reception for 4 cycles.
reg key_en;
reg text_en;
reg [127:0] mem [128:0];
reg [31:0] pt_in;
reg [31:0] pt_out;
reg data_wr;
reg [2:0] data_wr_counter;
always@(posedge clk or negedge rst)
if(!rst) begin
data_out <= 0;
data_out_ready <= 0;
pair_reg_index_1 <= 0;
pair_reg_counter_1 <= 0;
end
else if(pair_reg_index_1<pair_reg_index && fifo_in_ready==1) begin
data_out_ready <= 1;
case(pair_reg_counter_1)
0: begin
data_out <= pair_reg[pair_reg_index_1][31:0];
pair_reg_counter_1 <= 1;
end
1: begin
data_out <= pair_reg[pair_reg_index_1][63:32];
pair_reg_counter_1 <= 2;
end
2: begin
data_out <= pair_reg[pair_reg_index_1][95:64];
pair_reg_counter_1 <= 3;
end
3: begin
data_out <= pair_reg[pair_reg_index_1][127:96];
pair_reg_index_1 <= pair_reg_index_1 + 1;
pair_reg_counter_1 <= 0;
end
default: begin
end
endcase
end
else begin
data_out_ready <= 0;
data_out <= 0;
end
always@(posedge clk or negedge rst)
if(!rst)
pair_out_reg <= 0;
else
pair_out_reg <= pair_out;
always@(posedge clk or negedge rst)
if(!rst) begin
for(i=0; i<PAIR_NUM; i=i+1)
pair_reg[i] <= 0;
pair_reg_counter <= 0;
pair_reg_index <= 0;
end
else if(pair_out_reg == 1) begin
case(pair_reg_counter)
0: begin
pair_reg[pair_reg_index][31:0] <= pair;
pair_reg_counter <= 1;
end
1: begin
pair_reg[pair_reg_index][63:32] <= pair;
pair_reg_counter <= 2;
end
2: begin
pair_reg[pair_reg_index][95:64] <= pair;
pair_reg_counter <= 3;
end
3: begin
pair_reg[pair_reg_index][127:96] <= pair;
pair_reg_counter <= 0;
pair_reg_index <= pair_reg_index + 1;
end
default: begin
pair_reg[pair_reg_index] <= pair_reg[pair_reg_index];
end
endcase
//pair_reg_index <= pair_reg_index + 1;
end
else
pair_reg[pair_reg_index] <= pair_reg[pair_reg_index];
/*always@(posedge clk or negedge rst)
if(!rst) begin
data_out <= 0;
data_out_ready <= 0;
end
else if(fifo_in_ready==1) begin
data_out <= 0;
data_out_ready <= 0;
end
else begin
end */
assign keyword_in = (key_en == 1'b1)?keyword_in_reg:32'bz;
always@(posedge clk or negedge rst)
if(!rst)
current_state <= IDLE;
else
current_state <= next_state;
always@*
case(current_state)
IDLE: begin
if(data_in_ready == 1'b1) next_state = IDLE1;
else next_state = IDLE;
end
IDLE1: begin
next_state = KEYWORD;
end
KEYWORD: begin
if(key_counter == 3) next_state = TEXTFILE;
else next_state = KEYWORD;
end
TEXTFILE: begin
if( pt_out==pt_in && pt_in!=0 ) next_state = TEXTFILE_1;
else next_state = TEXTFILE;
end
TEXTFILE_1: begin
end
default: begin
next_state = IDLE;
end
endcase
always@(posedge clk)
case(current_state)
IDLE: begin
key_counter <= 0;
key_en <= 0;
text_en <= 0;
pt_in <= 0;
pt_out <= 0;
data_wr_counter <= 0;
end
IDLE1: begin
end
KEYWORD: begin
key_counter <= key_counter + 1'd1;
key_en <= 1;
keyword_in_reg <= data_in[31:0];
end
TEXTFILE: begin
key_en <= 0;
text_en <= 1;
if(data_in_ready == 1)
mem[pt_in] <= data_in;
else begin
end
if(data_in_ready==1 && pt_in < 1024) begin
pt_in <= pt_in + 1;
end
else if(pt_in < 1024) begin
pt_in <= pt_in;
end
else begin
pt_in <= 0;
end
if(data_wr_counter == 6) begin
data_wr_counter <=0;
end
else if(data_wr_counter == 1) begin
data_wr <= 1'b1;
data_wr_counter <= data_wr_counter + 1;
text_in <= mem[pt_out];
pt_out <= pt_out + 1;
end
else if(data_wr_counter == 2) begin
data_wr <= 1'b0;
data_wr_counter <= data_wr_counter + 1;
end
else
data_wr_counter <= data_wr_counter + 1;
end
default: begin
end
endcase
node node0(
.clk(clk),
.rst(rst),
.textfile(text_in),
.keyword(keyword_in),
.key_en(key_en),
.data_wr(data_wr));
//.write_free(),
//.pair(pair),
//.pair_out(pair_out),
//.pair_out(pair_out));
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long dx[4] = {-1, 0, 1, 0}; const long long dy[4] = {0, -1, 0, 1}; const long long dxx[] = {1, 1, 0, -1, -1, -1, 0, 1}; const long long dyy[] = {0, 1, 1, 1, 0, -1, -1, -1}; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << n ; err(++it, args...); } long long gcd(long long a, long long b) { if (!b) return a; return gcd(b, a % b); } long long lcm(long long a, long long b) { return (a * b) / gcd(a, b); } long long modexpo(long long x, long long n, long long M) { if (n == 0) return 1; else if (n % 2 == 0) return modexpo((x * x) % M, n / 2, M); else return (x * modexpo((x * x) % M, (n - 1) / 2, M)) % M; } long long bexpo(long long x, long long n) { if (n == 0) return 1; else if (n % 2 == 0) return bexpo(x * x, n / 2); else return x * bexpo(x * x, (n - 1) / 2); } bool isPrime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } const long long mod = 1e9 + 7; const long long N = 4e5 + 5; const long long INF = 1e18; void solve() { long long n; cin >> n; ; string second; cin >> second; vector<long long> a; for (__typeof(n) i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - 2 * ((0) > (n))) a.push_back(second[i] - 0 ); long long sum = 0; for (__typeof(n - 1) k = (0) - ((0) > (n - 1)); k != (n - 1) - ((0) > (n - 1)); k += 1 - 2 * ((0) > (n - 1))) { sum += a[k]; long long c_sum = 0; for (__typeof(n) i = (k + 1) - ((k + 1) > (n)); i != (n) - ((k + 1) > (n)); i += 1 - 2 * ((k + 1) > (n))) { if (a[i] == 0) { continue; } if (c_sum == sum) { c_sum = 0; } c_sum += a[i]; if (c_sum > sum) { break; } } if (c_sum == sum) { cout << YES << n ; ; return; } } cout << NO << n ; ; } int32_t main() { long long t; t = 1; while (t--) { solve(); } } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:22:46 05/08/2015
// Design Name: branch
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_branch.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: branch
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_branch;
// Inputs
reg branch_d;
reg [3:0] branch_condition_d;
reg Z;
reg N;
reg V;
reg C;
// Outputs
wire PC_source;
// Instantiate the Unit Under Test (UUT)
branch uut (
.branch_d(branch_d),
.branch_condition_d(branch_condition_d),
.Z(Z),
.N(N),
.V(V),
.C(C),
.PC_source(PC_source)
);
initial begin
// Initialize Inputs
branch_d = 0;
branch_condition_d = 0;
Z = 0;
N = 0;
V = 0;
C = 0;
// Wait 100 ns for global reset to finish
//#100;
#1;
branch_condition_d = 4'h1;
branch_d = 1;
#1;
branch_condition_d = 4'h2;
#1;
branch_condition_d = 4'h3;
#1;
C = 1;
branch_condition_d = 4'h8;
#1;
branch_condition_d = 4'ha;
#1;
V = 1;
// Add stimulus here
end
endmodule
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 2
*/
/**
* Testbench for behavioral model for Finite State Machine model of the
* PISO convertor
*/
// Import the modules that will be tested for in this testbench
`include "piso.v"
// IMPORTANT: To run this, try: ncverilog -f piso.f +gui
module tb_piso();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the PISO convertor
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// serial_out & out_valid output signals
wire s_out,valid_op;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// load, clk, & reset_b
reg load_en,clock,reset_low;
reg [7:0] data_input;
// ============================================================
// Counter for loop to enumerate all the values of r
//integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of ee577bHw1q5model1() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
PISO pisoc (
// instance_name(signal name),
// Signal name can be the same as the instance name
s_out,valid_op,data_input,load_en,reset_low,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
reset_low=1'd0;
load_en=1'd1;
data_input=8'd10;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd13;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd6;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd5;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd7;
#40 // Ignored input data
reset_low=1'd1;
load_en=1'd1;
data_input=8'd3;
#30 // Reset the data again
reset_low=1'd0;
load_en=1'd1;
data_input=8'd2;
#20
reset_low=1'd1;
load_en=1'd1;
data_input=8'd15;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd9;
#70 // Ignored input data
reset_low=1'd1;
load_en=1'd1;
data_input=8'd14;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd12;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd10;
#90
reset_low=1'd1;
load_en=1'd0;
data_input=8'd236;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd174;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd214;
#120
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_crc32_d1.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// http://www.opencores.org/projects/DebugInterface/ ////
//// ////
//// Author(s): ////
//// Igor Mohor () ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// File: CRC32_D1.v
// Date: Thu Nov 27 13:56:49 2003
//
// Copyright (C) 1999-2003 Easics NV.
// This source file may be used and distributed without restriction
// provided that this copyright statement is not removed from the file
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose: Verilog module containing a synthesizable CRC function
// * polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
// * data width: 1
//
// Info: (Jan Zegers)
// http://www.easics.com
///////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_crc32_d1.v,v $
// Revision 1.3 2004/03/28 20:27:02 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.2 2003/12/23 15:26:26 mohor
// Small fix.
//
// Revision 1.1 2003/12/23 15:09:04 mohor
// New directory structure. New version of the debug interface.
//
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module dbg_crc32_d1 (data, enable, shift, rst, sync_rst, crc_out, clk, crc_match);
input data;
input enable;
input shift;
input rst;
input sync_rst;
input clk;
output crc_out;
output crc_match;
reg [31:0] crc;
wire [31:0] new_crc;
assign new_crc[0] = data ^ crc[31];
assign new_crc[1] = data ^ crc[0] ^ crc[31];
assign new_crc[2] = data ^ crc[1] ^ crc[31];
assign new_crc[3] = crc[2];
assign new_crc[4] = data ^ crc[3] ^ crc[31];
assign new_crc[5] = data ^ crc[4] ^ crc[31];
assign new_crc[6] = crc[5];
assign new_crc[7] = data ^ crc[6] ^ crc[31];
assign new_crc[8] = data ^ crc[7] ^ crc[31];
assign new_crc[9] = crc[8];
assign new_crc[10] = data ^ crc[9] ^ crc[31];
assign new_crc[11] = data ^ crc[10] ^ crc[31];
assign new_crc[12] = data ^ crc[11] ^ crc[31];
assign new_crc[13] = crc[12];
assign new_crc[14] = crc[13];
assign new_crc[15] = crc[14];
assign new_crc[16] = data ^ crc[15] ^ crc[31];
assign new_crc[17] = crc[16];
assign new_crc[18] = crc[17];
assign new_crc[19] = crc[18];
assign new_crc[20] = crc[19];
assign new_crc[21] = crc[20];
assign new_crc[22] = data ^ crc[21] ^ crc[31];
assign new_crc[23] = data ^ crc[22] ^ crc[31];
assign new_crc[24] = crc[23];
assign new_crc[25] = crc[24];
assign new_crc[26] = data ^ crc[25] ^ crc[31];
assign new_crc[27] = crc[26];
assign new_crc[28] = crc[27];
assign new_crc[29] = crc[28];
assign new_crc[30] = crc[29];
assign new_crc[31] = crc[30];
always @ (posedge clk or posedge rst)
begin
if(rst)
crc[31:0] <= 32'hffffffff;
else if(sync_rst)
crc[31:0] <= 32'hffffffff;
else if(enable)
crc[31:0] <= new_crc;
else if (shift)
crc[31:0] <= {crc[30:0], 1'b0};
end
assign crc_match = (crc == 32'h0);
assign crc_out = crc[31];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFRTP_SYMBOL_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; struct node { long long t, d, g, h, s, ds, dq, dis, sum; } A[100100]; int p[100100], nxt[2 * 100100], C[2 * 100100], V[2 * 100100], f[100100], g[100100][19], n, q, i, ed; int gi() { int s = 0; char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) s = s * 10 + c - 0 , c = getchar(); return s; } void Add(int u, int v, int c) { V[++ed] = v, C[ed] = c, nxt[ed] = p[u], p[u] = ed; } long long sqr(long long x) { return (x * x) % 1000000007; }; long long Mul(long long x, long long y) { return ((x % 1000000007) * y) % 1000000007; } void Dfs(int x, int fa) { f[x] = fa, A[x].s = 1, A[x].t = A[f[x]].t + 1; for (int i = p[x]; i != -1; i = nxt[i]) { int v = V[i]; if (v == fa) continue; A[v].d = (A[x].d + C[i]) % 1000000007; A[v].g = (A[x].g + A[v].d) % 1000000007; A[v].h = (A[x].h + sqr(A[v].d)) % 1000000007; Dfs(v, x); A[x].s = (A[x].s + A[v].s) % 1000000007; A[x].ds = (A[x].ds + A[v].ds + A[v].s * C[i]) % 1000000007; A[x].dq = (A[x].dq + A[v].dq + Mul(A[v].s, sqr(C[i])) + 2LL * Mul(A[v].ds, C[i])) % 1000000007; } } void Calc(int x, long long c) { A[x].dis = (A[f[x]].dis - Mul(A[x].s, c) + Mul((n - A[x].s), c)) % 1000000007; A[x].sum = (A[f[x]].sum + Mul(n, sqr(c))) % 1000000007; A[x].sum = (A[x].sum - 2LL * Mul(A[x].ds + Mul(A[x].s, c), c)) % 1000000007; A[x].sum = (A[x].sum + 2LL * Mul(A[x].dis - A[x].ds - Mul(n - A[x].s, c), c)) % 1000000007; for (int i = p[x]; i != -1; i = nxt[i]) if (V[i] != f[x]) Calc(V[i], C[i]); } int Lca(int u, int v) { if (A[u].t < A[v].t) swap(u, v); for (int i = 18; i >= 0; i--) if (A[g[u][i]].t >= A[v].t) u = g[u][i]; if (u == v) return u; for (int i = 18; i >= 0; i--) if (g[u][i] != g[v][i]) u = g[u][i], v = g[v][i]; return f[u]; } int find(int u) { for (int i = 18; i >= 0; i--) if (A[g[u][i]].t >= 2) u = g[u][i]; return u; } int main() { memset(p, -1, sizeof(p)); scanf( %d , &n); for (i = 1; i < n; i++) { int u = gi(), v = gi(), c = gi(); Add(u, v, c), Add(v, u, c); } Dfs(1, 0); for (i = 1; i <= n; i++) g[i][0] = f[i]; for (i = 1; i <= 17; i++) for (int j = 1; j <= n; j++) g[j][i] = g[g[j][i - 1]][i - 1]; for (i = 1; i <= n; i++) A[1].sum += sqr(A[i].d), A[1].dis += A[i].d; A[1].sum %= 1000000007, A[1].dis %= 1000000007; for (i = p[1]; i != -1; i = nxt[i]) Calc(V[i], C[i]); scanf( %d , &q); for (i = 1; i <= q; i++) { int u = gi(), v = gi(); int z = Lca(u, v); long long ans, o, h, b; if (z == v && u != v) { o = (A[v].d - A[f[v]].d) % 1000000007; b = (A[u].d - A[f[v]].d) % 1000000007; h = (A[f[v]].dis - A[v].ds - Mul(o, A[v].s)) % 1000000007; ans = (A[f[v]].sum - A[v].dq - Mul(A[v].s, sqr(o)) - 2LL * Mul(A[v].ds, o)) % 1000000007; ans = (ans + Mul(n - A[v].s, sqr(b)) + 2LL * Mul(h, b)) % 1000000007; ans = (A[u].sum - 2 * ans) % 1000000007; if (v == 1) ans = A[u].sum; } else { long long det = (A[u].d + A[v].d - 2LL * A[z].d) % 1000000007; ans = (A[v].dq + Mul(A[v].s, sqr(det))) % 1000000007; o = (2LL * Mul(A[v].ds, det)) % 1000000007; ans = (2LL * (ans + o) - A[u].sum) % 1000000007; } printf( %I64d n , (1000000007 + ans) % 1000000007); } } |
/*
* TODO: add input and out put buffers that drive I/O signal
*/
/*
* Comperator module:
* compare 3 inputs and forward to output samllest element and it's index
* this module is combinatorical.
*
* INPUTS:
* d0,d1,d2: are the data inputs
* great_n_small:
* operation to be performed. '1' - greater index will be returned
* '0' - smaller index will be returned
* OUTPUT:
* c_dat: choosen data amoung d0,d1,d2
* c_idx: index of choosen data
* c_vd: data valid of output signal
*
* PARAMETERS:
* data_wd: width of input data
* idx_wd: width of index
* lo: bit select. starting mark of significant bits to be taken
into accound in comperation
* hi: bit select. end of mark region
*
* ASSUME: at least one of data inputs are valid
*
* Author: Kimi
*/
`ifndef _comperator_3
`define _comperator_3
`timescale 1ns /1ps
// `include "../rtl_lib/comperator_2.v"
module comperator_3 #(parameter data_wd = 16,idx_wd = 4,hi = 15, lo = 0)
(
output wire [data_wd-1:0] c_dat,
output wire [idx_wd-1 :0] c_idx,
output wire c_dv,
input wire [data_wd-1:0] d0, d1, d2,
input wire [idx_wd-1 :0] d0_idx, d1_idx, d2_idx,
input wire d0_dv, d1_dv, d2_dv,
input wire great_n_small
);
wire [data_wd-1:0] c_dat_tmp;
wire [idx_wd-1:0] c_idx_tmp;
wire c_dv_tmp;
comperator_2 #(.data_wd(data_wd),.idx_wd(idx_wd),.hi(hi),.lo(lo))
c1 (
.c_dat(c_dat_tmp),
.c_idx(c_idx_tmp),
.c_dv(c_dv_tmp),
.d0(d0),
.d0_idx(d0_idx),
.d0_dv(d0_dv),
.d1(d1),
.d1_idx(d1_idx),
.d1_dv(d1_dv),
.great_n_small(great_n_small)
);
comperator_2 #(.data_wd(data_wd),.idx_wd(idx_wd),.hi(hi),.lo(lo))
c2 (
.c_dat(c_dat),
.c_idx(c_idx),
.c_dv(c_dv),
.d0(c_dat_tmp),
.d0_idx(c_idx_tmp),
.d0_dv(c_dv_tmp),
.d1(d2),
.d1_idx(d2_idx),
.d1_dv(d2_dv),
.great_n_small(great_n_small)
);
endmodule
`endif |
#include <bits/stdc++.h> using namespace std; const double pi = 3.1415926535897; int main() { string pass; string str[10]; cin >> pass; for (int i = 0; i < 10; i++) { cin >> str[i]; } for (int i = 0; i < 80; i += 10) { string tmp = pass.substr(i, 10); for (int io = 0; io < 10; io++) { if (tmp == str[io]) { cout << io; break; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int c, t, n, a[1000005], b[1000005], used[100005]; int main() { cin >> t; while (t--) { cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; used[i] = 0; } for (int i = 1; i <= n; i++) cin >> b[i]; if (n % 2 == 1 && a[n / 2 + 1] != b[n / 2 + 1]) { cout << NO << endl; continue; } c = 1; long long int l, r; if (n % 2 == 1) l = n / 2, r = n / 2 + 2; else l = n / 2, r = n / 2 + 1; for (int j = l; j >= 1; j--) { long long int ok = 1; for (int i = 1; i <= n / 2; i++) { if (used[i] == 1) continue; if ((a[i] == b[l] && a[n - i + 1] == b[r]) || (a[i] == b[r] && a[n - i + 1] == b[l])) { used[i] = 1; ok = 0; break; } } if (ok == 1) { c = 0; break; } l--; r++; } if (c == 1) cout << YES << endl; else cout << NO << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; if ((a >= 0 && b < 0) || (a < 0 && b >= 0)) { cout << -1 ; return 0; } if (a == 0 && b == 0) { cout << -1 ; return 0; } if (a < 0 && b < 0) { cout << -1 ; return 0; } if (b == 0 && a > 0) { cout << -1 ; return 0; } if (a == b) { cout << a; return 0; } if (a > 0 && b > 0) { if (b > a) { cout << -1 ; return 0; } else { int k1 = (a - b) / (2 * b); double x1 = (double)(a - b) / (2 * k1); int k2 = (a + b) / (2 * b); double x2 = (double)(a + b) / (2 * k2); cout << setprecision(10) << min(x1, x2); } } return 0; } |
#include <bits/stdc++.h> using namespace std; char change(char curranswer) { if (curranswer == z ) curranswer = A ; else if (curranswer == Z ) curranswer = 0 ; else if (curranswer == 9 ) ; else curranswer++; return curranswer; } int main() { long long i, j, t; cin >> t; while (t--) { long long r, c, k; long long rice = 0; char a[100][100]; cin >> r >> c >> k; for (i = 0; i < r; i++) { for (j = 0; j < c; j++) { cin >> a[i][j]; if (a[i][j] == R ) rice++; } } long long ans = rice / k; long long maxx = rice - k * ans; long long minn = k - maxx; char curranswer = a ; long long currcount = 0; bool flag = true; for (i = 0; i < r; i++) { for (flag ? (j = 0) : (j = c - 1); flag ? (j < c) : j >= 0; flag ? j++ : j--) { bool local = false; if (a[i][j] == R ) local = true; a[i][j] = curranswer; if (local) { currcount++; if (maxx > 0) { if (currcount == ans + 1) { maxx--; currcount = 0; curranswer = change(curranswer); } } else if (minn > 0) { if (currcount == ans) { minn--; currcount = 0; if (minn) curranswer = change(curranswer); } } } } flag = !flag; } for (i = 0; i < r; i++) { for (j = 0; j < c; j++) cout << a[i][j]; cout << endl; } } } |
#include <bits/stdc++.h> using namespace std; set<int> s; int main() { int x; cin >> x; s.insert(x); for (;;) { x++; while (x % 10 == 0) x /= 10; int sz = s.size(); s.insert(x); if (sz == s.size()) { printf( %d , s.size()); return 0; } } } |
#include <bits/stdc++.h> char ans[100]; int n; int main() { scanf( %s%d , ans, &n); for (int i = 0; i < strlen(ans); i++) { if (ans[i] < a ) ans[i] += a - A ; if (ans[i] < 97 + n) ans[i] += A - a ; } printf( %s n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; char S[maxn][10]; int ju(char a[], char b[]) { int n = strlen(a), m = strlen(b); int x = 0, y = 0; for (int i = 0; i < n; i++) x = x * 10 + a[i] - 0 ; for (int j = 0; j < m; j++) y = y * 10 + (b[j] == ? ? 9 : b[j] - 0 ); return x < y; } int f(int ind) { int m = strlen(S[ind - 1]), n = strlen(S[ind]); if (m < n) { for (int i = 0; i < n; i++) if (S[ind][i] == ? ) { if (i == 0) S[ind][i] = 1 ; else S[ind][i] = 0 ; } } else if (m > n) { return 1; } else { for (int i = 0; i < n; i++) { if (S[ind][i] == ? ) for (int j = 0; j <= 9; j++) { S[ind][i] = 0 + j; if (ju(S[ind - 1], S[ind])) break; } } if (!ju(S[ind - 1], S[ind])) return 1; } return 0; } int main() { int n; while (scanf( %d , &n) > 0) { int si = 1; S[0][0] = 0 ; S[0][1] = 0 ; for (int i = 1; i <= n; i++) { scanf( %s , S[i]); if (si && f(i)) si = 0; } if (si) { printf( YES n ); for (int i = 1; i <= n; i++) printf( %s n , S[i]); } else { printf( NO n ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; bool checkbit(int mask, int bit) { return mask & (1 << bit); } int setbit(int mask, int bit) { return mask | (1 << bit); } int clearbit(int mask, int bit) { return mask & ~(1 << bit); } int togglebit(int mask, int bit) { return mask ^ (1 << bit); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; int l, r, PR, PL; cin >> n >> l >> r >> PL >> PR; int ans = INT_MAX; int a[n + 1]; int PrefixSum[n + 1]; for (int i = 1; i <= n; i++) { cin >> a[i]; } PrefixSum[0] = 0; for (int i = 1; i <= n; i++) PrefixSum[i] = PrefixSum[i - 1] + a[i]; for (int i = 0; i <= n; i++) { int usedL = i; int usedR = n - i; int now = PrefixSum[i] * l + (PrefixSum[n] - PrefixSum[i]) * r; if (i > n - i) { now += (2 * i - n - 1) * PL; } if (i < n - i) { now += (n - 2 * i - 1) * PR; } ans = min(ans, now); } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); vector<int> a(n); for (auto &i : a) scanf( %d , &i); map<int, int> dp; int ans = 0; int last = 0; for (int i = 0; i < n; i++) { int x = a[i]; dp[x] = dp[x - 1] + 1; if (ans < dp[x]) { ans = dp[x]; last = x; } } vector<int> res; for (int i = n - 1; i >= 0; i--) { if (a[i] == last) { res.push_back(i); last--; } } reverse(res.begin(), res.end()); printf( %d n , ans); for (auto &i : res) printf( %d , i + 1); return 0; } |
`timescale 1ns / 1ps
/*
-- Module Name: DES Sbox 3
-- Description: Sbox 3 del algoritmo DES
-- Dependencies: -- none
-- Parameters: -- none
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- Creacion 05 de Junio 2015
*/
module des_sbox3
(
// -- inputs --------------------------------------------------------- >>>>>
input wire [0:5] right_xor_key_segment_din,
// -- outputs -------------------------------------------------------- >>>>>
output reg [0:3] sbox_dout
);
always @(*)
case ({right_xor_key_segment_din[0], right_xor_key_segment_din[5]})
2'b00:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd10;
4'd1: sbox_dout = 4'd0;
4'd2: sbox_dout = 4'd9;
4'd3: sbox_dout = 4'd14;
4'd4: sbox_dout = 4'd6;
4'd5: sbox_dout = 4'd3;
4'd6: sbox_dout = 4'd15;
4'd7: sbox_dout = 4'd5;
4'd8: sbox_dout = 4'd1;
4'd9: sbox_dout = 4'd13;
4'd10: sbox_dout = 4'd12;
4'd11: sbox_dout = 4'd7;
4'd12: sbox_dout = 4'd11;
4'd13: sbox_dout = 4'd4;
4'd14: sbox_dout = 4'd2;
4'd15: sbox_dout = 4'd8;
endcase
2'b01:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd13;
4'd1: sbox_dout = 4'd7;
4'd2: sbox_dout = 4'd0;
4'd3: sbox_dout = 4'd9;
4'd4: sbox_dout = 4'd3;
4'd5: sbox_dout = 4'd4;
4'd6: sbox_dout = 4'd6;
4'd7: sbox_dout = 4'd10;
4'd8: sbox_dout = 4'd2;
4'd9: sbox_dout = 4'd8;
4'd10: sbox_dout = 4'd5;
4'd11: sbox_dout = 4'd14;
4'd12: sbox_dout = 4'd12;
4'd13: sbox_dout = 4'd11;
4'd14: sbox_dout = 4'd15;
4'd15: sbox_dout = 4'd1;
endcase
2'b10:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd13;
4'd1: sbox_dout = 4'd6;
4'd2: sbox_dout = 4'd4;
4'd3: sbox_dout = 4'd9;
4'd4: sbox_dout = 4'd8;
4'd5: sbox_dout = 4'd15;
4'd6: sbox_dout = 4'd3;
4'd7: sbox_dout = 4'd0;
4'd8: sbox_dout = 4'd11;
4'd9: sbox_dout = 4'd1;
4'd10: sbox_dout = 4'd2;
4'd11: sbox_dout = 4'd12;
4'd12: sbox_dout = 4'd5;
4'd13: sbox_dout = 4'd10;
4'd14: sbox_dout = 4'd14;
4'd15: sbox_dout = 4'd7;
endcase
2'b11:
case (right_xor_key_segment_din[1:4])
4'd0: sbox_dout = 4'd1;
4'd1: sbox_dout = 4'd10;
4'd2: sbox_dout = 4'd13;
4'd3: sbox_dout = 4'd0;
4'd4: sbox_dout = 4'd6;
4'd5: sbox_dout = 4'd9;
4'd6: sbox_dout = 4'd8;
4'd7: sbox_dout = 4'd7;
4'd8: sbox_dout = 4'd4;
4'd9: sbox_dout = 4'd15;
4'd10: sbox_dout = 4'd14;
4'd11: sbox_dout = 4'd3;
4'd12: sbox_dout = 4'd11;
4'd13: sbox_dout = 4'd5;
4'd14: sbox_dout = 4'd2;
4'd15: sbox_dout = 4'd12;
endcase
endcase // right_xor_key_segment_din[0], right_xor_key_segment_din[5]
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
des_sbox3 sbox3
(
// -- inputs ------------------------------------------------- >>>>>
.right_xor_key_segment_din (right_xor_key_segment),
// -- outputs ------------------------------------------------ >>>>>
sbox_dout (sbox_dout)
);
*/ |
#include <bits/stdc++.h> const long long INF = 2e18; const double EPS = 1e-9; using namespace std; void WEZaa() { std::ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); } int main() { WEZaa(); unsigned long long n, k; cin >> n >> k; vector<unsigned long long> a(n), b(n); for (auto& i : a) cin >> i; for (auto& i : b) cin >> i; unsigned long long l = 0, r = 1e10, ans = 0, md; while (l <= r) { md = (l + r) / 2; unsigned long long sum = 0; for (int i = 0; i < n; i++) { unsigned long long st = a[i] * md; if (b[i] < st) sum += st - b[i]; } if (sum <= k) l = md + 1, ans = md; else r = md - 1; } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; struct FenwickTree { vector<int> tree; FenwickTree(int n = 0) { tree.resize(n); } void update(int i, int delta) { for (; i < (int)tree.size(); i |= i + 1) tree[i] += delta; } int sum(int ind) { int sum = 0; while (ind >= 0) { sum += tree[ind]; ind &= ind + 1; ind--; } return sum; } int sumRange(int hi, int lo) { return sum(hi) - sum(lo); } int val(int i) { return sum(i) - sum(i - 1); } }; int N, Q; int main() { scanf( %d%d , &N, &Q); FenwickTree ft(100010); for (int i = 1; i <= N; i++) ft.update(i, 1); int L = 0, R = N; bool l = true; while (Q--) { int op, a, b; scanf( %d%d , &op, &a); if (op == 1) { int ra = R - L - a; if (l) { if (a <= ra) { L += a; for (int i = 0; i < a; i++) ft.update(L + i + 1, ft.val(L - i)); } else { R -= ra; for (int i = 0; i < ra; i++) ft.update(R - i, ft.val(R + i + 1)); l = false; } } else { if (a <= ra) { R -= a; for (int i = 0; i < a; i++) ft.update(R - i, ft.val(R + i + 1)); } else { L += ra; for (int i = 0; i < ra; i++) ft.update(L + i + 1, ft.val(L - i)); l = true; } } } else { scanf( %d , &b); int ans = l ? ft.sumRange(L + b, L + a) : ft.sumRange(R - a, R - b); printf( %d n , ans); } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD2_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD2_PP_SYMBOL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlygate4sd2 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> void _R(T &x) { cin >> x; } void _R(int &x) { scanf( %d , &x); } void _R(long long &x) { scanf( % PRId64, &x); } void _R(double &x) { scanf( %lf , &x); } void _R(char &x) { scanf( %c , &x); } void _R(char *x) { scanf( %s , x); } void R() {} template <typename T, typename... U> void R(T &head, U &...tail) { _R(head); R(tail...); } template <typename T> void _W(const T &x) { cout << x; } void _W(const int &x) { printf( %d , x); } template <typename T> void _W(const vector<T> &x) { for (auto i = x.cbegin(); i != x.cend(); i++) { if (i != x.cbegin()) putchar( ); _W(*i); } } void W() {} template <typename T, typename... U> void W(const T &head, const U &...tail) { _W(head); putchar(sizeof...(tail) ? : n ); W(tail...); } const int N = 1e5 + 10; struct E { int to, flow; long double ang; }; bool operator<(const E &a, const E &b) { return a.ang < b.ang; } int n, m; long long x[N], y[N]; vector<E> e[N]; vector<int> sf[N]; inline long double get_ang(int a, int b) { map<pair<int, int>, long double> memo; auto k = make_pair(a, b); if (memo.count(k)) return memo[k]; else return memo[k] = atan2l(y[b] - y[a], x[b] - x[a]); } double cross(int a, int b) { return x[a] * y[b] - x[b] * y[a]; } bool vis[N]; int dfs(int p) { vis[p] = 1; int s = 1; for (auto &i : e[p]) if (!vis[i.to]) { int f = dfs(i.to); i.flow = -f; for (auto &j : e[i.to]) if (j.to == p) j.flow = f; s += f; } return s; } int main() { R(n, m); for (int i = 0; i < int(m); i++) { int a, b; R(a, b); e[a].push_back({b, 0, 0}); e[b].push_back({a, 0, 0}); } for (int i = (1); i <= int(n); i++) R(x[i], y[i]); int w = 1; for (int i = (1); i <= int(n); i++) if (x[i] < x[w]) w = i; x[0] = x[w] - 1; e[0].push_back({w, 0, 0}); e[w].push_back({0, 0, 0}); dfs(0); for (int i = (0); i <= int(n); i++) { for (auto &j : e[i]) j.ang = get_ang(i, j.to); sort(begin(e[i]), end(e[i])); sf[i].push_back(0); for (auto &j : e[i]) sf[i].push_back(sf[i].back() + j.flow); ; } int q; R(q); while (q--) { static int np, p[N]; R(np); for (int i = 0; i < int(np); i++) R(p[i]); p[np] = p[0]; double area = 0; for (int i = 0; i < int(np); i++) area += cross(p[i], p[i + 1]); if (area < 0) reverse(p, p + np + 1); p[np + 1] = p[1]; int ans = 0; for (int ii = 0; ii < int(np); ii++) { int i = p[ii], j = p[ii + 1], k = p[ii + 2]; auto aji = get_ang(j, i); auto ajk = get_ang(j, k); int ti = lower_bound(begin(e[j]), end(e[j]), E{0, 0, aji}) - e[j].begin(); int tk = lower_bound(begin(e[j]), end(e[j]), E{0, 0, ajk}) - e[j].begin(); assert(ti < ((int)(e[j]).size()) && e[j][ti].to == i); assert(tk < ((int)(e[j]).size()) && e[j][tk].to == k); ; if (ti < tk) { ans += sf[j][tk] - sf[j][ti + 1]; } else { ans += sf[j].back() - sf[j][ti + 1]; ans += sf[j][tk]; } } W(ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { return a % b == 0 ? b : gcd(b, a % b); } const int MAXN = 100010; int fst[MAXN], sec[MAXN]; int ans[MAXN]; int N, K; int cmp(const int &a, const int &b) { return a > b; } int main() { while (scanf( %d%d , &N, &K) != EOF) { for (int i = 1; i <= N; i++) scanf( %d , &fst[i]); for (int i = 1; i <= N; i++) scanf( %d , &sec[i]); sort(fst + 1, fst + 1 + N, cmp); sort(sec + 1, sec + 1 + N, cmp); int pos = N; int cnt = 0, stepl = 1, stepr = N; while (cnt < N && stepl <= N && stepr >= 1) { if (fst[stepl] + sec[stepr] >= K) { ans[cnt++] = fst[stepl] + sec[stepr]; stepl++; stepr--; } else { stepr--; } } int tot = 0; for (int i = 0; i < N; i++) if (ans[i] >= K) tot++; printf( 1 %d n , min(tot, pos)); } return 0; } |
#include <bits/stdc++.h> using namespace std; char a[100][1000] = {0}; int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long int t; cin >> t; while (t--) { long long int n, m, x, y; cin >> n >> m >> x >> y; for (long long int i = 1; i <= n; i++) { for (long long int j = 1; j <= m; j++) { cin >> a[i][j]; } } long long int ans = 0; for (long long int i = 1; i <= n; i++) { for (long long int j = 1; j <= m; j++) { if (a[i][j] == . ) { long long int pos = j; for (long long int k = j; k <= m; k++) { if (a[i][k] == . ) { pos = k; } else { break; } } long long int temp = pos - j + 1; ans += min(temp * x, (temp / 2) * y + x * (temp % 2 == 1)); j = pos; } } } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int max_height(long long n) { return (long long)(sqrt(24 * n + 1) - 1) / 6; } int main() { int t; cin >> t; while (t--) { long long n; cin >> n; int pyramids = 0; while (1) { long long height = max_height(n); if (!height) break; long long int cards = (3 * height + 1) * height / 2; pyramids += n / cards; n -= n / cards * cards; } cout << pyramids << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int MAXN = 2e5 + 5; int n, k, d, ansL = 1, ansR = 1, top1, top2, flag, pos; int a[MAXN], st1[MAXN], st2[MAXN]; map<int, int> lst; namespace SegmentTree { struct Tree { int l, r; int w, tag; } tree[MAXN << 2]; void update(int k) { tree[k].w = min(tree[k << 1].w, tree[k << 1 | 1].w); } void apply(int k, int val) { tree[k].w += val; tree[k].tag += val; } void down(int k) { if (tree[k].tag != 0) { apply(k << 1, tree[k].tag); apply(k << 1 | 1, tree[k].tag); tree[k].tag = 0; } } void Build(int k, int l, int r) { tree[k].l = l; tree[k].r = r; if (l == r) { tree[k].w = l; return; } int mid = (l + r) >> 1; Build(k << 1, l, mid); Build(k << 1 | 1, mid + 1, r); update(k); } void Modify(int k, int l, int r, int val) { if (tree[k].l >= l && tree[k].r <= r) { apply(k, val); return; } down(k); int mid = (tree[k].l + tree[k].r) >> 1; if (l <= mid) Modify(k << 1, l, r, val); if (r > mid) Modify(k << 1 | 1, l, r, val); update(k); } void Delete(int k, int x) { if (tree[k].l == tree[k].r) { tree[k].w = 0; return; } down(k); int mid = (tree[k].l + tree[k].r) >> 1; if (x <= mid) Delete(k << 1, x); else Delete(k << 1 | 1, x); update(k); } int Find(int k, int x) { if (tree[k].l == tree[k].r) return tree[k].l; down(k); if (tree[k << 1].w <= x) return Find(k << 1, x); else return Find(k << 1 | 1, x); } void Query(int k, int l, int r, int x) { if (tree[k].l >= l && tree[k].r <= r) { if (tree[k].w <= x) { flag = 1; pos = Find(k, x); } return; } down(k); int mid = (tree[k].l + tree[k].r) >> 1; if (l <= mid && !flag) Query(k << 1, l, r, x); if (r > mid && !flag) Query(k << 1 | 1, l, r, x); } } // namespace SegmentTree int main() { scanf( %d%d%d , &n, &k, &d); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); a[i] += INF; } if (d == 0) { for (int i = 1; i <= n; i++) { int l = i; while (a[i] == a[i + 1] && i < n) i += 1; if (i - l + 1 > ansR - ansL + 1) { ansL = l; ansR = i; } } printf( %d %d n , ansL, ansR); return 0; } SegmentTree::Build(1, 1, n); int L = 1; for (int R = 1; R <= n; R++) { int tmp = L; if (a[R] % d == a[R - 1] % d) L = max(lst[a[R]] + 1, L); else L = R; lst[a[R]] = R; while (tmp < L) { SegmentTree::Delete(1, tmp); tmp += 1; } while (top1 && st1[top1] >= L && a[st1[top1]] >= a[R]) { SegmentTree::Modify(1, max(L, st1[top1 - 1] + 1), st1[top1], a[st1[top1]] / d); top1 -= 1; } SegmentTree::Modify(1, max(L, st1[top1] + 1), R, -a[R] / d); st1[++top1] = R; while (top2 && st2[top2] >= L && a[st2[top2]] <= a[R]) { SegmentTree::Modify(1, max(L, st2[top2 - 1] + 1), st2[top2], -a[st2[top2]] / d); top2 -= 1; } SegmentTree::Modify(1, max(L, st2[top2] + 1), R, a[R] / d); st2[++top2] = R; flag = 0; pos = 0; SegmentTree::Query(1, L, R, k + R); if (R - pos + 1 > ansR - ansL + 1) { ansL = pos; ansR = R; } } printf( %d %d n , ansL, ansR); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 50005; const unsigned long long MOD = 1e8 + 7; const unsigned long long MAX = 1e15; int X[N], Y[N], T[N], K[N]; int n; double P[N], dp[N], ans = 0; bool cmp(int a, int b) { return T[a] < T[b]; } double dist(int i, int j) { double ans = sqrt((X[K[i]] - X[K[j]]) * (X[K[i]] - X[K[j]]) + (Y[K[i]] - Y[K[j]]) * (Y[K[i]] - Y[K[j]])); return ans; } void work() { for (int i = 1; i <= n; i++) { dp[i] = P[K[i]]; for (int j = 1; j < i; j++) if (dist(i, j) + T[K[j]] <= T[K[i]]) dp[i] = max(dp[j] + P[K[i]], dp[i]); ans = max(ans, dp[i]); } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d%d%d%lf , &X[i], &Y[i], &T[i], &P[i]); K[i] = i; } sort(K + 1, K + n + 1, cmp); work(); printf( %.7f n , ans); } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n < 6) cout << -1 << endl; else { for (int i = 2; i <= 4; i++) cout << 1 << << i << endl; for (int i = 5; i <= n; i++) { cout << 2 << << i << endl; } } for (int i = 1; i < n; i++) { cout << i << << i + 1 << endl; } } |
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
Require Export CoRN.reals.Intervals.
(**
* Metric Spaces (traditional)
*)
Section Relations.
(**
** Relations necessary for Pseudo Metric Spaces and Metric Spaces
%\begin{convention}%
Let [A : CSetoid], [d : (CSetoid_bin_fun A A IR)].
%\end{convention}%
*)
Variable A : CSetoid.
Variable d : CSetoid_bin_fun A A IR.
Set Implicit Arguments.
Unset Strict Implicit.
Definition com : Prop := forall x y : A, d x y[=]d y x.
Definition nneg : Prop := forall x y : A, [0][<=]d x y.
Definition pos_imp_ap : CProp := forall x y : A, [0][<]d x y -> x[#]y.
Definition tri_ineq : Prop := forall x y z : A, d x z[<=]d x y[+]d y z.
Set Strict Implicit.
Unset Implicit Arguments.
Definition diag_zero (X : CSetoid) (d : CSetoid_bin_fun X X IR) : Prop :=
forall x : X, d x x[=][0].
Definition apdiag_imp_grzero (X : CSetoid) (d : CSetoid_bin_fun X X IR) :
CProp := forall x y : X, x[#]y -> [0][<]d x y.
End Relations.
Section Definition_PsMS0.
(**
** Definition of Pseudo Metric Space
*)
(**
A pseudo metric space consists of a setoid and a %''pseudo metric''% #"pseudo metric"#, also called
%''distance''% #"distance"#, a binairy function that fulfils certain properties.
*)
Record is_CPsMetricSpace (A : CSetoid) (d : CSetoid_bin_fun A A IR) :
Type :=
{ax_d_com : com d;
ax_d_nneg : nneg d;
ax_d_pos_imp_ap : pos_imp_ap d;
ax_d_tri_ineq : tri_ineq d}.
Record CPsMetricSpace : Type :=
{cms_crr :> CSetoid;
cms_d : CSetoid_bin_fun cms_crr cms_crr IR;
cms_proof : is_CPsMetricSpace cms_crr cms_d}.
End Definition_PsMS0.
Arguments cms_d {c}.
Infix "[-d]" := cms_d (at level 68, left associativity).
Section PsMS_axioms.
(**
** Pseudo Metric Space axioms
%\begin{convention}%
Let [A] be a pseudo metric space.
%\end{convention}%
*)
Variable A : CPsMetricSpace.
Lemma CPsMetricSpace_is_CPsMetricSpace : is_CPsMetricSpace A cms_d.
Proof cms_proof A.
Lemma d_com : com (cms_d (c:=A)).
Proof.
elim CPsMetricSpace_is_CPsMetricSpace.
auto.
Qed.
Lemma d_nneg : nneg (cms_d (c:=A)).
Proof.
elim CPsMetricSpace_is_CPsMetricSpace.
auto.
Qed.
Lemma d_pos_imp_ap : pos_imp_ap (cms_d (c:=A)).
Proof.
elim CPsMetricSpace_is_CPsMetricSpace.
auto.
Qed.
Lemma d_tri_ineq : tri_ineq (cms_d (c:=A)).
Proof.
elim CPsMetricSpace_is_CPsMetricSpace.
auto.
Qed.
End PsMS_axioms.
Section PsMS_basics.
(**
** Pseudo Metric Space basics
%\begin{convention}%
Let [Y] be a pseudo metric space.
%\end{convention}%
*)
Variable Y : CPsMetricSpace.
Lemma rev_tri_ineq :
forall a b c : cms_crr Y, AbsSmall (b[-d]c) ((a[-d]b)[-](a[-d]c)).
Proof.
intros.
unfold AbsSmall in |- *.
split.
apply shift_leEq_minus.
apply shift_plus_leEq'.
unfold cg_minus in |- *.
cut ([--][--](b[-d]c)[=]b[-d]c).
intros.
apply leEq_wdr with ((a[-d]b)[+](b[-d]c)).
apply ax_d_tri_ineq.
apply CPsMetricSpace_is_CPsMetricSpace.
apply eq_symmetric_unfolded.
apply bin_op_wd_unfolded.
apply eq_reflexive_unfolded.
exact H.
apply cg_inv_inv.
astepr (c[-d]b).
apply shift_minus_leEq.
apply shift_leEq_plus'.
apply shift_minus_leEq.
apply ax_d_tri_ineq.
apply CPsMetricSpace_is_CPsMetricSpace.
apply ax_d_com.
apply CPsMetricSpace_is_CPsMetricSpace.
Qed.
(**
Instead of taking [pos_imp_ap] as axiom,
we could as well have taken [diag_zero].
*)
Lemma diag_zero_imp_pos_imp_ap :
forall (X : CSetoid) (d : CSetoid_bin_fun X X IR),
diag_zero X d -> pos_imp_ap d.
Proof.
intros X d.
unfold diag_zero in |- *.
unfold pos_imp_ap in |- *.
intros H.
intros x y H0.
cut (x[#]x or x[#]y).
intro H1.
elim H1.
cut (Not (x[#]x)).
intros H3 H4.
set (H5 := H3 H4) in *.
intuition.
apply ap_irreflexive_unfolded.
intro H2.
exact H2.
apply (csbf_strext X X IR d).
astepl ZeroR.
apply less_imp_ap.
exact H0.
Qed.
Lemma pos_imp_ap_imp_diag_zero :
forall (X : CSetoid) (d : CSetoid_bin_fun X X IR),
pos_imp_ap d -> nneg d -> diag_zero X d.
Proof.
intros X d.
unfold pos_imp_ap in |- *.
unfold nneg in |- *.
intros H H6.
unfold diag_zero in |- *.
intro x.
apply not_ap_imp_eq.
red in |- *.
intro H0.
set (H1 := less_conf_ap IR (d x x) [0]) in *.
generalize H1.
unfold Iff in |- *.
intro H2.
elim H2.
intros H3 H4.
set (H5 := H3 H0) in *.
elim H5.
generalize H6.
intros H7 H8.
set (H9 := H7 x x) in *.
rewrite -> leEq_def in H9.
set (H10 := H9 H8) in *.
exact H10.
intro H7.
set (H8 := H x x) in *.
set (H9 := H8 H7) in *.
set (H10 := ap_irreflexive_unfolded X x H9) in *.
exact H10.
Qed.
Lemma is_CPsMetricSpace_diag_zero :
forall (X : CSetoid) (d : CSetoid_bin_fun X X IR),
com d /\ tri_ineq d /\ nneg d /\ diag_zero X d -> is_CPsMetricSpace X d.
Proof.
intros X d H.
elim H.
intros H1 H2.
elim H2.
intros H3 H4.
elim H4.
intros H5 H6.
apply (Build_is_CPsMetricSpace X d H1 H5 (diag_zero_imp_pos_imp_ap X d H6) H3).
Qed.
End PsMS_basics.
Section Zerof.
(**
** Zero function
*)
(**
Every setoid forms with the binary function that always returns zero,
a pseudo metric space.
*)
Definition zero_fun (X : CSetoid) (x y : X) : IR := ZeroR.
Lemma zero_fun_strext :
forall X : CSetoid, bin_fun_strext X X IR (zero_fun X).
Proof.
intro X.
unfold bin_fun_strext in |- *.
unfold zero_fun in |- *.
intros x1 x2 y1 y2 Z.
set (H := ap_irreflexive_unfolded IR [0] Z) in *.
intuition.
Qed.
Definition Zero_fun (X : CSetoid) :=
Build_CSetoid_bin_fun X X IR (zero_fun X) (zero_fun_strext X).
Lemma zero_fun_com : forall X : CSetoid, com (Zero_fun X).
Proof.
intro X.
unfold com in |- *.
intros x y.
unfold Zero_fun in |- *.
simpl in |- *.
unfold zero_fun in |- *.
intuition.
Qed.
Lemma zero_fun_nneg : forall X : CSetoid, nneg (Zero_fun X).
Proof.
intro X.
unfold nneg in |- *.
intros x y.
unfold Zero_fun in |- *.
simpl in |- *.
unfold zero_fun in |- *.
apply eq_imp_leEq.
intuition.
Qed.
Lemma zero_fun_pos_imp_ap : forall X : CSetoid, pos_imp_ap (Zero_fun X).
Proof.
intro X.
unfold pos_imp_ap in |- *.
intros x y.
unfold Zero_fun in |- *.
simpl in |- *.
unfold zero_fun in |- *.
intro Z.
set (H := less_irreflexive IR [0] Z) in *.
intuition.
Qed.
Lemma zero_fun_tri_ineq : forall X : CSetoid, tri_ineq (Zero_fun X).
Proof.
intro X.
unfold tri_ineq in |- *.
intros x y z.
unfold Zero_fun in |- *.
simpl in |- *.
unfold zero_fun in |- *.
apply eq_imp_leEq.
rational.
Qed.
Definition zf_is_CPsMetricSpace (X : CSetoid) :=
Build_is_CPsMetricSpace X (Zero_fun X) (zero_fun_com X) (
zero_fun_nneg X) (zero_fun_pos_imp_ap X) (zero_fun_tri_ineq X).
Definition zf_as_CPsMetricSpace (X : CSetoid) :=
Build_CPsMetricSpace X (Zero_fun X) (zf_is_CPsMetricSpace X).
End Zerof.
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10, inf = 0x3f3f3f3f; void cmin(int& x, int y) { if (x > y) { x = y; } } int n, a[N]; long long answer; vector<int> adj[N]; void dfs(int u, int p, int d, int s) { if (d & 1) { answer += a[u] - s; s = a[u]; } else { int minv = inf; for (auto v : adj[u]) { if (v != p) { cmin(minv, a[v]); } } if (minv < s) { puts( -1 ); exit(0); } else if (minv != inf) { answer += minv - s; s = minv; } } for (auto v : adj[u]) { if (v != p) { dfs(v, u, d + 1, s); } } } int main() { scanf( %d , &n); for (int i = 2; i <= n; ++i) { int x; scanf( %d , &x); adj[x].push_back(i); } for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); } dfs(1, 0, 1, 0); printf( %lld n , answer); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n = 0, m = 1, i = 0, j = 0, k = 0, x = 0; int area[51][51] = {0}; cin >> n; for (i = 0; i < n; i++) for (x = 0; x < n; x++) cin >> area[i][x]; for (i = 0; i < n; i++) for (x = 0; x < n; x++) if (area[i][x] != 1) { m = 1; for (j = 0; j < n; j++) { if (j == i) continue; for (k = 0; k < n; k++) { if (k == x) continue; if (area[i][x] == area[j][x] + area[i][k]) { m = 0; break; } } if (m == 0) break; } if (m == 1) { cout << NO << endl; return 0; } } cout << YES << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y; cin >> n >> x >> y; int a[n + 1]; for (int i = 1; i <= n; i++) { cin >> a[i]; } for (int i = 1; i <= n; i++) { int flag = 1; for (int j = i - 1; j >= 1 && j >= i - x; j--) { if (a[i] > a[j]) { flag = 0; break; } } for (int j = i + 1; j <= n && j <= i + y; j++) { if (a[i] > a[j]) { flag = 0; break; } } if (flag == 1) { cout << i << endl; return 0; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 101; int a[N]; int n; int main() { int i, t; cin >> n; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); t = a[0]; a[0] = a[n - 1]; a[n - 1] = t; for (i = 0; i < n; i++) cout << a[i] << ; cout << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_PP_V
/**
* lpflow_inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso0p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire sleepn ;
wire and0_out_X;
// Name Output Other arguments
not not0 (sleepn , SLEEP );
and and0 (and0_out_X, A, sleepn );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0P_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTP_TB_V
`define SKY130_FD_SC_HD__DLRTP_TB_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlrtp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 RESET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 RESET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 RESET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 RESET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hd__dlrtp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTP_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; map<int, int> mp; map<int, int> np; for (int i = 1; i <= n; i++) { int x, y; cin >> x >> y; int p = y - x; int q = y + x; mp[p]++; np[q]++; } map<int, int>::iterator it; int box = 0; for (it = mp.begin(); it != mp.end(); it++) { int g = it->second; box += (g * (g - 1)) / 2; } for (it = np.begin(); it != np.end(); it++) { int g = it->second; box += (g * (g - 1)) / 2; } cout << box << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, i, l, r, l1 = 0, r1 = 1e9, l2 = 0, r2 = 1e9; cin >> n; for (i = 0; i < n; i++) { cin >> l >> r; l1 = max(l1, l); r1 = min(r1, r); } cin >> n; for (i = 0; i < n; i++) { cin >> l >> r; l2 = max(l2, l); r2 = min(r2, r); } cout << max(l1 - r2, max(l2 - r1, 0)); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, ar[1010]; bool b[1010]; int main() { cin >> n; for (int i = 1; i <= n; ++i) { cin >> ar[i]; } for (int i = 1; i <= n; ++i) { int yk = i; while (1) { if (b[yk]) break; b[yk] = 1; yk = ar[yk]; } cout << yk << ; fill(b, b + 1010, 0); } return 0; } |
#include <bits/stdc++.h> using namespace std; unordered_map<int, int> mapa; vector<int> tab; int main() { ios_base::sync_with_stdio(false); int n, k, a; cin >> n >> k; int aktIlosc = n; for (int i = 0; i < n; i++) { cin >> a; if (mapa[a] == 0) tab.push_back(a); mapa[a]++; } sort(tab.begin(), tab.end()); for (int i = 0; i + 1 < tab.size(); i++) { if (tab[i] < tab[i + 1] && tab[i] + k >= tab[i + 1]) aktIlosc -= mapa[tab[i]]; } cout << aktIlosc; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A311O_FUNCTIONAL_PP_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311O_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; struct point { int x, y; }; int F[500][500]; int x, y; void Init() { F[0 + 200][0 + 200] = 0; F[1 + 200][0 + 200] = 0; F[1 + 200][1 + 200] = 1; F[-1 + 200][1 + 200] = 2; F[-1 + 200][-1 + 200] = 3; for (int i = 2; i <= 110; i++) F[i + 200][i + 200] = F[i - 1 + 200][i - 1 + 200] + 4; for (int i = 2; i <= 110; i++) F[-i + 200][i + 200] = F[-i + 1 + 200][i - 1 + 200] + 4; for (int i = 2; i <= 110; i++) F[-i + 200][-i + 200] = F[-i + 1 + 200][-i + 1 + 200] + 4; for (int i = 2; i <= 110; i++) F[i + 200][-i + 1 + 200] = F[i - 1 + 200][-i + 2 + 200] + 4; } void thuchien() { if (x == 0 && y == 0) { cout << 0 << endl; return; } if (x == 1 && y == 0) { cout << 0 << endl; return; } if (y - x > 0 && x + y >= 0 && y > 0) { cout << F[-y + 200][y + 200] << endl; return; } if (x + y < 0 && y - x >= 0 && x < 0) { cout << F[x + 200][x + 200] << endl; return; } if (y - x < 0 && x + y - 1 <= 0 && y < 0) { cout << F[-y + 1 + 200][y + 200] << endl; return; } if (x + y - 1 > 0 && y - x <= 0 && x > 0) { cout << F[x + 200][x + 200] << endl; return; } } int main() { Init(); while (cin >> x >> y) thuchien(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, cnt; long long arr[100000], h[100000]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (long long i = 0; i <= n - 1; i++) { cin >> arr[i]; h[i] = arr[i]; } sort(h, h + n); for (long long i = 0; i <= n - 1; i++) { if (arr[i] != h[i]) cnt++; } if (cnt > 2) cout << NO n ; else cout << YES n ; cin >> n; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000 * 1000 * 1000 + 7; inline long long mod(long long n) { if (n < 0) { return (n % MOD + MOD) % MOD; } else { return n % MOD; } } long long fp(long long a, long long p) { long long ans = 1, cur = a; for (long long i = 0; (1ll << i) <= p; ++i) { if ((p >> i) & 1) ans = mod(ans * cur); cur = mod(cur * cur); } return ans; } long long dv(long long a, long long b) { return mod(a * fp(b, MOD - 2)); } const long long N = 103; long long m[N][N], ans[N][N], t[N][N]; void add(long long a[N][N], long long b[N][N]) { for (long long i = 0; i < N; ++i) { for (long long j = 0; j < N; ++j) { t[i][j] = 0; } } for (long long i = 0; i < N; ++i) { for (long long j = 0; j < N; ++j) { for (long long k = 0; k < N; ++k) { t[i][j] = mod(t[i][j] + a[i][k] * b[k][j]); } } } for (long long i = 0; i < N; ++i) { for (long long j = 0; j < N; ++j) { a[i][j] = t[i][j]; } } } void pw(long long p) { for (long long i = 0; i < N; ++i) ans[i][i] = 1; for (long long i = 0; (1ll << i) <= p; ++i) { if ((p >> i) & 1) add(ans, m); add(m, m); } } bool a[N]; long long cnt[2]; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, k; cin >> n >> k; for (long long i = 0; i < n; ++i) { cin >> a[i]; ++cnt[a[i]]; } long long l = cnt[0]; long long r = n - l; long long op = n * (n - 1) / 2; for (long long l1 = 0; l1 <= cnt[0] && l1 <= cnt[1]; ++l1) { long long l0 = l - l1; long long r0 = cnt[0] - l0; long long r1 = cnt[1] - l1; m[l1][l1] = op; if (l1) { m[l1][l1 - 1] = mod(l1 * r0); m[l1][l1] = mod(m[l1][l1] - m[l1][l1 - 1]); } m[l1][l1 + 1] = mod(l0 * r1); m[l1][l1] = mod(m[l1][l1] - m[l1][l1 + 1]); } pw(k); long long sum = 0; for (long long i = 0; i < l; ++i) sum += a[i]; cout << dv(ans[sum][0], fp(op, k)) << n ; } |
#include <bits/stdc++.h> using namespace std; inline bool check_diags(int x0, int y0, int x, int y) { return abs(x0 - x) == abs(y0 - y); } inline bool check_lines(int x0, int y0, int x, int y) { return x - x0 == 0 || y - y0 == 0; } vector<int> a, b, c, d; int n, x, s, m, k; void read() { for (int i = 0; i < m; ++i) { int t; scanf( %d , &t); a.push_back(t); } for (int i = 0; i < m; ++i) { int t; scanf( %d , &t); b.push_back(t); } a.push_back(x); b.push_back(0); c.push_back(0); d.push_back(0); for (int i = 0; i < k; ++i) { int t; scanf( %d , &t); c.push_back(t); } for (int i = 0; i < k; ++i) { int t; scanf( %d , &t); d.push_back(t); } } int main() { scanf( %d %d %d %d %d , &n, &m, &k, &x, &s); read(); int64_t ans = numeric_limits<int64_t>::max(); for (int i = 0; i < m + 1; ++i) { int avail = s - b[i]; if (avail < 0) continue; auto pos = upper_bound(d.begin(), d.end(), avail); if (pos != d.begin()) { int j = distance(d.begin(), pos - 1); int64_t val = ((int64_t)a[i]) * (n - c[j]); ans = min(ans, val); } } printf( %lld n , ans); return EXIT_SUCCESS; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3_1_V
`define SKY130_FD_SC_HS__NAND3_1_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand3_1 (
Y ,
A ,
B ,
C ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand3_1 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3_1_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:26 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_nco_0_0/ip_design_nco_0_0_stub.v
// Design : ip_design_nco_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "nco,Vivado 2017.3" *)
module ip_design_nco_0_0(s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_AWVALID, s_axi_AXILiteS_AWREADY, s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB, s_axi_AXILiteS_WVALID, s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_BRESP, s_axi_AXILiteS_BVALID, s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_ARADDR, s_axi_AXILiteS_ARVALID, s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_RDATA, s_axi_AXILiteS_RRESP, s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY, ap_clk, ap_rst_n)
/* synthesis syn_black_box black_box_pad_pin="s_axi_AXILiteS_AWADDR[5:0],s_axi_AXILiteS_AWVALID,s_axi_AXILiteS_AWREADY,s_axi_AXILiteS_WDATA[31:0],s_axi_AXILiteS_WSTRB[3:0],s_axi_AXILiteS_WVALID,s_axi_AXILiteS_WREADY,s_axi_AXILiteS_BRESP[1:0],s_axi_AXILiteS_BVALID,s_axi_AXILiteS_BREADY,s_axi_AXILiteS_ARADDR[5:0],s_axi_AXILiteS_ARVALID,s_axi_AXILiteS_ARREADY,s_axi_AXILiteS_RDATA[31:0],s_axi_AXILiteS_RRESP[1:0],s_axi_AXILiteS_RVALID,s_axi_AXILiteS_RREADY,ap_clk,ap_rst_n" */;
input [5:0]s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [31:0]s_axi_AXILiteS_WDATA;
input [3:0]s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
output [1:0]s_axi_AXILiteS_BRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
input [5:0]s_axi_AXILiteS_ARADDR;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
output [31:0]s_axi_AXILiteS_RDATA;
output [1:0]s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
input ap_clk;
input ap_rst_n;
endmodule
|
// This is a component of pluto_step, a hardware step waveform generator
// Copyright 2007 Jeff Epler <>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module stepgen(clk, enable, position, velocity, dirtime, steptime, step, dir, tap);
`define STATE_STEP 0
`define STATE_DIRCHANGE 1
`define STATE_DIRWAIT 2
parameter W=12;
parameter F=10;
parameter T=5;
input clk, enable;
output [W+F-1:0] position; reg [W+F-1:0] position;
input [F:0] velocity;
input [T-1:0] dirtime, steptime;
input [1:0] tap;
output step, dir;
reg step, dir;
reg [T-1:0] timer;
reg [1:0] state;
reg ones;
wire dbit = velocity[F];
wire pbit = (tap == 0 ? position[F]
: (tap == 1 ? position[F+1]
: (tap == 2 ? position[F+2]
: position[F+3])));
wire [W+F-1:0] xvelocity = {{W{velocity[F]}}, {1{velocity[F-1:0]}}};
`ifdef TESTING
// for testing:
initial position = 1'b0;
initial state = `STATE_STEP;
initial timer = 0;
initial dir = 0;
initial ones = 0;
`endif
always @(posedge clk) begin
if(enable) begin
// $display("state=%d timer=%d position=%h velocity=%h dir=%d dbit=%d pbit=%d ones=%d", state, timer, position, xvelocity, dir, dbit, pbit, ones);
if((dir != dbit) && (pbit == ones)) begin
if(state == `STATE_DIRCHANGE) begin
if(timer == 0) begin
dir <= dbit;
timer <= dirtime;
state <= `STATE_DIRWAIT;
end else begin
timer <= timer - 1'd1;
end
end else begin
if(timer == 0) begin
step <= 0;
timer <= dirtime;
state <= `STATE_DIRCHANGE;
end else begin
timer <= timer - 1'd1;
end
end
end else if(state == `STATE_DIRWAIT) begin
if(timer == 0) begin
state <= `STATE_STEP;
end else begin
timer <= timer - 1'd1;
end
end else begin
if(timer == 0) begin
if(pbit != ones) begin
ones <= pbit;
step <= 1'd1;
timer <= steptime;
end else begin
step <= 0;
end
end else begin
timer <= timer - 1'd1;
end
if(dir == dbit)
position <= position + xvelocity;
end
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_bram_7vx_req.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_bram_7vx_req.v //
// Description : Instantiates the request buffer primitives; 8KB Dual Port //
// Request FIFO //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_req.v //
// pcie_bram_7vx_8k.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_bram_7vx_req #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [8:0] waddr0_i, // write address
input [8:0] waddr1_i, // write address
input [127:0] wdata_i, // write data
input [15:0] wdip_i, // write parity
input wen0_i, // write enable
input wen1_i, // write enable
input wen2_i, // write enable
input wen3_i, // write enable
input [8:0] raddr0_i, // write address
input [8:0] raddr1_i, // write address
output [127:0] rdata_o, // read data
output [15:0] rdop_o, // read parity
input ren0_i, // read enable
input ren1_i, // read enable
input ren2_i, // read enable
input ren3_i // read enable
);
pcie3_7x_0_pcie_bram_7vx_8k # (
.IMPL_TARGET(IMPL_TARGET),
.NO_DECODE_LOGIC(NO_DECODE_LOGIC),
.INTERFACE_SPEED(INTERFACE_SPEED),
.COMPLETION_SPACE(COMPLETION_SPACE)
)
U0
(
.clk_i (clk_i),
.reset_i (reset_i),
.waddr0_i (waddr0_i[8:0]),
.waddr1_i (waddr1_i[8:0]),
.wdata_i (wdata_i[127:0]),
.wdip_i (wdip_i[15:0]),
.wen_i ({wen3_i, wen2_i, wen1_i, wen0_i}),
.raddr0_i (raddr0_i[8:0]),
.raddr1_i (raddr1_i[8:0]),
.rdata_o (rdata_o[127:0]),
.rdop_o (rdop_o[15:0]),
.ren_i ({ren3_i, ren2_i, ren1_i, ren0_i})
);
endmodule // pcie_bram_7vx_req
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dac_buf.v when simulating
// the core, dac_buf. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dac_buf(
clka,
wea,
addra,
dina,
clkb,
addrb,
doutb
);
input clka;
input [0 : 0] wea;
input [10 : 0] addra;
input [7 : 0] dina;
input clkb;
input [8 : 0] addrb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.ENA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 5; int n; pair<long long, long long> a[maxn + 1]; pair<long long, long long> b; priority_queue<long long, vector<long long>, greater<long long> > q; bool cmp(pair<long long, long long> a, pair<long long, long long> b) { return a > b; } int main() { int ans; scanf( %d n , &n); for (int i = 1; i <= n; i++) { scanf( %lld%lld , &a[i - 1].first, &a[i - 1].second); } b = a[0]; sort(a + 1, a + n, cmp); int i = 1; for (; i <= n && a[i].first > b.first; i++) q.push(a[i].second - a[i].first + 1); ans = i; int lans = 0; while (!q.empty()) { long long k = q.top(); q.pop(); if (k > b.first) break; b.first -= k; lans++; for (; i <= n && a[i].first > b.first; i++) q.push(a[i].second - a[i].first + 1); ans = min(ans, i - lans); } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> long long a[100001]; int main() { int n; scanf( %d , &n); int i, j, k; int m = n / 2; for (i = 1; i < n; i += 2) { scanf( %I64d , &a[i]); } long long cur = 100000000000001LL; for (i = n - 1; i >= 1; i -= 2) { bool ok = false; for (k = 2 - a[i] % 2; (long long)(k)*k <= a[i]; k += 2) { if (a[i] % k) continue; long long miden = a[i] / k; if ((miden - k) % 2) continue; long long upper = (a[i] / k) + (k - 1); if (upper + 2 < cur) { ok = true; long long lower = (a[i] / k) - (k - 1); a[i + 1] = ((upper + 2) + (cur - 2)) * ((cur - (upper + 2)) / 2) / 2; cur = lower; break; } } if (!ok) { break; } } a[0] = (1 + (cur - 2)) * ((cur - 1) / 2) / 2; if (a[0] > 0 && i < 1) { puts( Yes ); for (i = 0; i < n; i++) { printf( %I64d%c , a[i], n [i == n - 1]); } } else { puts( No ); } } |
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
parameter [7:0] in = 8'b10100101;
reg [3:0] out;
initial begin
pass = 1'b1;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in[7:'dx];
`else
out = 4'bxxxx;
`endif
if (out !== 4'bxxxx) begin
$display("FAILED: part select LSB is X, expected 4'bxxxx, got %b", out);
pass = 1'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in['dx:0];
`else
out = 4'bxxxx;
`endif
if (out !== 4'bxxxx) begin
$display("FAILED: part select MSB is X, expected 4'bxxxx, got %b", out);
pass = 1'b0;
end
out = 4'b0000;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out[0] = in['dx];
`else
out[0] = 1'bx;
`endif
if (out !== 4'b000x) begin
$display("FAILED: bit select is X, expected 4'b000x, got %b", out);
pass = 1'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in[7:'dz];
`else
out = 4'bxxxx;
`endif
if (out !== 4'bxxxx) begin
$display("FAILED: part select LSB is Z, expected 4'bxxxx, got %b", out);
pass = 1'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in['dz:0];
`else
out = 4'bxxxx;
`endif
if (out !== 4'bxxxx) begin
$display("FAILED: part select MSB is Z, expected 4'bxxxx, got %b", out);
pass = 1'b0;
end
out = 4'b0000;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out[0] = in['dz];
`else
out[0] = 1'bx;
`endif
if (out !== 4'b000x) begin
$display("FAILED: bit select is Z, expected 4'b000x, got %b", out);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[5] = {0}; for (int i = 0; i < n; ++i) { int tmp; cin >> tmp; arr[tmp]++; } int ret = arr[4]; ret += min(arr[1], arr[3]); ret += arr[2] / 2; if (arr[3] > arr[1]) { ret += arr[3] - arr[1]; ret += (arr[2] % 2) ? 1 : 0; } else { int tmp = arr[1] - arr[3]; ret += tmp / 4; if (arr[2] % 2) { if (tmp % 4 <= 2) ret += 1; else ret += 2; } else { ret += (tmp % 4) ? 1 : 0; } } cout << ret << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A41O_BEHAVIORAL_PP_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41O_BEHAVIORAL_PP_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_scbuf_rptr2.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_scbuf_rptr2 (/*AUTOARG*/
// Outputs
sctag_scbuf_fbrd_en_c3_buf, sctag_scbuf_fbrd_wl_c3_buf,
sctag_scbuf_fbwr_wen_r2_buf, sctag_scbuf_fbwr_wl_r2_buf,
sctag_scbuf_fbd_stdatasel_c3_buf, sctag_scbuf_stdecc_c3_buf,
sctag_scbuf_ev_dword_r0_buf, sctag_scbuf_evict_en_r0_buf,
sctag_scbuf_wbwr_wen_c6_buf, sctag_scbuf_wbwr_wl_c6_buf,
sctag_scbuf_wbrd_en_r0_buf, sctag_scbuf_wbrd_wl_r0_buf,
sctag_scbuf_rdma_wren_s2_buf, sctag_scbuf_rdma_wrwl_s2_buf,
sctag_scbuf_rdma_rden_r0_buf, sctag_scbuf_rdma_rdwl_r0_buf,
sctag_scbuf_ctag_en_c7_buf, sctag_scbuf_ctag_c7_buf,
sctag_scbuf_req_en_c7_buf, sctag_scbuf_word_c7_buf,
sctag_scbuf_word_vld_c7_buf, scbuf_sctag_ev_uerr_r5_buf,
scbuf_sctag_ev_cerr_r5_buf, scbuf_sctag_rdma_uerr_c10_buf,
scbuf_sctag_rdma_cerr_c10_buf,
// Inputs
sctag_scbuf_fbrd_en_c3, sctag_scbuf_fbrd_wl_c3,
sctag_scbuf_fbwr_wen_r2, sctag_scbuf_fbwr_wl_r2,
sctag_scbuf_fbd_stdatasel_c3, sctag_scbuf_stdecc_c3,
sctag_scbuf_ev_dword_r0, sctag_scbuf_evict_en_r0,
sctag_scbuf_wbwr_wen_c6, sctag_scbuf_wbwr_wl_c6,
sctag_scbuf_wbrd_en_r0, sctag_scbuf_wbrd_wl_r0,
sctag_scbuf_rdma_wren_s2, sctag_scbuf_rdma_wrwl_s2,
sctag_scbuf_rdma_rden_r0, sctag_scbuf_rdma_rdwl_r0,
sctag_scbuf_ctag_en_c7, sctag_scbuf_ctag_c7,
sctag_scbuf_req_en_c7, sctag_scbuf_word_c7,
sctag_scbuf_word_vld_c7, scbuf_sctag_ev_uerr_r5,
scbuf_sctag_ev_cerr_r5, scbuf_sctag_rdma_uerr_c10,
scbuf_sctag_rdma_cerr_c10
);
//////////////////////////////////////////////////////////////////////////////
input sctag_scbuf_fbrd_en_c3;
input [2:0] sctag_scbuf_fbrd_wl_c3 ;
input [15:0] sctag_scbuf_fbwr_wen_r2 ;
input [2:0] sctag_scbuf_fbwr_wl_r2 ;
input sctag_scbuf_fbd_stdatasel_c3;
input [77:0] sctag_scbuf_stdecc_c3;
input [2:0] sctag_scbuf_ev_dword_r0;
input sctag_scbuf_evict_en_r0;
input [3:0] sctag_scbuf_wbwr_wen_c6;
input [2:0] sctag_scbuf_wbwr_wl_c6;
input sctag_scbuf_wbrd_en_r0;
input [2:0] sctag_scbuf_wbrd_wl_r0;
input [15:0] sctag_scbuf_rdma_wren_s2;
input [1:0] sctag_scbuf_rdma_wrwl_s2;
input sctag_scbuf_rdma_rden_r0;
input [1:0] sctag_scbuf_rdma_rdwl_r0;
input sctag_scbuf_ctag_en_c7;
input [14:0] sctag_scbuf_ctag_c7;
input sctag_scbuf_req_en_c7;
input [3:0] sctag_scbuf_word_c7;
input sctag_scbuf_word_vld_c7;
output sctag_scbuf_fbrd_en_c3_buf;
output [2:0] sctag_scbuf_fbrd_wl_c3_buf;
output [15:0] sctag_scbuf_fbwr_wen_r2_buf;
output [2:0] sctag_scbuf_fbwr_wl_r2_buf;
output sctag_scbuf_fbd_stdatasel_c3_buf;
output [77:0] sctag_scbuf_stdecc_c3_buf;
output [2:0] sctag_scbuf_ev_dword_r0_buf;
output sctag_scbuf_evict_en_r0_buf;
output [3:0] sctag_scbuf_wbwr_wen_c6_buf;
output [2:0] sctag_scbuf_wbwr_wl_c6_buf;
output sctag_scbuf_wbrd_en_r0_buf;
output [2:0] sctag_scbuf_wbrd_wl_r0_buf;
output [15:0] sctag_scbuf_rdma_wren_s2_buf;
output [1:0] sctag_scbuf_rdma_wrwl_s2_buf;
output sctag_scbuf_rdma_rden_r0_buf;
output [1:0] sctag_scbuf_rdma_rdwl_r0_buf;
output sctag_scbuf_ctag_en_c7_buf;
output [14:0] sctag_scbuf_ctag_c7_buf;
output sctag_scbuf_req_en_c7_buf;
output [3:0] sctag_scbuf_word_c7_buf;
output sctag_scbuf_word_vld_c7_buf;
input scbuf_sctag_ev_uerr_r5;
input scbuf_sctag_ev_cerr_r5;
input scbuf_sctag_rdma_uerr_c10;
input scbuf_sctag_rdma_cerr_c10;
output scbuf_sctag_ev_uerr_r5_buf;
output scbuf_sctag_ev_cerr_r5_buf;
output scbuf_sctag_rdma_uerr_c10_buf;
output scbuf_sctag_rdma_cerr_c10_buf;
//////////////////////////////////////////////////////////////////////////////
wire sctag_scbuf_fbrd_en_c3_buf;
wire [2:0] sctag_scbuf_fbrd_wl_c3_buf;
wire [15:0] sctag_scbuf_fbwr_wen_r2_buf;
wire [2:0] sctag_scbuf_fbwr_wl_r2_buf;
wire sctag_scbuf_fbd_stdatasel_c3_buf;
wire [77:0] sctag_scbuf_stdecc_c3_buf;
wire [2:0] sctag_scbuf_ev_dword_r0_buf;
wire sctag_scbuf_evict_en_r0_buf;
wire [3:0] sctag_scbuf_wbwr_wen_c6_buf;
wire [2:0] sctag_scbuf_wbwr_wl_c6_buf;
wire sctag_scbuf_wbrd_en_r0_buf;
wire [2:0] sctag_scbuf_wbrd_wl_r0_buf;
wire [15:0] sctag_scbuf_rdma_wren_s2_buf;
wire [1:0] sctag_scbuf_rdma_wrwl_s2_buf;
wire sctag_scbuf_rdma_rden_r0_buf;
wire [1:0] sctag_scbuf_rdma_rdwl_r0_buf;
wire sctag_scbuf_ctag_en_c7_buf;
wire [14:0] sctag_scbuf_ctag_c7_buf;
wire sctag_scbuf_req_en_c7_buf;
wire [3:0] sctag_scbuf_word_c7_buf;
wire sctag_scbuf_word_vld_c7_buf;
wire scbuf_sctag_ev_uerr_r5_buf;
wire scbuf_sctag_ev_cerr_r5_buf;
wire scbuf_sctag_rdma_uerr_c10_buf;
wire scbuf_sctag_rdma_cerr_c10_buf;
//////////////////////////////////////////////////////////////////////////////
assign sctag_scbuf_fbrd_en_c3_buf = sctag_scbuf_fbrd_en_c3;
assign sctag_scbuf_fbrd_wl_c3_buf = sctag_scbuf_fbrd_wl_c3;
assign sctag_scbuf_fbwr_wen_r2_buf = sctag_scbuf_fbwr_wen_r2;
assign sctag_scbuf_fbwr_wl_r2_buf = sctag_scbuf_fbwr_wl_r2;
assign sctag_scbuf_fbd_stdatasel_c3_buf = sctag_scbuf_fbd_stdatasel_c3;
assign sctag_scbuf_stdecc_c3_buf = sctag_scbuf_stdecc_c3;
assign sctag_scbuf_ev_dword_r0_buf = sctag_scbuf_ev_dword_r0;
assign sctag_scbuf_evict_en_r0_buf = sctag_scbuf_evict_en_r0;
assign sctag_scbuf_wbwr_wen_c6_buf = sctag_scbuf_wbwr_wen_c6;
assign sctag_scbuf_wbwr_wl_c6_buf = sctag_scbuf_wbwr_wl_c6;
assign sctag_scbuf_wbrd_en_r0_buf = sctag_scbuf_wbrd_en_r0;
assign sctag_scbuf_wbrd_wl_r0_buf = sctag_scbuf_wbrd_wl_r0;
assign sctag_scbuf_rdma_wren_s2_buf = sctag_scbuf_rdma_wren_s2;
assign sctag_scbuf_rdma_wrwl_s2_buf = sctag_scbuf_rdma_wrwl_s2;
assign sctag_scbuf_rdma_rden_r0_buf = sctag_scbuf_rdma_rden_r0;
assign sctag_scbuf_rdma_rdwl_r0_buf = sctag_scbuf_rdma_rdwl_r0;
assign sctag_scbuf_ctag_en_c7_buf = sctag_scbuf_ctag_en_c7;
assign sctag_scbuf_ctag_c7_buf = sctag_scbuf_ctag_c7;
assign sctag_scbuf_req_en_c7_buf = sctag_scbuf_req_en_c7;
assign sctag_scbuf_word_c7_buf = sctag_scbuf_word_c7;
assign sctag_scbuf_word_vld_c7_buf = sctag_scbuf_word_vld_c7;
assign scbuf_sctag_ev_uerr_r5_buf = scbuf_sctag_ev_uerr_r5;
assign scbuf_sctag_ev_cerr_r5_buf = scbuf_sctag_ev_cerr_r5;
assign scbuf_sctag_rdma_uerr_c10_buf = scbuf_sctag_rdma_uerr_c10;
assign scbuf_sctag_rdma_cerr_c10_buf = scbuf_sctag_rdma_cerr_c10;
endmodule
|
#include <bits/stdc++.h> using namespace std; int nextt[200007], c[200007], vis[200007]; long long ans, n; template <class T> void read(T &x) { int f = 0; x = 0; char ch = getchar(); while (ch < 0 || ch > 9 ) { f |= (ch == - ); ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } x = f ? -x : x; } int MIN(int now) { int min = c[now]; for (int i = nextt[now];; i = nextt[i]) { if (i == now) return min; else if (c[i] < min) min = c[i]; } } int main() { read(n); for (int i = 1; i <= n; i++) read(c[i]); for (int i = 1; i <= n; i++) { read(nextt[i]); if (nextt[i] == i) vis[i] = -1, ans += c[i]; } for (int now = 1; now <= n; now++) { if (vis[now]) continue; for (int i = now;; i = nextt[i]) { if (vis[i]) { if (vis[i] == now) ans += MIN(i); break; } vis[i] = now; } } printf( %I64d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, k, i, j, a[1000000], b[1000000], x, res = 1; int main() { cin >> n; for (i = 0; i < n; i++) { cin >> a[i]; } for (i = 0; i < n; i++) { cin >> x; b[x] = i; } while (b[a[res]] > b[a[res - 1]]) { res++; } res = n - res; cout << res; } |
#include <bits/stdc++.h> using namespace std; int a[100005]; int main() { int n, k, x, sum; scanf( %d %d , &n, &k); for (int i = 0; i < (n); i++) scanf( %d , &a[i]); int ng = 0, ps = 0, nm = -(1 << 28), pm = (1 << 28); for (int i = 0; i < (n); i++) { if (a[i] < 0) ng++; else ps++; if (a[i] < 0 && a[i] > nm) nm = a[i]; else if (a[i] >= 0 && a[i] < pm) pm = a[i]; } if (ng >= k) { sum = 0; for (int i = 0; i < (n); i++) { if (i < k) sum += ((a[i]) < 0 ? -(a[i]) : (a[i])); else sum += a[i]; } } else { sum = 0; for (int i = 0; i < (n); i++) { sum += ((a[i]) < 0 ? -(a[i]) : (a[i])); } if ((k - ng) & 1) { if (!ng) sum = sum - 2 * a[0]; else sum = ((sum + 2 * nm > sum - 2 * pm) ? (sum + 2 * nm) : (sum - 2 * pm)); } } printf( %d n , sum); return 0; } |
/*------------------------------------------------------------------------
Purpose
Clocks generation.
------------------------------------------------------------------------*/
module tenv_clockgen #(parameter clocks_number=2)
(
input[(clocks_number-1):0] init,
input[(clocks_number-1):0] en,
input[(clocks_number*32)-1:0] time_high,
input[(clocks_number*32)-1:0] time_low,
output reg[(clocks_number-1):0] clocks
);
reg[(clocks_number-1):0] init_ended;
integer index;
//CLOCKS GENERATION
generate
genvar i;
for(i=0 ; i<clocks_number ; i=i+1)
begin
//BEGIN COPY CODE
initial
begin
init_ended[i]=1'b0;
wait(init[i]==1'b0 | init[i]==1'b1);
clocks[i]=init[i];
init_ended[i]=1'b1;
forever
begin
wait(en[i]==1'b1);
fork:loop
forever
begin
if(clocks[i]==1'b0)
begin
#(time_high[((i+1)*32)-1:i*32]);
clocks[i]=~clocks[i];
#(time_low[((i+1)*32)-1:i*32]);
end
else
begin
#(time_low[((i+1)*32)-1:i*32]);
clocks[i]=~clocks[i];
#(time_high[((i+1)*32)-1:i*32]);
end
clocks[i]=~clocks[i];
end
begin
wait(en[i]==1'b0);
disable loop;
end
join
end
end
//END COPY CODE
end
endgenerate
//VALIDATION INPUTS STATE
initial
begin
forever @(time_low, time_high, en, init)
begin
index=(clocks_number*32)-1;
while(index!=-1)
begin
if(time_high[index]===1'bz | time_high[index]===1'bx)
begin
$display("%0t [clocks_generator]: Error - time_high[%0d] = %b",
$realtime,index,time_high[index]);
$finish;
end
if(time_low[index]===1'bz | time_low[index]===1'bx)
begin
$display("%0t [clocks_generator]: Error - time_low[%0d] = %b",
$realtime,index,time_low[index]);
$finish;
end
index= index-1;
end
index= (clocks_number)-1;
while(index!=-1)
begin
if(en[index]===1'bz | en[index]===1'bx)
begin
$display("%0t [clocks_generator]: Error - en[%0d] = %b",
$realtime,index,en[index]);
$finish;
end
if( (init[index]===1'bz | init[index]===1'bx) &
init_ended[index]==1'b0 )
begin
$display("%0t [clocks_generator]: Error - init[%0d] = %b",
$realtime,index,init[index]);
$finish;
end
index= index-1;
end
end
end
endmodule
|
/* The test bench for an 8 bit shift-register FIFO.
*
* Case I:
* Tests the FIFO by writing eight 1s and reading them back.
*
* Created by David Tran
* Version 0.1.0.0
* Last Modified:04-24-2014
*/
`include "shift_fifo.v"
module shift_fifo_tb (
readMode, // Specifies if we want to read to the FIFO
writeMode, // Specifies if we want to write to the FIFO
inputData // The input bit to write to the shift-register
);
output readMode, writeMode, inputData;
reg readMode, writeMode, inputData;
wire outputData;
reg clk, rst;
shift_fifo fifoInstance (readMode, writeMode,
inputData, outputData, clk, rst);
initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
forever begin
@(posedge clk); // Only output on positive edge
$display("time=%04d RW=%b%b IO=%b%b clk=%b", $time,
readMode, writeMode, inputData, outputData, clk);
end
end
initial
begin
// Test Case I: Write to capacity and empty out
readMode = 0;
writeMode = 0;
inputData = 0;
#5 rst = 1;
#5 rst = 0;
#5 inputData = 1; writeMode = 1;
#80 readMode = 1; writeMode = 0; inputData = 0;
#80 readMode = 0;
if (1'b1 === outputData) begin // Check if last value is 1
$display("Pass");
end else begin
$display("Fail");
end
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { long long n; cin >> n; n = 4 * n; for (long long i = 0; i < (n / 4); i++) { cout << n - (2 * i) << ; } cout << endl; } } |
module system
(
processing_system7_0_MIO,
processing_system7_0_PS_SRSTB,
processing_system7_0_PS_CLK,
processing_system7_0_PS_PORB,
processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB,
processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP,
xillybus_bus_clk,
xillybus_bus_rst_n,
xillybus_S_AXI_AWADDR,
xillybus_S_AXI_AWVALID,
xillybus_S_AXI_WDATA,
xillybus_S_AXI_WSTRB,
xillybus_S_AXI_WVALID,
xillybus_S_AXI_BREADY,
xillybus_S_AXI_ARADDR,
xillybus_S_AXI_ARVALID,
xillybus_S_AXI_RREADY,
xillybus_S_AXI_ARREADY,
xillybus_S_AXI_RDATA,
xillybus_S_AXI_RRESP,
xillybus_S_AXI_RVALID,
xillybus_S_AXI_WREADY,
xillybus_S_AXI_BRESP,
xillybus_S_AXI_BVALID,
xillybus_S_AXI_AWREADY,
xillybus_M_AXI_ARREADY,
xillybus_M_AXI_ARVALID,
xillybus_M_AXI_ARADDR,
xillybus_M_AXI_ARLEN,
xillybus_M_AXI_ARSIZE,
xillybus_M_AXI_ARBURST,
xillybus_M_AXI_ARPROT,
xillybus_M_AXI_ARCACHE,
xillybus_M_AXI_RREADY,
xillybus_M_AXI_RVALID,
xillybus_M_AXI_RDATA,
xillybus_M_AXI_RRESP,
xillybus_M_AXI_RLAST,
xillybus_M_AXI_AWREADY,
xillybus_M_AXI_AWVALID,
xillybus_M_AXI_AWADDR,
xillybus_M_AXI_AWLEN,
xillybus_M_AXI_AWSIZE,
xillybus_M_AXI_AWBURST,
xillybus_M_AXI_AWPROT,
xillybus_M_AXI_AWCACHE,
xillybus_M_AXI_WREADY,
xillybus_M_AXI_WVALID,
xillybus_M_AXI_WDATA,
xillybus_M_AXI_WSTRB,
xillybus_M_AXI_WLAST,
xillybus_M_AXI_BREADY,
xillybus_M_AXI_BVALID,
xillybus_M_AXI_BRESP,
xillybus_host_interrupt,
xillyvga_0_clk_in,
xillyvga_0_vga_hsync,
xillyvga_0_vga_vsync,
xillyvga_0_vga_de,
xillyvga_0_vga_red,
xillyvga_0_vga_green,
xillyvga_0_vga_blue,
xillyvga_0_vga_clk,
processing_system7_0_GPIO,
processing_system7_0_USB0_VBUS_PWRFAULT,
xillybus_lite_0_user_clk_pin,
xillybus_lite_0_user_wren_pin,
xillybus_lite_0_user_wstrb_pin,
xillybus_lite_0_user_rden_pin,
xillybus_lite_0_user_rd_data_pin,
xillybus_lite_0_user_wr_data_pin,
xillybus_lite_0_user_addr_pin,
xillybus_lite_0_user_irq_pin
);
inout [53:0] processing_system7_0_MIO;
input processing_system7_0_PS_SRSTB;
input processing_system7_0_PS_CLK;
input processing_system7_0_PS_PORB;
inout processing_system7_0_DDR_Clk;
inout processing_system7_0_DDR_Clk_n;
inout processing_system7_0_DDR_CKE;
inout processing_system7_0_DDR_CS_n;
inout processing_system7_0_DDR_RAS_n;
inout processing_system7_0_DDR_CAS_n;
output processing_system7_0_DDR_WEB;
inout [2:0] processing_system7_0_DDR_BankAddr;
inout [14:0] processing_system7_0_DDR_Addr;
inout processing_system7_0_DDR_ODT;
inout processing_system7_0_DDR_DRSTB;
inout [31:0] processing_system7_0_DDR_DQ;
inout [3:0] processing_system7_0_DDR_DM;
inout [3:0] processing_system7_0_DDR_DQS;
inout [3:0] processing_system7_0_DDR_DQS_n;
inout processing_system7_0_DDR_VRN;
inout processing_system7_0_DDR_VRP;
output xillybus_bus_clk;
output xillybus_bus_rst_n;
output [31:0] xillybus_S_AXI_AWADDR;
output xillybus_S_AXI_AWVALID;
output [31:0] xillybus_S_AXI_WDATA;
output [3:0] xillybus_S_AXI_WSTRB;
output xillybus_S_AXI_WVALID;
output xillybus_S_AXI_BREADY;
output [31:0] xillybus_S_AXI_ARADDR;
output xillybus_S_AXI_ARVALID;
output xillybus_S_AXI_RREADY;
input xillybus_S_AXI_ARREADY;
input [31:0] xillybus_S_AXI_RDATA;
input [1:0] xillybus_S_AXI_RRESP;
input xillybus_S_AXI_RVALID;
input xillybus_S_AXI_WREADY;
input [1:0] xillybus_S_AXI_BRESP;
input xillybus_S_AXI_BVALID;
input xillybus_S_AXI_AWREADY;
output xillybus_M_AXI_ARREADY;
input xillybus_M_AXI_ARVALID;
input [31:0] xillybus_M_AXI_ARADDR;
input [3:0] xillybus_M_AXI_ARLEN;
input [2:0] xillybus_M_AXI_ARSIZE;
input [1:0] xillybus_M_AXI_ARBURST;
input [2:0] xillybus_M_AXI_ARPROT;
input [3:0] xillybus_M_AXI_ARCACHE;
input xillybus_M_AXI_RREADY;
output xillybus_M_AXI_RVALID;
output [31:0] xillybus_M_AXI_RDATA;
output [1:0] xillybus_M_AXI_RRESP;
output xillybus_M_AXI_RLAST;
output xillybus_M_AXI_AWREADY;
input xillybus_M_AXI_AWVALID;
input [31:0] xillybus_M_AXI_AWADDR;
input [3:0] xillybus_M_AXI_AWLEN;
input [2:0] xillybus_M_AXI_AWSIZE;
input [1:0] xillybus_M_AXI_AWBURST;
input [2:0] xillybus_M_AXI_AWPROT;
input [3:0] xillybus_M_AXI_AWCACHE;
output xillybus_M_AXI_WREADY;
input xillybus_M_AXI_WVALID;
input [31:0] xillybus_M_AXI_WDATA;
input [3:0] xillybus_M_AXI_WSTRB;
input xillybus_M_AXI_WLAST;
input xillybus_M_AXI_BREADY;
output xillybus_M_AXI_BVALID;
output [1:0] xillybus_M_AXI_BRESP;
input xillybus_host_interrupt;
input xillyvga_0_clk_in;
output xillyvga_0_vga_hsync;
output xillyvga_0_vga_vsync;
output xillyvga_0_vga_de;
output [7:0] xillyvga_0_vga_red;
output [7:0] xillyvga_0_vga_green;
output [7:0] xillyvga_0_vga_blue;
output xillyvga_0_vga_clk;
inout [55:0] processing_system7_0_GPIO;
input processing_system7_0_USB0_VBUS_PWRFAULT;
output xillybus_lite_0_user_clk_pin;
output xillybus_lite_0_user_wren_pin;
output [3:0] xillybus_lite_0_user_wstrb_pin;
output xillybus_lite_0_user_rden_pin;
input [31:0] xillybus_lite_0_user_rd_data_pin;
output [31:0] xillybus_lite_0_user_wr_data_pin;
output [31:0] xillybus_lite_0_user_addr_pin;
input xillybus_lite_0_user_irq_pin;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MAX = 10e5; vector<long long> graph[MAX]; queue<long long> q; bool visit[MAX]; long long a[MAX]; long long s[MAX]; long long parent[MAX]; int main() { memset(visit, false, sizeof(visit)); long long nodes; cin >> nodes; for (auto i = 2; i <= nodes; ++i) { long long tmp; cin >> tmp; parent[i] = tmp; graph[i].push_back(tmp); graph[tmp].push_back(i); } for (auto i = 1; i <= nodes; ++i) { cin >> s[i]; } a[1] = s[1]; q.push(1); visit[1] = true; while (!q.empty()) { long long n = q.front(); q.pop(); if (n != 1) { if (s[n] == -1) { s[n] = s[parent[n]]; if (graph[n].size() > 1) { long long mini = 10e9; for (auto v : graph[n]) { if (v == parent[n]) continue; mini = min(mini, s[v]); } if (mini < s[n]) { cout << -1; return 0; } else { a[n] = mini - s[n]; s[n] = mini; } } else { a[n] = 0; s[n] = s[parent[n]]; } } else { a[n] = s[n] - s[parent[n]]; } } for (auto p : graph[n]) { if (visit[p]) continue; q.push(p); visit[p] = true; } } long long ans = 0; for (auto i = 1; i <= nodes; i++) { ans += a[i]; } cout << ans; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__SDFSTP_BEHAVIORAL_PP_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hdll__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSTP_BEHAVIORAL_PP_V |
`define CYCLE_TIME 50
module TestBench;
reg Clk;
reg Reset;
reg Start;
integer i, outfile, outfile2, counter;
reg flag;
reg [26:0] address;
reg [23:0] tag;
reg [4:0] index;
wire [256-1:0] mem_cpu_data;
wire mem_cpu_ack;
wire [256-1:0] cpu_mem_data;
wire [32-1:0] cpu_mem_addr;
wire cpu_mem_enable;
wire cpu_mem_write;
always #(`CYCLE_TIME/2) Clk = ~Clk;
CPU CPU(
.clk (Clk),
.rst (Reset),
.start(Start),
.MemReadData(mem_cpu_data),
.MemAck(mem_cpu_ack),
.MemWriteData(cpu_mem_data),
.MemAddr(cpu_mem_addr),
.MemEnable(cpu_mem_enable),
.MemWrite(cpu_mem_write)
);
Data_Memory Data_Memory
(
.clk_i(Clk),
.rst_i (Reset),
.addr_i(cpu_mem_addr),
.data_i(cpu_mem_data),
.enable_i(cpu_mem_enable),
.write_i(cpu_mem_write),
.ack_o(mem_cpu_ack),
.data_o(mem_cpu_data)
);
initial begin
counter = 0;
// initialize instruction memory (2KB)
for(i=0; i<512; i=i+1) begin
CPU.Instruction_Memory.memory[i] = 32'b0;
end
// initialize data memory (16KB)
for(i=0; i<512; i=i+1) begin
Data_Memory.memory[i] = 256'b0;
end
// initialize cache memory (1KB)
for(i=0; i<32; i=i+1) begin
CPU.dcache.dcache_tag_sram.memory[i] = 24'b0;
CPU.dcache.dcache_data_sram.memory[i] = 256'b0;
end
// initialize Register File
for(i=0; i<32; i=i+1) begin
CPU.Registers.register[i] = 32'b0;
end
// Load instructions into instruction memory
$readmemb("instruction.txt", CPU.Instruction_Memory.memory);
// Open output file
outfile = $fopen("output.txt") | 1;
outfile2 = $fopen("cache.txt") | 1;
// Set Input n into data memory at 0x00
Data_Memory.memory[0] = 256'h5; // n = 5 for example
Clk = 1;
Start = 0;
Reset = 0;
#(`CYCLE_TIME/2)
Start = 1;
Reset = 1;
end
always@(posedge Clk) begin
if(counter == 150) begin // store cache to memory
$fdisplay(outfile, "Flush Cache! \n");
for(i=0; i<32; i=i+1) begin
tag = CPU.dcache.dcache_tag_sram.memory[i];
index = i;
address = {tag[21:0], index};
Data_Memory.memory[address] = CPU.dcache.dcache_data_sram.memory[i];
end
end
if(counter > 150) begin // stop
$stop;
end
$fdisplay(outfile, "cycle = %d, Start = %b", counter, Start);
// print PC
$fdisplay(outfile, "PC = %d", CPU.PC.pc_o);
// print Registers
$fdisplay(outfile, "Registers");
$fdisplay(outfile, "R0(r0) = %h, R8 (t0) = %h, R16(s0) = %h, R24(t8) = %h", CPU.Registers.register[0], CPU.Registers.register[8] , CPU.Registers.register[16], CPU.Registers.register[24]);
$fdisplay(outfile, "R1(at) = %h, R9 (t1) = %h, R17(s1) = %h, R25(t9) = %h", CPU.Registers.register[1], CPU.Registers.register[9] , CPU.Registers.register[17], CPU.Registers.register[25]);
$fdisplay(outfile, "R2(v0) = %h, R10(t2) = %h, R18(s2) = %h, R26(k0) = %h", CPU.Registers.register[2], CPU.Registers.register[10], CPU.Registers.register[18], CPU.Registers.register[26]);
$fdisplay(outfile, "R3(v1) = %h, R11(t3) = %h, R19(s3) = %h, R27(k1) = %h", CPU.Registers.register[3], CPU.Registers.register[11], CPU.Registers.register[19], CPU.Registers.register[27]);
$fdisplay(outfile, "R4(a0) = %h, R12(t4) = %h, R20(s4) = %h, R28(gp) = %h", CPU.Registers.register[4], CPU.Registers.register[12], CPU.Registers.register[20], CPU.Registers.register[28]);
$fdisplay(outfile, "R5(a1) = %h, R13(t5) = %h, R21(s5) = %h, R29(sp) = %h", CPU.Registers.register[5], CPU.Registers.register[13], CPU.Registers.register[21], CPU.Registers.register[29]);
$fdisplay(outfile, "R6(a2) = %h, R14(t6) = %h, R22(s6) = %h, R30(s8) = %h", CPU.Registers.register[6], CPU.Registers.register[14], CPU.Registers.register[22], CPU.Registers.register[30]);
$fdisplay(outfile, "R7(a3) = %h, R15(t7) = %h, R23(s7) = %h, R31(ra) = %h", CPU.Registers.register[7], CPU.Registers.register[15], CPU.Registers.register[23], CPU.Registers.register[31]);
// print Data Memory
$fdisplay(outfile, "Data Memory: 0x0000 = %h", Data_Memory.memory[0]);
$fdisplay(outfile, "Data Memory: 0x0020 = %h", Data_Memory.memory[1]);
$fdisplay(outfile, "Data Memory: 0x0040 = %h", Data_Memory.memory[2]);
$fdisplay(outfile, "Data Memory: 0x0060 = %h", Data_Memory.memory[3]);
$fdisplay(outfile, "Data Memory: 0x0080 = %h", Data_Memory.memory[4]);
$fdisplay(outfile, "Data Memory: 0x00A0 = %h", Data_Memory.memory[5]);
$fdisplay(outfile, "Data Memory: 0x00C0 = %h", Data_Memory.memory[6]);
$fdisplay(outfile, "Data Memory: 0x00E0 = %h", Data_Memory.memory[7]);
$fdisplay(outfile, "Data Memory: 0x0400 = %h", Data_Memory.memory[32]);
$fdisplay(outfile, "\n");
// print Data Cache Status
if(CPU.dcache.p1_stall_o && CPU.dcache.state==0) begin
if(CPU.dcache.sram_dirty) begin
if(CPU.dcache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h (Write Back!)", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_i);
else if(CPU.dcache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h (Write Back!)", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_o);
end
else begin
if(CPU.dcache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Miss, Address: %h, Write Data: %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_i);
else if(CPU.dcache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Miss , Address: %h, Read Data : %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_o);
end
flag = 1'b1;
end
else if(!CPU.dcache.p1_stall_o) begin
if(!flag) begin
if(CPU.dcache.p1_MemWrite_i)
$fdisplay(outfile2, "Cycle: %d, Write Hit , Address: %h, Write Data: %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_i);
else if(CPU.dcache.p1_MemRead_i)
$fdisplay(outfile2, "Cycle: %d, Read Hit , Address: %h, Read Data : %h", counter, CPU.dcache.p1_addr_i, CPU.dcache.p1_data_o);
end
flag = 1'b0;
end
counter = counter + 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int D = 1e6 + 3; const int MAXN = 110; int F[MAXN]; struct Mt { int v[MAXN][MAXN]; int N, M; Mt() { for (int i = 0; i < MAXN; i++) { for (int j = 0; j < MAXN; j++) { v[i][j] = 0; } } } void I() { for (int i = 0; i < N; i++) { for (int j = 0; j < M; j++) { v[i][j] = 0; } v[i][i] = 1; } } void pr() { for (int i = 0; i < N; i++) { for (int j = 0; j < M; j++) { cout << v[i][j]; } cout << endl; } } }; Mt operator*(Mt A, Mt B) { Mt Res; Res.N = A.N; Res.M = B.M; for (int k = 0; k < A.M; k++) { for (int i = 0; i < Res.N; i++) { for (int j = 0; j < Res.M; j++) { Res.v[i][j] += (1ll * A.v[i][k] * B.v[k][j]) % D; Res.v[i][j] %= D; } } } return Res; } Mt pw(Mt A, int p) { Mt Res; Res.N = A.N; Res.M = A.M; Res.I(); while (p) { if (p & 1) { Res = Res * A; } A = A * A; p >>= 1; } return Res; } int main() { int C, W, H; cin >> C >> W >> H; F[0] = 1; for (int i = 1; i < W + 1; i++) { F[i] = H * F[i - 1]; F[i] %= D; } Mt A; A.N = W + 1; A.M = W + 1; for (int i = 0; i < W; i++) { A.v[i][i + 1] = 1; } for (int i = 0; i < W + 1; i++) { A.v[W][i] = F[W - i]; } Mt ans = pw(A, C); cout << (ans.v[W][W] + ans.v[W][W - 1]) % D << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int N, Y[50001]; set<int> pos[50001]; set<int> used; priority_queue<int> q; int next(int x) { int temp = x; while (x != 0) { if (used.count(x) == 0) return x; x /= 2; } return temp; } int main() { cin >> N; for (int i = 0; i < N; i++) { cin >> Y[i]; used.insert(Y[i]); q.push(Y[i]); } for (;;) { int num = next(q.top()); if (q.top() == num) break; used.erase(num); used.insert(num); q.pop(); q.push(num); } while (!q.empty()) { cout << q.top() << ; q.pop(); } cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, k, x, y, z, a[5005], b[50005], ans, val; int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n; for (long long i = 0; i < n; i++) cin >> a[i]; cin >> m; for (long long i = 0; i < m; i++) cin >> b[i]; sort(a, a + n); sort(b, b + m); cout << a[n - 1] << << b[m - 1]; return 0; } |
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2005,2006 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module shifter(input wire [33:0] in, output wire [15:0] out, input wire [7:0] shift);
// Wish we could do assign out = in[15+shift:shift];
reg [15:0] quotient, remainder;
wire [15:0] out_unclipped;
reg [18:0] msbs;
wire in_range;
always @*
case(shift)
0 : quotient = in[15:0];
1 : quotient = in[16:1];
2 : quotient = in[17:2];
3 : quotient = in[18:3];
4 : quotient = in[19:4];
5 : quotient = in[20:5];
6 : quotient = in[21:6];
7 : quotient = in[22:7];
8 : quotient = in[23:8];
9 : quotient = in[24:9];
10 : quotient = in[25:10];
11 : quotient = in[26:11];
12 : quotient = in[27:12];
13 : quotient = in[28:13];
14 : quotient = in[29:14];
15 : quotient = in[30:15];
16 : quotient = in[31:16];
17 : quotient = in[32:17];
18 : quotient = in[33:18];
default : quotient = in[15:0];
endcase // case(shift)
always @*
case(shift)
0 : remainder = 16'b0;
1 : remainder = {in[0],15'b0};
2 : remainder = {in[1:0],14'b0};
3 : remainder = {in[2:0],13'b0};
4 : remainder = {in[3:0],12'b0};
5 : remainder = {in[4:0],11'b0};
6 : remainder = {in[5:0],10'b0};
7 : remainder = {in[6:0],9'b0};
8 : remainder = {in[7:0],8'b0};
9 : remainder = {in[8:0],7'b0};
10 : remainder = {in[9:0],6'b0};
11 : remainder = {in[10:0],5'b0};
12 : remainder = {in[11:0],4'b0};
13 : remainder = {in[12:0],3'b0};
14 : remainder = {in[13:0],2'b0};
15 : remainder = {in[14:0],1'b0};
16 : remainder = in[15:0];
17 : remainder = in[16:1];
18 : remainder = in[17:2];
default : remainder = 16'b0;
endcase // case(shift)
always @*
case(shift)
0 : msbs = in[33:15];
1 : msbs = {in[33],in[33:16]};
2 : msbs = {{2{in[33]}},in[33:17]};
3 : msbs = {{3{in[33]}},in[33:18]};
4 : msbs = {{4{in[33]}},in[33:19]};
5 : msbs = {{5{in[33]}},in[33:20]};
6 : msbs = {{6{in[33]}},in[33:21]};
7 : msbs = {{7{in[33]}},in[33:22]};
8 : msbs = {{8{in[33]}},in[33:23]};
9 : msbs = {{9{in[33]}},in[33:24]};
10 : msbs = {{10{in[33]}},in[33:25]};
11 : msbs = {{11{in[33]}},in[33:26]};
12 : msbs = {{12{in[33]}},in[33:27]};
13 : msbs = {{13{in[33]}},in[33:28]};
14 : msbs = {{14{in[33]}},in[33:29]};
15 : msbs = {{15{in[33]}},in[33:30]};
16 : msbs = {{16{in[33]}},in[33:31]};
17 : msbs = {{17{in[33]}},in[33:32]};
18 : msbs = {{18{in[33]}},in[33]};
default : msbs = in[33:15];
endcase // case(shift)
assign in_range = &msbs | ~(|msbs);
assign out_unclipped = quotient + (in[33] & |remainder);
assign out = in_range ? out_unclipped : {in[33],{15{~in[33]}}};
endmodule // shifter
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BO_BLACKBOX_V
`define SKY130_FD_SC_MS__A21BO_BLACKBOX_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BO_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { string s; cin >> s; s = * + s; int add = 0; int n = (s.length()) - 1; for (int i = 1; i + i <= n; i++) { if (s[i] != s[s.size() - i]) { add++; } } if (add <= 1 && (n & 1) || add == 1) cout << YES n ; else cout << NO n ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVPWRVGND_FUNCTIONAL_V
`define SKY130_FD_SC_LS__TAPVPWRVGND_FUNCTIONAL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__tapvpwrvgnd ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVPWRVGND_FUNCTIONAL_V |
#include <bits/stdc++.h> int main() { char x[205]; scanf( %s , x); for (int i = 0; i < strlen(x); i++) { if (x[i] == . ) { x[i] = 0 ; printf( %c , x[i]); } if (x[i] == - && x[i + 1] == . ) { x[i] = 1 ; printf( %c , x[i]); i = i + 1; } if (x[i] == - && x[i + 1] == - ) { x[i] = 2 ; printf( %c , x[i]); i = i + 1; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int t, memo[402][402][402], idx, n, m; string x, y; void read(string &s) { char c[404]; scanf( %s , c); s = c; } int dp(int i, int j, int k) { if (i == n) { if (k == m) return j; else return -10; } int &ret = memo[i][j][k]; if (ret != -1) return ret; ret = dp(i + 1, j, k); if (j < m) { if (x[i] == y[j]) { ret = max(ret, dp(i + 1, j + 1, k)); } } if (k < m) { if (x[i] == y[k]) { ret = max(ret, dp(i + 1, j, k + 1)); } } return ret; } int main() { scanf( %d , &t); while (t--) { read(x); read(y); n = x.size(); m = y.size(); for (int i = 0; i < n + 2; i++) { for (int j = 0; j < m + 2; j++) { for (int k = 0; k < m + 2; k++) { memo[i][j][k] = -1; } } } bool b = 0; for (int i = 0; i < m; i++) { idx = dp(0, 0, i); if (i <= idx) { b = 1; break; } } b ? printf( YES n ) : printf( NO n ); } } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; long long a[N], pre[N]; int n; long long check(int p, int len) { return pre[p] - pre[p - len - 1] + pre[n] - pre[n - len]; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); sort(a + 1, a + 1 + n); for (int i = 1; i <= n; i++) pre[i] = pre[i - 1] + a[i]; int p = 1, len = 0; long long ans = 0; for (int i = 1; i <= n; i++) { int l = 1, r = min(i - 1, n - i), mid; while (r >= l) { mid = l + r >> 1; if ((long long)check(i, mid) * (mid * 2 - 1) >= (long long)check(i, mid - 1) * (mid * 2 + 1)) { l = mid + 1; if ((long long)check(i, mid) * (len * 2 + 1) - a[i] * (len * 2 + 1) * (mid * 2 + 1) > (long long)ans * (mid * 2 + 1) - a[p] * (len * 2 + 1) * (mid * 2 + 1)) ans = check(i, mid), p = i, len = mid; } else r = mid - 1; } } printf( %d n , len * 2 + 1); for (int i = p - len; i <= p; i++) printf( %d , pre[i] - pre[i - 1]); for (int i = n - len + 1; i <= n; i++) printf( %d , pre[i] - pre[i - 1]); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using vvi = vector<vi>; using vll = vector<ll>; using vvll = vector<vll>; using vb = vector<bool>; using vd = vector<double>; using vs = vector<string>; using vpii = vector<pair<int, int>>; using vpll = vector<pair<ll, ll>>; using pii = pair<int, int>; using pll = pair<ll, ll>; int dx[8] = {0, 1, 1, 1, 0, -1, -1, -1}; int dy[8] = {1, 1, 0, -1, -1, -1, 0, 1}; void solve() { vi a(6); for (ll i = 0; i < 6; i++) cin >> a[i]; ; ll ans = ((a[0] + a[1] + a[2]) * (a[0] + a[1] + a[2]) - a[0] * a[0] - a[2] * a[2] - a[4] * a[4]); cout << ans << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ll t = 1; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { int n; cin >> n; getchar(); string s; cin >> s; int ans = 1000000; string cnt = ; for (int i = 0; i < n; ++i) { cnt += s[i]; string s1 = cnt; string s2 = s.substr(i + 1, i + 1); if (s1 == s2) { int x = (n - 2 * (i + 1)) + 1 + i + 1; if (ans > x) { ans = x; } } } printf( %d n , min(ans, n)); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int t; cin >> t; for (int k = 0; k < t; k++) { int n, total = 0; cin >> n; while (n / 10 > 0) { total = total + (n - (n % 10)); n = ((n - (n % 10)) / 10) + n % 10; } cout << total + (n % 10) << ; } return 0; } |
#include <bits/stdc++.h> int NEXT_FREE_ID = 0; std::unordered_map<std::string, int> stringId; namespace persistentid { int NEXT_FREE_INDEX = 1; int s[10000000], L[10000000], R[10000000]; int root[100005]; int n = 1 << 30; int upd(int p, int v, int id, int l = 0, int r = n) { int ID = NEXT_FREE_INDEX++; s[ID] = s[id] + v; if (r - l < 2) return ID; int mid = (l + r) / 2; L[ID] = L[id], R[ID] = R[id]; if (p < mid) L[ID] = upd(p, v, L[ID], l, mid); else R[ID] = upd(p, v, R[ID], mid, r); return ID; } int f(int p, int id, int l = 0, int r = n) { if (r - l < 2) return s[id]; int mid = (l + r) / 2; if (p < mid) return f(p, L[id], l, mid); else return f(p, R[id], mid, r); } } // namespace persistentid namespace persistentcount { int NEXT_FREE_INDEX = 1; int s[10000000], L[10000000], R[10000000]; int root[100005]; int n = 1 << 30; int upd(int p, int v, int id, int l = 0, int r = n) { int ID = NEXT_FREE_INDEX++; s[ID] = s[id] + v; if (r - l < 2) return ID; int mid = (l + r) / 2; L[ID] = L[id], R[ID] = R[id]; if (p < mid) L[ID] = upd(p, v, L[ID], l, mid); else R[ID] = upd(p, v, R[ID], mid, r); return ID; } int sum(int x, int y, int id, int l = 0, int r = n) { if (x >= r || l >= y) return 0; if (x <= l && r <= y) return s[id]; int mid = (l + r) / 2; return sum(x, y, L[id], l, mid) + sum(x, y, R[id], mid, r); } } // namespace persistentcount int main() { std::ios::sync_with_stdio(0); std::cin.tie(0); std::cout.tie(0); int Q; std::cin >> Q; for (int q = 1; q <= Q; q++) { std::string type; std::cin >> type; if (type == set ) { std::string a; std::cin >> a; int x; std::cin >> x; if (stringId.count(a) == 0) { stringId[a] = NEXT_FREE_ID++; persistentid::root[q] = persistentid::NEXT_FREE_INDEX; persistentid::upd(stringId[a], x, persistentid::root[q - 1]); persistentcount::root[q] = persistentcount::NEXT_FREE_INDEX; persistentcount::upd(x, 1, persistentcount::root[q - 1]); } else { persistentid::root[q] = persistentid::NEXT_FREE_INDEX; int val = persistentid::f(stringId[a], persistentid::root[q - 1]); persistentid::upd(stringId[a], -val + x, persistentid::root[q - 1]); int temp = persistentcount::NEXT_FREE_INDEX; persistentcount::upd(val, -1, persistentcount::root[q - 1]); persistentcount::root[q] = persistentcount::NEXT_FREE_INDEX; persistentcount::upd(x, 1, temp); } } else if (type == remove ) { std::string a; std::cin >> a; if (stringId.count(a) != 0 && persistentid::f(stringId[a], persistentid::root[q - 1]) != 0) { int val = persistentid::f(stringId[a], persistentid::root[q - 1]); persistentcount::root[q] = persistentcount::NEXT_FREE_INDEX; persistentcount::upd(val, -1, persistentcount::root[q - 1]); persistentid::root[q] = persistentid::NEXT_FREE_INDEX; persistentid::upd(stringId[a], -val, persistentid::root[q - 1]); } else { persistentcount::root[q] = persistentcount::root[q - 1]; persistentid::root[q] = persistentid::root[q - 1]; } } else if (type == query ) { std::string a; std::cin >> a; persistentcount::root[q] = persistentcount::root[q - 1]; persistentid::root[q] = persistentid::root[q - 1]; if (stringId.count(a) != 0 && persistentid::f(stringId[a], persistentid::root[q - 1]) != 0) { std::cout << persistentcount::sum( 1, persistentid::f(stringId[a], persistentid::root[q - 1]), persistentcount::root[q - 1]) << n << std::flush; } else { std::cout << -1 n << std::flush; } } else { int d; std::cin >> d; d = q - 1 - d; persistentcount::root[q] = persistentcount::root[d]; persistentid::root[q] = persistentid::root[d]; } } } |
#include <bits/stdc++.h> using namespace std; int N; vector<int> fen, v; void _update(int i) { while (i <= N) { fen[i]++; i += i & -i; } } int _sum(int i) { int ret = 0; while (i > 0) { ret += fen[i]; i -= i & -i; } return ret; } int _bin(int i) { int sum = _sum(i); int imin = 1, imax = i; while (imin <= imax) { int imid = (imin + imax) / 2; if (sum - _sum(imid - 1) >= v[i]) imin = imid + 1; else imax = imid - 1; } return imax; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int Q; cin >> N >> Q; v = vector<int>(N + 1); for (int n = 1; n <= N; ++n) { cin >> v[n]; } for (int n = 1; n <= N; ++n) { v[n] = n - v[n]; } vector<int> answer(Q); vector<vector<pair<int, int>>> _query(N + 1); for (int q = 0; q < Q; ++q) { int x, y; cin >> x >> y; _query[N - y].push_back({x + 1, q}); } fen = vector<int>(N + 1); for (int r = 1; r <= N; ++r) { if (v[r] == 0) { _update(r); } else if (v[r] > 0) { int tmp = _bin(r); if (tmp) _update(tmp); } for (auto x : _query[r]) { answer[x.second] = _sum(r) - _sum(x.first - 1); } } for (auto x : answer) cout << x << n ; return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module setting_reg
#(parameter my_addr = 0,
parameter width = 32,
parameter at_reset=32'd0)
(input clk, input rst, input strobe, input wire [7:0] addr,
input wire [31:0] in, output reg [width-1:0] out, output reg changed);
always @(posedge clk)
if(rst)
begin
out <= at_reset;
changed <= 1'b0;
end
else
if(strobe & (my_addr==addr))
begin
out <= in;
changed <= 1'b1;
end
else
changed <= 1'b0;
endmodule // setting_reg
|
#include <bits/stdc++.h> int cnt; int n, m, k; char s[1111][1111]; int c[1111][1111], vis[1111][1111]; int b[1111]; int tot; void dfs(int p, int q) { c[p][q] = cnt; vis[p][q] = 1; if (s[p - 1][q] == . && !vis[p - 1][q]) dfs(p - 1, q); if (s[p - 1][q] == * ) tot++; if (s[p + 1][q] == . && !vis[p + 1][q]) dfs(p + 1, q); if (s[p + 1][q] == * ) tot++; if (s[p][q - 1] == . && !vis[p][q - 1]) dfs(p, q - 1); if (s[p][q - 1] == * ) tot++; if (s[p][q + 1] == . && !vis[p][q + 1]) dfs(p, q + 1); if (s[p][q + 1] == * ) tot++; } int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) scanf( %s , s[i] + 1); for (int i = 0; i <= m + 1; i++) { s[0][i] = s[n + 1][i] = # ; } for (int i = 1; i <= n; i++) s[i][0] = s[i][m + 1] = # ; cnt = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) vis[i][j] = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (!vis[i][j] && s[i][j] == . ) { tot = 0; cnt++; dfs(i, j); b[cnt] = tot; } for (int i = 1; i <= k; i++) { int x, y; scanf( %d%d , &x, &y); printf( %d n , b[c[x][y]]); } return 0; } |
#include <bits/stdc++.h> using namespace std; class Data { public: int l, r, num; Data() {} Data(int a, int b, int c) { l = a; r = b; num = c; } bool operator<(const Data& a) const { return l < a.r; } }; vector<Data> a; int main() { int L, b, f, n, q, k; cin >> L >> b >> f >> n; for (int(qwe) = 0; (qwe) < (n); ++(qwe)) { cin >> q >> k; if (q == 2) { for (__typeof((a).begin()) i = (a).begin(); i != (a).end(); ++i) if (i->num == k) { a.erase(i); break; } } else { bool ok = 0; int l = 0; int r = L - k; if (!a.empty()) r = a[0].l - k - f; if (l <= r) { a.insert(a.begin(), Data(l, l + k, qwe + 1)); cout << l << endl; continue; } for (int i = 0; i < ((int)(a).size()) - 1; ++i) if (a[i].r + b <= a[i + 1].l - f - k) { cout << a[i].r + b << endl; a.insert(a.begin() + i + 1, Data(a[i].r + b, a[i].r + b + k, qwe + 1)); ok = 1; break; } if (ok) continue; r = L - k; l = 0; if (!a.empty()) l = a.back().r + b; if (l <= r) { a.push_back(Data(l, l + k, qwe + 1)); cout << l << endl; } else cout << -1 n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int p[50001], n, l, r; queue<int> ver[50001]; void go(int pre, int v) { int t; p[v] = pre; if (v != l) { while (!ver[v].empty()) { t = ver[v].front(); ver[v].pop(); if (t != pre) go(v, t); } } } int main() { scanf( %d%d%d , &n, &l, &r); l--; r--; for (int i = 0; i < n; i++) if (i == l) continue; else { scanf( %d , &p[i]); p[i]--; ver[p[i]].push(i); ver[i].push(p[i]); } go(-1, r); for (int i = 0; i < n; i++) if (i == r) continue; else printf( %d , p[i] + 1); return 0; } |
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