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// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
integer v;
reg i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oa; // From a of a.v
wire oz; // From z of z.v
// End of automatics
a a (.*);
z z (.*);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n",$time, cyc, i, oa, oz);
`endif
cyc <= cyc + 1;
i <= cyc[0];
if (cyc==0) begin
v = 3;
if (v !== 3) $stop;
if (assignin(v) !== 2) $stop;
if (v !== 3) $stop; // Make sure V didn't get changed
end
else if (cyc<10) begin
if (cyc==11 && oz!==1'b0) $stop;
if (cyc==12 && oz!==1'b1) $stop;
if (cyc==12 && oa!==1'b1) $stop;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer assignin(input integer i);
i = 2;
assignin = i;
endfunction
endmodule
module a (input i, output oa);
// verilator lint_off ASSIGNIN
assign i = 1'b1;
assign oa = i;
endmodule
module z (input i, output oz);
assign oz = i;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, t; cin >> n; vector<int> v; for (int i = 0; i < n; i++) { cin >> t; v.push_back(t); } bool is = true; for (int i = 0; i < n; i++) { bool br = false; for (int j = 1000; j >= 1; j /= 10) { for (int k = (v[i] % (j * 10)) / j; k > 0; k--) { if (v[i] - k * j <= 2011 && v[i] - k * j >= 1000 && (i == 0 || v[i - 1] <= v[i] - k * j)) { v[i] -= (k * j); br = true; break; } } if (br) break; } if (v[i] <= 2011 && v[i] >= 1000 && (i == 0 || v[i - 1] <= v[i])) continue; if (!br) { for (int j = 1; j <= 1000; j *= 10) { for (int k = 1; k <= 9 - (v[i] % (j * 10)) / j; k++) { if (v[i] + k * j <= 2011 && v[i] + k * j >= 1000 && (i == 0 || v[i - 1] <= v[i] + k * j)) { v[i] += (k * j); br = true; break; } } if (br) break; } } if (!br) { is = false; break; } } if (!is) { cout << No solution << endl; } else { for (int i = 0; i < n; i++) cout << v[i] << endl; } } |
#include <bits/stdc++.h> using namespace std; int N, L, K; string s; int cnt[26]; string res[1000]; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> N >> L >> K; cin >> s; for (int i = 0; i < N * L; i++) cnt[s[i] - a ]++; int l = 0; int t = 0; while (l < K - 1 and t < 26) { int st = cnt[t]; for (int j = 0, _t = cnt[t]; j < _t; j++) { if (res[l + j % (K - l)].size() == L) { l = K + 1; break; } res[l + j % (K - l)] += (char)(t + a ); cnt[t]--; } l += st % (K - l); t++; } int lst = 25; for (int i = 0; i < K - 1; i++) { while (res[i].size() < L) { while (cnt[lst] == 0) lst--; res[i] += (char)(lst + a ); cnt[lst]--; } } int fst = 0; for (int i = K - 1; i < N; i++) { while (res[i].size() < L) { while (cnt[fst] == 0) fst++; res[i] += (char)(fst + a ); cnt[fst]--; } } sort(res, res + N); for (int i = 0; i < N; i++) { cout << res[i] << n ; } } |
#include <bits/stdc++.h> using namespace std; map<int, int> s; int a[2000]; int main(int argc, char const *argv[]) { int n; cin >> n; for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { int sum = a[i] + a[j]; if (s.find(sum) == s.end()) s[sum] = 1; else s[sum]++; } } int ans = 0; for (auto i : s) { ans = max(ans, i.second); } cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_PP_SYMBOL_V
`define SKY130_FD_SC_HS__O41A_PP_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o41a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int a[20007]; int main() { ios_base::sync_with_stdio(0); int t = 1; while (t--) { int n; cin >> n; map<int, int> mp; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; mp[x] = y; if (mp[x] == -1 * mp[x + y]) { cout << YES ; return 0; } } cout << NO << n ; } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:54:25 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_ov7670_vga_1_0 -prefix
// system_ov7670_vga_1_0_ system_ov7670_vga_0_0_stub.v
// Design : system_ov7670_vga_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_vga,Vivado 2016.4" *)
module system_ov7670_vga_1_0(pclk, data, rgb)
/* synthesis syn_black_box black_box_pad_pin="pclk,data[7:0],rgb[15:0]" */;
input pclk;
input [7:0]data;
output [15:0]rgb;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long best; int n, m, k; int main() { cin >> n >> m >> k; if (k > n + m - 2) cout << -1 << endl; else { for (int area = 1; area <= (int)sqrt(n); area++) { int x = n / area; if (n / x == area) { int cut = min(k, x - 1); int remainCut = k - cut; if (remainCut + 1 != 0) best = max(best, (long long)area * (long long)(m / (remainCut + 1))); } int _area = n / area; x = n / _area; if (n / x == _area) { int cut = min(k, x - 1); int remainCut = k - cut; if (remainCut + 1 != 0) best = max(best, (long long)_area * (long long)(m / (remainCut + 1))); } } cout << best << endl; } return 0; } |
//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
//VERSION_BEGIN 15.1 cbx_altiobuf_out 2015:10:21:18:09:22:SJ cbx_mgl 2015:10:21:18:12:49:SJ cbx_stratixiii 2015:10:21:18:09:23:SJ cbx_stratixv 2015:10:21:18:09:23:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module lpddr2_cntrlr_p0_clock_pair_generator
(
datain,
dataout,
dataout_b) /* synthesis synthesis_clearbox=1 */;
input [0:0] datain;
output [0:0] dataout;
output [0:0] dataout_b;
wire [0:0] wire_obuf_ba_o;
wire [0:0] wire_obuf_ba_oe;
wire [0:0] wire_obufa_o;
wire [0:0] wire_obufa_oe;
wire [0:0] wire_pseudo_diffa_o;
wire [0:0] wire_pseudo_diffa_obar;
wire [0:0] wire_pseudo_diffa_oebout;
wire [0:0] wire_pseudo_diffa_oein;
wire [0:0] wire_pseudo_diffa_oeout;
wire [0:0] oe_w;
cyclonev_io_obuf obuf_ba_0
(
.i(wire_pseudo_diffa_obar),
.o(wire_obuf_ba_o[0:0]),
.obar(),
.oe(wire_obuf_ba_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obuf_ba_0.bus_hold = "false",
obuf_ba_0.open_drain_output = "false",
obuf_ba_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obuf_ba_oe = {(~ wire_pseudo_diffa_oebout[0])};
cyclonev_io_obuf obufa_0
(
.i(wire_pseudo_diffa_o),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_oe = {(~ wire_pseudo_diffa_oeout[0])};
cyclonev_pseudo_diff_out pseudo_diffa_0
(
.dtc(),
.dtcbar(),
.i(datain),
.o(wire_pseudo_diffa_o[0:0]),
.obar(wire_pseudo_diffa_obar[0:0]),
.oebout(wire_pseudo_diffa_oebout[0:0]),
.oein(wire_pseudo_diffa_oein[0:0]),
.oeout(wire_pseudo_diffa_oeout[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dtcin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
assign
wire_pseudo_diffa_oein = {(~ oe_w[0])};
assign
dataout = wire_obufa_o,
dataout_b = wire_obuf_ba_o,
oe_w = 1'b1;
endmodule //lpddr2_cntrlr_p0_clock_pair_generator
//VALID FILE
|
#include <bits/stdc++.h> typedef struct { int dollar; int cent; } money; money q[110]; int w[110]; int main() { int i, j, n, m, k = 0, l = 0; scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) scanf( %d%d , &q[i].dollar, &q[i].cent); for (i = 1; i <= n; i++) { if (q[i].dollar < m || (q[i].dollar == m && q[i].cent == 0)) { if (!k) k = 1; if (q[i].cent == 0) continue; else l = (l > 100 - q[i].cent) ? l : 100 - q[i].cent; } } if (!k) printf( -1 n ); else printf( %d n , l); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_POWER_LVC_WPAD_BLACKBOX_V
`define SKY130_FD_IO__TOP_POWER_LVC_WPAD_BLACKBOX_V
/**
* top_power_lvc_wpad: A power pad with an ESD low-voltage clamp.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_power_lvc_wpad (
P_PAD ,
AMUXBUS_A,
AMUXBUS_B
);
inout P_PAD ;
inout AMUXBUS_A;
inout AMUXBUS_B;
// Voltage supply signals
supply0 SRC_BDY_LVC1;
supply0 SRC_BDY_LVC2;
supply1 OGC_LVC ;
supply1 DRN_LVC1 ;
supply1 BDY2_B2B ;
supply0 DRN_LVC2 ;
supply1 P_CORE ;
supply1 VDDIO ;
supply1 VDDIO_Q ;
supply1 VDDA ;
supply1 VCCD ;
supply1 VSWITCH ;
supply1 VCCHIB ;
supply0 VSSA ;
supply0 VSSD ;
supply0 VSSIO_Q ;
supply0 VSSIO ;
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_POWER_LVC_WPAD_BLACKBOX_V
|
module sgpr_simx_wr_port_mux (
wr_port_select,
port0_wr_en,
port0_wr_addr,
port0_wr_data,
port0_wr_mask,
port1_wr_en,
port1_wr_addr,
port1_wr_data,
port1_wr_mask,
port2_wr_en,
port2_wr_addr,
port2_wr_data,
port2_wr_mask,
port3_wr_en,
port3_wr_addr,
port3_wr_data,
port3_wr_mask,
port4_wr_en,
port4_wr_addr,
port4_wr_data,
port4_wr_mask,
port5_wr_en,
port5_wr_addr,
port5_wr_data,
port5_wr_mask,
port6_wr_en,
port6_wr_addr,
port6_wr_data,
port6_wr_mask,
port7_wr_en,
port7_wr_addr,
port7_wr_data,
port7_wr_mask,
muxed_port_wr_en,
muxed_port_wr_addr,
muxed_port_wr_data,
muxed_port_wr_mask
);
output muxed_port_wr_en;
output [8:0] muxed_port_wr_addr;
output [63:0] muxed_port_wr_data;
output [63:0] muxed_port_wr_mask;
input [15:0] wr_port_select;
input port0_wr_en;
input [8:0] port0_wr_addr;
input [63:0] port0_wr_data;
input [63:0] port0_wr_mask;
input port1_wr_en;
input [8:0] port1_wr_addr;
input [63:0] port1_wr_data;
input [63:0] port1_wr_mask;
input port2_wr_en;
input [8:0] port2_wr_addr;
input [63:0] port2_wr_data;
input [63:0] port2_wr_mask;
input port3_wr_en;
input [8:0] port3_wr_addr;
input [63:0] port3_wr_data;
input [63:0] port3_wr_mask;
input port4_wr_en;
input [8:0] port4_wr_addr;
input [63:0] port4_wr_data;
input [63:0] port4_wr_mask;
input port5_wr_en;
input [8:0] port5_wr_addr;
input [63:0] port5_wr_data;
input [63:0] port5_wr_mask;
input port6_wr_en;
input [8:0] port6_wr_addr;
input [63:0] port6_wr_data;
input [63:0] port6_wr_mask;
input port7_wr_en;
input [8:0] port7_wr_addr;
input [63:0] port7_wr_data;
input [63:0] port7_wr_mask;
reg muxed_port_wr_en;
reg [8:0] muxed_port_wr_addr;
reg [63:0] muxed_port_wr_data;
reg [63:0] muxed_port_wr_mask;
always @ (
wr_port_select or
port0_wr_en or
port0_wr_addr or
port0_wr_data or
port0_wr_mask or
port1_wr_en or
port1_wr_addr or
port1_wr_data or
port1_wr_mask or
port2_wr_en or
port2_wr_addr or
port2_wr_data or
port2_wr_mask or
port3_wr_en or
port3_wr_addr or
port3_wr_data or
port3_wr_mask or
port4_wr_en or
port4_wr_addr or
port4_wr_data or
port4_wr_mask or
port5_wr_en or
port5_wr_addr or
port5_wr_data or
port5_wr_mask or
port6_wr_en or
port6_wr_addr or
port6_wr_data or
port6_wr_mask or
port7_wr_en or
port7_wr_addr or
port7_wr_data or
port7_wr_mask
) begin
casex(wr_port_select)
16'h0001:
begin
muxed_port_wr_en <= port0_wr_en;
muxed_port_wr_addr <= port0_wr_addr;
muxed_port_wr_data <= port0_wr_data;
muxed_port_wr_mask <= port0_wr_mask;
end
16'h0002:
begin
muxed_port_wr_en <= port1_wr_en;
muxed_port_wr_addr <= port1_wr_addr;
muxed_port_wr_data <= port1_wr_data;
muxed_port_wr_mask <= port1_wr_mask;
end
16'h0004:
begin
muxed_port_wr_en <= port2_wr_en;
muxed_port_wr_addr <= port2_wr_addr;
muxed_port_wr_data <= port2_wr_data;
muxed_port_wr_mask <= port2_wr_mask;
end
16'h0008:
begin
muxed_port_wr_en <= port3_wr_en;
muxed_port_wr_addr <= port3_wr_addr;
muxed_port_wr_data <= port3_wr_data;
muxed_port_wr_mask <= port3_wr_mask;
end
16'h0010:
begin
muxed_port_wr_en <= port4_wr_en;
muxed_port_wr_addr <= port4_wr_addr;
muxed_port_wr_data <= port4_wr_data;
muxed_port_wr_mask <= port4_wr_mask;
end
16'h0020:
begin
muxed_port_wr_en <= port5_wr_en;
muxed_port_wr_addr <= port5_wr_addr;
muxed_port_wr_data <= port5_wr_data;
muxed_port_wr_mask <= port5_wr_mask;
end
16'h0040:
begin
muxed_port_wr_en <= port6_wr_en;
muxed_port_wr_addr <= port6_wr_addr;
muxed_port_wr_data <= port6_wr_data;
muxed_port_wr_mask <= port6_wr_mask;
end
16'h0080:
begin
muxed_port_wr_en <= port7_wr_en;
muxed_port_wr_addr <= port7_wr_addr;
muxed_port_wr_data <= port7_wr_data;
muxed_port_wr_mask <= port7_wr_mask;
end
16'b0000:
begin
muxed_port_wr_en <= 1'b0;
muxed_port_wr_addr <= {9{1'bx}};
muxed_port_wr_data <= {64{1'bx}};
muxed_port_wr_mask <= {64{1'bx}};
end
default:
begin
muxed_port_wr_en <= 1'bx;
muxed_port_wr_addr <= {9{1'bx}};
muxed_port_wr_data <= {64{1'bx}};
muxed_port_wr_mask <= {64{1'bx}};
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_S_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_S_SYMBOL_V
/**
* udp_dff$PS_pp$PKG$s: Positive edge triggered D flip-flop with
* active high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PS_pp$PKG$s (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B,
input KAPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PS_PP_PKG_S_SYMBOL_V
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/virtex4/BUFIO.v,v 1.4 2007/06/01 22:41:59 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Local Clock Buffer for I/O
// /___/ /\ Filename : BUFIO.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:43 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/30/07 - change timescale to 1ps/1ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFIO (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
reg notifier;
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; void bogo(vector<int>& a) { for (int i = 0; i < a.size() - 1; i++) { int biggest = i; for (int j = i + 1; j < a.size(); j++) if (a[biggest] < a[j]) biggest = j; if (biggest != i) swap(a[i], a[biggest]); } } int main(int argc, char** argv) { int t = 0; cin >> t; for (int i = 0; i < t; i++) { int n = 0; cin >> n; vector<int> a; for (int j = 0; j < n; j++) { int v = 0; cin >> v; a.push_back(v); } bogo(a); for (auto v : a) cout << v << ; cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 1e5 + 5; long long qpow(long long a, long long b, long long r) { long long ans = 1, buff = a % r; while (b) { if (b & 1) ans = (ans * buff) % r; buff = (buff * buff) % r; b >>= 1; } return ans; } long long f_inv(long long a, long long p) { return qpow(a, p - 2, p); } string s; long long k, ans = 0; int main() { ios::sync_with_stdio(false); cin >> s >> k; if (s[0] == - || s[0] == + ) s.erase(s.begin()); long long len = s.length(); for (long long i = 0; i < len; i++) { if (s[i] == 0 || s[i] == 5 ) { ans += qpow(2, i, mod); ans %= mod; } } long long x = qpow(2, len, mod); long long y = qpow(x, k, mod); x--, y--; ans = ans * (y * f_inv(x, mod) % mod) % mod; cout << ans << endl; return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9361_tx_channel (
// dac interface
dac_clk,
dac_rst,
dac_dds_data,
// processor interface
dac_dds_enable,
dac_dds_data_enable,
dac_dds_format,
dac_dds_pattenb,
dac_lb_enb,
dac_pn_enb,
// bus interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter CHID = 32'h0;
parameter DP_DISABLE = 0;
// dac interface
input dac_clk;
input dac_rst;
output [15:0] dac_dds_data;
// processor interface
input dac_dds_enable;
input dac_dds_data_enable;
input dac_dds_format;
input dac_dds_pattenb;
output dac_lb_enb;
output dac_pn_enb;
// bus interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal signals
wire [15:0] dac_dds_patt_1_s;
wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
wire [ 3:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_patt_2_s;
wire [15:0] dac_dds_init_2_s;
wire [15:0] dac_dds_incr_2_s;
wire [ 3:0] dac_dds_scale_2_s;
// single channel dds
axi_ad9361_tx_dds #(.DP_DISABLE(DP_DISABLE)) i_tx_dds (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_data (dac_dds_data),
.dac_dds_enable (dac_dds_enable),
.dac_dds_data_enable (dac_dds_data_enable),
.dac_dds_format (dac_dds_format),
.dac_dds_pattenb (dac_dds_pattenb),
.dac_dds_patt_1 (dac_dds_patt_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_patt_2 (dac_dds_patt_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_dds_scale_2 (dac_dds_scale_2_s));
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_2 (dac_dds_scale_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_dds_patt_1 (dac_dds_patt_1_s),
.dac_dds_patt_2 (dac_dds_patt_2_s),
.dac_lb_enb (dac_lb_enb),
.dac_pn_enb (dac_pn_enb),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_interpolation_m (),
.up_usr_interpolation_n (),
.dac_usr_datatype_be (1'b0),
.dac_usr_datatype_signed (1'b1),
.dac_usr_datatype_shift (8'd0),
.dac_usr_datatype_total_bits (8'd16),
.dac_usr_datatype_bits (8'd16),
.dac_usr_interpolation_m (16'd1),
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata),
.up_ack (up_ack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int f(long long p) { int ans = 0; while (p) { ans += p % 10; p /= 10; } return ans; } long long g(long long a) { if (a == 0) return 0; int digit = 0; long long b = a; while (b >= 10) { digit++; b /= 10; } int b_digit = b; long long ans = b * digit; for (int i = 0; i < digit; i++) ans *= 10, b *= 10; ans *= 9; ans /= 2; for (int i = 0; i < b_digit; i++) ans += i * (b / b_digit); ans += g(a - b) + b_digit * (a - b + 1); return ans; } int main() { long long a; scanf( %lld , &a); long long l = 1, r = 20000000000000000LL; while (l < r) { long long mid = (l + r) / 2; if (g(mid) >= a) r = mid; else l = mid + 1; } l = 1; long long cur = g(r); while (cur != a) { if (cur > a) { cur -= f(l); l++; } else { cur += f(r + 1); r++; } } printf( %lld %lld , l, r); } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; long long n, q, op, root = 1; long long a[maxn]; long long head[maxn], to[maxn << 1], nxt[maxn << 1], cnt; inline void add(long long u, long long v) { nxt[++cnt] = head[u]; to[cnt] = v; head[u] = cnt; } namespace Tree_chain_partition { long long fa[maxn], son[maxn], size[maxn], dep[maxn], top[maxn]; void dfs1(long long u, long long f) { size[u] = 1; fa[u] = f; dep[u] = dep[f] + 1; for (register long long i = head[u]; i; i = nxt[i]) { long long v = to[i]; if (v == f) continue; dfs1(v, u); size[u] += size[v]; if (size[v] > size[son[u]]) son[u] = v; } } long long id[maxn], w[maxn], tot; void dfs2(long long u, long long topf) { id[u] = ++tot; w[tot] = a[u]; top[u] = topf; if (!son[u]) return; dfs2(son[u], topf); for (register long long i = head[u]; i; i = nxt[i]) { long long v = to[i]; if (v == son[u] || v == fa[u]) continue; dfs2(v, v); } } inline long long lca(long long x, long long y) { while (top[x] != top[y]) { if (dep[top[x]] < dep[top[y]]) swap(x, y); x = fa[top[x]]; } return dep[x] < dep[y] ? x : y; } long long find(long long x, long long y) { while (top[x] != top[y]) { if (dep[top[x]] < dep[top[y]]) swap(x, y); if (fa[top[x]] == y) return top[x]; x = fa[top[x]]; } return dep[x] < dep[y] ? son[x] : son[y]; } inline long long LCA(long long x, long long y) { if (dep[x] > dep[y]) swap(x, y); if (lca(x, y) == x) { if (id[y] <= id[root] && id[root] <= id[y] + size[y] - 1) { return y; } if (lca(x, root) == x) return lca(root, y); return x; } if (id[root] >= id[x] && id[root] <= id[x] + size[x] - 1) return x; if (id[root] >= id[y] && id[root] <= id[y] + size[y] - 1) return y; if ((lca(x, root) == root && lca(x, y) == lca(root, y)) || (lca(y, root) == root && lca(x, y) == lca(root, x))) { return root; } if (lca(x, root) == lca(y, root)) return lca(x, y); if (lca(x, y) != lca(x, root)) return lca(x, root); if (lca(x, y) != lca(y, root)) return lca(y, root); } } // namespace Tree_chain_partition using namespace Tree_chain_partition; namespace SegmentTree { struct SegmentTree { long long v, tag; } st[maxn << 2]; inline void push_up(long long rt) { st[rt].v = st[rt << 1].v + st[rt << 1 | 1].v; } void build(long long rt, long long l, long long r) { st[rt].tag = 0; if (l == r) { st[rt].v = w[l]; return; } long long mid = (l + r) >> 1; build(rt << 1, l, mid); build(rt << 1 | 1, mid + 1, r); push_up(rt); } inline void push_down(long long rt, long long l, long long r) { long long mid = (l + r) >> 1; st[rt << 1].v += st[rt].tag * (mid - l + 1); st[rt << 1 | 1].v += st[rt].tag * (r - mid); st[rt << 1].tag += st[rt].tag; st[rt << 1 | 1].tag += st[rt].tag; st[rt].tag = 0; } void modify(long long rt, long long l, long long r, long long ql, long long qr, long long val) { if (ql > r || qr < l) return; if (ql <= l && qr >= r) { st[rt].v += (r - l + 1) * val; st[rt].tag += val; return; } push_down(rt, l, r); long long mid = (l + r) >> 1; modify(rt << 1, l, mid, ql, qr, val); modify(rt << 1 | 1, mid + 1, r, ql, qr, val); push_up(rt); } long long query(long long rt, long long l, long long r, long long ql, long long qr) { if (ql > r || qr < l) return 0; if (ql <= l && qr >= r) return st[rt].v; push_down(rt, l, r); long long mid = (l + r) >> 1; return query(rt << 1, l, mid, ql, qr) + query(rt << 1 | 1, mid + 1, r, ql, qr); } void update(long long pos, long long val) { if (root == pos) { modify(1, 1, n, 1, n, val); return; } long long tmp = lca(root, pos); if (tmp != pos) { modify(1, 1, n, id[pos], id[pos] + size[pos] - 1, val); } else { long long loc = find(root, pos); modify(1, 1, n, 1, n, val); modify(1, 1, n, id[loc], id[loc] + size[loc] - 1, -val); } } long long ask(long long pos) { if (pos == root) return query(1, 1, n, 1, n); long long tmp = lca(pos, root); if (tmp != pos) { return query(1, 1, n, id[pos], id[pos] + size[pos] - 1); } long long loc = find(root, pos); return query(1, 1, n, 1, n) - query(1, 1, n, id[loc], id[loc] + size[loc] - 1); } } // namespace SegmentTree using namespace SegmentTree; template <typename T> inline void read(T &x) { x = 0; T f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + (ch ^ 48); ch = getchar(); } x *= f; } signed main() { read(n); read(q); for (register long long i = 1; i <= n; i++) { read(a[i]); } for (register long long i = 1, u, v; i < n; i++) { read(u), read(v); add(u, v); add(v, u); } dfs1(1, 0); dfs2(1, 1); build(1, 1, n); while (q--) { read(op); if (op == 1) read(root); if (op == 2) { long long x, y, val; read(x), read(y), read(val); update(LCA(x, y), val); } if (op == 3) { long long x; read(x); printf( %lld n , ask(x)); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main(void) { int t; cin >> t; while (t--) { long long n, p, k; cin >> n >> p >> k; long long ans = 0, pre = 0; vector<long long> a(n, -1); for (long long i = 0; i < n; ++i) { cin >> a[i]; } sort(a.begin(), a.end()); for (long long i = 0; i <= k; ++i) { long long sum = pre; if (sum > p) break; long long ct = i; for (long long j = i + k - 1; j < n; j += k) { if (sum + a[j] <= p) { ct += k; sum += a[j]; } else break; } pre += a[i]; ans = max(ans, ct); } cout << ans << endl; } return 0; } |
module LED (input clk, input enable, input [3:0] val, input [2:0] sidx, output reg[7:0] digit, output reg[7:0] segment);
always @(posedge clk)
begin
if (enable)
begin
case (sidx)
3'd0: begin digit <= 8'b11111110; end
3'd1: begin digit <= 8'b11111101; end
3'd2: begin digit <= 8'b11111011; end
3'd3: begin digit <= 8'b11110111; end
3'd4: begin digit <= 8'b11101111; end
3'd5: begin digit <= 8'b11011111; end
3'd6: begin digit <= 8'b10111111; end
3'd7: begin digit <= 8'b01111111; end
default: begin digit <= 8'b11111111; end
endcase
case (val)
3'b000: begin segment <= 8'b00000011; end
3'b001: begin segment <= 8'b10011111; end
3'b010: begin segment <= 8'b00100101; end
3'b011: begin segment <= 8'b00001101; end
3'b100: begin segment <= 8'b10011001; end
3'b101: begin segment <= 8'b01001001; end
3'b110: begin segment <= 8'b01000001; end
3'b111: begin segment <= 8'b00011111; end
4'b1000: begin segment <= 8'b00000001; end
4'b1001: begin segment <= 8'b00001001; end
default: begin segment <= 8'b11111111; end
endcase
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32A_BLACKBOX_V
`define SKY130_FD_SC_MS__O32A_BLACKBOX_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o32a (
X ,
A1,
A2,
A3,
B1,
B2
);
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32A_BLACKBOX_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Short halfband decimator (intended to be followed by another stage)
// Implements impulse responses of the form [A 0 B 0.5 B 0 A]
//
// These taps designed by halfgen4 from ldoolittle:
// 2 * 131072 * halfgen4(.75/8,2)
module small_hb_int
#(parameter WIDTH=18)
(input clk,
input rst,
input bypass,
input stb_in,
input [WIDTH-1:0] data_in,
input [7:0] output_rate,
input stb_out,
output reg [WIDTH-1:0] data_out);
reg phase;
reg [WIDTH-1:0] d1, d2, d3, d4, d5, d6;
localparam MWIDTH = 36;
wire [MWIDTH-1:0] prod;
reg [6:0] stbin_d;
always @(posedge clk)
stbin_d <= {stbin_d[5:0],stb_in};
always @(posedge clk)
if(stb_in)
begin
d1 <= data_in;
d2 <= d1;
d3 <= d2;
d4 <= d3;
d5 <= d4;
d6 <= d5;
end
wire [WIDTH-1:0] sum_outer, sum_inner;
add2_and_round_reg #(.WIDTH(WIDTH)) add_outer (.clk(clk),.in1(d1),.in2(d4),.sum(sum_outer));
add2_and_round_reg #(.WIDTH(WIDTH)) add_inner (.clk(clk),.in1(d2),.in2(d3),.sum(sum_inner));
wire [17:0] coeff_outer = -10690;
wire [17:0] coeff_inner = 75809;
MULT18X18S mult(.C(clk), .CE(1), .R(rst), .P(prod), .A(stbin_d[1] ? coeff_outer : coeff_inner),
.B(stbin_d[1] ? sum_outer : sum_inner) );
wire [MWIDTH:0] accum;
acc #(.IWIDTH(MWIDTH),.OWIDTH(MWIDTH+1))
acc (.clk(clk),.clear(stbin_d[2]),.acc(|stbin_d[3:2]),.in(prod),.out(accum));
wire [WIDTH+2:0] accum_rnd;
round_reg #(.bits_in(MWIDTH+1),.bits_out(WIDTH+3))
final_round (.clk(clk),.in(accum),.out(accum_rnd));
wire [WIDTH-1:0] clipped;
clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) final_clip
(.clk(clk),.in(accum_rnd),.strobe_in(1'b1), .out(clipped));
reg [WIDTH-1:0] saved, saved_d3;
always @(posedge clk)
if(stbin_d[6])
saved <= clipped;
always @(posedge clk)
if(stbin_d[3])
saved_d3 <= d3;
always @(posedge clk)
if(bypass)
data_out <= data_in;
else if(stb_in & stb_out)
case(output_rate)
1 : data_out <= d6;
2 : data_out <= d4;
3, 4, 5, 6, 7 : data_out <= d3;
default : data_out <= d2;
endcase // case(output_rate)
else if(stb_out)
data_out <= saved;
endmodule // small_hb_int
|
#include <bits/stdc++.h> using namespace std; inline long long min2(long long a, long long b) { return (a) < (b) ? (a) : (b); } inline long long max2(long long a, long long b) { return (a) > (b) ? (a) : (b); } inline long long max3(long long a, long long b, long long c) { return (a) > (b) ? ((a) > (c) ? (a) : (c)) : ((b) > (c) ? (b) : (c)); } inline long long min3(long long a, long long b, long long c) { return (a) < (b) ? ((a) < (c) ? (a) : (c)) : ((b) < (c) ? (b) : (c)); } pair<long long int, long long int> fsi(pair<long long int, long long int> a, pair<long long int, long long int> b) { pair<long long int, long long int> x; if (max(a.first, b.first) > min(a.second, b.second)) { x.first = 10000000000002; x.second = 10000000000002; } else { x.first = max(a.first, b.first); x.second = min(a.second, b.second); } return x; } void process() { long long int n, m, l, h, pt, ct; pair<long long int, long long int> p, curr; string ans; ans = YES ; bool and_found = false; pt = 0; cin >> n >> m; p.first = m; p.second = m; for (long long int i = 0; i < n; i++) { cin >> ct >> curr.first >> curr.second; if (!and_found) { p.first -= ct - pt; p.second += ct - pt; p = fsi(p, curr); if (p.first == 10000000000002) { and_found = true; ans = NO ; } pt = ct; } } cout << ans << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int t; cin >> t; ; while (t--) process(); } |
#include <bits/stdc++.h> using namespace std; const double EPS = 1e-7; const double PI = acos(-1.0); const double ZERO = 0; const double DOUBLE_MAX = 1 / ZERO; int main() { long double t, s, q; cin >> t >> s >> q; long double speed = (q - 1) / q; long double x = 0, d; int res = 0; while (t - s > 1e-9) { x += s * speed; while (t - s > 1e-9 && x > 1e-10) { s += (x) + 1e-9; x *= speed; } res++; } cout << res; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUFBUF_PP_SYMBOL_V
`define SKY130_FD_SC_HD__BUFBUF_PP_SYMBOL_V
/**
* bufbuf: Double buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__bufbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUFBUF_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long int n; int main() { cin >> n; long long int cnt = 0, c; for (long long int i = 2; i <= sqrt(n); i++) { if (n % i == 0) cnt++; } if (cnt == 0) { cout << n; goto skip; } for (long long int i = 2; i <= sqrt(n); i++) if (n % i == 0) { c = i; break; } while (n % c == 0) { n /= c; } if (n == 1) { cout << c; } else { cout << 1; } skip:; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, c[100005], visit[100005], tp = 0; vector<int> a[100005], ans; bool ok[100005]; void dfs(int u) { visit[u] = tp; for (int i = 0; i < a[u].size(); i++) { int v = a[u][i]; if (ok[v]) continue; if (visit[v] == tp) { cout << -1; exit(0); } else dfs(v); } ans.push_back(u); ok[u] = 1; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> k; for (int i = 1; i <= k; i++) cin >> c[i]; for (int i = 1; i <= n; i++) { int t; cin >> t; while (t--) { int u; cin >> u; a[i].push_back(u); } } for (int i = 1; i <= k; i++) { if (!visit[c[i]]) { tp++; dfs(c[i]); } } cout << ans.size() << n ; for (int i = 0; i < ans.size(); i++) cout << ans[i] << ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__OR3_PP_BLACKBOX_V
/**
* or3: 3-input OR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { long long a, b, c, i, j; cin >> a >> b >> c; string f, s, third; if (a) { s = string(a + 1, 0 ); } if (c) { f = string(c + 1, 1 ); } if (b) { bool flag; if (a == 0 && c) { flag = true; for (i = 0; i < b; i++) { if (flag) { third += 0 ; flag = false; } else { third += 1 ; flag = true; } } cout << f << third << endl; continue; } if (c) { b--; } flag = true; for (i = 0; i < b; i++) { if (flag) { third += 1 ; flag = false; } else { third += 0 ; flag = true; } } if (a == 0 && c == 0) { if (b & 1) third += 0 ; else third += 1 ; } } cout << f << s << third << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int t; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> t; while (t--) { string s; cin >> s; s = 0 + s; s = s + 0 ; for (int i = 1; i <= s.size(); i++) { if (s[i] == ? ) { if (s[i - 1] == a ) { if (s[i + 1] == b ) { s[i] = c ; } else { s[i] = b ; } } else { if (s[i - 1] == b ) { if (s[i + 1] == a ) { s[i] = c ; } else { s[i] = a ; } } else { if (s[i + 1] == b ) { s[i] = a ; } else { s[i] = b ; } } } } } bool b = 1; for (int i = 1; i <= s.size(); i++) { if (s[i] == s[i - 1]) { b = 0; } } if (b) { for (int i = 1; i <= s.size() - 2; i++) { cout << s[i]; } } else { cout << -1 ; } cout << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTN_2_V
`define SKY130_FD_SC_HS__DLXTN_2_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxtn_2 (
Q ,
D ,
GATE_N,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxtn_2 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTN_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BAI_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O21BAI_PP_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BAI_PP_SYMBOL_V
|
module alu_chkr(clk, reset_n, opcode_valid, opcode, data, result, overflow, done, checker_enable);
parameter DATA_WIDTH = 8;
input clk;
input reset_n;
input opcode_valid;
input opcode;
input [DATA_WIDTH-1:0] data;
input result;
input overflow;
input done;
input [4:0] checker_enable;
reg [DATA_WIDTH:0] result_buf;
reg [DATA_WIDTH-1:0] data_A;
reg [DATA_WIDTH-1:0] data_B;
reg [1:0] opcode_buf;
reg chkr1_State;
reg [1:0] chkr3_State;
reg [1:0] chkr4_State;
reg [1:0] chkr5_State;
parameter chkr1_CHECK = 1'b1;
parameter chkr1_RESET = 1'b0;
parameter chkr3_OPCODE1 = 2'b00;
parameter chkr3_OPCODE2 = 2'b01;
parameter chkr3_COMPUTE = 2'b10;
parameter chkr3_CHECK = 2'b11;
parameter chkr4_OPCODE1 = 2'b00;
parameter chkr4_OPCODE2 = 2'b01;
parameter chkr4_DONE = 2'b10;
parameter chkr5_OPCODE1 = 2'b00;
parameter chkr5_OPCODE2 = 2'b01;
parameter chkr5_DONE = 2'b10;
initial
begin
chkr1_State = chkr1_RESET;
chkr3_State = chkr3_OPCODE1;
chkr4_State = chkr4_OPCODE1;
chkr5_State = chkr5_OPCODE1;
end
always @(posedge clk)
begin
//$display("opcode: %h \t opcode_valid: %h \t data: %h \t result: %h \t overflow: %h \t done: %h",opcode, opcode_valid, data, result, overflow, done);
end
//Checker 1: when reset_n is asserted (driven to 0), all outputs become 0
//within 1 clock cycle.
always @(posedge clk)
begin
case(chkr1_State)
chkr1_RESET:
begin
if(reset_n && checker_enable[0])
begin
chkr1_State = chkr1_CHECK;
end
else
begin
chkr1_State = chkr1_RESET;
end
end
chkr1_CHECK:
begin
if (!data && !overflow && !done)
begin
$display("CHECKER 1 FAILED");
end
else
begin
$display("CHECKER 1 PASSED");
end
chkr1_State = chkr1_RESET;
end
endcase
end
//Checker 2: when opcode_valid is asserted, valid opcode and valid data
//(no X or Z) must be driven on the same cycle.
always @(posedge clk)
begin
if (opcode_valid && checker_enable[1])
begin
if(opcode == "x" || data == "xxxxxxxx")
begin
$display("CHECKER 2 FAILED");
end
else if(opcode == "z" || data == "zzzzzzzz")
begin
$display("CHECKER 2 FAILED");
end
else
begin
$display("CHECKER 2 PASSED");
end
end
end
//Checker 3: Output “done” must be asserted within 2 cycles after both valid data
//have been captured.
always @(posedge clk)
begin
case(chkr3_State)
chkr3_OPCODE1:
begin
if (opcode_valid && checker_enable[2])
begin
chkr3_State = chkr3_OPCODE2;
end
else
begin
chkr3_State = chkr3_OPCODE1;
end
end
chkr3_OPCODE2:
begin
if (opcode_valid)
begin
chkr3_State = chkr3_COMPUTE;
end
else
begin
chkr3_State = chkr3_OPCODE2;
end
end
chkr3_COMPUTE:
begin
chkr3_State = chkr3_CHECK;
end
chkr3_CHECK:
begin
if (done)
begin
$display("CHECKER 3 PASSED");
chkr3_State = chkr3_OPCODE1;
end
else
begin
$display("CHECKER 3 FAILED");
chkr3_State = chkr3_OPCODE1;
end
end
endcase
end
//Checker 4: Once “done’ is asserted, output “result” must be correct
//on the same cycle.
always @(posedge clk or done or opcode_valid or result or data or overflow or checker_enable[3])
begin
case(chkr4_State)
chkr4_OPCODE1:
begin
if(opcode_valid && checker_enable[3])
begin
data_A = data;
opcode_buf[0] = opcode;
chkr4_State = chkr4_OPCODE2;
end
else
begin
chkr4_State = chkr4_OPCODE1;
end
end
chkr4_OPCODE2:
begin
if(opcode_valid)
begin
data_B = data;
opcode_buf[1] = opcode;
chkr4_State = chkr4_DONE;
end
else
begin
chkr4_State = chkr4_OPCODE2;
end
end
chkr4_DONE:
begin
if(done)
begin
case(opcode_buf)
2'b00:
begin
result_buf = data_A + data_B;
end
2'b01:
begin
result_buf = data_A - data_B;
end
2'b10:
begin
result_buf = data_A ^ data_B;
end
2'b11:
begin
result_buf = data_A ~^ data_B;
end
endcase
if (result == result_buf[DATA_WIDTH-1:0])
begin
$display("CHECKER 4 PASSED");
end
else
begin
$display("CHECKER 4 FAILED");
end
chkr4_State = chkr4_OPCODE1;
end
else
begin
chkr4_State = chkr4_OPCODE1;
end
end
endcase
end
//Checker 5: Once “done’ is asserted, output “overflow” must be correct on the
//same cycle.
always @(posedge clk or done or overflow or checker_enable[4])
begin
case(chkr5_State)
chkr5_OPCODE1:
begin
if(opcode_valid && checker_enable[3])
begin
data_A = data;
opcode_buf[0] = opcode;
chkr5_State = chkr5_OPCODE2;
end
else
begin
chkr5_State = chkr5_OPCODE1;
end
end
chkr5_OPCODE2:
begin
if(opcode_valid)
begin
data_B = data;
opcode_buf[1] = opcode;
chkr5_State = chkr5_DONE;
end
else
begin
chkr5_State = chkr5_OPCODE2;
end
end
chkr5_DONE:
begin
if(done)
begin
case(opcode_buf)
2'b00:
begin
result_buf = data_A + data_B;
end
2'b01:
begin
result_buf = data_A - data_B;
end
2'b10:
begin
result_buf = data_A ^ data_B;
end
2'b11:
begin
result_buf = data_A ~^ data_B;
end
endcase
if (overflow == result_buf[DATA_WIDTH])
begin
$display("CHECKER 5 PASSED");
end
else
begin
$display("CHECKER 5 FAILED");
end
chkr5_State = chkr5_OPCODE1;
end
else
begin
chkr5_State = chkr5_OPCODE1;
end
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = INT_MAX; const long long INFL = LLONG_MAX; const long double pi = acos(-1); int N, M; string s[100]; long long d[1 << 20]; long double f[1 << 20]; int main() { ios_base::sync_with_stdio(0); cout.precision(15); cout << fixed; cout.tie(0); cin >> N; for (int(i) = 0, j123 = N; (i) < j123; (i)++) cin >> s[i]; M = s[0].size(); for (int(i) = 0, j123 = N; (i) < j123; (i)++) for (int(j) = 0, j123 = N; (j) < j123; (j)++) if (i != j) { int same = 0; for (int(k) = 0, j123 = M; (k) < j123; (k)++) if (s[i][k] == s[j][k]) same |= (1 << k); d[same] |= (1LL << i); } for (int mask = (1 << M) - 1; mask >= 0; mask--) for (int(i) = 0, j123 = M; (i) < j123; (i)++) if (!((mask >> i) & 1)) d[mask] |= d[mask | (1 << i)]; for (int mask = (1 << M) - 1; mask >= 0; mask--) { if (d[mask] == 0) continue; long double tot = 0; int cnt = 0; for (int(i) = 0, j123 = M; (i) < j123; (i)++) if (!((mask >> i) & 1)) { cnt++; tot += f[mask | (1 << i)] * __builtin_popcountll(d[mask | (1 << i)]) / __builtin_popcountll(d[mask]); } tot /= cnt; tot += 1; f[mask] = tot; } cout << f[0] << n ; } |
#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( O3 ) using namespace std; const double eps = 1e-9; const double pi = acos(-1.0); const int inf = 2e5 + 10; int mod = 1e9 + 7; const int MAXN = 1e5 + 7; long double C(int n, int k) { long double res = 1.; if (2 * k > n) k = n - k; for (int i = 1; i <= k; ++i) { res *= n - k + i; res /= i; } return res; } int32_t main() { ios_base::sync_with_stdio(0); cout << fixed << setprecision(10); cin.tie(0); int n, m; cin >> n >> m; long double res = 0; for (int k = 1; k <= min(n, m); ++k) { res += C(m, k) * C(m * (n - 1), n - k) * k * k; } res /= n; res /= C(n * m, n); cout << res; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } const long long maxn = (long long)1e6 + 6; const long double EPS = 1e-9; const long long INF = (long long)1e18 + 18; const long long mod = (long long)1e9 + 9; long long n, m, k; inline long long add(long long x, long long y) { x += y; if (x >= mod) x -= mod; return x; } inline long long sub(long long x, long long y) { x -= y; if (x < 0) x += mod; return x; } inline long long mul(long long x, long long y) { return (x * 1LL * y) % mod; } inline long long binpow(long long a, long long b) { long long x = 1 % mod; while (b) { if (b & 1) x = mul(x, a); a = mul(a, a); b >>= 1; } return x; } inline long long inv(long long a) { return binpow(a, mod - 2); } bool works(long long x) { long long t = x * k + ((n - x * k) / k) * (k - 1) + (n - x * k) % k; return t >= m; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m >> k; long long left = 0, right = (n + k - 1) / k; while (left < right) { long long mid = (left + right) >> 1; if (works(mid)) { right = mid; } else { left = mid + 1; } } long long ans = binpow(2, left + 1); ans = sub(ans, 2); ans = mul(ans, k); ans = add(ans, sub(m, left * k)); cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long cum[(int)1e6], input[(int)1e6], k, ans; char c; int sz, t; map<long long, vector<int>> pos; int main() { cin >> sz >> k; for (int i = 0; i < sz; i++) { scanf( %c%d , &c, &t); input[i] = t; if (i == 0) { cum[0] = t; } else { cum[i] = cum[i - 1] + input[i]; } pos[cum[i]].push_back(i); } for (long long target = 1; abs(target) <= 1e16; target *= k) { for (int i = 0; i < sz; i++) { if (i == 0) { ans += pos[target].size(); } else { ans += pos[target + cum[i - 1]].end() - lower_bound(pos[target + cum[i - 1]].begin(), pos[target + cum[i - 1]].end(), i); } } if ((k == 1) || (k == -1 && target == k)) { cout << ans << endl; return 0; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> const long long int mod = 1e9 + 7; using namespace std; bool prime(long long int n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long int i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } bool isPowerOfTwo(long long int n) { if (n == 0) return false; return (ceil(log2(n)) == floor(log2(n))); } void SieveOfEratosthenes(long long int n) { bool prime[n + 1]; memset(prime, true, sizeof(prime)); for (long long int p = 2; p * p <= n; p++) { if (prime[p] == true) { for (long long int i = p * p; i <= n; i += p) prime[i] = false; } } for (long long int p = 2; p <= n; p++) if (prime[p]) cout << p << ; } long long int modularinv(long long int x, long long int n) { if (n == 0) return 1; else if (n % 2 == 0) return modularinv((x * x) % mod, n / 2); else return (x * modularinv((x * x) % mod, (n - 1) / 2)) % mod; } class node { public: long long int first; bool operator<(const node& rhs) const { return first > rhs.first; } }; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long int n, i; cin >> n; vector<long long int> v(n); long long int sum = 0; for (i = 0; i < n; i++) { cin >> v[i]; sum += v[i]; } long long int count = 0; long long int d; if (sum % 2 != 0) sum = sum / 2 + 1; else sum = sum / 2; for (i = 0; i < n; i++) { count += v[i]; if (count >= sum) { d = i + 1; break; } } cout << d; } |
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; bool IsPowerOfTwo(long long int x) { return (x != 0) && ((x & (x - 1)) == 0); } long long int poer(long long int a, long long int b) { long long int rs = 1; while (b > 0) { if (b & 1) rs *= a; a *= a; b /= 2; } return rs; } long long int mod_poer(long long int a, long long int b, long long int mo) { long long int rs = 1; while (b > 0) { if (b & 1) rs = (rs * a) % mo; a = (a * a) % mo; b /= 2; } return rs % mo; } long long int d, x, y; void ext_euclid(long long int a, long long int b) { if (b == 0) { d = a; x = 1; y = 0; } else { ext_euclid(b, a % b); long long int temp = x; x = y; y = temp - (a / b) * y; } } long long int mod_inverse1(long long int a, long long int m) { ext_euclid(a, m); return (x % m + m) % m; } long long int mod_inverse2(long long int a, long long int m) { return mod_poer(a, m - 2, m); } long long int gcd(long long int a, long long int b) { if (b == 0) return a; else return gcd(b, a % b); } long long int fact[200005]; void fac() { fact[1] = fact[0] = 1; for (long long int i = 2; i <= 200005; ++i) { fact[i] = ((fact[i - 1] % mod) * i) % mod; } } long long int combi(long long int a, long long int b) { if (b > a) return 0; if (b == a) return 1; else { long long int x = mod_poer(fact[b], mod - 2, mod) % mod; long long int y = mod_poer(fact[a - b], mod - 2, mod) % mod; return ((((fact[a]) * x) % mod) * y) % mod; } } long long int len[54]; string str1 = What are you doing while sending ; string str2 = ? Are you busy? Will you send ; string str3 = ? ; long long int len1 = str1.size(); long long int len2 = str2.size(); long long int len3 = str3.size(); string f0 = What are you doing at the end of the world? Are you busy? Will you save us? ; char get(long long int n, long long int k) { if (n > 54) { if (k <= len1) return str1[k - 1]; return get(n - 1, k - len1); } if (n < 54 && k > len[n]) return . ; if (n == 0) return f0[k - 1]; if (k <= len1) return str1[k - 1]; if (k <= len1 + len[n - 1]) return get(n - 1, k - len1); if (k <= len1 + len[n - 1] + len2) return str2[k - len1 - len[n - 1] - 1]; if (k <= len1 + len[n - 1] * 2 + len2) return get(n - 1, k - len1 - len[n - 1] - len2); return str3[k - len1 - len[n - 1] * 2 - len2 - 1]; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); len[0] = f0.size(); for (long long int i = 1; i < 54; ++i) { len[i] = (len[i - 1] * 2) + len1 + len2 + len3; } long long int t; cin >> t; while (t--) { long long int n, k; cin >> n >> k; cout << get(n, k); } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mx = 2e5 + 10; const int mxb = 60; long long int a[mx], b[mx], c[mx]; int cnt[mxb][2]; int bat(int idx, long long int v) { if (v & (1ll << idx)) return 1; return 0; } int main() { int n; scanf( %d , &n); long long int sm = 0; for (int i = 0; i < n; i++) scanf( %lld , b + i); for (int i = 0; i < n; i++) scanf( %lld , c + i), sm += b[i] + c[i]; sm /= n + n; for (int i = 0; i < n; i++) { a[i] = (b[i] + c[i] - sm) / n; if (a[i] < 0) { puts( -1 ); return 0; } for (int j = 0; j < mxb; j++) cnt[j][bat(j, a[i])]++; } for (int i = 0; i < n; i++) { long long int bi = 0, ci = 0; int cb = 0, cc = 0; for (int j = 0; j < mxb; j++) { int db = cb, dc = cc; for (int x = 0; x < 2; x++) { db += cnt[j][x] * (bat(j, a[i]) & x); dc += cnt[j][x] * (bat(j, a[i]) | x); } cb = db / 2, cc = dc / 2; if (db & 1) bi |= (1ll << j); if (dc & 1) ci |= (1ll << j); } if (bi != b[i] || ci != c[i]) { puts( -1 ); return 0; } } for (int i = 0; i < n; i++) printf( %lld , a[i]); puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a; if (a == 1) { cout << 1 ; return 0; } if (a == 2) { cout << 13 ; return 0; } long long sol = 1; sol += 1LL * 6 * a * (a + 1) / 2; sol += 1LL * 6 * ((a - 2) * (a - 1) / 2 - 1); cout << sol << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYMETAL6S6S_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DLYMETAL6S6S_BEHAVIORAL_PP_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__dlymetal6s6s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYMETAL6S6S_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; bool neg = false; for (int i = 1; i <= n / 4 && !neg; i++) { for (int k = 0; k <= n - 1 - 4 * i; k++) if (s[k] == * && s[k + i] == * && s[k + 2 * i] == * && s[k + 3 * i] == * && s[k + 4 * i] == * ) neg = true; } if (neg) cout << yes ; else cout << no ; return 0; } |
module enc(rst_n, freq_clk, enable, pha, phb, home, index, led);
input rst_n;
input freq_clk;
input enable;
output pha;
output phb;
output home;
output index;
output led;
reg pha_reg;
reg phb_reg;
reg home_reg;
reg index_reg;
reg[7:0] pha_count;
//debug led
reg led;
// generate 100 Hz from 50 MHz
reg [31:0] count_reg;
reg out_200hz;
always @(posedge freq_clk or negedge rst_n) begin
if (!rst_n) begin
count_reg <= 0;
out_200hz <= 0;
count_reg <= 0;
out_200hz <= 0;
end
else if (enable)
begin
if (count_reg < 124999) begin
count_reg <= count_reg + 1;
end else begin
count_reg <= 0;
out_200hz <= ~out_200hz;
end
end
end
/*
we will be generating waveform like below
_ _
pha | |_| |_
_ _
phb _| |_| |_
_
home <every 12 clock of pha> _| |_
_
index <every 12 clock of pha> _| |_
*/
/* process the pha_count*/
always @ (posedge out_200hz or negedge rst_n)
begin
if (!rst_n)
begin
pha_count <= 8'd0;
led <= 1'b0;
end
else if (out_200hz)
begin
led <= ~led;
if(pha_count>8'd24)
pha_count <= 8'd0;
else
pha_count <= pha_count + 8'd1;
end
end
reg[1:0] Phase90_Count;
/*process the pha signal*/
always @ (posedge out_200hz or negedge rst_n)
begin
if (!rst_n)
begin
Phase90_Count <= 2'b0;
end
else if (out_200hz)
begin
case (Phase90_Count)
2'd0:
begin
pha_reg <= 1'd1;
Phase90_Count <= Phase90_Count + 2'd1;
end
2'd1:
begin
phb_reg <= 1'd1;
Phase90_Count <= Phase90_Count + 2'd1;
end
2'd2:
begin
pha_reg <= 1'd0;
Phase90_Count <= Phase90_Count + 2'd1;
end
2'd3:
begin
phb_reg <= 1'd0;
Phase90_Count <= 2'd0;
end
endcase
end
end
assign pha = pha_reg;
assign phb = phb_reg;
/*process the home signal*/
always @ (posedge out_200hz or negedge rst_n)
begin
if (!rst_n)
begin
home_reg <= 1'b0;
end
else if (out_200hz)
begin
case (pha_count)
8'd23: home_reg <= 1'd1;
8'd24: home_reg <= 1'd1;
default: home_reg <= 1'd0;
endcase
end
end
assign home = home_reg;
/*process the index signal*/
always @ (posedge out_200hz or negedge rst_n)
begin
if (!rst_n)
begin
index_reg <= 1'b0;
end
else if (out_200hz)
begin
case (pha_count)
8'd23: index_reg <= 1'd1;
8'd24: index_reg <= 1'd1;
default: index_reg <= 1'd0;
endcase
end
end
assign index = index_reg;
endmodule |
#include <bits/stdc++.h> using namespace std; string a[100]; int id[30]; vector<int> cn[30]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 1; i < n; i++) { char l1 = - ; char l2 = - ; int j = -1; int s = a[i - 1].size(); if (a[i - 1].size() > a[i].size()) { s = a[i].size(); if (a[i] == string(a[i - 1].substr(0, s))) id[0]++; } while (++j < s) { if (a[i - 1][j] == a[i][j]) continue; l1 = a[i - 1][j]; l2 = a[i][j]; break; } if (l1 != - ) { cn[l1 - a ].push_back(l2 - a ); id[l2 - a ]++; } } queue<int> ts; for (int i = 0; i < 26; i++) if (!id[i]) ts.push(i); string anw = ; while (!ts.empty()) { int u = ts.front(); ts.pop(); anw += char(u + a ); for (auto v : cn[u]) { id[v]--; if (!id[v]) ts.push(v); } } cout << (anw.size() == 26 ? anw : Impossible ) << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAP_SYMBOL_V
`define SKY130_FD_SC_LP__TAP_SYMBOL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAP_SYMBOL_V
|
`include "core.h"
`default_nettype none
module execute_forwarding(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Writeback - General Register
input wire iWB_GR_VALID,
input wire [31:0] iWB_GR_DATA,
input wire [4:0] iWB_GR_DEST,
input wire iWB_GR_DEST_SYSREG,
//Writeback - Stack Point Register
input wire iWB_SPR_VALID,
input wire [31:0] iWB_SPR_DATA,
//Writeback - FRCR
input wire iWR_FRCR_VALID,
input wire [63:0] iWR_FRCR_DATA,
//Previous Writeback - General Register
input wire iPREV_WB_GR_VALID,
input wire [31:0] iPREV_WB_GR_DATA,
input wire [4:0] iPREV_WB_GR_DEST,
input wire iPREV_WB_GR_DEST_SYSREG,
//Previous Writeback - Stack Point Register
input wire iPREV_WB_SPR_VALID,
input wire [31:0] iPREV_WB_SPR_DATA,
//Previous Writeback - FRCR
input wire iPREV_WB_FRCR_VALID,
input wire [63:0] iPREV_WB_FRCR_DATA,
//Source
input wire iPREVIOUS_SOURCE_SYSREG,
input wire [4:0] iPREVIOUS_SOURCE_POINTER,
input wire iPREVIOUS_SOURCE_IMM,
input wire [31:0] iPREVIOUS_SOURCE_DATA,
input wire [31:0] iPREVIOUS_SOURCE_PDTR,
input wire [31:0] iPREVIOUS_SOURCE_KPDTR,
input wire [31:0] iPREVIOUS_SOURCE_TIDR,
input wire [31:0] iPREVIOUS_SOURCE_PSR,
//Output
output wire [31:0] oNEXT_SOURCE_DATA,
output wire [31:0] oNEXT_SOURCE_SPR,
output wire [31:0] oNEXT_SOURCE_PDTR,
output wire [31:0] oNEXT_SOURCE_KPDTR,
output wire [31:0] oNEXT_SOURCE_TIDR,
output wire [31:0] oNEXT_SOURCE_PSR
);
/************************************************************************
Fowarding Function
************************************************************************/
function [31:0] func_forwarding_rewrite;
input func_src_settle; //No forwarding
input [4:0] func_src_pointer;
input func_src_sysreg;
input [31:0] func_src_data;
//Previous
input func_prev_valid;
input func_prev_sysreg;
input func_prev_spr_writeback;
input func_prev_frcr_writeback;
input [4:0] func_prev_dest_pointer;
//input [31:0] func_prev_pcr;
input [31:0] func_prev_spr;
input [63:0] func_prev_frcr;
input [31:0] func_prev_gr_data;
begin
//Forwarding Valid
if(func_prev_valid && !func_src_settle)begin
//SPR Forwarding
//Source Sysreg -> Valid, Source Pointer -> SPR, Previous Data -> Valid, Previous SPR Writeback -> Valid
if(func_src_sysreg && func_src_pointer == `SYSREG_SPR && (func_prev_spr_writeback || func_prev_dest_pointer == `SYSREG_SPR))begin
func_forwarding_rewrite = func_prev_spr;
end
//FRCLR Forwarding
else if(func_src_sysreg && func_src_pointer == `SYSREG_FRCLR && func_prev_dest_pointer == `SYSREG_FRCR2FRCXR)begin
func_forwarding_rewrite = func_prev_frcr[31:0];
end
//FRCHR Forwarding
else if(func_src_sysreg && func_src_pointer == `SYSREG_FRCHR && func_prev_dest_pointer == `SYSREG_FRCR2FRCXR)begin
func_forwarding_rewrite = func_prev_frcr[63:32];
end
//General Register Fowerding
else if(!func_src_sysreg && !func_prev_sysreg && func_src_pointer == func_prev_dest_pointer)begin
func_forwarding_rewrite = func_prev_gr_data;
end
//No Forwarding
else begin
func_forwarding_rewrite = func_src_data;
end
end
//No Forwarding
else begin
func_forwarding_rewrite = func_src_data;
end
end
endfunction
function [31:0] func_forwarding_reqrite_spr;
input [31:0] func_prev_data;
input func_cuur_valid;
input [31:0] func_cuur_data;
begin
if(func_cuur_valid)begin
func_forwarding_reqrite_spr = func_cuur_data;
end
else begin
func_forwarding_reqrite_spr = func_prev_data;
end
end
endfunction
function [31:0] func_forwarding_rewrite_sysreg;
input [4:0] func_target_sysreg;
//Current
input [31:0] func_src_data;
//Previous
input func_prev_valid;
input func_prev_sysreg;
input [4:0] func_prev_dest_pointer;
input [31:0] func_prev_data;
begin
//Forwarding Valid
if(func_prev_valid && func_prev_sysreg && func_prev_dest_pointer == func_target_sysreg)begin
//Forwarding
func_forwarding_rewrite_sysreg = func_prev_data;
end
//No Forwarding
else begin
func_forwarding_rewrite_sysreg = func_src_data;
end
end
endfunction
/************************************************************************
Assign
************************************************************************/
//GR
wire [31:0] prev_forwarding_data = func_forwarding_rewrite(
iPREVIOUS_SOURCE_IMM,
iPREVIOUS_SOURCE_POINTER,
iPREVIOUS_SOURCE_SYSREG,
iPREVIOUS_SOURCE_DATA,
iPREV_WB_GR_VALID,
iPREV_WB_GR_DEST_SYSREG,
iPREV_WB_SPR_VALID,
iPREV_WB_FRCR_VALID,
iPREV_WB_GR_DEST,
iPREV_WB_SPR_DATA,
iPREV_WB_FRCR_DATA,
iPREV_WB_GR_DATA
);
wire [31:0] cuur_forwarding_data = func_forwarding_rewrite(
iPREVIOUS_SOURCE_IMM,
iPREVIOUS_SOURCE_POINTER,
iPREVIOUS_SOURCE_SYSREG,
prev_forwarding_data,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_SPR_VALID,
iWR_FRCR_VALID,
iWB_GR_DEST,
iWB_SPR_DATA,
iWR_FRCR_DATA,
iWB_GR_DATA
);
//SPR
wire [31:0] cuur_forwarding_spr = func_forwarding_reqrite_spr(
iPREV_WB_SPR_DATA,
iWB_SPR_VALID,
iWB_SPR_DATA
);
//PDTR
wire [31:0] prev_forwarding_pdtr = func_forwarding_rewrite_sysreg(
`SYSREG_PDTR,
iPREVIOUS_SOURCE_PDTR,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
wire [31:0] cuur_forwarding_pdtr = func_forwarding_rewrite_sysreg(
`SYSREG_PDTR,
prev_forwarding_pdtr,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
//KPDTR
wire [31:0] prev_forwarding_kpdtr = func_forwarding_rewrite_sysreg(
`SYSREG_KPDTR,
iPREVIOUS_SOURCE_KPDTR,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
wire [31:0] cuur_forwarding_kpdtr = func_forwarding_rewrite_sysreg(
`SYSREG_KPDTR,
prev_forwarding_kpdtr,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
//TIDR
wire [31:0] prev_forwarding_tidr = func_forwarding_rewrite_sysreg(
`SYSREG_TIDR,
iPREVIOUS_SOURCE_TIDR,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
wire [31:0] cuur_forwarding_tidr = func_forwarding_rewrite_sysreg(
`SYSREG_TIDR,
prev_forwarding_tidr,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
//PSR
wire [31:0] prev_forwarding_psr = func_forwarding_rewrite_sysreg(
`SYSREG_PSR,
iPREVIOUS_SOURCE_PSR,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
wire [31:0] cuur_forwarding_psr = func_forwarding_rewrite_sysreg(
`SYSREG_PSR,
prev_forwarding_psr,
iWB_GR_VALID,
iWB_GR_DEST_SYSREG,
iWB_GR_DEST,
iWB_GR_DATA
);
assign oNEXT_SOURCE_DATA = cuur_forwarding_data;
assign oNEXT_SOURCE_SPR = cuur_forwarding_spr;
assign oNEXT_SOURCE_PDTR = cuur_forwarding_pdtr;
assign oNEXT_SOURCE_KPDTR = cuur_forwarding_kpdtr;
assign oNEXT_SOURCE_TIDR = cuur_forwarding_tidr;
assign oNEXT_SOURCE_PSR = cuur_forwarding_psr;
endmodule
`default_nettype wire
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc_iobuf4(
input [3:0] T,
input [3:0] I,
output [3:0] O,
inout [3:0] IO
);
IOBUF iobuf0(
.T(T[0]),
.I(I[0]),
.O(O[0]),
.IO(IO[0])
);
IOBUF iobuf1(
.T(T[1]),
.I(I[1]),
.O(O[1]),
.IO(IO[1])
);
IOBUF iobuf2(
.T(T[2]),
.I(I[2]),
.O(O[2]),
.IO(IO[2])
);
IOBUF iobuf3(
.T(T[3]),
.I(I[3]),
.O(O[3]),
.IO(IO[3])
);
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_intr_rd_mem.v
*
* Date : 2012-11
*
* Description : Mimics interconnect for Reads between AFI and DDRC/OCM
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_intr_rd_mem(
sw_clk,
rstn,
full,
empty,
req,
invalid_rd_req,
rd_info,
RD_DATA_OCM,
RD_DATA_DDR,
RD_DATA_VALID_OCM,
RD_DATA_VALID_DDR
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input sw_clk, rstn;
output full, empty;
input RD_DATA_VALID_DDR, RD_DATA_VALID_OCM;
input [max_burst_bits-1:0] RD_DATA_DDR, RD_DATA_OCM;
input req, invalid_rd_req;
input [rd_info_bits-1:0] rd_info;
reg [intr_cnt_width-1:0] wr_ptr = 0, rd_ptr = 0;
reg [rd_afi_fifo_bits-1:0] rd_fifo [0:intr_max_outstanding-1]; // Data, addr, size, burst, len, RID, RRESP, valid bytes
wire full, empty;
assign empty = (wr_ptr === rd_ptr)?1'b1: 1'b0;
assign full = ((wr_ptr[intr_cnt_width-1]!== rd_ptr[intr_cnt_width-1]) && (wr_ptr[intr_cnt_width-2:0] === rd_ptr[intr_cnt_width-2:0]))?1'b1 :1'b0;
/* read from the fifo */
task read_mem;
output [rd_afi_fifo_bits-1:0] data;
begin
data = rd_fifo[rd_ptr[intr_cnt_width-1:0]];
if(rd_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
rd_ptr[intr_cnt_width-2:0] = 0;
else
rd_ptr = rd_ptr + 1;
end
endtask
reg state;
reg invalid_rd;
/* write in the fifo */
always@(negedge rstn or posedge sw_clk)
begin
if(!rstn) begin
wr_ptr = 0;
rd_ptr = 0;
state = 0;
invalid_rd = 0;
end else begin
case (state)
0 : begin
state = 0;
invalid_rd = 0;
if(req)begin
state = 1;
invalid_rd = invalid_rd_req;
end
end
1 : begin
state = 1;
if(RD_DATA_VALID_OCM | RD_DATA_VALID_DDR | invalid_rd) begin
if(RD_DATA_VALID_DDR)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_DDR,rd_info};
else if(RD_DATA_VALID_OCM)
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = {RD_DATA_OCM,rd_info};
else
rd_fifo[wr_ptr[intr_cnt_width-2:0]] = rd_info;
if(wr_ptr[intr_cnt_width-2:0] === intr_max_outstanding-1)
wr_ptr[intr_cnt_width-2:0] = 0;
else
wr_ptr = wr_ptr + 1;
state = 0;
invalid_rd = 0;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long b, deocoai, g, n, p, q, i, a[300], t, tong, z, a1, a2, k2, k1; cin >> b >> g >> n; if (min(b, g) >= n) { cout << n + 1; return 0; } if (max(b, g) >= n && min(b, g) <= n) { cout << min(b, g) + 1; return 0; } cout << b + g - n + 1; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S6S_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DLYMETAL6S6S_BEHAVIORAL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlymetal6s6s (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S6S_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int M = 1e6 + 10; struct node { int l, r, sum, mus; } tr[M]; int n, a[M], now[M], sz[M], place[M], q, p; vector<int> g[M]; void maket(int l, int r, int t) { tr[t].l = l; tr[t].r = r; if (l == r) { tr[t].sum += now[a[l]]; return; } maket(l, (l + r) / 2, 2 * t); maket((l + r) / 2 + 1, r, 2 * t + 1); tr[t].sum = tr[2 * t].sum + tr[2 * t + 1].sum; } void change(int l, int r, int t) { if (tr[t].l == l && tr[t].r == r) { tr[t].sum = r - l + 1 - tr[t].sum; tr[t].mus ^= 1; return; } if (tr[t].mus) { change(tr[2 * t].l, tr[2 * t].r, 2 * t); change(tr[2 * t + 1].l, tr[2 * t + 1].r, 2 * t + 1); tr[t].mus = 0; } if (r <= tr[2 * t].r) change(l, r, 2 * t); else if (l >= tr[2 * t + 1].l) change(l, r, 2 * t + 1); else { change(l, tr[2 * t].r, 2 * t); change(tr[2 * t + 1].l, r, 2 * t + 1); } tr[t].sum = tr[2 * t].sum + tr[2 * t + 1].sum; } int query(int l, int r, int t) { if (tr[t].l == l && tr[t].r == r) return tr[t].sum; if (tr[t].mus) { change(tr[2 * t].l, tr[2 * t].r, 2 * t); change(tr[2 * t + 1].l, tr[2 * t + 1].r, 2 * t + 1); tr[t].mus = 0; } if (r <= tr[2 * t].r) return query(l, r, 2 * t); else if (l >= tr[2 * t + 1].l) return query(l, r, 2 * t + 1); else return query(l, tr[2 * t].r, 2 * t) + query(tr[2 * t + 1].l, r, 2 * t + 1); tr[t].sum = tr[2 * t].sum + tr[2 * t + 1].sum; } void dfs(int v) { a[++p] = v; place[v] = p; sz[v] = 1; for (int i = 0; i < g[v].size(); i++) { dfs(g[v][i]); sz[v] += sz[g[v][i]]; } } int main() { cin >> n; for (int i = 2; i <= n; i++) { int x; scanf( %d , &x); g[x].push_back(i); } for (int i = 1; i <= n; i++) scanf( %d , now + i); dfs(1); maket(1, n, 1); cin >> q; while (q--) { string s; cin >> s; int v; scanf( %d , &v); if (s == get ) printf( %d n , query(place[v], place[v] + sz[v] - 1, 1)); else change(place[v], place[v] + sz[v] - 1, 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; int i = k - 1; while (n % i != 0) { i--; } cout << n / i * k + i << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O31A_FUNCTIONAL_PP_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31A_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int i, j, n, m, flag = 0, cnt = 0, temp; cin >> n >> m; char a[108][106]; for (i = 0; i < n; i++) { cin >> a[i]; } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { cnt = 0; if (a[i][j] == . ) { if (a[i - 1][j] == * || a[i - 1][j - 1] == * || a[i][j - 1] == * || a[i + 1][j] == * || a[i][j + 1] == * || a[i + 1][j + 1] == * || a[i - 1][j + 1] == * || a[i + 1][j - 1] == * ) flag = 1; } else if (a[i][j] == * ) continue; else { if (a[i - 1][j] == * ) cnt++; if (a[i - 1][j - 1] == * ) cnt++; if (a[i][j - 1] == * ) cnt++; if (a[i + 1][j] == * ) cnt++; if (a[i + 1][j + 1] == * ) cnt++; if (a[i][j + 1] == * ) cnt++; if (a[i - 1][j + 1] == * ) cnt++; if (a[i + 1][j - 1] == * ) cnt++; temp = (int)(a[i][j] - 0 ); if (cnt != temp) flag = 1; } } } if (flag == 1) cout << NO ; else cout << YES ; } |
#include <bits/stdc++.h> using namespace std; void solve() { long long x, y, ans; cin >> x >> y; ans = (x / 2) * y; if (x % 2) ans += y / 2; cout << ans; } int32_t main() { ios_base::sync_with_stdio(false); long long t = 1; while (t--) { solve(); } return 0; } |
//Verilint 182 off // WARNING: Illegal statement for synthesis: $realtobits (in1)
//Verilint 311 off // WARNING: Converting real to unsigned: $realtobits (in1)
//Verilint 20 off // WARNING: Assign statement may not be synthesizable: assign out7[i] = ...;
//Verilint 599 off // WARNING: This construct is not supported by Synopsys
//Verilint 433 off // WARNING: More than one top level module
//Verilint 71 off // WARNING: Case statement without default clause
module testmodule (/*AUTOARG*/
// Outputs
out1, out2, out3, out4, out5, out7, out8, outb2, outb3, outb4, outb6, outb7, outb8, outb9,
outb10, outw1, outw2, outw3,
// Inputs
in1, in2, in3, in4, in5
);
function [2:0] ffs;
input [2:0] in;
ffs = in & 3'b010;
endfunction
task show;
input [2:0] in;
begin
$display ("Hi %x", in);
end
endtask
input [2:0] in1,in2,in3,in4,in5;
output [2:0] out1, out2,out3,out4,out5,out7,out8;
output outb2,outb3,outb4,outb6,outb7,outb8,outb9,outb10;
output [7:0] outw1,outw2,outw3;
reg [2:0] memarry [0:2];
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [2:0] out1;
reg [2:0] out2;
reg [2:0] out3;
reg [2:0] out4;
reg [2:0] out5;
reg [2:0] out8;
reg outb2;
reg outb3;
reg outb4;
reg outb6;
reg outb7;
reg [7:0] outw1;
reg [7:0] outw2;
reg [7:0] outw3;
// End of automatics
wire outb8=1'b1, outb9=|{in1[0],in2[0]}, outb10=1'b0;
always @(/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
:ignore_label
out1 = $realtobits(in1);
out2 = ffs(in1 | (in2) );
out3 = ffs /*check*/ (in2);
$display ("chk ", in1);
show (in4);
if (|in3) out4=1; else out4=0;
end
always @ (/*AUTOSENSE*/in1 or in2 or in3 or in5) begin
casex ({in5[1:0], (3'b010==in2)})
3'bx_1_0: out5=3'b000;
3'bx_1_1: out5=3'b010;
3'bx_0_x: out5=3'b100;
endcase
casex ({in3[in1]})
1'bx: out5=3'b000;
endcase
end
/*AUTO_CONSTANT (`temp) */
`define temp 3'b010
always @(/*AUTOSENSE*/in3) begin
outb6 = (in3 == `temp);
end
integer i;
reg [2:0] out7;
always @ (/*AUTOSENSE*/in1) begin
for (i=0; i<3; i=i+1) begin
assign out7[i] = ~in1[i];
end
end
always @ (/*AUTOSENSE*/in1 or in2 or in3) begin
{outw1 [ffs(in1)], outw2 [ffs(in2)]} = 2'b10;
{outw3[(|in1)?in2:in3], outb2} = 2'b10;
end
initial memarry[0] = in2;
always @ (/*AUTOSENSE*/ /*memory or*/ in1) begin
$display (memarry[in1]);
end
always @(/*AUTOSENSE*/in1 or in2)
casex(in1[1:0]) // synopsys full_case parallel_case
2'b01 : out8 = 3'b001;
2'b10 : out8 = 3'b010;
default
out8 = in2;
endcase
parameter READ = 3'b111,
//WRITE = 3'b111,
CFG = 3'b010;
//supply1 one;
always @(/*AUTOSENSE*/in1 or in2) begin
outb7 = (in1==READ) || (in2==CFG);
end
always @(/*AUTOSENSE*/in1) begin
if (|in1) $display("We're at %t\n",$time);
end // case: default
`define shift_instr 5'b01011
always @(/*AUTOSENSE*/in1 or in2 or in3 or in4 or in5 or outw1)
/*AUTO_CONSTANT(`shift_instr)*/
begin: label_no_sense
casex (outw1) // synopsys full_case parallel_case
{`shift_instr,3'bxxx}:
outb3 = in3[0];
8'b00001x10: outb3 = in4[0];
8'b00110011:
if (in5[0])
outb3 = in1[0];
else
outb3 = in2[1];
default
outb3 = in4[0];
endcase
end
parameter WIDLE = 0; // No Manual Write Burst
always @ (/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
case(1'b1)
in2[WIDLE]:
outb4 = in1[0];
in3[in4]:
outb4 = in1[0];
default:
outb4 = 1'bx;
endcase
end
endmodule
module darren_jones_2 (/*AUTOARG*/
// Outputs
next_WSTATE,
// Inputs
WSTATE
);
input [1:0] WSTATE;
output [1:0] next_WSTATE;
reg [1:0] next_WSTATE;
parameter
WIDLE = 0, // No Manual Write Burst
WCB0 = 1; // 1st of the 4 Manual Write Burst
always @ (/*AUTOSENSE*/WSTATE) begin
next_WSTATE = 2'b0;
case (1'b1)
WSTATE[WIDLE]:
next_WSTATE[1'b0] = 1'b1;
WSTATE[WCB0]:
next_WSTATE[WCB0] = 1'b1;
endcase
end
endmodule
module darren_jones_3 (/*AUTOARG*/
// Outputs
var1,
// Inputs
state
);
input [2:1] state;
output var1;
reg var1;
parameter
IDLE = 1,
CAS1 = 2;
always @(/*AUTOSENSE*/state) begin
case (1'b1)
state[IDLE] : begin
var1 = 1'b1;
end
state[CAS1] : begin
var1 = 1'b1;
end
default : begin
var1 = 1'b1;
end
endcase
end
always @(/*AUTOSENSE*/add or lo or mc_32pff or mc_losel or slo or var1) begin
case(mc_losel)
6'b000001: lo_mux = mc_32pff ? {add[39:0],lo[31:8]} :
{add[7:0],lo[63:8]};
6'b010000: lo_mux = lo;
6'b100000: lo_mux = var1 ? IDLE : slo;
endcase
end // always @ (...
endmodule
|
//=============================================================
//
// Copyright (c) 2017 Simon Southwell. All rights reserved.
//
// Date: 10th June 2017
//
// This code is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// The code is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this code. If not, see <http://www.gnu.org/licenses/>.
//
// $Id: uart_drv.v,v 1.2 2017/06/29 14:26:58 simon Exp $
// $Source: /home/simon/CVS/src/cpu/mico32/HDL/test/verilog/uart_drv.v,v $
//
//=============================================================
//
// Simple UART driver.
//
//=============================================================
`include "test_defs.vh"
module uart_drv (clk, nreset, rx, tx,
rxdata, rxrdy, rxerr,
txdata, txrdy, txack);
//-------------------------------------------------------------
// Parameters
//-------------------------------------------------------------
// User overridable parameters
parameter clk_period_ns = `CLKPERIOD50/`NANOSECOND;
parameter baud_rate = `TEST_BAUDRATE;
parameter stop_bits = 1;
parameter data_bits = 8;
parameter parity_bit = 0;
parameter parity_odd = 0;
// Derived parameters
parameter clks_per_bit = (`MILLISECOND/clk_period_ns)/baud_rate;
//-------------------------------------------------------------
// Port declarations
//-------------------------------------------------------------
input clk;
input nreset;
input rx;
output tx;
input [7:0] txdata;
input txrdy;
output txack;
output [7:0] rxdata;
output rxrdy;
output rxerr;
//-------------------------------------------------------------
// Internal state
//-------------------------------------------------------------
reg [7:0] rxdata;
reg rxrdy;
reg txack;
reg txack_last;
reg [7:0] rx_shift;
reg last_rx;
reg rxerr;
reg last_txrdy;
reg [7:0] txdata_reg;
reg txdata_par_reg;
reg [3:0] txidx;
reg [3:0] rx_bit_count;
integer rx_dly_count;
reg [3:0] tx_bit_count;
integer tx_dly_count;
//-------------------------------------------------------------
// Combinatorial logic
//-------------------------------------------------------------
// RX shift register is LSB first
wire [7:0] next_rx_shift = {rx, rx_shift[7:1]};
// Create appropriate wide tx data with start bit (1'b0), data, optional parity
// and stop bits, right justified to index from 0 to n (LSB first). Blanks are
// filled with 1'b1 for stop bit(s).
wire [11:0] tx_data = {2'b11, parity_bit ? {txdata_par_reg, txdata_reg} : {1'b1, txdata_reg}, 1'b0};
// TX output is as per index into tx_data
assign tx = tx_data[txidx];
//-------------------------------------------------------------
// Receiver logic
//-------------------------------------------------------------
always @(posedge clk or negedge nreset)
begin
if (nreset == 1'b0)
begin
rx_bit_count <= 4'h0;
rx_dly_count <= 4'h0;
last_rx <= 1'b1;
rxrdy <= 1'b0;
rxerr <= 1'b0;
end
else
begin
rxrdy <= 1'b0;
last_rx <= rx;
rx_dly_count <= rx_dly_count - ((rx_dly_count != 4'h0) ? 1 : 0);
// Start bit detected
if (rx == 1'b0 && last_rx == 1'b1 && rx_bit_count == 4'h0 && rx_dly_count == 4'h0)
begin
// Set the bit counter to count data all bits, including parity.
rx_bit_count <= data_bits + parity_bit;
// First delay count if for half of the period
rx_dly_count <= clks_per_bit + clks_per_bit/2;
end
// If the delay count is at the end of the count...
if (rx_dly_count == 4'h1)
begin
// If the bits still to be processed...
if (rx_bit_count != 0)
begin
// Decrement the bit count for this bit
rx_bit_count <= rx_bit_count - 4'h1;
// Reset the bit delay for a whole bit period, plus 1 to compensate
// for the delay count being at 1 now, rather than 0.
rx_dly_count <= clks_per_bit + 1;
// Sample the RX data and shift in.
rx_shift <= next_rx_shift;
// When at the last data bit, display the received character
if (rx_bit_count == parity_bit+1)
begin
rxrdy <= 1'b1;
rxdata <= next_rx_shift;
end
// If a parity bit, and at the last bit, check the parity
if (parity_bit == 1 && rx_bit_count == 4'h1)
begin
if (^rx_shift[7:0] != (parity_odd ? 1'b1 : 1'b0))
begin
$display("UART: ***ERROR parity failed");
rxerr <= 1'b1;
end
end
end
end
end
end
//-------------------------------------------------------------
// Transmission logic
//-------------------------------------------------------------
always @(posedge clk or negedge nreset)
begin
if (nreset == 1'b0)
begin
txack <= 1'b0;
txack_last <= 1'b0;
tx_bit_count <= 4'h0;
tx_dly_count <= 4'h0;
txidx <= 4'd11; // Point to top stop bit by default.
end
else
begin
last_txrdy <= txrdy;
txack <= 1'b0;
txack_last <= txack;
tx_dly_count <= tx_dly_count - ((tx_dly_count != 0) ? 1 : 0);
// Start of transmission (txrdy goes from 0 to 1, or acknowledged last cycle
// and txrdy active, for back to back transmissions.
if ((txrdy == 1'b1 && last_txrdy == 1'b0) || (txrdy == 1'b1 && txack_last == 1'b1))
begin
txdata_reg <= txdata;
txdata_par_reg <= (^txdata) ^ (parity_odd ? 1'b0 : 1'b1);
tx_bit_count <= 1 + data_bits + parity_bit + stop_bits;
tx_dly_count <= clks_per_bit;
txidx <= 0;
end
// Active transmission
if (tx_bit_count != 4'h0 && tx_dly_count == 4'h1)
begin
tx_bit_count <= tx_bit_count - 4'h1;
txidx <= txidx + 4'h1;
tx_dly_count <= clks_per_bit;
end
// Last cycle of transmission
if (tx_bit_count == 4'h1 && tx_dly_count == 1)
begin
txack <= 1'b1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[3]; int main() { scanf( %I64d%I64d%I64d , &a[0], &a[1], &a[2]); long long ans = a[0] + a[1] + a[2]; for (int i = 0; i <= 2; i++) { long long A = a[i], B = a[(i + 1) % 3]; if (((A - B) < 0 ? -(A - B) : (A - B)) & 1) continue; ans = ((ans) < (((A) > (B) ? (A) : (B))) ? (ans) : (((A) > (B) ? (A) : (B)))); } printf( %I64d n , ans); return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: afifo_32x256.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module afifo_32x256 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull,
wrusedw);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [31:0] sub_wire1;
wire sub_wire2;
wire [7:0] sub_wire3;
wire wrfull = sub_wire0;
wire [31:0] q = sub_wire1[31:0];
wire rdempty = sub_wire2;
wire [7:0] wrusedw = sub_wire3[7:0];
dcfifo dcfifo_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.wrusedw (sub_wire3),
.rdfull (),
.rdusedw (),
.wrempty ());
defparam
dcfifo_component.intended_device_family = "Arria II GX",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL "wrusedw[7..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL afifo_32x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL afifo_32x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL afifo_32x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL afifo_32x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL afifo_32x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL afifo_32x256_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the on board periphal devices *
* on the DE2-35 board. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_de2_35 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
parameter VID_INPUT_CONTROL = 16'h0040;
parameter VID_CHROMA_GAIN_1 = 16'h2df4;
parameter VID_CHROMA_GAIN_2 = 16'h2e00;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [26: 0] audio_rom_data;
wire [26: 0] video_rom_data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = audio_rom_data | video_rom_data;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_av_config_auto_init_ob_audio Auto_Init_Audio_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (audio_rom_data)
);
defparam
Auto_Init_Audio_ROM.AUD_LINE_IN_LC = AUD_LINE_IN_LC,
Auto_Init_Audio_ROM.AUD_LINE_IN_RC = AUD_LINE_IN_RC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_LC = AUD_LINE_OUT_LC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_RC = AUD_LINE_OUT_RC,
Auto_Init_Audio_ROM.AUD_ADC_PATH = AUD_ADC_PATH,
Auto_Init_Audio_ROM.AUD_DAC_PATH = AUD_DAC_PATH,
Auto_Init_Audio_ROM.AUD_POWER = AUD_POWER,
Auto_Init_Audio_ROM.AUD_DATA_FORMAT = AUD_DATA_FORMAT,
Auto_Init_Audio_ROM.AUD_SAMPLE_CTRL = AUD_SAMPLE_CTRL,
Auto_Init_Audio_ROM.AUD_SET_ACTIVE = AUD_SET_ACTIVE;
altera_up_av_config_auto_init_ob_adv7181 Auto_Init_Video_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (video_rom_data)
);
defparam
Auto_Init_Video_ROM.INPUT_CONTROL = VID_INPUT_CONTROL,
Auto_Init_Video_ROM.CHROMA_GAIN_1 = VID_CHROMA_GAIN_1,
Auto_Init_Video_ROM.CHROMA_GAIN_2 = VID_CHROMA_GAIN_2;
endmodule
|
#include <bits/stdc++.h> using namespace std; int M[17], R[17], n, sum; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> M[i]; for (int i = 1; i <= n; i++) cin >> R[i]; for (int i = 1; i <= 720719; i++) for (int j = 1; j <= n; j++) { if (i % M[j] == R[j]) { sum++; break; } } double ans = 1.0 * sum / 720720; printf( %.6lf , ans); } |
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
// Basic DFF
module \$_DFF_P_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
// Async reset
module \$_DFF_PP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
// Async set
module \$_DFF_PP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
// Async reset, enable
module \$_DFFE_PP0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));
endmodule
// Async set, enable
module \$_DFFE_PP1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffse _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(S));
endmodule
// Async set & reset
module \$_DFFSR_PPP_ (D, C, R, S, Q);
input D;
input C;
input R;
input S;
output Q;
dffsr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(S));
endmodule
// Async set, reset & enable
module \$_DFFSRE_PPPP_ (D, Q, C, E, R, S);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
endmodule
// Latch with async set and reset
module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q);
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(R), .S(S));
endmodule
// The following techmap operation are not performed right now
// as Negative edge FF are not legalized in synth_quicklogic for qlf_k6n10
// but in case we implement clock inversion in the future, the support is ready for it.
module \$_DFF_N_ (D, C, Q);
input D;
input C;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dff #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
endmodule
module \$_DFF_NP0_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
endmodule
module \$_DFF_NP1_ (D, C, R, Q);
input D;
input C;
input R;
output Q;
dffs #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
endmodule
module \$_DFFE_NP0P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffre #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .R(R));
endmodule
module \$_DFFE_NP1P_ (D, C, E, R, Q);
input D;
input C;
input E;
input R;
output Q;
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
dffse #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .E(E), .S(S));
endmodule
module \$_DFFSR_NPP_ (D, C, R, S, Q);
input D;
input C;
input R;
input S;
output Q;
dffsr #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R), .S(S));
endmodule
module \$_DFFSRE_PPPP_ (D, C, E, R, S, Q);
input D;
input C;
input E;
input R;
input S;
output Q;
dffsre #(.IS_C_INVERTED(1'b1)) _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGSBP_1_V
`define SKY130_FD_SC_LP__SREGSBP_1_V
/**
* sregsbp: ????.
*
* Verilog wrapper for sregsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sregsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sregsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sregsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.ASYNC(ASYNC),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sregsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sregsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.ASYNC(ASYNC)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGSBP_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 100005; int a[N], n, i, k, j, c, p, b[N], m, r, t, check, mr; struct tree { int data = 0; int rank = 1; } * ROOT[N], *f[N]; vector<int> leafs; void push(tree*& node, int number) { tree* child = new tree(); child->data = number; child->rank = node->rank + 1; f[number] = child; if (leafs.size()) { for (int it = leafs.size() - 1; it >= 0; it--) { if (leafs[it] == node->data) { leafs.erase(leafs.begin() + it); break; } } } leafs.push_back(number); c = max(c, child->rank); }; int main() { cin >> n; for (i = 0; i < n; i++) cin >> a[i]; for (i = 0; i < n; i++) { if (a[i] > m) { j++; ROOT[j] = new tree(); ROOT[j]->data = a[i]; m = a[i]; if (leafs.size()) leafs.clear(); continue; } if (a[i] > a[i - 1]) { if (!leafs.size()) { push(ROOT[j], a[i]); continue; } else { r = 0; mr = 0; check = 0; for (int it = leafs.size() - 1; it >= 0; it--) { if (f[leafs[it]]->rank < r) leafs.erase(leafs.begin() + it); if (mr <= f[leafs[it]]->rank) { if (leafs[it] < a[i]) { if (f[leafs[it]]->rank > r) { r = f[leafs[it]]->rank; t = leafs[it]; check = 1; } } } mr = max(mr, f[leafs[it]]->rank); } if (check) push(f[t], a[i]); else push(ROOT[j], a[i]); } } else { c = max(c, 1); } } if (c) cout << c; else cout << 0; } |
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_10g
*/
module test_eth_mac_10g_32;
// Parameters
parameter DATA_WIDTH = 32;
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter CTRL_WIDTH = (DATA_WIDTH/8);
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_PTP_TS_ENABLE = 0;
parameter TX_PTP_TS_WIDTH = 96;
parameter TX_PTP_TAG_ENABLE = TX_PTP_TS_ENABLE;
parameter TX_PTP_TAG_WIDTH = 16;
parameter RX_PTP_TS_ENABLE = 0;
parameter RX_PTP_TS_WIDTH = 96;
parameter TX_USER_WIDTH = (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1;
parameter RX_USER_WIDTH = (RX_PTP_TS_ENABLE ? RX_PTP_TS_WIDTH : 0) + 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg [DATA_WIDTH-1:0] tx_axis_tdata = 0;
reg [KEEP_WIDTH-1:0] tx_axis_tkeep = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg [TX_USER_WIDTH-1:0] tx_axis_tuser = 0;
reg [DATA_WIDTH-1:0] xgmii_rxd = 0;
reg [CTRL_WIDTH-1:0] xgmii_rxc = 0;
reg [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts = 0;
reg [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire tx_axis_tready;
wire [DATA_WIDTH-1:0] rx_axis_tdata;
wire [KEEP_WIDTH-1:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire [RX_USER_WIDTH-1:0] rx_axis_tuser;
wire [DATA_WIDTH-1:0] xgmii_txd;
wire [CTRL_WIDTH-1:0] xgmii_txc;
wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts;
wire [TX_PTP_TAG_WIDTH-1:0] tx_axis_ptp_ts_tag;
wire tx_axis_ptp_ts_valid;
wire [1:0] tx_start_packet;
wire tx_error_underflow;
wire [1:0] rx_start_packet;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
tx_axis_tdata,
tx_axis_tkeep,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
xgmii_rxd,
xgmii_rxc,
tx_ptp_ts,
rx_ptp_ts,
ifg_delay
);
$to_myhdl(
tx_axis_tready,
rx_axis_tdata,
rx_axis_tkeep,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
xgmii_txd,
xgmii_txc,
tx_axis_ptp_ts,
tx_axis_ptp_ts_tag,
tx_axis_ptp_ts_valid,
tx_start_packet,
tx_error_underflow,
rx_start_packet,
rx_error_bad_frame,
rx_error_bad_fcs
);
// dump file
$dumpfile("test_eth_mac_10g_32.lxt");
$dumpvars(0, test_eth_mac_10g_32);
end
eth_mac_10g #(
.DATA_WIDTH(DATA_WIDTH),
.KEEP_WIDTH(KEEP_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.TX_PTP_TS_WIDTH(TX_PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.TX_PTP_TAG_WIDTH(TX_PTP_TAG_WIDTH),
.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.RX_PTP_TS_WIDTH(RX_PTP_TS_WIDTH),
.TX_USER_WIDTH(TX_USER_WIDTH),
.RX_USER_WIDTH(RX_USER_WIDTH)
)
UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.tx_ptp_ts(tx_ptp_ts),
.rx_ptp_ts(rx_ptp_ts),
.tx_axis_ptp_ts(tx_axis_ptp_ts),
.tx_axis_ptp_ts_tag(tx_axis_ptp_ts_tag),
.tx_axis_ptp_ts_valid(tx_axis_ptp_ts_valid),
.tx_start_packet(tx_start_packet),
.tx_error_underflow(tx_error_underflow),
.rx_start_packet(rx_start_packet),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
package Pkg;
class Cls;
int c_no = 2;
//automatic int c_au = 2; // automatic not a legal keyword here
static int c_st = 22;
function int f_c_no ();
++c_no; return c_no;
endfunction
function int f_c_st ();
++c_st; return c_st;
endfunction
static function int f_cs_st ();
++c_st; return c_st;
endfunction
endclass
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
Pkg::Cls a = new;
Pkg::Cls b = new;
int v;
initial begin
v = a.f_c_no(); `checkh(v, 3);
v = a.f_c_no(); `checkh(v, 4);
v = b.f_c_no(); `checkh(v, 3);
v = b.f_c_no(); `checkh(v, 4);
v = a.f_c_st(); `checkh(v, 23);
v = a.f_c_st(); `checkh(v, 24);
v = b.f_c_st(); `checkh(v, 25);
v = b.f_c_st(); `checkh(v, 26);
//
v = Pkg::Cls::f_cs_st(); `checkh(v, 27);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0); cout.tie(0); iostream::sync_with_stdio(false); long long n, m; cin >> n >> m; set<int> taken_lines, taken_cols; long long base = n * n; for (int i = 0; i < m; ++i) { int x, y; cin >> x >> y; bool lined = false, coled = false; if (taken_lines.count(x) == 0) lined = true; if (taken_cols.count(y) == 0) coled = true; if (lined) { base -= n - taken_cols.size(); } if (coled) { base -= n - taken_lines.size(); } if (lined && coled) { base++; } taken_lines.insert(x); taken_cols.insert(y); cout << base << ; } cout << n ; } |
#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 10; const long long inf = 1e18; long long n; long long arr[20]; bool flag = false; void rec(long long i, long long s) { if (i == n + 1 && s % 360 == 0) flag = true; if (i > n) return; rec(i + 1, s + arr[i]); rec(i + 1, s - arr[i]); } int32_t main() { cin >> n; for (long long i = 1; i <= n; i++) cin >> arr[i]; rec(1, 0); if (flag) cout << YES ; else cout << NO ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_BLACKBOX_V
`define SKY130_FD_SC_HVL__BUF_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__buf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off BLKANDNBLK
// verilator lint_off COMBDLY
// verilator lint_off LATCH
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
// verilator lint_off MULTIDRIVEN
reg [31:0] runnerm1, runner; initial runner = 0;
reg [31:0] runcount; initial runcount = 0;
reg [31:0] clkrun; initial clkrun = 0;
reg [31:0] clkcount; initial clkcount = 0;
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
reg run0;
always @ (/*AS*/runnerm1) begin
if ((runner & 32'hf)!=0) begin
runcount = runcount + 1;
runner = runnerm1;
$write(" seq runcount=%0d runner =%0x\n", runcount, runnerm1);
end
run0 = (runner[8:4]!=0 && runner[3:0]==0);
end
always @ (posedge run0) begin
// Do something that forces another combo run
clkcount <= clkcount + 1;
runner[8:4] <= runner[8:4] - 1;
runner[3:0] <= 3;
$write ("[%0t] posedge runner=%0x\n", $time, runner);
end
reg [7:0] cyc; initial cyc = 0;
always @ (posedge clk) begin
$write("[%0t] %x counts %0x %0x\n", $time, cyc, runcount, clkcount);
cyc <= cyc + 8'd1;
case (cyc)
8'd00: begin
runner <= 0;
end
8'd01: begin
runner <= 32'h35;
end
default: ;
endcase
case (cyc)
8'd02: begin
if (runcount!=32'he) $stop;
if (clkcount!=32'h3) $stop;
end
8'd03: begin
$write("*-* All Finished *-*\n");
$finish;
end
default: ;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPMET1_2_V
`define SKY130_FD_SC_MS__TAPMET1_2_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog wrapper for tapmet1 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__tapmet1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tapmet1_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__tapmet1 base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__tapmet1_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__tapmet1 base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPMET1_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/07 13:20:30
// Design Name:
// Module Name: _3bit_binary_multiplier_control_unit
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module binary_multiplier_control_unit
(
input start,
input clk,
input cnt_done,
input lsb,
output start_process,
output reg add,
output reg shift,
output reg count_up,
output reg done
// ,output state
);
reg [2:0] state, nextState;
parameter off = 0, on = 1, process = 2, finish = 3;
assign start_process = start;
initial begin
state = off;
end
// update state
always @(posedge clk) begin
state <= nextState;
end
//compute mealy output and state
always @(start or lsb or cnt_done or state) begin
add = 0;
case (state)
off: begin
if (start) nextState = on;
else nextState = off;
end
on: begin
if (lsb) begin
nextState = process;
add = 1;
end
else begin
nextState = process;
end
end
process: begin
if (cnt_done) nextState = finish;
else nextState = on;
end
finish: begin
nextState = off;
end
default: begin
nextState = off;
end
endcase
end
// compute Moore output
always @(state) begin
shift = 0;
count_up = 0;
done = 0;
case (state)
process: begin
shift = 1;
count_up = 1;
end
finish: begin
done = 1;
end
default: begin
shift = 0;
count_up = 0;
done = 0;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxk = 101, maxn = 100000 + 10; long long n, k, a[maxk], dp[maxk][maxn]; long long f(int x, long long num) { if (num == 0) return 0; if (x == k + 1) return num; if (num < maxn && dp[x][num] != -1) return dp[x][num]; long long p = f(x + 1, num) - f(x + 1, num / a[x]); if (num < maxn) return dp[x][num] = p; return p; } bool cmp(int x, int y) { return y < x; } int main() { memset(dp, -1, sizeof dp); cin >> n >> k; for (int i = 1; i <= k; i++) cin >> a[i]; sort(a + 1, a + 1 + k, cmp); cout << f(1, n) << endl; return 0; } |
#define DEBUG 0 #include <bits/stdc++.h> using namespace std; #if DEBUG // basic debugging macros int __i__,__j__; #define printLine(l) for(__i__=0;__i__<l;__i__++){cout<< - ;}cout<<endl #define printLine2(l,c) for(__i__=0;__i__<l;__i__++){cout<<c;}cout<<endl #define printVar(n) cout<<#n<< : <<n<<endl #define printArr(a,l) cout<<#a<< : ;for(__i__=0;__i__<l;__i__++){cout<<a[__i__]<< ;}cout<<endl #define print2dArr(a,r,c) cout<<#a<< : n ;for(__i__=0;__i__<r;__i__++){for(__j__=0;__j__<c;__j__++){cout<<a[__i__][__j__]<< ;}cout<<endl;} #define print2dArr2(a,r,c,l) cout<<#a<< : n ;for(__i__=0;__i__<r;__i__++){for(__j__=0;__j__<c;__j__++){cout<<setw(l)<<setfill( )<<a[__i__][__j__]<< ;}cout<<endl;} // advanced debugging class // debug 1,2, A , test ; class _Debug { public: template<typename T> _Debug& operator,(T val) { cout << val << endl; return *this; } }; #define debug _Debug(), #else #define printLine(l) #define printLine2(l,c) #define printVar(n) #define printArr(a,l) #define print2dArr(a,r,c) #define print2dArr2(a,r,c,l) #define debug #endif // define #define MAX_VAL 999999999 #define MAX_VAL_2 999999999999999999LL #define EPS 1e-6 #define mp make_pair #define pb push_back // typedef typedef unsigned int UI; typedef long long int LLI; typedef unsigned long long int ULLI; typedef unsigned short int US; typedef pair<int,int> pii; typedef pair<LLI,LLI> plli; typedef vector<int> vi; typedef vector<LLI> vlli; typedef vector<pii> vpii; typedef vector<plli> vplli; // ---------- END OF TEMPLATE ---------- #define MOD 1000000007 int modPow(int b,int e) { int r = 1; while (e > 0) { if (e & 1) r = ((LLI) r*b) % MOD; e >>= 1; b = ((LLI) b*b) % MOD; } return r; } int fact[41],C[41][41],ways[40]; int p[40],v[40],occ[41],occ2[41]; int dp[1000000]; int main() { int i; int n; scanf( %d ,&n); for (i = 0; i < n; i++) scanf( %d ,&p[i]),p[i]--; int j,k; fact[0] = 1; for (i = 1; i <= n; i++) fact[i] = ((LLI) i*fact[i-1]) % MOD; for (i = 0; i <= n; i++) { C[i][0] = 1; for (j = 1; j <= i; j++) C[i][j] = (C[i-1][j-1]+C[i-1][j]) % MOD; } for (i = 0; i < n; i++) { for (j = 0; j <= i; j++) { ways[i] += ((((LLI) C[i][j]*fact[j]) % MOD)*fact[n-j-1]) % MOD; ways[i] %= MOD; } } for (i = 0; i < n; i++) { if (!v[i]) { int u = i,c = 0; while (!v[u]) v[u] = 1,u = p[u],c++; occ[c]++; } } int s = 1; for (i = 1; i <= n; i++) s *= occ[i]+1; dp[0] = 1; for (i = 1; i < s; i++) { int t = i,s2 = 1,sum = 0; for (j = 1; j <= n; j++) { occ2[j] = t % (occ[j]+1),s2 *= occ2[j]+1,sum += occ2[j]*j; t /= occ[j]+1; } for (j = 1; j < s2; j++) { int t2 = j,sum2 = 0,num = 0,j2 = 0,pp = 1; LLI c = 1; for (k = 1; k <= n; k++) { int occ3 = t2 % (occ2[k]+1); c *= C[occ2[k]][occ3],c %= MOD,num += occ3,sum2 += occ3*k; j2 += (occ2[k]-occ3)*pp; t2 /= occ2[k]+1,pp *= occ[k]+1; } if (!(num & 1)) c = MOD-c; c *= dp[j2],c %= MOD; dp[i] += (c*modPow(ways[sum-sum2],sum2)) % MOD,dp[i] %= MOD; } } printf( %d n ,dp[s-1]); return 0; } |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.3 (lin64) Build Fri Oct 3 16:31:15 MDT 2014
// Date : Sun Oct 25 15:43:51 2015
// Host : arthas-ubuntu running 64-bit Ubuntu 14.04.3 LTS
// Command : write_verilog -force -mode synth_stub /home/arthas/git/SHD/SHD.srcs/sources_1/ip/shd_fifo/shd_fifo_stub.v
// Design : shd_fifo
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.3" *)
module shd_fifo(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[255:0],wr_en,rd_en,dout[255:0],full,empty" */;
input rst;
input wr_clk;
input rd_clk;
input [255:0]din;
input wr_en;
input rd_en;
output [255:0]dout;
output full;
output empty;
endmodule
|
`timescale 1ns / 1ps
// ////////////////////////////////////////////////////////////////////////////////
// Boot CPLD design, only for u2_rev2
// ////////////////////////////////////////////////////////////////////////////////
module boot_cpld
(input CLK_25MHZ,
output CLK_25MHZ_EN,
output [2:0] LED,
output [8:0] DEBUG,
input POR,
// To SD Card
output SD_nCS,
output SD_Din,
output SD_CLK,
input SD_Dout,
input SD_DAT1, // Unused
input SD_DAT2, // Unused
input SD_prot, // Write Protect
input SD_det, // Card Detect
// To FPGA Config Interface
input CFG_INIT_B,
output CFG_Din, // Also used in Data interface
output CFG_CCLK,
input CFG_DONE,
output CFG_PROG_B,
// To FPGA data interface
output CPLD_CLK,
input START,
input MODE,
input DONE,
output detached,
input CPLD_misc // Unused for now
);
assign CLK_25MHZ_EN = 1'b1;
assign LED[0] = ~CFG_DONE;
assign LED[1] = CFG_INIT_B;
assign LED[2] = ~CFG_PROG_B;
wire en_outs;
wire [3:0] set_sel = 4'd0;
assign CPLD_CLK = CFG_CCLK;
assign DEBUG[8:0] = { CLK_25MHZ, SD_nCS, SD_CLK, SD_Din, SD_Dout,
START, MODE, DONE, CPLD_misc};
// Handle cutover to FPGA control of SD
wire fpga_takeover = ~CPLD_misc;
wire SD_CLK_int, SD_nCS_int, SD_Din_int, CFG_Din_int;
assign SD_CLK = fpga_takeover ? START : SD_CLK_int;
assign SD_nCS = fpga_takeover ? MODE : SD_nCS_int;
assign SD_Din = fpga_takeover ? DONE : SD_Din_int;
assign CFG_Din = fpga_takeover ? SD_Dout : CFG_Din_int;
spi_boot #(.width_set_sel_g(4), // How many sets (16)
.width_bit_cnt_g(6), // Block length (12 is faster, 6 is minimum)
.width_img_cnt_g(2), // How many images per set
.num_bits_per_img_g(20), // Image size, 20 = 1MB
.sd_init_g(1), // SD-specific initialization
.mmc_compat_clk_div_g(0),// No MMC support
.width_mmc_clk_div_g(0), // No MMC support
.reset_level_g(0)) // Active low reset
spi_boot(.clk_i(CLK_25MHZ),
.reset_i(POR),
// To SD Card
.spi_clk_o(SD_CLK_int),
.spi_cs_n_o(SD_nCS_int),
.spi_data_in_i(SD_Dout),
.spi_data_out_o(SD_Din_int),
.spi_en_outs_o(en_outs),
// Data Port
.start_i(START),
.mode_i(MODE), // 0->conf mode, 1->data mode
.detached_o(detached),
.dat_done_i(DONE),
.set_sel_i(set_sel),
// To FPGA
.config_n_o(CFG_PROG_B),
.cfg_init_n_i(CFG_INIT_B),
.cfg_done_i(CFG_DONE),
.cfg_clk_o(CFG_CCLK),
.cfg_dat_o(CFG_Din_int)
);
endmodule // boot_cpld
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4_BLACKBOX_V
`define SKY130_FD_SC_HD__OR4_BLACKBOX_V
/**
* or4: 4-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename T1> T amax(T& a, T1 b) { if (b > a) a = b; return a; } template <typename T, typename T1> T amin(T& a, T1 b) { if (b < a) a = b; return a; } const long long N = 200005, INF = 2000000000000000000; const long long SIX = 1000000; bool prime(long long n) { long long i = 0; for (i = 2; i * i <= n; i++) { if (n % i == 0) { return false; } } return true; } void solve() { long long n, k; cin >> n >> k; string s; cin >> s; long long i = 0; long long ans = 0; if (n == 1 && k != 0) { cout << 0 ; return; } for (i = 0; i < n; i++) { if (i == 0 && ans < k) { if (s[i] != 1 ) { s[i] = 1 ; ans++; } } else if (i > 0 && ans < k) { if (s[i] != 0 ) { s[i] = 0 ; ans++; } } } cout << s << n ; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(NULL); long long t; t = 1; while (t--) solve(); } |
#include<bits/stdc++.h> using namespace std; typedef long long ll; typedef unsigned long long ull; typedef unsigned int uint; typedef pair<int, int> pii; int n, k; char s[300005]; void solve() { while (~scanf( %d%d , &n, &k)) { memset(s, 0, sizeof(s)); s[n + 1] = 0 ; int top = 0; s[++top] = a ; for (int i = 1; i <= k; ++i) { char cur = a + i - 1; s[++top] = cur; for (int j = k; j >= i + 1; --j) { char tcur = a + j - 1; s[++top] = tcur; if (j != i + 1) s[++top] = cur; } } for (int i = k - 1; i >= 1; --i) { char cur = a + i - 1; s[++top] = cur; } // puts(s + 1); int len = top; int sumlen = len; while (top <= n) { for (int i = 2; i <= len; ++i) s[++top] = s[i]; } s[n + 1] = 0 ; puts(s + 1); } } int main() { int T = 1; // scanf( %d , &T); for (int i = 1; i <= T; ++i) { // printf( Case #%d: , i); solve(); } } |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_solo_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2011 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Input Buffer
// /___/ /\ Filename : IBUF_INTERMDISABLE.v
// \ \ / \ Timestamp : Wed Apr 20 17:49:56 PDT 2011
// \___\/\___\
//
// Revision:
// 04/20/11 - Initial version.
// 06/15/11 - CR 613347 -- made ouput logic_1 when IBUFDISABLE is active
// 08/31/11 - CR 623170 -- added attribute USE_IBUFDISABLE
// 09/20/11 - CR 624774, 625725 -- Removed attributes IBUF_DELAY_VALUE, IFD_DELAY_VALUE and CAPACITANCE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUF_INTERMDISABLE (O, I, IBUFDISABLE, INTERMDISABLE);
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
parameter SIM_DEVICE = "7SERIES";
parameter USE_IBUFDISABLE = "TRUE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
output O;
input I;
input IBUFDISABLE;
input INTERMDISABLE;
// define constants
localparam MODULE_NAME = "IBUF_INTERMDISABLE";
wire out_val;
initial begin
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF_INTERMDISABLE instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
#1 $finish;
end
endcase
if ((SIM_DEVICE != "7SERIES") &&
(SIM_DEVICE != "ULTRASCALE") &&
(SIM_DEVICE != "VERSAL_AI_CORE") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_EDGE") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE != "VERSAL_AI_RF") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE != "VERSAL_HBM") &&
(SIM_DEVICE != "VERSAL_HBM_ES1") &&
(SIM_DEVICE != "VERSAL_HBM_ES2") &&
(SIM_DEVICE != "VERSAL_PREMIUM") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE != "VERSAL_PRIME") &&
(SIM_DEVICE != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE != "VERSAL_PRIME_ES2")) begin
$display("Error: [Unisim %s-103] SIM_DEVICE attribute is set to %s. Legal values for this attribute are 7SERIES, ULTRASCALE, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE);
#1 $finish;
end
end
generate
case (SIM_DEVICE)
"7SERIES" : begin
assign out_val = 1'b1;
end
default : begin
assign out_val = 1'b0;
end
endcase
endgenerate
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign O = (IBUFDISABLE == 0)? I : (IBUFDISABLE == 1)? out_val : 1'bx;
end
"FALSE" : begin
assign O = I;
end
endcase
endgenerate
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
#include<bits/stdc++.h> using namespace std; const int N=10,M=405,mod=998244353; int n,m,k,t,v[M],id[M][M],ch[M][30],l[N]; char s[N][N]; struct mat{int a[M][M];}; mat operator*(mat x,mat y) { mat z; for(int i=1;i<=t;i++) { for(int j=1;j<=t;j++) { z.a[i][j]=0; for(int k=1;k<=t;k++) z.a[i][j]=(z.a[i][j]+1ll*x.a[i][k]*y.a[k][j]%mod)%mod; } } return z; } mat qp(mat a,int b) { mat ans=a; b--; while(b) { if(b&1) ans=ans*a; a=a*a; b>>=1; } return ans; } mat tr; int sol(int x,int y) { if(x>y) swap(x,y); if(id[x][y]) return id[x][y]; int u=++t; id[x][y]=u; for(int i=0;i<26;i++) { if(ch[x][i]&&ch[y][i]) { int nx1=ch[x][i],nx2=ch[y][i]; tr.a[u][sol(nx1,nx2)]++; if(v[nx1]) tr.a[u][sol(1,nx2)]++; if(v[nx2]) tr.a[u][sol(nx1,1)]++; if(v[nx1]&&v[nx2]) tr.a[u][sol(1,1)]++; } } return u; } int main() { scanf( %d%d ,&n,&m); k=1; for(int i=1;i<=n;i++) { scanf( %s ,s[i]+1),l[i]=strlen(s[i]+1); int u=1; for(int j=1;j<=l[i];j++) { int x=s[i][j]- a ; if(!ch[u][x]) ch[u][x]=++k; u=ch[u][x]; } v[u]=1; } memset(tr.a,0,sizeof(tr.a)); int b=sol(1,1); tr=qp(tr,m); printf( %d n ,tr.a[b][b]); return 0; } |
#include <bits/stdc++.h> using namespace std; char s[10][10]; int t, i, j, o, x[2], y[2], ok; int main() { scanf( %d , &t); while (t--) { for (i = o = 0; i < 8; i++) { scanf( %s , s + i); for (j = 0; j < 8; j++) if (s[i][j] == K ) x[o] = i, y[o++] = j; } if (abs(x[0] - x[1]) % 4 || abs(y[0] - y[1]) % 4) puts( NO ); else puts( YES ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int a[n]; map<int, int> mp; for (int i = 0; i < n; i++) { cin >> a[i]; mp[a[i]]++; } int mx = 0, p = 0; for (auto it = mp.begin(); it != mp.end(); it++) { mx = max(mx, it->second); p++; } cout << max(min(mx, p - 1), min(mx - 1, p)) << endl; } return 0; } |
/////////////////////////////////////////////////////////////////////
//// ////
//// Universal FIFO Dual Clock, gray encoded ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// D/L from: http://www.opencores.org/cores/generic_fifos/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: generic_fifo_dc_gray.v,v 1.2 2004-01-13 09:11:55 rudi Exp $
//
// $Date: 2004-01-13 09:11:55 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1 2003/10/14 09:34:41 rudi
// Dual clock FIFO Gray Code encoded version.
//
//
//
//
//
//`include "timescale.v"
/*
Description
===========
I/Os
----
rd_clk Read Port Clock
wr_clk Write Port Clock
rst low active, either sync. or async. master reset (see below how to select)
clr synchronous clear (just like reset but always synchronous), high active
re read enable, synchronous, high active
we read enable, synchronous, high active
din Data Input
dout Data Output
full Indicates the FIFO is full (driven at the rising edge of wr_clk)
empty Indicates the FIFO is empty (driven at the rising edge of rd_clk)
wr_level indicates the FIFO level:
2'b00 0-25% full
2'b01 25-50% full
2'b10 50-75% full
2'b11 %75-100% full
rd_level indicates the FIFO level:
2'b00 0-25% empty
2'b01 25-50% empty
2'b10 50-75% empty
2'b11 %75-100% empty
Status Timing
-------------
All status outputs are registered. They are asserted immediately
as the full/empty condition occurs, however, there is a 2 cycle
delay before they are de-asserted once the condition is not true
anymore.
Parameters
----------
The FIFO takes 2 parameters:
dw Data bus width
aw Address bus width (Determines the FIFO size by evaluating 2^aw)
Synthesis Results
-----------------
In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 97 LUTs and runs
at about 113 MHz (IO insertion disabled).
Misc
----
This design assumes you will do appropriate status checking externally.
IMPORTANT ! writing while the FIFO is full or reading while the FIFO is
empty will place the FIFO in an undefined state.
*/
module generic_fifo_dc_gray( rd_clk, wr_clk, rst, clr, din, we,
dout, re, full, empty, wr_level, rd_level );
parameter dw=16;
parameter aw=8;
input rd_clk, wr_clk, rst, clr;
input [dw-1:0] din;
input we;
output [dw-1:0] dout;
input re;
output full;
output empty;
output [1:0] wr_level;
output [1:0] rd_level;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [aw:0] wp_bin, wp_gray;
reg [aw:0] rp_bin, rp_gray;
reg [aw:0] wp_s, rp_s;
reg full, empty;
wire [aw:0] wp_bin_next, wp_gray_next;
wire [aw:0] rp_bin_next, rp_gray_next;
wire [aw:0] wp_bin_x, rp_bin_x;
reg [aw-1:0] d1, d2;
reg rd_rst, wr_rst;
reg rd_rst_r, wr_rst_r;
reg rd_clr, wr_clr;
reg rd_clr_r, wr_clr_r;
////////////////////////////////////////////////////////////////////
//
// Reset Logic
//
always @(posedge rd_clk or negedge rst)
if(!rst) rd_rst <= 1'b0;
else
if(rd_rst_r) rd_rst <= 1'b1; // Release Reset
always @(posedge rd_clk or negedge rst)
if(!rst) rd_rst_r <= 1'b0;
else rd_rst_r <= 1'b1;
always @(posedge wr_clk or negedge rst)
if(!rst) wr_rst <= 1'b0;
else
if(wr_rst_r) wr_rst <= 1'b1; // Release Reset
always @(posedge wr_clk or negedge rst)
if(!rst) wr_rst_r <= 1'b0;
else wr_rst_r <= 1'b1;
always @(posedge rd_clk or posedge clr)
if(clr) rd_clr <= 1'b1;
else
if(!rd_clr_r) rd_clr <= 1'b0; // Release Clear
always @(posedge rd_clk or posedge clr)
if(clr) rd_clr_r <= 1'b1;
else rd_clr_r <= 1'b0;
always @(posedge wr_clk or posedge clr)
if(clr) wr_clr <= 1'b1;
else
if(!wr_clr_r) wr_clr <= 1'b0; // Release Clear
always @(posedge wr_clk or posedge clr)
if(clr) wr_clr_r <= 1'b1;
else wr_clr_r <= 1'b0;
////////////////////////////////////////////////////////////////////
//
// Memory Block
//
generic_dpram #(aw,dw) u0(
.rclk( rd_clk ),
.rrst( !rd_rst ),
.rce( 1'b1 ),
.oe( 1'b1 ),
.raddr( rp_bin[aw-1:0] ),
.do( dout ),
.wclk( wr_clk ),
.wrst( !wr_rst ),
.wce( 1'b1 ),
.we( we ),
.waddr( wp_bin[aw-1:0] ),
.di( din )
);
////////////////////////////////////////////////////////////////////
//
// Read/Write Pointers Logic
//
always @(posedge wr_clk)
if(!wr_rst) wp_bin <= {aw+1{1'b0}};
else
if(wr_clr) wp_bin <= {aw+1{1'b0}};
else
if(we) wp_bin <= wp_bin_next;
always @(posedge wr_clk)
if(!wr_rst) wp_gray <= {aw+1{1'b0}};
else
if(wr_clr) wp_gray <= {aw+1{1'b0}};
else
if(we) wp_gray <= wp_gray_next;
assign wp_bin_next = wp_bin + {{aw{1'b0}},1'b1};
assign wp_gray_next = wp_bin_next ^ {1'b0, wp_bin_next[aw:1]};
always @(posedge rd_clk)
if(!rd_rst) rp_bin <= {aw+1{1'b0}};
else
if(rd_clr) rp_bin <= {aw+1{1'b0}};
else
if(re) rp_bin <= rp_bin_next;
always @(posedge rd_clk)
if(!rd_rst) rp_gray <= {aw+1{1'b0}};
else
if(rd_clr) rp_gray <= {aw+1{1'b0}};
else
if(re) rp_gray <= rp_gray_next;
assign rp_bin_next = rp_bin + {{aw{1'b0}},1'b1};
assign rp_gray_next = rp_bin_next ^ {1'b0, rp_bin_next[aw:1]};
////////////////////////////////////////////////////////////////////
//
// Synchronization Logic
//
// write pointer
always @(posedge rd_clk) wp_s <= wp_gray;
// read pointer
always @(posedge wr_clk) rp_s <= rp_gray;
////////////////////////////////////////////////////////////////////
//
// Registered Full & Empty Flags
//
assign wp_bin_x = wp_s ^ {1'b0, wp_bin_x[aw:1]}; // convert gray to binary
assign rp_bin_x = rp_s ^ {1'b0, rp_bin_x[aw:1]}; // convert gray to binary
always @(posedge rd_clk)
empty <= (wp_s == rp_gray) | (re & (wp_s == rp_gray_next));
always @(posedge wr_clk)
full <= ((wp_bin[aw-1:0] == rp_bin_x[aw-1:0]) & (wp_bin[aw] != rp_bin_x[aw])) |
(we & (wp_bin_next[aw-1:0] == rp_bin_x[aw-1:0]) & (wp_bin_next[aw] != rp_bin_x[aw]));
////////////////////////////////////////////////////////////////////
//
// Registered Level Indicators
//
reg [1:0] wr_level;
reg [1:0] rd_level;
reg [aw-1:0] wp_bin_xr, rp_bin_xr;
reg full_rc;
reg full_wc;
always @(posedge wr_clk) full_wc <= full;
always @(posedge wr_clk) rp_bin_xr <= ~rp_bin_x[aw-1:0] + {{aw-1{1'b0}}, 1'b1};
always @(posedge wr_clk) d1 <= wp_bin[aw-1:0] + rp_bin_xr[aw-1:0];
always @(posedge wr_clk) wr_level <= {d1[aw-1] | full | full_wc, d1[aw-2] | full | full_wc};
always @(posedge rd_clk) wp_bin_xr <= ~wp_bin_x[aw-1:0];
always @(posedge rd_clk) d2 <= rp_bin[aw-1:0] + wp_bin_xr[aw-1:0];
always @(posedge rd_clk) full_rc <= full;
always @(posedge rd_clk) rd_level <= full_rc ? 2'h0 : {d2[aw-1] | empty, d2[aw-2] | empty};
////////////////////////////////////////////////////////////////////
//
// Sanity Check
//
// synopsys translate_off
//always @(posedge wr_clk)
// if(we && full)
// $display("%m WARNING: Writing while fifo is FULL (%t)",$time);
//always @(posedge rd_clk)
// if(re && empty)
// $display("%m WARNING: Reading while fifo is EMPTY (%t)",$time);
// synopsys translate_on
endmodule
|
// date:2016/2/19 11:00 done!
// engineer:ZhaiShaoMin
// module name:arbiter_4_enq
// module function:decide which fifo should receive coming flit according to the head flit of msg
// since arbiter dequeue has done most of the selction work , this part seems much easier!
module arbiter_4_enq ( // input
flit,
ctrl,
en_dest_fifo,
dest_fifo,
// output
flit2pass_req, // seled flit output to pass req
ctrl2pass_req, // seled ctrl output to pass req
flit2pass_rep, // seled flit output to pass rep
ctrl2pass_rep, // seled ctrl output to pass rep
flit2local_in_req, // seled flit output to local in req
ctrl2local_in_req, // seled ctrl output to local in req
flit2local_in_rep, // seled flit output to local in rep
ctrl2local_in_rep, // seled ctrl output to local in rep
en_pass_req,
en_pass_rep,
en_local_in_req,
en_local_in_rep
);
//INPUT
input [15:0] flit;
input [1:0] ctrl;
input en_dest_fifo; // enable selection between 4 fifos
input [1:0] dest_fifo;// used to decide write flit to pass fifos or In_local fifos
// 00:write to pass req fifo; 01:write to pass rep fifo;
// 10:write to IN_local req fifo; 11:write to IN_local rep fifo;
//output
//output [1:0] enq_select; // 00:enq for pass fifo req;
// 01:enq for pass fifo rep; 10:enq for local fifo req;
// 11:enq for local fifo rep.
output [15:0] flit2pass_req; // seled flit output to pass req
output [1:0] ctrl2pass_req; // seled ctrl output to pass req
output [15:0] flit2pass_rep; // seled flit output to pass req
output [1:0] ctrl2pass_rep; // seled ctrl output to pass req
output [15:0] flit2local_in_req; // seled flit output to pass req
output [1:0] ctrl2local_in_req; // seled ctrl output to pass req
output [15:0] flit2local_in_rep; // seled flit output to pass req
output [1:0] ctrl2local_in_rep; // seled ctrl output to pass req
output en_pass_req; // enable for pass req fifo to write data to tail
output en_pass_rep; // enable for pass rep fifo to write data to tail
output en_local_in_req; // enable for local in req fifo to write data to tail
output en_local_in_rep; // enable for local in rep fifo to write data to tail
reg [15:0] flit2pass_req; // seled flit output to pass req
reg [1:0] ctrl2pass_req; // seled ctrl output to pass req
reg [15:0] flit2pass_rep; // seled flit output to pass req
reg [1:0] ctrl2pass_rep; // seled ctrl output to pass req
reg [15:0] flit2local_in_req; // seled flit output to pass req
reg [1:0] ctrl2local_in_req; // seled ctrl output to pass req
reg [15:0] flit2local_in_rep; // seled flit output to pass req
reg [1:0] ctrl2local_in_rep; // seled ctrl output to pass req
reg en_pass_req;
reg en_pass_rep;
reg en_local_in_req;
reg en_local_in_rep;
always@(*)
begin
{en_pass_req,flit2pass_req,ctrl2pass_req}={1'b0,flit,ctrl};
{en_pass_rep,flit2pass_rep,ctrl2pass_rep}={1'b0,flit,ctrl};
{en_local_in_req,flit2local_in_req,ctrl2local_in_req}={1'b0,flit,ctrl};
{en_local_in_rep,flit2local_in_rep,ctrl2local_in_rep}={1'b0,flit,ctrl};
if(en_dest_fifo)
begin
case(dest_fifo)
2'b00:{en_pass_req,flit2pass_req,ctrl2pass_req}={1'b1,flit,ctrl};
2'b01:{en_pass_rep,flit2pass_rep,ctrl2pass_rep}={1'b1,flit,ctrl};
2'b10:{en_local_in_req,flit2local_in_req,ctrl2local_in_req}={1'b1,flit,ctrl};
2'b11:{en_local_in_rep,flit2local_in_rep,ctrl2local_in_rep}={1'b1,flit,ctrl};
// default:{en_pass_req,flit2pass_req,ctrl2pass_req}={1'b1,flit,ctrl};
endcase
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { x = 0; char c = getchar(); int f = 1; while (!isdigit(c)) { if (c == - ) f = -1; c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } x *= f; } const int N = 6666; const double eps = 1e-9; int n, m, a[N], b[N]; void Get(double &x, int y) { x -= (double)(x / y); } int main() { read(n); read(m); for (register int i = 1; i <= n; i++) read(a[i]); for (register int i = 1; i <= n; i++) read(b[i]); double l = 0, r = 1e9, res = 2e9; for (register int t = 70; t >= 1; t--) { double mid = (l + r) / 2, now = m + mid; for (register int i = 1; i <= n; i++) Get(now, a[i]), Get(now, b[i < n ? i + 1 : 1]); if (now > m - eps) res = mid, r = mid; else l = mid; } if (res > 1e9 + eps) puts( -1 ); else printf( %.9lf , res); return 0; } |
#include <bits/stdc++.h> using namespace std; void solve_problem() { int n; cin >> n; set<int> s; for (int i = 1; i * i <= n; ++i) { s.insert(i * i); } for (int i = 1; i * i * i <= n; ++i) { s.insert(i * i * i); } cout << s.size() << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.exceptions(cin.failbit); cin.tie(0); int T = 1; cin >> T; for (int tc = 0; tc < T; ++tc) { solve_problem(); } } |
#include <bits/stdc++.h> using namespace std; void move(char b[], int n, int i) { for (int j = i; j < n - 1; ++j) { b[j] = b[j + 1]; } } int main() { int a[10]; char b[101]; char d[101]; int c; int n, q, nd, nn; cin >> n >> q; for (int i = 0; i < n; ++i) { cin >> b[i]; } for (int i = 0; i < q; ++i) { for (int j = 0; j < 10; ++j) a[j] = 0; int l, r; cin >> l >> r; nn = 0; for (int j = l - 1; j < r; ++j) { d[j - (l - 1)] = b[j]; if (d[j - (l - 1)] >= 0 && d[j - (l - 1)] <= 9 ) ++nn; } nd = r - l + 1; int cp = 0; char dp = > ; while (1) { if (nn <= 0 || cp < 0 || cp >= nd) { break; } if (d[cp] == < ) { dp = < ; if (cp == 0) { break; } if (d[cp - 1] == > || d[cp - 1] == < ) { move(d, nd, cp); --nd; } } else if (d[cp] == > ) { dp = > ; if (cp == nd - 1) { break; } if (d[cp + 1] == > || d[cp + 1] == < ) { move(d, nd, cp); --cp; --nd; } } else if (d[cp] >= 1 && d[cp] <= 9 ) { ++a[d[cp] - 0 ]; --d[cp]; } else if (d[cp] == 0 ) { ++a[0]; move(d, nd, cp); if (dp == > ) { --cp; } --nn; --nd; } if (dp == < ) { --cp; } else { ++cp; } } for (int j = 0; j < 9; ++j) { cout << a[j] << ; } cout << a[9] << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBP_SYMBOL_V
`define SKY130_FD_SC_MS__DFBBP_SYMBOL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBP_SYMBOL_V
|
// UART Receiver: Exercise 2.4
`include "uart_params.v"
module uart_rx(
input wire clk,
input wire rst,
input wire din,
output reg valid,
output reg [7:0] data_in);
reg [8:0] etu_cnt;
reg [2:0] bit_cnt;
reg [7:0] data;
reg [1:0] state;
reg starting;
wire etu_full = (etu_cnt == `UART_FULL_ETU);
wire etu_half = (etu_cnt == `UART_HALF_ETU);
always @(posedge clk) begin
etu_cnt <= (etu_cnt + 1);
bit_cnt <= bit_cnt;
state <= state;
valid <= valid;
data <= data;
starting <= starting;
if (rst) begin
state <= `UART_START;
bit_cnt <= 2'd0;
etu_cnt <= 9'd0;
data <= 8'd0;
valid <= 1'b0;
data_in <= 8'd0;
end
else
begin
case (state)
`UART_START:
begin
valid <= 1'd0;
// If din is low, wait half an ETU, then check to see if it's low again.
// If it is, then it's time to start reading data
if (~din) begin
if (~starting) begin
starting <= 1'd1;
etu_cnt <= 9'd0;
end
else // din is low, and we've already toggled starting
begin
if (etu_half) begin
etu_cnt <= 0;
bit_cnt <= 0;
state <= `UART_DATA;
end
end
end
else // din is high
begin
starting <= 1'd0;
end
end
`UART_DATA:
begin
if (etu_full) begin
etu_cnt <= 9'd0;
bit_cnt <= (bit_cnt + 1);
data <= {din, data[7:1]};
if (bit_cnt == 7) begin
state <= `UART_STOP;
end
end
end
`UART_STOP:
begin
if (etu_full) begin
etu_cnt <= 9'd0;
data_in <= data;
valid <= din;
state <= `UART_START;
end
end
endcase
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { int n, i; cin >> n; bool t[2 * n], s[2 * n]; char tmp; for (i = 0; i < 2 * n; i++) { cin >> tmp; t[i] = (tmp == 1 ); } for (i = 0; i < 2 * n; i++) { cin >> tmp; s[i] = (tmp == 1 ); } int t_sum = 0, s_sum = 0, and_sum = 0, t_sum1 = 0, s_sum1 = 0; for (i = 0; i < 2 * n; i++) { t_sum += int(t[i]); s_sum += int(s[i]); and_sum += int(t[i] & s[i]); t_sum1 += int(!t[i] & s[i]); s_sum1 += int(t[i] & !s[i]); } if (t_sum > s_sum) { if (and_sum % 2 == 0) t_sum -= min(t_sum - s_sum, s_sum1) / 2; else t_sum -= min(t_sum - s_sum, s_sum1) / 2 + min(t_sum - s_sum, s_sum1) % 2; } else if (t_sum < s_sum) { if (and_sum % 2 == 0) s_sum -= min(s_sum - t_sum, t_sum1) / 2 + min(s_sum - t_sum, t_sum1) % 2; else s_sum -= min(s_sum - t_sum, t_sum1) / 2; } t_sum -= and_sum / 2; s_sum -= and_sum / 2 + and_sum % 2; if (t_sum == s_sum) cout << Draw ; else if (t_sum > s_sum) cout << First ; else cout << Second ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_PKG_SN_TB_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_PKG_SN_TB_V
/**
* udp_dlatch$PSa_pp$PKG$sN: Positive level sensitive D-type -latch
* with active low
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_dlatch_psa_pp_pkg_sn.v"
module top();
// Inputs are registered
reg D;
reg SET_ASYNC;
reg SLEEP_B;
reg NOTIFIER_REG;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
NOTIFIER_REG = 1'bX;
SET_ASYNC = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 NOTIFIER_REG = 1'b0;
#80 SET_ASYNC = 1'b0;
#100 SLEEP_B = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 KAPWR = 1'b1;
#200 NOTIFIER_REG = 1'b1;
#220 SET_ASYNC = 1'b1;
#240 SLEEP_B = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 KAPWR = 1'b0;
#340 NOTIFIER_REG = 1'b0;
#360 SET_ASYNC = 1'b0;
#380 SLEEP_B = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 SLEEP_B = 1'b1;
#500 SET_ASYNC = 1'b1;
#520 NOTIFIER_REG = 1'b1;
#540 KAPWR = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 SLEEP_B = 1'bx;
#640 SET_ASYNC = 1'bx;
#660 NOTIFIER_REG = 1'bx;
#680 KAPWR = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__udp_dlatch$PSa_pp$PKG$sN dut (.D(D), .SET_ASYNC(SET_ASYNC), .SLEEP_B(SLEEP_B), .NOTIFIER_REG(NOTIFIER_REG), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_PKG_SN_TB_V
|
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const double eps = 1e-12; const int INF = (1 << 31) - 1; const long long LLINF = ((long long)1 << 62) - 1; const int maxn = 1000 * 100 + 10; int a[maxn], sum[maxn], sum2[maxn]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); if (i) sum[i] = sum[i - 1] + a[i]; else sum[i] = a[i]; } string s; getline(cin, s); getline(cin, s); for (int i = (int)s.size() - 1; i >= 0; i--) { if (i != (int)s.size() - 1) { sum2[i] = sum2[i + 1] + (s[i] - 0 ) * a[i]; } else { sum2[i] = (s[i] - 0 ) * a[i]; } } long long maxx = 0LL; for (int i = (int)s.size() - 1; i >= 0; i--) { if (s[i] == 1 ) { long long cur = 0LL; cur = sum[i - 1]; cur += sum2[i + 1]; maxx = max(maxx, cur); } } printf( %lld , max(maxx, (long long)sum2[0])); return 0; } |
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ulight_fifo_counter_rx_fifo (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 5: 0] in_port;
input reset_n;
wire clk_en;
wire [ 5: 0] data_in;
wire [ 5: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {6 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long even[222222] = {0}, a[222222], odd[222222] = {0}, backEven[222222], cur, best = numeric_limits<int>::min(), besteven = 0; int main() { int n; scanf( %d , &n); for (int i = 2; i <= n; i++) cin >> a[i]; even[1] = 0; odd[1] = 0; for (int i = 2; i <= n; i++) { even[i] = even[i - 1] + (a[i] / 2) * 2; if (a[i] < 2) even[i] = 0; odd[i] = odd[i - 1] + a[i]; if (a[i] % 2 == 0) odd[i]--; } backEven[n] = 0; for (int i = n - 1; i >= 1; i--) { backEven[i] = backEven[i + 1] + (a[i + 1] / 2) * 2; if (a[i + 1] < 2) backEven[i] = 0; } for (int j = 1; j <= n; j++) { cur = besteven + backEven[j] + odd[j]; best = max(cur, best); besteven = max(besteven, even[j + 1] - odd[j + 1]); } cout << best; return 0; } |
module uartmm(input clk,
input rst,
input RX,
output TX,
output reg [31:0] data_b,
output reg strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
wire [7:0] uart_din;
wire uart_valid;
wire uart_ready;
reg uart_wr;
reg uart_rd;
reg [7:0] uart_dout;
reg [7:0] uart_din_r;
reg uart_valid_r;
reg uart_ready_r;
wire uart_RXD;
inpin _rcxd(.clk(clk), .pin(RX), .rd(uart_RXD));
wire uart_busy;
assign uart_ready = ~uart_busy;
buart _uart (
.clk(clk),
.resetq(1'b1),
.rx(uart_RXD),
.tx(TX),
.rd(uart_rd),
.wr(uart_wr),
.valid(uart_valid),
.busy(uart_busy),
.tx_data(uart_dout),
.rx_data(uart_din));
wire strobe_b_next;
wire [31:0] data_b_next;
assign strobe_b_next = (addr_b == 65537) | (addr_b == 65538) | (addr_b == 65539);
assign data_b_next = (addr_b == 65537)?uart_valid_r:
(addr_b == 65538)?uart_ready_r:
(addr_b == 65539)?uart_din_r:0;
always @(posedge clk)
if (~rst) begin
uart_wr <= 0;
uart_rd <= 0;
uart_valid_r <= 0;
uart_din_r <= 0;
uart_dout <= 0;
strobe_b <= 0;
data_b <= 0;
end else begin
strobe_b <= strobe_b_next;
data_b <= data_b_next;
if (uart_wr) begin
uart_wr <= 0;
end
if (uart_valid & ~uart_rd) begin
uart_rd <= 1; // TODO: read into a FIFO / raise an IRQ (when we had a support for them)
end
uart_ready_r <= uart_ready; // delay
if (uart_rd) begin
uart_rd <= 0;
uart_din_r <= uart_din;
uart_valid_r <= 1;
end else if ((addr_b == 65539) & ~data_b_we & uart_valid_r) begin
uart_valid_r <= 0;
end else if ((addr_b == 65539) & data_b_we & uart_ready & ~uart_wr) begin
uart_dout <= data_b[7:0];
uart_wr <= 1;
end
end
endmodule
module ledwriter (input clk,
input rst,
output reg [7:0] LED,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
always @(posedge clk)
if (~rst) begin
LED <= 0;
end else begin
if (addr_b == 65540)
LED <= data_b_in[7:0];
end
endmodule
// TODO:
// implement a 2-port RAM by using a double clock frequency + a single port
module socram(input clk,
input rst,
output reg [31:0] data_a,
input [31:0] addr_a,
output reg [31:0] data_b,
output reg strobe_b,
input [31:0] addr_b,
input [31:0] data_b_in,
input [31:0] data_b_we);
parameter RAM_DEPTH = 1024;
`ifdef ENABLE_EXT
parameter INIT_FILE = "../../custom_ice.hex";
`else
parameter INIT_FILE = "ram.hex";
`endif
reg [31:0] mem [0:RAM_DEPTH-1];
initial begin
if (INIT_FILE != "")
$readmemh(INIT_FILE, mem);
end
always @(posedge clk)
begin
if (data_b_we & (addr_b[31:16] == 0)) begin
mem[addr_b] <= data_b_in;
end
data_a <= mem[addr_a];
data_b <= mem[addr_b];
strobe_b <= (addr_b[31:16] == 0);
end
endmodule
module mul16x16 (input [15:0] a,
input [15:0] b,
output [31:0] o);
assign o = a * b;
endmodule // mul16x16
`include "../rtl/mul.v"
module hls_Mul(input clk,
input reset,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
wire [15:0] a = p0r[31:16];
wire [15:0] b = p0r[15:0];
wire [15:0] c = p1r[31:16];
wire [15:0] d = p1r[15:0];
wire [15:0] ad = a * d;
wire [15:0] bc = b * c;
wire [31:0] bd = b * d;
reg [15:0] adr;
reg [31:0] p0r;
reg [31:0] p1r;
reg [31:0] t1;
reg [31:0] t2;
assign out = t2;
always @(posedge clk)
begin
p0r <= p0; p1r <= p1;
t1 <= bd + {bc[15:0], 16'b0}; adr <= ad[15:0];
t2 <= t1 + {adr[15:0], 16'b0};
end
endmodule // hls_Mul
module hls_MulFSM(input clk,
input reset,
input req,
output ack,
input [31:0] p0,
input [31:0] p1,
output [31:0] out);
mul32x32_fsm S(.clk(clk),
.rst(reset),
.req(req),
.ack(ack),
.p0(p0),
.p1(p1),
.out(out));
endmodule // hls_MulFSM
|
#include <bits/stdc++.h> using namespace std; long long n, m, w, r, k, i, j, s, q, x, y, l, a[22000]; int main() { ios_base::sync_with_stdio(0); cin >> n; for (i = 1; i <= n; i++) { cin >> a[i], s += a[i]; if (a[i] < 0) k = 1; } if (k == 0) { cout << s; return 0; } for (l = 2; l <= n; l++) if (n % l == 0 && n / l >= 3) for (j = 1; j <= l; j++) { m = 0; for (i = j; i <= n; i += l) m += a[i]; s = max(s, m); } cout << s; } |
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