text stringlengths 59 71.4k |
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#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; void solve() { int n, b, d; cin >> n >> b >> d; int res = 0; int currMass = 0; for (int i = 0; i < n; i++) { int got; cin >> got; if (got > b) continue; currMass += got; if (currMass > d) { currMass = 0; res++; } } cout << res; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__SDFXBP_BEHAVIORAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_no_pg/sky130_fd_sc_hs__u_df_p_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfxbp (
VPWR,
VGND,
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE
);
// Module ports
input VPWR;
input VGND;
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_no_pg u_df_p_no_pg0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXBP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; mt19937_64 rng(chrono::steady_clock::now().time_since_epoch().count()); struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; void _print() { cout << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { cout << t; if (sizeof...(v)) cout << , ; _print(v...); } using ll = long long int; using ld = long double; template <typename T, typename V> using P = pair<T, V>; template <typename T> using V = vector<T>; constexpr ll MOD = 1e9 + 7; constexpr ll INF = 0x3f3f3f3f; constexpr ld PI = 3.1415926535897932384626; constexpr ld EPS = 1e-9; constexpr ll MAX = 1e5 + 5; void solve() { ll n; cin >> n; V<ll> a(n + 1); for (ll i = (ll)(1); i < (ll)(n + 1); i++) cin >> a[i]; if (a[1]) { cout << n + 1 << ; for (ll i = (ll)(1); i < (ll)(n + 1); i++) cout << i << n [i == n]; return; } else if (!a[n]) { for (ll i = (ll)(1); i < (ll)(n + 1); i++) cout << i << ; cout << n + 1 << n ; return; } for (ll i = (ll)(1); i < (ll)(n); i++) if (!a[i] && a[i + 1]) { for (ll j = (ll)(1); j < (ll)(i + 1); j++) cout << j << ; cout << n + 1 << ; for (ll j = (ll)(i + 1); j < (ll)(n + 1); j++) cout << j << n [j == n]; return; } cout << -1 n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); ll t = 1; cin >> t; for (ll i = (ll)(1); i < (ll)(t + 1); i++) solve(); } |
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : MAC1.v ** //
// ** Project : ISAAC Newton ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Multiplier-Accumulator Module ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : MAC1.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ** ** //
// ** File : MAC1.v ** //
// ** Revision : 2 ** //
// ** Author : kaylangu ** //
// ** Date : October 23, 2008 ** //
// ** Notes : Added Sync Signal to synchronize the MAC ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module MAC1
(/*AUTOARG*/
// Outputs
OutData, output_Valid,
// Inputs
CLK, ARST, input_Valid, initialize, InData, filterCoef
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - INPUTS AND OUTPUTS
input CLK ; // 60MHz Clock
input ARST ;
input input_Valid ;
input initialize ;
input signed [(15):0] InData, filterCoef ;
// input Sync;
output signed [(31):0] OutData ;
output output_Valid ;
// DATA TYPE - REGISTERS
reg signed [(31):0] mult ;
reg signed [31:0] accum;
reg input_Valid0 ;
reg initialize1 ;
reg output_Valid_1 ;
wire output_Valid ;
reg [3:0] count ;
// DATA TYPE - WIRES
wire signed [(31):0] accum_tmp ;
wire [3:0] taps ;
// assign taps = (15 == 15) ? 0 : (15 - 15 + 15) ;
//**************************************************************************//
//* Input Buffers *//
//**************************************************************************//
always @(posedge CLK or posedge ARST)
if (ARST) input_Valid0 <= 1'b0 ;
else input_Valid0 <= input_Valid ;
always @(posedge CLK or posedge ARST)
if (ARST) initialize1 <= 1'b0 ;
else initialize1 <= initialize ;
//**************************************************************************//
//* Multiply-Accumulate *//
//**************************************************************************//
// Multiplier
always @(posedge CLK or posedge ARST)
if (ARST) mult[(31):0] <= {(31){1'b0}} ;
else mult[(31):0] <= filterCoef*InData ;
assign accum_tmp[(31):0] = mult[(31):0] + accum[(31):0];
// Accumulator
always @(posedge CLK or posedge ARST)// or initialize)
if (ARST) accum[(31):0] <= {(32){1'b0}} ;
else accum[(31):0] <= (initialize1) ?
mult[31:0] :
(input_Valid0 ? accum_tmp[31:0]
: accum[31:0]) ;
//**************************************************************************//
//* Counters *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST ) count[3:0] <= {(4){1'b0}} ;
else count[3:0] <= initialize ?
0 :
input_Valid0 + count[3:0] ;
//**************************************************************************//
//* Output Buffers *//
//**************************************************************************//
always @(posedge CLK or posedge ARST)
if (ARST) output_Valid_1 <= 1'b0 ;
else output_Valid_1 <= (count[3:0]==(14)) ;
assign output_Valid = output_Valid_1 & (count[3:0]==0) ;
assign OutData[31:0] = accum[31:0] ;
endmodule //MAC1 |
#include <bits/stdc++.h> using namespace std; int a[101], b[101], g[101][101]; int main() { int i, j, n, k; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , &a[i]); for (i = 1; i <= n; i++) scanf( %d , &b[i]); memset(g, 0, sizeof(g)); for (i = 1; i <= n; i++) { if (i + b[i] <= n) g[i][i + b[i]] = g[i + b[i]][i] = 1; if (i - b[i] >= 1) g[i][i - b[i]] = g[i - b[i]][i] = 1; } for (k = 1; k <= n; k++) { for (i = 1; i <= n; i++) { for (j = 1; j <= n; j++) { if (g[i][k] && g[k][j]) g[i][j] = 1; } } } bool flag = 1; for (i = 1; i <= n; i++) { if (i == a[i]) continue; if (g[i][a[i]] == 0) flag = 0; if (flag == 0) break; } if (flag) printf( YES n ); else printf( NO n ); } |
#include <bits/stdc++.h> using namespace std; const long long N = 1e6 + 3; long long n, x, a, cnt, ans, sum; string g; deque<long long> v; void DNM() { cin >> n; for (long long i = 0; i < n; i++) { cin >> a; v.push_back(a); if (a > 0) cnt = i; } for (long long i = 0; i <= cnt; i++) { if (i == cnt and i == n - 1) { for (long long j = 1; j <= v[i]; j++) { if (j == v[i]) g += P ; else g += P , g += L , g += R ; } break; } for (long long j = 0; j < v[i]; j++) { g += P ; g += R ; g += L ; } g += R ; } cout << g << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int Qu_l_uQ = 1; while (Qu_l_uQ--) DNM(); } |
/* amiga_clk.v */
/* 2012, */
module amiga_clk (
input wire rst, // asynhronous reset input
input wire clk_in, // input clock ( 27.000000MHz)
output wire clk_114, // SDRAM ctrl clock (114.750000MHz)
output wire clk_sdram, // SDRAM output clock (114.750000MHz, -146.25 deg)
output wire clk_28, // 28MHz output clock ( 28.375160MHz)
output wire clk_7, // 7MHz output clock ( 7.171875MHz)
output wire clk7_en, // 7MHz output clock enable (on 28MHz clock domain)
output wire clk7n_en, // 7MHz negedge output clock enable (on 28MHz clock domain)
output wire c1, // clk28m clock domain signal synchronous with clk signal
output wire c3, // clk28m clock domain signal synchronous with clk signal delayed by 90 degrees
output wire cck, // colour clock output (3.54 MHz)
output wire [ 10-1:0] eclk, // 0.709379 MHz clock enable output (clk domain pulse)
output wire locked // PLL locked output
);
//// simulation clocks ////
`ifdef SOC_SIM
reg clk_114_r;
reg clk_28_r;
reg clk_sdram_r;
reg pll_locked_r;
initial begin
pll_locked_r = 1'b0;
wait (!rst);
#50;
pll_locked_r = 1'b1;
end
initial begin
clk_114_r = 1'b1;
#1;
wait (pll_locked_r);
#3;
forever #4.357 clk_114_r = ~clk_114_r;
end
initial begin
clk_28_r = 1'b1;
#1;
wait (pll_locked_r);
#5;
forever #17.428 clk_28_r = ~clk_28_r;
end
initial begin
clk_sdram_r = 1'b1;
#1;
wait (pll_locked_r);
#3;
forever #4.357 clk_sdram_r = ~clk_sdram_r;
end
assign clk_114 = clk_114_r;
assign clk_28 = clk_28_r;
assign clk_sdram = clk_sdram_r;
assign locked = pll_locked_r;
`else
//// hardware clocks ////
// device-specific PLL/DCM
`ifdef MINIMIG_ALTERA
amiga_clk_altera amiga_clk_i (
.areset (rst ),
.inclk0 (clk_in ),
.c0 (clk_sdram),
.c1 (clk_114 ),
.c2 (clk_28 ),
.locked (locked )
);
`endif
`ifdef MINIMIG_XILINX
amiga_clk_xilinx amiga_clk_i (
.areset (rst ),
.inclk0 (clk_in ),
.c0 (clk_114 ),
.c1 (clk_28 ),
.c2 (clk_sdram),
.locked (locked )
);
`endif
`endif
//// generated clocks ////
// 7MHz
reg [2-1:0] clk7_cnt = 2'b10;
reg clk7_en_reg = 1'b1;
reg clk7n_en_reg = 1'b1;
always @ (posedge clk_28, negedge locked) begin
if (!locked) begin
clk7_cnt <= 2'b10;
clk7_en_reg <= #1 1'b1;
clk7n_en_reg <= #1 1'b1;
end else begin
clk7_cnt <= clk7_cnt + 2'b01;
clk7_en_reg <= #1 (clk7_cnt == 2'b00);
clk7n_en_reg <= #1 (clk7_cnt == 2'b10);
end
end
assign clk_7 = clk7_cnt[1];
assign clk7_en = clk7_en_reg;
assign clk7n_en = clk7n_en_reg;
// amiga clocks & clock enables
// __ __ __ __ __
// clk_28 __/ \__/ \__/ \__/ \__/
// ___________ __
// clk_7 __/ \___________/
// ___________ __
// c1 __/ \___________/ <- clk28m domain
// ___________
// c3 ________/ \________ <- clk28m domain
//
// clk_28 clock domain signal synchronous with clk signal delayed by 90 degrees
reg c3_r = 1'b0;
always @(posedge clk_28) begin
c3_r <= clk_7;
end
assign c3 = c3_r;
// clk28m clock domain signal synchronous with clk signal
reg c1_r = 1'b0;
always @(posedge clk_28) begin
c1_r <= ~c3_r;
end
assign c1 = c1_r;
// counter used to generate e clock enable
reg [3:0] e_cnt = 4'b0000;
always @(posedge clk_7) begin
if (e_cnt[3] && e_cnt[0])
e_cnt[3:0] <= 4'd0;
else
e_cnt[3:0] <= e_cnt[3:0] + 4'd1;
end
// CCK clock output
assign cck = ~e_cnt[0];
// 0.709379 MHz clock enable output (clk domain pulse)
assign eclk[0] = ~e_cnt[3] & ~e_cnt[2] & ~e_cnt[1] & ~e_cnt[0]; // e_cnt == 0
assign eclk[1] = ~e_cnt[3] & ~e_cnt[2] & ~e_cnt[1] & e_cnt[0]; // e_cnt == 1
assign eclk[2] = ~e_cnt[3] & ~e_cnt[2] & e_cnt[1] & ~e_cnt[0]; // e_cnt == 2
assign eclk[3] = ~e_cnt[3] & ~e_cnt[2] & e_cnt[1] & e_cnt[0]; // e_cnt == 3
assign eclk[4] = ~e_cnt[3] & e_cnt[2] & ~e_cnt[1] & ~e_cnt[0]; // e_cnt == 4
assign eclk[5] = ~e_cnt[3] & e_cnt[2] & ~e_cnt[1] & e_cnt[0]; // e_cnt == 5
assign eclk[6] = ~e_cnt[3] & e_cnt[2] & e_cnt[1] & ~e_cnt[0]; // e_cnt == 6
assign eclk[7] = ~e_cnt[3] & e_cnt[2] & e_cnt[1] & e_cnt[0]; // e_cnt == 7
assign eclk[8] = e_cnt[3] & ~e_cnt[2] & ~e_cnt[1] & ~e_cnt[0]; // e_cnt == 8
assign eclk[9] = e_cnt[3] & ~e_cnt[2] & ~e_cnt[1] & e_cnt[0]; // e_cnt == 9
endmodule
|
module helloworld_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy // AVR Rx buffer full
);
// make reset active high
wire rst = ~rst_n;
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
// LEDs 7 is rst, 6:0 is off
assign led[7] = rst;
assign led[6:0] = 7'b0;
// AVR Serial Interface
wire [7:0] tx_data;
wire new_tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire new_rx_data;
avr_interface avr_interface (
.clk(clk),
.rst(rst),
.cclk(cclk),
.spi_miso(spi_miso),
.spi_mosi(spi_mosi),
.spi_sck(spi_sck),
.spi_ss(spi_ss),
.spi_channel(spi_channel),
.tx(avr_rx), // FPGA tx goes to AVR rx
.rx(avr_tx),
.channel(4'd15), // invalid channel disables the ADC
.new_sample(),
.sample(),
.sample_channel(),
.tx_data(tx_data),
.new_tx_data(new_tx_data),
.tx_busy(tx_busy),
.tx_block(avr_rx_busy),
.rx_data(rx_data),
.new_rx_data(new_rx_data)
);
helloworld helloworld (
.clk(clk),
.rst(rst),
.tx_data(tx_data),
.new_tx_data(new_tx_data),
.tx_busy(tx_busy),
.rx_data(rx_data),
.new_rx_data(new_rx_data)
);
endmodule
|
module note_pitch2dds_3st_gen(clk, note, pitch, adder);
input wire clk;
input wire [6:0] note;
input wire [13:0] pitch;
output reg [31:0] adder;
reg [32:0] adder_sum;
reg [7:0] adder_mul;
reg [3:0] state;
reg [6:0] note_local;
reg [13:0] pitch_local;
initial begin
note_local <= 7'd0;
pitch_local <= 14'd08192; // 0 - pitch wheel
adder <= 32'd0;
state <= 4'd0;
Snote <= 9'D0;
end
//считаем pitch Wheel
// in_val сначала << 7
// а потом
//; ALGORITHM:
//; Clear accumulator
//; Add input / 1024 to accumulator >> 10
//; Add input / 2048 to accumulator >> 11
//; Move accumulator to result
//; Approximated constant: 0.00146484, Error: 0 %
//вычитаем 8192
wire signed [14:0] in_val_centered = (pitch - 14'd08192);
//15+11 = 26 бит
wire signed [26:0] in_val_fix = in_val_centered <<< 11;
//mul 0.00146484
wire signed [26:0] in_val_mul = (in_val_fix >>> 10) + (in_val_fix >>> 11);
//старшая часть, которую прибавим к номеру ноты
wire signed [26:0] t_in_val_hi = in_val_mul >>> 11;
wire signed [7:0] in_val_hi = t_in_val_hi[7:0];
//младшая 8 битная часть, которую будем применять в линейной интерполяции
wire [7:0] in_val_lo = in_val_mul[10:3];
reg signed [8:0] Snote ; //= note;
wire [7:0] note_n = ((Snote + in_val_hi)< 0) ? 7'd0 :
((Snote + in_val_hi)> 127) ? 7'd0127 : Snote + in_val_hi;
wire [31:0] adder_by_table;
note2dds note2dds_table(clk, note_n[6:0], adder_by_table);
always @ (posedge clk) begin
if (state==4'd00) begin
Snote <= note;
if ((note!=note_local)||(pitch!=pitch_local)) begin
note_local<=note;
pitch_local<=pitch;
adder_sum<=33'd0;
adder_mul<=8'd0;
end
end else if ((state==4'd01)||(state==4'd02)||(state==4'd03)) begin
Snote <= Snote + 1'b1; //if не обязателен
if (state==4'd01) adder_mul <= 8'd0255 - in_val_lo;
if (state==4'd02) adder_mul <= in_val_lo;
adder_sum <= adder_sum + (adder_mul * adder_by_table);
end else if (state==4'd04) begin
adder <= adder_sum >> 8;
end
end
always @ (posedge clk) begin
//смена стейтов
if (state==4'd00) begin
if ((note!=note_local)||(pitch!=pitch_local)) begin
state<=4'd01;
end else begin
state<=4'd00;
end
end else if (state==4'd01) begin
state<=4'd02;
end else if (state==4'd02) begin
state<=4'd03;
end else if (state==4'd03) begin
state<=4'd04;
end else if (state==4'd04) begin
state<=4'd00;
end
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of vgch_subb
//
// Generated
// by: wig
// on: Fri Jul 7 06:44:20 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: vgch_subb.v,v 1.2 2006/07/10 07:30:09 wig Exp $
// $Date: 2006/07/10 07:30:09 $
// $Log: vgch_subb.v,v $
// Revision 1.2 2006/07/10 07:30:09 wig
// Updated more testcasess.
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of vgch_subb
//
// No user `defines in this module
module vgch_subb
//
// Generated Module vgch_subb_i
//
(
p_mix_ebi_cs2_s_io_go,
ebi_cs3_s_io_go // EBI bug, worked because only one step
);
// Generated Module Outputs:
output p_mix_ebi_cs2_s_io_go;
output ebi_cs3_s_io_go;
// Generated Wires:
wire p_mix_ebi_cs2_s_io_go;
wire ebi_cs3_s_io_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire ebi_cs2_s_io; // __W_PORT_SIGNAL_MAP_REQ
wire ebi_cs3_s_io; // __W_PORT_SIGNAL_MAP_REQ
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
assign p_mix_ebi_cs2_s_io_go = ebi_cs2_s_io; // __I_O_BIT_PORT
assign ebi_cs3_s_io_go = ebi_cs3_s_io; // __I_O_BIT_PORT
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for ebi_i
wire mix_dmy_open_0; //__I_OPEN_DUMMY
wire mix_dmy_open_1; //__I_OPEN_DUMMY
wire mix_dmy_open_2; //__I_OPEN_DUMMY
ebi ebi_i (
.cs2_o(ebi_cs2_s_io), // EBI bug missing generated port
.cs3_o(ebi_cs3_s_io), // EBI bug, worked because only one step
.open_t({ mix_dmy_open_2, mix_dmy_open_1, mix_dmy_open_0 }), // __I_BIT_TO_BUSPORT // Merge open port 2 // __I_BIT_TO_BUSPORT // Merge open port 1 // __I_BIT_TO_BUSPORT // Merge open port 0 // __I_COMBINE_SPLICES
.open_tbs() // open bus port
);
// End of Generated Instance Port Map for ebi_i
// Generated Instance Port Map for tmp_i
tmp tmp_i (
);
// End of Generated Instance Port Map for tmp_i
endmodule
//
// End of Generated Module rtl of vgch_subb
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int ans, a, b, n, x; int main() { scanf( %d , &n); while (n--) { scanf( %d , &x); if (n == 0) a = x; b = max(b, x); } printf( %d n , a ^ b); return 0; } |
module coreir_reg_arst #(
parameter width = 1,
parameter arst_posedge = 1,
parameter clk_posedge = 1,
parameter init = 1
) (
input clk,
input arst,
input [width-1:0] in,
output [width-1:0] out
);
reg [width-1:0] outReg;
wire real_rst;
assign real_rst = arst_posedge ? arst : ~arst;
wire real_clk;
assign real_clk = clk_posedge ? clk : ~clk;
always @(posedge real_clk, posedge real_rst) begin
if (real_rst) outReg <= init;
else outReg <= in;
end
assign out = outReg;
endmodule
module commonlib_muxn__N2__width16 (
input [15:0] in_data_0,
input [15:0] in_data_1,
input [0:0] in_sel,
output [15:0] out
);
assign out = in_sel[0] ? in_data_1 : in_data_0;
endmodule
module Mux2xOutUInt16 (
input [15:0] I0,
input [15:0] I1,
input S,
output [15:0] O
);
commonlib_muxn__N2__width16 coreir_commonlib_mux2x16_inst0 (
.in_data_0(I0),
.in_data_1(I1),
.in_sel(S),
.out(O)
);
endmodule
module Counter_comb (
input inc,
input [15:0] self_count_O,
output [15:0] O0,
output [15:0] O1
);
Mux2xOutUInt16 Mux2xOutUInt16_inst0 (
.I0(self_count_O),
.I1(self_count_O + 16'h0001),
.S(inc),
.O(O0)
);
assign O1 = O0;
endmodule
module Counter (
input inc,
input CLK,
input ASYNCRESET,
output [15:0] O
);
wire [15:0] Counter_comb_inst0_O0;
wire [15:0] reg_PR_inst0_out;
Counter_comb Counter_comb_inst0 (
.inc(inc),
.self_count_O(reg_PR_inst0_out),
.O0(Counter_comb_inst0_O0),
.O1(O)
);
coreir_reg_arst #(
.arst_posedge(1'b1),
.clk_posedge(1'b1),
.init(16'h0000),
.width(16)
) reg_PR_inst0 (
.clk(CLK),
.arst(ASYNCRESET),
.in(Counter_comb_inst0_O0),
.out(reg_PR_inst0_out)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int const maxn = int(2 * 1e5 + 5); int dp1[maxn], dp2[maxn], dp3[maxn], n, k, t; string second; char chuyen(char c) { if (c == R ) return G ; if (c == G ) return B ; if (c == B ) return R ; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> t; while (t--) { cin >> n >> k >> second; second = + second; for (int i = 0; i <= second.length(); i++) { dp1[i] = dp2[i] = dp3[i] = 0; } char c = R ; for (int i = 1; i <= second.length() - 1; i++) { if (second[i] != c) dp1[i] = dp1[i - 1] + 1; else dp1[i] = dp1[i - 1]; c = chuyen(c); } c = G ; for (int i = 1; i <= second.length() - 1; i++) { if (second[i] != c) dp2[i] = dp2[i - 1] + 1; else dp2[i] = dp2[i - 1]; c = chuyen(c); } c = B ; for (int i = 1; i <= second.length() - 1; i++) { if (second[i] != c) dp3[i] = dp3[i - 1] + 1; else dp3[i] = dp3[i - 1]; c = chuyen(c); } int res = int(1e9 + 5); for (int i = 1; i <= second.length() - k; i++) { res = min(res, dp1[i + k - 1] - dp1[i - 1]); res = min(res, dp2[i + k - 1] - dp2[i - 1]); res = min(res, dp3[i + k - 1] - dp3[i - 1]); } cout << res << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; char s[100100], sir[100100]; int viz[100100], mi, ma, t, n, freq[100100], fre[100100]; int prim(int x) { for (int i = 2; i <= x; ++i) { if (i * i > x) return 1; if (x % i == 0) return 0; } return 1; } int main() { cin >> (s + 1); n = strlen(s + 1); for (int i = 2; i <= n; ++i) { if (prim(i)) { mi = ++t; for (int j = 1; j <= n; ++j) { if (i * j > n) break; if (viz[i * j]) mi = min(mi, viz[i * j]); } if (mi != t) --t; for (int j = 1; j <= n; ++j) { if (i * j > n) break; viz[i * j] = mi; } } } for (int i = 1; i <= n; ++i) freq[viz[i]]++; for (int i = 1; i <= n; ++i) fre[s[i]]++; for (int i = 1; i <= t; ++i) { ma = 0; for (int j = a ; j <= z ; ++j) if (fre[j] > fre[ma]) { ma = j; } if (fre[ma] >= freq[i]) { fre[ma] -= freq[i]; for (int j = 1; j <= n; ++j) if (viz[j] == i) s[j] = ma; } else { cout << NO ; return 0; } } t = 0; for (int j = a ; j <= z ; ++j) while (fre[j]) { --fre[j]; sir[++t] = j; } for (int i = 1; i <= n; ++i) if (!viz[i]) { s[i] = sir[t--]; } cout << YES n ; cout << (s + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int MX = 2e5 + 5; const long long INF = 1e18; const long double PI = 4 * atan((long double)1); template <class T> bool ckmin(T& a, const T& b) { return a > b ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } set<int> v[26]; string ans; int visited[26] = {0}; void dfs(int s) { visited[s] = true; ans += s + a ; for (auto& i : v[s]) { if (visited[i] == false) dfs(i); } } int main() { int test; cin >> test; while (test--) { string str; cin >> str; for (int i = 0; i < 26; i++) { visited[i] = 0; v[i].clear(); } ans.clear(); int num1 = str.size(); for (int i = 1; i < num1; i++) { v[str[i] - a ].insert(str[i - 1] - a ); v[str[i - 1] - a ].insert(str[i] - a ); } int ok = 0; for (int i = 0; i < 26; i++) { if (v[i].size() > 2) { ok = 1; break; } } if (ok == 1) { cout << NO << endl; } else { for (int i = 0; i < 26; i++) { if (visited[i] == 0 && v[i].size() < 2) { dfs(i); } } bool ok = true; for (int i = 0; i < 26; i++) { if (visited[i] == 0) { ok = false; } } if (ok == false) { cout << NO << endl; } else { cout << YES << endl; cout << ans << endl; } } } } |
/* -------------------------------------------------------------------------------
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
*--------------------------------------------------------------------------------
*/
module LAG_router (i_flit_in, i_flit_out,
i_cntrl_in, i_cntrl_out,
i_input_full_flag,
clk, rst_n);
parameter NP=router_radix;
parameter NV=router_num_pls;
parameter global_links_num = 2;
parameter integer links[router_radix][2] = '{'{2,2}, '{2,2}, '{2,2}, '{2,2}, '{2,2} };
// FIFO rec. data from tile/core is full?
output [router_num_pls_on_entry-1:0] i_input_full_flag;
// link data and control
input flit_t i_flit_in [NP-1:0][global_links_num-1:0];
output flit_t i_flit_out [NP-1:0][global_links_num-1:0];
input [global_links_num-1:0] i_cntrl_in [NP-1:0];
output [global_links_num-1:0] i_cntrl_out [NP-1:0];
input clk, rst_n;
LAG_pl_router #(.buf_len(router_buf_len),
.global_links_num(global_links_num),
.network_x(network_x),
.network_y(network_y),
.NP(NP),
.links(links),
.alloc_stages(router_alloc_stages),
.router_num_pls_on_entry(router_num_pls_on_entry),
.router_num_pls_on_exit(router_num_pls_on_exit)
) router
(i_flit_in, i_flit_out,
i_cntrl_in, i_cntrl_out,
i_input_full_flag,
clk, rst_n);
endmodule
|
module inout_port(GO, clk, reset, iDATA, oReady, oDATA, SCL, SDA, ACK, ctr);
input GO; // output enable
input clk;
input reset;
input [23:0] iDATA;
output oReady;
output oDATA;
output SCL;
inout SDA;
output ACK;
output [5:0] ctr;
reg a; // output data
wire a_z;
reg b; // input data
wire next_b;
wire ACK;
reg CLK_Disable;
reg RW;
reg END;
assign a_z = a? 1'b1:0;
assign SDA = RW? a_z: 1'bz;
assign SCL = CLK_Disable | ( ( (SD_Counter >= 4) & (SD_Counter <= 31))? ~clk:0);
assign ACK = b;
assign next_b = RW?1:SDA;
// states
//parameter S_START = 2'd0;
//parameter S_SEND = 2'd1;
//parameter S_WAIT = 2'd2;
//parameter S_FIN = 2'd3;
reg [5:0] SD_Counter;
wire [5:0] next_SD_Counter;
wire [5:0] ctr;
reg [23:0] SD;
reg FAIL;
// combinational circuit
assign oReady = END;
assign next_SD_Counter = FAIL?32:SD_Counter + 1;
assign ctr = SD_Counter;
//-----------------------------------
always @(negedge reset or negedge clk )
begin
if (!reset)
begin
SD_Counter = 6'b111111;
end
else begin
if (GO == 1)
begin
SD_Counter = 0;
end
else begin
if (SD_Counter < 6'b111111)
begin
SD_Counter = next_SD_Counter;
end
else
SD_Counter = 6'b111111;
end
end
end
always @(posedge clk or negedge reset) begin
if(!reset) begin
CLK_Disable = 1;
a = 1;
//b = 1'bz;
END = 1;
RW = 0;
FAIL = 0;
end
else begin
case(SD_Counter)
6'd0: begin
END = 0;
CLK_Disable = 1;
a = 1;
RW = 1;
FAIL = 0;
end
6'd1: begin
SD = iDATA;
RW = 1;
a = 0;
end
6'd2: CLK_Disable = 0;
6'd3: begin
FAIL = 0;
a = SD[23];
end
6'd4: a = SD[22];
6'd5: a = SD[21];
6'd6: a = SD[20];
6'd7: a = SD[19];
6'd8: a = SD[18];
6'd9: a = SD[17];
6'd10: a = SD[16];
6'd11: RW = 0;
6'd12: begin
RW = 1;
if (b != 0)
FAIL = 1;
else FAIL = 0;
a = SD[15];
end
6'd13: a = SD[14];
6'd14: a = SD[13];
6'd15: a = SD[12];
6'd16: a = SD[11];
6'd17: a = SD[10];
6'd18: a = SD[9];
6'd19: a = SD[8];
6'd20: RW = 0;
6'd21: begin
RW = 1;
if (b != 0)
FAIL = 1;
else FAIL = 0;
a = SD[7];
end
6'd22: a = SD[6];
6'd23: a = SD[5];
6'd24: a = SD[4];
6'd25: a = SD[3];
6'd26: a = SD[2];
6'd27: a = SD[1];
6'd28: a = SD[0];
6'd29: RW = 0;
6'd30: begin
RW = 1;
if (b != 0)
FAIL = 1;
else FAIL = 0;
a =0;
end
6'd31: begin
a = 0;
CLK_Disable = 1;
end
6'd32: begin
a = 1;
END = 1;
RW = 0;
end
endcase
end
end
always @(negedge clk) begin
b = RW?next_b:SDA;
end
endmodule
|
`timescale 1 ns / 1 ps
module address_remap_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S_AXI_in
parameter integer C_S_AXI_in_ID_WIDTH = 1,
parameter integer C_S_AXI_in_DATA_WIDTH = 32,
parameter integer C_S_AXI_in_ADDR_WIDTH = 6,
parameter integer C_S_AXI_in_AWUSER_WIDTH = 0,
parameter integer C_S_AXI_in_ARUSER_WIDTH = 0,
parameter integer C_S_AXI_in_WUSER_WIDTH = 0,
parameter integer C_S_AXI_in_RUSER_WIDTH = 0,
parameter integer C_S_AXI_in_BUSER_WIDTH = 0,
// Parameters of Axi Master Bus Interface M_AXI_out
parameter C_M_AXI_out_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M_AXI_out_BURST_LEN = 16,
parameter integer C_M_AXI_out_ID_WIDTH = 1,
parameter integer C_M_AXI_out_ADDR_WIDTH = 32,
parameter integer C_M_AXI_out_DATA_WIDTH = 32,
parameter integer C_M_AXI_out_AWUSER_WIDTH = 0,
parameter integer C_M_AXI_out_ARUSER_WIDTH = 0,
parameter integer C_M_AXI_out_WUSER_WIDTH = 0,
parameter integer C_M_AXI_out_RUSER_WIDTH = 0,
parameter integer C_M_AXI_out_BUSER_WIDTH = 0
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S_AXI_in
input wire s_axi_in_aclk,
input wire s_axi_in_aresetn,
input wire [C_S_AXI_in_ID_WIDTH-1 : 0] s_axi_in_awid,
input wire [C_S_AXI_in_ADDR_WIDTH-1 : 0] s_axi_in_awaddr,
input wire [7 : 0] s_axi_in_awlen,
input wire [2 : 0] s_axi_in_awsize,
input wire [1 : 0] s_axi_in_awburst,
input wire s_axi_in_awlock,
input wire [3 : 0] s_axi_in_awcache,
input wire [2 : 0] s_axi_in_awprot,
input wire [3 : 0] s_axi_in_awqos,
input wire [3 : 0] s_axi_in_awregion,
input wire [C_S_AXI_in_AWUSER_WIDTH-1 : 0] s_axi_in_awuser,
input wire s_axi_in_awvalid,
output wire s_axi_in_awready,
input wire [C_S_AXI_in_DATA_WIDTH-1 : 0] s_axi_in_wdata,
input wire [(C_S_AXI_in_DATA_WIDTH/8)-1 : 0] s_axi_in_wstrb,
input wire s_axi_in_wlast,
input wire [C_S_AXI_in_WUSER_WIDTH-1 : 0] s_axi_in_wuser,
input wire s_axi_in_wvalid,
output wire s_axi_in_wready,
output wire [C_S_AXI_in_ID_WIDTH-1 : 0] s_axi_in_bid,
output wire [1 : 0] s_axi_in_bresp,
output wire [C_S_AXI_in_BUSER_WIDTH-1 : 0] s_axi_in_buser,
output wire s_axi_in_bvalid,
input wire s_axi_in_bready,
input wire [C_S_AXI_in_ID_WIDTH-1 : 0] s_axi_in_arid,
input wire [C_S_AXI_in_ADDR_WIDTH-1 : 0] s_axi_in_araddr,
input wire [7 : 0] s_axi_in_arlen,
input wire [2 : 0] s_axi_in_arsize,
input wire [1 : 0] s_axi_in_arburst,
input wire s_axi_in_arlock,
input wire [3 : 0] s_axi_in_arcache,
input wire [2 : 0] s_axi_in_arprot,
input wire [3 : 0] s_axi_in_arqos,
input wire [3 : 0] s_axi_in_arregion,
input wire [C_S_AXI_in_ARUSER_WIDTH-1 : 0] s_axi_in_aruser,
input wire s_axi_in_arvalid,
output wire s_axi_in_arready,
output wire [C_S_AXI_in_ID_WIDTH-1 : 0] s_axi_in_rid,
output wire [C_S_AXI_in_DATA_WIDTH-1 : 0] s_axi_in_rdata,
output wire [1 : 0] s_axi_in_rresp,
output wire s_axi_in_rlast,
output wire [C_S_AXI_in_RUSER_WIDTH-1 : 0] s_axi_in_ruser,
output wire s_axi_in_rvalid,
input wire s_axi_in_rready,
// Ports of Axi Master Bus Interface M_AXI_out
input wire m_axi_out_aclk,
input wire m_axi_out_aresetn,
output wire [C_M_AXI_out_ID_WIDTH-1 : 0] m_axi_out_awid,
output wire [C_M_AXI_out_ADDR_WIDTH-1 : 0] m_axi_out_awaddr,
output wire [7 : 0] m_axi_out_awlen,
output wire [2 : 0] m_axi_out_awsize,
output wire [1 : 0] m_axi_out_awburst,
output wire m_axi_out_awlock,
output wire [3 : 0] m_axi_out_awcache,
output wire [2 : 0] m_axi_out_awprot,
output wire [3 : 0] m_axi_out_awqos,
output wire [C_M_AXI_out_AWUSER_WIDTH-1 : 0] m_axi_out_awuser,
output wire m_axi_out_awvalid,
input wire m_axi_out_awready,
output wire [C_M_AXI_out_DATA_WIDTH-1 : 0] m_axi_out_wdata,
output wire [C_M_AXI_out_DATA_WIDTH/8-1 : 0] m_axi_out_wstrb,
output wire m_axi_out_wlast,
output wire [C_M_AXI_out_WUSER_WIDTH-1 : 0] m_axi_out_wuser,
output wire m_axi_out_wvalid,
input wire m_axi_out_wready,
input wire [C_M_AXI_out_ID_WIDTH-1 : 0] m_axi_out_bid,
input wire [1 : 0] m_axi_out_bresp,
input wire [C_M_AXI_out_BUSER_WIDTH-1 : 0] m_axi_out_buser,
input wire m_axi_out_bvalid,
output wire m_axi_out_bready,
output wire [C_M_AXI_out_ID_WIDTH-1 : 0] m_axi_out_arid,
output wire [C_M_AXI_out_ADDR_WIDTH-1 : 0] m_axi_out_araddr,
output wire [7 : 0] m_axi_out_arlen,
output wire [2 : 0] m_axi_out_arsize,
output wire [1 : 0] m_axi_out_arburst,
output wire m_axi_out_arlock,
output wire [3 : 0] m_axi_out_arcache,
output wire [2 : 0] m_axi_out_arprot,
output wire [3 : 0] m_axi_out_arqos,
output wire [C_M_AXI_out_ARUSER_WIDTH-1 : 0] m_axi_out_aruser,
output wire m_axi_out_arvalid,
input wire m_axi_out_arready,
input wire [C_M_AXI_out_ID_WIDTH-1 : 0] m_axi_out_rid,
input wire [C_M_AXI_out_DATA_WIDTH-1 : 0] m_axi_out_rdata,
input wire [1 : 0] m_axi_out_rresp,
input wire m_axi_out_rlast,
input wire [C_M_AXI_out_RUSER_WIDTH-1 : 0] m_axi_out_ruser,
input wire m_axi_out_rvalid,
output wire m_axi_out_rready
);
// Instantiation of Axi Bus Interface S_AXI_in
assign m_axi_out_awid = s_axi_in_awid;
assign m_axi_out_awaddr = s_axi_in_awaddr;
assign m_axi_out_awlen = s_axi_in_awlen;
assign m_axi_out_awsize = s_axi_in_awsize;
assign m_axi_out_awburst = s_axi_in_awburst;
assign m_axi_out_awlock = s_axi_in_awlock;
assign m_axi_out_awcache = s_axi_in_awcache;
assign m_axi_out_awprot = s_axi_in_awprot;
assign m_axi_out_awqos = s_axi_in_awqos;
assign m_axi_out_awuser = s_axi_in_awuser;
assign m_axi_out_awvalid = s_axi_in_awvalid;
assign s_axi_in_awready = m_axi_out_awready;
assign m_axi_out_wdata = s_axi_in_wdata;
assign m_axi_out_wstrb = s_axi_in_wstrb;
assign m_axi_out_wlast = s_axi_in_wlast;
assign m_axi_out_wuser = s_axi_in_wuser;
assign m_axi_out_wvalid = s_axi_in_wvalid;
assign s_axi_in_wready = m_axi_out_wready;
assign s_axi_in_bid = m_axi_out_bid;
assign s_axi_in_bresp = m_axi_out_bresp;
assign s_axi_in_buser = m_axi_out_buser;
assign s_axi_in_bvalid = m_axi_out_bvalid;
assign m_axi_out_bready = s_axi_in_bready;
assign m_axi_out_arid = s_axi_in_arid;
assign m_axi_out_araddr = s_axi_in_araddr;
assign m_axi_out_arlen = s_axi_in_arlen;
assign m_axi_out_arsize = s_axi_in_arsize;
assign m_axi_out_arburst = s_axi_in_arburst;
assign m_axi_out_arlock = s_axi_in_arlock;
assign m_axi_out_arcache = s_axi_in_arcache;
assign m_axi_out_arprot = s_axi_in_arprot;
assign m_axi_out_arqos = s_axi_in_arqos;
assign m_axi_out_aruser = s_axi_in_aruser;
assign m_axi_out_arvalid = s_axi_in_arvalid;
assign s_axi_in_arready = m_axi_out_arready;
assign s_axi_in_rid = m_axi_out_rid;
assign s_axi_in_rdata = m_axi_out_rdata;
assign s_axi_in_rresp = m_axi_out_rresp;
assign s_axi_in_rlast = m_axi_out_rlast;
assign s_axi_in_ruser = m_axi_out_ruser;
assign s_axi_in_rvalid = m_axi_out_rvalid;
assign m_axi_out_rready = s_axi_in_rready;
// Add user logic here
// Add user logic here
// User logic ends
endmodule
|
/// date :2016/3/4
/// engineer :ZhaiShaoMin
/// module name :memory_state_data_ram
/// module function : here is placed the ram of state and data
/// because of design division
/// note: state[3:0] is directory
/// state[5:4] is home directory state .00 :R(dir),01 :W(id),10 TR(dir),11 TW(id).
/// every home memeory has 2KB
module memory_state_data_ram(// input
clk,
state_we_in,
state_re_in,
addr_in,
state_in,
data_we_in,
data_re_in,
data_in,
// output
state_out,
data_out);
input clk;
input state_we_in;
input state_re_in;
input [31:0] addr_in;
input [5:0] state_in;
input data_we_in;
input data_re_in;
input [127:0] data_in;
//output
output [5:0] state_out;
output [127:0] data_out;
/*wire [31:0] seled_addr;
wire [5:0] m_state_out;
wire [127:0] seled_data;
wire [127:0] data_read; */
/////////////////////////////////////////////////////////////////////////
////////////// directory_ram and data_ram////////////////////////////////////
////////////////////////////////////////////////////////////////////////
SP_BRAM_SRd #(128,6,7) tag_ram(.clk(clk), .we(state_we_in), .re(state_re_in), .a(addr_in[10:4]), .di(state_in), .dout(state_out));
SP_BRAM_SRd #(128,128,7) data_ram(.clk(clk), .we(data_we_in), .re(data_re_in), .a(addr_in[10:4]), .di(data_in), .dout(data_out));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int h, l; scanf( %lld %lld , &h, &l); printf( %.9f n , (l * l - h * h + 0.0) / (2 * h)); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3B_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__NAND3B_FUNCTIONAL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nand3b (
Y ,
A_N,
B ,
C
);
// Module ports
output Y ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire nand0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y, B, not0_out, C );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3B_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYMETAL6S4S_BLACKBOX_V
`define SKY130_FD_SC_MS__DLYMETAL6S4S_BLACKBOX_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlymetal6s4s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYMETAL6S4S_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int modu = 1e9 + 7; long long int mod(long long int n) { return (n % modu); } bool cmp(long long int a, long long int b) { return a > b; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int N, a, b, c, d, x = 0; pair<int, int> P[205], s; cin >> N; for (int i = 0; i < N; i++) { cin >> P[i].first >> P[i].second; } for (int i = 0; i < N; i++) { a = b = c = d = 0; s.first = P[i].first; s.second = P[i].second; for (int j = 0; j < N; j++) { if (i != j) { if (P[j].first > s.first && P[j].second == s.second) a = 1; else if (P[j].first < s.first && P[j].second == s.second) b = 1; else if (P[j].first == s.first && P[j].second > s.second) c = 1; else if (P[j].first == s.first && P[j].second < s.second) d = 1; } } if (a == 1 && b == 1 && c == 1 && d == 1) x++; } cout << x; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; ; int beauty[n]; for (int asdf = 0; asdf < n; asdf++) { cin >> beauty[asdf]; }; map<int, long long int> occ; long long int most = 0; for (int i = 0; i < n; i++) { int x = i - beauty[i]; if (!occ.count(x)) occ[x] = 0LL; occ[x] = occ[x] + beauty[i]; if (occ[x] > most) most = occ[x]; } cout << most; } |
#include <bits/stdc++.h> using namespace std; long long po(long long x, long long y) { if (y == 0) return 1; else return x * po(x, y - 1); } vector<long long> a[7], b[7]; void solve(long long l, long long r, long long d) { if (l == r) return; long long m = (l + r) >> 1; for (long long i = l; i <= m; i++) a[d].push_back(i); for (long long i = m + 1; i <= r; i++) b[d].push_back(i); solve(l, m, d + 1); solve(m + 1, r, d + 1); } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); long long t; cin >> t; while (t--) { long long n; cin >> n; for (long long i = 0; i < 7; i++) { a[i].clear(); b[i].clear(); } solve(1, n, 0); long long ans = 0; for (long long i = 0; i < 7; i++) { if (a[i].empty() || b[i].empty()) break; cout << a[i].size() << << b[i].size() << ; for (auto it : a[i]) cout << it << ; for (auto it : b[i]) cout << it << ; cout << endl; long long x; cin >> x; ans = max(ans, x); } cout << -1 << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long t, n, max_gcd = 1; cin >> t; while (t--) { cin >> n; cout << n / 2 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { char str1[50], str2[50]; int n, c, k, cnt, flag; cin >> n; while (n--) { flag = cnt = 0; cin >> str1; k = strlen(str1); str1[k] = : ; str1[k + 1] = 0 ; for (int i = 0; i <= k; ++i) { if (str1[i] != : ) flag = 1; else if (flag == 1) { cnt++; flag = 0; } } for (int i = 0; i <= 38; ++i) { if (i == 4 || i == 9 || i == 14 || i == 19 || i == 24 || i == 29 || i == 34) str2[i] = : ; else str2[i] = 0 ; } c = 0; int j = 38; for (int i = k - 1; i >= 0; i--) { if (str1[i] != : ) { c++; str2[j--] = str1[i]; } if (str1[i] == : ) { if (c == 4) j--; if (c == 3) j -= 2; if (c == 2) j -= 3; if (c == 1) j -= 4; c = 0; } if (str1[i] == : && str1[i - 1] == : ) { j -= (8 - cnt) * 5; i--; } } for (int i = 0; i <= 37; ++i) cout << str2[i]; cout << str2[38] << endl; } } |
#include <bits/stdc++.h> using namespace std; int dp[1 << 25]; int tick[25][25], value[25][25], cost[25][25]; int n, m; string s[25]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> s[i]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> value[i][j]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { int maxi = 0; for (int x = 0; x < n; x++) if (s[i][j] == s[x][j]) { tick[i][j] |= (1 << x); maxi = max(maxi, value[x][j]); cost[i][j] += value[x][j]; } cost[i][j] -= maxi; } memset(dp, 1000000005, sizeof(dp)); dp[0] = 0; for (int mask = 1; mask < (1 << n); mask++) { int t; for (int pos = 0; pos < n; pos++) if ((mask >> pos) & 1) { t = pos; break; } for (int pos = 0; pos < m; pos++) { dp[mask] = min(dp[mask], dp[mask & (mask ^ tick[t][pos])] + cost[t][pos]); dp[mask] = min(dp[mask], dp[mask - (1 << t)] + value[t][pos]); } } cout << dp[(1 << n) - 1]; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[1000][1000]; int main() { int n, m, x, y; cin >> n >> m; for (int i = 0; i < m; i++) { cin >> x >> y; x--, y--; for (int k = -2; k < 1; k++) for (int l = -2; l < 1; l++) if (x + k >= 0 && x + k < n && y + l >= 0 && y + l < n) { a[x + k][y + l]++; if (a[x + k][y + l] == 9) { cout << i + 1; return 0; } } } cout << -1; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 1e3 + 10; char s[N], x[N], y[N]; int n, d; namespace Trie { const int M = N * 60; int ch[M][10], tot = 1, rt = 1, fail[M]; bool ed[M]; inline void insert(int l, int r) { int now = rt; for (int i = l; i <= r; ++i) { int v = s[i] - 0 ; if (!ch[now][v]) ch[now][v] = ++tot; now = ch[now][v]; } ed[now] = true; } inline void getfail() { for (int i = 0; i < 10; ++i) ch[0][i] = rt; fail[rt] = 0; queue<int> q; q.push(rt); while (!q.empty()) { int u = q.front(); q.pop(); for (int i = 0; i < 10; ++i) { if (!ch[u][i]) ch[u][i] = ch[fail[u]][i]; else fail[ch[u][i]] = ch[fail[u]][i], q.push(ch[u][i]); } } } } // namespace Trie using namespace Trie; int dp[2][N * 50][2][2][2]; inline void upd(int &x, int y) { x = (x + y >= mod) ? x + y - mod : x + y; } int main() { scanf( %s%s%s , s + 1, x + 1, y + 1); n = strlen(s + 1); d = strlen(x + 1); int nd = d / 2; for (int i = 1; i + nd - 1 <= n; ++i) insert(i, i + nd - 1); getfail(); dp[0][rt][1][1][0] = 1; for (int i = 1; i <= d; ++i) { int cur = i & 1, last = !cur; for (int pos = 0; pos <= tot; ++pos) for (int limx = 0; limx <= 1; ++limx) for (int limy = 0; limy <= 1; ++limy) for (int ok = 0; ok <= 1; ++ok) { int &d = dp[last][pos][limx][limy][ok]; if (!d) continue; int s = limx ? x[i] - 0 : 0, t = limy ? y[i] - 0 : 9; for (int c = s; c <= t; ++c) { int npos = ch[pos][c]; upd(dp[cur][npos][limx && c == x[i] - 0 ] [limy && c == y[i] - 0 ][ok | ed[npos]], d); } d = 0; } } int ans = 0; for (int pos = 0; pos <= tot; ++pos) for (int limx = 0; limx <= 1; ++limx) for (int limy = 0; limy <= 1; ++limy) upd(ans, dp[d & 1][pos][limx][limy][1]); printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> using v2d = vector<vector<T> >; template <class T> bool uin(T &a, T b) { return a > b ? (a = b, true) : false; } template <class T> bool uax(T &a, T b) { return a < b ? (a = b, true) : false; } mt19937 rng(chrono::system_clock::now().time_since_epoch().count()); const int maxN = 2e5 + 10; const long long inf = 1e18; int n; long long k, a[maxN]; bool check(long long d) { long long c = 1, x = d - 1, y = 0, sum = 0; bool ovf = 0; for (int i = n; i; i--) { if (a[i] > 0 && (ovf || (long double)sum + (long double)c * a[i] > inf)) { return 1; } if (a[i] > 0) { sum += c * a[i]; } if (sum >= k) { return 1; } x++; y++; if ((long double)c * x / y > inf) { ovf = 1; } else { __int128 tmp = c; tmp *= x; tmp /= y; c = tmp; } } return sum >= k; } void solve() { cin >> n >> k; for (int i = 1; i <= (int)(n); ++i) { cin >> a[i]; } if (*max_element(a + 1, a + n + 1) >= k) { cout << 0; return; } long long l = 0, r = inf; while (r - l > 1) { long long mid = (l + r) / 2; if (check(mid)) { r = mid; } else { l = mid; } } cout << r; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int T = 1; while (T--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n, k; cin >> n >> k; int cnt = 1; if (k & 1) puts( 1 ); else { do { k /= 2; cnt++; } while (k % 2 != 1); cout << cnt; } return 0; } |
#include <bits/stdc++.h> const long long mod = 998244353; const int kN = 5e3 + 10; int n, a[kN], lim[kN]; long long f[kN], fac[kN], invfac[kN]; inline int read() { int f = 1, w = 0; char ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -1; for (; isdigit(ch); ch = getchar()) { w = (w << 3) + (w << 1) + (ch ^ 0 ); } return f * w; } void Chkmax(int &fir_, int sec_) { if (sec_ > fir_) fir_ = sec_; } void Chkmin(int &fir_, int sec_) { if (sec_ < fir_) fir_ = sec_; } long long QPow(long long x_, long long y_) { x_ %= mod; long long ret = 1; for (; y_; y_ >>= 1ll) { if (y_ & 1) ret = ret * x_ % mod; x_ = x_ * x_ % mod; } return ret; } long long A(long long n_, long long m_) { if (n_ < 0 || m_ < 0 || m_ > n_) return 0; return 1ll * fac[n_] * invfac[n_ - m_] % mod; } void Prepare() { n = read(); invfac[0] = fac[0] = 1; for (int i = 1; i <= n; ++i) { a[i] = read(); fac[i] = 1ll * fac[i - 1] * i % mod; invfac[i] = QPow(fac[i], mod - 2); } std::sort(a + 1, a + n + 1); for (int i = 1, j = 0; i <= n; ++i) { while (j <= n && 2ll * a[j] <= 1ll * a[i]) ++j; --j; lim[i] = j; } } int main() { Prepare(); if (lim[n] != n - 1) { printf( 0 n ); return 0; } f[0] = 1, lim[0] = -1; for (int i = 1; i <= n; ++i) { for (int j = 0; j <= lim[i]; ++j) { f[i] += 1ll * f[j] * A(1ll * n - 2ll - lim[j], 1ll * lim[i] - lim[j] - 1ll) % mod; f[i] %= mod; } } printf( %lld n , f[n]); return 0; } |
(** * Gen: Generalizing Induction Hypotheses *)
(* $Date: 2011-06-07 16:49:17 -0400 (Tue, 07 Jun 2011) $ *)
Require Export Poly.
(** In the previous chapter, we saw a proof that the [double] function
is injective. The way we _start_ this proof is a little bit
delicate: if we begin it with
[[
intros n. induction n.
]]
all is well. But if we begin it with
[[
intros n m. induction n.
]]
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'".
assert (n' = m') as H.
SSCase "Proof of assertion".
(* Here we are stuck. We need the assertion in order to
rewrite the final goal (subgoal 2 at this point) to an
identity. But the induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the assertion is not provable. *)
Admitted.
(** What went wrong here?
The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context
-- intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we can prove
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.)
To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective' : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for *every* [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O". inversion eq. (* The 0 case is trivial *)
SCase "m = S m'".
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
assert (n' = m') as H.
SSCase "Proof of assertion". apply IHn'.
inversion eq. reflexivity.
rewrite -> H. reflexivity. Qed.
(** So what we've learned is that we need to be careful about
using induction to try to prove something too specific: If
we're proving a property of [n] and [m] by induction on [n],
we may need to leave [m] generic.
However, this strategy doesn't always apply directly;
sometimes a little rearrangement is needed. Suppose, for
example, that we had decided we wanted to prove
[double_injective] by induction on [m] instead of [n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'".
assert (n' = m') as H.
SSCase "Proof of assertion".
(* Here we are stuck again, just like before. *)
Admitted.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) What can we do about this?
One possibility is to rewrite the statement of the lemma so
that [m] is quantified before [n]. This will work, but it's
not nice: We don't want to have to mangle the statements of
lemmas to fit the needs of a particular strategy for proving
them -- we want to state them in the most clear and natural
way.
What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'".
assert (n' = m') as H.
SSCase "Proof of assertion".
apply IHm'. inversion eq. reflexivity.
rewrite -> H. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that the
proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Carry out this proof by induction on [m]. *)
Theorem plus_n_n_injective_take2 : forall n m,
n + n = m + m ->
n = m.
Proof.
(* FILL IN HERE *) Admitted.
(** Now prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index (S n) l = None.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_opt) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
|
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2018, Darryl Ring.
//
// This program is free software: you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation, either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <https://www.gnu.org/licenses/>.
//
// Additional permission under GNU GPL version 3 section 7:
// If you modify this program, or any covered work, by linking or combining it
// with independent modules provided by the FPGA vendor only (this permission
// does not extend to any 3rd party modules, "soft cores" or macros) under
// different license terms solely for the purpose of generating binary
// "bitstream" files and/or simulating the code, the copyright holders of this
// program give you the right to distribute the covered work without those
// independent modules as long as the source code for them is available from
// the FPGA vendor free of charge, and there is no dependence on any encrypted
// modules for simulating of the combined code. This permission applies to you
// if the distributed code contains all the components and scripts required to
// completely simulate it with at least one of the Free Software programs.
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1 ps
module axis_phase_generator #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer PHASE_WIDTH = 30
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [PHASE_WIDTH-1:0] cfg_data,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [PHASE_WIDTH-1:0] int_cntr_reg = 0, int_cntr_next;
reg int_enbl_reg = 1'b0, int_enbl_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_cntr_reg <= {(PHASE_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
end
else
begin
int_cntr_reg <= int_cntr_next;
int_enbl_reg <= int_enbl_next;
end
end
always @*
begin
int_cntr_next = int_cntr_reg;
int_enbl_next = int_enbl_reg;
if(~int_enbl_reg)
begin
int_enbl_next = 1'b1;
end
if(int_enbl_reg & m_axis_tready)
begin
int_cntr_next = int_cntr_reg + cfg_data;
end
end
assign m_axis_tdata = {{(AXIS_TDATA_WIDTH-PHASE_WIDTH){int_cntr_reg[PHASE_WIDTH-1]}}, int_cntr_reg};
assign m_axis_tvalid = int_enbl_reg;
endmodule |
#include <bits/stdc++.h> using namespace std; const int N = 20, Mod = 1e9 + 7; int pl, pr, vl, vr, k; long double p, q; vector<int> v; void count(int t) { int L, R; L = min(v[t], pr) - max(v[t - 1] + 1, pl); R = min(v[t + k] - 1, vr) - max(v[t + k - 1], vl); p += max(L + 1, 0) * 1ll * max(R + 1, 0); L = min(v[t], vr) - max(v[t - 1] + 1, vl); R = min(v[t + k] - 1, pr) - max(v[t + k - 1], pl); p += max(L + 1, 0) * 1ll * max(R + 1, 0); if (k == 1) { if (vl <= v[t] && v[t] <= vr && pl <= v[t] && v[t] <= pr) p--; } } void add(int length) { for (int i = 0; i < (1 << length); i++) { int num = 0; for (int j = 0; j < length; j++) { num *= 10; if (i & (1 << j)) num += 4; else num += 7; } v.push_back(num); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> pl >> pr >> vl >> vr >> k; q = (pr - pl + 1) * 1ll * (vr - vl + 1); for (int i = 1; i <= 9; i++) add(i); v.push_back(0); v.push_back(Mod); v.push_back(Mod); sort(v.begin(), v.end()); int n = v.size(); for (int i = 1; i < n - k - 1; i++) { count(i); } cout << fixed << setprecision(10) << p / q; return 0; } |
#include <bits/stdc++.h> using namespace std; string s; int n; int main() { cin >> n; cin >> s; for (int i = 0; i < n; i++) { if (i + 2 < n && s[i] == o && s[i + 1] == g && s[i + 2] == o ) { while (i + 2 < n && s[i + 1] == g && s[i + 2] == o ) i += 2; cout << *** ; } else cout << s[i]; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct point { int x, y; }; struct ConvexHull { vector<point> hull; int m; ConvexHull() : m(0) { hull.clear(); } bool ccw(point x, point y, point z) { return ((y.x - x.x) * (z.y - x.y) > (y.y - x.y) * (z.x - x.x)); } void MakeHull(int n, vector<point> a) { hull.clear(); if (!n) return; int x = 0; for (int i = 0; i < n; i++) if ((a[i].y == a[x].y) ? a[i].x < a[x].x : a[i].y < a[x].y) x = i; swap(a[0], a[x]); hull.push_back({a[0].x, a[0].y + 1}); hull.push_back(a[0]); sort(a.begin() + 1, a.begin() + n, [=](point x, point y) { return (((x.y - a[0].y) * (y.x - a[0].x)) < (x.x - a[0].x) * (y.y - a[0].y)); }); m = 1; for (int i = 1; i < n; i++) { while (!ccw(hull[m - 1], hull[m], a[i])) if (m > 1) hull.pop_back(), m--; else if (i + 1 == n) break; else i++; hull.push_back(a[i]); m++; } hull.erase(hull.begin()); } }; int n; int r; vector<point> v; ConvexHull cw; int ma = 0; vector<point> rez; void rec(int l, int rem, int s, point r) { if (!rem) { int d = s * n - r.x * r.x - r.y * r.y; if (d > ma) { ma = d; rez = v; } return; } if (l == cw.m) return; rec(l + 1, rem, s, r); v.push_back(cw.hull[l]); r = {r.x + v.back().x, r.y + v.back().y}; s += v.back().x * v.back().x + v.back().y * v.back().y; rec(l, rem - 1, s, r); v.pop_back(); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> r; for (int i = 0; i * i <= r * r; i++) for (int j = 0; j * j + i * i <= r * r; j++) { v.push_back({i, j}); if (i) v.push_back({-i, j}); if (j) v.push_back({i, -j}); if (i - j) v.push_back({j, i}); if (i * j) v.push_back({-i, -j}); } cw.MakeHull(v.size(), v); v.clear(); rec(0, n, 0, {0, 0}); cout << ma << n ; for (int i = 0; i < n; i++) cout << rez[i].x << << rez[i].y << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; int x[1000005], y[1000005]; int s[1000005], _sum[1000006], _sumx[1000006], _sumy[1000006], *sum = _sum + 1, *sumx = _sumx + 1, *sumy = _sumy + 1; long long _tot[1000006], *tot = _tot + 1; const int MOD = 1e9 + 7; inline int area(int x, int y, int xx, int yy) { int ret = ((long long)x * yy - (long long)xx * y) % MOD; if (ret < 0) ret += MOD; return ret; } inline long long areaL(int x, int y, int xx, int yy) { return (long long)x * yy - (long long)xx * y; } int main() { scanf( %d , &n); for (int i = 0; i < (int)(n); ++i) scanf( %d%d , x + i, y + i); int ans = 0, mul = -1; for (int times = 0; times < (int)(2); ++times) { for (int i = 0; i < (int)(n + 5); ++i) { x[n + i] = x[i]; y[n + i] = y[i]; } int N = 2 * n + 4; for (int i = 0; i < (int)(N); ++i) s[i] = area(x[i], y[i], x[i + 1], y[i + 1]); tot[-1] = sum[-1] = sumx[-1] = sumy[-1] = 0; for (int i = 0; i < (int)(N); ++i) tot[i] = tot[i - 1] + areaL(x[i], y[i], x[i + 1], y[i + 1]); for (int i = 0; i < (int)(N); ++i) sum[i] = (sum[i - 1] - (long long)i * s[i]) % MOD; for (int i = 0; i < (int)(N); ++i) sumx[i] = (sumx[i - 1] + x[i]) % MOD; for (int i = 0; i < (int)(N); ++i) sumy[i] = (sumy[i - 1] + y[i]) % MOD; for (int i = 0, j = 1; i < n; ++i) { if (j == i) ++j; while (j < i + n - 2 && abs(tot[j] - tot[i - 1] + areaL(x[j + 1], y[j + 1], x[i], y[i])) + times <= abs(tot[n + i - 1] - tot[j] + areaL(x[i], y[i], x[j + 1], y[j + 1]))) { ++j; } if (j == i + 1) continue; ans = (ans + mul * (sum[j - 1] - sum[i - 1] + (tot[j - 1] - tot[i - 1]) % MOD * j - s[i])) % MOD; ans = (ans + mul * areaL(sumx[j] - sumx[i + 1], sumy[j] - sumy[i + 1], x[i], y[i])) % MOD; } if (times == 0) { reverse(x + 1, x + n); reverse(y + 1, y + n); mul = 1; } } int ss = 0; for (int i = 0; i < (int)(n); ++i) ss = (ss + area(x[i], y[i], x[i + 1], y[i + 1])) % MOD; ans = ((long long)ss * ((long long)n * (n - 3) / 2 % MOD) - ans) % MOD; if (ans < 0) ans += MOD; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); int arr[3][3]; for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) cin >> arr[i][j]; } bool chk[3][3]; for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) chk[i][j] = 1; } for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { if (arr[i][j] % 2 == 0) continue; else { if (chk[i][j] == 1) chk[i][j] = 0; else chk[i][j] = 1; if (j + 1 <= 2) { if (chk[i][j + 1] == 1) chk[i][j + 1] = 0; else chk[i][j + 1] = 1; } if (j - 1 >= 0) { if (chk[i][j - 1] == 1) chk[i][j - 1] = 0; else chk[i][j - 1] = 1; } if (i + 1 <= 2) { if (chk[i + 1][j] == 1) chk[i + 1][j] = 0; else chk[i + 1][j] = 1; } if (i - 1 >= 0) { if (chk[i - 1][j] == 1) chk[i - 1][j] = 0; else chk[i - 1][j] = 1; } } } } for (int i = 0; i < 3; i++) { for (int j = 0; j < 3; j++) { cout << chk[i][j]; } cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; vector<pair<string, int>> v; priority_queue<int, vector<int>, greater<int>> pq; for (int i = 0; i < n; ++i) { string s; cin >> s; int x; if (s != removeMin ) { cin >> x; v.push_back({s, x}); } else v.push_back({s, INT_MIN}); } vector<pair<string, int>> ans; for (int i = 0; i < n; ++i) { if (v[i].first == insert ) ans.push_back({v[i].first, v[i].second}), pq.push(v[i].second); else if (v[i].first == getMin ) { int val = v[i].second; if (pq.empty()) { ans.push_back({ insert , val}); pq.push(val); } while (!pq.empty() && val > pq.top()) { ans.push_back({ removeMin , INT_MIN}); pq.pop(); } if (!pq.empty() && val < pq.top()) { ans.push_back({ insert , val}); pq.push(val); } else if (pq.empty()) { ans.push_back({ insert , val}); pq.push(val); } ans.push_back({ getMin , val}); } else { if (pq.empty()) { ans.push_back({ insert , 0}); pq.push(0); } ans.push_back({ removeMin , INT_MIN}); pq.pop(); } } cout << ans.size() << endl; for (int i = 0; i < ans.size(); ++i) { if (ans[i].first == removeMin ) cout << ans[i].first << endl; else cout << ans[i].first << << ans[i].second << endl; } } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always if ( bool_expr) statement_1 else statement_2 ;
module main ;
reg [3:0] value1 ;
initial
begin
value1 = 0;
# 5 ;
if(value1 != 4'd4)
$display("FAILED - always 3.1.5F always if ( bool_expr) statementelse ;");
else
$display("PASSED");
$finish;
end
always if( 1'b1 | 1'b1) begin
# 1;
value1 = value1 + 1;
end
else value1 = 0 ;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NOR2_BEHAVIORAL_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor2 (
Y ,
A ,
B ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
// Local signals
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const double EPS = 1e-6; const int MOD = 1e9 + 7; const int MAXN = 110; const double PI = acos(-1.0); int ipt[MAXN][MAXN]; int main() { int n, m, k; while (~scanf( %d%d%d , &n, &m, &k)) { int ans = INF, all = 1 << m; for (int i = 0; i < (n); ++i) for (int j = 0; j < (m); ++j) scanf( %d , &ipt[i][j]); if (n < m) { for (int i = 0; i < (n); ++i) for (int j = (i + 1); j < (m); ++j) swap(ipt[i][j], ipt[j][i]); swap(n, m); } if (n > k) { for (int i = 0; i < (n); ++i) { int tans = 0; for (int j = 0; j < (n); ++j) { int cnt = 0; for (int k = 0; k < (m); ++k) cnt += ipt[i][k] ^ ipt[j][k]; tans += min(cnt, m - cnt); } ans = min(ans, tans); } } else { for (int mask = 0; mask < all; mask++) { int tans = 0; for (int i = 0; i < (n); ++i) { int cnt = 0; for (int j = 0; j < (m); ++j) cnt += ipt[i][j] ^ (mask >> j & 1); tans += min(cnt, m - cnt); } ans = min(ans, tans); } } printf( %d n , ans <= k ? ans : -1); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, t; int main() { cin >> n >> t; long long z = pow(10, n - 2); if (n == 1 and t == 10) return cout << -1 << endl, 0; if (n == 1) return cout << t << endl, 0; if (t == 2 or t == 4 or t == 5 or t == 8 or t == 10) cout << 40; else if (t == 7) cout << 14; else cout << 18; n -= 2; while (n) { cout << 0 ; n--; } cout << endl; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:25:53 06/10/2015
// Design Name:
// Module Name: ControlUnit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ControlUnit(
input clk,
input[5:0] opcode,
input[5:0] func,
input[4:0] RS,
input MemOK,
input[31:0] C0State,
output MemRead,
output PCWrite,
output PCWriteCond,
output IorD,
output MemWrite,
output[2:0] WriteData,
output IRWrite,
output[1:0] ALUSrcA,
output RegWrite,
output[1:0] RegDst,
output SaveHalf,
output LoadHalf,
output[1:0] ALUop,
output[2:0] ALUSrcB,
output[2:0] PCSource,
output[5:0] CUState,
output[5:0] ALUFunc,
output C0Write,
output[1:0] C0Dst,
output[2:0] C0Src,
output CauseSource,
output SyscallInte,
output IsBne
);
reg [5:0] state;
assign CUState = state;
assign InteEn = C0State[0];
assign INTE = C0State[1];
initial begin
state <= 0;
end
assign R =(opcode==6'h00);
assign SLL_SRL_SRA =(opcode==6'h00 && func[5:2]==4'h0);
assign JR =(opcode==6'h00 && func==6'h8);
assign JALR =(opcode==6'h00 && func==6'h9);
assign SYSCALL = (opcode==6'h00 && func==6'hC);
assign J =(opcode==6'h02);
assign JAL =(opcode==6'h03);
assign BEQ =(opcode==6'h04);
assign BNE =(opcode==6'h05);
assign ADDI =(opcode==6'h08);
assign ADDIU =(opcode==6'h09);
assign SLTI =(opcode==6'h0A);
assign SLTIU =(opcode==6'h0B);
assign ANDI =(opcode==6'h0C);
assign ORI =(opcode==6'h0D);
assign XORI =(opcode==6'h0E);
assign LUI =(opcode==6'h0F);
assign MFC0 =(opcode==6'h10 && RS==5'h0);
assign MTC0 =(opcode==6'h10 && RS==5'h4);
assign ERET =(opcode==6'h10 && RS==5'h10 && func==6'h18);
assign MUL =(opcode==6'h1c);
assign LH =(opcode==6'h21);
assign LW =(opcode==6'h23);
assign SH =(opcode==6'h29);
assign SW =(opcode==6'h2B);
always @(posedge clk) begin
case(state)
0: begin
if(INTE && InteEn) begin
state <= 25;
end
else begin
state <= 23;
end
end
1: begin
if(LW | SW | LH | SH) begin
state <= 2;
end
else if (R)begin
if(JR) begin
state <= 14;
end
else if(JALR) begin
state <= 15;
end
else if(SLL_SRL_SRA) begin
state <= 19;
end
else if(SYSCALL) begin
state <= 29;
end
else begin
state <= 6;
end
end
else if (BEQ) begin
state <= 8;
end
else if (J) begin
state <= 9;
end
else if(JAL) begin
state <= 13;
end
else if(MFC0) begin
state <= 16;
end
else if(MTC0) begin
state <= 17;
end
else if(LUI) begin
state <= 18;
end
else if(ADDI | SLTI) begin
state <= 20;
end
else if(ANDI | ORI |XORI | ADDIU | SLTIU) begin
state <= 21;
end
else if(MUL) begin
state <= 22;
end
else if(ERET) begin
state <= 32;
end
else if(BNE) begin
state <= 34;
end
end
2: begin
if (LW)begin
state <= 3;
end
else if (SW)begin
state <= 5;
end
else if (SH)begin
state <= 11;
end
else if (LH)begin
state <= 10;
end
end
3: begin
state <= 4;
end
4: begin
if(MemOK) begin
state <= 0;
end
end
5: begin
state <= 33;
end
6: begin
state <= 7;
end
7: begin
state <= 0;
end
8: begin
state <= 0;
end
9: begin
state <= 0;
end
10: begin
state <= 4;
end
11: begin
state <= 33;
end
12: begin
state <= 0;
end
13: begin
state <=0;
end
14: begin
state <= 0;
end
15: begin
state <= 0;
end
16: begin
state <= 0;
end
17: begin
state <= 0;
end
18: begin
state <= 0;
end
19: begin
state <= 7;
end
20: begin
state <= 24;
end
21: begin
state <= 24;
end
22: begin
state <= 7;
end
23: begin
if(MemOK) begin
state <= 1;
end
end
24: begin
state <= 0;
end
25: begin
state <= 26;
end
26: begin
state <= 27;
end
27: begin
state <= 0;
end
28: begin
state <= 31;
end
29: begin
state <= 30;
end
30: begin
state <= 0;
end
31: begin
state <= 0;
end
32: begin
state <= 28;
end
33: begin
if(MemOK) begin
state <= 0;
end
end
34: begin
state <= 0;
end
default: begin
state <= 0;
end
endcase
end
assign state0 = (state == 0);
assign state1 = (state == 1);
assign state2 = (state == 2);
assign state3 = (state == 3);
assign state4 = (state == 4);
assign state5 = (state == 5);
assign state6 = (state == 6);
assign state7 = (state == 7);
assign state8 = (state == 8);
assign state9 = (state == 9);
assign state10 = (state == 10);
assign state11 = (state == 11);
assign state13 = (state == 13);
assign state14 = (state == 14);
assign state15 = (state == 15);
assign state16 = (state == 16);
assign state17 = (state == 17);
assign state18 = (state == 18);
assign state19 = (state == 19);
assign state20 = (state == 20);
assign state21 = (state == 21);
assign state22 = (state == 22);
assign state23 = (state == 23);
assign state24 = (state == 24);
assign state25 = (state == 25);
assign state26 = (state == 26);
assign state27 = (state == 27);
assign state28 = (state == 28);
assign state29 = (state == 29);
assign state30 = (state == 30);
assign state31 = (state == 31);
assign state32 = (state == 32);
assign state33 = (state == 33);
assign state34 = (state == 34);
assign PCWrite = state9 | state13 | state14 | state15 | (state23 & MemOK)|state27 | state28;
assign PCWriteCond = state8 | state34;
assign IorD = state3 | state5 | state10 | state11;
assign MemRead = state0 | state3 | state10;
assign MemWrite = state5 | state11;
assign WriteData[2] = state18;
assign WriteData[1] = state13 | state15 | state16;
assign WriteData[0] = state4 | state16;
assign IRWrite = state23 & MemOK;
assign ALUop[1] = state6 | state19 | state20 | state21 | state22;
assign ALUop[0] = state8 | state34;
assign ALUSrcA[1] = state19;
assign ALUSrcA[0] = state2 | state6 | state8 | state20 | state21 | state22 | state34;
assign ALUSrcB[2] = state21;
assign ALUSrcB[1] = state1 | state2 | state20;
assign ALUSrcB[0] = state1 | state23;
assign RegWrite = (state4 & MemOK) | state7 | state13 | state15 | state16 | state18 | state24;
assign RegDst[1] = state13;
assign RegDst[0] = state7 | state15;
assign SaveHalf = state11;
assign LoadHalf = state10;
assign PCSource[2] = state27 | state28;
assign PCSource[1] = state9 | state13 | state14 | state15;
assign PCSource[0] = state8 | state14 | state15 | state27 | state34;
assign IsBne = state34;
assign ALUFunc =
{6{R}} & func |
{6{ADDI}} & 6'h20 |
{6{ADDIU}} & 6'h21 |
{6{SLTI}} & 6'h2A |
{6{SLTIU}} & 6'h2B |
{6{ANDI}} & 6'h24 |
{6{ORI}} & 6'h25 |
{6{XORI}} & 6'h26 |
{6{MUL}} & 6'h3f;
assign C0Write = state17 | state25 | state26 | state29 | state31;
assign C0Dst[1]= state0 | state25 | state29 | state28 | state31;
assign C0Dst[0]= state26 | state29 | state32;
assign C0Src[2]= state31;
assign C0Src[1]= state25 | state29;
assign C0Src[0]= state26 | state29;
assign CauseSource = state30;
assign SyscallInte = state30;
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> solve() { const int N = 3e6; vector<bool> isPrime(N, true); isPrime[0] = isPrime[1] = false; for (int i = 0; i * i < N; i++) { if (isPrime[i]) { for (int j = i * 2; j < N; j += i) { isPrime[j] = false; } } } int n; cin >> n; vector<int> a(n); for (int i = 0; i < n; i++) cin >> a[i]; int one = count(a.begin(), a.end(), 1); vector<int> ans; ans.push_back(a[0]); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (i == j) continue; vector<int> cand; if (isPrime[a[i] + a[j]]) { cand.push_back(a[i]); cand.push_back(a[j]); if (isPrime[a[i] + 1] && isPrime[a[j] + 1] && a[i] != 1 && a[j] == 1) { for (int k = 0; k < one - 1; k++) cand.push_back(1); return cand; } if (ans.size() < cand.size()) ans = cand; } } } if (one >= 2) { ans.assign(one, 1); } return ans; } int main() { auto ans = solve(); cout << ans.size() << endl; for (int x : ans) cout << x << ; cout << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__INV_SYMBOL_V
`define SKY130_FD_SC_HS__INV_SYMBOL_V
/**
* inv: Inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__inv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__INV_SYMBOL_V
|
//////////////////////////////////////////////////////////
// Copyright (c) 2006 Rice University //
// All Rights Reserved //
// This code is covered by the Rice-WARP license //
// See http://warp.rice.edu/license/ for details //
//////////////////////////////////////////////////////////
module radio_bridge
(
converter_clock_in,
converter_clock_out,
user_RSSI_ADC_clk,
radio_RSSI_ADC_clk,
user_RSSI_ADC_D,
user_EEPROM_IO_T,
user_EEPROM_IO_O,
user_EEPROM_IO_I,
radio_EEPROM_IO,
radio_DAC_I,
radio_DAC_Q,
radio_ADC_I,
radio_ADC_Q,
user_DAC_I,
user_DAC_Q,
user_ADC_I,
user_ADC_Q,
user_RF_gain,
user_BB_gain,
radio_RF_gain,
radio_BB_gain,
controller_spi_clk,
controller_spi_data,
controller_radio_cs,
controller_dac_cs,
controller_SHDN,
controller_TxEn,
controller_RxEn,
controller_RxHP,
controller_24PA,
controller_5PA,
controller_ANTSW,
controller_LED,
controller_RX_ADC_DCS,
controller_RX_ADC_DFS,
controller_RX_ADC_PWDNA,
controller_RX_ADC_PWDNB,
controller_DIPSW,
controller_RSSI_ADC_CLAMP,
controller_RSSI_ADC_HIZ,
controller_RSSI_ADC_SLEEP,
controller_RSSI_ADC_D,
controller_LD,
controller_RX_ADC_OTRA,
controller_RX_ADC_OTRB,
controller_RSSI_ADC_OTR,
controller_DAC_PLL_LOCK,
controller_DAC_RESET,
dac_spi_data,
dac_spi_cs,
dac_spi_clk,
radio_spi_clk,
radio_spi_data,
radio_spi_cs,
radio_SHDN,
radio_TxEn,
radio_RxEn,
radio_RxHP,
radio_24PA,
radio_5PA,
radio_ANTSW,
radio_LED,
radio_RX_ADC_DCS,
radio_RX_ADC_DFS,
radio_RX_ADC_PWDNA,
radio_RX_ADC_PWDNB,
radio_DIPSW,
radio_RSSI_ADC_CLAMP,
radio_RSSI_ADC_HIZ,
radio_RSSI_ADC_SLEEP,
radio_RSSI_ADC_D,
radio_LD,
radio_RX_ADC_OTRA,
radio_RX_ADC_OTRB,
radio_RSSI_ADC_OTR,
radio_DAC_PLL_LOCK,
radio_DAC_RESET
);
/**********************/
/* Clock & Data Ports */
/**********************/
input converter_clock_in;
output converter_clock_out;
input user_RSSI_ADC_clk;
output radio_RSSI_ADC_clk;
output [0:9] user_RSSI_ADC_D;
input user_EEPROM_IO_T;
input user_EEPROM_IO_O;
output user_EEPROM_IO_I;
output [0:15] radio_DAC_I;
output [0:15] radio_DAC_Q;
input [0:13] radio_ADC_I;
input [0:13] radio_ADC_Q;
input [0:15] user_DAC_I;
input [0:15] user_DAC_Q;
output [0:13] user_ADC_I;
output [0:13] user_ADC_Q;
input [0:1] user_RF_gain;
input [0:4] user_BB_gain;
output [0:1] radio_RF_gain;
output [0:4] radio_BB_gain;
/*******************************************/
/* Radio Controller <-> Radio Bridge Ports */
/*******************************************/
input controller_spi_clk;
input controller_spi_data;
input controller_radio_cs;
input controller_dac_cs;
input controller_SHDN;
input controller_TxEn;
input controller_RxEn;
input controller_RxHP;
input controller_24PA;
input controller_5PA;
input [0:1] controller_ANTSW;
input [0:2] controller_LED;
input controller_RX_ADC_DCS;
input controller_RX_ADC_DFS;
input controller_RX_ADC_PWDNA;
input controller_RX_ADC_PWDNB;
input controller_RSSI_ADC_CLAMP;
input controller_RSSI_ADC_HIZ;
input controller_RSSI_ADC_SLEEP;
input controller_DAC_RESET;
output [0:3] controller_DIPSW;
output [0:9] controller_RSSI_ADC_D;
output controller_LD;
output controller_RX_ADC_OTRA;
output controller_RX_ADC_OTRB;
output controller_RSSI_ADC_OTR;
output controller_DAC_PLL_LOCK;
/**************************************/
/* Radio Bridge <-> Radio Board Ports */
/**************************************/
output dac_spi_data;
output dac_spi_cs;
output dac_spi_clk;
output radio_spi_clk;
output radio_spi_data;
output radio_spi_cs;
output radio_SHDN;
output radio_TxEn;
output radio_RxEn;
output radio_RxHP;
output radio_24PA;
output radio_5PA;
output [0:1] radio_ANTSW;
output [0:2] radio_LED;
output radio_RX_ADC_DCS;
output radio_RX_ADC_DFS;
output radio_RX_ADC_PWDNA;
output radio_RX_ADC_PWDNB;
output [0:3] radio_DIPSW;
output radio_RSSI_ADC_CLAMP;
output radio_RSSI_ADC_HIZ;
output radio_RSSI_ADC_SLEEP;
output radio_DAC_RESET;
input [0:9] radio_RSSI_ADC_D;
input radio_LD;
input radio_RX_ADC_OTRA;
input radio_RX_ADC_OTRB;
input radio_RSSI_ADC_OTR;
input radio_DAC_PLL_LOCK;
inout radio_EEPROM_IO;
/**********************************/
/* Clocks and analog data signals */
/**********************************/
assign converter_clock_out = converter_clock_in;
assign radio_RSSI_ADC_clk = user_RSSI_ADC_clk;
assign user_ADC_I = radio_ADC_I;
assign user_ADC_Q = radio_ADC_Q;
assign radio_DAC_I = user_DAC_I;
assign radio_DAC_Q = user_DAC_Q;
assign radio_RF_gain = user_RF_gain;
assign radio_BB_gain = user_BB_gain;
/********************************************/
/* Instantiate the IOBUF for EEPROM Devices */
/********************************************/
IOBUF xIOBUF(
.T(user_EEPROM_IO_T),
.I(user_EEPROM_IO_O),
.O(user_EEPROM_IO_I),
.IO(radio_EEPROM_IO)
);
/*******************************************/
/* Radio Controller -> Radio Board Drivers */
/*******************************************/
assign dac_spi_clk = controller_spi_clk;
assign dac_spi_data = controller_spi_data;
assign dac_spi_cs = controller_dac_cs;
assign radio_spi_clk = controller_spi_clk;
assign radio_spi_data = controller_spi_data;
assign radio_spi_cs = controller_radio_cs;
assign radio_SHDN = controller_SHDN;
assign radio_TxEn = controller_TxEn;
assign radio_RxEn = controller_RxEn;
assign radio_RxHP = controller_RxHP;
assign radio_24PA = controller_24PA;
assign radio_5PA = controller_5PA;
assign radio_ANTSW = controller_ANTSW;
assign radio_LED = controller_LED;
assign radio_RX_ADC_DCS = controller_RX_ADC_DCS;
assign radio_RX_ADC_DFS = controller_RX_ADC_DFS;
assign radio_RX_ADC_PWDNA = controller_RX_ADC_PWDNA;
assign radio_RX_ADC_PWDNB = controller_RX_ADC_PWDNB;
assign radio_RSSI_ADC_CLAMP = controller_RSSI_ADC_CLAMP;
assign radio_RSSI_ADC_HIZ = controller_RSSI_ADC_HIZ;
assign radio_RSSI_ADC_SLEEP = controller_RSSI_ADC_SLEEP;
/*******************************************/
/* Radio Board -> Radio Controller Drivers */
/*******************************************/
assign controller_DIPSW = radio_DIPSW;
assign controller_RSSI_ADC_D = radio_RSSI_ADC_D;
assign user_RSSI_ADC_D = radio_RSSI_ADC_D;
assign controller_LD = radio_LD;
assign controller_RX_ADC_OTRA = radio_RX_ADC_OTRA;
assign controller_RX_ADC_OTRB = radio_RX_ADC_OTRB;
assign controller_RSSI_ADC_OTR = radio_RSSI_ADC_OTR;
assign controller_DAC_PLL_LOCK = radio_DAC_PLL_LOCK;
assign radio_DAC_RESET = controller_DAC_RESET;
endmodule |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Mar 31 18:24:55 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top mig_wrap_proc_sys_reset_1_0 -prefix
// mig_wrap_proc_sys_reset_1_0_ mig_wrap_proc_sys_reset_0_0_stub.v
// Design : mig_wrap_proc_sys_reset_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx485tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
module mig_wrap_proc_sys_reset_1_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { string s[] = { zero , one , two , three , four , five , six , seven , eight , nine , ten , eleven , twelve , thirteen , fourteen , fifteen , sixteen , seventeen , eighteen , nineteen }; string c[] = { , , twenty , thirty , forty , fifty , sixty , seventy , eighty , ninety }; int n; cin >> n; if (n < 20) { cout << s[n]; } else { if (n % 10 == 0) cout << c[n / 10]; else cout << c[n / 10] << - << s[n % 10]; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:13:27 05/30/2013
// Design Name:
// Module Name: sqncdetct
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sqncdetctr(input in, clk,rst,output detctd
);
localparam s0=5'b00001,
s1=5'b00010,
s2=5'b00100, ///one hot stat machin
s3=5'b01000,
s4=5'b10000;
reg [4:0] stat_reg,next_reg;
always @(posedge clk,posedge rst)
if(rst)
stat_reg<=s0;
else
stat_reg<=next_reg;
always@(*)
case(stat_reg)
s0: if(in) next_reg=s1;
else next_reg=s0;
s1: if(in) next_reg=s1;
else next_reg=s2;
s2: if(in) next_reg=s3;
else next_reg=s1;
s3: if(in) next_reg=s4;
else next_reg=s0;
s4: if(in) next_reg=s1;
else next_reg=s0;
default: next_reg=s0;
endcase
assign detctd= in?(stat_reg==s4):1'b0;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: DynamicDelay_Start.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module DynamicDelay_Start (
address,
clock,
q);
input [0:0] address;
input clock;
output [127:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "DynamicDelay_Start.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "1"
// Retrieval info: PRIVATE: WidthData NUMERIC "128"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "DynamicDelay_Start.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "128"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 1 0 INPUT NODEFVAL address[0..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 128 0 OUTPUT NODEFVAL q[127..0]
// Retrieval info: CONNECT: @address_a 0 0 1 0 address 0 0 1 0
// Retrieval info: CONNECT: q 0 0 128 0 @q_a 0 0 128 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL DynamicDelay_Start_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22O_TB_V
`define SKY130_FD_SC_HD__A22O_TB_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a22o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hd__a22o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22O_TB_V
|
module conmutacion
(
input [3:0] centenas,
input [3:0] decenas,
input [3:0] unidades,
input C,
input D,
input U,
input CLKOUTseg,
output reg [1:0] mostrar,
output reg [3:0] digito
);
reg logic0;
reg [1:0] titileo;
initial
begin
titileo = 0;
end
always@(posedge CLKOUTseg or C or D or U)
begin
if(C && D && U)
begin
/*if(titileo == 3)
begin
titileo <= 1;
end*/
titileo <= titileo + 1;
end
else
begin
if(D && U)
begin
/*if(titileo == 1)
begin
titileo <= 1;
end*/
titileo <= titileo + 1;
end
else
begin
if(U)
begin
titileo <= 1;
end
else
begin
titileo <= 0;
end
end
end
end
always@(posedge CLKOUTseg)
begin
case(titileo)
2'b00:
begin
mostrar = 2'b01;
digito = 0;
end
2'b01:
begin
mostrar = 2'b01;
digito = unidades;
end
2'b10:
begin
mostrar = 2'b10;
digito = decenas;
end
2'b11:
begin
mostrar = 2'b11;
digito = centenas;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> int main() { int n; scanf( %d , &n); int s = 0; s = n * (n + 1) / 2; if (s % 2 == 0) { printf( 0 ); } else { printf( 1 ); } return 0; } |
#include <bits/stdc++.h> int main() { int n, m; char ch[51]; scanf( %s , &ch); n = strlen(ch); if (n == 1) printf( %c , ch[0]); else { if (n % 2 == 0) m = (n / 2) - 1; else m = (n / 2); printf( %c , ch[m]); int j = 1; for (int i = 1; i <= n / 2; i++) { if (j < n) printf( %c , ch[m + i]); j++; if (j < n) printf( %c , ch[m - i]); j++; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { float n; cin >> n; cout << ceil(n / 5); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A311O_FUNCTIONAL_PP_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a311o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311O_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int MAXN = 16; int from[MAXN], to[MAXN], p[MAXN], q[MAXN]; bool w[MAXN][MAXN]; long long dp[1 << MAXN]; int main() { int n, m, a, b; long long y; cin >> n >> y >> m; fill(from, from + n, 0); fill(to, to + n, 0); fill(w[0], w[m], false); for (int i = 0; i < m; ++i) { cin >> a >> b; --a; --b; w[a][b] = true; } for (int k = 0; k < n; ++k) { for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { w[i][j] |= w[i][k] && w[k][j]; } } } for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { if (w[i][j]) { from[j] |= 1 << i; to[i] |= 1 << j; } } } fill(dp, dp + (1 << n), 0); dp[0] = 1; for (int i = 1; i < (1 << n); ++i) { for (int j = 0; j < n; ++j) { if ((i & (1 << j)) != 0 && (i & from[j]) == 0) { dp[i] += dp[i ^ (1 << j)]; } } } y -= 2001; m = (1 << n) - 1; if (y >= dp[m]) { cout << The times have changed << endl; return 0; } fill(p, p + n, -1); for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { if (p[j] != -1) { continue; } p[j] = i; { fill(dp, dp + (1 << n), 0); dp[0] = 1; for (int i = 1; i < (1 << n); ++i) { int k = n - __builtin_popcount(i); if (p[k] != -1) { int j = p[k]; if ((i & (1 << j)) != 0 && (i & from[j]) == 0) { dp[i] += dp[i ^ (1 << j)]; } } else { for (int j = 0; j < n; ++j) { if ((i & (1 << j)) != 0 && (i & from[j]) == 0) { dp[i] += dp[i ^ (1 << j)]; } } } } } if (y < dp[m]) { q[i] = j; break; } else { p[j] = -1; y -= dp[m]; } } } for (int i = 0; i < n; ++i) { printf( %d%c , q[i] + 1, i == n - 1 ? n : ); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input [31:0] cyc
);
`ifdef FAIL_ASSERT_1
assert property (@(posedge clk) cyc==3)
else $display("cyc != 3, cyc == %0d", cyc);
`endif
`ifdef FAIL_ASSERT_2
assert property (@(posedge clk) cyc!=3);
`endif
assert property (@(posedge clk) cyc < 100);
restrict property (@(posedge clk) cyc==1); // Ignored in simulators
// Unclocked is not supported:
// assert property (cyc != 6);
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/15.1/ip/merlin/altera_irq_bridge/altera_irq_bridge.v#1 $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
// -------------------------------------------------------
// Altera IRQ Bridge
//
// Parameters
// IRQ_WIDTH : $IRQ_WIDTH
//
// -------------------------------------------------------
//------------------------------------------
// Message Supression Used
// QIS Warnings
// 15610 - Warning: Design contains x input pin(s) that do not drive logic
//------------------------------------------
`timescale 1 ns / 1 ns
module altera_irq_bridge
#(
parameter IRQ_WIDTH = 32
)
(
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on clk
input clk,
(*altera_attribute = "-name MESSAGE_DISABLE 15610" *) // setting message suppression on reset
input reset,
input [IRQ_WIDTH - 1:0] receiver_irq,
output sender31_irq,
output sender30_irq,
output sender29_irq,
output sender28_irq,
output sender27_irq,
output sender26_irq,
output sender25_irq,
output sender24_irq,
output sender23_irq,
output sender22_irq,
output sender21_irq,
output sender20_irq,
output sender19_irq,
output sender18_irq,
output sender17_irq,
output sender16_irq,
output sender15_irq,
output sender14_irq,
output sender13_irq,
output sender12_irq,
output sender11_irq,
output sender10_irq,
output sender9_irq,
output sender8_irq,
output sender7_irq,
output sender6_irq,
output sender5_irq,
output sender4_irq,
output sender3_irq,
output sender2_irq,
output sender1_irq,
output sender0_irq
);
wire [31:0] receiver_temp_irq;
assign receiver_temp_irq = {{(32 - IRQ_WIDTH){1'b0}}, receiver_irq}; //to align a non-32bit receiver interface with 32 interfaces of the receiver
assign sender0_irq = receiver_temp_irq[0];
assign sender1_irq = receiver_temp_irq[1];
assign sender2_irq = receiver_temp_irq[2];
assign sender3_irq = receiver_temp_irq[3];
assign sender4_irq = receiver_temp_irq[4];
assign sender5_irq = receiver_temp_irq[5];
assign sender6_irq = receiver_temp_irq[6];
assign sender7_irq = receiver_temp_irq[7];
assign sender8_irq = receiver_temp_irq[8];
assign sender9_irq = receiver_temp_irq[9];
assign sender10_irq = receiver_temp_irq[10];
assign sender11_irq = receiver_temp_irq[11];
assign sender12_irq = receiver_temp_irq[12];
assign sender13_irq = receiver_temp_irq[13];
assign sender14_irq = receiver_temp_irq[14];
assign sender15_irq = receiver_temp_irq[15];
assign sender16_irq = receiver_temp_irq[16];
assign sender17_irq = receiver_temp_irq[17];
assign sender18_irq = receiver_temp_irq[18];
assign sender19_irq = receiver_temp_irq[19];
assign sender20_irq = receiver_temp_irq[20];
assign sender21_irq = receiver_temp_irq[21];
assign sender22_irq = receiver_temp_irq[22];
assign sender23_irq = receiver_temp_irq[23];
assign sender24_irq = receiver_temp_irq[24];
assign sender25_irq = receiver_temp_irq[25];
assign sender26_irq = receiver_temp_irq[26];
assign sender27_irq = receiver_temp_irq[27];
assign sender28_irq = receiver_temp_irq[28];
assign sender29_irq = receiver_temp_irq[29];
assign sender30_irq = receiver_temp_irq[30];
assign sender31_irq = receiver_temp_irq[31];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100005, INF = 0X3F3F3F3F; int n, tot; char s[N]; vector<int> ans; set<int> s1, s2; int main() { scanf( %s , s + 1), n = strlen(s + 1); for (int i = (1); i <= (n); ++i) { if (s[i] == L ) s1.insert(i); else s2.insert(i); } s1.insert(INF), s2.insert(INF); if (make_pair(-((int)(s1).size()), *s1.begin()) > make_pair(-((int)(s2).size()), *s2.begin())) swap(s1, s2); int go = *s1.begin(); for (int i = (1); i <= (n); ++i) { if (i & 1) { if (go == INF || (*s2.lower_bound(go) == INF && *s1.begin() != go && *s1.begin() < *s2.begin())) { ++tot; go = *s1.begin(); } s1.erase(go); ans.push_back(go); go = *s2.lower_bound(go); } else { if (go == INF || (*s1.lower_bound(go) == INF && *s2.begin() != go && *s2.begin() < *s1.begin())) { ++tot; go = *s2.begin(); } s2.erase(go); ans.push_back(go); go = *s1.lower_bound(go); } } printf( %d n , tot); for (auto x : ans) printf( %d , x); return 0; } |
/*
Copyright (C) {2014} {Ganesh Ajjanagadde} <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`default_nettype none
///////////////////////////////////////////////////////////////////////////////////////////////////
// vga: Generate XVGA display signals (640 x 480 @ 60Hz)
// essentially a copy of staff xvga module with different timings
// Credits: timings from Jose's project (Fall 2011),
// general code from staff xvga module (e.g Lab 3 - pong game)
///////////////////////////////////////////////////////////////////////////////////////////////////
module vga(input vclock,
output reg [9:0] hcount, // pixel number on current line
output reg [9:0] vcount, // line number
output reg vsync,hsync,blank);
// VGA (640x480) @ 60 Hz
parameter VGA_HBLANKON = 10'd639;
parameter VGA_HSYNCON = 10'd655;
parameter VGA_HSYNCOFF = 10'd751;
parameter VGA_HRESET = 10'd799;
parameter VGA_VBLANKON = 10'd479;
parameter VGA_VSYNCON = 10'd490;
parameter VGA_VSYNCOFF = 10'd492;
parameter VGA_VRESET = 10'd523;
// horizontal: 800 pixels total
// display 640 pixels per line
reg hblank,vblank;
wire hsyncon,hsyncoff,hreset,hblankon;
assign hblankon = (hcount == VGA_HBLANKON);
assign hsyncon = (hcount == VGA_HSYNCON);
assign hsyncoff = (hcount == VGA_HSYNCOFF);
assign hreset = (hcount == VGA_HRESET);
// vertical: 524 lines total
// display 480 lines
wire vsyncon,vsyncoff,vreset,vblankon;
assign vblankon = hreset & (vcount == VGA_VBLANKON);
assign vsyncon = hreset & (vcount == VGA_VSYNCON);
assign vsyncoff = hreset & (vcount == VGA_VSYNCOFF);
assign vreset = hreset & (vcount == VGA_VRESET);
// sync and blanking
wire next_hblank,next_vblank;
assign next_hblank = hreset ? 0 : hblankon ? 1 : hblank;
assign next_vblank = vreset ? 0 : vblankon ? 1 : vblank;
always @(posedge vclock) begin
hcount <= hreset ? 0 : hcount + 1;
hblank <= next_hblank;
hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync; // active low
vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;
vblank <= next_vblank;
vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync; // active low
blank <= next_vblank | (next_hblank & ~hreset);
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_vb_e
//
// Generated
// by: wig
// on: Sat Mar 3 11:02:57 2007
// cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../../udc.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_vb_e.v,v 1.1 2007/03/03 11:17:34 wig Exp $
// $Date: 2007/03/03 11:17:34 $
// $Log: inst_vb_e.v,v $
// Revision 1.1 2007/03/03 11:17:34 wig
// Extended ::udc: language dependent %AINS% and %PINS%: e.g. <VHDL>...</VHDL>
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1./03/01 16:28:38 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
udc: Verilog HEAD HOOK inst_bc1_i
//
//
// Start of Generated Module rtl of inst_vb_e
//
// No user `defines in this module
module inst_vb_e
//
// Generated Module inst_bc1_i
//
(
);
udc: Verilog PARA HOOK inst_bc1_i
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
udc: Verilog BODY HOOK inst_bc1_i
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_vb_e
//
udc: Verilog FOOT HOOK two lines inst_bc1_i
second line inst_bc1_i, config here inst_vb_e_rtl_conf and description verilog udc inst_bc2_i
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; vector<long long> adj[100005]; long long a[100005]; long long col; bool ok; bool dfs(long long v, long long par) { ok &= (col == a[v]); for (auto i : adj[v]) { if (i != par) dfs(i, v); } } bool fn(long long v) { bool res = 1; for (auto i : adj[v]) { ok = 1; col = a[i]; dfs(i, v); res &= ok; } return res; } int main() { int t = 1; ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); while (t--) { long long n; cin >> n; long long i; long long p = -1, q = -1; for (i = 1; i < n; i++) { long long x, y; cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } for (i = 0; i < n; i++) cin >> a[i + 1]; for (i = 1; i <= n; i++) { for (auto j : adj[i]) { if (a[j] != a[i]) { p = i; q = j; } } } if (q == -1) { cout << YES << endl; cout << 1 << endl; continue; } bool a1 = fn(p); bool a2 = fn(q); if (a1) { cout << YES << endl; cout << p << endl; } else if (a2) { cout << YES << endl; cout << q << endl; } else cout << NO << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3_2_V
`define SKY130_FD_SC_MS__NAND3_2_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand3_2 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand3_2 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3_2_V
|
#include <cassert> #include <cstdio> #include <cstdlib> #include <cstring> #include <algorithm> #include <iostream> #include <set> #include <map> #include <vector> #include <string> #include <cmath> #include <queue> #include <stack> #include <unordered_set> #include <unordered_map> #include <array> using namespace std; #define LL long long inline int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) { f = -1; } c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } inline void write(int x) { static int sta[35]; int top = 0; do { sta[top++] = x % 10, x /= 10; } while (x); while (top) putchar(sta[--top] + 48); } inline void writeln(int x) { if (x < 0) { putchar( - ); x = -x; } static int sta[35]; int top = 0; do { sta[top++] = x % 10, x /= 10; } while (x); while (top) putchar(sta[--top] + 48); putchar( n ); } inline LL readll() { LL x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) { f = -1; } c = getchar(); } while (c >= 0 && c <= 9 ) { x = x * 10 + c - 0 ; c = getchar(); } return x * f; } inline void writell(LL x) { if (x < 0) { putchar( - ); x = -x; } static LL sta[35]; int top = 0; do { sta[top++] = x % 10, x /= 10; } while (x); while (top) putchar(sta[--top] + 48); } inline void writellln(LL x) { if (x < 0) { putchar( - ); x = -x; } static LL sta[35]; int top = 0; do { sta[top++] = x % 10, x /= 10; } while (x); while (top) putchar(sta[--top] + 48); putchar( n ); } const int hashMod = 999983; template<class TYPENAME> class HashNode { public: TYPENAME val; int key, next; HashNode(TYPENAME _val, int _key, int _next): val(_val), key(_key), next(_next) {} bool isNull() { return key == -1; } }; template<class TYPENAME> class Hash { public: vector<HashNode<TYPENAME> > nodes; vector<int> d; int nodeN; Hash() { nodeN = 0; d = vector<int>(hashMod, -1); } void push(int key, TYPENAME val) { nodes.push_back(HashNode<TYPENAME>(val, key, d[key])); d[key] = nodeN++; } HashNode<TYPENAME> find(int key, TYPENAME val) { for (int p = d[key]; p != -1; p = nodes[p].next) { if (nodes[p].val == val) { return nodes[p]; } } return HashNode<TYPENAME>(val, -1, -1); } }; int n, c, q; vector<int> ii; vector<LL> jj; vector<int> p; vector<vector<LL> > ways, wayC; LL permContained(int l, int r, int cc) { if (l == -1) { return 1; // result for {-1, -1} } // otherwise, we can rotate (r, n) // we have n - r - 1 to rotate, and cc - (r - l) coins return ways[n - r - 1][cc - (r - l)]; } // we can discretize all the queries, so we have an index for each query // for each layer, we first save all the queries into boxes // and take them out bool pSmaller(const pair<int, int> &a, const pair<int, int> &b) { return p[a.second] < p[b.second]; } bool pGreater(const pair<int, int> &a, const pair<int, int> &b) { return p[a.second] > p[b.second]; } class Query { public: int ii, idx; LL jj; Query(int _idx, int _ii, LL _jj): idx(_idx), ii(_ii), jj(_jj) {} void print() { printf( Query(idx = %d, ii = %d, jj = %lld) , idx, ii, jj); } }; bool cmpQuery(const Query &a, const Query &b) { return a.jj < b.jj; } void solve() { n = read(); c = read(); q = read(); // printf( task: n = %d. c = %d, q = %d n , n, c, q); p = vector<int>(n); for (int i = 0; i < n; ++i) { p[i] = read(); } ii = vector<int>(q); jj = vector<LL>(q); for (int i = 0; i < q; ++i) { ii[i] = read() - 1; jj[i] = readll() - 1; // cout << ii[i] << << jj[i] << endl; } // for (int i = 0; i < q; ++i) { // // ii[i] = read() - 1; jj[i] = readll() - 1; // cout << ii[i] << << jj[i] << endl; // } wayC = vector<vector<LL> >(n); for (int i = 0; i < n; ++i) { wayC[i] = vector<LL>(c + 1, 0); wayC[i][0] = 1; } // wayC[n][c] = C(n, c) for (int i = 0; i < n; ++i) { for (int j = 1; j <= c; ++j) { // consider C(i, j) if (i < j) { wayC[i][j] = 0; } else { wayC[i][j] = wayC[i - 1][j] + wayC[i - 1][j - 1]; } } } // cout << finish wayC << endl; // for (int i = 0; i < q; ++i) { // // ii[i] = read() - 1; jj[i] = readll() - 1; // cout << ii[i] << << jj[i] << endl; // } ways = vector<vector<LL> >(n + 1); for (int i = 0; i <= n; ++i) { ways[i] = vector<LL>(c + 1, 1); } // ways[n][c] = C(n - 1, 0) + C(n - 1, 1) + ... + C(n - 1, c) // ways[n][c] = ways[n][c - 1] + wayC[n - 1][c] (n > 0) for (int i = 1; i <= n; ++i) { ways[i][0] = wayC[i - 1][0]; for (int j = 1; j <= c; ++j) { ways[i][j] = ways[i][j - 1] + wayC[i - 1][j]; // printf( ways(len = %d, c = %d) = %lld n , i, j, ways[i][j]); } } // cout << finish ways << endl; // for (int i = 0; i < q; ++i) { // // ii[i] = read() - 1; jj[i] = readll() - 1; // cout << ii[i] << << jj[i] << endl; // } // now ways[len][c] = ways(n, c) // we should build a deque for each 0 .. c, contains // the [l, r] as the leftmost rotation(not over c) // and sorted by the lex order. Our queries are all on layer c(we can use at most c coins) // we sort all the jj, and scan the deque, every time we find an [l, r] so that jj is behind this // we know that [0 .. r] has been decided for this jj query. if ii <= r, we can return the query result // otherwise we want to decide the remaining part jj - ord([l, r]) = jj , with coins c - r + l, // and start from r + 1 // for each c, we can decide p[l] permutations before using [l, r] started at l for each l in [0, n) // so the query becomes another query (c - r + l, jj + p[r + 1], ii) on layer c - r + l // finally we have all queryies on layer 0, so there is only one state for queries // queries down to here must asks something hard to decide, and here we must have jj = 1 // then we just return i-th // first to make deques for each c = [0 .. c] vector<deque<pair<int, int> > > dq(c + 1); for (int cc = 0; cc <= c; ++cc) { // dq[cc].push_back({-1, -1}); // no change dq[cc].push_back({n - 1, n - 1}); for (int i = n - 1; i >= 0; --i) { vector<pair<int, int> > lft, rgt; for (int j = i + 1; j <= i + cc && j < n; ++j) { // we have rotations [i, j] // current deque has all permutations with i-th = p[i] // so [i, j] is with i-th = p[j] // we should divide it into two parts: p[j] < p[i] && p[j] > p[i] // for p[j] < p[i], we insert it at front, from the order p[j] large to small // for p[j] > p[i], we insert it at back, from small to large // printf( p[j = %d] = %d, p[i = %d] = %d n , j, p[j], i, p[i]); if (p[j] < p[i]) { lft.push_back({i, j}); } else { rgt.push_back({i, j}); } } sort(lft.begin(), lft.end(), pGreater); sort(rgt.begin(), rgt.end(), pSmaller); for (int i = 0; i < lft.size(); ++i) { dq[cc].push_front(lft[i]); } for (int i = 0; i < rgt.size(); ++i) { dq[cc].push_back(rgt[i]); } } // cout << c = << cc << endl; // for (auto pr: dq[cc]) { // printf( (%d, %d) , pr.first, pr.second); // } // putchar( n ); } // cout << finish creating deques << endl; // int mc = 0; // vector<int> queryIdx = discretize(jj, mc); // vector<LL> ts(mc + 1, 0); // for (int i = 0; i < q; ++i) { // ts[queryIdx[i]] = jj[i]; // } // vector<vector<vector<Query> > > ids(c + 1); // for (int i = 0; i <= c; ++i) { // ids[i] = vector<vector<Query> >(mc + 1); // } // for (int i = 0; i < q; ++i) { // ids[c][queryIdx[i]].push_back(Query(i, ii[i], queryIdx[i], jj[i])); // } vector<int> ans(q, -1); // for (int i = 0; i < q; ++i) { // ans[i] = -1; // } // for (int i = 0; i < q; ++i) { // cout << ans[i] << ; // } // cout << endl; vector<vector<Query> > que(c + 1); for (int i = 0; i < q; ++i) { que[c].push_back(Query(i, ii[i], jj[i])); // que[c].back().print(); } vector<vector<LL> > pp(c + 1); // pp[cc][l]: the permutations before the first [l, r] started at l(l in [0, n - 1)) for (int cc = 0; cc <= c; ++cc) { pp[cc] = vector<LL>(n, -1); LL perms = 0; int ll, rr; for (pair<int, int> pr: dq[cc]) { ll = pr.first; rr = pr.second; if (ll == -1) { continue; } if (pp[cc][ll] == -1) { pp[cc][ll] = perms; // printf( pp[c = %d][l = %d] = %lld, from (l = %d, r = %d) n , cc, ll, pp[cc][ll], ll, rr); } perms += permContained(ll, rr, cc); } // pp[cc][n - 1] = perms - 1; for (int i = n - 2; i >= 0; --i) { pp[cc][i] = min(pp[cc][i], pp[cc][i + 1]); } for (int i = 0; i < n; ++i) { // printf( pp[c = %d][l = %d] = %lld n , cc, i, pp[cc][i]); } // how to deal with -1, -1? it means no rotation at all // and contains exactly 1 permutation p0 ... p_{n - 1} } // cout << finish calculating pp s << endl; for (int cc = c; cc >= 0; --cc) { // work on layer cc if (que[cc].size() == 0) { continue; } sort(que[cc].begin(), que[cc].end(), cmpQuery); // now we have queries saved in que[cc] // and sorted by order of jj // for [l, r] on layer cc, the undecided part is (r, n), len = n - r - 1 // so it contains ways[n - r - 1][cc - (r - l)] // we go from the beginning of dq[cc], and use a pointer in que[cc] for current // when we want to insert a new query c , jj , ii, we just do que[c ].push_back(Query(idx, ii, jj )) // TODO: !!!!! int qcur = 0; LL currPerm = 0; // cout << coin << cc << : ; // for (int i = 0; i < que[cc].size(); ++i) { // // printf( Query(idx = %d, ii = %d, jj = %lld) , que[cc][i].idx, que[cc][i].ii, que[cc][i].jj); // que[cc][i].print(); // } // cout << endl; // for (int i = 0; i < q; ++i) { // cout << ans[i] << ; // } // cout << endl; for (pair<int, int> pr: dq[cc]) { int ll = pr.first, rr = pr.second; // printf( (%d, %d) , ll, rr); // printf( l = %d, r = %d, cc = %d, currPerm = %lld n , ll, rr, cc, currPerm); LL newPerm = permContained(ll, rr, cc); // printf( new perm = %lld n , newPerm); while (qcur < que[cc].size() && que[cc][qcur].jj < currPerm + newPerm) { int cii = que[cc][qcur].ii; LL cjj = que[cc][qcur].jj; int cidx = que[cc][qcur].idx; // printf( qcur = %d: idx = %d, ii = %d, jj = %lld n , qcur, cidx, cii, cjj); if (ll == -1 || cii < ll) { // cout << quit1 << endl; ans[cidx] = p[cii]; ++qcur; continue; } if (cii >= ll && cii <= rr) { // cout << quit2 << endl; ans[cidx] = p[rr - (cii - ll)]; ++qcur; continue; } // otherwise, it is not determined // we should insert it into cc - (rr - ll) int nc = cc - (rr - ll); // what is the rank of the permutation in nc? // all [0, r] fixed, so we need to find the (que[cc][qucr].jj - currPerm)-th // in dq[cc], after pp[cc][r + 1] if (rr >= n - 1) { // cout << quit-1 << endl; ans[cidx] = -1; ++qcur; continue; } // otherwise, we should insert it to layer nc que[nc].push_back(Query(cidx, cii, pp[nc][rr + 1] + cjj - currPerm)); ++qcur; // cout << quit0 << endl; } currPerm += newPerm; } } for (int i = 0; i < q; ++i) { writeln(ans[i]); } } int main() { // std::ios::sync_with_stdio(false); // std::cin.tie(0); int t = read(); for (int i = 0; i < t; ++i) { solve(); } return 0; } |
module sgpr_simxlsu_wr_port_mux
(/*AUTOARG*/
// Outputs
muxed_port_wr_en, muxed_port_wr_addr, muxed_port_wr_data,
muxed_port_wr_mask,
// Inputs
//**CHANGE [PSP]
//**add ports 9 for SALU integration
wr_port_select, port0_wr_en, port0_wr_addr, port0_wr_data,
port0_wr_mask, port1_wr_en, port1_wr_addr, port1_wr_data,
port1_wr_mask, port2_wr_en, port2_wr_addr, port2_wr_data,
port2_wr_mask, port3_wr_en, port3_wr_addr, port3_wr_data,
port3_wr_mask, port4_wr_en, port4_wr_addr, port4_wr_data,
port4_wr_mask, port5_wr_en, port5_wr_addr, port5_wr_data,
port5_wr_mask, port6_wr_en, port6_wr_addr, port6_wr_data,
port6_wr_mask, port7_wr_en, port7_wr_addr, port7_wr_data,
port7_wr_mask, port8_wr_en, port8_wr_addr, port8_wr_data,
port8_wr_mask, port9_wr_en, port9_wr_addr, port9_wr_data,
port9_wr_mask
//**
);
output [3:0] muxed_port_wr_en;
output [8:0] muxed_port_wr_addr;
output [127:0] muxed_port_wr_data;
output [127:0] muxed_port_wr_mask;
input [15:0] wr_port_select;
input[3:0] port0_wr_en;
input [8:0] port0_wr_addr;
input [127:0] port0_wr_data;
input [127:0] port0_wr_mask;
input [3:0] port1_wr_en;
input [8:0] port1_wr_addr;
input [127:0] port1_wr_data;
input [127:0] port1_wr_mask;
input [3:0] port2_wr_en;
input [8:0] port2_wr_addr;
input [127:0] port2_wr_data;
input [127:0] port2_wr_mask;
input [3:0] port3_wr_en;
input [8:0] port3_wr_addr;
input [127:0] port3_wr_data;
input [127:0] port3_wr_mask;
input [3:0] port4_wr_en;
input [8:0] port4_wr_addr;
input [127:0] port4_wr_data;
input [127:0] port4_wr_mask;
input [3:0] port5_wr_en;
input [8:0] port5_wr_addr;
input [127:0] port5_wr_data;
input [127:0] port5_wr_mask;
input [3:0] port6_wr_en;
input [8:0] port6_wr_addr;
input [127:0] port6_wr_data;
input [127:0] port6_wr_mask;
input [3:0] port7_wr_en;
input [8:0] port7_wr_addr;
input [127:0] port7_wr_data;
input [127:0] port7_wr_mask;
input [3:0] port8_wr_en;
input [8:0] port8_wr_addr;
input [127:0] port8_wr_data;
input [127:0] port8_wr_mask;
reg [3:0] muxed_port_wr_en;
reg [8:0] muxed_port_wr_addr;
reg [127:0] muxed_port_wr_data;
reg [127:0] muxed_port_wr_mask;
//**CHANGE [PSP]
//** add extra SALU port
input [3:0] port9_wr_en;
input [8:0] port9_wr_addr;
input [127:0] port9_wr_data;
input [127:0] port9_wr_mask;
//**
always @ (
wr_port_select or
port0_wr_en or
port0_wr_addr or
port0_wr_data or
port0_wr_mask or
port1_wr_en or
port1_wr_addr or
port1_wr_data or
port1_wr_mask or
port2_wr_en or
port2_wr_addr or
port2_wr_data or
port2_wr_mask or
port3_wr_en or
port3_wr_addr or
port3_wr_data or
port3_wr_mask or
port4_wr_en or
port4_wr_addr or
port4_wr_data or
port4_wr_mask or
port5_wr_en or
port5_wr_addr or
port5_wr_data or
port5_wr_mask or
port6_wr_en or
port6_wr_addr or
port6_wr_data or
port6_wr_mask or
port7_wr_en or
port7_wr_addr or
port7_wr_data or
port7_wr_mask or
port8_wr_en or
port8_wr_addr or
port8_wr_data or
port8_wr_mask or
//**CHANGE
port9_wr_en or
port9_wr_addr or
port9_wr_data or
port9_wr_mask
//**
) begin
casex(wr_port_select)
16'h0001:
begin
muxed_port_wr_en <= port0_wr_en;
muxed_port_wr_addr <= port0_wr_addr;
muxed_port_wr_data <= port0_wr_data;
muxed_port_wr_mask <= port0_wr_mask;
end
16'h0002:
begin
muxed_port_wr_en <= port1_wr_en;
muxed_port_wr_addr <= port1_wr_addr;
muxed_port_wr_data <= port1_wr_data;
muxed_port_wr_mask <= port1_wr_mask;
end
16'h0004:
begin
muxed_port_wr_en <= port2_wr_en;
muxed_port_wr_addr <= port2_wr_addr;
muxed_port_wr_data <= port2_wr_data;
muxed_port_wr_mask <= port2_wr_mask;
end
16'h0008:
begin
muxed_port_wr_en <= port3_wr_en;
muxed_port_wr_addr <= port3_wr_addr;
muxed_port_wr_data <= port3_wr_data;
muxed_port_wr_mask <= port3_wr_mask;
end
16'h0010:
begin
muxed_port_wr_en <= port4_wr_en;
muxed_port_wr_addr <= port4_wr_addr;
muxed_port_wr_data <= port4_wr_data;
muxed_port_wr_mask <= port4_wr_mask;
end
16'h0020:
begin
muxed_port_wr_en <= port5_wr_en;
muxed_port_wr_addr <= port5_wr_addr;
muxed_port_wr_data <= port5_wr_data;
muxed_port_wr_mask <= port5_wr_mask;
end
16'h0040:
begin
muxed_port_wr_en <= port6_wr_en;
muxed_port_wr_addr <= port6_wr_addr;
muxed_port_wr_data <= port6_wr_data;
muxed_port_wr_mask <= port6_wr_mask;
end
16'h0080:
begin
muxed_port_wr_en <= port7_wr_en;
muxed_port_wr_addr <= port7_wr_addr;
muxed_port_wr_data <= port7_wr_data;
muxed_port_wr_mask <= port7_wr_mask;
end
16'h0100:
begin
muxed_port_wr_en <= port8_wr_en;
muxed_port_wr_addr <= port8_wr_addr;
muxed_port_wr_data <= port8_wr_data;
muxed_port_wr_mask <= port8_wr_mask;
end
//**CHANGE [PSP]
//**actual port assigning for SALU
16'h0200:
begin
muxed_port_wr_en <= port9_wr_en;
muxed_port_wr_addr <= port9_wr_addr;
muxed_port_wr_data <= port9_wr_data;
muxed_port_wr_mask <= port9_wr_mask;
end
//**
16'b0000:
begin
muxed_port_wr_en <= 1'b0;
muxed_port_wr_addr <= {9{1'bx}};
muxed_port_wr_data <= {64{1'bx}};
muxed_port_wr_mask <= {64{1'bx}};
end
default:
begin
muxed_port_wr_en <= 1'bx;
muxed_port_wr_addr <= {9{1'bx}};
muxed_port_wr_data <= {64{1'bx}};
muxed_port_wr_mask <= {64{1'bx}};
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long t[500005], mid; long long l[500005], r[500005], h[500005]; struct st { long long h, cnt; }; stack<st> q; int main() { cin.sync_with_stdio(0); int n; cin >> n; for (int i = 1; i <= n; i++) cin >> t[i]; q.push({-1, 1}); for (int i = 1; i <= n; i++) { long long c = 0, h = 0; while (q.top().h >= t[i]) { c += q.top().cnt; h += q.top().cnt * q.top().h; q.pop(); } l[i] = l[i - 1] - h + (t[i] * (c + 1)); q.push({t[i], c + 1}); } while (q.size()) q.pop(); q.push({0, 1}); for (int i = n; i > 0; i--) { long long c = 0, h = 0; while (q.top().h >= t[i]) { c += q.top().cnt; h += q.top().cnt * q.top().h; q.pop(); } r[i] = r[i + 1] - h + (t[i] * (c + 1)); q.push({t[i], c + 1}); } while (q.size()) q.pop(); long long ms = 0; for (int i = 1; i <= n; i++) if (l[i] + r[i] - t[i] > ms) ms = l[i] + r[i] - t[i], mid = i; h[mid] = t[mid]; for (int i = mid + 1; i <= n; i++) { h[i] = min(h[i - 1], t[i]); } for (int i = mid - 1; i > 0; i--) { h[i] = min(h[i + 1], t[i]); } for (int i = 1; i <= n; i++) cout << h[i] << ; } |
/*main function
1)receiving packet from inputctrl module,and forwarding packets to classification module and offset module
*/
module INGRESS_CTRL(
input clk,
input reset,
input in_inputctrl_pkt_wr,// the packet write request of input_ctrl moudle to inputctrl module
input [133:0] in_inputctrl_pkt,// the packet of input_ctrl moudle to inputctrl module
input in_inputctrl_valid_wr,//the valid flag write request of input_ctrl moudle to inputctrl module
input in_inputctrl_valid,// the valid flag of input_ctrl moudle to inputctrl module
output out_inputctrl_pkt_almostfull,
output reg out_class_key_wr,// the packet write request of input_ctrl moudle to classification module
output reg [133:0] out_class_key,// the packet of input_ctrl moudle to classification module
input in_class_key_almostfull,
output reg out_class_valid,// the valid flag of input_ctrl moudle to classification module
output reg out_class_valid_wr,//the valid flag write request of input_ctrl moudle to classification module
output reg out_offset_pkt_wr,// the packet write request of input_ctrl moudle to offset module
output reg [133:0] out_offset_pkt,// the packet of input_ctrl moudle to offset module
output reg out_offset_valid,// the valid flag of input_ctrl moudle to offset module
output reg out_offset_valid_wr,//the valid flag write request of iinput_ctrl moudle to offset module
input in_offset_pkt_almostfull
);
reg [2:0] current_state;
reg [2:0] counter;
wire in_inputctrl_valid_q;
wire in_inputctrl_valid_empty;
reg out_inputctrl_valid_rd;
wire [7:0] out_inputctrl_pkt_usedw;
assign out_inputctrl_pkt_almostfull = out_inputctrl_pkt_usedw[7];
reg out_inputctrl_pkt_rd;
wire [133:0]in_inputctrl_pkt_q;
parameter idle_s = 3'd0,
send_meta1_s = 3'd1,
send_meta2_s = 3'd2,
send_key_s = 3'd3,
send_data_s = 3'd4,
discard_s=3'd5;
always@(posedge clk or negedge reset) begin
if(!reset) begin
out_class_key_wr<=1'b0;
out_class_key<=134'b0;
out_class_valid<=1'b1;
out_class_valid_wr<=1'b0;
out_offset_pkt_wr<=1'b0;
out_offset_pkt<=134'b0;
out_offset_valid<=1'b0;
out_offset_valid_wr<=1'b0;
out_inputctrl_valid_rd<=1'b0;
out_inputctrl_pkt_rd<=1'b0;
counter<=3'b0;
current_state<=idle_s;
end
else begin
case(current_state)
idle_s:begin
counter<=3'b0;
out_class_key_wr<=1'b0;
out_class_valid_wr<=1'b0;
out_offset_pkt_wr<=1'b0;
out_offset_valid_wr<=1'b0;
out_offset_valid<=1'b0;
if((in_offset_pkt_almostfull==1'b0) && (in_inputctrl_valid_empty==1'b0) && (in_class_key_almostfull==1'b0))begin
if(in_inputctrl_valid_q==1'b1)begin
out_inputctrl_valid_rd<=1'b1;
out_inputctrl_pkt_rd<=1'b1;
current_state<=send_meta1_s;
end
else begin
out_inputctrl_valid_rd<=1'b1;
out_inputctrl_pkt_rd<=1'b1;
current_state<=discard_s;
end
end
else begin
out_inputctrl_valid_rd<=1'b0;
out_inputctrl_pkt_rd<=1'b0;
current_state<=idle_s;
end
end
send_meta1_s:begin//forward to first pat metadata
out_inputctrl_valid_rd<=1'b0;
out_offset_pkt_wr<=1'b1;
out_offset_pkt<=in_inputctrl_pkt_q;
current_state<=send_meta2_s;
end
send_meta2_s:begin//forward to second pat metadata
out_offset_pkt<=in_inputctrl_pkt_q;
current_state<=send_key_s;
end
send_key_s:begin//forward to first pat packet
out_offset_pkt_wr<=1'b1;
out_class_key_wr<=1'b1;
out_offset_pkt<=in_inputctrl_pkt_q;
out_class_key<=in_inputctrl_pkt_q;
counter<=counter+1'b1;//the number of forward to packet
if(in_inputctrl_pkt_q[133:132]==2'b10)begin
out_inputctrl_pkt_rd<=1'b0;
out_offset_valid_wr<=1'b1;
out_offset_valid<=1'b1;
out_class_valid_wr<=1'b1;
current_state<=idle_s;
end
else begin
out_inputctrl_pkt_rd<=1'b1;
out_offset_valid_wr<=1'b0;
out_offset_valid<=1'b0;
if(counter<3'd3)begin //four packets forward to inputctrl
out_class_valid_wr<=1'b0;
current_state<=send_key_s;
end
else begin
out_class_valid_wr<=1'b1;
current_state<=send_data_s;
end
end
end
send_data_s:begin//forward other packets to offset module
out_class_key_wr<=1'b0;
out_class_valid_wr<=1'b0;
if(in_inputctrl_pkt_q[133:132]==2'b10)begin
out_inputctrl_pkt_rd<=1'b0;
out_offset_pkt_wr<=1'b1;
out_offset_pkt<=in_inputctrl_pkt_q;
out_offset_valid_wr<=1'b1;
out_offset_valid<=1'b1;
current_state<=idle_s;
end
else begin
out_inputctrl_pkt_rd<=1'b1;
out_offset_pkt_wr<=1'b1;
out_offset_pkt<=in_inputctrl_pkt_q;
current_state<=send_data_s;
end
end
discard_s:begin
out_inputctrl_valid_rd<=1'b0;
if(in_inputctrl_pkt_q[133:132]==2'b10)begin
out_inputctrl_pkt_rd<=1'b0;
current_state<=idle_s;
end
else begin
out_inputctrl_pkt_rd<=1'b1;
current_state<=discard_s;
end
end
default:;
endcase
end
end
fifo_64_1 FIFO_VALID_input_ctrl (
.aclr(!reset),
.data(in_inputctrl_valid),
.clock(clk),
.rdreq(out_inputctrl_valid_rd),
.wrreq(in_inputctrl_valid_wr),
.q(in_inputctrl_valid_q),
.empty(in_inputctrl_valid_empty)
);
fifo_256_134 FIFO_PKT_input_ctrl (
.aclr(!reset),
.data(in_inputctrl_pkt),
.clock(clk),
.rdreq(out_inputctrl_pkt_rd),
.wrreq(in_inputctrl_pkt_wr),
.q(in_inputctrl_pkt_q),
.usedw(out_inputctrl_pkt_usedw)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7, siz = 1e6 + 5; long long t, n, m, k, a[siz], dp[5002][5002], dp2[5002]; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> t; while (t--) { cin >> n; string s; cin >> s; s = 0 + s; for (long long i = 1; i <= n + 1; i++) for (long long j = i + 1; j <= n + 1; j++) dp[i][j] = 0; for (long long i = n; i >= 1; i--) { for (long long j = i - 1; j >= 1; j--) { if (s[i] == s[j]) { dp[j][i] = 1 + dp[j + 1][i + 1]; } } } long long ans = 0; for (long long i = 1; i <= n; i++) { dp2[i] = n - i + 1; for (long long j = 1; j < i; j++) { if (s[i] > s[j]) dp2[i] = max(dp2[j] + n - i + 1, dp2[i]); else if (s[i] == s[j]) { if (s[i + dp[j][i]] > s[j + dp[j][i]]) { dp2[i] = max(dp2[i], dp2[j] + n - (i + dp[j][i]) + 1); } } } ans = max(ans, dp2[i]); } cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; double e[1010][510]; double c[510], b[510]; int main() { int n, m, in, im; scanf( %d%d%d%d , &n, &m, &in, &im); if (m == 1) { e[n][1] = 0.0; for (int i = n - 1; i >= in; --i) { e[i][1] = 2 + e[i + 1][1]; } printf( %.9lf n , e[in][1]); return 0; } if (im > m / 2) im = m + 1 - im; int g = (m + 1) / 2; for (int i = 1; i <= g; ++i) e[n][i] = 0.0; for (int r = n - 1; r >= in; --r) { c[1] = 1.5 + e[r + 1][1] * 0.5; b[1] = 0.5; for (int i = 2; i <= g; ++i) { double w = 1.0 - 0.25 - b[i - 1] * 0.25; c[i] = (1.0 + 0.25 * e[r + 1][i] + 0.25 * c[i - 1]) / w; b[i] = (0.25) / w; } if (m % 2 == 0) { e[r][g] = c[g] / (1.0 - b[g]); } else { e[r][g] = (c[g] + b[g] * c[g - 1]) / (1.0 - b[g] * b[g - 1]); } for (int i = g - 1; i >= 1; --i) e[r][i] = c[i] + b[i] * e[r][i + 1]; } printf( %.9lf n , e[in][im]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; cin >> n; vector<long long> dp; dp.push_back(0); dp.push_back(1); while (dp.back() <= n - 1) { dp.push_back(dp[dp.size() - 1] + dp[dp.size() - 2] + 1); } cout << dp.size() - 2 << endl; } |
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
/*
*******************************************************************************
* File Name : ada_bram.v
* Project : ADA processor
* Version : 0.1
* Date : Sept 1st, 2014
* Author : Angel Terrones <>
*
* Disclaimer : Copyright (c) 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Block RAM used for the Internal Memory
*******************************************************************************
*/
module ada_bram #(
parameter DATA = 32,
parameter ADDR = 8
)(
// Port A
input a_clk,
input a_wr,
input [ADDR-1:0] a_addr,
input [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
// Port B
input b_clk,
input b_wr,
input [ADDR-1:0] b_addr,
input [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
//--------------------------------------------------------------------------
// Shared memory
//--------------------------------------------------------------------------
reg [DATA-1:0] mem [(2**ADDR)-1:0];
// initiate the memory to zeros. For testing.
// TODO: Add interface to modify this memory using a debug interface
integer i;
initial begin
for (i=0; i < 256; i=i+1)
mem[i] = 32'b0;
end
//--------------------------------------------------------------------------
// Port A
//--------------------------------------------------------------------------
always @(posedge a_clk) begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
//--------------------------------------------------------------------------
// Port B
//--------------------------------------------------------------------------
always @(posedge b_clk) begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: psi2c_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2.16 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module psi2c_fifo (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q);
input aclr;
input clock;
input [11:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [11:0] q;
wire sub_wire0;
wire sub_wire1;
wire [11:0] sub_wire2;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [11:0] q = sub_wire2[11:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.almost_empty (),
.almost_full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 12,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "12"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "12"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "12"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 12 0 INPUT NODEFVAL "data[11..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 12 0 data 0 0 12 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL psi2c_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL psi2c_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL psi2c_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL psi2c_fifo.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL psi2c_fifo_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL psi2c_fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ================================================================================
// Legal Notice: Copyright (C) 1991-2008 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
// ================================================================================
//
`timescale 1ns / 1ps
module lpf_tb;
// inputs
reg clk;
reg reset_n;
wire clken;
reg[31:0] in_data;
wire[31:0] out_data;
wire[1:0] in_error;
wire[1:0] out_error;
reg in_valid;
wire out_ready;
wire in_ready;
wire out_valid;
reg start;
reg end_test;
integer data_in_int,data_file_in,data_file_out;
integer data_out_int;
parameter MAXVAL_c = ;
parameter OFFSET_c = ;
initial
begin
data_file_in = $fopen("lpf_tb_input.txt","r");
data_file_out = $fopen("lpf_tb_output.txt");
///////////////////////////////////////////////////////////////////////////////////////////////
// Reset Generation
#0 clk = 1'b0;
#0 reset_n = 1'b0;
#92 reset_n = 1'b1;
end
///////////////////////////////////////////////////////////////////////////////////////////////
// Clock Generation
///////////////////////////////////////////////////////////////////////////////////////////////
always
begin
if (end_test == 1'b1)
begin
clk = 1'b0;
$fclose(data_file_in);
$fclose(data_file_out);
$finish; //stop
end
else
begin
#5 clk = 1'b1;
#5 clk = 1'b0;
end
end
// clock enable
// always enabled
assign clken = 1'b1;
// for example purposes, the ready wire is always asserted.
assign out_ready = 1'b1;
// no input error
assign in_error = 2'b0;
// start valid for first cycle to indicate that the file reading should start.
always @ (posedge clk)
begin
if (reset_n == 1'b0)
start <= 1'b1;
else
begin
if (in_valid == 1'b1 & in_ready == 1'b1)
start <= 1'b0;
end
end
//////////////////////////////////////////////////////////////////////////////////////////////
// Read input data from files
//////////////////////////////////////////////////////////////////////////////////////////////
integer c_x;
always @ (posedge clk)
begin
if (reset_n == 1'b0)
begin
in_data <= 32'b0;
in_valid <= 1'b0;
end_test <= 1'b0;
end
else
begin
if (!$feof(data_file_in))
begin
if ((in_valid == 1'b1 & in_ready == 1'b1) ||
(start == 1'b1 & !(in_valid == 1'b1 & in_ready == 1'b0)))
begin
c_x = $fscanf(data_file_in,"%d",data_in_int);
in_data <= data_in_int;
in_valid <= 1'b1;
end
end
else
begin
if (end_test == 1'b0)
begin
if (in_valid == 1'b1 & in_ready == 1'b1)
begin
end_test <= 1'b1;
in_valid <= 1'b0;
in_data <= 32'b0;
end
else
begin
in_valid <= 1'b1;
in_data <= data_in_int;
end
end
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////
// Write data output to Files
////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge clk)
begin
if (reset_n == 1'b1 & out_valid == 1'b1 & out_ready == 1'b1)
begin
data_out_int = out_data;
$fdisplay(data_file_out, "%d", (data_out_int < MAXVAL_c) ? data_out_int : data_out_int - OFFSET_c - 1);
end
end
////////////////////////////////////////////////////////////////////////////////////////////
// CIC Module Instantiation
////////////////////////////////////////////////////////////////////////////////////////////
lpf lpf_inst (
.clk(clk),
.clken(clken),
.reset_n(reset_n),
.in_ready(in_ready),
.in_valid(in_valid),
.in_data(in_data),
.out_data(out_data),
.in_error(in_error),
.out_error(out_error),
.out_ready(out_ready),
.out_valid(out_valid)
);
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the TRDB DC2 digital camera. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_dc2 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DC_ROW_START = 16'h000C;
parameter DC_COLUMN_START = 16'h001E;
parameter DC_ROW_WIDTH = 16'h0400;
parameter DC_COLUMN_WIDTH = 16'h0500;
parameter DC_H_BLANK_B = 16'h0088; // 16'h018C;
parameter DC_V_BLANK_B = 16'h0019; // 16'h0032;
parameter DC_H_BLANK_A = 16'h00C6;
parameter DC_V_BLANK_A = 16'h0019;
parameter DC_SHUTTER_WIDTH = 16'h0432;
parameter DC_ROW_SPEED = 16'h0011;
parameter DC_EXTRA_DELAY = 16'h0000;
parameter DC_SHUTTER_DELAY = 16'h0000;
parameter DC_RESET = 16'h0008;
parameter DC_FRAME_VALID = 16'h0000;
parameter DC_READ_MODE_B = 16'h0001;
parameter DC_READ_MODE_A = 16'h040C;
parameter DC_DARK_COL_ROW = 16'h0129;
parameter DC_FLASH = 16'h0608;
parameter DC_GREEN_GAIN_1 = 16'h00B0;
parameter DC_BLUE_GAIN = 16'h00CF;
parameter DC_RED_GAIN = 16'h00CF;
parameter DC_GREEN_GAIN_2 = 16'h00B0;
//parameter DC_GLOBAL_GAIN = 16'h0120;
parameter DC_CONTEXT_CTRL = 16'h000B;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 4: 0] rom_address;
// Bidirectionals
// Outputs
output [35: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [31: 0] data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = {data[31:24], 1'b0,
data[23:16], 1'b0,
data[15: 8], 1'b0,
data[ 7: 0], 1'b0};
// Internal Assignments
always @(*)
begin
case (rom_address)
0 : data <= {8'hBA, 8'h01, DC_ROW_START};
1 : data <= {8'hBA, 8'h02, DC_COLUMN_START};
2 : data <= {8'hBA, 8'h03, DC_ROW_WIDTH};
3 : data <= {8'hBA, 8'h04, DC_COLUMN_WIDTH};
4 : data <= {8'hBA, 8'h05, DC_H_BLANK_B};
5 : data <= {8'hBA, 8'h06, DC_V_BLANK_B};
6 : data <= {8'hBA, 8'h07, DC_H_BLANK_A};
7 : data <= {8'hBA, 8'h08, DC_V_BLANK_A};
8 : data <= {8'hBA, 8'h09, DC_SHUTTER_WIDTH};
9 : data <= {8'hBA, 8'h0A, DC_ROW_SPEED};
10 : data <= {8'hBA, 8'h0B, DC_EXTRA_DELAY};
11 : data <= {8'hBA, 8'h0C, DC_SHUTTER_DELAY};
12 : data <= {8'hBA, 8'h0D, DC_RESET};
13 : data <= {8'hBA, 8'h1F, DC_FRAME_VALID};
14 : data <= {8'hBA, 8'h20, DC_READ_MODE_B};
15 : data <= {8'hBA, 8'h21, DC_READ_MODE_A};
16 : data <= {8'hBA, 8'h22, DC_DARK_COL_ROW};
17 : data <= {8'hBA, 8'h23, DC_FLASH};
18 : data <= {8'hBA, 8'h2B, DC_GREEN_GAIN_1};
19 : data <= {8'hBA, 8'h2C, DC_BLUE_GAIN};
20 : data <= {8'hBA, 8'h2D, DC_RED_GAIN};
21 : data <= {8'hBA, 8'h2E, DC_GREEN_GAIN_2};
22 : data <= {8'hBA, 8'hC8, DC_CONTEXT_CTRL};
default : data <= 32'h00000000;
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; const long long inf = 0x3f3f3f3f3f3f3f3f; int n, k, b, c; int a[N], A[N], cost[N]; long long ans = inf; void solve(int x) { for (int i = 1; i <= n; ++i) { A[i] = a[i]; cost[i] = 0; while (A[i] % 5 != x) ++A[i], cost[i] += c; } priority_queue<long long> heap; long long res = 0; for (int i = 1; i <= k; ++i) { long long val = 5 * cost[i] - 1LL * b * A[i]; res += val; heap.push(val); } ans = min(ans, (res + 1LL * k * b * A[k]) / 5); for (int i = k + 1; i <= n; ++i) { long long val = 5 * cost[i] - 1LL * b * A[i]; if (val < heap.top()) { res -= heap.top(); heap.pop(); heap.push(val); res += val; } ans = min(ans, (res + 1LL * k * b * A[i]) / 5); } } int main() { cin >> n >> k >> b >> c; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); a[i] += 1e9; } sort(a + 1, a + n + 1); b = min(b, c * 5); for (int i = 0; i < 5; ++i) solve(i); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const long long INF = 1e18; const double eps = 1e-10; mt19937 mrand(chrono::high_resolution_clock::now().time_since_epoch().count()); template <class T> inline void upmin(T &x, T y) { x = x > y ? y : x; } template <class T> inline void upmax(T &x, T y) { x = x < y ? y : x; } const int maxn = 1e5 + 233; vector<int> G[maxn]; int n; int col[maxn]; int fa[maxn]; int cnt[maxn]; void dfs(int u, int f) { for (auto v : G[u]) { if (v == f) continue; col[v] = 3 - col[u]; fa[v] = u; dfs(v, u); } } int deg[maxn]; int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cout << fixed << setprecision(10); cin >> n; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; G[u].emplace_back(v); G[v].emplace_back(u); deg[u]++; deg[v]++; } for (int i = 1; i <= n; i++) { if (deg[i] > 1) { col[i] = 1; dfs(i, 0); break; } } int f1 = 0, f2 = 0; for (int i = 1; i <= n; i++) { if (deg[i] == 1) { if (col[i] == 1) f1 = 1; else f2 = 1; cnt[fa[i]]++; } } int mn, mx; if (f1 && f2) mn = 3; else mn = 1; mx = n - 1; for (int i = 1; i <= n; i++) { if (cnt[i]) mx -= cnt[i] - 1; } cout << mn << << mx << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int n, k; int pr[N], sz[N]; int root(int x) { return pr[x] = (pr[x] == x ? x : root(pr[x])); } void merge(int x, int y) { x = root(x); y = root(y); if (x == y) return; if (rand() & 1) { pr[x] = y; sz[y] += sz[x]; } else { pr[y] = x; sz[x] += sz[y]; } } int main() { for (int i = 0; i < N; i++) { pr[i] = i; sz[i] = 1; } scanf( %d %d , &n, &k); for (int i = 0; i < k; i++) { int u, v; scanf( %d %d , &u, &v); u--; v--; merge(u, v); } int sat = 0; for (int i = 0; i < n; i++) if (root(i) == i) sat += sz[i] - 1; printf( %d n , k - sat); return 0; } |
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/spartan4/IDDR2.v,v 1.1 2004/06/21 21:45:36 wloo Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Dual Data Rate Input D Flip-Flop
// /___/ /\ Filename : IDDR2.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:51 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
`timescale 1 ps / 1 ps
module IDDR2 (Q0, Q1, C0, C1, CE, D, R, S);
output Q0;
output Q1;
input C0;
input C1;
input CE;
input D;
tri0 GSR = glbl.GSR;
input R;
input S;
parameter DDR_ALIGNMENT = "NONE";
parameter INIT_Q0 = 1'b0;
parameter INIT_Q1 = 1'b0;
parameter SRTYPE = "SYNC";
reg q0_out, q1_out;
reg q0_out_int, q1_out_int;
reg q0_c1_out_int, q1_c0_out_int;
buf buf_q0 (Q0, q0_out);
buf buf_q1 (Q1, q1_out);
initial begin
if ((INIT_Q0 != 1'b0) && (INIT_Q0 != 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q0);
$finish;
end
if ((INIT_Q1 != 1'b0) && (INIT_Q1 != 1'b1)) begin
$display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d. Legal values for this attribute are 0 or 1.", INIT_Q1);
$finish;
end
if ((DDR_ALIGNMENT != "C1") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "NONE")) begin
$display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on IDDR2 instance %m is set to %s. Legal values for this attribute are C0, C1 or NONE.", DDR_ALIGNMENT);
$finish;
end
if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
$display("Attribute Syntax Error : The attribute SRTYPE on IDDR2 instance %m is set to %s. Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
$finish;
end
end // initial begin
always @(GSR or R or S) begin
if (GSR == 1) begin
assign q0_out_int = INIT_Q0;
assign q1_out_int = INIT_Q1;
assign q0_c1_out_int = INIT_Q0;
assign q1_c0_out_int = INIT_Q1;
end
else begin
deassign q0_out_int;
deassign q1_out_int;
deassign q0_c1_out_int;
deassign q1_c0_out_int;
if (SRTYPE == "ASYNC") begin
if (R == 1) begin
assign q0_out_int = 0;
assign q1_out_int = 0;
assign q0_c1_out_int = 0;
assign q1_c0_out_int = 0;
end
else if (R == 0 && S == 1) begin
assign q0_out_int = 1;
assign q1_out_int = 1;
assign q0_c1_out_int = 1;
assign q1_c0_out_int = 1;
end
end // if (SRTYPE == "ASYNC")
end // if (GSR == 1'b0)
end // always @ (GSR or R or S)
always @(posedge C0) begin
if (R == 1 && SRTYPE == "SYNC") begin
q0_out_int <= 0;
q1_c0_out_int <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q0_out_int <= 1;
q1_c0_out_int <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
q0_out_int <= D;
q1_c0_out_int <= q1_out_int;
end
end // always @ (posedge C0)
always @(posedge C1) begin
if (R == 1 && SRTYPE == "SYNC") begin
q1_out_int <= 0;
q0_c1_out_int <= 0;
end
else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
q1_out_int <= 1;
q0_c1_out_int <= 1;
end
else if (CE == 1 && R == 0 && S == 0) begin
q1_out_int <= D;
q0_c1_out_int <= q0_out_int;
end
end // always @ (posedge C1)
always @(q0_out_int or q1_out_int or q1_c0_out_int or q0_c1_out_int) begin
case (DDR_ALIGNMENT)
"NONE" : begin
q0_out <= q0_out_int;
q1_out <= q1_out_int;
end
"C0" : begin
q0_out <= q0_out_int;
q1_out <= q1_c0_out_int;
end
"C1" : begin
q0_out <= q0_c1_out_int;
q1_out <= q1_out_int;
end
endcase // case(DDR_ALIGNMENT)
end // always @ (q0_out_int or q1_out_int or q1_c0_out_int or q0_c1_out_int)
specify
if (C0) (C0 => Q0) = (100, 100);
if (C0) (C0 => Q1) = (100, 100);
if (C1) (C1 => Q1) = (100, 100);
if (C1) (C1 => Q0) = (100, 100);
specparam PATHPULSE$ = 0;
endspecify
endmodule // IDDR2
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EBUFN_SYMBOL_V
`define SKY130_FD_SC_HDLL__EBUFN_SYMBOL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__ebufn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EBUFN_SYMBOL_V
|
`define INPUTS_P 4
/***************** TEST RATIONALE **********************
1. STATE SPACE
The UUT is tested with every possible reqs_i. Each reqs_i
is maintained for 2*INPUTS_P cycles and the grant_count,
no. of times a given input line is granted, of each line
is checked to verify the fairness of the arbitrer.
2. PARAMETERIZATION
The no. of inputs is the parameter of this test module.
A reasonable set of tests would include INPUTS_P = 1 2 3,
to check corner cases, and INPUTS_P = 4 10, which include
a power of 2 and a non power of 2.
********************************************************/
module test_bsg;
localparam cycle_time_lp = 20;
localparam inputs_lp = `INPUTS_P;
localparam case_num_lp = 4;
// Clock and reset generation
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_lp)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(1)
, .reset_cycles_hi_p(5)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display("\n\n\n");
$display("===========================================================");
$display("testing with ...");
$display("INPUTS_P: %d\n", inputs_lp);
end
logic test_input_ready;
logic [inputs_lp-1:0] test_input_reqs_v [case_num_lp];
logic [inputs_lp-1:0] test_output_grants_v [case_num_lp];
logic [inputs_lp-1:0] test_input_reqs ;
logic [inputs_lp-1:0] test_output_grants;
//assign the test cases
initial begin
test_input_reqs_v[ 0 ] = 4'b0000 ; test_output_grants_v[ 0 ] = 4'b0000;
test_input_reqs_v[ 1 ] = 4'b0100 ; test_output_grants_v[ 1 ] = 4'b0100; //single request,
test_input_reqs_v[ 2 ] = 4'b1010 ; test_output_grants_v[ 2 ] = 4'b1000; //
test_input_reqs_v[ 3 ] = 4'b1110 ; test_output_grants_v[ 3 ] = 4'b0010; //
end
integer case_num;
// test input generation
always_ff @(posedge clk) begin
if(reset) begin
case_num <= 0;
test_input_reqs <= (inputs_lp)'(0);
test_input_ready <= 1'b1;
end else begin
case_num <= (case_num + 1)%case_num_lp ;
test_input_reqs <= test_input_reqs_v [ ( case_num +1) % case_num_lp ];
end
end
//instantiate the instance
wire v;
bsg_round_robin_arb #(.inputs_p(inputs_lp)
,.reset_on_sr_p( 1'b1 )
) UUT
( .clk_i (clk)
,.reset_i (reset)
,.grants_en_i (test_input_ready)
,.reqs_i (test_input_reqs)
,.grants_o(test_output_grants)
,.v_o (v)
,.tag_o ( )
,.yumi_i(v)
);
// check the result
always_ff @(negedge clk) begin
if(v) begin
$display("\n case num = %d, requests = %b", case_num, test_input_reqs ); if( test_output_grants_v [ case_num ] == test_output_grants )
$display("grants =%b, last_n=%b, last_r=%b, ==>Pass", test_output_grants, UUT.last_n, UUT.last_r);
else
$display("grants =%b, expect=%b, last_n=%b, last_r=%b,==>fail", test_output_grants,test_output_grants_v[ case_num ], UUT.last_n, UUT.last_r );
end
end
// finish
always@(negedge clk)
if( case_num == (case_num_lp -1) ) begin
$display("==========================================================");
#20 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long gcd(long long ar1, long long ar2) { return ar2 == 0 ? ar1 : gcd(ar2, ar1 % ar2); } long long add(long long ar1, long long ar2, long long m) { if (ar1 >= m) ar1 %= m; if (ar2 >= m) ar2 %= m; if (ar1 < 0) ar1 += m; if (ar2 < 0) ar2 += m; long long res = ar1 + ar2; if (res >= m or res <= -m) res %= m; if (res < 0) res += m; return res; } long long mul(long long ar1, long long ar2, long long m) { if (ar1 >= m) ar1 %= m; if (ar2 >= m) ar2 %= m; if (ar1 < 0) ar1 += m; if (ar2 < 0) ar2 += m; long long res = ar1 * ar2; if (res >= m or res <= -m) res %= m; if (res < 0) res += m; return res; } long long pow_mod(long long ar1, long long ar2, long long m) { long long res = 1; ar1 = ar1 % m; while (ar2) { if (ar2 & 1) res = mul(res, ar1, m); ar2 >>= 1; ar1 = mul(ar1, ar1, m); } return res; } long long fastexp(long long ar1, long long ar2) { long long res = 1; while (ar2) { if (ar2 & 1) res = res * ar1; ar2 >>= 1; ar1 *= ar1; } return res; } long long gcdExtendido(long long ar1, long long ar2, long long *x, long long *y) { if (ar1 == 0) { *x = 0; *y = 1; return ar2; } long long x1, y1; long long gcd = gcdExtendido(ar2 % ar1, ar1, &x1, &y1); *x = y1 - (ar2 / ar1) * x1; *y = x1; return gcd; } long long modInverso(long long ar1, long long m) { long long x, y; long long g = gcdExtendido(ar1, m, &x, &y); if (g != 1) return -1; else return (x % m + m) % m; } bool sortbysec(const pair<long long, long long> &ar1, const pair<long long, long long> &ar2) { return (ar1.second < ar2.second); } long long fact(long long n) { if (n <= 1) return 1; return mul(n, fact(n - 1), 1000000007); } bool probablyPrimeFermat(long long n, long long iter) { if (n < 4) return n == 2 || n == 3; for (long long i = 0; i < iter; i++) { long long a = 2 + abs(rand() % (n - 3)); if (pow_mod(a, n - 1, n) != 1) return false; } return true; } bool checkPow2(long long n) { return (n > 0) && ((n & (n - 1)) == 0); } signed main() { long long t = 3; vector<pair<long long, char> > cnt; cnt.push_back({0, A }); cnt.push_back({0, B }); cnt.push_back({0, C }); while (t--) { string s; cin >> s; if (s[1] == > ) { if (t == 0 && cnt[s[0] - A ].first < cnt[s[2] - A ].first) { cout << Impossible n ; return 0; } cnt[s[0] - A ].first += cnt[s[2] - A ].first + 1; } else { if (t == 0 && cnt[s[2] - A ].first < cnt[s[0] - A ].first) { cout << Impossible n ; return 0; } cnt[s[2] - A ].first += cnt[s[0] - A ].first + 1; } } sort(cnt.begin(), cnt.end()); if (cnt[0].first == cnt[1].first || cnt[1].first == cnt[2].first) { cout << Impossible n ; } else { for (long long i = 0; i < 3; i++) cout << cnt[i].second; } cout << n ; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFRTP_OV2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SDFRTP_OV2_BEHAVIORAL_PP_V
/**
* sdfrtp_ov2: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_lp__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__sdfrtp_ov2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFRTP_OV2_BEHAVIORAL_PP_V |
// test_simulation_sop_basic_10_test.v
module f1_test(input [1:0] in, input select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
endcase
endmodule
// test_simulation_sop_basic_11_test.v
module f2_test(input [3:0] in, input [1:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
endcase
endmodule
// test_simulation_sop_basic_12_test.v
module f3_test(input [7:0] in, input [2:0] select, output reg out);
always @( in or select)
case (select)
0: out = in[0];
1: out = in[1];
2: out = in[2];
3: out = in[3];
4: out = in[4];
5: out = in[5];
6: out = in[6];
7: out = in[7];
endcase
endmodule
// test_simulation_sop_basic_18_test.v
module f4_test(input [7:0] in, output out);
assign out = ~^in;
endmodule
// test_simulation_sop_basic_3_test.v
module f5_test(input in, output out);
assign out = ~in;
endmodule
// test_simulation_sop_basic_7_test.v
module f6_test(input in, output out);
assign out = in;
endmodule
// test_simulation_sop_basic_8_test.v
module f7_test(output out);
assign out = 1'b0;
endmodule
// test_simulation_sop_basic_9_test.v
module f8_test(input in, output out);
assign out = ~in;
endmodule
|
// ----------------------------------------------------------------------------
// Module: memory.v
// Project: MOS 6502 Processor
// Author: George Castillo <>
// Date: 23 April 2018
//
// Description: Behavioral model for a 64kB asynchronous memory. The module
// reads a text file into a large array and then either reads or writes to the
// array in a clocked process with a programmable delay. A reset immediately
// reloads the contents of the data file provided during compilation.
//
// This is not truly an asynchronous memory - if it were, it would respond to
// things other than just the rising edge of the clock. For that matter, if
// it were truly asynchronous, it would not have a clock at all. The purpose
// of this module is to model a memory which accepts an address on the rising
// edge of a clock and provides the data a configurable amount of time later,
// like an asynchronous RAM would. This model was designed to be used with a
// simulated clock frequency of 100MHz. Higher speeds could be done, but it
// would require modifying the timescale directive and some parameters.
//
// Read:
// - The `enable' net should be driven high and `wr_enable' driven low
// - An address is expected to be provided on the rising edge of `clk'
// - Some time after that clock edge, determined by ASYNC_DELAY, data will
// arrive on the data lines and will be available by the next clock cycle
//
// Write:
// - The `enable' and `wr_enable' nets should both be driven high
// - An address is expected to be provided on the rising edge of `clk'
// - Data is expected to be provided on the rising edge of `clk'
// - Some time after that clock edge, determined by ASYNC_DELAY, the data
// will be stored in memory
//
// A reset operation, which is active low, will reload the contents of the
// DATA_FILE into the memory array.
//
// If neither `enable' or `wr_enable' are driven high, the memory will drive
// the data lines to high impedance
// ----------------------------------------------------------------------------
`timescale 1ns / 1ps
module memory
#(
// Used to determine how deep to make the memory array. The number of
// addresses provided is 2 raised to the power of DEPTH
parameter DEPTH = 16,
// Number of bits to store at each address
parameter WIDTH = 8,
// The amount of simulation time to wait after an address is clocked in on
// the address line before providing the data at the data line (read) or
// writing the data to the memory (write)
parameter ASYNC_DELAY = 1,
// File containing binary data (ASCII). These are expected to be .mif files
// from a Xilinx memory core generator or an output of the oddball
// assembler
parameter DATA_FILE = "data.mif"
) (
input wire clk,
input wire resetn,
input wire enable,
input wire [(DEPTH-1):0] address,
input wire wr_enable,
input wire [(WIDTH-1):0] wr_data,
output reg [(WIDTH-1):0] rd_data
);
// High Z the memory if not reading or writing
localparam DISABLED = 8'hzz;
reg [(WIDTH-1):0] mem_array [0:(2**DEPTH-1)];
// Load the image file at the beginning of the simulation
initial begin
$readmemb(DATA_FILE, mem_array);
end
// -- Reset logic
always @(posedge clk) begin
if ( resetn == 1'b0 ) begin
$readmemb(DATA_FILE, mem_array);
end
end
// -- Memory model
always @(posedge clk) begin
#ASYNC_DELAY;
if ( wr_enable && enable ) begin
mem_array[address] <= wr_data;
end else if ( enable ) begin
rd_data <= mem_array[address];
end else begin
rd_data <= DISABLED;
end
end
endmodule // memory
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12:52:08 03/28/2014
// Design Name:
// Module Name: aluc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies :
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu(a,b,aluc,wzero,zero,result);
input[31:0] a,b;
input[3:0] aluc;
input wzero;
output zero;
reg zero;
output[31:0] result;
reg[31:0] result;
initial begin
zero = 0;
end
//assign zero = (result==0);
wire right,arith,sub;
wire [31:0] sh,as_result,and_result,or_result;
wire slct[1:0];
assign right = ~aluc[3]&aluc[2]&aluc[1];
assign arith = ~aluc[3]&aluc[2]&aluc[1]&aluc[0];
assign sub = ~aluc[3]&~aluc[2]&aluc[1]&aluc[0];
shift shifter(b,a[4:0],right,arith,sh);
addsub32 as32(a,b,sub,as_result);
assign and_result = a&b;
assign or_result = a|b;
function [31:0] select;
input [31:0] a0,a1,a2,a3;
input [3:0] aluc;
case(aluc)
0:select=a0;
1:select=a1;
2:select=a2;
3:select=a2;
4:select=a2;
5:select=a3;
6:select=a3;
7:select=a3;
endcase
endfunction
always @(*)
begin
#1;
result = select(and_result,or_result,as_result,sh,aluc);
//if ((aluc==2) || (aluc==3))
//zero = (result==0);
//if (~aluc[3] & ~aluc[2] & aluc[1])
if (wzero)
zero = (result==0);
/*case (aluc)
0: result <= a & b;
1: result <= a | b;
2: begin
result <= a + b;
zero <= (result==0);
end
3: begin
result <= a - b;
zero <= (result==0);
end
4: result <= a + b;
5: result <= sh;
6: result <= sh;
7: result <= sh;
default : result <= 0;
endcase*/
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_82x256_la.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sfifo_82x256_la (
aclr,
clock,
data,
rdreq,
wrreq,
almost_full,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [95:0] data;
input rdreq;
input wrreq;
output almost_full;
output empty;
output full;
output [95:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [95:0] sub_wire3;
wire sub_wire4;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [95:0] q = sub_wire3[95:0];
wire almost_full = sub_wire4;
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_full (sub_wire4),
.almost_empty (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.almost_full_value = 192,
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 96,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "192"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "96"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "96"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "192"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "96"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL "almost_full"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 96 0 INPUT NODEFVAL "data[95..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 96 0 OUTPUT NODEFVAL "q[95..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 96 0 data 0 0 96 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 96 0 @q 0 0 96 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_82x256_la.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_82x256_la.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_82x256_la.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_82x256_la.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_82x256_la_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_82x256_la_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module flt_add_sub
(
input clk,
input sub,
input [31:0] afl,
input [31:0] bfl,
output reg [31:0] fl
);
reg [24:0] ai_0; // Mantisa of the Float
reg [24:0] bi_0; // Mantisa of the Float
reg sub_0;
reg [7:0] aefl_0; // Exponent of the Float
reg [24:0] n_ai_0; // Mantisa of the Float
reg [24:0] n_bi_0; // Mantisa of the Float
reg [24:0] n_mfl_0; // Mantisa of the Float
reg sfl_0; // Sign of the Float
reg [24:0] nn_mfl_0; // Mantisa of the Float
reg [31:0] afl_0;
reg [31:0] bfl_0;
reg afl_eq_bfl_0;
reg afl_eqz_0;
reg bfl_eqz_0;
reg [24:0] nn_mfl_1; // Mantisa of the Float
reg [7:0] nom_shft_1; // Mantisa of the Float
reg [24:0] nmfl_1; // Mantisa of the Float
reg [7:0] n_efl_1; // Exponent of the Float
reg sub_1;
reg afl_eqz_1;
reg bfl_eqz_1;
reg afl_eq_bfl_1;
reg [7:0] aefl_1; // Exponent of the Float
reg sfl_1; // Sign of the Float
reg [31:0] afl_1;
reg [31:0] bfl_1;
reg [8:0] agb; // Exponent difference.
reg [8:0] bga; // Exponent difference.
always @* agb = bfl[30:23] - afl[30:23];
always @* bga = afl[30:23] - bfl[30:23];
// Pipe 0
always @(posedge clk) begin
sub_0 <= sub;
afl_0 <= afl;
bfl_0 <= bfl;
afl_eq_bfl_0 <= (afl[30:0] == bfl[30:0]) &
((~sub & (afl[31] ^ bfl[31])) | (sub & (afl[31] ~^ bfl[31])));
afl_eqz_0 <= ~|afl[30:0];
bfl_eqz_0 <= ~|bfl[30:0];
if(agb[8]) // A exponant is greater than B exponant.
begin
bi_0 <= {(sub ^ bfl[31]), ({1'b1,bfl[22:0]} >> (bga[7:0]))};
ai_0 <= {afl[31], {1'b1,afl[22:0]}};
aefl_0 <= afl[30:23];
end
else // B exponant is greater than A exponant.
begin
ai_0 <= {afl[31], ({1'b1,afl[22:0]} >> (agb[7:0]))};
aefl_0 <= bfl[30:23];
bi_0 <= {(sub ^ bfl[31]), {1'b1,bfl[22:0]}};
end
end
always @*
begin
case({ai_0[24],bi_0[24]})
2'b00:begin
n_ai_0 = ai_0;
n_bi_0 = bi_0;
end
2'b11:begin
n_ai_0 = {1'b0,ai_0[23:0]};
n_bi_0 = {1'b0,bi_0[23:0]};
end
2'b10:begin
n_ai_0 = {ai_0[24],~ai_0[23:0]};
n_bi_0 = bi_0;
end
2'b01:begin
n_ai_0 = ai_0;
n_bi_0 = {bi_0[24],~bi_0[23:0]};
end
endcase
end
always @* n_mfl_0 = n_ai_0 + n_bi_0;
always @* // Calculate the sign bit.
begin
casex({ai_0[24],bi_0[24],n_mfl_0[24]})
3'b00x:sfl_0 = 1'b0;
3'b11x:sfl_0 = 1'b1;
3'b100:sfl_0 = 1'b0;
3'b101:sfl_0 = 1'b1;
3'b010:sfl_0 = 1'b0;
3'b011:sfl_0 = 1'b1;
endcase
end
always @* // Calculate the end result.
begin
casex({ai_0[24],bi_0[24],n_mfl_0[24]})
3'b00x:nn_mfl_0 = n_mfl_0[24:0];
3'b11x:nn_mfl_0 = n_mfl_0[24:0];
3'b100:begin
nn_mfl_0[23:0] = n_mfl_0[23:0]+24'h1;
nn_mfl_0[24] = 1'b0;
end
3'b101:begin
nn_mfl_0[23:0] = ~n_mfl_0[23:0];
nn_mfl_0[24] = 1'b0;
end
3'b010:begin
nn_mfl_0[23:0] = n_mfl_0[23:0]+24'h1;
nn_mfl_0[24] = 1'b0;
end
3'b011:begin
nn_mfl_0[23:0] = ~n_mfl_0[23:0];
nn_mfl_0[24] = 1'b0;
end
endcase
end
always @(posedge clk)
begin
sub_1 <= sub_0;
sfl_1 <= sfl_0;
afl_eqz_1 <= afl_eqz_0;
bfl_eqz_1 <= bfl_eqz_0;
afl_eq_bfl_1 <= afl_eq_bfl_0;
aefl_1 <= aefl_0;
afl_1 <= afl_0;
bfl_1 <= bfl_0;
nn_mfl_1 <= nn_mfl_0;
nom_shft_1 <=0;
casex(nn_mfl_0) /* synopsys parallel_case */
25'b1xxxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1 <=24;
25'b01xxxxxxxxxxxxxxxxxxxxxxx: nom_shft_1 <=0;
25'b001xxxxxxxxxxxxxxxxxxxxxx: nom_shft_1 <=1;
25'b0001xxxxxxxxxxxxxxxxxxxxx: nom_shft_1 <=2;
25'b00001xxxxxxxxxxxxxxxxxxxx: nom_shft_1 <=3;
25'b000001xxxxxxxxxxxxxxxxxxx: nom_shft_1 <=4;
25'b0000001xxxxxxxxxxxxxxxxxx: nom_shft_1 <=5;
25'b00000001xxxxxxxxxxxxxxxxx: nom_shft_1 <=6;
25'b000000001xxxxxxxxxxxxxxxx: nom_shft_1 <=7;
25'b0000000001xxxxxxxxxxxxxxx: nom_shft_1 <=8;
25'b00000000001xxxxxxxxxxxxxx: nom_shft_1 <=9;
25'b000000000001xxxxxxxxxxxxx: nom_shft_1 <=10;
25'b0000000000001xxxxxxxxxxxx: nom_shft_1 <=11;
25'b00000000000001xxxxxxxxxxx: nom_shft_1 <=12;
25'b000000000000001xxxxxxxxxx: nom_shft_1 <=13;
25'b0000000000000001xxxxxxxxx: nom_shft_1 <=14;
25'b00000000000000001xxxxxxxx: nom_shft_1 <=15;
25'b000000000000000001xxxxxxx: nom_shft_1 <=16;
25'b0000000000000000001xxxxxx: nom_shft_1 <=17;
25'b00000000000000000001xxxxx: nom_shft_1 <=18;
25'b000000000000000000001xxxx: nom_shft_1 <=19;
25'b0000000000000000000001xxx: nom_shft_1 <=20;
25'b00000000000000000000001xx: nom_shft_1 <=21;
25'b000000000000000000000001x: nom_shft_1 <=22;
25'b0000000000000000000000001: nom_shft_1 <=23;
default: nom_shft_1 <=0;
endcase
end
always @(nn_mfl_1 or nom_shft_1)
begin
if(nom_shft_1[4] & nom_shft_1[3])nmfl_1 = nn_mfl_1 >> 1;
else nmfl_1 = nn_mfl_1 << nom_shft_1;
end
always @* // Calculate the sign bit.
begin
if(nom_shft_1[4] & nom_shft_1[3])n_efl_1 = aefl_1+8'h1;
else n_efl_1 = aefl_1 - nom_shft_1;
end
// Final Answer.
always @(posedge clk)
begin
casex({sub_1, afl_eqz_1, bfl_eqz_1, afl_eq_bfl_1})
4'b0000: fl <= {sfl_1,n_efl_1,nmfl_1[22:0]}; // Normal Add, afl + bfl.
4'b0010: fl <= afl_1; // Add, (afl != 0), (bfl = 0), fl = afl;
4'b0100: fl <= bfl_1; // Add, (afl = 0), (bfl != 0), fl = bfl;
4'b011x: fl <= 0; // Add, (afl = 0), (bfl = 0), fl = 0;
4'b1xx1: fl <= 0; // afl = bfl, subtract, fl = 0;
4'b1xx0: fl <= {sfl_1,n_efl_1,nmfl_1[22:0]}; // Normal Subtract.
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t = 1; ios_base::sync_with_stdio(false); cin.tie(NULL); while (t--) { long long int i, j, k, m, n, ans = 0; cin >> n >> k; if (n >= k) n = k - 1; if (k - n >= n) { cout << 0; return 0; } long long int hi = n, lo = k - n; cout << (hi - lo + 1) / 2; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; vector<int> id(n + 1); for (int i = 0; i < n; i++) { int x; cin >> x; id[x] = i; } vector<int> dp(n + 1, 1); for (int i = 2; i <= n; i++) { if (id[i] > id[i - 1]) { dp[i] += dp[i - 1]; } } cout << n - *max_element(dp.begin(), dp.end()); } |
module erx (/*AUTOARG*/
// Outputs
rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, rxwr_access, rxwr_packet, rxrd_access, rxrd_packet,
rxrr_access, rxrr_packet, erx_cfg_wait, timeout, mailbox_full,
mailbox_not_empty,
// Inputs
erx_reset,erx_ioreset, sys_reset, sys_clk, rx_lclk, rx_lclk_div4,
rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p,
rxi_data_n, rxwr_wait, rxrd_wait, rxrr_wait, erx_cfg_access,
erx_cfg_packet
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h800;
parameter IOSTD_ELINK = "LVDS_25";
parameter ETYPE = 1;
//Synched resets
input erx_reset; // reset for core logic
input sys_reset; // reset for fifos
input erx_ioreset;
//Clocks
input sys_clk; // system clock for rx fifos
input rx_lclk; // fast clock for io
input rx_lclk_div4; // slow clock for rest of logic
output rx_lclk_pll; // clock output for pll
//FROM IO Pins
input rxi_lclk_p, rxi_lclk_n; // rx clock input
input rxi_frame_p, rxi_frame_n; // rx frame signal
input [7:0] rxi_data_p, rxi_data_n; // rx data
output rxo_wr_wait_p,rxo_wr_wait_n; // rx write pushback output
output rxo_rd_wait_p,rxo_rd_wait_n; // rx read pushback output
//Master write
output rxwr_access;
output [PW-1:0] rxwr_packet;
input rxwr_wait;
//Master read request
output rxrd_access;
output [PW-1:0] rxrd_packet;
input rxrd_wait;
//Slave read response
output rxrr_access;
output [PW-1:0] rxrr_packet;
input rxrr_wait;
//Configuration Interface (from ETX)
input erx_cfg_access;
input [PW-1:0] erx_cfg_packet;
output erx_cfg_wait;
//Readback timeout (synchronized to sys_c
output timeout;
output mailbox_full;
output mailbox_not_empty;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire rx_access; // From erx_io of erx_io.v
wire rx_burst; // From erx_io of erx_io.v
wire [PW-1:0] rx_packet; // From erx_io of erx_io.v
wire rx_rd_wait; // From erx_core of erx_core.v
wire rx_wr_wait; // From erx_core of erx_core.v
wire rxrd_fifo_access; // From erx_core of erx_core.v
wire [PW-1:0] rxrd_fifo_packet; // From erx_core of erx_core.v
wire rxrd_fifo_wait; // From erx_fifo of erx_fifo.v
wire rxrr_fifo_access; // From erx_core of erx_core.v
wire [PW-1:0] rxrr_fifo_packet; // From erx_core of erx_core.v
wire rxrr_fifo_wait; // From erx_fifo of erx_fifo.v
wire rxwr_fifo_access; // From erx_core of erx_core.v
wire [PW-1:0] rxwr_fifo_packet; // From erx_core of erx_core.v
wire rxwr_fifo_wait; // From erx_fifo of erx_fifo.v
// End of automatics
/***********************************************************/
/*RECEIVER I/O LOGIC */
/***********************************************************/
defparam erx_io.IOSTD_ELINK=IOSTD_ELINK;
defparam erx_io.ETYPE=ETYPE;
erx_io erx_io (.reset (erx_ioreset),
/*AUTOINST*/
// Outputs
.rx_lclk_pll (rx_lclk_pll),
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
.rx_access (rx_access),
.rx_burst (rx_burst),
.rx_packet (rx_packet[PW-1:0]),
// Inputs
.rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4),
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p),
.rxi_frame_n (rxi_frame_n),
.rxi_data_p (rxi_data_p[7:0]),
.rxi_data_n (rxi_data_n[7:0]),
.rx_wr_wait (rx_wr_wait),
.rx_rd_wait (rx_rd_wait));
/**************************************************************/
/*ELINK CORE LOGIC */
/**************************************************************/
/*erx_core AUTO_TEMPLATE ( .rx_packet (rx_packet[PW-1:0]),
.rx_access (rx_access),
.erx_cfg_access (erx_cfg_access),
.erx_cfg_packet (erx_cfg_packet[PW-1:0]),
.erx_cfg_wait (erx_cfg_wait),
.rx_rd_wait (rx_rd_wait),
.rx_wr_wait (rx_wr_wait),
.\(.*\)_packet (\1_fifo_packet[PW-1:0]),
.\(.*\)_access (\1_fifo_access),
.\(.*\)_wait (\1_fifo_wait),
);
*/
defparam erx_core.ID=ID;
erx_core erx_core ( .clk (rx_lclk_div4),
.reset (erx_reset),
/*AUTOINST*/
// Outputs
.rx_rd_wait (rx_rd_wait), // Templated
.rx_wr_wait (rx_wr_wait), // Templated
.rxrd_access (rxrd_fifo_access), // Templated
.rxrd_packet (rxrd_fifo_packet[PW-1:0]), // Templated
.rxrr_access (rxrr_fifo_access), // Templated
.rxrr_packet (rxrr_fifo_packet[PW-1:0]), // Templated
.rxwr_access (rxwr_fifo_access), // Templated
.rxwr_packet (rxwr_fifo_packet[PW-1:0]), // Templated
.erx_cfg_wait (erx_cfg_wait), // Templated
.mailbox_full (mailbox_full),
.mailbox_not_empty(mailbox_not_empty),
// Inputs
.rx_packet (rx_packet[PW-1:0]), // Templated
.rx_access (rx_access), // Templated
.rx_burst (rx_burst),
.rxrd_wait (rxrd_fifo_wait), // Templated
.rxrr_wait (rxrr_fifo_wait), // Templated
.rxwr_wait (rxwr_fifo_wait), // Templated
.erx_cfg_access (erx_cfg_access), // Templated
.erx_cfg_packet (erx_cfg_packet[PW-1:0])); // Templated
/************************************************************/
/*FIFOs */
/************************************************************/
erx_fifo erx_fifo (
/*AUTOINST*/
// Outputs
.rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access),
.rxrd_packet (rxrd_packet[PW-1:0]),
.rxrr_access (rxrr_access),
.rxrr_packet (rxrr_packet[PW-1:0]),
.rxrd_fifo_wait (rxrd_fifo_wait),
.rxrr_fifo_wait (rxrr_fifo_wait),
.rxwr_fifo_wait (rxwr_fifo_wait),
// Inputs
.erx_reset (erx_reset),
.sys_reset (sys_reset),
.rx_lclk_div4 (rx_lclk_div4),
.sys_clk (sys_clk),
.rxwr_wait (rxwr_wait),
.rxrd_wait (rxrd_wait),
.rxrr_wait (rxrr_wait),
.rxrd_fifo_access(rxrd_fifo_access),
.rxrd_fifo_packet(rxrd_fifo_packet[PW-1:0]),
.rxrr_fifo_access(rxrr_fifo_access),
.rxrr_fifo_packet(rxrr_fifo_packet[PW-1:0]),
.rxwr_fifo_access(rxwr_fifo_access),
.rxwr_fifo_packet(rxwr_fifo_packet[PW-1:0]));
endmodule // erx
// Local Variables:
// verilog-library-directories:(".")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { bool f = false; set<int> v1; int n, ans = -1; cin >> n; int a[n]; for (long long i = 0; i < n; i++) { cin >> a[i]; v1.insert(a[i]); } for (int i = 1; i <= 1024; i++) { long long count = 0; for (int j = 0; j < n; j++) { int m = a[j] ^ i; v1.insert(a[j] ^ i); if (v1.size() > n) { count++; v1.erase(v1.find(m)); break; } } if (count == 0) { ans = i; break; } } cout << ans << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21AI_BLACKBOX_V
`define SKY130_FD_SC_LP__O21AI_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21ai (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21AI_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int Scan(); int n, m, w, num; double aver, cur[105]; vector<pair<int, double> > res[105]; double place(double V, int i) { double D = aver - cur[num]; double L = min(D, V); res[num].push_back(make_pair(i, L)); cur[num] += L; if (fabs(cur[num] - aver) <= 1e-6) num++; return fabs(V - L); } int main() { scanf( %d%d%d , &n, &w, &m); aver = (double)w * n / m; num = 1; memset(cur, 0, sizeof cur); for (int i = 1; i <= n; ++i) { double now = place(w, i); if (now > 1e-6) now = place(now, i); } if (num != m + 1) puts( NO ); else { puts( YES ); for (int i = 1; i <= m; ++i) { for (int j = 0; j < res[i].size(); ++j) { printf( %d %.6lf , res[i][j].first, res[i][j].second); j == res[i].size() - 1 ? puts( ) : putchar( ); } } } } int Scan() { int res = 0, ch, flag = 0; if ((ch = getchar()) == - ) flag = 1; else if (ch >= 0 && ch <= 9 ) res = ch - 0 ; while ((ch = getchar()) >= 0 && ch <= 9 ) res = res * 10 + ch - 0 ; return flag ? -res : res; } |
#include <bits/stdc++.h> int nextInt() { int x; scanf( %d , &x); return x; } double nextDouble() { double x; scanf( %lf , &x); return x; } long long nextLong() { long long x; scanf( %I64d , &x); return x; } char nextChar() { char x; scanf( %c , &x); return x; } void newLine() { printf( n ); } long long powM(long long a, long long b, long long MOD) { long long x = 1, y = a; while (b > 0) { if (b % 2 == 1) { x = (x * y); if (x > MOD) x %= MOD; } y = (y * y); if (y > MOD) y %= MOD; b /= 2; } return x; } long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return (a * b) / gcd(a, b); } int countSetBits(long long n) { int ans = 0; while (n != 0) { n -= (n & -n); ++ans; } return ans; } long long mod = 1000000007; long long mod2 = 1000000009; const int N = 1100; const int M = 111; const int LOG = 21; const long long INF = 1e18; const long double EPS = 1e-6; const long double PI = 2 * acos(0); using namespace std; int a[N], b[N]; int main() { int n = nextInt(); int m = nextInt(); int d = 0; bool ok = true; for (int i = 0; i < m; i++) { int x = nextInt(), y = nextInt(); a[x] += 1; a[y + 1] -= 1; } for (int i = 1; i <= n; i++) a[i] += a[i - 1]; for (int i = 1; i <= n; i++) { if (a[i] != 1) { cout << i << << a[i] << endl; ok = false; break; } } if (ok) puts( OK ); return 0; } |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AxiLite Slave Conversion
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axilite_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_axilite_conv #
(
parameter C_FAMILY = "virtex6",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [3-1:0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, // Constant =0
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [3-1:0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST, // Constant =1
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, // Constant =0
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [3-1:0] M_AXI_AWPROT,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [3-1:0] M_AXI_ARPROT,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
wire s_awvalid_i;
wire s_arvalid_i;
wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr;
// Arbiter
reg read_active;
reg write_active;
reg busy;
wire read_req;
wire write_req;
wire read_complete;
wire write_complete;
reg [1:0] areset_d; // Reset delay register
always @(posedge ACLK) begin
areset_d <= {areset_d[0], ~ARESETN};
end
assign s_awvalid_i = S_AXI_AWVALID & (C_AXI_SUPPORTS_WRITE != 0);
assign s_arvalid_i = S_AXI_ARVALID & (C_AXI_SUPPORTS_READ != 0);
assign read_req = s_arvalid_i & ~busy & ~|areset_d & ~write_active;
assign write_req = s_awvalid_i & ~busy & ~|areset_d & ((~read_active & ~s_arvalid_i) | write_active);
assign read_complete = M_AXI_RVALID & S_AXI_RREADY;
assign write_complete = M_AXI_BVALID & S_AXI_BREADY;
always @(posedge ACLK) begin : arbiter_read_ff
if (|areset_d)
read_active <= 1'b0;
else if (read_complete)
read_active <= 1'b0;
else if (read_req)
read_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_write_ff
if (|areset_d)
write_active <= 1'b0;
else if (write_complete)
write_active <= 1'b0;
else if (write_req)
write_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_busy_ff
if (|areset_d)
busy <= 1'b0;
else if (read_complete | write_complete)
busy <= 1'b0;
else if ((write_req & M_AXI_AWREADY) | (read_req & M_AXI_ARREADY))
busy <= 1'b1;
end
assign M_AXI_ARVALID = read_req;
assign S_AXI_ARREADY = M_AXI_ARREADY & read_req;
assign M_AXI_AWVALID = write_req;
assign S_AXI_AWREADY = M_AXI_AWREADY & write_req;
assign M_AXI_RREADY = S_AXI_RREADY & read_active;
assign S_AXI_RVALID = M_AXI_RVALID & read_active;
assign M_AXI_BREADY = S_AXI_BREADY & write_active;
assign S_AXI_BVALID = M_AXI_BVALID & write_active;
// Address multiplexer
assign m_axaddr = (read_req | (C_AXI_SUPPORTS_WRITE == 0)) ? S_AXI_ARADDR : S_AXI_AWADDR;
// Id multiplexer and flip-flop
reg [C_AXI_ID_WIDTH-1:0] s_axid;
always @(posedge ACLK) begin : axid
if (read_req) s_axid <= S_AXI_ARID;
else if (write_req) s_axid <= S_AXI_AWID;
end
assign S_AXI_BID = s_axid;
assign S_AXI_RID = s_axid;
assign M_AXI_AWADDR = m_axaddr;
assign M_AXI_ARADDR = m_axaddr;
// Feed-through signals
assign S_AXI_WREADY = M_AXI_WREADY & ~|areset_d;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_WVALID = S_AXI_WVALID & ~|areset_d;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_ARPROT = S_AXI_ARPROT;
endmodule
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