text stringlengths 59 71.4k |
|---|
module butterfly1_8(
enable,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input enable;
input signed [17:0] i_0;
input signed [17:0] i_1;
input signed [17:0] i_2;
input signed [17:0] i_3;
input signed [17:0] i_4;
input signed [17:0] i_5;
input signed [17:0] i_6;
input signed [17:0] i_7;
output signed [18:0] o_0;
output signed [18:0] o_1;
output signed [18:0] o_2;
output signed [18:0] o_3;
output signed [18:0] o_4;
output signed [18:0] o_5;
output signed [18:0] o_6;
output signed [18:0] o_7;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire signed [18:0] b_0;
wire signed [18:0] b_1;
wire signed [18:0] b_2;
wire signed [18:0] b_3;
wire signed [18:0] b_4;
wire signed [18:0] b_5;
wire signed [18:0] b_6;
wire signed [18:0] b_7;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign b_0=i_0+i_7;
assign b_1=i_1+i_6;
assign b_2=i_2+i_5;
assign b_3=i_3+i_4;
assign b_4=i_3-i_4;
assign b_5=i_2-i_5;
assign b_6=i_1-i_6;
assign b_7=i_0-i_7;
assign o_0=enable?b_0:i_0;
assign o_1=enable?b_1:i_1;
assign o_2=enable?b_2:i_2;
assign o_3=enable?b_3:i_3;
assign o_4=enable?b_4:i_4;
assign o_5=enable?b_5:i_5;
assign o_6=enable?b_6:i_6;
assign o_7=enable?b_7:i_7;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_dp_macb_r.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of PCX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
module pcx_dp_macb_r(/*AUTOARG*/
// Outputs
data_out_px_l, scan_out, shiftenable_buf,
// Inputs
arb_pcxdp_qsel1_pa, arb_pcxdp_qsel0_pa, arb_pcxdp_grant_pa,
arb_pcxdp_shift_px, arb_pcxdp_q0_hold_pa, src_pcx_data_pa,
data_prev_px_l, rclk, scan_in, shiftenable
);
output [129:0] data_out_px_l; // pcx to destination pkt
output scan_out;
output shiftenable_buf;
input arb_pcxdp_qsel1_pa; // queue write sel
input arb_pcxdp_qsel0_pa; // queue write sel
input arb_pcxdp_grant_pa;//grant signal
input arb_pcxdp_shift_px;//grant signal
input arb_pcxdp_q0_hold_pa;//grant signal
input [129:0] src_pcx_data_pa; // spache to pcx data
input [129:0] data_prev_px_l;
input rclk;
//input tmb_l;
input scan_in;
input shiftenable;
wire grant_px;
wire [129:0] q0_datain_pa;
wire [129:0] q1_dataout, q0_dataout;
wire [129:0] data_px_l;
wire clkq0, clkq1;
reg clkenq0, clkenq1;
// Generate gated clocks for hold function
assign shiftenable_buf = shiftenable;
//replace tmb_l w/ ~se
wire se_l ;
assign se_l = ~shiftenable ;
clken_buf ck0 (
.clk (clkq0),
.rclk (rclk),
.enb_l(~arb_pcxdp_q0_hold_pa),
.tmb_l(se_l));
clken_buf ck1 (
.clk (clkq1),
.rclk (rclk),
.enb_l(~arb_pcxdp_qsel1_pa),
.tmb_l(se_l));
// Latch and drive grant signal
// Generate write selects
dff_s #(1) dff_pcx_grin_r(
.din (arb_pcxdp_grant_pa),
.q (grant_px),
.clk (rclk),
.se (1'b0),
.si (1'b0),
.so ());
//DATAPATH SECTION
dff_s #(130) dff_pcx_datain_q1(
.din (src_pcx_data_pa[129:0]),
.q (q1_dataout[129:0]),
.clk (clkq1),
.se (1'b0),
.si (),
.so ());
/*
mux2ds #(`PCX_WIDTH) mx2ds_pcx_datain_q0(
.dout (q0_datain_pa[`PCX_WIDTH-1:0]),
.in0 (q1_dataout[`PCX_WIDTH-1:0]),
.in1 (src_pcx_data_pa[`PCX_WIDTH-1:0]),
.sel0 (arb_pcxdp_shift_px),
.sel1 (arb_pcxdp_qsel0_pa));
*/
assign q0_datain_pa[129:0] =
(arb_pcxdp_qsel0_pa ? src_pcx_data_pa[129:0] : 130'd0) |
(arb_pcxdp_shift_px ? q1_dataout[129:0] : 130'd0) ;
dff_s #(130) dff_pcx_datain_q0(
.din (q0_datain_pa[129:0]),
.q (q0_dataout[129:0]),
.clk (clkq0),
.se (1'b0),
.si (),
.so ());
assign data_px_l[129:0] = ~(grant_px ? q0_dataout[129:0]:130'd0);
assign data_out_px_l[129:0] = data_px_l[129:0] & data_prev_px_l[129:0];
// Global Variables:
// verilog-library-directories:("." "../../../../../common/rtl" "../rtl")
// End:
// Code start here
//
endmodule
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// This module provides profiler support for the interface between a kernel
// system and the global memory interfaces provided by the board. It instruments
// the Avalon-MM interface at the root of the interconnect to memory. Some signals
// are passed through from the Avalon interface to the profiler counters
// inside the kernel, such as readdatavalid. Other signals are generated within
// this IP such as a signal asserted at the start of each burst request.
//
// A different instance of this IP is created for each kernel and each memory interface
// used by that kernel. We only aggregate data when the enable signal is asserted.
// This allows the external memory stats to be correlated with the execution of specific kernels.
// Read bursts do not need to be tracked in detail - they are fire and forget with each read
// request starting a new burst. Write bursts do need to be tracked in more detail.
// We need to find the start of each burst so that the burst size can be accumulated.
//
module acl_profiler_external_memory
#(
parameter BURSTCOUNT_WIDTH=6
)
(
input clk,
input resetn,
// Input signals from boundary between the memory interconnect and memory interface
input [BURSTCOUNT_WIDTH-1:0] burstcount_in,
input readdatavalid_in,
input write_in,
input read_in,
input waitrequest_in,
// Outputs to profiling infrastructure:
// First two signals are single bit increment enables
output reg read_count_enable_out,
output reg write_count_enable_out,
// Other two signals cause accumulation of burstcount values, so each contain two signals:
// 1. Single bit increment enable
// 2. Multi-bit burst value to increment by
output reg read_burst_count_enable_out,
output reg [BURSTCOUNT_WIDTH-1:0] read_burst_count_value_out,
output reg write_burst_count_enable_out,
output reg [BURSTCOUNT_WIDTH-1:0] write_burst_count_value_out,
// Replicate the the incement enables for the burst counter. Simplifies implementation in system integrator.
output reg read_burst_count_dup_enable_out,
output reg write_burst_count_dup_enable_out
);
logic new_read_request, new_write_request, new_request;
logic write_burst_in_progress;
logic [BURSTCOUNT_WIDTH-1:0] r_burst_counter;
logic read_burst_count_en;
logic write_burst_count_en;
assign read_burst_count_enable_out = read_burst_count_en;
assign read_burst_count_dup_enable_out = read_burst_count_en;
assign write_burst_count_enable_out = write_burst_count_en;
assign write_burst_count_dup_enable_out = write_burst_count_en;
assign new_read_request = read_in && !waitrequest_in;
assign new_write_request = write_in && !waitrequest_in && !write_burst_in_progress;
assign new_request = new_read_request || new_write_request;
assign write_burst_in_progress = (r_burst_counter > 1);
always@(posedge clk or negedge resetn)
begin
if (!resetn)
begin
read_count_enable_out <= '0;
write_count_enable_out <= '0;
read_burst_count_en <= '0;
write_burst_count_en <= '0;
read_burst_count_value_out <= '0;
write_burst_count_value_out <= '0;
end
else
begin
// "valid data on bus" signals to rd/wr word count signals in profile infrastructure
read_count_enable_out <= readdatavalid_in;
write_count_enable_out <= write_in && !waitrequest_in;
// Burstcount accumulation signals to the profile infrastructure
read_burst_count_en<= read_in && new_request;
write_burst_count_en<= write_in && new_request;
read_burst_count_value_out <= burstcount_in;
write_burst_count_value_out <= burstcount_in;
end
end
// Counter that tracks where we are in a write burst transfer. Lets us
// pick out burst boundaries.
always@(posedge clk or negedge resetn)
begin
if (!resetn)
begin
r_burst_counter <= 1;
end
else
begin
if (new_write_request)
begin
r_burst_counter <= burstcount_in;
end
else
begin
if (write_in && !waitrequest_in)
begin
r_burst_counter <= r_burst_counter - 1;
end
end
end
end
endmodule
|
//% @file fifo_over_ufc_tb.v
//% @brief test bench of FIFO I/O via Aurora 64B66B UFC interface
//% @author Yuan Mei
//%
`timescale 1ns / 1ps
module fifo_over_ufc_tb
#(
parameter FIFO_DATA_WIDTH = 32,
parameter AURORA_DATA_WIDTH = 64
)
();
reg clk;
reg reset;
wire a_tx_req;
wire [7:0] a_tx_ms;
reg a_tx_tready;
wire [AURORA_DATA_WIDTH-1:0] a_tx_tdata;
wire a_tx_tvalid;
wire [AURORA_DATA_WIDTH-1:0] a_rx_tdata;
reg a_rx_tvalid;
wire fifo_clk;
wire [FIFO_DATA_WIDTH-1:0] tx_fifo_q;
wire tx_fifo_wren;
reg tx_fifo_full;
reg [FIFO_DATA_WIDTH-1:0] rx_fifo_q;
wire rx_fifo_rden;
reg rx_fifo_empty;
wire err;
fifo_over_ufc #(.FIFO_DATA_WIDTH(FIFO_DATA_WIDTH), .AURORA_DATA_WIDTH(AURORA_DATA_WIDTH))
uut
(
.RESET(reset),
.AURORA_USER_CLK(clk),
.AURORA_TX_REQ(a_tx_req),
.AURORA_TX_MS(a_tx_ms),
.AURORA_TX_TREADY(a_tx_tready),
.AURORA_TX_TDATA(a_tx_tdata),
.AURORA_TX_TVALID(a_tx_tvalid),
.AURORA_RX_TDATA(a_rx_tdata),
.AURORA_RX_TVALID(a_rx_tvalid),
.FIFO_CLK(fifo_clk),
.TX_FIFO_Q(tx_fifo_q),
.TX_FIFO_WREN(tx_fifo_wren),
.TX_FIFO_FULL(tx_fifo_full),
.RX_FIFO_Q(rx_fifo_q),
.RX_FIFO_RDEN(rx_fifo_rden),
.RX_FIFO_EMPTY(rx_fifo_empty),
.ERR(err)
);
//initial begin
//$dumpfile("fifo_over_ufc.vcd");
//$dumpvars(0, fifo_over_ufc);
//end
initial begin
clk = 0;
reset = 0;
#16 reset = 1;
#26 reset = 0;
#200 reset = 1;
#10 reset = 0;
end
always #5 clk = ~clk;
initial begin
rx_fifo_empty = 1;
a_rx_tvalid = 0;
tx_fifo_full = 0;
#46 rx_fifo_empty = 0;
#120 rx_fifo_empty = 1;
#40 a_rx_tvalid = 1;
#10 a_rx_tvalid = 0; tx_fifo_full = 1;
end
// emulate Aurora UFC interface
reg [1:0] state;
localparam S0 = 2'h0;
localparam S1 = 2'h1;
localparam S2 = 2'h2;
localparam S3 = 2'h3;
always @ (posedge clk or posedge reset) begin
if (reset) begin
state <= S0;
a_tx_tready <= 1;
end
else begin
a_tx_tready <= 1;
case (state)
S0: begin
state <= S0;
if (a_tx_req == 1) begin
state <= S1;
a_tx_tready <= 0;
end
end
S1: begin
state <= S2;
a_tx_tready <= 0;
end
S2: begin
state <= S3;
a_tx_tready <= 1;
end
S3: begin
state <= S3;
a_tx_tready <= 1;
if (a_tx_tvalid == 1) begin
state <= S0;
end
end
default: begin
state <= S0;
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> #define MOD 998244353 using namespace std; #define rep(i, a, b) for(int i = a; i < (b); ++i) #define rrep(i, a, b) for(int i = (a-1); i >= (b); --i) #define trav(a, x) for(auto& a : x) #define all(x) begin(x), end(x) #define sz(x) (int)(x).size() typedef long long ll; typedef pair<int, int> pii; typedef vector<int> vi; void solve() { int n; cin >> n; vector<vector<int>> a(2*n, vector<int>(n)); vector<vector<set<int>>> S(n, vector<set<int>>(n)); rep(i,0,2*n) { rep(j,0,n) { cin >> a[i][j]; --a[i][j]; S[j][a[i][j]].insert(i); } } ll ans = 1; vector<bool> used(2*n, false); vector<int> side(2*n); int I = 0; while (true) { bool any = false; int r; int i = I; while (!any) { rep(j,0,n) { if (sz(S[i][j]) == 1) { any = true; r = *S[i][j].begin(); break; } } if (any) break; i = (i+1)%n; if (i == I) break; } I = i; if (!any) { rep(i,0,2*n) if (!used[i]) { r = i; any = true; } if (!any) break; ans = (ans*2) % MOD; } used[r] = true; side[r] = 0; set<int> toRemove; rep(l,0,n) { for (int k : S[l][a[r][l]]) { toRemove.insert(k); } } for (int k : toRemove) { used[k] = true; side[k] = k == r; rep(l,0,n) S[l][a[k][l]].erase(k); } } cout << ans << endl; rep(i,0,2*n) { if (side[i] == 1) { cout << i+1 << ; } } cout << endl; } int main() { cin.sync_with_stdio(0); cin.tie(0); cin.exceptions(cin.failbit); int t; cin >> t; while (t--) solve(); } |
#include <bits/stdc++.h> using namespace std; inline int read() { register int res = 0; register char c = getchar(), f = 1; while (c < 48 || c > 57) { if (c == - ) f = 0; c = getchar(); } while (c >= 48 && c <= 57) res = (res << 3) + (res << 1) + (c & 15), c = getchar(); return f ? res : -res; } inline void write(long long x) { register char c[21], len = 0; if (!x) return putchar( 0 ), void(); if (x < 0) x = -x, putchar( - ); while (x) c[++len] = x % 10, x /= 10; while (len) putchar(c[len--] + 48); } const int N = 1e5 + 10, L = 20; struct node { int sz, a[L]; inline node(int x = -1) { if (~x) { sz = 1; for (int i = 0; i < L; ++i, x >>= 1) a[i] = x & 1; } else sz = 0, memset(a, 0, sizeof(a)); } inline node operator+(const node& p) const { node r = *this; r.sz += p.sz; for (int i = 0; i < L; ++i) r.a[i] += p.a[i]; return r; } inline node operator^(int x) const { node r = *this; for (int i = 0; i < L; ++i, x >>= 1) r.a[i] = x & 1 ? sz - a[i] : a[i]; return r; } } a[N], sum[N]; inline void write(const node& x) { long long r = 0; for (int i = 0; i < L; ++i) r += (long long)x.a[i] << i; write(r); } int n, m, rt, w[N], lc[N], rc[N], tag[N], tot = 0; inline void pu(int x) { sum[x] = sum[lc[x]] + sum[rc[x]] + a[x]; } int build(int l, int r) { if (l > r) return 0; int mid = (l + r) >> 1, x = mid; w[x] = ++tot; lc[x] = build(l, mid - 1), rc[x] = build(mid + 1, r); pu(x); return x; } inline void add(int x, int t) { a[x] = a[x] ^ t, sum[x] = sum[x] ^ t, tag[x] ^= t; } inline void pd(int x) { if (tag[x]) add(lc[x], tag[x]), add(rc[x], tag[x]), tag[x] = 0; } int merge(int x, int y) { if (!x || !y) return x | y; if (w[x] < w[y]) { pd(x), rc[x] = merge(rc[x], y), pu(x); return x; } else { pd(y), lc[y] = merge(x, lc[y]), pu(y); return y; } } void split(int rt, int k, int& x, int& y) { if (!rt) return x = y = 0, void(); pd(rt); if (sum[lc[rt]].sz < k) { x = rt; split(rc[x], k - sum[lc[x]].sz - 1, rc[x], y); pu(x); } else { y = rt; split(lc[y], k, x, lc[y]); pu(y); } } int op, l, r, x, y, z; int main() { n = read(); for (int i = 1; i <= n; ++i) sum[i] = a[i] = read(); m = read(); rt = build(1, n); while (m--) { op = read(), l = read(), r = read(); if (op == 1) { split(rt, r, x, z); split(x, l - 1, x, y); write(sum[y]), putchar( n ); rt = merge(merge(x, y), z); } else { split(rt, r, x, z); split(x, l - 1, x, y); add(y, read()); rt = merge(merge(x, y), z); } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_MUX_2TO1_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_MUX_2TO1_BLACKBOX_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_mux_2to1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_MUX_2TO1_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O22AI_BEHAVIORAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_BEHAVIORAL_PP_V |
`timescale 1ns/1ps
module tx_packer
( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
input [15:0]usbdata,
// TX Side
input reset,
input txclk,
output reg [31:0] usbdata_final,
output reg WR_final,
output wire test_bit0,
output reg test_bit1
);
reg [8:0] write_count;
/* Fix FX2 bug */
always @(posedge usbclk)
begin
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR_fx2 & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR_fx2 ? write_count : 9'b0;
end
reg WR_fx2_fixed;
reg [15:0]usbdata_fixed;
always @(posedge usbclk)
begin
WR_fx2_fixed <= WR_fx2 & ~write_count[8];
usbdata_fixed <= usbdata;
end
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
reg word_complete ;
reg [15:0] usbdata_delayed ;
reg writing ;
wire [31:0] usbdata_packed ;
wire WR_packed ;
//////////////////////////////////////////////test code
// assign usbdata_xor = ((usbdata_fixed[15] ^ usbdata_fixed[14]) | (usbdata_fixed[13] ^ usbdata_fixed[12]) |
// (usbdata_fixed[11] ^ usbdata_fixed[10]) | (usbdata_fixed[9] ^ usbdata_fixed[8]) |
// (usbdata_fixed[7] ^ usbdata_fixed[6]) | (usbdata_fixed[5] ^ usbdata_fixed[4]) |
// (usbdata_fixed[3] ^ usbdata_fixed[2]) | (usbdata_fixed[1] ^ usbdata_fixed[0]) |
// (usbdata_fixed[15] ^ usbdata_fixed[11]) | (usbdata_fixed[7] ^ usbdata_fixed[3]) |
// (usbdata_fixed[13] ^ usbdata_fixed[9]) | (usbdata_fixed[5] ^ usbdata_fixed[1]) )
// & WR_fx2_fixed;
assign usbdata_xor = ((usbdata_fixed[15] & usbdata_fixed[14]) & (usbdata_fixed[13] & usbdata_fixed[12]) &
(usbdata_fixed[11] & usbdata_fixed[10]) & (usbdata_fixed[9] & usbdata_fixed[8]) &
(usbdata_fixed[7] & usbdata_fixed[6]) & (usbdata_fixed[5] & usbdata_fixed[4]) &
(usbdata_fixed[3] & usbdata_fixed[2]) & (usbdata_fixed[1] & usbdata_fixed[0]) &
WR_fx2_fixed);
assign test_bit0 = txclk ;
//always @(posedge usbclk)
// begin
// test_bit0 <= usbdata_xor;
// end
//////////////////////////////////////////////test code
always @(posedge usbclk)
begin
if (bus_reset)
begin
word_complete <= 0 ;
writing <= 0 ;
end
else if (WR_fx2_fixed)
begin
writing <= 1 ;
if (word_complete)
word_complete <= 0 ;
else
begin
usbdata_delayed <= usbdata_fixed ;
word_complete <= 1 ;
end
end
else
writing <= 0 ;
end
assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
assign WR_packed = word_complete & writing ;
/* Make sure data are sync with usbclk */
reg [31:0]usbdata_usbclk;
reg WR_usbclk;
always @(posedge usbclk)
begin
if (WR_packed)
usbdata_usbclk <= usbdata_packed;
WR_usbclk <= WR_packed;
end
/* Cross clock boundaries */
reg [31:0] usbdata_tx ;
reg WR_tx;
reg WR_1;
reg WR_2;
always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
always @(posedge txclk)
if (reset)
WR_1 <= 0;
else
WR_1 <= WR_usbclk;
always @(posedge txclk)
if (reset)
WR_2 <= 0;
else
WR_2 <= WR_1;
always @(posedge txclk)
begin
if (reset)
WR_tx <= 0;
else
WR_tx <= WR_1 & ~WR_2;
end
always @(posedge txclk)
begin
if (reset)
WR_final <= 0;
else
begin
WR_final <= WR_tx;
if (WR_tx)
usbdata_final <= usbdata_tx;
end
end
///////////////////test output
always @(posedge txclk)
begin
if (reset)
test_bit1 <= 0;
else if (!WR_final)
test_bit1 <= test_bit1;
else if ((usbdata_final == 32'hffff0000))
test_bit1 <= 0;
else
test_bit1 <= 1;
end
///////////////////////////////
// always @(posedge usbclk)
// begin
// if (bus_reset)
// begin
// test_bit0 <= 1'b0;
// end
// else if (usbdata_packed[0] ^ usbdata_packed[16])
// test_bit0 <= 1'b1;
// else
// test_bit0 <= 1'b0;
// end
// Test comparator for 16 bit hi & low data
// add new test bit
// wire [15:0] usbpkd_low;
// wire [15:0] usbpkd_hi;
//
// assign usbpkd_low = usbdata_delayed;
// assign usbpkd_hi = usbdata_fixed;
//
// always @(posedge usbclk)
// begin
// if (bus_reset)
// begin
// test_bit1 <= 1'b0;
// end
// else
// begin
// // test_bit1 <= (usbpkd_low === usbpkd_hi) ? 1'b1 : 1'b0;
// if (usbpkd_low == usbpkd_hi)
// test_bit1 <= 1'b1;
// else
// test_bit1 <= 1'b0;
// end
// end
endmodule
|
module RegisterFileTestBench4;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] in,Pcin;
reg [19:0] RSLCT;
reg Clk, RESET, LOADPC, LOAD,IR_CU;
wire [31:0] Rn,Rm,Rs,PCout;
//RegisterFile(input [31:0] in,Pcin,input [19:0] RSLCT,input Clk, RESET, LOADPC, LOAD,IR_CU, output [31:0] Rn,Rm,Rs,PCout);
RegisterFile RF(in,Pcin,RSLCT,Clk, RESET, LOADPC, LOAD,IR_CU, Rn,Rm,Rs,PCout);
initial fork
//Clk 0
Clk = 0 ; RESET = 1 ; Pcin = 32'bz ; in = 32'bz ; LOADPC = 0 ; LOAD = 0 ;IR_CU = 1 ; RSLCT[3:0] = 0 ; RSLCT[7:4] = 0 ; RSLCT[11:8] = 0 ; RSLCT[15:12] = 0 ; RSLCT[19:16] = 0 ;
//Clk 1 (Rising Edge)
#1 RESET = 0 ; #1 Pcin = 0 ; #1 in =0 ; #1 LOADPC = 0 ; #1 LOAD = 0 ; #1 IR_CU = 1 ; #1 RSLCT[3:0] = 0 /* Rn */ ; #1 RSLCT[7:4] = 0 /* Rm */; #1 RSLCT[11:8] = 0 /* Rs */; #1 RSLCT[15:12] = 0 /* Rd */; #1 RSLCT[19:16] = 0 /* Rn */ ;
//Clk 0 (Falling Edge)
#2 Pcin = 1; #2 in = 0 ; #2 LOADPC = 1 ; #2 LOAD = 0 ; #2 IR_CU = 1 ; #2 RSLCT[3:0] = 0 /* Rn */ ; #2 RSLCT[7:4] = 0 /* Rm */; #2 RSLCT[11:8] = 0 /* Rs */; #2 RSLCT[15:12] = 0 /* Rd */; #2 RSLCT[19:16] = 0 /* Rn */ ;
//Clk 1 (Rising Edge)
#3 Pcin = 1 ; #3 in =0 ; #3 LOADPC = 1 ; #3 LOAD = 0 ; #3 IR_CU = 1 ; #3 RSLCT[3:0] = 0 /* Rn */ ; #3 RSLCT[7:4] = 0 /* Rm */; #3 RSLCT[11:8] = 0 /* Rs */; #3 RSLCT[15:12] = 0 /* Rd */; #3 RSLCT[19:16] = 0 /* Rn */ ;
//Clk 0 (Falling Edge)
#4 Pcin = 1; #4 in = 0 ; #4 LOADPC = 1 ; #4 LOAD = 0 ; #4 IR_CU = 1 ; #4 RSLCT[3:0] = 0 /* Rn */ ; #4 RSLCT[7:4] = 0 /* Rm */; #4 RSLCT[11:8] = 0 /* Rs */; #4 RSLCT[15:12] = 0 /* Rd */; #4 RSLCT[19:16] = 0 /* Rn */ ;
//Clk 1 (Rising Edge)
#5 Pcin = in ; #5 in =1 ; #5 LOADPC = 0 ; #5 LOAD = 0 ; #5 IR_CU = 1 ; #5 RSLCT[3:0] = 0 /* Rn */ ; #5 RSLCT[7:4] = 0 /* Rm */; #5 RSLCT[11:8] = 0 /* Rs */; #5 RSLCT[15:12] = 0 /* Rd */; #5 RSLCT[19:16] = 0 /* Rn */ ;
//Clk 0 (Falling Edge)
#6 Pcin = in; #6 in = 1 ; #6 LOADPC = 1 ; #6 LOAD = 0 ; #6 IR_CU = 1 ; #6 RSLCT[3:0] = 0 /* Rn */ ; #6 RSLCT[7:4] = 0 /* Rm */; #6 RSLCT[11:8] = 0 /* Rs */; #6 RSLCT[15:12] = 0 /* Rd */; #6 RSLCT[19:16] = 0 /* Rn */ ;
//Clk 1 (Rising Edge)
#7 Pcin = in ; #7 in =1 ; #7 LOADPC = 1 ; #7 LOAD = 0 ; #7 IR_CU = 1 ; #7 RSLCT[3:0] = 0 /* Rn */ ; #7 RSLCT[7:4] = 0 /* Rm */; #7 RSLCT[11:8] = 0 /* Rs */; #7 RSLCT[15:12] = 0 /* Rd */; #7 RSLCT[19:16] = 0 /* Rn */ ;
//Clk 0 (Falling Edge)
#8 Pcin = in; #8 in = 1 ; #8 LOADPC = 1 ; #8 LOAD = 0 ; #8 IR_CU = 1 ; #8 RSLCT[3:0] = 0 /* Rn */ ; #8 RSLCT[7:4] = 0 /* Rm */; #8 RSLCT[11:8] = 0 /* Rs */; #8 RSLCT[15:12] = 0 /* Rd */; #8 RSLCT[19:16] = 0 /* Rn */ ;
//Clk 1 (Rising Edge)
#9 Pcin = in ; #9 in =2 ; #9 LOADPC = 0 ; #9 LOAD = 0 ; #9 IR_CU = 1 ; #9 RSLCT[3:0] = 0 /* Rn */ ; #9 RSLCT[7:4] = 0 /* Rm */; #9 RSLCT[11:8] = 0 /* Rs */; #9 RSLCT[15:12] = 0 /* Rd */; #9 RSLCT[19:16] = 0 /* Rn */ ;
//Clk 0 (Falling Edge)
#10 Pcin = in; #10 in = 2 ; #10 LOADPC = 0 ; #10 LOAD = 1 ; #10 IR_CU = 1 ; #10 RSLCT[3:0] = 0 /* Rn */ ; #10 RSLCT[7:4] = 0 /* Rm */; #10 RSLCT[11:8] = 0 /* Rs */; #10 RSLCT[15:12] = 0 /* Rd */; #10 RSLCT[19:16] = 0 /* Rn */ ;
//Clk 1 (Rising Edge)
#11 Pcin = in ; #11 in =2 ; #11 LOADPC = 0 ; #11 LOAD = 1 ; #11 IR_CU = 1 ; #11 RSLCT[3:0] = 0 /* Rn */ ; #11 RSLCT[7:4] = 0 /* Rm */; #11 RSLCT[11:8] = 0 /* Rs */; #11 RSLCT[15:12] = 0 /* Rd */; #11 RSLCT[19:16] = 0 /* Rn */ ;
//Clk 0 (Falling Edge)
#12 Pcin = in; #12 in = 2 ; #12 LOADPC = 0 ; #12 LOAD = 1 ; #12 IR_CU = 1 ; #12 RSLCT[3:0] = 0 /* Rn */ ; #12 RSLCT[7:4] = 0 /* Rm */; #12 RSLCT[11:8] = 0 /* Rs */; #12 RSLCT[15:12] = 0 /* Rd */; #12 RSLCT[19:16] = 0 /* Rn */ ;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("RegisterFileTestBench4.vcd");
$dumpvars(0,RegisterFileTestBench4);
$display(" Test Results" );
$monitor("time = %3d ,Pcin = %3d , in = %3d , LOADPC = %3d , LOAD = %3d , IR_CU = %3d , RSLCT = %3d , Rn = %3d ,Rm = %3d ,Rs = %3d ,PCout = %3d",$time,Pcin, in, LOADPC, LOAD, IR_CU, RSLCT,Rn,Rm,Rs,PCout);
end
endmodule
//iverilog Buffer32_32.v Decoder4x16.v Multiplexer2x1_32b.v Register.v RegisterFile.v RegisterFileTestBench4.v |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// ALTERA Confidential and Proprietary
// Copyright 2007 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
`timescale 1ps/1ps
module altera_tse_fake_master(
// Clock and reset
input clk,
input reset,
// Avalon MM master interface
output [8:0] phy_mgmt_address,
output phy_mgmt_read,
input [31:0] phy_mgmt_readdata,
output phy_mgmt_write,
output reg [31:0] phy_mgmt_writedata,
input phy_mgmt_waitrequest,
// Serial data loopback control
input sd_loopback
);
//////////////////////////////////internal registers and paramaters//////////////////////////////////
reg [1:0] state;
reg [1:0] next_state;
reg sd_loopback_r1, sd_loopback_r2;
reg bit_event;
localparam IDLE = 2'b0 ;
localparam WRITE_DATA = 2'b1;
////////////////////to detect the toggled data from sd_loopback //////////
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
sd_loopback_r1 <= 1'b0;
sd_loopback_r2 <= 1'b0;
end
else
begin
sd_loopback_r2 <= sd_loopback_r1;
sd_loopback_r1 <= sd_loopback;
end
end
// bit_event is the bit to remember there is an event happening at the sd_loopback
// and used to trigger IDLE -> WRITE_DATA state transition
// This bit is only cleared during WRITE_DATA -> IDLE transition and make sure that
// phy_mgmt_writedata[0] value is equal to sd_loopback data
// This is to ensure that our Avalon MM write transaction is always in sync with sd_loopback value
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bit_event <= 0;
end
else
begin
if ( sd_loopback_r1 != sd_loopback_r2)
begin
bit_event <= 1'b1;
end
else
begin
if (next_state == IDLE && state == WRITE_DATA && phy_mgmt_writedata[0] == sd_loopback)
begin
bit_event <= 1'b0;
end
end
end
end
// State machine
always @ (posedge clk or posedge reset)
begin
if (reset)
state <= IDLE;
else
state <= next_state;
end
// next_state logic
always @ (*)
begin
case (state)
IDLE:
begin
if (bit_event)
next_state = WRITE_DATA;
else
next_state = IDLE;
end
WRITE_DATA:
begin
if (!phy_mgmt_waitrequest)
next_state = IDLE;
else
next_state = WRITE_DATA;
end
default : next_state = IDLE;
endcase
end
// Connection to PHYIP (Avalon MM master signals)
assign phy_mgmt_write = (state == WRITE_DATA)? 1'b1 : 1'b0;
assign phy_mgmt_read = 1'b0;
assign phy_mgmt_address = (state == WRITE_DATA) ? 9'h61 : 9'h0;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
phy_mgmt_writedata <= 32'b0;
end
else
begin
if (state == IDLE && next_state == WRITE_DATA)
begin
phy_mgmt_writedata <= {31'b0, sd_loopback};
end
else if (state == WRITE_DATA && next_state == IDLE)
begin
phy_mgmt_writedata <= 32'b0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 100; int ans[N], link[N]; int main() { ios_base ::sync_with_stdio(0); cin.tie(0); int n, k; cin >> n >> k; for (int i = 1; i <= n; ++i) { int x; cin >> x; int down = max(1, i - k); int up = min(n, i + k); int down2 = max(1, x - k); int up2 = min(n, x + k); if (x == 0) { ans[i] = up - down + 1 + ans[x]; } else { if (up2 < down) ans[i] = up - down + 1 + ans[x]; else ans[i] = up - down + 1 + ans[x] - (up2 - down + 1); } cout << ans[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; bool ask(long long l, long long r) { printf( %lld %lld n , l, r); fflush(stdout); char x[4]; scanf( %s , x); return x[0] == Y ; } long long n, k; int main() { cin >> n >> k; long long l = 1, r = n; srand(time(0)); while (1) { if (r - l + 1 <= 50) { long long q = l + rand() % (r - l + 1); if (ask(q, q)) return 0; l = max(1LL, l - k); r = min(n, r + k); } else { long long md = l + ((r - l) >> 1); if (ask(l, md)) { l = max(1LL, l - k); r = min(n, md + k); } else { l = max(1LL, md + 1 - k); r = min(n, r + k); } } } } |
#include <bits/stdc++.h> using namespace std; int main() { long long int n; cin >> n; long long int sum = n * (n - 1) / 2; if (n == 0) { cout << 0; return 0; } if ((n % 2 == 0 && n % 4 != 0) || (n % 2 == 1 && n % 4 != 3)) cout << 1; else cout << 0; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; long long s = 0; cin >> n; for (int i = 2; i <= n / 2; i++) { for (int j = 2; j * i <= n; j++) s += 4 * j; } cout << s << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__HA_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__HA_PP_BLACKBOX_V
/**
* ha: Half adder.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__ha (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__HA_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const long long int N = 70, M = 11, MA = 1030; long long int dp[M][N][M][MA], dps[M][N][MA], dpt[M][N], n, q, b, l, r, x; vector<long long int> v; long long int get(long long int a, long long int b) { long long int x = a, ans, mask = 0, l; v.resize(0); while (x > 0) { v.push_back(x % b); x /= b; } l = (long long int)v.size(); ans = dpt[b][l]; reverse(v.begin(), v.end()); for (auto y : v) { for (int j = b - 1; j > y; j--) ans -= dp[b][l][j][mask]; mask ^= (1 << y); l--; } return ans; } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); for (long long int bi = 2; bi <= 10; bi++) { for (int l = 2; l <= 65; l++) { for (int c = 0; c < bi; c++) { dp[bi][1][c][(1ll << c)] = 1; for (int mask = 0; mask < (1ll << bi); mask++) dps[bi][1][mask] += dp[bi][1][c][mask]; } dpt[bi][1] = 0; } } for (long long int bi = 2; bi <= 10; bi++) { for (int l = 2; l <= 65; l++) { dpt[bi][l] = dpt[bi][l - 1]; for (int c = 0; c < bi; c++) { for (int i = 0; i < bi; i++) for (int mask = 0; mask < (1ll << bi); mask++) { x = mask, x ^= (1ll << c); dp[bi][l][c][mask] += dp[bi][l - 1][i][x]; } for (int mask = 0; mask < (1ll << bi); mask++) dps[bi][l][mask] += dp[bi][l][c][mask]; if (c != 0) dpt[bi][l] += dp[bi][l][c][0]; } } } cin >> q; for (int i = 1; i <= q; i++) { cin >> b >> l >> r; l--; cout << get(r, b) - get(l, b) << n ; } } |
#include <bits/stdc++.h> using namespace std; int main() { long long int r, x1, y1, x2, y2; cin >> r >> x1 >> y1 >> x2 >> y2; long long int xd = x2 - x1, yd = y2 - y1; double dist = sqrt(xd * xd + yd * yd); long long int int_part = (int)dist; double frac_part = dist - int_part; long long int ans; ans = int_part / (2 * r); if (int_part % (2 * r) == 0 && frac_part == 0) ans--; ans++; cout << ans << endl; } |
module auto_module
( input my_clk,
input my_rst_n,
output manually_listed,
/*AUTOINOUTMODPORT("automodport_if" "pure_mp")*/
// Beginning of automatic in/out/inouts (from modport)
output out_pure,
input in_pure,
// End of automatics
//ex: input in_pure;
//ex: output out_pure;
/*AUTOINOUTMODPORT("automodport_if" "req_mon_mp")*/
// Beginning of automatic in/out/inouts (from modport)
input req_val,
input [63:0] req_dat,
input req_credit,
// End of automatics
//ex: input req_credit, // To auto_i of auto_intf.sv
//ex: input [63:0] req_data, // To auto_i of auto_intf.sv
//ex: input req_val, // To auto_i of auto_intf.sv
/*AUTOINOUTMODPORT("automodport_if" "rsp_drv_mp")*/
// Beginning of automatic in/out/inouts (from modport)
output [1:0] rsp_cmd,
output [63:0] rsp_data,
input rsp_credit
// End of automatics
//ex: output [1:0] rsp_cmd, // From auto_i of auto_intf.sv
//ex: input rsp_credit, // To auto_i of auto_intf.sv
//ex: output [63:0] rsp_data // From auto_i of auto_intf.sv
);
auto_intf auto_i
(// Inputs
.clk (my_clk),
.rst_n (my_rst_n));
/*AUTOASSIGNMODPORT("automodport_if", "req_mon_mp", "auto_i" )*/
// Beginning of automatic assignments from modport
assign auto_i.manually_listed = manually_listed;
assign auto_i.req_credit = req_credit;
assign auto_i.req_dat = req_dat;
assign auto_i.req_val = req_val;
// End of automatics
//ex: assign auto_i.req_credit = req_credit;
//ex: assign auto_i.req_data = req_data;
//ex: assign auto_i.req_val = req_val;
/*AUTOASSIGNMODPORT("automodport_if", "rsp_drv_mp", "auto_i" )*/
// Beginning of automatic assignments from modport
assign rsp_cmd = auto_i.rsp_cmd;
assign rsp_data = auto_i.rsp_data;
assign auto_i.rsp_credit = rsp_credit;
// End of automatics
//ex: assign rsp_cmd = auto_i.rsp_cmd;
//ex: assign rsp_data = auto_i.rsp_data;
//ex: assign auto_i.rsp_credit = rsp_credit;
/*AUTOASSIGNMODPORT("automodport_if", "r.*", "auto_i" )*/
// Beginning of automatic assignments from modport
assign rsp_cmd = auto_i.rsp_cmd;
assign rsp_data = auto_i.rsp_data;
assign auto_i.manually_listed = manually_listed;
assign auto_i.req_credit = req_credit;
assign auto_i.req_dat = req_dat;
assign auto_i.req_val = req_val;
assign auto_i.rsp_credit = rsp_credit;
// End of automatics
initial begin
`cn_set_intf(virtual auto_intf.req_mon_mp, "auto_pkg::auto_intf", "req_mon_vi", auto_i.req_mon_mp );
`cn_set_intf(virtual auto_intf.rsp_drv_mp, "auto_pkg::auto_intf", "rsp_drv_vi", auto_i.rsp_drv_mp );
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_impctl_dtl_dnrcn.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_impctl_dtl_dnrcn(above ,global_reset_n ,cbd ,sclk ,se ,vddo
,si_l ,pad ,clk ,so_l );
input [8:1] cbd ;
output above ;
output pad ;
output so_l ;
input global_reset_n ;
input sclk ;
input se ;
input vddo ;
input si_l ;
input clk ;
supply1 vdd ;
supply0 vss ;
wire net102 ;
wire net103 ;
wire net104 ;
wire net105 ;
wire net106 ;
wire net71 ;
wire net73 ;
wire net111 ;
wire sclk1 ;
wire sclk2 ;
wire net115 ;
wire srcv ;
wire bsr_dn_l ;
wire si ;
wire scan1 ;
wire net95 ;
wire bsr_dn25_l ;
wire net064 ;
wire bsr_up ;
wire net56 ;
wire net57 ;
wire abvref ;
wire net65 ;
wire net68 ;
wire net101 ;
bw_io_dtl_drv_zctl I227 (
.cbu ({vss ,vss ,vss ,vss ,vss ,vss ,vss ,vss } ),
.cbd ({cbd } ),
.pad (pad ),
.sel_data_n (vss ),
.pad_up (net111 ),
.pad_dn_l (net101 ),
.pad_dn25_l (net102 ),
.por (net115 ),
.bsr_up (bsr_up ),
.bsr_dn_l (bsr_dn_l ),
.bsr_dn25_l (bsr_dn25_l ),
.vddo (vddo ) );
bw_io_dtlhstl_rcv I1 (
.out (abvref ),
.so (srcv ),
.pad (net95 ),
.ref (net064 ),
.clk (clk ),
.pad_clk_en_l (net103 ),
.cmsi_clk_en_l (net104 ),
.cmsi_l (net105 ),
.se_buf (net106 ),
.vddo (vddo ) );
bw_u1_soff_4x I257 (
.q (sclk1 ),
.so (net56 ),
.ck (clk ),
.d (sclk ),
.se (se ),
.sd (srcv ) );
bw_u1_soffr_4x I260 (
.q (sclk2 ),
.so (scan1 ),
.ck (clk ),
.d (sclk1 ),
.se (se ),
.sd (net56 ),
.r_l (global_reset_n ) );
bw_u1_soffr_4x I263 (
.q (above ),
.so (net57 ),
.ck (clk ),
.d (net71 ),
.se (se ),
.sd (scan1 ),
.r_l (global_reset_n ) );
bw_u1_inv_4x I268 (
.z (net73 ),
.a (sclk2 ) );
bw_u1_nand2_4x I269 (
.z (net71 ),
.a (net65 ),
.b (net68 ) );
bw_u1_nand2_4x I270 (
.z (net68 ),
.a (net73 ),
.b (above ) );
bw_u1_nand2_4x I271 (
.z (net65 ),
.a (abvref ),
.b (sclk2 ) );
bw_u1_inv_4x I304 (
.z (si ),
.a (si_l ) );
bw_u1_inv_4x I305 (
.z (so_l ),
.a (net57 ) );
bw_io_dtl_edgelogic I306 (
.pad_clk_en_l (net103 ),
.cmsi_clk_en_l (net104 ),
.bsr_dn25_l (bsr_dn25_l ),
.pad_dn_l (net101 ),
.pad_dn25_l (net102 ),
.bsr_up (bsr_up ),
.bsr_mode (vss ),
.bsr_data_to_core (vss ),
.por_l (vdd ),
.bsr_dn_l (bsr_dn_l ),
.se_buf (net106 ),
.cmsi_l (net105 ),
.por (net115 ),
.reset_l (vdd ),
.sel_bypass (vss ),
.up_open (vss ),
.oe (vdd ),
.down_25 (vss ),
.clk (clk ),
.data (vss ),
.se (se ),
.si (si ),
.pad_up (net111 ) );
bw_io_ic_filter I310 (
.torcvr (net95 ),
.topad (pad ),
.vddo (vddo ) );
bw_io_dtl_vref I313 (
.vref_impctl (net064 ),
.vddo (vddo ) );
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR2_BLACKBOX_V
`define SKY130_FD_SC_HD__XOR2_BLACKBOX_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xor2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR2_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBP_1_V
`define SKY130_FD_SC_LP__DFBBP_1_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog wrapper for dfbbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfbbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBP_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> v(n); for (int i = 0; i != n; ++i) { cin >> v[i]; v[i] -= (n - i); } sort(v.begin(), v.end()); for (int i = 0; i != n - 1; ++i) { if (v[i] + 1 > v[i + 1]) { cout << :( n ; return 0; } } for (int i = 0; i != n; ++i) { cout << v[i] + (n - i) << ; } return 0; } |
`timescale 1ns / 1ps
module RM_ctl # (
parameter integer C_STEP_NUMBER_WIDTH = 32,
parameter integer C_SPEED_DATA_WIDTH = 32
) (
input wire clk,
input wire resetn,
output reg exe_done,
input wire req_abs,
input wire [C_SPEED_DATA_WIDTH-1:0] req_speed,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] req_step,
output wire m_sel ,
input wire m_ntsign ,
input wire m_zpsign ,
input wire m_ptsign ,
input wire m_state ,
input wire signed [C_STEP_NUMBER_WIDTH-1:0] m_position,
output reg m_start ,
output reg m_stop ,
output reg [C_SPEED_DATA_WIDTH-1:0] m_speed ,
output reg signed [C_STEP_NUMBER_WIDTH-1:0] m_step ,
output reg m_abs ,
output reg m_mod_remain,
output reg signed [C_STEP_NUMBER_WIDTH-1:0] m_new_remain
);
reg m_started;
wire m_running;
assign m_running = m_state;
always @ (posedge clk) begin
if (resetn == 1'b0)
m_started <= 1'b0;
else if (m_start)
m_started <= 1'b1;
end
reg m_run_over;
always @ (posedge clk) begin
if (resetn == 1'b0)
m_run_over <= 1'b0;
else if (m_running)
m_run_over <= 1'b1;
end
wire m_stopped;
assign m_stopped = (m_run_over && ~m_running);
/// stop
always @ (posedge clk) begin
if (resetn == 1'b0)
m_stop <= 1'b0;
else if (m_stop == 1'b1)
m_stop <= 1'b0;
/// @todo always 0 now
end
/// start
always @ (posedge clk) begin
if (resetn == 1'b0) begin
m_start <= 1'b0;
end
else if (m_start == 1'b1) begin
m_start <= 1'b0;
end
else if (m_started == 1'b0) begin
m_start <= 1'b1;
m_speed <= req_speed;
m_step <= req_step;
m_abs <= req_abs;
end
end
/// change remain step
always @ (posedge clk) begin
if (resetn == 1'b0) begin
m_mod_remain <= 1'b0;
m_new_remain <= 0;
end
end
//////////////// exe_done
always @ (posedge clk) begin
if (resetn == 1'b0)
exe_done <= 1'b0;
else if (m_stopped)
exe_done <= 1'b1;
end
assign m_sel = resetn;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long a, b, c, d = 0, e = 0, f = 0, g = 0, i, j, k = 1, l = 1, r = 1, n[300001], m[300001], q, u, v, w, y, z[400001], h[400001], p[500001]; string s, t, x; cin >> a >> b >> c; for (i = 1; i <= a; i++) { cin >> d >> e; f += (d - g) / c; g = d + e; } cout << f + ((b - g) / c); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD3_BEHAVIORAL_PP_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD3_BEHAVIORAL_PP_V |
// soc_design_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
soc_design_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; constexpr int kN = int(1E7 + 10); vector<long long int> prime; int l[kN], mu[kN], s[kN]; long long int n; void pre() { mu[1] = 1; for (int i = 2; i <= n; i++) { if (l[i] == 0) { mu[i] = -1; prime.push_back(l[i] = i); } for (int j : prime) { if (i * j > n) break; l[i * j] = min(l[i], j); if (i % j == 0) { mu[i * j] = 0; break; } else mu[i * j] = -mu[i]; } } for (int i = 2; i <= n; i++) s[l[i]]++; for (int i = 3; i <= n; i++) s[i] += s[i - 1]; return; } int main() { long long int ans = 0, one = 0, two = 0, three = 0, zero = 0, cnt = 1; scanf( %lld , &n); pre(); for (int k = 1; k <= n; k++) one += mu[k] * (n / k) * (n / k); one = n * (n - 1) / 2 - (one >> 1); for (long long int i : prime) if (i * i < n) continue; else if ((i << 1) > n) cnt++; else if (i > n / i) three += s[i - 1] - s[n / i]; zero = (((n - 1) + (n - cnt)) * cnt) >> 1; two = n * (n - 1) / 2 - zero - one - three; ans = one + two * 2 + three * 3; printf( %lld n , ans); } |
// Via http://www.edaplayground.com/s/6/591
// stackoverflow 20556634
// http://stackoverflow.com/questions/20556634/how-can-i-iteratively-create-buses-of-parameterized-size-to-connect-modules-also
// Code your design here
`define macro_args
`define indexed_part_select
module Multiplier_flat #(parameter M = 4, parameter N = 4)(
input [M-1:0] A, //Input A, size M
input [N-1:0] B, //Input B, size N
output [M+N-1:0] P ); //Output P (product), size M+N
/* Calculate LSB using Wolfram Alpha
N==3 : http://www.wolframalpha.com/input/?i=0%2C+4%2C+9%2C+15%2C+...
N==4 : http://www.wolframalpha.com/input/?i=0%2C+5%2C+11%2C+18%2C+26%2C+35%2C+...
N==5 : http://www.wolframalpha.com/input/?i=0%2C+6%2C+13%2C+21%2C+30%2C+...
*/
`ifdef macro_args
// initial $display("Use Macro Args");
`define calc_pp_lsb(n) (((n)-1)*((n)+2*M)/2)
//`define calc_pp_msb(n) (`calc_pp_lsb(n+1)-1)
`define calc_pp_msb(n) ((n**2+(2*M+1)*n-2)/2)
//`define calc_range(n) `calc_pp_msb(n):`calc_pp_lsb(n)
`define calc_pp_range(n) `calc_pp_lsb(n) +: (M+n)
wire [`calc_pp_msb(N):0] PP;
assign PP[`calc_pp_range(1)] = { 1'b0 , { A & {M{B[0]}} } };
assign P = PP[`calc_pp_range(N)];
`elsif indexed_part_select
// initial $display("Use Indexed Part Select");
localparam MSB = (N**2+(2*M+1)*N-2)/2;
wire [MSB:0] PP;
assign PP[M:0] = { 1'b0 , { A & {M{B[0]}} } };
assign P = PP[MSB -: M+N];
`else
// initial $display("Use Worst Case");
localparam MSB = (N**2+(2*M+1)*N-2)/2;
wire [MSB:0] PP;
assign PP[M:0] = { 1'b0 , { A & {M{B[0]}} } };
assign P = PP[MSB : MSB+1-M-N];
`endif
genvar i;
generate
for (i=1; i < N; i=i+1)
begin: addPartialProduct
wire [M+i-1:0] gA,gB,gS;
wire Cout;
assign gA = { A & {M{B[i]}} , {i{1'b0}} };
`ifdef macro_args
assign gB = PP[`calc_pp_range(i)];
assign PP[`calc_pp_range(i+1)] = {Cout,gS};
`elsif indexed_part_select
assign gB = PP[(i-1)*(i+2*M)/2 +: M+i];
assign PP[i*((i+1)+2*M)/2 +: M+i+1] = {Cout,gS};
`else
localparam LSB = (i-1)*(i+2*M)/2;
localparam MSB = (i**2+(2*M+1)*i-2)/2;
localparam MSB2 = ((i+1)**2+(2*M+1)*(i+1)-2)/2;
assign gB = PP[MSB : LSB];
assign PP[ MSB2 : MSB+1] = {Cout,gS};
`endif
RippleCarryAdder#(M+i) adder( .A(gA), .B(gB), .S(gS), .Cin (1'b0), .Cout(Cout) );
end
endgenerate
`ifdef macro_args
// Cleanup global space
`undef calc_pp_range
`undef calc_pp_msb
`undef calc_pp_lsb
`endif
endmodule
module Multiplier_2D #(parameter M = 4, parameter N = 4)(
input [M-1:0] A, //Input A, size M
input [N-1:0] B, //Input B, size N
output [M+N-1:0] P ); //Output P (product), size M+N
wire [M+N-1:0] PP [N-1:0];
// Note: bits PP[0][M+N-1:M+1] are never used. Unused bits are optimized out during synthesis
//assign PP[0][M:0] = { {1'b0} , { A & {M{B[0]}} } };
//assign PP[0][M+N-1:M+1] = {(N-1){1'b0}}; // uncomment to make probing readable
assign PP[0] = { {N{1'b0}} , { A & {M{B[0]}} } };
assign P = PP[N-1];
genvar i;
generate
for (i=1; i < N; i=i+1)
begin: addPartialProduct
wire [M+i-1:0] gA,gB,gS; wire Cout;
assign gA = { A & {M{B[i]}} , {i{1'b0}} };
assign gB = PP[i-1][M+i-1:0];
//assign PP[i][M+i:0] = {Cout,gS};
//if (i+1<N) assign PP[i][M+N-1:M+i+1] = {(N-i){1'b0}}; // uncomment to make probing readable
assign PP[i] = { {(N-i){1'b0}}, Cout, gS};
RippleCarryAdder#(M+i) adder(
.A(gA), .B(gB), .S(gS), .Cin(1'b0), .Cout(Cout) );
end
endgenerate
//always@* foreach(S[i]) $display("S[%0d]:%b",i,S[i]);
endmodule
module RippleCarryAdder#(parameter N = 4)(A,B,Cin,S,Cout);
input [N-1:0] A;
input [N-1:0] B;
input Cin;
output [N-1:0] S;
output Cout;
wire [N:0] CC;
assign CC[0] = Cin;
assign Cout = CC[N];
genvar i;
generate
for (i=0; i < N; i=i+1)
begin: addbit
FullAdder unit(A[i],B[i],CC[i],S[i],CC[i+1]);
end
endgenerate
endmodule
module FullAdder(input A,B,Cin, output wire S,Cout);
assign {Cout,S} = A+B+Cin;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
wire bit [255:0] C = {32'h1111_1111,
32'h2222_2222,
32'h3333_3333,
32'h4444_4444,
32'h5555_5555,
32'h6666_6666,
32'h7777_7777,
32'h8888_8888};
// Same values as above, but with different type
wire logic [255:0] D = {32'h1111_1111,
32'h2222_2222,
32'h3333_3333,
32'h4444_4444,
32'h5555_5555,
32'h6666_6666,
32'h7777_7777,
32'h8888_8888};
initial begin
// Note: Base index via $c to prevent optimizatoin by Verilator
$display("0x%32x", C[$c(0*32)+:32]);
$display("0x%32x", D[$c(1*32)+:32]);
$display("0x%32x", C[$c(2*32)+:32]);
$display("0x%32x", D[$c(3*32)+:32]);
$display("0x%32x", C[$c(4*32)+:32]);
$display("0x%32x", D[$c(5*32)+:32]);
$display("0x%32x", C[$c(6*32)+:32]);
$display("0x%32x", D[$c(7*32)+:32]);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/27/2015 03:47:45 PM
// Design Name:
// Module Name: wildcard_processer
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module wildcard_processor
#(parameter NUM_OUTPUT_QUEUES = 8,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = DATA_WIDTH/8,
parameter RESULT_WIDTH = `OPENFLOW_ACTION_WIDTH,
parameter CURRENT_TABLE_ID = 0,
parameter TABLE_NUM=2
)
(
input [RESULT_WIDTH-1:0] result_fifo_dout,
output reg result_fifo_rd_en,
input result_fifo_empty,
input [CTRL_WIDTH-1:0] in_fifo_ctrl,
input [DATA_WIDTH-1:0] in_fifo_data,
output reg in_fifo_rd_en,
input in_fifo_empty,
output reg [DATA_WIDTH-1:0] out_data,
output reg [CTRL_WIDTH-1:0] out_ctrl,
output reg out_wr,
input out_rdy,
input wildcard_hit_dout,
output reg actions_en,
output reg actions_hit,
output reg [`OPENFLOW_ACTION_WIDTH-1:0] actions,
input clk,
input reset,
output reg [3:0] src_port,
input skip_lookup
);
reg [DATA_WIDTH-1:0] out_data_d1;
reg [CTRL_WIDTH-1:0] out_ctrl_d1;
reg [DATA_WIDTH-1:0] out_data_d2;
reg [CTRL_WIDTH-1:0] out_ctrl_d2;
reg out_wr_d1;
reg out_wr_d2;
reg out_wr_d3;
// assign out_data_d1=in_fifo_data;
// assign out_ctrl_d1=in_fifo_ctrl;
always@(posedge clk)
actions_hit<=wildcard_hit_dout;
always@(posedge clk)
begin
out_data_d1<=in_fifo_data;
out_ctrl_d1<=in_fifo_ctrl;
out_data_d2<=out_data_d1;
out_ctrl_d2<=out_ctrl_d1;
out_data<=out_data_d2;
out_ctrl<=out_ctrl_d2;
out_wr_d1<=in_fifo_rd_en;
out_wr_d2<=out_wr_d1;
out_wr_d3<=out_wr_d2;
out_wr<=out_wr_d3;
end
reg [`OPENFLOW_NEXT_TABLE_ID_WIDTH-1:0] pkt_dst_table_id;
reg [5:0]cur_st,nxt_st;
always@(posedge clk)
if(reset)
cur_st<=0;
else
cur_st<=nxt_st;
localparam IDLE=0,
WAIT_FOR_ACTION=1,
READ_ACTION=2,
READ_HEAD=3,
READ_DATA=4,
WAIT_EOP=5;
always@(*)
begin
nxt_st=cur_st;
case(cur_st)
IDLE:
nxt_st=WAIT_FOR_ACTION;
WAIT_FOR_ACTION:
if(!result_fifo_empty) nxt_st=READ_ACTION;
READ_ACTION:
nxt_st=READ_HEAD;
READ_HEAD:
if(out_rdy) nxt_st=READ_DATA;
READ_DATA:
if(in_fifo_ctrl==0 && out_rdy) nxt_st=WAIT_EOP;
WAIT_EOP:
if(in_fifo_ctrl!=0 && out_rdy) nxt_st=IDLE;
default:nxt_st=IDLE;
endcase
end
always@(*)
begin
result_fifo_rd_en=0;
in_fifo_rd_en=0;
if(cur_st==READ_ACTION)
result_fifo_rd_en=out_rdy;
else if(cur_st==READ_HEAD)
in_fifo_rd_en=out_rdy;
else if(cur_st==READ_DATA)
in_fifo_rd_en=out_rdy;
else if(cur_st==WAIT_EOP)
begin
if(in_fifo_ctrl!=0)
in_fifo_rd_en=0;
else in_fifo_rd_en=out_rdy;
end
end
always@(posedge clk)
if(reset)
src_port<=0;
else// if(cur_st==READ_HEAD)
if(in_fifo_ctrl==`IO_QUEUE_STAGE_NUM)
src_port<=in_fifo_data[`IOQ_SRC_PORT_POS + `OPENFLOW_ENTRY_SRC_PORT_WIDTH - 1 : `IOQ_SRC_PORT_POS] ;
always@(posedge clk)
if(reset)
actions<=0;
else if(cur_st==READ_DATA)
actions<= result_fifo_dout;
always@(posedge clk)
if(reset)
actions_en<=0;
else if(in_fifo_ctrl==`IO_QUEUE_STAGE_NUM)
begin
if(in_fifo_data[`IOQ_DST_TABLE_ID_POS+8-1:`IOQ_DST_TABLE_ID_POS]==CURRENT_TABLE_ID)
actions_en<=1;
else actions_en<=0;
end
else if(cur_st==IDLE)
actions_en<=0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7, A = 5e5 + 5; vector<vector<long long>> v; long long n, m, val; long long ans[A]; bool vis[A], vis2[A]; void DFS(long long node) { if (vis[node]) return; vis[node] = 1; for (auto child : v[node]) { if (vis[child]) continue; val++; DFS(child); } } void DFSmemo(long long node) { if (vis2[node]) return; vis2[node] = 1; for (auto child : v[node]) { if (vis2[child]) continue; ans[child] = val; DFSmemo(child); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; v.resize(n + 2); for (int i = 0; i < m; i++) { long long g, x, y; cin >> g; if (g != 0) cin >> x; for (int j = 1; j < g; j++) { cin >> y; v[x].push_back(y), v[y].push_back(x); } } for (int i = 1; i <= n; i++) { if (ans[i] == 0) { val = 1; DFS(i); DFSmemo(i); } else val = ans[i]; cout << val << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = (int)1e5 + 12; int a[maxn], n; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + n + 1); int cnt = 0; for (int i = 2; i < n; i++) { if (a[1] < a[i] && a[i] < a[n]) cnt++; } cout << cnt; } |
module no_clock_model(
input [7:0]in_8bit,
input [23:0]in_24bit,
input [63:0]in_64bit,
input [95:0]in_96bit,
input [7:0]in_mem_8bit[0:9],
input [63:0]in_mem_64bit[0:9],
input [77:0]in_mem_78bit[0:9],
output [23:0]out_24bit,
output [63:0]out_64bit,
output [95:0]out_96bit,
output reg [7:0]out_mem_8bit[0:9],
output reg [77:0]out_mem_78bit[0:9]
//InOut signals in module interface are not supported by vmodel
);
assign out_96bit = {in_64bit,in_24bit,in_8bit}+{32'b0,in_64bit};
assign out_64bit = ~in_64bit;
assign out_24bit = {in_8bit,in_8bit,in_8bit} - in_24bit;
wire hidden_var/*verilator public*/;
assign hidden_var=~in_8bit[0];
reg [1:0]hidden_mem[0:9] /*verilator public*/;
reg [7:0]hidden_mem_data;
reg [100:0]huge_hidden_mem[0:5] /*verilator public*/;
integer i;
always @(*)
begin
for (i=0; i<10; i=i+1)
begin
out_mem_8bit[i]=in_mem_8bit[i]+1;
out_mem_78bit[i]=in_mem_78bit[9-i];
hidden_mem_data=in_mem_8bit[i];
hidden_mem[i]=hidden_mem_data[1:0];
end
for (i=0; i<6; i=i+1)
begin
huge_hidden_mem[i]=0;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; template <class T> T abs(T x) { return x > 0 ? x : -x; } const int LEN = 300; const int MAX = (100000 + LEN - 1) / LEN; int n; int m; int was[100000], x[100000], y[100000]; int l[MAX], r[MAX], w[MAX]; vector<pair<pair<int, int>, int> > v; vector<int> res; int get(int a, int b) { int A = a / LEN; int B = b / LEN; if (abs(A - B) <= 1) { for (int i = a; i <= b; i++) if (!was[i]) return i; } else { for (int i = a; i <= r[A]; i++) if (!was[i]) return i; for (int i = A + 1; i < B; i++) if (w[i] > 0) { for (int j = l[i]; j <= r[i]; j++) if (!was[j]) return j; } for (int i = l[B]; i <= b; i++) if (!was[i]) return i; } return -1; } int add(int x) { was[x] = 1; int y = x / LEN; w[y]--; return 0; } int main() { scanf( %d%d , &n, &m); for (int i = 0; i < m; i++) { scanf( %d%d , &x[i], &y[i]); x[i]--; y[i]--; v.push_back(make_pair(make_pair(x[i], y[i]), i)); } int NUM = (n + LEN - 1) / LEN; for (int i = 0; i < NUM; i++) { l[i] = i * LEN; r[i] = min((i + 1) * LEN, n) - 1; w[i] = r[i] - l[i] + 1; } sort((v).begin(), (v).end()); for (int i = 0; i < m; i++) { int j = v[i].second; int a = n - y[j] - 1; int b = x[j]; int c = get(a, b); if (c != -1) { res.push_back(j + 1); add(c); } } sort((res).begin(), (res).end()); printf( %d n , ((int)(res).size())); for (int i = 0; i < ((int)(res).size()); i++) printf( %d , res[i]); printf( n ); return 0; } |
/* problem : CF1466I The Riddle of the Sphinx reference : https://www.luogu.com.cn/blog/CXY07/solution-cf1466i */ #include <bits/stdc++.h> #define mp std::make_pair #define pb push_back #define fi first #define se second #define gc getchar #define pc putchar #define ep emplace #define eb emplace_back #define ctz __builtin_ctz typedef unsigned char u8; typedef unsigned short u16; typedef unsigned int u32; typedef long long ll; typedef long double ld; typedef unsigned long long ull; typedef std::pair <int, int> pii; typedef std::pair <int, ll> pil; typedef std::pair <ll, int> pli; typedef std::pair <ll, ll> pll; const int max_N = 207; int n, b; std::string ans; int read() { char c = gc(); int ans = 0; bool flag = true; while (!isdigit(c)) flag &= (c != - ), c = gc(); while (isdigit(c)) ans = ans * 10 + c - 0 , c = gc(); return flag ? ans : -ans; } void Write(int x) { if (x < 0) pc( - ), x = -x; if (x < 10) pc(x + 0 ); else Write(x / 10), pc(x % 10 + 0 ); } int min(int x, int y) {return x < y ? x : y;} int max(int x, int y) {return x > y ? x : y;} void _min(int &x, int y) {if (x > y) x = y;} void _max(int &x, int y) {if (x < y) x = y;} namespace Interactive { bool compare(int x, std::string y) { std::cout << x << << y << std::endl; return std::cin >> y, y == yes ; } bool compare_less(int x, std::string y) { if (!std::count(y.begin(), y.end(), 1 )) return false; for (int pos = y.size() - 1; y[pos] == 0 ? (y[pos] = 1 , true) : (y[pos] = 0 , false); pos--); return y.insert(y.end(), b - y.size(), 1 ), !compare(x, y); } bool compare_greater(int x, std::string y) { if (!std::count(y.begin(), y.end(), 0 )) return false; return y.insert(y.end(), b - y.size(), 1 ), compare(x, y); } void report(std::string x) { std::cout << 0 << << x << std::endl; } } void solve(std::vector <int> vec, int w) { std::vector <int> stack; for (auto i : vec) { while (!stack.empty() && Interactive::compare_greater(i, (std::string) {ans.begin(), ans.begin() + w + stack.size()})) stack.pop_back(); if (w + stack.size() < b) ans[w + stack.size()] = !Interactive::compare_less(i, (std::string) {ans.begin(), ans.begin() + w + stack.size()} + 1 ) + 0 , stack.pb(i); } for (int i = stack.size() - 1; i >= 0; i--) if (Interactive::compare_greater(stack[i], (std::string) {ans.begin(), ans.begin() + w + stack.size()})) stack.resize(i + 1); if (w + stack.size() < b) solve(stack, w + stack.size()); } int main() { std::cin >> n >> b; std::vector <int> vec; vec.resize(n); std::iota(vec.begin(), vec.end(), 1); ans.resize(b); solve(vec, 0); return Interactive::report(ans), 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__NAND4_BEHAVIORAL_PP_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__nand4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , D, C, B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4_BEHAVIORAL_PP_V |
// MBT 7/24/2014
//
// bsg_sync_sync
//
// This is just two synchronization flops.
//
// We use the rp placement flop from synopsys.
// Fixme: move this into asic-specific components.
//
`include "bsg_defines.v"
`ifndef rp_group
`define rp_group(x)
`define rp_place(x)
`define rp_endgroup(x)
`define rp_fill(x)
`define rp_array_dir(up)
`endif
`define bsg_sync_sync_unit(width_p) \
\
module bsg_sync_sync_``width_p``_unit \
( \
input oclk_i \
, input [width_p-1:0] iclk_data_i \
, output [width_p-1:0] oclk_data_o // after sync flops \
); \
\
\
`rp_group (bss_bank) \
`rp_place (hier bss_1 0 0) \
`rp_place (hier bss_2 1 0) \
`rp_endgroup (bss_bank) \
\
logic [width_p-1:0] bsg_SYNC_1_r; \
logic [width_p-1:0] bsg_SYNC_2_r; \
\
assign oclk_data_o = bsg_SYNC_2_r; \
\
always_ff @(posedge oclk_i) \
begin \
`rp_group(bss_1) \
`rp_fill(0 0 UX) \
`rp_array_dir(up) \
`rp_endgroup(bss_1) \
bsg_SYNC_1_r <= iclk_data_i; \
end \
\
always_ff @(posedge oclk_i) \
begin \
`rp_group(bss_2) \
`rp_fill(0 0 UX) \
`rp_array_dir(up) \
`rp_endgroup(bss_2) \
bsg_SYNC_2_r <= bsg_SYNC_1_r; \
end \
\
endmodule
`bsg_sync_sync_unit(1)
`bsg_sync_sync_unit(2)
`bsg_sync_sync_unit(3)
`bsg_sync_sync_unit(4)
`bsg_sync_sync_unit(5)
`bsg_sync_sync_unit(6)
`bsg_sync_sync_unit(7)
`bsg_sync_sync_unit(8)
// warning: if you make this != 8, you need to modify other
// parts of this code.
`define bss_max_block 8
`define bss_if_clause(num) if ((width_p % `bss_max_block) == num) begin: z\
bsg_sync_sync_``num``_unit bss \
(.oclk_i \
,.iclk_data_i(iclk_data_i[width_p-1-:num]) \
,.oclk_data_o(oclk_data_o[width_p-1-:num]) \
); end
module bsg_sync_sync #(parameter `BSG_INV_PARAM(width_p ))
(
input oclk_i
, input [width_p-1:0] iclk_data_i
, output [width_p-1:0] oclk_data_o // after sync flops
);
genvar i;
// synopsys translate_off
/*
initial
begin
$display("%m: instantiating bss of size %d",width_p);
end
*/
// synopsys translate_on
for (i = 0; i < (width_p/`bss_max_block); i = i + 1)
begin : maxb
bsg_sync_sync_8_unit bss8
(.oclk_i
,.iclk_data_i(iclk_data_i[i*`bss_max_block+:`bss_max_block])
,.oclk_data_o(oclk_data_o[i*`bss_max_block+:`bss_max_block])
);
end
`bss_if_clause(1) else
`bss_if_clause(2) else
`bss_if_clause(3) else
`bss_if_clause(4) else
`bss_if_clause(5) else
`bss_if_clause(6) else
`bss_if_clause(7)
endmodule
`BSG_ABSTRACT_MODULE(bsg_sync_sync)
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
#include <bits/stdc++.h> #define int long long using namespace std; const int maxm=5e5+5; int stk[maxm],head; int d[maxm]; int a[maxm]; int n; // int rt[maxm],tot; int lc[maxm*40],rc[maxm*40],ma[maxm*40]; inline void pp(int k){ ma[k]=max(ma[lc[k]],ma[rc[k]]); } void update(int x,int val,int l,int r,int &k,int last){ k=++tot; lc[k]=lc[last]; rc[k]=rc[last]; if(l==r){ ma[k]=val; return ; } int mid=(l+r)/2; if(x<=mid)update(x,val,l,mid,lc[k],lc[last]); else update(x,val,mid+1,r,rc[k],rc[last]); pp(k); } int ask(int st,int ed,int l,int r,int k){ if(!k)return 0; if(st<=l&&ed>=r)return ma[k]; int mid=(l+r)/2; int ans=0; if(st<=mid)ans=max(ans,ask(st,ed,l,mid,lc[k])); if(ed>mid)ans=max(ans,ask(st,ed,mid+1,r,rc[k])); return ans; } // void solve(){ cin>>n; //init tot=0; ma[0]=0; // for(int i=1;i<=n;i++){ cin>>a[i]; } int ans=0; head=0; for(int i=1;i<=n;i++){ while(head&&a[stk[head]]<a[i]){ head--; } d[i]=1; d[i]=max(d[i],ask(1,a[i],1,n,rt[i-1])+1); if(head){ int k=stk[head]; d[i]=max(d[i],ask(1,a[i],1,n,rt[k-1])+2); } update(a[i],d[i],1,n,rt[i],rt[i-1]); stk[++head]=i; ans=max(ans,d[i]); } cout<<ans<<endl; } signed main(){ ios::sync_with_stdio(0); int T;cin>>T; while(T--){ solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = int(3002), mod = int(1e9) + 7; char second[N][N]; int n, m; long long dp1[N][N], dp2[N][N], a, b, c, d; bool used[N][N]; inline long long dp(int x, int y) { if (x <= 0 || y <= 0) return 0; if (second[x][y] == # ) return 0; if (x == 1 && y == 2) return 1; if (used[x][y]) return dp1[x][y]; used[x][y] = 1; return dp1[x][y] = (dp(x - 1, y) + dp(x, y - 1)) % mod; } inline long long rec(int x, int y) { if (x <= 0 || y <= 0) return 0; if (second[x][y] == # ) return 0; if (x == 2 && y == 1) return 1; if (used[x][y]) return dp2[x][y]; used[x][y] = 1; return dp2[x][y] = (rec(x - 1, y) + rec(x, y - 1)) % mod; } int main() { scanf( %d%d n , &n, &m); for (int i = 1; i <= n; i++) { scanf( %s n , second[i] + 1); } a = rec(n, m - 1), c = rec(n - 1, m); memset(used, 0, sizeof(used)); b = dp(n - 1, m), d = dp(n, m - 1); a = a * b % mod; c = c * d % mod; a = (a - c) % mod; if (a < 0) a += mod; printf( %d , a); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:05:24 03/30/2016
// Design Name:
// Module Name: Bloque_Top_pruebas
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Bloque_Top_pruebas
(
input clock_FPGA, reset,
input [1:0]sw,
output hsync, vsync,
output [7:0]RGB
);
wire [3:0] digit0_HH, digit1_HH, digit0_MM, digit1_MM, digit0_SS, digit1_SS,//
digit0_DAY, digit1_DAY, digit0_MES, digit1_MES, digit0_YEAR, digit1_YEAR,//
digit0_HH_T, digit1_HH_T, digit0_MM_T, digit1_MM_T, digit0_SS_T, digit1_SS_T;
wire AM_PM;
wire [1:0] funcion;
wire [1:0] cursor_location;
wire timer_end;//bandera proveniente del RTC que indica la finalización del tiempo del timer
wire formato_hora;//Señal que indica si la hora esta en formato 12 hrs o 24 hrs (0->24 hrs)
bloque_prueba_frames instancia_bloque_prueba_frames
(
.sw(sw),
.digit0_HH(digit0_HH), .digit1_HH(digit1_HH), .digit0_MM(digit0_MM), .digit1_MM(digit1_MM), .digit0_SS(digit0_SS), .digit1_SS(digit1_SS),//
.digit0_DAY(digit0_DAY), .digit1_DAY(digit1_DAY), .digit0_MES(digit0_MES), .digit1_MES(digit1_MES), .digit0_YEAR(digit0_YEAR), .digit1_YEAR(digit1_YEAR),//
.digit0_HH_T(digit0_HH_T), .digit1_HH_T(digit1_HH_T), .digit0_MM_T(digit0_MM_T), .digit1_MM_T(digit1_MM_T), .digit0_SS_T(digit0_SS_T), .digit1_SS_T(digit1_SS_T),//Decenas y unidades para los números en pantalla (18 inputs de 3 bits)
.AM_PM(AM_PM),//Entrada para conocer si en la información de hora se despliega AM o PM
.funcion(funcion),//2-bits: cuatro estados del modo configuración
.cursor_location(cursor_location),//Marca la posición del cursor en modo configuración
.timer_end(timer_end),//bandera proveniente del RTC que indica la finalización del tiempo del timer
.formato_hora(formato_hora)//Señal que indica si la hora esta en formato 12 hrs o 24 hrs (0->24 hrs)
);
controlador_VGA instancia_controlador_VGA
(
.clock(clock_FPGA), .reset(reset),
.digit0_HH(digit0_HH), .digit1_HH(digit1_HH), .digit0_MM(digit0_MM), .digit1_MM(digit1_MM), .digit0_SS(digit0_SS), .digit1_SS(digit1_SS),//
.digit0_DAY(digit0_DAY), .digit1_DAY(digit1_DAY), .digit0_MES(digit0_MES), .digit1_MES(digit1_MES), .digit0_YEAR(digit0_YEAR), .digit1_YEAR(digit1_YEAR),//
.digit0_HH_T(digit0_HH_T), .digit1_HH_T(digit1_HH_T), .digit0_MM_T(digit0_MM_T), .digit1_MM_T(digit1_MM_T), .digit0_SS_T(digit0_SS_T), .digit1_SS_T(digit1_SS_T),//Decenas y unidades para los números en pantalla (18 inputs de 3 bits)
.AM_PM(AM_PM),//Entrada para conocer si en la información de hora se despliega AM o PM
.config_mode(funcion),//1-bit: OR de los tres estados del modo configuración
.cursor_location(cursor_location),//Marca la posición del cursor en modo configuración
.formato_hora(formato_hora),//Señal que indica si la hora esta en formato 12 hrs o 24 hrs (0->24 hrs)
.estado_alarma(timer_end),//bandera proveniente del RTC que indica la finalización del tiempo del timer
.hsync(hsync),.vsync(vsync),
.RGB(RGB)
);
endmodule
|
module ARM_CU_ALU_TestBench5;
parameter sim_time = 2000*2; // Num of Cycles * 2
reg Reset , Clk , MEMSTORE,MEMLOAD;
wire [31:0] MEMDAT;
wire MFA,READ_WRITE,WORD_BYTE,MFC;
wire [7:0] MEMADD;
//module memory (inout reg[31:0] Data, output reg MFC, input MFA, ReadWrite, input [7:0] Address, input wordByte, Reset);
memory mem( MEMDAT, MFC, MFA, READ_WRITE, MEMADD, WORD_BYTE, Reset);
//module ARM_CU_ALU( input MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, output MEMADD, MFA,READ_WRITE,WORD_BYTE);
ARM_CU_ALU CPU( MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT,MEMADD, MFA,READ_WRITE,WORD_BYTE);
initial fork
Reset =1; Clk = 0; MEMSTORE=0;MEMLOAD=0;
#1 Reset = 0;
#(sim_time-1) Reset = 1; // print out memory before stopping simulation
join
always@(*) begin
$display("MEMADD = %d", MEMADD);
MEMSTORE=!READ_WRITE;
MEMLOAD=READ_WRITE;
end
always
#1 Clk = ~Clk;
initial #sim_time $finish;
initial begin
$dumpfile("ARM_CU_ALU_TestBench5.vcd");
$dumpvars(0,ARM_CU_ALU_TestBench5);
//$display(" Test Results" );
//$monitor("input MFC =%d, Reset =%d, Clk =%d, MEMSTORE=%d,MEMLOAD=%d,MEMDAT=%d, output MEMADD=%d, MFA=%d,READ_WRITE=%d,WORD_BYTE=%d,",MFC , Reset , Clk , MEMSTORE,MEMLOAD,MEMDAT, MEMADD, MFA,READ_WRITE,WORD_BYTE);
end
endmodule
//iverilog ARM_ALU.v ARM_CU_ALU.v BarrelShifter.v Buffer32_32.v controlunit6.v Decoder4x16.v Multiplexer2x1_32b.v Register.v Register2.v RegisterFile.v Register2Buff.v MEM_256B.v ARM_CU_ALU_TestBench5.v |
#include <bits/stdc++.h> int p[100005], q[100005], n, m, V; double a[100005], x[100005], y[100005], dx[100005], dy[100005], h, vx, vy, t, w; bool cmp1(const int i, const int j) { return a[i] < a[j]; } bool cmp2(const int i, const int j) { return x[i] < x[j]; } bool up(double t, double y) { return (h = vy * t - 9.8 * t * t / 2) > y; } int main() { scanf( %d%d , &n, &V); for (int i = 0; i < n; i++) scanf( %lf , &a[i]), q[i] = i; scanf( %d , &m); for (int i = 0; i < m; i++) scanf( %lf %lf , &x[i], &y[i]), p[i] = i; std::sort(q, q + n, cmp1); std::sort(p, p + m, cmp2); int j = 0; for (int k = 0; k < n; k++) { int i = q[k]; vx = V * cos(a[i]), vy = V * sin(a[i]), t = vy / 4.9, w = vx * t; while (j < m && x[p[j]] < w && up(x[p[j]] / vx, y[p[j]])) j++; if (j < m && x[p[j]] < w) dx[i] = x[p[j]], dy[i] = h; else dx[i] = w; } for (int i = 0; i < n; i++) printf( %lf %lf n , dx[i], dy[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; long long m; int k; vector<int> a; long long memo[66][2][66]; long long dp(int id, int tight, int cnt) { long long &res = memo[id][tight][cnt]; if (res == -1) { res = 0; if (id == a.size()) { if (cnt == k) res = 1; } else { for (int i = 0; i < 2; i++) { if (tight && i > a[id]) continue; int new_tight = tight ? i == a[id] : false; int new_cnt = cnt + (i == 1 ? 1 : 0); res += dp(id + 1, new_tight, new_cnt); } } } return res; } long long solve(long long n) { a.clear(); while (n) { a.push_back(n % 2); n /= 2; } a.push_back(0); reverse(a.begin(), a.end()); memset(memo, -1, sizeof(memo)); return dp(0, 1, 0); } long long possible(long long n) { return solve(2 * n) - solve(n); } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cin >> m >> k; long long lo = 1, hi = (long long)1e18 + 15; long long ans = -1; while (lo <= hi) { long long mid = (lo + hi) / 2; if (possible(mid) == m) { ans = mid; break; } if (possible(mid) < m) { lo = mid + 1; } else hi = mid - 1; } assert(ans != -1); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; double pi = 3.141592653589793238462; string numkey = 0123456789 ; string uni = abcdefghijklmnopqrstuvwxyz ; bool check(char ch) { string s = aeiou ; for (long long int i = 0; i < s.size(); i++) { if (s[i] == ch) return true; } return false; } signed main() { string s; cin >> s; long long int n = s.length(), ctr = 0; set<char> st; for (long long int i = 0; i < n; i++) { if (check(s[i]) == false) ctr++, st.insert(s[i]); else ctr = 0, st.clear(); if (ctr > 2 && st.size() > 1) { st.clear(); cout << ; st.insert(s[i]); ctr = 1; } cout << s[i]; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int i, j, l, n, k, d, max = 0, gen, e = 0; long long p; scanf( %d %d , &n, &k); vector<vector<int> > v(n); for (i = 0; i < n; i++) { scanf( %d , &d); v[d].push_back(i); if (d > max) max = d; } p = 1; for (i = 0; i <= max; i++) { gen = v[i].size(); if (i > 0) e += gen; if (gen > p || gen <= 0) break; p = gen; if (i == 0) p = k; else p = p * (k - 1); } if (i <= max) printf( -1 n ); else { printf( %d n , e); for (i = 0; i < max; i++) { gen = 0; if (i == 0) e = k; else e = k - 1; for (j = 0; j < (int)(v[i].size()); j++) { for (l = gen; l < gen + e && l < (int)(v[i + 1].size()); l++) { printf( %d %d n , v[i][j] + 1, v[i + 1][l] + 1); } gen += e; if (gen >= v[i + 1].size()) break; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1000 * 1000 * 1000 + 7; const int INF = 2000 * 1000 * 1000; const double EPS = 1e-9; const double pi = acos(-1.0); const int maxn = 1010; const int maxsum = 10010; template <typename T> inline T sqr(T n) { return (n * n); } int n, a[maxn], mem[maxn][2 * maxsum]; int* dp[maxn]; long long ans; int main() { scanf( %d , &n); dp[0] = mem[0] + maxsum; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); dp[i] = mem[i] + maxsum; } dp[0][0] = 1; ans = 0; for (int i = 1; i <= n; i++) { for (int sum = -10000; sum <= 10000; sum++) { if (sum + a[i] <= 10000) dp[i][sum] += dp[i - 1][sum + a[i]]; if (sum - a[i] >= -10000) dp[i][sum] += dp[i - 1][sum - a[i]]; dp[i][sum] %= MOD; } ans += dp[i][0]; ans %= MOD; dp[i][0]++; } printf( %I64d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long double add[3 * 100 * 1000]; const long double inf = 1e18; long double max(long double a, long double b, long double c, long double d) { return max(max(a, b), max(c, d)); } struct rmq { int l, r; long double pref, suf, all, best; rmq *left, *right; }; rmq *build(int l, int r) { rmq *root = (rmq *)malloc(sizeof(rmq)); root->l = l; root->r = r; if (l == r) { root->left = root->right = NULL; root->suf = max((long double)0, add[l]); root->pref = root->suf; root->all = add[l]; root->best = root->suf; } else { root->left = build(l, (l + r) / 2); root->right = build((l + r) / 2 + 1, r); root->all = root->left->all + root->right->all; root->pref = max(root->left->pref, root->left->all + root->right->pref); root->suf = max(root->right->suf, root->left->suf + root->right->all); root->best = max(root->left->best, root->right->best, root->left->suf + root->right->pref, root->all); } return root; } void get(int l, int r, rmq *root, long double &pref, long double &suf, long double &all, long double &best) { if (root->l == l && root->r == r) { pref = root->pref; suf = root->suf; all = root->all; best = root->best; return; } long double prefL = -inf, prefR = -inf, sufL = -inf, sufR = -inf, allL = -inf, allR = -inf, bestL = -inf, bestR = -inf; if (root->left && root->left->r >= l) get(l, min(r, root->left->r), root->left, prefL, sufL, allL, bestL); if (root->right && root->right->l <= r) get(max(root->right->l, l), r, root->right, prefR, sufR, allR, bestR); pref = max(prefL, allL + prefR); suf = max(sufR, allR + sufL); all = allL + allR; best = max(bestL, bestR, prefR + sufL, all); } int main() { cout.setf(ios::fixed); cout.precision(10); int n, m, c; cin >> n >> m >> c; long long x[n]; for (int i = 0; i < n; ++i) cin >> x[i]; long double p[n]; for (int i = 1; i < n; ++i) { cin >> p[i]; p[i] /= 100.0; } add[0] = 0; for (int i = 1; i < n; ++i) add[i] = 0.5 * (x[i] - x[i - 1]) - c * p[i]; rmq *root = build(0, n - 1); long double res = 0; long double best, all, suf, pref; for (int i = 0; i < m; ++i) { int a, b; cin >> a >> b; --b; get(a, b, root, pref, suf, all, best); res += best; } cout << res; cin >> n; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Base Mixed Mode Clock Manager (MMCM)
// /___/ /\ Filename : MMCME2_BASE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/27/10 - Initial version
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MMCME2_BASE (
CLKFBOUT,
CLKFBOUTB,
CLKOUT0,
CLKOUT0B,
CLKOUT1,
CLKOUT1B,
CLKOUT2,
CLKOUT2B,
CLKOUT3,
CLKOUT3B,
CLKOUT4,
CLKOUT5,
CLKOUT6,
LOCKED,
CLKFBIN,
CLKIN1,
PWRDWN,
RST
);
parameter BANDWIDTH = "OPTIMIZED";
parameter real CLKFBOUT_MULT_F = 5.000;
parameter real CLKFBOUT_PHASE = 0.000;
parameter real CLKIN1_PERIOD = 0.000;
parameter real CLKOUT0_DIVIDE_F = 1.000;
parameter real CLKOUT0_DUTY_CYCLE = 0.500;
parameter real CLKOUT0_PHASE = 0.000;
parameter integer CLKOUT1_DIVIDE = 1;
parameter real CLKOUT1_DUTY_CYCLE = 0.500;
parameter real CLKOUT1_PHASE = 0.000;
parameter integer CLKOUT2_DIVIDE = 1;
parameter real CLKOUT2_DUTY_CYCLE = 0.500;
parameter real CLKOUT2_PHASE = 0.000;
parameter integer CLKOUT3_DIVIDE = 1;
parameter real CLKOUT3_DUTY_CYCLE = 0.500;
parameter real CLKOUT3_PHASE = 0.000;
parameter CLKOUT4_CASCADE = "FALSE";
parameter integer CLKOUT4_DIVIDE = 1;
parameter real CLKOUT4_DUTY_CYCLE = 0.500;
parameter real CLKOUT4_PHASE = 0.000;
parameter integer CLKOUT5_DIVIDE = 1;
parameter real CLKOUT5_DUTY_CYCLE = 0.500;
parameter real CLKOUT5_PHASE = 0.000;
parameter integer CLKOUT6_DIVIDE = 1;
parameter real CLKOUT6_DUTY_CYCLE = 0.500;
parameter real CLKOUT6_PHASE = 0.000;
parameter integer DIVCLK_DIVIDE = 1;
parameter real REF_JITTER1 = 0.010;
parameter STARTUP_WAIT = "FALSE";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output CLKFBOUT;
output CLKFBOUTB;
output CLKOUT0;
output CLKOUT0B;
output CLKOUT1;
output CLKOUT1B;
output CLKOUT2;
output CLKOUT2B;
output CLKOUT3;
output CLKOUT3B;
output CLKOUT4;
output CLKOUT5;
output CLKOUT6;
output LOCKED;
input CLKFBIN;
input CLKIN1;
input PWRDWN;
input RST;
// define constants
localparam MODULE_NAME = "MMCME2_BASE";
wire OPEN_DRDY;
wire OPEN_PSDONE;
wire OPEN_FBS;
wire OPEN_INS;
wire [15:0] OPEN_DO;
MMCME2_ADV #(
.BANDWIDTH(BANDWIDTH),
.CLKFBOUT_MULT_F(CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(10),
.CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_CASCADE(CLKOUT4_CASCADE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE),
.CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE),
.CLKOUT6_PHASE(CLKOUT6_PHASE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.REF_JITTER1(REF_JITTER1),
.STARTUP_WAIT(STARTUP_WAIT)
) mmcm_adv_1 (
.CLKFBOUT (CLKFBOUT),
.CLKFBOUTB (CLKFBOUTB),
.CLKFBSTOPPED(OPEN_FBS),
.CLKINSTOPPED(OPEN_INS),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUT2 (CLKOUT2),
.CLKOUT2B (CLKOUT2B),
.CLKOUT3 (CLKOUT3),
.CLKOUT3B (CLKOUT3B),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.CLKOUT6 (CLKOUT6),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.LOCKED (LOCKED),
.PSDONE(OPEN_PSDONE),
.CLKFBIN (CLKFBIN),
.CLKIN1 (CLKIN1),
.CLKIN2 (1'b0),
.CLKINSEL(1'b1),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(PWRDWN),
.RST (RST)
);
endmodule
`endcelldefine
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:28:58 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_gpio_1_0_stub.v
// Design : zqynq_lab_1_design_axi_gpio_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, ip2intc_irpt, gpio_io_i)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[4:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output ip2intc_irpt;
input [4:0]gpio_io_i;
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for udp_ip_rx_64
*/
module test_udp_ip_rx_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_ip_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [3:0] s_ip_version = 0;
reg [3:0] s_ip_ihl = 0;
reg [5:0] s_ip_dscp = 0;
reg [1:0] s_ip_ecn = 0;
reg [15:0] s_ip_length = 0;
reg [15:0] s_ip_identification = 0;
reg [2:0] s_ip_flags = 0;
reg [12:0] s_ip_fragment_offset = 0;
reg [7:0] s_ip_ttl = 0;
reg [7:0] s_ip_protocol = 0;
reg [15:0] s_ip_header_checksum = 0;
reg [31:0] s_ip_source_ip = 0;
reg [31:0] s_ip_dest_ip = 0;
reg [63:0] s_ip_payload_axis_tdata = 0;
reg [7:0] s_ip_payload_axis_tkeep = 0;
reg s_ip_payload_axis_tvalid = 0;
reg s_ip_payload_axis_tlast = 0;
reg s_ip_payload_axis_tuser = 0;
reg m_udp_hdr_ready = 0;
reg m_udp_payload_axis_tready = 0;
// Outputs
wire s_ip_hdr_ready;
wire s_ip_payload_axis_tready;
wire m_udp_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [3:0] m_ip_version;
wire [3:0] m_ip_ihl;
wire [5:0] m_ip_dscp;
wire [1:0] m_ip_ecn;
wire [15:0] m_ip_length;
wire [15:0] m_ip_identification;
wire [2:0] m_ip_flags;
wire [12:0] m_ip_fragment_offset;
wire [7:0] m_ip_ttl;
wire [7:0] m_ip_protocol;
wire [15:0] m_ip_header_checksum;
wire [31:0] m_ip_source_ip;
wire [31:0] m_ip_dest_ip;
wire [15:0] m_udp_source_port;
wire [15:0] m_udp_dest_port;
wire [15:0] m_udp_length;
wire [15:0] m_udp_checksum;
wire [63:0] m_udp_payload_axis_tdata;
wire [7:0] m_udp_payload_axis_tkeep;
wire m_udp_payload_axis_tvalid;
wire m_udp_payload_axis_tlast;
wire m_udp_payload_axis_tuser;
wire busy;
wire error_header_early_termination;
wire error_payload_early_termination;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_ip_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_ip_version,
s_ip_ihl,
s_ip_dscp,
s_ip_ecn,
s_ip_length,
s_ip_identification,
s_ip_flags,
s_ip_fragment_offset,
s_ip_ttl,
s_ip_protocol,
s_ip_header_checksum,
s_ip_source_ip,
s_ip_dest_ip,
s_ip_payload_axis_tdata,
s_ip_payload_axis_tkeep,
s_ip_payload_axis_tvalid,
s_ip_payload_axis_tlast,
s_ip_payload_axis_tuser,
m_udp_hdr_ready,
m_udp_payload_axis_tready
);
$to_myhdl(
s_ip_hdr_ready,
s_ip_payload_axis_tready,
m_udp_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_ip_version,
m_ip_ihl,
m_ip_dscp,
m_ip_ecn,
m_ip_length,
m_ip_identification,
m_ip_flags,
m_ip_fragment_offset,
m_ip_ttl,
m_ip_protocol,
m_ip_header_checksum,
m_ip_source_ip,
m_ip_dest_ip,
m_udp_source_port,
m_udp_dest_port,
m_udp_length,
m_udp_checksum,
m_udp_payload_axis_tdata,
m_udp_payload_axis_tkeep,
m_udp_payload_axis_tvalid,
m_udp_payload_axis_tlast,
m_udp_payload_axis_tuser,
busy,
error_header_early_termination,
error_payload_early_termination
);
// dump file
$dumpfile("test_udp_ip_rx_64.lxt");
$dumpvars(0, test_udp_ip_rx_64);
end
udp_ip_rx_64
UUT (
.clk(clk),
.rst(rst),
// IP frame input
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_ip_version(s_ip_version),
.s_ip_ihl(s_ip_ihl),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_identification(s_ip_identification),
.s_ip_flags(s_ip_flags),
.s_ip_fragment_offset(s_ip_fragment_offset),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_header_checksum(s_ip_header_checksum),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(s_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(m_udp_hdr_valid),
.m_udp_hdr_ready(m_udp_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_ip_version(m_ip_version),
.m_ip_ihl(m_ip_ihl),
.m_ip_dscp(m_ip_dscp),
.m_ip_ecn(m_ip_ecn),
.m_ip_length(m_ip_length),
.m_ip_identification(m_ip_identification),
.m_ip_flags(m_ip_flags),
.m_ip_fragment_offset(m_ip_fragment_offset),
.m_ip_ttl(m_ip_ttl),
.m_ip_protocol(m_ip_protocol),
.m_ip_header_checksum(m_ip_header_checksum),
.m_ip_source_ip(m_ip_source_ip),
.m_ip_dest_ip(m_ip_dest_ip),
.m_udp_source_port(m_udp_source_port),
.m_udp_dest_port(m_udp_dest_port),
.m_udp_length(m_udp_length),
.m_udp_checksum(m_udp_checksum),
.m_udp_payload_axis_tdata(m_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(m_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(m_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(m_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(m_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(m_udp_payload_axis_tuser),
// Status signals
.busy(busy),
.error_header_early_termination(error_header_early_termination),
.error_payload_early_termination(error_payload_early_termination)
);
endmodule
|
#include <bits/stdc++.h> const long long M = 1000005; const long long mod = 1e9 + 7; using namespace std; long long n, m, a, b, fac[M], Ans; inline long long Fpw(long long Base, long long k) { long long temp = 1; while (k) { if (k & 1) temp = (1LL * temp * Base) % mod; Base = (1LL * Base * Base) % mod; k >>= 1; } return temp; } inline long long Inv(long long a) { return Fpw(a, mod - 2); } inline long long C(long long n, long long m) { if (n < 0 || m < 0 || n < m) return 0; return fac[n] * Inv(fac[m]) % mod * Inv(fac[n - m]) % mod; } int main() { scanf( %lld%lld , &n, &m); fac[0] = 1; for (long long i = 1; i <= 1000000; i++) fac[i] = (1LL * fac[i - 1] * i) % mod; for (long long i = 2; i <= n; i++) { long long temp = C(n - 2, i - 2) * fac[i - 2] % mod; temp = temp * C(m - 1, i - 2) % mod; if (n - i - 1 >= 0) temp = temp * i % mod * Fpw(n, n - i - 1) % mod; temp = temp * Fpw(m, n - i) % mod; Ans = (Ans + temp) % mod; } printf( %lld n , Ans); return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const ll inf = INT_MAX - 1; bool check(ll r, ll g, ll b, ll w, ll total) { if (r < 0 || g < 0 || b < 0 || w < 0) { return false; } ll numberIsOne = 0; if (r & 1) { numberIsOne++; } if (g & 1) { numberIsOne++; } if (b & 1) { numberIsOne++; } if (w & 1) { numberIsOne++; } if (numberIsOne == 0 && total % 2 == 0) { return true; } if (total % 2 == 1 && numberIsOne == 1) { return true; } } void solve() { ll r, g, b, w; cin >> r >> g >> b >> w; ll total = r + g + b + w; ll minNum = min(r, min(g, b)); if (check(r, g, b, w, total)) { cout << Yes n ; return; } if (check(r - 1, g - 1, b - 1, w + 3, total)) { cout << Yes n ; return; } if (check(r - 2, g - 2, b - 2, w + 6, total)) { cout << Yes n ; return; } if (check(r - minNum, g - minNum, b - minNum, w + minNum * 3, total)) { cout << Yes n ; return; } cout << No n ; } int main() { ios_base::sync_with_stdio(false); ll t; cin >> t; while (t--) { solve(); } } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 23:00:32 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_gpio_0_1_stub.v
// Design : zqynq_lab_1_design_axi_gpio_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_gpio,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready,
s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, gpio_io_o)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,gpio_io_o[7:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [8:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [8:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
output [7:0]gpio_io_o;
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file gsu_cache.v when simulating
// the core, gsu_cache. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module gsu_cache(
clka,
wea,
addra,
dina,
douta
);
input clka;
input [0 : 0] wea;
input [8 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(9),
.C_ADDRB_WIDTH(9),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(512),
.C_READ_DEPTH_B(512),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(512),
.C_WRITE_DEPTH_B(512),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; while (scanf( %d , &n) != EOF) { int a[n][n]; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { scanf( %d , &a[i][j]); } } if (n == 1) { printf( %d n , a[0][0]); break; } int sum = 0; for (int i = 1; i < n - 1; i++) { for (int j = 1; j < n - 1; j++) { sum += a[i][j]; } } sum += a[0][0] + a[0][n - 1] + a[n - 1][n - 1] + a[n - 1][0]; sum += a[0][(n - 1) / 2] + a[n - 1][(n - 1) / 2] + a[(n - 1) / 2][0] + a[(n - 1) / 2][n - 1]; printf( %d n , sum); } } |
#include <bits/stdc++.h> using namespace std; int const N = 1e5 + 13; int const INF = 1e9 + 13; int n, m; set<int> p[N]; int l[N], r[N]; int pos[N], x[N]; int tsz; int a[N]; int type[N]; vector<int> t[N * 4], tright[N * 4]; vector<long long> F[N * 4]; vector<int> qid; vector<pair<int, int>> qpos[N]; vector<int> lposes; bool cmpl(int i, int j) { return l[i] < l[j]; } void merge(vector<int> &v, vector<int> &l, vector<int> &r) { int lp = 0; int rp = 0; int ln = l.size(); int rn = r.size(); while (lp < ln || rp < rn) { if (rp == rn || (lp < ln && ::r[l[lp]] < ::r[r[rp]])) { v.push_back(l[lp++]); } else { v.push_back(r[rp++]); } } } void build(int v, int tl, int tr) { if (tl == tr) { t[v].push_back(qid[tl]); F[v].assign(1, 0LL); for (int i = 0; i < t[v].size(); ++i) { qpos[t[v][i]].push_back(make_pair(v, i)); } tright[v].push_back(r[qid[tl]]); } else { int tm = (tl + tr) / 2; build(v * 2 + 1, tl, tm); build(v * 2 + 2, tm + 1, tr); merge(t[v], t[v * 2 + 1], t[v * 2 + 2]); for (int i = 0; i < t[v].size(); ++i) { qpos[t[v][i]].push_back(make_pair(v, i)); tright[v].push_back(r[t[v][i]]); } F[v].assign(t[v].size(), 0LL); } } void updF(vector<long long> &F, int x, int v) { int n = F.size(); while (x < n) { F[x] += v; x |= (x + 1); } } long long getF(vector<long long> &F, int x) { long long res = 0; while (x >= 0) { res += F[x]; x = (x & (x + 1)) - 1; } return res; } void upd(vector<long long> &F, int l, int r, int val) { if (l > r) return; updF(F, l, val); updF(F, r + 1, -val); } int getLeft(vector<int> &v, int val) { int l = -1; int r = v.size(); while (r - l > 1) { int m = (l + r) / 2; if (v[m] >= val) r = m; else l = m; } return r; } int getRight(vector<int> &v, int val) { int l = -1; int r = v.size(); while (r - l > 1) { int m = (l + r) / 2; if (v[m] <= val) l = m; else r = m; } return l; } void upd(int v, int tl, int tr, int ll, int lr, int rl, int rr, int val) { if (tl > lr || ll > tr) return; if (ll <= tl && tr <= lr) { int left = getLeft(tright[v], rl); int right = getRight(tright[v], rr); upd(F[v], left, right, val); return; } int tm = (tl + tr) / 2; upd(v * 2 + 1, tl, tm, ll, lr, rl, rr, val); upd(v * 2 + 2, tm + 1, tr, ll, lr, rl, rr, val); } long long answer(int id) { long long res = 0; for (int i = 0; i < qpos[id].size(); ++i) { res += getF(F[qpos[id][i].first], qpos[id][i].second); } return res; } void push(int pos, int val) { set<int>::iterator bef, aft; bef = p[val].lower_bound(pos); aft = p[val].upper_bound(pos); if (bef != p[val].begin()) { --bef; int lp = (*bef); int dist = pos - lp; lp = getRight(lposes, lp); int rp = (aft == p[val].end() ? INF : (*aft) - 1); upd(0, 0, tsz - 1, 0, lp, pos, rp, dist); } bef = p[val].lower_bound(pos); aft = p[val].upper_bound(pos); if (aft != p[val].end()) { int lp; if (bef != p[val].begin()) { --bef; lp = (*bef) + 1; } else { lp = 0; } lp = getLeft(lposes, lp); int rp = getRight(lposes, pos); int rpp = (*aft); int dist = rpp - pos; upd(0, 0, tsz - 1, lp, rp, rpp, INF, dist); } p[val].insert(pos); } void pop(int pos, int val) { p[val].erase(pos); set<int>::iterator bef, aft; bef = p[val].lower_bound(pos); aft = p[val].upper_bound(pos); if (bef != p[val].begin()) { --bef; int lp = (*bef); int dist = pos - lp; lp = getRight(lposes, lp); int rp = (aft == p[val].end() ? INF : (*aft) - 1); upd(0, 0, tsz - 1, 0, lp, pos, rp, -dist); } bef = p[val].lower_bound(pos); aft = p[val].upper_bound(pos); if (aft != p[val].end()) { int lp; if (bef != p[val].begin()) { --bef; lp = (*bef) + 1; } else { lp = 0; } lp = getLeft(lposes, lp); int rp = getRight(lposes, pos); int rpp = (*aft); int dist = rpp - pos; upd(0, 0, tsz - 1, lp, rp, rpp, INF, -dist); } } void solve() { cin >> n >> m; for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < m; ++i) { cin >> type[i]; if (type[i] == 1) { cin >> pos[i] >> x[i]; --pos[i]; } else { cin >> l[i] >> r[i]; --l[i]; --r[i]; qid.push_back(i); } } tsz = qid.size(); if (tsz == 0) return; sort(qid.begin(), qid.end(), cmpl); for (int i = 0; i < qid.size(); ++i) lposes.push_back(l[qid[i]]); build(0, 0, tsz - 1); for (int i = 0; i < n; ++i) push(i, a[i]); for (int i = 0; i < m; ++i) { if (type[i] == 1) { pop(pos[i], a[pos[i]]); a[pos[i]] = x[i]; push(pos[i], a[pos[i]]); } else { long long ans = answer(i); cout << ans << endl; } } } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 132700; int n; tuple<int, int, int, int> esq[N], dir[N]; vector<tuple<int, int, int, int>> v; int main(void) { ios_base::sync_with_stdio(false); cin >> n; for (int i = 0; i < n; i++) { int a, b, c, d; cin >> a >> b >> c >> d; v.emplace_back(a, b, c, d); } esq[0] = make_tuple(-0x3f3f3f3f, -0x3f3f3f3f, +0x3f3f3f3f, +0x3f3f3f3f); for (int i = 1; i <= n; i++) { int xb, yb, xu, yu; tie(xb, yb, xu, yu) = v[i - 1]; get<0>(esq[i]) = max(get<0>(esq[i - 1]), xb); get<1>(esq[i]) = max(get<1>(esq[i - 1]), yb); get<2>(esq[i]) = min(get<2>(esq[i - 1]), xu); get<3>(esq[i]) = min(get<3>(esq[i - 1]), yu); } dir[n + 1] = make_tuple(-0x3f3f3f3f, -0x3f3f3f3f, +0x3f3f3f3f, +0x3f3f3f3f); for (int i = n; i >= 1; i--) { int xb, yb, xu, yu; tie(xb, yb, xu, yu) = v[i - 1]; get<0>(dir[i]) = max(get<0>(dir[i + 1]), xb); get<1>(dir[i]) = max(get<1>(dir[i + 1]), yb); get<2>(dir[i]) = min(get<2>(dir[i + 1]), xu); get<3>(dir[i]) = min(get<3>(dir[i + 1]), yu); } for (int i = 1; i <= n; i++) { int xb, yb, xu, yu; xb = max(get<0>(esq[i - 1]), get<0>(dir[i + 1])); yb = max(get<1>(esq[i - 1]), get<1>(dir[i + 1])); xu = min(get<2>(esq[i - 1]), get<2>(dir[i + 1])); yu = min(get<3>(esq[i - 1]), get<3>(dir[i + 1])); if (xb <= xu and yb <= yu) { cout << xb << << yb << endl; return 0; } } assert(0); return 0; } |
#include <bits/stdc++.h> const double PI = acos(-1.0); using namespace std; int t[100010]; void update(int x, int v) { for (; x < 100010; x += (x & -x)) t[x] += v; } int sum(int r) { int ans = 0; for (; r > 0; r -= (r & -r)) ans += t[r]; return ans; } int sum(int l, int r) { if (l > r) swap(l, r); return sum(r) - sum(l - 1); } int main() { int n, q; scanf( %d %d , &n, &q); for (int i = 1; i <= n; ++i) update(i, 1); int ll = 0, rr = n, dir = 1; while (q--) { int type; scanf( %d , &type); if (type == 1) { int p; scanf( %d , &p); if (2 * p <= abs(ll - rr)) { for (int j = 1; j <= p; ++j) { int w = sum(ll + j * dir, ll + j * dir); update(ll + j * dir, -w); update(ll + (2 * p - j + 1) * dir, w); } ll += p * dir; } else { for (int j = abs(ll - rr); j > p; --j) { int w = sum(ll + j * dir, ll + j * dir); update(ll + j * dir, -w); update(ll + (2 * p - j + 1) * dir, w); } ll += (p + 1) * dir; rr = ll - p * dir; dir *= -1; } } else { int l, r; scanf( %d %d , &l, &r); printf( %d n , sum(ll + (l + 1) * dir, ll + r * dir)); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, p[3000], k, m = 0, c; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> p[i]; for (int i = 1; i <= n; i++) { k = p[i]; c = 1; while (k > 0) { c++; k = p[k]; } m = max(c, m); } cout << m; return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, stack:200000000 ) #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; long long freq[3000005], mul[3000005], n, q, x; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = n; i--; ++freq[x]) cin >> x; for (int i = 1; i < 3000005; ++i) if (freq[i]) for (int j = i; j < 3000005; j += i) mul[j] += freq[i] * (freq[j / i] - (i == j / i)); for (int i = 1; i < 3000005; ++i) mul[i] += mul[i - 1]; for (cin >> q; q--; cout << n * (n - 1) - mul[x - 1] << n ) cin >> x; } |
module main(
// clocks
input fclk,
output clkz_out,
input clkz_in,
// z80
input iorq_n,
input mreq_n,
input rd_n,
input wr_n,
input m1_n,
input rfsh_n,
input int_n,
input nmi_n,
input wait_n,
output res,
inout [7:0] d,
output [15:0] a,
// zxbus and related
output csrom,
output romoe_n,
output romwe_n,
output rompg0_n,
output dos_n, // aka rompg1
output rompg2,
output rompg3,
output rompg4,
input iorqge1,
input iorqge2,
output iorq1_n,
output iorq2_n,
// DRAM
input [15:0] rd,
input [9:0] ra,
output rwe_n,
output rucas_n,
output rlcas_n,
output rras0_n,
output rras1_n,
// video
output reg [1:0] vred,
output reg [1:0] vgrn,
output reg [1:0] vblu,
output vhsync,
output vvsync,
output vcsync,
// AY control and audio/tape
input ay_clk,
output ay_bdir,
output ay_bc1,
output beep,
// IDE
input [2:0] ide_a,
input [15:0] ide_d,
output ide_dir,
input ide_rdy,
output ide_cs0_n,
output ide_cs1_n,
output ide_rs_n,
output ide_rd_n,
output ide_wr_n,
// VG93 and diskdrive
input vg_clk,
output vg_cs_n,
output vg_res_n,
input vg_hrdy,
input vg_rclk,
input vg_rawr,
input [1:0] vg_a, // disk drive selection
input vg_wrd,
input vg_side,
input step,
input vg_sl,
input vg_sr,
input vg_tr43,
input rdat_b_n,
input vg_wf_de,
input vg_drq,
input vg_irq,
input vg_wd,
// serial links (atmega-fpga, sdcard)
output sdcs_n,
output sddo,
output sdclk,
input sddi,
input spics_n,
input spick,
input spido,
output spidi,
input spiint_n
);
//--Dummy----------------------------------------------------------------------
assign iorq1_n = 1'b1;
assign iorq2_n = 1'b1;
assign res= 1'b1;
assign rwe_n = 1'b1;
assign rucas_n = 1'b1;
assign rlcas_n = 1'b1;
assign rras0_n = 1'b1;
assign rras1_n = 1'b1;
assign ay_bdir = 1'b0;
assign ay_bc1 = 1'b0;
assign vg_cs_n = 1'b1;
assign vg_res_n = 1'b0;
assign ide_dir=1'b1;
assign ide_rs_n = 1'b0;
assign ide_cs0_n = 1'b1;
assign ide_cs1_n = 1'b1;
assign ide_rd_n = 1'b1;
assign ide_wr_n = 1'b1;
assign a[15:14] = 2'b00;
//-----------------------------------------------------------------------------
reg [2:0] main_osc;
always @(posedge fclk)
main_osc <= main_osc + 3'h1;
assign clkz_out = main_osc[2]; // 3.5 MHz
assign beep = spiint_n;
//--Video----------------------------------------------------------------------
localparam HBLNK_BEG = 9'd384;
localparam CSYNC_CUT = 9'd415;
//localparam CSYNC_CUT2 = 9'd382;
localparam HSYNC_BEG = 9'd0;
localparam HSYNC_END = 9'd33;
localparam HSYNC_END2 = 9'd53;
localparam HBLNK_END = 9'd128;
localparam HMAX = 9'd447;
localparam VBLNK_BEG = 10'd512; // 256
localparam VSYNC_BEG = 10'd0; // 0
localparam VSYNC_END = 10'd4; // 2
localparam VBLNK_END = 10'd128; // 64
localparam VMAX = 10'd623; // 311
reg [8:0] hcount;
reg [9:0] vcount;
reg [5:0] hcharcount;
reg [2:0] vcharline;
reg [6:0] voffset;
reg hsync, hblank, vsync, vblank, csync;
wire [9:0] video_addr;
wire [6:0] charcode;
wire [7:0] charpix;
wire pixel;
wire [5:0] fcolor;
wire [5:0] bcolor;
wire [5:0] color;
always @(posedge fclk)
begin
//
if ( {(main_osc[1]&scr_tv_mode),main_osc[0]}==2'h0 )
begin
if ( hcount[2:0]==3'h0 )
begin
if ( hblank )
hcharcount <= 6'h00;
else
hcharcount <= hcharcount + 6'h01;
end
if ( hcount==HMAX )
hcount <= 9'd0;
else
hcount <= hcount + 9'd1;
if ( hcount==HBLNK_BEG )
hblank <= 1'b1;
else if ( hcount==HBLNK_END )
hblank <= 1'b0;
if ( hcount==HSYNC_BEG )
begin
hsync <= 1'b1;
if ( vc0 )
csync <= 1'b1;
end
if ( (~scr_tv_mode) && (hcount==HSYNC_END2) )
begin
hsync <= 1'b0;
if ( !vsync )
csync <= 1'b0;
end
if ( scr_tv_mode && (hcount==HSYNC_END) )
begin
hsync <= 1'b0;
if ( !vsync )
csync <= 1'b0;
end
if ( (~vc0) && (hcount==HBLNK_BEG) ) // localparam CSYNC_CUT2 = 9'd382;
csync <= 1'b0;
if ( scr_tv_mode && (hcount==CSYNC_CUT) )
csync <= 1'b0;
vgrn[1] <= color[5];
vgrn[0] <= color[4];
vred[1] <= color[3];
vred[0] <= color[2];
vblu[1] <= color[1];
vblu[0] <= color[0];
end
//
if ( (main_osc[1:0]==2'h3) && (hcount==HSYNC_BEG) )
begin
if ( vblank )
begin
voffset <= 7'd0;
vcharline <= 3'h0;
end
else
begin
if ( (vcharline==3'h7) && vc0 )
voffset <= voffset + 7'd4; // 32 / 8 = 4
vcharline <= vcharline + {2'b00,vc0};
end
if ( {vcount[9:1],vc0}==VMAX )
vcount <= 10'd0;
else
vcount <= {vcount[9:1],vc0} + 10'd1;
if ( vcount==VBLNK_BEG )
vblank <= 1'b1;
else if ( vcount==VBLNK_END )
vblank <= 1'b0;
if ( vcount==VSYNC_BEG )
vsync <= 1'b1;
else if ( vcount==VSYNC_END )
vsync <= 1'b0;
end
//
end
assign vc0 = vcount[0] | scr_tv_mode;
assign video_addr = { voffset[6:0], 3'h0 } + { 4'h0, hcharcount[5:0] };
lpm_ram_dp0 scr_mem ( .data(scr_char), .rdaddress(video_addr), .wraddress(scr_addr), .wren(scr_wren_c), .q(charcode) );
lpm_rom0 chargen ( .address({ charcode, vcharline[2:0] }), .q(charpix) );
assign fcolor = 6'b111111;
assign bcolor = 6'b000001;
assign pixel = charpix[~(hcount[2:0]-3'h1)];
assign color = (hblank | vblank) ? 6'h00 : ( pixel ? fcolor : bcolor ) ;
assign vhsync = hsync;
assign vvsync = vsync;
assign vcsync = ~csync;
//--AVRSPI--FlashROM-----------------------------------------------------------
localparam SD_CS0 = 8'h57;
localparam SD_CS1 = 8'h5f;
localparam FLASH_LOADDR = 8'hf0;
localparam FLASH_MIDADDR = 8'hf1;
localparam FLASH_HIADDR = 8'hf2;
localparam FLASH_DATA = 8'hf3;
localparam FLASH_CTRL = 8'hf4;
localparam SCR_LOADDR = 8'h40;
localparam SCR_HIADDR = 8'h41;
localparam SCR_CHAR = 8'h44;
localparam SCR_MODE = 8'h4e;
reg [7:0] number;
reg [7:0] indata;
reg [7:0] outdata;
reg [2:0] bitptr;
reg [1:0] spick_resync;
reg [1:0] spicsn_resync;
reg [18:0] flash_addr;
reg flash_cs;
reg flash_oe;
reg flash_we;
reg [7:0] flash_data_out;
reg [9:0] scr_addr;
reg [6:0] scr_char;
reg scr_wren_c;
reg scr_tv_mode;
wire spicsn_rising;
wire spicsn_falling;
wire sd_selected;
always @(posedge spick)
begin
if ( spics_n )
number <= { number[6:0], spido };
else
indata <= { indata[6:0], spido };
end
always @(negedge spick or posedge spics_n)
begin
if ( spics_n )
bitptr <= 3'b111;
else
bitptr <= bitptr - 3'b001;
end
always @(posedge fclk)
begin
spicsn_resync <= { spicsn_resync[0], spics_n };
if ( spicsn_rising )
case ( number )
FLASH_LOADDR: flash_addr[7:0] <= indata;
FLASH_MIDADDR: flash_addr[15:8] <= indata;
FLASH_HIADDR: flash_addr[18:16] <= indata[2:0];
FLASH_DATA: flash_data_out <= indata;
FLASH_CTRL: begin
flash_cs <= indata[0];
flash_oe <= indata[1];
flash_we <= indata[2];
end
SCR_LOADDR: scr_addr[7:0] <= indata;
SCR_HIADDR: scr_addr[9:8] <= indata[1:0];
SCR_CHAR: begin
scr_char <= indata[6:0];
scr_wren_c <= 1'b1;
end
SCR_MODE: scr_tv_mode <= ~indata[0];
endcase
if ( spicsn_falling )
begin
scr_wren_c <= 1'b0;
if ( number==SCR_CHAR )
scr_addr <= scr_addr + 10'd1;
if ( number==FLASH_DATA )
outdata <= d;
else
outdata <= 8'hff;
end
end
assign spicsn_rising = (spicsn_resync==2'b01);
assign spicsn_falling = (spicsn_resync==2'b10);
assign sd_selected = ( ( (number==SD_CS0) || (number==SD_CS1) ) && (~spics_n) );
assign spidi = sd_selected ? sddi : outdata[bitptr];
assign sddo = sd_selected ? spido : 1'b1;
assign sdclk = sd_selected ? spick : 1'b0;
assign sdcs_n = !( (number==SD_CS0) && (~spics_n) );
assign a[13:0] = flash_addr[13:0];
assign rompg0_n = ~flash_addr[14];
assign { rompg4, rompg3, rompg2, dos_n } = flash_addr[18:15];
assign csrom = flash_cs;
assign romoe_n = ~flash_oe;
assign romwe_n = ~flash_we;
assign d = flash_oe ? 8'bZZZZZZZZ : flash_data_out;
//-----------------------------------------------------------------------------
endmodule
|
#include <bits/stdc++.h> using namespace std; const int mx=2e5+10; const int INF=0x3f3f3f; long long tes[mx][2][2]; bool flg[mx][2][2]; int hd[mx],nx[mx*2],t[mx*2],vl[mx*2]; int sum; struct Node { int x,y,z; long long jud; bool operator < (const Node &nd) const { return jud>nd.jud; } }; void add(int x,int y,int z) { t[++sum]=y; nx[sum]=hd[x]; vl[sum]=z; hd[x]=sum; } void chg() { priority_queue<Node> q; q.push({1,0,0,0}); memset(tes,0x3f,sizeof(tes)); tes[1][0][0]=0; while(!q.empty()) { Node upp=q.top(); q.pop(); int x=upp.x,y=upp.y,z=upp.z; if(flg[x][y][z]) continue; flg[x][y][z]=1; for(int i=hd[x];i;i=nx[i]) { int a=vl[i],b=t[i]; if(tes[b][y][z]>tes[x][y][z]+a) { tes[b][y][z]=tes[x][y][z]+a; q.push({b,y,z,tes[b][y][z]}); } if(!y) { if(tes[b][y^1][z]>tes[x][y][z]) { tes[b][y^1][z]=tes[x][y][z]; q.push({b,y^1,z,tes[b][y^1][z]}); } } if(!z) { if(tes[b][y][z^1]>tes[x][y][z]+a*2) { tes[b][y][z^1]=tes[x][y][z]+a*2; q.push({b,y,z^1,tes[b][y][z^1]}); } } if(!y&&!z) { if(tes[b][y^1][z^1]>tes[x][y][z]+a) { tes[b][y^1][z^1]=tes[x][y][z]+a; q.push({b,y^1,z^1,tes[b][y^1][z^1]}); } } } } } int main() { int n,m; scanf( %d %d ,&n,&m); for(int i=1;i<=m;i++) { int x,y,z; scanf( %d %d %d ,&x,&y,&z); add(x,y,z); add(y,x,z); } chg(); for(int i=2;i<=n;i++) cout<<tes[i][1][1]<< ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2111AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O2111AI_BEHAVIORAL_PP_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2111ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
// Local signals
wire C1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2111AI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; int main() { long long dp[3001][100][2] = {0}; long long n, l; cin >> n >> l; vector<long long> a(n), b(n); for (long long i = 0; i < n; ++i) { cin >> a[i] >> b[i]; dp[a[i]][i][0] = 1; dp[b[i]][i][1] = 1; } for (long long i = 1; i <= l; ++i) { for (long long j = 0; j < n; ++j) { for (long long k = 0; k < n; ++k) { if (j != k) { if (a[j] == b[k] && i - a[j] >= 0) { dp[i][j][0] = (dp[i][j][0] + dp[i - a[j]][k][0]) % mod; } if (a[j] == a[k] && a[k] != b[k] && i - a[j] >= 0) { dp[i][j][0] = (dp[i][j][0] + dp[i - a[j]][k][1]) % mod; } if (b[j] == b[k] && a[j] != b[j] && i - b[j] >= 0) { dp[i][j][1] = (dp[i][j][1] + dp[i - b[j]][k][0]) % mod; } if (b[j] == a[k] && a[j] != b[j] && a[k] != b[k] && i - b[j] >= 0) { dp[i][j][1] = (dp[i][j][1] + dp[i - b[j]][k][1]) % mod; } } } } } long long res = 0; for (long long i = 0; i < n; ++i) { res = (res + dp[l][i][0]) % mod; if (a[i] != b[i]) res = (res + dp[l][i][1]) % mod; } cout << res << endl; return 0; } |
module TX_control
#( parameter INTER_BYTE_DELAY = , // ciclos de reloj de espera entre el envio de 2 bytes consecutivos
parameter WAIT_FOR_REGISTER_DELAY = 100 // tiempo de espera para iniciar la transmision luego de registrar el dato a enviar
)(
input clock,
input reset,
input PB, // Push Button
input send16, // Indica si se deben enviar 8 o 16 bits
input [15:0] dataIn16, // Dato que se desea transmitir de 16 bits
output reg [7:0] tx_data, // Datos entregados al driver UART para transmision
output reg tx_start, // Pulso para iniciar transmision por la UART
output reg busy // Indica si hay una transmision en proceso
);
reg [2:0] next_state, state;
reg [15:0] tx_data16;
reg [31:0] hold_state_timer;
//state encoding
localparam IDLE = 3'd0; // Modo espera
localparam REGISTER_DATAIN16 = 3'd1; // Cuando se presiona boton, registrar 16 bits a enviar
localparam SEND_BYTE_0 = 3'd2; // Enviar el primer byte
localparam DELAY_BYTE_0 = 3'd3; // Esperar un tiempo suficiente para que la transmision anterior termine
localparam SEND_BYTE_1 = 3'd4; // Si es necesario, enviar el segundo byte
localparam DELAY_BYTE_1 = 3'd5; // Esperar a que la transmision anterior termine
// combo logic of FSM
always@(*) begin
//default assignments
next_state = state;
busy = 1'b1;
tx_start = 1'b0;
tx_data = tx_data16[7:0];
case (state)
IDLE: begin
busy = 1'b0;
if(PB) begin
next_state=REGISTER_DATAIN16;
end
end
REGISTER_DATAIN16: begin
if(hold_state_timer >= WAIT_FOR_REGISTER_DELAY)
next_state=SEND_BYTE_0;
end
SEND_BYTE_0: begin
next_state = DELAY_BYTE_0;
tx_start = 1'b1;
end
DELAY_BYTE_0: begin
//tx_data = tx_data16[15:8];
if(hold_state_timer >= INTER_BYTE_DELAY) begin
if (send16)
next_state = SEND_BYTE_1;
else
next_state = IDLE;
end
end
SEND_BYTE_1: begin
tx_data = tx_data16[15:8];
next_state = DELAY_BYTE_1;
tx_start = 1'b1;
end
DELAY_BYTE_1: begin
if(hold_state_timer >= INTER_BYTE_DELAY)
next_state = IDLE;
end
endcase
end
//when clock ticks, update the state
always@(posedge clock) begin
if(reset)
state <= IDLE;
else
state <= next_state;
end
// registra los datos a enviar
always@ (posedge clock) begin
if(state == REGISTER_DATAIN16)
tx_data16 <= dataIn16;
end
//activa timer para retener un estado por cierto numero de ciclos de reloj
always@(posedge clock) begin
if(state == DELAY_BYTE_0 || state == DELAY_BYTE_1 || state == REGISTER_DATAIN16) begin
hold_state_timer <= hold_state_timer + 1;
end else begin
hold_state_timer <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; string itos(int a) { if (!a) return 0 ; string res; while (a) { res += (char)( 0 + (a % 10)); a /= 10; } reverse((res).begin(), (res).end()); return res; } int main() { int n; int a[10], can = 0; ; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; can |= 1 << a[i]; } if (n > 6) { cout << 0 << endl; return 0; } vector<string> v; vector<int> mask; for (int i = 0; i < 256; i++) { string s = itos(i); int tmp = 0; for (int j = 0; j < s.size(); j++) { tmp |= 1 << (int)(s[j] - 0 ); } if ((tmp & can) == tmp) { v.push_back(s); mask.push_back(tmp); } } vector<string> ans; for (int i = 0; i < (int)(v.size()); i++) for (int j = 0; j < (int)(v.size()); j++) { int size = min(v[i].size(), v[j].size()); bool f = true; for (int k = 0; k < size; k++) { if (v[i][k] != v[j][v[j].size() - 1 - k]) { f = false; break; } } if (!f) continue; for (int k = 0; k < (int)(v.size()); k++) for (int l = 0; l < (int)(v.size()); l++) { if ((mask[i] | mask[j] | mask[k] | mask[l]) != can) continue; string s = v[i] + v[k] + v[l] + v[j]; bool f = true; for (int x = 0; 2 * x < s.size(); x++) { if (s[x] != s[s.size() - 1 - x]) { f = false; break; } } if (f) ans.push_back(v[i] + . + v[k] + . + v[l] + . + v[j]); } } cout << ans.size() << endl; for (int i = 0; i < ans.size(); i++) cout << ans[i] << endl; } |
#include <bits/stdc++.h> using namespace std; inline namespace Infinity { inline namespace Constant { constexpr const int eof = EOF; constexpr const int maxint = INT_MAX; constexpr const long long maxll = LLONG_MAX; } // namespace Constant inline namespace TypeDefine { using uint = unsigned int; using ull = unsigned long long int; using ld = long double; template <typename T = vector<int>> using iter = typename T::iterator; template <typename T = int> using vector_vector = vector<vector<T>>; template <typename T = int, typename U = int> using vector_pair = vector<pair<T, U>>; } // namespace TypeDefine inline namespace IO { const char CR = n ; const char SP = ; inline void write(const int n) { printf( %d , n); } inline void write(const unsigned n) { printf( %u , n); } inline void write(const long long n) { cout << n; } inline void write(const unsigned long long n) { cout << n; } inline void writef(const double a, const int n = 15) { printf( %.*f , n, a); } inline void writef(const long double a, const int n = 18) { cout << setprecision(n) << fixed << a; } inline void write(const char c) { printf( %c , c); } inline void write(const char s[]) { printf( %s , s); } inline void write(const string &s) { printf( %s , s.data()); } inline void write(const pair<int, int> &p) { printf( %d %d , p.first, p.second); } template <class T> inline void write(const T a) { for (auto i = a.begin(); i != a.end(); i++) { if (i != a.begin()) write(SP); write(*i); } } template <typename T> inline void writer(T begin, T end) { for (write(*begin++); begin != end; ++begin) write(SP), write(*begin); } inline void writeln() { write(CR); } template <typename T> inline void writeln(const T &a) { write(a); write(CR); } inline void writefln(const double a, int n) { printf( %.*f , n, a); write(CR); } inline void writefln(const long double a, int n = 18) { cout << setprecision(n) << fixed << a << endl; } inline void writesln(const int *a, const int l, const int r) { for (int i = l; i <= r; i++) printf( %d , a[i]); writeln(CR); } template <typename T> inline void writerln(T begin, T end) { for (write(*begin++); begin != end; ++begin) write(SP), write(*begin); write(CR); } template <class T> inline void writelns(const T &a) { for (auto n : a) writeln(n); } template <typename T, typename... types> inline void write(const T &a, const types &...args) { write(a); write(args...); } template <typename... types> inline void writeln(const types &...args) { write(args...); write(CR); } template <typename... types> inline void writeSP(const types &...args) { write(args...); write(SP); } inline void writelnYN(bool b) { writeln(b ? YES : NO ); } inline void writelnyn(bool b) { writeln(b ? Yes : No ); } string caseSharpSpace(int n) { return Case # + to_string(n) + : ; } string caseNoSharpSpace(int n) { return Case + to_string(n) + : ; } string caseSharpNoSpace(int n) { return Case # + to_string(n) + : ; } string caseNoSharpNoSpace(int n) { return Case + to_string(n) + : ; } inline int read(int &n) { return scanf( %d , &n); } inline int read(long long &n) { return cin >> n ? 1 : -1; } template <typename T, typename... types> inline int read(T &n, types &...args) { return read(n) == -1 ? -1 : read(args...) + 1; } inline char getcc() { char c; do c = getchar(); while (c == || c == n ); return c; } inline int getint() { int n; read(n); return n; } inline long long getll() { long long n; read(n); return n; } inline double getdouble() { double n; scanf( %lf , &n); return n; } inline vector<int> getints(int n) { vector<int> v(n); for (int i = 0; i < n; i++) v[i] = getint(); return v; } inline vector<pair<int, int>> getpairs(int n) { vector<pair<int, int>> v(n); for (int i = 0; i < n; i++) { int a = getint(), b = getint(); v[i] = pair<int, int>(a, b); } return v; } inline void read(string &str, const unsigned size) { char s[size]; scanf( %s , s); str.assign(s); } inline string getstr(const unsigned size = 1048576) { string s; read(s, size + 1); return s; } inline string getln(const unsigned size = 1048576) { char s[size + 1]; scanf( %[^ n] , s); getchar(); return string(s); } } // namespace IO inline namespace Function { inline constexpr int ctoi(const char c) { return c - 0 ; } inline constexpr char itoc(const int n) { return n + 0 ; } inline int dtoi(const double d) { return round(d); } template <typename T> inline constexpr bool in(T x, T l, T r) { return l <= x && x <= r; } template <class T> inline int size(const T &a) { return a.size(); } template <class T> inline void sort(T &a) { std::sort(a.begin(), a.end()); } template <class T1, class T2> inline void sort(T1 &a, T2 comp) { std::sort(a.begin(), a.end(), comp); } template <class T1, typename T2> inline int lbound(const T1 &a, const T2 k) { return lower_bound(a.begin(), a.end(), k) - a.begin(); } template <class T1, typename T2> inline int ubound(const T1 &a, const T2 k) { return upper_bound(a.begin(), a.end(), k) - a.begin(); } template <class T1, class T2> int count(T1 &a, T2 k) { return ubound(a, k) - lbound(a, k); } template <class T1, class T2> int find(T1 &a, T2 k) { return count(a, k) ? lbound(a, k) : -1; } template <typename T> inline void clear(T &a) { memset(a, 0, sizeof a); } template <typename T> T gcd(T a, T b) { while (b) { T t = a % b; a = b; b = t; } return a; } template <typename T> T lcm(T a, T b) { return a / gcd(a, b) * b; } long long qpow(long long a, long long b, long long c) { return b ? qpow(a * a % c, b >> 1, c) * (b & 1 ? a : 1) % c : 1; } template <typename T> T exGcd(T a, T b, T &x, T &y) { T d = a; if (b) { d = exGcd(b, a % b, y, x); y -= a / b * x; } else { x = 1; y = 0; } return d; } template <typename T> T constexpr inline mps(T l, T r, T k) { return ((r - (r % k + k) % k) - (l + (k - l % k) % k)) / k + 1; } template <typename T> T constexpr inline sgn(T a) { return a == 0 ? 0 : a > 0 ? 1 : -1; } template <typename T> constexpr inline T sq(T a) { return a * a; } template <typename T> constexpr inline bool odd(T a) { return bool(a % 2); } template <typename T> constexpr inline bool even(T a) { return !bool(a % 2); } template <typename T1, typename T2> constexpr inline T1 smod(T1 x, T2 m) { return x > m ? x - m : x + m < m ? x + m : x; } template <typename T, typename F> T dichotomy(T l, T r, F check, T prec = 1) { while (r - l > prec) { T m = l + (r - l) / 2; check(m) ? l = m : r = m; } return l; } bool contains(const string &s, const string &t) { return s.find(t) != string::npos; } template <typename T> bool contains(const T &s, typename T::value_type t) { for (typename T::value_type c : s) if (c == t) return true; return false; } } // namespace Function } // namespace Infinity int main(int, char *[]) { int n = getint(); vector<int> a = getints(n); vector<string> s(n), r(n); for (int i = 0; i < n; i++) { cin >> s[i]; r[i].resize(s[i].size()); reverse_copy(s[i].begin(), s[i].end(), r[i].begin()); } vector<vector<unsigned long long>> d(n, vector<unsigned long long>(2, -1)); d[0][0] = 0; d[0][1] = a[0]; for (int i = 1; i < n; i++) { if (s[i] >= s[i - 1]) { d[i][0] = min(d[i][0], d[i - 1][0]); } if (s[i] >= r[i - 1]) { d[i][0] = min(d[i][0], d[i - 1][1]); } if (r[i] >= s[i - 1] && d[i - 1][0] != -1) { d[i][1] = min(d[i][1], d[i - 1][0] + a[i]); } if (r[i] >= r[i - 1] && d[i - 1][1] != -1) { d[i][1] = min(d[i][1], d[i - 1][1] + a[i]); } } writeln((long long)(min(d.back().front(), d.back().back()))); return 0; } |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200005; int n, m; char s[maxn]; long long ans[maxn]; int sz[maxn]; int cnt[1 << 20]; vector<int> g[maxn]; bool die[maxn]; int getsz(int x, int f) { sz[x] = 1; for (int y : g[x]) if (y != f && !die[y]) sz[x] += getsz(y, x); return sz[x]; } int getrt(int tot, int x, int f) { for (int y : g[x]) if (y != f && !die[y]) if (sz[y] * 2 >= tot) return getrt(tot, y, x); return x; } int h(int x) { return 1 << (s[x] - a ); } void update(int x, int f, int coe, int pre) { cnt[pre ^= h(x)] += coe; for (int y : g[x]) if (y != f && !die[y]) update(y, x, coe, pre); } long long query(int x, int f, int pre) { long long pass = cnt[pre ^= h(x)]; for (int i = 0; i < 20; i++) pass += cnt[pre ^ (1 << i)]; for (int y : g[x]) if (y != f && !die[y]) pass += query(y, x, pre); ans[x] += pass; return pass; } void solve(int x) { die[x] = 1; update(x, 0, 1, h(x)); long long pass = cnt[h(x)]; for (int i = 0; i < 20; i++) pass += cnt[(1 << i) ^ h(x)]; for (int y : g[x]) if (!die[y]) { update(y, x, -1, 0); pass += query(y, x, h(x)); update(y, x, 1, 0); } update(x, 0, -1, h(x)); ans[x] += pass / 2 + 1; for (int y : g[x]) if (!die[y]) solve(getrt(getsz(y, x), y, x)); } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); g[u].push_back(v); g[v].push_back(u); } scanf( %s , s + 1); solve(getrt(getsz(1, 0), 1, 0)); for (int i = 1; i <= n; i++) printf( %lld , ans[i]); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BO_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__A21BO_BEHAVIORAL_PP_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BO_BEHAVIORAL_PP_V |
`include "defines.vh"
module primogen #(
parameter WIDTH_LOG = 4
) (clk, go, rst, ready, error, res);
localparam WIDTH = 1 << WIDTH_LOG;
localparam HI = WIDTH - 1;
input clk;
input go;
input rst;
output reg ready;
output reg error;
output reg [HI:0] res;
localparam MAX = {WIDTH{1'b1}};
// Note that incrementing address width
// by 1 bit would double BRAM consumption
localparam ADDR_WIDTH = 8;
localparam ADDR_HI = ADDR_WIDTH - 1;
`ifdef SIM
// Use reduced RAM for tests
localparam ADDR_MAX = 4'd8;
`else
localparam ADDR_MAX = {ADDR_WIDTH{1'b1}};
`endif
localparam XW = {WIDTH{1'bx}};
localparam X7 = 7'bx;
localparam XA = {ADDR_WIDTH{1'bx}};
localparam READY = 4'd0;
localparam ERROR = 4'd1;
localparam NEXT_CANDIDATE = 4'd2;
localparam NEXT_PRIME_DIVISOR = 4'd3;
localparam PRIME_DIVIDE_START = 4'd4; // TODO: can we get rid of this?
localparam PRIME_DIVIDE_WAIT = 4'd5;
localparam NEXT_DIVISOR = 4'd6;
localparam DIVIDE_START = 4'd7; // TODO: can we get rid of this?
localparam DIVIDE_WAIT = 4'd8;
// Combinational logic for outputs
reg [HI:0] next_res;
wire next_ready;
wire next_error;
// State
reg [3:0] state;
reg [HI:0] res_squared;
// And it's combinational logic
reg [3:0] next_state;
reg [HI:0] next_res_squared;
// Submodule inputs
reg [HI:0] div;
reg [HI:0] div_squared;
reg div_go;
reg [ADDR_HI:0] addr;
reg [ADDR_HI:0] naddrs;
reg write_en;
// And their combinational logic
reg [HI:0] next_div;
reg [HI:0] next_div_squared;
reg next_div_go;
reg [ADDR_HI:0] next_addr;
reg [ADDR_HI:0] next_naddrs;
reg next_write_en;
// Submodule outputs
wire div_ready;
wire div_error;
wire [HI:0] rem;
wire [HI:0] dout;
wire [HI:0] dout_squared;
// We store both primes and their squares
ram #(.WIDTH(2*WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) primes(
.din({res, res_squared}),
.addr(addr),
.write_en(write_en),
.clk(clk),
.dout({dout, dout_squared})
);
divrem #(.WIDTH_LOG(WIDTH_LOG)) dr(
.clk(clk),
.go(div_go),
.rst(rst),
.num(res),
.den(div),
.ready(div_ready),
.error(div_error),
.rem(rem));
assign next_ready = next_state == READY || next_state == ERROR;
assign next_error = next_state == ERROR;
always @* begin
next_state = state;
next_res = res;
next_res_squared = res_squared;
next_div = div;
next_div_squared = div_squared;
next_div_go = 0;
next_addr = addr;
next_naddrs = naddrs;
next_write_en = 0;
case (state)
READY:
begin
if (go) begin
next_state = NEXT_CANDIDATE;
next_addr = 0;
end
end
ERROR:
; // Do nothing
NEXT_CANDIDATE: // TODO: can probably be merged with NEXT_PRIME_DIVISOR
begin
// Search for next prime
case (res)
1:
begin
next_res = 8'd2;
next_res_squared = 8'd4;
end
2:
begin
next_res = 8'd3;
next_res_squared = 8'd9;
end
default:
begin
next_res = res + 8'd2;
// Square is subject to overflow
if (next_res < (1'd1 << (WIDTH / 2))) begin
next_res_squared = res_squared + (res << 2) + 8'd4;
`assert_lt(res_squared, next_res_squared);
end else
next_res_squared = MAX;
end
endcase
next_addr = 0;
// Check for overflow
next_state = next_res > res ? NEXT_PRIME_DIVISOR : ERROR;
end
NEXT_PRIME_DIVISOR:
if (naddrs == 0 || dout_squared > res) begin
next_state = READY;
// Store found prime
if (res != 1'd1 && res != 2'd2) begin
next_write_en = 1'd1;
next_addr = naddrs;
next_naddrs = naddrs + 1'd1;
end
end else if (addr < naddrs) begin
next_state = PRIME_DIVIDE_START;
next_div = dout;
next_div_squared = dout_squared;
next_div_go = 1;
end else if (naddrs == ADDR_MAX) begin
// Prime table overflow => use slow check
next_state = NEXT_DIVISOR;
next_div = div + 8'd2;
next_div_squared = div_squared + (div << 2) + 8'd4;
`assert_lt(div_squared, next_div_squared);
end else begin
next_state = ERROR;
`unreachable;
end
PRIME_DIVIDE_START:
// Wait state to allow divrem to register inputs and update ready bit
next_state = PRIME_DIVIDE_WAIT;
PRIME_DIVIDE_WAIT:
if (div_error) begin
next_state = ERROR;
end else if (!div_ready)
; // Keep waiting
else if (rem == 0) begin
// Divisable => abort and try next candidate
next_state = NEXT_CANDIDATE;
next_addr = 0;
end else begin
// Not divisable => try next divisor
next_state = NEXT_PRIME_DIVISOR;
next_addr = addr + 1'd1;
end
NEXT_DIVISOR:
if (div_squared > res) begin
// None of potential divisors matched => number is prime!
next_state = READY;
end else begin
next_state = DIVIDE_START;
next_div_go = 1;
end
DIVIDE_START:
// Wait state to allow divrem to register inputs and update ready bit
next_state = DIVIDE_WAIT;
DIVIDE_WAIT:
if (div_error) begin
next_state = ERROR;
end else if (!div_ready)
; // Keep waiting
else if (rem == 0) begin
// Divisable => abort and try next candidate
next_state = NEXT_CANDIDATE;
end else begin
// Not divisable => try next divisor
case (div)
2:
begin
next_div = 8'd3;
next_div_squared = 8'd9;
end
7:
begin
next_div = 8'd11;
next_div_squared = 8'd121;
end
// 3, 5 and 11 are covered by default branch
default:
begin
next_div = div + 8'd2;
next_div_squared = div_squared + (div << 2) + 8'd4;
end
endcase
// div * div < res so shouldn't overflow
`assert_lt(next_div, div);
// Clamp square as it's subject to overflow
// TODO: this may not be necessary
if (next_div_squared <= div_squared)
next_div_squared = MAX;
next_state = NEXT_DIVISOR;
end
default:
begin
next_state = 3'bx;
next_res = XW;
next_res_squared = XW;
next_div = XW;
next_div_squared = XW;
next_div_go = 1'bx;
next_addr = XA;
end
endcase
end
always @(posedge clk)
if (rst) begin
// Start by outputting the very first prime...
state <= READY;
res_squared <= 1;
res <= 1;
ready <= 1;
error <= 0;
div <= XW;
div_squared <= XW;
div_go <= 0;
addr <= XA;
naddrs <= 0;
write_en <= 0;
end else begin
state <= next_state;
res_squared <= next_res_squared;
res <= next_res;
ready <= next_ready;
error <= next_error;
div <= next_div;
div_squared <= next_div_squared;
div_go <= next_div_go;
addr <= next_addr;
naddrs <= next_naddrs;
write_en <= next_write_en;
end
`ifdef SIM
always @(posedge clk) begin
// Precondition: core signals must always be valid
`assert_nox(rst);
`assert_nox(clk);
if (!rst) begin
// Invariant: output looks like prime
`assert(res[0] || (res == 2));
end
end
`endif
`ifdef SIM
// initial
// $monitor("%t: clk=%b, go=%b, state=%h, res=%0d, res_squared=%0d, addr=%0d, next_addr=%0d, naddrs=%0d, write_en=%0d, div=%0d, div_squared=%0d, div_go=%b, rem=%0d, div_ready=%b, dout=%0d, dout_squared=%0d", $time, clk, go, state, res, res_squared, addr, next_addr, naddrs, write_en, div, div_squared, div_go, rem, div_ready, dout, dout_squared);
`endif
endmodule
|
#include <bits/stdc++.h> int a[1005][1005]; int n; void solve(int x) { for (int flag = 0; flag < n; flag++) { if (a[x][flag] == 0) { for (int flag1 = flag; flag1 < n; flag1++) { a[x][flag1] = a[x][flag1 + 1]; } break; } } } int main() { while (scanf( %d , &n) != EOF) { memset(a, 0, sizeof(a)); for (int flag = 0; flag < n; flag++) { for (int flag1 = 0; flag1 < n; flag1++) { a[flag][flag1] = (flag + flag1) % n; } } for (int flag = 1; flag < n; flag++) { solve(flag); } for (int flag = 1; flag < n; flag++) { a[flag][n - 1] = a[flag][flag]; a[flag][flag] = 0; } for (int flag = 0; flag < n; flag++) { for (int flag1 = 0; flag1 < flag; flag1++) { a[flag][flag1] = a[flag1][flag]; } } for (int flag = 0; flag < n; flag++) { printf( %d , a[flag][0]); for (int flag1 = 1; flag1 < n; flag1++) { printf( %d , a[flag][flag1]); } printf( n ); } } } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Ted Campbell.
// SPDX-License-Identifier: CC0-1.0
//With MULTI_CLK defined shows bug, without it is hidden
`define MULTI_CLK
//bug634
module t (
input i_clk_wr,
input i_clk_rd
);
wire wr$wen;
wire [7:0] wr$addr;
wire [7:0] wr$wdata;
wire [7:0] wr$rdata;
wire rd$wen;
wire [7:0] rd$addr;
wire [7:0] rd$wdata;
wire [7:0] rd$rdata;
wire clk_wr;
wire clk_rd;
`ifdef MULTI_CLK
assign clk_wr = i_clk_wr;
assign clk_rd = i_clk_rd;
`else
assign clk_wr = i_clk_wr;
assign clk_rd = i_clk_wr;
`endif
FooWr u_wr (
.i_clk ( clk_wr ),
.o_wen ( wr$wen ),
.o_addr ( wr$addr ),
.o_wdata ( wr$wdata ),
.i_rdata ( wr$rdata )
);
FooRd u_rd (
.i_clk ( clk_rd ),
.o_wen ( rd$wen ),
.o_addr ( rd$addr ),
.o_wdata ( rd$wdata ),
.i_rdata ( rd$rdata )
);
FooMem u_mem (
.iv_clk ( {clk_wr, clk_rd } ),
.iv_wen ( {wr$wen, rd$wen } ),
.iv_addr ( {wr$addr, rd$addr } ),
.iv_wdata ( {wr$wdata,rd$wdata} ),
.ov_rdata ( {wr$rdata,rd$rdata} )
);
endmodule
// Memory Writer
module FooWr(
input i_clk,
output o_wen,
output [7:0] o_addr,
output [7:0] o_wdata,
input [7:0] i_rdata
);
reg [7:0] cnt = 0;
// Count [0,200]
always @( posedge i_clk )
if ( cnt < 8'd50 )
cnt <= cnt + 8'd1;
// Write addr in (10,30) if even
assign o_wen = ( cnt > 8'd10 ) && ( cnt < 8'd30 ) && ( cnt[0] == 1'b0 );
assign o_addr = cnt;
assign o_wdata = cnt;
endmodule
// Memory Reader
module FooRd(
input i_clk,
output o_wen,
output [7:0] o_addr,
output [7:0] o_wdata,
input [7:0] i_rdata
);
reg [7:0] cnt = 0;
reg [7:0] addr_r;
reg en_r;
// Count [0,200]
always @( posedge i_clk )
if ( cnt < 8'd200 )
cnt <= cnt + 8'd1;
// Read data
assign o_wen = 0;
assign o_addr = cnt - 8'd100;
// Track issued read
always @( posedge i_clk )
begin
addr_r <= o_addr;
en_r <= ( cnt > 8'd110 ) && ( cnt < 8'd130 ) && ( cnt[0] == 1'b0 );
end
// Display to console 100 cycles after writer
always @( negedge i_clk )
if ( en_r ) begin
`ifdef TEST_VERBOSE
$display( "MEM[%x] == %x", addr_r, i_rdata );
`endif
if (addr_r != i_rdata) $stop;
end
endmodule
// Multi-port memory abstraction
module FooMem(
input [2 -1:0] iv_clk,
input [2 -1:0] iv_wen,
input [2*8-1:0] iv_addr,
input [2*8-1:0] iv_wdata,
output [2*8-1:0] ov_rdata
);
FooMemImpl u_impl (
.a_clk ( iv_clk [0*1+:1] ),
.a_wen ( iv_wen [0*1+:1] ),
.a_addr ( iv_addr [0*8+:8] ),
.a_wdata ( iv_wdata[0*8+:8] ),
.a_rdata ( ov_rdata[0*8+:8] ),
.b_clk ( iv_clk [1*1+:1] ),
.b_wen ( iv_wen [1*1+:1] ),
.b_addr ( iv_addr [1*8+:8] ),
.b_wdata ( iv_wdata[1*8+:8] ),
.b_rdata ( ov_rdata[1*8+:8] )
);
endmodule
// Dual-Port L1 Memory Implementation
module FooMemImpl(
input a_clk,
input a_wen,
input [7:0] a_addr,
input [7:0] a_wdata,
output reg [7:0] a_rdata,
input b_clk,
input b_wen,
input [7:0] b_addr,
input [7:0] b_wdata,
output reg [7:0] b_rdata
);
/* verilator lint_off MULTIDRIVEN */
reg [7:0] mem[0:255];
/* verilator lint_on MULTIDRIVEN */
always @( posedge a_clk )
if ( a_wen )
mem[a_addr] <= a_wdata;
always @( posedge b_clk )
if ( b_wen )
mem[b_addr] <= b_wdata;
always @( posedge a_clk )
a_rdata <= mem[a_addr];
always @( posedge b_clk )
b_rdata <= mem[b_addr];
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program checks that the code generator properly handles
* ocncatenation expressions as parameters to system tasks.
*/
module main;
reg [3:0] a, b;
initial begin
a = 0;
b = 0;
for (a = 0 ; a < 4'd15 ; a = a + 1)
for (b = 0 ; b < 4'd15 ; b = b + 1)
$display("{a, b} == %b", {a, b});
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; vector<long long int> f(200005, 0), d(200005, 0), l(200005, 0), r(200005, -1); map<pair<long long int, long long int>, long long int> mp; long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } long long int bpow(long long int a, long long int b) { long long int res = 1; while (b > 0) { if (b & 1) res = (res * a) % 1000000007; a = (a * a) % 1000000007; b >>= 1; } return res % 1000000007; } void fact(long long int i) { f[0] = 1; for (long long int k = 1; k <= i; k++) { (f[k] = f[k - 1] * k) %= 1000000007; } } long long int isprime(long long int n) { if (n == 1) return 0; for (long long int i = 2; i <= sqrt(n); i++) if (n % i == 0) return 0; return 1; } long long int find(long long int x) { if (f[x] == x) return x; else return f[x] = find(f[x]); } bool cmp(long long int x, long long int y) { return x < y; } long long int comb(long long int i, long long int j) { long long int k = f[i]; long long int g = (f[j] * (f[i - j])) % 1000000007; long long int h = bpow(g, 1000000007 - 2); return (k * h) % 1000000007; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n; cin >> n; vector<long long int> a(n); for (long long int i = 0; i < n; i++) cin >> a[i]; long long int mx = 0; for (long long int i = 0; i < n; i++) { mx = max(mx, a[i]); } for (long long int i = 0; i < n; i++) { long long int k = a[i], c = 0; while (k > 0) { f[k]++; r[k] = i; l[k] += (c); long long int h = k, j = c; while (h <= mx) { h *= 2; j++; if (r[h] != i) { f[h]++; r[h] = i; l[h] += j; } else break; } k /= 2; c++; } } long long int ans = 1e18; for (long long int i = 1; i <= 100000; i++) { if (f[i] == n) { ans = min(ans, l[i]); } } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 200005; int n, MOD; pair<int, int> s[MAXN]; int main() { scanf( %d , &n); int m = 0; for (int i = 1; i <= n; i++) { int a, b; scanf( %d , &a); s[++m] = make_pair(a, i); } for (int i = 1; i <= n; i++) { int a, b; scanf( %d , &a); s[++m] = make_pair(a, i); } sort(s + 1, s + m + 1); scanf( %d , &MOD); long long res = 1; for (int i = 1, j = 1; i <= m; i = j) { while (j <= m && s[i].first == s[j].first) j++; int l = j - i; int t = 0; for (int k = i + 1; k < j; k++) if (s[k] == s[k - 1]) t++; for (int k = 1; k <= l; k++) { int tk = k; while (t > 0 && tk % 2 == 0) tk /= 2, t--; res = (res * tk) % MOD; } } printf( %I64d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { os << { ; string sep; for (const auto &x : v) os << sep << x, sep = , ; return os << } ; } template <typename T, size_t size> ostream &operator<<(ostream &os, const array<T, size> &arr) { os << { ; string sep; for (const auto &x : arr) os << sep << x, sep = , ; return os << } ; } template <typename A, typename B> ostream &operator<<(ostream &os, const pair<A, B> &p) { return os << ( << p.first << , << p.second << ) ; } void dbg_out() { cerr << endl; } template <typename Head, typename... Tail> void dbg_out(Head H, Tail... T) { cerr << << H; dbg_out(T...); } const int INF = 1e9 + 5; struct segment_change { int to_add; segment_change(int _to_add = 0) : to_add(_to_add) {} void reset() { to_add = 0; } bool has_change() const { return to_add != 0; } segment_change combine(const segment_change &other) const { return segment_change(to_add + other.to_add); } }; struct segment { int minimum, count_of_min; segment(int _minimum = INF, int _count_of_min = 0) : minimum(_minimum), count_of_min(_count_of_min) {} void apply(int, const segment_change &change) { minimum += change.to_add; } void join(const segment &other) { if (other.minimum < minimum) *this = other; else if (other.minimum == minimum) count_of_min += other.count_of_min; } void join(const segment &a, const segment &b) { *this = a; join(b); } int get_goal_count(int goal) const { return minimum == goal ? count_of_min : 0; } }; pair<int, int> right_half[32]; struct min_count_seg_tree { int tree_n = 0; vector<segment> tree; vector<segment_change> changes; min_count_seg_tree(int n = -1) { if (n >= 0) init(n); } void init(int n) { tree_n = 1; while (tree_n < n) tree_n *= 2; tree.assign(2 * tree_n, segment()); changes.assign(tree_n, segment_change()); } void build(const vector<segment> &initial) { int n = int(initial.size()); init(n); assert(n <= tree_n); for (int i = 0; i < n; i++) tree[tree_n + i] = initial[i]; for (int position = tree_n - 1; position > 0; position--) tree[position].join(tree[2 * position], tree[2 * position + 1]); } void push_down(int position, int length) { if (!changes[position].has_change()) return; if (2 * position < tree_n) { changes[2 * position] = changes[2 * position].combine(changes[position]); changes[2 * position + 1] = changes[2 * position + 1].combine(changes[position]); } tree[2 * position].apply(length / 2, changes[position]); tree[2 * position + 1].apply(length / 2, changes[position]); changes[position].reset(); } void push_all(int a, int b) { assert(0 <= a && a < b && b <= tree_n); a += tree_n; b += tree_n - 1; for (int up = 31 - __builtin_clz(tree_n); up > 0; up--) { int x = a >> up, y = b >> up; push_down(x, 1 << up); if (x != y) push_down(y, 1 << up); } } void join_and_apply(int position, int length) { tree[position].join(tree[2 * position], tree[2 * position + 1]); tree[position].apply(length, changes[position]); } void join_all(int a, int b) { assert(0 <= a && a < b && b <= tree_n); a += tree_n; b += tree_n - 1; int length = 1; while (a > 1) { a /= 2; b /= 2; length *= 2; join_and_apply(a, length); if (a != b) join_and_apply(b, length); } } template <typename T_range_op> void process_range(int a, int b, bool needs_join, T_range_op &&range_op) { if (a == b) return; push_all(a, b); int original_a = a, original_b = b; int length = 1, r_size = 0; for (a += tree_n, b += tree_n; a < b; a /= 2, b /= 2, length *= 2) { if (a & 1) range_op(a++, length); if (b & 1) right_half[r_size++] = {--b, length}; } for (int i = r_size - 1; i >= 0; i--) range_op(right_half[i].first, right_half[i].second); if (needs_join) join_all(original_a, original_b); } segment query(int a, int b) { assert(0 <= a && a <= b && b <= tree_n); segment answer; process_range(a, b, false, [&](int position, int) { answer.join(tree[position]); }); return answer; } void update(int a, int b, const segment_change &change) { assert(0 <= a && a <= b && b <= tree_n); process_range(a, b, true, [&](int position, int length) { tree[position].apply(length, change); if (position < tree_n) changes[position] = changes[position].combine(change); }); } }; struct rectangle { int x1, y1, x2, y2; }; struct rect_event { int x, y1, y2, change; bool operator<(const rect_event &other) const { return x < other.x; } }; int64_t rectangle_union_area(const vector<rectangle> &rects) { if (rects.empty()) return 0; vector<int> Xs, Ys; vector<rect_event> events; for (const rectangle &rect : rects) { Xs.push_back(rect.x1); Xs.push_back(rect.x2); Ys.push_back(rect.y1); Ys.push_back(rect.y2); events.push_back({rect.x1, rect.y1, rect.y2, +1}); events.push_back({rect.x2, rect.y1, rect.y2, -1}); } sort(Xs.begin(), Xs.end()); sort(Ys.begin(), Ys.end()); Xs.resize(unique(Xs.begin(), Xs.end()) - Xs.begin()); Ys.resize(unique(Ys.begin(), Ys.end()) - Ys.begin()); int XC = int(Xs.size()); int YC = int(Ys.size()); int Y_range = Ys.back() - Ys.front(); sort(events.begin(), events.end()); int E = int(events.size()); auto &&compress_y = [&](int y) { return int(lower_bound(Ys.begin(), Ys.end(), y) - Ys.begin()); }; min_count_seg_tree tree(YC - 1); vector<segment> initial(YC - 1); for (int i = 0; i < YC - 1; i++) initial[i] = segment(0, Ys[i + 1] - Ys[i]); tree.build(initial); int64_t area = 0; for (int i = 0, e = 0; i < XC - 1; i++) { while (e < E && events[e].x <= Xs[i]) { int y1 = compress_y(events[e].y1); int y2 = compress_y(events[e].y2); tree.update(y1, y2, segment_change(events[e].change)); e++; } segment result = tree.tree[1]; area += int64_t(Y_range - result.get_goal_count(0)) * (Xs[i + 1] - Xs[i]); } return area; } int N, M, NM; vector<string> grid; vector<int> slides_to; vector<vector<int>> adj; vector<int> tour_start, tour_end; int tour; bool valid(int r, int c) { return 0 <= r && r < N && 0 <= c && c < M; } int key(int r, int c) { return valid(r, c) ? r * M + c : -1; }; void dfs(int node, int parent) { tour_start[node] = tour++; for (int neigh : adj[node]) if (neigh != parent) dfs(neigh, node); tour_end[node] = tour; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cin >> N >> M; NM = N * M; grid.resize(N); for (string &row : grid) cin >> row; slides_to.assign(NM, -1); for (int r = 0; r < N; r++) for (int c = 0; c < M; c++) { int me = key(r, c); switch (grid[r][c]) { case L : slides_to[me] = key(r, c + 2); break; case R : slides_to[me] = key(r, c - 2); break; case U : slides_to[me] = key(r + 2, c); break; case D : slides_to[me] = key(r - 2, c); break; } } adj.assign(NM, {}); for (int i = 0; i < NM; i++) if (slides_to[i] >= 0) adj[slides_to[i]].push_back(i); tour_start.assign(NM, -1); tour_end.assign(NM, -1); tour = 0; for (int i = 0; i < NM; i++) if (slides_to[i] < 0) dfs(i, -1); vector<rectangle> rects; for (int r = 0; r < N; r++) for (int c = 0; c < M; c++) if (grid[r][c] == L || grid[r][c] == U ) { int key0 = key(r, c); int key1 = grid[r][c] == L ? key(r, c + 1) : key(r + 1, c); if ((r + c) % 2 != 0) swap(key0, key1); rects.push_back({tour_start[key0], tour_start[key1], tour_end[key0], tour_end[key1]}); } cout << rectangle_union_area(rects) << n ; } |
#include <bits/stdc++.h> using namespace std; bool issub(string s, string t) { int cur = 0; for (char c : s) { if (c == t[cur]) cur++; if (cur == t.size()) return true; } return false; } int main() { int q, i; cin >> q; while (q--) { string s, t, p; cin >> s >> t >> p; int a[26], flag = 0; memset(a, 0, sizeof(a)); for (char c : s) a[c - a ]++; for (char c : p) a[c - a ]++; for (char c : t) a[c - a ]--; for (i = 0; i < 26; i++) { if (a[i] < 0) { flag = 1; } } if (flag == 0 && issub(t, s) == true) { cout << YES << endl; } else { cout << NO << endl; } } } |
#include <bits/stdc++.h> using namespace std; void _print(long long t) { cerr << t; } void _print(int t) { cerr << t; } void _print(string t) { cerr << t; } void _print(char t) { cerr << t; } void _print(long double t) { cerr << t; } void _print(double t) { cerr << t; } void _print(unsigned long long t) { cerr << t; } template <class T, class V> void _print(pair<T, V> p); template <class T> void _print(vector<T> v); template <class T> void _print(set<T> v); template <class T, class V> void _print(map<T, V> v); template <class T> void _print(multiset<T> v); template <class T, class V> void _print(pair<T, V> p) { cerr << { ; _print(p.first); cerr << , ; _print(p.second); cerr << } ; } template <class T> void _print(vector<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(set<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(multiset<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T, class V> void _print(map<T, V> v) { cerr << [ ; for (auto i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T, class V> void _print(unordered_map<T, V> v) { cerr << [ ; for (auto i : v) { _print(i); cerr << ; } cerr << ] ; } template <class T> void _print(list<T> v) { cerr << [ ; for (T i : v) { _print(i); cerr << ; } cerr << ] ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int tc = 0, T; cin >> T; while (++tc <= T) { int N; cin >> N; cout << (int)sqrt(N) + (int)cbrt(N) - (int)sqrt((int)cbrt(N)) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; vector<string> words(4 * n); string S; int aabb = 0, abab = 0, abba = 0, aaaa = 0, NO = 0; for (int i = (0); i < (4 * n); ++i) { cin >> S; int size = S.size(); int Kth = 0; string newS = ; bool canRhyme = false; for (int j = size - 1; j >= 0; --j) { if (S[j] == a || S[j] == e || S[j] == i || S[j] == u || S[j] == o ) { ++Kth; } newS = S[j] + newS; if (Kth == k) { canRhyme = true; break; } } if (canRhyme) words[i] = newS; else { stringstream out; out << i; words[i] = out.str(); } } for (int i = 0; i < n; ++i) { if (words[4 * i].compare(words[4 * i + 1]) == 0 && words[4 * i + 2].compare(words[4 * i + 3]) == 0) { if (words[4 * i].compare(words[4 * i + 2]) == 0) { ++aaaa; ++aabb; ++abab; ++abba; } else ++aabb; } else if (words[4 * i].compare(words[4 * i + 2]) == 0 && words[4 * i + 1].compare(words[4 * i + 3]) == 0) ++abab; else if (words[4 * i].compare(words[4 * i + 3]) == 0 && words[4 * i + 1].compare(words[4 * i + 2]) == 0) ++abba; else ++NO; } if (NO) cout << NO << endl; else { if (aaaa == n) cout << aaaa << endl; else if (aabb == n) cout << aabb << endl; else if (abab == n) cout << abab << endl; else if (abba == n) cout << abba << endl; else cout << NO << endl; } } |
`timescale 1ns/1ps
`define CODE_RAM U_ASYNC_MEM.U_SSRAM
module tb;
`include "useful_tasks.v" // some helper tasks
parameter ROM_ADDRESS_SIZE = 14;
reg rst_async_n; // asynchronous reset
wire req0, req1, req2;
wire ack0, ack1, ack2;
reg req0_reg;
reg start;
wire [31:0] data0;
reg [31:0] data0_reg;
wire [31:0] data1;
wire [31:0] data2;
wire [31:0] pc_fetch;
wire [31:0] next_pc_fetch;
wire [31:0] instruction;
wire [31:0] mem_dout;
// assign data0 = data0_reg;
// two_phase_event_gen U_PORT1_EVENT_GEN (
// .run(rst_async_n),
// .req(req0),
// .ack(a)
// );
mousetrap_elt #(
.WIDTH(32),
.RESET_VALUE(32'hFFFF_FFFF)
) U_MOUSETRAP_PC(
.ackNm1(), // out
.reqN(req_pc), // In
.ackN(ack_pc), // In
.doneN(pc_done), // Out
.datain(next_pc_fetch),
.dataout(pc_fetch),
.rstn(rst_async_n)
);
assign req_mem = pc_done;
/* async_mem AUTO_TEMPLATE(
); */
async_mem U_ASYNC_MEM (
.ack (mem_ack),
.dout (mem_dout),
.req (req_mem),
.addr (pc_fetch[11:0]),
.din (0),
.we (0));
mousetrap_elt #(.WIDTH(32)) U_MOUSETRAP_INSTRUCTION(
.ackNm1(inst_ack), // out
.reqN(mem_ack), // In
.ackN(ack_inst), // In
.doneN(inst_done), // Out
.datain(mem_dout),
.dataout(instruction),
.rstn(rst_async_n)
);
buff #(.DELAY(20)) U_DELAY0(.i(pc_done), .z(adder_ack));
assign #10 next_pc_fetch = pc_fetch + 1;
muller2 U_MULLER_ACK_PC(.a(adder_ack),.b(inst_ack),.rstn(rstn),.z(ack_pc));
// Nothing to do with the instruction right now
assign #5 ack_inst = inst_done;
inv U_INV(.i(ack_pc), .zn(req_pc));
// two_phase_slave U_SLAVE(.req(req3), .ack(ack2));
// assign #30 ack2_tmp = req3;
// assign ack2 = (ack2_tmp === 1'b1);
// Dump all nets to a vcd file called tb.vcd
task load_program_memory;
reg [1024:0] filename;
reg [7:0] memory [1<<ROM_ADDRESS_SIZE:0]; // byte type memory
integer i;
reg [31:0] tmp;
integer dummy;
begin
`ifndef NTL_SIM
filename = 0;
dummy = $value$plusargs("program_memory=%s", filename);
if(filename ==0) begin
$display("WARNING! No content specified for program memory");
end
else begin
$display("-I- Loading <%s>",filename);
$readmemh (filename, memory);
for(i=0; i<((1<<ROM_ADDRESS_SIZE)/4); i=i+1) begin
tmp[7:0] = memory[i*4+0];
tmp[15:8] = memory[i*4+1];
tmp[23:16] = memory[i*4+2];
tmp[31:24] = memory[i*4+3];
`CODE_RAM.RAM[i] = tmp;
end
end // else: !if(filename ==0)
`endif
end
endtask // load_program_memory
event dbg_finish;
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
initial begin
rst_async_n <= 1'b0;
start <= 1'b0;
// Wait long enough for the X's in the delay elements to disappears
#50;
rst_async_n = 1'b1;
$display("-I- Reset is released");
#5;
start <= 1'b1;
#5;
#200000;
start <= 1'b0;
$display("-I- Done !");
$finish;
end // initial begin
initial begin
#1;
load_program_memory();
end
endmodule // tb
/*
Local Variables:
verilog-library-directories:(
"."
"../../misc_lib"
"../../async_lib/memories"
)
End:
*/
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_sysid_qsys (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? : ;
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
* -------------------------------------------------------------------------------
*
* Mesh Network
*
*/
`include "types.v"
`include "parameters.v"
module LAG_mesh_network (din, dout,
input_full_flag,
cntrl_in,
clk, rst_n);
parameter XS=network_x;
parameter YS=network_y;
parameter NT=router_radix;
parameter NPL=router_num_pls;
// parameter channel_latency = 0; // number of registers in router to router link or channel
input clk, rst_n;
input [XS*YS*$bits(chan_cntrl_t) - 1 : 0] cntrl_in;
input [XS*YS*$bits(flit_t) - 1 : 0] din;
output [XS*YS*router_num_pls_on_exit*$bits(flit_t) - 1 : 0] dout;
output [XS*YS*router_num_pls_on_entry - 1 : 0] input_full_flag;
// network connections
flit_t i_flit_in [XS-1:0][YS-1:0][NT-1:0][NPL-1:0];
flit_t i_flit_in_ [XS-1:0][YS-1:0][NT-1:0][NPL-1:0];
flit_t i_flit_out [XS-1:0][YS-1:0][NT-1:0][NPL-1:0];
flit_t i_flit_out_ [XS-1:0][YS-1:0][NT-1:0][NPL-1:0];
flit_t terminator [NPL-1:0];
chan_cntrl_t i_cntrl_in [XS-1:0][YS-1:0][NT-1:0];
chan_cntrl_t i_cntrl_out [XS-1:0][YS-1:0][NT-1:0];
reg clk_g [XS-1:0][YS-1:0];
genvar x,y,p,c;
// *********************************************************
// implement router-level clock gating if requested
// *********************************************************
//
generate
for (y=0; y<YS; y=y+1) begin:ycg
for (x=0; x<XS; x=x+1) begin:xcg
//
// no router level clock gating, router clock = global clock
//
always@(clk) begin
clk_g[x][y]<=clk;
end
end // block: xcg
end // block: ycg
endgenerate
// *********************************************************
generate
for (y=0; y<YS; y=y+1) begin:yl
for (x=0; x<XS; x=x+1) begin:xl
//
// make network connections
//
// tile port - external interface
always_comb
begin
i_flit_in[x][y][`TILE] = terminator;
i_flit_in[x][y][`TILE][0] = din[$bits(flit_t)*(x*YS + y + 1) - 1 : $bits(flit_t)*(x*YS + y)]; ;
end
assign i_cntrl_in[x][y][`TILE] = cntrl_in[$bits(chan_cntrl_t)*(x*YS + y + 1) - 1 : $bits(chan_cntrl_t)*(x*YS + y)];
for (c=0; c<router_num_pls_on_exit; c++) begin:network_out_to_sink
assign dout[$bits(flit_t)*(x*YS*router_num_pls_on_exit + y*router_num_pls_on_exit + c + 1) - 1 : $bits(flit_t)*(x*YS*router_num_pls_on_exit + y*router_num_pls_on_exit + c)] = i_flit_out[x][y][`TILE][c];
end
// north port
if (y==0) begin
assign i_flit_in[x][y][`NORTH] = terminator;
assign i_cntrl_in[x][y][`NORTH] = '0;
end else begin
assign i_flit_in[x][y][`NORTH] = i_flit_out[x][y-1][`SOUTH];
assign i_cntrl_in[x][y][`NORTH] = i_cntrl_out[x][y-1][`SOUTH];
end
// east port
if (x==XS-1) begin
assign i_flit_in[x][y][`EAST] = terminator;
assign i_cntrl_in[x][y][`EAST] = '0;
end else begin
assign i_flit_in[x][y][`EAST] = i_flit_out[x+1][y][`WEST];
assign i_cntrl_in[x][y][`EAST] = i_cntrl_out[x+1][y][`WEST];
end
// south port
if (y==YS-1) begin
assign i_flit_in[x][y][`SOUTH] = terminator;
assign i_cntrl_in[x][y][`SOUTH] = '0;
end else begin
assign i_flit_in[x][y][`SOUTH] = i_flit_out[x][y+1][`NORTH];
assign i_cntrl_in[x][y][`SOUTH] = i_cntrl_out[x][y+1][`NORTH];
end
// west port
if (x==0) begin
assign i_flit_in[x][y][`WEST] = terminator;
assign i_cntrl_in[x][y][`WEST] = '0;
end else begin
assign i_flit_in[x][y][`WEST] = i_flit_out[x-1][y][`EAST];
assign i_cntrl_in[x][y][`WEST] = i_cntrl_out[x-1][y][`EAST];
end
for (p=0; p<NT; p++) begin:prts
for (c=0; c<NPL; c++) begin:channels2
always_comb
begin
i_flit_in_[x][y][p][c] = i_flit_in[x][y][p][c];
end
end
end
// ###################################
// Channel (link) between routers - ** NOT FROM ROUTER TO TILE **
// ###################################
// i_flit_out_ -> CHANNEL -> i_flit_out
//
/*for (p=0; p<NT; p++) begin:prts2
assign i_flit_out[x][y][p]=i_flit_out_[x][y][p];
end*/
for (p=0; p<NT; p++) begin:prts2
if (p==`TILE) begin
// router to tile is a local connection
assign i_flit_out[x][y][p]=i_flit_out_[x][y][p];
end else begin
LAG_pipelined_channel #(.nPC(NPL), .stages(channel_latency)) channel
(.data_in(i_flit_out_[x][y][p]),
.data_out(i_flit_out[x][y][p]), .clk, .rst_n);
end
end
// ###################################
// Router
// ###################################
// # parameters for router are read from parameters.v
LAG_router #(
.buf_len(router_buf_len),
.network_x(network_x),
.network_y(network_y),
.NT(router_radix),
.NPL(router_num_pls),
.alloc_stages(router_alloc_stages),
.router_num_pls_on_entry(router_num_pls_on_entry),
.router_num_pls_on_exit(router_num_pls_on_exit)
) node
(i_flit_in_[x][y],
i_flit_out_[x][y],
i_cntrl_in[x][y],
i_cntrl_out[x][y],
input_full_flag[router_num_pls_on_entry*(x*YS + y + 1) - 1 : router_num_pls_on_entry*(x*YS + y)],
clk_g[x][y],
rst_n);
end //x
end //y
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; struct _ { ios_base::Init i; _() { cin.sync_with_stdio(0); cin.tie(0); } } _; const int MAXN = -1; int n, m; int main() { int a, b; cin >> a >> b; int n = a + b + 1; for (int i = n - a; i <= n; ++i) cout << i << ; for (int i = n - a - 1; i >= 1; --i) cout << i << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int num[100005]; int main() { int n, k; scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , &num[i]); } sort(num, num + n); if (n < k) { printf( %d n , num[n - 1]); return 0; } else { vector<int> ans; for (int i = 0; i < n - k; i++) { ans.push_back(num[i] + num[2 * n - 2 * k - 1 - i]); } for (int i = 2 * n - 2 * k; i < n; i++) ans.push_back(num[i]); sort(ans.begin(), ans.end()); printf( %d n , ans[ans.size() - 1]); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> void chmin(T &x, const T &y) { if (x > y) x = y; } template <typename T> void chmax(T &x, const T &y) { if (x < y) x = y; } int read() { char c; while ((c = getchar()) < - ) ; if (c == - ) { int x = (c = getchar()) - 0 ; while ((c = getchar()) >= 0 ) x = x * 10 + c - 0 ; return -x; } int x = c - 0 ; while ((c = getchar()) >= 0 ) x = x * 10 + c - 0 ; return x; } const int N = 2e5 + 5, D = 998244353; int64_t mi(int64_t x, int y = D - 2) { int64_t ans = 1; while (y) { if (y & 1) ans = ans * x % D; x = x * x % D; y >>= 1; } return ans; } void operator+=(pair<int64_t, int64_t> &a, const pair<int64_t, int64_t> &b) { (a.first += b.first) %= D; (a.second += b.second) %= D; } void mul(int64_t &a0, int64_t &a1, int64_t m[2][2]) { int64_t b0 = (m[0][0] * a0 + m[0][1] * a1) % D, b1 = (m[1][0] * a0 + m[1][1] * a1) % D; a0 = b0; a1 = b1; } int64_t m[2][2], m1[2][2]; namespace SEG { const int64_t T = N * 4; int64_t tag[T][2][2], sum[T][2]; int n; void mul(int k, int64_t m[2][2]) { for (int i = 0; i <= 1; ++i) { ::mul(tag[k][0][i], tag[k][1][i], m); } ::mul(sum[k][0], sum[k][1], m); } void push_down(int k) { if ((tag[k][0][0] - 1) % D || tag[k][0][1] || tag[k][1][0] || (tag[k][1][1] - 1) % D) { mul((k * 2), tag[k]); mul(((k * 2) + 1), tag[k]); for (int i = 0; i <= 1; ++i) for (int j = 0; j <= 1; ++j) tag[k][i][j] = i == j; } } void push_up(int k) { for (int i = 0; i <= 1; ++i) sum[k][i] = (sum[(k * 2)][i] + sum[((k * 2) + 1)][i]) % D; } void add(int x, const pair<int64_t, int64_t> &a) { int k = 1, l = 1, r = n; while (1) { (sum[k][0] += a.first) %= D; (sum[k][1] += a.second) %= D; if (l == r) break; push_down(k); if (x <= ((l + r) / 2)) { k = (k * 2); r = ((l + r) / 2); } else { k = ((k * 2) + 1); l = ((l + r) / 2) + 1; } } } pair<int64_t, int64_t> query(int x) { int k = 1, l = 1, r = n; pair<int64_t, int64_t> ans = pair<int64_t, int64_t>(0, 0); while (l != r) { push_down(k); if (x <= ((l + r) / 2)) { ans += pair<int64_t, int64_t>(sum[((k * 2) + 1)][0], sum[((k * 2) + 1)][1]); k = (k * 2); r = ((l + r) / 2); } else { k = ((k * 2) + 1); l = ((l + r) / 2) + 1; } } ans += pair<int64_t, int64_t>(sum[k][0], sum[k][1]); return ans; } int ql, qr; void modify(int k, int l, int r) { if (ql > r || qr < l) return; if (ql <= l && qr >= r) { mul(k, m); return; } push_down(k); modify((k * 2), l, ((l + r) / 2)); modify(((k * 2) + 1), ((l + r) / 2) + 1, r); push_up(k); } void modify(int l, int r) { ql = l; qr = r; modify(1, 1, n); } }; // namespace SEG bool cmp(const pair<int, int> &a, const pair<int, int> &b) { return 1LL * a.first * b.second < 1LL * a.second * b.first; } pair<int, int> q[N]; int t; int main() { int n = read(); static int x[N], v[N], p[N]; for (int i = 1; i <= n; ++i) { x[i] = read(); v[i] = read(); p[i] = read() * mi(100) % D; } t = 1; q[1] = pair<int, int>(1, 0); for (int i = 2; i <= n; ++i) { q[++t] = pair<int, int>(x[i] - x[i - 1], v[i] + v[i - 1]); if (v[i] != v[i - 1]) q[++t] = pair<int, int>(x[i] - x[i - 1], abs(v[i] - v[i - 1])); } sort(q + 1, q + t + 1, cmp); SEG::n = t; SEG::add(t, pair<int64_t, int64_t>(1 - p[1], p[1])); for (int i = 2; i <= n; ++i) { int j0 = lower_bound(q + 1, q + t, pair<int, int>(x[i] - x[i - 1], v[i] + v[i - 1]), cmp) - q; int j1 = lower_bound(q + 1, q + t, pair<int, int>(x[i] - x[i - 1], abs(v[i] - v[i - 1])), cmp) - q; pair<int64_t, int64_t> s0 = SEG::query(j0), s1 = SEG::query(j1); int64_t np = p[i]; for (int i = 0; i <= 1; ++i) for (int j = 0; j <= 1; ++j) m[i][j] = (i == 0) ? 1 - np : np; SEG::modify(1, j0 - 1); for (int i = 0; i <= 1; ++i) for (int j = 0; j <= 1; ++j) if (j == 1 && i == 0) { m1[i][j] = m[i][j]; m[i][j] = 0; } else m1[i][j] = 0; mul(s0.first, s0.second, m1); SEG::modify(j0, j1 - 1); SEG::add(j0, s0); int ni = v[i] > v[i - 1] ? 0 : 1; for (int i = 0; i <= 1; ++i) for (int j = 0; j <= 1; ++j) if (i == j && (i == ni)) { m1[i][j] = m[i][j]; m[i][j] = 0; } else m1[i][j] = 0; mul(s1.first, s1.second, m1); SEG::modify(j1, t); SEG::add(j1, s1); } auto S = [&](const pair<int64_t, int64_t> &a) -> int64_t { return (a.first + a.second) % D; }; int64_t ans = 0; for (int i = 1; i <= t - 1; ++i) (ans += (S(SEG::query(i)) - S(SEG::query(i + 1))) * q[i].first % D * mi(q[i].second)) %= D; cout << (ans + D) % D << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int t, n; char s[200050]; map<int, map<int, int>> vis, cnt; scanf( %d , &t); while (t--) { vis.clear(); cnt.clear(); int l = -5, r = 0x3f3f3f3f; scanf( %d%s , &n, s); int x = 0, y = 0; vis[x][y] = 1; cnt[x][y] = 0; for (int i = 0; i < n; i++) { if (s[i] == L ) { x -= 1; } else if (s[i] == R ) { x += 1; } else if (s[i] == D ) { y -= 1; } else { y += 1; } if (vis[x][y] && i - cnt[x][y] < r - l) { l = cnt[x][y] + 1; r = i + 1; } cnt[x][y] = i + 1; vis[x][y] = 1; } if (l != -5) printf( %d %d n , l, r); else printf( -1 n ); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_BLACKBOX_V
`define SKY130_FD_SC_LP__NOR3B_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor3b (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; using ll = int64_t; using ii = pair<ll, ll>; int main() { cin.tie(nullptr); cout.tie(nullptr); ios::sync_with_stdio(false); ll n, m; cin >> n >> m; ll nn = n - 2; ll n1 = nn / 2; ll n2 = nn - n1; ll sm = (n1 + 1) * n1 / 2 + (n2 + 1) * n2 / 2; if (m == 0) { ll fff = ll(1e9) - 5050 * 5050; for (int i = (0); i < (n); i++) { cout << fff + i * 5050 << ; } cout << endl; return 0; } if (sm >= m) { if (m == 1) { cout << 1 << << 2 << << 3 << ; n -= 3; ll fff = ll(1e9) - 5050 * 5050; for (int i = (0); i < (n); i++) { cout << fff + i * 5050 << ; } cout << endl; return 0; } ll f1 = 1, f2 = 1; sm = 0; for (int i = (0); i < (n - 2); i++) { if (sm + f1 >= m) { f2 = i - 1; break; } sm += f1; if (i % 2 == 1) f1++; } ll last; ll ff1 = f1 - (m - sm); if (f2 % 2 == 0) { last = 2 * ff1 + 1; } else { last = 2 * ff1; if (ff1 == 0) last = 1; } cout << 1 << << 2 << ; for (int i = (0); i < (f2 + 1); i++) { cout << i + 3 << ; if (i == f2) { cout << i + 3 + last << ; } } ll kk = f2 + 4; kk = n - kk; ll fff = ll(1e9) - 5050 * 5050; for (int i = (0); i < (kk); i++) { cout << fff + i * 5050 << ; } cout << endl; } else { cout << -1 << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_PP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2B_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; typedef long long s64; const int MaxN = 100000 + 5; int a[MaxN]; void work() { int n; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %d , a + i); } sort(a + 1, a + n + 1); s64 ans = a[n]; for (int i = 2; i <= n; ++i) ans -= 1LL * a[i] * ((i - 1) - (n - i)); printf( %lld n , ans); } int main() { int T; scanf( %d , &T); while (T--) work(); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long o = 101; const long long p = 6e4; struct qwq { long long x, y; } a[o], b[o]; long long n, m, l, r, f[p + 1], ans = -1; bool cmp1(qwq u, qwq v) { return u.x == v.x ? u.y > v.y : u.x < v.x; } bool cmp2(qwq u, qwq v) { return u.x + u.y > v.x + v.y; } signed main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m; for (long long i = 1, x, y; i <= n; i++) { cin >> x >> y; if (y >= 0) a[++l] = (qwq){x, y}; else b[++r] = (qwq){x, y}; } memset(f, -1, sizeof(f)), f[m] = 0; sort(a + 1, a + l + 1, cmp1), sort(b + 1, b + r + 1, cmp2); for (long long i = 1; i <= l; i++) for (long long j = p; j >= a[i].x; j--) if (f[j] != -1) f[j + a[i].y] = max(f[j] + 1, f[j + a[i].y]); for (long long i = 1; i <= r; i++) for (long long j = max(b[i].x, -b[i].y); j <= p; j++) if (f[j] != -1) f[j + b[i].y] = max(f[j] + 1, f[j + b[i].y]); for (long long i = 0; i <= p; i++) ans = max(f[i], ans); cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int fr[301][301]; int al[301]; int i, j, n; cin >> n; for (i = 1; i <= n; ++i) for (j = 1; j <= n; ++j) cin >> fr[i][j]; for (i = 1; i <= n; ++i) cin >> al[i]; int k, best[301], best_time[301], cur; for (j = 1; j <= n; ++j) { best[j] = 301; best_time[j] = 301; for (i = 1; i <= n; ++i) { if (j == 1 && i == 1) continue; for (k = 1; k <= n; ++k) if (al[k] <= i && al[k] != j) { cur = al[k]; break; } for (k = 1; k <= n; ++k) { if (cur == fr[j][k]) { if (k < best[j]) { best[j] = k; best_time[j] = i; } break; } } } } for (i = 1; i <= n; ++i) cout << best_time[i] << t ; } |
#include <bits/stdc++.h> using namespace std; long long n, i, j, k, x, y, col; vector<long long> ans; long long last[100100]; int main() { cin >> n; for (i = 0; i < n; i++) { cin >> x >> y; col = 0; j = 1; while (j * j <= x) { if (x % j == 0) { k = x / j; if (last[j] < i - y + 1) { last[j] = i + 1; col++; } last[j] = i + 1; if (k != j && last[k] < i - y + 1) { col++; } last[k] = i + 1; } j++; } ans.push_back(col); } for (i = 0; i < n; i++) cout << ans[i] << endl; return 0; } |
// MBT BSG 11/13/2014
//
// a data structure that takes one word per cycle
// and allows more than one word per cycle to exit.
// the number of words extracted can vary dynamically.
//
// els_p and out_els_p can be set differently in order
// to increase the amount of buffering internal to the module
//
// * this data structure supports bypassing, so can
// have zero latency.
//
// this is a shifting-based fifo; so this is probably
// not ideal from power perspective
//
//
`include "bsg_defines.v"
module bsg_serial_in_parallel_out #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter out_els_p = els_p)
(input clk_i
, input reset_i
, input valid_i
, input [width_p-1:0] data_i
, output ready_o
, output logic [out_els_p-1:0] valid_o
, output logic [out_els_p-1:0][width_p-1:0] data_o
, input [$clog2(out_els_p+1)-1:0] yumi_cnt_i
);
localparam double_els_lp = els_p * 2;
logic [els_p-1:0][width_p-1:0] data_r, data_nn;
logic [2*els_p-1:0 ][width_p-1:0] data_n;
logic [els_p-1:0] valid_r, valid_nn;
logic [double_els_lp-1:0] valid_n;
logic [$clog2(els_p+1)-1:0] num_els_r, num_els_n;
always_ff @(posedge clk_i)
begin
if (reset_i)
begin
num_els_r <= 0;
valid_r <= 0;
end
else
begin
num_els_r <= num_els_n;
valid_r <= valid_nn;
end
end
always_ff @(posedge clk_i) begin
data_r <= data_nn;
end
// we are ready if we have at least
// one spot that is not full
assign ready_o = ~valid_r[els_p-1];
// update element count
assign num_els_n = (num_els_r + (valid_i & ready_o)) - yumi_cnt_i;
always_comb begin
data_n = data_r;
valid_n = (double_els_lp) ' (valid_r);
data_n[els_p+:els_p] = 0;
// bypass in values
data_n [num_els_r] = data_i;
valid_n[num_els_r] = valid_i & ready_o;
// this temporary value is
// the output of this function
valid_o = valid_n[out_els_p-1:0];
data_o = data_n [out_els_p-1:0];
// now we calculate the update
for (integer i = 0; i < els_p; i++) begin
data_nn[i] = data_n[yumi_cnt_i+i];
end
valid_nn = valid_n[yumi_cnt_i+:els_p];
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_serial_in_parallel_out)
|
module ArithAlu(
/* verilator lint_off UNUSED */
clk,
opMode,
srca,
srcb,
dst,
sri,
sro
);
input clk;
input[3:0] opMode;
input[63:0] srca;
input[63:0] srcb;
output[63:0] dst;
input[3:0] sri;
output[3:0] sro;
parameter[3:0] UOP_NONE = 4'h00;
parameter[3:0] UOP_ADD = 4'h01;
parameter[3:0] UOP_SUB = 4'h02;
parameter[3:0] UOP_MUL = 4'h03;
parameter[3:0] UOP_AND = 4'h04;
parameter[3:0] UOP_OR = 4'h05;
parameter[3:0] UOP_XOR = 4'h06;
parameter[3:0] UOP_SHL = 4'h07;
parameter[3:0] UOP_SHR = 4'h08;
parameter[3:0] UOP_SAR = 4'h09;
parameter[3:0] UOP_ADDC = 4'h0A;
parameter[3:0] UOP_CMPEQ = 4'h0B;
parameter[3:0] UOP_CMPGT = 4'h0C;
parameter[3:0] UOP_CMPGE = 4'h0D;
parameter[3:0] UOP_CMPHS = 4'h0E;
parameter[3:0] UOP_CMPHI = 4'h0F;
// reg[63:0] tSrcaQ;
// reg[63:0] tSrcbQ;
/* verilator lint_off UNOPTFLAT */
reg[63:0] tDstQ;
// reg[31:0] tDst;
reg[5:0] tShl;
reg[3:0] tSr;
assign dst=tDstQ;
assign sro=tSr;
always @ (opMode) begin
case(opMode)
UOP_ADD: begin
tDstQ = srca+srcb;
tSr=sri;
end
UOP_SUB: begin
tDstQ = srca-srcb;
tSr=sri;
end
UOP_MUL: begin
tDstQ = srca*srcb;
tSr=sri;
end
UOP_AND: begin
tDstQ = srca&srcb;
tSr=sri;
end
UOP_OR: begin
tDstQ = srca|srcb;
tSr=sri;
end
UOP_XOR: begin
tDstQ = srca^srcb;
tSr=sri;
end
UOP_SHL: begin
tShl = srcb[5:0];
tDstQ = srca<<tShl;
tSr=sri;
end
UOP_SHR: begin
tShl = srcb[5:0];
tDstQ = srca>>tShl;
tSr=sri;
end
UOP_SAR: begin
tShl = srcb[5:0];
tDstQ = srca>>>tShl;
tSr=sri;
end
UOP_ADDC: begin
if(sri[0])
tDstQ = srca+srcb+1;
else
tDstQ = srca+srcb;
tSr[3:2]=sri[3:2];
tSr[0]=tDstQ[31]^srca[31];
tSr[1]=tDstQ[63]^srca[63];
end
UOP_CMPEQ: begin
tDstQ = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]==srcb[31:0]);
tSr[1]=(srca[63:0]==srcb[63:0]);
end
UOP_CMPGT: begin
tDstQ = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>srcb[31:0]);
tSr[1]=(srca[63:0]>srcb[63:0]);
end
UOP_CMPGE: begin
tDstQ = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>=srcb[31:0]);
tSr[1]=(srca[63:0]>=srcb[63:0]);
end
UOP_CMPHS: begin
tDstQ = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>srcb[31:0]);
tSr[1]=(srca[63:0]>srcb[63:0]);
end
UOP_CMPHI: begin
tDstQ = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>=srcb[31:0]);
tSr[1]=(srca[63:0]>=srcb[63:0]);
end
default: begin
tDstQ = 64'h0000_0000_0000_0000;
tSr=sri;
end
endcase
// dst=tDstQ;
// sro=tSr;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int zero(int n) { if (n == 0) return 0; if (n % 10 == 0) return zero(n / 10); return 10 * zero(n / 10) + (n % 10); } int main() { int a, b; cin >> a >> b; if (zero(a) + zero(b) == zero(a + b)) { cout << YES ; } else { cout << NO ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int dx[] = {0, 0, -1, 1}; int dy[] = {-1, 1, 0, 0}; const int N = 1e6 + 5; long long ans, sum, d[N]; int n, m; int main() { int a, b; while (~scanf( %d%d , &n, &m)) { memset(d, 0, sizeof(d)); for (int i = 0; i < (m); ++i) { scanf( %d%d , &a, &b); d[a]++, d[b]++; } if (n < 3) { puts( 0 ); continue; } ans = (long long)n * (n - 1) * (n - 2) / 6; sum = 0; for (int i = (1); i <= (n); ++i) sum += d[i] * (n - 1 - d[i]); sum /= 2; printf( %lld n , ans - sum); } return 0; } |
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