text stringlengths 59 71.4k |
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/*
* Copyright 2013, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20
module test_rconst2in1;
// Inputs
reg [11:0] i;
// Outputs
wire [63:0] rc1;
wire [63:0] rc2;
// Instantiate the Unit Under Test (UUT)
rconst2in1 uut (
.i(i),
.rc1(rc1),
.rc2(rc2)
);
initial begin
// Initialize Inputs
i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
i=0; i[0] = 1;
#(`P/2);
if(rc1 !== 64'h1) begin $display("E"); $finish; end
if(rc2 !== 64'h8082) begin $display("E"); $finish; end
i=0; i[1] = 1;
#(`P/2);
if(rc1 !== 64'h800000000000808a) begin $display("E"); $finish; end
if(rc2 !== 64'h8000000080008000) begin $display("E"); $finish; end
i=0; i[2] = 1;
#(`P/2);
if(rc1 !== 64'h808b) begin $display("E"); $finish; end
if(rc2 !== 64'h80000001) begin $display("E"); $finish; end
i=0; i[3] = 1;
#(`P/2);
if(rc1 !== 64'h8000000080008081) begin $display("E"); $finish; end
if(rc2 !== 64'h8000000000008009) begin $display("E"); $finish; end
i=0; i[4] = 1;
#(`P/2);
if(rc1 !== 64'h8a) begin $display("E"); $finish; end
if(rc2 !== 64'h88) begin $display("E"); $finish; end
i=0; i[5] = 1;
#(`P/2);
if(rc1 !== 64'h80008009) begin $display("E"); $finish; end
if(rc2 !== 64'h8000000a) begin $display("E"); $finish; end
i=0; i[6] = 1;
#(`P/2);
if(rc1 !== 64'h8000808b) begin $display("E"); $finish; end
if(rc2 !== 64'h800000000000008b) begin $display("E"); $finish; end
i=0; i[7] = 1;
#(`P/2);
if(rc1 !== 64'h8000000000008089) begin $display("E"); $finish; end
if(rc2 !== 64'h8000000000008003) begin $display("E"); $finish; end
i=0; i[8] = 1;
#(`P/2);
if(rc1 !== 64'h8000000000008002) begin $display("E"); $finish; end
if(rc2 !== 64'h8000000000000080) begin $display("E"); $finish; end
i=0; i[9] = 1;
#(`P/2);
if(rc1 !== 64'h800a) begin $display("E"); $finish; end
if(rc2 !== 64'h800000008000000a) begin $display("E"); $finish; end
i=0; i[10] = 1;
#(`P/2);
if(rc1 !== 64'h8000000080008081) begin $display("E"); $finish; end
if(rc2 !== 64'h8000000000008080) begin $display("E"); $finish; end
i=0; i[11] = 1;
#(`P/2);
if(rc1 !== 64'h80000001) begin $display("E"); $finish; end
if(rc2 !== 64'h8000000080008008) begin $display("E"); $finish; end
$display("Good!");
$finish;
end
endmodule
`undef P
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__SDFSBP_PP_BLACKBOX_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_6_V
`define SKY130_FD_SC_HD__BUF_6_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 6 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__buf_6 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__buf_6 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_6_V
|
module brainfuck_top
(
input clk, rst_n,
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
input [7:0] key_in,
input key_d_en,
output txd,
input rxd,
output of_err
);
wire [31:0] op;
reg op_en;
wire [11:0] dp;
wire [15:0] d_o;
wire w_en, w_sel, w_wait;
wire [15:0] d_i;
wire r_en, d_en, r_sel;
wire ram_w_en, ram_r_en;
reg ram_d_en;
wire [15:0] ram_d_i;
wire s_rst;
wire rst;
reg lcd_wen;
reg [8:0] lcd_wdt;
wire lcd_status;
wire [11:0] pc;
wire pc_r;
assign rst = !rst_n;
brainfuck bf( .clk(clk), .rst(rst), .s_rst(s_rst),
.pc(pc), .op_r_req(pc_r), .op(op), .op_den(op_en),
.dp_adr(dp), .data_out(d_o), .data_w_req(w_en), .data_w_sel(w_sel), .data_w_wait(w_wait),
.data_in(d_i), .data_r_req(r_en), .data_r_sel(r_sel), .data_den(d_en)
);
LCDCONTROL lcd(.CLK(clk), .RST(rst), .WRITE(lcd_wen), .WRDATA(lcd_wdt), .STATUS(lcd_status),
.LCD_BLON(LCD_BLON), .LCD_RW(LCD_RW), .LCD_EN(LCD_EN), .LCD_RS(LCD_RS), .LCD_DATA(LCD_DATA)
);
wire [8:0] cmd_in;
reg [8:0] cmd [31:0];
reg [5:0] cmd_len;
wire cmd_st, cmd_busy, cmd_en;
integer ci;
wire [7:0] udout;
wire udout_en;
uart uart_1( .clk(clk), .rst(rst), .txd(txd), .rxd(rxd), .din(cmd_in), .din_en(cmd_en),
.dout(udout), .dout_en(udout_en), .of_err(of_err)
);
always @(posedge clk or posedge rst) begin
if (rst) begin
cmd[0] <= 9'h38;
cmd[1] <= 9'h0c;
cmd[2] <= 9'h01;
cmd[3] <= 9'h06;
cmd[4] <= 9'h80;
for(ci=5; ci<32; ci=ci+1) begin
cmd[ci] <= 0;
end
cmd_len <= 6'd5;
end // if (rst)
else begin
if (cmd_st) begin
for(ci=0; ci<31; ci=ci+1) begin
cmd[ci] <= cmd[ci+1];
end
if (cmd_en) begin
cmd[cmd_len-6'h1] <= cmd_in;
end
else begin
cmd_len <= cmd_len - 6'h1;
end
end
else if (cmd_len < 6'd32 & cmd_en==1) begin
cmd[cmd_len] <= cmd_in;
cmd_len <= cmd_len + 6'h1;
end
end // else: !if(rst)
end // always @ (posedge clk or posedge rst)
assign cmd_st = (cmd_len>0 & cmd_busy==0);
assign cmd_busy = lcd_status | lcd_wen;
assign cmd_in = {1'b1, d_o[7:0]};
assign cmd_en = (w_en & w_sel) ? 1'b1 : 1'b0;
assign w_wait = (w_sel & cmd_len >= 6'h32) ? 1'b1 : 1'b0;
always @(posedge clk or posedge rst) begin
if (rst) begin
lcd_wen <= 0;
lcd_wdt <= 0;
end
else begin
if (cmd_st) begin
lcd_wen <= 1;
lcd_wdt <= cmd[0];
end
else begin
lcd_wen <= 0;
end
end // else: !if(rst)
end // always @ (posedge clk or rst)
// program memory
drom32 drom_inst ( .address ( pc ), .clock ( clk ), .q ( op ) );
// data memory
dmem16 dmem_inst (.address ( dp ), .clock ( clk ), .data ( d_o ), .wren ( ram_w_en ), .q ( ram_d_i ));
assign ram_w_en = (w_sel==0) ? w_en : 1'b0;
assign ram_r_en = (r_sel==0) ? r_en : 1'b0;
assign d_en = (r_sel==0) ? ram_d_en : key_d_en;
assign d_i = (r_sel==0) ? ram_d_i : {8'h0, key_in};
assign s_rst = 0;
always @(posedge clk or posedge rst) begin
if (rst)
op_en <= 0;
else
op_en <= pc_r;
end
always @(posedge clk or posedge rst) begin
if (rst)
ram_d_en <= 0;
else
ram_d_en <= ram_r_en;
end
endmodule // brainfuck_top
|
`ifndef ALU_V
`define ALU_V
`define OP_NOP 2'h0
`define OP_ADD 2'h1
`define OP_SUB 2'h2
// Simple single cycle adder
module alu(
input clk,
input reset,
input [31:0] i_a, // 1st operand
input [31:0] i_b, // 2nd operand
input [1:0] i_cmd, // command
output [31:0] o_result,
output o_valid, // result is valid
output o_ready // ready to take input
);
reg [31:0] reg_result;
reg reg_valid = 1'b0;
// ALU state machine macros
`define ST_RESET 2'h0
`define ST_READY 2'h1
`define ST_BUSY 2'h2
// begin in reset state
reg [1:0] reg_status = `ST_RESET;
// Synchronous reset
always @(posedge clk && reset) begin
reg_status <= `ST_READY;
end
// Assign outputs
assign o_ready = ((reg_status == `ST_READY) && !reset);
assign o_valid = (reg_valid && (reg_status == `ST_READY));
assign o_result = o_valid ? reg_result : 32'hx; // Ternary operator
// Main processing loop
always @(posedge clk && !reset) begin
case (reg_status)
`ST_READY: begin
reg_status <= `ST_BUSY;
if (i_cmd == `OP_ADD) begin
reg_result = i_a + i_b;
end
// TODO: add OP_SUB
end
`ST_BUSY: begin
reg_valid <= 1'b1;
reg_status <= `ST_READY;
end
default: begin
$display("should not happen");
$finish;
end
endcase
end
endmodule
`endif
|
// Module m_ckt_jno is the circuit which handles the JNO or
// "jump if not overflow" instruction. When JNO is called, the
// status register is checked for an overflow of the program
// register. If the program register has not overflowed, the following
// two bits in w_bus_data (the two least-significant bits) will
// be stored into program counter (i.e., the program counter will
// "jump" to that address). If the program register has overflowed,
// the program counter will simply increment by 1, pointing to
// the next address in memory.
module m_ckt_jno (m_bus_pc_in, w_bus_addr, w_bus_data, w_jno, w_sr_out, w_low, w_high);
output [1:0] m_bus_pc_in;
input [1:0] w_bus_addr;
input [3:0] w_bus_data;
input w_jno, w_sr_out, w_low, w_high, w_clock, w_reset;
wire w_tmp_carry, w_tmp_sum0, w_tmp_sum1, w_demux_channel;
and (w_demux_channel, w_jno, ~w_sr_out); // logic for demux channel
m_two_bit_adder two_bit_add_0 (w_tmp_carry, w_tmp_sum1, w_tmp_sum0, w_low, w_high, w_bus_addr[1], w_bus_addr[0]); // hard wire adder to add 1 to pc
m_demux demux_0 (m_bus_pc_in[1], m_bus_pc_in[0], w_tmp_sum1, w_tmp_sum0, w_bus_data[1], w_bus_data[0], w_demux_channel);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; while (cin >> n >> k) { set<int> s; int l = 0, r = 0; int ans[200005]; int a; while (n--) { cin >> a; if (s.count(a)) { continue; } s.insert(a); ans[r++] = a; if (r > k) { s.erase(ans[l++]); } } n = min(r - l, k); cout << n << n ; while (n--) { cout << ans[--r] << ; } cout << n ; } } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 100000; const long long INFLL = 1e15; int N, Q; long long a[MAX_N + 1], b[MAX_N + 1]; long long S = 0; long long zero(long long x) { return (x > 0) ? x : -x; } struct SEG1 { struct NODE { int l, r; bool b; }; vector<NODE> seg; int SZ; void add() { seg.push_back({-1, -1, false}); } void Init(int x) { SZ = x; add(); init(0, 1, SZ); } void init(int idx, int s, int e) { if (s == e) return; seg[idx].l = seg.size(); add(); seg[idx].r = seg.size(); add(); init(seg[idx].l, s, (s + e) / 2); init(seg[idx].r, (s + e) / 2 + 1, e); } void Update(int x, bool y) { update(0, 1, SZ, x, y); } void update(int idx, int s, int e, int x, bool y) { if (s == e) { seg[idx].b = y; return; } if (x <= (s + e) / 2) { update(seg[idx].l, s, (s + e) / 2, x, y); } else { update(seg[idx].r, (s + e) / 2 + 1, e, x, y); } seg[idx].b = (seg[seg[idx].l].b | seg[seg[idx].r].b); } bool Ret(int x, int y) { return ret(0, 1, SZ, x, y); } bool ret(int idx, int s, int e, int x, int y) { if (x <= s && e <= y) { return seg[idx].b; } if (x > e || y < s) return false; return (ret(seg[idx].l, s, (s + e) / 2, x, y) | ret(seg[idx].r, (s + e) / 2 + 1, e, x, y)); } } Seg1; struct SEG2 { struct NODE { int l, r; long long mn; }; int SZ; vector<NODE> seg; void add() { seg.push_back({-1, -1, INFLL}); } void Init(int x) { SZ = x; add(); init(0, 1, SZ); } void init(int idx, int s, int e) { if (s == e) return; seg[idx].l = seg.size(); add(); seg[idx].r = seg.size(); add(); init(seg[idx].l, s, (s + e) / 2); init(seg[idx].r, (s + e) / 2 + 1, e); } void Update(int x, long long y) { update(0, 1, SZ, x, y); } void update(int idx, int s, int e, int x, long long y) { if (s == e) { seg[idx].mn = y; return; } if (x <= (s + e) / 2) { update(seg[idx].l, s, (s + e) / 2, x, y); } else { update(seg[idx].r, (s + e) / 2 + 1, e, x, y); } seg[idx].mn = min(seg[seg[idx].l].mn, seg[seg[idx].r].mn); } long long Mn(int x, int y) { return mn(0, 1, SZ, x, y); } long long mn(int idx, int s, int e, int x, int y) { if (x <= s && e <= y) return seg[idx].mn; if (x > e || y < s) return INFLL; return min(mn(seg[idx].l, s, (s + e) / 2, x, y), mn(seg[idx].r, (s + e) / 2 + 1, e, x, y)); } } Seg2; void make(int x) { if (b[x - 1] >= 0 && b[x] <= 0) { Seg2.Update(x, INFLL); Seg1.Update(x, true); return; } Seg1.Update(x, false); if (b[x - 1] < 0 && b[x] > 0) { Seg2.Update(x, 2LL * b[x] - 2LL * b[x - 1]); return; } if (b[x - 1] >= 0) { Seg2.Update(x, 2LL * b[x]); } else { Seg2.Update(x, -2LL * b[x - 1]); } } int main() { scanf( %d , &N); Seg1.Init(N); Seg2.Init(N); for (int i = 1; i <= N; i++) { scanf( %lld , &a[i]); if (i >= 2) { b[i - 1] = a[i] - a[i - 1]; S += zero(b[i - 1]); } } for (int i = 2; i < N; i++) { make(i); } scanf( %d , &Q); for (int i = 1; i <= Q; i++) { int t, l, r; long long x; scanf( %d%d%d%lld , &t, &l, &r, &x); if (t == 1) { if (l == r) { if (l == 1) { printf( %lld n , S - zero(b[1]) + zero(b[1] - x)); } else if (l == N) { printf( %lld n , S - zero(b[N - 1]) + zero(b[N - 1] + x)); } else { printf( %lld n , S - zero(b[l]) - zero(b[l - 1]) + zero(b[l] - x) + zero(b[l - 1] + x)); } } else if (Seg1.Ret(l, r)) { printf( %lld n , S + x * 2LL); } else { long long mx = 0LL; long long t = Seg2.Mn(l, r); mx = max(mx, 2LL * x - t); if (l == 1) { mx = max(mx, zero(b[1] - x) - zero(b[1])); } if (r == N) { mx = max(mx, zero(x + b[N - 1]) - zero(b[N - 1])); } printf( %lld n , S + mx); } } else { if (l != 1) { S -= zero(b[l - 1]); b[l - 1] += x; S += zero(b[l - 1]); make(l); if (l != 2) make(l - 1); } if (r != N) { S -= zero(b[r]); b[r] -= x; S += zero(b[r]); make(r); if (r != N - 1) make(r + 1); } } } } |
/*
-- ============================================================================
-- FILE NAME : mem_ctrl.v
-- DESCRIPTION : ¥á¥â¥ê¥¢¥¯¥»¥¹ÖÆÓù¥æ¥Ë¥Ã¥È
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "isa.h"
`include "cpu.h"
`include "bus.h"
/********** ¥â¥¸¥å©`¥ë **********/
module mem_ctrl (
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
input wire ex_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
input wire [`MemOpBus] ex_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`WordDataBus] ex_mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
input wire [`WordDataBus] ex_out, // IÀí½Y¹û
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output wire [`WordAddrBus] addr, // ¥¢¥É¥ì¥¹
output reg as_, // ¥¢¥É¥ì¥¹Óп
output reg rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û **********/
output reg [`WordDataBus] out , // ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û
output reg miss_align // ¥ß¥¹¥¢¥é¥¤¥ó
);
/********** ÄÚ²¿ÐźŠ**********/
wire [`ByteOffsetBus] offset; // ¥ª¥Õ¥»¥Ã¥È
/********** ³öÁ¦¤Î¥¢¥µ¥¤¥ó **********/
assign wr_data = ex_mem_wr_data; // ø¤Þz¤ß¥Ç©`¥¿
assign addr = ex_out[`WordAddrLoc]; // ¥¢¥É¥ì¥¹
assign offset = ex_out[`ByteOffsetLoc]; // ¥ª¥Õ¥»¥Ã¥È
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹¤ÎÖÆÓù **********/
always @(*) begin
/* ¥Ç¥Õ¥©¥ë¥È */
miss_align = `DISABLE;
out = `WORD_DATA_W'h0;
as_ = `DISABLE_;
rw = `READ;
/* ¥á¥â¥ê¥¢¥¯¥»¥¹ */
if (ex_en == `ENABLE) begin
case (ex_mem_op)
`MEM_OP_LDW : begin // ¥ï©`¥ÉÕi¤ß³ö¤·
/* ¥Ð¥¤¥È¥ª¥Õ¥»¥Ã¥È¤Î¥Á¥§¥Ã¥¯ */
if (offset == `BYTE_OFFSET_WORD) begin // ¥¢¥é¥¤¥ó
out = rd_data;
as_ = `ENABLE_;
end else begin // ¥ß¥¹¥¢¥é¥¤¥ó
miss_align = `ENABLE;
end
end
`MEM_OP_STW : begin // ¥ï©`¥Éø¤Þz¤ß
/* ¥Ð¥¤¥È¥ª¥Õ¥»¥Ã¥È¤Î¥Á¥§¥Ã¥¯ */
if (offset == `BYTE_OFFSET_WORD) begin // ¥¢¥é¥¤¥ó
rw = `WRITE;
as_ = `ENABLE_;
end else begin // ¥ß¥¹¥¢¥é¥¤¥ó
miss_align = `ENABLE;
end
end
default : begin // ¥á¥â¥ê¥¢¥¯¥»¥¹¤Ê¤·
out = ex_out;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_SYMBOL_V
`define SKY130_FD_SC_LS__DECAPHE_SYMBOL_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__decaphe ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void RI() {} template <typename... T> void RI(int &head, T &...tail) { scanf( %d , &head); RI(tail...); } struct Maxflow { struct E { int to, cap, rev, rcap, ucap; E() {} E(int _to, int _cap, int _rev) : to(_to), cap(_cap), rev(_rev), rcap(_cap) {} }; int n; vector<vector<E> > e; vector<vector<E>::iterator> cur; vector<int> dis; void init(int _n) { n = _n; e.resize(n); cur.resize(n); dis.resize(n); for (int i = 0; i < int(n); i++) e[i].clear(); } void add(int a, int b, int c) { if (a == b) return; e[a].push_back(E(b, c, e[b].size())); e[b].push_back(E(a, 0, e[a].size() - 1)); } bool bfs() { fill(dis.begin(), dis.end(), -1); queue<int> q; dis[0] = 0; q.push(0); while (!q.empty() && dis[n - 1] == -1) { int p = q.front(); q.pop(); for (auto it = (e[p]).begin(); it != (e[p]).end(); it++) { if (it->cap == 0 || dis[it->to] != -1) continue; dis[it->to] = dis[p] + 1; q.push(it->to); } } return dis[n - 1] != -1; } long long go(int p, long long c) { if (p == n - 1) return c; long long ret = 0; for (; cur[p] != e[p].end(); cur[p]++) { if (cur[p]->cap == 0 || dis[cur[p]->to] != dis[p] + 1) continue; long long now = go(cur[p]->to, min((long long)cur[p]->cap, c - ret)); ret += now; cur[p]->cap -= now; e[cur[p]->to][cur[p]->rev].cap += now; if (ret == c) break; } if (ret == 0) dis[p] = -1; return ret; } long long maxflow() { long long ret = 0; while (bfs()) { for (int i = 0; i < int(n); i++) cur[i] = e[i].begin(); ret += go(0, 1LL << 60); } return ret; } bool _addPath(int wh, vector<vector<int> > &ans) { if (wh == n - 1) { ans.push_back(vector<int>()); ans.back().push_back(wh); return true; } for (auto it = (e[wh]).begin(); it != (e[wh]).end(); it++) if (it->ucap > 0 && _addPath(it->to, ans)) { it->ucap--; ans.back().push_back(wh); return true; } return false; } vector<vector<int> > getPath() { vector<vector<int> > ans; for (auto it = (e).begin(); it != (e).end(); it++) for (auto jt = (*it).begin(); jt != (*it).end(); jt++) jt->ucap = max(0, jt->rcap - jt->cap); while (_addPath(0, ans)) reverse(ans.back().begin(), ans.back().end()); return ans; } } flow; bool pt[51400]; void predo() { for (int i = 2; i < 51400; i++) if (!pt[i]) for (int j = i + i; j < 51400; j += i) pt[j] = 1; } int n, a[210]; vector<int> e[210], sol; bool vis[210]; void dfs(int p) { sol.push_back(p); vis[p] = 1; for (auto it = (e[p]).begin(); it != (e[p]).end(); it++) if (!vis[*it]) { dfs(*it); break; } } int main() { predo(); RI(n); for (int i = (1); i <= int(n); i++) RI(a[i]); int sink = n + 1; flow.init(sink + 1); for (int i = (1); i <= int(n); i++) { if (a[i] % 2 == 0) flow.add(0, i, 2); else flow.add(i, sink, 2); } for (int i = (1); i <= int(n); i++) if (a[i] % 2 == 0) for (int j = (1); j <= int(n); j++) if (!pt[a[i] + a[j]]) flow.add(i, j, 1); int mf = flow.maxflow(); if (mf != n) { puts( Impossible ); return 0; } auto ps = flow.getPath(); for (auto it = (ps).begin(); it != (ps).end(); it++) { assert(((int)(*it).size()) == 4); int x = it->at(1); int y = it->at(2); e[x].push_back(y); e[y].push_back(x); } for (int i = (1); i <= int(n); i++) assert(((int)(e[i]).size()) == 2); vector<vector<int> > sols; for (int i = (1); i <= int(n); i++) if (!vis[i]) { sol.clear(); dfs(i); assert(((int)(sol).size()) % 2 == 0 && ((int)(sol).size()) >= 4); sols.push_back(sol); } printf( %d n , ((int)(sols).size())); for (auto &s : sols) { printf( %d , ((int)(s).size())); for (auto it = (s).begin(); it != (s).end(); it++) printf( %d , *it); puts( ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 400000 + 1000; struct node { int l, r, dir; long long w; } temp; vector<node> v; long long vis[N]; bool cmp(node a, node b) { if (a.l == b.l) return a.dir < b.dir; return a.l < b.l; } int main() { int n, x, i, l, w, r, time; long long ans; memset(vis, 0, sizeof(vis)); ans = 1e11; scanf( %d%d , &n, &x); for (i = 0; i < n; i++) { scanf( %d%d%d , &l, &r, &w); temp.w = w; temp.l = l; temp.r = r; temp.dir = -1; v.push_back(temp); temp.l = r; temp.r = l; temp.dir = 1; v.push_back(temp); } sort(v.begin(), v.end(), cmp); for (i = 0; i < v.size(); i++) { time = abs(v[i].r - v[i].l) + 1; if (time >= x) continue; if (v[i].dir == -1) { if (vis[x - time] != 0) ans = min(ans, vis[x - time] + v[i].w); } else { if (!vis[time]) vis[time] = v[i].w; else vis[time] = min(vis[time], v[i].w); } } if (ans == 1e11) printf( -1 n ); else printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 5; const int MOD = 1e9 + 7; inline int read() { int s = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { s = (s << 1) + (s << 3) + ch - 0 ; ch = getchar(); } return s * f; } inline void write(long long x) { if (x < 0) x = -x, putchar( - ); if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } int a[maxn]; int main() { int T = read(), n, m, k; while (T--) { n = read(), k = read(); for (int i = 1; i <= n; i++) a[i] = read(); sort(a + 1, a + n + 1); int ans = 0; for (int i = 2; i <= n; i++) { if (a[1] + a[i] > k) continue; ans += (k - a[i]) / a[1]; } write(ans); putchar( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); int ans = -1; int sum = 7; int i = 1; while (sum <= n) { int y = n - sum; if (y % 4 == 0) ans = i; sum += 7; i++; } if (ans != -1) { int s = 7 * ans; int y = n - s; int x = y / 4; while (x--) { cout << 4 ; } while (ans--) { cout << 7 ; } return 0; } if (n % 7 == 0) { int x = n / 7; while (x--) cout << 7 ; return 0; } if (n % 4 == 0) { int x = n / 4; while (x--) cout << 4 ; return 0; } cout << -1 ; return 0; } |
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 100ps/100ps
module SerialTransmitterTest;
reg clk;
reg rst_x;
reg [7:0] r_data;
reg r_valid;
wire w_error;
wire w_busy;
wire w_tx2rx;
wire [7:0] w_data;
wire w_valid;
wire w_nostop;
always #4 clk = ~clk;
always @ (posedge w_valid) begin
$display("receive: $%02x", w_data);
end
always @ (posedge w_nostop) begin
$display("receive: can not detect stop bit");
end
always @ (posedge w_error) begin
$display("transmit: unexpected request on a busy cycle");
end
SerialTransmitter dut(
.clk_x4 (clk ),
.rst_x (rst_x ),
.i_data (r_data ),
.i_valid(r_valid ),
.o_tx (w_tx2rx ),
.o_busy (w_busy ),
.o_error(w_error ));
SerialReceiver rx(
.clk_x4 (clk ),
.rst_x (rst_x ),
.i_rx (w_tx2rx ),
.o_data (w_data ),
.o_valid(w_valid ),
.o_error(w_nostop));
initial begin
$dumpfile("SerialTransmitter.vcd");
$dumpvars(0, dut);
clk <= 1'b0;
rst_x <= 1'b1;
r_valid <= 1'b0;
#32
rst_x <= 1'b0;
#32
rst_x <= 1'b1;
#20
// Transmit a data.
r_data <= 8'hde;
r_valid <= 1'b1;
#8
r_valid <= 1'b0;
#312
// Transmit another data immediately.
r_data <= 8'had;
r_valid <= 1'b1;
#8
r_valid <= 1'b0;
#308
// Error due to request on busy cycle.
r_valid <= 1'b1;
#4
$finish;
end
endmodule // SerialTransmitterTest
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32O_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A32O_PP_BLACKBOX_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a32o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32O_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2A_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O2BB2A_PP_SYMBOL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2A_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { long long int t, i, j, cnt, k, lo, hi, mid; cin >> t; while (t--) { string s, t; cin >> s >> t; vector<long long int> v[26]; for (i = 0; s[i]; i++) { v[s[i] - a ].push_back(i); } bool flag = true; cnt = 1; j = -1; for (i = 0; t[i]; i++) { k = -1; lo = 0; hi = (int)v[t[i] - a ].size() - 1; while (lo <= hi) { mid = (lo + hi) / 2LL; if (v[t[i] - a ][mid] > j) { k = v[t[i] - a ][mid]; hi = mid - 1; } else { lo = mid + 1; } } if (j == -1 and k == -1) { flag = false; break; } else if (k != -1) { j = k; } else { j = -1; i--; cnt++; } } if (!flag) cnt = -1; cout << cnt << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct nade { int pos, tag, sum, l, r; } tree[600005 * 2]; int n; void puup(int x) { if (tree[x * 2].sum > tree[x * 2 + 1].sum) { tree[x].pos = tree[x * 2].pos; tree[x].sum = tree[x * 2].sum; } else { tree[x].pos = tree[x * 2 + 1].pos; tree[x].sum = tree[x * 2 + 1].sum; } } void pudo(int x) { tree[x * 2].tag += tree[x].tag; tree[x * 2].sum += tree[x].tag; tree[x * 2 + 1].tag += tree[x].tag; tree[x * 2 + 1].sum += tree[x].tag; tree[x].tag = 0; } void build(int x, int l, int r) { tree[x].l = l; tree[x].r = r; if (l == r) { tree[x].pos = l; return; } int mid = (l + r) / 2; build(x * 2, l, mid); build(x * 2 + 1, mid + 1, r); tree[x].pos = tree[x * 2].pos; } void add(int l, int r, int val, int x) { if (tree[x].l >= l && tree[x].r <= r) { tree[x].sum += val; tree[x].tag += val; return; } pudo(x); if (tree[x * 2].r >= l) add(l, r, val, x * 2); if (tree[x * 2 + 1].l <= r) add(l, r, val, x * 2 + 1); puup(x); } int l[200005], r[200005], v[200005]; struct node { int x, u, d; bool b; } s[200005]; bool cmp(node a, node b) { if (a.x != b.x) return a.x < b.x; return a.b < b.b; } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d%d%d , &l[i], &v[i], &r[i]); s[i * 2].x = l[i]; s[i * 2].u = r[i]; s[i * 2].d = v[i]; s[i * 2].b = 0; s[i * 2 + 1].x = v[i]; s[i * 2 + 1].u = r[i]; s[i * 2 + 1].d = v[i]; s[i * 2 + 1].b = 1; } build(1, 1, 3e5 + 1); sort(s, s + 2 * n, cmp); int ans = 0, ansp = 0, ansx = 0; for (int i = 0; i < n * 2; i++) { add(s[i].d, s[i].u, s[i].b ? -1 : 1, 1); if (tree[1].sum > ans) { ans = tree[1].sum; ansp = tree[1].pos; ansx = s[i].x; } } printf( %d n , ans); for (int i = 0; i < n; i++) if (l[i] <= ansx && ansx <= v[i] && v[i] <= ansp && ansp <= r[i]) printf( %d , i + 1); } |
#include <bits/stdc++.h> using namespace std; bool isvowel(char c) { return c == a || c == e || c == i || c == o || c == u ; } int main() { char arr[110]; scanf( %s , arr); int len = strlen(arr); bool check = true; for (int i = 0; i < len; i++) { if (isvowel(arr[i])) { } else if (arr[i] == n ) { } else { if (i == len - 1 || !isvowel(arr[i + 1])) check = false; } } puts(check ? YES : NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void read(T &x) { x = 0; register char c = getchar(); bool f = 0; while (c != - && (c < 0 || c > 9 )) c = getchar(); if (c == - ) c = getchar(), f = 1; while (c >= 0 && c <= 9 ) x = x * 10 + c - 48, c = getchar(); x = f ? -x : x; return; } template <class T> inline void write(T x) { if (!x) { putchar(48); return; } if (x < 0) x = -x, putchar( - ); int len = -1, z[20]; while (x > 0) z[++len] = x % 10, x /= 10; for (register int i = len; i >= 0; i--) putchar(z[i] + 48); return; } const int N = 10010; struct node { int to, nxt, w; } g[N * 10]; int lst[N], gl; void add(int x, int y, int z) { g[++gl] = (node){y, lst[x], z}; lst[x] = gl; } vector<pair<int, int> > E[N]; vector<int> E2[N]; bool vis1[N], visn[N]; void dfs(int x) { vis1[x] = 1; for (int i = 0; i < E[x].size(); i++) { int v = E[x][i].first; if (!vis1[v]) dfs(v); } } void dfs2(int x) { visn[x] = 1; for (int i = 0; i < E2[x].size(); i++) { int v = E2[x][i]; if (!visn[v]) dfs2(v); } } int cnt[N], dis[N], n, m; queue<int> q; bool vis[N]; bool spfa() { q.push(1); memset(dis, 127 / 3, sizeof(dis)); dis[1] = 0; while (!q.empty()) { int u = q.front(); q.pop(); vis[u] = 0; for (int i = lst[u]; i; i = g[i].nxt) { int v = g[i].to; if (dis[v] > dis[u] + g[i].w) { dis[v] = dis[u] + g[i].w; if ((++cnt[v]) == n) return 0; if (!vis[v]) { vis[v] = 1; q.push(v); } } } } return 1; } int ans[N]; int main() { read(n), read(m); for (int i = 1, x, y; i <= m; i++) { read(x), read(y); E[x].push_back(make_pair(y, i)); E2[y].push_back(x); } dfs(1); dfs2(n); for (int u = 1; u <= n; u++) for (auto v : E[u]) if (vis1[u] && visn[v.first]) { add(v.first, u, 2); add(u, v.first, -1); } if (!spfa()) puts( No ); else { puts( Yes ); int flg = 0; for (int u = 1; u <= n; u++) for (auto v : E[u]) if (vis1[u] && visn[v.first]) ans[v.second] = dis[u] - dis[v.first]; else ans[v.second] = 1; for (int i = 1; i <= m; i++) printf( %d n , ans[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, mod, s, s1, s2; inline long long get(long long id, long long rem, long long l, long long r, long long b, long long e, long long x) { if (e < l || r < b) { return 0; } if (b <= l && r <= e) { if (x < rem) { return 0; } s = (x - rem) / (1LL << id); s1 = s; s2 = s + 1; if (s % 2 == 0) { s1 /= 2; } else { s2 /= 2; } return (((s + 1) % mod) * (rem % mod) % mod + ((1LL << id) % mod) * (s1 % mod) % mod * (s2 % mod) % mod) % mod; } long long lrem = rem, rrem = rem + (1LL << id); if (rem == 0) { rrem = 0; lrem = (1LL << id); } return (get(id + 1, lrem, l, (l + r) / 2, b, e, x) + get(id + 1, rrem, (l + r) / 2 + 1, r, b, e, x)) % mod; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long m, l, r, u, v; cin >> n >> m >> mod; while (m--) { cin >> l >> r >> u >> v; cout << (get(0, 0, 1, n, l, r, min(n, v)) - get(0, 0, 1, n, l, r, min(n + 1, u) - 1) + mod) % mod << endl; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRTN_1_V
`define SKY130_FD_SC_LS__DFRTN_1_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog wrapper for dfrtn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfrtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfrtn_1 (
Q ,
CLK_N ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfrtn_1 (
Q ,
CLK_N ,
D ,
RESET_B
);
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfrtn base (
.Q(Q),
.CLK_N(CLK_N),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRTN_1_V
|
/*
Distributed under the MIT license.
Copyright (c) 2016 Dave McCoy ()
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description: AXI Master
*
* Changes:
* 10/2/2016: Initial Commit
*/
`timescale 1 ns/1 ps
`include "axi_defines.v"
`define BIT_STATUS_BUSY 0
`define BIT_STATUS_BAD_COMMAND 4
`define BIT_STATUS_BAD_TXRX_WIDTH 5
`define BIT_BUS_STATUS_RANGE 9:8
module axi_lite_master #(
//Parameters
parameter INVERT_AXI_RESET = 1,
parameter ADDR_WIDTH = 32,
parameter INTERRUPT_WIDTH = 32,
parameter DEFAULT_TIMEOUT = 32'd100000000 //1 Second at 100MHz
)(
//************* User Facing Side *******************************************
//User Facing Interface end
//indicate to the input that we are ready
output [31:0] o_cmd_status,
output reg o_cmd_interrupt,
input i_cmd_en,
output reg o_cmd_error,
output reg o_cmd_ack,
//Modifier flags, these will be used to change the way address are modified when reading/writing
input [ADDR_WIDTH - 1:0] i_cmd_addr,
input i_cmd_wr_rd, //1 = Write, 0 = Read
input [3:0] i_cmd_byte_en,
input [31:0] i_cmd_data,
output reg [31:0] o_cmd_data,
//***************** AXI Bus ************************************************
input clk,
input rst,
//bus write addr path
output [3:0] o_awid, //Write ID
output [ADDR_WIDTH - 1:0] o_awaddr, //Write Addr Path Address
output [2:0] o_awsize, //Write Addr Path Burst Size (Byte with (00 = 8 bits wide, 01 = 16 bits wide)
output reg o_awvalid, //Write Addr Path Address Valid
input i_awready, //Write Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus write data
output [3:0] o_wid, //Write ID
output reg [31:0] o_wdata, //Write Data (this size is set with the 32 Parameter
//Valid values are: 8, 16, 32, 64, 128, 256, 512, 1024
output reg [3:0] o_wstrobe, //Write Strobe (a 1 in the write is associated with the byte to write)
output o_wlast, //Write Last transfer in a write burst
output reg o_wvalid, //Data through this bus is valid
input i_wready, //Slave is ready for data
//Write Response Channel
input [3:0] i_bid, //Response ID (this must match awid)
input [1:0] i_bresp, //Write Response
// 0 = OKAY
// 1 = EXOKAY
// 2 = SLVERR
// 3 = DECERR
input i_bvalid, //Write Response is:
// 1 = Available
// 0 = Not Available
output reg o_bready, //WBM Ready
//bus read addr path
output [3:0] o_arid, //Read ID
output [ADDR_WIDTH - 1:0] o_araddr, //Read Addr Path Address
output reg [7:0] o_arlen, //Read Addr Path Burst Length
output [2:0] o_arsize, //Read Addr Path Burst Size (Byte with (00 = 8 bits wide, 01 = 16 bits wide)
output reg o_arvalid, //Read Addr Path Address Valid
input i_arready, //Read Addr Path Slave Ready
// 1 = Slave Ready
// 0 = Slave Not Ready
//bus read data
input [3:0] i_rid, //Write ID
input [31: 0] i_rdata, //Read Data (this size is set with the 32 Parameter)
input [1:0] i_rresp, //Read Response
// 0 = OKAY
// 1 = EXOKAY
// 2 = SLVERR
// 3 = DECERR
input [3:0] i_rstrobe, //Read Strobe (a 1 in the write is associated with the byte to write)
input i_rlast, //Read Last transfer in a write burst
input i_rvalid, //Data through this bus is valid
output reg o_rready, //WBM is ready for data
// 1 = WBM Ready
// 0 = Slave Ready
input [INTERRUPT_WIDTH - 1:0] i_interrupts
);
//local parameters
//States
localparam IDLE = 4'h0;
localparam WRITE_CMD = 4'h1; //Write Command and Address to Slave
localparam WRITE_DATA = 4'h2; //Write Data to Slave
localparam WRITE_RESP = 4'h3; //Receive Response from device
localparam READ_CMD = 4'h4; //Send Read Command and Address to Slave
localparam READ_DATA = 4'h5; //Receive Read Response from Slave (including data)
localparam READ_RESP = 4'h6;
localparam COMMAND_FINISHED = 4'h7;
localparam SEND_RESPONSE = 4'h8;
localparam SEND_INTERRUPT = 5'h9;
//registes/wires
reg [3:0] state = IDLE;
wire [15:0] w_flags;
wire [31:0] w_data_size;
reg [ADDR_WIDTH - 1:0] r_address;
reg [31:0] r_output_data;
wire [31:0] w_status;
reg [31:0] r_data_count; //Techinically this should go all the way up to DATA_COUNT - 1: 0
reg [31:0] r_interrupts;
wire w_writing_data;
reg [1:0] r_bus_status;
wire w_rst;
reg [INTERRUPT_WIDTH - 1:0] r_prev_int;
reg r_bad_command = 0;
reg r_bad_txrx_width;
reg [31:0] r_nack_timeout;
//Some Features are not supported at this time
assign o_cmd_status[`BIT_STATUS_BUSY] = (state != IDLE);
assign o_cmd_status[3:1] = 0;
assign o_cmd_status[`BIT_STATUS_BAD_COMMAND] = r_bad_command;
assign o_cmd_status[`BIT_STATUS_BAD_TXRX_WIDTH] = r_bad_txrx_width;
assign o_cmd_status[7:6] = 0;
assign o_cmd_status[`BIT_BUS_STATUS_RANGE] = r_bus_status;
assign o_cmd_status[9:8] = 0;
assign o_cmd_status[31:6] = 0;
assign o_awsize = `AXI_BURST_SIZE_32BIT;
assign o_arsize = `AXI_BURST_SIZE_32BIT;
//Submodules
//asynchronous logic
assign w_rst = (INVERT_AXI_RESET) ? ~rst : rst;
assign o_awaddr = r_address;
assign o_araddr = r_address;
assign o_wlast = 1'b1;
assign o_arid = 4'h0;
assign o_awid = 4'h0;
assign o_wid = 4'h0;
//synchronous logic
always @ (posedge clk) begin
//De-assert Strobes
//AXI Strobes
o_awvalid <= 0;
o_bready <= 0;
o_arvalid <= 0;
if (w_rst) begin
o_cmd_error <= 0;
r_output_data <= 0;
r_bad_command <= 0;
r_bad_txrx_width <= 0;
r_address <= 0;
r_data_count <= 32'h0;
r_nack_timeout <= DEFAULT_TIMEOUT;
r_prev_int <= 0;
//AXI
//Write Address Path
//Write Data Path
//Read Address Path
o_arlen <= 0;
r_bus_status <= 0;
o_cmd_ack <= 0;
o_cmd_interrupt <= 0;
o_wstrobe <= 0;
o_cmd_data <= 0;
o_wvalid <= 0;
o_rready <= 0;
o_wdata <= 0;
end
else begin
case (state)
IDLE: begin
r_bad_command <= 0;
r_bad_txrx_width <= 0;
o_rready <= 0;
o_wvalid <= 0;
r_address <= 32'h0;
r_data_count <= 32'h0;
o_wdata <= i_cmd_data;
o_wstrobe <= i_cmd_byte_en;
//Strobe in a command
if (i_cmd_en) begin
o_arlen <= 1;
r_bus_status <= 0;
//Something new from host
r_data_count <= 0;
r_address <= i_cmd_addr;
if (i_cmd_wr_rd) begin
//Write Path
state <= WRITE_CMD;
end
else begin
//Read Path
state <= READ_CMD;
end
end
else if (((!r_prev_int) & i_interrupts) > 0) begin
//Something new from interrupts
state <= SEND_INTERRUPT;
r_interrupts <= 0;
end
end
//Write Path
WRITE_CMD: begin
//Wait for the slave to acknowledge my request to write data to the specified address
o_awvalid <= 1;
if (i_awready && o_awvalid) begin
o_awvalid <= 0;
state <= WRITE_DATA;
end
end
WRITE_DATA: begin
o_wvalid <= 1;
if (i_wready && o_wvalid) begin
o_wvalid <= 0;
state <= WRITE_RESP;
end
end
WRITE_RESP: begin
o_bready <= 1;
if (i_bvalid)begin
//Incomming ID matches the one we sent out
r_bus_status <= i_bresp;
if (r_bus_status != 0) begin
o_cmd_error <= 1;
end
state <= COMMAND_FINISHED;
end
end
//Read Path
READ_CMD: begin
o_arvalid <= 1;
if (i_arready && o_arvalid) begin
o_arvalid <= 0;
state <= READ_DATA;
end
end
READ_DATA: begin
o_rready <= 1;
if (i_rvalid && o_rready) begin
o_rready <= 0;
o_cmd_data <= i_rdata;
r_bus_status <= i_rresp;
state <= COMMAND_FINISHED;
end
end
COMMAND_FINISHED: begin
o_cmd_ack <= 1;
if (!i_cmd_en && o_cmd_ack) begin
state <= IDLE;
end
end
SEND_INTERRUPT: begin
end
default: begin
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int from, to, next, w, dir, id; } e[1500000]; int head[350000]; int in[350000]; int out[350000]; int ans[350000]; int n, m, cont; void add(int from, int to, int w, int dir, int id) { e[cont].from = from; e[cont].to = to; e[cont].w = w; e[cont].dir = dir; e[cont].id = id; e[cont].next = head[from]; head[from] = cont++; } void Top() { queue<int> s; s.push(1); in[1] = out[1] = 0; while (!s.empty()) { int u = s.front(); s.pop(); for (int i = head[u]; i != -1; i = e[i].next) { int v = e[i].to; int w = e[i].w; int dir = e[i].dir; if (v == 1 || (in[v] == out[v] && v != n)) continue; if (u == 1 || v == n) { if (u == 1) { ans[e[i].id] = dir; in[v] += w; } else { ans[e[i].id] = dir; } } else { if (in[v] != out[v]) { in[v] += w; ans[e[i].id] = dir; } else ans[e[i].id] = 1 - dir; } if (in[v] == out[v] && v != n) { s.push(v); } } } for (int i = 1; i <= m; i++) printf( %d n , ans[i]); } int main() { while (~scanf( %d%d , &n, &m)) { cont = 0; memset(in, 0, sizeof(in)); memset(out, 0, sizeof(out)); memset(head, -1, sizeof(head)); for (int i = 1; i <= m; i++) { int x, y, w; scanf( %d%d%d , &x, &y, &w); add(x, y, w, 0, i); add(y, x, w, 1, i); out[y] += w; out[x] += w; } for (int i = 1; i <= n; i++) out[i] = out[i] / 2; Top(); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXTP_1_V
`define SKY130_FD_SC_LS__DFXTP_1_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog wrapper for dfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfxtp_1 (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfxtp_1 (
Q ,
CLK,
D
);
output Q ;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfxtp base (
.Q(Q),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXTP_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4_TB_V
`define SKY130_FD_SC_MS__NOR4_TB_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor4.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A = 1'b1;
#200 B = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A = 1'b0;
#360 B = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B = 1'b1;
#640 A = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B = 1'bx;
#800 A = 1'bx;
end
sky130_fd_sc_ms__nor4 dut (.A(A), .B(B), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31A_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O31A_PP_BLACKBOX_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31A_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221O_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A221O_PP_SYMBOL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a221o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221O_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; set<pair<long long, long long> > s[17]; long long a[100002]; long long g[100002]; signed main() { ios ::sync_with_stdio(0), cin.tie(0), cout.tie(0); long long n, m; cin >> n >> m; for (long long i = 0; i <= n; i++) g[i] = (i * (i + 1)) / 2LL; long long ans = 0; for (long long i = 0; i <= n - 1; i++) cin >> a[i]; for (long long j = 0; j <= 16; j++) { for (long long i = 0; i <= n - 1; i++) { if (a[i] & (1LL << j)) { long long len = 1; long long st = i; i++; while (1) { if (i == n or !(a[i] & (1LL << j))) { s[j].insert({st, len}); ans += (g[len] * (1LL << j)); break; } len++; i++; } } } } while (m--) { long long idx, val, pval; cin >> idx >> val; idx--; pval = a[idx]; for (long long j = 0; j <= 16; j++) { if (val & (1LL << j) and !(pval & (1LL << j))) { auto it = s[j].lower_bound({idx, 1e9}); if (it == s[j].end() or (*it).first != idx + 1) s[j].insert({idx, 1}), ans += (1LL << j); else ans += (1LL << j) * ((*it).second + 1), s[j].insert({idx, (*it).second + 1}), s[j].erase(it); it = s[j].lower_bound({idx, -1}); if (it != s[j].begin()) { auto pt = prev(it); if ((*pt).second + (*pt).first - 1 == idx - 1) { ans -= (1LL << j) * (g[(*pt).second] + g[(*it).second]), ans += (1LL << j) * g[(*it).second + (*pt).second], s[j].insert({(*pt).first, (*pt).second + (*it).second}), s[j].erase(it), s[j].erase(pt); } } } else if (pval & (1LL << j) and !(val & (1LL << j))) { auto it = s[j].lower_bound({idx, -1}); if (it != s[j].end() and (*it).first == idx) { if ((*it).second == 1) ans -= (1LL << j), s[j].erase({idx, 1}); else ans -= (1LL << j) * ((*it).second), s[j].insert({idx + 1, (*it).second - 1}), s[j].erase(it); } else { it = prev(it); if ((*it).first + (*it).second - 1 == idx) ans -= (1LL << j) * ((*it).second), s[j].insert({(*it).first, (*it).second - 1}), s[j].erase(it); else { ans -= (1LL << j) * g[(*it).second], ans += (1LL << j) * g[idx - 1 - (*it).first + 1], ans += (1LL << j) * g[(*it).first + (*it).second - 1 - idx - 1 + 1]; s[j].insert({(*it).first, idx - 1 - (*it).first + 1}), s[j].insert( {idx + 1, (*it).first + (*it).second - 1 - idx - 1 + 1}), s[j].erase(it); } } } } a[idx] = val; cout << ans << n ; } } |
#include <bits/stdc++.h> int main() { int N, L, i, count = 0, vivos = 0; int vet[1000000]; scanf( %d , &N); for (i = N - 1; i >= 0; i--) { scanf( %d , &vet[i]); } for (i = 0; i < N; i++) { if (count == 0) { count = vet[i]; vivos++; } else { count--; if (vet[i] > count) { count = vet[i]; } if (count == 0) { count = vet[i]; } } } printf( %d n , vivos); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 2e9; const long long INFL = 1e18; const int N = 3e5; int n, m, R; vector<int> adj[N + 5]; pair<int, int> E[2 * N + 5]; long long d[N + 5]; struct cmp { bool operator()(pair<int, long long> x, pair<int, long long> y) { return (x.second > y.second); } }; priority_queue<pair<int, long long>, vector<pair<int, long long> >, cmp> H; int tr[N + 5]; void Dijkstra() { for (int i = (1), _b = (n); i <= _b; ++i) d[i] = INFL; d[R] = 0; H.push(make_pair(R, d[R])); while (!H.empty()) { int u = H.top().first; long long oldDist = H.top().second; H.pop(); if (oldDist != d[u]) continue; for (int i = (0), _b = (((int)(adj[u]).size())); i < _b; ++i) { int v = E[adj[u][i]].first, w = E[adj[u][i]].second; if (d[u] + w < d[v] || d[u] + w == d[v] && E[adj[u][i]].second < E[tr[v]].second) { d[v] = d[u] + w; H.push(make_pair(v, d[v])); tr[v] = adj[u][i]; } } } } vector<int> pth; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> n >> m; int cntE = 0; while (m--) { int u, v, w; cin >> u >> v >> w; E[++cntE] = make_pair(v, w); adj[u].push_back(cntE); E[++cntE] = make_pair(u, w); adj[v].push_back(cntE); } cin >> R; Dijkstra(); long long res = 0; for (int i = (1), _b = (n); i <= _b; ++i) if (i != R) { res += E[tr[i]].second; pth.push_back(tr[i]); } cout << res << n ; for (int i = (0), _b = (((int)(pth).size())); i < _b; ++i) cout << (pth[i] + 1) / 2 << ; cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int inf = 0x3f3f3f3f; const int N = 1e6 + 10; const int mod = 998244353; int m, n, k = 0, flag = 0, cnt = 0; int a[N], ans[N]; long long pow2[N]; bool did[N]; int main() { ios::sync_with_stdio(false); cin >> n >> k; ; for (int i = 0; i < n; i++) { cin >> a[i]; if (a[i] <= k && !flag) { cnt++; did[i] = 1; } if (a[i] > k) flag = 1; } flag = 0; for (int i = n - 1; i >= 0; i--) { if (a[i] <= k && !flag && !did[i]) cnt++; if (a[i] > k) flag = 1; } cout << cnt << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2B_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__NOR2B_PP_BLACKBOX_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2B_PP_BLACKBOX_V
|
//-----------------------------------------------------------------
//
// Filename : synth_reg.v
//
// Date : 4/19/2005
//
// Description : Verilog description of SRL16E based delay and
// retiming register module.
// This code is synthesizable.
//
//
// Mod. History : Translated VHDL code to Verilog
// : Fixed synth_reg_reg
//
// Mod. Dates : 6/29/2004
// : 12/14/2004
//
//-------------------------------------------------------------------
`timescale 1 ns / 10 ps
module srl17e (clk, ce, d, q);
parameter width = 16;
parameter latency = 8;
input clk, ce;
input [width-1:0] d;
output [width-1:0] q;
parameter signed [5:0] a = latency - 2;
wire[width - 1:0] #0.2 d_delayed;
wire[width - 1:0] srl16_out;
genvar i;
assign d_delayed = d ;
generate
for(i=0; i<width; i=i+1)
begin:reg_array
if (latency > 1)
begin: has_2_latency
SRL16E u1 (.CLK(clk), .D(d_delayed[i]), .Q(srl16_out[i]), .CE(ce), .A0(a[0]), .A1(a[1]), .A2(a[2]), .A3(a[3]));
end
if (latency <= 1)
begin: has_1_latency
assign srl16_out[i] = d_delayed[i];
end
if (latency != 0)
begin: has_latency
FDE u2 (.C(clk), .D(srl16_out[i]), .Q(q[i]), .CE(ce));
end
if (latency == 0)
begin:has_0_latency
assign q[i] = srl16_out[i];
end
end
endgenerate
endmodule
module synth_reg (i, ce, clr, clk, o);
parameter width = 8;
parameter latency = 1;
input[width - 1:0] i;
input ce,clr,clk;
output[width - 1:0] o;
parameter complete_num_srl17es = latency/17;
parameter remaining_latency = latency%17;
parameter temp_num_srl17es = (latency/17) + ((latency%17)?1:0);
parameter num_srl17es = temp_num_srl17es ? temp_num_srl17es : 1;
wire [width - 1:0] z [0:num_srl17es-1];
genvar t;
generate
if (latency <= 17)
begin:has_only_1
srl17e #(width, latency) srl17e_array0(.clk(clk), .ce(ce), .d(i), .q(o));
end
endgenerate
generate
if (latency > 17)
begin:has_1
assign o = z[num_srl17es-1];
srl17e #(width, 17) srl17e_array0(.clk(clk), .ce(ce), .d(i), .q(z[0]));
end
endgenerate
generate
if (latency > 17)
begin:more_than_1
for (t=1; t < complete_num_srl17es; t=t+1)
begin:left_complete_ones
srl17e #(width, 17) srl17e_array(.clk(clk), .ce(ce), .d(z[t-1]), .q(z[t]));
end
end
endgenerate
generate
if ((remaining_latency > 0) && (latency>17))
begin:remaining_ones
srl17e #(width, (latency%17)) last_srl17e (.clk(clk), .ce(ce), .d(z[num_srl17es-2]), .q(z[num_srl17es-1]));
end
endgenerate
endmodule
module synth_reg_reg (i, ce, clr, clk, o);
parameter width = 8;
parameter latency = 1;
input[width - 1:0] i;
input ce, clr, clk;
output[width - 1:0] o;
wire[width - 1:0] o;
genvar idx;
reg[width - 1:0] reg_bank [latency:0];
integer j;
initial
begin
for (j=0; j < latency+1; j=j+1)
begin
reg_bank[j] = {width{1'b0}};
end
end
generate
if (latency == 0)
begin:has_0_latency
assign o = i;
end
endgenerate
always @(i)
begin
reg_bank[0] = i;
end
generate
if (latency > 0)
begin:more_than_1
assign o = reg_bank[latency];
for (idx=0; idx < latency; idx=idx+1) begin:sync_loop
always @(posedge clk)
begin
if(clr)
begin
//for (j=0; j < latency+1; j=j+1)
// begin
reg_bank[idx+1] = {width{1'b0}};
// end
end
else if (ce)
begin
reg_bank[idx+1] <= reg_bank[idx] ;
end
end
end
end
endgenerate
endmodule
|
(** * ImpCEvalFun: Evaluation Function for Imp *)
(* $Date: 2013-07-01 18:48:47 -0400 (Mon, 01 Jul 2013) $ *)
(* #################################### *)
(** ** Evaluation Function *)
Require Import Imp.
(** Here's a first try at an evaluation function for commands,
omitting [WHILE]. *)
Fixpoint ceval_step1 (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step1 st c1 in
ceval_step1 st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step1 st c1
else ceval_step1 st c2
| WHILE b1 DO c1 END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the WHILE case as follows:
<<
| WHILE b1 DO c1 END =>
if (beval st b1)
then ceval_step1 st (c1;; WHILE b1 DO c1 END)
else st
>>
Coq doesn't accept such a definition ([Error: Cannot guess
decreasing argument of fix]) because the function we want to
define is not guaranteed to terminate. Indeed, the changed
[ceval_step1] function applied to the [loop] program from [Imp.v] would
never terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is an
invalid(!) Coq program showing what would go wrong if Coq allowed
non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become
provable (e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_step1] cannot be written in Coq -- at least not
without one additional trick... *)
(** Second try, using an extra numeric argument as a "step index" to
ensure that evaluation always terminates. *)
Fixpoint ceval_step2 (st : state) (c : com) (i : nat) : state :=
match i with
| O => empty_state
| S i' =>
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step2 st c1 i' in
ceval_step2 st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step2 st c1 i'
else ceval_step2 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then let st' := ceval_step2 st c1 i' in
ceval_step2 st' c i'
else st
end
end.
(** _Note_: It is tempting to think that the index [i] here is
counting the "number of steps of evaluation." But if you look
closely you'll see that this is not the case: for example, in the
rule for sequencing, the same [i] is passed to both recursive
calls. Understanding the exact way that [i] is treated will be
important in the proof of [ceval__ceval_step], which is given as
an exercise below. *)
(** Third try, returning an [option state] instead of just a [state]
so that we can distinguish between normal and abnormal
termination. *)
Fixpoint ceval_step3 (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c2 i'
| None => None
end
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step3 st c1 i'
else ceval_step3 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c i'
| None => None
end
else Some st
end
end.
(** We can improve the readability of this definition by introducing a
bit of auxiliary notation to hide the "plumbing" involved in
repeatedly matching against optional states. *)
Notation "'LETOPT' x <== e1 'IN' e2"
:= (match e1 with
| Some x => e2
| None => None
end)
(right associativity, at level 60).
Fixpoint ceval_step (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step st c1 i'
else ceval_step st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c i'
else Some st
end
end.
Definition test_ceval (st:state) (c:com) :=
match ceval_step st c 500 with
| None => None
| Some st => Some (st X, st Y, st Z)
end.
(* Eval compute in
(test_ceval empty_state
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)).
====>
Some (2, 0, 4) *)
(** **** Exercise: 2 stars (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y]. Make sure
your solution satisfies the test that follows. *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
(*
Example pup_to_n_1 :
test_ceval (update empty_state X 5) pup_to_n
= Some (0, 15, 0).
Proof. reflexivity. Qed.
*)
(** [] *)
(** **** Exercise: 2 stars, optional (peven) *)
(** Write a [While] program that sets [Z] to [0] if [X] is even and
sets [Z] to [1] otherwise. Use [ceval_test] to test your
program. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################ *)
(** ** Equivalence of Relational and Step-Indexed Evaluation *)
(** As with arithmetic and boolean expressions, we'd hope that
the two alternative definitions of evaluation actually boil down
to the same thing. This section shows that this is the case.
Make sure you understand the statements of the theorems and can
follow the structure of the proofs. *)
Theorem ceval_step__ceval: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros c st st' H.
inversion H as [i E].
clear H.
generalize dependent st'.
generalize dependent st.
generalize dependent c.
induction i as [| i' ].
Case "i = 0 -- contradictory".
intros c st st' H. inversion H.
Case "i = S i'".
intros c st st' H.
com_cases (destruct c) SCase;
simpl in H; inversion H; subst; clear H.
SCase "SKIP". apply E_Skip.
SCase "::=". apply E_Ass. reflexivity.
SCase ";;".
destruct (ceval_step st c1 i') eqn:Heqr1.
SSCase "Evaluation of r1 terminates normally".
apply E_Seq with s.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSCase "Otherwise -- contradiction".
inversion H1.
SCase "IFB".
destruct (beval st b) eqn:Heqr.
SSCase "r = true".
apply E_IfTrue. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SSCase "r = false".
apply E_IfFalse. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SCase "WHILE". destruct (beval st b) eqn :Heqr.
SSCase "r = true".
destruct (ceval_step st c i') eqn:Heqr1.
SSSCase "r1 = Some s".
apply E_WhileLoop with s. rewrite Heqr. reflexivity.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSSCase "r1 = None".
inversion H1.
SSCase "r = false".
inversion H1.
apply E_WhileEnd.
rewrite <- Heqr. subst. reflexivity. Qed.
(** **** Exercise: 4 stars (ceval_step__ceval_inf) *)
(** Write an informal proof of [ceval_step__ceval], following the
usual template. (The template for case analysis on an inductively
defined value should look the same as for induction, except that
there is no induction hypothesis.) Make your proof communicate
the main ideas to a human reader; do not simply transcribe the
steps of the formal proof.
(* FILL IN HERE *)
[]
*)
Theorem ceval_step_more: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
induction i1 as [|i1']; intros i2 st st' c Hle Hceval.
Case "i1 = 0".
simpl in Hceval. inversion Hceval.
Case "i1 = S i1'".
destruct i2 as [|i2']. inversion Hle.
assert (Hle': i1' <= i2') by omega.
com_cases (destruct c) SCase.
SCase "SKIP".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase "::=".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase ";;".
simpl in Hceval. simpl.
destruct (ceval_step st c1 i1') eqn:Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "st1'o = None".
inversion Hceval.
SCase "IFB".
simpl in Hceval. simpl.
destruct (beval st b); apply (IHi1' i2') in Hceval; assumption.
SCase "WHILE".
simpl in Hceval. simpl.
destruct (beval st b); try assumption.
destruct (ceval_step st c i1') eqn: Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite -> Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "i1'o = None".
simpl in Hceval. inversion Hceval. Qed.
(** **** Exercise: 3 stars (ceval__ceval_step) *)
(** Finish the following proof. You'll need [ceval_step_more] in a
few places, as well as some basic facts about [<=] and [plus]. *)
Theorem ceval__ceval_step: forall c st st',
c / st || st' ->
exists i, ceval_step st c i = Some st'.
Proof.
intros c st st' Hce.
ceval_cases (induction Hce) Case.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem ceval_and_ceval_step_coincide: forall c st st',
c / st || st'
<-> exists i, ceval_step st c i = Some st'.
Proof.
intros c st st'.
split. apply ceval__ceval_step. apply ceval_step__ceval.
Qed.
(* ####################################################### *)
(** ** Determinism of Evaluation (Simpler Proof) *)
(** Here's a slicker proof showing that the evaluation relation is
deterministic, using the fact that the relational and step-indexed
definition of evaluation are the same. *)
Theorem ceval_deterministic' : forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 He1 He2.
apply ceval__ceval_step in He1.
apply ceval__ceval_step in He2.
inversion He1 as [i1 E1].
inversion He2 as [i2 E2].
apply ceval_step_more with (i2 := i1 + i2) in E1.
apply ceval_step_more with (i2 := i1 + i2) in E2.
rewrite E1 in E2. inversion E2. reflexivity.
omega. omega. Qed.
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: stage1.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module stage1 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/bachelors.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/bachelors.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/bachelors.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const signed int inf = (signed)((1u << 31) - 1); const signed long long llf = (signed long long)((1ull << 61) - 1); const double eps = 1e-6; const int binary_limit = 128; template <typename T> inline bool readInteger(T& u) { char x; int aFlag = 1; while (!isdigit((x = getchar())) && x != - && x != -1) ; if (x == -1) { ungetc(x, stdin); return false; } if (x == - ) { x = getchar(); aFlag = -1; } for (u = x - 0 ; isdigit((x = getchar())); u = (u << 1) + (u << 3) + x - 0 ) ; ungetc(x, stdin); u *= aFlag; return true; } int n; char a[1005]; char b[1005]; map<char, char> ctc; const char utl = a - A ; inline void init() { gets(a); gets(b); for (int i = 0; a[i]; i++) { ctc[a[i]] = b[i]; ctc[a[i] - utl] = b[i] - utl; } } inline void solve() { gets(a); for (int i = 0; a[i]; i++) { if ((a[i] >= a && a[i] <= z ) || (a[i] >= A && a[i] <= Z )) { putchar(ctc[a[i]]); } else { putchar(a[i]); } } } int main() { init(); solve(); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: GDA_St_N16_M4_P4
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LOAGDA_St_N16_M4_P4(
input [15:0] in1,
input [15:0] in2,
output [16:0] res
);
wire [4:0] temp1, temp2, temp3, temp4;
//C4
wire g0,g1,g2,g3,p0,p1,p2,p3;
wire p3g2,p3p2,p3p2g1,p3p2p1,p3p2p1g0;
wire res_or_1, res_or_2;
wire c4;
and and_3(g3,in1[3],in2[3]);
and and_2(g2,in1[2],in2[2]);
and and_1(g1,in1[1],in2[1]);
and and_0(g0,in1[0],in2[0]);
xor xor_3(p3,in1[3],in2[3]);
xor xor_2(p2,in1[2],in2[2]);
xor xor_1(p1,in1[1],in2[1]);
xor xor_0(p0,in1[0],in2[0]);
and and_4(p3g2,p3,g2);
and and_5(p3p2,p3,p2);
and and_6(p3p2g1,p3p2,g1);
and and_7(p3p2p1,p3p2,p1);
and and_8(p3p2p1g0,p3p2p1,g0);
or or_3(res_or_1,g3,p3g2);
or or_2(res_or_2,p3p2g1,p3p2p1g0);
or or_1(c4,res_or_1,res_or_2);
//C8
wire g4,g5,g6,g7,p4,p5,p6,p7;
wire p7g6,p7p6,p7p6g5,p7p6p5,p7p6p5g4;
wire res_or_3, res_or_4;
wire c8;
and and_9 (g7,in1[7],in2[7]);
and and_10(g6,in1[6],in2[6]);
and and_11(g5,in1[5],in2[5]);
and and_12(g4,in1[4],in2[4]);
xor xor_7(p7,in1[7],in2[7]);
xor xor_6(p6,in1[6],in2[6]);
xor xor_5(p5,in1[5],in2[5]);
xor xor_4(p4,in1[4],in2[4]);
and and_13(p7g6,p7,g6);
and and_14(p7p6,p7,p6);
and and_15(p7p6g5,p7p6,g5);
and and_16(p7p6p5,p7p6,p5);
and and_17(p7p6p5g4,p7p6p5,g4);
or or_6(res_or_3,g7,p7g6);
or or_5(res_or_4,p7p6g5,p7p6p5g4);
or or_4(c8,res_or_3,res_or_4);
//C12
wire g8,g9,g10,g11,p8,p9,p10,p11;
wire p11g10,p11p10,p11p10g9,p11p10p9;
wire res_or_5, res_or_6;
wire c12;
and and_18(g11,in1[11],in2[11]);
and and_19(g10,in1[10],in2[10]);
and and_20(g9,in1[9],in2[9]);
and and_21(g8,in1[8],in2[8]);
xor xor_11(p11,in1[11],in2[11]);
xor xor_10(p10,in1[10],in2[10]);
xor xor_9(p9,in1[9],in2[9]);
xor xor_8(p8,in1[8],in2[8]);
and and_22(p11g10,p11,g10);
and and_23(p11p10,p11,p10);
and and_24(p11p10g9,p11p10,g9);
and and_25(p11p10p9,p11p10,p9);
and and_26(p11p10p9g8,p11p10p9,g8);
or or_9(res_or_5,g11,p11g10);
or or_8(res_or_6,p11p10g9,p11p10p9g8);
or or_7(c12,res_or_5,res_or_6);
// Results
assign temp1[4:0] = (in1[ 3: 0] | in2[ 3: 0]);
assign temp2[4:0] = (in1[ 7: 4] | in2[ 7: 4]) + c4;
assign temp3[4:0] = (in1[11: 8] + in2[11: 8]) + c8;
assign temp4[4:0] = in1[15:12] + in2[15:12] + c12;
assign res[16:0] = {temp4[4:0],temp3[3:0],temp2[3:0],temp1[3:0]};
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, i, j = 0, r = 0, c = 1; cin >> n; long long matrix[n][n]; for (i = 0; i < n - 1; i++) { for (j = 0; j < n - 1; j++) { matrix[i][j] = (i + j) % (n - 1) + 1; } } for (i = 0; i < n - 1; i++) { matrix[i][n - 1] = matrix[n - 1][i] = matrix[i][i]; matrix[i][i] = 0; } matrix[n - 1][n - 1] = 0; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { cout << matrix[i][j] << ; } cout << endl; } } |
#include <bits/stdc++.h> int main() { int n, i, sum = 0; scanf( %d , &n); if (n == 1) sum = 1; if (n == 2) sum = 5; if (n == 3) sum = 13; if (n >= 4) { for (i = 4; i <= n; i++) { sum = sum + i * i - (i - 2) * (i - 2); } sum = sum + 13; } printf( %d , sum); } |
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
(** printing Q %\ensuremath{\mathbb{Q}}% *)
(** printing QZERO %\ensuremath{0_\mathbb{Q}}% #0<sub>Q</sub># *)
(** printing QONE %\ensuremath{1_\mathbb{Q}}% #1<sub>Q</sub># *)
(** printing QTWO %\ensuremath{2_\mathbb{Q}}% #2<sub>Q</sub># *)
(** printing QFOUR %\ensuremath{4_\mathbb{Q}}% #4<sub>Q</sub># *)
Require Export CLogic.
Require Import Arith.
Require Import Peano_dec.
Require Import Zsec.
Require Export QArith.
Require Import stdlib_omissions.Q.
Close Scope Q_scope.
Open Local Scope Q_scope.
(**
* [Q]
** About [Q]
We define the structure of rational numbers as follows. First of all,
it consists of the set of rational numbers, defined as the set of
pairs $\langle a,n\rangle$#⟨a,n⟩# with [a:Z] and
[n:positive]. Intuitively, $\langle a,n\rangle$#⟨a,n⟩#
represents the rational number [a[/]n]. Then there is the equality on
[Q]: $\langle a,m\rangle=\langle
b,n\rangle$#⟨a,m⟩=⟨b,n⟩# iff [an [=] bm]. We
also define apartness, order, addition, multiplication, opposite,
inverse an de constants 0 and 1. *)
Instance Q_default : @DefaultRelation Q Qeq | 2.
Definition Qap (x y : Q) := ~(Qeq x y).
Infix "/=" := Qap (no associativity, at level 70) : Q_scope.
Definition Qinv_dep (x : Q) (x_ : Qap x 0) := Qinv x.
(**
*** Apartness
*)
Lemma Q_non_zero : forall x : Q, (x/=0) -> Qnum x <> 0%Z.
Proof. firstorder. Qed.
Lemma ap_Q_irreflexive0 : forall x : Q, Not (x/=x).
Proof. firstorder. Qed.
Lemma ap_Q_symmetric0 : forall x y : Q, (x/=y) -> y/=x.
Proof. firstorder. Qed.
Lemma ap_Q_cotransitive0 : forall x y : Q, (x/=y) ->
forall z : Q, (x/=z) or (z/=y).
Proof.
intros x y X z.
unfold Qap in |- *.
case (Qeq_dec x z).
intro e.
right.
red in |- *.
intro H0.
apply X.
exact (Qeq_trans x z y e H0).
intros n.
left.
intro H.
elim n.
auto.
Qed.
Lemma ap_Q_tight0 : forall x y : Q, Not (x/=y) <-> x==y.
Proof.
intros x y.
red in |- *.
split.
unfold Qap in |- *.
intro.
case (Qeq_dec x y).
intro e.
assumption.
intro n.
elim H.
intro H0.
elim n.
assumption.
intro H.
unfold Qap in |- *.
red in |- *.
intro H0.
elim H0.
assumption.
Qed.
(**
*** Addition
*)
Lemma Qplus_strext0 : forall x1 x2 y1 y2 : Q,
(x1+y1/=x2+y2) -> (x1/=x2) or (y1/=y2).
Proof.
unfold Qap in |- *.
intros x1 x2 y1 y2 X.
case (Qeq_dec x1 x2).
intro e.
right.
red in |- *.
intro H0.
apply X.
apply Qplus_comp; auto.
tauto.
Qed.
(**
*** Multiplication
*)
Lemma Qmult_strext0 : forall x1 x2 y1 y2 : Q,
(x1*y1/=x2*y2) -> (x1/=x2) or (y1/=y2).
Proof.
intros x1 x2 y1 y2 X.
case (Qeq_dec x1 x2).
right.
intros ?.
apply X.
apply Qmult_comp; auto.
tauto.
Qed.
Lemma nonZero : forall x : Q, ~(x==0) ->
~(Qmake (Zsgn (Qnum x) * Qden x)%Z (posZ (Qnum x))==0).
Proof.
intro x.
unfold Qeq in |- *.
unfold Qnum at 2 6 in |- *.
repeat rewrite Zmult_0_l.
unfold Qden at 1 3 in |- *.
repeat rewrite Zplus_0_l.
repeat rewrite Zmult_1_r.
simpl in |- *.
intro H.
cut (Zsgn (Qnum x) <> 0%Z).
intro H0.
cut (Zpos (Qden x) <> 0%Z).
intro H1.
intro H2.
elim H0.
exact (Zmult_integral_l (Qden x) (Zsgn (Qnum x)) H1 H2).
apply Zgt_not_eq.
auto with zarith.
apply Zsgn_3.
intro; elim H; auto.
Qed.
(**
*** Inverse
*)
Lemma Qinv_strext : forall (x y : Q) x_ y_,
~(Qinv_dep x x_==Qinv_dep y y_) -> ~(x==y).
Proof.
firstorder using Qinv_comp.
Qed.
Lemma Qinv_is_inv : forall (x : Q) (Hx : x/=0),
(x*Qinv_dep x Hx==1) /\ (Qinv_dep x Hx*x==1).
Proof.
intros x Hx.
split.
now apply (Qmult_inv_r x).
rewrite -> Qmult_comm.
now apply (Qmult_inv_r x).
Qed.
(**
*** Less-than
*)
Program Definition Zdec_sign (z: Z): (z < Z0)%Z + (Z0 < z)%Z + (z = Z0) :=
match z with
| Zneg p => inl _ (inl _ _)
| Zpos p => inl _ (inr _ _)
| Z0 => inr _ _
end.
Next Obligation. reflexivity. Qed.
Next Obligation. reflexivity. Qed.
Program Definition Qdec_sign (q: Q): (q < 0) + (0 < q) + (q == 0) :=
match Zdec_sign (Qnum q) with
| inl (inr H) => inl _ (inr _ _)
| inl (inl _) => inl _ (inl _ _)
| inr _ => inr _ _
end.
Next Obligation. unfold Qlt. simpl. rewrite Zmult_1_r. assumption. Qed.
Next Obligation. unfold Qlt. simpl. rewrite Zmult_1_r. assumption. Qed.
Next Obligation. unfold Qeq. simpl. rewrite Zmult_1_r. assumption. Qed.
Lemma Qlt_strext_unfolded : forall x1 x2 y1 y2 : Q,
(x1<y1) -> (x2<y2) or (x1/=x2) or (y1/=y2).
Proof with auto.
intros x1 x2 y1 y2 E.
destruct (Q_dec x2 y2) as [[|] | ]...
destruct (Qeq_dec x1 x2) as [G | ]...
right. right. apply Qnot_eq_sym, Qlt_not_eq. apply Qlt_trans with x2...
eapply Qlt_compat. symmetry. apply G. reflexivity. assumption. (* rewrite fails *)
right.
destruct (Qeq_dec x1 y2) as [G|G].
right. apply Qnot_eq_sym, Qlt_not_eq.
eapply Qlt_compat. symmetry. apply G. reflexivity. assumption.
left. unfold Qap. intro F. apply G. transitivity x2...
Qed.
Lemma Qlt_is_antisymmetric_unfolded : forall x y : Q, (x<y) -> Not (y<x).
Proof.
intros x y E1 E2.
apply (Qlt_irrefl x).
eapply Qlt_trans; eauto.
Qed.
Lemma Qlt_gives_apartness : forall x y : Q, Iff (x/=y) ((x<y) or (y<x)).
Proof with intuition.
intros x y; split; intros E.
destruct (Q_dec x y)...
destruct E.
apply Qlt_not_eq...
apply Qnot_eq_sym, Qlt_not_eq...
Qed.
(**
*** Miscellaneous
We consider the injection [inject_Z] from [Z] to [Q] as a coercion.
*)
Coercion inject_Z : Z >-> Q.
Lemma injz_plus : forall m n : Z,
(inject_Z (m + n):Q)==(inject_Z m:Q)+inject_Z n.
Proof.
intros m n.
unfold inject_Z in |- *.
simpl in |- *.
unfold Qeq in |- *.
unfold Qnum at 1 in |- *.
unfold Qden at 2 in |- *.
replace ((m + n) * 1)%Z with (m + n)%Z.
replace (Qnum (Qmake m 1+Qmake n 1)%Q * 1)%Z with (Qnum (Qmake m 1+Qmake n 1)).
unfold Qplus in |- *.
simpl in |- *.
ring.
ring.
ring.
Qed.
Lemma injZ_One : (inject_Z 1:Q)==1.
Proof. reflexivity. Qed.
(** We can always find a natural Qnumber that is bigger than a given rational
Qnumber.
*)
Theorem Q_is_archemaedian0 : forall x : Q,
{n : positive | x<Qmake n 1%positive}.
Proof.
intro x.
case x.
intros p q.
exists (P_of_succ_nat (Zabs_nat p)).
red in |- *.
unfold Qnum at 1 in |- *.
unfold Qden in |- *.
apply toCProp_Zlt.
simpl in |- *.
rewrite Zmult_1_r.
apply Zlt_le_trans with (P_of_succ_nat (Zabs_nat p) * 1)%Z.
rewrite Zmult_1_r.
case p; simpl in |- *; auto with zarith.
intros; rewrite P_of_succ_nat_o_nat_of_P_eq_succ; rewrite Pplus_one_succ_r.
change (p0 < p0 + 1)%Z in |- *.
auto with zarith.
intros; unfold Zlt in |- *; auto.
change (P_of_succ_nat (Zabs_nat p) * 1%positive <= P_of_succ_nat (Zabs_nat p) * q)%Z in |- *.
apply Zmult_le_compat_l.
change (Zsucc 0 <= q)%Z in |- *.
apply Zgt_le_succ.
auto with zarith.
auto with zarith.
Qed.
Lemma Qle_is_not_lt : forall x y : Q, x <= y <-> ~ y < x.
Proof. firstorder using Qle_not_lt Qnot_lt_le. Qed.
Lemma Qge_is_not_gt : forall x y : Q, x >= y <-> y <= x.
Proof. firstorder. Qed.
Lemma Qgt_is_lt : forall x y : Q, x > y IFF y < x.
Proof. firstorder. Qed.
Lemma QNoDup_CNoDup_Qap(l: list Q): QNoDup l IFF CNoDup Qap l.
Proof with auto.
induction l; simpl; split; intro...
apply NoDup_nil.
split.
apply IHl. inversion_clear H...
apply (CForall_prop _).
intros ? A.
inversion_clear H.
intro E.
apply H0.
rewrite E.
apply in_map...
apply NoDup_cons. 2: firstorder.
intro.
destruct (proj1 (in_map_iff _ _ _) H) as [x [H0 H1]].
destruct X.
apply (snd (@CForall_prop Q (Qap a) l) c0 x)...
rewrite <- (Qred_correct x).
rewrite H0.
symmetry.
apply Qred_correct.
Qed.
|
#include <bits/stdc++.h> using namespace std; void solve() { int n = 0; cin >> n; string s; vector<vector<int> > v(5, vector<int>(0)); for (int i = 0; i < n; i++) { cin >> s; vector<int> cnt(5, 0); int sum = 0; for (int j = 0; j < s.size(); j++) { cnt[s[j] - a ]++; sum++; } for (int j = 0; j < 5; j++) { v[j].push_back(cnt[j] - (sum - cnt[j])); } } long long ans = -1; for (int i = 0; i < 5; i++) { sort(v[i].rbegin(), v[i].rend()); long long sum = 0; long long cnt = 0; for (int j = 0; j < v[i].size(); j++) { sum += v[i][j]; if (sum > 0) { cnt++; } } ans = max(ans, cnt); } cout << ans << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 0; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> namespace FASTIO { char buf[1 << 21]; char *p1, *p2; template <typename T> inline void wt(T x, char c = n ) { if (x < 0) { x = -x; putchar( - ); } static char sta[sizeof(T) * 8]; T top = 0; do { sta[top++] = x % 10; x /= 10; } while (x); while (top) putchar(sta[--top] + 0 ); putchar(c); } template <typename T> inline T rd() { T sum = 0, fl = 1; char ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); for (; ch < 0 || ch > 9 ; ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++)) if (ch == - ) fl = -1; else if (ch == EOF) exit(0); for (; 0 <= ch && ch <= 9 ; ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++)) sum = sum * 10 + ch - 0 ; return sum * fl; } } // namespace FASTIO using namespace FASTIO; int n, m; int k; int len; std::vector<int> a; struct node { node *son[2]; int cnt; node() { son[0] = NULL; son[1] = NULL; cnt = 0; } ~node() { delete son[0]; delete son[1]; } } root; inline void insert(int x) { node *p = &root; for (int i = len; i >= 0; i--) { p->cnt++; const bool $ = (x & 1 << i) != 0; if (!p->son[$]) p->son[$] = new node(); p = p->son[$]; } p->cnt++; return; } inline int query() { const node *p = &root; int ans = 0; for (int i = len; p && i >= 0; i--) { const bool $ = (k & 1 << i) != 0; if (!p->son[$] || p->son[$]->cnt < 1 << i) p = p->son[$]; else { p = p->son[!$]; ans |= 1 << i; } } return ans; } int main() { n = rd<int>(); m = rd<int>(); a.resize(n); for (int &ele : a) ele = rd<int>(); std::sort(a.begin(), a.end()); a.erase(std::unique(a.begin(), a.end()), a.end()); len = a.back(); len = len ? log2(len) + 2 : 2; for (const int &A : a) insert(A); while (m--) { k ^= rd<int>(); wt(query()); } return 0; } |
/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
University of Illinois/NCSA
Open Source License
Copyright(C) 2004, The Board of Trustees of the
University of Illinois. All rights reserved
IVM 1.0
Developed by:
Advanced Computing Systems Group
Center for Reliable and High-Performance Computing
University of Illinois at Urbana-Champaign
http://www.crhc.uiuc.edu/ACS
-- with support from --
Center for Circuits and Systems Solutions (C2S2)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the Software), to
deal with the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimers.
Redistributions in binary, gate-level, layout-level, or physical form must
reproduce the above copyright notice, this list of conditions and the
following disclaimers in the documentation and/or other materials provided
with the distribution.
Neither the names of Advanced Computing Systems Group, Center for Reliable
and High-Performance Computing, Center for Circuits and Systems Solution
(C2S2), University of Illinois at Urbana-Champaign, nor the names of its
contributors may be used to endorse or promote products derived from this
Software without specific prior written permission.
THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
WITH THE SOFTWARE.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
/*******************************************************************************
File: MUXn_8_1.v
Description: This file contains the definition of a n-bit 8-to-1 MUX
******************************************************************************/
`timescale 1ns/100ps
/*
* FUNC_NAME: MUXn_2_1
*
* DESCRIPTION:
* Definition for a n-bit 2-to-1 MUX
*
* INPUT:
* mux_in0 - the input to be output if mux_sel is 0
* mux_in1 - the input to be output if mux_sel is 1
* mux_sel - chooses between the inputs
*
* OUTPUT:
* mux_out - the output of the mux
*
* ASSUMPTIONS:
*
* AUTHOR:
* Justin Quek
* DATE:
* 25-apr-03
* LAST MODIFICATION:
* <modifier's name> <date modified>
*/
module MUXn_2_1(mux_in0, mux_in1, mux_sel, mux_out);
parameter MuxLen = 63;
// outputs
output [MuxLen:0] mux_out;
// inputs
input [MuxLen:0] mux_in0;
input [MuxLen:0] mux_in1;
input mux_sel;
// internal vars
// assign vars
// assing outputs
reg [MuxLen:0] mux_out;
// instantiate other modules
// code
always @(mux_in0 or mux_in1 or mux_sel)
begin
if (mux_sel == 1'b1)
mux_out = mux_in1;
else
mux_out = mux_in0;
end
endmodule // MUXn_2_1
/*
* FUNC_NAME: MUXn_4_1
*
* DESCRIPTION:
* Definition for a n-bit 4-to-1 MUX
*
* INPUT:
* mux_in0 - the input to be output if mux_sel is 00
* mux_in1 - the input to be output if mux_sel is 01
* mux_in2 - the input to be output if mux_sel is 10
* mux_in3 - the input to be output if mux_sel is 11
* mux_sel - chooses between the inputs
*
* OUTPUT:
* mux_out - the output of the mux
*
* ASSUMPTIONS:
*
* AUTHOR:
* Justin Quek
* DATE:
* 25-apr-03
* LAST MODIFICATION:
* <modifier's name> <date modified>
*/
module MUXn_4_1(mux_in0, mux_in1, mux_in2, mux_in3, mux_sel, mux_out);
parameter MuxLen = 63;
// outputs
output [MuxLen:0] mux_out;
// inputs
input [MuxLen:0] mux_in0;
input [MuxLen:0] mux_in1;
input [MuxLen:0] mux_in2;
input [MuxLen:0] mux_in3;
input [1:0] mux_sel;
// internal vars
wire [MuxLen:0] mux_tmp0;
wire [MuxLen:0] mux_tmp1;
// assign vars
// assing outputs
// instantiate other modules
MUXn_2_1 #(MuxLen) mux0(mux_in0, mux_in1, mux_sel[0], mux_tmp0);
MUXn_2_1 #(MuxLen) mux1(mux_in2, mux_in3, mux_sel[0], mux_tmp1);
MUXn_2_1 #(MuxLen) msel(mux_tmp0, mux_tmp1, mux_sel[1], mux_out);
// code
endmodule // MUXn_4_1
/*
* FUNC_NAME: MUXn_8_1
*
* DESCRIPTION:
* Definition for a n-bit 8-to-1 MUX
*
* INPUT:
* mux_in0 - the input to be output if mux_sel is 000
* mux_in1 - the input to be output if mux_sel is 001
* mux_in2 - the input to be output if mux_sel is 010
* mux_in3 - the input to be output if mux_sel is 011
* mux_in4 - the input to be output if mux_sel is 100
* mux_in5 - the input to be output if mux_sel is 101
* mux_in6 - the input to be output if mux_sel is 110
* mux_in7 - the input to be output if mux_sel is 111
* mux_sel - chooses between the inputs
*
* OUTPUT:
* mux_out - the output of the mux
*
* ASSUMPTIONS:
*
* AUTHOR:
* Justin Quek
* DATE:
* 25-apr-03
* LAST MODIFICATION:
* <modifier's name> <date modified>
*/
module MUXn_8_1(mux_in0, mux_in1, mux_in2, mux_in3, mux_in4, mux_in5, mux_in6, mux_in7, mux_sel, mux_out);
parameter MuxLen = 63;
// outputs
output [MuxLen:0] mux_out;
// inputs
input [MuxLen:0] mux_in0;
input [MuxLen:0] mux_in1;
input [MuxLen:0] mux_in2;
input [MuxLen:0] mux_in3;
input [MuxLen:0] mux_in4;
input [MuxLen:0] mux_in5;
input [MuxLen:0] mux_in6;
input [MuxLen:0] mux_in7;
input [2:0] mux_sel;
// internal vars
wire [MuxLen:0] mux_tmp0;
wire [MuxLen:0] mux_tmp1;
// assign vars
// assing outputs
// instantiate other modules
MUXn_4_1 #(MuxLen) mux0(mux_in0, mux_in1, mux_in2, mux_in3, mux_sel[1:0], mux_tmp0);
MUXn_4_1 #(MuxLen) mux1(mux_in4, mux_in5, mux_in6, mux_in7, mux_sel[1:0], mux_tmp1);
MUXn_2_1 #(MuxLen) msel(mux_tmp0, mux_tmp1, mux_sel[2], mux_out);
// code
endmodule // MUXn_8_1
|
#include <bits/stdc++.h> using namespace std; int main() { int n, y; cin >> n; set<int> t; for (int i = 0; i < n; i++) { cin >> y; if (y != 0) t.insert(y); } cout << t.size() << endl; } |
`timescale 1 ns / 1 ps
module asym_ram(clkW, clkR, we, re, wa, ra, wd, rd);
parameter WR_DATA_WIDTH = 64;
parameter WR_ADDR_WIDTH = 9;
parameter RD_DATA_WIDTH = 8;
parameter RD_ADDR_WIDTH = 12;
input clkW;
input we;
input [WR_ADDR_WIDTH-1:0] wa;
input [WR_DATA_WIDTH-1:0] wd;
input clkR;
input re;
input [RD_ADDR_WIDTH-1:0] ra;
output [RD_DATA_WIDTH-1:0] rd;
`define max(a,b) {(a) > (b) ? (a) : (b)}
`define min(a,b) {(a) < (b) ? (a) : (b)}
function integer log2;
input integer value;
integer shifted;
integer res;
begin
shifted = value-1;
for (res=0; shifted>0; res=res+1)
shifted = shifted>>1;
log2 = res;
end
endfunction
localparam SIZEA = 2**WR_ADDR_WIDTH;
localparam SIZEB = 2**RD_ADDR_WIDTH;
localparam maxSIZE = `max(SIZEA, SIZEB);
localparam maxWIDTH = `max(WR_DATA_WIDTH, RD_DATA_WIDTH);
localparam minWIDTH = `min(WR_DATA_WIDTH, RD_DATA_WIDTH);
localparam RATIO = maxWIDTH / minWIDTH;
localparam log2RATIO = log2(RATIO);
reg [minWIDTH-1:0] RAM [0:maxSIZE-1];
reg [RD_DATA_WIDTH-1:0] readB;
assign rd = readB;
generate
if (WR_DATA_WIDTH <= RD_DATA_WIDTH) begin
always @(posedge clkW) begin
if (we)
RAM[wa] <= wd;
end
end
else begin
always @(posedge clkW) begin: ramwrite
integer i;
reg [log2RATIO-1:0] lsbaddr;
if (we) begin
for (i = 0; i < RATIO; i = i+1) begin
lsbaddr = i;
RAM[{wa,lsbaddr}] <= wd[(i+1)*minWIDTH-1 -: minWIDTH];
end
end
end
end
if (WR_DATA_WIDTH >= RD_DATA_WIDTH) begin
always @(posedge clkR) begin
if (re)
readB <= RAM[ra];
end
end
else begin
always @(posedge clkR) begin : ramread
integer i;
reg [log2RATIO-1:0] lsbaddr;
if (re) begin
for (i = 0; i < RATIO; i = i+1) begin
lsbaddr = i;
readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{ra,lsbaddr}];
end
end
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD1_FUNCTIONAL_PP_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD1_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long T; void Read(long long &x) { char c; while (c = getchar(), c != EOF) if (c >= 0 && c <= 9 ) { x = c - 0 ; while (c = getchar(), c >= 0 && c <= 9 ) x = x * 10 + c - 0 ; ungetc(c, stdin); return; } } struct wall { int x1, y1, x2, y2; inline wall() {} inline wall(int x1, int y1, int x2, int y2) : x1(x1), y1(y1), x2(x2), y2(y2) {} } ans[300 + 10]; int cnt; int main() { Read(T); long long a = 1; int t, now = 2, i, tot = 2; while (a <= T) a *= 6, tot += 2; printf( %d %d n , tot, tot); ans[++cnt] = wall(1, 2, 2, 2); ans[++cnt] = wall(2, 1, 2, 2); while (a != 1) { a /= 6; t = T / a; T -= t * a; now += 2; ans[++cnt] = wall(now - 3, now - 1, now - 2, now - 1); if (now != tot) { if (now != 4) { ans[++cnt] = wall(now - 4, now + 1, now - 3, now + 1); ans[++cnt] = wall(now + 1, now - 4, now + 1, now - 3); } ans[++cnt] = wall(now - 2, now, now - 2, now + 1); ans[++cnt] = wall(now - 1, now, now - 1, now + 1); ans[++cnt] = wall(now - 2, now + 2, now - 1, now + 2); ans[++cnt] = wall(now, now - 1, now + 1, now - 1); ans[++cnt] = wall(now, now - 2, now + 1, now - 2); ans[++cnt] = wall(now + 2, now - 2, now + 2, now - 1); } if (t % 3 == 0) ans[++cnt] = wall(now - 3, now, now - 2, now); if (t % 3 <= 1) ans[++cnt] = wall(now, now - 3, now, now - 2); if (t < 3) ans[++cnt] = wall(now - 1, now - 3, now - 1, now - 2); } printf( %d n , cnt); for (i = 1; i <= cnt; i++) printf( %d %d %d %d n , ans[i].x1, ans[i].y1, ans[i].x2, ans[i].y2); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long int INF = 1000000007; const int N = 100000 + 7; int power(int x, unsigned int y) { int res = 1; while (y > 0) { if (y & 1) res = res * x; y = y >> 1; x = x * x; } return res; } int GCD(int A, int B) { if (B == 0) return A; else return GCD(B, A % B); } string decToBin(int number) { if (number == 0) return 0 ; if (number == 1) return 1 ; if (number % 2 == 0) return decToBin(number / 2) + 0 ; else return decToBin(number / 2) + 1 ; } int binToDec(string number) { int result = 0, pow = 1; for (int i = number.length() - 1; i >= 0; --i, pow <<= 1) result += (number[i] - 0 ) * pow; return result; } void seive(int n) { vector<int> primeNums; bool prime[n + 1]; memset(prime, true, sizeof(prime)); for (int p = 2; p * p <= n; p++) { if (prime[p]) { for (int i = 2 * p; i <= n; i += p) prime[i] = false; } } for (int i = 2; i <= n; i++) { if (prime[i]) { primeNums.push_back(i); } } } long long powerMod(long long x, int y, int m) { x = x % m; long long res = 1; while (y > 0) { if (y & 1) { res = (res * x) % m; } y = y >> 1; x = (x * x) % m; } return res; } long long D, X, Y; void extendedEuclid(int a, int b) { if (b == 0) { D = a; X = 1; Y = 0; } else { extendedEuclid(b, a % b); int temp = X; X = Y; Y = temp - (a / b) * Y; } } long long solve(long long n) { if (n == 1) return 0; return n / 2 + 2 * solve((n + 1) / 2); } int main() { long long n; cin >> n; cout << solve(n) << endl; return 0; } |
/*
* This program tests that enumeration value first/last/next
* methods work properly. The .next method requires some run-time
* support for enumeration.
*/
module main;
enum { RED, GREEN = 2, BLUE } color1;
initial begin
color1 = RED;
$display("color1.first == %0d", color1.first);
$display("color1.last == %0d", color1.last);
$display("color1.num == %0d", color1.num);
$display("color1.next == %0d", color1.next);
color1 = color1.next;
if (color1 != GREEN || color1 !== 2) begin
$display("FAILED -- should be %0d, got %0d", GREEN, color1);
$finish;
end
color1 = color1.next;
if (color1 != BLUE || color1 !== 3 || color1 != color1.last) begin
$display("FAILED -- should be %0d, got %0d", BLUE, color1);
$finish;
end
color1 = color1.prev;
if (color1 != GREEN || color1 !== 2) begin
$display("FAILED -- should be %0d, got %0d", GREEN, color1);
$finish;
end
color1 = color1.prev;
if (color1 != RED || color1 !== 0 || color1 != color1.first) begin
$display("FAILED -- should be %0d, got %0d", RED, color1);
$finish;
end
$display("PASSED");
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int n, m, as = 0; template <class T> void read(T &x) { char ch; bool ok; for (ok = 0, ch = getchar(); !isdigit(ch); ch = getchar()) if (ch == - ) ok = 1; for (x = 0; isdigit(ch); x = x * 10 + ch - 0 , ch = getchar()) ; if (ok) x = -x; } int fp(int x, int y) { int asi = 1; while (y) { if (y & 1) asi = 1ll * asi * x % 1000000007; x = 1ll * x * x % 1000000007; y >>= 1; } return asi; } int get_miu(int x) { int asi = 1; for (int i = (2), en = (x); i <= en; ++i) { if (i * i > x) break; if (x % i == 0) { asi = 1000000007 - asi; x /= i; if (x % i == 0) return 0; } } if (x != 1) asi = 1000000007 - asi; return asi; } int main() { read(n); read(m); if (m % n) { puts( 0 ); return 0; }; m /= n; for (int i = (1), en = (m); i <= en; ++i) { if (i * i > m) break; if (m % i == 0) { as = (as + 1ll * fp(2, m / i - 1) * get_miu(i) % 1000000007) % 1000000007; if (i * i != m) as = (as + 1ll * fp(2, i - 1) * get_miu(m / i) % 1000000007) % 1000000007; } } printf( %d n , as); return 0; } |
#include <bits/stdc++.h> int main() { char ai[105]; while (~scanf( %s , ai)) { int t = 1, max = 1; for (int i = 0; ai[i] != 0 ; i++) { if (ai[i] != A && ai[i] != E && ai[i] != I && ai[i] != O && ai[i] != U && ai[i] != Y ) { t++; max = max > t ? max : t; } else t = 1; } printf( %d n , max); } } |
#include <bits/stdc++.h> using namespace std; int main() { int m, n; int i; cin >> m >> n; double p[m]; double pre[m]; p[0] = pow(1.0 / m, n); pre[0] = p[0]; for (i = 1; i < m; i++) { p[i] = pow(double(i + 1) / m, n) - pre[i - 1]; pre[i] = pre[i - 1] + p[i]; } double a = 0; for (int k = 1; k <= m; k++) { a += k * p[k - 1]; } cout << a << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int MAXN = 1e5 + 3; const int inf = 2e9; int max(int a, int b) { if (a > b) return a; else return b; } int min(int a, int b) { if (a < b) return a; else return b; } bool cmp(pair<int, int> p1, pair<int, int> p2) { if (p1.first < p2.first) return true; else if (p1.first == p2.first) { if (p1.second < p2.second) return true; return false; } return false; } void solve() { int n, m, d; cin >> n >> m >> d; int a[n][m]; for (int i = (int)0; i < (int)n; ++i) { for (int j = (int)0; j < (int)m; ++j) { cin >> a[i][j]; } } int check = a[0][0] % d; vector<int> v; bool pr = false; for (int i = (int)0; i < (int)n; ++i) { for (int j = (int)0; j < (int)m; ++j) { if (a[i][j] % d == check) { v.push_back(a[i][j]); } else { pr = true; break; } } } if (pr) cout << -1 << n ; else { sort((v).begin(), (v).end()); int cc = (n * m); int bi = (cc / 2); int ans = 0; for (int i = (int)0; i < (int)cc; ++i) { ans += abs(v[i] - v[bi]); } cout << ans / d << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> int n, C, orig[600010], top, stk[300010], all, Add[300010], One[300010], cost[600010], ctop; struct info { int mx, ord, skdmx; } c[3000010]; info merge(info a, info b) { info c; if (a.mx > b.mx) c = a, c.skdmx = std::max(c.skdmx, b.mx); else c = b, c.skdmx = std::max(c.skdmx, a.mx); return c; } void build(int root, int l, int r) { c[root] = (info){-0x7f7f7f7f, 0, -0x7f7f7f7f}; if (l == r) return; build(root << 1, l, (l + r) >> 1); build(root << 1 | 1, ((l + r) >> 1) + 1, r); } void update(int root, int l, int r, int e, info x) { if (l == r) { c[root] = x; return; } if ((l + r) >> 1 >= e) update(root << 1, l, (l + r) >> 1, e, x); else update(root << 1 | 1, ((l + r) >> 1) + 1, r, e, x); c[root] = merge(c[root << 1], c[root << 1 | 1]); } info query(int root, int l, int r, int el, int er) { if (el > r || er < l) return (info){-0x7f7f7f7f, 0, -0x7f7f7f7f}; if (el <= l && er >= r) return c[root]; return merge(query(root << 1, l, (l + r) >> 1, el, er), query(root << 1 | 1, ((l + r) >> 1) + 1, r, el, er)); } bool Del[300010]; long long f[600010], g[600010]; struct line { int l, r, c; } num[300001]; std::vector<int> add[600010], del[600010]; bool cmp(line a, line b) { return (a.r < b.r) || (a.r == b.r && a.l < b.l); } int main() { scanf( %d%d , &n, &C); for (int i = 1; i <= n; i++) scanf( %d%d%d , &num[i].l, &num[i].r, &num[i].c), orig[++top] = num[i].l, orig[++top] = num[i].r, cost[++ctop] = num[i].c; cost[++ctop] = 0; std::sort(cost + 1, cost + ctop + 1); ctop = std::unique(cost + 1, cost + ctop + 1) - cost - 1; build(1, 1, ctop); orig[++top] = 0; orig[++top] = 0x7f7f7f7f; std::sort(orig + 1, orig + top + 1); top = std::unique(orig + 1, orig + top + 1) - orig - 1; for (int i = 1; i <= n; i++) num[i].l = std::lower_bound(orig + 1, orig + top + 1, num[i].l) - orig, num[i].r = std::lower_bound(orig + 1, orig + top + 1, num[i].r) - orig - 1; for (int i = 1; i <= n; i++) add[num[i].l].push_back(i), del[num[i].r].push_back(i); g[0] = -1e18; for (int i = 1, cnt = 0, last1 = -1, last2 = -1, Sum = 0, empty = 0; i <= top; i++) { f[i] = std::max(f[i - 1], g[i - 1] + orig[i] - 1); g[i] = -1e18; for (int j = 0; j < add[i].size(); j++) stk[++all] = add[i][j], ++cnt; if (!cnt) g[i] = std::max(g[i], f[i] - orig[i] + 1), empty += orig[i + 1] - orig[i]; else if (cnt == 1) { while (Del[stk[all]]) --all; if (num[stk[all]].c <= C) { Add[stk[all]] += orig[i + 1] - orig[i]; g[i] = std::max(g[i], 1ll * empty + 1ll * Add[stk[all]] + 1ll * One[stk[all]] - 1ll * orig[i + 1] + 1); auto now = query( 1, 1, ctop, 1, std::upper_bound(cost + 1, cost + ctop + 1, C - num[stk[all]].c) - cost - 1); g[i] = std::max(g[i], 1ll * empty + 1ll * Add[stk[all]] + 1ll * (now.ord == stk[all] ? now.skdmx : now.mx) - 1ll * orig[i + 1] + 1); update( 1, 1, ctop, std::lower_bound(cost + 1, cost + ctop + 1, num[stk[all]].c) - cost, (info){Add[stk[all]], stk[all], -0x7f7f7f7f}); } } else if (cnt == 2) { while (Del[stk[all]]) --all; int p1 = stk[all]; --all; while (Del[stk[all]]) --all; int p2 = stk[all]; stk[++all] = p1; if (num[p1].c + num[p2].c <= C) { if (last1 != p1 || last2 != p2) Sum = 0, last1 = p1, last2 = p2; Sum += orig[i + 1] - orig[i]; g[i] = std::max( g[i], 1ll * empty + Sum + Add[p1] + Add[p2] - orig[i + 1] + 1); One[p2] = std::max(One[p2], Sum + Add[p1]); One[p1] = std::max(One[p1], Sum + Add[p2]); } } for (int j = 0; j < del[i].size(); j++) Del[del[i][j]] = 1, --cnt; } int m; scanf( %d , &m); for (int i = 1, k; i <= m; i++) { scanf( %d , &k); int l = 1, r = top - 1, mid, ans = -1; while (l <= r) { mid = (l + r) >> 1; if (std::max(f[mid], g[mid] + 1ll * orig[mid + 1] - 1) >= 1ll * k) ans = mid, r = mid - 1; else l = mid + 1; } printf( %lld n , std::max(1ll * orig[ans], 1ll * k - 1ll * g[ans]) + 1ll); } } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; long long gcd(long long p, long long q) { return q == 0 ? p : gcd(q, p % q); } int to[4][2] = {{-1, 0}, {1, 0}, {0, -1}, {0, 1}}; long long n, ans; long long qp(long long a, long long b) { long long s = 1; while (b) { if (b & 1) s = s * a % 998244353; a = a * a % 998244353; b >>= 1; } return s; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; ans = (qp(3, n * n) - qp(qp(3, n) - 3, n) + 998244353) % 998244353; long long xs = -1, c1 = 1; for (int i = 1; i <= n; i++) { xs *= -1; c1 = c1 * (n - i + 1) % 998244353; c1 = c1 * qp(i, 998244353 - 2) % 998244353; ans += xs * (3 * c1 % 998244353 * qp(qp(3, n - i) - 1, n) % 998244353 + c1 * (qp(3, i) - 3) % 998244353 * qp(3, (n - i) * n) % 998244353) % 998244353; } ans = (ans % 998244353 + 998244353) % 998244353; cout << ans << endl; return 0; } |
// Notes to self: latency is parameterized by LATENCY_CYCLES
// bandwidth is DATA_WIDTH / cycle
// latency_cycles is minus one the true latency due to a reg needed to isolate RAM from the rest of the chip
module wb_shift_ram
#(
parameter DATA_WIDTH = 32,
parameter WORD_WIDTH = 8,
parameter ADDR_WIDTH = 3,
parameter LATENCY_CYCLES = 3,
)
(
input wire clk_i,
input wire rst_i,
input wire [0 +: ADDR_WIDTH] adr_i,
input wire [0 +: DATA_WIDTH] dat_i,
output wire [0 +: DATA_WIDTH] dat_o,
output wire [0 +: ADDR_WIDTH] tag_o, // replies back with the requested address, for cacheline purposes
input wire sel_i,
input wire we_i,
input wire stb_i,
input wire cyc_i,
output wire ack_o,
output wire stall_o
);
// FIFO shift registers
reg [0 +: ADDR_WIDTH] lat_pipe_addr [LATENCY_CYCLES];
reg [0 +: DATA_WIDTH] lat_pipe_data [LATENCY_CYCLES];
reg [0 +: DATA_WIDTH / WORD_WIDTH] lat_pipe_sel [LATENCY_CYCLES];
reg lat_pipe_we [LATENCY_CYCLES];
reg lat_pipe_stb [LATENCY_CYCLES];
// RAM
reg [0 +: DATA_WIDTH] mem [1<<ADDR_WIDTH];
// Internal wires
reg [0 +: ADDR_WIDTH] current_addr;
reg [0 +: DATA_WIDTH] current_data;
reg [0 +: DATA_WIDTH / WORD_WIDTH] current_sel;
reg current_we;
reg current_stb;
integer lat_idx;
// Outputs
assign stall_o = 1'b0; // Never stall (no need to, there will always be one slot open
assign ack_o = current_stb; // Send an ACK once everything's gone through the pipe
assign tag_o = current_addr; // Send back the requested address for caching purposes (assuming the synthizer will optimize out unneeded bits)
assign dat_o = current_data;
// Write to mem only the parts we requested, leaving the others alone
genvar sel_idx;
generate
for (sel_idx = 0 ; sel_idx < (DATA_WIDTH / WORD_WIDTH); sel_idx++) begin : gen_sel_cases
always @(posedge clk_i) begin
if(!rst_i && current_stb && current_we && current_sel[sel_idx]) begin
// mem[current_addr][0:7] <= current_data[0:7];
mem[current_addr][sel_idx*WORD_WIDTH : (sel_idx+1)*WORD_WIDTH - 1] <= current_data[sel_idx*WORD_WIDTH: (sel_idx+1)*WORD_WIDTH - 1];
end
end
endgenerate
always @(posedge clk_i) begin
if (rst_i) begin
for (lat_idx = 0; lat_idx < LATENCY_CYCLES; lat_idx++) begin
lat_pipe_stb[lat_idx] <= 0;
end
end
else begin
lat_pipe_stb [0] <= stb_i;
lat_pipe_sel [0] <= sel_i;
lat_pipe_we [0] <= we_i;
lat_pipe_addr[0] <= adr_i;
lat_pipe_data[0] <= dat_i;
current_addr <= lat_pipe_addr[LATENCY_CYCLES - 1];
current_data <= mem[lat_pipe_addr[LATENCY_CYCLES - 1]];;
current_sel <= lat_pipe_sel [LATENCY_CYCLES - 1];
current_we <= lat_pipe_we [LATENCY_CYCLES - 1];
current_stb <= lat_pipe_stb [LATENCY_CYCLES - 1];
for (lat_idx = 1; lat_idx < LATENCY_CYCLES; lat_idx++) begin
lat_pipe_addr[lat_idx] <= lat_pipe_addr[lat_idx-1];
lat_pipe_data[lat_idx] <= lat_pipe_data[lat_idx-1];
lat_pipe_sel [lat_idx] <= lat_pipe_sel [lat_idx-1];
lat_pipe_we [lat_idx] <= lat_pipe_we [lat_idx-1];
lat_pipe_stb [lat_idx] <= lat_pipe_stb [lat_idx-1];
end
end
end
endmodule
|
/*
* Copyright (C)2005-2015 AQUAXIS TECHNOLOGY.
* Don't remove this header.
* When you use this source, there is a need to inherit this header.
*
* This software is released under the MIT License.
* http://opensource.org/licenses/mit-license.php
*
* For further information please contact.
* URI: http://www.aquaxis.com/
* E-Mail: info(at)aquaxis.com
*/
module aq_func_ctl(
input RST_N,
input CLK,
input LOCAL_CS,
input LOCAL_RNW,
output LOCAL_ACK,
input [31:0] LOCAL_ADDR,
input [3:0] LOCAL_BE,
input [31:0] LOCAL_WDATA,
output [31:0] LOCAL_RDATA,
output FUNC_START,
input FUNC_READY,
input FUNC_DONE
);
localparam A_FUNC_START = 8'h00;
localparam A_FUNC_STATUS = 8'h04;
localparam A_FUNC_ARGS_00 = 8'h10;
wire wr_ena, rd_ena, wr_ack;
reg rd_ack;
reg reg_func_start, reg_func_start_d;
reg [31:0] reg_func_args_00;
reg [31:0] reg_rdata;
assign wr_ena = (LOCAL_CS & ~LOCAL_RNW)?1'b1:1'b0;
assign rd_ena = (LOCAL_CS & LOCAL_RNW)?1'b1:1'b0;
assign wr_ack = wr_ena;
// Write Register
always @(posedge CLK or negedge RST_N) begin
if(!RST_N) begin
reg_func_start <= 1'b0;
reg_func_start_d <= 1'b0;
reg_func_args_00 <= 32'd0;
end else begin
if(wr_ena & ((LOCAL_ADDR[7:0] & 8'hFC) == A_FUNC_START)) begin
reg_func_start <= 1'b1;
end else begin
reg_func_start <= 1'b0;
end
reg_func_start_d <= reg_func_start;
if(wr_ena) begin
case(LOCAL_ADDR[7:0] & 8'hFC)
A_FUNC_ARGS_00: begin
reg_func_args_00[31:0] <= LOCAL_WDATA[31:0];
end
default: begin
end
endcase
end
end
end
// Read Register
always @(posedge CLK or negedge RST_N) begin
if(!RST_N) begin
reg_rdata[31:0] <= 32'd0;
rd_ack <= 1'b0;
end else begin
rd_ack <= rd_ena;
if(rd_ena) begin
case(LOCAL_ADDR[7:0] & 8'hFC)
A_FUNC_START: begin
reg_rdata[31:0] <= 32'd0;
end
A_FUNC_STATUS: begin
reg_rdata[31:0] <= {30'd0, FUNC_READY, FUNC_DONE};
end
A_FUNC_ARGS_00: begin
reg_rdata[31:0] <= reg_func_args_00[31:0];
end
default: begin
reg_rdata[31:0] <= 32'd0;
end
endcase
end else begin
reg_rdata[31:0] <= 32'd0;
end
end
end
assign LOCAL_ACK = (wr_ack | rd_ack);
assign LOCAL_RDATA[31:0] = reg_rdata[31:0];
assign FUNC_START = (reg_func_start & ~reg_func_start_d)?1'b1:1'b0;
assign FUNC_ARGS_00 = reg_func_args_00;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { int n, x; while (cin >> n) { map<int, int> a; for (int i = 0; i < n; i++) { cin >> x; if (x != 0) a[x]++; } int ans = 0, ans1 = 0, ans2 = 0; for (map<int, int>::iterator it = a.begin(); it != a.end(); it++) { if (it->second == 2) ans++; else if (it->second < 2) ans1++; else ans2++; } if (ans2 == 0 && ans > 0) cout << ans << endl; else if (ans2 == 0 && ans == 0) cout << 0 << endl; else cout << -1 << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXBN_BLACKBOX_V
`define SKY130_FD_SC_LP__DLXBN_BLACKBOX_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlxbn (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXBN_BLACKBOX_V
|
// Zhiyang Ong
// Andrew Mattheisen
// EE577b Troy WideWord Processor Project
// make module match terms in module defn'
module pipe2(aluop_in, aluop_out,
ww_in, ww_out,
memEn_in, memEn_out,
memWrEn_in, memWrEn_out,
memAddr_in, memAddr_out,
wbyteen_in, wbyteen_out,
regwren_in, regwren_out,
rwraddrd_in, rwraddrd_out,
reginmuxop_in, reginmuxop_out,
aluinmuxop_in, aluinmuxop_out,
immediate_in, immediate_out,
wrdata, hz1data,
instruction_in, instruction_out,
clk,
reset);
// INPUTS
input [0:4] aluop_in;
input [0:1] ww_in;
input memEn_in, memWrEn_in;
input [0:20] memAddr_in;
input [0:15] wbyteen_in;
input regwren_in;
input [0:4] rwraddrd_in;
input reginmuxop_in;
input aluinmuxop_in;
input [0:127] immediate_in;
input [0:127] wrdata;
input [0:31] instruction_in;
input clk, reset;
// OUTPUTS
output [0:4] aluop_out;
output [0:1] ww_out;
output memWrEn_out;
output memEn_out;
output [0:20] memAddr_out;
output [0:15] wbyteen_out;
output regwren_out;
output [0:4] rwraddrd_out;
output reginmuxop_out;
output aluinmuxop_out;
output [0:127] immediate_out;
output [0:127] hz1data;
output [0:31] instruction_out;
//REGISTERS
reg [0:4] aluop_out;
reg [0:2] ppp_out;
reg [0:1] ww_out;
reg memWrEn_out;
reg memEn_out;
reg [0:20] memAddr_out;
reg [0:15] wbyteen_out;
reg regwren_out;
reg [0:4] rwraddrd_out;
reg reginmuxop_out;
reg aluinmuxop_out;
reg [0:127]immediate_out;
reg [0:127] hz1data;
reg [0:31] instruction_out;
always @ (posedge clk)
begin
if (reset == 1'b1)
begin
aluop_out<=5'b0;
ww_out<=2'b0;
memWrEn_out<=1'b0;
memEn_out<=1'b0;
memAddr_out<=21'b0;
wbyteen_out<=16'b0;
regwren_out<=1'b0;
rwraddrd_out<=5'b0;
reginmuxop_out<=1'b0;
aluinmuxop_out<=1'b0;
immediate_out<=128'b0;
hz1data<=128'b0;
instruction_out<=32'b0;
end
else
begin
aluop_out<=aluop_in;
ww_out<=ww_in;
memWrEn_out<=memWrEn_in;
memEn_out<=memEn_in;
memAddr_out<=memAddr_in;
wbyteen_out<=wbyteen_in;
regwren_out<=regwren_in;
rwraddrd_out<=rwraddrd_in;
reginmuxop_out<=reginmuxop_in;
aluinmuxop_out<=aluinmuxop_in;
immediate_out<=immediate_in;
hz1data<=wrdata;
instruction_out<=instruction_in;
end
end // always @ (posedge clk);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Todd Strader.
// SPDX-License-Identifier: CC0-1.0
module t;
typedef struct packed {
logic [ 31 : 0 ] b;
logic [ 7 : 0 ] bar;
} sub_params_t;
typedef struct packed {
logic [ 31 : 0 ] a;
logic [ 5 : 0 ] foo;
sub_params_t sub_params;
} params_t;
localparam P24 = f_add2(7, 8, 9);
initial begin
// Should never get here
$write("*-* All Finished *-*\n");
$finish;
end
function integer f_add(input params_t [ 1 : 0 ] params);
f_add = params[0].a+params[1].sub_params.b;
if (f_add == 15)
$fatal(2, "f_add = 15");
endfunction
// Speced ok: function called from function
function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c);
params_t [ 1 : 0 ] params;
sub_params_t sp0;
sub_params_t sp1;
sp0 = '{b:55, bar:111};
params[0] = '{a:a, foo:11, sub_params:sp0};
sp1 = '{b:b, bar:112};
params[1] = '{a:12345, foo:12, sub_params:sp1};
f_add2 = f_add(params)+c;
endfunction
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_PR_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_DFF_PR_BLACKBOX_V
/**
* udp_dff$PR: Positive edge triggered D flip-flop with active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$PR (
Q ,
D ,
CLK ,
RESET
);
output Q ;
input D ;
input CLK ;
input RESET;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_PR_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e4 + 10; int dp[maxn][40]; long long pw[maxn][40]; long long n; int dfs(int a, int b) { if (dp[a][b]) return dp[a][b]; if (pw[a][b] >= n) return dp[a][b] = 1; if (pw[a][2] >= n) { if ((n - a) % 2 == 0) return dp[a][b] = 1; else return dp[a][b] = 2; } if (dfs(a + 1, b) == 2 || dfs(a, b + 1) == 2) return dp[a][b] = 1; return dp[a][b] = 2; } long long a, b; int main() { scanf( %lld%lld%lld , &a, &b, &n); for (int i = 1; i < maxn; i++) { pw[i][0] = 1; for (int j = 1; j <= 35; j++) { pw[i][j] = pw[i][j - 1] * i; if (pw[i][j] >= n) { for (int k = j; k <= 35; k++) pw[i][k] = n; break; } } } dfs(a, b); if (a == 1) { for (int i = b; i <= 36; i++) { if (i > 35) { printf( Missing n ); break; } if (dp[2][i] == 2) { if ((i - b) % 2 == 0) printf( Masha n ); else printf( Stas n ); break; } } } else { if (dp[a][b] == 1) printf( Masha n ); else printf( Stas n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int Maxn = 102; int n, K; double dp[2][Maxn][Maxn]; int a[Maxn]; inline int c2(int x) { return x * (x - 1) / 2; } inline int max(int x, int y) { return x > y ? x : y; } inline int min(int x, int y) { return x < y ? x : y; } int main() { scanf( %d%d , &n, &K); if (K > 875) K = 875; for (int i = 1; i <= n; i++) scanf( %d , a + i); for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) dp[0][i][j] = a[i] > a[j]; int cs = 1; for (int k = 1; k <= K; k++, cs ^= 1) { for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) { dp[cs][i][j] = 0; dp[cs][i][j] += dp[cs ^ 1][i][j] * (c2(i) + c2(n - j + 1) + c2(j - i)); for (int sum = j + 1; sum <= i + n; sum++) { dp[cs][i][j] += (1.0 - dp[cs ^ 1][sum - j][sum - i]) * (min(i, sum - j) - max(1, sum - n) + 1); } for (int sum = i + 1; sum <= i + j - 1; sum++) dp[cs][i][j] += dp[cs ^ 1][sum - i][j] * (min(i, sum - i) - max(1, sum - j + 1) + 1); for (int sum = j + i + 1; sum <= n + j; sum++) dp[cs][i][j] += dp[cs ^ 1][i][sum - j] * (min(j, sum - j) - max(i + 1, sum - n) + 1); dp[cs][i][j] /= c2(n + 1); } } double ans = 0; for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) ans += dp[cs ^ 1][i][j]; printf( %.12f n , ans); } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int a, b, c, d; cin >> a >> b >> c >> d; if (a < b) swap(a, b); if (c < d) swap(c, d); cout << ((a == c && b + d == a) ? Yes n : No n ); } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:55:26 03/14/2015
// Design Name:
// Module Name: or_gate
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////`timescale 1ns / 1ps
//-----------------------------------------------
module or_gate
(
input [9:0] i,
output o
);
//-----------------------------------------------
//wire [4095:0]data=4096'h4444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444440;
//wire [4095:0]data=4096'hf5ffe6ecf6c7fd7c7577ec5e5f46e55ef474ee66444ff77d756475fde5d76f6fd7ced54c7f67476cdf5fed477ff4644fdf4eee4e476f776665e4fefd7ee5f4f5def75ce5fe4d75ffcc7f47ffcfcffde657cd5475dfc566f66d7cdc675cd655cdf46fd476f7cdddd7fe4dd7e4f545d4c467ee457c5f654664cc6f4567fc6e77fcc6e7cfff4ee6f74eedfdf7e54dee5c7e77fcdeecf6545d44dce676f4cf4fd7ed647f544edeedecdde46ec44d7ed77dfeddc564d657dece675ddf565f7fde7d4dc6c47ec5544f75fdfd5de7f57c466f67e6f5cc5cfd4647777676c46d5fed6d67574f6fecee75dee7d54eee6dce74eedcff6dd5cfd4674ffc4447d6cc5fccee4666f46df547e7e6d67e6f5f457e45ed45ddce565c5656754c5e546e5464d664fddfe5f5efecdf5eee45447f7f4fdcf5e4dd677cd4fef7ce6ce6c6ff4f5f4544ed575feffc675cc6edecee47dc64776d4e5e57644dd75ef4eefc47e5d6465c5cecdf4c4d74cf4ddf6f5d6465cfdc56c4c5cc7f7ec46c5dfd5d6ec57755e4de6eeddc5d46df4ff67f54c77de546445f4f7d7de7c746e7c7d677775dde6e457c7e6dd4f6e7ef67ccf6e55e454f45fdf7ef6c6d4e4d4657d54f7ded5f5e5d7c6e6747efcdc5ceecc7ed7d577d6fd4f74ecd6ef6de5e67e4df4cfc447d56ded46c75f7cdff74f746476de544de74cfedee6554f45e56ec7f75dcde4f647defdf6ee4d9;
wire [4095:0]data=4096'hf5ffe6ecf6c7fd7c7577ec5e5f46e55ef474ee66444ff77d756475fde5d76f6fd7ced54c7f67476cdf5fed477ff4644fdf4eee4e476f776665e4fefd7ee5f4f5def75ce5fe4d75ffcc7f47ffcfcffde657cd5475dfc566f66d7cdc675cd655cdf46fd476f7cdddd7fe4dd7e4f545d4c467ee457c5f654664cc6f4567fc6e77fcc6e7cfff4ee6f74eedfdf7e54dee5c7e77fcdeecf6545d44dce676f4cf4fd7ed647f544edeedecdde46ec44d7ed77dfeddc564d657dece675ddf565f7fde7d4dc6c47ec5544f75fdfd5de7f57c466f67e6f5cc5cfd4647777676c46d5fed6d67574f6fecee75dee7d54eee6dce74eedcff6dd5cfd4674ffc4447d6cc5fccee4666f46df547e7e6d67e6f5f457e45ed45ddce565c5656754c5e546e5464d664fddfe5f5efecdf5eee45447f7f4fdcf5e4dd677cd4fef7ce6ce6c6ff4f5f4544ed575feffc675cc6edecee47dc64776d4e5e57644dd75ef4eefc47e5d6465c5cecdf4c4d74cf4ddf6f5d6465cfdc56c4c1cc7f7ec46c5dfd596ec57755e4de6ee9dc5d46df4ff67f54c77de546445f4f7d7de7c746e7c7d677775dde6e457c7e6dd4f6e7ef67ccf6e55e454f45fdf7ef686d4e4d4657d54f79ed5f5e5d7c6e6743efcdc5ceecc7ed7d577d6fd4f74ecd6ef6de5e67e4df4cfc447d56ded46c75f7cdff74f746476de544de74cfedee6550f45e56ec7f75dcda4f647defdf6ee4d9;
//-----------------------------------------------
assign o = data[4*i+2];
//-----------------------------------------------
endmodule
//----------------------------------------------- |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__SRSDFSTP_BEHAVIORAL_V
/**
* srsdfstp: Scan flop with sleep mode, inverted set, non-inverted
* clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dff_ps_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_ps_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srsdfstp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B ,
SLEEP_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B ;
input SLEEP_B;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire SET ;
wire mux_out ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed ;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
wire pwrgood_pp0_out_Q;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PKG$sN dff0 (buf_Q , mux_out, CLK_delayed, SET, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( ( SLEEP_B === 1'b1 ) && awake );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 && awake );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Q, buf_Q, VPWR, VGND );
buf buf0 (Q , pwrgood_pp0_out_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFSTP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const long long N = 2e5 + 5; stack<pair<long long, long long> > q; long long n, a[N], go[N]; struct cell { long long max_l, max_r, or_l, or_r; }; bool d[N][35]; cell b[N]; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (long long i = 1; i <= n; i++) cin >> a[i]; for (long long i = 1; i <= n; i++) { long long q = a[i], k = 1; while (q != 0) { d[i][k] = q % 2; q /= 2; k++; } } q.push({0, 2e9}); for (long long i = 1; i <= n; i++) { while (q.top().second <= a[i]) q.pop(); b[i].max_l = q.top().first; q.push({i, a[i]}); } while (!q.empty()) q.pop(); q.push({n + 1, 2e9}); for (long long i = n; i > 0; i--) { while (q.top().second < a[i]) q.pop(); b[i].max_r = q.top().first; q.push({i, a[i]}); } while (!q.empty()) q.pop(); for (long long i = 1; i <= n; i++) { long long k = 0; for (long long j = 1; j < 35; j++) if (d[i][j] == 0) k = max(k, go[j]); else go[j] = i; b[i].or_l = k; } for (long long i = 1; i < 35; i++) go[i] = n + 1; for (long long i = n; i > 0; i--) { long long k = n + 1; for (long long j = 1; j < 35; j++) if (d[i][j] == 0) k = min(k, go[j]); else go[j] = i; b[i].or_r = k; } long long ans = 0; for (long long i = 1; i <= n; i++) { if (b[i].max_l >= b[i].or_l) if (b[i].max_r <= b[i].or_r) continue; else ans += (i - b[i].max_l) * (b[i].max_r - b[i].or_r); else if (b[i].max_r <= b[i].or_r) ans += (b[i].or_l - b[i].max_l) * (b[i].max_r - i); else { ans += (b[i].or_l - b[i].max_l) * (b[i].or_r - i); ans += (b[i].max_r - b[i].or_r) * (i - b[i].or_l); ans += (b[i].or_l - b[i].max_l) * (b[i].max_r - b[i].or_r); } } cout << ans; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLYGATE4SD3_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; void readi(int &x) { int v = 0, f = 1; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = v * 10 + c - 0 ; while (isdigit(c = getchar())) v = v * 10 + c - 0 ; x = v * f; } void readll(long long &x) { long long v = 0ll, f = 1ll; char c = getchar(); while (!isdigit(c) && c != - ) c = getchar(); if (c == - ) f = -1; else v = v * 10 + c - 0 ; while (isdigit(c = getchar())) v = v * 10 + c - 0 ; x = v * f; } void readc(char &x) { char c; while ((c = getchar()) == ) ; x = c; } void writes(string s) { puts(s.c_str()); } void writeln() { writes( ); } void writei(int x) { if (x < 0) { putchar( - ); x = abs(x); } if (!x) putchar( 0 ); char a[25]; int top = 0; while (x) { a[++top] = (x % 10) + 0 ; x /= 10; } while (top) { putchar(a[top]); top--; } } void writell(long long x) { if (x < 0) { putchar( - ); x = abs(x); } if (!x) putchar( 0 ); char a[25]; int top = 0; while (x) { a[++top] = (x % 10) + 0 ; x /= 10; } while (top) { putchar(a[top]); top--; } } inline long long inc(int &x) { return ++x; } inline long long inc(long long &x) { return ++x; } inline long long inc(int &x, long long y) { return x += y; } inline long long inc(long long &x, long long y) { return x += y; } inline double inc(double &x, double y) { return x += y; } inline long long dec(int &x) { return --x; } inline long long dec(long long &x) { return --x; } inline long long dec(int &x, long long y) { return x -= y; } inline long long dec(long long &x, long long y) { return x -= y; } inline double dec(double &x, double y) { return x -= y; } inline long long mul(int &x) { return x = ((long long)x) * x; } inline long long mul(long long &x) { return x = x * x; } inline long long mul(int &x, long long y) { return x *= y; } inline long long mul(long long &x, long long y) { return x *= y; } inline double mul(double &x, double y) { return x *= y; } inline long long divi(const int &x) { long long ans, l, r, mid; ans = 0; l = 0; r = 0x3fffffff; while (l < r) { mid = (l + r) / 2; if (mid * mid <= x) { ans = mid; l = mid + 1; } else r = mid; } return ans; } inline long long divi(const long long &x) { long long ans, l, r, mid; ans = 0; l = 0; r = 0x3fffffff; while (l < r) { mid = (l + r) / 2; if (mid * mid <= x) { ans = mid; l = mid + 1; } else r = mid; } return ans; } inline long long divi(int &x, long long y) { return x /= y; } inline long long divi(long long &x, long long y) { return x /= y; } inline double divi(double &x, double y) { return x /= y; } inline long long mod(int &x, long long y) { return x %= y; } inline long long mod(long long &x, long long y) { return x %= y; } long long n, m, i, j, l, r, ans[200005], f, lst; map<long long, long long> cnt; int main() { readll(n); for (i = 1; i <= n; i++) { readll(l); readll(r); cnt[l]++; cnt[r + 1]--; } lst = f = 0; for (__typeof((cnt).begin()) it = (cnt).begin(); it != (cnt).end(); it++) { ans[f] += (it->first - lst); lst = it->first; f += it->second; } if ((1) <= ((n))) for (((i)) = (1); ((i)) <= ((n)); ((i))++) printf( %I64d , ans[i]); return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Drawing Engine Register Block Misc.
// File : der_misc.v
// Author : Frank Bruno
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module is the top level register block for Imagine-MI
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module der_misc
(
input de_clk, /* drawing engine clock input */
input hb_clk, /* host bus clock input */
input prst, /* Pattern Reset */
input cr_pulse,
input [1:0] ps_sel_2, // buf_ctrl_2[10:9]
input bc_co,
input [31:0] mf_sorg_2, /* multi function sorg. */
input [31:0] mf_dorg_2, /* multi function dorg. */
input [1:0] apat_1,
input sd_selector, // buf_ctrl_2[4]
output reg prst_1,
output hb_ca_rdy,
output de_ca_rdy,
output ps16s_2,
output ps565s_2,
output [31:0] de_sorg_2, /* source origin register output */
output [31:0] de_dorg_2, /* destination origin register output */
output [27:0] sorg_2, /* source origin register output */
output [27:0] dorg_2, /* destination origin register output */
output or_apat_1
);
// reg hb_ca_rdy_d;
// reg hb_ca_rdy_ddd;
// reg de_ca_rdy_d;
// reg de_ca_rdy_ddd;
// reg ca_rdy;
// wire crdy_rstn;
// wire hb_ca_rdy_dd;
// wire de_ca_rdy_dd;
assign or_apat_1 = |apat_1;
always @(posedge de_clk) prst_1 <= prst;
assign ps16s_2 = ~ps_sel_2[1] & ps_sel_2[0];
assign ps565s_2 = &ps_sel_2[1:0];
/*
// Cache ready for HB and DE
assign crdy_rstn = rstn;
always @(posedge cr_pulse or negedge crdy_rstn)
if(!crdy_rstn) ca_rdy <= 1'b0;
else ca_rdy <= 1'b1;
always @(posedge hb_clk) hb_ca_rdy_d <= ca_rdy;
always @(posedge hb_clk) hb_ca_rdy_ddd <= hb_ca_rdy_d;
assign hb_ca_rdy = ca_rdy | hb_ca_rdy_ddd;
always @(posedge de_clk) de_ca_rdy_d <= ca_rdy;
always @(posedge de_clk) de_ca_rdy_ddd <= de_ca_rdy_d;
assign de_ca_rdy = (ca_rdy & de_ca_rdy_ddd) | bc_co;
*/
assign hb_ca_rdy = 1'b1;
assign de_ca_rdy = 1'b1;
assign de_sorg_2 = {32{sd_selector}} & mf_sorg_2;
assign de_dorg_2 = {32{sd_selector}} & mf_dorg_2;
// assign sorg_2 = {28{~sd_selector}} & mf_sorg_2[31:4];
// assign dorg_2 = {28{~sd_selector}} & mf_dorg_2[31:4];
assign sorg_2 = {28{~sd_selector}} & {6'h0, mf_sorg_2[25:4]};
assign dorg_2 = {28{~sd_selector}} & {6'h0, mf_dorg_2[25:4]};
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> adj[300005]; vector<int> vec; int par[300005]; int vis1[300005]; int vis2[300005]; int vis3[300005]; int vis4[300005]; int dia[300005]; int root(int x) { return par[x] = ((par[x] == x) ? x : root(par[x])); } void unite(int x, int y) { par[root(y)] = root(x); } void dfs1(int x, int cnt, int &y, int &mx, int t) { if (t) vis1[x] = 1; else vis2[x] = 1; int i; for (i = 0; i < int(adj[x].size()); i++) { if ((!vis1[adj[x][i]] && t) || (!vis2[adj[x][i]] && !t)) { dfs1(adj[x][i], cnt + 1, y, mx, t); } } if (cnt > mx) { mx = cnt; y = x; } } bool dfs2(int x, int y) { if (x == y) { vec.push_back(y); return true; } vis3[x] = 1; int i; for (i = 0; i < int(adj[x].size()); i++) { if (!vis3[adj[x][i]]) { if (dfs2(adj[x][i], y)) { vec.push_back(adj[x][i]); return true; } } } return false; } void dfs3(int x, int y) { vis4[x] = 1; unite(y, x); int i; for (i = 0; i < int(adj[x].size()); i++) { if (!vis4[adj[x][i]]) { dfs3(adj[x][i], y); } } } int main() { int i, n, m, q, x, y, c; scanf( %d %d %d , &n, &m, &q); for (i = 0; i <= n; i++) par[i] = i; for (i = 0; i < m; i++) { scanf( %d %d , &x, &y); adj[x].push_back(y); adj[y].push_back(x); } int mx = 0; for (i = 1; i <= n; i++) { if (!vis1[i]) { vec.clear(); mx = 0; x = i; y = i; dfs1(i, 0, y, mx, 0); mx = 0; dfs1(y, 0, x, mx, 1); dfs2(x, y); int k = int(vec.size()); dfs3(x, vec[k / 2]); dia[vec[k / 2]] = k - 1; } } while (q--) { scanf( %d %d , &c, &x); if (c == 1) { x = root(x); printf( %d n , dia[x]); } else { scanf( %d , &y); x = root(x); y = root(y); if (x == y) continue; if (dia[x] >= dia[y]) { unite(x, y); dia[x] = max(dia[x], 1 + (dia[x] - dia[x] / 2) + (dia[y] - dia[y] / 2)); } else { unite(y, x); dia[y] = max(dia[y], 1 + (dia[x] - dia[x] / 2) + (dia[y] - dia[y] / 2)); } } } return 0; } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_embedded_workgroup_issuer_fifo #(
parameter unsigned MAX_SIMULTANEOUS_WORKGROUPS = 2, // >0
parameter unsigned MAX_WORKGROUP_SIZE = , // >0
parameter unsigned WG_SIZE_BITS = $clog2({1'b0, MAX_WORKGROUP_SIZE} + 1),
parameter unsigned LLID_BITS = (MAX_WORKGROUP_SIZE > 1 ? $clog2(MAX_WORKGROUP_SIZE) : 1),
parameter unsigned WG_ID_BITS = (MAX_SIMULTANEOUS_WORKGROUPS > 1 ? $clog2(MAX_SIMULTANEOUS_WORKGROUPS) : 1)
)
(
input logic clock,
input logic resetn,
// Handshake for item entry into function.
input logic valid_in,
output logic stall_out,
// Handshake with entry basic block
output logic valid_entry,
input logic stall_entry,
// Observe threads exiting the function .
// This is asserted when items are ready to be retired from the workgroup.
input logic valid_exit,
// This is asserted when downstream is not ready to retire an item from
// the workgroup.
input logic stall_exit,
// Need workgroup_size to know when one workgroup ends
// and another begins.
input logic [WG_SIZE_BITS - 1:0] workgroup_size,
// Linearized local id. In range of [0, workgroup_size - 1].
output logic [LLID_BITS - 1:0] linear_local_id_out,
// Hardware work-group id. In range of [0, MAX_SIMULTANEOUS_WORKGROUPS - 1].
output logic [WG_ID_BITS - 1:0] hw_wg_id_out,
// The hardware work-group id of the work-group that is exiting.
input logic [WG_ID_BITS - 1:0] done_hw_wg_id_in,
// Pass though global_id, local_id and group_id.
input logic [31:0] global_id_in[2:0],
input logic [31:0] local_id_in[2:0],
input logic [31:0] group_id_in[2:0],
output logic [31:0] global_id_out[2:0],
output logic [31:0] local_id_out[2:0],
output logic [31:0] group_id_out[2:0]
);
// Entry: 1 cycle latency
// Exit: 1 cycle latency
acl_work_group_limiter #(
.WG_LIMIT(MAX_SIMULTANEOUS_WORKGROUPS),
.KERNEL_WG_LIMIT(MAX_SIMULTANEOUS_WORKGROUPS),
.MAX_WG_SIZE(MAX_WORKGROUP_SIZE),
.WG_FIFO_ORDER(1),
.IMPL("kernel") // this parameter is very important to get the right implementation
)
limiter(
.clock(clock),
.resetn(resetn),
.wg_size(workgroup_size),
.entry_valid_in(valid_in),
.entry_k_wgid(),
.entry_stall_out(stall_out),
.entry_valid_out(valid_entry),
.entry_l_wgid(hw_wg_id_out),
.entry_stall_in(stall_entry),
.exit_valid_in(valid_exit & ~stall_exit),
.exit_l_wgid(done_hw_wg_id_in),
.exit_stall_out(),
.exit_valid_out(),
.exit_stall_in(1'b0)
);
// Pass through ids (global, local, group).
// Match the latency of the work-group limiter, which is one cycle.
always @(posedge clock)
if( ~stall_entry )
begin
global_id_out <= global_id_in;
local_id_out <= local_id_in;
group_id_out <= group_id_in;
end
// local id 3 generator
always @(posedge clock or negedge resetn)
if( ~resetn )
linear_local_id_out <= '0;
else if( valid_entry & ~stall_entry )
begin
if( linear_local_id_out == workgroup_size - 'd1 )
linear_local_id_out <= '0;
else
linear_local_id_out <= linear_local_id_out + 'd1;
end
endmodule
// vim:set filetype=verilog_systemverilog:
|
#include <bits/stdc++.h> using namespace std; int main() { string s; bool neg = false; cin >> s; int n = s.length(); if (s[0] == - ) { neg = true; n--; } int cur = 0; if (n < 3) cur = 1; else if (n == 3) if ((!neg && s <= 127 ) || (neg && s <= -128 )) cur = 1; else cur = 2; else if (n < 5) cur = 2; else if (n == 5) if ((!neg && s <= 32767 ) || (neg && s <= -32768 )) cur = 2; else cur = 3; else if (n < 10) cur = 3; else if (n == 10) if ((!neg && s <= 2147483647 ) || (neg && s <= -2147483648 )) cur = 3; else cur = 4; else if (n < 19) cur = 4; else if (n == 19) if ((!neg && s <= 9223372036854775807 ) || (neg && s <= -9223372036854775808 )) cur = 4; else cur = 5; else cur = 5; if (cur == 1) cout << byte << endl; else if (cur == 2) cout << short << endl; else if (cur == 3) cout << int << endl; else if (cur == 4) cout << long << endl; else cout << BigInteger << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, x = 0; cin >> n; char ch[n]; for (int i = 0; i < n; i++) { cin >> ch[i]; } cout << n + 1 << endl; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Nov 01 14:23:49 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25, probe26, probe27, probe28,
probe29, probe30, probe31)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[8:0],probe20[7:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[0:0],probe25[7:0],probe26[3:0],probe27[0:0],probe28[0:0],probe29[0:0],probe30[7:0],probe31[7:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [8:0]probe19;
input [7:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [0:0]probe24;
input [7:0]probe25;
input [3:0]probe26;
input [0:0]probe27;
input [0:0]probe28;
input [0:0]probe29;
input [7:0]probe30;
input [7:0]probe31;
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { long long x, n; cin >> x >> n; int pp = n % 4; long long z; if (pp == 0) z = 0; else if (pp == 1) z = -n; else if (pp == 2) z = 1; else z = n + 1; long long dre = x % 2 == 0 ? 1 : -1; x += dre * z; cout << x << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin.tie(NULL); long long t = 1; cin >> t; while (t--) { solve(); } return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2020 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dec_table.v when simulating
// the core, dec_table. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dec_table(
clka,
addra,
douta
);
input clka;
input [7 : 0] addra;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("dec_table.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = 2000000002; pair<long long, long long> p[100005]; long long minl[100005], maxl[100005], minr[100005], maxr[100005]; int main() { int i, j, n, a, b; while (~scanf( %d , &n)) { for (i = 0; i < n; i++) { scanf( %d%d , &a, &b); p[i] = make_pair(a - b, a + b); } sort(p, p + n); minl[0] = maxl[0] = p[0].second; for (i = 1; i < n; i++) minl[i] = min(minl[i - 1], p[i].second), maxl[i] = max(maxl[i - 1], p[i].second); minr[n - 1] = maxr[n - 1] = p[n - 1].second; for (i = n - 2; i >= 0; i--) minr[i] = min(minr[i + 1], p[i].second), maxr[i] = max(maxr[i + 1], p[i].second); long long l = 0, r = 4 * inf; while (l < r) { long long s = (l + r) / 2; bool can = 0; j = 0; for (i = 0; i < n; i++) { while (j < n - 1 && p[j + 1].first - p[i].first <= s) j++; if (i == 0 && j == n - 1) { can = true; break; } long long miny = inf, maxy = -inf; if (i > 0) miny = min(minl[i - 1], miny), maxy = max(maxl[i - 1], maxy); if (j < n - 1) miny = min(miny, minr[j + 1]), maxy = max(maxr[j + 1], maxy); if (maxy - miny <= s) can = true; if (can) break; } if (can) r = s; else l = s + 1; } double t = l * 0.5; printf( %.8lf n , t); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t, n, m, i, j; cin >> n >> m; string a[n]; for (long long i = 0; i < n; i++) cin >> a[i]; long long f = 0; for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { if (a[i][j] == . ) continue; if (i - 1 >= 0 && j - 1 >= 0 && a[i - 1][j] == X && a[i][j - 1] == X && a[i - 1][j - 1] == . ) { f = 1; break; } if (i - 1 >= 0 && j + 1 < n && a[i - 1][j] == X && a[i][j + 1] == X && a[i - 1][j + 1] == . ) { f = 1; break; } if (i + 1 < n && j - 1 >= 0 && a[i][j - 1] == X && a[i + 1][j] == X && a[i + 1][j - 1] == . ) { f = 1; break; } if (i + 1 < n && j + 1 < n && a[i + 1][j] == X && a[i][j + 1] == X && a[i + 1][j + 1] == . ) { f = 1; break; } } if (f) break; } for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) { if (a[i][j] == . ) continue; if (i - 1 >= 0 && j - 1 >= 0 && a[i - 1][j - 1] == X && (a[i - 1][j] == . || a[i][j - 1] == . )) { f = 1; break; } if (i - 1 >= 0 && j + 1 < n && a[i - 1][j + 1] == X && (a[i - 1][j] == . || a[i][j + 1] == . )) { f = 1; break; } if (i + 1 < n && j - 1 >= 0 && a[i + 1][j - 1] == X && (a[i + 1][j] == . || a[i][j - 1] == . )) { f = 1; break; } if (i + 1 < n && j + 1 < n && a[i + 1][j + 1] == X && (a[i + 1][j] == . || a[i][j + 1] == . )) { f = 1; break; } } if (f) break; } if (f) cout << NO n ; else cout << YES n ; } |
`timescale 1ps/1ps
module srio_gen2_0_srio_clk
(// Clock in ports
input sys_clkp,
input sys_clkn,
// Status and control signals
input sys_rst,
input mode_1x,
// Clock out ports
output log_clk,
output phy_clk,
output gt_pcs_clk,
output gt_clk,
output refclk,
output drpclk,
// Status and control signals
output clk_lock
);
//------------------------------------
// wire declarations
//------------------------------------
wire refclk_bufg;
wire clkout0;
wire clkout1;
wire clkout2;
wire clkout3;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire to_feedback_in;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
// End wire declarations
//------------------------------------
// // input buffering
//------------------------------------
IBUFDS_GTE2 u_refclk_ibufds(
.O (refclk),
.I (sys_clkp),
.IB (sys_clkn),
.CEB (1'b0),
.ODIV2 ()
);
BUFG refclk_bufg_inst
(.O (refclk_bufg),
.I (refclk));
// End input buffering
// MMCME2_ADV instantiation
//------------------------------------
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (6.500),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (6.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (26),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (13),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (6.400),
.REF_JITTER1 (0.010))
srio_mmcm_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN1 (refclk_bufg),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (clk_lock),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0)
);
// End 7 series MMCM instantiation
//______________________________________________________________________________
// output buffering
//-----------------------------------
BUFG drpclk_bufr_inst
(.O (drpclk),
.I (clkout1));
BUFG gt_clk_bufg_inst
(.O (gt_clk),
.I (clkout0));
BUFG gt_pcs_clk_bufg_inst
(.O (gt_pcs_clk),
.I (clkout2));
BUFGMUX phy_clk_bufg_inst
(.O (phy_clk),
.I0(clkout2),
.I1(clkout1),
.S (mode_1x));
// Note that this bufg is a duplicate of the gt_pcs_clk bufg, and is not necessary if BUFG resources are limited.
BUFG log_clk_bufg_inst
(.O (log_clk),
.I (clkout2));
// End output buffering
//______________________________________________________________________________
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_2_V
`define SKY130_FD_SC_HDLL__XNOR2_2_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xnor2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__xnor2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_2_V
`define SKY130_FD_SC_LS__XOR2_2_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xor2_2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xor2_2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_2_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module cdc_syncfifo #(
parameter DSIZE = 34,
parameter ASIZE = 2
) (
output wire [DSIZE-1:0] rdata,
output wire wfull,
output wire rempty,
input wire [DSIZE-1:0] wdata,
input wire winc, wclk, wrst,
input wire rinc, rclk, rrst
);
wire [ASIZE-1:0] waddr, raddr;
wire [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
cdc_sync_r2w #(.ADDRSIZE(ASIZE)) sync_r2w_inst (.wq2_rptr(wq2_rptr), .rptr(rptr),
.wclk(wclk), .wrst(wrst));
cdc_sync_w2r #(.ADDRSIZE(ASIZE)) sync_w2r_inst (.rq2_wptr(rq2_wptr), .wptr(wptr),
.rclk(rclk), .rrst(rrst));
cdc_fifomem #(.DATASIZE(DSIZE), .ADDRSIZE(ASIZE)) cdc_fifomem_inst
(.rdata(rdata), .wdata(wdata),
.waddr(waddr), .raddr(raddr),
.wclken(winc), .wfull(wfull),
.wclk(wclk));
rptr_empty #(.ADDRSIZE(ASIZE)) rptr_empty_inst
(.rempty(rempty),
.raddr(raddr),
.rptr(rptr), .rq2_wptr(rq2_wptr),
.rinc(rinc), .rclk(rclk),
.rrst(rrst));
wptr_full #(.ADDRSIZE(ASIZE)) wptr_full_inst
(.wfull(wfull), .waddr(waddr),
.wptr(wptr), .wq2_rptr(wq2_rptr),
.winc(winc), .wclk(wclk),
.wrst(wrst));
endmodule
module cdc_fifomem #(
parameter DATASIZE = 34, // Memory data word widt
parameter ADDRSIZE = 2 // Number of mem address
) (
output wire [DATASIZE-1:0] rdata,
input wire [DATASIZE-1:0] wdata,
input wire [ADDRSIZE-1:0] waddr, raddr,
input wire wclken, wfull, wclk
);
//`ifdef VENDORRAM
//
// // instantiation of a vendor's dual-port RAM
// vendor_ram mem (.dout(rdata), .din(wdata),
// .waddr(waddr), .raddr(raddr),
// .wclken(wclken),
// .wclken_n(wfull), .clk(wclk));
//`else
// RTL Verilog memory model
localparam DEPTH = 1<<ADDRSIZE;
reg [DATASIZE-1:0] cdc_mem [0:DEPTH-1];
assign rdata = cdc_mem[raddr];
//always @(posedge wclk)
// rdata <= mem[raddr];
always @(posedge wclk)
if (wclken && !wfull) cdc_mem[waddr] <= wdata;
//`endif
endmodule
module rptr_empty #(
parameter ADDRSIZE = 2
) (
output reg rempty,
output wire [ADDRSIZE-1:0] raddr,
output reg [ADDRSIZE :0] rptr,
input wire [ADDRSIZE :0] rq2_wptr,
input wire rinc, rclk, rrst
);
reg [ADDRSIZE:0] rbin;
wire [ADDRSIZE:0] rgraynext, rbinnext;
//-------------------
// GRAYSTYLE2 pointer
//-------------------
//synopsys sync_set_reset "rrst"
always @(posedge rclk)
if (rrst) {rbin, rptr} <= 0;
else {rbin, rptr} <= {rbinnext, rgraynext};
// Memory read-address pointer (okay to use binary to address memory)
assign raddr = rbin[ADDRSIZE-1:0];
assign rbinnext = rbin + (rinc & ~rempty);
assign rgraynext = (rbinnext>>1) ^ rbinnext;
//---------------------------------------------------------------
// FIFO empty when the next rptr == synchronized wptr or on reset
//---------------------------------------------------------------
wire rempty_val;
assign rempty_val = (rgraynext == rq2_wptr);
//synopsys sync_set_reset "rrst"
always @(posedge rclk)
if (rrst) rempty <= 1'b1;
else rempty <= rempty_val;
endmodule
module wptr_full #(
parameter ADDRSIZE = 2
) (
output reg wfull,
output wire [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE :0] wptr,
input wire [ADDRSIZE :0] wq2_rptr,
input wire winc, wclk, wrst
);
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext;
// GRAYSTYLE2 pointer
//synopsys sync_set_reset "wrst"
always @(posedge wclk)
if (wrst) {wbin, wptr} <= 0;
else {wbin, wptr} <= {wbinnext, wgraynext};
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + (winc & ~wfull);
assign wgraynext = (wbinnext>>1) ^ wbinnext;
//------------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//------------------------------------------------------------------
wire wfull_val;
assign wfull_val = (wgraynext=={~wq2_rptr[ADDRSIZE:ADDRSIZE-1], wq2_rptr[ADDRSIZE-2:0]});
//synopsys sync_set_reset "wrst"
always @(posedge wclk)
if (wrst) wfull <= 1'b0;
else wfull <= wfull_val;
endmodule
module cdc_sync_r2w #(
parameter ADDRSIZE = 2
) (
output reg [ADDRSIZE:0] wq2_rptr,
input wire [ADDRSIZE:0] rptr,
input wire wclk, wrst
);
reg [ADDRSIZE:0] cdc_sync_wq1_rptr;
//synopsys sync_set_reset "wrst"
always @(posedge wclk)
if (wrst) {wq2_rptr,cdc_sync_wq1_rptr} <= 0;
else {wq2_rptr,cdc_sync_wq1_rptr} <= {cdc_sync_wq1_rptr,rptr};
endmodule
module cdc_sync_w2r #(
parameter ADDRSIZE = 2
) (
output reg [ADDRSIZE:0] rq2_wptr,
input wire [ADDRSIZE:0] wptr,
input wire rclk, rrst
);
reg [ADDRSIZE:0] cdc_sync_rq1_wptr;
//synopsys sync_set_reset "rrst"
always @(posedge rclk)
if (rrst) {rq2_wptr,cdc_sync_rq1_wptr} <= 0;
else {rq2_wptr,cdc_sync_rq1_wptr} <= {cdc_sync_rq1_wptr,wptr};
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[1000001]; int nodeNumber[1000001], nodeStart[1000001], nodeEnd[1000001], leftStart[1000001], leftEnd[1000001], rightStart[1000001], rightEnd[1000001]; void Initialise(int n) { sort(a + 1, a + n + 1); for (int i = 0; i <= n; ++i) { nodeStart[i] = 0; nodeEnd[i] = -1; nodeNumber[i] = 1; } nodeStart[1] = 1; nodeEnd[1] = n; } void FixStartEnd(int &i, int &j) { if (i > j) { i = 0, j = -1; } } void FillChildNumbers(int n, int k) { for (int i = 0; i <= n; ++i) { int j = nodeStart[i]; for (; j <= nodeEnd[i] && (a[j] & (1ll << k)) == 0; ++j) ; leftStart[i] = nodeStart[i], leftEnd[i] = j - 1; rightStart[i] = j, rightEnd[i] = nodeEnd[i]; FixStartEnd(leftStart[i], leftEnd[i]); FixStartEnd(rightStart[i], rightEnd[i]); j = (nodeStart[i] > 0) ? nodeEnd[i] : i; nodeStart[i] = 0; nodeEnd[i] = -1; i = j; } } long long ZeroBitCount(int n, int k) { long long ans = 0; for (int i = 1; i <= n; ++i) { int targetBit = ((a[i] & (1ll << k)) > 0), j = nodeNumber[i]; ans += ((targetBit == 1) ? (rightEnd[j] - rightStart[j] + 1) : (leftEnd[j] - leftStart[j] + 1)); } return ans; } void TakeZeroBit(int n, int k) { for (int i = 1; i <= n; ++i) { int targetBit = ((a[i] & (1ll << k)) > 0), j = nodeNumber[i], x, start, end; if (targetBit) { x = rightStart[j], start = rightStart[j], end = rightEnd[j]; } else { x = leftStart[j], start = leftStart[j], end = leftEnd[j]; } nodeNumber[i] = x, nodeStart[x] = start, nodeEnd[x] = end; } } void TakeOneBit(int n, int k) { for (int i = 1; i <= n; ++i) { int targetBit = 1 - ((a[i] & (1ll << k)) > 0), j = nodeNumber[i], x, start, end; if (targetBit) { x = rightStart[j], start = rightStart[j], end = rightEnd[j]; } else { x = leftStart[j], start = leftStart[j], end = leftEnd[j]; } nodeNumber[i] = x, nodeStart[x] = start, nodeEnd[x] = end; } } int main() { int n; long long m; scanf( %d%lld , &n, &m); for (int j = 2; j <= n; ++j) { int i; long long w; scanf( %d%lld , &i, &w); a[j] = (w ^ a[i]); } Initialise(n); long long ans = 0; for (int k = 61; k > -1; --k) { FillChildNumbers(n, k); long long cnt = ZeroBitCount(n, k); if (cnt >= m) { TakeZeroBit(n, k); } else { ans += (1ll << k); m -= cnt; TakeOneBit(n, k); } } printf( %lld n , ans); return 0; } |
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_doubler.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 156 11/29/2004 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.activeclock (),
.areset (),
.clkbad (),
.clkena (),
.clkloss (),
.clkswitch (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena (),
.fbin (),
.locked (),
.pfdena (),
.pllena (),
.scanaclr (),
.scanclk (),
.scandata (),
.scandataout (),
.scandone (),
.scanread (),
.scanwrite (),
.sclkout0 (),
.sclkout1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 2,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC ""
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:55:30 03/10/2014
// Design Name:
// Module Name: Frequency
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Cumulative_Sums(
input wire clk,
input wire rst,
input wire rand,
output reg pass
);
parameter N = 20000, U = 397, L = -397;
reg [14:0] count_bits0, count_bits1, count_bits2;
reg signed [15:0] cum_sum;
wire [14:0] abs_cum_sum;
reg [14:0] max_abs_cum_sum;
assign abs_cum_sum = cum_sum[15]? (-cum_sum) : cum_sum;
always @(posedge clk)
if (rst) begin
count_bits0 <= 15'H7FFF;
count_bits1 <= 0;
count_bits2 <= 1;
cum_sum <= 0;
max_abs_cum_sum <= 0;
pass <= 0;
end
else begin
count_bits0 <= count_bits0 + 1;
count_bits1 <= count_bits0;
count_bits2 <= count_bits1;
if (count_bits0 == (N-1)) begin
count_bits0 <= 0;
end
if (rand) cum_sum <= cum_sum + 1;
else cum_sum <= cum_sum - 1;
if (count_bits1 == (N-1)) begin
cum_sum <= rand ? 1 : -1;
end
if (abs_cum_sum > max_abs_cum_sum) max_abs_cum_sum <= abs_cum_sum;
if (count_bits2 == (N-1)) begin
max_abs_cum_sum <= 1;
if (max_abs_cum_sum <= U) pass <= 1;
else pass <= 0;
end
end
endmodule
|
#include<bits/stdc++.h> #define pb push_back #define mk make_pair #define ll long long #define ss second #define ff first #define pll pair<ll,ll> #define vll vector<ll> #define mll map<ll,ll> #define mod 1000000007 #define w(x) ll x; cin>>x; while(x--) #define ps(x,y) fixed<<setprecision(y)<<x; #define fo(i, j, k, in) for (ll i=j ; i<k ; i+=in) #define re(i, j) fo(i, 0, j, 1) #define pi 3.1415926535897932384626433832795 #define all(cont) cont.begin(), cont.end() #define countbit(x) __builtin_popcount(x) #define mod 1000000007 #define lo lower_bound #define de(n) ll n;cin>>n; #define def(a,n) ll n;cin>>n;ll a[n];re(i,n){cin>>a[i];} #define defi(a,n,k) ll n;cin>>n; ll k;cin>>k;ll a[n];re(i,n){cin>>a[i];} #define deb(x) cout<<#x<< = <<x<<endl; #define tr(it,a) for(auto it=a.begin();it!=a.end();it++) #define nl cout<<endl; using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin>>n; int x[2]={1,-1}; int y[2]={1,-1}; pair<int,int> p; p.first=0; p.second=0; int a1=n/2; int a2=n-n/2; if(n%2!=0){ int c=a2+1; int d=(a1+1); ll ans=1ll*2*(c*d); cout<<ans<<endl; } else{ int c=a2+1; int d=a1+1; ll ans=1ll*c*d; cout<<ans<<endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4B_FUNCTIONAL_V
`define SKY130_FD_SC_HS__AND4B_FUNCTIONAL_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4b (
VPWR,
VGND,
X ,
A_N ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B ;
input C ;
input D ;
// Local signals
wire D not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4B_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; cin >> n; vector<pair<long long, long long>> a(n); vector<long long> ord(n); for (long long i = 0; i < n; i++) { cin >> a[i].first; a[i].second = i; } sort(a.begin(), a.end()); for (long long i = 0; i < n; i++) { ord[a[i].second] = i; } for (long long i = 0; i < n; i++) { cout << (a[(ord[i] + 1) % n].first) << ; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; bool Finish_read; template <class T> inline void read(T &x) { Finish_read = 0; x = 0; int f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; if (ch == EOF) return; ch = getchar(); } while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); x *= f; Finish_read = 1; } template <class T> inline void print(T x) { if (x / 10 != 0) print(x / 10); putchar(x % 10 + 0 ); } template <class T> inline void writeln(T x) { if (x < 0) putchar( - ); x = abs(x); print(x); putchar( n ); } template <class T> inline void write(T x) { if (x < 0) putchar( - ); x = abs(x); print(x); putchar( ); } int main() { int n; scanf( %d , &n); int t = sqrt(n); if (n % t) { for (int i = n / t * t + 1; i <= n; i++) printf( %d , i); } for (int i = n / t; i >= 1; i--) for (int j = (i - 1) * t + 1; j <= i * t; j++) printf( %d , j); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; using ui32 = unsigned; using ui64 = unsigned long long; using i64 = long long; using i32 = int; static constexpr bool debug = false; struct node { node *c[2] = {0, 0}; int cnt = 0; }; node *root = new node; void insert_rec(node *nd, ui32 number, int i) { ++nd->cnt; if (i != -1) { int bit = (number >> i) & 1; if (nd->c[bit] == nullptr) nd->c[bit] = new node; insert_rec(nd->c[bit], number, i - 1); } } void insert(ui32 number) { insert_rec(root, number, 31); } bool remove_rec(node *nd, ui32 number, int i) { if (i != -1) { int bit = (number >> i) & 1; if (remove_rec(nd->c[bit], number, i - 1)) nd->c[bit] = nullptr; } if (--nd->cnt == 0) { delete nd; return true; } else { return false; } } void remove(ui32 number) { remove_rec(root, number, 31); } void print_numbers_rec(node *nd, ui32 number, int i) { if (nd == nullptr) return; if (i == -1) { for (int j = 0; j < nd->cnt; ++j) { cerr << number << ; } } print_numbers_rec(nd->c[0], number << 1, i - 1); print_numbers_rec(nd->c[1], (number << 1) | 1, i - 1); } void print_numbers() { print_numbers_rec(root, 0, 31); cerr << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; vector<ui32> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) { ui32 t; cin >> t; insert(t); } vector<int> o(n); for (int i = 0; i < n; ++i) { node *cur = root; ui32 xored = 0; for (int j = 31; j >= 0; --j) { int bit = (a[i] >> j) & 1; if (cur->c[bit] != nullptr) { cur = cur->c[bit]; xored = (xored << 1) | bit; } else { cur = cur->c[bit ^ 1]; xored = (xored << 1) | (bit ^ 1); } } o[i] = a[i] ^ xored; remove(xored); } for (int i = 0; i < n; ++i) { cout << o[i] << n [i + 1 == n]; } } |
#include <bits/stdc++.h> using namespace std; const int M = 1e5, INF = 1e9; const double PI = 3.141592653589793238462643383279502884197, eps = 1e-9; int sum; void getstring(int st, int ed, int n, bool val) { string s; sum = 0; cout << ? ; for (int i = 0; i < st; i++) cout << 0; for (int i = st; i < ed; i++) cout << (i % 2 ? !val : val), sum += ((val && i % 2 == 0) || (!val && i % 2)); for (int i = ed; i < n; i++) cout << 0; cout << endl; } bool check(int cnt, int total, bool x) { return (cnt != total + sum && x) || (cnt != total - sum && !x); } int main() { int n, total, cnt, st, ed, md; bool val, x; string s1, s2; cin >> n; cout << ? ; for (int i = 0; i < n; i++) cout << 0; cout << endl; cin >> total; cout << ? ; for (int i = 1; i < n; i++) cout << 0; cout << 1 << endl; cin >> cnt; x = (cnt == total - 1); getstring(0, n, n, 0); cin >> cnt; val = !check(cnt, total, !x); st = 0, ed = n - 1; while (st < ed) { md = (st + ed) / 2; getstring(st, md + 1, n, val); cin >> cnt; if (check(cnt, total, !x)) ed = md; else st = md + 1; } if (x) cout << ! << st + 1 << << n; else cout << ! << n << << st + 1; return 0; } |
#include <bits/stdc++.h> char str[110]; int main() { int len, t, _max = 0; scanf( %s , str); len = strlen(str); for (int i = 0; i < len; i++) for (int j = i + 1; j < len; j++) { t = 0; while (str[i + t] == str[j + t]) t++; if (t > _max) _max = t; } printf( %d , _max); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; pair<long long, long long> dp[20][1 << 10]; int a[20]; long long pw[20]; int change(long long n) { int cnt = 0; while (n) { if (n & 1) cnt++; n /= 2; } return cnt; } int k; long long pow(int e, int n) { long long ans = 1; while (n--) { ans *= e; } return ans; } pair<long long, long long> dfs(int len, long long Set, bool zero, bool limit) { if (len == 0) { if (change(Set) <= k) return make_pair(1, 0); return make_pair(0, 0); } if (!limit && dp[len][Set].first != 0 && !zero) return dp[len][Set]; int u = limit ? a[len - 1] : 9; pair<long long, long long> ans = make_pair(0, 0); for (int i = 0; i <= u; i++) { pair<long long, long long> tem = make_pair(0, 0); if (change(Set | (1 << i)) > k) continue; if (zero && i == 0) tem = dfs(len - 1, Set, zero, i == u && limit); else { tem = dfs(len - 1, Set | (1 << i), zero && i == 0, i == u && limit); } ans.first += tem.first; ans.first %= mod; ans.second = (ans.second + i * tem.first % mod * pw[len - 1] % mod + tem.second) % mod; } if (!limit && !zero) dp[len][Set] = ans; return ans; } void init() { pw[0] = 1; for (int i = 1; i < 20; i++) pw[i] = (pw[i - 1] * 10) % mod; for (int i = 0; i < 20; i++) for (int j = 0; j < 1 << 9; j++) dp[i][j].first = dp[i][j].second = 0; } long long solve(long long n) { int len = 0; init(); while (n) { a[len++] = n % 10; n /= 10; } return dfs(len, 0, 1, 1).second; } int main() { long long l, r; while (cin >> l >> r >> k) { cout << (solve(r) - solve(l - 1) + mod) % mod << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[100001], i, l, r, n, j, c44, c1, c4, c, x, ans, h, y, m, step[101], v, b[100500], d[100500]; string s; int main() { cin >> n; for (i = 1; i <= n; i++) { cin >> a[i]; b[i] = a[i]; } sort(b + 1, b + n + 1); for (i = 1; i <= n; i++) { if (l <= b[i]) { c++; l += b[i]; } } cout << c; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5e3 + 5; int readint() { int x = 0, f = 1; char s = getchar(); while (s < 0 || s > 9 ) { if (s == - ) f = -1; (s = getchar()); } while (s >= 0 && s <= 9 ) { x = (x << 3) + (x << 1) + (s ^ 48); (s = getchar()); } return x * f; } long long dp[maxn][maxn]; int a[maxn]; int q[maxn]; int main() { int n = readint(), k = readint(), x = readint(); for (int i = 1; i <= n; i++) { a[i] = readint(); } memset(dp, -0x3f, sizeof(dp)); dp[0][0] = 0; for (int j = 1; j <= x; j++) { int head = 1, tail = 0; q[++tail] = 0; for (int i = 1; i <= n; i++) { while (head <= tail && i - q[head] > k) head++; dp[i][j] = dp[q[head]][j - 1] + a[i] + 0ll; while (head <= tail && dp[q[tail]][j - 1] <= dp[i][j - 1]) tail--; q[++tail] = i; } } long long ans = -1; for (int i = n; i >= n - k + 1; i--) { ans = max(ans, dp[i][x]); } cout << ans; return 0; } |
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