text stringlengths 59 71.4k |
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#include <bits/stdc++.h> using namespace std; int a[102]; int b[102]; int main() { int n, m; cin >> n >> m; int num = 0; for (int i = 1; i <= m; i++) { int q = 0; for (int j = 1; j <= n; j++) { cin >> a[j]; q = max(q, a[j]); } for (int l = 1; l <= n; l++) { if (a[l] == q) { b[l]++; break; } } } int t = 0; for (int j = 1; j <= 100; j++) { t = max(t, b[j]); } for (int l = 1; l <= 100; l++) { if (t == b[l]) { cout << l; break; } } } |
/* fopen2 - test $fopen and $fclose system tasks */
module fopen2;
integer fp1, fp2, fp3, fp4;
integer dfp;
reg error;
reg [31:0] foo;
initial begin
error = 0;
fp1 = $fopen("work/fopen2.out1");
checkfp(fp1);
dfp = fp1|1;
$fdisplay(dfp, "fp1=%d", fp1);
fp2 = $fopen("work/fopen2.out2");
checkfp(fp2);
dfp = fp2|1;
$fdisplay(dfp, "fp2=%d", fp2);
fp3 = $fopen("work/fopen2.out3");
checkfp(fp3);
dfp = fp3|1;
$fdisplay(dfp, "fp3=%d", fp3);
$fclose(fp2);
fp4 = $fopen("work/fopen2.out4");
checkfp(fp4);
dfp = fp4|1;
$fdisplay(dfp, "fp4=%d", fp4);
$fclose(fp1);
$fclose(fp2);
$fclose(fp3);
$fclose(fp4);
if(error == 0)
$display("PASSED");
end // initial begin
task checkfp;
input [31:0] fp;
begin
if(fp != 2 && fp != 4 && fp != 8 && fp != 16 && fp != 32 && fp != 64) begin
$display("FAILED fopen fp=%d", fp);
error = 1;
end
end
endtask // checkfp
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, p, q, ans = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> p; cin >> q; if (q - p >= 2) ans++; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int gcd(int x, int y) { if (y == 0) return x; return gcd(y, x % y); } int lcm(int x, int y) { return x * y / gcd(x, y); } string in; int check(string s) { int ret = 0; while (true) { bool beforem = s[0] == M ; bool changed = false; for (int i = 1; i < s.size(); ++i) { if (s[i] == F ) { if (beforem) { s[i - 1] = F ; s[i] = M ; changed = true; } beforem = false; } else { beforem = true; } } if (!changed) break; ++ret; } return ret; } int main() { cin >> in; vector<int> times; int fcnt = 0; for (int i = 0; i < in.size(); ++i) { if (in[i] == F ) { if (times.size() == 0) { if (i == fcnt) { times.push_back(0); } else { times.push_back(i); } } else { if (i == fcnt) { times.push_back(0); } else { int move = i - fcnt; if (times[times.size() - 1] + 1 <= move) { times.push_back(move); } else { times.push_back(times[times.size() - 1] + 1); } } } ++fcnt; } } int ret = 0; for (int i = 0; i < times.size(); ++i) ret = max(ret, times[i]); printf( %d , ret); return 0; } |
`default_nettype none
`timescale 1ns / 1ps
`include "asserts.vh"
`include "xrs.vh"
module xrs_tb();
reg [11:0] story_to;
reg fault_to;
reg clk_i;
reg [2:0] rwe_i;
reg [4:0] ra_i, rb_i, rd_i;
reg [63:0] rdat_i;
wire [63:0] rdata_o, rdatb_o;
`STANDARD_FAULT
`DEFASSERT(rdata, 63, o)
`DEFASSERT(rdatb, 63, o)
xrs x(
.clk_i(clk_i),
.rd_i(rd_i),
.rdat_i(rdat_i),
.rwe_i(rwe_i),
.rdata_o(rdata_o),
.rdatb_o(rdatb_o),
.ra_i(ra_i),
.rb_i(rb_i)
);
always begin
#5 clk_i <= ~clk_i;
end
initial begin
$dumpfile("xrs.vcd");
$dumpvars;
{
story_to, fault_to, clk_i, rwe_i, ra_i, rb_i, rd_i,
rdat_i
} <= 0;
wait(~clk_i); wait(clk_i); #1;
// Try to store some values in the register file.
rdat_i <= 64'h1122334455667788;
rwe_i <= `XRS_RWE_S64;
rd_i <= 1;
wait(~clk_i); wait(clk_i); #1;
rdat_i <= 64'h7766554433221100;
rd_i <= 2;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_NO;
// Now try to read back the registers we just wrote.
ra_i <= 1;
rb_i <= 2;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h1122334455667788);
assert_rdatb(64'h7766554433221100);
ra_i <= 2;
rb_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h7766554433221100);
assert_rdatb(64'h1122334455667788);
ra_i <= 1;
rb_i <= 0;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h1122334455667788);
assert_rdatb(64'h0);
ra_i <= 0;
rb_i <= 2;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h0);
assert_rdatb(64'h7766554433221100);
// Confirm operation of sign-extension
rdat_i <= 64'h7766554433221100;
rwe_i <= `XRS_RWE_S8;
rd_i <= 1;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_S16;
rd_i <= 2;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_S32;
rd_i <= 3;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_S64;
rd_i <= 4;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_NO;
rdat_i <= 64'h8766554483228180;
rwe_i <= `XRS_RWE_S8;
rd_i <= 5;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_S16;
rd_i <= 6;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_S32;
rd_i <= 7;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_S64;
rd_i <= 8;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_NO;
ra_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h0000000000000000);
ra_i <= 2;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h0000000000001100);
ra_i <= 3;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h0000000033221100);
ra_i <= 4;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h7766554433221100);
ra_i <= 5;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'hFFFFFFFFFFFFFF80);
ra_i <= 6;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'hFFFFFFFFFFFF8180);
ra_i <= 7;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'hFFFFFFFF83228180);
ra_i <= 8;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h8766554483228180);
// Confirm operation of zero-extension
rdat_i <= 64'hFFFFFFFFFFFFFFFF;
rwe_i <= `XRS_RWE_U8;
rd_i <= 1;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_U16;
rd_i <= 2;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_U32;
rd_i <= 3;
wait(~clk_i); wait(clk_i); #1;
rwe_i <= `XRS_RWE_NO;
ra_i <= 1;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h00000000000000FF);
ra_i <= 2;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h000000000000FFFF);
ra_i <= 3;
wait(~clk_i); wait(clk_i); #1;
assert_rdata(64'h00000000FFFFFFFF);
#100;
$stop;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int a, b, rem; cin >> a >> b; long long int count = 0; a = max(a, b); b = min(a, b); while (a != b && b != 0) { count += a / b; a = a % b; a = a + b; b = a - b; a = a - b; } cout << count; return 0; } |
#include <bits/stdc++.h> using namespace std; const int oo = 0x3f3f3f3f; const int max0 = 1e7; const int maxm = 400; const int maxabs = 101; const int max1 = 1e3; bool a[(maxabs << 1) + 5][(maxabs << 1) + 5] = {{0}}; int pre[(max1 << 1) + 5][(max1 << 1) + 5] = {{0}}; int n, ax, ay, bx, by; int walk[4][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}}; char cr[4] = { U , D , R , L }; bool go(const int &first) { putchar(cr[first]); ax += walk[first][0], ay += walk[first][1]; int ux = bx + walk[first][0], uy = by + walk[first][1]; if (ux >= 0 && ux <= maxabs << 1 && uy >= 0 && uy <= maxabs << 1 && a[ux][uy]) return 0; bx = ux, by = uy; return 1; } void bfs(const int &ax, const int &ay) { static pair<int, int> q[max0 + 5]; memset(pre, -1, sizeof pre); pre[ax + max1][ay + max1] = 4; int tot = 0; q[tot++] = make_pair(ax, ay); for (int i = 0; i != tot; ++i) { const pair<int, int> &first = q[i]; for (int j = (0), _end_ = (4); j != _end_; ++j) { int ux = first.first + walk[j][0], uy = first.second + walk[j][1]; if (ux < -max1 || uy < -max1 || ux >= max1 << 1 || uy >= max1 << 1 || pre[ux + max1][uy + max1] != -1) continue; if (ux >= 0 && ux <= maxabs << 1 && uy >= 0 && uy <= maxabs << 1 && a[ux][uy]) continue; pre[ux + max1][uy + max1] = j; q[tot++] = make_pair(ux, uy); } } } void trace_path(const int &first, const int &second, const int &bx, const int &by, const bool &flag = 0) { static int qq[max0 + 5]; int ux = first, uy = second; int tot = 0; while (ux != bx || uy != by) { int tmp = pre[ux + max1][uy + max1]; qq[tot++] = tmp; ux -= walk[tmp][0], uy -= walk[tmp][1]; } reverse(qq, qq + tot); for (int i = 0; i != tot; ++i) { if (go(qq[i]) && flag) qq[tot++] = qq[i]; if (ax == ::bx && ay == ::by) break; } } void solve_inf() { memset(pre, -1, sizeof pre); if (ay > by) { swap(cr[0], cr[1]); for (int i = (0), _end_ = (maxabs); i != _end_; ++i) for (int j = (0), _end_ = (maxabs << 1); j <= _end_; ++j) swap(a[j][i], a[j][(maxabs << 1) - i]); ay = (maxabs << 1) - ay, by = (maxabs << 1) - by; } if (ax > bx) { swap(cr[2], cr[3]); for (int i = (0), _end_ = (maxabs); i != _end_; ++i) for (int j = (0), _end_ = (maxabs << 1); j <= _end_; ++j) swap(a[i][j], a[(maxabs << 1) - i][j]); ax = (maxabs << 1) - ax, bx = (maxabs << 1) - bx; } bfs(ax, ay), trace_path(0, 0, ax, ay); for (int i = (0), _end_ = (maxabs * 3); i != _end_; ++i) go(1); bfs(bx, by), trace_path(0, 0, bx, by); pair<int, int> yyt = make_pair(oo, oo); for (int i = (0), _end_ = (maxabs << 1); i <= _end_; ++i) for (int j = (0), _end_ = (maxabs << 1); j <= _end_; ++j) if (a[i][j]) yyt = min(yyt, make_pair(j, i)); swap(yyt.first, yyt.second); while (bx != yyt.first) go(2); while (ay != by || by != yyt.second - 1) go(0); go(3), go(0); while (ax != bx) go(2); exit(0); } int main() { scanf( %d%d%d%d%d , &ax, &ay, &bx, &by, &n), ax += maxabs, ay += maxabs, bx += maxabs, by += maxabs; if (!n) printf( -1 n ), exit(0); for (int i = (0), _end_ = (n); i != _end_; ++i) { static int first, second; scanf( %d%d , &first, &second); a[first + maxabs][second + maxabs] = 1; } bfs(ax, ay); if (pre[bx + max1][by + max1] == -1) printf( -1 n ), exit(0); if (pre[max1][max1] != -1) solve_inf(); trace_path(bx, by, ax, ay, 1); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a[100010], i, x, val; cin >> n >> x; int cnt[100010] = {0}; int cnt2[100010] = {0}; for (i = 0; i < n; i++) { cin >> a[i]; cnt[a[i]]++; } for (i = 0; i < 100010; i++) { if (cnt[i] > 1) { cout << 0 n ; return 0; } } for (i = 0; i < n; i++) { val = a[i] & x; if (cnt[val] > 0 && val != a[i]) { cout << 1 n ; return 0; } } for (i = 0; i < n; i++) { val = a[i] & x; cnt2[val]++; } for (i = 0; i < 100010; i++) { if (cnt2[i] > 1) { cout << 2 n ; return 0; } } cout << -1 n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2OI_2_V
`define SKY130_FD_SC_LP__A2BB2OI_2_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog wrapper for a2bb2oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2oi_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2bb2oi_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2bb2oi base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2OI_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLRTN_FUNCTIONAL_PP_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_pg/sky130_fd_sc_hs__u_dl_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrtn (
VPWR ,
VGND ,
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hs__u_dl_p_r_pg `UNIT_DELAY u_dl_p_r_pg0 (buf_Q , D, intgate, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTN_FUNCTIONAL_PP_V |
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module altera_mem_if_hhp_qseq_synth_top
# ( parameter
APB_DATA_WIDTH = 32,
APB_ADDR_WIDTH = 32,
AVL_DATA_WIDTH = 32,
AVL_ADDR_WIDTH = 16, // for PHY
AVL_MMR_DATA_WIDTH = 32,
AVL_MMR_ADDR_WIDTH = 8,
MEM_IF_DQS_WIDTH = 1,
MEM_IF_DQ_WIDTH = 8,
MEM_IF_DM_WIDTH = 1,
MEM_IF_CS_WIDTH = 1
) (
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int read() { int x = 0, f = 1; char ch = getchar(); while (ch - 0 < 0 || ch - 0 > 9) { if (ch == - ) f = -1; ch = getchar(); } while (ch - 0 >= 0 && ch - 0 <= 9) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } int n, m, A, B; int a[200010], w[200010]; int quick_pow(int x, int p) { int an = 1; int po = x; while (p) { if (p & 1) an = 1ll * an * po % 998244353; po = 1ll * po * po % 998244353; p >>= 1; } return an; } int f[3010][3010], g[3010][3010]; int inv[3010 * 2]; int main() { n = read(); m = read(); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 1; i <= n; i++) w[i] = read(); for (int i = 1; i <= n; i++) { A += (a[i] == 1) * w[i]; A %= 998244353; B += (a[i] == 0) * w[i]; B %= 998244353; } for (int i = 1; i <= 2 * m; i++) inv[i] = quick_pow(A + B + i - m, 998244353 - 2); for (int i = m; i >= 0; i--) { f[i][m - i] = g[i][m - i] = 1; for (int j = min(m - i - 1, B); j >= 0; j--) { f[i][j] = (1ll * f[i + 1][j] * (A + i + 1) % 998244353 * inv[i - j + m] % 998244353 + 1ll * f[i][j + 1] * (B - j) % 998244353 * inv[i - j + m] % 998244353) % 998244353; g[i][j] = (1ll * g[i + 1][j] * (A + i) % 998244353 * inv[i - j + m] % 998244353 + 1ll * g[i][j + 1] * (B - j - 1) % 998244353 * inv[i - j + m] % 998244353) % 998244353; } } for (int i = 1; i <= n; i++) { if (a[i] == 1) printf( %d n , 1ll * w[i] * f[0][0] % 998244353); else printf( %d n , 1ll * w[i] * g[0][0] % 998244353); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2_SYMBOL_V
`define SKY130_FD_SC_MS__MUX2_SYMBOL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux2 (
//# {{data|Data Signals}}
input A0,
input A1,
output X ,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; void solve() { string n; cin >> n; vector<string> vec; int si = n.size(); for (int i = 0; i < si; i++) { if (n[i] == 0 ) continue; string s = ; s += n[i]; for (int j = i + 1; j < si; j++) { s += 0 ; } vec.push_back(s); } cout << vec.size() << n ; for (int i = 0; i < int(vec.size()); i++) { cout << vec[i] << ; } } int main() { int t; cin >> t; while (t--) { solve(); cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base ::sync_with_stdio(0); long long int n; cin >> n; cout << 1 << ; n--; for (int i = 1; i <= 2; i++) { if ((n - i) % 3 != 0) { cout << i << << n - i; break; } } } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module reads and writes data to the RS232 connectpr on Altera's *
* DE1 and DE2 Development and Education Boards. *
* *
******************************************************************************/
module altera_up_rs232_counters (
// Inputs
clk,
reset,
reset_counters,
// Bidirectionals
// Outputs
baud_clock_rising_edge,
baud_clock_falling_edge,
all_bits_transmitted
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // BAUD COUNTER WIDTH
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // TOTAL DATA WIDTH
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input reset_counters;
// Bidirectionals
// Outputs
output reg baud_clock_rising_edge;
output reg baud_clock_falling_edge;
output reg all_bits_transmitted;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [(CW-1):0] baud_counter;
reg [ 3: 0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
baud_counter <= {CW{1'b0}};
else if (reset_counters)
baud_counter <= {CW{1'b0}};
else if (baud_counter == BAUD_TICK_COUNT)
baud_counter <= {CW{1'b0}};
else
baud_counter <= baud_counter + 1;
end
always @(posedge clk)
begin
if (reset)
baud_clock_rising_edge <= 1'b0;
else if (baud_counter == BAUD_TICK_COUNT)
baud_clock_rising_edge <= 1'b1;
else
baud_clock_rising_edge <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
baud_clock_falling_edge <= 1'b0;
else if (baud_counter == HALF_BAUD_TICK_COUNT)
baud_clock_falling_edge <= 1'b1;
else
baud_clock_falling_edge <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
bit_counter <= 4'h0;
else if (reset_counters)
bit_counter <= 4'h0;
else if (bit_counter == TDW)
bit_counter <= 4'h0;
else if (baud_counter == BAUD_TICK_COUNT)
bit_counter <= bit_counter + 4'h1;
end
always @(posedge clk)
begin
if (reset)
all_bits_transmitted <= 1'b0;
else if (bit_counter == TDW)
all_bits_transmitted <= 1'b1;
else
all_bits_transmitted <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int test; cin >> test; while (test--) { int n; cin >> n; for (int i = 0; i < n; i++) { cout << 8 << ; } cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; #define int long long const int MAX = 1e6 + 7; int num[MAX]; signed main() { int T; cin >> T; while (T--) { int N, u, v; cin >> N >> u >> v; for (int i = 1; i <= N; i++) { cin >> num[i]; } int canget = 0; int flag = 0; for (int i = 1; i < N; i++) { if (abs(num[i] - num[i + 1]) > 1) { canget = 1; cout << 0 << n ; flag = 1; break; } } if (flag == 1) { continue; } if (canget) { continue; } int ban = 0; for (int i = 1; i < N; i++) { if (num[i] != num[i + 1]) { ban = 1; } } if (ban) { cout << min(u, v) << n ; } else { cout << min(u + v, v * 2) << n ; } } return 0; } |
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build Tue Nov 18 16:47:07 MST 2014
//Date : Mon Mar 14 19:31:48 2016
//Host : ubuntu-desktop running 64-bit Ubuntu 14.04.4 LTS
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
GND GND
(.G(GND_1));
design_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.MIO(FIXED_IO_mio[53:0]),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.USB0_VBUS_PWRFAULT(GND_1));
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 999999999999999999; const double PI = acos(-1.0); void stop() { exit(0); } long long A[200005]; int main() { ios::sync_with_stdio(false); long long n; cin >> n; for (long long i = 0; i < n; i++) { cin >> A[i]; } long long res = 1; long long curr = 1; for (long long i = 0; i < n - 1; i++) { if (A[i] * 2 >= A[i + 1]) { curr++; } else { if (curr > res) res = curr; curr = 1; } } if (curr > res) res = curr; cout << res; stop(); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DFXBP_PP_SYMBOL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_PP_SYMBOL_V
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module ALU16(A, B, sel, out);
input [15:0] A, B;
input [2:0] sel;
output [15:0] out;
assign less = 1'b0;;
//Still need to account for less
wire [15:0] c;
wire set;
alu_slice a1(A[0], B[0], sel[2], set, sel, c[0], out[0]);
alu_slice a2(A[1], B[1], c[0], less, sel, c[1], out[1]);
alu_slice a3(A[2], B[2], c[1], less, sel, c[2], out[2]);
alu_slice a4(A[3], B[3], c[2], less, sel, c[3], out[3]);
alu_slice a5(A[4], B[4], c[3], less, sel, c[4], out[4]);
alu_slice a6(A[5], B[5], c[4], less, sel, c[5], out[5]);
alu_slice a7(A[6], B[6], c[5], less, sel, c[6], out[6]);
alu_slice a8(A[7], B[7], c[6], less, sel, c[7], out[7]);
alu_slice a9(A[8], B[8], c[7], less, sel, c[8], out[8]);
alu_slice a10(A[9], B[9], c[8], less, sel, c[9], out[9]);
alu_slice a11(A[10], B[10], c[9], less, sel, c[10], out[10]);
alu_slice a12(A[11], B[11], c[10], less, sel, c[11], out[11]);
alu_slice a13(A[12], B[12], c[11], less, sel, c[12], out[12]);
alu_slice a14(A[13], B[13], c[12], less, sel, c[13], out[13]);
alu_slice a15(A[14], B[14], c[13], less, sel, c[14], out[14]);
alu_slice_msb a16(A[15], B[15], c[14], less, sel, c[15], out[15],set);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct milk { int x, num; bool operator<(const milk &mm) const { return x < mm.x; } } b[1000010]; int a[1000010], n, m, k; bool ok(int p2) { int p1 = 1, now = 0; while (p1 <= n || p2 <= m) { if ((p1 <= n && a[p1] < now) || (p2 <= m && b[p2].x < now)) return 0; for (int i = 1; i <= k; i++) if (p1 <= n && (p2 > m || a[p1] < b[p2].x)) p1++; else p2++; now++; } return 1; } int main() { int l, r, mid; scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= m; i++) { scanf( %d , &b[i].x); b[i].num = i; } sort(a + 1, a + n + 1); sort(b + 1, b + m + 1); if (!ok(m + 1)) { printf( -1 n ); return 0; } l = 1; r = m + 1; while (l < r) { mid = (l + r) / 2; if (ok(mid)) r = mid; else l = mid + 1; } printf( %d n , m - l + 1); for (int i = l; i <= m; i++) printf( %d%c , b[i].num, i == m ? n : ); } |
#include <bits/stdc++.h> using namespace std; long long int a[1000005]; int main() { long long int i, j, k, l, n, m; cin >> n >> m; if (n / m < 3) { cout << -1; return 0; } j = 1; long long int f = 0; long long int x, y; x = 1, y = n - 1; while (y - x >= 4 && j < m) { a[x] = a[x + 1] = a[y] = j; j++; x += 2; y--; } while (x <= y) { a[x] = j; x++; } a[n] = j; for (i = 1; i <= n; i++) cout << a[i] << ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FA_BLACKBOX_V
`define SKY130_FD_SC_MS__FA_BLACKBOX_V
/**
* fa: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FA_BLACKBOX_V
|
/****************************************************
SIM Memory Model
with byte & half_word access controller
Version : 1.0.0
1.0.0 : 2014/07/05 Basic Mode
Memory Model
Little Endian
Ex :
data = 0x01234567
-Load
load_word[0] = 0x01234567
load_hf_word[0] = 0x0123
load_byte[0] = 0x01
-Store
store_word[0], 0x89abcdef = 0x89abcdef
store_hf_word[0], 0x89ab = 0x89ab4567
store_byte[0], 0x89 = 0x89234567
****************************************************/
`default_nettype none
module sim_memory_model(
input wire iCLOCK,
input wire inRESET,
//Req
input wire iMEMORY_REQ,
output wire oMEMORY_LOCK,
input wire [1:0] iMEMORY_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
input wire [3:0] iMEMORY_MASK,
input wire iMEMORY_RW, //1:Write | 0:Read
input wire [25:0] iMEMORY_ADDR,
//This -> Data RAM
input wire [31:0] iMEMORY_DATA,
//Data RAM -> This
output wire oMEMORY_VALID,
input wire iMEMORY_LOCK,
output wire [63:0] oMEMORY_DATA
);
parameter P_MEM_INIT_LOAD = 1; //0:not load | 1:load | 2:addr=data(Double Word Order) | 3:addr=data(Word Order) | 5:addr=data(Byte Order) | 7:Addr(Word)=Data(Word)
parameter P_MEM_INIT_LOAD_FIEL = "binary_file.bin";
parameter P_MEM_SIZE = 134217728/8;
parameter P_DISP_WRITE = 0; //0:No Display | 1:Display | 2:Display with endian convert
parameter P_DISP_READ = 0; //0:No Display | 1:Display | 2:Display with endian convert
wire fifo_write_full;
wire fifo_read_empty;
wire [63:0] fifo_read_data;
reg [63:0] b_mem_data[0:P_MEM_SIZE-1];
integer i;
wire system_busy = fifo_write_full;
wire system_read_condition = iMEMORY_REQ && !iMEMORY_RW && !system_busy && !fifo_write_full;
wire system_write_condition = iMEMORY_REQ && iMEMORY_RW && !system_busy;
function [63:0] func_data_mask;
input func_word_select; //0
input [3:0] func_byte_enable; //1111
input [31:0] func_new_data;
input [63:0] func_current_data;
reg [63:0] func_private_data;
begin
if(!func_word_select)begin
func_private_data[7:0] = (func_byte_enable[0])? func_new_data[7:0] : func_current_data[7:0];
func_private_data[15:8] = (func_byte_enable[1])? func_new_data[15:8] : func_current_data[15:8];
func_private_data[23:16] = (func_byte_enable[2])? func_new_data[23:16] : func_current_data[23:16];
func_private_data[31:24] = (func_byte_enable[3])? func_new_data[31:24] : func_current_data[31:24];
func_private_data[63:32] = func_current_data[63:32];
end
else begin
func_private_data[39:32] = (func_byte_enable[0])? func_new_data[7:0] : func_current_data[39:32];
func_private_data[47:40] = (func_byte_enable[1])? func_new_data[15:8] : func_current_data[47:40];
func_private_data[55:48] = (func_byte_enable[2])? func_new_data[23:16] : func_current_data[55:48];
func_private_data[63:56] = (func_byte_enable[3])? func_new_data[31:24] : func_current_data[63:56];
func_private_data[31:0] = func_current_data[31:0];
end
func_data_mask = func_private_data;
end
endfunction
//Memory Write Block
wire [63:0] write_data = func_data_mask(
iMEMORY_ADDR[2],
iMEMORY_MASK,
iMEMORY_DATA,
b_mem_data[iMEMORY_ADDR[25:3]]
);
always@(posedge iCLOCK)begin
if(system_write_condition)begin
b_mem_data[iMEMORY_ADDR[25:3]] <= write_data;
end
end
//Memory
initial begin
#0 begin
if(P_MEM_INIT_LOAD == 1)begin
//Load File
$readmemh(P_MEM_INIT_LOAD_FIEL, b_mem_data);
//Endian Convert
$display("[INF][sim_memory_model.v]Please wait. Endian converting for test file.");
for(i = 0; i < P_MEM_SIZE; i = i + 1)begin
b_mem_data[i] = func_endian_convert(b_mem_data[i]); //[]
end
$display("[INF][sim_memory_model.v]Mem[0]->%x", b_mem_data[0]);
end
//Double Word Order
else if(P_MEM_INIT_LOAD == 2)begin
for(i = 0; i < P_MEM_SIZE; i = i + 1)begin
b_mem_data[i] = func_endian_convert(i);
end
end
//Word Order
else if(P_MEM_INIT_LOAD == 3)begin
for(i = 0; i < P_MEM_SIZE; i = i + 1)begin
b_mem_data[i] = func_endian_convert({func_32bit(i*2+1), func_32bit(i*2)});
end
end
//Byte Order
else if(P_MEM_INIT_LOAD == 5)begin
for(i = 0; i < P_MEM_SIZE; i = i + 1)begin
b_mem_data[i] = func_endian_convert(
{
func_8bit(i*8+7),
func_8bit(i*8+6),
func_8bit(i*8+5),
func_8bit(i*8+4),
func_8bit(i*8+3),
func_8bit(i*8+2),
func_8bit(i*8+1),
func_8bit(i*8)
}
);
end
end
//Word Order(Addr=Data)
else if(P_MEM_INIT_LOAD == 7)begin
for(i = 0; i < P_MEM_SIZE; i = i + 1)begin
b_mem_data[i] = func_endian_convert({func_32bit({i*2+1, 2'h0}), func_32bit({i*2, 2'h0})});
end
end
//Half Word Order(Addr=Data)
//Byte Order(Addr=Data)
//Double Word Order(Addr=Data*2)
//Word Order(Addr=Data*2)
else if(P_MEM_INIT_LOAD == 11)begin
for(i = 0; i < P_MEM_SIZE; i = i + 1)begin
b_mem_data[i] = func_endian_convert({func_32bit({i*4+2, 2'h0}), func_32bit({i*4, 2'h0})});
end
end
end
end
//Read Write Display
always@(posedge iCLOCK)begin
//Write
if(system_write_condition && P_DISP_WRITE == 1)begin
$display("[INFO][sim_memory_model.v] : Write Memory[%x(Byte)] = %x", iMEMORY_ADDR[25:0], write_data);
end
else if(system_write_condition && P_DISP_WRITE == 2)begin
$display("[INFO][sim_memory_model.v][EC-Display] : Write Memory[%x(Byte)] = %x", iMEMORY_ADDR[25:0], func_endian_convert(write_data));
end
//Read
if(system_read_condition && P_DISP_READ == 1)begin
$display("[INFO][sim_memory_model.v] : Read Memory[%x(Byte)] = %x", iMEMORY_ADDR[25:0], b_mem_data[iMEMORY_ADDR[25:3]]);
end
else if(system_read_condition && P_DISP_READ == 2)begin
$display("[INFO][sim_memory_model.v][EC-Display] : Read Memory[%x(Byte)] = %x", iMEMORY_ADDR[25:0], func_endian_convert(b_mem_data[iMEMORY_ADDR[25:3]]));
end
end
function [63:0] func_endian_convert;
input [63:0] func_data;
reg [31:0] func_tmp;
begin
func_tmp = func_data[63:32];
func_endian_convert = {
func_tmp[7:0], func_tmp[15:8], func_tmp[23:16], func_tmp[31:24],
func_data[7:0], func_data[15:8], func_data[23:16], func_data[31:24]
};
end
endfunction
function [31:0] func_32bit;
input [31:0] func_data;
begin
func_32bit = func_data;
end
endfunction
function [7:0] func_8bit;
input [7:0] func_data;
begin
func_8bit = func_data;
end
endfunction
mist1032isa_sync_fifo #(64, 8, 3) OUT_FIFO(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.oCOUNT(),
.iWR_EN(system_read_condition),
.iWR_DATA(b_mem_data[iMEMORY_ADDR[25:3]]),
.oWR_FULL(fifo_write_full),
.iRD_EN(!iMEMORY_LOCK && !fifo_read_empty),
.oRD_DATA(fifo_read_data),
.oRD_EMPTY(fifo_read_empty)
);
assign oMEMORY_VALID = !iMEMORY_LOCK && !fifo_read_empty;
assign oMEMORY_DATA = fifo_read_data;
assign oMEMORY_LOCK = fifo_write_full;
endmodule
`default_nettype wire
|
`timescale 1ns / 1ps
module EXMEM
(
// Input
input Clk,
input Reset,
input [31:0] PCIn,
input [2:0] WBIn,
input [1:0] MIn,
input [31:0] ALUResultIn,
// input ALUZeroIn,
input [31:0] MemDataIn,
input [4:0] DstMuxIn,
// Output
output reg [31:0] PCOut,
(* equivalent_register_removal = "no" *) output reg [2:0] WBOut,
(* equivalent_register_removal = "no" *) output reg [1:0] MOut,
output reg [31:0] ALUResultOut,
// output reg ALUZeroOut,
output reg [31:0] MemDataOut,
output reg [4:0] DstMuxOut
);
always @( posedge Clk or posedge Reset )
begin
if ( Reset )
begin
PCOut <= 32'b0;
WBOut <= 2'b0;
MOut <= 2'b0;
ALUResultOut <= 32'b0;
// ALUZeroOut <= 1'b0;
MemDataOut <= 32'b0;
DstMuxOut <= 5'b0;
end
else
begin
PCOut <= PCIn;
WBOut <= WBIn;
MOut <= MIn;
ALUResultOut <= ALUResultIn;
// ALUZeroOut <= ALUZeroIn;
MemDataOut <= MemDataIn;
DstMuxOut <= DstMuxIn;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; map<string, int> m; string s; string pr[109]; int darab[109][26]; int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n; cout << ? << 1 << << n << endl; for (int i = 1; i <= (n * (n + 1)) / 2; i++) { cin >> s; sort(s.begin(), s.end()); m[s]++; } if (n == 1) { cout << ! << s << endl; return 0; } cout << ? << 2 << << n << endl; for (int i = 1; i <= (n * (n - 1)) / 2; i++) { cin >> s; sort(s.begin(), s.end()); m[s]--; } auto it = m.begin(); while (it != m.end()) { if (it->second > 0) { pr[(it->first).size()] = (it->first); } it++; } for (int i = n; i >= 1; i--) { for (int j = 0; j < i; j++) { darab[i][pr[i][j] - a ]++; } } string ans = ; for (int i = 1; i <= n; i++) { int kul = 0; for (int j = 0; j < 26; j++) { if (darab[i][j] != darab[i - 1][j]) { kul = j; break; } } ans += ((char)( a + kul)); } cout << ! << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int Maxn = 100010; int ans = -1, ansd, a[Maxn], b[Maxn], n, m; inline int Pow(int x, int y, int mod) { int s = 1; for (; y; y >>= 1, x = 1ll * x * x % mod) if (y & 1) s = 1ll * s * x % mod; return s; } inline bool find(int *a, int n, int x) { int t = lower_bound(a + 1, a + n + 1, x) - a; return a[t] == x; } inline void sol(int *a, int n) { if (n == 1) { ans = a[1], ansd = 1; return; } int tmp = a[2] - a[1], cnt = 0; for (int i = 1; i <= n; i++) if (find(a, n, (a[i] + tmp) % m)) cnt++; ansd = 1ll * tmp * Pow(n - cnt, m - 2, m) % m; int d = (m - ansd) % m; for (int i = 1; i <= n; i++) if (!find(a, n, (a[i] + d) % m)) { if (ans == -1) ans = a[i]; else { ans = -1; return; } } } int main() { scanf( %d%d , &m, &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); if (n == 1 || n == m) return printf( %d %d n , a[1], 1), 0; if (2 * n < m) sol(a, n); else { int t = 0; for (int i = 0; i < m; i++) if (!find(a, n, i)) b[++t] = i; sol(b, t); if (ans != -1) (ans += 1ll * ansd * t % m) %= m; } if (ans == -1) return printf( -1 n ), 0; return printf( %d %d n , ans, ansd), 0; } |
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: afifo.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:41:58 $
// \ \ / \ Date Created: Oct 21 2008
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: A generic synchronous fifo.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module afifo #
(
parameter TCQ = 100,
parameter DSIZE = 32,
parameter FIFO_DEPTH = 16,
parameter ASIZE = 4,
parameter SYNC = 1 // only has always '1' logic.
)
(
input wr_clk,
input rst,
input wr_en,
input [DSIZE-1:0] wr_data,
input rd_en,
input rd_clk,
output [DSIZE-1:0] rd_data,
output reg full,
output reg empty,
output reg almost_full
);
// memory array
reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1];
//Read Capture Logic
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
reg [ASIZE:0] rd_gray_nxt;
reg [ASIZE:0] rd_gray;
reg [ASIZE:0] rd_capture_ptr;
reg [ASIZE:0] pre_rd_capture_gray_ptr;
reg [ASIZE:0] rd_capture_gray_ptr;
reg [ASIZE:0] wr_gray;
reg [ASIZE:0] wr_gray_nxt;
reg [ASIZE:0] wr_capture_ptr;
reg [ASIZE:0] pre_wr_capture_gray_ptr;
reg [ASIZE:0] wr_capture_gray_ptr;
wire [ASIZE:0] buf_avail;
wire [ASIZE:0] buf_filled;
wire [ASIZE-1:0] wr_addr, rd_addr;
reg [ASIZE:0] wr_ptr, rd_ptr;
integer i,j,k;
// for design that use the same clock for both read and write
generate
if (SYNC == 1) begin: RDSYNC
always @ (rd_ptr)
rd_capture_ptr = rd_ptr;
end
endgenerate
//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers
// before do comparison.
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
generate
if (SYNC == 1) begin: WRSYNC
always @ (wr_ptr)
wr_capture_ptr = wr_ptr;
end
endgenerate
// dualport ram
// Memory (RAM) that holds the contents of the FIFO
assign wr_addr = wr_ptr;
assign rd_data = mem[rd_addr];
always @(posedge wr_clk)
begin
if (wr_en && !full)
mem[wr_addr] <= #TCQ wr_data;
end
// Read Side Logic
assign rd_addr = rd_ptr[ASIZE-1:0];
assign rd_strobe = rd_en && !empty;
integer n;
reg [ASIZE:0] rd_ptr_tmp;
// change the binary pointer to gray pointer
always @ (rd_ptr)
begin
// rd_gray_nxt[ASIZE] = rd_ptr_tmp[ASIZE];
// for (n=0; n < ASIZE; n=n+1)
// rd_gray_nxt[n] = rd_ptr_tmp[n] ^ rd_ptr_tmp[n+1];
rd_gray_nxt[ASIZE] = rd_ptr[ASIZE];
for (n=0; n < ASIZE; n=n+1)
rd_gray_nxt[n] = rd_ptr[n] ^ rd_ptr[n+1];
end
always @(posedge rd_clk)
begin
if (rst)
begin
rd_ptr <= #TCQ 'b0;
rd_gray <= #TCQ 'b0;
end
else begin
if (rd_strobe)
rd_ptr <= #TCQ rd_ptr + 1;
rd_ptr_tmp <= #TCQ rd_ptr;
// change the binary pointer to gray pointer
rd_gray <= #TCQ rd_gray_nxt;
end
end
//generate empty signal
assign buf_filled = wr_capture_ptr - rd_ptr;
always @ (posedge rd_clk )
begin
if (rst)
empty <= #TCQ 1'b1;
else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe))
empty <= #TCQ 1'b1;
else
empty <= #TCQ 1'b0;
end
// write side logic;
reg [ASIZE:0] wbin;
wire [ASIZE:0] wgraynext, wbinnext;
always @(posedge rd_clk)
begin
if (rst)
begin
wr_ptr <= #TCQ 'b0;
wr_gray <= #TCQ 'b0;
end
else begin
if (wr_en)
wr_ptr <= #TCQ wr_ptr + 1;
// change the binary pointer to gray pointer
wr_gray <= #TCQ wr_gray_nxt;
end
end
// change the write pointer to gray pointer
always @ (wr_ptr)
begin
wr_gray_nxt[ASIZE] = wr_ptr[ASIZE];
for (n=0; n < ASIZE; n=n+1)
wr_gray_nxt[n] = wr_ptr[n] ^ wr_ptr[n+1];
end
// calculate how many buf still available
assign buf_avail = (rd_capture_ptr + FIFO_DEPTH) - wr_ptr;
always @ (posedge wr_clk )
begin
if (rst)
full <= #TCQ 1'b0;
else if ((buf_avail == 0) || (buf_avail == 1 && wr_en))
full <= #TCQ 1'b1;
else
full <= #TCQ 1'b0;
end
always @ (posedge wr_clk )
begin
if (rst)
almost_full <= #TCQ 1'b0;
else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en))
almost_full <= #TCQ 1'b1;
else
almost_full <= #TCQ 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; int n, m, far[MAXN], a[MAXN]; struct LCT { int fa[MAXN], ch[MAXN][2]; int s[MAXN], xs[MAXN]; long long xs2[MAXN], sum[MAXN], ans[MAXN], xans[MAXN]; bool isroot(int x) { return ch[fa[x]][0] != x && ch[fa[x]][1] != x; } int get(int x) { return ch[fa[x]][1] == x; } void up(int x) { s[x] = s[ch[x][0]] + s[ch[x][1]] + xs[x] + 1; sum[x] = sum[ch[x][0]] + sum[ch[x][1]] + 1ll * a[x] * (xs[x] + 1); ans[x] = ans[ch[x][0]] + ans[ch[x][1]] + xans[x] + a[x] * (1ll * (xs[x] + 1) * (xs[x] + 1) - xs2[x]) + 2ll * a[x] * (xs[x] + 1) * s[ch[x][1]] + 2ll * sum[ch[x][0]] * (s[x] - s[ch[x][0]]); } void rotate(int x) { int f1 = fa[x], f2 = fa[f1], id = get(x); ch[f1][id] = ch[x][id ^ 1]; fa[ch[f1][id]] = f1; if (!isroot(f1)) ch[f2][get(f1)] = x; fa[x] = f2; ch[x][id ^ 1] = f1; fa[f1] = x; up(f1); } void splay(int x) { while (!isroot(x)) { int f1 = fa[x]; if (!isroot(f1)) { if (get(x) == get(f1)) rotate(f1); else rotate(x); } rotate(x); } up(x); } void access(int x) { for (int y = 0; x; y = x, x = fa[x]) { splay(x); xs[x] += s[ch[x][1]] - s[y]; xs2[x] += 1ll * s[ch[x][1]] * s[ch[x][1]] - 1ll * s[y] * s[y]; xans[x] += ans[ch[x][1]] - ans[y]; ch[x][1] = y; up(x); } } void link(int x, int y) { access(x), splay(x); access(y), splay(y); fa[x] = y; xs[y] += s[x]; xans[y] += ans[x]; xs2[y] += 1ll * s[x] * s[x]; up(y); } void cut(int x, int y) { access(y), splay(y); splay(x); fa[x] = 0; xs[y] -= s[x]; xans[y] -= ans[x]; xs2[y] -= 1ll * s[x] * s[x]; up(y); } bool is_anc(int x, int y) { access(y); splay(y), splay(x); return !isroot(y); } long long ask() { splay(1); return ans[1]; } void modify(int x, int v) { access(x), splay(x); a[x] = v, up(x); } } tr; char op[2]; int main() { scanf( %d , &n); for (int i = 2; i <= n; i++) scanf( %d , &far[i]); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) tr.s[i] = 1; for (int i = 2; i <= n; i++) tr.link(i, far[i]); printf( %.10lf n , (double)tr.ask() / n / n); scanf( %d , &m); while (m--) { int x, y; scanf( %s%d%d , op, &x, &y); if (op[0] == P ) { if (tr.is_anc(x, y)) swap(x, y); tr.cut(x, far[x]); far[x] = y; tr.link(x, far[x]); } else tr.modify(x, y); printf( %.10lf n , (double)tr.ask() / n / n); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5 + 5; const int mod = 1e9 + 7; char str[maxn]; long long qp(long long a, long long b) { long long ret = 1; while (b) { if (b & 1) ret = ret * a % mod; a = a * a % mod; b >>= 1; } return ret; } long long inv(long long a) { return qp(a, mod - 2); } void solve(long long); int main() { scanf( %s , str); long long k; cin >> k; solve(k); return 0; } void solve(long long k) { long long n = (long long)strlen(str); long long ans = 0; for (int i = 0; i < n; i++) { if (str[i] == 0 || str[i] == 5 ) { long long tmp = (qp(2, n * k + i) - qp(2, i) + mod) % mod; tmp = tmp * inv(qp(2, n) - 1) % mod; ans = (ans + tmp) % mod; while (ans < 0) ans += mod; } } cout << ans << endl; return; } |
module regfile_16x32b_4rd_2wr(input wire clk,
input wire rst,
input wire [3:0] rdport1_ctrl_add,
output wire [31:0] rdport1_data_out,
input wire [3:0] rdport2_ctrl_add,
output wire [31:0] rdport2_data_out,
input wire [3:0] rdport3_ctrl_add,
output wire [31:0] rdport3_data_out,
input wire [3:0] rdport4_ctrl_add,
output wire [31:0] rdport4_data_out,
input wire [3:0] wrport1_ctrl_add,
input wire [31:0] wrport1_data_in,
input wire wrport1_wren,
input wire [3:0] wrport2_ctrl_add,
input wire [31:0] wrport2_data_in,
input wire wrport2_wren
);
// 16 x 32b register file
reg [31:0] regFile [15:0];
// variables
integer i = 0;
// Read register file
assign rdport1_data_out = regFile[rdport1_ctrl_add];
assign rdport2_data_out = regFile[rdport2_ctrl_add];
assign rdport3_data_out = regFile[rdport3_ctrl_add];
assign rdport4_data_out = regFile[rdport4_ctrl_add];
// Write register file
always @ ( posedge clk )
begin
if( rst )
begin
for( i = 0; i<16; i = i+1 ) regFile[i] <= 0;
end
else
if( wrport1_wren && wrport2_wren )
begin
if( wrport1_ctrl_add == wrport2_ctrl_add )
begin
// in case of write collision, we ignore write on second port
regFile[wrport1_ctrl_add] <= wrport1_data_in;
end
else
begin
// there is no write collision and we can safely write to both wr ports
regFile[wrport1_ctrl_add] <= wrport1_data_in;
regFile[wrport2_ctrl_add] <= wrport2_data_in;
end
end
else
begin
if ( wrport1_wren ) regFile[wrport1_ctrl_add] <= wrport1_data_in;
if ( wrport2_wren ) regFile[wrport1_ctrl_add] <= wrport1_data_in;
end
end
endmodule // regfile_16x32b_4rd_2wr
|
#include <bits/stdc++.h> using namespace std; int n, m; long long int dp[503][5030]; long long int cnt[100100]; long long int fav[100100]; int t[550]; int used[100100]; long long int h[15]; int main() { cin.tie(nullptr); ios::sync_with_stdio(false); cin >> n >> m; for (int i = 0; i < n * m; i++) { int x; cin >> x; cnt[x]++; } for (int i = 0; i < n; i++) { cin >> t[i]; fav[t[i]]++; } for (int i = 0; i < m; i++) { cin >> h[i]; } long long int ans = 0; for (int i = 0; i < n; i++) { if (used[t[i]]) continue; used[t[i]] = 1; cnt[t[i]] = min(cnt[t[i]], fav[t[i]] * (long long int)m); for (int j = 0; j <= fav[t[i]]; j++) { for (int k = 0; k <= cnt[t[i]]; k++) { dp[j][k] = -1e15; } } dp[0][0] = 0; for (int j = 0; j < fav[t[i]]; j++) { for (int k = 0; k <= cnt[t[i]]; k++) { if (dp[j][k] < 0) continue; for (int l = 0; l <= min((int)m, (int)cnt[t[i]] - k); l++) { dp[j + 1][k + l] = max(dp[j + 1][k + l], dp[j][k] + (l == 0 ? 0 : (long long int)h[l - 1])); } } } long long int ma = 0; for (int j = 0; j <= cnt[t[i]]; j++) { ma = max(ma, dp[fav[t[i]]][j]); } ans += ma; } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int MX = 505, mod = 998244353; int n, m; vector<int> c, pos[MX]; long long mem[2 * MX][2 * MX]; bool isValid(int a, int b) { if (a != pos[c[a]][0] && a != pos[c[a]].back()) return 0; if (b != pos[c[b]][0] && b != pos[c[b]].back()) return 0; for (int i = 1; i <= n; i++) if ((a <= pos[i][0] && pos[i][0] <= b) != (a <= pos[i].back() && pos[i].back() <= b)) return 0; return 1; } long long dp(int a, int b) { if (a > b) return 1; long long &res = mem[a][b]; if (res != -1) return res; if (!isValid(a, b)) return res = 0; int mn = c[a]; for (int i = a; i <= b; i++) mn = min(mn, c[i]); int ind = pos[mn][0]; long long x = dp(a, ind - 1); for (int i = a; i < ind; i++) x += dp(a, i) * dp(i + 1, ind - 1) % mod; x %= mod; ind = pos[mn].back(); long long y = dp(ind + 1, b); for (int i = ind + 1; i <= b; i++) y += dp(ind + 1, i) * dp(i + 1, b) % mod; y %= mod; res = 1; for (int i = 0; i + 1 < pos[mn].size(); i++) (res *= dp(pos[mn][i] + 1, pos[mn][i + 1] - 1)) %= mod; (res *= x) %= mod; (res *= y) %= mod; return res; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; c.resize(m); for (int i = 0; i < m; i++) cin >> c[i]; c.erase(unique(c.begin(), c.end()), c.end()); if (c.size() > 2 * n) { cout << 0 << n ; return 0; } m = c.size(); for (int i = 0; i < m; i++) pos[c[i]].emplace_back(i); memset(mem, -1, sizeof(mem)); cout << dp(0, m - 1) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; vector<set<int> > v(n); vector<set<int> > w(n); for (int i = 0; i < m; i++) { int a, b; cin >> a >> b; a--; b--; if (a > b) v[a].insert(b); else v[b].insert(a); if (a > b) w[b].insert(a); else w[a].insert(b); } vector<int> pairs(n), pairs2(n); pairs[0] = v[0].size(); for (int i = 1; i < n; i++) pairs[i] = pairs[i - 1] + v[i].size(); pairs2[n - 1] = 0; for (int i = n - 2; i >= 0; i--) pairs2[i] = pairs2[i + 1] + w[i].size(); long long ans = 0; for (int i = 0; i < n - 1; i++) if (pairs[i] == 0 && pairs2[i + 1] == 0) ans++; cout << ans << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long double n, k; cin >> n >> k; string s; cin >> s; set<string, greater<string> > st; queue<string> stk; stk.push(s); while (k && !stk.empty()) { string temp = stk.front(); stk.pop(); if (st.find(temp) == st.end()) { st.insert(temp); k--; for (long double i = 0; i < temp.length(); i++) { string s1 = temp; s1.erase(s1.begin() + i); if (s1.size()) stk.push(s1); } } } long double ans = 0; if (k == 0 || (k == 1 && stk.empty())) { for (auto i = st.begin(); i != st.end(); i++) { ans += (n - (*i).length()); } if (stk.empty()) ans += n; cout << ans << endl; } else { cout << -1 << endl; } } |
#include <bits/stdc++.h> using namespace std; priority_queue<int, vector<int>, greater<int> > pq; int dp[11][11]; void ini() { int i, j; for (int i = 0; i < 11; i++) for (j = 0; j <= max(i, 10); j++) { if (i == 0) dp[i][j] = 0; else if (i == j || j == 0) dp[i][j] = 1; else if (j == 1) dp[i][j] = i; else dp[i][j] = dp[i - 1][j] + dp[i - 1][j - 1]; } } int main() { ini(); int b, i, n, t, m, sum, x, y; string s1, s2; cin >> s1; cin >> s2; int l = s1.length(); sum = 0; x = 0; y = 0; for (int i = 0; i < l; i++) if (s1[i] == + ) sum++; int sum2 = 0; for (int i = 0; i < l; i++) { if (s2[i] == + ) sum2++; else if (s2[i] == ? ) x++; } int anss = 0; double answ = 0; if (sum - sum2 < 0) answ = 0; else if (sum == sum2 && x == 0) answ = 1; else if (sum != sum2 && x == 0) answ = 0; else { anss = dp[x][sum - sum2]; answ = (double)anss / pow(2, x); } printf( %0.11lf , answ); } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int t; cin >> t; while (t--) { int n, m; cin >> n >> m; string a; cin >> a; int arr[n + 5]; set<int> st; int mark[n + 5]; memset(mark, 0, sizeof mark); for (int i = 0; i < m; i++) { int x; cin >> x; mark[0]++; mark[x]--; } mark[0]++; for (int i = 1; i <= n; i++) { mark[i] += mark[i - 1]; } int ans[28]; memset(ans, 0, sizeof ans); for (int i = 0; i < n; i++) { int x = a[i] - a ; ans[x] += mark[i]; } for (int i = 0; i < 26; i++) { cout << ans[i] << ; } cout << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_4_V
`define SKY130_FD_SC_HS__NAND3B_4_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand3b_4 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand3b_4 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_4_V
|
module packet_builder #(parameter NUM_CHAN = 2)(
// System
input rxclk,
input reset,
input [31:0] timestamp_clock,
input [3:0] channels,
// ADC side
input [15:0]chan_fifodata,
input [NUM_CHAN:0]chan_empty,
input [9:0]chan_usedw,
output reg [3:0]rd_select,
output reg chan_rdreq,
// FX2 side
output reg WR,
output reg [15:0]fifodata,
input have_space,
input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
input wire [31:0]rssi_3, output wire [7:0] debugbus,
input [NUM_CHAN:0] underrun);
// States
`define IDLE 3'd0
`define HEADER1 3'd1
`define HEADER2 3'd2
`define TIMESTAMP 3'd3
`define FORWARD 3'd4
`define MAXPAYLOAD 504
`define PAYLOAD_LEN 8:0
`define TAG 12:9
`define MBZ 15:13
`define CHAN 4:0
`define RSSI 10:5
`define BURST 12:11
`define DROPPED 13
`define UNDERRUN 14
`define OVERRUN 15
reg [NUM_CHAN:0] overrun;
reg [2:0] state;
reg [8:0] read_length;
reg [8:0] payload_len;
reg timestamp_complete;
reg [3:0] check_next;
wire [31:0] true_rssi;
wire [4:0] true_channel;
wire ready_to_send;
assign debugbus = {chan_empty[0], rd_select[0], have_space,
(chan_usedw >= 10'd504), (chan_usedw ==0),
ready_to_send, state[1:0]};
assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
((rd_select[0]) ? rssi_1:rssi_0);
assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
assign ready_to_send = (chan_usedw >= 10'd504) || (chan_usedw == 0) ||
((rd_select == NUM_CHAN)&&(chan_usedw > 0));
always @(posedge rxclk)
begin
if (reset)
begin
overrun <= 0;
WR <= 0;
rd_select <= 0;
chan_rdreq <= 0;
timestamp_complete <= 0;
check_next <= 0;
state <= `IDLE;
end
else case (state)
`IDLE: begin
chan_rdreq <= #1 0;
//check if the channel is full
if(~chan_empty[check_next])
begin
if (have_space)
begin
//transmit if the usb buffer have space
//check if we should send
if (ready_to_send)
state <= #1 `HEADER1;
overrun[check_next] <= 0;
end
else
begin
state <= #1 `IDLE;
overrun[check_next] <= 1;
end
rd_select <= #1 check_next;
end
check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
end
`HEADER1: begin
fifodata[`PAYLOAD_LEN] <= #1 9'd504;
payload_len <= #1 9'd504;
fifodata[`TAG] <= #1 0;
fifodata[`MBZ] <= #1 0;
WR <= #1 1;
state <= #1 `HEADER2;
read_length <= #1 0;
end
`HEADER2: begin
fifodata[`CHAN] <= #1 true_channel;
fifodata[`RSSI] <= #1 true_rssi[5:0];
fifodata[`BURST] <= #1 0;
fifodata[`DROPPED] <= #1 0;
fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel];
fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel];
state <= #1 `TIMESTAMP;
end
`TIMESTAMP: begin
fifodata <= #1 (timestamp_complete ? timestamp_clock[31:16] : timestamp_clock[15:0]);
timestamp_complete <= #1 ~timestamp_complete;
if (~timestamp_complete)
chan_rdreq <= #1 1;
state <= #1 (timestamp_complete ? `FORWARD : `TIMESTAMP);
end
`FORWARD: begin
read_length <= #1 read_length + 9'd2;
fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata);
if (read_length >= `MAXPAYLOAD)
begin
WR <= #1 0;
state <= #1 `IDLE;
chan_rdreq <= #1 0;
end
else if (read_length == payload_len - 4)
chan_rdreq <= #1 0;
end
default: begin
//handling error state
state <= `IDLE;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__A31O_FUNCTIONAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int n, cnt, a[220000]; long long sum; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int l = 1; l <= n; l++) { sum = a[l + 1]; for (int r = l + 2; r <= n; r++) { if (a[l] < a[r]) { sum += a[r]; if (sum > (1 << ((int)log2(a[l]) + 1))) break; continue; } if ((a[l] ^ a[r]) == sum) cnt++; sum += a[r]; if (sum > (1 << ((int)log2(a[l]) + 1))) break; } } reverse(a + 1, a + n + 1); for (int l = 1; l <= n; l++) { sum = a[l + 1]; for (int r = l + 2; r <= n; r++) { if (a[l] <= a[r]) { sum += a[r]; if (sum > (1 << ((int)log2(a[l]) + 1))) break; continue; } if ((a[l] ^ a[r]) == sum) cnt++; sum += a[r]; if (sum > (1 << ((int)log2(a[l]) + 1))) break; } } printf( %d , cnt); return 0; } |
#include <bits/stdc++.h> int main() { long long n, m, i; scanf( %lld%lld , &n, &m); printf( YES n ); for (i = n; i < m; i += 2) printf( %lld %lld n , i, i + 1); printf( n ); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 06/17/2017 06:06:47 PM
// Design Name:
// Module Name: tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb();
reg CLOCK_50;
reg rst;
wire vsync;
wire[11:0] color_out;
wire[7:0] seg_out;
wire[3:0] sel;
wire hsync;
//integer file_output;
initial begin
//file_output = $fopen("D:/Computer Architecture/My-CPU/TestResult/beq.txt");
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = 1'b1;
#195 rst= 1'b0;
# $stop;
end
Small_Program_Top top1(
.clk(CLOCK_50),
.rst(rst),
.left(0),
.right(0),
.up(0),
.down(0),
.hsync(hsync),
.vsync(vsync),
.color_out(color_out),
.seg_out(seg_out),
.sel(sel)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using ull = unsigned long long; const double PI = acos(-1.0); const int EPS = (1e-10); const int N = 1e5 * 2 + 10; const int inf = 1e9 * 2 + 10; const ll INF = 1e18 * 2 + 10; const int MOD = 1e9 + 7; int nxt() { int x; cin >> x; return x; } int fcmp(double a, double b) { return (fabs(a - b) < EPS ? 0 : a > b ? 1 : -1); } int n; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin >> n; int mx = 0, p = 0; for (int i = (1); i <= (n); ++i) { int k, a; cin >> k >> a; mx = max(mx, k); ll s = 1; int m = 0; while (s < a) { s *= 4; m++; } p = max(p, k + m); } if (mx == p) p++; cout << p; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 666; const int inf = 1e9; struct edge { int pr; int to; int cap; } e[111111]; int tot = 1, la[N]; void clr() { tot = 1; memset(la, 0, sizeof(la)); } void adde(int x, int y, int z) { e[++tot].pr = la[x]; la[x] = tot; e[tot].to = y; e[tot].cap = z; } void addf(int x, int y, int z = inf) { adde(x, y, z); adde(y, x, 0); } int d[N]; int bfs(int s, int t) { queue<int> Q; int i, x, y; memset(d, 0, sizeof(d)); d[s] = 1; Q.push(s); while (!Q.empty()) { x = Q.front(); Q.pop(); for (i = la[x]; i; i = e[i].pr) { if (!e[i].cap) continue; y = e[i].to; if (!d[y]) { d[y] = d[x] + 1; Q.push(y); } } } return d[t]; } int dfs(int s, int t, int f) { if (s == t) return f; int i, x, y, r = 0; for (i = la[s]; i; i = e[i].pr) { if (!e[i].cap || !f) continue; y = e[i].to; if (d[y] != d[s] + 1) continue; x = dfs(y, t, min(f, e[i].cap)); if (x) { f -= x; r += x; e[i].cap -= x; e[i ^ 1].cap += x; } } if (!r) d[s] = 0; return r; } int maxflow(int s, int t) { int x, r = 0; while (bfs(s, t)) { x = dfs(s, t, inf); if (x) r += x; else break; } return r; } int vis[N], w[N]; bool hungary(int x) { int i, y; for (i = la[x]; i; i = e[i].pr) { y = e[i].to; if (!vis[y]) { vis[y] = 1; if (!w[y] || hungary(w[y])) { w[y] = x; return true; } } } return false; } int n, a[N][N]; int main() { int i, j, o, s, t, ans; scanf( %d , &n); clr(); for (i = 1; i <= n; i = i + 1) { scanf( %d , &o); while (o--) { scanf( %d , &j); a[i][j] = 1; adde(i, j, 0); } } for (i = 1; i <= n; i = i + 1) { memset(vis, 0, sizeof(vis)); hungary(i); } clr(); s = 0, t = n + 1; for (i = 1; i <= n; i = i + 1) for (j = 1; j <= n; j = j + 1) if (a[i][j]) addf(i, w[j]); ans = 0; for (i = 1; i <= n; i = i + 1) { scanf( %d , &o); if (o > 0) addf(i, t, o); else { ans += o; addf(s, i, -o); } } printf( %d , ans + maxflow(s, t)); return 0; } |
/*
Teak synthesiser for the Balsa language
Copyright (C) 2007-2010 The University of Manchester
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Andrew Bardsley <> (and others, see AUTHORS)
School of Computer Science, The University of Manchester
Oxford Road, MANCHESTER, M13 9PL, UK
*/
/*
example-mapping.v : Teak tech mapping for the `example' technology
*/
// tkg_{and,or,nand,nor}[23] : 2/3 input AND/OR/NAND/NOR gates
module tkg_and2 (output o, input i0, i1);
AND2 I0 (o, i0, i1);
endmodule
module tkg_and3 (output o, input i0, i1, i2);
AND3 I0 (o, i0, i1, i2);
endmodule
module tkg_or2 (output o, input i0, i1);
OR2 I0 (o, i0, i1);
endmodule
module tkg_or3 (output o, input i0, i1, i2);
OR3 I0 (o, i0, i1, i2);
endmodule
module tkg_nand2 (output o, input i0, i1);
NAND2 I0 (o, i0, i1);
endmodule
module tkg_nand3 (output o, input i0, i1, i2);
NAND3 I0 (o, i0, i1, i2);
endmodule
module tkg_nor2 (output o, input i0, i1);
NOR2 I0 (o, i0, i1);
endmodule
module tkg_nor3 (output o, input i0, i1, i2);
NOR3 I0 (o, i0, i1, i2);
endmodule
// tkg_c[23] : 2/3 input symmetric C-elements
module tkg_c2 (output o, input i0, i1);
C2 I0 (o, i0, i1);
endmodule
module tkg_c3 (output o, input i0, i1, i2);
C3 I0 (o, i0, i1, i2);
endmodule
// tkg_c2r1 : 2 input symmetric C-element with active high reset
module tkg_c2r1 (output o, input i0, i1, r);
C2R I0 (o, i0, i1, r);
endmodule
// tkg_c1u1 : asymmetric C-element with one 'symmetric' and one 'up' input
module tkg_c1u1 (output o, input s0, u0);
AO22 I0 (o, s0, u0, s0, o);
endmodule
// tkg_ao22 : AND-OR-22. o = i0&i1 | i2&i3
module tkg_ao22 (output o, input i0, i1, i2, i3);
AO22 I0 (o, i0, i1, i2, i3);
endmodule
// tkg_ao222 : AND-OR-222. o = i0&i1 | i2&i3 | i4&i5
module tkg_ao222 (output o, input i0, i1, i2, i3, i4, i5);
AO222 I0 (o, i0, i1, i2, i3, i4, i5);
endmodule
// tkg_gnd : logic 0 connection
module tkg_gnd (output o);
GND I0 (o);
endmodule
// tkg_inv : inverter
module tkg_inv (output o, input i);
INV I0 (o, i);
endmodule
// tkg_buff : non-inverting logical buffer
module tkg_buff (output o, input i);
BUFF I0 (o, i);
endmodule
// tkg_mutex : mutual exclusion element. ag&bg is never true.
module tkg_mutex (input ar, br, output ag, bg);
MUTEX I0 (ar, br, ag, bg);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); long long t, n, h, i, j, x, y, z, k, e, m; string s; cin >> n >> m; x = 0; for (i = 1; i <= n; i++) { y = i / 5; z = (i + m) / 5; x += (z - y); } cout << x; return 0; } |
`ifndef _MEM_ACCESS
`define _MEM_ACCESS
`include "../misc/mux.v"
`include "../misc/plus_one.v"
`include "../memory/data_mem.v"
module mem_access(IRfrompipe4, IRfrompipe5, RAFromPipe, ALUOut, RAMemSelectInput, wASelectInput, MemData, DataInSelect, WriteMem, RAFromPipeInc, SignalC
, Rfout1, Rfout2, mem_wb_CCR_write, ex_mem_CCR_write);
output [15:0] MemData, RAFromPipeInc;
wire [15:0] DataIn;
input [15:0] ALUOut, RAFromPipe, Rfout1, Rfout2, SignalC, , IRfrompipe5, IRfrompipe4;
input RAMemSelectInput, wASelectInput, WriteMem, DataInSelect, mem_wb_CCR_write, ex_mem_CCR_write;
wire [15:0] readAddSelected, writeAddSelected, DataInSelected;
mux16x2 RASelect(.data0(RAFromPipe), .data1(ALUOut), .selectInput(RAMemSelectInput), .out(readAddSelected));
mux16x2 WASelect(.data0(RAFromPipe), .data1(ALUOut), .selectInput(WAMemSelectInput), .out(writeAddSelected));
mux16x4 DataSelect2(.data0(DataInSelected), .data1(SignalB), .data2(SignalC), .data3(16'b0), .SelectInput(F3), .out(DataIn));
mux16x2 DataSelect1(.data0(Rfout1), .data1(Rfout2), .selectInput(DataInSelect), .out(DataInSelected));
data_mem DataMemory(.readAdd(readAddSelected), .out(MemData), .writeAdd(writeAddSelected), .in(DataIn), .write(WriteMem));
plus_one Inc(.in(RAFromPipe), .out(RAFromPipeInc));
forward_mem_stage(.mem_wb_op(IRfrompipe5[15:12]), .mem_wb_regA(IRfrompipe5[11:9]), .mem_wb_regC(IRfrompipe5[5:3]), .ex_mem_op(IRfrompipe4[15:12]),
.ex_mem_regA(IRfrompipe4[11:9]), .F3(F3) ,mem_wb_CCR_write(mem_wb_CCR_write), .ex_mem_CCR_write(ex_mem_CCR_write));
endmodule
module forward_mem_stage(mem_wb_op,mem_wb_regA,mem_wb_regC,ex_mem_op,ex_mem_regA,F3,mem_wb_CCR_write,ex_mem_CCR_write);
parameter ADD = 6'b000000;
parameter NDU = 6'b001000;
parameter ADC = 6'b000010;
parameter ADZ = 6'b000001;
parameter ADI = 4'b0001;
parameter NDC = 6'b001010;
parameter NDZ = 6'b001001;
parameter LHI = 4'b0011;
parameter LW = 4'b0100;
parameter SW = 4'b0101;
parameter LM = 4'b0110;
parameter SM = 4'b0111;
parameter BEQ = 4'b1100;
parameter JAL = 4'b1000;
parameter JLR = 4'b1001;
input [2:0] mem_wb_regA,mem_wb_regC,ex_mem_regA;
input [5:0]mem_wb_op,ex_mem_op;
input mem_wb_CCR_write,ex_mem_CCR_write;
output reg [1:0]F3;
always @(*)
begin
if(ex_mem_op[5:2]==SW)
begin
if((ex_mem_regA == mem_wb_regC)&&(mem_wb_op==ADD||mem_wb_op==NDU||mem_wb_op==ADC||mem_wb_op==ADZ
||mem_wb_op==NDC||mem_wb_op==NDZ)&&(mem_wb_CCR_write==1'b0))
F3 = 2'd1;//b
else if((ex_mem_regA==mem_wb_regA)&&(mem_wb_op[5:2]==LW))
F3 = 2'd2;//c
else
F3 = 2'b0;
end
else
F3 = 2'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:20:43 02/02/2015
// Design Name:
// Module Name: sha256_W
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sha256_W (
input clk,
input load_i,
input busy_i,
input [511:0] data_i,
output [31:0] W_o
);
`define DATA_IDX(x) data_i[512 - (x * 32) - 1:512 - (x * 32) - 32]
reg [31:0] W[15:0];
reg [31:0] W_new00, W_new01, W_new02, W_new03, W_new04, W_new05, W_new06, W_new07;
reg [31:0] W_new08, W_new09, W_new10, W_new11, W_new12, W_new13, W_new14, W_new15;
reg [31:0] W_new;
reg [31:0] h0, h1, h0_new, h1_new;
always @(posedge clk)
begin
W[ 0] <= W_new00;
W[ 1] <= W_new01;
W[ 2] <= W_new02;
W[ 3] <= W_new03;
W[ 4] <= W_new04;
W[ 5] <= W_new05;
W[ 6] <= W_new06;
W[ 7] <= W_new07;
W[ 8] <= W_new08;
W[ 9] <= W_new09;
W[10] <= W_new10;
W[11] <= W_new11;
W[12] <= W_new12;
W[13] <= W_new13;
W[14] <= W_new14;
W[15] <= W_new15;
h0 <= h0_new;
h1 <= h1_new;
end
assign W_o = W[0];
always @*
begin : W_update
reg [31:0] w_0, w_1, w_9, w_14, d0, d1;
W_new00 = 0;
W_new01 = 0;
W_new02 = 0;
W_new03 = 0;
W_new04 = 0;
W_new05 = 0;
W_new06 = 0;
W_new07 = 0;
W_new08 = 0;
W_new09 = 0;
W_new10 = 0;
W_new11 = 0;
W_new12 = 0;
W_new13 = 0;
W_new14 = 0;
W_new15 = 0;
w_0 = W[1];
w_1 = W[2];
w_9 = W[10];
w_14 = W[15];
W_new = h0 + h1;
if(load_i)
begin
W_new00 = `DATA_IDX( 0);
W_new01 = `DATA_IDX( 1);
W_new02 = `DATA_IDX( 2);
W_new03 = `DATA_IDX( 3);
W_new04 = `DATA_IDX( 4);
W_new05 = `DATA_IDX( 5);
W_new06 = `DATA_IDX( 6);
W_new07 = `DATA_IDX( 7);
W_new08 = `DATA_IDX( 8);
W_new09 = `DATA_IDX( 9);
W_new10 = `DATA_IDX(10);
W_new11 = `DATA_IDX(11);
W_new12 = `DATA_IDX(12);
W_new13 = `DATA_IDX(13);
W_new14 = `DATA_IDX(14);
W_new15 = `DATA_IDX(15);
w_0 = `DATA_IDX(0);
w_1 = `DATA_IDX(1);
w_9 = `DATA_IDX(9);
w_14 = `DATA_IDX(14);
end
else if(busy_i)
begin
W_new00 = W[ 1];
W_new01 = W[ 2];
W_new02 = W[ 3];
W_new03 = W[ 4];
W_new04 = W[ 5];
W_new05 = W[ 6];
W_new06 = W[ 7];
W_new07 = W[ 8];
W_new08 = W[ 9];
W_new09 = W[10];
W_new10 = W[11];
W_new11 = W[12];
W_new12 = W[13];
W_new13 = W[14];
W_new14 = W[15];
W_new15 = W_new;
end
d0 = {w_1[ 6: 0], w_1[31: 7]} ^ {w_1[17: 0], w_1[31:18]} ^ {3'h0, w_1[31: 3]};
d1 = {w_14[16: 0], w_14[31:17]} ^ {w_14[18: 0], w_14[31:19]} ^ {10'h0, w_14[31:10]};
h0_new = d0 + w_0;
h1_new = d1 + w_9;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 85; double l[N], r[N], ans[N][N], ago[N], now[N], dp[N][N]; int main() { vector<double> g; int n; scanf( %d , &n); for (int i = 1; i <= n; ++i) { scanf( %lf%lf , &l[i], &r[i]); g.push_back(l[i]), g.push_back(r[i]); } sort(g.begin(), g.end()); g.erase(unique(g.begin(), g.end()), g.end()); vector<pair<double, double> > p; for (int i = 0; i < g.size() - 1; ++i) p.push_back(make_pair(g[i], g[i + 1])); for (int t = 0; t < p.size(); ++t) { for (int i = 1; i <= n; ++i) { double L = p[t].first, R = p[t].second; if (!(l[i] >= R || r[i] <= L)) { for (int j = 0; j <= n; ++j) for (int k = 0; k <= n; ++k) dp[j][k] = 0.0; dp[0][0] = 1.0; int cnt = 0; vector<int> used; for (int k = 1; k <= n; ++k) { if (l[k] >= R || r[k] <= L) { now[k] = 0.0; if (r[k] <= L) cnt++; } else now[k] = (R - L) / (r[k] - l[k]), used.push_back(k); } int m = used.size(); for (int _ = 0; _ < m; ++_) { int x = used[_]; if (x == i) continue; for (int k = _ + 1; k >= 0; --k) for (int o = _ + 1 - k; o >= 0; --o) { dp[k + 1][o] += dp[k][o] * ago[x]; dp[k][o + 1] += dp[k][o] * now[x]; dp[k][o] *= 1.0 - now[x] - ago[x]; } } for (int j = 0; j < m; ++j) for (int k = 0; k < m - j; ++k) { ans[i][cnt + j] += dp[j][k] * now[i] / (1 + k); ans[i][cnt + j + k + 1] -= dp[j][k] * now[i] / (1 + k); } } } for (int i = 1; i <= n; ++i) ago[i] += now[i]; } for (int i = 1; i <= n; ++i) { for (int j = 0; j < n; ++j) { if (j) { ans[i][j] += ans[i][j - 1]; } printf( %.12f%c , ans[i][j], j == n - 1 ? n : ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int f[10001]; int main() { int a, b = -99999, c = 0; cin >> a; for (int i = 1; i <= a; i++) cin >> f[i]; for (int i = 1; i <= a; i++) b = max(b, f[i]); for (int i = 1; i <= a; i++) c += (b - f[i]); cout << c << endl; return 0; } |
`timescale 1 ns / 1 ps
`default_nettype none
`define WIDTH 16
module j1a(input wire clk,
input wire resetq,
output wire uart0_wr,
output wire uart0_rd,
output wire [7:0] uart_w,
input wire uart0_valid,
input wire [7:0] uart0_data
);
wire io_rd, io_wr;
wire [15:0] mem_addr;
wire mem_wr;
wire [15:0] dout;
wire [15:0] io_din;
/* verilator lint_off UNUSED */
wire [12:0] code_addr;
/* verilator lint_on UNUSED */
wire [15:0] insn;
reg [15:0] ram_prog[0:4095] /* verilator public_flat */;
always @(posedge clk) begin
// $display("pc=%x", code_addr * 2);
insn <= ram_prog[code_addr[11:0]];
if (mem_wr)
ram_prog[mem_addr[12:1]] <= dout;
end
j1 _j1(
.clk(clk),
.resetq(resetq),
.io_rd(io_rd),
.io_wr(io_wr),
.mem_wr(mem_wr),
.dout(dout),
.io_din(io_din),
.mem_addr(mem_addr),
.code_addr(code_addr),
.insn(insn));
// ###### IO SIGNALS ####################################
reg io_wr_, io_rd_;
/* verilator lint_off UNUSED */
reg [15:0] dout_;
reg [15:0] io_addr_;
/* verilator lint_on UNUSED */
always @(posedge clk) begin
{io_rd_, io_wr_, dout_} <= {io_rd, io_wr, dout};
if (io_rd | io_wr)
io_addr_ <= mem_addr;
end
// ###### UART ##########################################
wire uart0_wr = io_wr_ & io_addr_[12];
wire uart0_rd = io_rd_ & io_addr_[12];
assign uart_w = dout_[7:0];
// always @(posedge clk) begin
// if (uart0_wr)
// $display("--- out %x %c", uart_w, uart_w);
// if (uart0_rd)
// $display("--- in %x %c", uart0_data, uart0_data);
// end
// ###### IO PORTS ######################################
/* bit READ WRITE
1000 12 UART RX UART TX
2000 13 misc.in
*/
assign io_din =
(io_addr_[12] ? {8'd0, uart0_data} : 16'd0) |
(io_addr_[13] ? {12'd0, 1'b0, 1'b0, uart0_valid, 1'b1} : 16'd0);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1e2 + 10; const long long mod = 1e9 + 7; const long long INF = 1e9; inline long long bpow(long long t, long long n) { long long ans = 1; while (n > 0) { if (n & 1) ans = (ans * t) % mod; t = (t * t) % mod, n >>= 1; } return ans; } int a[MAX_N][MAX_N]; int row[MAX_N]; int col[MAX_N]; int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cout << fixed << setprecision(0); int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) cin >> a[i][j]; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) row[i] += a[i][j], col[j] += a[i][j]; long long ans = 0; for (int i = 1; i <= n; i++) ans += (1ll << row[i]) - 1 + (1ll << (m - row[i])) - 1; for (int j = 1; j <= m; j++) ans += (1ll << col[j]) - 1 + (1ll << (n - col[j])) - 1; ans -= n * m; cout << ans; } |
#include <bits/stdc++.h> using namespace std; char getc() { char c = getchar(); while ((c < A || c > Z ) && (c < a || c > z ) && (c < 0 || c > 9 )) c = getchar(); return c; } int gcd(int n, int m) { return m == 0 ? n : gcd(m, n % m); } int read() { int x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); return x * f; } int n, k, a[5010], f[5010][5010], ans; int ksm(int a, int k) { int s = 1; for (; k; k >>= 1, a = 1ll * a * a % 1000000007) if (k & 1) s = 1ll * s * a % 1000000007; return s; } int inv(int a) { return ksm(a, 1000000007 - 2); } void inc(int &x, int y) { x += y; if (x >= 1000000007) x -= 1000000007; } signed main() { const char LL[] = %lld n ; n = read(), k = read(); for (int i = 1; i <= n; i++) a[i] = read(); f[0][0] = 1; for (int i = 1; i <= n; i++) { f[i][0] = 1ll * f[i - 1][0] * a[i] % 1000000007; for (int j = 1; j <= i; j++) f[i][j] = (1ll * f[i - 1][j] * a[i] - f[i - 1][j - 1] + 1000000007) % 1000000007; } int s = 1; for (int i = 0; i <= min(k, n); i++) { inc(ans, 1ll * ksm(n, k - i) * f[n][i] % 1000000007 * s % 1000000007); s = 1ll * s * (k - i) % 1000000007; } ans = 1ll * ans * inv(ksm(n, k)) % 1000000007; ans = (f[n][0] - ans + 1000000007) % 1000000007; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 105; int freq[N]; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, m; cin >> n >> m; for (int i = 0; i < m; i++) { int type; cin >> type; freq[type]++; } int start = 1, end = 100; while (start <= end) { int mid = (start + end) >> 1; int persons = 0; for (int types = 1; types <= 100; types++) { persons += (freq[types] / mid); } if (persons >= n) start = mid + 1; else end = mid - 1; } cout << end << n ; return 0; } |
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31;
parameter DATA_DEPTH = 128;
parameter AW = 6;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data),
// Unused
// synopsys translate_off
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
// DEFINES
`define BITS 8 // Bit width of the operands
`define B2TS 16 // Bit width of the operands
`define USEAND 0 // No available documentation provides for macros without values so we use 0
module bm_base_multiply(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
e_in,
f_in,
out0,
out2,
out3,
out4,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input [`BITS-1:0] c_in;
input [`BITS-1:0] d_in;
input [`BITS-1:0] e_in;
input [`BITS-2:0] f_in;
output [`B2TS-1:0] out0;
output [`B2TS-1:0] out1;
output [`B2TS-1:0] out2;
output [14:0] out3;
output [14:0] out4;
reg [`B2TS-1:0] out0;
wire [`B2TS-1:0] out1;
reg [`B2TS-1:0] out2;
reg [14:0] out3;
wire [14:0] out4;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, b_in, temp_a);
b top_b(clock, a_in, b_in, temp_b);
always @(posedge clock)
begin
out0 <= a_in * b_in;
out2 <= temp_a & temp_b;
out3 <= e_in * f_in;
end
assign out1 = c_in * d_in;
assign out4 = f_in * e_in;
endmodule
`ifndef USEAND
`include "ifndef_else_module_a_and.v"
`else
`include "ifndef_else_module_a_or.v"
`endif
`include "ifndef_else_module_b.v"
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; const long long M = (long long)1e9 + 7; int Int() { int x; scanf( %d , &x); return x; } long long Long() { long long x; scanf( %lld , &x); return x; } void Char(char *ch) { scanf( %s , ch); } template <typename t> inline t abs(t a) { if (a >= 0) return a; return -a; } template <typename T> inline T modpow(T b, T p, T Mod) { T res = 1; while (p) { if (p & 1) { res *= b; res %= Mod; } b *= b; b %= Mod; p >>= 1; } return res; } template <typename T> inline T ModInv(T b, T Mod) { return modpow(b, Mod - 2, Mod); } template <typename T> inline T pwr(T b, T p) { T res = 1; while (p) { if (p & 1) { res *= b; } b *= b; p >>= 1; } return res; } template <typename T> inline T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <typename T> inline void Int(T &n) { n = 0; int f = 1; register int ch = getchar(); for (; !isdigit(ch); ch = getchar()) if (ch == - ) f = -1; for (; isdigit(ch); ch = getchar()) n = (n << 3) + (n << 1) + ch - 0 ; n = n * f; } template <typename T, typename U> inline void Int(T &a, U &b) { Int(a); Int(b); } template <typename T, typename U, typename W> inline void Int(T &a, U &b, W &c) { Int(a, b); Int(c); } template <typename T, typename U, typename W, typename X> inline void Int(T &a, U &b, W &c, X &d) { Int(a, b, c); Int(d); } vector<int> Unique(vector<int> v) { sort(v.begin(), v.end()); v.erase(unique(v.begin(), v.end()), v.end()); return v; } vector<string> split(const string &s, char c) { vector<string> v; stringstream ss(s); string x; while (getline(ss, x, c)) v.emplace_back(x); return move(v); } void err(vector<string>::iterator it) {} template <typename T, typename... Args> void err(vector<string>::iterator it, T a, Args... args) { cout << it->substr((*it)[0] == , it->length()) << = << a << ; err(++it, args...); } struct node { int cnt; node *tree[2]; node() { cnt = 0; tree[0] = tree[1] = NULL; } } * root; void add(int x) { node *cur = root; for (int i = 30; i >= 0; i--) { int f = (bool)(x & (1 << i)); if (cur->tree[f] == NULL) { cur->tree[f] = new node(); } cur = cur->tree[f]; cur->cnt++; } } int sum(int x, int k) { int res = 0; node *cur = root; for (int i = 30; i >= 0; i--) { int p = (bool)(x & (1 << i)); int q = (bool)(k & (1 << i)); if (q == 0) { if (p == 1) { if (cur->tree[1] != NULL) { cur = cur->tree[1]; } else { return res; } } else { if (cur->tree[0] != NULL) { cur = cur->tree[0]; } else { return res; } } } else { if (p == 1) { if (cur->tree[1] != NULL) res += cur->tree[1]->cnt; if (cur->tree[0] != NULL) { cur = cur->tree[0]; } else { return res; } } else { if (cur->tree[0] != NULL) res += cur->tree[0]->cnt; if (cur->tree[1] != NULL) { cur = cur->tree[1]; } else { return res; } } } } return res; } int a[N]; int main() { int t = 1, tc = 0; while (t--) { root = new node(); int n = Int(), k = Int(); long long res = 0; add(0); for (int i = 1; i <= n; i++) { a[i] = Int(); a[i] ^= a[i - 1]; res += sum(a[i], k); add(a[i]); } long long s = (1LL * n * (n + 1LL)) / 2LL; printf( %lld n , s - res); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int a[200005]; vector<long long int> g[200005]; vector<long long int> c[200005]; multiset<long long int> st[200005]; long long int idx[200005], toAdd[200005], ans[200005]; void mergeTree(long long int id1, long long int id2) { multiset<long long int>::iterator it; long long int x; for (it = st[id2].begin(); it != st[id2].end(); it++) { x = *it + toAdd[id2] - toAdd[id1]; st[id1].insert(x); } return; } void dfs(long long int u) { idx[u] = u; long long int i, j, k, mx; mx = st[idx[u]].size(); long long int id = idx[u]; for (i = 0; i < g[u].size(); i++) { long long int v = g[u][i]; dfs(v); if (st[idx[v]].size() > mx) { mx = st[idx[v]].size(); id = idx[v]; } toAdd[idx[v]] -= c[u][i]; } idx[u] = id; for (i = 0; i < g[u].size(); i++) { long long int v = g[u][i]; if (id != idx[v]) mergeTree(id, idx[v]); st[id].insert((a[v] - c[u][i]) - toAdd[id]); } multiset<long long int>::iterator it; while (!st[id].empty()) { it = st[id].begin(); if ((*it + toAdd[id]) < 0) st[id].erase(it); else break; } ans[u] = (long long int)st[id].size(); return; } int main() { long long int i, j, k, l, m, n; cin >> n; for (i = 1; i <= n; i++) scanf( %lld , &a[i]); for (i = 2; i <= n; i++) { scanf( %lld %lld , &k, &l); g[k].push_back(i); c[k].push_back(l); } memset(toAdd, 0, sizeof(toAdd)); dfs(1); for (i = 1; i <= n; i++) { printf( %lld , ans[i]); if (i < n) printf( ); else printf( n ); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t ();
sub a (.inst(1));
sub b (.inst(2));
initial begin
a.test1;
b.test1;
a.test2;
b.test2;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub (input integer inst);
import "DPI-C" context function int dpic_line();
import "DPI-C" context function int dpic_save(int value);
import "DPI-C" context function int dpic_restore();
int result;
task test1;
// Check line numbering
`ifndef verilator // Not all sims support SV2009 `__LINE__, and some that do fail the specific-line test
result = dpic_line(); if (!result) $stop;
`else
result = dpic_line(); if (result !== `__LINE__) $stop;
//
result = dpic_line(); if (result !== `__LINE__) $stop;
`endif
// Check save-restore
result = dpic_save(23+inst);
if (result==0) $stop;
endtask
task test2;
if (dpic_restore() != 23+inst) $stop;
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; int main() { char s1[15], s2[15], s3[15]; int p[15]; scanf( %s%s , s1, s2); int len = strlen(s1); int pos = 0; for (int i = 0; i < len; i++) { if (s1[i] == + ) pos++; else pos--; } int cnt = 0; for (int i = 0; i < len; i++) if (s2[i] == ? ) p[cnt++] = i; int m = 1 << cnt, ans = 0; for (int i = 0; i < m; i++) { int k = i, u = 0; strcpy(s3, s2); for (int j = 0; j < cnt; j++) { if (k & 1) s3[p[u]] = + ; else s3[p[u]] = - ; k >>= 1; u++; } int w = 0; for (int j = 0; j < len; j++) { if (s3[j] == + ) w++; else w--; } if (w == pos) ans++; } printf( %.12f n , ans * 1.0 / m); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, ans, dp[105], a[105]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); if (n % 2 == 0 || n == 1) { printf( -1 ); return 0; } for (int i = n; i >= 2; i--) { ans += max(a[i], a[i - 1]); a[(i - 1) / 2] -= min(a[(i - 1) / 2], max(a[i], a[i - 1])); i--; } printf( %d , ans + a[1]); } |
/*
** Copyright (C) 2015 Klaus Rudolph <>
**
** This program is free software; you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation; either version 2 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License along
** with this program; if not, write to the Free Software Foundation, Inc.,
** 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA..
**
*/
`timescale 1ns / 1ns
module test;
wire clk1;
wire clk2;
wire [7:0] pb, pc, pd; // dummy only;
wire sum; // signal is connected 2 pin PA0 from both devices under test
wire out1;
wire out2;
wire mirror1;
wire mirror2;
wire driver_enabled1;
wire driver_enabled2;
wire logic_level1;
wire logic_level2;
wire unused;
defparam avr1.progfile="vst.elf";
defparam avr2.progfile="vst.elf";
ATmega32 avr1(clk1, { dummy, dummy, logic_level1, driver_enabled1, mirror1, sum, out1, sum}, pb, pc, pd);
ATmega32 avr2(clk2, { dummy, dummy, logic_level2, driver_enabled2, mirror2, sum, out2, sum}, pb, pc, pd);
// now lets get to clocks a bit shifted against each other
reg clkr1=1;
reg clkr2=1;
assign clk1 = clkr1;
assign clk2 = clkr2;
always begin
#10 clkr1 =~clkr1;
end
always begin
#5 clkr2 = ~clkr2;
end
initial begin
$display( "Core Number %d", avr1.core.handle );
$display( "Core Number %d", avr2.core.handle );
end
initial begin
//$avr_trace("avr.trace");
$dumpfile("vst.vcd");
$dumpvars(0, test);
#100_000 $finish;
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ab
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ab.v,v 1.6 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_ab.v,v $
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ab
//
// No user `defines in this module
module ent_ab
//
// Generated Module inst_ab
//
(
port_ab_1, // Use internally test1
port_ab_2, // Use internally test2, no port generated
sig_13, // Create internal signal name
sig_14 // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// Generated Module Inputs:
input port_ab_1;
input [4:0] sig_13;
input [6:0] sig_14;
// Generated Module Outputs:
output port_ab_2;
// Generated Wires:
wire port_ab_1;
wire port_ab_2;
wire [4:0] sig_13;
wire [6:0] sig_14;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ab
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; int i, j, n; void write(int X) { if (X < 0) putchar( - ), X = -X; if (X > 9) write(X / 10); putchar(X % 10 | 48); } void print(int k) { int h; for (h = 1; h <= (4); h++) { write(((i - 1) << 2) + h); putchar( ); write(((j - 1) << 2) + (!((h + k) % 4) ? 4 : (h + k) % 4)); putchar( n ); } } int main() { cin >> n; if (n % 4 == 2 || n % 4 == 3) puts( NO ), exit(0); puts( YES ); for (i = 1; i <= (n >> 2); i++) { if (n % 4 == 1) { write(((i - 1) << 2) + 1); putchar( ); write(n); putchar( n ); } write(((i - 1) << 2) + 1); putchar( ); write(((i - 1) << 2) + 3); putchar( n ); if (n % 4 == 1) { write(((i - 1) << 2) + 3); putchar( ); write(n); putchar( n ); } if (n % 4 == 1) { write(((i - 1) << 2) + 2); putchar( ); write(n); putchar( n ); } write(((i - 1) << 2) + 2); putchar( ); write(((i - 1) << 2) + 4); putchar( n ); if (n % 4 == 1) { write(((i - 1) << 2) + 4); putchar( ); write(n); putchar( n ); } write(((i - 1) << 2) + 1); putchar( ); write(((i - 1) << 2) + 2); putchar( n ); write(((i - 1) << 2) + 3); putchar( ); write(((i - 1) << 2) + 4); putchar( n ); write(((i - 1) << 2) + 2); putchar( ); write(((i - 1) << 2) + 3); putchar( n ); write(((i - 1) << 2) + 1); putchar( ); write(((i - 1) << 2) + 4); putchar( n ); } for (i = 1; i <= ((n >> 2) - 1); i++) for (j = i + 1; j <= (n >> 2); j++) { print(2), print(1); print(3), print(0); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int n, m; cin >> n >> m; long long int s = 0, x, y, i, j; vector<long long int> a, b; for (i = 0; i < n; i++) { cin >> x; if (x < 0) a.push_back(x); else b.push_back(x); } sort(a.begin(), a.end()); sort(b.begin(), b.end()); if (a.size() > 0 && b.size() > 0) { if (abs(a[0]) > b[b.size() - 1]) { s += abs(a[0]); for (i = m; i < a.size(); i += m) s += abs(2 * a[i]); for (i = b.size() - 1; i >= 0; i -= m) s += (2 * b[i]); } else { s += b[b.size() - 1]; for (i = b.size() - 1 - m; i >= 0; i -= m) s += (2 * b[i]); for (i = 0; i < a.size(); i += m) s += abs(2 * a[i]); } } else if (a.size() > 0) { s += abs(a[0]); for (i = m; i < a.size(); i += m) s += abs(2 * a[i]); } else { s += b[b.size() - 1]; for (i = b.size() - 1 - m; i >= 0; i -= m) s += (2 * b[i]); } cout << s << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int k; scanf( %d , &k); if (k % 2 == 1) { printf( -1 n ); return 0; } char a[k][k]; memset(a, 0, sizeof(a)); for (int layer = 0; layer < k / 2; layer++) { char c; if (layer % 2) c = w ; else c = b ; for (int runner = layer; runner < k - layer; runner++) a[runner][layer] = a[layer][runner] = a[runner][k - layer - 1] = a[k - layer - 1][runner] = c; } for (int i = 0; i < k; i++) for (int j = 0; j < k; j++) { for (int l = 0; l < k; l++) if (i % 2) if (a[j][l] == w ) printf( b ); else printf( w ); else printf( %c , a[j][l]); printf( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int max_n = 2e5 + 10; int n, temp; vector<int> ans; int main() { ios_base::sync_with_stdio(false), cin.tie(0); cin >> n; for (int i = 0; i < n; i++) { cin >> temp; int pos = lower_bound(ans.begin(), ans.end(), temp) - ans.begin(); if (pos == ans.size()) ans.push_back(temp); else ans[pos] = temp; } cout << ans.size() << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0; bool f = false; char ch = getchar(); while (!isdigit(ch)) { f |= ch == - ; ch = getchar(); } while (isdigit(ch)) { x = (x << 3) + (x << 1) + (ch ^ 48); ch = getchar(); } return f ? -x : x; } void write(int x) { if (x < 0) putchar( - ), x = -x; if (x > 9) write(x / 10); putchar(x % 10 + 48); } const int N = 2505, INF = 0x7fffffff; int n; int a[N][N]; int fa[N], d[N]; bool vis[N]; inline void prim() { for (int i = 2; i <= n; i++) fa[i] = 1, d[i] = a[1][i]; memset(vis, false, sizeof(vis)); vis[1] = true; int k, minn; for (int tot = 2; tot <= n; tot++) { minn = INF; for (int i = 1; i <= n; i++) if (minn > d[i] && !vis[i]) minn = d[i], k = i; vis[k] = true; for (int i = 1; i <= n; i++) if (a[k][i] < d[i] && !vis[i]) d[i] = a[k][i], fa[i] = k; } } int dep[N]; void getdep(int x) { if (!dep[fa[x]]) getdep(fa[x]); dep[x] = dep[fa[x]] + 1; } int main() { n = read(); for (register int i = 1; i <= n; i++) for (register int j = 1; j <= n; j++) a[i][j] = read(); for (register int i = 1; i <= n; i++) if (a[i][i]) return puts( NOT MAGIC ), 0; for (register int i = 1; i <= n; i++) for (register int j = i + 1; j <= n; j++) if (a[i][j] != a[j][i]) return puts( NOT MAGIC ), 0; prim(); dep[1] = 1; for (register int i = 2; i <= n; i++) if (!dep[i]) getdep(i); for (register int i = 1; i <= n; i++) for (register int j = i + 1; j <= n; j++) { int x = i, y = j; if (dep[x] < dep[y]) swap(x, y); if (a[x][y] > max(a[fa[x]][y], a[fa[x]][x])) return puts( NOT MAGIC ), 0; } return puts( MAGIC ), 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_axi_basic_rx.v
// Version : 1.11
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_11_0_axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [KEEP_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_11_0_axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
pcie_7x_v1_11_0_axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A222OI_TB_V
`define SKY130_FD_SC_HD__A222OI_TB_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a222oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg C2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
C2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 C2 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A1 = 1'b1;
#240 A2 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 C1 = 1'b1;
#320 C2 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A1 = 1'b0;
#440 A2 = 1'b0;
#460 B1 = 1'b0;
#480 B2 = 1'b0;
#500 C1 = 1'b0;
#520 C2 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 C2 = 1'b1;
#720 C1 = 1'b1;
#740 B2 = 1'b1;
#760 B1 = 1'b1;
#780 A2 = 1'b1;
#800 A1 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 C2 = 1'bx;
#920 C1 = 1'bx;
#940 B2 = 1'bx;
#960 B1 = 1'bx;
#980 A2 = 1'bx;
#1000 A1 = 1'bx;
end
sky130_fd_sc_hd__a222oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A222OI_TB_V
|
//==================================================================================================
// Filename : FSM_input_enable.v
// Created On : 2016-09-21 00:26:00
// Last Modified : 2016-09-25 21:37:40
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email :
//
// Description : FSM controlling the initialization and input of the operands and the
// desired operation
//
//==================================================================================================
`timescale 1ns / 1ps
module FSM_INPUT_ENABLE(
//INPUTS
input wire clk,
input wire rst,
input wire init_OPERATION,
output reg enable_input_internal,
//output enable for the first stage of the pipeline
output wire enable_Pipeline_input,
output reg enable_shift_reg
);
////////States///////////
//Zero Phase
parameter [3:0] State0 = 3'd0,
State1 = 3'd1,
State2 = 3'd2,
State3 = 3'd3,
State4 = 3'd4,
State5= 3'd5,
State6 = 3'd6,
State7 = 3'd7;
//State registers
reg [2:0] state_reg, state_next;
//State registers reset and standby logic
always @(posedge clk, posedge rst)
if(rst)
state_reg <= State0;
else
state_reg <= state_next;
//Transition and Output Logic
always @*
begin
//DEFAULT INITIAL VALUES
//STATE DEFAULT BEHAVIOR
state_next = state_reg; //If no changes, keep the value of the register unaltered
enable_input_internal=1; //It is internal because its an intermediary value
enable_shift_reg = 0;
case(state_reg)
State0:
begin
//OUTPUT SIGNAL
enable_input_internal=1;
enable_shift_reg = 0;
//NEXT STATE
if(init_OPERATION)
state_next = State1; //JUMP TO NEXT STATE
else begin
state_next = State0; //STAY
end
end
State1:
begin
//OUTPUT SIGNAL
enable_input_internal=1;
enable_shift_reg = 1;
//NEXT STATE
state_next = State2;
end
State2:
begin
//OUTPUT SIGNAL
enable_input_internal=1;
enable_shift_reg = 1;
//NEXT STATE
state_next = State3;
end
State3:
begin
//OUTPUT SIGNAL
enable_input_internal=0;
enable_shift_reg = 1;
//NEXT STATE
state_next = State4;
end
State4:
begin
//OUTPUT SIGNAL
enable_input_internal=0;
enable_shift_reg = 1;
//NEXT STATE
state_next = State5;
end
State5:
begin
//OUTPUT SIGNAL
enable_input_internal=0;
enable_shift_reg = 1;
//NEXT STATE
state_next = State0;
end
// State6:
// begin
// //OUTPUT SIGNAL
// enable_input_internal=0;
// enable_shift_reg = 1;
// //NEXT STATE
// state_next = State7;
// end
// State7:
// begin
// //OUTPUT SIGNAL
// enable_input_internal=0;
// enable_shift_reg = 1;
// //NEXT STATE
// state_next = State0;
// end
default:
begin
state_next =State0;
end
endcase
end
assign enable_Pipeline_input = enable_input_internal & init_OPERATION;
endmodule
|
#include <bits/stdc++.h> using namespace std; int inf = 1000000000, mxx, mxy, mnx = inf, mny = inf, n, m, i, j, r = 0, x[2000001], y[2000001]; char a[3001][3001], c[3001][3001]; bool ok(int mxx, int mxy, int mnx, int mny) { for (int i = 0; i < r; i++) if (x[i] < mnx || x[i] > mxx || y[i] < mny || y[i] > mxy || (x[i] != mxx && x[i] != mnx && y[i] != mxy && y[i] != mny)) return false; return (mxx - mnx == mxy - mny && mxx < n && mxy < m && mnx >= 0 && mny >= 0); } void go(int mxx, int mxy, int mnx, int mny) { int i, j; for (i = 0; i < n; i++) for (j = 0; j < m; j++) { if (i >= mnx && i <= mxx && j >= mny && j <= mxy && ((i == mxx || i == mnx) || (j == mxy || j == mny)) && a[i][j] != w ) c[i][j] = + ; else c[i][j] = a[i][j]; } } int main() { cin >> n >> m; for (i = 0; i < n; i++) for (j = 0; j < m; j++) { cin >> a[i][j]; if (a[i][j] == w ) { x[r] = i; y[r] = j; r++; } } for (i = 0; i < r; i++) { if (x[i] > mxx) mxx = x[i]; if (y[i] > mxy) mxy = y[i]; if (x[i] < mnx) mnx = x[i]; if (y[i] < mny) mny = y[i]; } for (i = 0; i <= m; i++) { if (ok(mxx, i + (mxx - mnx), mnx, i)) { go(mxx, i + (mxx - mnx), mnx, i); for (i = 0; i < n; i++) for (j = 0; j < m; j++) { cout << c[i][j]; if (j == m - 1) cout << endl; } return 0; } } for (i = 0; i <= n; i++) { if (ok(i + (mxy - mny), mxy, i, mny)) { go(i + (mxy - mny), mxy, i, mny); for (i = 0; i < n; i++) for (j = 0; j < m; j++) { cout << c[i][j]; if (j == m - 1) cout << endl; } return 0; } } cout << -1 ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND4BB_TB_V
`define SKY130_FD_SC_MS__AND4BB_TB_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__and4bb.v"
module top();
// Inputs are registered
reg A_N;
reg B_N;
reg C;
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B_N = 1'bX;
C = 1'bX;
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B_N = 1'b0;
#60 C = 1'b0;
#80 D = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A_N = 1'b1;
#200 B_N = 1'b1;
#220 C = 1'b1;
#240 D = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A_N = 1'b0;
#360 B_N = 1'b0;
#380 C = 1'b0;
#400 D = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 D = 1'b1;
#600 C = 1'b1;
#620 B_N = 1'b1;
#640 A_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 D = 1'bx;
#760 C = 1'bx;
#780 B_N = 1'bx;
#800 A_N = 1'bx;
end
sky130_fd_sc_ms__and4bb dut (.A_N(A_N), .B_N(B_N), .C(C), .D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND4BB_TB_V
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_for_test.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_for_test (
address,
clock,
data,
wren,
q);
input [18:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 524288,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "TRUE",
altsyncram_component.widthad_a = 19,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "524288"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "19"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "524288"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "TRUE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "19"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 19 0 INPUT NODEFVAL "address[18..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 19 0 address 0 0 19 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_for_test.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_for_test.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_for_test.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_for_test.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_for_test_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_for_test_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; void solve() { vector<pair<long long, long long>> ar(4); for (long long i = 1; i <= 3; i++) { long long a, b; cin >> a >> b; ar[i] = {a, b}; } sort(ar.begin() + 1, ar.end()); set<pair<long long, long long>> ans; for (long long i = ar[1].first; i <= ar[2].first; i++) { ans.insert({i, ar[1].second}); } long long dy = 1; if (ar[2].second < ar[1].second) dy = -1; for (long long i = ar[1].second; i != ar[2].second; i += dy) { ans.insert({ar[2].first, i}); } ans.insert({ar[2].first, ar[2].second}); long long low = ar[1].second, high = ar[2].second; long long temp = min(high, low); high = max(high, low); low = temp; if (ar[3].second >= low && ar[3].second <= high) { for (long long i = ar[3].first; i >= ar[2].first; i--) { ans.insert({i, ar[3].second}); } } else if (ar[3].second > high) { for (long long i = ar[3].first; i >= ar[2].first; i--) { ans.insert({i, ar[3].second}); } for (long long i = ar[3].second; i > high; i--) { ans.insert({ar[2].first, i}); } } else { for (long long i = ar[3].first; i >= ar[2].first; i--) { ans.insert({i, ar[3].second}); } for (long long i = ar[3].second; i < low; i++) { ans.insert({ar[2].first, i}); } } cout << signed(ans.size()) << n ; for (auto i : ans) cout << i.first << << i.second << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long t = 1; while (t--) solve(); return 0; } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 22:04:02 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_0_stub.v
// Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_bram_ctrl,Vivado 2017.2.1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_aclk, s_axi_aresetn, s_axi_awid,
s_axi_awaddr, s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache,
s_axi_awprot, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp, s_axi_rlast,
s_axi_rvalid, s_axi_rready, bram_rst_a, bram_clk_a, bram_en_a, bram_we_a, bram_addr_a,
bram_wrdata_a, bram_rddata_a, bram_rst_b, bram_clk_b, bram_en_b, bram_we_b, bram_addr_b,
bram_wrdata_b, bram_rddata_b)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awid[11:0],s_axi_awaddr[12:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock,s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[12:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock,s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,bram_rst_a,bram_clk_a,bram_en_a,bram_we_a[3:0],bram_addr_a[12:0],bram_wrdata_a[31:0],bram_rddata_a[31:0],bram_rst_b,bram_clk_b,bram_en_b,bram_we_b[3:0],bram_addr_b[12:0],bram_wrdata_b[31:0],bram_rddata_b[31:0]" */;
input s_axi_aclk;
input s_axi_aresetn;
input [11:0]s_axi_awid;
input [12:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [12:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output bram_rst_a;
output bram_clk_a;
output bram_en_a;
output [3:0]bram_we_a;
output [12:0]bram_addr_a;
output [31:0]bram_wrdata_a;
input [31:0]bram_rddata_a;
output bram_rst_b;
output bram_clk_b;
output bram_en_b;
output [3:0]bram_we_b;
output [12:0]bram_addr_b;
output [31:0]bram_wrdata_b;
input [31:0]bram_rddata_b;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long int a, b, c, d, n, ans = 0; int main() { cin >> a; cin >> b; cin >> c; cin >> d; if ((a + b > c && a + c > b && b + c > a) || (a + b > d && a + d > b && b + d > a) || (a + d > c && a + c > d && d + c > a) || (d + b > c && d + c > b && b + c > d)) { cout << TRIANGLE ; } else if ((a + b == c) || (a + b == d) || (a + c == b) || (a + c == d) || (a + d == c) || (a + d == b) || (b + c == a) || (b + c == d) || (b + d == a) || (b + d == c) || (c + d == a) || (c + d == b)) { cout << SEGMENT ; } else { cout << IMPOSSIBLE ; } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_sync_flops.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - Andrej Erzen () ////
//// - Tadej Markovic () ////
//// ////
//// Created: 2004/05/20 ////
//// Last Updated: 2004/05/20 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//`include "timescale.v"
module uart_sync_flops
(
// internal signals
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter Tp = 1;
parameter width = 1;
parameter init_value = 1'b0;
input rst_i; // reset input
input clk_i; // clock input
input stage1_rst_i; // synchronous reset for stage 1 FF
input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
input [width-1:0] async_dat_i; // asynchronous data input
output [width-1:0] sync_dat_o; // synchronous data output
//
// Interal signal declarations
//
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
// first stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
flop_0 <= #Tp {width{init_value}};
else
flop_0 <= #Tp async_dat_i;
end
// second stage
always @ (posedge clk_i or posedge rst_i)
begin
if (rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= #Tp {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= #Tp flop_0;
end
endmodule
|
module erx_remap (/*AUTOARG*/
// Outputs
emesh_access_out, emesh_packet_out,
// Inputs
clk, emesh_access_in, emesh_packet_in, remap_mode, remap_sel,
remap_pattern, remap_base
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter ID = 12'h808;
//Clock/reset
input clk;
//Input from arbiter
input emesh_access_in;
input [PW-1:0] emesh_packet_in;
//Configuration
input [1:0] remap_mode; //00=none,01=static,02=continuity
input [11:0] remap_sel; //number of bits to remap
input [11:0] remap_pattern; //static pattern to map to
input [31:0] remap_base; //remap offset
//Output to TX IO
output emesh_access_out;
output [PW-1:0] emesh_packet_out;
wire [31:0] static_remap;
wire [31:0] dynamic_remap;
wire [31:0] remap_mux;
wire write_in;
wire read_in;
wire [31:0] addr_in;
wire [31:0] addr_out;
wire remap_en;
reg emesh_access_out;
reg [PW-1:0] emesh_packet_out;
//TODO:FIX!??
parameter[5:0] colid = ID[5:0];
//parsing packet
assign addr_in[31:0] = emesh_packet_in[39:8];
assign write_in = emesh_packet_in[1];
assign read_in = ~emesh_packet_in[1];
//simple static remap
assign static_remap[31:20] = (remap_sel[11:0] & remap_pattern[11:0]) |
(~remap_sel[11:0] & addr_in[31:20]);
assign static_remap[19:0] = addr_in[19:0];
//more complex compresssed map
assign dynamic_remap[31:0] = addr_in[31:0] //input
- (colid << 20) //subtracing elink (start at 0)
+ remap_base[31:0] //adding back base
- (addr_in[31:26]<<$clog2(colid));
//Static, dynamic, or no remap
assign remap_mux[31:0] = (remap_mode[1:0]==2'b00) ? addr_in[31:0] :
(remap_mode[1:0]==2'b01) ? static_remap[31:0] :
dynamic_remap[31:0];
//Access pipeline
always @ (posedge clk)
emesh_access_out <= emesh_access_in;
//Packet Remapping
always @ (posedge clk)
emesh_packet_out[PW-1:0] <= {emesh_packet_in[103:40],
remap_mux[31:0],
emesh_packet_in[7:0]
};
endmodule // etx_mux
|
#include <bits/stdc++.h> using namespace std; const int MAXM = 2e5 + 3, MAXN = 2e5 + 3, MAXQ = 2e5 + 3, MAXC = 2e5 + 3, ADD = 1 << 18; int n, m, q; int edge_from[MAXM << 1], edge_to[MAXM << 1], edge_nex[MAXM << 1]; int cntm = 1, head[MAXN]; void link(int from, int to) { edge_from[++cntm] = from; edge_to[cntm] = to; edge_nex[cntm] = head[from]; head[from] = cntm; } bool isb[MAXM << 1]; int edge1_to[MAXC << 1], edge1_nex[MAXC << 1]; int cntm1 = 0, head1[MAXC]; void link1(int from, int to) { edge1_to[++cntm1] = to; edge1_nex[cntm1] = head1[from]; head1[from] = cntm1; } int dfn[MAXN], low[MAXN], cntd = 0; void tarjan(int now, int fa) { low[now] = dfn[now] = ++cntd; for (int i = head[now]; i; i = edge_nex[i]) { if ((i ^ 1) == fa) continue; if (!dfn[edge_to[i]]) { tarjan(edge_to[i], i); if (low[edge_to[i]] > low[now]) { isb[i] = isb[i ^ 1] = 1; } else { low[now] = low[edge_to[i]]; } } else { low[now] = min(low[now], low[edge_to[i]]); } } } int col[MAXN], cntc = 0, Fa[MAXC][23], Deep[MAXC], cntd1 = 0; void dfs(int now) { col[now] = cntc; for (int i = head[now]; i; i = edge_nex[i]) if (!col[edge_to[i]] && !isb[i]) dfs(edge_to[i]); } void dfs2(int now) { for (int i = head1[now]; i; i = edge1_nex[i]) { if (!Deep[edge1_to[i]] && edge1_to[i] != Fa[now][0]) { Fa[edge1_to[i]][0] = now; Deep[edge1_to[i]] = Deep[now] + 1; dfs2(edge1_to[i]); } } } long long val1[MAXN]; long long sum1; bool Arr[MAXN]; int ans = 1; void dfs3(int now) { if (!ans) return; Arr[now] = 1; long long in1 = sum1; sum1 += val1[now]; for (int i = head1[now]; i; i = edge1_nex[i]) if (!Arr[edge1_to[i]] && ans) dfs3(edge1_to[i]); in1 = sum1 - in1; if ((in1 >> 18) && in1 - ((in1 >> 18) << 18)) ans = 0; } inline int lca(register int A, register int B) { if (Deep[A] < Deep[B]) swap(A, B); for (int i = 17; i >= 0; i--) { if (Deep[Fa[A][i]] >= Deep[B]) A = Fa[A][i]; } if (A == B) return A; for (int i = 17; i >= 0; i--) { if (Fa[A][i] != Fa[B][i]) { A = Fa[A][i]; B = Fa[B][i]; } } if (Fa[A][0] == Fa[B][0] && Fa[A][0] != 0) return Fa[A][0]; return -1; } int main() { ios::sync_with_stdio(false); cin >> n >> m >> q; for (int i = 1, U, V; i <= m; i++) { cin >> U >> V; link(U, V); link(V, U); } for (int i = 1; i <= n; i++) if (!dfn[i]) tarjan(i, 0); for (int i = 1; i <= n; i++) if (!col[i]) { cntc++; dfs(i); } for (int i = 2; i <= cntm; i++) if (isb[i]) link1(col[edge_from[i]], col[edge_to[i]]); for (int i = 1; i <= cntc; i++) if (!Deep[i]) { Deep[i] = 1; dfs2(i); } for (int i = 1; i <= 17; i++) for (int j = 1; j <= cntc; j++) Fa[j][i] = Fa[Fa[j][i - 1]][i - 1]; for (int i = 1, i2, i3, i4; i <= q; i++) { cin >> i2 >> i3; i2 = col[i2]; i3 = col[i3]; if (i2 == i3) continue; i4 = lca(i2, i3); if (i4 == -1) { ans = 0; break; } val1[i2] += 1; val1[i4] -= 1; val1[i3] += ADD; val1[i4] -= ADD; } for (int i = 1; i <= cntc; i++) if (!Arr[i]) dfs3(i); if (ans) cout << Yes ; else cout << No ; } |
//
// Copyright 2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//The following module is used to re-write receive packets to the host.
//This module provides a packet-based ram interface for manipulating packets.
//By default, this module uses the built-in 16 to 8 bit converter engine.
module vita_rx_engine_glue
#(
//the dsp unit number: 0, 1, 2...
parameter DSPNO = 0,
//buffer size for ram interface engine
parameter BUF_SIZE = 10,
//base address for built-in settings registers used in this module
parameter MAIN_SETTINGS_BASE = 0
)
(
//control signals
input clock, input reset, input clear,
//main settings bus for built-in modules
input set_stb_main, input [7:0] set_addr_main, input [31:0] set_data_main,
//user settings bus, controlled through user setting regs API
input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
//ram interface for engine
output access_we,
output access_stb,
input access_ok,
output access_done,
output access_skip_read,
output [BUF_SIZE-1:0] access_adr,
input [BUF_SIZE-1:0] access_len,
output [35:0] access_dat_o,
input [35:0] access_dat_i,
//debug output (optional)
output [31:0] debug
);
generate
if (DSPNO==0) begin
`ifndef RX_ENG0_MODULE
dspengine_16to8 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE)) dspengine_16to8
(.clk(clock),.reset(reset),.clear(clear),
.set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main),
.access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
.access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
.access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
`else
`RX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng0_custom
(.clock(clock),.reset(reset),.clear(clear),
.set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
.access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
.access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
.access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
`endif
end
else begin
`ifndef RX_ENG1_MODULE
dspengine_16to8 #(.BASE(MAIN_SETTINGS_BASE), .BUF_SIZE(BUF_SIZE)) dspengine_16to8
(.clk(clock),.reset(reset),.clear(clear),
.set_stb(set_stb_main), .set_addr(set_addr_main), .set_data(set_data_main),
.access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
.access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
.access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
`else
`RX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng1_custom
(.clock(clock),.reset(reset),.clear(clear),
.set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
.access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
.access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
.access_dat_i(access_dat_i), .access_dat_o(access_dat_o));
`endif
end
endgenerate
endmodule //vita_rx_engine_glue
|
#include <bits/stdc++.h> using namespace std; int main() { int x, y; cin >> x >> y; if (((x < y) ? x : y) % 2) cout << Akshat ; else cout << Malvika ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n >> a >> b; if (b) b = (b / abs(b)) * (abs(b) % n); if (!b) { cout << a; return 0; } if (b > 0) { int i, cnt = 0; for (i = a; cnt != b; (i != n) ? (i++) : i = 1) { cnt++; } cout << i; return 0; } if (b < 0) { b = abs(b); int i, cnt = 0; for (i = a; cnt != b; (i != 1) ? (i--) : i = n) { cnt++; } cout << i; return 0; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3_TB_V
`define SKY130_FD_SC_LS__OR3_TB_V
/**
* or3: 3-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ls__or3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3_TB_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void remax(T& A, T B) { if (A < B) A = B; } template <class T> inline void remin(T& A, T B) { if (A > B) A = B; } string ToString(long long num) { string ret; do { ret += ((num % 10) + 0 ); num /= 10; } while (num); reverse(ret.begin(), ret.end()); return ret; } long long ToNumber(string s) { long long r = 0, p = 1; for (int i = s.size() - 1; i >= 0; --i) r += (s[i] - 0 ) * p, p *= 10; return r; } long long Gcd(long long a, long long b) { while (a %= b ^= a ^= b ^= a) ; return b; } long long Power(long long base, long long power) { long long ret = 1; while (power) { if (power & 1) ret *= base; power >>= 1; base *= base; } return ret; } long long PowerMod(long long base, long long power, long long mod) { if (!power) return 1; if (power & 1) return (base * PowerMod(base, power - 1, mod)) % mod; return PowerMod((base * base) % mod, power >> 1, mod); } int Log(long long num, long long base) { int ret = 0; while (num) { ++ret; num /= base; } return ret; } int Count(long long mask) { int ret = 0; while (mask) { if (mask & 1) ++ret; mask >>= 1; } return ret; } inline void run() { unsigned long long ans; long long n; scanf( %I64d , &n); ans = n * 3; ans *= (n + 1); cout << ++ans << n ; } int main() { FILE* input = stdin; FILE* output = stdout; while (!feof(input)) { run(); break; } return 0; } |
#include <bits/stdc++.h> using namespace std; int inf = INT_MAX >> 1; double PI = 3.1415926535897932384626433832795; set<vector<char> > st; int ans = 0; void rotX(vector<char> &c); void rotY(vector<char> &c); void solve(string s) { vector<char> c(6); for (int i = 0; i < s.size(); i++) c[i] = s[i]; bool found = 0; set<vector<char> > ss; for (int i = 0; i < 4; i++) { rotX(c); for (int j = 0; j < 4; j++) { rotY(c); if (st.find(c) != st.end()) { found = 1; break; } ss.insert(c); } } if (!found) { for (auto it : ss) st.insert(it); ans++; } } int main() { string s; cin >> s; sort(s.begin(), s.end()); do { solve(s); } while (next_permutation(s.begin(), s.end())); printf( %d n , ans); return 0; } void rotX(vector<char> &c) { swap(c[0], c[1]); swap(c[0], c[4]); swap(c[0], c[3]); } void rotY(vector<char> &c) { swap(c[0], c[5]); swap(c[0], c[4]); swap(c[0], c[2]); } |
#include <bits/stdc++.h> using namespace std; const int MAX = 2e5; int main() { int n; cin >> n; int f = 0, z = 0; for (int i = 0; i < n; i++) { int val; scanf( %d , &val); if (val == 5) f++; else z++; } int mx = 0; for (int i = 0; i <= f; i++) if ((5 * i) % 9 == 0) mx = i; if (!z) cout << -1; else { if (!mx) cout << 0; else { for (int i = 0; i < mx; i++) cout << 5; for (int i = 0; i < z; i++) cout << 0; } } } |
#include <bits/stdc++.h> using namespace std; int n, m; int num[105]; int a[105][105], sum[105][105], mx[105][105]; int f[105][10005]; int main() { cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> num[i]; for (int j = 1; j <= num[i]; j++) { cin >> a[i][j]; sum[i][j] = sum[i][j - 1] + a[i][j]; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= num[i]; j++) { for (int k = 0; k <= j; k++) { mx[i][j] = max(mx[i][j], sum[i][k] + (sum[i][num[i]] - sum[i][num[i] - (j - k)])); } } } for (int i = 1; i <= n; i++) { for (int j = 0; j <= m; j++) { int maxi = 0; for (int k = 0; k <= num[i] && k <= j; k++) { maxi = max(maxi, f[i - 1][j - k] + mx[i][k]); } f[i][j] = maxi; } } cout << f[n][m] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int arr[100005], lazy[4 * 100005], num, value; bool flag; struct Node { int maxi, mini, one, two; } tree[4 * 100005]; Node merge(Node a, Node b) { Node temp; int num = max(a.maxi, b.maxi); temp.maxi = num, temp.one = num == a.maxi ? a.one : b.one; num = min(a.mini, b.mini); temp.mini = num, temp.two = num == a.mini ? a.two : b.two; return temp; } void build(int node, int a, int b) { if (a > b) return; if (a == b) { tree[node] = (Node){arr[a], arr[a], a, a}; return; } int left, right; left = 2 * node + 1, right = 2 * node + 2; build(left, a, (a + b) / 2); build(right, (a + b) / 2 + 1, b); tree[node] = merge(tree[left], tree[right]); } void lazy_update(int node, int a, int b) { int left, right; left = 2 * node + 1, right = 2 * node + 2; tree[node].maxi -= lazy[node]; tree[node].mini -= lazy[node]; if (a != b) { lazy[left] += lazy[node]; lazy[right] += lazy[node]; } lazy[node] = 0; } void update(int node, int a, int b, int i, int j, int val) { if (lazy[node]) lazy_update(node, a, b); if (a > b || a > j || b < i) return; if (a >= i && b <= j) { lazy[node] = val; lazy_update(node, a, b); return; } int left, right; left = 2 * node + 1, right = 2 * node + 2; update(left, a, (a + b) / 2, i, j, val); update(right, (a + b) / 2 + 1, b, i, j, val); tree[node] = merge(tree[left], tree[right]); } void query(int node, int a, int b, int i, int j, int val) { if (lazy[node]) lazy_update(node, a, b); if (flag) return; if (a > b || a > j || b < i) return; if (val > tree[node].mini) { if (a == b) { flag = true; num = a; return; } int left, right; left = 2 * node + 1, right = 2 * node + 2; query(left, a, (a + b) / 2, i, j, val); query(right, (a + b) / 2 + 1, b, i, j, val); } } void find(int node, int a, int b, int i, int j) { if (lazy[node]) lazy_update(node, a, b); if (a > b || a > j || b < i) return; if (a == b) { value = tree[node].mini; return; } int left, right; left = 2 * node + 1, right = 2 * node + 2; find(left, a, (a + b) / 2, i, j); find(right, (a + b) / 2 + 1, b, i, j); } int main() { int n, a, b, one, two, k = 0, diff; scanf( %d , &n); set<int> zero; for (int i = 0; i < n; i++) { scanf( %d , &arr[i]); if (!arr[i]) zero.insert(i); } build(0, 0, n - 1); zero.insert(n); vector<pair<int, int> > vec; while (true) { if (lazy[0]) lazy_update(0, 0, n - 1); if (tree[0].maxi == 0) break; int index = tree[0].one, x, y; y = *zero.upper_bound(index); flag = false; query(0, 0, n - 1, index + 1, y - 1, tree[0].maxi); if (flag) a = index, b = num - 1; else a = index, b = min(n - 1, y - 1); update(0, 0, n - 1, a, b, 1); vec.push_back(make_pair(a + 1, b + 1)); } printf( %d n , vec.size()); for (int i = 0; i < vec.size(); i++) printf( %d %d n , vec[i].first, vec[i].second); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__AND2B_PP_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2b (
//# {{data|Data Signals}}
input A_N ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2B_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 500005; int n, m, u[MAXN], v[MAXN]; bool cho[MAXN], sel[MAXN]; void solve() { int ans = 0; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d , &u[i], &v[i]); if (!cho[u[i]] && !cho[v[i]]) { sel[i] = 1; ++ans; cho[u[i]] = cho[v[i]] = 1; } } if (ans >= n) { printf( Matching n ); int cnt = 0; for (int i = 1; i <= m && cnt < n; i++) if (sel[i]) { printf( %d , i); ++cnt; } printf( n ); } else { printf( IndSet n ); int cnt = 0; for (int i = 1; i <= 3 * n && cnt < n; i++) if (!cho[i]) { printf( %d , i); ++cnt; } printf( n ); } for (int i = 1; i <= 3 * n; i++) cho[i] = 0; for (int i = 1; i <= m; i++) sel[i] = 0; } int main() { int T; scanf( %d , &T); while (T--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 7; long long sumb, sumc; int n, a[N], b[N], c[N], cnt[30]; bool check() { for (int i = 0; i < n; i++) { for (int j = 0; j < 30; j++) { if (a[i] & 1 << j) cnt[j]++; } } for (int i = 0; i < n; i++) { long long sum = 0; for (int j = 0; j < 30; j++) { if (a[i] & 1 << j) sum += cnt[j] * (1 << j); } if (sum != b[i]) return 0; } return 1; } int main() { cin >> n; for (int i = 0; i < n; i++) scanf( %d , b + i), sumb += b[i]; for (int i = 0; i < n; i++) scanf( %d , c + i), sumc += c[i]; for (int i = 0; i < n; i++) { long long buf = b[i] + c[i] - (sumb + sumc) / 2 / n; if ((sumb + sumc) % (2 * n) || buf % n) { puts( -1 ); return 0; } a[i] = buf / n; } if (!check()) puts( -1 ); else { for (int i = 0; i < n; i++) { printf( %d%c , a[i], n [i == n - 1]); } } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// UART Module
// Paul Mumby 2012
//////////////////////////////////////////////////////////////////////////////////
module uart(
clk,
rx_pin,
tx_pin,
rx_byte,
tx_byte,
rx_data_ready,
tx_start,
rx_busy,
tx_busy,
rx_error
);
//Parameters:
//================================================
parameter CLOCK = 25000000; //Overridden by parent
parameter BAUD = 9600; //Overridden by parent
parameter SAMPLE_POINT = 8; //Overridden by parent
//IO Definitions:
//================================================
input clk;
input rx_pin;
output tx_pin;
output [7:0] rx_byte;
input [7:0] tx_byte;
output rx_data_ready;
input tx_start;
output rx_busy;
output tx_busy;
output rx_error;
//Register/Wire Definitions:
//================================================
//BUFG Instatiation:
//================================================
//Module Instantiation:
//================================================
uart_tx #(
.CLOCK(CLOCK),
.BAUD(BAUD)
) TXCORE (
.clk(clk),
.tx(tx_pin),
.tx_byte(tx_byte),
.start(tx_start),
.busy(tx_busy)
);
uart_rx #(
.CLOCK(CLOCK),
.BAUD(BAUD),
.SAMPLE_POINT(SAMPLE_POINT)
) RXCORE (
.clk(clk),
.rx(rx_pin),
.rx_byte(rx_byte),
.data_ready(rx_data_ready),
.busy(rx_busy),
.error(rx_error)
);
//Assignments:
//================================================
//Toplevel Logic:
//================================================
endmodule
|
`timescale 1ns / 1ps
//`define DATA_PATTERN_0 16'hA635
//`define DATA_PATTERN_1 16'h59CA // inverse of DATA_PATTERN_0
`define DATA_PATTERN_0 16'h35A9
`define DATA_PATTERN_1 16'hCA56 // inverse of DATA_PATTERN_0
`define MRAM_LATENCY 10
module MRAM_RW(
input CLKM,
input RST,
input start,
output done_wire,
input inverse_pattern,
input [1:0] pOPER,
input [17:0] pADDR,
output [31:0] latency,
output [15:0] badbits,
output [7:0] Led,
//MRAM wires
output e_n,
output w_n,
output g_n,
output ub_n,
output lb_n,
output [17:0] addr,
inout [15:0] dq
);
//debug led
assign Led[7:0] = {start,done_wire,CLKM,NSTAT[4:0]};
// FSM
parameter
INIT = 30, OPER_CHECK = 29,
DATA_IN_0 = 1, DATA_IN_1 = 2, DATA_IN_2 = 3, DATA_IN_3 = 4, //WRITE
DATA_OUT_0 = 5, DATA_OUT_1 = 6, DATA_OUT_2 = 7, DATA_OUT_3 = 8, DATA_OUT_4 = 9, DATA_OUT_5 = 10, //READ
RESET_0 = 11, RESET_1 = 12,
END_0 = 13,
STOP = 00;
parameter
oWR = 0,
oRD = 1,
oER = 2,
oRS = 3;
assign e_n = e_n_reg;
assign w_n = w_n_reg;
assign g_n = g_n_reg;
assign ub_n = ub_n_reg;
assign lb_n = lb_n_reg;
assign addr[17:0] = addr_reg[17:0];
assign dq[15:0] = (DQ_input_en)? 16'bzzzz_zzzz_zzzz_zzzz : dq_reg[15:0];
assign badbits[15:0] = cnt_badbits[15:0];
assign latency[31:0] = cnt_latency[31:0];
reg e_n_reg;
reg w_n_reg;
reg g_n_reg;
reg ub_n_reg;
reg lb_n_reg;
reg [17:0] addr_reg;
reg [15:0] dq_reg;
reg [15:0] dq_comp;
reg DQ_input_en;
reg [7:0] cnt_wait;
reg [31:0] cnt_latency;
reg [15:0] cnt_badbits;
reg [4:0] NSTAT;
assign done_wire = (NSTAT == STOP) ? 1'b1 : 1'b0;
always@(posedge CLKM)
begin
if(RST)
begin
//CE <= 0;
NSTAT <= INIT;
end
else
begin
case (NSTAT)
INIT:
begin
cnt_wait <= 0;
cnt_latency <= 32'h0;
cnt_badbits <= 16'h0;
DQ_input_en <= 0;
e_n_reg <= 1;
w_n_reg <= 1;
g_n_reg <= 1;
ub_n_reg <= 1;
lb_n_reg <= 1;
addr_reg <= pADDR[17:0];
if (inverse_pattern)
dq_reg <= `DATA_PATTERN_1;
else
dq_reg <= `DATA_PATTERN_0;
if( start == 0 )
NSTAT <= INIT;
else
NSTAT <= OPER_CHECK;
end
OPER_CHECK:
begin
if(pOPER == oRS)
NSTAT <= RESET_0;
else if(pOPER == oWR)
NSTAT <= DATA_IN_0;
else
NSTAT <= DATA_OUT_0;
end
// FSM: RESET ==========================================
RESET_0:
begin
cnt_latency <= 0;
NSTAT <= RESET_1;
end
RESET_1:
begin
if ( cnt_latency != 32'd200_000) //2ms => 2,000,000 ns => (10ns/cycle) 200_000 cycle
begin
cnt_latency <= cnt_latency + 1'b1;
NSTAT <= RESET_1;
end
else
begin
cnt_latency <= 0;
NSTAT <= END_0;
end
end
// FSM: WRITE ==========================================
DATA_IN_0: // WR_START
begin
DQ_input_en <= 0;
e_n_reg <= 0;
w_n_reg <= 0;
g_n_reg <= 1;
ub_n_reg <= 0;
lb_n_reg <= 0;
addr_reg <= pADDR[17:0];
if (inverse_pattern)
dq_reg <= `DATA_PATTERN_1;
else
dq_reg <= `DATA_PATTERN_0;
NSTAT <= DATA_IN_1;
end
DATA_IN_1: // WR_WAIT
begin
if(cnt_wait<`MRAM_LATENCY)
begin
cnt_wait <= cnt_wait + 1'b1;
NSTAT <= DATA_IN_1;
end
else
begin
cnt_wait <= 0;
NSTAT <= DATA_IN_2;
end
end
DATA_IN_2: // WR_END
begin
//dbg
cnt_badbits <= dq_reg[15:0];
cnt_wait <= 0;
e_n_reg <= 0;
w_n_reg <= 1;
g_n_reg <= 0;
ub_n_reg <= 0;
lb_n_reg <= 0;
//addr_reg <= data_host[39:24];
//data_reg <=data_reg;
//NSTAT <= DATA_IN_3;
if(addr_reg[0]==0) addr_reg[0] <=1;
else addr_reg[0] <=0;
NSTAT <= DATA_IN_0; //force power-test -write
end
DATA_IN_3:
begin
if(cnt_wait<5)
begin
cnt_wait <= cnt_wait + 1'b1;
NSTAT <= DATA_IN_3;
end
else
begin
cnt_wait <= 0;
NSTAT <= END_0;
end
end
// FSM: READ ==========================================
DATA_OUT_0:
begin // RD_START
DQ_input_en <= 1;
cnt_badbits <= 0;
e_n_reg <= 0;
w_n_reg <= 1;
g_n_reg <= 0;
ub_n_reg <= 0;
lb_n_reg <= 0;
if (inverse_pattern)
dq_comp <= `DATA_PATTERN_1;
else
dq_comp <= `DATA_PATTERN_0;
addr_reg <= pADDR[15:0];
//data_reg <= data_host[23:8];
NSTAT <= DATA_OUT_1;
end
DATA_OUT_1: // RD_WAIT
begin
if(cnt_wait<`MRAM_LATENCY)
begin
cnt_wait <= cnt_wait + 1'b1;
NSTAT <= DATA_OUT_1;
end
else
begin
NSTAT <= DATA_OUT_2;
cnt_wait <= 0;
end
end
DATA_OUT_2: // RD_END
begin
e_n_reg <= 0;
w_n_reg <= 1;
g_n_reg <= 0;
ub_n_reg <= 0;
lb_n_reg <= 0;
//addr_reg <= data_host[39:24];
//data_reg <= data_host[23:8];
//NSTAT <= DATA_OUT_3;
if(addr_reg[0]==0) addr_reg[0] <=1;
else addr_reg[0] <=0;
NSTAT <= DATA_OUT_0; //force - power - test
end
DATA_OUT_3: //RD_VERIFY
begin
if(cnt_wait<5)
begin
cnt_wait <= cnt_wait + 1'b1;
NSTAT <= DATA_OUT_3;
end
else
begin
cnt_wait <= 0;
NSTAT <= DATA_OUT_4;
end
end
DATA_OUT_4:
begin
//dbg
cnt_latency <= { dq_comp[15:0], dq[15:0] };
cnt_badbits <= ( dq[15] ^ dq_comp[15] ) + ( dq[14] ^ dq_comp[14] ) +
( dq[13] ^ dq_comp[13] ) + ( dq[12] ^ dq_comp[12] ) +
( dq[11] ^ dq_comp[11] ) + ( dq[10] ^ dq_comp[10] ) +
( dq[ 9] ^ dq_comp[ 9] ) + ( dq[ 8] ^ dq_comp[ 8] ) +
( dq[ 7] ^ dq_comp[ 7] ) + ( dq[ 6] ^ dq_comp[ 6] ) +
( dq[ 5] ^ dq_comp[ 5] ) + ( dq[ 4] ^ dq_comp[ 4] ) +
( dq[ 3] ^ dq_comp[ 3] ) + ( dq[ 2] ^ dq_comp[ 2] ) +
( dq[ 1] ^ dq_comp[ 1] ) + ( dq[ 0] ^ dq_comp[ 0] );
NSTAT <= DATA_OUT_5;
end
DATA_OUT_5:
begin
NSTAT <= END_0;
end
// FSM: RW_END ==========================================
END_0:
begin
DQ_input_en <= 0;
e_n_reg <= 1;
w_n_reg <= 1;
g_n_reg <= 1;
ub_n_reg <= 1;
lb_n_reg <= 1;
//addr_reg <= addr_reg;
//data_reg <= data_reg;
NSTAT <= STOP;
end
STOP:
begin
if( start==1 )
NSTAT <= STOP;
else
NSTAT <= INIT;
end
default:
begin
NSTAT <= INIT;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2AI_2_V
`define SKY130_FD_SC_MS__O2BB2AI_2_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog wrapper for o2bb2ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2bb2ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2ai_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2bb2ai_2 (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o2bb2ai base (
.Y(Y),
.A1_N(A1_N),
.A2_N(A2_N),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2AI_2_V
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 5e3 + 3; map<int, int> mapa; vector<int> v; int mw[103030]; int main() { int n, m, a, maxi = 0; scanf( %d %d , &n, &m); for (int i = (int)0; i < (int)n; i++) { scanf( %d , &a); mapa[a] = 1; mw[i] = a; if (maxi > a) maxi = a; } int o = 1; while (m) { if (m - o < 0) break; if (!mapa[o]) v.push_back(o), m -= o; o++; } printf( %d n , v.size()); for (int i = (int)0; i < (int)v.size(); i++) printf( %d , v[i]); printf( n ); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_2_V
`define SKY130_FD_SC_LS__INV_2_V
/**
* inv: Inverter.
*
* Verilog wrapper for inv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__inv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__inv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__inv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__inv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__inv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_2_V
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