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#include <bits/stdc++.h> using namespace std; char c[100005]; int cut[100005], num[100005]; int f[100005], h[2][100005]; int main() { int n, m; cin >> n >> c + 1 >> m; for (int i = 1; i <= n; i++) { num[i] = num[i - 1]; if (c[i] == a ) h[0][i] = h[1][i - 1] + 1; else if (c[i] == b ) h[1][i] = h[0][i - 1] + 1; else { h[0][i] = h[1][i - 1] + 1; h[1][i] = h[0][i - 1] + 1; num[i]++; } f[i] = f[i - 1], cut[i] = cut[i - 1]; if (h[(m + 1) & 1][i] >= m) { if (f[i] < f[i - m] + 1) { f[i] = f[i - m] + 1, cut[i] = cut[i - m] + num[i] - num[i - m]; } if (f[i] == f[i - m] + 1) { cut[i] = min(cut[i], cut[i - m] + num[i] - num[i - m]); } } } cout << cut[n] << endl; } |
#include <bits/stdc++.h> using namespace std; int n; double p[100008]; struct Tprogram { void open() { freopen( 1.in , r , stdin); freopen( 1.out , w , stdout); } void close() {} void init() { scanf( %d , &n); for (int i = 0; i <= n; i++) scanf( %lf , &p[i]); } void work() { double ans = 0; for (int i = 0; i <= n >> 1; i++) for (int j = (n >> 1) + 1; j <= n; j++) ans = ((p[i] * (2 * j - n) + p[j] * (n - 2 * i)) / (2 * j - 2 * i) > ans ? (p[i] * (2 * j - n) + p[j] * (n - 2 * i)) / (2 * j - 2 * i) : ans); printf( %.10lf n , ans); } } Program; int main() { Program.init(); Program.work(); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize(2) #pragma G++ optimize(2) using namespace std; const int MAX_N = 2e3 + 5; char s[MAX_N], t[MAX_N]; int sufs[MAX_N][26], suft[MAX_N][26]; int dp[MAX_N][MAX_N]; int solve(int i, int j) { if (j == 0) return 0; if (~dp[i][j]) return dp[i][j]; int res = 2e9; if (i > 0) { res = 1 + solve(i - 1, j); if (s[i] == t[j]) res = min(res, solve(i - 1, j - 1)); } int c = t[j] - a ; if (sufs[i + 1][c] > suft[j + 1][c]) res = min(res, solve(i, j - 1)); return dp[i][j] = res; } int main() { int T; scanf( %d , &T); while (T--) { int n; scanf( %d , &n), scanf( %s , s + 1), scanf( %s , t + 1); for (register int i = 0; i <= 25; ++i) sufs[n + 1][i] = suft[n + 1][i] = 0; for (register int i = 0; i <= n; ++i) for (register int j = 0; j <= n; ++j) dp[i][j] = -1; for (register int i = n; i >= 1; --i) { for (register int j = 0; j <= 25; ++j) sufs[i][j] = sufs[i + 1][j], suft[i][j] = suft[i + 1][j]; sufs[i][s[i] - a ]++, suft[i][t[i] - a ]++; } int ans = solve(n, n); if (ans > 1e9) ans = -1; printf( %d n , ans); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:37:20 09/24/2014
// Design Name:
// Module Name: SynchronizeClkDomains
// Project Name:
// Target Devices:
// Tool versions:
// Description: This module is for synchronization of signals between 200M( System workspace)clk domain and
// 83M(flash controller moduler) clk domain.
// Method: Adding two FFs betwwn the two specified clk domains to mitigate the damage cased by metastability.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SynchronizeClkDomains(
clk_200M,clk_83M,rst_n,
//From flash controller module to Scheduler module
controller_rb_l,controller_rb_l_o, read_data_stall ,read_data_stall_o,
//From Scheduler module to flash controller module
Target_Addr, page_offset_addr, Operation_en,Operation_Type,
Target_Addr_o,page_offset_addr_o,Operation_en_o,Operation_Type_o
);
`include"Dynamic_Controller_Parameters.vh"
//clk and reset
input clk_200M;
input clk_83M;
input rst_n;
//From flash controller module to Scheduler module
input controller_rb_l;
input read_data_stall;
output reg controller_rb_l_o;
output reg read_data_stall_o;
//From Scheduler module to flash controller module
input [2:0] Target_Addr;
input [ADDR_WIDTH-4:0] page_offset_addr;
input Operation_en;
input [2:0] Operation_Type;
output reg [2:0] Target_Addr_o;
output reg [ADDR_WIDTH-4:0] page_offset_addr_o;
output reg Operation_en_o;
output reg [2:0] Operation_Type_o;
////////////////////////////////////////////////////////////////
reg controller_rb_l_sync;
reg read_data_stall_sync;
//From flash controller module to Scheduler module
always@(posedge clk_200M or negedge rst_n)
begin
if(!rst_n)
begin
controller_rb_l_sync<=1'b0;
read_data_stall_sync<=1'b0;
controller_rb_l_o<=1'b0;
read_data_stall_o<=1'b0;
end
else
begin
controller_rb_l_sync<=controller_rb_l;
controller_rb_l_o<=controller_rb_l_sync;
read_data_stall_sync<=read_data_stall;
read_data_stall_o<=read_data_stall_sync;
end
end
//sync FFs
reg [2:0] Target_Addr_sync;
reg [ADDR_WIDTH-4:0] page_offset_addr_sync;
reg Operation_en_sync;
reg [2:0] Operation_Type_sync;
//From Scheduler module to flash controller module.
always@(posedge clk_83M or negedge rst_n)
begin
if(!rst_n)
begin
Target_Addr_sync<=3'b0;
page_offset_addr_sync<='b0;
Operation_Type_sync<=3'b0;
Operation_en_sync<=1'b0;
Target_Addr_o<=3'b0;
page_offset_addr_o<='b0;
Operation_en_o<=1'b0;
Operation_Type_o<=3'b0;
end
else
begin
Target_Addr_sync<=Target_Addr;
page_offset_addr_sync<=page_offset_addr;
Operation_en_sync<=Operation_en;
Operation_Type_sync<=Operation_Type;
Target_Addr_o<=Target_Addr_sync;
page_offset_addr_o<=page_offset_addr_sync;
Operation_en_o<=Operation_en_sync;
Operation_Type_o<=Operation_Type_sync;
end
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_convert_with_rounding_8(clock, resetn, dataa, result, valid_in, valid_out, stall_in, stall_out, enable);
// Latency = 4.
parameter UNSIGNED = 1;
parameter ROUNDING_MODE = 0;
parameter HIGH_CAPACITY = 1;
// Rounding mode values are:
// 0 - round to nearest even
// 1 - round to nearest with ties away from zero
// 2 - round towards zero (truncation)
// 3 - round up
// 4 - round down
input clock;
input enable, resetn;
input [31:0] dataa;
output [7:0] result;
input valid_in, stall_in;
output stall_out, valid_out;
// STAGE 0 - extract input data into format we can work with.
wire sign_0;
wire [7:0] exp_0;
wire [22:0] man_0;
wire [23:0] implied_man_0;
assign {sign_0, exp_0, man_0} = dataa;
assign implied_man_0 = (|exp_0) ? {1'b1, man_0} : 24'd0;
// STAGE 1
reg sign_c1;
reg [10:0] man_c1;
reg [8:0] shift_amount_c1;
reg [7:0] exp_c1;
reg valid_c1;
wire stall_c1;
wire enable_c1;
assign stall_out = stall_c1 & valid_c1;
assign enable_c1 = (HIGH_CAPACITY == 1) ? (~stall_c1 | ~valid_c1) : enable;
always @( posedge clock or negedge resetn)
begin
if( ~resetn )
begin
sign_c1 <= 1'bx;
man_c1 <= 11'dx;
shift_amount_c1 <= 9'dx;
exp_c1 <= 8'dx;
valid_c1 <= 1'b0;
end
else if (enable_c1)
begin
sign_c1 <= sign_0;
valid_c1 <= valid_in;
if (UNSIGNED == 1)
begin
man_c1 <= {implied_man_0[23:14], |implied_man_0[13:0]};
shift_amount_c1 <= 9'd134 - exp_0;
end
else
begin
man_c1 <= {1'b0, implied_man_0[23:15], |implied_man_0[14:0]};
shift_amount_c1 <= 9'd133 - exp_0;
end
exp_c1 <= exp_0;
end
end
// STAGE 2
reg sign_c2;
reg [10:0] extended_mantissa_c2;
reg [2:0] shift_amount_c2;
reg valid_c2;
wire stall_c2;
wire enable_c2 = (HIGH_CAPACITY == 1) ? (~stall_c2 | ~valid_c2) : enable;
assign stall_c1 = stall_c2 & valid_c2;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
sign_c2 <= 1'bx;
extended_mantissa_c2 <= 11'dx;
shift_amount_c2 <= 3'dx;
valid_c2 <= 1'b0;
end
else if (enable_c2)
begin
sign_c2 <= sign_c1;
valid_c2 <= valid_c1;
shift_amount_c2 <= (shift_amount_c1[2:0]) & {3{(~(&exp_c1)) & ~shift_amount_c1[8]}};
// Now handle the corner cases of NaN and INF. Make it maximum positive or negative integer depending on the sign.
// Then handle overflow and regular shifting.
if ((UNSIGNED == 1) && (exp_c1 == 8'hff))
extended_mantissa_c2 <= {8'hff, 3'd0};
else if ((UNSIGNED == 0) && (exp_c1 == 8'hff))
extended_mantissa_c2 <= {8'h7f + sign_c1, 3'd0};
else if (shift_amount_c1[8])
extended_mantissa_c2 <= {(UNSIGNED == 0) ? 8'h7f + sign_c1 : 8'hff, 3'd0}; // Overflow/Saturation.
else if (|shift_amount_c1[7:4])
begin
// Shift by more than 16+
sign_c2 <= sign_c1 & (|man_c1);
extended_mantissa_c2 <= {10'd0, |man_c1};
end
else if (|shift_amount_c1[3])
begin
// Shift by 8+
extended_mantissa_c2 <= {8'd0, man_c1[10:9], |man_c1[8:0]};
end
else
extended_mantissa_c2 <= man_c1;
end
end
// STAGE 3
reg [10:0] extended_mantissa_c3;
reg valid_c3;
reg sign_c3;
wire stall_c3;
wire enable_c3 = (HIGH_CAPACITY == 1) ? (~valid_c3 | ~stall_c3) : enable;
assign stall_c2 = valid_c3 & stall_c3;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
extended_mantissa_c3 <= 35'dx;
sign_c3 <= 1'bx;
valid_c3 <= 1'b0;
end
else if (enable_c3)
begin
valid_c3 <= valid_c2;
sign_c3 <= sign_c2;
case (shift_amount_c2)
3'b111: extended_mantissa_c3 <= {7'd0, extended_mantissa_c2[10:8], |extended_mantissa_c2[7:0]};
3'b110: extended_mantissa_c3 <= {6'd0, extended_mantissa_c2[10:7], |extended_mantissa_c2[6:0]};
3'b101: extended_mantissa_c3 <= {5'd0, extended_mantissa_c2[10:6], |extended_mantissa_c2[5:0]};
3'b100: extended_mantissa_c3 <= {4'd0, extended_mantissa_c2[10:5], |extended_mantissa_c2[4:0]};
3'b011: extended_mantissa_c3 <= {3'd0, extended_mantissa_c2[10:4], |extended_mantissa_c2[3:0]};
3'b010: extended_mantissa_c3 <= {2'd0, extended_mantissa_c2[10:3], |extended_mantissa_c2[2:0]};
3'b001: extended_mantissa_c3 <= {1'd0, extended_mantissa_c2[10:2], |extended_mantissa_c2[1:0]};
3'b000: extended_mantissa_c3 <= extended_mantissa_c2;
endcase
end
end
// STAGE 4
reg [8:0] result_c4;
reg valid_c4;
wire stall_c4;
wire enable_c4 = (HIGH_CAPACITY == 1) ? (~valid_c4 | ~stall_c4) : enable;
assign stall_c3 = valid_c4 & stall_c4;
assign stall_c4 = stall_in;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
result_c4 <= 9'dx;
valid_c4 <= 1'b0;
end
else if (enable_c4)
begin
valid_c4 <= valid_c3;
case(ROUNDING_MODE)
2:
begin // 2 is round to zero
if (UNSIGNED == 0)
begin
result_c4 <= ({9{sign_c3}} ^ (extended_mantissa_c3[10:3])) + sign_c3;
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3];
end
end
4:
begin // 4 is round down
if (|extended_mantissa_c3[2:0])
begin
if (UNSIGNED == 0)
begin
result_c4 <= (sign_c3) ? (({9{sign_c3}} ^ (extended_mantissa_c3[10:3] + 1'b1)) + 1'b1) : extended_mantissa_c3[10:3];
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3];
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
3:
begin // 3 is round up
if (|extended_mantissa_c3[2:0])
begin
if (UNSIGNED == 0)
begin
result_c4 <= (sign_c3) ? (({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + 1'b1) : (extended_mantissa_c3[10:3] + 1'b1);
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
1:
begin // 1 is round to nearest with ties rounded away from zero.
if (extended_mantissa_c3[2])
begin
if (UNSIGNED == 0)
begin
result_c4 <= ({9{sign_c3}} ^ (extended_mantissa_c3[10:3] + 1'b1)) + sign_c3;
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
default:
begin // 0 and default are round to nearest even
if ((extended_mantissa_c3[3:0] == 4'hc) | (extended_mantissa_c3[2] & (|extended_mantissa_c3[1:0])))
begin
if (UNSIGNED == 0)
begin
result_c4 <= ({9{sign_c3}} ^ (extended_mantissa_c3[10:3] + 1'b1)) + sign_c3;
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
endcase
end
end
// handle saturation here too, just in case rounding went over the limit of the expected range.
assign result = (UNSIGNED == 1) ? ({8{result_c4[8]}} | result_c4) : ((result_c4[8] ^ result_c4[7]) ? {result_c4[8], {7{~result_c4[8]}}} : result_c4[7:0]);
assign valid_out = valid_c4;
endmodule
|
#include <bits/stdc++.h> using namespace std; int o, e, oC, eC, n, en; int main() { cin >> n; for (int i = 1; i <= n; i++) { cin >> en; if (en % 2 == 0) { e = i; eC++; } else { o = i; oC++; } } if (oC == 1) cout << o; else cout << e; } |
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// UTMI Interface ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/usb/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: usbf_utmi_if.v,v 1.1 2008/05/07 22:43:23 daughtry Exp $
//
// $Date: 2008/05/07 22:43:23 $
// $Revision: 1.1 $
// $Author: daughtry $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: usbf_utmi_if.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.5 2003/11/11 07:15:16 rudi
// Fixed Resume signaling and initial attachment
//
// Revision 1.4 2003/10/17 02:36:57 rudi
// - Disabling bit stuffing and NRZI encoding during speed negotiation
// - Now the core can send zero size packets
// - Fixed register addresses for some of the higher endpoints
// (conversion between decimal/hex was wrong)
// - The core now does properly evaluate the function address to
// determine if the packet was intended for it.
// - Various other minor bugs and typos
//
// Revision 1.3 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.2 2001/09/24 01:15:28 rudi
//
// Changed reset to be active high async.
//
// Revision 1.1 2001/08/03 05:30:09 rudi
//
//
// 1) Reorganized directory structure
//
// Revision 1.2 2001/03/31 13:00:52 rudi
//
// - Added Core configuration
// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode
// - Modified WISHBONE interface and sync logic
// - Moved SSRAM outside the core (added interface)
// - Many small bug fixes ...
//
// Revision 1.0 2001/03/07 09:17:12 rudi
//
//
// Changed all revisions to revision 1.0. This is because OpenCores CVS
// interface could not handle the original '0.1' revision ....
//
// Revision 0.2 2001/03/07 09:08:13 rudi
//
// Added USB control signaling (Line Status) block. Fixed some minor
// typos, added resume bit and signal.
//
// Revision 0.1.0.1 2001/02/28 08:11:45 rudi
// Initial Release
//
//
`include "usbf_defines.v"
module usbf_utmi_if( // UTMI Interface (EXTERNAL)
phy_clk, rst,
DataOut, TxValid, TxReady,
RxValid, RxActive, RxError, DataIn,
XcvSelect, TermSel, SuspendM, LineState,
OpMode, usb_vbus,
// Internal Interface
rx_data, rx_valid, rx_active, rx_err,
tx_data, tx_valid, tx_valid_last, tx_ready,
tx_first,
// Misc Interfaces
mode_hs, usb_reset, usb_suspend, usb_attached,
resume_req, suspend_clr
);
input phy_clk;
//input wclk;
input rst;
output [7:0] DataOut;
output reg TxValid;
input TxReady;
input [7:0] DataIn;
input RxValid;
input RxActive;
input RxError;
output XcvSelect;
output TermSel;
output SuspendM;
input [1:0] LineState;
output [1:0] OpMode;
input usb_vbus;
output [7:0] rx_data;
output rx_valid, rx_active, rx_err;
input [7:0] tx_data;
input tx_valid;
input tx_valid_last;
output tx_ready;
input tx_first;
output mode_hs; // High Speed Mode
output usb_reset; // USB Reset
output usb_suspend; // USB Suspend
output usb_attached; // Attached to USB
input resume_req;
output suspend_clr;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
reg [7:0] rx_data;
reg rx_valid, rx_active, rx_err;
reg [7:0] DataOut;
reg tx_ready;
wire drive_k;
reg drive_k_r;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
///////////////////////////////////////////////////////////////////
//
// RX Interface Input registers
//
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) rx_valid <= 1'b0;
//to the prefered high reset
if(rst) rx_valid <= 1'b0;
else rx_valid <= RxValid;
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) rx_active <= 1'b0;
//to the prefered high reset
if(rst) rx_active <= 1'b0;
else rx_active <= RxActive;
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) rx_err <= 1'b0;
//to the prefered high reset
if(rst) rx_err <= 1'b0;
else rx_err <= RxError;
always @(posedge phy_clk)
rx_data <= DataIn;
///////////////////////////////////////////////////////////////////
//
// TX Interface Output/Input registers
//
always @(posedge phy_clk)
if(tx_ready || tx_first) DataOut <= tx_data;
else
if(drive_k) DataOut <= 8'h00;
always @(posedge phy_clk)
tx_ready <= TxReady;
always @(posedge phy_clk)
drive_k_r <= drive_k;
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) TxValid <= 1'b0;
//to the prefered high reset
if(rst) TxValid <= 1'b0;
else
TxValid <= tx_valid | drive_k | tx_valid_last | (TxValid & !(tx_ready | drive_k_r));
///////////////////////////////////////////////////////////////////
//
// Line Status Signaling & Speed Negotiation Block
//
usbf_utmi_ls u0(
.clk( phy_clk ),
.rst( rst ),
.resume_req( resume_req ),
.rx_active( rx_active ),
.tx_ready( tx_ready ),
.drive_k( drive_k ),
.XcvSelect( XcvSelect ),
.TermSel( TermSel ),
.SuspendM( SuspendM ),
.LineState( LineState ),
.OpMode( OpMode ),
.usb_vbus( usb_vbus ),
.mode_hs( mode_hs ),
.usb_reset( usb_reset ),
.usb_suspend( usb_suspend ),
.usb_attached( usb_attached ),
.suspend_clr( suspend_clr )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_1_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_1_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog wrapper for inputiso1p with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inputiso1p.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inputiso1p_1 (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__inputiso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__inputiso1p_1 (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__inputiso1p base (
.X(X),
.A(A),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_1_V
|
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 1ns/100ps
module RAM(
i_addr,
i_enable_x,
i_write_x,
i_data,
o_data);
parameter delay = 10;
parameter depth = 16;
parameter width = 8;
input [depth - 1:0] i_addr;
input i_enable_x;
input i_write_x;
input [width - 1:0] i_data;
output [width - 1:0] o_data;
reg [width - 1:0] o_data;
reg [width - 1:0] r_ram[0:2**depth];
reg [depth - 1:0] r_addr;
reg r_enable_x;
reg r_write_x;
reg [width - 1:0] r_data;
always r_addr = #delay i_addr;
always r_enable_x = #delay i_enable_x;
always r_write_x = #delay i_write_x;
always r_data = #delay i_data;
always @ (r_addr or r_enable_x or r_write_x or r_data) begin
if (r_enable_x) begin
o_data <= {width{1'bz}};
end else if (r_write_x) begin
o_data <= r_ram[r_addr];
end else begin
o_data <= {width{1'bx}};
r_ram[r_addr] <= r_data;
end
end
endmodule // module RAM
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:268435456 ) using namespace std; template <typename T> T sqr(const T &x) { return x * x; } template <typename T> T my_abs(const T &x) { return x < 0 ? -x : x; } const int INF = (int)1e9; const long long LINF = (long long)6e18; const long long INF64 = LINF; const long long INFLL = LINF; const long double EPS = 1e-8; const long double PI = 3.1415926535897932384626433832795; const long double ME = 1e-5; const long long MOD = (int)1e9 + 7; const long long MOD2 = (int)1e9 + 21; const int dx[] = {-1, 0, 1, 0}; const int dy[] = {0, 1, 0, -1}; const int SQN = 400; const int LOGN = 20; const int N = (int)1e5 + 10; const int M = (int)1e5 + 10; map<string, int> hosts; map<string, int> paths; map<int, set<int>> nums; string oh[N]; char buf[100]; pair<vector<int>, int> a[N]; void solve() { int n; scanf( %d n , &n); int idx_host = 0, idx_path = 0; for (int i = 0; i < int(n); ++i) { scanf( %s n , buf); string s = string(buf); string h = ; int cnt = 0; int pos = 0; while (pos < int(s.size())) { if (s[pos] == / ) { cnt++; } if (cnt == 3) { break; } h.push_back(s[pos++]); } string p = ; while (pos < int(s.size())) { p.push_back(s[pos++]); } if (!hosts.count(h)) { oh[idx_host] = h; hosts[h] = idx_host++; } if (!paths.count(p)) { paths[p] = idx_path++; } nums[hosts[h]].insert(paths[p]); } int idx = 0; for (auto it = nums.begin(); it != nums.end(); ++it) { a[idx].first.resize(int(it->second.size())); a[idx].second = it->first; int pos = 0; for (auto i = it->second.begin(); i != it->second.end(); ++i) { a[idx].first[pos++] = *i; } idx++; } sort(a, a + idx); vector<vector<int>> ans; ans.push_back(vector<int>()); for (int i = 1; i < int(idx); ++i) { bool ok = true; if (int(a[i].first.size()) != int(a[i - 1].first.size())) { ok = false; } else { for (int j = 0; j < int(int(a[i].first.size())); ++j) { if (a[i].first[j] != a[i - 1].first[j]) { ok = false; break; } } } if (ok) { if (int(ans.back().size()) == 0) { ans.back().push_back(a[i - 1].second); } ans.back().push_back(a[i].second); } else { if (int(ans.back().size()) != 0) { ans.push_back(vector<int>()); } } } if (int(ans.back().size()) == 0) { ans.pop_back(); } printf( %d n , ans.size()); for (int i = 0; i < int(int(ans.size())); ++i) { for (int j = 0; j < int(int(ans[i].size())); ++j) { printf( %s , oh[ans[i][j]].c_str()); } printf( n ); } } int main() { srand((unsigned int)time(NULL)); cout << setprecision(10) << fixed; solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 250 + 7; int a[MAXN][MAXN], ans[MAXN][MAXN]; bool rmax[MAXN * MAXN], cmax[MAXN * MAXN], vis[MAXN * MAXN]; bool canr[MAXN], canc[MAXN]; int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { scanf( %d , &a[i][j]); } for (int i = 1; i <= n; i++) { int MAX = 0; for (int j = 1; j <= m; j++) MAX = max(MAX, a[i][j]); rmax[MAX] = 1; } for (int j = 1; j <= m; j++) { int MAX = 0; for (int i = 1; i <= n; i++) MAX = max(MAX, a[i][j]); cmax[MAX] = 1; } int x = 0, y = 0; queue<pair<int, int> > pos; for (int num = n * m; num >= 1; num--) { x += rmax[num]; y += cmax[num]; if (rmax[num] || cmax[num]) { ans[x][y] = num; } else { pair<int, int> p = pos.front(); pos.pop(); ans[p.first][p.second] = num; } if (rmax[num]) { canr[x] = 1; for (int j = y - 1; j >= 1; j--) if (canc[j]) pos.push({x, j}); for (int j = y + 1; j <= m; j++) if (canc[j]) pos.push({x, j}); } if (cmax[num]) { canc[y] = 1; for (int i = x - 1; i >= 1; i--) if (canr[i]) pos.push({i, y}); for (int i = x + 1; i <= n; i++) if (canr[i]) pos.push({i, y}); } } for (int i = 1; i <= n; i++, puts( )) for (int j = 1; j <= m; j++) printf( %d , ans[i][j]); return 0; } |
//-------------------------------------------------------------------
//-- counter4_tb.v
//-- Banco de pruebas para el contador de 4 bits con prescaler
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
module counter4_tb();
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Datos de salida del contador
wire [3:0] data;
//-- Registro para comprobar si el contador cuenta correctamente
reg [3:0] counter_check = 0;
//-- Instanciar el contador, con prescaler de 1 bit (para la simulacion)
counter4 #(.N(1))
C1(
.clk(clk),
.data(data)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk = ~clk;
//-- Proceso de comprobación. Cada vez que hay un cambio en
//-- el contador se comprueba con el valor de prueba
always @(data) begin
if (counter_check != data)
$display("-->ERROR!. Esperado: %d. Leido: %d",counter_check, data);
counter_check = counter_check + 1;
end
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("counter4_tb.vcd");
$dumpvars(0, counter4_tb);
//-- Comprobación del reset.
# 0.5 if (data != 0)
$display("ERROR! Contador NO está a 0!");
else
$display("Contador inicializado. OK.");
# 99 $display("FIN de la simulacion");
# 100 $finish;
end
endmodule
|
#include <bits/stdc++.h> int cmpfnc(const void* a, const void* b) { return (*(int*)a - *(int*)b); } int main() { int i, n; scanf( %d , &n); int arr[300005]; for (i = 0; i < n; i++) scanf( %d , &arr[i]); qsort(arr, n, sizeof(int), cmpfnc); long long int sum = arr[0]; long long int count = 1; long long int t2 = 0; for (i = 1; i < n; i++) { long long int t3 = ((count % 1000000007) * (arr[i] % 1000000007)) % 1000000007; t2 = (t2 + (t3 - sum + 1000000007) % 1000000007) % 1000000007; sum = (sum * 2 + arr[i]) % 1000000007; count = (count * 2 + 1) % 1000000007; } printf( %lld n , t2); return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx ) using namespace std; namespace SimplexMethod { const long double EPS = 1.0E-12; vector<vector<long double>> a; vector<long double> b, c, res; vector<int> N, kt; int m; void pivot(int k, int s, int e) { int first = kt[s]; long double p = a[s][e]; for (int _n((k)-1), i(0); i <= _n; i++) a[s][i] /= p; b[s] /= p; N[e] = false; for (int _n((m)-1), i(0); i <= _n; i++) if (i != s) { b[i] -= a[i][e] * b[s]; a[i][first] = -a[i][e] * a[s][first]; } for (int _n((k)-1), j(0); j <= _n; j++) if (N[j]) { c[j] -= c[e] * a[s][j]; for (int _n((m)-1), i(0); i <= _n; i++) if (i != s) a[i][j] -= a[i][e] * a[s][j]; } kt[s] = e; N[first] = true; c[first] = -c[e] * a[s][first]; } vector<long double> doit(int k) { vector<long double> res; while (true) { int e = -1, s = -1; for (int _n((k)-1), i(0); i <= _n; i++) if (N[i] && c[i] > EPS) { e = i; break; } if (e == -1) break; for (int _n((m)-1), i(0); i <= _n; i++) if (a[i][e] > EPS && (s == -1 || b[i] / a[i][e] < b[s] / a[s][e])) s = i; if (s == -1) return vector<long double>(); pivot(k, s, e); } res.resize(k, 0); for (int _n((m)-1), i(0); i <= _n; i++) res[kt[i]] = b[i]; return res; } void apply_rand(vector<long double>& a, const vector<int>& ind) { for (int _n(((int)((a).size())) - 1), i(0); i <= _n; i++) { if (i < ind[i]) { swap(a[i], a[ind[i]]); } } } long double simplex(vector<vector<long double>> _A, vector<long double> _b, vector<long double> _c) { vector<int> ind((int)((_A[0]).size())); for (int _n(((int)((ind).size())) - 1), i(0); i <= _n; i++) { ind[i] = i; } srand(std::chrono::duration_cast<std::chrono::nanoseconds>( (std::chrono::high_resolution_clock::now().time_since_epoch())) .count() + time(0)); auto rgen = [](int n) -> unsigned { return ((unsigned)(rand() << 15) + (unsigned)rand()) % n; }; random_shuffle(ind.begin(), ind.end(), rgen); for (int _n(((int)((_A).size())) - 1), i(0); i <= _n; i++) { apply_rand(_A[i], ind); } apply_rand(_c, ind); a = _A; b = _b; c = _c; m = (int)((a).size()); int n = (int)((a[0]).size()); int k = n + m + 1; c.resize(n + m); kt.resize(m); N = vector<int>(k, true); for (int _n((m)-1), i(0); i <= _n; i++) { a[i].resize(k); a[i][n + i] = 1; a[i][k - 1] = -1; kt[i] = n + i; N[kt[i]] = false; } int s = min_element((b).begin(), (b).end()) - b.begin(); if (b[s] < -EPS) { c = vector<long double>(k, 0); c[k - 1] = -1; pivot(k, s, k - 1); res = doit(k); if (res[k - 1] > EPS) return -1e100; for (int _n((m)-1), i(0); i <= _n; i++) if (kt[i] == k - 1) for (int _n((k - 1) - 1), j(0); j <= _n; j++) if (N[j] && (a[i][j] < -EPS || EPS < a[i][j])) { pivot(k, i, j); break; } c = _c; c.resize(k, 0); for (int _n((m)-1), i(0); i <= _n; i++) for (int _n((k)-1), j(0); j <= _n; j++) if (N[j]) c[j] -= c[kt[i]] * a[i][j]; } res = doit(k - 1); if (!res.empty()) res.resize(n); long double ans = 0.0; for (int _n(((int)((res).size())) - 1), i(0); i <= _n; i++) { ans += res[i] * _c[i]; } return ans; } } // namespace SimplexMethod int d, n, m, k, p, q; int main() { scanf( %d%d%d , &n, &p, &q); vector<long double> a, b, c; a.resize(n); b.resize(n); c.resize(n); vector<pair<int, int>> tp; for (int _n((n)-1), i(0); i <= _n; i++) { int first, second; scanf( %d%d , &first, &second); tp.push_back(make_pair(first, second)); } for (int _n((n)-1), i(0); i <= _n; i++) { int first = tp[i].first, second = tp[i].second; a[i] = -first; b[i] = -second; c[i] = -1.0; } vector<vector<long double>> A; A.push_back(a); A.push_back(b); vector<long double> B; B.push_back(-p); B.push_back(-q); auto res = -SimplexMethod::simplex(A, B, c); printf( %.12lf n , (double)res); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, pos, cnt = 0; cin >> n >> a >> b; for (int pos = 1; pos <= n; pos++) { if (n - pos <= b && pos - 1 >= a) cnt++; } cout << cnt; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; mt19937 rnd(chrono::high_resolution_clock::now().time_since_epoch().count()); template <typename T> bool uax(T& a, T b) { if (a < b) { a = b; return true; } return false; } template <typename T> bool uin(T& a, const T b) { if (a > b) { a = b; return true; } return false; } template <typename T1, typename T2> istream& operator>>(istream& in, pair<T1, T2>& p) { in >> p.first >> p.second; return in; } template <typename T1, typename T2> ostream& operator<<(ostream& out, pair<T1, T2>& p) { out << p.first << << p.second; return out; } const int N = 200 + 7; int n; vector<int> g[N]; vector<int> p[N]; int sz[N]; int ans[N]; vector<int> wr; int s[N]; bool used[N]; int last_ind = 0; int arr[N]; void del(int x) { used[x] = true; for (int i = 0; i < p[x].size(); i++) { s[p[x][i]]--; if (s[p[x][i]] == 1) { arr[last_ind++] = p[x][i]; } } } bool solve(int x) { last_ind = 0; for (int i = 0; i <= n; i++) { s[i] = sz[i]; used[i] = false; } ans[0] = x; del(x); for (int i = 1; i < n; i++) { if (last_ind != 1) { return false; } int ind = arr[0]; int cur = 0; for (int j = 0; j < g[ind].size(); j++) { if (!used[g[ind][j]]) cur = g[ind][j]; } ans[i] = cur; wr.clear(); for (int j = 0; j < sz[ind]; j++) { wr.push_back(ans[i - j]); } sort(wr.begin(), wr.end()); for (int j = 0; j < g[ind].size(); j++) { if (g[ind][j] != wr[j]) return false; } last_ind = 0; del(cur); } for (int i = 0; i < n; i++) { cout << ans[i] << ; } cout << n ; return true; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long T; cin >> T; while (T--) { fill(p, p + n + 1, vector<int>()); cin >> n; int k; for (int i = 0; i < n - 1; i++) { cin >> k; g[i].resize(k); sz[i] = k; for (int j = 0; j < k; j++) { cin >> g[i][j]; p[g[i][j]].push_back(i); } } for (int i = 1; i <= n; i++) { if (solve(i)) { break; } } } } |
#include <bits/stdc++.h> using namespace std; template <class T, class L> bool smax(T& x, L y) { return x < y ? (x = y, 1) : 0; } template <class T, class L> bool smin(T& x, L y) { return x > y ? (x = y, 1) : 0; } const int maxn = 16; int n, a[maxn], b[maxn][maxn], ex; bool mark[maxn]; vector<vector<int> > all; void bt(int s = 0) { if (s == n) { for (int i = 0, sum = 0; i < n; i++, sum = 0) { for (int j = 0; j < n; j++) sum += b[j][i]; if (sum != ex) return; } { int sum = 0; for (int i = 0; i < n; i++) sum += b[i][i]; if (sum != ex) return; } { int sum = 0; for (int i = 0; i < n; i++) sum += b[i][n - i - 1]; if (sum != ex) return; } for (int i = 0; i < n; i++, cout << n ) for (int j = 0; j < n; j++) cout << b[i][j] << ; exit(0); } for (auto v : all) { bool reval = 1; for (auto x : v) if (mark[x]) { reval = 0; break; } if (!reval) continue; do { for (int i = 0; i < n; i++) b[s][i] = a[v[i]], mark[v[i]] = 1; bt(s + 1); for (int i = 0; i < n; i++) mark[v[i]] = 0; } while (next_permutation(v.begin(), v.end())); } } int main() { ios::sync_with_stdio(0), cin.tie(); cin >> n; for (int i = 0; i < n * n; i++) cin >> a[i], ex += a[i]; ex /= n; cout << ex << n ; for (int i = 0; i < 1 << n * n; i++) if (__builtin_popcount(i) == n) { int sum = 0; for (int j = 0; j < n * n; j++) sum += (i >> j & 1) * a[j]; if (sum == ex) { all.push_back({}); for (int j = 0; j < n * n; j++) if (i >> j & 1) all.back().push_back(j); sort(all.back().begin(), all.back().end()); } } bt(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDLCLKP_2_V
`define SKY130_FD_SC_HS__SDLCLKP_2_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog wrapper for sdlclkp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdlclkp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdlclkp_2 (
GCLK,
GATE,
CLK ,
SCE ,
VPWR,
VGND
);
output GCLK;
input GATE;
input CLK ;
input SCE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__sdlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdlclkp_2 (
GCLK,
GATE,
CLK ,
SCE
);
output GCLK;
input GATE;
input CLK ;
input SCE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdlclkp base (
.GCLK(GCLK),
.GATE(GATE),
.CLK(CLK),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDLCLKP_2_V
|
module usb_top(
input I_sys_clk ,
input I_usb_clk ,
input I_sys_rst ,
input I_usb_rst ,
//===================System GPIF data in/out====================
input I_usb_wfifo_aclr ,
input I_usb_wrreq ,
input [15: 0] I_usb_din ,
output O_usb_wrfull ,
output [15: 0] O_usb_wruesdw ,
input I_usb_rdreq ,
output [31: 0] O_usb_dout ,
output O_usb_rdempty ,
//=====================System usb_uart_if===========================
input I_usb_uart_tx_req ,
input [7 : 0] I_usb_uart_tx_data ,
output O_usb_uart_tx_full ,
input I_usb_uart_rx_req ,
output [7 : 0] O_usb_uart_rx_data ,
output O_usb_uart_rx_empty ,
//==================USB3.0 IO=======================================
output O_usb_pclk , //not used
output O_usb_clk , //not used
input I_usb_flga ,
input I_usb_flgb ,
output O_usb_cs , // CTL[0] SLCS#
output O_usb_wr , // CTL[1] SLWR#
output O_usb_rd , // CTL[2] SLOE#
output O_usb_oe , // CTL[3] SLRD#
output O_usb_a0 , // CTL[4] FLAGA
output O_usb_a1 , // CTL[5] FLAGB
output O_usb_pkt , // CTL[7] PKTEND#
output O_usb_reset , // CTL[12] A0
// CTL[11] A1
inout [31:0] IO_usb_dq ,
output O_usb_uart_txd ,
input I_usb_uart_rxd ,
input I_usb_dir
);
usb_gpif_ctrl usb_gpif_ctrl_inst(
.I_sys_clk (I_sys_clk ),
.I_usb_clk (I_usb_clk ),
.I_sys_rst (I_sys_rst ),
.I_usb_rst (I_usb_rst ),
.I_usb_wfifo_aclr (I_usb_wfifo_aclr ),
.I_usb_wrreq (I_usb_wrreq ),
.I_usb_din (I_usb_din ),
.O_usb_wrfull (O_usb_wrfull ),
.O_usb_wruesdw (O_usb_wruesdw ),
.I_usb_rdreq (I_usb_rdreq ),
.O_usb_dout (O_usb_dout ),
.O_usb_rdempty (O_usb_rdempty ),
.O_usb_pclk (O_usb_pclk ),
.O_usb_clk (O_usb_clk ),
.I_usb_flga (I_usb_flga ),
.I_usb_flgb (I_usb_flgb ),
.O_usb_cs (O_usb_cs ),
.O_usb_wr (O_usb_wr ),
.O_usb_rd (O_usb_rd ),
.O_usb_oe (O_usb_oe ),
.O_usb_a0 (O_usb_a0 ), // 0 wr ,1 rd
.O_usb_a1 (O_usb_a1 ),
.O_usb_pkt (O_usb_pkt ),
.O_usb_reset (O_usb_reset ),
.IO_usb_dq (IO_usb_dq ),
.I_usb_dir (I_usb_dir )
);
usb_uart usb_uart_inst(
.I_sys_clk (I_sys_clk ),
.I_usb_clk (I_usb_clk ),
.I_sys_rst (I_sys_rst ),
.I_usb_rst (I_usb_rst ),
.I_usb_uart_tx_req (I_usb_uart_tx_req ),
.I_usb_uart_tx_data (I_usb_uart_tx_data ),
.O_usb_uart_tx_full (O_usb_uart_tx_full ),
.I_usb_uart_rx_req (I_usb_uart_rx_req ),
.O_usb_uart_rx_data (O_usb_uart_rx_data ),
.O_usb_uart_rx_empty (O_usb_uart_rx_empty ),
.O_usb_uart_txd (O_usb_uart_txd ),
.I_usb_uart_rxd (I_usb_uart_rxd )
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
module secret (
input [31:0] accum_in,
output wire [31:0] accum_out,
input accum_bypass,
output [31:0] accum_bypass_out,
input s1_in,
output logic s1_out,
input [1:0] s2_in,
output logic [1:0] s2_out,
input [7:0] s8_in,
output logic [7:0] s8_out,
input [32:0] s33_in,
output logic [32:0] s33_out,
input [63:0] s64_in,
output logic [63:0] s64_out,
input [64:0] s65_in,
output logic [64:0] s65_out,
input [128:0] s129_in,
output logic [128:0] s129_out,
input [3:0] [31:0] s4x32_in,
output logic [3:0] [31:0] s4x32_out,
input clk);
logic [31:0] secret_accum_q = 0;
logic [31:0] secret_value = 7;
initial $display("created %m");
always @(posedge clk) begin
secret_accum_q <= secret_accum_q + accum_in + secret_value;
end
// Test combinatorial paths of different sizes
always @(*) begin
s1_out = s1_in;
s2_out = s2_in;
s8_out = s8_in;
s33_out = s33_in;
s64_out = s64_in;
s65_out = s65_in;
s129_out = s129_in;
s4x32_out = s4x32_in;
end
// Test sequential path
assign accum_out = secret_accum_q;
// Test mixed combinatorial/sequential path
assign accum_bypass_out = accum_bypass ? accum_in : secret_accum_q;
final $display("destroying %m");
endmodule
|
#include <bits/stdc++.h> using namespace std; map<long long, long long> mp; long long ar[200005]; long long br[200005]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; t = 1; while (t--) { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> ar[i]; } long long prv = 1; mp[0] = 0; long long ans = 0; for (int i = 1; i <= n; i++) { br[i] = br[i - 1] + ar[i]; if (mp.count(br[i])) { prv = max(prv, mp[br[i]] + 2); } ans += i - prv + 1; mp[br[i]] = i; } cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; const int N = 2e6 + 10; int n, a[N], vis[N]; int main() { scanf( %d , &n); int64_t ans = 0; int f = 0, g = 1, pos = 0; for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); ans += abs(a[i] - i); if (a[i] == 1) continue; if (a[i] > i) ++f, ++vis[a[i] - i]; else ++g, ++vis[a[i] - i + n]; } int64_t ret = ans; for (int k = 1; k < n; ++k) { ret -= abs(n + 1 - a[n - k + 1]); ret += abs(1 - a[n - k + 1]); ret += -f + g; if (a[n - k + 1] != 1) ++f, --g; f -= vis[k]; g += vis[k]; if (ret < ans) ans = ret, pos = k; } printf( %lld %d n , ans, pos); } |
#include <bits/stdc++.h> using namespace std; int main() { string a, b, c; cin >> a >> b; sort(a.begin(), a.end()); if (a.length() < b.length()) { reverse(a.begin(), a.end()); cout << a << endl; } else { for (int i = 0; i < a.length(); i++) { for (int j = a.length() - 1; j > i; j--) { c = a; swap(a[i], a[j]); sort(a.begin() + i + 1, a.end()); if (a > b) { a = c; } else break; } } cout << a << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, p; string s, number; cin >> n; string name[n]; int taxi[n], pizza[n], cg[n], tax, pizz, cgc, taxmax = -1, pizzmax = -1, cgcmax = -1; int taxifinal[n], pizzafinal[n], cgcfinal[n], ct = 0, cp = 0, cc = 0; for (int i = 0; i < n; i++) { cin >> p >> name[i]; tax = 0; pizz = 0; cgc = 0; for (int j = 0; j < p; j++) { cin >> number; if (((number[0] == number[3]) && (number[3] == number[6])) && ((number[0] == number[1]) && (number[3] == number[4]) && (number[6] == number[7]))) { tax++; } else if ((int(number[0]) > int(number[1])) && (int(number[1]) > int(number[3])) && (int(number[3]) > int(number[4])) && (int(number[4]) > int(number[6])) && (int(number[6]) > int(number[7]))) { pizz++; } else { cgc++; } } taxi[i] = tax; pizza[i] = pizz; cg[i] = cgc; } for (int i = 0; i < n; i++) { taxmax = max(taxmax, taxi[i]); pizzmax = max(pizzmax, pizza[i]); cgcmax = max(cgcmax, cg[i]); } for (int i = 0; i < n; i++) { if (taxmax == taxi[i]) { taxifinal[ct] = i; ct++; } if (pizzmax == pizza[i]) { pizzafinal[cp] = i; cp++; } if (cgcmax == cg[i]) { cgcfinal[cc] = i; cc++; } } cout << If you want to call a taxi, you should call: ; if (ct > 1) { for (int j = 0; j < ct - 1; j++) { cout << << name[taxifinal[j]] << , ; } cout << << name[taxifinal[ct - 1]] << . << endl; } else { cout << << name[taxifinal[ct - 1]] << . << endl; } cout << If you want to order a pizza, you should call: ; if (cp > 1) { for (int j = 0; j < cp - 1; j++) { cout << << name[pizzafinal[j]] << , ; } cout << << name[pizzafinal[cp - 1]] << . << endl; } else { cout << << name[pizzafinal[cp - 1]] << . << endl; } cout << If you want to go to a cafe with a wonderful girl, you should call: ; if (cc > 1) { for (int j = 0; j < cc - 1; j++) { cout << << name[cgcfinal[j]] << , ; } cout << << name[cgcfinal[cc - 1]] << . << endl; } else { cout << << name[cgcfinal[cc - 1]] << . << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1024; double p[MAXN][MAXN]; int a[MAXN]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) { scanf( %d , a + i); for (int j = 0; j < i; ++j) p[i][j] = a[i] > a[j], p[j][i] = 1 - p[i][j]; } for (int x, y; m--;) { scanf( %d%d , &x, &y), --x, --y; for (int i = 0; i < n; ++i) if (i != x && i != y) { p[i][x] = p[i][y] = (p[i][x] + p[i][y]) / 2; p[x][i] = p[y][i] = 1 - p[i][x]; } p[x][y] = (p[x][y] + p[y][x]) / 2, p[y][x] = 1 - p[x][y]; } double e = 0; for (int i = 0; i < n; ++i) for (int j = i + 1; j < n; ++j) e += p[i][j]; printf( %.16lf n , e); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> XandY, XXX, YYY; int NOseg; int query(int x, int y) { cout << 0 << << x << << y << endl; int ret; cin >> ret; return ret; } void SOLVE(int l, int r) { if (l > r) return; int mid = (l + r) / 2; int x = query(mid, mid); if (x == 0) XandY.push_back(mid), x = 1; else NOseg = mid; SOLVE(l, mid - x); SOLVE(mid + x, r); } void solve() { SOLVE(-100000000, 100000000); for (int k : XandY) { if (query(NOseg, k) == 0) YYY.push_back(k); if (query(k, NOseg) == 0) XXX.push_back(k); } } int main() { solve(); cout << 1 << XXX.size() << << YYY.size() << endl; for (int x : XXX) cout << x << ; cout << endl; for (int y : YYY) cout << y << ; cout << endl; } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module bus_to_ip
#(
parameter BASEADDR = 0,
parameter HIGHADDR = 0,
parameter ABUSWIDTH = 16,
parameter DBUSWIDTH = 8
)
(
input wire BUS_RD,
input wire BUS_WR,
input wire [ABUSWIDTH-1:0] BUS_ADD,
inout wire [DBUSWIDTH-1:0] BUS_DATA,
output wire IP_RD,
output wire IP_WR,
output wire [ABUSWIDTH-1:0] IP_ADD,
output wire [DBUSWIDTH-1:0] IP_DATA_IN,
input wire [DBUSWIDTH-1:0] IP_DATA_OUT
);
wire CS;
/* verilator lint_off UNSIGNED */
assign CS = (BUS_ADD >= BASEADDR && BUS_ADD <= HIGHADDR);
/* verilator lint_on UNSIGNED */
assign IP_ADD = CS ? BUS_ADD - BASEADDR : {ABUSWIDTH{1'b0}};
assign IP_RD = CS ? BUS_RD : 1'b0;
assign IP_WR = CS ? BUS_WR: 1'b0;
assign IP_DATA_IN = BUS_DATA;
assign BUS_DATA = (CS && BUS_WR) ? {DBUSWIDTH{1'bz}} : (CS ? IP_DATA_OUT : {DBUSWIDTH{1'bz}});
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module simple_gemac_tb;
`include "eth_tasks.v"
reg clk = 0;
reg reset = 1;
initial #1000 reset = 0;
always #50 clk = ~clk;
wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
wire [7:0] GMII_RXD, GMII_TXD;
wire rx_valid, rx_error, rx_ack;
wire tx_ack, tx_valid, tx_error;
wire [7:0] rx_data, tx_data;
reg [15:0] pause_time;
reg pause_req = 0;
wire GMII_RX_CLK = GMII_GTX_CLK;
reg [7:0] FORCE_DAT_ERR = 0;
reg FORCE_ERR = 0;
// Loopback
assign GMII_RX_DV = GMII_TX_EN;
assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR;
assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR;
wire [47:0] ucast_addr = 48'hF1F2_F3F4_F5F6;
wire [47:0] mcast_addr = 0;
wire pass_ucast =1, pass_mcast=0, pass_bcast=1, pass_pause=0, pass_all=0;
simple_gemac simple_gemac
(.clk125(clk), .reset(reset),
.GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
.pause_req(pause_req), .pause_time(pause_time), .pause_en(1),
.ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
.pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast),
.pass_pause(pass_pause), .pass_all(pass_all),
.rx_clk(rx_clk), .rx_data(rx_data),
.rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
.tx_clk(tx_clk), .tx_data(tx_data),
.tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack)
);
wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2;
reg rx_ll_dst_rdy2 = 1;
wire [7:0] rx_ll_data, rx_ll_data2;
wire rx_ll_error, rx_ll_error2;
rxmac_to_ll8 rx_adapt
(.clk(clk), .reset(reset), .clear(0),
.rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
.ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(rx_ll_error),
.ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
ll8_shortfifo rx_sfifo
(.clk(clk), .reset(reset), .clear(0),
.datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof),
.error_i(rx_ll_error), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy),
.dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2),
.error_o(rx_ll_error2), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2));
wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
reg tx_ll_sof2=0, tx_ll_eof2=0;
reg tx_ll_src_rdy2 = 0;
wire tx_ll_dst_rdy2;
wire [7:0] tx_ll_data;
reg [7:0] tx_ll_data2 = 0;
wire tx_ll_error;
wire tx_ll_error2 = 0;
ll8_shortfifo tx_sfifo
(.clk(clk), .reset(reset), .clear(clear),
.datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
.error_i(tx_ll_error2), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
.dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
.error_o(tx_ll_error), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
ll8_to_txmac ll8_to_txmac
(.clk(clk), .reset(reset), .clear(clear),
.ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
.ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
.tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
initial $dumpfile("simple_gemac_tb.vcd");
initial $dumpvars(0,simple_gemac_tb);
integer i;
reg [7:0] pkt_rom[0:65535];
reg [1023:0] ROMFile;
initial
for (i=0;i<65536;i=i+1)
pkt_rom[i] <= 8'h0;
initial
begin
@(negedge reset);
repeat (10)
@(posedge clk);
SendFlowCtrl(16'h0007); // Send flow control
@(posedge clk);
#30000;
@(posedge clk);
SendFlowCtrl(16'h0009); // Increas flow control before it expires
#10000;
@(posedge clk);
SendFlowCtrl(16'h0000); // Cancel flow control before it expires
@(posedge clk);
SendPacket_to_ll8(8'hAA,10); // This packet gets dropped by the filters
repeat (10)
@(posedge clk);
SendPacketFromFile_ll8(60,0,0); // The rest are valid packets
repeat (10)
@(posedge clk);
SendPacketFromFile_ll8(61,0,0);
repeat (10)
@(posedge clk);
SendPacketFromFile_ll8(62,0,0);
repeat (10)
@(posedge clk);
SendPacketFromFile_ll8(63,0,0);
repeat (1)
@(posedge clk);
SendPacketFromFile_ll8(64,0,0);
repeat (10)
@(posedge clk);
SendPacketFromFile_ll8(59,0,0);
repeat (1)
@(posedge clk);
SendPacketFromFile_ll8(58,0,0);
repeat (1)
@(posedge clk);
SendPacketFromFile_ll8(100,0,0);
repeat (1)
@(posedge clk);
SendPacketFromFile_ll8(200,150,30); // waiting 14 empties the fifo, 15 underruns
repeat (1)
@(posedge clk);
SendPacketFromFile_ll8(100,0,30);
#10000 $finish;
end
// Force a CRC error
initial
begin
#90000;
@(posedge clk);
FORCE_DAT_ERR <= 8'h10;
@(posedge clk);
FORCE_DAT_ERR <= 8'h00;
end
// Force an RX_ER error (i.e. link loss)
initial
begin
#116000;
@(posedge clk);
FORCE_ERR <= 1;
@(posedge clk);
FORCE_ERR <= 0;
end
// Cause receive fifo to fill, causing an RX overrun
initial
begin
#126000;
@(posedge clk);
rx_ll_dst_rdy2 <= 0;
repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows
@(posedge clk);
rx_ll_dst_rdy2 <= 1;
end
// Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
// Still need to test: CRC errors on Pause Frames
always @(posedge clk)
if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
begin
if(rx_ll_sof2 & ~rx_ll_eof2)
$display("RX-PKT-START %d",$time);
$display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
if(rx_ll_eof2 & ~rx_ll_sof2)
$display("RX-PKT-END %d",$time);
end
endmodule // simple_gemac_tb
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 6
*/
// Testbench for behavioral model for the advanced register file
// Import the modules that will be tested for in this testbench
//`include "regfileww.v"
`include "RegFileWW.syn.v"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f regfileww.f +gui
module tb_regfileww();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the advanced register file
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// rd1data or rd2data output signals
wire [127:0] rd1_d,rd2_d;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// clk, wren,rd1en,rd2en;
reg clock,wr_en,r1_en,r2_en;
// wrdata
reg [127:0] wr_d;
// wraddr, rd1addr, rd2addr
reg [4:0] w_addr,r1_addr,r2_addr;
// wrbyteen
reg [15:0] wrbytn;
// 32 Words of 128-bits
reg r[0:31];
reg [127:0] r_row;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 6'd32;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 5ns <==> 200 MHz clock
*/
#2.5 clock = 0;
#2.5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of regfile() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
RegFileWW rg (
// instance_name(signal name),
// Signal name can be the same as the instance name
rd1_d,rd2_d,wr_d,r1_addr,r2_addr,w_addr,r1_en,r2_en,
wr_en,wrbytn,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
$sdf_annotate("../sdf/RegFileWW.sdf",rg,"TYPICAL", "1.0:1.0:1.0", "FROM_MTM");
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
/**
* Read the input data for r from an input file named
* "testfile.bit"
*/
$readmemb("testfile.bit",r);
/*
for(count=0;count<=size_of_input;count=count+1)
begin
#10
//$display("Next");
r_row=r[count];
$display("Next",r_row);
end
*/
// Write to 8 data locations
#20
wr_d=128'h12fec60caef787897ea12fec60cae787897eac22354;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd0;
wrbytn=16'hff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h2092384578672348973465465465464645664654666;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd1;
wrbytn=16'h7f;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h1247815925648545618548486131875531264684565;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd2;
wrbytn=16'h3f;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h1425423544648646517897894613514684987984614;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd3;
wrbytn=16'h1f;
r1_en=0;
r2_en=0;
wr_en=1;
// ===================================
#20
wr_d=128'h12121352caf4caacecce09c4ae54864c6ae464ca3544;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd4;
wrbytn=16'hfff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h21231363caeceac45564c1ae151c53ae15c153ae1c4;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd5;
wrbytn=16'h7ff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
wr_d=128'h195442347acdc46da456c1ad561c65ad1c6ad61c455;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd6;
wrbytn=16'h3ff;
r1_en=0;
r2_en=0;
wr_en=1;
#20
//wr_d=128'h18342cad864c65da4654cad646c5d4a564cd56ca552;
wr_d=128'h18342cad864c65da4654cad646c5d4a564cd56ca552;
r1_addr=5'd10;
r2_addr=5'd11;
w_addr=5'd7;
wrbytn=16'h1ff;
r1_en=0;
r2_en=0;
wr_en=1;
// Read the data from the aforementioned locations
#20
wr_d=128'd12345;
r1_addr=5'd0;
r2_addr=5'd7;
w_addr=5'd20;
wrbytn=16'hffff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd1;
r2_addr=5'd6;
w_addr=5'd20;
wrbytn=16'h7fff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd2;
r2_addr=5'd5;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd3;
r2_addr=5'd4;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
// ====================================================
#20
wr_d=128'd12345;
r1_addr=5'd4;
r2_addr=5'd3;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd5;
r2_addr=5'd2;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd6;
r2_addr=5'd1;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
#20
wr_d=128'd12345;
r1_addr=5'd7;
r2_addr=5'd0;
w_addr=5'd20;
wrbytn=16'hff;
r1_en=1;
r2_en=1;
wr_en=0;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////
//
// To test:
// (a) The use & representation of time variables
// (b) The display of time variables
//
// Compile and run the program
// iverilog tt_clean.v
// vvp a.out
//
// VISUALLY INSPECT the displays. (There ain't no way to automate this)
//
///////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
`define PCI_CLK_PERIOD 15.0 // 66 Mhz
module top;
reg PCI_Clk;
reg fail;
initial PCI_Clk <= 0;
always #(`PCI_CLK_PERIOD/2) PCI_Clk <= ~PCI_Clk;
initial begin
fail = 0;
$display("\n\t\t==> CHECK THIS DISPLAY ==>\n");
$display("pci_clk_period:\t\t\t %0d",`PCI_CLK_PERIOD);
$display("pci_clk_period:\t\t\t %0t",`PCI_CLK_PERIOD);
if($time !== 0) fail = 1;
if (fail == 1)
$display("$time=%0d (0)", $time);
delay_pci(3);
if($simtime !== 4500) fail = 1;
if($time !== 45) fail = 1;
if (fail == 1)
$display("$time=%0d (45)", $time);
#15;
if($simtime !== 6000) fail = 1;
if($time !== 60) fail = 1;
#(`PCI_CLK_PERIOD);
if($simtime !== 7500) fail = 1;
if($time !== 75) fail = 1;
#(`PCI_CLK_PERIOD *2);
if($simtime !== 10500) fail = 1;
if($time !== 105) fail = 1;
$timeformat(-9,2,"ns",20);
$display("after setting timeformat:");
$display("pci_clk_period:\t\t\t %0d",`PCI_CLK_PERIOD);
$display("pci_clk_period:\t\t\t %0t",`PCI_CLK_PERIOD);
delay_pci(3);
if($simtime !== 15000) fail = 1;
if($time !== 150) fail = 1;
#15;
if($simtime !== 16500) fail = 1;
if($time !== 165) fail = 1;
#(`PCI_CLK_PERIOD);
if($simtime !== 18000) fail = 1;
if($time !== 180) fail = 1;
#(`PCI_CLK_PERIOD *2);
if($simtime !== 21000) fail = 1;
if($time !== 210) fail = 1;
$display("\t\t**********************************************");
if(fail) $display("\t\t****** time representation test BAD *******");
else $display("\t\t****** time representation test OK *******");
$display("\t\t**********************************************\n");
$finish(0);
end
task delay_pci;
input delta;
integer delta;
integer ii;
begin
#(`PCI_CLK_PERIOD * delta);
end
endtask
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221OI_BEHAVIORAL_V |
#include<bits/stdc++.h> #define fi first #define se second #define all(x) (x).begin(), (x).end() #define rall(x) (x).rbegin(), (x).rend() #define pb push_back #define len(x) (int)(x).size() typedef long long ll; typedef long double ld; using namespace std; const int N = 1001; const int mod = 998244353; int g[N][N]; int perm[N][N]; int cnt[N][N]; int n; void add(int id, int val){ for(int x = 0; x < n; ++x){ cnt[x][perm[id][x]] += val; } } void md(int &a){ if(a >= mod) a-=mod; } void solve(){ cin >> n; for(int i = 0; i < 2*n; ++i){ for(int j = 0 ; j < n; ++j){ cin >> perm[i][j]; } add(i , +1); } vector < bool > active(2*n, 1); int ans = 1; vector < int > answer; while(true){ bool have = 0; for(int x = 0; x < 2*n; ++x) if(active[x])have = 1; if(!have) break; int found = -1; for(int x = 0 ;x < 2 * n; ++x){ if(active[x]){ for(int i = 0 ;i < n; ++i){ if(cnt[i][perm[x][i]] == 1){ found = x; break; } } } } if(found == -1){ ans *= 2, md(ans); for(int x = 0; x < 2*n; ++x) if(active[x]) found = x; } answer.pb(found); /// dell all shit for(int j = 0; j < 2*n;++j){ if(active[j]){ bool del = 0; for(int z = 0; z < n; ++z){ if(perm[found][z] == perm[j][z]) del = 1; } if(del) active[j] = 0, add(j , -1); } } } cout << ans << n ; for(auto u : answer) cout << u + 1 << ; cout << n ; } signed main() { ios_base::sync_with_stdio(0),cin.tie(0),cout.tie(0); int t;cin >> t; while(t--){ solve(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_SYMBOL_V
`define SKY130_FD_SC_LP__MUX2I_SYMBOL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__mux2i (
//# {{data|Data Signals}}
input A0,
input A1,
output Y ,
//# {{control|Control Signals}}
input S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 4 * 1000 * 100 + 10; int n, c[N], st[N], en[N], who[N], TM; vector<int> adj[N]; void dfs(int root, int par = 0) { st[root] = TM++; who[st[root]] = root; for (auto u : adj[root]) if (u ^ par) dfs(u, root); en[root] = TM; } struct Node { int lazy = -1; long long lol = 0; void merge(Node L, Node R) { lol = L.lol | R.lol; } void add(int x) { if (x == -1) return; lazy = x; lol = 1LL << x; } } seg[N << 2]; void push(int root) { seg[root << 1].add(seg[root].lazy), seg[root << 1 | 1].add(seg[root].lazy); seg[root].lazy = -1; } void build(int l = 0, int r = n, int root = 1) { if (l + 1 == r) { seg[root].add(c[who[l]]); return; } int mid = l + r >> 1; build(l, mid, root << 1), build(mid, r, root << 1 | 1); seg[root].merge(seg[root << 1], seg[root << 1 | 1]); } void upd(int s, int e, int w, int l = 0, int r = n, int root = 1) { if (s <= l && e >= r) { seg[root].add(w); return; } if (s >= r || e <= l) return; push(root); int mid = l + r >> 1; upd(s, e, w, l, mid, root << 1), upd(s, e, w, mid, r, root << 1 | 1); seg[root].merge(seg[root << 1], seg[root << 1 | 1]); } Node get(int s, int e, int l = 0, int r = n, int root = 1) { if (s <= l && e >= r) return seg[root]; if (s >= r || e <= l) return seg[0]; push(root); int mid = l + r >> 1; Node res; res.merge(get(s, e, l, mid, root << 1), get(s, e, mid, r, root << 1 | 1)); return res; } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); int Q; cin >> n >> Q; for (int i = 1; i <= n; i++) cin >> c[i]; for (int i = 1, v, u; i < n; i++) { cin >> v >> u; adj[v].push_back(u); adj[u].push_back(v); } dfs(1); build(); while (Q--) { int t, v, c; cin >> t; if (t == 1) { cin >> v >> c; upd(st[v], en[v], c); } else { cin >> v; cout << __builtin_popcountll(get(st[v], en[v]).lol) << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[1010][1010]; int p[1010][1010]; int w[1010]; int n, m; int ok(int d) { int cur, i, j, k; for (i = 0; i < m; i++) for (j = 0; j < m; j++) p[i][j] = 0; for (i = 0; i < n; i++) { cur = 0; for (j = 0; j < m; j++) if (a[i][j] >= d) w[cur++] = j; for (j = 0; j < cur; j++) { for (k = 0; k < j; k++) { if (1 == p[w[k]][w[j]]) return 1; p[w[k]][w[j]] = 1; } } } return 0; } int main() { int i, j; scanf( %d%d , &n, &m); for (i = 0; i < n; i++) for (j = 0; j < m; j++) scanf( %d , &a[i][j]); int l, r, res, mid; res = 0; l = 0; r = 1000000000; ok(11); while (l < r) { mid = (l + r + 1) / 2; if (1 == ok(mid)) { res = mid; l = mid; } else r = mid - 1; } printf( %d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = (int)1e9 + 1; const int MAXN = (int)5001; int solve(vector<pair<int, int> > sg, int pos) { sg.erase(sg.begin() + pos); int mx = sg[0].first, mn = sg[0].second; for (int i = (1); i < (int)(sg.size()); i++) { if (sg[i].first > mn || sg[i].second < mx) return 0; mx = max(mx, sg[i].first); mn = min(mn, sg[i].second); } return abs(mx - mn); } bool comp1(const pair<int, int> &a, const pair<int, int> &b) { return (a.first == b.first) ? (a.second - a.first > b.second - b.first) : (a.first < b.first); } bool comp2(const pair<int, int> &a, const pair<int, int> &b) { return (a.second == b.second) ? (a.second - a.first < b.second - b.first) : (a.second < b.second); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, x, y; cin >> n; vector<pair<int, int> > sgm; for (int i = (0); i < (int)(n); i++) { cin >> x >> y; sgm.push_back(make_pair(x, y)); } sort((sgm).begin(), (sgm).end(), comp1); x = solve(sgm, n - 1); sort((sgm).begin(), (sgm).end(), comp2); cout << max(x, solve(sgm, 0)); } |
#include <bits/stdc++.h> using namespace std; void solve() { int n, m; cin >> n >> m; vector<vector<vector<int>>> dp(n + 1, vector<vector<int>>(m + 1, vector<int>(2, 0))); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { dp[i][j][1] = dp[i][j - 1][0] + 1; dp[i][j][0] = dp[i - 1][j][1] + 1; } int ans = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { ans += dp[i][j][0] + dp[i][j][1]; } ans -= n * m; int q; cin >> q; vector<vector<int>> a(n, vector<int>(m, 1)); auto calc_len = [&](int x, int y, int dx, int dy) { int res = 0; while (1) { x += dx; y += dy; if (x < 0 || y < 0 || x >= n || y >= m || a[x][y] == 0) { break; } res++; swap(dx, dy); } return res; }; while (q--) { int i, j; cin >> i >> j; i--, j--; { int x = calc_len(i, j, -1, 0); int y = calc_len(i, j, 0, 1); ans += (a[i][j] == 1 ? -1 : 1) * ((x + 1) * (y + 1)); } { int x = calc_len(i, j, 0, -1); int y = calc_len(i, j, 1, 0); ans += (a[i][j] == 1 ? -1 : 1) * ((x + 1) * (y + 1)); } ans += (a[i][j] == 1 ? 1 : -1); a[i][j] ^= 1; cout << ans << endl; } } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int T = 1; while (T--) { solve(); } } |
Require Bedrock.Word Crypto.Util.WordUtil.
Require Coq.ZArith.Znumtheory Coq.ZArith.BinInt.
Require Coq.Numbers.Natural.Peano.NPeano.
Require Crypto.CompleteEdwardsCurve.CompleteEdwardsCurveTheorems.
Require Import Omega. (* TODO: remove this import when we drop 8.4 *)
Require Import Crypto.Spec.ModularArithmetic.
(** In Coq 8.4, we have [NPeano.pow] and [NPeano.modulo]. In Coq 8.5,
they are [Nat.pow] and [Nat.modulo]. To allow this file to work
with both versions, we create a module where we (locally) import
both [NPeano] and [Nat], and define the notations with unqualified
names. By importing the module, we get access to the notations
without importing [NPeano] and [Nat] in the top-level of this
file. *)
Module Import Notations.
Import NPeano Nat.
Infix "^" := pow.
Infix "mod" := modulo (at level 40, no associativity).
Infix "++" := Word.combine.
Notation setbit := setbit.
End Notations.
Generalizable All Variables.
Section EdDSA.
Class EdDSA (* <https://eprint.iacr.org/2015/677.pdf> *)
{E Eeq Eadd Ezero Eopp} {EscalarMult} (* the underllying elliptic curve operations *)
{b : nat} (* public keys are k bits, signatures are 2*k bits *)
{H : forall {n}, Word.word n -> Word.word (b + b)} (* main hash function *)
{c : nat} (* cofactor E = 2^c *)
{n : nat} (* secret keys are (n+1) bits *)
{l : BinPos.positive} (* order of the subgroup of E generated by B *)
{B : E} (* base point *)
{Eenc : E -> Word.word b} (* normative encoding of elliptic cuve points *)
{Senc : F l -> Word.word b} (* normative encoding of scalars *)
:=
{
EdDSA_group:@Algebra.group E Eeq Eadd Ezero Eopp;
EdDSA_scalarmult:@Algebra.ScalarMult.is_scalarmult E Eeq Eadd Ezero EscalarMult;
EdDSA_c_valid : c = 2 \/ c = 3;
EdDSA_n_ge_c : n >= c;
EdDSA_n_le_b : n <= b;
EdDSA_B_not_identity : not (Eeq B Ezero);
EdDSA_l_prime : Znumtheory.prime l;
EdDSA_l_odd : BinInt.Z.lt 2 l;
EdDSA_l_order_B : Eeq (EscalarMult (BinInt.Z.to_nat l) B) Ezero
}.
Global Existing Instance EdDSA_group.
Global Existing Instance EdDSA_scalarmult.
Context `{prm:EdDSA}.
Local Coercion Word.wordToNat : Word.word >-> nat.
Local Coercion BinInt.Z.to_nat : BinInt.Z >-> nat.
Local Notation secretkey := (Word.word b) (only parsing).
Local Notation publickey := (Word.word b) (only parsing).
Local Notation signature := (Word.word (b + b)) (only parsing).
Local Arguments H {n} _.
Local Notation wfirstn n w := (@WordUtil.wfirstn n _ w _) (only parsing).
Local Obligation Tactic := destruct prm; simpl; intros; omega.
Program Definition curveKey (sk:secretkey) : nat :=
let x := wfirstn n (H sk) in (* hash the key, use first "half" for secret scalar *)
let x := x - (x mod (2^c)) in (* it is implicitly 0 mod (2^c) *)
setbit x n. (* and the high bit is always set *)
Local Infix "+" := Eadd.
Local Infix "*" := EscalarMult.
Definition prngKey (sk:secretkey) : Word.word b := Word.split2 b b (H sk).
Definition public (sk:secretkey) : publickey := Eenc (curveKey sk*B).
Program Definition sign (A_:publickey) sk {n} (M : Word.word n) :=
let r : nat := H (prngKey sk ++ M) in (* secret nonce *)
let R : E := r * B in (* commitment to nonce *)
let s : nat := curveKey sk in (* secret scalar *)
let S : F l := F.nat_mod l (r + H (Eenc R ++ A_ ++ M) * s) in
Eenc R ++ Senc S.
Definition valid {n} (message : Word.word n) pubkey signature :=
exists A S R, Eenc A = pubkey /\ Eenc R ++ Senc S = signature /\
Eeq (F.to_nat S * B) (R + (H (Eenc R ++ Eenc A ++ message) mod l) * A).
End EdDSA.
|
#include <bits/stdc++.h> using namespace std; bool comp(int x, int y) { return x > y; } int dx[] = {0, 0, 1, -1}; int dy[] = {1, -1, 0, 0}; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } int main() { int n; cin >> n; vector<pair<int, int> > a(n); for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; a[i] = make_pair(x, y); } int res = 0; for (int i = 0; i < n; i++) { int x1 = a[i].first; int y1 = a[i].second; int upper = 0, lower = 0, right = 0, left = 0; for (int j = 0; j < n; j++) { if (i != j) { int x2 = a[j].first; int y2 = a[j].second; if (x2 > x1 && y1 == y2) right++; if (x2 < x1 && y1 == y2) left++; if (x1 == x2 && y2 > y1) upper++; if (x1 == x2 && y2 < y1) lower++; } } if (upper >= 1 && lower >= 1 && right >= 1 && left >= 1) res++; } cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 100000000; const double eps = 1e-10; const int MAXN = 110; set<int> sx, sy; int in[10][2]; set<int>::iterator it1, it2; int main() { int x, y; for (int i = 0; i < (8); ++i) { scanf( %d%d , &x, &y); in[i][0] = x; in[i][1] = y; if (!sx.count(x)) sx.insert(x); if (!sy.count(y)) sy.insert(y); } if ((int)sx.size() != 3 || (int)sy.size() != 3) printf( %s n , ugly ); else { int mat[5][5]; memset(mat, 0, sizeof(mat)); int cnt = 0, f = 1; map<int, int> xx, yy; for (__typeof((sx).begin()) it1 = (sx).begin(); it1 != (sx).end(); it1++) xx[(*it1)] = cnt++; cnt = 0; for (__typeof((sy).begin()) it2 = (sy).begin(); it2 != (sy).end(); it2++) yy[(*it2)] = cnt++; for (int i = 0; i < (8); ++i) mat[xx[in[i][0]]][yy[in[i][1]]] = 1; for (int i = 0; i < (3); ++i) { for (int j = 0; j < (3); ++j) { if (i == 1 && j == 1 && mat[i][j]) f = 0; if ((i != 1 || j != 1) && !mat[i][j]) f = 0; } } if (f) printf( %s n , respectable ); else printf( %s n , ugly ); } } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface, note that overrange is independent of data path,
// software will not be able to relate overrange to a specific sample!
// Alternative is to concatenate sample value and or status for data.
`timescale 1ns/100ps
module axi_ad9434_if (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// interface outputs
adc_clk,
adc_rst,
adc_data,
adc_or,
adc_status,
// delay control signals
delay_clk,
delay_rst,
delay_sel,
delay_rwn,
delay_addr,
delay_wdata,
delay_rdata,
delay_ack_t,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
localparam PCORE_DEVICE_7SERIES = 0;
localparam PCORE_DEVICE_VIRTEX6 = 1;
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [11:0] adc_data_in_p;
input [11:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
input adc_rst;
output [47:0] adc_data;
output adc_or;
output adc_status;
// delay control signals
input delay_clk;
input delay_rst;
input delay_sel;
input delay_rwn;
input [ 7:0] delay_addr;
input [ 4:0] delay_wdata;
output [ 4:0] delay_rdata;
output delay_ack_t;
output delay_locked;
// internal registers
reg [47:0] adc_data = 'd0;
reg adc_or = 'd0;
reg adc_status = 'd0;
// internal clocks and resets
wire adc_clk_in;
// internal signals
wire [11:0] adc_data_ibuf_s;
wire [ 3:0] adc_data_serdes_s[11:0];
wire adc_or_ibuf_s;
wire [ 3:0] adc_or_serdes_s;
wire adc_clk_ibuf_s;
// delay elements are not used
assign delay_ack_t = 1'b0;
assign delay_rdata = 5'd0;
assign delay_locked = 1'b0;
// de-multiplex the adc data
always @(posedge adc_clk) begin
adc_data <= {adc_data_serdes_s[11][3], adc_data_serdes_s[10][3],
adc_data_serdes_s[ 9][3], adc_data_serdes_s[ 8][3],
adc_data_serdes_s[ 7][3], adc_data_serdes_s[ 6][3],
adc_data_serdes_s[ 5][3], adc_data_serdes_s[ 4][3],
adc_data_serdes_s[ 3][3], adc_data_serdes_s[ 2][3],
adc_data_serdes_s[ 1][3], adc_data_serdes_s[ 0][3],
adc_data_serdes_s[11][2], adc_data_serdes_s[10][2],
adc_data_serdes_s[ 9][2], adc_data_serdes_s[ 8][2],
adc_data_serdes_s[ 7][2], adc_data_serdes_s[ 6][2],
adc_data_serdes_s[ 5][2], adc_data_serdes_s[ 4][2],
adc_data_serdes_s[ 3][2], adc_data_serdes_s[ 2][2],
adc_data_serdes_s[ 1][2], adc_data_serdes_s[ 0][2],
adc_data_serdes_s[11][1], adc_data_serdes_s[10][1],
adc_data_serdes_s[ 9][1], adc_data_serdes_s[ 8][1],
adc_data_serdes_s[ 7][1], adc_data_serdes_s[ 6][1],
adc_data_serdes_s[ 5][1], adc_data_serdes_s[ 4][1],
adc_data_serdes_s[ 3][1], adc_data_serdes_s[ 2][1],
adc_data_serdes_s[ 1][1], adc_data_serdes_s[ 0][1],
adc_data_serdes_s[11][0], adc_data_serdes_s[10][0],
adc_data_serdes_s[ 9][0], adc_data_serdes_s[ 8][0],
adc_data_serdes_s[ 7][0], adc_data_serdes_s[ 6][0],
adc_data_serdes_s[ 5][0], adc_data_serdes_s[ 4][0],
adc_data_serdes_s[ 3][0], adc_data_serdes_s[ 2][0],
adc_data_serdes_s[ 1][0], adc_data_serdes_s[ 0][0]};
if (adc_or_serdes_s == 4'd0) begin
adc_or <= 1'b0;
end else begin
adc_or <= 1'b1;
end
adc_status <= 1'b1;
end
// data path - input-buffer - input-serdes (4:1)
genvar l_inst;
generate
for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin : g_adc_if
IBUFDS i_data_ibuf (
.I (adc_data_in_p[l_inst]),
.IB (adc_data_in_n[l_inst]),
.O (adc_data_ibuf_s[l_inst]));
ISERDESE1 #(
.DATA_RATE ("SDR"),
.DATA_WIDTH (4),
.INTERFACE_TYPE ("NETWORKING"),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.NUM_CE (2),
.OFB_USED ("FALSE"),
.IOBDELAY ("NONE"),
.SERDES_MODE ("MASTER"))
i_data_serdes (
.Q1 (adc_data_serdes_s[l_inst][3]),
.Q2 (adc_data_serdes_s[l_inst][2]),
.Q3 (adc_data_serdes_s[l_inst][1]),
.Q4 (adc_data_serdes_s[l_inst][0]),
.Q5 (),
.Q6 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (adc_clk_in),
.CLKB (~adc_clk_in),
.CLKDIV (adc_clk),
.D (adc_data_ibuf_s[l_inst]),
.DDLY (1'b0),
.RST (adc_rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.OFB (1'b0),
.OCLK (1'b0),
.O ());
end
endgenerate
// over-range - input-buffer - input-serdes (4:1)
IBUFDS i_or_ibuf (
.I (adc_or_in_p),
.IB (adc_or_in_n),
.O (adc_or_ibuf_s));
ISERDESE1 #(
.DATA_RATE ("SDR"),
.DATA_WIDTH (4),
.INTERFACE_TYPE ("NETWORKING"),
.DYN_CLKDIV_INV_EN ("FALSE"),
.DYN_CLK_INV_EN ("FALSE"),
.NUM_CE (2),
.OFB_USED ("FALSE"),
.IOBDELAY ("NONE"),
.SERDES_MODE ("MASTER"))
i_or_serdes (
.Q1 (adc_or_serdes_s[3]),
.Q2 (adc_or_serdes_s[2]),
.Q3 (adc_or_serdes_s[1]),
.Q4 (adc_or_serdes_s[0]),
.Q5 (),
.Q6 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (adc_clk_in),
.CLKB (~adc_clk_in),
.CLKDIV (adc_clk),
.D (adc_or_ibuf_s),
.DDLY (1'b0),
.RST (adc_rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
.OFB (1'b0),
.OCLK (1'b0),
.O ());
// clock - input-buffer ---> bufio & bufr combination (4:1)
IBUFGDS i_clk_ibuf (
.I (adc_clk_in_p),
.IB (adc_clk_in_n),
.O (adc_clk_ibuf_s));
BUFIO i_clk_hs_buf (
.I (adc_clk_ibuf_s),
.O (adc_clk_in));
BUFR #(.BUFR_DIVIDE("4")) i_clk_buf (
.CLR(1'b0),
.CE(1'b1),
.I (adc_clk_ibuf_s),
.O (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int main() { string s, hours, mins; cin >> s; int a = 1, b = 1, colon, i, radix = 0; for (i = 0; i < s.length(); i++) { if (s[i] == : ) { colon = i; break; } } for (i = 0; i < colon; i++) { if (s[i] != 0 ) { break; } } hours = s.substr(i, colon - i); for (i = colon + 1; i < s.length(); i++) { if (s[i] != 0 ) { break; } } mins = s.substr(i); if (hours.length() <= 1 and mins.length() <= 1) { hours.length() == 1 and hours[0] - A + 10 >= 24 ? cout << 0 : cout << -1; return 0; } for (i = 0; i < s.length(); i++) { if (i != colon) { int cur = s[i] >= 0 and s[i] <= 9 ? s[i] - 0 : s[i] - A + 10; radix = max(radix, cur); } } radix++; if (radix == 1) { radix = 2; } for (i = radix;; i++) { int HOURS = 0, MINS = 0; for (int j = 0; j < hours.length(); j++) { HOURS *= i; HOURS += hours[j] >= 0 and hours[j] <= 9 ? hours[j] - 0 : hours[j] - A + 10; } for (int j = 0; j < mins.length(); j++) { MINS *= i; MINS += mins[j] >= 0 and mins[j] <= 9 ? mins[j] - 0 : mins[j] - A + 10; } if (HOURS <= 23 and MINS <= 59) { cout << i << ; } else { if (i == radix) { cout << 0; } return 0; } } } |
// Copyright (C) 1991-2011 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// PROGRAM "Quartus II 64-Bit"
// VERSION "Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Full Version"
// CREATED "Wed Nov 28 11:17:40 2012"
module buslvds(
doutp,
oe,
din,
p,
n
);
input wire doutp;
input wire oe;
output wire din;
inout wire p;
inout wire n;
wire oebout;
wire oeout;
wire [0:0] SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;
pdo b2v_inst(
.i(doutp),
.oein(oe),
.o(SYNTHESIZED_WIRE_2),
.obar(SYNTHESIZED_WIRE_3),
.oebout(oebout),
.oeout(oeout));
assign din = SYNTHESIZED_WIRE_0 & SYNTHESIZED_WIRE_1;
assign SYNTHESIZED_WIRE_1 = ~oe;
twentynm_io_obuf b2v_inst3(
.i(SYNTHESIZED_WIRE_2),
.oe(oeout),
.o(p),
.obar());
twentynm_io_obuf b2v_inst4(
.i(SYNTHESIZED_WIRE_3),
.oe(oebout),
.o(n),
.obar());
diffin b2v_inst5(
.datain(p),
.datain_b(n),
.dataout(SYNTHESIZED_WIRE_0));
endmodule
|
#include <bits/stdc++.h> const long long maxn = 8e9 + 5; long long v[10000000]; long long k[10000000]; long long n, sum; int judge(long long m) { long long i, sum1 = sum; for (i = 0; i < n; i++) { if (m * v[i] > k[i]) { if (k[i] + sum1 < m * v[i]) break; else if (k[i] + sum1 >= m * v[i]) sum1 = sum1 + k[i] - m * v[i]; } } if (i < n) return 0; else return 1; } int main() { long long l, r, mid; scanf( %I64d%I64d , &n, &sum); for (long long i = 0; i < n; i++) { scanf( %I64d , &v[i]); } for (long long i = 0; i < n; i++) { scanf( %I64d , &k[i]); } l = 0; r = maxn; while (l + 1 < r) { mid = l + (r - l) / 2; if (judge(mid)) { l = mid; } else r = mid; } if (judge(l + 1)) printf( %I64d , l + 1); else printf( %I64d , l); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_FUNCTIONAL_V
`define SKY130_FD_SC_LS__FILL_DIODE_FUNCTIONAL_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fill_diode ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_FUNCTIONAL_V |
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_generic_ddio(
datain,
halfratebypass,
dataout,
clk_hr,
clk_fr
);
parameter WIDTH = 1;
localparam DATA_IN_WIDTH = 4 * WIDTH;
localparam DATA_OUT_WIDTH = WIDTH;
input [DATA_IN_WIDTH-1:0] datain;
input halfratebypass;
input [WIDTH-1:0] clk_hr;
input [WIDTH-1:0] clk_fr;
output [DATA_OUT_WIDTH-1:0] dataout;
generate
genvar pin;
for (pin = 0; pin < WIDTH; pin = pin + 1)
begin:acblock
wire fr_data_hi;
wire fr_data_lo;
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_hi (
.datainhi(datain[pin * 4]),
.datainlo(datain[pin * 4 + 2]),
.dataout(fr_data_hi),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_lo (
.datainhi(datain[pin * 4 + 1]),
.datainlo(datain[pin * 4 + 3]),
.dataout(fr_data_lo),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.async_mode("none"),
.half_rate_mode("false"),
.sync_mode("none"),
.use_new_clocking_model("true")
) ddio_out (
.datainhi(fr_data_hi),
.datainlo(fr_data_lo),
.dataout(dataout[pin]),
.clkhi (clk_fr[pin]),
.clklo (clk_fr[pin]),
.muxsel (clk_fr[pin])
);
end
endgenerate
endmodule
|
/* Copyright (C) 2000 Stephen G. Tell
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
/* fdisplay2 - test $fopen and $fdisplay system tasks */
module fdisplay2;
integer fp, dfp;
reg [7:0] a;
initial begin
fp = $fopen("work/fdisplay2.out");
if(fp != 2 && fp != 4 && fp != 8 && fp != 16 && fp != 32 && fp != 64)
begin
$display("FAILED fopen fp=%d", fp);
$finish;
end
$fwrite(fp, "hello, world\n");
a = 8'hac;
//$fdisplay(1|fp, "a = %h; x: %b\n", a, a^8'h0f);
dfp = 1|fp;
$fdisplay(dfp, "a = 'h%h = 'b%b", a, a);
$finish;
end // initial begin
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long maxS = 2e5 + 5; long long N, M; long long A[201], B[201]; long long DP[201][515]; long long go(long long pos, long long prev) { if (pos == N + 1) return 0; if (DP[pos][prev] != -1) return DP[pos][prev]; long long ans = INT_MAX; for (long long i = 1; i <= M; i++) ans = min(ans, (prev | (A[pos] & B[i]) | go(pos + 1, (prev | (A[pos] & B[i]))))); return DP[pos][prev] = ans; } void code_idhr_h() { cin >> N >> M; for (long long i = 1; i <= N; i++) cin >> A[i]; for (long long i = 1; i <= M; i++) cin >> B[i]; memset(DP, -1, sizeof DP); cout << go(1, 0) << n ; } int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long T = 1; for (long long t = 1; t <= T; t++) { code_idhr_h(); } return 0; } |
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn bus master interface for tawas core.
* Uses 8 master ids x 4 sequence ids to map to 32-threads.
*
*/
module tawas_rcn_master
(
input rst,
input clk,
input [68:0] rcn_in,
output [68:0] rcn_out,
input cs,
input [4:0] seq,
output busy,
input wr,
input [3:0] mask,
input [23:0] addr,
input [31:0] wdata,
output rdone,
output wdone,
output [4:0] rsp_seq,
output [3:0] rsp_mask,
output [23:0] rsp_addr,
output [31:0] rsp_data
);
parameter MASTER_GROUP_8 = 0;
reg [68:0] rin;
reg [68:0] rout;
assign rcn_out = rout;
wire [2:0] my_id = MASTER_GROUP_8;
wire my_resp = rin[68] && !rin[67] && (rin[65:63] == MASTER_GROUP_8);
wire req_valid;
wire [68:0] req;
always @ (posedge clk or posedge rst)
if (rst)
begin
rin <= 69'd0;
rout <= 69'd0;
end
else
begin
rin <= rcn_in;
rout <= (req_valid) ? req : (my_resp) ? 69'd0 : rin;
end
assign busy = rin[68] && !my_resp;
assign req_valid = cs && !(rin[68] && !my_resp);
assign req = {1'b1, 1'b1, wr, my_id, seq[4:2], mask, addr[23:2], seq[1:0], wdata};
assign rdone = my_resp && !rin[66];
assign wdone = my_resp && rin[66];
assign rsp_seq = {rin[62:60], rin[33:32]};
assign rsp_mask = rin[59:56];
assign rsp_addr = {rin[55:34], 2'd0};
assign rsp_data = rin[31:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x7f7f7f7f; char s[1005]; int dp[1005][2]; int main() { int n; scanf( %d , &n); scanf( %s , s); if (1 == n) { puts( 0 ); return 0; } memset(dp, 0x7f, sizeof(dp)); dp[0][s[0] - 0 ] = 0; dp[0][(s[0] - 0 ) ^ 1] = 1; for (int i = 1; i < n; ++i) { if (s[i] == 1 ) { dp[i][1] = dp[i - 1][0]; dp[i][0] = dp[i - 1][1] + 1; } else { dp[i][0] = dp[i - 1][1]; dp[i][1] = dp[i - 1][0] + 1; } } int ans = min(dp[n - 1][0], dp[n - 1][1]); if (ans >= INF) ans = -1; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b, numa, numb, ans; bool f = 0; cin >> n >> a >> b; for (int i = 2, cnt = 1; i <= n; i *= 2) { numa = a / i; if (a % i != 0) numa++; numb = b / i; if (b % i != 0) numb++; if (numa == numb) { if (i == n) f = 1; ans = cnt; break; } cnt++; } if (f == 1) cout << Final! << endl; else cout << ans << endl; return 0; } |
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_idelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module instantiates the IDELAYCTRL primitive of the Virtex-5 device
// which continuously calibrates the IDELAY elements in the region in case of
// varying operating conditions. It takes a 200MHz clock as an input
//Reference:
//Revision History:
// Rev 1.1 - Parameter IODELAY_GRP added and constraint IODELAY_GROUP added
// on IOELAYCTRL primitive. Generate logic on IDELAYCTRL removed
// since tools will replicate idelactrl primitives.PK. 11/27/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_idelay_ctrl #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter IODELAY_GRP = "IODELAY_MIG"
)
(
input clk200,
input rst200,
output idelay_ctrl_rdy
);
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY(idelay_ctrl_rdy),
.REFCLK(clk200),
.RST(rst200)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2B_1_V
`define SKY130_FD_SC_HS__NAND2B_1_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog wrapper for nand2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand2b_1 (
Y ,
A_N ,
B ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand2b_1 (
Y ,
A_N,
B
);
output Y ;
input A_N;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand2b base (
.Y(Y),
.A_N(A_N),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2B_1_V
|
module Lolhi(
input A,
input B,
input C,
input AnalogLDir,
input AnalogRDir,
output Len,
output Ldir,
output Ren,
output Rdir
);
wire Z_A;
wire Z_B;
wire Z_C;
wire Ldir_int;
wire Len_int;
wire Rdir_int;
wire Ren_int;
wire Analog_select;
supply0 GND;
assign Analog_select = AnalogLDir & AnalogRDir;
inverter_nick_yay invA(.A(A), .Z(Z_A));
inverter_nick_yay invB(.A(B), .Z(Z_B));
inverter_nick_yay invC(.A(C), .Z(Z_C));
section2_schematic lab2Logic(.A(Z_A),
.B(Z_B),
.C(Z_C),
.Ld(Ldir_int),
.Le(Len_int),
.Rd(Rdir_int),
.Re(Ren_int)
);
mux2 mux_1(.d0(AnalogLDir), .d1(Ldir_int), .s(Analog_select), .y(Ldir));
mux2 mux_2(.d0(GND), .d1(Len_int), .s(Analog_select), .y(Len));
mux2 mux_3(.d0(AnalogRDir), .d1(Rdir_int), .s(Analog_select), .y(Rdir));
mux2 mux_4(.d0(GND), .d1(Ren_int), .s(Analog_select), .y(Ren));
endmodule
module mux2(
input d0,
input d1,
input s,
output y);
assign y = (s) ? d1 : d0;
endmodule
module inverter_nick_yay (input A,
output Z);
assign Z = ~A;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void splitstr(const string &s, vector<T> &out) { istringstream in(s); out.clear(); copy(istream_iterator<T>(in), istream_iterator<T>(), back_inserter(out)); } template <class T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } static void redirect(int argc, const char **argv) { ios::sync_with_stdio(false); cin.tie(NULL); if (argc > 1) { static filebuf f; f.open(argv[1], ios::in); cin.rdbuf(&f); if (!cin) { cerr << Failed to open << argv[1] << << endl; exit(1); } } if (argc > 2) { static filebuf f; f.open(argv[2], ios::out | ios::trunc); cout.rdbuf(&f); if (!cout) { cerr << Failed to open << argv[2] << << endl; } } } static void no() { cout << -1 n ; exit(0); } static void check_dist(const vector<int> &dist, const vector<vector<int>> &edges, int cur, int parent, int depth) { if (dist[cur] != depth) no(); for (int v : edges[cur]) if (v != parent) check_dist(dist, edges, v, cur, depth + 1); } int main(int argc, const char **argv) { redirect(argc, argv); int N, K; cin >> N >> K; vector<vector<int>> dist(K, vector<int>(N)); vector<int> opos(K, -1); for (int i = 0; i < K; i++) for (int j = 0; j < N; j++) { cin >> dist[i][j]; if (dist[i][j] == 0) opos[i] = j; } if (count(begin(opos), end(opos), -1)) no(); int root = opos[0]; vector<int> parent(N, -1); parent[root] = -2; vector<vector<int>> order(K); for (int i = 1; i < K; i++) { if (dist[i][root] == 0) no(); order[i].resize(dist[i][root] + 1, -1); for (int j = 0; j < N; j++) if (dist[i][j] + dist[0][j] == dist[i][root]) order[i][dist[0][j]] = j; if (order[i][0] != root) no(); for (int j = 1; j < ((long long)(order[i]).size()); j++) { int v = order[i][j]; if (v == -1) no(); if (parent[v] != -1 && parent[v] != order[i][j - 1]) no(); parent[v] = order[i][j - 1]; } } vector<vector<pair<int, int>>> down(N); for (int i = 0; i < N; i++) if (parent[i] == -1) { int hi = -1; int v = root; int d = dist[0][i]; pair<int, int> best(0, 0); for (int j = 1; j < K; j++) { int a = dist[0][i] + dist[j][root] - dist[j][i]; if (a < 0 || a > 2 * dist[j][root] || (a & 1)) no(); a /= 2; if (a > hi) { hi = a; v = order[j][a]; d = dist[0][i] - a; } } down[v].emplace_back(d, i); } vector<int> lvl; for (int i = 0; i < N; i++) { if (down[i].empty()) continue; sort(begin(down[i]), end(down[i])); lvl.clear(); lvl.push_back(i); for (const auto &entry : down[i]) { int d = entry.first; int v = entry.second; if (d > ((long long)(lvl).size())) no(); else { parent[v] = lvl[d - 1]; if (d == ((long long)(lvl).size())) lvl.push_back(v); } } } vector<vector<int>> edges(N); for (int i = 0; i < N; i++) { if (parent[i] == -1) no(); else if (parent[i] >= 0) { edges[parent[i]].push_back(i); edges[i].push_back(parent[i]); } } for (int i = 0; i < K; i++) check_dist(dist[i], edges, opos[i], -1, 0); for (int i = 0; i < N; i++) if (parent[i] >= 0) cout << i + 1 << << parent[i] + 1 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 7; const int MOD = 1e9 + 7; const int LEN = 8, MAGIC = 1e8; int a[N], b[N]; int n; char bignum[N]; long long m[N]; int tot; int f[N], g[N]; int add(int a, int b) { a += b; if (a < 0) a += MOD; if (a >= MOD) a -= MOD; return a; } int divide(int d) { long long remain = 0; for (int i = tot - 1; i >= 0; i--) { remain = remain * MAGIC + m[i]; m[i] = remain / d; remain = remain % d; } while (tot > 1 && m[tot - 1] == 0) tot--; return remain; } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { scanf( %d , &a[i]); } a[n] = 1e9 + 7; for (int i = 1; i <= n; i++) { scanf( %d , &b[i]); } { scanf( %s , bignum); tot = 0; int cur = 0, l = strlen(bignum); for (int i = l - 1; i >= 0; i -= LEN) { cur = 0; for (int j = max(0, i - LEN + 1); j <= i; j++) { cur = cur * 10 + bignum[j] - 0 ; } m[tot++] = cur; } } int carry = 0; f[0] = 1; for (int i = 1; i <= n; i++) { int new_carry = carry + b[i], s = 0; fill(g, g + new_carry + 1, 0); for (int j = 0; j <= new_carry; j++) { s = add(s, f[j]); if (j > b[i]) { s = add(s, -f[j - b[i] - 1]); } g[j] = s; } fill(f, f + carry + 1, 0); if (a[i] > 1) { int remainder = divide(a[i]); for (int ii = remainder, jj = 0; ii <= new_carry; ii += a[i], jj++) { f[jj] = g[ii]; } carry = (new_carry - remainder) / a[i]; } else if (a[i] == 1) { for (int i = 0; i <= new_carry; i++) f[i] = g[i]; carry = new_carry; } else { assert(false); } } if (tot == 1 && m[0] == 0) { printf( %d n , f[0]); } else { puts( 0 ); } return 0; } |
#include <bits/stdc++.h> using namespace std; #define sim template < class c #define ris return * this #define dor > debug & operator << #define eni(x) sim > typename enable_if<sizeof dud<c>(0) x 1, debug&>::type operator<<(c i) { sim > struct rge { c b, e; }; sim > rge<c> range(c i, c j) { return rge<c>{i, j}; } sim > auto dud(c* x) -> decltype(cerr << *x, 0); sim > char dud(...); struct debug { #ifndef ONLINE_JUDGE ~debug() { cerr << endl; } eni(!=) cerr << boolalpha << i; ris; } eni(==) ris << range(begin(i), end(i)); } sim, class b dor(pair < b, c > d) { ris << ( << d.first << , << d.second << ) ; } sim dor(rge<c> d) { *this << [ ; for (auto it = d.b; it != d.e; ++it) *this << , + 2 * (it == d.b) << *it; ris << ] ; } #else sim dor(const c&) { ris; } #endif }; #define imie(...) [ << #__VA_ARGS__ : << (__VA_ARGS__) << ] #define ll long long const ll mod = 998244353; long long power(long long x, ll y, ll p) { long long res = 1; // Initialize result x = x % p; // Update x if it is more than or // equal to p while (y > 0) { // If y is odd, multiply x with result if (y & 1) res = (res * x) % p; // y must be even now y = y >> 1; // y = y/2 x = (x * x) % p; } return res; } // Returns n^(-1) mod p long long modInverse(long long n, int p) { return power(n, p - 2, p); } // Returns nCr % p using Fermat s little // theorem. long long nCrModPFermat(long long n,int r, int p) { // If n<r, then nCr should return 0 if (n < r) return 0; // Base case if (r == 0) return 1; // Fill factorial array so that we // can find all factorial of r, n // and n-r long long fac[n + 1]; fac[0] = 1; for (int i = 1; i <= n; i++) fac[i] = (fac[i - 1] * i) % p; return (fac[n] * modInverse(fac[r], p) % p * modInverse(fac[n - r], p) % p) % p; } void test_case() { ll n; cin >> n; string s; cin >> s; ll cnt = 0, cnt2 = 0, tmp = 0; for(ll i = 0; i < n; ++i) { if(s[i] == 0 ) { cnt2 = cnt2 + (tmp) / 2; tmp = 0; cnt++; } else { tmp++; } } cnt2 = cnt2 + (tmp) / 2; cout << nCrModPFermat(cnt + cnt2, cnt, mod) << endl; } int main() { ll T; cin >> T; for(ll i = 1; i <= T; ++i) { test_case(); } return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int x, y; } fei1[60], fei2[60]; int _hash[5100]; int main() { int p, q, l, r, i, t, j, x, k; scanf( %d%d%d%d , &p, &q, &l, &r); for (i = 0; i < p; i++) { scanf( %d%d , &fei1[i].x, &fei1[i].y); } for (i = 0; i < q; i++) { scanf( %d%d , &fei2[i].x, &fei2[i].y); } x = 0; for (i = l; i <= r; i++) { memset(_hash, 0, sizeof(_hash)); for (j = 0; j < p; j++) { for (k = fei1[j].x; k <= fei1[j].y; k++) { _hash[k] = 1; } } int flag = 0; for (j = 0; j < q; j++) { for (k = fei2[j].x + i; k <= fei2[j].y + i; k++) { if (_hash[k]) { flag = 1; break; } } if (flag) break; } if (flag) { x++; } } printf( %d n , x); return 0; } |
// megafunction wizard: %ARM-Based Excalibur%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ARM-Based Excalibur
// PROJECT: excalibur
// ============================================================
// File Name: h:\data\excalibur\excalibur.v
// Megafunction Name(s): ARM-Based Excalibur
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
//
// Copyright (C) 1991-2002 Altera Corporation
// Any megafunction design, and related netlist (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only
// to program PLD devices (but not masked PLD devices) from Altera. Any
// other use of such megafunction design, netlist, support information,
// device programming or simulation file, or any other related documentation
// or information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to the
// intellectual property, including patents, copyrights, trademarks, trade
// secrets, or maskworks, embodied in any such megafunction design, netlist,
// support information, device programming or simulation file, or any other
// related documentation or information provided by Altera or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.
//
module excalibur
(
clk_ref,
npor,
nreset,
uartrxd,
uartdsrn,
uartctsn,
uartrin,
uartdcdn,
uarttxd,
uartrtsn,
uartdtrn,
intextpin,
ebiack,
ebidq,
ebiclk,
ebiwen,
ebioen,
ebiaddr,
ebibe,
ebicsn,
sdramdq,
sdramdqs,
sdramclk,
sdramclkn,
sdramclke,
sdramwen,
sdramcasn,
sdramrasn,
sdramaddr,
sdramcsn,
sdramdqm,
slavehclk,
slavehwrite,
slavehreadyi,
slavehselreg,
slavehsel,
slavehmastlock,
slavehaddr,
slavehtrans,
slavehsize,
slavehburst,
slavehwdata,
slavehreadyo,
slavebuserrint,
slavehresp,
slavehrdata,
masterhclk,
masterhready,
masterhgrant,
masterhrdata,
masterhresp,
masterhwrite,
masterhlock,
masterhbusreq,
masterhaddr,
masterhburst,
masterhsize,
masterhtrans,
masterhwdata,
intuart,
inttimer0,
inttimer1,
intcommtx,
intcommrx,
debugrq,
debugext0,
debugext1,
debugextin,
debugack,
debugrng0,
debugrng1,
debugextout
);
input clk_ref;
input npor;
inout nreset;
input uartrxd;
input uartdsrn;
input uartctsn;
inout uartrin;
inout uartdcdn;
output uarttxd;
output uartrtsn;
output uartdtrn;
input intextpin;
input ebiack;
inout [15:0] ebidq;
output ebiclk;
output ebiwen;
output ebioen;
output [24:0] ebiaddr;
output [1:0] ebibe;
output [3:0] ebicsn;
inout [15:0] sdramdq;
inout [1:0] sdramdqs;
output sdramclk;
output sdramclkn;
output sdramclke;
output sdramwen;
output sdramcasn;
output sdramrasn;
output [14:0] sdramaddr;
output [1:0] sdramcsn;
output [1:0] sdramdqm;
input slavehclk;
input slavehwrite;
input slavehreadyi;
input slavehselreg;
input slavehsel;
input slavehmastlock;
input [31:0] slavehaddr;
input [1:0] slavehtrans;
input [1:0] slavehsize;
input [2:0] slavehburst;
input [31:0] slavehwdata;
output slavehreadyo;
output slavebuserrint;
output [1:0] slavehresp;
output [31:0] slavehrdata;
input masterhclk;
input masterhready;
input masterhgrant;
input [31:0] masterhrdata;
input [1:0] masterhresp;
output masterhwrite;
output masterhlock;
output masterhbusreq;
output [31:0] masterhaddr;
output [2:0] masterhburst;
output [1:0] masterhsize;
output [1:0] masterhtrans;
output [31:0] masterhwdata;
output intuart;
output inttimer0;
output inttimer1;
output intcommtx;
output intcommrx;
input debugrq;
input debugext0;
input debugext1;
input [3:0] debugextin;
output debugack;
output debugrng0;
output debugrng1;
output [3:0] debugextout;
wire proc_ntrst;
wire proc_tck;
wire proc_tdi;
wire proc_tms;
wire proc_tdo;
wire [5:0] intpld;
assign proc_ntrst = 1'b1;
assign proc_tck = 1'b0;
assign proc_tdi = 1'b0;
assign proc_tms = 1'b0;
assign intpld = 6'b0;
alt_exc_stripe lpm_instance
(
.clk_ref(clk_ref),
.npor(npor),
.nreset(nreset),
.uartrxd(uartrxd),
.uartdsrn(uartdsrn),
.uartctsn(uartctsn),
.uartrin(uartrin),
.uartdcdn(uartdcdn),
.uarttxd(uarttxd),
.uartrtsn(uartrtsn),
.uartdtrn(uartdtrn),
.intextpin(intextpin),
.ebiack(ebiack),
.ebidq(ebidq),
.ebiclk(ebiclk),
.ebiwen(ebiwen),
.ebioen(ebioen),
.ebiaddr(ebiaddr),
.ebibe(ebibe),
.ebicsn(ebicsn),
.sdramdq(sdramdq),
.sdramdqs(sdramdqs),
.sdramclk(sdramclk),
.sdramclkn(sdramclkn),
.sdramclke(sdramclke),
.sdramwen(sdramwen),
.sdramcasn(sdramcasn),
.sdramrasn(sdramrasn),
.sdramaddr(sdramaddr),
.sdramcsn(sdramcsn),
.sdramdqm(sdramdqm),
.slavehclk(slavehclk),
.slavehwrite(slavehwrite),
.slavehreadyi(slavehreadyi),
.slavehselreg(slavehselreg),
.slavehsel(slavehsel),
.slavehmastlock(slavehmastlock),
.slavehaddr(slavehaddr),
.slavehtrans(slavehtrans),
.slavehsize(slavehsize),
.slavehburst(slavehburst),
.slavehwdata(slavehwdata),
.slavehreadyo(slavehreadyo),
.slavebuserrint(slavebuserrint),
.slavehresp(slavehresp),
.slavehrdata(slavehrdata),
.masterhclk(masterhclk),
.masterhready(masterhready),
.masterhgrant(masterhgrant),
.masterhrdata(masterhrdata),
.masterhresp(masterhresp),
.masterhwrite(masterhwrite),
.masterhlock(masterhlock),
.masterhbusreq(masterhbusreq),
.masterhaddr(masterhaddr),
.masterhburst(masterhburst),
.masterhsize(masterhsize),
.masterhtrans(masterhtrans),
.masterhwdata(masterhwdata),
.intuart(intuart),
.inttimer0(inttimer0),
.inttimer1(inttimer1),
.intcommtx(intcommtx),
.intcommrx(intcommrx),
.debugrq(debugrq),
.debugext0(debugext0),
.debugext1(debugext1),
.debugextin(debugextin),
.debugack(debugack),
.debugrng0(debugrng0),
.debugrng1(debugrng1),
.debugextout(debugextout),
.proc_ntrst(proc_ntrst),
.proc_tck(proc_tck),
.proc_tdi(proc_tdi),
.proc_tms(proc_tms),
.proc_tdo(proc_tdo),
.intpld(intpld)
);
defparam
lpm_instance.sdram_width = 16,
lpm_instance.sdramdqm_width = 2,
lpm_instance.processor = "ARM",
lpm_instance.device_size = 100,
lpm_instance.boot_from_flash = "TRUE",
lpm_instance.debug_extensions = "TRUE",
lpm_instance.ebi0_width = 16,
lpm_instance.use_initialisation_files = "TRUE",
lpm_instance.use_short_reset = "TRUE",
lpm_instance.dp0_output_mode = "UNREG",
lpm_instance.dp1_output_mode = "UNREG",
lpm_instance.dp0_mode = "UNUSED",
lpm_instance.dp1_mode = "UNUSED";
endmodule
|
/*
* Copyright 2017 Google Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define IVERILOG_SIM
`define TEST_PROG "prog_load_store.list"
`include "top.v"
module top_test_load_store;
localparam WIDTH = 8;
localparam UART_WIDTH = $clog2(WIDTH);
localparam OUTPUT_CNT = 3;
reg clk = 1;
reg uart_clk = 0;
reg receiving = 0;
reg display = 0;
reg [UART_WIDTH-1 : 0] serial_cnt = 0;
reg [WIDTH-1 : 0] serial_data;
wire uart_tx;
reg [WIDTH-1 : 0] expected_output = 1;
always #2 clk = !clk;
always #4 uart_clk = !uart_clk;
top t(
.clk(clk),
.uart_tx_line(uart_tx));
always @ (posedge uart_clk) begin
if (receiving) begin
if (serial_cnt == WIDTH - 1) begin
receiving <= 0;
display <= 1;
end
serial_data[serial_cnt] <= uart_tx;
serial_cnt <= serial_cnt + 1;
end else if (display) begin
if (expected_output >= OUTPUT_CNT) begin
$display("Load and store test passed!\n");
$finish;
end
if (serial_data != expected_output) begin
$display("Load and store test failed!\n");
$display("Serial output:%d doesn't match expected_output:%d\n",
serial_data, expected_output);
$finish;
end
expected_output <= expected_output + 1;
display <= 0;
end else begin
if (uart_tx == 0) begin
receiving <= 1;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, k; cin >> n >> k; char arr[] = { a , b , c , d , e , f , g , h , i , j , k , l , m , n , o , p , q , r , s , t , u , v , w , x , y , z }; int i = 0; while (n--) { cout << arr[i]; i++; if (i == k) { i = 0; } } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; int b[4], c, n, l = 0, a, i; int main() { scanf( %d , &n); for (i = 0; i < n; i++) { scanf( %d , &a); b[a]++; } cout << n - max(b[1], max(b[2], b[3])) << endl; return 0; } |
/*module MIPS_Single_Register(Rs_addr,Rt_addr,Rd_addr,Clk,Rd_write_byte_en,Rd_in,Rs_out,Rt_out);
input Clk;
input [4:0]Rs_addr,Rt_addr,Rd_addr;
input [7:0]Rd_in;
input Rd_write_byte_en;
output [7:0]Rs_out,Rt_out;
reg [7:0]register[31:0];
always @(negedge Clk)
begin
if(Rd_addr!=0 && Rd_write_byte_en)
register[Rd_addr][7:0] <= Rd_in[7:0];
end
assign Rs_out = register[Rs_addr];
assign Rt_out = register[Rt_addr];
endmodule
module MIPS_Register(Rs_addr,Rt_addr,Rd_addr,Clk,Rd_write_byte_en,Rd_in,Rs_out,Rt_out);
input Clk;
input [4:0]Rs_addr,Rt_addr,Rd_addr;
input [31:0]Rd_in;
input [3:0]Rd_write_byte_en;
output [31:0]Rs_out,Rt_out;
MIPS_Single_Register(Rs_addr,Rt_addr,Rd_addr,Clk,Rd_write_byte_en[0],Rd_in[7:0],Rs_out[7:0],Rt_out[7:0]);
MIPS_Single_Register(Rs_addr,Rt_addr,Rd_addr,Clk,Rd_write_byte_en[1],Rd_in[15:8],Rs_out[15:8],Rt_out[15:8]);
MIPS_Single_Register(Rs_addr,Rt_addr,Rd_addr,Clk,Rd_write_byte_en[2],Rd_in[23:16],Rs_out[23:16],Rt_out[23:16]);
MIPS_Single_Register(Rs_addr,Rt_addr,Rd_addr,Clk,Rd_write_byte_en[3],Rd_in[31:24],Rs_out[31:24],Rt_out[31:24]);
endmodule
*/
module MIPS_Register(Rs_addr,Rt_addr,Rd_addr,Clk,Rd_write_byte_en,Rd_in,Rs_out,Rt_out);
input Clk;
input [4:0]Rs_addr,Rt_addr,Rd_addr;
input [31:0]Rd_in;
input [3:0]Rd_write_byte_en;
output [31:0]Rs_out,Rt_out;
reg [31:0]register[31:0];
assign Rs_out = register[Rs_addr];
assign Rt_out = register[Rt_addr];
initial
begin
//register[1] = 1;
//register[2] = 100;
//register[3] = 0;
register[0] = 32'h0;
register[1] = 32'h11112345;
register[2] = 32'h2;
register[3] = 32'h3;
register[4] = 32'h4;
register[5] = 32'h55556789;
register[8] = 32'h88;
register[9] = 32'h5467_8932;
register[10] = 32'h3476_8906;
register[11] = 32'hfffa_bcde;
register[12] = 32'h6789_3954;
register[13] = 32'h88;
register[30] = 32'hffff_ffff;
register[31] = 32'h7fff_ffff;
end
always @(negedge Clk)
begin
if(Rd_addr!=0)
begin
case(Rd_write_byte_en)
4'b0001: register[Rd_addr][7:0] <= Rd_in[7:0];
4'b0010: register[Rd_addr][15:8] <= Rd_in[15:8];
4'b0011: register[Rd_addr][15:0] <= Rd_in[15:0];
4'b0100: register[Rd_addr][23:16] <= Rd_in[23:16];
4'b0101: begin register[Rd_addr][23:16] <= Rd_in[23:16]; register[Rd_addr][7:0] <= Rd_in[7:0];end
4'b0110: register[Rd_addr][23:8] <= Rd_in[23:8];
4'b0111: register[Rd_addr][23:0] <= Rd_in[23:0];
4'b1000: register[Rd_addr][31:24] <= Rd_in[31:24];
4'b1001: begin register[Rd_addr][31:24] <= Rd_in[31:24]; register[Rd_addr][7:0] <= Rd_in[7:0];end
4'b1010: begin register[Rd_addr][31:24] <= Rd_in[31:24]; register[Rd_addr][15:8] <= Rd_in[15:8];end
4'b1011: begin register[Rd_addr][31:24] <= Rd_in[31:24]; register[Rd_addr][15:0] <= Rd_in[15:0];end
4'b1100: register[Rd_addr][31:16] <= Rd_in[31:16];
4'b1101: begin register[Rd_addr][31:16] <= Rd_in[31:16]; register[Rd_addr][7:0] <= Rd_in[7:0];end
4'b1110: register[Rd_addr][31:8] <= Rd_in[31:8];
4'b1111: register[Rd_addr] <= Rd_in;
default:;
endcase
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> inline void chmin(A &a, B b) { if (a > b) a = b; } template <typename A, typename B> inline void chmax(A &a, B b) { if (a < b) a = b; } template <class A, class B> ostream &operator<<(ostream &ost, const pair<A, B> &p) { ost << { << p.first << , << p.second << } ; return ost; } template <class T> ostream &operator<<(ostream &ost, const vector<T> &v) { ost << { ; for (long long i = 0; i < v.size(); i++) { if (i) ost << , ; ost << v[i]; } ost << } ; return ost; } template <class T> vector<long long> zalgorithm(T s) { vector<long long> a(s.size()); a[0] = s.size(); long long i = 1, j = 0; while (i < s.size()) { while (i + j < s.size() && s[j] == s[i + j]) j++; a[i] = j; if (j == 0) { i++; continue; } long long k = 1; while (i + k < s.size() && k + a[k] < j) a[i + k] = a[k], k++; i += k; j -= k; } return a; } long long N, K, M; vector<long long> calcPre(const string &s, const string &p) { string X = s + p; vector<long long> z = zalgorithm(X); vector<long long> a(p.size() + 1); for (long long i = 1; i <= p.size(); i++) { if (z[X.size() - i] == i) a[i] = 1; } return a; } vector<long long> calcSuf(const string &s, const string &p) { string X = p + s; vector<long long> z = zalgorithm(X); vector<long long> a(p.size() + 1); for (long long i = 1; i <= p.size(); i++) { if (z[X.size() - i] == i) a[i] = 1; } return a; } long long calcOcc(const string &s, const string &p) { string X = p + s; vector<long long> z = zalgorithm(X); long long ret = 0; for (long long i = 0; i < s.size(); i++) if (z[p.size() + i] >= p.size()) ret++; return ret; } long long mrg(const vector<long long> &a, const vector<long long> &b) { long long cnt = 0; for (long long i = 0; i < a.size(); i++) if (a[i] && b[b.size() - 1 - i]) cnt++; return cnt; } vector<long long> pre[222], suf[222]; long long occ[222]; vector<string> first; void calc(string s) { long long t; if (N <= 1) { t = 0; } else { t = 2; while (first[t].size() < s.size()) t++; } for (long long k = 0; k < (2); k++) { pre[t + k] = calcPre(first[t + k], s); suf[t + k] = calcSuf(first[t + k], s); occ[t + k] = calcOcc(first[t + k], s); chmin(occ[t + k], K + 1); } long long BC = mrg(suf[t], pre[t + 1]); long long BA = mrg(suf[t], pre[t]); for (long long i = t + 2; i <= N; i++) { occ[i] = occ[i - 1] + occ[i - 2] + BC; chmin(occ[i], K + 1); swap(pre[i], pre[i - 2]); swap(suf[i], suf[i - 2]); swap(BC, BA); } } signed main() { first.push_back( 0 ); first.push_back( 1 ); while (first.back().size() < 10000) { first.push_back(first[first.size() - 2] + first[first.size() - 1]); } cin >> N >> K >> M; K--; string ans; for (long long i = 0; i < M; i++) { if (i) { if (suf[N][ans.size()]) { if (K == 0) break; K--; } } calc(ans + 0 ); long long tmp = occ[N]; if (tmp <= K) { K -= tmp; ans += 1 ; calc(ans); } else { ans += 0 ; } } cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211OI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__A211OI_BEHAVIORAL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a211oi (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211OI_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4BB_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NOR4BB_FUNCTIONAL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4bb (
VPWR,
VGND,
Y ,
A ,
B ,
C_N ,
D_N
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
// Local signals
wire DN nor0_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , nor0_out, C_N, D_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4BB_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int v[1010][10], rez[1010]; int main() { int n, nr = 0, l = 0; scanf( %d , &n); for (int i = 1; i <= n; i++) { int p = 0; for (int j = 1; j <= 5; j++) scanf( %d , &v[i][j]); } if (n > 200) { printf( 0 ); return 0; } for (int i = 1; i <= n; i++) { int p = 0; for (int j = 1; j <= n; j++) if (i != j) { for (int k = 1; k <= n; k++) if (j != k && i != k) { int c = 0; for (int m = 1; m <= 5; m++) c += (v[j][m] - v[i][m]) * (v[k][m] - v[i][m]); if (c > 0) { p = 1; break; } } if (p == 1) break; } if (p == 0) rez[++l] = i; } printf( %d n , l); for (int i = 1; i <= l; i++) printf( %d n , rez[i]); return 0; } |
timeunit 10us;
timeprecision 10us;
module fast_g (out);
output out;
reg out;
initial begin
#0 out = 0;
#1 out = 1; // 10us
end
endmodule // fast_g
`timescale 100us / 1us
// These will be ignored since a `timescale was already given.
timeunit 10us;
timeprecision 10us;
module slow (out);
output out;
reg out;
initial begin
#0 out = 0;
#1 out = 1; // 100us
end
endmodule // slow
module fast (out);
timeunit 10us;
timeprecision 1us;
output out;
reg out;
initial begin
#0 out = 0;
#1 out = 1; // 10us
end
endmodule // fast
module saf(out);
output out;
reg out;
initial begin
#0 out = 0;
#1 out = 1; // 100us
end
endmodule // saf
`timescale 1us / 1us
module main;
reg pass;
wire slow, fast, fast_g, saf;
slow m1 (slow);
fast_g m2 (fast_g);
fast m3 (fast);
saf m4 (saf);
initial begin
pass = 1'b1;
#9;
if (slow !== 1'b0) begin
$display("FAILED: slow at 9us, expected 1'b0, got %b.", slow);
pass = 1'b0;
end
if (saf !== 1'b0) begin
$display("FAILED: saf at 9us, expected 1'b0, got %b.", saf);
pass = 1'b0;
end
if (fast !== 1'b0) begin
$display("FAILED: fast at 9us, expected 1'b0, got %b.", fast);
pass = 1'b0;
end
if (fast_g !== 1'b0) begin
$display("FAILED: fast_g at 9us, expected 1'b0, got %b.", fast_g);
pass = 1'b0;
end
#2 // 11us
if (slow !== 1'b0) begin
$display("FAILED: slow at 11us, expected 1'b0, got %b.", slow);
pass = 1'b0;
end
if (saf !== 1'b0) begin
$display("FAILED: saf at 11us, expected 1'b0, got %b.", saf);
pass = 1'b0;
end
if (fast !== 1'b1) begin
$display("FAILED: fast at 11us, expected 1'b1, got %b.", fast);
pass = 1'b0;
end
if (fast_g !== 1'b1) begin
$display("FAILED: fast_g at 11us, expected 1'b1, got %b.", fast_g);
pass = 1'b0;
end
#88 // 99 us
if (slow !== 1'b0) begin
$display("FAILED: slow at 99us, expected 1'b0, got %b.", slow);
pass = 1'b0;
end
if (saf !== 1'b0) begin
$display("FAILED: saf at 99us, expected 1'b0, got %b.", saf);
pass = 1'b0;
end
if (fast !== 1'b1) begin
$display("FAILED: fast at 99us, expected 1'b1, got %b.", fast);
pass = 1'b0;
end
if (fast_g !== 1'b1) begin
$display("FAILED: fast_g at 99us, expected 1'b1, got %b.", fast_g);
pass = 1'b0;
end
#2 // 101 us
if (slow !== 1'b1) begin
$display("FAILED: slow at 101us, expected 1'b1, got %b.", slow);
pass = 1'b0;
end
if (saf !== 1'b1) begin
$display("FAILED: saf at 101us, expected 1'b1, got %b.", saf);
pass = 1'b0;
end
if (fast !== 1'b1) begin
$display("FAILED: fast at 101us, expected 1'b1, got %b.", fast);
pass = 1'b0;
end
if (fast_g !== 1'b1) begin
$display("FAILED: fast_g at 101us, expected 1'b1, got %b.", fast_g);
pass = 1'b0;
end
if (pass) $display("PASSED");
end // initial begin
endmodule // main
|
#include <bits/stdc++.h> using namespace std; const int N = 510; int t, n, m, a, b, c; vector<pair<int, int> > g[N]; int dp[N][N], inDegree[N][N], source, ans[N][N]; bool vis[N]; void dfs(int u) { if (vis[u]) return; vis[u] = 1; for (int i = 0; i < g[u].size(); i++) { int v = g[u][i].first; int newCost = g[u][i].second + dp[source][u]; if (dp[source][v] == newCost) { inDegree[source][v]++; dfs(v); } } } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { dp[i][j] = 1e9; } dp[i][i] = 0; } for (int i = 0; i < m; ++i) { scanf( %d%d%d , &a, &b, &c); g[a].push_back(make_pair(b, c)); g[b].push_back(make_pair(a, c)); dp[a][b] = min(dp[a][b], c); dp[b][a] = min(dp[b][a], c); } for (int k = 1; k <= n; k++) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { dp[i][j] = min(dp[i][j], dp[i][k] + dp[k][j]); } } } for (source = 1; source <= n; source++) { memset(vis, 0, sizeof vis); dfs(source); } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { for (int k = 1; k <= n; k++) { if (dp[i][k] + dp[k][j] == dp[i][j]) { ans[i][j] += inDegree[i][k]; } } } } for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { printf( %d , ans[i][j]); } } puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline T BM(T p, T e, T M) { long long int ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % M; p = (p * p) % M; } return (T)ret; } template <class T> inline T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> inline T mdINV(T a, T M) { return BM(a, M - 2, M); } template <class T> inline T PW(T p, T e) { long long int ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p); p = (p * p); } return (T)ret; } template <class T> string NTS(T Number) { stringstream ss; ss << Number; return ss.str(); } template <class T> T stringtonumber(const string &Text) { istringstream ss(Text); T result; return ss >> result ? result : 0; } template <class T> bool ISLEFT(T a, T b, T c) { if (((a.first.first - b.first.first) * (b.second.second - c.second.second) - (b.first.first - c.first.first) * (a.second.second - b.second.second)) < 0.0) return 1; else return 0; } int n, k; vector<int> v[300ll + 2]; long long int dp[102][44]; void go(int u, int p) { dp[u][0] = 1; dp[u][k + 1] = 1; for (int i = 0; i < v[u].size(); i++) { int first = v[u][i]; if (first == p) continue; go(first, u); long long int kop[44]; memset(kop, 0, sizeof kop); for (int j = 0; j <= k * 2; j++) { for (int l = 0; l <= k * 2; l++) { if (j + l <= k * 2) { kop[min(j, l + 1)] = (kop[min(j, l + 1)] + dp[u][j] * dp[first][l]) % 1000000007; } else { kop[max(j, l + 1)] = (kop[max(j, l + 1)] + dp[u][j] * dp[first][l]) % 1000000007; } } } for (int j = 0; j <= k * 2; j++) dp[u][j] = kop[j]; } } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n - 1; i++) { int first, second; scanf( %d%d , &first, &second); v[first].push_back(second); v[second].push_back(first); } go(1, -1); int ans = 0; for (int i = 0; i <= k; i++) { ans += dp[1][i]; if (ans >= 1000000007) ans -= 1000000007; } printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> pat[100000]; int main() { int num, way; scanf( %d%d , &num, &way); set<pair<int, int> > se; for (int i = 0; i < way; i++) { int za, zb; scanf( %d%d , &za, &zb); za--; zb--; pat[za].push_back(zb); pat[zb].push_back(za); se.insert(make_pair(za, zb)); se.insert(make_pair(zb, za)); } if (num <= 9) { vector<int> vec; for (int i = 0; i < num; i++) { vec.push_back(i); } for (;;) { bool f = true; for (int i = 0; i < way; i++) { if (se.find(make_pair(vec[i], vec[(i + 1) % num])) != se.end()) { f = false; break; } } if (f) { for (int i = 0; i < way; i++) { printf( %d %d n , vec[i] + 1, vec[(i + 1) % num] + 1); } return 0; } if (!next_permutation(vec.begin(), vec.end())) { printf( -1 n ); return 0; } } } vector<pair<int, int> > ans; int now = 0; set<int> rem; for (int i = 1; i < num; i++) { rem.insert(i); } for (int i = 0; i < num - 9; i++) { set<int>::iterator it = rem.begin(); for (;;) { if (se.find(make_pair(now, (*it))) == se.end()) { ans.push_back(make_pair(now, (*it))); now = *it; rem.erase(it); break; } it++; } } set<int>::iterator it = rem.begin(); vector<int> vec; for (int i = num - 8; i < num; i++) { vec.push_back((*it)); it++; } for (;;) { bool f = true; for (int i = 0; i < 7; i++) { if (se.find(make_pair(vec[i], vec[i + 1])) != se.end()) { f = false; break; } } if (se.find(make_pair(ans[ans.size() - 1].second, vec[0])) != se.end() || se.find(make_pair(vec[vec.size() - 1], ans[0].first)) != se.end()) { f = false; } if (f) { ans.push_back(make_pair(ans[ans.size() - 1].second, vec[0])); for (int i = 0; i < 7; i++) { ans.push_back(make_pair(vec[i], vec[i + 1])); } ans.push_back(make_pair(vec[vec.size() - 1], ans[0].first)); break; } if (!next_permutation(vec.begin(), vec.end())) { abort(); return 0; } } for (int i = 0; i < way; i++) { printf( %d %d n , ans[i].first + 1, ans[i].second + 1); } } |
#include <bits/stdc++.h> using namespace std; string s; int len; set<string> v; bool check[111111][5]; void fuck(string father, int now) { if (now - 2 > 4) { string now1 = s.substr(now - 2, 2); if (now1 != father) { v.insert(now1); if (check[now - 2][2] == true) check[now - 2][2] = false, fuck(now1, now - 2); } } if (now - 3 > 4) { string now2 = s.substr(now - 3, 3); if (now2 != father) { v.insert(now2); if (check[now - 3][3] == true) check[now - 3][3] = false, fuck(now2, now - 3); } } } int main() { cin >> s; memset(check, true, sizeof(check)); len = s.length(); fuck( , len); cout << v.size() << endl; for (set<string>::iterator it = v.begin(); it != v.end(); it++) cout << *it << endl; } |
#include <bits/stdc++.h> using namespace std; const int Mod = 1e9 + 7; const double pi = 2 * acos(0.0); const int N = 3e5 + 5; int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, t; cin >> t; while (t--) { cin >> n; int x, z = 0, tot = 0; for (int i = 0; i < n; i++) { cin >> x; if (!x) z++; tot += x; } cout << z + ((tot + z) == 0) << endl; } return 0; } |
#include <bits/stdc++.h> int cnt[1001][1001], que[1000001][2], head = -1, tail; char map[1001][1001]; int n, m; int main() { int i, j, a, go[4][2] = {1, 0, 0, 1, -1, 0, 0, -1}, print; scanf( %d %d , &n, &m); for (i = 0; i < n; i++) { scanf( %s , map[i]); for (j = 0; j < m; j++) { if (map[i][j] == E ) { que[++head][0] = i; que[head][1] = j; cnt[i][j] = 1; } } } while (head >= tail) { i = que[tail][0]; j = que[tail++][1]; for (a = 0; a < 4; a++) { if (i + go[a][0] >= 0 && j + go[a][1] >= 0 && i + go[a][0] < n && j + go[a][1] < m && map[i + go[a][0]][j + go[a][1]] != T && cnt[i + go[a][0]][j + go[a][1]] == 0) { que[++head][0] = i + go[a][0]; que[head][1] = j + go[a][1]; cnt[i + go[a][0]][j + go[a][1]] = cnt[i][j] + 1; } } } for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (map[i][j] == S ) print = cnt[i][j]; } } int sum = 0; for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (print >= cnt[i][j] && map[i][j] >= 0 && map[i][j] <= 9 && cnt[i][j] != 0) sum += map[i][j] - 0 ; } } printf( %d n , sum); return 0; } |
#include <bits/stdc++.h> using namespace std; int kol[10], ans = -1, ans0 = 0; vector<int> a, b; int main() { memset(kol, 0, sizeof(kol)); char c; while (cin >> c) kol[c - 0 ]++; for (int i = 1; i < 10; i++) { vector<int> c, d; int K1[10], K2[10], res = 0, nul = 0; for (int j = 0; j < 10; j++) { K1[j] = kol[j]; K2[j] = kol[j]; } if (K1[i] > 0 && K2[10 - i] > 0) { c.push_back(i); d.push_back(10 - i); K1[i]--; K2[10 - i]--; res++; for (int j = 0; j < 10; j++) { while (K1[j] > 0 && K2[9 - j] > 0) { K1[j]--; K2[9 - j]--; c.push_back(j); d.push_back(9 - j); res++; } } } while (K1[0] > 0 && K2[0] > 0) { K1[0]--; K2[0]--; res++; nul++; } for (int j = 0; j < 10; j++) { while (K1[j] > 0) { K1[j]--; c.push_back(j); } while (K2[j] > 0) { K2[j]--; d.push_back(j); } } if (res > ans) { ans = res; ans0 = nul; a.swap(c); b.swap(d); } } for (int i = a.size() - 1; i >= 0; i--) cout << a[i]; for (int i = 0; i < ans0; i++) cout << 0; cout << endl; for (int i = a.size() - 1; i >= 0; i--) cout << b[i]; for (int i = 0; i < ans0; i++) cout << 0; } |
`timescale 1ns / 1ps
/* This file is part of JT51.
JT51 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Based on hardware measurements and Sauraen VHDL version of OPN/OPN2,
which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-4-2017
*/
module jt51_exprom
(
input [4:0] addr,
input clk,
output reg [44:0] exp
);
reg [44:0] explut[31:0];
initial
begin
explut[0] = 45'b111110101011010110001011010000010010111011011;
explut[1] = 45'b111101010011010101000011001100101110110101011;
explut[2] = 45'b111011111011010011110111001000110010101110011;
explut[3] = 45'b111010100101010010101111000100110010101000011;
explut[4] = 45'b111001001101010001100111000000110010100001011;
explut[5] = 45'b110111111011010000011110111101010010011011011;
explut[6] = 45'b110110100011001111010110111001010010010100100;
explut[7] = 45'b110101001011001110001110110101110010001110011;
explut[8] = 45'b110011111011001101000110110001110010001000011;
explut[9] = 45'b110010100011001011111110101110010010000010011;
explut[10] = 45'b110001010011001010111010101010010001111011011;
explut[11] = 45'b101111111011001001110010100110110001110101011;
explut[12] = 45'b101110101011001000101010100011001101101111011;
explut[13] = 45'b101101010101000111100110011111010001101001011;
explut[14] = 45'b101100000011000110100010011011110001100011011;
explut[15] = 45'b101010110011000101011110011000010001011101011;
explut[16] = 45'b101001100011000100011010010100101101010111011;
explut[17] = 45'b101000010011000011010010010001001101010001011;
explut[18] = 45'b100111000011000010010010001101101101001011011;
explut[19] = 45'b100101110011000001001110001010001101000101011;
explut[20] = 45'b100100100011000000001010000110010000111111011;
explut[21] = 45'b100011010010111111001010000011001100111001011;
explut[22] = 45'b100010000010111110000101111111101100110011011;
explut[23] = 45'b100000110010111101000001111100001100101101011;
explut[24] = 45'b011111101010111100000001111000101100101000010;
explut[25] = 45'b011110011010111011000001110101001100100010011;
explut[26] = 45'b011101001010111010000001110001110000011100011;
explut[27] = 45'b011100000010111001000001101110010000010110011;
explut[28] = 45'b011010110010111000000001101011001100010001011;
explut[29] = 45'b011001101010110111000001100111101100001011011;
explut[30] = 45'b011000100000110110000001100100010000000110010;
explut[31] = 45'b010111010010110101000001100001001100000000011;
end
always @ (posedge clk)
exp <= explut[addr];
endmodule
|
#include <bits/stdc++.h> using namespace std; long long cdiv(long long x, long long y) { return x / y + (x % y > 0); } long long w(long long a, long long b) { return cdiv(a, 2) * cdiv(b, 2) + (a / 2) * (b / 2); } long long W(long long x1, long long y1, long long x2, long long y2) { return w(x2, y2) - w(x2, y1 - 1) - w(x1 - 1, y2) + w(x1 - 1, y1 - 1); } long long B(long long x1, long long y1, long long x2, long long y2) { return (y2 - y1 + 1) * (x2 - x1 + 1) - W(x1, y1, x2, y2); } int main() { int t; cin >> t; while (t--) { int x1, x2, x3, x4, y1, y2, y3, y4; long long n, m; cin >> n >> m; cin >> x1 >> y1 >> x2 >> y2 >> x3 >> y3 >> x4 >> y4; long long white = W(1, 1, m, n); long long black = B(1, 1, m, n); white = white + B(x1, y1, x2, y2); black = black - B(x1, y1, x2, y2); white = white - W(x3, y3, x4, y4); black = black + W(x3, y3, x4, y4); if (max(x1, x3) <= min(x2, x4) && max(y1, y3) <= min(y2, y4)) { white = white - B(max(x1, x3), max(y1, y3), min(x2, x4), min(y2, y4)); black = black + B(max(x1, x3), max(y1, y3), min(x2, x4), min(y2, y4)); } cout << white << << black << n ; } } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) using namespace std; void read(long long &x) { char ch = getchar(); x = 0; while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 48, ch = getchar(); } const long long N = 105, mod = 1e9 + 9; long long n, now, m, sz[N], f[N][N], p[N], in[N], res[N]; long long cnt, h[N], to[N * N], nxt[N * N], c[N], inv[N]; void add(long long u, long long v) { to[++cnt] = v, nxt[cnt] = h[u], h[u] = cnt, ++c[v]; } queue<long long> q; long long vis[N], used[N]; void topo() { for (long long i = 1; i <= n; ++i) if (c[i] <= 1) vis[i] = 1, q.push(i); while (!q.empty()) { long long t = q.front(); q.pop(); for (long long i = h[t], v; i; i = nxt[i]) { if ((--c[v = to[i]]) <= 1 && !vis[v]) vis[v] = 1, q.push(v); } } } long long C(long long x, long long y) { return p[x] * in[y] % mod * in[x - y] % mod; } void dp(long long u) { used[u] = sz[u] = f[u][0] = 1; for (long long i = h[u], v; i; i = nxt[i]) { if (used[v = to[i]] || !vis[v]) continue; dp(v); for (long long x = sz[u] - 1; x >= 0; --x) for (long long y = 1; y <= sz[v]; ++y) ((f[u][x + y] += f[u][x] * f[v][y] % mod * C(x + y, x) % mod) >= mod && (f[u][x + y] -= mod)); sz[u] += sz[v]; } f[u][sz[u]] = f[u][sz[u] - 1]; } long long Pow(long long x, long long y) { long long tmp = 1; while (y) { if (y & 1) tmp = tmp * x % mod; x = x * x % mod, y >>= 1; } return tmp; } vector<long long> st; void find(long long u, long long la) { st.push_back(u); for (long long i = h[u], v; i; i = nxt[i]) if ((v = to[i]) != la) find(v, u); } long long tmp[N]; void work(long long u, long long la) { memset(f[u], 0, sizeof(f[u])); sz[u] = f[u][0] = 1; for (long long i = h[u], v; i; i = nxt[i]) { if ((v = to[i]) == la) continue; work(v, u); for (long long x = sz[u] - 1; x >= 0; --x) for (long long y = 1; y <= sz[v]; ++y) ((f[u][x + y] += f[u][x] * f[v][y] % mod * C(x + y, y) % mod) >= mod && (f[u][x + y] -= mod)); sz[u] += sz[v]; } f[u][sz[u]] = f[u][sz[u] - 1]; } void merge(long long *a, long long tot) { for (long long i = now; i >= 0; --i) for (long long j = 1; j <= tot; ++j) ((res[i + j] += res[i] * a[j] % mod * C(i + j, i) % mod) >= mod && (res[i + j] -= mod)); now += tot; } signed main() { read(n), read(m); for (long long i = 1, u, v; i <= m; ++i) read(u), read(v), add(u, v), add(v, u); topo(); p[0] = res[0] = 1; for (long long i = 1; i <= n; ++i) p[i] = p[i - 1] * i % mod; in[n] = Pow(p[n], mod - 2); for (long long i = n - 1; i >= 0; --i) in[i] = in[i + 1] * (i + 1) % mod; for (long long i = 1; i <= n; ++i) inv[i] = Pow(i, mod - 2); for (long long i = 1; i <= n; ++i) { if (vis[i]) continue; for (long long j = h[i], v; j; j = nxt[j]) if (vis[v = to[j]] && !used[v]) dp(v), merge(f[v], sz[v]); } for (long long i = 1; i <= n; ++i) if (vis[i] && !used[i]) { st.clear(), find(i, i); long long tot = st.size(); memset(tmp, 0, sizeof(tmp)); for (long long j = 0; j < tot; ++j) { work(st[j], st[j]), used[st[j]] = 1; for (long long k = 0; k <= tot; ++k) ((tmp[k] += f[st[j]][k]) >= mod && (tmp[k] -= mod)); } for (long long j = 0; j < tot; ++j) tmp[j] = tmp[j] * inv[tot - j] % mod; merge(tmp, tot); } for (long long i = 0; i <= n; ++i) printf( %lld n , res[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 11; const long long oo = 1e17 + 123; int tcases = 1; int n, m = 0; long long a[N], b[N], s[N], res[N]; pair<int, int> q[N]; struct Point { double x, y; Point() { x = y = 0; } Point(double _x, double _y) : x(_x), y(y) {} }; struct line { double a, b; line() { a = 1; b = 0; } line(double _a, double _b) { a = _a; b = _b; } long long val(double x) { return (long long)a >= oo ? oo : x * a + b; } double getIntersection(line ll) { return (ll.b - b) / (a - ll.a); } } l0[N]; struct LiChaoTree { vector<int> coor; vector<int> queries; vector<line> f; int m; void addline(int k, int l, int r, line ll) { if (l == r) { if (f[k].val(coor[l - 1]) > ll.val(coor[l - 1])) f[k] = ll; return; } int mid = (l + r) >> 1; bool sl = ll.val(coor[l - 1]) < f[k].val(coor[l - 1]), smid = ll.val(coor[mid] - 1) < f[k].val(coor[mid] - 1); if (smid) swap(f[k], ll); if (sl == smid) { addline(k << 1 | 1, mid + 1, r, ll); } else { addline(k << 1, l, mid, ll); } } long long cal(int k, int l, int r, long long x) { if (coor[l - 1] > x || coor[r - 1] < x) return oo; if (l == r) return f[k].val(x); long long rr = f[k].val(x); int mid = (l + r) >> 1; return min(rr, min(cal(k << 1, l, mid, x), cal(k << 1 | 1, mid + 1, r, x))); } void init(int l, int r) { coor.push_back(-n); coor.push_back(0); for (int i : queries) { coor.push_back(q[i].first - q[i].second - 1); } sort((coor).begin(), (coor).end()); coor.erase(unique((coor).begin(), (coor).end()), coor.end()); m = coor.size() - 1; f.assign(m * 4 + 11, line(oo, oo)); for (int i = l; i <= r; ++i) { addline(1, 1, m, l0[i]); } } void getMin(int l, int r) { init(l, r); for (int i : queries) { int x = q[i].first, y = q[i].second; res[i] = min(res[i], cal(1, 1, m, x - y - 1) + s[y]); } } }; struct IT { LiChaoTree f[N * 4]; void insert(int k, int l, int r, int L, int R, int i) { if (L > r || l > R) return; if (L <= l && r <= R) { f[k].queries.push_back(i); return; } int mid = (l + r) >> 1; insert(k << 1, l, mid, L, R, i); insert(k << 1 | 1, mid + 1, r, L, R, i); } void getMin(int k, int l, int r) { f[k].getMin(l, r); if (l < r) { int mid = (l + r) >> 1; getMin(k << 1, l, mid); getMin(k << 1 | 1, mid + 1, r); } } } segmentTree; void testcase() { cin >> n; for (int i = 1; i <= n; ++i) { cin >> a[i]; s[i] = s[i - 1] + a[i]; l0[i] = line(a[i], a[i] * i - s[i - 1]); } cin >> m; for (int i = 1; i <= m; ++i) { int x, y; cin >> x >> y; segmentTree.insert(1, 1, n, y - x + 1, y, i); q[i] = make_pair(x, y); } for (int i = 1; i <= m; ++i) res[i] = oo; segmentTree.getMin(1, 1, n); for (int i = 1; i <= m; ++i) cout << res[i] << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(); cout.tie(); for (int i = 1; i <= tcases; ++i) testcase(); cerr << nTime elapsed: << 1000 * clock() / CLOCKS_PER_SEC << ms n ; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 14:43:33 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode synth_stub -rename_top mul17_16 -prefix
// mul17_16_ mult_17x16_stub.v
// Design : mult_17x16
// Purpose : Stub declaration of top-level module interface
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
module mul17_16(CLK, A, B, P)
/* synthesis syn_black_box black_box_pad_pin="CLK,A[16:0],B[15:0],P[24:0]" */;
input CLK;
input [16:0]A;
input [15:0]B;
output [24:0]P;
endmodule
|
#include <bits/stdc++.h> const int md = 1e9 + 7; const long long hs = 199; using namespace std; int n, x; set<int> a; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) a.insert(i); cout << 1 ; while (--n) { cin >> x; a.erase(x); auto it = a.end(); it--; cout << 1 + *it - n << n ; } cout << 1 << n ; } |
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module mult_ireg (
input wire CLK,
input wire [ 8:0] A,
input wire [ 8:0] B,
output wire [17:0] Z
);
reg [8:0] ra;
always @(posedge CLK)
ra <= A;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (ra),
.B (B),
.Z (Z)
);
endmodule
module mult_oreg (
input wire CLK,
input wire [ 8:0] A,
input wire [ 8:0] B,
output reg [17:0] Z
);
reg [17:0] z;
always @(posedge CLK)
Z <= z;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (A),
.B (B),
.Z (z)
);
endmodule
module mult_all (
input wire CLK,
input wire [ 8:0] A,
input wire [ 8:0] B,
output reg [17:0] Z
);
reg [8:0] ra;
always @(posedge CLK)
ra <= A;
reg [8:0] rb;
always @(posedge CLK)
rb <= B;
reg [17:0] z;
always @(posedge CLK)
Z <= z;
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (ra),
.B (rb),
.Z (z)
);
endmodule
module mult_ctrl (
input wire CLK,
input wire [ 8:0] A,
input wire SA,
input wire [ 8:0] B,
output wire [17:0] Z
);
reg [8:0] ra;
reg rsa;
always @(posedge CLK) begin
ra <= A;
rsa <= SA;
end
MULT9X9 # (
.REGINPUTA("BYPASS"),
.REGINPUTB("BYPASS"),
.REGOUTPUT("BYPASS")
) mult (
.A (ra),
.SIGNEDA (rsa),
.B (B),
.Z (Z)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2_FUNCTIONAL_V
`define SKY130_FD_SC_HS__NAND2_FUNCTIONAL_V
/**
* nand2: 2-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand2 (
VPWR,
VGND,
Y ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
input B ;
// Local signals
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 310; int mod[3]; int n; string s[maxn]; long long ha[maxn][3]; int prel[maxn]; int main() { ios::sync_with_stdio(false); mod[0] = 1e9 + 7; mod[1] = 1e9 + 9; mod[2] = 19260817; cin >> n; int ans = 0; for (int i = 1; i <= n; i++) { cin >> s[i]; int l = s[i].size(); for (int j = l - 1; j >= 0; j--) { for (int k = 0; k < 3; k++) { ha[i][k] = (ha[i][k] * 131 + s[i][j]) % mod[k]; } } prel[i] = prel[i - 1] + l; } ans = prel[n] + n - 1; int res = 0; for (int i = 1; i <= n; i++) { for (int j = i; j <= n; j++) { int len = j - i + 1, cnt = 0; for (int k = j + 1; k + len - 1 <= n; k++) { bool f = 1; for (int l = 0; l < len; l++) { if (ha[i + l][0] != ha[k + l][0] || ha[i + l][1] != ha[k + l][1] || ha[i + l][2] != ha[k + l][2]) { f = 0; break; } } if (f) cnt++, k += len - 1; } if (cnt == 0) continue; res = max(res, (cnt + 1) * (prel[j] - prel[i - 1] - 1)); } } cout << ans - res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; signed main() { long long int n, m, k; cin >> n >> m >> k; vector<long long int> ans; if (k > 1) { long long int last = 0; for (long long int i = 0; i < k; i++) { ans.push_back(0); } last = n - 1; for (long long int i = 1; i < n + m; i++) { if (i == last) { ans.push_back(i); } else if (i == last + 1) { for (long long int j = 0; j < k - 1; j++) ans.push_back(i); last = i + n - 1; } } } else { ans.push_back(0); long long int last = n - 1; for (long long int i = 1; i < n + m; i++) { if (i == last) { ans.push_back(i); last = i + n - 1; } } } cout << ans.size() << n ; for (auto i : ans) cout << i + 1 << ; return 0; } |
module gost89_cfb(
input clk,
input reset,
input mode,
input load_data,
input [511:0] sbox,
input [255:0] key,
input [63:0] in,
output reg [63:0] out,
output reg busy
);
reg [63:0] gamma;
reg [63:0] in_value;
wire [63:0] out_ecb;
wire reset_ecb, load_ecb, busy_ecb;
assign load_ecb = !reset && load_data;
assign reset_ecb = load_ecb;
gost89_ecb_encrypt
ecb_encrypt(clk, reset_ecb, load_ecb, sbox, key, gamma, out_ecb, busy_ecb);
always @(posedge clk) begin
if (reset && !load_data) begin
gamma <= in;
busy <= 0;
end
if (!reset & load_data) begin
in_value <= in;
busy <= 1;
end
if (!reset && !load_data && !busy_ecb && busy) begin
if (mode) gamma <= in_value;
else gamma <= out_ecb ^ in_value;
out <= out_ecb ^ in_value;
busy <= 0;
end
end
endmodule
module gost89_cfb_encrypt(
input clk,
input reset,
input load_data,
input [511:0] sbox,
input [255:0] key,
input [63:0] in,
output reg [63:0] out,
output reg busy
);
reg [63:0] gamma;
reg [63:0] in_value;
wire [63:0] out_ecb;
wire load_ecb, busy_ecb;
assign load_ecb = !reset && load_data;
assign reset_ecb = load_ecb;
gost89_ecb_encrypt
ecb_encrypt(clk, reset_ecb, load_ecb, sbox, key, gamma, out_ecb, busy_ecb);
always @(posedge clk) begin
if (reset && !load_data) begin
gamma <= in;
busy <= 0;
end
if (!reset & load_data) begin
in_value <= in;
busy <= 1;
end
if (!reset && !load_data && !busy_ecb && busy) begin
gamma <= out_ecb ^ in_value;
out <= out_ecb ^ in_value;
busy <= 0;
end
end
endmodule
module gost89_cfb_decrypt(
input clk,
input reset,
input load_data,
input [511:0] sbox,
input [255:0] key,
input [63:0] in,
output reg [63:0] out,
output reg busy
);
reg [63:0] gamma;
reg [63:0] in_value;
wire [63:0] out_ecb;
wire load_ecb, busy_ecb;
assign load_ecb = !reset && load_data;
assign reset_ecb = load_ecb;
gost89_ecb_encrypt
ecb_encrypt(clk, reset_ecb, load_ecb, sbox, key, gamma, out_ecb, busy_ecb);
always @(posedge clk) begin
if (reset && !load_data) begin
gamma <= in;
busy <= 0;
end
if (!reset & load_data) begin
in_value <= in;
busy <= 1;
end
if (!reset && !load_data && !busy_ecb && busy) begin
gamma <= in_value;
out <= out_ecb ^ in_value;
busy <= 0;
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////////////////////////
// Filename: counter_9bit.v
// Author: T. Martin, Danny Dutton
// Date: 09/07/04
// Version: 4
// Description: This module is a behavioral description of a nine-bit counter with enable and
// asynchronous clear.
//
// This module has three inputs and one output:
//
// clk: (input) system clock
// clear: (input) active-high asynchronous clear
// enable: (input) count advances when asserted high
// cout: (output) 9-bit counter output
//
// This module has two parameters:
//
// CLRDEL: delay from clear asserted to output valid
// CLKDEL: delay from clk rising to output valid
//
// This module is not synthesizable. It is intended for modeling only and should not
// be used as a template for synthesizable modules.
//
// Modification History:
// Date By Version Change Description
// ========================================================
// 09/07/2004 TLM 1 Original
// 08/24/2005 PMA 2 Restructured for Fall 2005
// 10/03/2013 TLM 3 Revised for DD 1, Fall 2013
// 03/23/2015 DJD 4 Modified for 9-bit counter
`timescale 1 ns/100 ps
module counter_9bit (enable, clear, clk, cout);
parameter CLRDEL = 10; // delay from clear asserted to output valid
parameter CLKDEL = 15; // delay from clk rising to output valid
input enable; // count advances when asserted high
input clear; // asynchronous clear (active high)
input clk; // system clock
output [8:0] cout; // 9-bit counter output
reg [8:0] cout; // cout is a reg
// Locally declared nets
reg [8:0] count; // local count holder register
initial count = 0;
// Build behavioral 4-bit up-counter with asynchronous clear
always @(posedge clk or clear) begin
if (clear == 1) begin
count = 9'b0;
cout = #CLRDEL count;
end
else if (clk == 1) begin
if (enable == 1) begin
if (count == 9'd15) begin
count = 0;
end
else begin
count = count + 9'd1;
end
end
cout = #CLKDEL count;
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-7; double dp[10050][1005]; int ans[1005]; int main() { int k, q, p, i, j; cin >> k >> q; memset(dp, 0, sizeof dp); dp[0][0] = 1; for (i = 1;; ++i) { for (j = 1; j <= k; ++j) { dp[i][j] += dp[i - 1][j] * j / k; dp[i][j] += dp[i - 1][j - 1] * (k - j + 1.0) / k; } if (dp[i][k] >= 0.5) break; } int cout = 1; for (i = 1; i <= 1000; ++i) { while (dp[cout][k] < (i - eps) / 2000) cout++; ans[i] = cout; } while (q--) { cin >> p; printf( %d n , ans[p]); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return a * (b / gcd(a, b)); } long long Max(long long a, long long b) { return a > b ? a : b; } long long Min(long long a, long long b) { return a < b ? a : b; } long long power(long long x, long long y, long long p) { long long res = 1; x = x % p; while (y > 0) { if (y & 1) res = ((res % p) * (x % p)) % p; y = y >> 1; x = ((x % p) * (x % p)) % p; } return res; } bool isprime(long long n) { if (n == 2) return true; if (n % 2 == 0) return false; for (long long i = 3; i * i <= n; i += 2) { if (n % i == 0) return false; } return true; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long n, lo = 0, hi = 1000000007LL, ans = -1000000007LL, flag = 0; cin >> n; vector<pair<long long, long long> > arr(n); vector<pair<long long, long long> > poss(n + 1); for (long long i = 0; i < n; i++) { cin >> arr[i].first >> arr[i].second; if (arr[i].second == 2) flag = 1; } if (arr[0].second == 1) { poss[0].first = 1900; poss[0].second = 1000000007LL; } else { poss[0].first = -1000000007LL; poss[0].second = 1899; } for (long long i = 1; i < n; i++) { poss[i].first = poss[i - 1].first + arr[i - 1].first; poss[i].second = poss[i - 1].second + arr[i - 1].first; if (poss[i].first > poss[i].second) { cout << Impossible ; return 0; } if (arr[i].second == 1) { poss[i].first = Max(poss[i].first, 1900); if (poss[i].second < poss[i].first) { cout << Impossible ; return 0; } } else { poss[i].second = Min(poss[i].second, 1899); if (poss[i].second < poss[i].first) { cout << Impossible ; return 0; } } } poss[n].first = poss[n - 1].first + arr[n - 1].first; poss[n].second = poss[n - 1].second + arr[n - 1].first; if (poss[n].first > poss[n].second) { cout << Impossible ; return 0; } else if (flag == 0) { cout << Infinity ; } else { cout << poss[n].second; } return 0; } |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
integer cnt;
`ifdef OVL_SYNTHESIS
`else
initial begin
cnt=0;
end
`endif
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_push;
wire valid_pop;
assign valid_push = ~((^push) ^ (^push));
assign valid_pop = ~((^pop) ^ (^pop));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SHARED_CODE
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
if ({push!=0,pop!=0} == 2'b10) begin // push
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("fifo_push covered");
end
end
`endif // OVL_COVER_ON
if ((cnt + push) > depth) begin
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Fifo overflow detected");
`endif // OVL_ASSERT_ON
end
else begin
cnt <= cnt + push;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if ((cnt + push) == depth) begin
ovl_cover_t("fifo_full covered");
end
end //corner coverage
end
`endif // OVL_COVER_ON
end
end
else if ({push!=0,pop!=0} == 2'b01) begin // pop
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("fifo_pop covered");
end
end
`endif // OVL_COVER_ON
if (cnt < pop) begin
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Fifo underflow detected");
`endif // OVL_ASSERT_ON
end
else begin
cnt <= cnt - pop;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if ((cnt - pop) == 0) begin
ovl_cover_t("fifo_empty covered");
end
end //corner coverage
end
`endif // OVL_COVER_ON
end
end
else if ({push!=0,pop!=0} == 2'b11) begin // push & pop
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
ovl_cover_t("fifo_simultaneous_push_pop covered");
end
end
`endif// OVL_COVER_ON
if (!simultaneous_push_pop) begin
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Illegal simultaneous push pop detected");
`endif
end
else begin
if ((cnt + push - pop) > depth) begin
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Fifo overflow detected due to simultaneous push pop operations");
`endif
end
else if ((cnt + push) < pop) begin
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Fifo underflow detected due to simultaneous push pop operations");
`endif
end
else begin
cnt <= cnt + push - pop;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if ((cnt + push - pop) == depth) begin
ovl_cover_t("fifo_full covered");
end
else if ((cnt + push - pop) == 0) begin
ovl_cover_t("fifo_empty covered");
end
end //corner coverage
end
`endif // OVL_COVER_ON
end
end
end
end
else begin
cnt <= 0;
end
end
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
always @ (posedge clk)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_push == 1'b1)
begin
// Do nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"push contains X or Z");
end
end
always @ (posedge clk)
begin
if (`OVL_RESET_SIGNAL != 1'b0)
begin
if (valid_pop == 1'b1)
begin
// Do nothing
end
else
ovl_error_t(`OVL_FIRE_XCHECK,"pop contains X or Z");
end
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`endif // OVL_SHARED_CODE
|
//////////////////////////////////////////////////////////////////
// //
// Arithmetic Logic Unit (ALU) for Amber 2 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Supported functions: 32-bit add and subtract, AND, OR, //
// XOR, NOT, Zero extent 8-bit numbers //
// //
// Author(s): //
// - Conor Santifort, //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a23_alu (
input [31:0] i_a_in,
input [31:0] i_b_in,
input i_barrel_shift_carry,
input i_status_bits_carry,
input [8:0] i_function,
output [31:0] o_out,
output [3:0] o_flags // negative, zero, carry, overflow
);
wire [31:0] a, b, b_not;
wire [31:0] and_out, or_out, xor_out;
wire [31:0] sign_ex8_out, sign_ex_16_out;
wire [31:0] zero_ex8_out, zero_ex_16_out;
wire [32:0] fadder_out;
wire swap_sel;
wire not_sel;
wire [1:0] cin_sel;
wire cout_sel;
wire [3:0] out_sel;
wire carry_in;
wire carry_out;
wire overflow_out;
wire fadder_carry_out;
assign { swap_sel, not_sel, cin_sel, cout_sel, out_sel } = i_function;
// ========================================================
// A Select
// ========================================================
assign a = (swap_sel ) ? i_b_in : i_a_in ;
// ========================================================
// B Select
// ========================================================
assign b = (swap_sel ) ? i_a_in : i_b_in ;
// ========================================================
// Not Select
// ========================================================
assign b_not = (not_sel ) ? ~b : b ;
// ========================================================
// Cin Select
// ========================================================
assign carry_in = (cin_sel==2'd0 ) ? 1'd0 :
(cin_sel==2'd1 ) ? 1'd1 :
i_status_bits_carry ; // add with carry
// ========================================================
// Cout Select
// ========================================================
assign carry_out = (cout_sel==1'd0 ) ? fadder_carry_out :
i_barrel_shift_carry ;
// For non-addition/subtractions that incorporate a shift
// operation, C is set to the last bit
// shifted out of the value by the shifter.
// ========================================================
// Overflow out
// ========================================================
// Only assert the overflow flag when using the adder
assign overflow_out = out_sel == 4'd1 &&
// overflow if adding two positive numbers and get a negative number
( (!a[31] && !b_not[31] && fadder_out[31]) ||
// or adding two negative numbers and get a positive number
(a[31] && b_not[31] && !fadder_out[31]) );
// ========================================================
// ALU Operations
// ========================================================
assign fadder_out = { 1'd0,a} + {1'd0,b_not} + {32'd0,carry_in};
assign fadder_carry_out = fadder_out[32];
assign and_out = a & b_not;
assign or_out = a | b_not;
assign xor_out = a ^ b_not;
assign zero_ex8_out = {24'd0, b_not[7:0]};
assign zero_ex_16_out = {16'd0, b_not[15:0]};
assign sign_ex8_out = {{24{b_not[7]}}, b_not[7:0]};
assign sign_ex_16_out = {{16{b_not[15]}}, b_not[15:0]};
// ========================================================
// Out Select
// ========================================================
assign o_out = out_sel == 4'd0 ? b_not :
out_sel == 4'd1 ? fadder_out[31:0] :
out_sel == 4'd2 ? zero_ex_16_out :
out_sel == 4'd3 ? zero_ex8_out :
out_sel == 4'd4 ? sign_ex_16_out :
out_sel == 4'd5 ? sign_ex8_out :
out_sel == 4'd6 ? xor_out :
out_sel == 4'd7 ? or_out :
and_out ;
wire only_carry;
// activate for adc
assign only_carry = (out_sel == 4'd1) && (cin_sel == 2'd2);
assign o_flags = only_carry ?
{1'b0, 1'b0, carry_out, 1'b0}:
{
o_out[31], // negative
|o_out == 1'd0, // zero
carry_out, // carry
overflow_out // overflow
};
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 16657 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w16384,
w16385,
w256,
w16641,
w16,
w16657;
assign w1 = i_data0;
assign w16 = w1 << 4;
assign w16384 = w1 << 14;
assign w16385 = w1 + w16384;
assign w16641 = w16385 + w256;
assign w16657 = w16641 + w16;
assign w256 = w1 << 8;
assign o_data0 = w16657;
//multiplier_block area estimate = 4770.05771526471;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x, y, flag = 0; cin >> n >> x >> y; n /= 2; if ((n == x && n == y) || (n == (x - 1) && n == (y - 1)) || (n == (x) && n == (y - 1)) || (n == (x - 1) && n == (y))) flag = 1; if (flag) cout << NO << endl; else cout << YES << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long n; vector<long long> v; cin >> n; long long a = 1; while (a * (a + 1) / 2 <= n) v.push_back(a * (a + 1) / 2), a++; for (long long i = 1; i * (i + 1) / 2 <= n; i++) { int cur = n - i * (i + 1) / 2; if (binary_search(v.begin(), v.end(), cur)) { puts( YES ); return 0; } } puts( NO ); return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_axi_basic_top.v
// Version : 1.11
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_11_0_axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_11_0_axi_basic_rx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
pcie_7x_v1_11_0_axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; using pii = pair<int, int>; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m, k, t; cin >> n >> m >> k >> t; vector<pii> waste(k); for (int i = 0; i < k; ++i) { cin >> waste[i].first >> waste[i].second; --waste[i].first; --waste[i].second; } sort(begin(waste), end(waste)); vector<pair<pii, int>> queries(t); for (int i = 0; i < t; ++i) { cin >> queries[i].first.first >> queries[i].first.second; --queries[i].first.first; --queries[i].first.second; queries[i].second = i; } sort(begin(queries), end(queries)); vector<int> ans(t); int ptr = 0; for (auto& p : queries) { pii pos = p.first; int idx = p.second; while (ptr < k and waste[ptr] < pos) { ++ptr; } if (ptr < k and waste[ptr] == pos) { ans[idx] = 3; } else { int tot = m * pos.first + pos.second; tot -= ptr; ans[idx] = tot % 3; } } vector<string> res = { Carrots , Kiwis , Grapes , Waste }; for (int x : ans) cout << res[x] << n ; return 0; } |
#include <bits/stdc++.h> const long long N = 500005; const long long mod = 1e9 + 7; using namespace std; std::vector<long long> adj[N]; std::vector<bool> vis(N); void solve() { long long n, m, k, x = 0, y = 0, c = 0, q, ans = 0; cin >> n >> m; for (long long i = 0; i < m; ++i) { cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } x = 0; for (int i = 1; i <= n; ++i) { if (x < adj[i].size()) { x = adj[i].size(); y = i; } } std::vector<pair<long long, long long> > v; queue<long long> nodes; nodes.push(y); vis[y] = 1; while (!nodes.empty()) { x = nodes.front(); nodes.pop(); for (auto i : adj[x]) { if (!vis[i]) { vis[i] = 1; nodes.push(i); v.push_back({x, i}); } } } for (int i = 0; i < v.size(); ++i) { cout << v[i].first << << v[i].second << n ; } } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long T = 1; while (T--) { solve(); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND2_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__TAPVGND2_FUNCTIONAL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tapvgnd2 ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND2_FUNCTIONAL_V |
/**
\file "channel-source-sink.v"
Chain a source and sink in prsim to verilog.
$Id: channel-source-sink.v,v 1.4 2010/04/06 00:08:26 fang Exp $
*/
`timescale 1ns/1ps
`include "standard.v"
`define inv_delay 0.020
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg l0, l1, re;
wire le, r0, r1;
DELAY #(.delay(`inv_delay)) d0(l0, r0);
DELAY #(.delay(`inv_delay)) d1(l1, r1);
DELAY #(.delay(`inv_delay)) de(re, le);
// prsim stuff
initial
begin
// @haco@ channel-source-sink.haco-c
$prsim("channel-source-sink.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("echo-commands on");
$from_prsim("L.d[0]","TOP.l0");
$from_prsim("L.d[1]","TOP.l1");
$to_prsim("TOP.le", "L.e");
$to_prsim("TOP.r0", "R.d[0]");
$to_prsim("TOP.r1", "R.d[1]");
$from_prsim("R.e", "TOP.re");
$prsim_cmd("breaks");
$prsim_cmd("watchall");
// $prsim_cmd("watchall-queue");
$prsim_cmd("channel L e:0 :0 d:2");
$prsim_cmd("channel R e:1 :0 d:2");
$prsim_cmd("channel-source-args-loop L 0 1 1 0");
$prsim_cmd("channel-sink R");
$prsim_cmd("channel-watchall");
$prsim_cmd("channel-reset-all");
$prsim_cmd("channel-show-all");
$prsim_cmd("breaks");
end
initial #5 $prsim_cmd("channel-release-all");
initial #5 $prsim_cmd("channel-show-all");
initial #6 $prsim_cmd("nowatchall");
initial #9 $prsim_cmd("why-not-verbose R.e");
initial #9 $prsim_cmd("why-not-verbose R.d[0]");
initial #10 $finish;
/**
initial
$monitor("@%7.3f: l = %d,%d:%d; r = %d,%d:%d", $realtime,
l0, l1, le, r0, r1, re);
**/
endmodule
|
#include <bits/stdc++.h> using namespace std; int getDaysOfMonth(int m) { if (m == 1 || m == 3 || m == 5 || m == 7 || m == 8 || m == 10 || m == 12) return 31; if (m == 2) return 28; return 30; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int n; cin >> n; char a[n]; for (int i = 0; i < int(n); i++) cin >> a[i]; for (int i = 1; i <= n; i++) { if (n % i == 0) { reverse(a, a + i); } } for (int i = 0; i < int(n); i++) cout << a[i]; return 0; } |
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