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#include <bits/stdc++.h> using namespace std; namespace IO { template <typename T> inline void read(T &x) { x = 0; long long f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -f; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 48; ch = getchar(); } x = x * f; } } // namespace IO using namespace IO; const long long maxn = 200000; long long dp[maxn + 10][4]; long long a[maxn + 10]; void DP(long long &x, long long y) { x = max(x, y); } signed main() { long long _; read(_); while (_--) { long long n; read(n); for (long long i = 0; i <= n; i++) { dp[i][0] = dp[i][1] = dp[i][2] = 0; a[i] = 0; } for (long long i = 0; i < n; i++) { read(a[i]); } for (long long i = 0; i < n; i++) { if (i % 2 == 1) { DP(dp[i + 1][0], dp[i][0]); if (i + 2 <= n) DP(dp[i + 2][1], max(dp[i][1] + a[i], dp[i][0] + a[i])); DP(dp[i + 1][2], max(dp[i][1], max(dp[i][0], dp[i][2]))); } else { DP(dp[i + 1][0], dp[i][0] + a[i]); if (i + 2 <= n) DP(dp[i + 2][1], max(dp[i][1], dp[i][0]) + a[i + 1]); DP(dp[i + 1][2], max(dp[i][1], max(dp[i][0], dp[i][2])) + a[i]); } } cout << max(dp[n][1], max(dp[n][2], dp[n][0])) << endl; } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 50 + 10; int a[maxn][maxn]; int dx[10] = {0, 2, 1, 0, -1, -2}; int dy[10] = {2, 0, 1, -2, -1, 0}; int sx, sy; struct Node { int x, y; }; int main() { int n; scanf( %d , &n); memset(a, -1, sizeof(a)); a[1][1] = 1; a[n][n] = 0; queue<Node> q; q.push((Node){1, 1}); while (!q.empty()) { Node tmp = q.front(); q.pop(); int x = tmp.x, y = tmp.y; for (int i = 0; i < 3; i++) { int tx = x + dx[i], ty = y + dy[i]; if (tx < 1 || ty < 1 || tx > n || ty > n) continue; if (a[tx][ty] != -1) continue; cout << ? << << x << << y << << tx << << ty << n ; cout.flush(); int t; cin >> t; a[tx][ty] = t ? a[x][y] : a[x][y] ^ 1; q.push((Node){tx, ty}); } } for (int i = 1; i <= n; i++) { if (i + 2 > n) break; for (int j = 1; j <= n; j++) { if (j + 2 > n) break; if (a[i][j] == 1 && a[i + 2][j + 2] == 0) { sx = i, sy = j; break; } } } int tmp; cout << ? << << sx << << sy + 1 << << sx + 1 << << sy + 2 << n ; cout.flush(); cin >> tmp; if (tmp) { cout << ? << << sx << << sy << << sx + 1 << << sy + 2 << n ; cout.flush(); cin >> tmp; if (tmp) { a[sx][sy + 1] = a[sx + 1][sy + 2] = 1; } else { if (a[sx][sy + 2] == 1) { a[sx][sy + 1] = a[sx + 1][sy + 2] = 0; } else { cout << ? << << sx << << sy + 1 << << sx + 2 << << sy + 2 << n ; cout.flush(); cin >> tmp; if (tmp) { a[sx][sy + 1] = a[sx + 1][sy + 2] = 0; } else { a[sx][sy + 1] = a[sx + 1][sy + 2] = 1; } } } } else { cout << ? << << sx << << sy << << sx + 1 << << sy + 2 << n ; cout.flush(); cin >> tmp; if (tmp) { a[sx][sy + 1] = 0; a[sx + 1][sy + 2] = 1; } else { cout << ? << << sx << << sy + 1 << << sx + 2 << << sy + 2 << n ; cout.flush(); cin >> tmp; if (tmp) { a[sx][sy + 1] = 0; a[sx + 1][sy + 2] = 1; } else { a[sx][sy + 1] = 1; a[sx + 1][sy + 2] = 0; } } } q.push((Node){sx, sy + 1}); while (!q.empty()) { Node tmp = q.front(); q.pop(); int x = tmp.x, y = tmp.y; for (int i = 0; i < 6; i++) { int tx = x + dx[i], ty = y + dy[i]; if (tx < 1 || ty < 1 || tx > n || ty > n) continue; if (a[tx][ty] != -1) continue; if (i < 3) cout << ? << << x << << y << << tx << << ty << n ; else cout << ? << << tx << << ty << << x << << y << n ; cout.flush(); int t; cin >> t; a[tx][ty] = t ? a[x][y] : a[x][y] ^ 1; q.push((Node){tx, ty}); } } cout << ! << n ; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { cout << a[i][j]; } cout << n ; } cout << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2O_SYMBOL_V
`define SKY130_FD_SC_HD__A2BB2O_SYMBOL_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a2bb2o (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2O_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int inf = (int)1e9; const double pi = acos(-1.0); const double eps = 1e-9; long long x, second, res, xx, first; int main() { cin >> second >> x; xx = x; if ((second & 1) != (x & 1)) { cout << 0; return 0; } res = 1; while (xx) { if (xx & 1) res *= 2; xx /= 2; } if (second == x) { cout << res - 2; return 0; } first = second - x; if (first < 0) { cout << 0; return 0; } for (int i = 0; i <= 50; i++) { long long z = (1ll << (i)); long long zz = (1ll << (i + 1)); if ((x & z) > 0 && (first & zz) > 0) { cout << 0; return 0; } } cout << res; return 0; } |
//-----------------------------------------------------------------------------
// module_1_stub.v
//-----------------------------------------------------------------------------
module module_1_stub
(
processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP,
coprocessor_0_LED_OUT_pin,
coprocessor_0_SW_IN_pin,
coprocessor_0_BTN_IN_pin
);
inout [53:0] processing_system7_0_MIO;
input processing_system7_0_PS_SRSTB_pin;
input processing_system7_0_PS_CLK_pin;
input processing_system7_0_PS_PORB_pin;
inout processing_system7_0_DDR_Clk;
inout processing_system7_0_DDR_Clk_n;
inout processing_system7_0_DDR_CKE;
inout processing_system7_0_DDR_CS_n;
inout processing_system7_0_DDR_RAS_n;
inout processing_system7_0_DDR_CAS_n;
output processing_system7_0_DDR_WEB_pin;
inout [2:0] processing_system7_0_DDR_BankAddr;
inout [14:0] processing_system7_0_DDR_Addr;
inout processing_system7_0_DDR_ODT;
inout processing_system7_0_DDR_DRSTB;
inout [31:0] processing_system7_0_DDR_DQ;
inout [3:0] processing_system7_0_DDR_DM;
inout [3:0] processing_system7_0_DDR_DQS;
inout [3:0] processing_system7_0_DDR_DQS_n;
inout processing_system7_0_DDR_VRN;
inout processing_system7_0_DDR_VRP;
output [7:0] coprocessor_0_LED_OUT_pin;
input [7:0] coprocessor_0_SW_IN_pin;
input [4:0] coprocessor_0_BTN_IN_pin;
(* BOX_TYPE = "user_black_box" *)
module_1
module_1_i (
.processing_system7_0_MIO ( processing_system7_0_MIO ),
.processing_system7_0_PS_SRSTB_pin ( processing_system7_0_PS_SRSTB_pin ),
.processing_system7_0_PS_CLK_pin ( processing_system7_0_PS_CLK_pin ),
.processing_system7_0_PS_PORB_pin ( processing_system7_0_PS_PORB_pin ),
.processing_system7_0_DDR_Clk ( processing_system7_0_DDR_Clk ),
.processing_system7_0_DDR_Clk_n ( processing_system7_0_DDR_Clk_n ),
.processing_system7_0_DDR_CKE ( processing_system7_0_DDR_CKE ),
.processing_system7_0_DDR_CS_n ( processing_system7_0_DDR_CS_n ),
.processing_system7_0_DDR_RAS_n ( processing_system7_0_DDR_RAS_n ),
.processing_system7_0_DDR_CAS_n ( processing_system7_0_DDR_CAS_n ),
.processing_system7_0_DDR_WEB_pin ( processing_system7_0_DDR_WEB_pin ),
.processing_system7_0_DDR_BankAddr ( processing_system7_0_DDR_BankAddr ),
.processing_system7_0_DDR_Addr ( processing_system7_0_DDR_Addr ),
.processing_system7_0_DDR_ODT ( processing_system7_0_DDR_ODT ),
.processing_system7_0_DDR_DRSTB ( processing_system7_0_DDR_DRSTB ),
.processing_system7_0_DDR_DQ ( processing_system7_0_DDR_DQ ),
.processing_system7_0_DDR_DM ( processing_system7_0_DDR_DM ),
.processing_system7_0_DDR_DQS ( processing_system7_0_DDR_DQS ),
.processing_system7_0_DDR_DQS_n ( processing_system7_0_DDR_DQS_n ),
.processing_system7_0_DDR_VRN ( processing_system7_0_DDR_VRN ),
.processing_system7_0_DDR_VRP ( processing_system7_0_DDR_VRP ),
.coprocessor_0_LED_OUT_pin ( coprocessor_0_LED_OUT_pin ),
.coprocessor_0_SW_IN_pin ( coprocessor_0_SW_IN_pin ),
.coprocessor_0_BTN_IN_pin ( coprocessor_0_BTN_IN_pin )
);
endmodule
module module_1
(
processing_system7_0_MIO,
processing_system7_0_PS_SRSTB_pin,
processing_system7_0_PS_CLK_pin,
processing_system7_0_PS_PORB_pin,
processing_system7_0_DDR_Clk,
processing_system7_0_DDR_Clk_n,
processing_system7_0_DDR_CKE,
processing_system7_0_DDR_CS_n,
processing_system7_0_DDR_RAS_n,
processing_system7_0_DDR_CAS_n,
processing_system7_0_DDR_WEB_pin,
processing_system7_0_DDR_BankAddr,
processing_system7_0_DDR_Addr,
processing_system7_0_DDR_ODT,
processing_system7_0_DDR_DRSTB,
processing_system7_0_DDR_DQ,
processing_system7_0_DDR_DM,
processing_system7_0_DDR_DQS,
processing_system7_0_DDR_DQS_n,
processing_system7_0_DDR_VRN,
processing_system7_0_DDR_VRP,
coprocessor_0_LED_OUT_pin,
coprocessor_0_SW_IN_pin,
coprocessor_0_BTN_IN_pin
);
inout [53:0] processing_system7_0_MIO;
input processing_system7_0_PS_SRSTB_pin;
input processing_system7_0_PS_CLK_pin;
input processing_system7_0_PS_PORB_pin;
inout processing_system7_0_DDR_Clk;
inout processing_system7_0_DDR_Clk_n;
inout processing_system7_0_DDR_CKE;
inout processing_system7_0_DDR_CS_n;
inout processing_system7_0_DDR_RAS_n;
inout processing_system7_0_DDR_CAS_n;
output processing_system7_0_DDR_WEB_pin;
inout [2:0] processing_system7_0_DDR_BankAddr;
inout [14:0] processing_system7_0_DDR_Addr;
inout processing_system7_0_DDR_ODT;
inout processing_system7_0_DDR_DRSTB;
inout [31:0] processing_system7_0_DDR_DQ;
inout [3:0] processing_system7_0_DDR_DM;
inout [3:0] processing_system7_0_DDR_DQS;
inout [3:0] processing_system7_0_DDR_DQS_n;
inout processing_system7_0_DDR_VRN;
inout processing_system7_0_DDR_VRP;
output [7:0] coprocessor_0_LED_OUT_pin;
input [7:0] coprocessor_0_SW_IN_pin;
input [4:0] coprocessor_0_BTN_IN_pin;
endmodule
|
#include <bits/stdc++.h> using namespace std; string s; int ans; map<int, int> f; int main() { cin >> s; int n = s.length(); f[0] = 1; int cur = 0; for (int i = 1; i < n; i++) { if (s[i] == s[i - 1]) { f[cur]++; } else { f[i]++; cur = i; } } while (f.size() > 1) { int _min = 10000000; for (auto i = f.begin(); i != f.end(); ++i) { if (i == f.begin() || next(i) == f.end()) cur = i->second; else cur = ceil(i->second / 2.0); _min = min(_min, cur); } ans += _min; for (auto i = f.begin(); i != f.end(); ++i) { cur = _min; auto ci = i; if (i == f.begin() || next(i) == f.end()) { i->second -= cur; } else { i->second -= cur + cur; } ci = i; } for (auto i = f.begin(); i != f.end();) { auto ci = i; ++i; if (ci->second < 1) f.erase(ci); } if (f.size()) for (auto it = f.begin(); it != prev(f.end());) { if (s[it->first] == s[next(it)->first]) { next(it)->second += it->second; auto cit = it; ++it; f.erase(cit); } else ++it; } } cout << ans; return 0; } |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 200MHz
* Reset: Push button, active high
*/
input wire clk_200mhz_p,
input wire clk_200mhz_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [3:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 500000 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// Clock and reset
wire clk_200mhz_ibufg;
// Internal 125 MHz clock
wire clk_mmcm_out;
wire clk_int;
wire clk90_mmcm_out;
wire clk90_int;
wire rst_int;
wire clk_200mhz_mmcm_out;
wire clk_200mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS
clk_200mhz_ibufgds_inst(
.I(clk_200mhz_p),
.IB(clk_200mhz_n),
.O(clk_200mhz_ibufg)
);
// MMCM instance
// 200 MHz in, 125 MHz out
// PFD range: 10 MHz to 500 MHz
// VCO range: 600 MHz to 1440 MHz
// M = 5, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
// Need two 125 MHz outputs with 90 degree offset
// Also need 200 MHz out for IODELAY
// 1000 / 5 = 200 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(8),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(90),
.CLKOUT2_DIVIDE(5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(5.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_200mhz_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(clk90_mmcm_out),
.CLKOUT1B(),
.CLKOUT2(clk_200mhz_mmcm_out),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
BUFG
clk90_bufg_inst (
.I(clk90_mmcm_out),
.O(clk90_int)
);
BUFG
clk_200mhz_bufg_inst (
.I(clk_200mhz_mmcm_out),
.O(clk_200mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [3:0] sw_int;
debounce_switch #(
.WIDTH(9),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
wire uart_rxd_int;
wire uart_cts_int;
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd, uart_cts}),
.out({uart_rxd_int, uart_cts_int})
);
// IODELAY elements for RGMII interface to PHY
wire [3:0] phy_rxd_delay;
wire phy_rx_ctl_delay;
IDELAYCTRL
idelayctrl_inst (
.REFCLK(clk_200mhz_int),
.RST(rst_int),
.RDY()
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_0 (
.IDATAIN(phy_rxd[0]),
.DATAOUT(phy_rxd_delay[0]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_1 (
.IDATAIN(phy_rxd[1]),
.DATAOUT(phy_rxd_delay[1]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_2 (
.IDATAIN(phy_rxd[2]),
.DATAOUT(phy_rxd_delay[2]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rxd_idelay_3 (
.IDATAIN(phy_rxd[3]),
.DATAOUT(phy_rxd_delay[3]),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
IDELAYE2 #(
.IDELAY_TYPE("FIXED")
)
phy_rx_ctl_idelay (
.IDATAIN(phy_rx_ctl),
.DATAOUT(phy_rx_ctl_delay),
.DATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.CINVCTRL(1'b0),
.CNTVALUEIN(5'd0),
.CNTVALUEOUT(),
.LD(1'b0),
.LDPIPEEN(1'b0),
.REGRST(1'b0)
);
fpga_core #(
.TARGET("XILINX")
)
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.clk90(clk90_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* Ethernet: 1000BASE-T RGMII
*/
.phy_rx_clk(phy_rx_clk),
.phy_rxd(phy_rxd_delay),
.phy_rx_ctl(phy_rx_ctl_delay),
.phy_tx_clk(phy_tx_clk),
.phy_txd(phy_txd),
.phy_tx_ctl(phy_tx_ctl),
.phy_reset_n(phy_reset_n),
.phy_int_n(phy_int_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd),
.uart_rts(uart_rts),
.uart_cts(uart_cts_int)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[4], i, j, s; int main() { for (i = 0; i < 4; i++) { scanf( %d , &a[i]); s += a[i]; } for (i = 0; i < 4; i++) { if (a[i] == s - a[i]) { puts( YES ); return 0; } for (j = i + 1; j < 4; j++) if (a[i] + a[j] == s - a[i] - a[j]) { puts( YES ); return 0; } } puts( NO ); return 0; } |
//
// Copyright (c) 2014 Jan Adelsbach <>.
// All Rights Reserved.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`include "nova_defs.v"
module nova_ram(pclk, prst, mm_adr, mm_we, mm_din, mm_dout);
parameter addr_width = 16;
parameter mem_size = 1 << addr_width;
parameter mem_mask = mem_size-1;
input pclk;
input prst;
input [0:15] mm_adr;
input mm_we;
input [0:15] mm_din;
output [0:15] mm_dout;
reg [0:15] m_mem[0:mem_size];
wire [0:addr_width-1] w_adr_masked;
integer i;
assign w_adr_masked = mm_adr[0:addr_width-1];
assign mm_dout = (~mm_we) ? m_mem[w_adr_masked] : 16'h0000;
always @(posedge pclk) begin
if(prst) begin
for(i = 0; i < mem_size; i = i + 1)
m_mem[i] = 16'h0000;
// #9 $readmemh("rdos.hex", m_mem);
// Interrupt test
m_mem[1] = 16'b0000_0000_0000_0100; // @4
// IORST
m_mem[2][0:2] = 3'b011;
m_mem[2][`NOVA_IO_TRANSFER] = `NOVA_IO_TRANSFER_DIC;
m_mem[2][`NOVA_IO_CONTROL] = `NOVA_IO_CONTROL_CLR;
m_mem[2][`NOVA_IO_DEVICE] = 6'o77;
// JMP 2
m_mem[3][`NOVA_LS_DISPLACE] = 8'h2;
// HALT
m_mem[4][0:2] = 3'b011;
m_mem[4][`NOVA_IO_TRANSFER] = `NOVA_IO_TRANSFER_DOC;
m_mem[4][`NOVA_IO_CONTROL] = `NOVA_IO_CONTROL_CLR;
m_mem[4][`NOVA_IO_DEVICE] = 6'o77;
end
else begin
if(mm_we) begin
// $display("M[%h] = %h", mm_adr, mm_din);
m_mem[w_adr_masked] <= mm_din;
end
end
end
endmodule // nova_ram
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DFSBP_BEHAVIORAL_PP_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSBP_BEHAVIORAL_PP_V |
//-----------------------------------------------------
// Design Name : pri_encoder_using_assign
// File Name : pri_encoder_using_assign.v
// Function : Pri Encoder using assign
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module pri_encoder_using_assign (
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable // Enable for the encoder
);
output [3:0] binary_out ;
input enable ;
input [15:0] encoder_in ;
wire [3:0] binary_out ;
assign binary_out = (!enable) ? 0 : (
(encoder_in == 16'bxxxx_xxxx_xxxx_xxx1) ? 0 :
(encoder_in == 16'bxxxx_xxxx_xxxx_xx10) ? 1 :
(encoder_in == 16'bxxxx_xxxx_xxxx_x100) ? 2 :
(encoder_in == 16'bxxxx_xxxx_xxxx_1000) ? 3 :
(encoder_in == 16'bxxxx_xxxx_xxx1_0000) ? 4 :
(encoder_in == 16'bxxxx_xxxx_xx10_0000) ? 5 :
(encoder_in == 16'bxxxx_xxxx_x100_0000) ? 6 :
(encoder_in == 16'bxxxx_xxxx_1000_0000) ? 7 :
(encoder_in == 16'bxxxx_xxx1_0000_0000) ? 8 :
(encoder_in == 16'bxxxx_xx10_0000_0000) ? 9 :
(encoder_in == 16'bxxxx_x100_0000_0000) ? 10 :
(encoder_in == 16'bxxxx_1000_0000_0000) ? 11 :
(encoder_in == 16'bxxx1_0000_0000_0000) ? 12 :
(encoder_in == 16'bxx10_0000_0000_0000) ? 13 :
(encoder_in == 16'bx100_0000_0000_0000) ? 14 : 15);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long N = 102, M = 200001; long long a[N], mem[M][N]; long long dp(long long n, long long k) { if (n < M && mem[n][k] != -1) return mem[n][k]; if (k == 0) return n; if (n == 0) return 0; if (n < M) return mem[n][k] = dp(n, k - 1) - dp(n / a[k], k - 1); else return dp(n, k - 1) - dp(n / a[k], k - 1); } int32_t main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); memset(mem, -1, sizeof mem); long long n, k; cin >> n >> k; for (long long i = 1; i <= k; i++) cin >> a[i]; sort(a + 1, a + k + 1); cout << dp(n, k); } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
logic use_AnB;
logic [1:0] active_command [8:0];
logic [1:0] command_A [8:0];
logic [1:0] command_B [8:0];
logic [1:0] active_command2 [8:0];
logic [1:0] command_A2 [8:0];
logic [1:0] command_B2 [8:0];
logic [1:0] active_command3 [1:0][2:0][3:0];
logic [1:0] command_A3 [1:0][2:0][3:0];
logic [1:0] command_B3 [1:0][2:0][3:0];
logic [2:0] use_A4nB4;
logic [8:0][1:0] active_command4;
logic [8:0][1:0] command_A4;
logic [8:0][1:0] command_B4;
logic [8:0] pipe1 [7:0];
logic [8:0] pipe1_input;
integer cyc;
assign active_command[8:0] = (use_AnB) ? command_A[8:0] : command_B[8:0];
assign active_command2 = (use_AnB) ? command_A2 : command_B2;
// Illegal to have [1:0][x:y] here - IEEE only allows single dimension slicing
assign active_command3[1:0] = (use_AnB) ? command_A3[1:0] : command_B3[1:0];
// Check we can cope with things other than packed arrays
assign active_command4 = (use_A4nB4[0]) ? command_A4 : command_B4;
always @ (posedge clk) begin
pipe1_input <= pipe1_input + 1;
pipe1[0] <= pipe1_input;
pipe1[7:1] <= pipe1[6:0];
end
logic [3:0][13:0] iq_read_data [15:0];
logic [3:0][13:0] iq_data;
logic [3:0] sel;
assign iq_data = iq_read_data[sel];
always @ (posedge clk) begin
sel = sel + 1;
end
initial begin
cyc = 0;
use_AnB = 0;
for (int i = 0; i < 7; ++i) begin
command_A[i] = 2'b00;
command_B[i] = 2'b11;
command_A2[i] = 2'b00;
command_B2[i] = 2'b11;
pipe1_input = 9'b0;
end
for (int i = 0; i < 2; ++i) begin
for (int j = 0; j < 3; ++j) begin
for (int k = 0; k < 4; ++k) begin
command_A3[i][j][k] = 2'b00;
command_B3[i][j][k] = 2'b11;
end
end
end
end
always @ (posedge clk) begin
use_AnB <= ~use_AnB;
cyc <= cyc + 1;
if (use_AnB) begin
if (active_command[3] != 2'b00) begin
$stop;
end
if (active_command2[3] != 2'b00) begin
$stop;
end
if (active_command3[0][1][2] != 2'b00) begin
$stop;
end
end
if (!use_AnB) begin
if (active_command[3] != 2'b11) begin
$stop;
end
if (active_command2[3] != 2'b11) begin
$stop;
end
end
end
logic [8:0] last_pipe;
always @(posedge clk) begin
if (cyc < 3) begin
last_pipe <= pipe1[0];
end
else begin
if (last_pipe + 1 != pipe1[0]) begin
$stop;
end
else begin
last_pipe <= pipe1[0];
end
end
if (cyc > 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule : t
|
#include <bits/stdc++.h> using namespace std; int main() { string a; cin >> a; int i, flag = 0; for (i = 1; i < a.size(); i++) { if (a[i] == 1 ) { flag = 1; break; } } i = (a.size()) / 2; if (flag == 1 && a.size() % 2 == 1) i++; cout << i; } |
#include <bits/stdc++.h> using namespace std; stack<int> S; int a[1005], n; bool judge() { for (int i = 0; i < n; i++) if (a[i] != i) return 0; return 1; } int main() { cin >> n; for (int i = 0; i < n; i++) scanf( %d , &a[i]); for (int i = 0; i <= n; i++) { if (judge()) { cout << Yes << endl; return 0; } for (int j = 0; j < n; j += 2) a[j] = (a[j] + 1) % n; for (int j = 1; j < n; j += 2) a[j] = (a[j] - 1 + n) % n; } cout << No << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; struct Edge { int u, v, w; }; const int N = 500005; int n, m, q; Edge edge[N]; vector<int> sorted_edge[N]; vector<pair<int, vector<int>>> query[N]; bool npos[N]; int par[N], rnk[N]; vector<int> rnk_roll, par_roll; void init() { for (int i = 1; i <= n; i++) par[i] = i, rnk[i] = 1; } int get(int u, bool roll = false) { if (u == par[u]) return u; if (roll) return get(par[u], roll); return par[u] = get(par[u], roll); } bool merge(int u, int v, bool roll = false) { u = get(u, roll), v = get(v, roll); if (u == v) return false; if (rnk[u] < rnk[v]) swap(u, v); if (roll) par_roll.push_back(v); par[v] = u; if (rnk[u] == rnk[v]) { rnk[u]++; rnk_roll.push_back(u); } return true; } void rollback() { for (auto u : rnk_roll) rnk[u]--; for (auto u : par_roll) par[u] = u; rnk_roll.clear(); par_roll.clear(); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d%d , &edge[i].u, &edge[i].v, &edge[i].w); sorted_edge[edge[i].w].push_back(i); } scanf( %d , &q); for (int i = 0, k; i < q; i++) { scanf( %d , &k); vector<int> elt(k); for (int i = 0; i < k; i++) scanf( %d , &elt[i]); sort(elt.begin(), elt.end(), [](int i, int j) { return edge[i].w < edge[j].w; }); int it = 0, j; do { vector<int> ei; for (j = it; j < k && edge[elt[j]].w == edge[elt[it]].w; j++) ei.push_back(elt[j]); query[edge[elt[it]].w].push_back({i, ei}); it = j; } while (it < k); } init(); for (int i = 1; i < N; i++) { for (auto qq : query[i]) { int qid = qq.first; for (auto e : qq.second) { if (!merge(edge[e].u, edge[e].v, true)) { npos[qid] = true; break; } } rollback(); } for (auto e : sorted_edge[i]) merge(edge[e].u, edge[e].v); } for (int i = 0; i < q; i++) { printf( %s n , npos[i] ? NO : YES ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, k; string s; vector<string> t; vector<pair<pair<int, int>, int> > cro; bool cmp(const pair<pair<int, int>, int> &x, const pair<pair<int, int>, int> &y) { if (x.second == y.second) { if (x.first.first == y.first.first) return x.first.second < y.first.second; return x.first.first < y.first.first; } return x.second < y.second; } int main() { cin >> n >> m >> k; for (int i = 0; i < (n); i++) { cin >> s; t.push_back(s); } for (int i = 0; i < (n); i++) { for (int j = 0; j < (m); j++) { if (t[i][j] == * ) { for (int r = (1); r <= (min(i, min(j, min(n - i - 1, m - j - 1)))); r++) { if ((t[i - r][j] == * ) && (t[i + r][j] == * ) && (t[i][j - r] == * ) && (t[i][j + r] == * )) cro.push_back(make_pair(make_pair(i, j), r)); } } } } if (cro.size() < k) cout << -1 n ; else { sort((cro).begin(), (cro).end(), cmp); cout << cro[k - 1].first.first + 1 << << cro[k - 1].first.second + 1 << n ; cout << cro[k - 1].first.first + 1 - cro[k - 1].second << << cro[k - 1].first.second + 1 << n ; cout << cro[k - 1].first.first + 1 + cro[k - 1].second << << cro[k - 1].first.second + 1 << n ; cout << cro[k - 1].first.first + 1 << << cro[k - 1].first.second + 1 - cro[k - 1].second << n ; cout << cro[k - 1].first.first + 1 << << cro[k - 1].first.second + 1 + cro[k - 1].second << n ; } return 0; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always disable block_identifier ;
module main ;
reg [3:0] value1 ;
always begin : block_id
#1 ;
$display("Hi there");
$finish ;
end
always disable block_id ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41AI_1_V
`define SKY130_FD_SC_LP__O41AI_1_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog wrapper for o41ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o41ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41ai_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o41ai_1 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o41ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41AI_1_V
|
`include "alink_define.v"
module rxc(
input clk ,
input rst ,
input reg_flush ,
input [31:0] reg_mask ,
input [31:0] reg_busy ,
input rx_almost_full ,
input tx_phy_start ,
input [31:0] tx_phy_sel ,
input task_id_vld ,
input [31:0] rx_phy_sel ,
input [31:0] task_id_h ,
input [31:0] task_id_l ,
input [`PHY_NUM*32-1:0] timer_cnt ,
output reg rx_vld ,
output reg [31:0] rx_dat ,
input [`PHY_NUM-1:0] RX_P ,
input [`PHY_NUM-1:0] RX_N
);
/*
>INPUT<
__
tx_phy_start _____| |_____________________________________
_____ __ _____________________________________
tx_phy_sel _____|0 |_________________dont care___________
__
tx_phy_done ________________________________________| |__
__
task_id_vld _________________| |_________________________
_________________ __ _________________________
[rx_phy_sel _________________|0_|_________________________
task_id_h
task_id_l]
>OUTPUT<
_____________________________________________
rx_vld __| |______________
__ _____________________________________________ ______________
rx_dat __|RXID |TaskID_H|TaskID_L|TIME |NONCE |______________
*/
wire [31:0] rx_start ;
wire [31:0] rx_last ;
wire [31:0] rx_vldx ;
wire [`PHY_NUM*32-1:0] rx_datx ;
reg [31:0] rx_sel ;
genvar i ;
generate
for(i=0;i<`PHY_NUM;i=i+1) begin : G
rx_phy #(.MY_RXID(i)) rx_phy(
/*input */ .clk (clk ) ,
/*input */ .rst (rst ) ,
/*input */ .reg_flush (reg_flush ) ,
/*input */ .reg_busy (reg_busy[i] ) ,
/*input */ .task_id_vld (task_id_vld&&rx_phy_sel[i] ) ,
/*input [31:0] */ .task_id_h (task_id_h ) ,
/*input [31:0] */ .task_id_l (task_id_l ) ,
/*input [31:0] */ .timer_cnt (timer_cnt[32*i+32-1:32*i] ) ,
/*output */ .rx_start (rx_start[i] ) ,
/*output */ .rx_last (rx_last[i] ) ,
/*output */ .rx_vld (rx_vldx[i] ) ,
/*output [31:0] */ .rx_dat (rx_datx[32*i+32-1:32*i] ) ,
/*input */ .RX_P (RX_P[i] ) ,
/*input */ .RX_N (RX_N[i] )
);
end
endgenerate
//--------------------------------------------
// RX.Select
//--------------------------------------------
always @ ( posedge clk ) begin
if( rst || reg_flush ) rx_sel <= 32'b0 ;
else if( |(rx_sel&rx_last) ) rx_sel <= 32'b0 ;//clear sel
else if( ~rx_almost_full && rx_start[0 ] ) rx_sel <= 32'b1<<0 ;
else if( ~rx_almost_full && rx_start[1 ] ) rx_sel <= 32'b1<<1 ;
else if( ~rx_almost_full && rx_start[2 ] ) rx_sel <= 32'b1<<2 ;
else if( ~rx_almost_full && rx_start[3 ] ) rx_sel <= 32'b1<<3 ;
else if( ~rx_almost_full && rx_start[4 ] ) rx_sel <= 32'b1<<4 ;
`ifdef PHY_10
else if( ~rx_almost_full && rx_start[5 ] ) rx_sel <= 32'b1<<5 ;
else if( ~rx_almost_full && rx_start[6 ] ) rx_sel <= 32'b1<<6 ;
else if( ~rx_almost_full && rx_start[7 ] ) rx_sel <= 32'b1<<7 ;
else if( ~rx_almost_full && rx_start[8 ] ) rx_sel <= 32'b1<<8 ;
else if( ~rx_almost_full && rx_start[9 ] ) rx_sel <= 32'b1<<9 ;
else if( ~rx_almost_full && rx_start[10] ) rx_sel <= 32'b1<<10 ;
else if( ~rx_almost_full && rx_start[11] ) rx_sel <= 32'b1<<11 ;
else if( ~rx_almost_full && rx_start[12] ) rx_sel <= 32'b1<<12 ;
else if( ~rx_almost_full && rx_start[13] ) rx_sel <= 32'b1<<13 ;
else if( ~rx_almost_full && rx_start[14] ) rx_sel <= 32'b1<<14 ;
else if( ~rx_almost_full && rx_start[15] ) rx_sel <= 32'b1<<15 ;
else if( ~rx_almost_full && rx_start[16] ) rx_sel <= 32'b1<<16 ;
else if( ~rx_almost_full && rx_start[17] ) rx_sel <= 32'b1<<17 ;
else if( ~rx_almost_full && rx_start[18] ) rx_sel <= 32'b1<<18 ;
else if( ~rx_almost_full && rx_start[19] ) rx_sel <= 32'b1<<19 ;
else if( ~rx_almost_full && rx_start[20] ) rx_sel <= 32'b1<<20 ;
else if( ~rx_almost_full && rx_start[21] ) rx_sel <= 32'b1<<21 ;
else if( ~rx_almost_full && rx_start[22] ) rx_sel <= 32'b1<<22 ;
else if( ~rx_almost_full && rx_start[23] ) rx_sel <= 32'b1<<23 ;
else if( ~rx_almost_full && rx_start[24] ) rx_sel <= 32'b1<<24 ;
else if( ~rx_almost_full && rx_start[25] ) rx_sel <= 32'b1<<25 ;
else if( ~rx_almost_full && rx_start[26] ) rx_sel <= 32'b1<<26 ;
else if( ~rx_almost_full && rx_start[27] ) rx_sel <= 32'b1<<27 ;
else if( ~rx_almost_full && rx_start[28] ) rx_sel <= 32'b1<<28 ;
else if( ~rx_almost_full && rx_start[29] ) rx_sel <= 32'b1<<29 ;
else if( ~rx_almost_full && rx_start[30] ) rx_sel <= 32'b1<<30 ;
else if( ~rx_almost_full && rx_start[31] ) rx_sel <= 32'b1<<31 ;
`endif
end
//--------------------------------------------
// RX.MUX
//--------------------------------------------
always @ ( posedge clk ) begin
if( rst )
rx_vld <= 1'b0 ;
else
rx_vld <= |rx_sel ;
rx_dat <= ({32{rx_sel[0 ]}} & rx_datx[32*1 -1:32*0 ])
| ({32{rx_sel[1 ]}} & rx_datx[32*2 -1:32*1 ])
| ({32{rx_sel[2 ]}} & rx_datx[32*3 -1:32*2 ])
| ({32{rx_sel[3 ]}} & rx_datx[32*4 -1:32*3 ])
| ({32{rx_sel[4 ]}} & rx_datx[32*5 -1:32*4 ])
`ifdef PHY_10
| ({32{rx_sel[5 ]}} & rx_datx[32*6 -1:32*5 ])
| ({32{rx_sel[6 ]}} & rx_datx[32*7 -1:32*6 ])
| ({32{rx_sel[7 ]}} & rx_datx[32*8 -1:32*7 ])
| ({32{rx_sel[8 ]}} & rx_datx[32*9 -1:32*8 ])
| ({32{rx_sel[9 ]}} & rx_datx[32*10-1:32*9 ])
| ({32{rx_sel[10]}} & rx_datx[32*11-1:32*10])
| ({32{rx_sel[11]}} & rx_datx[32*12-1:32*11])
| ({32{rx_sel[12]}} & rx_datx[32*13-1:32*12])
| ({32{rx_sel[13]}} & rx_datx[32*14-1:32*13])
| ({32{rx_sel[14]}} & rx_datx[32*15-1:32*14])
| ({32{rx_sel[15]}} & rx_datx[32*16-1:32*15])
| ({32{rx_sel[16]}} & rx_datx[32*17-1:32*16])
| ({32{rx_sel[17]}} & rx_datx[32*18-1:32*17])
| ({32{rx_sel[18]}} & rx_datx[32*19-1:32*18])
| ({32{rx_sel[19]}} & rx_datx[32*20-1:32*19])
| ({32{rx_sel[20]}} & rx_datx[32*21-1:32*20])
| ({32{rx_sel[21]}} & rx_datx[32*22-1:32*21])
| ({32{rx_sel[22]}} & rx_datx[32*23-1:32*22])
| ({32{rx_sel[23]}} & rx_datx[32*24-1:32*23])
| ({32{rx_sel[24]}} & rx_datx[32*25-1:32*24])
| ({32{rx_sel[25]}} & rx_datx[32*26-1:32*25])
| ({32{rx_sel[26]}} & rx_datx[32*27-1:32*26])
| ({32{rx_sel[27]}} & rx_datx[32*28-1:32*27])
| ({32{rx_sel[28]}} & rx_datx[32*29-1:32*28])
| ({32{rx_sel[29]}} & rx_datx[32*30-1:32*29])
| ({32{rx_sel[30]}} & rx_datx[32*31-1:32*30])
| ({32{rx_sel[31]}} & rx_datx[32*32-1:32*31])
`endif
;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; int const nmax = 1000; int const modulo = 1000000007; int dp[1 + nmax][1 + nmax]; int sum[1 + nmax][1 + nmax]; int main() { int n, m, cond; cin >> n >> m >> cond; if (m < n) { cout << 0; return 0; } dp[0][0] = 1; sum[0][0] = 1; for (int val = 1; val <= m; val++) { for (int i = 0; i <= n; i++) for (int j = 0; j <= i; j++) { dp[i][j] = 0; if (0 < i) dp[i][j] += sum[i - 1][j]; if (0 < j && val != cond) dp[i][j] += sum[i][j - 1]; if (modulo <= dp[i][j]) dp[i][j] -= modulo; if (0 < i && 0 < j) dp[i][j] += sum[i - 1][j - 1]; if (modulo <= dp[i][j]) dp[i][j] -= modulo; } if (val == cond) for (int i = 0; i <= n; i++) for (int j = 0; j <= n; j++) sum[i][j] = 0; for (int i = 0; i <= n; i++) for (int j = 0; j <= n; j++) { sum[i][j] += dp[i][j]; if (modulo <= sum[i][j]) sum[i][j] -= modulo; } } int result = sum[n][n]; for (int i = 1; i <= n; i++) result = 1LL * result * i % modulo; cout << result; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100010; bool vis[MAXN]; char str[MAXN]; int main() { gets(str); int len = strlen(str); char maxch = 0; memset(vis, false, sizeof(vis)); for (int i = len - 1; i >= 0; i--) { if (str[i] >= maxch) vis[i] = true; maxch = max(maxch, str[i]); } for (int i = 0; i < len; i++) { if (vis[i]) putchar(str[i]); } puts( ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_PS_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_DFF_PS_BLACKBOX_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dff$PS (
Q ,
D ,
CLK,
SET
);
output Q ;
input D ;
input CLK;
input SET;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_PS_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 3e5 + 100; long long n, x, y; int a[maxn]; vector<long long> v[maxn]; int vis[maxn]; int flag; void dfs(int u) { int i, j; vis[u] = 1; if (u == y) { flag = 1; return; } for (i = 0; i < v[u].size(); i++) { int k = v[u][i]; if (vis[k]) continue; vis[k] = 1; if (k == y) { flag = 1; return; } dfs(k); if (!flag) vis[k] = 0; else return; } } long long cnt = 0; void dfs2(int u) { int i, j; for (i = 0; i < v[u].size(); i++) { int k = v[u][i]; if (vis[k]) { continue; } vis[k] = 1; cnt++; dfs2(k); } } int main() { int i, j; cin >> n >> x >> y; for (i = 1; i <= n - 1; i++) { int l, r; cin >> l >> r; v[l].push_back(r); v[r].push_back(l); } if (n == 1) { cout << 0 << endl; return 0; } if (n == 2) { cout << 1 << endl; return 0; } dfs(x); long long ans = n * (n - 1); cnt = 0; dfs2(x); cnt++; long long x1 = cnt; cnt = 0; dfs2(y); cnt++; long long y1 = cnt; cout << ans - x1 * y1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { char c = getchar(); int x = 0, f = 1; for (; !isdigit(c); c = getchar()) if (c == - ) f = -1; for (; isdigit(c); c = getchar()) x = x * 10 + c - 0 ; return x * f; } const int MAXN = 1e5 + 5; int N, M, ans; int nxt[MAXN]; char s[MAXN], t[MAXN]; int main() { scanf( %s , s + 1); scanf( %s , t + 1); N = strlen(s + 1); M = strlen(t + 1); int j = 0; for (int i = 2; i <= M; i++) { while (j && t[i] != t[j + 1]) j = nxt[j]; if (t[i] == t[j + 1]) j++; nxt[i] = j; } int lst = 0; j = 0; for (int i = 1; i <= N; i++) { while (j && s[i] != t[j + 1]) j = nxt[j]; if (s[i] == t[j + 1]) j++; if (j == M) { if (i - M + 1 > lst) { if (lst) ans++; lst = i; } j = nxt[j]; } } if (lst) ans++; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 4; int n, m, a, b, ay[N], by[N], l[N], linkY[N << 1]; void read() { cin >> n >> m >> a >> b; for (int i = 1; i <= n; ++i) { cin >> ay[i]; } for (int i = 1; i <= m; ++i) { cin >> by[i]; } for (int i = 1; i <= m; ++i) { cin >> l[i]; } } long double dist = 1e18; int ida, idb, idTmp; long double sqr(long double x) { return x * x; } long double euc(long double xa, long double ya, long double xb, long double yb) { return sqrt(sqr(xa - xb) + sqr(ya - yb)); } long double f(int ni, int mi) { return euc(0, 0, a, ay[ni]) + euc(a, ay[ni], b, by[mi]); } long double ternarySearch(int num) { int l = 1, r = n; while (l + 2 < r) { int dm = (r - l) / 3; int m1 = l + dm; int m2 = r - dm; long double d1 = f(m1, num); long double d2 = f(m2, num); if (fabs(d1 - d2) < 1e-9) { l = m1; r = m2; } else if (d1 < d2) { r = m2; } else { l = m1; } } idTmp = l; for (int i = l + 1; i <= r; ++i) { if (f(i, num) < f(idTmp, num)) { idTmp = i; } } return f(idTmp, num); } void calc() { for (int i = 1; i <= m; ++i) { long double distTmp = ternarySearch(i) + l[i]; if (distTmp < dist) { dist = distTmp; ida = idTmp; idb = i; } } } void sovle() { read(); calc(); cout << ida << << idb; } int main() { ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(0); sovle(); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<int, int> > seg[2]; int n, m, k, x, y, dX, dY; bool flag = 0; long long ans; void add(int tx, int ty) { seg[0].push_back(pair<int, int>(tx - ty, tx)); seg[1].push_back(pair<int, int>(tx + ty, tx)); } void reflect() { int fc; if (dX == dY) fc = 0; else fc = 1; pair<int, int> p = (fc) ? pair<int, int>(x + y, x) : pair<int, int>(x - y, x); vector<pair<int, int> >::iterator it = upper_bound(seg[fc].begin(), seg[fc].end(), p); while (it->first != p.first) it--; if (dX < 0) while (it->second >= x) it--; ans += abs(x - it->second) - 1; x = it->second; y = (fc) ? (it->first - x) : (x - it->first); bool A = binary_search(seg[0].begin(), seg[0].end(), pair<int, int>(x - y - dX, x - dX)); bool B = binary_search(seg[0].begin(), seg[0].end(), pair<int, int>(x - y + dY, x)); if (A == B) flag = 1, dX = -dX, dY = -dY; else { if (A) x -= dX, dY = -dY; else if (B) y -= dY, dX = -dX; } } int main() { scanf( %d %d %d , &n, &m, &k); for (int i = 1; i <= m; i++) add(0, i), add(n + 1, i); for (int i = 0; i <= n + 1; i++) add(i, 0), add(i, m + 1); for (int i = 1; i <= k; i++) { scanf( %d %d , &x, &y); add(x, y); } scanf( %d %d , &x, &y); char c = getchar(); while (c != N && c != S && c != W && c != E ) c = getchar(); if (c == N ) dX = -1; else dX = 1; c = getchar(); if (c == W ) dY = -1; else dY = 1; sort(seg[0].begin(), seg[0].end()); sort(seg[1].begin(), seg[1].end()); reflect(); int sx = x, sy = y, sdx = dX, sdy = dY; ans = 0; do reflect(); while (!(x == sx && y == sy && dX == sdx && dY == sdy)); printf( %lld n , (flag) ? (ans >> 1) : ans); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD2_FUNCTIONAL_PP_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkdlyinv3sd2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD2_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 20500; int A[N]; int n; int B[N]; int get(int k) { if (n / k < 3) return -1e9; for (int i = 0; i < k; i++) B[i] = 0; for (int i = 0; i < n; i++) B[i % k] += A[i]; int ans = -1e9; for (int i = 0; i < k; i++) ans = max(ans, B[i]); return ans; } int main() { cin >> n; for (int i = 0; i < n; i++) cin >> A[i]; int ans = -1e9; for (int k = 1; k * k <= n; k++) if (n % k == 0) ans = max(ans, max(get(k), get(n / k))); cout << ans; return 0; } |
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <>
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
module esaxilite (/*AUTOARG*/
// Outputs
s_axicfg_arready, s_axicfg_awready, s_axicfg_bresp,
s_axicfg_bvalid, s_axicfg_rdata, s_axicfg_rresp, s_axicfg_rvalid,
s_axicfg_wready, mi_clk, mi_en, mi_we, mi_addr, mi_din,
// Inputs
s_axicfg_araddr, s_axicfg_arprot, s_axicfg_arvalid,
s_axicfg_awaddr, s_axicfg_awprot, s_axicfg_awvalid,
s_axicfg_bready, s_axicfg_rready, s_axicfg_wdata, s_axicfg_wstrb,
s_axicfg_wvalid, mi_rd_data
);
parameter RFAW = 16;
/*****************************/
/*AXI 32 bit lite interface */
/*****************************/
//read address channel
input [15:0] s_axicfg_araddr;
input [2:0] s_axicfg_arprot;
output s_axicfg_arready;
input s_axicfg_arvalid;
//write address channel
input [15:0] s_axicfg_awaddr;
input [2:0] s_axicfg_awprot;
output s_axicfg_awready;
input s_axicfg_awvalid;
//buffered read response channel
input s_axicfg_bready;
output [1:0] s_axicfg_bresp;
output s_axicfg_bvalid;
//read channel
output [31:0] s_axicfg_rdata;
input s_axicfg_rready;
output [1:0] s_axicfg_rresp;
output s_axicfg_rvalid;
//write channel
input [31:0] s_axicfg_wdata;
output s_axicfg_wready;
input [3:0] s_axicfg_wstrb;
input s_axicfg_wvalid;
/*****************************/
/*Simple memory interface */
/*****************************/
output mi_clk;
output mi_en;
output mi_we;
output [RFAW-1:0] mi_addr;
output [31:0] mi_din;
input [31:0] mi_rd_data;
//muxing done outside
endmodule // esaxilite
|
#include <bits/stdc++.h> using namespace std; long long read() { char ch = getchar(); long long f = 1, x = 0; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return f * x; } const long long MAXN = 2e5 + 10; long long n; long long a[MAXN]; long long gcd(long long x, long long y) { return y ? gcd(y, x % y) : x; } signed main() { long long t = read(); while (t--) { n = read(); for (long long i = 1; i <= n; i++) { a[i] = read(); } long long g = 0; for (long long i = 30; i >= 0; i--) { long long cnt = 0; for (long long j = 1; j <= n; j++) { if ((1 << i) & a[j]) { cnt++; } } if (cnt) { if (!g) { g = cnt; } else { g = gcd(g, cnt); } } } if (!g) { for (long long i = 1; i <= n; i++) { printf( %d , i); } puts( ); } else { for (long long i = 1; i * i < g; i++) { if (g % i == 0) { printf( %d , i); } } for (long long i = sqrt(g); i; i--) { if (g % i == 0) { printf( %d , g / i); } } puts( ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10, Mod = 1e9 + 7; int n, m, k, A[N], P[N]; map<int, int> M; long long tot; int main() { scanf( %d%d , &n, &k); m = (1 << k) - 1; for (int i = 1; i <= n; i++) scanf( %d , &A[i]), P[i] = P[i - 1] ^ A[i], M[min(P[i], m - P[i])]++; M[0]++; for (auto X : M) { int a = X.second >> 1; int b = X.second - a; tot += 1ll * a * (a - 1) / 2; tot += 1ll * b * (b - 1) / 2; } tot = 1ll * (n + 1) * n / 2 - tot; printf( %lld , tot); return (0); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BOI_2_V
`define SKY130_FD_SC_LS__A21BOI_2_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BOI_2_V
|
#include <bits/stdc++.h> using namespace std; pair<int, int> a[1010]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; ++i) { scanf( %d%d , &a[i].second, &a[i].first); if (a[i].first < a[i].second) swap(a[i].first, a[i].second); } sort(a, a + n); vector<int> ans; int last = INT_MIN; for (int i = 0; i < n; ++i) if (a[i].second > last) { ans.push_back(a[i].first); last = a[i].first; } printf( %d n , (int)ans.size()); for (int c : ans) printf( %d , c); printf( n ); } |
#include <bits/stdc++.h> using namespace std; int a[100005], f[100005]; int l[100005], r[100005]; int main() { int n; while (cin >> n) { memset(a, 0, sizeof(a)); memset(f, 0, sizeof(f)); for (int i = 0; i < n; i++) { cin >> a[i]; } int m; cin >> m; for (int i = 0; i < m; i++) { cin >> f[i]; } memset(l, 0, sizeof(l)); memset(r, 0, sizeof(r)); for (int i = 0; i < n; i++) { if (l[a[i]] == 0) { l[a[i]] = i; } } for (int i = n - 1; i >= 0; i--) { if (r[a[i]] == 0) { r[a[i]] = n - i; } } long long count1 = 0, count2 = 0; for (int i = 0; i < m; i++) { count1 = count1 + l[f[i]] + 1; } for (int i = 0; i < m; i++) { count2 = count2 + r[f[i]]; } cout << count1 << << count2 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<vector<int> > c(6, vector<int>(4, 0)); bool full[6]; bool polu[6]; int main() { ios_base::sync_with_stdio(0); cin.tie(nullptr); for (int i = 0; i < 6; ++i) { bool was[7] = {}; for (int j = 0; j < 4; ++j) { cin >> c[i][j]; was[c[i][j]] = 1; } int cnt = 0; for (int j = 1; j <= 6; ++j) cnt += was[j]; if (cnt == 1) full[i] = 1; if (cnt == 2) polu[i] = 1; } int cnt1 = 0, cnt2 = 0; for (int i = 0; i < 6; ++i) cnt1 += full[i], cnt2 += polu[i]; if (!(cnt1 == 2 && cnt2 == 4)) { cout << NO ; return 0; } if (full[0] && full[2]) { int path[5] = {3, 1, 4, 5, 3}; bool ok = true; for (int i = 0; i < 4; ++i) { if (!(c[path[i]][0] == c[path[i]][1] && c[path[i + 1]][2] == c[path[i + 1]][3] && c[path[i]][0] == c[path[i + 1]][2])) { ok = false; break; } } for (int i = 4; i > 0; --i) { if (!(c[path[i]][2] == c[path[i]][3] && c[path[i - 1]][0] == c[path[i - 1]][1] && c[path[i]][2] == c[path[i - 1]][0])) { ok = false; break; } } if (ok) { cout << YES ; return 0; } ok = true; for (int i = 0; i < 4; ++i) { if (!(c[path[i]][2] == c[path[i]][3] && c[path[i + 1]][0] == c[path[i + 1]][1] && c[path[i]][2] == c[path[i + 1]][0])) { ok = false; break; } } for (int i = 4; i > 0; --i) { if (!(c[path[i]][0] == c[path[i]][1] && c[path[i - 1]][2] == c[path[i - 1]][3] && c[path[i]][0] == c[path[i - 1]][2])) { ok = false; break; } } if (ok) { cout << YES ; return 0; } cout << NO ; } else if (full[3] && full[4]) { int path[5] = {0, 1, 2, 5, 0}; swap(c[5][0], c[5][1]); swap(c[5][2], c[5][3]); bool ok = true; for (int i = 0; i < 4; ++i) { if (!(c[path[i]][1] == c[path[i]][3] && c[path[i + 1]][0] == c[path[i + 1]][2] && c[path[i]][1] == c[path[i + 1]][0])) { ok = false; break; } } for (int i = 4; i > 0; --i) { if (!(c[path[i]][0] == c[path[i]][2] && c[path[i - 1]][1] == c[path[i - 1]][3] && c[path[i]][0] == c[path[i - 1]][1])) { ok = false; break; } } if (ok) { cout << YES ; return 0; } ok = true; for (int i = 0; i < 4; ++i) { if (!(c[path[i]][0] == c[path[i]][2] && c[path[i + 1]][1] == c[path[i + 1]][3] && c[path[i]][0] == c[path[i + 1]][1])) { ok = false; break; } } for (int i = 4; i > 0; --i) { if (!(c[path[i]][1] == c[path[i]][3] && c[path[i - 1]][0] == c[path[i - 1]][2] && c[path[i]][1] == c[path[i - 1]][0])) { ok = false; break; } } if (ok) { cout << YES ; return 0; } cout << NO ; } else if (full[1] && full[5]) { int path[5] = {0, 4, 2, 3, 0}; swap(c[4][1], c[4][2]); swap(c[2][0], c[2][3]); swap(c[2][1], c[2][2]); swap(c[3][0], c[3][3]); bool ok = true; for (int i = 0; i < 4; ++i) { if (i % 2 == 0) { if (!(c[path[i]][0] == c[path[i]][1] && c[path[i + 1]][0] == c[path[i + 1]][1] && c[path[i]][0] == c[path[i + 1]][0])) { ok = false; break; } } else { if (!(c[path[i]][2] == c[path[i]][3] && c[path[i + 1]][2] == c[path[i + 1]][3] && c[path[i]][2] == c[path[i + 1]][2])) { ok = false; break; } } } for (int i = 4; i > 0; --i) { if (i % 2 == 0) { if (!(c[path[i]][2] == c[path[i]][3] && c[path[i - 1]][2] == c[path[i - 1]][3] && c[path[i]][2] == c[path[i - 1]][2])) { ok = false; break; } } else { if (!(c[path[i]][0] == c[path[i]][1] && c[path[i - 1]][0] == c[path[i - 1]][1] && c[path[i]][0] == c[path[i - 1]][0])) { ok = false; break; } } } if (ok) { cout << YES ; return 0; } ok = true; for (int i = 0; i < 4; ++i) { if (i % 2 == 1) { if (!(c[path[i]][0] == c[path[i]][1] && c[path[i + 1]][0] == c[path[i + 1]][1] && c[path[i]][0] == c[path[i + 1]][0])) { ok = false; break; } } else { if (!(c[path[i]][2] == c[path[i]][3] && c[path[i + 1]][2] == c[path[i + 1]][3] && c[path[i]][2] == c[path[i + 1]][2])) { ok = false; break; } } } for (int i = 4; i > 0; --i) { if (i % 2 == 1) { if (!(c[path[i]][2] == c[path[i]][3] && c[path[i - 1]][2] == c[path[i - 1]][3] && c[path[i]][2] == c[path[i - 1]][2])) { ok = false; break; } } else { if (!(c[path[i]][0] == c[path[i]][1] && c[path[i - 1]][0] == c[path[i - 1]][1] && c[path[i]][0] == c[path[i - 1]][0])) { ok = false; break; } } } if (ok) { cout << YES ; return 0; } cout << NO ; } else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long cc = 1e9 + 7; map<int, int> A; map<int, int>::iterator itr, it; int main() { int n; cin >> n; for (int i = 0; i < n; i++) { string s; cin >> s; int nn = s.size(); vector<int> p; for (int j = 0; j < nn; j++) { int nnn = p.size(); if (p.size() == 0) { if (s[j] == ( ) p.push_back(1); else p.push_back(-1); } else { if (s[j] == ) ) { if (p[nnn - 1] == 1) p.pop_back(); else p.push_back(-1); } else { p.push_back(1); } } } int nnn = p.size(); if (nnn == 0) A[0]++; else if (p[0] == p[nnn - 1]) { A[(p[0] * nnn)]++; } } int sum = 0; for (itr = A.begin(); itr != A.end(); itr++) { if (itr->first == 0) { sum += (itr->second) / 2; } else { int yy = itr->first; it = A.find(0 - yy); if (it != A.end()) { sum += (min(itr->second, it->second)); it->second = 0; } } } cout << sum << endl; } |
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// mv_read O 32
// mav_write O 32
// CLK I 1 clock
// RST_N I 1 reset
// mav_write_misa I 28
// mav_write_wordxl I 32
// m_external_interrupt_req_req I 1 reg
// s_external_interrupt_req_req I 1 reg
// software_interrupt_req_req I 1 reg
// timer_interrupt_req_req I 1 reg
// EN_reset I 1
// EN_mav_write I 1
//
// Combinational paths from inputs to outputs:
// (mav_write_misa, mav_write_wordxl) -> mav_write
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkCSR_MIP(CLK,
RST_N,
EN_reset,
mv_read,
mav_write_misa,
mav_write_wordxl,
EN_mav_write,
mav_write,
m_external_interrupt_req_req,
s_external_interrupt_req_req,
software_interrupt_req_req,
timer_interrupt_req_req);
input CLK;
input RST_N;
// action method reset
input EN_reset;
// value method mv_read
output [31 : 0] mv_read;
// actionvalue method mav_write
input [27 : 0] mav_write_misa;
input [31 : 0] mav_write_wordxl;
input EN_mav_write;
output [31 : 0] mav_write;
// action method m_external_interrupt_req
input m_external_interrupt_req_req;
// action method s_external_interrupt_req
input s_external_interrupt_req_req;
// action method software_interrupt_req
input software_interrupt_req_req;
// action method timer_interrupt_req
input timer_interrupt_req_req;
// signals for module outputs
wire [31 : 0] mav_write, mv_read;
// register rg_meip
reg rg_meip;
wire rg_meip$D_IN, rg_meip$EN;
// register rg_msip
reg rg_msip;
wire rg_msip$D_IN, rg_msip$EN;
// register rg_mtip
reg rg_mtip;
wire rg_mtip$D_IN, rg_mtip$EN;
// register rg_seip
reg rg_seip;
wire rg_seip$D_IN, rg_seip$EN;
// register rg_ssip
reg rg_ssip;
wire rg_ssip$D_IN, rg_ssip$EN;
// register rg_stip
reg rg_stip;
wire rg_stip$D_IN, rg_stip$EN;
// register rg_ueip
reg rg_ueip;
wire rg_ueip$D_IN, rg_ueip$EN;
// register rg_usip
reg rg_usip;
wire rg_usip$D_IN, rg_usip$EN;
// register rg_utip
reg rg_utip;
wire rg_utip$D_IN, rg_utip$EN;
// rule scheduling signals
wire CAN_FIRE_m_external_interrupt_req,
CAN_FIRE_mav_write,
CAN_FIRE_reset,
CAN_FIRE_s_external_interrupt_req,
CAN_FIRE_software_interrupt_req,
CAN_FIRE_timer_interrupt_req,
WILL_FIRE_m_external_interrupt_req,
WILL_FIRE_mav_write,
WILL_FIRE_reset,
WILL_FIRE_s_external_interrupt_req,
WILL_FIRE_software_interrupt_req,
WILL_FIRE_timer_interrupt_req;
// remaining internal signals
wire [11 : 0] new_mip__h524, new_mip__h942;
wire seip__h558, ssip__h562, stip__h560, ueip__h559, usip__h563, utip__h561;
// action method reset
assign CAN_FIRE_reset = 1'd1 ;
assign WILL_FIRE_reset = EN_reset ;
// value method mv_read
assign mv_read = { 20'd0, new_mip__h524 } ;
// actionvalue method mav_write
assign mav_write = { 20'd0, new_mip__h942 } ;
assign CAN_FIRE_mav_write = 1'd1 ;
assign WILL_FIRE_mav_write = EN_mav_write ;
// action method m_external_interrupt_req
assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;
// action method s_external_interrupt_req
assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;
// action method software_interrupt_req
assign CAN_FIRE_software_interrupt_req = 1'd1 ;
assign WILL_FIRE_software_interrupt_req = 1'd1 ;
// action method timer_interrupt_req
assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
assign WILL_FIRE_timer_interrupt_req = 1'd1 ;
// register rg_meip
assign rg_meip$D_IN = m_external_interrupt_req_req ;
assign rg_meip$EN = 1'b1 ;
// register rg_msip
assign rg_msip$D_IN = software_interrupt_req_req ;
assign rg_msip$EN = 1'b1 ;
// register rg_mtip
assign rg_mtip$D_IN = timer_interrupt_req_req ;
assign rg_mtip$EN = 1'b1 ;
// register rg_seip
assign rg_seip$D_IN = s_external_interrupt_req_req ;
assign rg_seip$EN = 1'b1 ;
// register rg_ssip
assign rg_ssip$D_IN = !EN_reset && ssip__h562 ;
assign rg_ssip$EN = EN_mav_write || EN_reset ;
// register rg_stip
assign rg_stip$D_IN = !EN_reset && stip__h560 ;
assign rg_stip$EN = EN_mav_write || EN_reset ;
// register rg_ueip
assign rg_ueip$D_IN = !EN_reset && ueip__h559 ;
assign rg_ueip$EN = EN_mav_write || EN_reset ;
// register rg_usip
assign rg_usip$D_IN = !EN_reset && usip__h563 ;
assign rg_usip$EN = EN_mav_write || EN_reset ;
// register rg_utip
assign rg_utip$D_IN = !EN_reset && utip__h561 ;
assign rg_utip$EN = EN_mav_write || EN_reset ;
// remaining internal signals
assign new_mip__h524 =
{ rg_meip,
1'b0,
rg_seip,
rg_ueip,
rg_mtip,
1'b0,
rg_stip,
rg_utip,
rg_msip,
1'b0,
rg_ssip,
rg_usip } ;
assign new_mip__h942 =
{ rg_meip,
1'b0,
seip__h558,
ueip__h559,
rg_mtip,
1'b0,
stip__h560,
utip__h561,
rg_msip,
1'b0,
ssip__h562,
usip__h563 } ;
assign seip__h558 = mav_write_misa[18] && mav_write_wordxl[9] ;
assign ssip__h562 = mav_write_misa[18] && mav_write_wordxl[1] ;
assign stip__h560 = mav_write_misa[18] && mav_write_wordxl[5] ;
assign ueip__h559 = mav_write_misa[13] && mav_write_wordxl[8] ;
assign usip__h563 = mav_write_misa[13] && mav_write_wordxl[0] ;
assign utip__h561 = mav_write_misa[13] && mav_write_wordxl[4] ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_meip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_msip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_mtip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_seip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_ssip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_stip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_ueip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_usip <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_utip <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (rg_meip$EN) rg_meip <= `BSV_ASSIGNMENT_DELAY rg_meip$D_IN;
if (rg_msip$EN) rg_msip <= `BSV_ASSIGNMENT_DELAY rg_msip$D_IN;
if (rg_mtip$EN) rg_mtip <= `BSV_ASSIGNMENT_DELAY rg_mtip$D_IN;
if (rg_seip$EN) rg_seip <= `BSV_ASSIGNMENT_DELAY rg_seip$D_IN;
if (rg_ssip$EN) rg_ssip <= `BSV_ASSIGNMENT_DELAY rg_ssip$D_IN;
if (rg_stip$EN) rg_stip <= `BSV_ASSIGNMENT_DELAY rg_stip$D_IN;
if (rg_ueip$EN) rg_ueip <= `BSV_ASSIGNMENT_DELAY rg_ueip$D_IN;
if (rg_usip$EN) rg_usip <= `BSV_ASSIGNMENT_DELAY rg_usip$D_IN;
if (rg_utip$EN) rg_utip <= `BSV_ASSIGNMENT_DELAY rg_utip$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_meip = 1'h0;
rg_msip = 1'h0;
rg_mtip = 1'h0;
rg_seip = 1'h0;
rg_ssip = 1'h0;
rg_stip = 1'h0;
rg_ueip = 1'h0;
rg_usip = 1'h0;
rg_utip = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkCSR_MIP
|
#include <bits/stdc++.h> using namespace std; int main() { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; int ans; int a = abs(x1 - x2); int b = abs(y1 - y2); ans = max(a, b); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 16; signed main() { ios_base::sync_with_stdio(false); cin.tie(0); vector<int> ans(maxn, -1); ans[0] = 0; for (int i = 1; i < maxn; ++i) { for (auto j : vector<int>{4, 6, 9}) { if (i >= j && ans[i - j] != -1) { ans[i] = max(ans[i], ans[i - j] + 1); } } } int q; cin >> q; for (int i = 0; i < q; ++i) { int n; cin >> n; if (n < maxn) { cout << ans[n] << n ; } else { int t = (n - maxn) / 4 + 1; cout << t + ans[n - 4 * t] << n ; } } } |
#include <bits/stdc++.h> using namespace std; int P[111111]; int sz[111111]; int find(int x) { return (P[x] == x ? x : P[x] = find(P[x])); } void Union(int x, int y, int type) { x = find(x), y = find(y); if (sz[x] < sz[y]) swap(x, y); if (x == y) { if (type == -1) P[x] = 0; return; } if (type == -1) return; sz[x] += sz[y]; P[y] = x; } int main() { int N, K; cin >> N >> K; for (int i = 1; i <= N; i++) P[i] = i, sz[i] = 1; while (K--) { int u, v; cin >> u >> v; Union(u, v, 1); } cin >> K; while (K--) { int u, v; cin >> u >> v; Union(u, v, -1); } int best = 0; for (int i = 1; i <= N; i++) if (find(i)) best = max(best, sz[find(i)]); cout << best << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int test; cin >> test; while (test--) { int i, n, k; string s; cin >> n; cin >> s; vector<pair<string, int> > ans; for (i = 0; i < n; i++) { string sl = s.substr(0, i); string sr = s.substr(i, n - i); if (i % 2 != n % 2) reverse(sl.begin(), sl.end()); ans.push_back(make_pair(sr + sl, i + 1)); } sort(ans.begin(), ans.end()); cout << ans[0].first << endl << ans[0].second << endl; } } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bd_c3fe_slot_0_b_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat_v2_1_1_xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; struct point { long long x, y, index; point(long long x, long long y, long long index) : x(x), y(y), index(index) {} long long operator*(const point p) { return x * p.x + y * p.y; } long long operator^(const point p) { return x * p.y - y * p.x; } bool operator<(const point p) const { return make_pair(x, y) < make_pair(p.x, p.y); } bool operator==(const point p) const { return x == p.x && y == p.y; } bool operator!=(const point p) const { return !(*this == p); } point operator*(long long scale) { return point(scale * x, scale * y, index); } point operator+(const point p) { return point(x + p.x, y + p.y, index); } point operator-(const point p) { return point(x - p.x, y - p.y, index); } long long norm() { return (*this) * (*this); } }; bool half(point p) { assert(p.x != 0 || p.y != 0); return p.x > 0 || (p.x == 0 && p.y > 0); } void polarSort(point o, vector<point> &v, int L, int R) { sort(v.begin() + L, v.begin() + R, [&](point v, point w) { return make_tuple(half(v - o), 0, (v - o).norm()) < make_tuple(half(w - o), ((v - o) ^ (w - o)), (w - o).norm()); }); } const int N = 1515; int n; int Ans[N]; int Sub[N]; vector<point> pts; vector<int> Tree[N]; int DFS(int u, int p) { Sub[u] = 1; for (auto v : Tree[u]) if (v != p) Sub[u] += DFS(v, u); return Sub[u]; } void PaintTree(int u, int p, int L, int R) { int idx = L; for (int i = L; i <= R; i++) if (pts[idx].y < pts[i].y) idx = i; swap(pts[L], pts[idx]); Ans[pts[L].index] = u; polarSort(pts[L], pts, L + 1, R + 1); int pre = 0; for (auto v : Tree[u]) if (v != p) { PaintTree(v, u, L + pre + 1, L + pre + Sub[v]); pre += Sub[v]; } } int main() { scanf( %d , &n); for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); Tree[u].push_back(v); Tree[v].push_back(u); } for (int i = 0; i < n; i++) { int x, y; scanf( %d%d , &x, &y); pts.push_back(point(x, y, i + 1)); } DFS(1, 0); PaintTree(1, 0, 0, n - 1); for (int i = 1; i <= n; i++) printf( %d , Ans[i]); puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e5 + 10; int n; vector<int> g[MAXN]; int d[MAXN]; int bio[MAXN]; void dfs(int x, int dep) { d[x] = dep; bio[x] = 1; for (int i : g[x]) if (!bio[i]) dfs(i, dep + 1); } int main() { scanf( %d , &n); int a, b; for (int i = 0; i < n - 1; i++) { scanf( %d%d , &a, &b); a--; b--; g[a].push_back(b); g[b].push_back(a); } dfs(0, 1); double rj = 0; for (int i = 0; i < n; i++) { rj += 1.0 / d[i]; } printf( %lf n , rj); return 0; } |
module DelayCalculator(Clk_100MHz, rst, StartCounting, StopCounting, DelaySum, LastSlaveIDPlus1,
RegLoopDelay, AveTransDelay, AveLogicDelay, AveSlaveDelay);
input Clk_100MHz;
input rst;
input StartCounting;
input StopCounting;
input [15:0] DelaySum;
input [7:0] LastSlaveIDPlus1;
output [15:0] RegLoopDelay;
output [7:0] AveTransDelay;
output [7:0] AveLogicDelay;
output [7:0] AveSlaveDelay;
reg [31:0] Trans_mul;
reg [31:0] Logic_mul;
reg [15:0] LoopDelayCnt;
reg [15:0] RegLoopDelay;
reg [7:0] AveTransDelay;
reg [7:0] AveLogicDelay;
reg [7:0] AveSlaveDelay;
reg ResetLoopDelay_100MHzSync1;
reg ResetLoopDelay_100MHzSync2;
reg ResetLoopDelay_100MHzSync3;
reg StopLoopDelay_100MHzSync1;
reg StopLoopDelay_100MHzSync2;
reg StopLoopDelay_100MHzSync3;
wire [16:0] mul;
wire [8:0] shift;
wire [16:0] mul1;
wire [8:0] shift1;
wire ResetLoopDelay;
wire StopLoopDelay;
assign ResetLoopDelay = StartCounting; //.StartCounting(TxStateSoC), start counting after SoC, exclude SoC
assign StopLoopDelay = StopCounting; //.StopCounting(RxStateDelay[0]), stop counting after SoC, include SoC
//synchronized with 100 MHz clock
always @ (posedge Clk_100MHz or posedge rst)
begin
if(rst)
begin
ResetLoopDelay_100MHzSync1 <= 1'b0;
ResetLoopDelay_100MHzSync2 <= 1'b0;
ResetLoopDelay_100MHzSync3 <= 1'b0;
StopLoopDelay_100MHzSync1 <= 1'b0;
StopLoopDelay_100MHzSync2 <= 1'b0;
StopLoopDelay_100MHzSync3 <= 1'b0;
end
else
begin
ResetLoopDelay_100MHzSync1 <= ResetLoopDelay;
ResetLoopDelay_100MHzSync2 <= ResetLoopDelay_100MHzSync1;
ResetLoopDelay_100MHzSync3 <= ResetLoopDelay_100MHzSync2;
StopLoopDelay_100MHzSync1 <= StopLoopDelay;
StopLoopDelay_100MHzSync2 <= StopLoopDelay_100MHzSync1;
StopLoopDelay_100MHzSync3 <= StopLoopDelay_100MHzSync2;
end
end
// counting the loop delay
always @ (posedge Clk_100MHz or posedge rst)
begin
if(rst)
LoopDelayCnt <= 16'd0;
else
begin
if((~ResetLoopDelay_100MHzSync3) & ResetLoopDelay_100MHzSync2)
LoopDelayCnt <= 16'd0;
else
LoopDelayCnt <= LoopDelayCnt + 16'd1;
end
end
// register the loop delay
always @ (posedge Clk_100MHz or posedge rst)
begin
if(rst)
RegLoopDelay <= 16'd0;
else
begin
if((~StopLoopDelay_100MHzSync3) & (StopLoopDelay_100MHzSync2))
RegLoopDelay <= LoopDelayCnt ;
end
end
// calculate transmission delay/logic delay/Slave delay based on loop delay and logic delay sum
always @ (*)
begin
if( rst )
begin
AveTransDelay = 8'd0;
AveLogicDelay = 8'd0;
AveSlaveDelay = 8'd0;
Trans_mul = 32'd0;
Logic_mul = 32'd0;
end
else
begin
Trans_mul = (RegLoopDelay - DelaySum) * mul1;
AveTransDelay = Trans_mul >> shift1;
Logic_mul = DelaySum * mul;
AveLogicDelay = Logic_mul >> shift;
AveSlaveDelay = AveTransDelay + AveLogicDelay;
end
end
division_factor division_factor_ins
(
.div(LastSlaveIDPlus1),
.mul(mul),
.shift(shift)
);
division_factor division_factor_ins1
(
.div((LastSlaveIDPlus1 + 1'b1)),
.mul(mul1),
.shift(shift1)
);
endmodule |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:40:05 03/11/2015
// Design Name: Control_Unit
// Module Name: F:/ISE/work/cpu/cpu/Ctrl_Test.v
// Project Name: cpu
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Control_Unit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module Ctrl_Test;
// Inputs
reg clk;
reg [15:0] IR_in;
reg rst;
// Outputs
wire Load_NPC;
wire Load_PC;
wire Load_IR;
wire Load_RegA;
wire Load_RegB;
wire Load_Imm;
wire [3:0] WT_Reg;
wire [2:0] Extend;
wire [7:0] Send_Reg;
wire Load_LMD;
wire Cond_Kind;
wire [1:0] Jump_Kind;
wire Sel_Mux1;
wire Sel_Mux2;
wire [1:0] Sel_Mux4;
wire [4:0] Cal_ALU;
wire Write;
wire Load_ALU;
wire [2:0] state;
wire [5:0]cur_ins;
// Instantiate the Unit Under Test (UUT)
Control_Unit uut (
.Load_NPC(Load_NPC),
.Load_PC(Load_PC),
.Load_IR(Load_IR),
.Load_RegA(Load_RegA),
.Load_RegB(Load_RegB),
.Load_Imm(Load_Imm),
.WT_Reg(WT_Reg),
.Extend(Extend),
.Send_Reg(Send_Reg),
.Load_LMD(Load_LMD),
.Cond_Kind(Cond_Kind),
.Jump_Kind(Jump_Kind),
.Sel_Mux1(Sel_Mux1),
.Sel_Mux2(Sel_Mux2),
.Sel_Mux4(Sel_Mux4),
.Cal_ALU(Cal_ALU),
.Write(Write),
.Load_ALU(Load_ALU),
.clk(clk),
.IR_in(IR_in),
.rst(rst),
.state(state),
.cur_ins(cur_ins)
);
initial begin
// Initialize Inputs
clk = 0;
IR_in = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#100;
rst = 1;
IR_in = 16'b0110100100001000; // LI
//IR_in = 16'b0010000101010101; // BEQZ
//IR_in = 16'b1110000101110001; // ADDU
#500;
IR_in = 16'b0001000110011010; // B
// Add stimulus here
end
always begin
clk = 0;
#50;
clk = 1;
#50;
end
endmodule
|
#include <bits/stdc++.h> int main() { int n, o, i, k, m; scanf( %d%d , &n, &o); scanf( %d%d , &k, &m); int a[n], b[o]; for (i = 0; i < n; i++) scanf( %d , &a[i]); for (i = 0; i < o; i++) scanf( %d , &b[i]); if (a[k - 1] < b[o - m]) printf( YES ); else printf( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; char a[505][505]; long long int ans, mod; namespace tree { int edge[505][505]; long long int a[505][505]; inline void init() { memset(edge, 0, sizeof(edge)); } inline long long int qpow(long long int x, long long int y) { long long int ans = 1, base = x; while (y) { if (y & 1) ans = ans * base % mod; base = base * base % mod; y >>= 1; } return ans; } inline long long int solve(int n) { memset(a, 0, sizeof(a)); for (int i = 1; i <= n; ++i) for (int j = 1; j <= n; ++j) { (a[i][j] -= edge[i][j]) %= mod; (a[i][i] += edge[i][j]) %= mod; } long long int ans = 1; for (int i = 1; i < n; ++i) { int pos = i; while (pos < n && !a[pos][i]) ++pos; if (pos >= n) continue; if (pos != i) ans = mod - ans, swap(a[pos], a[i]); for (int j = i + 1; j < n; ++j) { long long int d = qpow(a[i][i], mod - 2) * a[j][i] % mod; for (int k = 1; k < n; ++k) a[j][k] = (a[j][k] - a[i][k] * d % mod) % mod; } } for (int i = 1; i < n; ++i) ans = ans * a[i][i] % mod; return (ans % mod + mod) % mod; } } // namespace tree struct UFO { int fa[123456]; inline void init() { for (int i = 0; i < 123456; ++i) fa[i] = i; } int find(int x) { return fa[x] == x ? x : fa[x] = find(fa[x]); } inline void merge(int x, int y) { fa[find(x)] = find(y); } } U; const int maxn = 1E6 + 5; inline void clear() { U.init(); } inline int num(int x, int y) { return x * (m + 1) + y + 1; } inline int c(int x) { if (m % 2 == 1) return (x + (x - 1) / (m + 1)) & 1; return x & 1; } int tot, bel[maxn]; inline void solve1() { clear(); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) if (a[i][j] == ) U.merge(num(i - 1, j - 1), num(i, j)); else if (a[i][j] == / ) U.merge(num(i - 1, j), num(i, j - 1)); for (int i = 1; i <= (n + 1) * (m + 1); ++i) if (c(i) == 0 && (!bel[U.find(i)])) bel[U.find(i)] = ++tot; for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) { if (a[i][j] != * ) continue; int u = num(i - 1, j - 1), v = num(i, j); if (c(num(i - 1, j - 1)) == 1) u = num(i, j - 1), v = num(i - 1, j); if (u > v) swap(u, v); u = bel[U.find(u)], v = bel[U.find(v)]; if (u == v) continue; ++tree::edge[u][v]; ++tree::edge[v][u]; } ans = (ans + tree::solve(tot)) % mod; } inline void solve2() { clear(); tree::init(); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) if (a[i][j] == ) U.merge(num(i - 1, j - 1), num(i, j)); else if (a[i][j] == / ) U.merge(num(i - 1, j), num(i, j - 1)); tot = 0; memset(bel, 0, sizeof(bel)); for (int i = 1; i <= (n + 1) * (m + 1); ++i) if (c(i) == 1 && (!bel[U.find(i)])) bel[U.find(i)] = ++tot; for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) { if (a[i][j] != * ) continue; int u = num(i - 1, j - 1), v = num(i, j); if (c(num(i - 1, j - 1)) == 0) u = num(i, j - 1), v = num(i - 1, j); if (u > v) swap(u, v); u = bel[U.find(u)], v = bel[U.find(v)]; if (u == v) continue; ++tree::edge[u][v]; ++tree::edge[v][u]; } ans = (ans + tree::solve(tot)) % mod; } int main() { ios::sync_with_stdio(false); cin >> n >> m >> mod; for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) cin >> a[i][j]; solve1(); solve2(); cout << ans << endl; return 0; } |
module ADT7310P32S32 (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output ADT7310CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output[7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="SPICounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPresetH_i,
(* intersynth_param="SPICounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPresetL_i,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_param="PeriodCounterPresetH_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_param="PeriodCounterPresetL_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
(* keep *)
wire SPIFSM_Start_s;
(* keep *)
wire SPIFSM_Done_s;
(* keep *)
wire [7:0] SPIFSM_Byte0_s;
(* keep *)
wire [7:0] SPIFSM_Byte1_s;
SPIFSM #(
.SPPRWidth (4),
.SPRWidth (4),
.DataWidth (8)
) SPIFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
// FSM control
.Start_i (SPIFSM_Start_s),
.Done_o (SPIFSM_Done_s),
.Byte0_o (SPIFSM_Byte0_s),
.Byte1_o (SPIFSM_Byte1_s),
// to/from SPI_Master
.SPI_Transmission_i (SPI_Transmission_i),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_Data_o (SPI_Data_o),
.SPI_Data_i (SPI_Data_i),
.SPI_FIFOFull_i (SPI_FIFOFull_i),
.SPI_FIFOEmpty_i (SPI_FIFOEmpty_i),
// to ADT7310
.ADT7310CS_n_o (ADT7310CS_n_o),
// parameters
.ParamCounterPreset_i({SPICounterPresetH_i, SPICounterPresetL_i})
);
SensorFSM #(
.DataWidth (8)
) SensorFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.Enable_i (Enable_i),
.CpuIntr_o (CpuIntr_o),
.SensorValue_o (SensorValue_o),
.MeasureFSM_Start_o (SPIFSM_Start_s),
.MeasureFSM_Done_i (SPIFSM_Done_s),
.MeasureFSM_Byte0_i (SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i (SPIFSM_Byte1_s),
// parameters
.ParamThreshold_i (Threshold_i),
.ParamCounterPreset_i({PeriodCounterPresetH_i, PeriodCounterPresetL_i})
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void rd(T &x) { char ch; x = 0; bool fl = false; while (!isdigit(ch = getchar())) (ch == - ) && (fl = true); for (x = (ch ^ 0 ); isdigit(ch = getchar()); x = x * 10 + (ch ^ 0 )) ; (fl == true) && (x = -x); } template <class T> inline void ot(T x) { x / 10 ? ot(x / 10) : putchar(x % 10 + 0 ); } template <class T> inline void prt(T a[], int st, int nd) { for (register int i = st; i <= nd; ++i) printf( %lld , a[i]); putchar( n ); } namespace Miracle { const int N = 1e5 + 10; const int mod = 1e9 + 7; int n; long long qm(long long x, long long y) { long long ret = 1; while (y) { if (y & 1) ret = ret * x % mod; x = x * x % mod; y >>= 1; } return ret; } long long jie[N], inv[N]; long long m25[N], i26[N]; int iv; int exi[N]; int ans[450][N]; int cnt; long long C(int n, int m) { if (n < 0 || m < 0 || n < m) return 0; return jie[n] * inv[m] % mod * inv[n - m] % mod; } char s[N]; int main() { jie[0] = 1; for (register int i = 1; i <= N - 5; ++i) jie[i] = jie[i - 1] * i % mod; inv[N - 5] = qm(jie[N - 5], mod - 2); for (register int i = N - 6; i >= 0; --i) inv[i] = inv[i + 1] * (i + 1) % mod; int m, t; iv = qm(26, mod - 2); m25[0] = 1, i26[0] = 1; for (register int i = 1; i <= N - 5; ++i) m25[i] = m25[i - 1] * 25 % mod, i26[i] = i26[i - 1] * iv % mod; rd(t); scanf( %s , s + 1); m = strlen(s + 1); int op; while (t--) { rd(op); if (op == 1) { scanf( %s , s + 1); m = strlen(s + 1); } else { rd(n); if (!exi[m]) { exi[m] = ++cnt; for (register int i = m; i <= N - 5; ++i) { ans[cnt][i] = ((long long)ans[cnt][i - 1] + C(i - 1, m - 1) * m25[i - m] % mod * i26[i] % mod) % mod; } } long long now = qm(26, n) * ans[exi[m]][n] % mod; printf( %lld n , now); } } return 0; } } // namespace Miracle signed main() { Miracle::main(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; vector<int> g(n), v(m), b(m); for (auto &i : g) cin >> i; for (auto &i : v) cin >> i; for (auto &i : b) cin >> i; int res = 0; vector<bool> news(n, false); vector<int> x(n, 1); for (int i = 1; i <= m; ++i) { int a = (v[i - 1] + res - 1) % n + 1; int rating = b[i - 1] >= n ? n : b[i - 1], ctr = 0, temp = a; if (!news[a - 1]) { news[a - 1] = 1; ctr++; } while (rating) { rating -= x[a - 1]; if (rating <= 0) break; temp = g[a - 1]; if (!news[temp - 1]) { news[temp - 1] = 1; ctr++; } x[a - 1] += x[temp - 1]; g[a - 1] = g[temp - 1]; a = temp; } res = ctr; cout << ctr << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BA_4_V
`define SKY130_FD_SC_LS__O21BA_4_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21ba_4 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BA_4_V
|
#include <bits/stdc++.h> using namespace std; int n; int main() { int s = 0, i; cin >> n; while (n != 0) { s = 0; for (i = 0;; ++i) { s += (1 << i); if (s >= n) break; } if (s == n) { cout << i + 1 << ; n -= (1 << i); } else { cout << i + 1 << ; n -= (1 << i); } } cout << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; struct Arc { int f, s, prev; } arr[400005]; Arc nbr[400005]; Arc br[400005]; int beg[400005]; int kol = 0; void add_arc(int f, int s) { arr[kol].f = f; arr[kol].s = s; arr[kol].prev = beg[f]; beg[f] = kol++; arr[kol].f = s; arr[kol].s = f; arr[kol].prev = beg[s]; beg[s] = kol++; } int pos[1 << 19]; int lev[1 << 19]; int llv[1 << 19]; int tin[1 << 19]; int tout[1 << 19]; int base[1 << 19]; int t = 0, ff = 0, q = 0; void DFS(int v, int p = -1) { tout[v] = tin[v] = ++t; for (int i = beg[v]; i != -1; i = arr[i].prev) { if (arr[i].s != p) { if (!tin[arr[i].s]) { DFS(arr[i].s, v); if (tout[arr[i].s] <= tin[v]) { tout[v] = min(tout[v], tout[arr[i].s]); nbr[ff++] = arr[i]; } else { br[q++] = arr[i]; } } else { tout[v] = min(tout[v], tout[arr[i].s]); } } } } void DFS2(int v, int lv = 0, int p = -1) { tin[v] = t; llv[v] = lv; lev[t] = lv; pos[t++] = v; for (int i = beg[v]; i != -1; i = arr[i].prev) { if (arr[i].s != p) { DFS2(arr[i].s, lv + 1, v); lev[t] = lv; pos[t++] = v; } } } int get_base(int v) { if (base[v] == v) { return v; } else { return base[v] = get_base(base[v]); } } void merge_base(int a, int b) { if (rand() & 1) { base[get_base(a)] = get_base(b); } else { base[get_base(b)] = get_base(a); } } void build_tree() { for (int i = (1 << 18) - 1; i; --i) { if (lev[i + i] < lev[i + i + 1]) { lev[i] = lev[i + i]; pos[i] = pos[i + i]; } else { lev[i] = lev[i + i + 1]; pos[i] = pos[i + i + 1]; } } } int get_min(int l, int r) { l = tin[l]; r = tin[r]; if (l > r) { swap(l, r); } ++r; int best = lev[l], bv = pos[l]; while (r - l > 1) { if (!(l & 1)) { if (lev[l + 1] < best) { best = lev[l + 1]; bv = pos[l + 1]; } } if (r & 1) { if (lev[r - 1] < best) { best = lev[r - 1]; bv = pos[r - 1]; } } l >>= 1; r >>= 1; } return bv; } int main() { memset(beg, -1, sizeof beg); int n, m, k; scanf( %d%d , &n, &m); for (int i = 0; i < m; ++i) { int f, s; scanf( %d%d , &f, &s); --f; --s; add_arc(f, s); } DFS(0); for (int i = 0; i < n; ++i) { base[i] = i; } for (int i = 0; i < ff; ++i) { merge_base(nbr[i].s, nbr[i].f); } memset(beg, -1, sizeof beg); memset(tin, -1, sizeof tin); for (int i = 0; i < q; ++i) { add_arc(get_base(br[i].f), get_base(br[i].s)); } t = 1 << 18; DFS2(get_base(0)); build_tree(); scanf( %d , &k); for (int i = 0; i < k; ++i) { int f, s; scanf( %d%d , &f, &s); --f; --s; f = get_base(f); s = get_base(s); int ret = llv[f] + llv[s] - 2 * llv[get_min(f, s)]; printf( %d n , ret); } return 0; } |
#include <bits/stdc++.h> int main() { int sum, n, i, t, p, sum1; char z[260]; scanf( %d , &n); getchar(); for (i = 0; i < n; i++) { scanf( %c , &z[i]); } getchar(); sum = 0; sum1 = 0; p = 0; t = 0; for (i = 0; i < n; i++) { if (z[i] >= a && z[i] <= z ) { sum++; if (sum >= t) t = sum; } if (z[i] >= A && z[i] <= Z ) { sum++; if (sum >= t) t = sum; } if (z[i] == _ ) { sum = 0; } if (z[i] == ( ) { sum = 0; i++; for (;; i++) { if (z[i] >= a && z[i] <= z ) { sum++; if (sum > p) p = sum; } if (z[i] >= A && z[i] <= Z ) { sum++; if (sum > p) p = sum; } if (z[i] == _ ) { p = sum; if (sum != 0) sum1++; sum = 0; } if (z[i] == ) ) { if (sum != 0) sum1++; sum = 0; break; } } } } printf( %d %d , t, sum1); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O2111AI_PP_BLACKBOX_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o2111ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); set<pair<int, int> > st; for (int i = 0; i < n; ++i) { int x; scanf( %d , &x); st.insert({x, i}); } int x = -1; vector<int> ans; while (x >= -1) { auto it = st.lower_bound({x + 1, -1}); if (it != st.end() and it->first == x + 1) { ans.emplace_back(it->second); st.erase(it); x++; } else { x -= 3; } } if (st.empty()) { cout << Possible n ; for (const int &x : ans) printf( %d , x + 1); } else { cout << Impossible n ; } } |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: one_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module one_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/one_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/one_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL one_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
Require Import Bag.
Require Import Proofs.
Require Import Proofs.Data.Foldable.
Require Import ListUtils.
Require Import Coq.Lists.List.
Import ListNotations.
Open Scope program_scope.
From Coq Require Import ssreflect ssrfun ssrbool.
Set Bullet Behavior "Strict Subproofs".
(* From Bag.hs:171-176, in the comments *)
Definition referenceFoldBag {r} {a} : (r -> r -> r) -> (a -> r) -> r -> Bag
a -> r :=
fix referenceFoldBag arg_27__ arg_28__ arg_29__ arg_30__
:= match arg_27__ , arg_28__ , arg_29__ , arg_30__ with
| t , u , e , Mk_EmptyBag => e
| t , u , e , (Mk_UnitBag x) => u x
| t , u , e , (Mk_TwoBags b1 b2) => t (referenceFoldBag t u e b1)
(referenceFoldBag t u e b2)
| t , u , e , (Mk_ListBag xs) => Coq.Lists.List.fold_right
(Coq.Program.Basics.compose t u) e xs
end.
(* Original:
foldBag t u e EmptyBag = e
foldBag t u e (UnitBag x) = u x
foldBag t u e (TwoBags b1 b2) = (foldBag t u e b1) `t` (foldBag t u e b2)
foldBag t u e (ListBag xs) = foldr (t.u) e xs
*)
(* This equivalence requires that `t` be associative, which is documented, but
also that `e` be the identity for `t`, which is *not*. `foldBag` is only
ever used twice in GHC, and in that case `e` is the identity, but there's a
documentation/definition disagreement. The ListBag case will always include
`e`, so for the real implementation and the reference implementation to
align, there must be a missing requirement that `e` be associative. But that
might be too strong of a requirement in the end! *)
Theorem referenceFoldBag_ok {A R} (f : R -> R -> R) (u : A -> R) (z : R) (b : Bag A) :
associative f -> right_id z f -> left_id z f ->
referenceFoldBag f u z b = fold_right f z (map u (bagToList b)).
Proof.
move=> f_assoc z_right_id z_left_id.
elim: b => [| x | l IHl r IHr | xs] //=.
- by rewrite bagToList_TwoBags IHl IHr -fold_right_fold_right // map_app fold_right_app.
- by rewrite bagToList_ListBag fold_right_map.
Qed.
Corollary foldBag_is_referenceFoldBag_if_id
{A R} (f : R -> R -> R) (u : A -> R) (z : R) (b : Bag A) :
associative f -> right_id z f -> left_id z f ->
foldBag f u z b = referenceFoldBag f u z b.
Proof.
move=> f_assoc z_right_id z_left_id.
rewrite foldBag_ok // referenceFoldBag_ok //.
Qed.
Corollary foldBag_isn't_referenceFoldBag_unless_id
{R} (f : R -> R -> R) (z : R) :
associative f ->
(exists x, f x z <> x) \/ (exists x, f z x <> x) ->
exists {A} (u : A -> R) (b : Bag A),
foldBag f u z b <> referenceFoldBag f u z b.
Proof.
move=> f_assoc [[a z_not_right_id] | [a z_not_left_id]].
- by exists unit, (fun _ => a), (Mk_UnitBag tt).
- admit.
(* Can we really prove this case? Do we really need left_id in
referenceFoldBag_ok, or is that an accident of our proof? *)
Abort.
Module BagNeedsUnit.
Definition pure {A} (x : A) : list A := [x].
Lemma same_empty_list' {A} (tail : list A) (b : Bag A) :
foldBag app pure tail b = referenceFoldBag app pure [] b ++ tail.
Proof.
elim: b tail => [| x | l IHl r IHr | xs] //= tail.
- by rewrite IHr IHl app_assoc.
- by rewrite
/Data.Foldable.foldr /Foldable.Foldable__list /Data.Foldable.foldr__
hs_coq_foldr_list' fold_right_cons fold_right_cons_nil.
Qed.
Lemma same_empty_list {A} (b : Bag A) :
foldBag app pure [] b = referenceFoldBag app pure [] b.
Proof. by rewrite same_empty_list' app_nil_r. Qed.
Theorem counterexample {A} (x : A) (xs : list A) :
exists b,
well_formed_bag b /\
foldBag app pure (x :: xs) b <> referenceFoldBag app pure (x :: xs) b.
Proof. by exists (Mk_UnitBag x). Qed.
End BagNeedsUnit.
|
#include <bits/stdc++.h> using namespace std; int ans, t, p, q, i, j, n, m, k, l, r, br1, br0; bool b[36][36]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); cin >> t; while (t--) { cin >> n >> m; ans = 0; vector<pair<int, int> > v; for (i = 1; i <= n; i++) { for (j = 1; j <= m; j++) { cin >> b[i][j]; } } for (i = 1; i <= m; i++) { p = 1; q = i; br1 = br0 = 0; while (p <= n && q > 0) { if (b[p][q] == 1) br1++; else br0++; p++; q--; } v.push_back({br0, br1}); } for (i = 2; i <= n; i++) { p = i; q = m; br1 = br0 = 0; while (p <= n && q > 0) { if (b[p][q] == 1) br1++; else br0++; p++; q--; } v.push_back({br0, br1}); } for (i = 0; i < v.size() / 2; i++) { pair<int, int> pr = v[i]; pair<int, int> pr1 = v[v.size() - i - 1]; ans += min(pr.first + pr1.first, pr.second + pr1.second); } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long a[100000]; int main() { long long n; long long cnt = 0; scanf( %I64d , &n); for (long long i = 0; i < n; i++) { scanf( %I64d , &a[i]); for (long long j = 0; j < i; j++) if (a[j] > a[i]) cnt++; } cout << (cnt % 2 + (cnt / 2) * 4) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; char buffer[1048576]; int main() { scanf( %s , buffer); string dat(buffer); int n = dat.length(); int Q; scanf( %d , &Q); int lgstep = 1; while ((1 << lgstep) <= n) lgstep++; while (Q--) { int k, d; scanf( %d%d , &k, &d); vector<int> invpi(k); { int lastval = 0; int grp = 0; for (int i = 1; i < k; i++) { lastval += d; if (lastval >= k) { grp++; lastval = grp; } invpi[i] = lastval; } } vector<int> from(k); vector<vector<int>> logfrom(lgstep, vector<int>(k)); for (int i = 0; i < k; i++) { from[i] = invpi[i] + 1; logfrom[0][i] = from[i]; } for (int i = 1; i < lgstep; i++) { for (int j = 0; j < k; j++) { int p = logfrom[i - 1][j]; int p2 = (p != k) ? logfrom[i - 1][p] : (k); logfrom[i][j] = p2; } } string answer(n, 0); for (int i = 0; i < n; i++) { int base = min(i, n - k); int fpos = i - base; int tracepos = fpos; int steps = 0; { int remain = base + 1; for (int l = lgstep - 1; l >= 0; l--) { if (remain >= (1 << l)) { if (logfrom[l][tracepos] != k) { remain -= (1 << l); steps += (1 << l); tracepos = logfrom[l][tracepos]; } } } if (remain) { tracepos = logfrom[0][tracepos]; remain--; steps++; } } answer[i] = dat[base + tracepos - steps]; } dat = move(answer); puts(dat.c_str()); } return 0; } |
//#############################################################################
//# Function: Dual data rate output buffer #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_oddr #(parameter DW = 1) // width of data inputs
(
input clk, // clock input
input [DW-1:0] din1, // data input1
input [DW-1:0] din2, // data input2
output [DW-1:0] out // ddr output
);
//regs("sl"=stable low, "sh"=stable high)
reg [DW-1:0] q1_sl;
reg [DW-1:0] q2_sl;
reg [DW-1:0] q2_sh;
//Generate different logic based on parameters
always @ (posedge clk)
begin
q1_sl[DW-1:0] <= din1[DW-1:0];
q2_sl[DW-1:0] <= din2[DW-1:0];
end
always @ (negedge clk)
q2_sh[DW-1:0] <= q2_sl[DW-1:0];
assign out[DW-1:0] = clk ? q1_sl[DW-1:0] :
q2_sh[DW-1:0];
endmodule // oh_oddr
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; int dp[N][3][2]; string a; int n; int solve(int x, int state, int start) { if (x >= n) return 0; if (dp[x][state][start] != -1) return dp[x][state][start]; int res = 0; if (state == 0) { if (start == a[x]) res = max(solve(x + 1, 0, 1 - start) + 1, solve(x + 1, 1, start)); else res = max(solve(x + 1, 1, 1 - start) + 1, solve(x + 1, 0, start)); } if (state == 1) { if (start == a[x]) res = max(solve(x + 1, 2, 1 - start) + 1, solve(x + 1, 1, start)); else res = max(solve(x + 1, 2, start), solve(x + 1, 1, 1 - start) + 1); } if (state == 2) { if (start == a[x]) res = solve(x + 1, 2, 1 - start) + 1; else res = solve(x + 1, 2, start); } dp[x][state][start] = res; return res; } int main() { std::ios::sync_with_stdio(false); ; cin >> n; memset((dp), (-1), sizeof(dp)); cin >> a; for (int i = 0; i < n; i++) a[i] -= 0 ; cout << solve(0, 0, a[0]) << n ; return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Thu Oct 26 22:45:02 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_prog_rom_0_0/RAT_prog_rom_0_0_stub.v
// Design : RAT_prog_rom_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "prog_rom,Vivado 2016.4" *)
module RAT_prog_rom_0_0(ADDRESS, INSTRUCTION, CLK)
/* synthesis syn_black_box black_box_pad_pin="ADDRESS[9:0],INSTRUCTION[17:0],CLK" */;
input [9:0]ADDRESS;
output [17:0]INSTRUCTION;
input CLK;
endmodule
|
// ctr_encoder.v
// cal-trg-res encoder
`timescale 1 ns / 1 ps
module ctr_encoder
(
input clk,
input sync,
input reset,
input cal, // send calibrate
input trg, // send trigger (maskable by trg_veto)
input res_roc, // send ROC reset (maskable by res_veto)
input res_tbm, // send TBM reset (maskable by res_veto)
input res_req, // ROC reset request (delayed if res_veto)
input nmr_req, // ROC reset request (not delayed if res_veto)
input trg_veto, // trigger veto
input res_veto, // ROC/TBM reset veto
output running,
output ctr_out,
output trg_out,
output res_out
);
// maskable reset request SRFF
reg res_req_ff;
always @(posedge clk or posedge reset)
begin
if (reset) res_req_ff <= 0;
else if (sync)
begin
if (res_req) res_req_ff <= 1;
else if (res_out) res_req_ff <= 0;
end
end
// non maskable reset request SRFF
reg nmr_req_ff;
always @(posedge clk or posedge reset)
begin
if (reset) nmr_req_ff <= 0;
else if (sync)
begin
if (nmr_req) nmr_req_ff <= 1;
else if (res_out) nmr_req_ff <= 0;
end
end
wire res = nmr_req_ff || ((res_roc || res_req_ff) && !res_veto);
wire rtbm = res_tbm && !res_veto;
wire trig = trg & !trg_veto;
// state machine
reg [6:0]ctrgen;
localparam SM_IDLE = 7'b000_0000;
localparam SM_CAL1 = 7'b000_1001;
localparam SM_CAL2 = 7'b000_0001;
localparam SM_CAL3 = 7'b001_0001;
localparam SM_TRG1 = 7'b000_1101;
localparam SM_TRG2 = 7'b001_1001;
localparam SM_TRG3 = 7'b010_0001;
localparam SM_RES1 = 7'b000_1011;
localparam SM_RES2 = 7'b010_1001;
localparam SM_RES3 = 7'b011_1001;
localparam SM_TBM1 = 7'b001_1011;
localparam SM_TBM2 = 7'b011_0001;
localparam SM_TBM3 = 7'b100_1001;
assign {ctr_out, trg_out, res_out, running} = ctrgen[3:0];
always @(posedge clk or posedge reset)
begin
if (reset) ctrgen <= SM_IDLE;
else if (sync)
casex ({ctrgen, res, rtbm, trig, cal})
// start (priority decoding)
{SM_IDLE, 1'b1, 1'bx, 1'bx, 1'bx}: ctrgen <= SM_RES1;
{SM_IDLE, 1'b0, 1'b1, 1'bx, 1'bx}: ctrgen <= SM_TBM1;
{SM_IDLE, 1'b0, 1'b0, 1'b1, 1'bx}: ctrgen <= SM_TRG1;
{SM_IDLE, 1'b0, 1'b0, 1'b0, 1'b1}: ctrgen <= SM_CAL1;
// process calibrate
{SM_CAL1, 1'bx, 1'bx, 1'bx, 1'bx}: ctrgen <= SM_CAL2;
{SM_CAL2, 1'bx, 1'bx, 1'bx, 1'bx}: ctrgen <= SM_CAL3;
{SM_CAL3, 1'bx, 1'bx, 1'bx, 1'bx}: ctrgen <= SM_IDLE;
// process trigger
{SM_TRG1, 1'bx, 1'bx, 1'bx, 1'bx}: ctrgen <= SM_TRG2;
{SM_TRG2, 1'bx, 1'bx, 1'bx, 1'bx}: ctrgen <= SM_TRG3;
{SM_TRG3, 1'bx, 1'bx, 1'bx, 1'bx}: ctrgen <= SM_IDLE;
// process ROC reset
{SM_RES1, 1'bx, 1'bx, 1'bx, 1'bx}: ctrgen <= SM_RES2;
{SM_RES2, 1'bx, 1'bx, 1'bx, 1'bx}: ctrgen <= SM_RES3;
{SM_RES3, 1'bx, 1'bx, 1'bx, 1'bx}: ctrgen <= SM_IDLE;
// process TBM reset
{SM_TBM1, 1'bx, 1'bx, 1'bx, 1'bx}: ctrgen <= SM_TBM2;
{SM_TBM2, 1'bx, 1'bx, 1'bx, 1'bx}: ctrgen <= SM_TBM3;
{SM_TBM3, 1'bx, 1'bx, 1'bx, 1'bx}: ctrgen <= SM_IDLE;
endcase
end
endmodule
|
/*
* Copyright (c) 2011-2012 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
`include "defines.v"
module alu(
input [3:0] op,
input [31:0] a,
input [31:0] b,
output reg [31:0] res
);
always @(op or a or b)
begin
case (op)
`ALU_OP_ADD: res = a + b;
`ALU_OP_SUB: res = a - b;
`ALU_OP_AND: res = a & b;
`ALU_OP_OR: res = a | b;
`ALU_OP_XOR: res = a ^ b;
`ALU_OP_LSL: res = a << b;
`ALU_OP_LSR: res = a >> b;
`ALU_OP_ASR: res = $signed(a) >>> b;
`ALU_OP_MVB: res = { a[31:16], b[15:0] };
`ALU_OP_MVT: res = a | (b << 16);
`ALU_OP_SEQ: res = { 31'd0 , a == b};
`ALU_OP_SLT: res = { 31'd0, a < b};
`ALU_OP_SLTE: res = { 31'd0, a <= b};
default: res = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
endcase
end
endmodule
|
// simulate together CPU, DRAM and VIDEO FETCH
`include "../include/tune.v"
module tb_cdv;
reg rst_n;
reg clk;
wire zclk,zclk_out;
wire mreq_n,iorq_n,rd_n,wrbad_n,m1_n,rfsh_n;
reg wr_n;
tri [7:0] zdata;
wire [15:0] zaddr;
wire [7:0] ramout;
wire ram_ena;
wire [4:0] rompg;
wire romoe_n,romwe_n,csrom;
wire [7:0] romdata;
wire cbeg,pre_cend,cend;
wire cpu_req,cpu_rnw,cpu_wrbsel,cpu_strobe;
wire [20:0] cpu_addr;
wire [7:0] cpu_wrdata;
wire [15:0] cpu_rddata;
wire cpu_stall;
wire [4:0] cpu_waitcyc;
wire video_strobe,video_next;
wire [15:0] video_data;
wire [20:0] video_addr;
wire go;
wire [1:0] bw;
wire [20:0] daddr;
wire dreq,drnw,drrdy;
wire [1:0] dbsel;
wire [15:0] drddata;
wire [15:0] dwrdata;
wire [9:0] ra;
tri [15:0] rd;
wire rwe_n,rucas_n,rlcas_n,rras0_n,rras1_n;
wire hsync,hblank,hpix,hsync_start,line_start;
wire vblank,vsync,vpix,int_start;
wire [5:0] pixel;
initial
begin
clk = 1'b0;
forever #17 clk = ~clk;
end
integer rst_count;
initial
begin
rst_n <= 1'b0;
for(rst_count=0;rst_count<=32;rst_count=rst_count+1) @(posedge clk);
rst_n <= 1'b1;
end
// for simulation
integer i;
initial
begin
for(i=0;i<32768;i=i+1)
begin
chip0.array[i] = 16'd0;
chip1.array[i] = 16'd0;
end
for(i=16'h000;i<16'h1b00;i=i+2)
begin
// zxmemwrite(5,i,i+16'h4000); // this particular thing is to check zx-mode addressing
zxmemwrite(4,i,i);
zxmemwrite(5,i,i+16'h4000);
zxmemwrite(4,i+16'h2000,i+16'h2000);
zxmemwrite(5,i+16'h2000,i+16'h6000);
end
end
task zxmemwrite; // writes a word given zx page and page offset (must be even)
input [2:0] page;
input [13:0] offset;
input [15:0] data;
reg [14:0] wordaddr;
begin
wordaddr = { page[2:0], offset[13:2] };
if( !offset[1] )
chip0.array[wordaddr] = data;
else
chip1.array[wordaddr] = data;
end
endtask
// route data to the Z80 bus
assign zdata = ram_ena ? ramout : 8'hZZ;
assign zdata = romdata;
T80a z80( .RESET_n(/*rst_n*/1'b0),
.CLK_n(zclk),
.WAIT_n(1'b1),
.INT_n(1'b1),
.NMI_n(1'b1),
.M1_n(m1_n),
.RFSH_n(rfsh_n),
.MREQ_n(mreq_n),
.IORQ_n(iorq_n),
.RD_n(rd_n),
.WR_n(wrbad_n),
.BUSRQ_n(1'b1),
.A(zaddr),
.D(zdata) );
//correct wr_n (valid only for MEMORY operations!)
always @(negedge zclk)
wr_n <= wrbad_n;
zclock z80clock( .rst_n(rst_n),
.fclk(clk),
.zclk_out(zclk_out),
.zclk(zclk),
.turbo(2'b01),
.pre_cend(pre_cend) );
assign zclk = ~zclk_out; // inversion in the schematics!
zmem z80memory( .rst_n(rst_n),
.fclk(clk),
.zpos(1'b1),
.zneg(1'b0),
.cend(cend),
.pre_cend(pre_cend),
.za(zaddr),
.zd_in(zdata),
.zd_out(ramout),
.zd_ena(ram_ena),
.m1_n(m1_n),
.rfsh_n(rfsh_n),
.mreq_n(mreq_n),
.iorq_n(iorq_n),
.rd_n(rd_n),
.wr_n(wr_n),
.win0_romnram(1'b1),
.win1_romnram(1'b0),
.win2_romnram(1'b0),
.win3_romnram(1'b0),
.win0_page(8'd0),
.win1_page(8'd1),
.win2_page(8'd2),
.win3_page(8'd3),
.dos(1'b0),
.rompg(rompg),
.romoe_n(romoe_n),
.romwe_n(romwe_n),
.csrom(csrom),
.cpu_req(cpu_req),
.cpu_rnw(cpu_rnw),
.cpu_wrbsel(cpu_wrbsel),
.cpu_strobe(cpu_strobe),
.cpu_addr(cpu_addr),
.cpu_wrdata(cpu_wrdata),
.cpu_rddata(cpu_rddata) );
arbiter dramarb( .clk(clk),
.rst_n(rst_n),
.dram_addr(daddr),
.dram_req(dreq),
.dram_rnw(drnw),
.dram_cbeg(cbeg),
.dram_rrdy(drrdy),
.dram_bsel(dbsel),
.dram_rddata(drddata),
.dram_wrdata(dwrdata),
.cend(cend),
.pre_cend(pre_cend),
.go(go),
.bw(bw),
.video_addr(video_addr),
.video_data(video_data),
.video_strobe(video_strobe),
.video_next(video_next),
.cpu_waitcyc(cpu_waitcyc),
.cpu_stall(cpu_stall),
.cpu_req(cpu_req),
.cpu_rnw(cpu_rnw),
.cpu_addr(cpu_addr),
.cpu_wrbsel(cpu_wrbsel),
.cpu_wrdata(cpu_wrdata),
.cpu_rddata(cpu_rddata),
.cpu_strobe(cpu_strobe) );
dram dramko( .clk(clk),
.rst_n(rst_n),
.addr(daddr),
.req(dreq),
.rnw(drnw),
.cbeg(cbeg),
.rrdy(drrdy),
.rddata(drddata),
.wrdata(dwrdata),
.bsel(dbsel),
.ra(ra),
.rd(rd),
.rwe_n(rwe_n),
.rucas_n(rucas_n),
.rlcas_n(rlcas_n),
.rras0_n(rras0_n),
.rras1_n(rras1_n) );
drammem chip0( .ma(ra),
.d(rd),
.ras_n(rras0_n),
.ucas_n(rucas_n),
.lcas_n(rlcas_n),
.we_n(rwe_n) );
drammem chip1( .ma(ra),
.d(rd),
.ras_n(rras1_n),
.ucas_n(rucas_n),
.lcas_n(rlcas_n),
.we_n(rwe_n) );
defparam chip0._add_to_addr_=0;
defparam chip1._add_to_addr_=1;
defparam chip0._filter_out_=0;
defparam chip1._filter_out_=0;
rom romko( .addr( {rompg[1:0],zaddr[13:0]} ),
.data(romdata),
.ce_n( (~csrom)|romoe_n ) );
synch horiz_sync( .clk(clk), .init(1'b0), .cend(cend), .pre_cend(pre_cend),
.hsync(hsync), .hblank(hblank), .hpix(hpix), .hsync_start(hsync_start),
.line_start(line_start) );
syncv vert_sync( .clk(clk), .hsync_start(hsync_start), .line_start(line_start),
.vblank(vblank), .vsync(vsync), .int_start(int_start),
.vpix(vpix) );
fetch fecher( .clk(clk), .cend(cend), .line_start(line_start), .vpix(vpix), .int_start(int_start),
.vmode(1'b1), .screen(1'b0), .video_addr(video_addr), .video_data(video_data), .video_strobe(video_strobe),
.video_next(video_next), .go(go), .bw(bw), .pixel(pixel) );
`ifdef FETCH_VERBOSE
always
begin
@(posedge video_next);
$write("video addr=$%h, ",video_addr); // address just before video_addr changes!
@(posedge video_strobe); @(negedge clk);
$write("data=$%h\n",video_data);
end
always
begin
@(negedge hsync)
if( vpix )
$display("new line");
end
`endif
endmodule
|
`default_nettype none
module original_gate (clk, ctrl, din, sel, dout);
input wire clk;
input wire [4:0] ctrl;
input wire [1:0] din;
input wire [0:0] sel;
output reg [31:0] dout;
always @(posedge clk)
case (({(ctrl)*(sel)})+(0))
0:
dout[31:0] <= din;
1:
dout[31:1] <= din;
2:
dout[31:2] <= din;
3:
dout[31:3] <= din;
4:
dout[31:4] <= din;
5:
dout[31:5] <= din;
6:
dout[31:6] <= din;
7:
dout[31:7] <= din;
8:
dout[31:8] <= din;
9:
dout[31:9] <= din;
10:
dout[31:10] <= din;
11:
dout[31:11] <= din;
12:
dout[31:12] <= din;
13:
dout[31:13] <= din;
14:
dout[31:14] <= din;
15:
dout[31:15] <= din;
16:
dout[31:16] <= din;
17:
dout[31:17] <= din;
18:
dout[31:18] <= din;
19:
dout[31:19] <= din;
20:
dout[31:20] <= din;
21:
dout[31:21] <= din;
22:
dout[31:22] <= din;
23:
dout[31:23] <= din;
24:
dout[31:24] <= din;
25:
dout[31:25] <= din;
26:
dout[31:26] <= din;
27:
dout[31:27] <= din;
28:
dout[31:28] <= din;
29:
dout[31:29] <= din;
30:
dout[31:30] <= din;
31:
dout[31:31] <= din;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; bool comp(string s, string t, vector<int> rows) { int i = 0; int m = s.size(); while (i < m && (s[i] == t[i] || (find(rows.begin(), rows.end(), i) != rows.end()))) i++; if (i == m) return false; return s[i] < t[i]; } int main() { int n, m; cin >> n >> m; vector<string> table(n); for (int i = 0; i < n; i++) cin >> table[i]; vector<int> rows; for (int j = 0; j < m; j++) { for (int i = 1; i < n; i++) { int k = i - 1; if (comp(table[i], table[k], rows)) { for (int l = 0; l < m; l++) { if (find(rows.begin(), rows.end(), l) != rows.end()) continue; if (table[i][l] < table[k][l]) { rows.push_back(l); break; } } } } } cout << rows.size() << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long mod; long long binPow(long long a, long long q) { a %= mod; if (q == 0) return 1; if (q % 2 == 1) return a * binPow(a * a, q / 2) % mod; else return binPow(a * a, q / 2) % mod; } bool prime(int x) { if (x % 2 == 0) return false; if (x % 3 == 0) return false; for (int i = 4; i <= sqrt(x); i++) if (x % i == 0) return false; return true; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int n; cin >> n; if (n > 4 && prime(n) == false) { cout << NO ; return 0; } cout << YES n ; if (n == 1) cout << 1; else if (n == 2) cout << 1 << endl << 2; else if (n == 3) cout << 1 << endl << 2 << endl << 3; else if (n == 4) cout << 1 << endl << 3 << endl << 2 << endl << 4; else { mod = n; cout << 1 << endl; int cnt = 2; while (cnt != n) { long long t = cnt * binPow(cnt - 1, n - 2) % mod; t %= n; cout << t << endl; cnt++; } cout << n; } } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2012.2
// Copyright (C) 2012 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module types_float_double_grp_fu_100_ACMP_ddiv_4_io(
clk,
reset,
io_ce,
io_rdy,
io_a,
io_b,
io_result);
input clk;
input reset;
input io_ce;
output io_rdy;
input[64 - 1:0] io_a;
input[64 - 1:0] io_b;
output[64 - 1:0] io_result;
divider64fp m(
.clk(clk),
.ce(io_ce),
.rdy(io_rdy),
.a(io_a),
.b(io_b),
.result(io_result));
endmodule
module divider64fp(
clk,
ce,
rdy,
a,
b,
result);
input clk;
input ce;
output rdy;
input[64 - 1:0] a;
input[64 - 1:0] b;
output[64 - 1:0] result;
//assign result = a + b;
//ACMP_ddiv #(
//.ID( ID ),
//.NUM_STAGE( 59 ),
//.din0_WIDTH( din0_WIDTH ),
//.din1_WIDTH( din1_WIDTH ),
//.dout_WIDTH( dout_WIDTH ))
//ACMP_ddiv_U(
// .clk( clk ),
// .reset( reset ),
// .ce( ce ),
// .din0( din0 ),
// .din1( din1 ),
// .dout( dout ));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLXBN_PP_BLACKBOX_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxbn (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_PP_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Jun 05 00:51:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_clk_wiz_0_0 -prefix
// system_clk_wiz_0_0_ system_clk_wiz_0_0_stub.v
// Design : system_clk_wiz_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_clk_wiz_0_0(clk_out1, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_in1" */;
output clk_out1;
input clk_in1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int N; vector<int> rating; void reading() { cin >> N; rating.resize(N); for (int i = 0; i < N; i++) cin >> rating[i]; } void processing() { for (int i = 0; i < N; i++) { int res = 0; for (int j = 0; j < N; j++) if (rating[i] < rating[j]) res++; cout << res + 1 << ; } } int main() { reading(); processing(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100; long long n, k; int a[15]; long long rc[15], p[15], ans; void solve() { scanf( %d%d , &n, &k); k++; scanf( %d , &a[1]); rc[1] = 1; long long now = 1, tmp; int ss = 0; for (int i = 2; i <= n; i++) { scanf( %d , &a[i]); tmp = 1; while (ss < a[i]) now *= 10, tmp *= 10, ss++; p[i - 1] = tmp - 1; rc[i] = now; } ans = 0; for (int i = 1; i < n; i++) { if (k >= p[i]) ans += p[i] * rc[i], k -= p[i]; else { ans += rc[i] * k; k = 0; } } if (k) ans += rc[n] * k; printf( %lld n , ans); } int main() { int t; scanf( %d , &t); while (t--) solve(); return 0; } |
/*
* Copyright (c) 2003 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program checks that some basics of real value support work.
*/
module main;
realtime x;
real a3, a4;
initial begin
a3 = 0.3;
a4 = 0.4;
x = 2 * a4 + a3;
$display("a3 = %f, a4 = %f, x = %f", a3, a4, x);
if (x > 1.1001) begin
$display("FAILED");
$finish;
end
if (x < 1.0999) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2B_BEHAVIORAL_V
`define SKY130_FD_SC_MS__AND2B_BEHAVIORAL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__and2b (
X ,
A_N,
B
);
// Module ports
output X ;
input A_N;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2B_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; long double esp = 1e-11; const long double PI = acos(-1.0); const long long int INF = 0x3f3f3f3f; const long long int MOD = 1000000007; const int maxn = 10010; const int NUM = 25; long long int wn[NUM]; long long int mu(long long int a, long long int b, long long int P) { long long int ans = 1; a %= P; while (b) { if (b & 1) ans = ans * a % P; a = a * a % P; b >>= 1; } return ans; } void GetWn(long long int G, long long int P) { long long int t; for (int i = 0; i < NUM; i++) { t = 1ll << i; wn[i] = mu(G, (P - 1) / t, P); } } void Rader(long long int a[], int len) { int j = len >> 1, k; for (int i = 1; i < len - 1; i++) { if (i < j) swap(a[i], a[j]); k = len >> 1; while (j >= k) { j -= k; k >>= 1; } if (j < k) j += k; } } void NTT(long long int a[], int len, int on, long long int P) { Rader(a, len); long long int id = 0, w, u, t; for (int h = 2; h <= len; h <<= 1) { id++; for (int j = 0; j < len; j += h) { w = 1; for (int k = j; k < j + h / 2; k++) { u = a[k] % P; t = w * a[k + h / 2] % P; a[k] = (u + t) % P; a[k + h / 2] = (u - t + P) % P; w = w * wn[id] % P; } } } if (on == -1) { for (int i = 1; i < len / 2; i++) swap(a[i], a[len - i]); long long int inv = mu(len, P - 2, P); for (int i = 0; i < len; i++) a[i] = a[i] * inv % P; } } long long int a[1ll << 20]; int main() { int n, k, tem; scanf( %d%d , &n, &k); memset(a, 0, sizeof(a)); for (int x = 1; x <= n; x++) { scanf( %d , &tem); a[tem] = 1; } long long int N = 1ll << 20, G = 3, P = 469762049ll; GetWn(G, P); NTT(a, N, 1, P); for (int i = 0; i < N; i++) a[i] = mu(a[i], k, P); NTT(a, N, -1, P); for (int i = 0; i < N; i++) if (a[i]) printf( %d , i); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd3 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// black box definition for pr module
`timescale 1ns/100ps
(* black_box *)
module prcfg (
input clk,
input [31:0] adc_gpio_input,
output [31:0] adc_gpio_output,
input [31:0] dac_gpio_input,
output [31:0] dac_gpio_output,
output dma_dac_en,
input dma_dac_dunf,
input [63:0] dma_dac_ddata,
input dma_dac_dvalid,
input core_dac_en,
output core_dac_dunf,
output [63:0] core_dac_ddata,
output core_dac_dvalid,
input core_adc_dwr,
input core_adc_dsync,
input [63:0] core_adc_ddata,
output core_adc_ovf,
output dma_adc_dwr,
output dma_adc_dsync,
output [63:0] dma_adc_ddata,
input dma_adc_ovf);
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string op; int x = 0; for (int k = 0; k < n; k++) { cin >> op; if (op == ++X || op == X++ ) { x++; } else if (op == --X || op == X-- ) { x--; } } cout << x << endl; } |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 12:17:59 11/12/2009
// Design Name:
// Module Name: performance_counter
// Project Name: Sora
// Target Devices: LX50T1136-1
// Tool versions: ISE 10.02
// Description: We measure the durations in this module (1) from TX_des request sent to tx_engine to new des
// received (2) from transfer start to transfer done.
// A counter (125MHz or 250MHz depends on DMA clock) is implemeted.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module performance_counter(
input clk,
input rst,
input transferstart_one,
input rd_dma_done_one,
input new_des_one,
output reg [23:0] round_trip_latency,
output reg [23:0] transfer_duration
);
reg [39:0] counter; /// free run 40bits counter, more than two hours per cycle on 125MHz clock
reg [23:0] snapshot_transferstart; /// record the lower 24 bit of counter when transferstart, more than 100ms per cycle on 125MHz clock
/// counter
always@(posedge clk) begin
if(rst)
counter <= 40'h00_0000_0000;
else
counter <= counter + 40'h00_0000_0001;
end
/// snapshot_transferstart
always@(posedge clk) begin
if(rst)
snapshot_transferstart <= 24'h00_0000;
else if (transferstart_one)
snapshot_transferstart <= counter[23:0];
else
snapshot_transferstart <= snapshot_transferstart;
end
/// round_trip_latency
always@(posedge clk) begin
if (rst)
round_trip_latency <= 24'h00_0000;
else if (new_des_one)
round_trip_latency <= counter[23:0] + (~snapshot_transferstart) + 24'h00_0001;
else
round_trip_latency <= round_trip_latency;
end
/// transfer_duration
always@(posedge clk) begin
if (rst)
transfer_duration <= 24'h00_0000;
else if (rd_dma_done_one)
transfer_duration <= counter[23:0] + (~snapshot_transferstart) + 24'h00_0001;
else
transfer_duration <= transfer_duration;
end
endmodule
|
module InstructionMemory(output reg[WORD_WIDTH-1:0] INSTR_out, input[WORD_WIDTH-1:0] INSTR_in);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter INSTR_WIDTH = WORD_WIDTH;
/*
0000 LDI R0,3
0001 LDI R1,7
0002 MOVA R2, R0
0003 MOVB R3, R1
0004 ADD R4,R0,R1
0005 SUB R5,R3,R4
0006 BRZ R5, 3
0007 BRN R5, 3
000A JMP R0
*/
always@(*)
begin
case(INSTR_in)
//16'h0000: INSTR_out = 16'b000_0000_000_000_000; //
16'h0000: INSTR_out = 16'b100_1100_000_000_011; // LDI R0 <- 3
16'h0001: INSTR_out = 16'b100_1100_001_000_111; // LDI R1 <- 7
16'h0002: INSTR_out = 16'b000_0000_010_010_XXX; // MOVA R2 <- R0
16'h0003: INSTR_out = 16'b000_1100_011_011_XXX; // MOVB R3 <- R1
16'h0004: INSTR_out = 16'b000_0010_010_000_001; // ADD R4 <- R0;R1
16'h0005: INSTR_out = 16'b000_0101_101_011_100; // SUB R5 <- R3;R4
16'h0006: INSTR_out = 16'b110_0000_000_101_011; // BRZ R5;3
16'h0007: INSTR_out = 16'b110_0001_000_101_011; // BRN R5;3
16'h0008: INSTR_out = 16'b111_0000_110_000_001; // JMP R0;
default: INSTR_out = 16'b0;
endcase
end
/*
always@(*)
begin //de acordo com a posição que o PC apontar, execute determinada instrução,
case(INSTR_in) //que basicamente é a que está salva naquela memória
16'h0000: INSTR_out = 16'b 0000000_001_010_XXX; // mova R1, R2 - NÃO TEM PROBLEMA DE DEIXAR O XXX OU 000.
16'h0001: INSTR_out = 16'b 0000001_110_100_001; // inc R6, R4
16'h0002: INSTR_out = 16'b 0000010_011_001_110; // add R3, R1, R6
16'h0003: INSTR_out = 16'b 0000101_010_101_010; // sub R2, R5, R2
16'h0004: INSTR_out = 16'b 0000110_000_111_001; // dec R0, R7
16'h0005: INSTR_out = 16'b 0001000_101_011_010; // and R5, R3, R2
16'h0006: INSTR_out = 16'b 0001001_000_100_110; // or R0, R4, R6
16'h0007: INSTR_out = 16'b 0001010_111_001_010; // xor R7, R1, R2
16'h0008: INSTR_out = 16'b 0001011_000_011_010; // not R0, R3
16'h0009: INSTR_out = 16'b 0001100_010_000_100; // movb R2, R4
16'h000A: INSTR_out = 16'b 0001101_001_100_011; // shr R1, R3
16'h000B: INSTR_out = 16'b 0001110_111_101_110; // shl R7, R6
16'h000C: INSTR_out = 16'b 1001100_010_000_010; // ldi R2, 2
16'h000D: INSTR_out = 16'b 1000010_100_011_100; // adi R4, R3, 4
16'h000E: INSTR_out = 16'b 0010000_101_000_010; // ld R5, R0
16'h000F: INSTR_out = 16'b 0100000_000_001_111; // st R1, R7
16'h0010: INSTR_out = 16'b 1100000_000_100_011; // brz R4, 3
16'h0011: INSTR_out = 16'b 1100001_111_010_000; // brn R2, 8
16'h0012: INSTR_out = 16'b 1110000_110_111_001; // jmp R7
default: INSTR_out = 16'b 1110000_110_000_001;
endcase
end //fim do always referente a memória de instruções
*/
endmodule |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SoC_nios2_qsys_0_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_TB_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_TB_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__inputiso1p.v"
module top();
// Inputs are registered
reg A;
reg SLEEP;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__inputiso1p dut (.A(A), .SLEEP(SLEEP), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 08/10/2017 09:26:11 AM
// Design Name:
// Module Name: MULTIPLEXER_16_TO_1
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MULTIPLEXER_16_TO_1 #(
parameter BUS_WIDTH = 32
) (
input [BUS_WIDTH - 1 : 0] IN1 ,
input [BUS_WIDTH - 1 : 0] IN2 ,
input [BUS_WIDTH - 1 : 0] IN3 ,
input [BUS_WIDTH - 1 : 0] IN4 ,
input [BUS_WIDTH - 1 : 0] IN5 ,
input [BUS_WIDTH - 1 : 0] IN6 ,
input [BUS_WIDTH - 1 : 0] IN7 ,
input [BUS_WIDTH - 1 : 0] IN8 ,
input [BUS_WIDTH - 1 : 0] IN9 ,
input [BUS_WIDTH - 1 : 0] IN10 ,
input [BUS_WIDTH - 1 : 0] IN11 ,
input [BUS_WIDTH - 1 : 0] IN12 ,
input [BUS_WIDTH - 1 : 0] IN13 ,
input [BUS_WIDTH - 1 : 0] IN14 ,
input [BUS_WIDTH - 1 : 0] IN15 ,
input [BUS_WIDTH - 1 : 0] IN16 ,
input [3 : 0] SELECT ,
output [BUS_WIDTH - 1 : 0] OUT
);
reg [BUS_WIDTH - 1 : 0] out_reg;
always@(*)
begin
case(SELECT)
4'b0000:
begin
out_reg = IN1 ;
end
4'b0001:
begin
out_reg = IN2 ;
end
4'b0010:
begin
out_reg = IN3 ;
end
4'b0011:
begin
out_reg = IN4 ;
end
4'b0100:
begin
out_reg = IN5 ;
end
4'b0101:
begin
out_reg = IN6 ;
end
4'b0110:
begin
out_reg = IN7 ;
end
4'b0111:
begin
out_reg = IN8 ;
end
4'b1000:
begin
out_reg = IN9 ;
end
4'b1001:
begin
out_reg = IN10 ;
end
4'b1010:
begin
out_reg = IN11 ;
end
4'b1011:
begin
out_reg = IN12 ;
end
4'b1100:
begin
out_reg = IN13 ;
end
4'b1101:
begin
out_reg = IN14 ;
end
4'b1110:
begin
out_reg = IN15 ;
end
4'b1111:
begin
out_reg = IN16 ;
end
endcase
end
assign OUT = out_reg;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct Edge { int to, w, type; Edge() {} Edge(int _to, int _w, int _type) : to(_to), w(_w), type(_type) {} bool operator<(const Edge other) { return type < other.type; } }; const long long N = 1e5 + 5, oo = 1e18; long long n, m, k, dist[N], res; int deg[N]; vector<Edge> adj[N]; bool mark[N]; int main(int argc, char const *argv[]) { ios_base::sync_with_stdio(0); cin.tie(0); clock_t tStart = clock(); cin >> n >> m >> k; for (long long huy = 0, _n = (m); huy < _n; huy++) { long long u, v, w; cin >> u >> v >> w; adj[u].push_back(Edge(v, w, 0)); adj[v].push_back(Edge(u, w, 0)); } for (long long nene = 0, _n = (k); nene < _n; nene++) { long long v, t; cin >> v >> t; adj[1].push_back(Edge(v, t, 1)); adj[v].push_back(Edge(1, t, 1)); } set<pair<long long, long long> > pq; pq.clear(); pq.insert(pair<long long, long long>(0, 1)); for (long long i = (2), _b = (n); i <= _b; i++) dist[i] = oo; while (!pq.empty()) { pair<long long, long long> front = *(pq.begin()); long long d = front.first, u = front.second; pq.erase(pq.begin()); if (d > dist[u]) continue; for (Edge e : adj[u]) if (dist[u] + e.w < dist[e.to]) { dist[e.to] = dist[u] + e.w; pq.insert(pair<long long, long long>(dist[e.to], e.to)); } } for (long long u = (1), _b = (n); u <= _b; u++) for (Edge e : adj[u]) { if (dist[u] + e.w == dist[e.to]) { deg[e.to]++; } } res = k; for (long long u = (1), _b = (n); u <= _b; u++) for (Edge e : adj[u]) { if (e.type == 1 && dist[u] + e.w == dist[e.to]) { if (deg[e.to] == 1) res--; deg[e.to]--; } } cout << res << n ; fprintf(stderr, Time taken: %.2fs n , (double)(clock() - tStart) / CLOCKS_PER_SEC); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUF_16_V
`define SKY130_FD_SC_LP__BUF_16_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__buf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUF_16_V
|
#include <bits/stdc++.h> using namespace std; const int N = 200005; int arr[N], f[N]; int main() { int n; scanf( %d , &n); set<int> st; for (int i = 1; i <= n; ++i) { st.insert(i); scanf( %d , arr + i); } st.insert(n + 1); int q; scanf( %d , &q); int t, x, v; while (q--) { scanf( %d , &t); if (t == 1) { scanf( %d %d , &x, &v); int cur = *st.lower_bound(x); while (v && cur <= n) { if (f[cur] + v < arr[cur]) { f[cur] += v; v = 0; } else { v -= (arr[cur] - f[cur]); f[cur] = arr[cur]; st.erase(cur); cur = *st.lower_bound(x); } } } else { scanf( %d , &x); printf( %d n , f[x]); } } } |
#include <bits/stdc++.h> using namespace std; long long const INF = (long long)1e9; long long const INF64 = (long long)4e18; long long const v10e5 = (long long)100000; long long const v10e6 = (long long)1000000; long long const v10e9 = (long long)1000000000; long long const s10e5 = (long long)100000 + 10; long long const s10e6 = (long long)1000000 + 10; long long const s10e9 = (long long)1000000000 + 10; long long __dummy__; int main() { ios_base::sync_with_stdio(0); long long n, k; cin >> n >> k; vector<long long> a(n + 1, 1); a[n] = 0; long long max_ = 1; for (long long(i) = (1); (i) <= (k); ++i) { for (long long(i) = (1); (i) <= (n); ++i) { if ((n - i) - a[i] >= max_) { cout << n - max_ << ; a[i] += max_; } else { cout << i + a[i] << ; a[i] = n - i; } } cout << endl; max_ = a[1]; } return 0; } |
`define SMV
`include "ovl_next_wrapped.v"
`include "ovl_ported/ovl_next.v"
/*
* File: ovl_next_wrapped_tb.v
* Test bench for ovl_next_wrapped.v
* Configuration values for ovl_next_wrapped must match the
* hard-coded values used here.
* Includes assertions for verification.
* Created 2013-10-16
*
*/
module main();
// Inputs to DUT
reg clk;
reg rst;
reg enable;
reg [2:0] num_cks;
reg start_event;
reg test_expr;
reg prevConfigInvalid;
// Outputs of DUT
wire out;
ovl_next_wrapped ovl_nw_t(.clk(clk),
.rst(rst),
.enable(enable),
.num_cks(num_cks),
.start_event(start_event),
.test_expr(test_expr),
.prevConfigInvalid(prevConfigInvalid),
.out(out));
initial begin
clk = 0;
rst = 1;
enable = 0;
num_cks = 0;
start_event = 0;
test_expr = 0;
prevConfigInvalid = 0;
end
always begin
clk = #5 !clk;
end
endmodule // main
/* *************** SMV Assertions *****************
//SMV-Assertions
# Verification is valid when num_cks_width=3 and num_cks_max=7
# Spec:
# @time t:
# IF start_event occurred at t-num_cks AND ~test_expr
# THEN @t+1, ~prevConfigInvalid -> out
# out and prevConfigInvalid are never both high.
\prevConfigInvalid_clears_out : assert \rst -> X(G(\out -> ~\prevConfigInvalid ));
# out is high only if test_expr was low in previous cycle.
\only_if_test_expr : assert \rst -> X(G(\test_expr -> X(~\out )));
# out is high only if there was a start_event in some previous cycle. Note that this can only be verified if num_cks is greater than 0. If num_cks = 0, the reg num_cks_1 wraps (num_cks_1 = num_cks - 1) and the monitor array is accessed at an invalid index.
\only_if_start_event : assert \rst -> X(G((\num_cks > 0) && ~\start_event ) -> G(~\out ));
# implements the spec for num_cks_max = 1
\correct_1 : assert \rst -> X(G((~\rst && \start_event && X(~\rst && ~\test_expr && (\num_cks = 1))) -> X(X(~\prevConfigInvalid -> \out ))));
# implements the spec for num_cks_max = 2
\correct_2 : assert \rst -> X(G((~\rst && \start_event && X(~\rst && X(~\rst && ~\test_expr && (\num_cks = 2)))) -> X(X(X(~\prevConfigInvalid -> \out )))));
# implements the spec for num_cks_max = 3
\correct_3 : assert \rst -> X(G((~\rst && \start_event && X(~\rst && X(~\rst && X(~\rst && ~\test_expr && (\num_cks = 3))))) -> X(X(X(X(~\prevConfigInvalid -> \out ))))));
# implements the spec for num_cks_max = 4
\correct_4 : assert \rst -> X(G((~\rst && \start_event && X(~\rst && X(~\rst && X(~\rst && X(~\rst && ~\test_expr && (\num_cks = 4)))))) -> X(X(X(X(X(~\prevConfigInvalid -> \out )))))));
# implements the spec for num_cks_max = 5
\correct_5 : assert \rst -> X(G((~\rst && \start_event && X(~\rst && X(~\rst && X(~\rst && X(~\rst && X(~\rst && ~\test_expr && (\num_cks = 5))))))) -> X(X(X(X(X(X(~\prevConfigInvalid -> \out ))))))));
# implements the spec for num_cks_max = 6
\correct_6 : assert \rst -> X(G((~\rst && \start_event && X(~\rst && X(~\rst && X(~\rst && X(~\rst && X(~\rst && X(~\rst && ~\test_expr && (\num_cks = 6)))))))) -> X(X(X(X(X(X(X(~\prevConfigInvalid -> \out )))))))));
# implements the spec for num_cks_max = 7
\correct_7 : assert \rst -> X(G((~\rst && \start_event && X(~\rst && X(~\rst && X(~\rst && X(~\rst && X(~\rst && X(~\rst && X(~\rst && ~\test_expr && (\num_cks = 7))))))))) -> X(X(X(X(X(X(X(X(~\prevConfigInvalid -> \out ))))))))));
//SMV-Assertions
*/
|
#include <bits/stdc++.h> using namespace std; ifstream fin( A.in ); ofstream fout( A.out ); long long r, h; int main() { cin >> r >> h; if (h % r == 0) { cout << (h / r) * 2 + 1; return 0; } double d = double(h) / double(r); int z = h / r; double dd = z + 0.5; if (d >= dd) { if ((r / 2) * (r / 2) + ((d - dd) * r + r / 2) * ((d - dd) * r + r / 2) >= r * r) cout << 2 * z + 3; else cout << 2 * z + 2; } else { cout << 2 * z + 1; } } |
/*
Teak synthesiser for the Balsa language
Copyright (C) 2007-2010 The University of Manchester
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Andrew Bardsley <> (and others, see AUTHORS)
School of Computer Science, The University of Manchester
Oxford Road, MANCHESTER, M13 9PL, UK
*/
`timescale 1ns/1ps
`ifdef RESET_PERIOD
`else
`define RESET_PERIOD 10
`endif
`ifdef HS_PERIOD
`else
`define HS_PERIOD 10
`endif
module top;
reg reset;
`ifdef HAS_GO
reg go_r;
wire go_a;
initial begin
go_r = 0;
@(negedge reset);
#`HS_PERIOD;
$display ("go");
go_r = 1;
@(posedge go_a);
#`HS_PERIOD;
go_r = 0;
@(negedge go_a);
#`HS_PERIOD;
end
`endif
`ifdef HAS_DONE
wire done_r;
reg done_a;
initial begin
done_a = 0;
@(posedge done_r);
#`HS_PERIOD;
$display ("done");
done_a = 1;
@(negedge done_r);
#`HS_PERIOD;
done_a = 0;
end
`endif
initial begin
reset = 1;
`ifdef DUMPFILE
$dumpfile (`DUMPFILE);
$dumpvars (0, top);
`endif
$display ("reset");
#`RESET_PERIOD;
reset = 0;
end
`DUT DUT (
`ifdef HAS_GO
.go_0r(go_r), .go_0a(go_a),
`endif
`ifdef HAS_DONE
.done_0r(done_r), .done_0a(done_a),
`endif
.reset(reset)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<int> A, B; for (int i = 1; i <= n; i++) A.push_back(i); long long sum = 0; for (int i = 2; i < n; i++) sum += i * (i + 1); cout << sum << n ; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 500 + 10; const int P = 998244353; int N, X, f[MAXN][MAXN], pw[MAXN][MAXN], binom[MAXN][MAXN]; void add(int& a, int b) { a = a + b >= P ? a + b - P : a + b; } int dif(int a, int b) { return a - b < 0 ? a - b + P : a - b; } int main() { for (int i = (0), iend = (MAXN); i < iend; ++i) { pw[i][0] = (i > 0); for (int j = (1), jend = (MAXN); j < jend; ++j) pw[i][j] = 1ll * pw[i][j - 1] * i % P; } binom[0][0] = 1; for (int i = (1), iend = (MAXN); i < iend; ++i) { binom[i][0] = 1; for (int j = (1), jend = (i + 1); j < jend; ++j) binom[i][j] = binom[i - 1][j - 1], add(binom[i][j], binom[i - 1][j]); } for (int i = (1), iend = (MAXN); i < iend; ++i) f[0][i] = 1; for (int i = (2), iend = (MAXN); i < iend; ++i) for (int j = (1), jend = (MAXN); j < jend; ++j) { for (int x = i - 1; x < j; x += i - 1) { for (int k = (1), kend = (i); k < kend; ++k) add(f[i][j], 1ll * binom[i][k] * f[i - k][j - x] % P * pw[i - 1][k] % P); } for (int x = 0; x < j; x += i - 1) add(f[i][j], pw[min(i - 1, j - x)][i]); } scanf( %d %d , &N, &X); printf( %d n , f[N][X]); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; int x; cin >> x; vector<int> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } if (n == 1) { cout << 0 << n ; return 0; } sort(a.begin(), a.end()); if (x < a[0]) { cout << a[0] - x + a[n - 2] - a[0] << n ; return 0; } if (x > a[n - 1]) { cout << x - a[n - 1] + a[n - 1] - a[1] << n ; return 0; } int ans1 = a[n - 2] - a[0] + min((int)abs(x - a[0]), (int)abs(x - a[n - 2])); int ans2 = a[n - 1] - a[1] + min((int)abs(x - a[1]), (int)abs(x - a[n - 1])); cout << min(ans1, ans2) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long INF = 1e18; const int MAXN = 3e5 + 10; const int MAXM = 1e4 + 500; const int N = 5600 + 15; const double EPS = 1e-9; double len(complex<long long> a) { return sqrt(a.real() * a.real() + a.imag() * a.imag()); } long long sq(complex<long long> a) { return a.real() * a.real() + a.imag() * a.imag(); } complex<long long> perp(complex<long long> p) { return {-p.imag(), p.real()}; } long long dotProduct(complex<long long> a, complex<long long> b) { return (conj(a) * b).real(); } long long crossProduct(complex<long long> a, complex<long long> b) { return (conj(a) * b).imag(); } long long orient(complex<long long> a, complex<long long> b, complex<long long> c) { return crossProduct(b - a, c - a); } bool inDisk(complex<long long> a, complex<long long> b, complex<long long> p) { return dotProduct(a - p, b - p) <= 0; } bool onSegment(complex<long long> a, complex<long long> b, complex<long long> p) { return orient(a, b, p) == 0 && inDisk(a, b, p); }; struct cmpX { bool operator()(complex<long long> a, complex<long long> b) { return make_pair(a.real(), a.imag()) < make_pair(b.real(), b.imag()); } }; struct line { complex<long long> v; long long c; line(complex<long long> v, long long c) : v(v), c(c) {} line(long long a, long long b, long long c) : v({b, -a}), c(c) {} line(complex<long long> p, complex<long long> q) : v(q - p), c(crossProduct(v, p)) {} long long side(complex<long long> p) { return crossProduct(v, p) - c; } double dist(complex<long long> p) { return abs(side(p)) / len(v); } line perpThrough(complex<long long> p) { return {p, p + perp(v)}; } bool cmpProj(complex<long long> p, complex<long long> q) { return dotProduct(v, p) < dotProduct(v, q); } line translate(complex<long long> t) { return {v, c + crossProduct(v, t)}; } complex<long long> proj(complex<long long> p) { return p - perp(v) * side(p) / sq(v); } }; double segPoint(complex<long long> a, complex<long long> b, complex<long long> p) { if (a != b) { line l(a, b); if (l.cmpProj(a, p) && l.cmpProj(p, b)) return l.dist(p); } return min(abs(p - a), abs(p - b)); } bool inAngle(complex<long long> a, complex<long long> b, complex<long long> c, complex<long long> p) { if (orient(a, b, c) < 0) swap(b, c); return orient(a, b, p) >= 0 && orient(a, c, p) <= 0; } bool isInsidePol(vector<complex<long long> > &a, complex<long long> b) { int n = a.size(); int pos = 0, neg = 0; for (int i = 0; i < n - 1; i++) { if (onSegment(a[i], a[(i + 1) % n], b)) return false; line l(a[i], a[i + 1]); if (l.side(b) > 0) pos++; else neg++; } line l(a[n - 1], a[0]); if (l.side(b) > 0) pos++; else neg++; return ((!pos && neg == n) || (!neg && pos == n)); } long long i, j, k; long long n, m, t; long long binpow(long long val, long long deg) { if (!deg) return 1; if (deg & 1) return binpow(val, deg - 1) * val % MOD; long long res = binpow(val, deg >> 1); return (res * res) % MOD; } long long inv(long long a, long long m) { return binpow(a, m - 2); } long long add(long long a, long long b) { return (a += b) < MOD ? a : a - MOD; } long long mul(long long a, long long b) { return a * b % MOD; } long long cleverMulMod(long long a, long long b) { if (b == 0) return 0; long long s = cleverMulMod(a, b / 2); if (b % 2 == 1) return (a % MOD + 2ll * (s % MOD)) % MOD; else return (2ll * (s % MOD)) % MOD; } class Matrix { public: vector<vector<long long> > A; int dim; Matrix(int n) : dim(n) { A.assign(n, vector<long long>(n)); } vector<long long> &operator[](int n) { return A[n]; } }; Matrix operator*(Matrix A, Matrix B) { int n = A.dim; Matrix C(n); for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) for (int k = 0; k < n; k++) { C[i][j] = add(C[i][j], mul(A[i][k], B[k][j])); } return C; } Matrix operator^(Matrix A, long long k) { int n = A.dim; Matrix R(n); for (int i = 0; i < n; i++) R[i][i] = 1; while (k > 0) { if (k % 2) R = R * A; A = A * A; k /= 2; } return R; } long long first, second, need; bool check(long long k) { long long total = 2 * k * (k + 1) + 1; k++; if (k > first) { total -= (k - first) * (k - first); } if (k > second) { total -= (k - second) * (k - second); } if (k > n - first) { total -= (k - (n - first)) * (k - (n - first)); } if (k > n - second) { total -= (k - (n - second)) * (k - (n - second)); } if (k > first + second) { total += (k - (first + second)) * (k - (first + second) + 1) / 2; } if (k + first > n + second) { total += (k + first - n - second) * (k + first - n - second + 1) / 2; } if (k + first + second - n - n > 0) { total += (k + first + second - n - n) * (k + first + second - n - n + 1) / 2; } if (k + second > n + first) { total += (k + second - n - first) * (k + second - n - first + 1) / 2; } return total >= need; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> first >> second >> need; n++; long long left = 0, right = 1e9 + 3; while (right - left > 1) { long long mid = (right + left) / 2; if (check(mid)) right = mid; else left = mid; } if (check(left)) right = left; cout << right << endl; return 0; } |
/*
*
* Clock, reset generation unit for ML501 board
*
* Implements clock generation according to design defines
*
*/
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "orpsoc-defines.v"
`include "synthesis-defines.v"
module clkgen
(
// Main clocks in, depending on board
sys_clk_in_p, sys_clk_in_n,
// Wishbone clock and reset out
wb_clk_o,
wb_rst_o,
// JTAG clock
`ifdef JTAG_DEBUG
tck_pad_i,
dbg_tck_o,
`endif
// Main memory clocks
`ifdef XILINX_DDR2
ddr2_if_clk_o,
ddr2_if_rst_o,
clk200_o,
`endif
// Asynchronous, active low reset in
rst_n_pad_i
);
input sys_clk_in_p,sys_clk_in_n;
output wb_rst_o;
output wb_clk_o;
`ifdef JTAG_DEBUG
input tck_pad_i;
output dbg_tck_o;
`endif
`ifdef XILINX_DDR2
output ddr2_if_clk_o;
output ddr2_if_rst_o;
output clk200_o;
`endif
// Asynchronous, active low reset (pushbutton, typically)
input rst_n_pad_i;
// First, deal with the asychronous reset
wire async_rst;
wire async_rst_n;
// Xilinx synthesis tools appear cluey enough to instantiate buffers when and
// where they're needed, so we do simple assigns for this tech.
assign async_rst_n = rst_n_pad_i;
// Everyone likes active-high reset signals...
assign async_rst = ~async_rst_n;
`ifdef JTAG_DEBUG
assign dbg_tck_o = tck_pad_i;
`endif
//
// Declare synchronous reset wires here
//
// An active-low synchronous reset signal (usually a PLL lock signal)
wire sync_rst_n;
// An active-low synchronous reset from ethernet PLL
wire sync_eth_rst_n;
wire sys_clk_in_200;
/* DCM0 wires */
wire dcm0_clk0_prebufg, dcm0_clk0;
wire dcm0_clkfx_prebufg, dcm0_clkfx;
wire dcm0_clkdv_prebufg, dcm0_clkdv;
wire dcm0_locked;
/* Dif. input buffer for 200MHz board clock, generate SE 200MHz */
IBUFGDS_LVPECL_25 sys_clk_in_ibufds
(
.O(sys_clk_in_200),
.I(sys_clk_in_p),
.IB(sys_clk_in_n));
/* DCM providing main system/Wishbone clock */
DCM_BASE dcm0
(
// Outputs
.CLK0 (dcm0_clk0_prebufg),
.CLK180 (),
.CLK270 (),
.CLK2X180 (),
.CLK2X (),
.CLK90 (),
.CLKDV (dcm0_clkdv_prebufg),
.CLKFX180 (),
.CLKFX (dcm0_clkfx_prebufg),
.LOCKED (dcm0_locked),
// Inputs
.CLKFB (dcm0_clk0),
.CLKIN (sys_clk_in_200),
.RST (1'b0));
// Generate 200 MHz from CLKFX
defparam dcm0.CLKFX_MULTIPLY = 3;
defparam dcm0.CLKFX_DIVIDE = 4;
// Generate 50 MHz from CLKDV
defparam dcm0.CLKDV_DIVIDE = 4;
BUFG dcm0_clk0_bufg
(// Outputs
.O (dcm0_clk0),
// Inputs
.I (dcm0_clk0_prebufg));
BUFG dcm0_clkfx_bufg
(// Outputs
.O (dcm0_clkfx),
// Inputs
.I (dcm0_clkfx_prebufg));
BUFG dcm0_clkdv_bufg
(// Outputs
.O (dcm0_clkdv),
// Inputs
.I (dcm0_clkdv_prebufg));
assign wb_clk_o = dcm0_clkdv;
assign sync_rst_n = dcm0_locked;
`ifdef XILINX_DDR2
assign ddr2_if_clk_o = dcm0_clkfx; // 150 MHz
assign clk200_o = dcm0_clk0; // 200 MHz
`endif
//
// Reset generation
//
//
// Reset generation for wishbone
reg [15:0] wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst)
if (async_rst)
wb_rst_shr <= 16'hffff;
else
wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
assign wb_rst_o = wb_rst_shr[15];
`ifdef XILINX_DDR2
// Reset generation for DDR2 controller
reg [15:0] ddr2_if_rst_shr;
always @(posedge ddr2_if_clk_o or posedge async_rst)
if (async_rst)
ddr2_if_rst_shr <= 16'hffff;
else
ddr2_if_rst_shr <= {ddr2_if_rst_shr[14:0], ~(sync_rst_n)};
assign ddr2_if_rst_o = ddr2_if_rst_shr[15];
`endif
endmodule // clkgen
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