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//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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// (including loss of data, profits, goodwill, or any type of
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// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
// limbus_tristate_conduit_pin_sharer_0.v
// This file was auto-generated from altera_tristate_conduit_pin_sharer_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module limbus_tristate_conduit_pin_sharer_0 (
input wire clk_clk, // clk.clk
input wire reset_reset, // reset.reset
output wire request, // tcm.request
input wire grant, // .grant
output wire [18:0] sram_tcm_address_out, // .sram_tcm_address_out_out
output wire [1:0] sram_tcm_byteenable_n_out, // .sram_tcm_byteenable_n_out_out
output wire [0:0] sram_tcm_outputenable_n_out, // .sram_tcm_outputenable_n_out_out
output wire [0:0] sram_tcm_write_n_out, // .sram_tcm_write_n_out_out
output wire [15:0] sram_tcm_data_out, // .sram_tcm_data_out_out
input wire [15:0] sram_tcm_data_in, // .sram_tcm_data_out_in
output wire sram_tcm_data_outen, // .sram_tcm_data_out_outen
output wire [0:0] sram_tcm_chipselect_n_out, // .sram_tcm_chipselect_n_out_out
input wire tcs0_request, // tcs0.request
output wire tcs0_grant, // .grant
input wire [18:0] tcs0_address_out, // .address_out
input wire [1:0] tcs0_byteenable_n_out, // .byteenable_n_out
input wire [0:0] tcs0_outputenable_n_out, // .outputenable_n_out
input wire [0:0] tcs0_write_n_out, // .write_n_out
input wire [15:0] tcs0_data_out, // .data_out
output wire [15:0] tcs0_data_in, // .data_in
input wire tcs0_data_outen, // .data_outen
input wire [0:0] tcs0_chipselect_n_out // .chipselect_n_out
);
wire [0:0] arbiter_grant_data; // arbiter:next_grant -> pin_sharer:next_grant
wire arbiter_grant_ready; // pin_sharer:ack -> arbiter:ack
wire pin_sharer_tcs0_arb_valid; // pin_sharer:arb_sram_tcm -> arbiter:sink0_valid
limbus_tristate_conduit_pin_sharer_0_pin_sharer pin_sharer (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // reset.reset
.request (request), // tcm.request
.grant (grant), // .grant
.sram_tcm_address_out (sram_tcm_address_out), // .sram_tcm_address_out_out
.sram_tcm_byteenable_n_out (sram_tcm_byteenable_n_out), // .sram_tcm_byteenable_n_out_out
.sram_tcm_outputenable_n_out (sram_tcm_outputenable_n_out), // .sram_tcm_outputenable_n_out_out
.sram_tcm_write_n_out (sram_tcm_write_n_out), // .sram_tcm_write_n_out_out
.sram_tcm_data_out (sram_tcm_data_out), // .sram_tcm_data_out_out
.sram_tcm_data_in (sram_tcm_data_in), // .sram_tcm_data_out_in
.sram_tcm_data_outen (sram_tcm_data_outen), // .sram_tcm_data_out_outen
.sram_tcm_chipselect_n_out (sram_tcm_chipselect_n_out), // .sram_tcm_chipselect_n_out_out
.tcs0_request (tcs0_request), // tcs0.request
.tcs0_grant (tcs0_grant), // .grant
.tcs0_tcm_address_out (tcs0_address_out), // .address_out
.tcs0_tcm_byteenable_n_out (tcs0_byteenable_n_out), // .byteenable_n_out
.tcs0_tcm_outputenable_n_out (tcs0_outputenable_n_out), // .outputenable_n_out
.tcs0_tcm_write_n_out (tcs0_write_n_out), // .write_n_out
.tcs0_tcm_data_out (tcs0_data_out), // .data_out
.tcs0_tcm_data_in (tcs0_data_in), // .data_in
.tcs0_tcm_data_outen (tcs0_data_outen), // .data_outen
.tcs0_tcm_chipselect_n_out (tcs0_chipselect_n_out), // .chipselect_n_out
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.arb_sram_tcm (pin_sharer_tcs0_arb_valid) // tcs0_arb.valid
);
limbus_tristate_conduit_pin_sharer_0_arbiter arbiter (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // clk_reset.reset
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.sink0_valid (pin_sharer_tcs0_arb_valid) // sink0.valid
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 4 * 1e5 + 5; vector<int> g[N]; int n, dp[N], res[N]; int dfs(int i, int p = -1) { dp[i] = 1; for (auto j : g[i]) { if (j != p) { dp[i] += dfs(j, i); } } return dp[i]; } int dfs2(int i, int p = -1) { for (auto j : g[i]) { if (j != p && dp[j] * 2 > n) { return dfs2(j, i); } } return i; } void dfs3(int i, int p, int c1, int c2) { if (c1 * 2 >= n) res[i] = 1; if ((dp[i] + c2) * 2 >= n) res[i] = 1; for (auto j : g[i]) { if (j != p) { dfs3(j, i, c1, c2); } } } int main() { std::ios::sync_with_stdio(false); cin >> n; for (int i = 1; i < n; ++i) { int a, b; cin >> a >> b; --a; --b; g[a].push_back(b); g[b].push_back(a); } dfs(0); int a = dfs2(0); dfs(a); res[a] = 1; int mx = -1, mx2 = -1, v; for (auto j : g[a]) { if (dp[j] > mx) { mx2 = mx; mx = dp[j]; v = j; } else if (dp[j] > mx2) { mx2 = dp[j]; } } for (auto j : g[a]) { if (j == v) dfs3(j, a, dp[j], mx2); else dfs3(j, a, dp[j], mx); } for (int i = 0; i < n; ++i) cout << res[i] << ; return 0; } |
/* nand2tetris 的要求應該用下列方式實作，但是由於這樣元件太多會導致 icarus 編譯失敗，
出現下列訊息：
D:\Dropbox\cccweb\db\n2t>iverilog ram_test.v -o ram_test
This application has requested the Runtime to terminate it in an unusual way.
Please contact the application's support team for more information.
所以我們在記憶體容量大的時候改用 verilog 的陣列型寫法，這樣就不會當機了。 */
`include "alu.v"
module DFF (input in, clock, load, output out);
reg q;
assign out = q;
always @(posedge clock) begin
if (load) q = in;
end
endmodule
module Bit(input in, clock, load, output out);
DFF dff1(in, clock, load, out);
endmodule
module Register(input[15:0] in, input clock, load, output[15:0] out);
Bit g01(in[15], clock, load, out[15]);
Bit g02(in[14], clock, load, out[14]);
Bit g03(in[13], clock, load, out[13]);
Bit g04(in[12], clock, load, out[12]);
Bit g05(in[11], clock, load, out[11]);
Bit g06(in[10], clock, load, out[10]);
Bit g07(in[9], clock, load, out[9]);
Bit g08(in[8], clock, load, out[8]);
Bit g09(in[7], clock, load, out[7]);
Bit g10(in[6], clock, load, out[6]);
Bit g11(in[5], clock, load, out[5]);
Bit g12(in[4], clock, load, out[4]);
Bit g13(in[3], clock, load, out[3]);
Bit g14(in[2], clock, load, out[2]);
Bit g15(in[1], clock, load, out[1]);
Bit g16(in[0], clock, load, out[0]);
endmodule
module PC(input[15:0] in, input clock, load, inc, reset, output[15:0] out);
wire[15:0] if1, if2, if3, oInc, o;
Or g1(load, inc, loadInc);
Or g2(loadInc, reset, loadIncReset);
Inc16 inc1(o, oInc);
And16 g3(o, o, out);
Mux16 g4(o, oInc, inc, if1);
Mux16 g5(if1, in, load, if2);
Mux16 g6(if2, 16'b0, reset, if3);
Register reg1(if3, clock, loadIncReset, o);
endmodule
module RAM8(input[15:0] in, input clock, load, input[2:0] address, output[15:0] out);
wire[15:0] o0,o1,o2,o3,o4,o5,o6,o7;
DMux8Way g0(1'b1, address, E0, E1, E2, E3, E4, E5, E6, E7);
And a0(load, E0, L0); Register r0(in, clock, L0, o0);
And a1(load, E1, L1); Register r1(in, clock, L1, o1);
And a2(load, E2, L2); Register r2(in, clock, L2, o2);
And a3(load, E3, L3); Register r3(in, clock, L3, o3);
And a4(load, E4, L4); Register r4(in, clock, L4, o4);
And a5(load, E5, L5); Register r5(in, clock, L5, o5);
And a6(load, E6, L6); Register r6(in, clock, L6, o6);
And a7(load, E7, L7); Register r7(in, clock, L7, o7);
Mux8Way16 g1(o0, o1, o2, o3, o4, o5, o6, o7, address, out);
endmodule
module RAM64(input[15:0] in, input clock, load, input[5:0] address, output[15:0] out);
wire[15:0] o0,o1,o2,o3,o4,o5,o6,o7;
DMux8Way g0(1'b1, address[5:3], E0, E1, E2, E3, E4, E5, E6, E7);
And a0(load, E0, L0); RAM8 m0(in, clock, L0, address[2:0], o0);
And a1(load, E1, L1); RAM8 m1(in, clock, L1, address[2:0], o1);
And a2(load, E2, L2); RAM8 m2(in, clock, L2, address[2:0], o2);
And a3(load, E3, L3); RAM8 m3(in, clock, L3, address[2:0], o3);
And a4(load, E4, L4); RAM8 m4(in, clock, L4, address[2:0], o4);
And a5(load, E5, L5); RAM8 m5(in, clock, L5, address[2:0], o5);
And a6(load, E6, L6); RAM8 m6(in, clock, L6, address[2:0], o6);
And a7(load, E7, L7); RAM8 m7(in, clock, L7, address[2:0], o7);
Mux8Way16 g1(o0, o1, o2, o3, o4, o5, o6, o7, address[5:3], out);
endmodule
module ROM32K(input[14:0] address, output[15:0] out);
reg[15:0] m[0:2**14-1];
assign out = m[address];
endmodule
module RAM8K(input[15:0] in, input clock, load, input[12:0] address, output[15:0] out);
reg[15:0] m[0:2**12-1];
assign out = m[address];
always @(posedge clock) begin
if (load) m[address] = in;
end
endmodule
module RAM16K(input[15:0] in, input clock, load, input[13:0] address, output[15:0] out);
reg[15:0] m[0:2**13-1];
assign out = m[address];
always @(posedge clock) begin
if (load) m[address] = in;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int x; scanf( %d , &x); printf( %d , x + 1 >> 1); } |
#include <bits/stdc++.h> using namespace std; template <class T, class S> ostream& operator<<(ostream& os, const pair<T, S>& v) { return os << ( << v.first << , << v.second << ) ; } template <class T> ostream& operator<<(ostream& os, const vector<T>& v) { os << [ ; for (int i = int(0); i <= int((static_cast<int>((v).size())) - 1); ++i) { if (i) os << , ; os << v[i]; } return os << ] ; } template <class T> bool setmax(T& _a, T _b) { if (_a < _b) { _a = _b; return true; } return false; } template <class T> bool setmin(T& _a, T _b) { if (_b < _a) { _a = _b; return true; } return false; } template <class T> T gcd(T _a, T _b) { return _b == 0 ? _a : gcd(_b, _a % _b); } int main() { int n, k; cin >> n >> k; vector<int> a(n); iota((a).begin(), (a).end(), 0); int cur = 0; while (k--) { int x; cin >> x; int next = (cur + x) % static_cast<int>((a).size()); cout << a[next] + 1 << ; a.erase(a.begin() + next); cur = next % static_cast<int>((a).size()); } cout << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O22AI_FUNCTIONAL_PP_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22AI_FUNCTIONAL_PP_V |
//------------------------------------------------------------------------------
// YF32 -- A small SOC implementation based on mlite (32-bit RISC CPU)
// @Taiwan
//------------------------------------------------------------------------------
//
// YF32 - A SOC implementation based on verilog ported mlite (32-bit RISC CPU)
// Copyright (C) 2003-2004 Yung-Fu Chen ()
//
//------------------------------------------------------------------------------
// FETURE
// . verilog ported mlite included
// . wishbone bus support
// . simple_pic (programmable interrupt controller)
// . most MIPS-I(TM) opcode support
// . do not support excption
// . do not support "unaligned memory accesses"
// . only user mode support
// . 32K byte ROM
// . 2K byte SRAM
// . UART/Timer are not fully tested yet
// . no internal tri-state bus
// TO DO
// . integrate UART
// . integrate LCD/VGA Controller
// . integrete PS/2 interface
//
//------------------------------------------------------------------------------
// Note:
// MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of
// MIPS Technologies, Inc. in the United States and other countries.
// MIPS Technologies, Inc. does not endorse and is not associated with
// this project. OpenCores and Steve Rhoads are not affiliated in any way
// with MIPS Technologies, Inc.
//------------------------------------------------------------------------------
//
// FILE: pc_next.v (tranlate from pc_next.vhd from opencores.org)
//
// Vertsion: 1.0
//
// Date: 2004/03/22
//
// Author: Yung-Fu Chen ()
//
// MODIFICATION HISTORY:
// Date By Version Change Description
//============================================================
// 2004/03/22 yfchen 1.0 Translate from pc_next.vhd
//------------------------------------------------------------------------------
//-------------------------------------------------------------------
// TITLE: Program Counter Next
// AUTHOR: Steve Rhoads ()
// DATE CREATED: 2/8/01
// FILENAME: pc_next.vhd
// PROJECT: Plasma CPU core
// COPYRIGHT: Software placed into the public domain by the author.
// Software 'as is' without warranty. Author liable for nothing.
// DESCRIPTION:
// Implements the Program Counter logic.
//-------------------------------------------------------------------
`include "yf32_define.v"
module pc_next (clk, reset, pc_new, take_branch, pause_in,
opcode25_0, pc_source, pc_out, pc_out_plus4,pc_out_next32);
input clk;
input reset;
input [31:2] pc_new;
input take_branch;
input pause_in;
input [25:0] opcode25_0;
input [ 1:0] pc_source;
output [31:0] pc_out;
output [31:0] pc_out_plus4;
output [31:0] pc_out_next32;
reg[31:2] pc_next;
// type pc_source_type is (from_inc4, from_opcode25_0, from_branch,
// from_lbranch);
reg[31:2] pc_reg;
wire [31:2] pc_inc = pc_reg + 1; //pc_reg+1
wire [31:0] pc_out = {pc_reg, 2'b00} ;
wire [31:0] pc_out_plus4 = {pc_inc, 2'b00} ;
always @(posedge clk or posedge reset)
begin
if (reset)
pc_reg <= 32'h23a; //`PC_RESET;
else
pc_reg <= pc_next;
end
always @(pc_source or pc_inc or pc_reg or opcode25_0 or
take_branch or pc_new or pause_in)
begin
case (pc_source)
`from_inc4 : pc_next = pc_inc;
`from_opcode25_0 : pc_next = {pc_reg[31:28], opcode25_0};
default : begin
//from_branch | from_lbranch =>
if (take_branch) pc_next = pc_new;
else pc_next = pc_inc;
end
endcase
if (pause_in == 1'b1)
begin
pc_next = pc_reg;
end
end
assign pc_out_next32 = {pc_next,2'b00};
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:37:23 10/06/2014
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart_rx(clk, reset, wren, rden, din, dout, rxin, addr);
input clk, reset, wren, rden;
input [7:0] din;
output [2:0] dout;
input rxin; //serial data in
input [2:0] addr;
reg [8:0] dout, frame_error;
reg [9:0] shift;
reg [7:0] control;
reg wr_baud, rd_baud, wr_fifo, rd_fifo, wr_control;
reg ld_shift, stop, count, finish, rd_shift, bittime;
reg [3:0] bittimer, bitcounter;
reg [2:0] nstate, pstate;
reg in_one, in_two, hold, frame_ready, loaded, load, clr_load;
`define period 3'b100
`define rx_reg 3'b101
`define control 3'b111
`define RXEN control[0]
`define DATARDY control[1]
`define OVERRUN control[2]
`define ERROR frame_error[8]
`define STOP shift[9]
`define START shift[0]
`define HOLD 3'b000
`define WAIT 3'b001
`define SHIFT1 3'b010
`define SHIFT2 3'b011
`define LD_FIFO 3'b100
`define RX_NOT_READY 3'b101
wire [7:0] dout_baud;
wire [8:0] dout_fifo;
wire baud, full, empty;
parameter PERIOD = 8'h1A; //must have this initial value
//baud generator
//module baudgen(wren, rden, reset, din, clk, sclr, baud, dout);
//input wren, rden, reset, clk, sclr;
//input [7:0] din;
//output baud;
//output [7:0] dout;
baudgen #(.PERIOD(PERIOD)) baud1(
.wren (wr_baud),
.rden (rd_baud),
.reset (reset),
.din (din),
.clk (clk),
.stop (stop),
.baud (baud),
.dout (dout_baud)
);
//fifo ipcore
//input clk;
//input srst;
//input [8 : 0] din;
//input wr_en;
//input rd_en;
//output [8 : 0] dout;
//output full;
//output empty;
fifo_rx fifo1(
.clk (clk),
.srst (hold),
.din (frame_error),
.wr_en (wr_fifo),
.rd_en (rd_fifo),
.dout (dout_fifo),
.full (full),
.empty (empty)
);
// input flip flops
always @(posedge clk) begin
//first flip flop
in_one <= rxin;
//second flip flop
in_two <= in_one;
end
// shift register
always @(posedge clk or posedge reset) begin
if(reset) begin
shift <= 10'b1111111111;
load = 0;
end
else begin
if(ld_shift) begin
shift <= {in_two, shift[9:1]};
load = 1;
end
else
load = 0;
end
end
// loaded flag
always @(negedge clk or posedge reset) begin
if(reset) begin
loaded = 0;
end
else begin
if(load)
loaded = 1;
if(clr_load)
loaded = 0;
end
end
// frame check
always @(posedge clk or posedge reset) begin
if(reset) begin
frame_error <= 8'b00000000;
frame_ready <= 0;
end
else begin
if(rd_shift)begin
frame_error[7:0] <= shift[8:1];
if(`START | ~`STOP)
`ERROR <= 1;
else
`ERROR <= 0;
frame_ready <= 1;
end
else
frame_ready <= 0;
end
end
//address write
always @* begin
wr_baud = 0;
wr_control = 0;
case(addr)
`period: begin
if(wren)
wr_baud = 1;
end
`control: begin
if(wren)
wr_control = 1;
end
endcase
end
//address read
always @* begin
rd_baud = 0;
rd_fifo = 0;
dout = 9'b000000000;
case(addr)
`period: begin
if(rden)
rd_baud = 1;
dout = dout_baud;
end
`rx_reg: begin
if(rden)
rd_fifo = 1;
dout = dout_fifo;
end
`control: begin
if(rden)
dout = control;
end
endcase
end
// control register
always @(posedge clk or posedge reset) begin
if(reset)
control[7:0] <= 8'b00000000;
else begin
`DATARDY <= ~empty;
if(wr_control)
control[0] <= din[0];
if(frame_ready & full)
`OVERRUN <= 1;
if(~`RXEN) begin
`DATARDY <= 0;
`OVERRUN <= 0;
end
end
end
// bittimer
always @(posedge baud or posedge reset) begin
if(reset)
bittimer <= 4'b0000;
else begin
if(bittime)
bittimer <= bittimer + 1;
end
end
// bitcounter
always @(posedge clk or posedge reset) begin
if(reset)begin
bitcounter <= 4'b0000;
end
else begin
if(count)
bitcounter <= bitcounter + 1;
if(finish)
bitcounter <= 4'b0000;
end
end
// set state during startup.
always @(posedge clk or posedge reset) begin
if (reset)
pstate <= `HOLD;
else begin
pstate <= nstate;
if(`OVERRUN)
pstate <= `RX_NOT_READY;
end
end
//fsm
always @* begin
hold = 0;
ld_shift = 0; clr_load = 0;
stop = 0; count = 0; finish = 0;
bittime = 0; rd_shift = 0; wr_fifo = 0;
nstate = pstate;
case (pstate)
`HOLD: begin
hold = 1;
stop = 1;
if(`RXEN == 1)
nstate = `WAIT;
end
`WAIT: begin
stop = 1;
if(~rxin) begin
stop = 0;
nstate = `SHIFT1;
end
end
`SHIFT1: begin
if(bitcounter == 4'b1010) begin
nstate = `LD_FIFO;
finish = 1;
rd_shift = 1;
end
else begin
if(baud)
nstate = `SHIFT2;
bittime = 1;
end
end
`SHIFT2: begin
bittime = 1;
if(bittimer == 4'b1000 & ~loaded)
ld_shift = 1;
if(~baud & (bittimer == 4'b0000)) begin
count = 1;
clr_load = 1;
nstate = `SHIFT1;
end
end
`LD_FIFO: begin
wr_fifo = 1;
nstate = `WAIT;
end
`RX_NOT_READY: begin
if(~`OVERRUN)
nstate = `HOLD;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n = 0; int answer = 0; cin >> n; int last = -1; int xs = 0, ys = 0, x = 0, y = 0; for (int i = 0; i < n; i++) { int px = x, py = y; char c; cin >> c; if (c == L ) x--; else if (c == R ) x++; else if (c == U ) y++; else y--; if (abs(x - xs) + abs(y - ys) != i - last) answer++, last = i - 1, xs = px, ys = py; } answer++; cout << answer; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NAND4_PP_SYMBOL_V
/**
* nand4: 4-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 100; int x[N], z[2 * N], n, m, k; struct node { int v, i; } y[N]; bool com(node k1, node k2) { return k1.v < k2.v; } bool f(int w) { int o = 0, i = 1, j = w, l; while (i <= n && j <= m) { if (x[i] <= y[j].v) z[++o] = x[i], i++; else z[++o] = y[j].v, j++; } while (i <= n) z[++o] = x[i], i++; while (j <= m) z[++o] = y[j].v, j++; for (i = 1, l = 0; i <= o; i += k, l++) for (j = i; j <= min(o, i + k - 1); j++) if (z[j] < l) return false; return true; } int main() { int i, l, r, mid; scanf( %d%d%d , &n, &m, &k); for (i = 1; i <= n; i++) scanf( %d , &x[i]); for (i = 1; i <= m; i++) scanf( %d , &y[i].v), y[i].i = i; sort(x + 1, x + n + 1); sort(y + 1, y + m + 1, com); if (!f(m + 1)) { puts( -1 ); return 0; } l = 0; r = m + 1; while (l + 1 < r) { mid = (l + r) / 2; if (f(mid)) r = mid; else l = mid; } printf( %d n , m - r + 1); for (i = r; i <= m; i++) printf( %d , y[i].i); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4BB_2_V
`define SKY130_FD_SC_HS__NAND4BB_2_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4bb_2 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4bb_2 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4BB_2_V
|
#include <bits/stdc++.h> using namespace std; long long max(long long a, long long b) { return a > b ? a : b; } long long a[100005]; int main() { int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } sort(a + 1, a + 1 + n); long long ans = a[n] * a[n - 1] * a[n - 2] * a[n - 3] * a[n - 4]; long long ans1 = a[n] * a[n - 1] * a[n - 2] * a[1] * a[2]; long long ans2 = a[n] * a[1] * a[2] * a[3] * a[4]; cout << max(max(ans, ans1), ans2) << endl; } } |
/*
* Copyright (c) 2014, Franck Jullien <>
* All rights reserved.
*
* Redistribution and use in source and non-source forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in non-source form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS WORK IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* WORK, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module ddr_ctrl_wrapper #(
parameter ADDR_WIDTH = 25 // Memory size = 2^ADDR_WIDTH = 32MB
)
(
// Internal interface
output rdy_o,
output idle_o,
input [31:0] adr_i,
output [31:0] adr_o,
input [31:0] dat_i,
output [31:0] dat_o,
input [3:0] sel_i,
input acc_i,
output ack_o,
input we_i,
input [3:0] buf_width_i,
output [ADDR_WIDTH-3:0] local_address_o,
output local_write_req_o,
output local_read_req_o,
output local_burstbegin_o,
output [31:0] local_wdata_o,
output [3:0] local_be_o,
output [6:0] local_size_o,
input [31:0] local_rdata_i,
input local_rdata_valid_i,
input local_reset_n_i,
input local_clk_i,
input local_ready_i
);
localparam LOCAL_ADR_WIDTH = ADDR_WIDTH-2;
function [31:0] get_mask;
input [3:0] width;
begin
get_mask = ((1 << (width)) - 1);
end
endfunction
assign local_be_o = sel_i;
assign dat_o = local_rdata_i;
assign local_address_o = we_i ? adr_i[LOCAL_ADR_WIDTH+1:2] : adr_i[LOCAL_ADR_WIDTH+1:2] & ~get_mask(buf_width_i);
assign local_wdata_o = dat_i;
reg [22:0] local_address;
reg local_write_req;
reg local_read_req;
reg local_burstbegin;
reg [31:0] local_wdata;
reg [6:0] local_size;
assign local_write_req_o = local_write_req;
assign local_read_req_o = local_read_req;
assign local_burstbegin_o = local_burstbegin;
assign local_size_o = local_size;
reg [3:0] state;
reg [31:0] count;
reg ack_w;
reg [31:0] adr;
// FSM states
localparam [3:0]
WAIT_READY = 4'h0,
IDLE = 4'h1,
WRITE = 4'h2,
READ = 4'h3;
assign rdy_o = local_ready_i;
assign idle_o = (state == IDLE);
assign adr_o = adr;
assign ack_o = acc_i ? (we_i ? ack_w : local_rdata_valid_i) : 1'b0;
always @(posedge local_clk_i) begin
if (local_reset_n_i == 1'b0) begin
local_write_req <= 1'b0;
local_read_req <= 1'b0;
local_burstbegin <= 1'b0;
local_size <= 6'b1;
count <= 0;
adr <= 32'b0;
state <= WAIT_READY;
end else begin
ack_w <= 1'b0;
local_burstbegin <= 1'b0;
local_write_req <= 1'b0;
local_burstbegin <= 1'b0;
local_read_req <= 1'b0;
case (state)
WAIT_READY: begin
if (local_ready_i)
state <= IDLE;
end
IDLE: begin
if (acc_i) begin
if (we_i & local_ready_i) begin
ack_w <= 1'b1;
local_burstbegin <= 1'b1;
local_write_req <= 1'b1;
local_size <= 1;
state <= WRITE;
end
if (!we_i & local_ready_i) begin
local_burstbegin <= 1'b1;
local_read_req <= 1'b1;
state <= READ;
local_size <= (1<<buf_width_i);
adr <= adr_i & ~get_mask(buf_width_i+2);
count <= 0;
end
end
end
WRITE : begin
state <= IDLE;
end
READ : begin
if (local_rdata_valid_i) begin
count <= count + 1'b1;
adr <= (adr & ~get_mask(buf_width_i+2)) | ((((adr >> 2) + 1) & get_mask(buf_width_i)) << 2);
end
if (count == (1<<buf_width_i)) begin
count <= 0;
state <= IDLE;
end
end
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 300005; const int MAXINT = 1073741823; vector<int> neighbors[MAXN]; int a[MAXN]; int greater_right[MAXN]; int greater_left[MAXN]; int less_right[MAXN]; int less_left[MAXN]; int dp[MAXN]; stack<int> s; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) { while (!s.empty() && a[s.top()] < a[i]) s.pop(); greater_left[i] = (s.empty() ? -1 : s.top()); s.push(i); } stack<int>().swap(s); for (int i = 0; i < n; i++) { while (!s.empty() && a[s.top()] > a[i]) s.pop(); less_left[i] = (s.empty() ? -1 : s.top()); s.push(i); } stack<int>().swap(s); for (int i = n - 1; i >= 0; i--) { while (!s.empty() && a[s.top()] < a[i]) s.pop(); greater_right[i] = (s.empty() ? -1 : s.top()); s.push(i); } stack<int>().swap(s); for (int i = n - 1; i >= 0; i--) { while (!s.empty() && a[s.top()] > a[i]) s.pop(); less_right[i] = (s.empty() ? -1 : s.top()); s.push(i); } for (int i = 0; i < n; i++) { if (greater_left[i] != -1) neighbors[greater_left[i]].push_back(i); if (greater_right[i] != -1) neighbors[i].push_back(greater_right[i]); if (less_left[i] != -1) neighbors[less_left[i]].push_back(i); if (less_right[i] != -1) neighbors[i].push_back(less_right[i]); } fill(dp, dp + n, MAXINT); dp[0] = 0; for (int i = 0; i < n; i++) for (int j : neighbors[i]) dp[j] = min(dp[j], dp[i] + 1); cout << dp[n - 1]; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DLATCH_PR_PP_PG_N_TB_V
`define SKY130_FD_SC_MS__UDP_DLATCH_PR_PP_PG_N_TB_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__udp_dlatch_pr_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg RESET;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
RESET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 RESET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 NOTIFIER = 1'b1;
#160 RESET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 NOTIFIER = 1'b0;
#260 RESET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 RESET = 1'b1;
#380 NOTIFIER = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 RESET = 1'bx;
#480 NOTIFIER = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_ms__udp_dlatch$PR_pp$PG$N dut (.D(D), .RESET(RESET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DLATCH_PR_PP_PG_N_TB_V
|
#include <bits/stdc++.h> using namespace std; int main() { int l, r; scanf( %d%d , &l, &r); if (l == r) printf( %d n , l); else puts( 2 ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_SYMBOL_V
`define SKY130_FD_SC_LP__NOR4_SYMBOL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_SYMBOL_V
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_sequencer_ram (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../altera_mem_if_ddr3_phy_0001_qsys_sequencer_sequencer_ram.hex";
output [ 31: 0] readdata;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 512,
the_altsyncram.numwords_a = 512,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 9;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "UNUSED",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 512,
// the_altsyncram.numwords_a = 512,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 9;
//
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long n, k, ans = 1e11; string s; cin >> n; if (n == 1 || n == 2) { cout << No << endl; return 0; } cout << Yes << endl; set<long long> s1, s2; for (long long i = 1; i < n + 1; i++) { i % 2 ? s1.insert(i) : s2.insert(i); } cout << s2.size() << ; for (auto i : s2) cout << i << ; cout << endl; cout << s1.size() << ; for (auto i : s1) cout << i << ; } |
module top;
reg pass, pass_f1, pass_f2, pass_f3, pass_f4, pass_f5;
reg [8*30:1] res;
initial begin
pass = 1'b1;
// Verify that the initial scope is correct.
$swrite(res, "%m");
if (res != "top") begin
$display("Failed initial, got \"%0s\"", res);
pass = 1'b0;
end
// Test %m in a named begin.
begin : my_begin
$swrite(res, "%m");
if (res != "top.my_begin") begin
$display("Failed named begin (1st), got \"%0s\"", res);
pass = 1'b0;
end
begin : my_begin_begin
// Test %m in a nested named begin.
$swrite(res, "%m");
if (res != "top.my_begin.my_begin_begin") begin
$display("Failed nested named begin, got \"%0s\"", res);
pass = 1'b0;
end
end
$swrite(res, "%m");
if (res != "top.my_begin") begin
$display("Failed named begin (2nd), got \"%0s\"", res);
pass = 1'b0;
end
// Test a named fork inside a named begin.
pass_f1 = 1'b1;
pass_f2 = 1'b1;
fork : my_begin_fork
begin
$swrite(res, "%m");
if (res != "top.my_begin.my_begin_fork") begin
$display("Failed after named begin/fork (1), got \"%0s\"", res);
pass_f1 = 1'b0;
end
end
begin
$swrite(res, "%m");
if (res != "top.my_begin.my_begin_fork") begin
$display("Failed after named begin/fork (2), got \"%0s\"", res);
pass_f2 = 1'b0;
end
end
join
pass = pass & pass_f1 & pass_f2;
$swrite(res, "%m");
if (res != "top.my_begin") begin
$display("Failed named begin (3rd), got \"%0s\"", res);
pass = 1'b0;
end
end
// Verify that the scope is back to normal.
$swrite(res, "%m");
if (res != "top") begin
$display("Failed after named begin, got \"%0s\"", res);
pass = 1'b0;
end
// Test %m in a named fork.
pass_f1 = 1'b1;
pass_f2 = 1'b1;
pass_f3 = 1'b1;
pass_f4 = 1'b1;
pass_f5 = 1'b1;
fork : my_fork
begin
$swrite(res, "%m");
if (res != "top.my_fork") begin
$display("Failed after named fork (1), got \"%0s\"", res);
pass_f1 = 1'b0;
end
end
// Test a %m in a nested named begin.
begin : my_fork_begin
$swrite(res, "%m");
if (res != "top.my_fork.my_fork_begin") begin
$display("Failed after named fork/begin, got \"%0s\"", res);
pass_f4 = 1'b0;
end
end
begin
$swrite(res, "%m");
if (res != "top.my_fork") begin
$display("Failed after named fork (2), got \"%0s\"", res);
pass_f2 = 1'b0;
end
end
fork : my_fork_fork
begin
$swrite(res, "%m");
if (res != "top.my_fork.my_fork_fork") begin
$display("Failed after named fork/fork, got \"%0s\"", res);
pass_f2 = 1'b0;
end
end
join
begin
$swrite(res, "%m");
if (res != "top.my_fork") begin
$display("Failed after named fork (3), got \"%0s\"", res);
pass_f3 = 1'b0;
end
end
join
pass = pass & pass_f1 & pass_f2 & pass_f3;
// Verify that the scope is back to normal.
$swrite(res, "%m");
if (res != "top") begin
$display("Failed final, got \"%0s\"", res);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long xl, xr, yu, yd; long long x, y; int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); long long n; cin >> n; for (int i = 0; i < n; i++) { cin >> x >> y; if (i == 0) { xl = x; xr = x; yu = y; yd = y; } else { if (x < xl) xl = x; if (x > xr) xr = x; if (y > yu) yu = y; if (y < yd) yd = y; } } long long ans = max(yu - yd, xr - xl); cout << ans * ans << endl; return 0; } |
//
// auto generated by mux_sel.py
//
// wire declaration
module uop_temp_out
(
{%-for output_name in output_lst%}
output {{output_name}},
{%-endfor%}
input wire [7:0] A0 , //src1 data
input wire [7:0] A1 , //src1 data
input wire [7:0] A2 , //src1 data
input wire [7:0] A3 , //src1 data
input wire [7:0] A4 , //src1 data
input wire [7:0] A5 , //src1 data
input wire [7:0] A6 , //src1 data
input wire [7:0] A7 , //src1 data
input wire [7:0] A8 , //src1 data
input wire [7:0] A9 , //src1 data
input wire [7:0] A10, //src1 data
input wire [7:0] A11, //src1 data
input wire [7:0] A12, //src1 data
input wire [7:0] A13, //src1 data
input wire [7:0] A14, //src1 data
input wire [7:0] A15, //src1 data
input wire [7:0] B0 , //src2 data
input wire [7:0] B1 , //src2 data
input wire [7:0] B2 , //src2 data
input wire [7:0] B3 , //src2 data
input wire [7:0] B4 , //src2 data
input wire [7:0] B5 , //src2 data
input wire [7:0] B6 , //src2 data
input wire [7:0] B7 , //src2 data
input wire [7:0] B8 , //src2 data
input wire [7:0] B9 , //src2 data
input wire [7:0] B10, //src2 data
input wire [7:0] B11, //src2 data
input wire [7:0] B12, //src2 data
input wire [7:0] B13, //src2 data
input wire [7:0] B14, //src2 data
input wire [7:0] B15, //src2 data
input wire [7:0] imm, //imm data
input wire [127:0] B, //src2 data
input wire [127:0] A, //src1 data
{%-for input_name in input_lst%}
{%-if loop.last%}
input {{input_name}}
{%-else%}
input {{input_name}},
{%-endif%}
{%-endfor%}
);
{%-for wire_name in wire_lst%}
wire {{wire_name}};
{%-endfor%}
// assignments
{%-for assign_key, assign_value in assign_dic|dictsort%}
assign {{assign_key}} = {{assign_value}};
{%-endfor%}
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// $Id: ethernet_parser.v 1976 2007-07-20 00:59:57Z grg $
//
// Module: ethernet_parser.v
// Project: NF2.1
// Description: parses the Ethernet header for a 32 or 64 bit datapath
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module ethernet_parser
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter NUM_IQ_BITS = 3,
parameter INPUT_ARBITER_STAGE_NUM = 2
)
(// --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
// --- Interface to output_port_lookup
output [47:0] dst_mac,
output [47:0] src_mac,
output [15:0] ethertype,
output eth_done,
output [NUM_IQ_BITS-1:0] src_port,
// --- Misc
input reset,
input clk
);
generate
genvar i;
if(DATA_WIDTH==64) begin: eth_parser_64bit
ethernet_parser_64bit
#(
.NUM_IQ_BITS(NUM_IQ_BITS),
.INPUT_ARBITER_STAGE_NUM(INPUT_ARBITER_STAGE_NUM))
eth_parser
(.in_data(in_data),
.in_ctrl(in_ctrl),
.in_wr(in_wr),
.dst_mac (dst_mac),
.src_mac(src_mac),
.ethertype (ethertype),
.eth_done (eth_done),
.src_port(src_port),
.reset(reset),
.clk(clk));
end // block: eth_parser_64bit
else if(DATA_WIDTH==32) begin: eth_parser_32bit
ethernet_parser_32bit
#(
.NUM_IQ_BITS(NUM_IQ_BITS),
.INPUT_ARBITER_STAGE_NUM(INPUT_ARBITER_STAGE_NUM))
eth_parser
(.in_data(in_data),
.in_ctrl(in_ctrl),
.in_wr(in_wr),
.dst_mac (dst_mac),
.src_mac(src_mac),
.ethertype (ethertype),
.eth_done (eth_done),
.src_port(src_port),
.reset(reset),
.clk(clk));
end // block: eth_parser_32bit
endgenerate
endmodule // ethernet_parser_64bit
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211OI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A211OI_FUNCTIONAL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a211oi (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211OI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; template <class T> ostream& operator<<(ostream& out, const tuple<T>& a) { out << [ << get<0>(a) << ] ; return out; } template <class T, class U> ostream& operator<<(ostream& out, const tuple<T, U>& a) { out << [ << get<0>(a) << << get<1>(a) << ] ; return out; } template <class T, class U, class V> ostream& operator<<(ostream& out, const tuple<T, U, V>& a) { out << [ << get<0>(a) << << get<1>(a) << << get<2>(a) << ] ; return out; } template <class T, class U, class V, class W> ostream& operator<<(ostream& out, const tuple<T, U, V, W>& a) { out << [ << get<0>(a) << << get<1>(a) << << get<2>(a) << << get<3>(a) << ] ; return out; } template <class T, class U> ostream& operator<<(ostream& out, const pair<T, U>& a) { out << [ << a.first << << a.second << ] ; return out; } template <class T> ostream& operator<<(ostream& out, const vector<T>& a) { out << [ ; for (auto& it : a) out << it << ; out << ] ; return out; } template <class T> ostream& operator<<(ostream& out, const set<T>& a) { out << [ ; for (auto& it : a) out << it << ; out << ] ; return out; } template <class T> ostream& operator<<(ostream& out, const multiset<T>& a) { out << [ ; for (auto& it : a) out << it << ; out << ] ; return out; } template <class T, class U> ostream& operator<<(ostream& out, const map<T, U>& a) { for (auto& it : a) out << it.first << -> << it.second << | ; return out; } template <class T, class U> ostream& operator<<(ostream& out, const multimap<T, U>& a) { for (auto& it : a) out << it.first << -> << it.second << | ; return out; } template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } void r(){}; template <typename T, typename... Args> void r(T& a, Args&... args) { cin >> a; r(args...); } void p() { cout << n ; }; template <typename T, typename... Args> void p(T& a, Args&... args) { cout << a << ; p(args...); } template <class T> T gcd(T a, T b) { return a ? gcd(b % a, a) : b; } template <class T> T lcm(T a, T b) { return ((a * b) / gcd(b % a, a)); } template <class T1, class T2> T1 binpow(T1 number, T2 power) { T1 result = number; while (power) { if (power & 1) result = result * number; number = number * number; power /= 2; } return result; } long long n; class Segtree { public: long long *tree, *lazy, *array, *color, *is_single; Segtree(long long* arr, long long sz) { array = new long long[sz]; lazy = new long long[4 * sz]; tree = new long long[4 * sz]; color = new long long[4 * sz]; is_single = new long long[4 * sz]; n = sz; for (auto i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - 2 * ((0) > (n))) array[i] = arr[i]; for (auto i = (0) - ((0) > (4 * sz)); i != (4 * sz) - ((0) > (4 * sz)); i += 1 - 2 * ((0) > (4 * sz))) tree[i] = 0; for (auto i = (0) - ((0) > (4 * sz)); i != (4 * sz) - ((0) > (4 * sz)); i += 1 - 2 * ((0) > (4 * sz))) lazy[i] = 0; for (auto i = (0) - ((0) > (4 * sz)); i != (4 * sz) - ((0) > (4 * sz)); i += 1 - 2 * ((0) > (4 * sz))) color[i] = 0; for (auto i = (0) - ((0) > (4 * sz)); i != (4 * sz) - ((0) > (4 * sz)); i += 1 - 2 * ((0) > (4 * sz))) is_single[i] = 0; build(); } void build(long long id = 1, long long l = 0, long long r = n) { if (r - l < 2) { tree[id] = 0; color[id] = array[l]; is_single[id] = 1; return; } auto mid = (l + r) / 2; build(2 * id, l, mid); build(2 * id + 1, mid, r); tree[id] = tree[2 * id] + tree[2 * id + 1]; if (color[2 * id] == color[2 * id + 1] and color[2 * id] != 0) is_single[id] = 1, color[id] = color[2 * id]; else is_single[id] = 0, color[id] = 0; } void upd(long long id, long long l, long long r, long long x, long long coloring) { lazy[id] += x; tree[id] += (r - l) * x; if (coloring != 0) color[id] = coloring; } void shift(long long id, long long l, long long r) { long long mid = (l + r) / 2; upd(id * 2, l, mid, lazy[id], color[id]); upd(id * 2 + 1, mid, r, lazy[id], color[id]); lazy[id] = 0; } long long sum(long long x, long long y, long long id = 1, long long l = 0, long long r = n) { if (l >= y or r <= x) return 0; if (l >= x and r <= y) return tree[id]; shift(id, l, r); auto mid = (l + r) / 2; return sum(x, y, 2 * id, l, mid) + sum(x, y, 2 * id + 1, mid, r); } void range_update(long long x, long long y, long long coloring, long long id = 1, long long l = 0, long long r = n) { auto mid = (l + r) / 2; if (l >= y or r <= x) return; if (x <= l and r <= y) { if (is_single[id]) { upd(id, l, r, abs(color[id] - coloring), coloring); } else { shift(id, l, r); range_update(x, y, coloring, 2 * id, l, mid); range_update(x, y, coloring, 2 * id + 1, mid, r); tree[id] = tree[2 * id] + tree[2 * id + 1]; } is_single[id] = 1; color[id] = coloring; return; } shift(id, l, r); range_update(x, y, coloring, 2 * id, l, mid); range_update(x, y, coloring, 2 * id + 1, mid, r); tree[id] = tree[2 * id] + tree[2 * id + 1]; if (color[2 * id] == color[2 * id + 1] and color[2 * id] != 0) is_single[id] = 1, color[id] = color[2 * id]; else is_single[id] = 0, color[id] = 0; } }; long long m, arr[112345], types, lef, ri, x; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); r(n, m); for (auto i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - 2 * ((0) > (n))) arr[i] = i + 1; Segtree tree(arr, n); for (auto i = (0) - ((0) > (m)); i != (m) - ((0) > (m)); i += 1 - 2 * ((0) > (m))) { r(types); if (types == 1) { r(lef, ri, x); tree.range_update(lef - 1, ri, x); } else { r(lef, ri); auto sum = tree.sum(lef - 1, ri); p(sum); } } } |
#include <bits/stdc++.h> int main() { int num, i, j, k, p; double prob[110], temp, tot, high, temp2; scanf( %d , &num); i = 0; while (i < num) { scanf( %lf , &prob[i]); i++; } i = 0; while (i < num) { p = i + 1; while (p < num) { if (prob[p] > prob[i]) { temp2 = prob[p]; prob[p] = prob[i]; prob[i] = temp2; } p++; } i++; } high = 0; i = 1; while (i <= num) { tot = 0; for (j = 0; j < i; j++) { temp = prob[j]; for (k = 0; k < i; k++) { if (j != k) temp *= 1 - prob[k]; } tot += temp; } if (tot > high) high = tot; i++; } printf( %.12f n , high); } |
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
mulRecFNToFullRaw#(parameter expWidth = 3, parameter sigWidth = 3) (
input [(`floatControlWidth - 1):0] control,
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
output invalidExc,
output out_isNaN,
output out_isInf,
output out_isZero,
output out_sign,
output signed [(expWidth + 1):0] out_sExp,
output [(sigWidth*2 - 1):0] out_sig
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaNA, isInfA, isZeroA, signA;
wire signed [(expWidth + 1):0] sExpA;
wire [sigWidth:0] sigA;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_a(a, isNaNA, isInfA, isZeroA, signA, sExpA, sigA);
wire isSigNaNA;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA);
wire isNaNB, isInfB, isZeroB, signB;
wire signed [(expWidth + 1):0] sExpB;
wire [sigWidth:0] sigB;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_b(b, isNaNB, isInfB, isZeroB, signB, sExpB, sigB);
wire isSigNaNB;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire notSigNaN_invalidExc = (isInfA && isZeroB) || (isZeroA && isInfB);
wire notNaN_isInfOut = isInfA || isInfB;
wire notNaN_isZeroOut = isZeroA || isZeroB;
wire notNaN_signOut = signA ^ signB;
wire signed [(expWidth + 1):0] common_sExpOut =
sExpA + sExpB - (1<<expWidth);
wire [(sigWidth*2 - 1):0] common_sigOut = sigA * sigB;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
assign invalidExc = isSigNaNA || isSigNaNB || notSigNaN_invalidExc;
assign out_isInf = notNaN_isInfOut;
assign out_isZero = notNaN_isZeroOut;
assign out_sExp = common_sExpOut;
`ifdef HardFloat_propagateNaNPayloads
assign out_isNaN = isNaNA || isNaNB || notSigNaN_invalidExc;
wire signNaN;
wire [(sigWidth - 2):0] fractNaN;
propagateFloatNaN_mul#(sigWidth)
propagateNaN(
control,
isNaNA,
signA,
sigA[(sigWidth - 2):0],
isNaNB,
signB,
sigB[(sigWidth - 2):0],
signNaN,
fractNaN
);
assign out_sign = out_isNaN ? signNaN : notNaN_signOut;
assign out_sig =
out_isNaN ? {1'b1, fractNaN}<<(sigWidth - 1) : common_sigOut;
`else
assign out_isNaN = isNaNA || isNaNB;
assign out_sign = notNaN_signOut;
assign out_sig = common_sigOut;
`endif
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
mulRecFNToRaw#(parameter expWidth = 3, parameter sigWidth = 3) (
input [(`floatControlWidth - 1):0] control,
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
output invalidExc,
output out_isNaN,
output out_isInf,
output out_isZero,
output out_sign,
output signed [(expWidth + 1):0] out_sExp,
output [(sigWidth + 2):0] out_sig
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaNA, isInfA, isZeroA, signA;
wire signed [(expWidth + 1):0] sExpA;
wire [sigWidth:0] sigA;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_a(a, isNaNA, isInfA, isZeroA, signA, sExpA, sigA);
wire isSigNaNA;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA);
wire isNaNB, isInfB, isZeroB, signB;
wire signed [(expWidth + 1):0] sExpB;
wire [sigWidth:0] sigB;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_b(b, isNaNB, isInfB, isZeroB, signB, sExpB, sigB);
wire isSigNaNB;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire notSigNaN_invalidExc = (isInfA && isZeroB) || (isZeroA && isInfB);
wire notNaN_isInfOut = isInfA || isInfB;
wire notNaN_isZeroOut = isZeroA || isZeroB;
wire notNaN_signOut = signA ^ signB;
wire signed [(expWidth + 1):0] common_sExpOut =
sExpA + sExpB - (1<<expWidth);
wire [(sigWidth*2 - 1):0] sigProd = sigA * sigB;
wire [(sigWidth + 2):0] common_sigOut =
{sigProd[(sigWidth*2 - 1):(sigWidth - 2)], |sigProd[(sigWidth - 3):0]};
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
assign invalidExc = isSigNaNA || isSigNaNB || notSigNaN_invalidExc;
assign out_isInf = notNaN_isInfOut;
assign out_isZero = notNaN_isZeroOut;
assign out_sExp = common_sExpOut;
`ifdef HardFloat_propagateNaNPayloads
assign out_isNaN = isNaNA || isNaNB || notSigNaN_invalidExc;
wire signNaN;
wire [(sigWidth - 2):0] fractNaN;
propagateFloatNaN_mul#(sigWidth)
propagateNaN(
control,
isNaNA,
signA,
sigA[(sigWidth - 2):0],
isNaNB,
signB,
sigB[(sigWidth - 2):0],
signNaN,
fractNaN
);
assign out_sign = out_isNaN ? signNaN : notNaN_signOut;
assign out_sig = out_isNaN ? {1'b1, fractNaN, 2'b00} : common_sigOut;
`else
assign out_isNaN = isNaNA || isNaNB;
assign out_sign = notNaN_signOut;
assign out_sig = common_sigOut;
`endif
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
mulRecFN#(parameter expWidth = 3, parameter sigWidth = 3) (
input [(`floatControlWidth - 1):0] control,
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
input [2:0] roundingMode,
output [(expWidth + sigWidth):0] out,
output [4:0] exceptionFlags
);
wire invalidExc, out_isNaN, out_isInf, out_isZero, out_sign;
wire signed [(expWidth + 1):0] out_sExp;
wire [(sigWidth + 2):0] out_sig;
mulRecFNToRaw#(expWidth, sigWidth)
mulRecFNToRaw(
control,
a,
b,
invalidExc,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig
);
roundRawFNToRecFN#(expWidth, sigWidth, 0)
roundRawOut(
control,
invalidExc,
1'b0,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig,
roundingMode,
out,
exceptionFlags
);
endmodule
|
#include <bits/stdc++.h> using namespace std; long long a[] = { 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8092, 16184, 32368, 64736, 129472, 258944, 517888, 1035776, 2071552, 4143104, 8286208, 16572416, 33144832, 66289664, 132579328, 265158656, 530317312, 1060634624, 2121269248, 4242538496, 8485076992, 16970153984, 33940307968}; int main() { int n; scanf( %d , &n); cout << a[n] << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, a, b; cin >> n >> a >> b; int position[21] = {0}; for (int i = 0; i < n; i++) cin >> position[i]; int head = 0, tail = n - 1, cost = 0; while (head <= tail) { if (position[head] != 2 && position[tail] != 2 && (position[head] != position[tail])) { cost = -1; break; } if (position[head] == 2 && position[tail] == 2 && head != tail) { if (a > b) cost += 2 * b; else cost += 2 * a; } else if (position[head] == 2 && position[tail] == 2 && head == tail) { if (a > b) cost += b; else cost += a; } else if (position[head] == 2 || position[tail] == 2) { if (position[head] == 2 && position[tail] == 0) cost += a; else if (position[head] == 2 && position[tail] == 1) cost += b; else if (position[tail] == 2 && position[head] == 0) cost += a; else if (position[tail] == 2 && position[head] == 1) cost += b; } head++; tail--; } cout << cost; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:26:25 11/01/2013
// Design Name:
// Module Name: i2s_out
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module i2s_out(input clock, input reset, input[15:0] left_data,
input[15:0] right_data, output mclk, output lrck, output sclk, output reg sdin);
wire[5:0] sclk_counter = 6'd1; // 2 - 1
wire[5:0] lrck_counter = 6'd63; // 64 - 1
reg [3:0] data_pos;
initial
begin
data_pos <= 4'b0000;
end
/** mclk es igual al clock . 50Mhz */
assign mclk = clock;
/** mclk/lrck = 64 entonces lrck se hace de 781250Hz */
clock_divider lrck_gen(
.clock(clock),
.reset(reset),
.counter(lrck_counter),
.clock_out(lrck)
);
/** sclk/lrck = 32 y mclk/sclk = 2. Entonces sclk = 25Mhz*/
clock_divider sclk_gen(
.clock(clock),
.reset(reset),
.counter(sclk_counter),
.clock_out(sclk)
);
/**
* flanco positivo de lrck = canal derecho
* flanco negativo de lrck = canal izquierdo
* los datos se mandan con sclk
**/
always @ (negedge sclk)
begin
if(lrck)
begin
if(data_pos == 4'b0000)
begin
sdin <= left_data[data_pos];
end
else
begin
sdin <= right_data[data_pos];
end
end
else
begin
if(data_pos == 4'b0000)
begin
sdin <= right_data[data_pos];
end
else
begin
sdin <= left_data[data_pos];
end
end
/** Siempre hay que cambiar la posicion */
data_pos <= data_pos - 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 7; const long long INFLL = 1e18 + 7; const long double EPS = 1e-9; const int MAXN = 1e5 + 17; mt19937 myRand(1337); mt19937_64 myRand64(1337); signed main(void) { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int k; cin >> k; int len = k / (int)1e6 + (k % (int)1e6 != 0) + 2; int r = k + len; vector<int> ans = {-1}; int m = r / (int)1e6; r = r - (r / (int)1e6) * 1e6; ans.push_back(r); for (int i = 0; i < m; ++i) { ans.push_back((int)1e6); } for (int i = 0; i < len - (int)ans.size(); ++i) ans.push_back(0); cout << (int)ans.size() << endl; for (int i : ans) cout << i << ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFSBP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fll; const int MAX = 1e3 + 10; vector<int> g[MAX]; int qt[MAX]; int dfs(int i, int p = -1) { int ret = 1; for (int j : g[i]) if (j != p) ret += dfs(j, i); return qt[i] = ret; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { int n, x; cin >> n >> x; x--; for (int i = 0; i < n; i++) g[i].clear(); int deg = 0; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; a--, b--; if (a == x or b == x) deg++; g[a].push_back(b); g[b].push_back(a); } if (deg <= 1) { cout << Ayush << n ; continue; } dfs(x); vector<int> v; for (int i : g[x]) v.push_back(qt[i]); int par = 0; for (int i : v) par += (i % 2 == 0); if (par % 2 != deg % 2) cout << Ayush << n ; else cout << Ashish << n ; } exit(0); } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); long long n, k, ans = 0; cin >> n >> k; if (k >= n / 2) ans = (n * (n - 1)) / 2; else { ans = (n * (n - 1)) / 2 - (((n - k) * (n - k - 1)) / 2) + k * (n - 2 * k) + (k * (k - 1)) / 2; } cout << ans << endl; } |
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email:
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_debug.v
// Title : Hardware debug registers and associated logic.
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// Version : 3.2
// : Fixed simulation bug which flares up when number of
// : watchpoints is zero.
// =============================================================================
`include "lm32_include.v"
`ifdef CFG_DEBUG_ENABLED
// States for single-step FSM
`define LM32_DEBUG_SS_STATE_RNG 2:0
`define LM32_DEBUG_SS_STATE_IDLE 3'b000
`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET 3'b001
`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN 3'b010
`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT 3'b011
`define LM32_DEBUG_SS_STATE_RESTART 3'b100
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_debug (
// ----- Inputs -------
clk_i,
rst_i,
pc_x,
load_x,
store_x,
load_store_address_x,
csr_write_enable_x,
csr_write_data,
csr_x,
`ifdef CFG_HW_DEBUG_ENABLED
jtag_csr_write_enable,
jtag_csr_write_data,
jtag_csr,
`endif
`ifdef LM32_SINGLE_STEP_ENABLED
eret_q_x,
bret_q_x,
stall_x,
exception_x,
q_x,
`ifdef CFG_DCACHE_ENABLED
dcache_refill_request,
`endif
`endif
// ----- Outputs -------
`ifdef LM32_SINGLE_STEP_ENABLED
dc_ss,
`endif
dc_re,
bp_match,
wp_match
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter breakpoints = 0; // Number of breakpoint CSRs
parameter watchpoints = 0; // Number of watchpoint CSRs
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input [`LM32_PC_RNG] pc_x; // X stage PC
input load_x; // Load instruction in X stage
input store_x; // Store instruction in X stage
input [`LM32_WORD_RNG] load_store_address_x; // Load or store effective address
input csr_write_enable_x; // wcsr instruction in X stage
input [`LM32_WORD_RNG] csr_write_data; // Data to write to CSR
input [`LM32_CSR_RNG] csr_x; // Which CSR to write
`ifdef CFG_HW_DEBUG_ENABLED
input jtag_csr_write_enable; // JTAG interface CSR write enable
input [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to CSR
input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
`endif
`ifdef LM32_SINGLE_STEP_ENABLED
input eret_q_x; // eret instruction in X stage
input bret_q_x; // bret instruction in X stage
input stall_x; // Instruction in X stage is stalled
input exception_x; // An exception has occured in X stage
input q_x; // Indicates the instruction in the X stage is qualified
`ifdef CFG_DCACHE_ENABLED
input dcache_refill_request; // Indicates data cache wants to be refilled
`endif
`endif
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
`ifdef LM32_SINGLE_STEP_ENABLED
output dc_ss; // Single-step enable
reg dc_ss;
`endif
output dc_re; // Remap exceptions
reg dc_re;
output bp_match; // Indicates a breakpoint has matched
wire bp_match;
output wp_match; // Indicates a watchpoint has matched
wire wp_match;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
genvar i; // Loop index for generate statements
// Debug CSRs
reg [`LM32_PC_RNG] bp_a[0:breakpoints-1]; // Instruction breakpoint address
reg bp_e[0:breakpoints-1]; // Instruction breakpoint enable
wire [0:breakpoints-1]bp_match_n; // Indicates if a h/w instruction breakpoint matched
reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1]; // Watchpoint enable
reg [`LM32_WORD_RNG] wp[0:watchpoints-1]; // Watchpoint address
wire [0:watchpoints]wp_match_n; // Indicates if a h/w data watchpoint matched
wire debug_csr_write_enable; // Debug CSR write enable (from either a wcsr instruction of external debugger)
wire [`LM32_WORD_RNG] debug_csr_write_data; // Data to write to debug CSR
wire [`LM32_CSR_RNG] debug_csr; // Debug CSR to write to
`ifdef LM32_SINGLE_STEP_ENABLED
// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
//reg [`LM32_DEBUG_SS_STATE_RNG] state; // State of single-step FSM
integer state; // State of single-step FSM
`endif
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`include "lm32_functions.v"
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Check for breakpoints
generate
for (i = 0; i < breakpoints; i = i + 1)
begin : bp_comb
assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
end
endgenerate
generate
`ifdef LM32_SINGLE_STEP_ENABLED
if (breakpoints > 0)
assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
else
assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
`else
if (breakpoints > 0)
assign bp_match = |bp_match_n;
else
assign bp_match = `FALSE;
`endif
endgenerate
// Check for watchpoints
generate
for (i = 0; i < watchpoints; i = i + 1)
begin : wp_comb
assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
end
endgenerate
generate
if (watchpoints > 0)
assign wp_match = |wp_match_n;
else
assign wp_match = `FALSE;
endgenerate
`ifdef CFG_HW_DEBUG_ENABLED
// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs
assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE);
assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
`else
assign debug_csr_write_enable = csr_write_enable_x;
assign debug_csr_write_data = csr_write_data;
assign debug_csr = csr_x;
`endif
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// Breakpoint address and enable CSRs
generate
for (i = 0; i < breakpoints; i = i + 1)
begin : bp_seq
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
bp_e[i] <= `FALSE;
end
else
begin
if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
begin
bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
bp_e[i] <= debug_csr_write_data[0];
end
end
end
end
endgenerate
// Watchpoint address and control flags CSRs
generate
for (i = 0; i < watchpoints; i = i + 1)
begin : wp_seq
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
wpc_c[i] <= `LM32_WPC_C_DISABLED;
end
else
begin
if (debug_csr_write_enable == `TRUE)
begin
if (debug_csr == `LM32_CSR_DC)
wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
if (debug_csr == `LM32_CSR_WP0 + i)
wp[i] <= debug_csr_write_data;
end
end
end
end
endgenerate
// Remap exceptions control bit
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
dc_re <= `FALSE;
else
begin
if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
dc_re <= debug_csr_write_data[1];
end
end
`ifdef LM32_SINGLE_STEP_ENABLED
// Single-step control flag
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
state <= `LM32_DEBUG_SS_STATE_IDLE;
dc_ss <= `FALSE;
end
else
begin
if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
begin
dc_ss <= debug_csr_write_data[0];
if (debug_csr_write_data[0] == `FALSE)
state <= `LM32_DEBUG_SS_STATE_IDLE;
else
state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
end
case (state)
`LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
begin
// Wait for eret or bret instruction to be executed
if ( ( (eret_q_x == `TRUE)
|| (bret_q_x == `TRUE)
)
&& (stall_x == `FALSE)
)
state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
end
`LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
begin
// Wait for an instruction to be executed
if ((q_x == `TRUE) && (stall_x == `FALSE))
state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
end
`LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
begin
// Wait for exception to be raised
`ifdef CFG_DCACHE_ENABLED
if (dcache_refill_request == `TRUE)
state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
else
`endif
if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
begin
dc_ss <= `FALSE;
state <= `LM32_DEBUG_SS_STATE_RESTART;
end
end
`LM32_DEBUG_SS_STATE_RESTART:
begin
// Watch to see if stepped instruction is restarted due to a cache miss
`ifdef CFG_DCACHE_ENABLED
if (dcache_refill_request == `TRUE)
state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
else
`endif
state <= `LM32_DEBUG_SS_STATE_IDLE;
end
endcase
end
end
`endif
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int dq[4040]; int st = 0; int dr = 0; int m[3030][3030]; int mn[3030][3030]; int N, M, K, L, X, Y, Z; long long ret = 0; void make() { for (int i = 1; i <= N; ++i) { int ind = 0; st = dr = 0; for (int j = 1; j <= M; ++j) { while (dr - st > 0 && m[i][dq[dr - 1]] > m[i][j]) { --dr; } dq[dr++] = j; while (dq[st] <= j - L) { ++st; } if (j - L >= 0) { mn[i][j - L + 1] = m[i][dq[st]]; } } } for (int j = 1; j <= M - L + 1; ++j) { st = dr = 0; for (int i = 1; i <= N; ++i) { while (dr - st > 0 && mn[dq[dr - 1]][j] > mn[i][j]) --dr; dq[dr++] = i; while (dq[st] <= i - K) ++st; if (i - K >= 0) { ret += mn[dq[st]][j]; } } } } int G[3030 * 3030]; int main() { cin.sync_with_stdio(false); cin >> N >> M >> K >> L; cin >> G[0] >> X >> Y >> Z; for (int i = 1; i <= N * M + 100; ++i) { G[i] = (1LL * G[i - 1] * X + Y) % Z; } for (int i = 1; i <= N; ++i) { for (int j = 1; j <= M; ++j) { m[i][j] = G[(i - 1) * M + j - 1]; } } make(); cout << ret << endl; } |
#include <bits/stdc++.h> using namespace std; const int maxn = (1 << 16) + 5, maxm = 125; int n, f[maxn][maxm], sa[maxn], sb[maxn], va, vb; struct node { int id, r, b; } a[20]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { char ch = getchar(); while (ch != R && ch != B ) ch = getchar(); a[i].id = (ch == B ); scanf( %d%d , &a[i].r, &a[i].b); } for (int i = 1; i < (1 << n); i++) { for (int j = 1; j <= n; j++) if (i & (1 << j - 1)) { if (a[j].id == 0) sa[i]++; else sb[i]++; ; } } for (int i = 1; i <= n; i++) va += a[i].r, vb += a[i].b; memset(f, 255, sizeof(f)); f[0][0] = 0; for (int i = 0; i < (1 << n) - 1; i++) { for (int j = 0; j <= n * (n - 1) / 2; j++) if (f[i][j] != -1) { for (int k = 1; k <= n; k++) if (!(i & (1 << k - 1))) { int p = (i | (1 << k - 1)); f[p][j + min(sa[i], a[k].r)] = max(f[p][j + min(a[k].r, sa[i])], f[i][j] + min(sb[i], a[k].b)); } } } int ans = (1 << 30); for (int i = 0; i <= n * (n - 1) / 2; i++) if (f[(1 << n) - 1][i] != -1) { ans = min(ans, max(va - i, vb - f[(1 << n) - 1][i]) + n); } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 2 * (1e5) + 10, inf = 2147483647; long long ans; int n, lastR, lastB, lastP, mxR, mxB; int main() { int x; char c; scanf( %d , &n); lastR = lastB = lastP = -inf; mxR = mxB = 0; for (int i = 1; i <= n; ++i) { scanf( %d %c n , &x, &c); if (c == R || c == P ) { if (lastR != -inf) ans += x - lastR, mxR = max(mxR, x - lastR); lastR = x; } if (c == B || c == P ) { if (lastB != -inf) ans += x - lastB, mxB = max(mxB, x - lastB); lastB = x; } if (c == P ) { if (lastP != -inf) ans += min(0, x - lastP - mxR - mxB); lastP = x; mxR = mxB = 0; } } printf( %I64d n , ans); } |
#include <bits/stdc++.h> using namespace std; const int L = 1e5 + 1; long long sofar[L], out[L]; struct node { long long l, r, q; }; long long ans = 0, counter[3000002], k; bool comp(node x, node y) { return x.r < y.r; } void add(long long val) { ans += counter[val ^ k]; counter[val]++; return; } void remove(long long val) { counter[val]--; ans -= counter[val ^ k]; return; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long a, n, m, cur = 0, l, r; cin >> n >> m >> k; for (int i = 1; i < n + 1; ++i) { cin >> a; sofar[i] ^= sofar[i - 1]; sofar[i] ^= a; } std::vector<node> v[n / 316 + 5]; node temp; for (int i = 0; i < m; ++i) { cin >> l >> r; l--, r++; temp.l = l, temp.r = r, temp.q = i; v[l / 316].push_back(temp); } for (int i = 0; i < n / 316 + 1; ++i) sort(v[i].begin(), v[i].end(), comp); for (int i = 0; i < n / 316 + 3; ++i) { l = r = i * 316; ans = 0; for (auto &x : v[i]) { while (r < x.r) { add(sofar[r]); ++r; } while (l < x.l) { remove(sofar[l]); l++; } while (l > x.l) { --l; add(sofar[l]); } out[x.q] = ans; } for (int j = l; j < r; ++j) remove(sofar[j]); } for (int i = 0; i < m; ++i) cout << out[i] << n ; return 0; } |
// Library - static, Cell - th54w322, View - schematic
// LAST TIME SAVED: May 23 18:16:51 2014
// NETLIST TIME: May 23 18:22:16 2014
`timescale 1ns / 1ns
module th54w322 ( y, a, b, c, d );
output y;
input a, b, c, d;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th54w322";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N13 ( .d(net037), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N14 ( .d(net037), .g(b), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N6 ( .d(net44), .g(d), .s(net45), .b(cds_globals.gnd_));
nfet_b N5 ( .d(net44), .g(a), .s(net037), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net044), .g(c), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net45), .g(y), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(y), .s(net037), .b(cds_globals.gnd_));
nfet_b N2 ( .d(net45), .g(b), .s(net044), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net44), .g(a), .s(net45), .b(cds_globals.gnd_));
pfet_b P12 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net047));
pfet_b P11 ( .b(cds_globals.vdd_), .g(a), .s(net036), .d(net44));
pfet_b P7 ( .b(cds_globals.vdd_), .g(b), .s(net047), .d(net036));
pfet_b P10 ( .b(cds_globals.vdd_), .g(c), .s(net047), .d(net036));
pfet_b P5 ( .b(cds_globals.vdd_), .g(y), .s(net047), .d(net036));
pfet_b P4 ( .b(cds_globals.vdd_), .g(y), .s(cds_globals.vdd_),
.d(net34));
pfet_b P3 ( .b(cds_globals.vdd_), .g(c), .s(net47), .d(net44));
pfet_b P2 ( .b(cds_globals.vdd_), .g(d), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net44);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBN_PP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFBBN_PP_SYMBOL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBN_PP_SYMBOL_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// SERDES TX and RX along with all flow control logic
module serdes
#(parameter TXFIFOSIZE = 9,
parameter RXFIFOSIZE = 9)
(input clk, input rst,
// TX side
output ser_tx_clk, output [15:0] ser_t, output ser_tklsb, output ser_tkmsb,
input [31:0] rd_dat_i, input [3:0] rd_flags_i, output rd_ready_o, input rd_ready_i,
// RX side
input ser_rx_clk, input [15:0] ser_r, input ser_rklsb, input ser_rkmsb,
output [31:0] wr_dat_o, output [3:0] wr_flags_o, output wr_ready_o, input wr_ready_i,
output [15:0] tx_occupied, output tx_full, output tx_empty,
output [15:0] rx_occupied, output rx_full, output rx_empty,
output serdes_link_up,
output [31:0] debug0,
output [31:0] debug1);
wire [15:0] fifo_space;
wire xon_rcvd, xoff_rcvd, inhibit_tx, send_xon, send_xoff, sent;
wire [31:0] debug_rx, debug_tx;
serdes_tx #(.FIFOSIZE(TXFIFOSIZE)) serdes_tx
(.clk(clk),.rst(rst),
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
.rd_dat_i(rd_dat_i),.rd_flags_i(rd_flags_i),.rd_ready_o(rd_ready_o),.rd_ready_i(rd_ready_i),
.inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff), .sent(sent),
.fifo_occupied(tx_occupied),.fifo_full(tx_full),.fifo_empty(tx_empty),
.debug(debug_tx) );
serdes_rx #(.FIFOSIZE(RXFIFOSIZE)) serdes_rx
(.clk(clk),.rst(rst),
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
.wr_dat_o(wr_dat_o),.wr_flags_o(wr_flags_o),.wr_ready_o(wr_ready_o),.wr_ready_i(wr_ready_i),
.fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd),
.fifo_occupied(rx_occupied),.fifo_full(rx_full),.fifo_empty(rx_empty),
.serdes_link_up(serdes_link_up), .debug(debug_rx) );
serdes_fc_tx serdes_fc_tx
(.clk(clk),.rst(rst),
.xon_rcvd(xon_rcvd),.xoff_rcvd(xoff_rcvd),.inhibit_tx(inhibit_tx) );
serdes_fc_rx #(.LWMARK(32),.HWMARK(128)) serdes_fc_rx
(.clk(clk),.rst(rst),
.fifo_space(fifo_space),.send_xon(send_xon),.send_xoff(send_xoff),.sent(sent) );
//assign debug = { fifo_space, send_xon, send_xoff, debug_rx[13:0] };
//assign debug = debug_rx;
assign debug0 = { { 2'b00, rd_ready_o, rd_ready_i, rd_flags_i[3:0]},
{ debug_tx[5:4] /* full,empty */ , inhibit_tx, send_xon, send_xoff, sent, ser_tkmsb, ser_tklsb},
{ ser_t[15:8] },
{ ser_t[7:0] } };
assign debug1 = { { debug_rx[7:0] }, /* odd,xfer_active,sop_i,eop_i,error_i,state[2:0] */
{ wr_flags_o[1:0], wr_ready_i, wr_ready_o, xon_rcvd, xoff_rcvd, ser_rkmsb, ser_rklsb },
{ ser_r[15:8] },
{ ser_r[7:0] } };
endmodule // serdes
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: dtysky:user:REGFILE:1.0
// IP Revision: 6
(* X_CORE_INFO = "REGFILE,Vivado 2014.2" *)
(* CHECK_LICENSE_TYPE = "MIPS_CPU_REGFILE_0_1,REGFILE,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module MIPS_CPU_REGFILE_0_1 (
clk,
clrn,
d,
we,
wn,
rna,
rnb,
qa,
qb
);
input wire clk;
input wire clrn;
input wire [31 : 0] d;
input wire we;
input wire [4 : 0] wn;
input wire [4 : 0] rna;
input wire [4 : 0] rnb;
output wire [31 : 0] qa;
output wire [31 : 0] qb;
REGFILE inst (
.clk(clk),
.clrn(clrn),
.d(d),
.we(we),
.wn(wn),
.rna(rna),
.rnb(rnb),
.qa(qa),
.qb(qb)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 300000 + 10; const long long MOD = 1000000000 + 7; const long long INF = 10000000; vector<long long> Poi; unordered_map<long long, long long> koj; long long q, SEG[4 * N][2], lazy[4 * N]; vector<pair<int, pair<long long, long long>>> Q; void modify(int id, int l, int r, int x) { if (x == -1) return; if (x == 0) { SEG[id][0] = INF; SEG[id][1] = l; lazy[id] = x; return; } if (x == 1) { SEG[id][0] = l; SEG[id][1] = INF; lazy[id] = x; return; } if (lazy[id] == -1) { swap(SEG[id][0], SEG[id][1]); lazy[id] = x; return; } if (lazy[id] == 2) { swap(SEG[id][0], SEG[id][1]); lazy[id] = -1; return; } if (lazy[id] == 0) { SEG[id][0] = l; SEG[id][1] = INF; lazy[id] = 1; return; } SEG[id][0] = INF; SEG[id][1] = l; lazy[id] = 0; return; } void shift(int id, int l, int r) { int mid = (l + r) >> 1; modify(id << 1, l, mid, lazy[id]); modify(id << 1 | 1, mid, r, lazy[id]); lazy[id] = -1; return; } void build(int id, int l, int r) { if (r - l == 1) { SEG[id][0] = l; SEG[id][1] = INF; return; } int mid = (l + r) >> 1; build(id << 1, l, mid); build(id << 1 | 1, mid, r); SEG[id][0] = l; SEG[id][1] = INF; return; } void update(int id, int lq, int rq, int x, int l, int r) { if (rq <= l || r <= lq) { return; } if (lq <= l && r <= rq) { modify(id, l, r, x); return; } int mid = (l + r) >> 1; shift(id, l, r); update(id << 1, lq, rq, x, l, mid); update(id << 1 | 1, lq, rq, x, mid, r); SEG[id][0] = min(SEG[id << 1][0], SEG[id << 1 | 1][0]); SEG[id][1] = min(SEG[id << 1][1], SEG[id << 1 | 1][1]); return; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> q; while (q--) { long long x, l, r; cin >> x >> l >> r; Poi.push_back(l); Poi.push_back(r); Poi.push_back(r + 1); Q.push_back({x, {l, r}}); } Poi.push_back(1); sort(Poi.begin(), Poi.end()); Poi.push_back(1000000000000000001); Poi.resize(unique(Poi.begin(), Poi.end()) - Poi.begin()); for (int i = 0; i < Poi.size(); i++) { koj[Poi[i]] = i + 1; } for (int i = 0; i < 4 * N; i++) { SEG[i][0] = INF; SEG[i][1] = INF; } memset(lazy, -1, sizeof lazy); build(1, 1, N); for (auto u : Q) { update(1, koj[u.second.first], koj[u.second.second] + 1, u.first - 1, 1, N); cout << Poi[SEG[1][0] - 1] << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> d[2], f; vector<vector<bool> > nab; int n, len = -1; const int INF = 1 << 29; int calc(vector<bool> &a, vector<bool> &b) { vector<bool> c(a.size() + b.size() + 1); for (int i = 0; i < b.size(); ++i) c[i] = b[i]; for (int i = b.size(); i < c.size(); ++i) c[i + 1] = a[i - (int)b.size()]; vector<int> p(c.size()); p[0] = 0; for (int i = 1; i < p.size(); ++i) { int j = p[i - 1]; while (j > 0 && (c[i] != c[j] || i == b.size() || j == b.size())) j = p[j - 1]; if (c[i] == c[j] && !(i == b.size() || j == b.size())) j++; p[i] = j; } return p[c.size() - 1]; } vector<vector<int> > p; inline int suf(vector<bool> &a, int &l) { int ans = 0; for (int i = len - l; i < len; ++i) ans |= ((int)a[i] << (i + l - len)); return ans; } inline int pref(vector<bool> &a, int &l) { int ans = 0; for (int i = 0; i < l; ++i) ans |= ((int)a[i] << i); return ans; } int main() { cin.sync_with_stdio(0); cin >> n; nab.resize(n); d[0].resize(n + 1); d[1].resize(n + 1); string str; for (int i = 0; i < n; ++i) { cin >> str; if (len == -1) len = str.size(); nab[i].resize(len); for (int j = 0; j < len; ++j) nab[i][j] = (str[j] == 0 ? 0 : 1); } p.resize(len + 1, vector<int>(1 << len, -1)); d[0][0] = d[1][0] = 0; p[0][0] = 1; vector<int> f(n); f[0] = len; for (int i = 1; i < n; ++i) f[i] = f[i - 1] + len - calc(nab[i - 1], nab[i]); int suffix[len + 1], prefix[len + 1]; d[1][1] = d[0][1] = len; int bestp, bestd, now; for (int i = 2; i <= n; ++i) { d[0][i] = min(d[0][i - 1], d[1][i - 1]) + f[i - 1] - f[i - 2]; d[1][i] = INF; for (int j = 1; j <= len; ++j) { suffix[j] = suf(nab[i - 2], j); prefix[j] = pref(nab[i - 1], j); } bestp = p[0][0]; d[1][i] = d[1][bestp] + f[i - 2] - f[bestp - 1] + len; for (int j = 1; j <= len; ++j) { int &pp = p[j][prefix[j]]; if (pp != -1) { now = d[1][pp] + f[i - 2] - f[pp - 1] + len - j; if (now < d[1][i]) { d[1][i] = now; bestp = pp; } } } if (d[1][i] < d[1][p[0][0]] + f[i - 1] - f[p[0][0] - 1]) p[0][0] = i; for (int j = 1; j <= len; ++j) { int &ps = p[j][suffix[j]]; if (ps == -1 || (d[1][i] < d[1][ps] + f[i - 1] - f[ps - 1])) ps = i; } } cout << min(d[1][n], d[0][n]); return 0; } |
#include <bits/stdc++.h> using namespace std; long long read() { long long a = 0; char c = getchar(); while (c > 9 || c < 0 ) c = getchar(); while ( 0 <= c && c <= 9 ) { a = a * 10 + c - 48; c = getchar(); } return a; } struct data { long long x, y, c; data(long long X = 0, long long Y = 0, long long C = 0) { x = X; y = Y; c = C; } } w[2005], e[2005]; long long n, k, L; bool cmp(data a, data b) { return a.x < b.x; }; bool cmp2(data a, data b) { return a.y < b.y; } long long nxt[2005], f[2005]; multiset<long long> Set[2005]; long long sum[2005 << 2], Max[2005 << 2], tag[2005 << 2]; void pushup(long long x) { sum[x] = (sum[(x << 1)] + sum[(x << 1 | 1)]) % 1000000007; assert(Max[(x << 1)] <= Max[(x << 1 | 1)]); Max[x] = Max[(x << 1 | 1)]; } void build(long long x, long long l, long long r) { tag[x] = 0; if (l == r) { sum[x] = f[l] * (e[l].y - e[l - 1].y) % 1000000007; Max[x] = f[l]; return; } build((x << 1), l, ((l + r) >> 1)); build((x << 1 | 1), ((l + r) >> 1) + 1, r); pushup(x); } void ptag(long long x, long long l, long long r, long long v) { assert(Max[x] <= v); sum[x] = v * (e[r].y - e[l - 1].y) % 1000000007; tag[x] = Max[x] = v; } void pushdown(long long x, long long l, long long r) { if (tag[x]) { ptag((x << 1), l, ((l + r) >> 1), tag[x]); ptag((x << 1 | 1), ((l + r) >> 1) + 1, r, tag[x]); tag[x] = 0; } } void chkmax(long long x, long long l, long long r, long long b, long long e, long long v) { if (r < b || l > e) return; if (l == r && Max[x] > v) return; if (Max[x] <= v && b <= l && r <= e) { ptag(x, l, r, v); return; } bool flag = (v > Max[(x << 1)]); pushdown(x, l, r); chkmax((x << 1), l, ((l + r) >> 1), b, e, v); if (flag) chkmax((x << 1 | 1), ((l + r) >> 1) + 1, r, b, e, v); pushup(x); } signed main() { n = read(); k = read(); L = read(); for (long long i = 1; i <= n; ++i) { w[i].x = read() + 1; w[i].y = read() + 1; w[i].c = read(); e[i] = w[i]; } sort(w + 1, w + 1 + n, cmp); sort(e + 1, e + 1 + n, cmp2); e[n + 1].y = L + 1; w[n + 1].x = w[n + 2].x = L + 1; w[n + 1].y = L + 1; long long ans = 0; for (long long i = n; i; --i) { long long tmp = (w[i].x - w[i - 1].x); if (!tmp) continue; multiset<long long> S; S.clear(); for (long long i = 1; i <= k; ++i) { S.insert(L + 1), nxt[i] = L + 1; Set[i].clear(); Set[i].insert(L + 1); Set[i].insert(0); } for (long long j = n; j; --j) { if (e[j].x >= w[i].x) { S.erase(S.find(nxt[e[j].c])); nxt[e[j].c] = e[j].y; S.insert(nxt[e[j].c]); Set[e[j].c].insert(e[j].y); } f[j] = (*(--S.end())); } build(1, 1, n); for (long long j = n + 1; j > i; --j) { if (w[j].c) { assert(Set[w[j].c].find(w[j].y) != Set[w[j].c].end()); Set[w[j].c].erase(Set[w[j].c].find(w[j].y)); multiset<long long>::iterator it = --Set[w[j].c].upper_bound(w[j].y), ir = it; ++ir; long long ll = lower_bound(e, e + 1 + n, data(0, *it, 0), cmp2) - e; if (ll) assert(e[ll].y != e[ll - 1].y); chkmax(1, 1, n, ll + 1, n, *ir); } long long res = ((L + 1) * e[n].y - sum[1] + 1000000007) % 1000000007; ans = (ans + (res * tmp % 1000000007 * (w[j].x - w[j - 1].x))) % 1000000007; } } printf( %lld n , ans); return 0; } |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: stage1.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module stage1 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/bachelors.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/bachelors.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage1_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( Ofast ) #pragma GCC optimize( O3 ) #pragma GCC target( avx ) const long long MOD = 1000000007; const long double PI = 3.1415926535898; const long long LIM = 100005; using namespace std; long long fpow(long long x, long long y) { long long temp; if (y == 0) return 1; temp = fpow(x, y / 2); if (y % 2 == 0) return temp * temp; else return x * temp * temp; } long long gcd(long long a, long long b) { if (b == 0) return a; return gcd(b, a % b); } void sieve(long long n) { bool prime[5 * LIM]; memset(prime, true, sizeof(prime)); for (long long p = 2; p * p <= n; p++) if (prime[p] == true) for (long long i = p * p; i <= n; i += p) prime[i] = false; prime[1] = 0; } inline long long read() { long long p = 1, ans = 0; char ch = getchar(); while (ch < 48 || ch > 57) { if (ch == - ) p = -1; ch = getchar(); } while (ch >= 48 && ch <= 57) { ans = (ans << 3) + (ans << 1) + ch - 48; ch = getchar(); } return ans * p; } bool isPrime(long long n) { if (n <= 1) return false; if (n <= 3) return true; if (n % 2 == 0 || n % 3 == 0) return false; for (long long i = 5; i * i <= n; i = i + 6) if (n % i == 0 || n % (i + 2) == 0) return false; return true; } map<long long, long long> primeFactors(long long n) { map<long long, long long> make_pair; while (n % 2 == 0) { if (make_pair.count(2) == 1) make_pair[2]++; else make_pair.insert({2, 1}); n = n / 2; } for (long long i = 3; i <= sqrt(n); i = i + 2) { while (n % i == 0) { if (make_pair.count(i) == 1) make_pair[i]++; else make_pair.insert({i, 1}); n = n / i; } } if (n > 2) { if (make_pair.count(n) == 1) make_pair[n]++; else make_pair.insert({n, 1}); } return make_pair; } long long compare(string a, string b) { if (a.empty()) return 0; for (long long i = 0; i < a.length(); i++) { if (a[i] > b[i]) return 1; else if (a[i] < b[i]) return -1; } return 0; } bool isPalindrome(string str) { long long l = 0; long long h = str.length() - 1; while (h > l) { if (str[l++] != str[h--]) { return false; } } return true; } long long maxSum(vector<long long> a) { long long max_so_far = a[0]; long long curr_max = a[0]; for (long long i = 1; i < a.size(); i++) { curr_max = max(a[i], curr_max + a[i]); max_so_far = max(max_so_far, curr_max); } return max_so_far; } long long maxlength(vector<long long> a) { long long size = a.size(); long long max_so_far = INT_MIN, max_ending_here = 0, start = 0, end = 0, s = 0; for (long long i = 0; i < size; i++) { max_ending_here += a[i]; if (max_so_far < max_ending_here) { max_so_far = max_ending_here; start = s; end = i; } if (max_ending_here <= 0) { max_ending_here = 0; s = i + 1; } } return (end - start + 1); } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; for (long long tt = 1; tt <= t; ++tt) { long long n, r, p, s, cnt = 0; cin >> n >> r >> p >> s; string str; cin >> str; vector<char> ans(n, A ); for (long long i = 0; i < str.length(); i++) { if (str[i] == R && p > 0) { ans[i] = P ; cnt++; p--; } if (str[i] == P && s > 0) { ans[i] = S ; cnt++; s--; } if (str[i] == S && r > 0) { ans[i] = R ; cnt++; r--; } } if (cnt < ceil(n / 2.0)) cout << NO << n ; else { cout << YES << n ; for (long long i = 0; i < n; i++) { if (ans[i] == A ) { if (p > 0) { ans[i] = P ; p--; } else if (r > 0) { ans[i] = R ; r--; } else if (s > 0) { ans[i] = S ; s--; } } cout << ans[i]; } cout << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; const int N = 2e5 + 5; struct tree { int l, r, add, lv, rv; ll sum; } tr[N << 2]; int n, q, a[N]; void Add(int rt, int x) { tr[rt].lv = tr[rt].rv = tr[rt].add = x; tr[rt].sum = 1ll * (tr[rt].r - tr[rt].l + 1) * x; } void Pushdown(int rt) { if (tr[rt].add) { Add(rt << 1, tr[rt].add); Add(rt << 1 | 1, tr[rt].add); tr[rt].add = 0; } } void Pushup(int rt) { tr[rt].lv = tr[rt << 1].lv; tr[rt].rv = tr[rt << 1 | 1].rv; tr[rt].sum = tr[rt << 1].sum + tr[rt << 1 | 1].sum; } void Build(int rt, int l, int r) { tr[rt].l = l, tr[rt].r = r; if (l == r) { tr[rt].sum = tr[rt].lv = tr[rt].rv = a[l]; tr[rt].add = 0; return; } int mid = (l + r) >> 1; Build(rt << 1, l, mid), Build(rt << 1 | 1, mid + 1, r); Pushup(rt); } void Modify(int rt, int x, int y) { if (tr[rt].l > x) return; if (tr[rt].rv >= y) return; if (tr[rt].lv <= y && tr[rt].r <= x) return Add(rt, y); Pushdown(rt); Modify(rt << 1, x, y), Modify(rt << 1 | 1, x, y); Pushup(rt); } int Ask(int rt, int x, int &y) { if (y < tr[rt].rv || tr[rt].r < x) return 0; int ret = 0; if (tr[rt].l >= x && tr[rt].sum <= y) return y -= tr[rt].sum, x = tr[rt].r + 1, tr[rt].r - tr[rt].l + 1; if (tr[rt].l == tr[rt].r) return 0; Pushdown(rt); ret += Ask(rt << 1, x, y); ret += Ask(rt << 1 | 1, x, y); return ret; } int main() { scanf( %d%d , &n, &q); for (int i = 1; i <= n; ++i) scanf( %d , a + i); Build(1, 1, n); while (q--) { int op, x, y; scanf( %d%d%d , &op, &x, &y); if (op == 1) Modify(1, x, y); else printf( %d n , Ask(1, x, y)); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class c> struct rge { c b, e; }; template <class c> rge<c> range(c i, c j) { return rge<c>{i, j}; } template <class c> auto dud(c* x) -> decltype(cerr << *x, 0); template <class c> char dud(...); struct debug { template <class c> debug& operator<<(const c&) { return *this; } }; template <class T> void clr(T& a, int n) { a.clear(); a.resize(n + 1); } void solve(); const int N = 2e5 + 10; const int INF = 1e9; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; while (t--) { solve(); } } int n; void solve() { cin >> n; vector<long long> a(n + 1); for (int i = int(1); i <= int(n); i++) { cin >> a[i]; } const int B = 20; vector<long long> count(B + 1); for (int i = int(1); i <= int(n); i++) { for (int j = int(0); j <= int(B); j++) { long long mask = (1ll << j); count[j] += (mask & a[i] ? 1 : 0); } } debug() << [ << count : << (count) << ] ; long long ans = 0; for (int i = int(1); i <= int(n); i++) { long long curr = 0; for (int j = int(0); j <= int(B); j++) { if (count[j] == 0) continue; curr += (1ll << j); count[j]--; } ans += curr * curr; } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 5500; int n, T; double p[MAX_N]; int t[MAX_N]; double dq[MAX_N]; int main() { scanf( %d%d , &n, &T); for (int i = 0; i < n; i++) { scanf( %lf%d , &p[i], &t[i]); p[i] /= 100; } vector<double> cur(T + 1), nxt(T + 1); double exp = 0; cur[0] = 1; for (int i = 0; i < n; i++) { double prb = 0; double f = 1.0; int s1 = 0, s2 = 0; for (int j = 0; j < t[i] - 1; j++) { f *= 1.0 - p[i]; } for (int j = 0; j <= T; j++) { double poped = 0; if (s2 - s1 > t[i] - 1) { poped = dq[s1]; prb -= f * dq[s1]; s1++; } nxt[j] = f * poped + prb * p[i]; dq[s2] = cur[j]; s2++; prb = (1.0 - p[i]) * prb + cur[j]; } exp += i * prb; cur.swap(nxt); fill(nxt.begin(), nxt.end(), 0); } printf( %.15f n , exp + n * accumulate(cur.begin(), cur.end(), 0.0)); } |
#include <bits/stdc++.h> using namespace std; int power(int a, int b) { if (b == 0) return 1; else if (b % 2 == 0) return power((a * a) % 1000000007, b / 2); else return (a * power((a * a) % 1000000007, b / 2) % 1000000007); } int main() { std::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t = 1; cin >> t; while (t--) { int n, x, i, m, res, a; cin >> n >> x; set<int> s; m = INT_MIN; bool flag = false; for (i = 0; i < n; i++) { cin >> a; s.insert(a); m = max(m, a); if (x == a) flag = true; } if (flag) { cout << 1 n ; continue; } res = x / m; if (x % m) cout << max(2, res + 1) << n ; else cout << res << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41O_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A41O_PP_BLACKBOX_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a41o (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41O_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } template <class T> inline T LCM(T a, T b) { if (a < 0) return LCM(-a, b); if (b < 0) return LCM(a, -b); return a * (b / gcd(a, b)); } vector<int> arr; const int N = 50005; int memo[5001]; int save[N]; int visit[N]; int find(int pos, int &xr) { for (int i = 0; i < N; i++) visit[i] = 0; vector<int> toAdd; int end = pos; visit[arr[pos]] = 1; for (int i = 0; i < pos; i++) { visit[arr[i]] = 2; } if (visit[arr[pos]] == 2) { return -1; } bool cant = false; for (int i = pos; i < arr.size(); i++) { if (visit[arr[i]] == 2) { cant = true; } if (visit[arr[i]] == 1) { if (cant) return -1; for (int j = 0; j < toAdd.size(); j++) { visit[toAdd[j]] = 1; } toAdd.clear(); end = i; } else { toAdd.push_back(arr[i]); } } xr = 0; for (int i = 0; i < N; i++) { if (visit[i] == 1) { xr = xr ^ i; } } return end; } int solve(int from) { int txr = 0; int ret = 0; if (from >= arr.size()) return 0; if (memo[from] != -1) { return memo[from]; } int end = find(from, txr); if (end != -1) { ret = max(txr + solve(end + 1), solve(from + 1)); } else { ret = solve(from + 1); } memo[from] = ret; return ret; } int main() { int n, i, temp, j; for (i = (int)0; i < (int)5001; ++i) { memo[i] = -1; } scanf( %d , &n); for (i = (int)0; i < (int)n; ++i) { scanf( %d , &temp); arr.push_back(temp); } int xx; cout << solve(0); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_4_V
`define SKY130_FD_SC_HD__NOR4B_4_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4b_4 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_4_V
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_ldc
(
pll_hr_clk,
pll_dq_clk,
pll_dqs_clk,
dll_phy_delayctrl,
afi_clk,
avl_clk,
adc_clk,
adc_clk_cps,
hr_clk
);
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = 0;
parameter ADC_INVERT_PHASE = "false";
parameter IS_HHP_HPS = "false";
input pll_hr_clk;
input pll_dq_clk;
input pll_dqs_clk;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
output afi_clk;
output avl_clk;
output adc_clk;
output adc_clk_cps;
output hr_clk;
wire phy_clk_dqs;
wire phy_clk_dq;
wire phy_clk_hr;
wire phy_clk_dqs_2x;
wire phy_clk_addr_cmd;
wire phy_clk_addr_cmd_cps;
generate
if (IS_HHP_HPS == "true") begin
assign phy_clk_hr = pll_hr_clk;
assign phy_clk_dq = pll_dq_clk;
assign phy_clk_dqs = pll_dqs_clk;
assign phy_clk_dqs_2x = 1'b0;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk ({pll_hr_clk, pll_dq_clk, pll_dqs_clk, 1'b0}),
.outclk ({phy_clk_hr, phy_clk_dq, phy_clk_dqs, phy_clk_dqs_2x})
);
end
endgenerate
wire [3:0] leveled_dqs_clocks;
wire [3:0] leveled_hr_clocks;
wire hr_seq_clock;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_dqs),
.delayctrlin (dll_phy_delayctrl),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
assign afi_clk = leveled_dqs_clocks[0];
cyclonev_leveling_delay_chain leveling_delay_chain_hr (
.clkin (phy_clk_hr),
.delayctrlin (),
.clkout(leveled_hr_clocks)
);
defparam leveling_delay_chain_hr.physical_clock_source = "HR";
assign avl_clk = leveled_hr_clocks[0];
cyclonev_clk_phase_select clk_phase_select_addr_cmd (
.clkin(leveled_dqs_clocks),
.clkout(adc_clk_cps)
);
defparam clk_phase_select_addr_cmd.physical_clock_source = "ADD_CMD";
defparam clk_phase_select_addr_cmd.use_phasectrlin = "false";
defparam clk_phase_select_addr_cmd.phase_setting = ADC_PHASE_SETTING;
defparam clk_phase_select_addr_cmd.invert_phase = ADC_INVERT_PHASE;
cyclonev_clk_phase_select clk_phase_select_hr (
.phasectrlin(),
.phaseinvertctrl(),
.dqsin(),
`ifndef SIMGEN
.clkin (leveled_hr_clocks[0]),
`else
.clkin (leveled_hr_clocks),
`endif
.clkout (hr_seq_clock)
);
defparam clk_phase_select_hr.physical_clock_source = "HR";
defparam clk_phase_select_hr.use_phasectrlin = "false";
defparam clk_phase_select_hr.phase_setting = 0;
assign hr_clk = hr_seq_clock;
generate
if (ADC_INVERT_PHASE == "true")
begin
assign adc_clk = ~leveled_dqs_clocks[ADC_PHASE_SETTING];
end else begin
assign adc_clk = leveled_dqs_clocks[ADC_PHASE_SETTING];
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1e-10; struct rec { double x, y; } a[110], s, e, f[2]; int g[2], n, m, i; double ans; double XJ(rec a, rec b, rec c) { return (b.x - a.x) * (c.y - a.y) - (b.y - a.y) * (c.x - a.x); } double dist(rec a, rec b) { return sqrt((a.x - b.x) * (a.x - b.x) + (a.y - b.y) * (a.y - b.y)); } void cross(rec a, rec b, rec c, rec d) { double t1 = XJ(a, c, b), t2 = XJ(a, b, d), t3 = XJ(c, a, d), t4 = XJ(c, d, b); if (fabs(t1) < eps && fabs(t2) < eps) return; if (fabs(dist(a, c) + dist(b, c) - dist(a, b)) < eps) { f[m] = c; g[m++] = i; return; } if (t1 * t2 > eps && t3 * t4 > eps) { f[m].x = (t1 * d.x + t2 * c.x) / (t1 + t2); f[m].y = (t1 * d.y + t2 * c.y) / (t1 + t2); g[m++] = i; return; } } double calc(int st, int ed, int s, int e) { if (ed == 1) ed = n; else ed--; double ans = dist(f[s], a[st]); for (int i = st; i != ed; i == n ? i = 1 : i++) ans += dist(a[i], a[i == n ? 1 : i + 1]); return ans + dist(a[ed], f[e]); } int main() { scanf( %lf%lf%lf%lf%d , &s.x, &s.y, &e.x, &e.y, &n); for (i = 1; i <= n; i++) cin >> a[i].x >> a[i].y; a[0] = a[n]; for (i = 1; i <= n; i++) cross(s, e, a[i - 1], a[i]); if (m > 1) { if (dist(s, f[0]) > dist(s, f[1])) swap(f[0], f[1]), swap(g[0], g[1]); ans = min(calc(g[0], g[1], 0, 1), calc(g[1], g[0], 1, 0)); ans = min(ans, 2 * dist(f[0], f[1])); ans += dist(s, f[0]) + dist(f[1], e); } else ans = dist(s, e); printf( %.10lf n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T1> void deb(T1 e) { cout << e << endl; } template <class T1, class T2> void deb(T1 e1, T2 e2) { cout << e1 << << e2 << endl; } template <class T1, class T2, class T3> void deb(T1 e1, T2 e2, T3 e3) { cout << e1 << << e2 << << e3 << endl; } template <class T1, class T2, class T3, class T4> void deb(T1 e1, T2 e2, T3 e3, T4 e4) { cout << e1 << << e2 << << e3 << << e4 << endl; } template <class T1, class T2, class T3, class T4, class T5> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5) { cout << e1 << << e2 << << e3 << << e4 << << e5 << endl; } template <class T1, class T2, class T3, class T4, class T5, class T6> void deb(T1 e1, T2 e2, T3 e3, T4 e4, T5 e5, T6 e6) { cout << e1 << << e2 << << e3 << << e4 << << e5 << << e6 << endl; } template <class T> T Abs(T x) { return x > 0 ? x : -x; } template <class T> inline T sqr(T x) { return x * x; } long long Pow(long long B, long long P) { long long R = 1; while (P > 0) { if (P % 2 == 1) R = (R * B); P /= 2; B = (B * B); } return R; } long long BigMod(long long B, long long P, long long M) { long long R = 1; while (P > 0) { if (P % 2 == 1) { R = (R * B) % M; } P /= 2; B = (B * B) % M; } return R; } long long n, m; vector<pair<long long, long long> > v; long long mod = 1000000007LL; long long stree[4 * 200050]; map<long long, int> M; set<long long> S; void update(int node, int left, int right, int pos, long long val) { if (pos < left || right < pos) return; if (left == right) { stree[node] = val; return; } int mid = (left + right) / 2; update(node * 2, left, mid, pos, val); update(node * 2 + 1, mid + 1, right, pos, val); stree[node] = stree[node * 2] % mod + stree[node * 2 + 1] % mod; return; } long long query(int node, int left, int right, int srch_l, int srch_r) { if (srch_l <= left && right <= srch_r) return stree[node]; if (right < srch_l || left > srch_r) return 0; int mid = (left + right) / 2; long long ret1 = query(node * 2, left, mid, srch_l, srch_r); ret1 %= mod; long long ret2 = query(node * 2 + 1, mid + 1, right, srch_l, srch_r); ret2 %= mod; long long ret = (ret1 + ret2) % mod; return ret; } vector<int> adj[200050]; int main(void) { long long a, b; cin >> n >> m; for (int i = 0; i < m; i++) { cin >> a >> b, v.push_back(make_pair(a, b)); S.insert(a); S.insert(b); } S.insert(0); S.insert(n); int track = 0; for (__typeof((S).begin()) it = (S.begin()); it != (S).end(); ++it) M[*it] = track++; n = (int)M.size() - 1; update(1, 0, n, 0, 1); for (int i = 0; i < (int)v.size(); i++) { long long right = v[i].second; right = M[right]; adj[right].push_back(i); } for (int i = 1; i < (int)M.size(); i++) { long long val = 0; for (int j = 0; j < (int)adj[i].size(); j++) { int indx = adj[i][j]; int left = v[indx].first; int right = v[indx].second; left = M[left]; right = M[right]; val += query(1, 0, n, left, right); val %= mod; } update(1, 0, n, i, val); } deb(query(1, 0, n, n, n)); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_SN_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_SN_SYMBOL_V
/**
* udp_dlatch$PSa_pp$sN: Positive level sensitive D-type -latch with
* active low
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dlatch$PSa_pp$sN (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_ASYNC ,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input SLEEP_B ,
input NOTIFIER_REG
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DLATCH_PSA_PP_SN_SYMBOL_V
|
`timescale 1ns / 1ns
/******************************************************************************
* (C) Copyright 2016 AGH UST All Rights Reserved
*
* MODULE: clk_divider
* DEVICE: general
* PROJECT: stopwatch
*
* ABSTRACT: The clock divider module. Assuming 100MHz input clock
*
* HISTORY:
* 1 Jan 2016, RS - initial version
* 7 Jan 2016, HG - dodano parametr FREQ pozwalajacy
na ustalenie pozadanej czestotliwosci
*
*******************************************************************************/
module clk_divider
# ( parameter
FREQ = 100 // clock freqency
)
(
input wire clk100MHz, // input clock 100 MHz
input wire rst, // async reset active high
output reg clk_div // output clock
);
// when the counter should restart from zero
localparam LOOP_COUNTER_AT = 1_000_000 / 2 / (FREQ/100) ;
reg [clog2(LOOP_COUNTER_AT)-1:0] count;
always @( posedge(clk100MHz), posedge(rst) )
begin
if(rst)
begin : counter_reset
count <= #1 0;
clk_div <= #1 1'b0;
end
else
begin : counter_operate
if (count == (LOOP_COUNTER_AT - 1))
begin : counter_loop
count <= #1 0;
clk_div <= #1 ~clk_div;
end
else
begin : counter_increment
count <= #1 count + 1;
clk_div <= #1 clk_div;
end
end
end
// function to calculate number of bits necessary to store the number
// (ceiling of base 2 logarithm)
function integer clog2(input integer number);
begin
clog2 = 0;
while (number)
begin
clog2 = clog2 + 1;
number = number >> 1;
end
end
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { { int t; cin >> t; long long int a[t]; for (int i = 0; i < t; i++) { cin >> a[i]; if (a[i] % 2 == 0 && a[i] != 0) cout << a[i] - 1 << ; else cout << a[i] << ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; struct Point { long long x, y; int type; void get(int t) { cin >> x >> y; type = t; } }; int N, M; Point R[500], B[500], P[1000], pivot; bool used[500]; Point operator-(Point p1, Point p2) { return Point{p1.x - p2.x, p1.y - p2.y}; } int quadrant(Point p) { if (p.x >= 0 && p.y >= 0) return 1; if (p.x <= 0 && p.y >= 0) return 2; if (p.x <= 0 && p.y <= 0) return 3; return 4; } long long cross(Point p1, Point p2) { return p1.x * p2.y - p1.y * p2.x; } bool operator<(Point p1, Point p2) { if (quadrant(p1 - pivot) != quadrant(p2 - pivot)) return quadrant(p1 - pivot) < quadrant(p2 - pivot); return cross(p1 - pivot, p2 - pivot) > 0; } int main() { while (cin >> N >> M) { for (int i = 0; i < N; i++) R[i].get(0); for (int i = 0; i < M; i++) B[i].get(1); memset(used, 0, sizeof(used)); int x = 0; for (int i = 0; i < N; i++) { used[i] = 1; pivot = R[i]; int cnt = 0; for (int j = 0; j < N; j++) if (!used[j]) P[cnt++] = R[j]; for (int j = 0; j < M; j++) P[cnt++] = B[j]; sort(P, P + cnt); for (int j = 0; j < cnt; j++) { if (P[j].type == 0) { int last = -1; for (int k = (j + 1) % cnt; k != j; k = (k + 1) % cnt) { bool ok = (last == -1 || cross(P[last] - P[j], P[k] - P[j]) > 0); if (P[k].type == 0) { if (cross(P[j] - R[i], P[k] - R[i]) < 0) break; if (ok) x++; } else if (ok) last = k; } } } } cout << x << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string table; string hand; getline(cin, table, n ); transform(table.begin(), table.end(), table.begin(), ::tolower); getline(cin, hand, n ); transform(hand.begin(), hand.end(), hand.begin(), ::tolower); if (hand.find(table[0]) != -1 || hand.find(table[1]) != -1) { cout << YES ; } else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long s, x, a, ans = 1; void setup() { cin >> s >> x; a = s - x; if (a & 1) { cout << 0; exit(0); } a >>= 1; } void xuly() { long long k = a; while (x) { if (x & 1) { if (a & 1) { cout << 0; return; } ans <<= 1; } x >>= 1; a >>= 1; } if (k == 0) ans -= 2; cout << ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); setup(); xuly(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_PP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor2b (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A );
and and0 (and0_out_Y , not0_out, B_N );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2B_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int nax = 1e2 + 5; string s; int n, k; int bonus[26][26]; const int inf = 1e9; long long int cnt = 0; int dp[nax][26][nax]; int solve(int i, int prev, int changes) { if (i >= s.length()) return 0; if (dp[i][prev][changes] != -inf) return dp[i][prev][changes]; int ans = -inf; if (changes < k) { for (int c = 0; c < 26; c++) { ans = max(ans, bonus[prev][c] + solve(i + 1, c, changes + ((c == (s[i] - a )) ? 0 : 1))); } } else ans = max(ans, bonus[prev][s[i] - a ] + solve(i + 1, (s[i] - a ), changes)); return dp[i][prev][changes] = ans; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> s >> k >> n; for (int i = 0; i < nax; i++) { for (int c = 0; c < 26; c++) { for (int j = 0; j < nax; j++) { dp[i][c][j] = -inf; } } } memset(bonus, 0, sizeof(bonus)); for (int i = 0; i < n; i++) { char x, y; int b; cin >> x >> y >> b; bonus[x - a ][y - a ] = b; } int ans = -inf; if (k > 0) { for (int c = 0; c < 26; c++) { ans = max(ans, solve(1, c, ((c == (s[0] - a )) ? 0 : 1))); } } else ans = max(ans, solve(1, s[0] - a , 0)); cout << ans << n ; } |
`timescale 1ns / 100ps
/* This test module works by tickling various inputs over a sequence of time.
* If the output waveforms graphically, each test scenario is uniquely
* identified by a number on the `scenario_o` bus.
*/
module test();
reg clk_o;
reg rst_o;
reg [7:0] scenario_o;
reg [1:0] mode_o;
reg d_o;
reg stb_o;
wire q_i;
/* Device Under Test */
GPIA_BIT dut (
.clk_i(clk_o),
.res_i(rst_o),
.mode_i(mode_o),
.d_i(d_o),
.stb_i(stb_o),
.q_o(q_i)
);
/* Initial models will correspond to a 12.5MHz system clock, to make it as
* close to the Kestrel-3's initial hardware configuration as possible.
* Alternative synthesis targets may want to adjust this setting if it affects
* how the circuit is synthesized. I have no experience with ASICs or large,
* mega-FPGAs, so I'm ignorant of its effects in those contexts.
*/
always begin
#20 clk_o <= ~clk_o;
end
/* Everything on the Wishbone bus happens on the rising edge of the clock.
* I'm not personally a fan of this approach, but it works well in an FPGA
* context. This task is responsible for synchronizing these unit tests
* against Wishbone's expectations of when a new cycle starts.
*/
task waitclk;
begin @(negedge clk_o); @(posedge clk_o);
end
endtask
/* About half of the test cases cover a reset bit, and the other half when
* the bit is set. This task fakes a Wishbone bus transaction which sets
* the bit.
*/
task setq;
begin
rst_o <= 0;
mode_o <= 0;
d_o <= 1;
stb_o <= 1;
waitclk;
end
endtask
/* The scenario tests commence here. */
initial begin
clk_o <= 0;
rst_o <= 0;
scenario_o <= 8'h00;
mode_o <= 0;
d_o <= 0;
stb_o <= 0;
$dumpfile("test.vcd");
$dumpvars;
/* Given a reset GPIA, all outputs MUST be low. */
@(posedge clk_o);
scenario_o <= 8'h01;
rst_o <= 1;
waitclk;
rst_o <= 0;
waitclk;
if(q_i == 1) begin
$display("FAIL 01: Q not 0"); $finish;
end
/* Given a reset GPIA, followed by a write of '0', q_i MUST
* become '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h10;
waitclk;
rst_o <= 0;
mode_o <= 0;
d_o <= 0;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 10: Q must remain 0"); $finish;
end
/* Given a reset GPIA, followed by a set-bit of '0', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h14;
waitclk;
rst_o <= 0;
mode_o <= 1;
d_o <= 0;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 14: Q must remain 0"); $finish;
end
/* Given a reset GPIA, followed by a clr-bit of '0', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h18;
waitclk;
rst_o <= 0;
mode_o <= 2;
d_o <= 0;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 18: Q must remain 0"); $finish;
end
/* Given a reset GPIA, followed by a tgl-bit of '0', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h1C;
waitclk;
rst_o <= 0;
mode_o <= 3;
d_o <= 0;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 1C: Q must remain 0"); $finish;
end
/* Given a reset GPIA, followed by a write of '1', q_i MUST
* become '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h20;
waitclk;
rst_o <= 0;
mode_o <= 0;
d_o <= 1;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i == 0) begin
$display("FAIL 20: Q not 1 on write"); $finish;
end
/* Given a reset GPIA, followed by a set-bit of '1', q_i MUST
* become '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h24;
waitclk;
rst_o <= 0;
mode_o <= 1;
d_o <= 1;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i == 0) begin
$display("FAIL 24: Q not 1 on set-bit"); $finish;
end
/* Given a reset GPIA, followed by a clr-bit of '1', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h28;
waitclk;
rst_o <= 0;
mode_o <= 2;
d_o <= 1;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i == 1) begin
$display("FAIL 28: a cleared Q must remain 0"); $finish;
end
/* Given a reset GPIA, followed by a tgl-bit of '1', q_i MUST
* become '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h2C;
waitclk;
rst_o <= 0;
mode_o <= 3;
d_o <= 1;
stb_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 1) begin
$display("FAIL 2C: a cleared Q must toggle to 1"); $finish;
end
/* Given a reset GPIA with a set output bit,
* and followed by a write of '0', q_i MUST
* reset to '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h30;
waitclk;
setq;
d_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 30: Q must reset to 0"); $finish;
end
/* Given a reset GPIA with set output bit,
* followed by a set-bit of '0', q_i MUST
* remain '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h34;
waitclk;
setq;
d_o <= 0;
mode_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 1) begin
$display("FAIL 34: Q must remain 0"); $finish;
end
/* Given a reset GPIA with set output bit,
* followed by a clr-bit of '0', q_i MUST
* remain '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h38;
waitclk;
setq;
mode_o <= 2;
d_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 1) begin
$display("FAIL 38: Q must remain 1"); $finish;
end
/* Given a reset GPIA with set output bit,
* followed by a tgl-bit of '0', q_i MUST
* remain '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h3C;
waitclk;
setq;
mode_o <= 3;
d_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 1) begin
$display("FAIL 3C: Q must remain 1"); $finish;
end
/* Given a reset GPIA with set output bit,
* followed by a write of '1', q_i MUST
* remain '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h40;
waitclk;
setq;
mode_o <= 0;
d_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i == 0) begin
$display("FAIL 40: Q not 1 on write"); $finish;
end
/* Given a reset GPIA with set output bit,
* followed by a set-bit of '1', q_i MUST
* remain '1'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h44;
waitclk;
setq;
mode_o <= 1;
d_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 1) begin
$display("FAIL 44: Q not 1 on set-bit"); $finish;
end
/* Given a reset GPIA with set output bit,
* followed by a clr-bit of '1', q_i MUST
* become '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h48;
waitclk;
setq;
mode_o <= 2;
d_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 48: a set Q must become 0"); $finish;
end
/* Given a reset GPIA with a set output bit,
* followed by a tgl-bit of '1', q_i MUST
* become '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h4C;
waitclk;
setq;
mode_o <= 3;
d_o <= 1;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 4C: a set Q must toggle to 0"); $finish;
end
/* Given a reset GPIA with clear output bit,
* a reset STB input,
* followed by a write of '1', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h50;
waitclk;
mode_o <= 0;
d_o <= 1;
stb_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 50: Q shouldn't be affected on masked write"); $finish;
end
/* Given a reset GPIA with clear output bit,
* a reset STB input,
* followed by a set-bit of '1', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h54;
waitclk;
mode_o <= 1;
d_o <= 1;
stb_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 54: Q shouldn't be affected on masked write"); $finish;
end
/* Given a reset GPIA with clear output bit,
* a reset STB input,
* followed by a clear-bit of '1', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h58;
waitclk;
mode_o <= 2;
d_o <= 1;
stb_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 58: Q shouldn't be affected on masked write"); $finish;
end
/* Given a reset GPIA with clear output bit,
* a reset STB input,
* followed by a toggle of '1', q_i MUST
* remain '0'.
*/
waitclk;
rst_o <= 1;
scenario_o <= 8'h5C;
waitclk;
mode_o <= 0;
d_o <= 1;
stb_o <= 0;
waitclk;
#2; /* let simulation catch up */
if(q_i != 0) begin
$display("FAIL 5C: Q shouldn't be affected on masked write"); $finish;
end
$display("PASS"); $finish;
end
endmodule
|
/*******************************************************************************
* Function: Packet-->Memory Mapped Transaction Converter
* Author: Andreas Olofsson
* License: MIT (see LICENSE file in OH! repository)
*
* Documentation:
*
* see ./enoc_pack.v for packet formatting
*
******************************************************************************/
module enoc_unpack
#(parameter AW = 32, // address width
parameter PW = 104) // packet width
(
//Input packet
input [PW-1:0] packet_in,
//Write
output cmd_write,//start write
output cmd_write_stop,//stop burst
//Read
output cmd_read,
//Atomic read/write
output cmd_atomic_add,
output cmd_atomic_and,
output cmd_atomic_or,
output cmd_atomic_xor,
output cmd_cas,
//Command Fields
output [3:0] cmd_opcode,//raw opcode
output [3:0] cmd_length,//bust length(up to 16)
output [2:0] cmd_size,//size of each transfer
output [7:0] cmd_user, //user field
//Address/Data
output [AW-1:0] dstaddr, // read/write target address
output [AW-1:0] srcaddr, // read return address
output [2*AW-1:0] data // write data
);
wire [15:0] cmd;
//############################################
// Command Decode
//############################################
enoc_decode enoc_decode (//Input
.cmd_in (cmd[15:0]),
// Outputs
.cmd_write (cmd_write),
.cmd_write_stop (cmd_write_stop),
.cmd_read (cmd_read),
.cmd_cas (cmd_cas),
.cmd_atomic_add (cmd_atomic_add),
.cmd_atomic_and (cmd_atomic_and),
.cmd_atomic_or (cmd_atomic_or),
.cmd_atomic_xor (cmd_atomic_xor),
.cmd_opcode (cmd_opcode[3:0]),
.cmd_user (cmd_user[7:0]),
.cmd_length (cmd_length[3:0]),
.cmd_size (cmd_size[2:0]));
generate
//######################
// 16-Bit ("lite/apb like")
//######################
if(AW==16) begin : aw16
if(PW==40) begin : p40
assign cmd[7:0] = packet_in[7:0];
assign cmd[15:8] = 8'b0;
assign dstaddr[15:0] = packet_in[23:8];
assign srcaddr[15:0] = packet_in[39:24];
assign data[31:0] = {16'b0,packet_in[39:24]};
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw16
//######################
// 32-Bit
//######################
if(AW==32) begin : aw32
if(PW==80) begin: p80
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[31:0] = packet_in[79:48];
assign data[31:0] = packet_in[79:48];
assign data[63:32] = 32'b0;
end
else if(PW==112) begin: p112
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[31:0] = packet_in[79:48];
assign data[63:0] = packet_in[111:48];
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw32
//######################
// 64-Bit
//######################
if(AW==64) begin : aw64
if(PW==144) begin: p144
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[63:0] = packet_in[111:48];
assign data[127:0] = packet_in[111:48];
assign dstaddr[63:32] = packet_in[143:112];
assign data[127:64] = 64'b0;
end
else if(PW==208) begin: p208
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[63:0] = packet_in[111:48];
assign data[63:0] = packet_in[111:48];
assign dstaddr[63:32] = packet_in[143:112];
assign data[127:64] = packet_in[207:144];
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw64
//######################
// 128-Bit
//######################
if(AW==128) begin : aw128
if(PW==272) begin: p272
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[63:0] = packet_in[111:48];
assign data[63:0] = packet_in[111:48];
assign dstaddr[63:32] = packet_in[143:112];
assign data[127:64] = packet_in[207:144];
assign srcaddr[127:64] = packet_in[207:144];
assign dstaddr[127:64] = packet_in[271:208];
assign data[255:128] = 128'b0;
end
else if(PW==400) begin: p400
assign cmd[15:0] = packet_in[15:0];
assign dstaddr[31:0] = packet_in[47:16];
assign srcaddr[63:0] = packet_in[111:48];
assign data[63:0] = packet_in[111:48];
assign dstaddr[63:32] = packet_in[143:112];
assign data[127:64] = packet_in[207:144];
assign srcaddr[127:64] = packet_in[207:144];
assign dstaddr[127:64] = packet_in[271:208];
assign data[255:128] = packet_in[399:272];
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw128
endgenerate
endmodule // enoc_unpack
|
#include <bits/stdc++.h> using namespace std; using ll = long long int; const int N = 2e5 + 10; int n, k, a[N], b[N], idx[N], kp = -1; char lc = a - 1, res[N]; int main() { ios_base::sync_with_stdio(false), cout.tie(nullptr), cin.tie(nullptr); cin >> n >> k; for (int i = 0; i < n; i++) { cin >> a[i]; idx[a[i]] = i; } for (int i = 0; i < n; i++) { cin >> b[i]; } for (int i = 0; i < n; i++) { if (kp < i && k > 0) { lc++; k--; } res[b[i]] = lc; kp = max(kp, idx[b[i]]); } if (k == 0) { cout << YES n << (res + 1); } else { cout << NO n ; } } |
#include <bits/stdc++.h> using namespace std; long long int n, m, modu = 1e9 + 7, prod = 1, sum = 0; long long int power(long long int x, long long int y) { if (y == 0) return 1; if (y & 1) return (x * power((x * x) % modu, y >> 1)) % modu; return power((x * x) % modu, y >> 1); } long long int combine(long long int n, long long int r) { long long int p1 = 1, p2 = 1; for (int i = 1; i <= n; i++) p1 = (p1 * i) % modu; for (int i = 1; i <= r; i++) p2 = (p2 * i) % modu; for (int i = 1; i <= (n - r); i++) p2 = (p2 * i) % modu; return (p1 * (power(p2, modu - 2))) % modu; } int main() { cin >> n >> m; int prev = 0; vector<int> aa; for (int i = 0; i < m; i++) { long long int x; cin >> x; aa.push_back(x); } sort(aa.begin(), aa.end()); for (int i = 0; i < m; i++) { long long int a = aa[i]; long long int c = a; a = a - prev - 1; if (a > 0) { sum += a; if (i > 0 && i <= m - 1) prod = (prod * power(2, a - 1)) % modu; prod = (prod * combine(sum, a)) % modu; } prev = c; } if (n - prev > 0) { sum += (n - prev); prod = (prod * (combine(sum, n - prev))) % modu; } cout << prod << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311OI_0_V
`define SKY130_FD_SC_LP__A311OI_0_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311oi_0 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311oi_0 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311OI_0_V
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module add4_LA(a, b, c_in, sum, c_out, P, G);
input [3:0] a, b;
input c_in;
output [3:0] sum;
output c_out;
output P, G;
wire [2:0] c;
wire [3:0] p, g;
fulladder_LA f0(a[0], b[0], c_in, sum[0], p[0], g[0]);
fulladder_LA f1(a[1], b[1], c[0], sum[1], p[1], g[1]);
fulladder_LA f2(a[2], b[2], c[1], sum[2], p[2], g[2]);
fulladder_LA f3(a[3], b[3], c[2], sum[3], p[3], g[3]);
lookahead l1(c_in, c_out, c, p, g, P, G);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { string s; cin >> s; set<char> st; for (int i = 0; i < s.size(); i++) { if (s[i] == s[i + 1]) { i++; } else { st.insert(s[i]); } } for (auto it : st) { cout << it; } cout << n ; } void withtest() { int t; cin >> t; while (t--) { solve(); } return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); withtest(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100005; int val[maxn]; int sito[maxn]; int main() { ios::sync_with_stdio(false); for (int i = 0; i < maxn; i++) { sito[i] = true; } vector<int> v; sito[0] = sito[1] = false; for (int i = 2; i < maxn; i++) { if (sito[i]) { v.push_back(i); if (i < 1000) { for (int j = i * i; j < maxn; j += i) { sito[j] = false; } } } } int n; cin >> n; for (int i = 0; i < n; i++) { cin >> val[i]; val[i]--; } vector<pair<int, int> > ss; for (int i = 0; i < n;) { int pos = i; if (pos == val[pos]) { i++; continue; } while (pos != val[pos]) { int l = 0, r = v.size() - 1; int best = 0; while (l <= r) { int mid = (l + r) / 2; if (pos + v[mid] - 1 <= val[pos]) { l = mid + 1; best = max(best, v[mid] - 1); } else { r = mid - 1; } } ss.push_back(make_pair(pos + 1, pos + best + 1)); swap(val[pos], val[pos + best]); pos += best; } } cout << ss.size() << endl; for (int i = 0; i < ss.size(); i++) { cout << ss[i].first << << ss[i].second << n ; } } |
#include <bits/stdc++.h> using namespace std; bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } long long int gcd(long long int a, long long int b) { if (b == 0) return a; return gcd(b, a % b); } long long int lcm(long long int a, long long int b) { return a * b / gcd(a, b); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { string s; cin >> s; int flag0 = 0, flag2 = 0, sum = 0; for (long long int i = 0; i < s.length(); i++) { if ((s[i] == 0 ) && (flag0 == 0)) flag0 = 1; else if (int(s[i] - 0 ) % 2 == 0) flag2 = 1; sum += int(s[i] - 0 ); } if ((flag0) && (flag2) && (sum % 3 == 0)) cout << red << n ; else cout << cyan << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { int n, i, u; cin >> n >> u; long long int a[n + 2]; bool pos = false; double res = 0; for (i = 0; i < n + 1; ++i) { cin >> a[i]; } int j = 0; for (int i = 0; i < n - 2; i++) { j = max(j, i + 2); while (j + 1 < n && a[j + 1] - a[i] <= u) j++; if (a[j] - a[i] <= u) { res = max(res, (double(a[j] - a[i + 1])) / (double(a[j] - a[i]))); pos = true; } } if (pos) cout << fixed << setprecision(10) << res; else cout << -1 ; return; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); solve(); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
bit global_bit;
module t (clk);
input clk;
integer cyc=0;
typedef struct packed {
bit b1;
bit b0;
} strp_t;
typedef struct packed {
strp_t x1;
strp_t x0;
} strp_strp_t;
typedef union packed {
strp_t x1;
strp_t x0;
} unip_strp_t;
typedef bit [2:1] arrp_t;
typedef arrp_t [4:3] arrp_arrp_t;
typedef strp_t [4:3] arrp_strp_t;
typedef bit arru_t [2:1];
typedef arru_t arru_arru_t [4:3];
typedef arrp_t arru_arrp_t [4:3];
typedef strp_t arru_strp_t [4:3];
strp_t v_strp;
strp_strp_t v_strp_strp;
unip_strp_t v_unip_strp;
arrp_t v_arrp;
arrp_arrp_t v_arrp_arrp;
arrp_strp_t v_arrp_strp;
arru_t v_arru;
arru_arru_t v_arru_arru;
arru_arrp_t v_arru_arrp;
arru_strp_t v_arru_strp;
real v_real;
real v_arr_real [2];
string v_string;
typedef struct packed {
logic [31:0] data;
} str32_t;
str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0
initial v_str32x2[0] = 32'hff;
initial v_str32x2[1] = 0;
p #(.PARAM(2)) p2 ();
p #(.PARAM(3)) p3 ();
always @ (posedge clk) begin
cyc <= cyc + 1;
v_strp <= ~v_strp;
v_strp_strp <= ~v_strp_strp;
v_unip_strp <= ~v_unip_strp;
v_arrp_strp <= ~v_arrp_strp;
v_arrp <= ~v_arrp;
v_arrp_arrp <= ~v_arrp_arrp;
v_real <= v_real + 0.1;
v_string <= "foo";
v_arr_real[0] <= v_arr_real[0] + 0.2;
v_arr_real[1] <= v_arr_real[1] + 0.3;
for (integer b=3; b<=4; b++) begin
v_arru[b] <= ~v_arru[b];
v_arru_strp[b] <= ~v_arru_strp[b];
v_arru_arrp[b] <= ~v_arru_arrp[b];
for (integer a=3; a<=4; a++) begin
v_arru_arru[a][b] = ~v_arru_arru[a][b];
end
end
v_str32x2[0] <= v_str32x2[0] - 1;
v_str32x2[1] <= v_str32x2[1] + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module p;
parameter PARAM = 1;
initial global_bit = 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 100000 + 10; const int maxm = 100000 + 10; vector<int> adj[maxn]; int fa[maxn][18], dep[maxn]; void trans(int prev, int u) { dep[u] = dep[prev] + 1; fa[u][0] = prev; for (int i = 1; (1 << i) <= dep[u]; i++) { fa[u][i] = fa[fa[u][i - 1]][i - 1]; } int len = adj[u].size(); for (int i = 0; i < len; i++) { int v = adj[u][i]; if (v == prev) continue; trans(u, v); } } int lca(int u, int v) { if (dep[u] > dep[v]) swap(u, v); for (int i = 0; (1 << i) <= dep[v] - dep[u]; i++) { if ((dep[v] - dep[u]) & 1 << i) v = fa[v][i]; } if (u == v) return u; for (int i = 18; i >= 0; i--) { if ((1 << i) <= dep[u] && fa[u][i] != fa[v][i]) { u = fa[u][i]; v = fa[v][i]; } } return fa[u][0]; } int dis(int u, int v) { int fff = lca(u, v); return dep[u] + dep[v] - 2 * dep[fff]; } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 2; i <= n; i++) { int j; scanf( %d , &j); adj[i].push_back(j); adj[j].push_back(i); } dep[1] = 0; trans(1, 1); for (int i = 0; i < m; i++) { int q[3]; for (int i = 0; i < 3; i++) scanf( %d , &q[i]); int a[3], ttt = 0; for (int i = 0; i < 3; i++) { for (int j = i + 1; j < 3; j++) { a[ttt++] = lca(q[i], q[j]); } } int k = 0; for (int i = 0; i < 3; i++) if (dep[a[i]] > dep[a[k]]) k = i; k = a[k]; int ans = 0; for (int i = 0; i < 3; i++) ans = max(ans, dis(k, q[i])); printf( %d n , ans + 1); } return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module flt_frac_test
(
input clk,
input rstn,
input [31:0] afl,
output reg frac_flag
);
reg [47:0] mant;
always @* begin
if(afl[30]) mant = {1'b1, afl[22:0]} << (afl[30:23] - 127);
else mant = {1'b1, afl[22:0]} >> (127 - afl[30:23]);
end
always @(posedge clk, negedge rstn) begin
if(!rstn) frac_flag <= 1'b0;
else begin
if(|mant[23:0]) frac_flag <= 1'b1;
else frac_flag <= 1'b0;
/*
casex(afl[30:23])
8'b0111_1011: frac_flag <= 1'b1; // .0001
8'b0111_1100: frac_flag <= 1'b1; // .001x
8'b0111_1101: frac_flag <= 1'b1; // .01xx
8'b0111_1110: frac_flag <= 1'b1; // .1xxx
8'b0111_1111: frac_flag <= |afl[22:19]; // 1.xxxx
8'b1000_0000: frac_flag <= |afl[21:18]; // 1x.xxxx
8'b1000_0001: frac_flag <= |afl[20:17]; // 1xx.xxxx
8'b1000_0010: frac_flag <= |afl[19:16]; // 1xxx.xxxx
8'b1000_0011: frac_flag <= |afl[18:15];
8'b1000_0100: frac_flag <= |afl[17:14];
8'b1000_0101: frac_flag <= |afl[16:13];
8'b1000_0110: frac_flag <= |afl[15:12];
8'b1000_0111: frac_flag <= |afl[14:11];
8'b1000_1000: frac_flag <= |afl[13:10];
8'b1000_1001: frac_flag <= |afl[12:9];
8'b1000_1010: frac_flag <= |afl[11:8];
8'b1000_1011: frac_flag <= |afl[10:7];
8'b1000_1100: frac_flag <= |afl[9:6];
8'b1000_1101: frac_flag <= |afl[8:5];
8'b1000_1110: frac_flag <= |afl[7:4];
8'b1000_1111: frac_flag <= |afl[6:3];
8'b1001_0000: frac_flag <= |afl[5:2];
8'b1001_0001: frac_flag <= |afl[4:1];
8'b1001_0010: frac_flag <= |afl[3:0];
8'b1001_0011: frac_flag <= |afl[2:0];
8'b1001_0100: frac_flag <= |afl[1:0];
8'b1001_0101: frac_flag <= afl[0];
8'b1001_011x: frac_flag <= 1'b0;
8'b101x_xxxx: frac_flag <= 1'b0;
8'b11xx_xxxx: frac_flag <= 1'b0;
default: frac_flag <= 1'b0;
endcase
*/
end
end
endmodule
|
/*
# Seven-Segment Display Decoder #
Decodes a single 4-bit word into the LED set to display it on a seven-segment
display. The display format is below:
```
--6--
| |
1 5
| |
--0--
| |
2 4
| |
--3--
```
*/
module SevenSegment (
input wire [3:0] data,
output reg [6:0] display
);
always @(data) begin
case (data)
4'h0 : display <= 7'b1111110;
4'h1 : display <= 7'b0110000;
4'h2 : display <= 7'b1101101;
4'h3 : display <= 7'b1111001;
4'h4 : display <= 7'b0110011;
4'h5 : display <= 7'b1011011;
4'h6 : display <= 7'b1011111;
4'h7 : display <= 7'b1110000;
4'h8 : display <= 7'b1111111;
4'h9 : display <= 7'b1111011;
4'hA : display <= 7'b1110111;
4'hB : display <= 7'b0011111;
4'hC : display <= 7'b1001110;
4'hD : display <= 7'b0111101;
4'hE : display <= 7'b1001111;
4'hF : display <= 7'b1000111;
default : display <= 7'b1111110;
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long re = 0, flag = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) flag = -1; ch = getchar(); } while (isdigit(ch)) re = (re << 1) + (re << 3) + ch - 0 , ch = getchar(); return re * flag; } long long n, mx, m, ans; namespace seg { long long seg[1000010]; inline void update(long long num) { seg[num] = seg[num << 1] + seg[num << 1 | 1]; } inline void add(long long l, long long r, long long num, long long pos) { if (l == r) { seg[num] = 1; return; } long long mid = (l + r) >> 1; if (mid >= pos) add(l, mid, num << 1, pos); else add(mid + 1, r, num << 1 | 1, pos); update(num); } inline long long query(long long l, long long r, long long ql, long long qr, long long num) { if (l >= ql && r <= qr) return seg[num]; long long mid = (l + r) >> 1, re = 0; if (mid >= ql) re += query(l, mid, ql, qr, num << 1); if (mid < qr) re += query(mid + 1, r, ql, qr, num << 1 | 1); return re; } } // namespace seg struct node { long long x, y; } a[200010]; inline bool cmp1(const node &a, const node &b) { return a.x < b.x; } inline bool cmp2(const node &a, const node &b) { if (a.y != b.y) return a.y < b.y; return a.x > b.x; } int main() { n = read(); long long i, j, k; for (i = 1; i <= n; i++) a[i].x = read(), a[i].y = read(); sort(a + 1, a + n + 1, cmp1); for (i = 1; i <= n; i = j + 1) { m++; j = i; while (j < n && a[j + 1].x == a[i].x) a[++j].x = m; a[i].x = m; } sort(a + 1, a + n + 1, cmp2); for (i = 1; i <= n; i = j + 1) { mx++; j = i; while (j < n && a[j + 1].y == a[i].y) a[++j].y = mx; a[i].y = mx; } reverse(a + 1, a + n + 1); for (i = 1; i <= n; i = j + 1) { j = i; while (j < n && a[j + 1].y == a[i].y) j++; for (k = i; k <= j; k++) { seg::add(1, m, 1, a[k].x); } for (k = i; k <= j; k++) { ans += seg::query(1, m, ((k == i) ? 1 : a[k - 1].x + 1), a[k].x, 1) * seg::query(1, m, a[k].x, m, 1); } } cout << ans << n ; } |
module MUX4_1_5bit(Sel,S0,S1,S2,S3,out);
input [1:0] Sel;
input [4:0] S0,S1,S2,S3;
output [4:0]out;
assign out = (Sel[1]?(Sel[0]?S3:S2) : (Sel[0]?S1:S0));
endmodule
module MUX4_1_32bit(Sel,S0,S1,S2,S3,out);
input [1:0] Sel;
input [31:0] S0,S1,S2,S3;
output [31:0]out;
assign out = (Sel[1]?(Sel[0]?S3:S2) : (Sel[0]?S1:S0));
endmodule
module Multiple_Cycles_CPU(
input Clk,
output [31:0] PC_in,PC_out,Mem_addr_in,Mem_data_out,IR_out,AddrReg_out,Mem_data_shift,Reg_data_shift,Shift_out,
output [31:0]A_in,B_in,ALU_out,ALUShift_out,Rs_out,Rt_out,Rd_in,
output [4:0] Rt_addr,Rd_addr,Rs_addr,
output [2:0] condition,ALU_SrcB,
output [3:0] ALU_op,Rd_write_byte_en,Mem_byte_write,
output [1:0] RegDst,MemtoReg,PC_source,Shift_op,
output ALU_SrcA,Ex_top,Shift_amountSrc,ALUShift_Sel,PC_write_cond,PC_write_en,IorD,IR_write_en,Addreg_write_en,
output Zero,Less,Overflow,PC_write,
output [3:0] state,
output RegDt0
);
PC pc(PC_in,PC_out,Clk,PC_write_en);
Instru_Control instruc_control(Less,Zero,PC_write_cond,PC_write,condition,PC_source,
IR_out[25:0],PC_out[31:28],ALUShift_out,AddrReg_out,Rs_out,PC_in,PC_write_en);
Controller controller(Clk,Overflow,IR_out,AddrReg_out[1:0],condition,ALU_SrcB,ALU_op,Rd_write_byte_en,Mem_byte_write,RegDst,MemtoReg,PC_source,Shift_op,
ALU_SrcA,Ex_top,Shift_amountSrc,ALUShift_Sel,PC_write_cond,PC_write,IorD,IR_write_en,Addreg_write_en,RegDt0,state);
assign Mem_addr_in = (IorD == 1'b1)?(AddrReg_out):(PC_out);
Memory memory(Reg_data_shift,Mem_addr_in,Mem_byte_write, Clk,Mem_data_out);
IRegister iregister(Mem_data_out,IR_out,Clk,IR_write_en);//Instructin Register
Register_ShiftOutput register_shiftOutput(Rt_out,Mem_addr_in[1:0],IR_out[31:26],Reg_data_shift);
Memory_ShiftOutput memory_shiftOutput(Mem_data_out,Mem_addr_in[1:0],IR_out[31:26],Mem_data_shift);
ExNumber exnumber(IR_out[15:0],Ex_top,ALU_SrcB,Rt_out,B_in);//位拓展模块
MUX4_1_5bit mux4_1_5bit_1(RegDst,IR_out[20:16],IR_out[15:11],5'b11111,5'b0,Rd_addr);
assign Rt_addr = (RegDt0 == 1'b1) ? 5'b0 : IR_out[20:16];
assign Rs_addr = IR_out[25:21];
MUX4_1_32bit mux4_1_32bit_1(MemtoReg,AddrReg_out,Mem_data_shift,ALU_out,32'b0,Rd_in);
MIPS_Register register(Rs_addr, Rt_addr, Rd_addr, Clk, Rd_write_byte_en, Rd_in, Rs_out, Rt_out);
assign A_in = (ALU_SrcA == 1'b1)?Rs_out:PC_out;
ALU alu(A_in,B_in,ALU_op,Zero,Less,Overflow,ALU_out);
wire [4:0] Shift_amount;
assign Shift_amount = (Shift_amountSrc == 1'b1) ? Rs_out[4:0] : IR_out[10:6];
MIPS_Shifter barrel_shifter(Rt_out,Shift_amount,Shift_op,Shift_out);
assign ALUShift_out = (ALUShift_Sel == 1'b1)? Shift_out: ALU_out;
AddrReg addrReg(ALUShift_out, Addreg_write_en, Clk, AddrReg_out);
endmodule |
#include <bits/stdc++.h> using namespace std; map<int, int> m; int main() { map<int, int>::iterator ptr; int n, i, x, a[3]; cin >> n; for (i = 0; i < n; i++) { cin >> x; m[x]++; } if (m.size() > 3) { cout << NO ; return 0; } if (m.size() <= 2) { cout << YES ; return 0; } i = 0; for (ptr = m.begin(); ptr != m.end(); ptr++) a[i++] = ptr->first; if ((a[0] + a[2]) == (2 * a[1])) cout << YES ; else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long base = 139; const long long M = 1000012309; long long p[200007]; vector<pair<long long, char> > vp1; vector<pair<long long, char> > vp2; long long hashtable[200007], hv, cnt = 0; void pcal() { p[0] = 1; for (long long i = 1; i < 200007; ++i) p[i] = (p[i - 1] * base) % M; } void hashfunc() { hashtable[0] = (vp1[0].first * vp1[0].second) % M; ; long long sz1 = vp1.size(); long long sz2 = vp2.size() - 2; long long sz3 = vp2.size(); for (long long i = 1; i < sz1; ++i) { long long val = (vp1[i].first * vp1[i].second) % M; hashtable[i] = ((hashtable[i - 1] * base) % M + val) % M; } for (long long i = 0; i < sz1 - 1; ++i) { long long l = i + 1; long long r = i + sz2; if (vp1[i].second == vp2[0].second && vp1[i].first >= vp2[0].first && r < sz1 - 1) { long long bad = (hashtable[l - 1] * p[r - l + 1]) % M; long long check = (hashtable[r] - bad + M) % M; if (check == hv && vp1[r + 1].second == vp2[sz3 - 1].second && vp1[r + 1].first >= vp2[sz3 - 1].first) cnt++; } } } int main() { long long n, m; cin >> n >> m; long long d; char c, a; pcal(); for (long long i = 0; i < n; ++i) { cin >> d >> c >> a; if (i == 0) vp1.push_back({d, a}); else { long long sz = vp1.size(); if (a == vp1[sz - 1].second) vp1[sz - 1].first += d; else vp1.push_back({d, a}); } } for (long long i = 0; i < m; ++i) { cin >> d >> c >> a; if (i == 0) vp2.push_back({d, a}); else { long long sz = vp2.size(); if (a == vp2[sz - 1].second) vp2[sz - 1].first += d; else vp2.push_back({d, a}); } } if (vp1.size() < vp2.size()) { cout << 0 << endl; return 0; } else if (vp2.size() == 1) { long long sz1 = vp1.size(); cnt = 0; for (long long i = 0; i < sz1; ++i) { if (vp2[0].second == vp1[i].second && vp2[0].first <= vp1[i].first) cnt += vp1[i].first - vp2[0].first + 1; } cout << cnt << endl; } else if (vp2.size() == 2) { long long sz1 = vp1.size(); cnt = 0; for (long long i = 0; i < sz1 - 1; ++i) { if (vp2[0].second == vp1[i].second && vp2[1].second == vp1[i + 1].second) if (vp2[0].first <= vp1[i].first && vp2[1].first <= vp1[i + 1].first) cnt++; } cout << cnt << endl; } else if (vp2.size() > 2) { long long sz = vp2.size(); cnt = 0; hv = (vp2[0].first * vp2[0].second) % M; for (long long i = 1; i < sz - 1; ++i) { long long d = vp2[i].first; long long a = vp2[i].second; long long val = (d * a) % M; hv = ((hv * base) % M + val) % M; } long long bad = ((vp2[0].first * vp2[0].second) % M * p[sz - 2]) % M; hv = (hv - bad + M) % M; hashfunc(); cout << cnt << endl; } } |
// Filename: channel_tb2.v
// Author: Danny Dutton
// Date: 03/23/15
// Version: 1
// Description: Module connecting transmit to receive. This uses a clock of
// insufficent period to ensure that the parity gen cant keep up.
`timescale 1ns/100ps
module channel_tb2();
reg enable; // Enable for counter
reg clear; // Clear for counter
reg clk_en; // Clock enable
wire clk; // Wire connecting clock to counter and both regs
wire[9:0] data; // Bus connecting transmit and receive modules
wire[8:0] data_out; // Data output of receive
wire data_valid; // Output of comparator from receive module
// Transmit module containing counter and parity gen.
transmit DUT1(enable, clear, clk, data);
// Receive module containing reg, parity gen, and comparator
receive DUT2(clk, data, data_out, data_valid);
// Clock feeding counter and both regs, period set to 10
clk #(17) DUT3(clk_en, clk);
// Using similar inputs as ctr_tb.v
initial begin
enable = 0;
clear = 0;
clk_en = 1;
//#10 clear = 1;
//#40 clear = 0;
#50 enable = 1;
//#400 enable = 0;
//#100 enable = 1;
//#500 clear = 1;
//#60 clear = 0;
end
endmodule |
#include <bits/stdc++.h> using namespace std; struct fenwick { int N; vector<int> sum; void init(int n) { N = n + 1; sum.assign(N, 0); } void add(int i, int x) { for (i++; i < N; i += i & -i) { sum[i] += x; } } int get(int i) { int tot = 0; for (i++; i > 0; i -= i & -i) { tot += sum[i]; } return tot; } int get(int i, int j) { return get(j) - (i > 0 ? get(i - 1) : 0); } }; fenwick xs; int lo, hi; bool flip; void init(int n, int x) { xs.init(n); for (int i = 0; i < n; i++) { xs.add(i, x); } lo = 0; hi = n - 1; } int len() { return hi - lo + 1; } int get(int i) { i = !flip ? lo + i : hi - i; return xs.get(i, i); } int get(int i, int j) { if (!flip) { i += lo; j += lo; } else { i = hi - i; j = hi - j; swap(i, j); } return xs.get(i, j); } void add(int i, int x) { i = !flip ? lo + i : hi - i; xs.add(i, x); } void drop(int k) { if (!flip) { lo += k; } else { hi -= k; } } void dump() { int n = len(); for (int i = 0; i < n; i++) { cerr << get(i) << ; } cerr << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n, q; cin >> n >> q; init(n, 1); while (q--) { int t, i, j; cin >> t >> i; if (t == 1) { if (i > len() / 2) { i = len() - i; flip = !flip; } for (int k = 0; i - 1 - k >= 0; k++) { add(i + k, get(i - 1 - k)); } drop(i); } else { cin >> j; cout << get(i, j - 1) << n ; } } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [1:0] in = crc[1:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [1:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[1:0]),
// Inputs
.in (in[1:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {62'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'hbb2d9709592f64bd
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [1:0] in;
output reg [1:0] out;
always @* begin
// bug99: Internal Error: ../V3Ast.cpp:495: New node already linked?
case (in[1:0])
2'd0, 2'd1, 2'd2, 2'd3: begin
out = in;
end
endcase
end
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n; string s1, s2; cin >> n >> s1 >> s2; long long count = 0; for (long long i = 0; i < n / 2; i++) { char a[4] = {s1[i], s1[n - i - 1], s2[i], s2[n - i - 1]}; if ((a[0] == a[1] and a[2] == a[3]) || (a[0] == a[3] and a[1] == a[2]) || (a[0] == a[2] and a[1] == a[3])) count += 0; else if ((a[0] == a[2] and a[1] != a[3]) || (a[0] == a[3] and a[1] != a[2]) || (a[0] != a[2] and a[1] == a[3]) || (a[0] != a[3] and a[1] == a[2]) || (a[0] != a[1] and a[2] == a[3])) count += 1; else count += 2; } if (n % 2 == 1) count += (s1[n / 2] != s2[n / 2]); cout << count; return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(false); cin.tie(0); long long n; cin >> n; map<pair<long long, long long>, set<pair<long long, long long>>> mp; for (long long i = 1; i <= n; i++) { long long x, y, z; cin >> x >> y >> z; mp[{x, y}].insert({z, i}); } map<long long, set<pair<long long, long long>>> mp2; for (auto &k : mp) { while (k.second.size() > 1) { cout << (*k.second.begin()).second << ; k.second.erase(k.second.begin()); cout << (*k.second.begin()).second << endl; k.second.erase(k.second.begin()); } if (k.second.size() == 1) mp2[k.first.first].insert({k.first.second, (*k.second.begin()).second}); } vector<long long> ind; for (auto &k : mp2) { while (k.second.size() > 1) { cout << (*k.second.begin()).second << ; k.second.erase(k.second.begin()); cout << (*k.second.begin()).second << endl; k.second.erase(k.second.begin()); } if (k.second.size() == 1) ind.push_back((*k.second.begin()).second); } for (long long i = 0; (unsigned)i < ind.size(); i += 2) { cout << ind[i] << << ind[i + 1] << endl; } } |
#include <bits/stdc++.h> using namespace std; const int N = 1000; const double eps = 1e-9; long long INF = 1e9; const int OO = 0x3f3f3f3f; int dx[] = {1, -1, 0, 0, 1, -1, 1, -1}; int dy[] = {0, 0, 1, -1, 1, -1, -1, 1}; bool comp(pair<int, int> a, pair<int, int> b) { if (a.first < b.first) return true; else if (a.first > b.first) return false; else return a.first < b.first; } void read(string str, int node) { stringstream ss; int number; ss << str; while (ss >> number) cout << number << endl; } long long fp(long long b, long long p) { if (p == 0) return 1; if (p % 2 == 0) return fp((b * b) % INF, p / 2); return (fp(b, p - 1) * b) % INF; } unsigned long long read_binary(string s) { unsigned long long x = 0, tmp = 1; for (int i = s.size() - 1; i >= 0; i--) { x = (x + tmp * (s[i] - 0 )) % INF; tmp = (tmp * 2) % INF; } return x; } long long com(long long x, long long y) { long long sum = 1; for (int i = 1; i <= y; i++) { sum *= x; x--; sum /= i; } return sum; } long long gcd(long long n1, long long n2) { if (n2 != 0) return gcd(n2, n1 % n2); else return n1; } int setBit(int num, int idx, int val = 1) { return (val) ? (num | (1 << idx)) : (num & ~(1 << idx)); } int getBit(int num, int idx) { return ((num >> idx) & 1) == 1; } int cntBit(int num) { int ret = 0; while (num) { if (num % 2) ret++; num /= 2; } return ret; } bool sum[1500]; void sieve() { sum[0] = sum[1] = 1; for (int i = 2; i * i < 1002; i++) { if (!sum[i]) { for (int j = 2 * i; j < 1002; j += i) { sum[j] = 1; } } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); ; long long n; cin >> n; string s = to_string(n); long long mi = INF; for (int i = 0; i < (1 << s.size()); ++i) { int cnt = 0; string k; for (int j = 0; j < s.size(); j++) { if (i & (1 << j)) { k += s[j]; cnt++; } } if (k[0] == 0 ) continue; long long val; istringstream ss(k); ss >> val; double d = sqrt(val); int ii = sqrt(val); if (d == ii) { mi = min(mi, (long long)s.size() - cnt); } } if (mi == INF) cout << -1 << endl; else cout << mi << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A41O_PP_SYMBOL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a41o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long int MAX = 1e6 + 5; const int N = 2e5 + 5; const long long int mod = 1e9 + 7; const long long int mx = 1e16; bool comp(const int a, const int b) { return a > b; } const double PI = 2 * acos(0.0); long long int fac[N]; void pre() { fac[0] = 1LL; for (long long int i = 1; i < N; i++) { fac[i] = 1LL * i * fac[i - 1]; if (fac[i] >= mod) fac[i] %= mod; } } long long int power(long long int a, long long int b) { long long int x = 1; while (b) { if (b & 1) { x *= a; if (x >= mod) x %= mod; } a *= a; if (a >= mod) a %= mod; b >>= 1; } return x; } long long int inv(long long int k) { return power(k, mod - 2); } int main() { vector<int> v1, v2; int x, t, a, b, da, db; cin >> x >> t >> a >> b >> da >> db; int t1 = t; int t2 = t; int x1 = x; int x2 = x; if (x == 0) { printf( YES n ); return 0; } for (long long int i = 0; i < t; i++) { if (a - i * da == x || b - i * db == x) { printf( YES n ); return 0; } } for (long long int i = 0; i < t; i++) { for (long long int j = 0; j < t; j++) { int res = a - i * da + b - j * db; if (res == x) { printf( YES n ); return 0; } } } printf( NO n ); } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5, inf = 9e8; int n, a[N]; array<int, 3> vals[N]; void compress(int arr[]) { vector<int> all; for (int i = 1; i <= n; i++) all.push_back(arr[i]); sort(all.begin(), all.end()); for (int i = 1; i <= n; i++) arr[i] = lower_bound(all.begin(), all.end(), arr[i]) - all.begin(), ++arr[i]; } class segTree { private: int n; vector<int> st; public: void init(int _n) { n = _n; st = vector<int>(4 * n + 5, 0); } void pointUpdate(int node, int tl, int tr, int pos, int val) { if (tl == tr) { st[node] = max(st[node], val); } else { int mid = (tl + tr) / 2; if (pos <= mid) pointUpdate(2 * node, tl, mid, pos, val); else pointUpdate(2 * node + 1, mid + 1, tr, pos, val); st[node] = max(st[2 * node], st[2 * node + 1]); } } int rangeQuery(int node, int tl, int tr, int l, int r) { if (l > r) return -inf; if ((l == tl) && (r == tr)) return st[node]; int mid = (tl + tr) / 2; int left_ans = rangeQuery(2 * node, tl, mid, l, min(r, mid)); int right_ans = rangeQuery(2 * node + 1, mid + 1, tr, max(l, mid + 1), r); return max(left_ans, right_ans); } void update(int pos, int val) { pointUpdate(1, 1, n, pos, val); } int query(int l, int r) { r = min(r, n); return rangeQuery(1, 1, n, l, r); } } rangeMax; int32_t main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; compress(a); for (int i = 1; i <= n; i++) vals[i][0] = a[i]; for (int i = 1; i <= n; i++) cin >> a[i]; compress(a); for (int i = 1; i <= n; i++) vals[i][1] = a[i]; for (int i = 1; i <= n; i++) cin >> a[i]; compress(a); for (int i = 1; i <= n; i++) vals[i][2] = a[i]; rangeMax.init(N); sort(vals + 1, vals + n + 1); reverse(vals + 1, vals + n + 1); int ans = 0; int j = 1; for (int i = 1; i <= n; i = j) { while (j <= n && vals[i][0] == vals[j][0]) ++j; for (int k = i; k < j; k++) { int max_c_for_all_valid_b = rangeMax.query(vals[k][1] + 1, inf); if (max_c_for_all_valid_b > vals[k][2]) ++ans; } for (int k = i; k < j; k++) { rangeMax.update(vals[k][1], vals[k][2]); } } cout << ans; } |
module Encoder(index, value);
parameter window_width = 3;
parameter full_win_bits = 4;
input[window_width * window_width - 1 : 0] index;
output[full_win_bits - 1 : 0] value;
reg[full_win_bits - 1 : 0] reg_value;
assign value = reg_value;
generate
case(window_width)
2 :
always@(*) begin
case(index)
1 : reg_value <= 0;
2 : reg_value <= 1;
4 : reg_value <= 2;
8 : reg_value <= 3;
default: reg_value <= 0;
endcase
end
3 :
always@(*) begin
case(index)
1 : reg_value <= 0;
2 : reg_value <= 1;
4 : reg_value <= 2;
8 : reg_value <= 3;
16 : reg_value <= 4;
32 : reg_value <= 5;
64 : reg_value <= 6;
128 : reg_value <= 7;
256 : reg_value <= 8;
default: reg_value <= 0;
endcase
end
4 :
always@(*) begin
case(index)
1 : reg_value <= 0;
2 : reg_value <= 1;
4 : reg_value <= 2;
8 : reg_value <= 3;
16 : reg_value <= 4;
32 : reg_value <= 5;
64 : reg_value <= 6;
128 : reg_value <= 7;
256 : reg_value <= 8;
512 : reg_value <= 9;
1024 : reg_value <= 10;
2048 : reg_value <= 11;
4096 : reg_value <= 12;
8192 : reg_value <= 13;
16384 : reg_value <= 14;
32768 : reg_value <= 15;
default: reg_value <= 0;
endcase
end
5 :
always@(*) begin
case(index)
1 : reg_value <= 0;
2 : reg_value <= 1;
4 : reg_value <= 2;
8 : reg_value <= 3;
16 : reg_value <= 4;
32 : reg_value <= 5;
64 : reg_value <= 6;
128 : reg_value <= 7;
256 : reg_value <= 8;
512 : reg_value <= 9;
1024 : reg_value <= 10;
2048 : reg_value <= 11;
4096 : reg_value <= 12;
8192 : reg_value <= 13;
16384 : reg_value <= 14;
32768 : reg_value <= 15;
65536 : reg_value <= 16;
131072 : reg_value <= 17;
262144 : reg_value <= 18;
524288 : reg_value <= 19;
: reg_value <= 20;
: reg_value <= 21;
: reg_value <= 22;
: reg_value <= 23;
16777216 : reg_value <= 24;
default: reg_value <= 0;
endcase
end
default : ;
endcase
endgenerate
endmodule |
#include <bits/stdc++.h> using namespace std; template <typename T0, typename T1> std::ostream& operator<<(std::ostream& os, const map<T0, T1>& v) { for (typename map<T0, T1>::const_iterator p = v.begin(); p != v.end(); p++) { os << p->first << : << p->second << ; } return os; } template <typename T0, typename T1> std::ostream& operator<<(std::ostream& os, const pair<T0, T1>& v) { os << v.first << : << v.second << ; return os; } template <typename T> std::ostream& operator<<(std::ostream& os, const vector<T>& v) { for (int i = 0; i < (int)v.size(); i++) { os << v[i] << ; } return os; } template <typename T> std::ostream& operator<<(std::ostream& os, const vector<vector<T> >& v) { for (int i = 0; i < (int)v.size(); i++) { os << v[i] << endl; } return os; } template <typename T> std::ostream& operator<<(std::ostream& os, const set<T>& v) { vector<T> tmp(v.begin(), v.end()); os << tmp; return os; } template <typename T> std::ostream& operator<<(std::ostream& os, const deque<T>& v) { vector<T> tmp(v.begin(), v.end()); os << tmp; return os; } int main() { long long N, W, H; while (cin >> H >> W) { vector<string> w(H); for (int y = 0, _n = (H); (y) < (int)_n; ++y) cin >> w[y]; vector<vector<long long> > tb(H, vector<long long>(W)); vector<vector<long long> > tbX(H, vector<long long>(W)); vector<vector<long long> > tbY(H, vector<long long>(W)); for (int y = 0, _n = (H); (y) < (int)_n; ++y) for (int x = 0, _n = (W); (x) < (int)_n; ++x) { { long long v = 0; if (0 <= y - 1) v += tb[y - 1][x]; if (0 <= y - 1 && w[y - 1][x] == . && w[y][x] == . ) v++; if (0 <= x - 1) v += tb[y][x - 1]; if (0 <= x - 1 && w[y][x - 1] == . && w[y][x] == . ) v++; if (0 <= x - 1 && 0 <= y - 1) v -= tb[y - 1][x - 1]; tb[y][x] = v; } { long long v = 0; if (0 <= x - 1) v += tbY[y][x - 1]; if (0 <= y - 1 && w[y - 1][x] == . && w[y][x] == . ) v++; tbY[y][x] = v; } { long long v = 0; if (0 <= y - 1) v += tbX[y - 1][x]; if (0 <= x - 1 && w[y][x - 1] == . && w[y][x] == . ) v++; tbX[y][x] = v; } } cin >> N; for (int i = 0, _n = (N); (i) < (int)_n; ++i) { long long y1, x1, y2, x2; cin >> y1 >> x1 >> y2 >> x2; y1--; x1--; y2--; x2--; long long v = tb[y2][x2]; if (0 <= y1 - 1) v -= tb[y1 - 1][x2]; { long long vv = tbY[y1][x2]; if (0 <= x1 - 1) vv -= tbY[y1][x1 - 1]; v -= vv; } if (0 <= x1 - 1) v -= tb[y2][x1 - 1]; { long long vv = tbX[y2][x1]; if (0 <= y1 - 1) vv -= tbX[y1 - 1][x1]; v -= vv; } if (0 <= x1 - 1 && 0 <= y1 - 1) v += tb[y1 - 1][x1 - 1]; cout << v << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, a[1010], s; long long pw[1010], c[1010][1010], ans = 1; int main() { pw[0] = pw[1] = 1; for (int i = 2; i < 1010; i++) pw[i] = 2 * pw[i - 1] % 1000000007; for (int i = 0; i < 1010; i++) for (int j = 0; j <= i; j++) c[i][j] = ((!i || !j || i == j) ? 1 : c[i - 1][j] + c[i - 1][j - 1]) % 1000000007; scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) scanf( %d , &a[i]); sort(a + 1, a + m + 1); s = n - m; for (int i = 2; i <= m; i++) { int w = a[i] - a[i - 1] - 1; ans = ans * c[s][w] % 1000000007 * pw[w] % 1000000007; s -= w; } ans = ans * c[s][a[1] - 1] % 1000000007; printf( %lld , ans); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__SDFSBP_BEHAVIORAL_PP_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hdll__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hdll__udp_dff$PS_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSBP_BEHAVIORAL_PP_V |
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