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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DFSBP_BEHAVIORAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ms__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSBP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0; char ch = getchar(); bool positive = 1; for (; ch < 0 || ch > 9 ; ch = getchar()) if (ch == - ) positive = 0; for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = x * 10 + ch - 0 ; return positive ? x : -x; } inline char RC() { char c = getchar(); while (c == || c == n ) c = getchar(); return c; } inline long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } inline long long lcm(long long a, long long b, long long MOD) { return a / gcd(a, b) * b % MOD; } inline long long Sub(long long x, long long y, long long mod) { long long res = x - y; while (res < 0) res += mod; return res; } inline long long Add(long long x, long long y, long long mod) { long long res = x + y; while (res >= mod) res -= mod; return res; } inline long long POW_MOD(long long x, long long y, long long mod) { long long ret = 1; while (y > 0) { if (y & 1) ret = ret * x % mod; x = x * x % mod; y >>= 1; } return ret; } const int N = 6005; const int inf = 2100000000; const long long INF = 1LL << 62; const double PI = 3.14159265358; int n, m; int dis[N][N]; vector<pair<int, int> > fr[N], to[N]; vector<int> e[N]; bool vis[N]; void spfa(int u) { memset(vis, false, sizeof(vis)); queue<int> q; q.push(u); vis[u] = true; dis[u][u] = 0; while (q.size()) { int cur = q.front(); q.pop(); vis[cur] = false; for (int i = 0; i < e[cur].size(); ++i) { int v = e[cur][i]; if (dis[u][v] > dis[u][cur] + 1) { dis[u][v] = dis[u][cur] + 1; if (!vis[v]) { q.push(v); } } } } } void init() { for (int i = 0; i <= n; ++i) { for (int j = 0; j <= n; ++j) { dis[i][j] = inf; } } } bool judge(int a, int b, int c, int d) { if (a == b || a == c || a == d || b == c || b == d || c == d) return false; return true; } int main() { cin >> n >> m; for (int i = 0; i < m; ++i) { int u, v; cin >> u >> v; e[u].push_back(v); } init(); for (int i = 1; i <= n; ++i) { spfa(i); } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { if (dis[i][j] == inf) continue; fr[i].push_back(make_pair(dis[i][j], j)); to[j].push_back(make_pair(dis[i][j], i)); } sort(fr[i].begin(), fr[i].end()); } for (int i = 1; i <= n; ++i) sort(to[i].begin(), to[i].end()); int ans = 0; int a, b, c, d; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= n; ++j) { if (i == j || dis[i][j] == inf) continue; for (int p = to[i].size() - 1; p >= max(0, (int)to[i].size() - 1 - 3); --p) { for (int q = fr[j].size() - 1; q >= max(0, (int)fr[j].size() - 4); --q) { int ii = to[i][p].second, jj = fr[j][q].second; if (judge(ii, i, j, jj)) { long long temp = dis[ii][i] + dis[i][j] + dis[j][jj]; if (temp > ans) { ans = temp; a = ii, b = i, c = j, d = jj; } } } } } } cout << a << << b << << c << << d << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int di[] = {0, 0, 1, -1, 1, 1, -1, -1}; int dj[] = {1, -1, 0, 0, -1, 1, 1, -1}; const double PI = 3.14159265359, EPS = 1e-9; const int N = 1000006, M = 1000006, Mod = 1000000007; vector<int> adj[N]; pair<int, int> tree[4 * N]; int n; string str; void build(int idx, int s, int e) { if (s == e) { if (str[s] == ( ) ++tree[idx].first; if (str[s] == ) ) ++tree[idx].second; return; } int m = (s + e) / 2; build(idx << 1, s, m); build(idx << 1 | 1, m + 1, e); tree[idx].first = tree[idx << 1 | 1].first + max(0, tree[idx << 1].first - tree[idx << 1 | 1].second); tree[idx].second = tree[idx << 1].second + max(0, tree[idx << 1 | 1].second - tree[idx << 1].first); } pair<int, int> maxx(int l, int r, int idx, int s, int e) { if (l > e || r < s) return pair<int, int>(0, 0); if (l <= s && r >= e) return tree[idx]; int m = (s + e) / 2; pair<int, int> p1 = maxx(l, r, idx << 1, s, m); pair<int, int> p2 = maxx(l, r, idx << 1 | 1, m + 1, e); pair<int, int> ret; ret.first = p2.first + max(0, p1.first - p2.second); ret.second = p1.second + max(0, p2.second - p1.first); return ret; } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0), cout.precision(10), cout << fixed; cin >> str; str = s + str; n = (int)str.size(); build(1, 1, n); int m; cin >> m; int l, r; while (m--) { cin >> l >> r; pair<int, int> p = maxx(l, r, 1, 1, n); cout << r - l + 1 - p.first - p.second << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int x, y, z; cin >> x >> y >> z; if (z == 0) { if (x > y) cout << + ; else if (x < y) cout << - ; else cout << 0 ; } else { if (x > y + z) cout << + ; else if (y > x + z) cout << - ; else cout << ? ; } return 0; } |
`timescale 1ns/1ps
module tb;
`include "useful_tasks.v" // some helper tasks
reg rst_async_n; // asynchronous reset
wire r1,r2;
wire a1,a2;
wire r,a;
two_phase_event_gen U_PORT1_EVENT_GEN (
.run(rst_async_n),
.req(r1),
.ack(a1)
);
two_phase_event_gen U_PORT2_EVENT_GEN (
.run(rst_async_n),
.req(r2),
.ack(a2)
);
or_r1_2ph U_ASYNC_OR(
// Input ports (req/ack)
.r1(r1),
.a1(a1),
.r2(r2),
.a2(a2),
// Output ports
.r(r),
.a(a),
.rstn(rst_async_n)
);
two_phase_slave U_SLAVE(.req(r), .ack(a));
// assign #55 a = r;
// Dump all nets to a vcd file called tb.vcd
event dbg_finish;
reg clk;
initial clk = 0;
always
#100 clk = ~clk;
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
initial begin
rst_async_n = 1'b0;
#5;
rst_async_n = 1'b1;
$display("-I- Reset is released");
#200000;
$display("-I- Done !");
$finish;
end
// four_phase_assertion U_CHECKER0(.req(r0),.ack(a0),.rstn(rst_async_n));
// four_phase_assertion U_CHECKER1(.req(r1),.ack(a1),.rstn(rst_async_n));
// four_phase_assertion U_CHECKER2(.req(r2),.ack(a2),.rstn(rst_async_n));
// just for debug
//assign input_port1_ongoing_req = r1 ^ a1;
//assign input_port2_ongoing_req = r2 ^ a2;
//assign output_port1_unstable = g1 ^ d1;
//assign output_port2_unstable = g2 ^ d2;
//
event error1;
event error2;
assign r1_qual = r1 & a1;
assign r2_qual = r2 & a2;
assign r_qual = r & a;
// If r rises, it is because of one of the incoming request
always@(posedge r)
if(! (r1 | r2)) ->error1;
initial begin
#1;
@(error1 or error2);
$display("-E error found in protocol");
#100;
$finish;
end
endmodule // tb
|
#include <iostream> #include <vector> #include <algorithm> #include <string> #include <set> #include <cmath> #include <bitset> #include <iomanip> #include <queue> #include <stack> #include <map> #include <unordered_map> #include <unordered_set> #include <chrono> #include <random> #include <complex> using namespace std; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); inline void boostIO() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << fixed << setprecision(10); } bool isPrime(int x) { if (x <= 4 || x % 2 == 0 || x % 3 == 0) return x == 2 || x == 3; for (int i = 5; i * i <= x; i += 6) if (x % i == 0 || x % (i + 2) == 0) return 0; return 1; } typedef long long int ll; typedef long double ld; typedef unsigned long long ull; typedef vector<int> vi; typedef vector<ll> vll; typedef pair<int, int> pii; #define fori(n) for(int i = 0; i < (n); ++i) #define forj(n) for(int j = 0; j < (n); ++j) #define fork(n) for(int k = 0; k < (n); ++k) #define forx(n) for(int x = 0; x < (n); ++x) #define all(x) (x).begin(), (x).end() #define rall(x) (x).rbegin(), (x).rend() #define ff first #define ss second #define debug(x) cerr << #x << = << x << endl; #define debug_p(x) cerr << #x << << x.ff << << x.ss << endl; #define debug_v(x) cerr << #x << ; for (auto ii : x) cout << i << ; cout << endl; #define debug_vp(x) cerr << #x << ; for (auto ii : x) cout << [ << ii.ff << << ii.ss << ] ; cout << endl; #define mp make_pair #define rand kjsdflsdfsdlsjdlkfsdjflsjdfl #define Return cerr<<endl<< RUNTIME: <<1.0*clock()/CLOCKS_PER_SEC << s <<endl; return 0; #define PI 3.14159265 ll gcd(ll a, ll b) { return b ? gcd(b, a % b) : a; } ll lcm(ll a, ll b) { return a * b / gcd(a, b); } ///////////////////// #define int long long int Mod = 1e9 + 7; #define endl n ///////////////////// int inf = 1e18; vector<int> A; int dp[2000][2000] = {}; int seen[2000][2000] = {}; int rec(int l, int r) { if (l == r) { return 0; } if (seen[l][r]) { return dp[l][r]; } seen[l][r] = 1; //here int ans = inf; ans = min(rec(l+1, r), rec(l, r-1)) + A[r] - A[l]; dp[l][r] = ans; return dp[l][r]; } int32_t main() { boostIO(); int n; cin >> n; A.assign(n, 0); fori(n) { cin >> A[i]; } sort(all(A)); cout << rec(0, n - 1); } |
#include <bits/stdc++.h> using namespace std; int main() { int t; int a[] = {1, 2, 3, 4, 6, 12}; int b[] = {12, 6, 4, 3, 2, 1}; cin >> t; while (t--) { string s; cin >> s; int ans[20]; int count = 0, n = 0, no; for (int i = 0; i < 6; i++) { for (int j = 0; j < b[i]; j++) { no = 0; for (int k = 0; k < a[i]; k++) { if (s[j + k * b[i]] != X ) { no = 1; break; } } if (!no) { ans[count++] = i; n++; break; } } } cout << n << ; for (int i = 0; i < n; i++) { cout << a[ans[i]] << x << b[ans[i]] << ; } cout << endl; } } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Sep 27 15:52:46 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[8:0],probe20[0:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[7:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [7:0]probe18;
input [8:0]probe19;
input [0:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [7:0]probe24;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1000000007; const int N = 10; int n, k; int a[1005]; int main() { ios_base::sync_with_stdio(false); cin >> n >> k; int nn = n; for (int i = 0; i < k; i++) { cin >> a[i]; while (a[i] >= 4 && nn > 0) { a[i] -= 4; nn--; } } int n2 = n * 2 + nn; for (int i = 0; i < k; i++) { while (a[i] >= 2 && n2 > 0) { a[i] -= 2; n2--; } } int sum = 0; for (int i = 0; i < k; i++) { sum += a[i]; } if (sum > nn + n2) { cout << NO << endl; } else { cout << YES << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1005; int n, m, q, u, v, w, l, r, ans, par[N], col[N], mark[N]; vector<pair<int, pair<int, int> > > yal, edge[N * N]; vector<int> cmp[N]; void add(int x) { for (int i = 0; i < edge[x].size(); i++) yal.push_back(edge[x][i]); } int Get_par(int u) { if (par[u] < 0) return u; return par[u] = Get_par(par[u]); } void query(int l, int r) { r++; for (l += m, r += m; l < r; l >>= 1, r >>= 1) { if (l & 1) add(l++); if (r & 1) add(--r); } } void reset(int x) { cmp[x].clear(); cmp[x].push_back(x); } void merge(int u, int v, int s) { u = Get_par(u), v = Get_par(v); if (par[u] > par[v]) swap(u, v); for (int i = 0; i < cmp[v].size(); i++) cmp[u].push_back(cmp[v][i]), col[cmp[v][i]] ^= s; par[u] += par[v], par[v] = u; } void solve(int x) { vector<pair<int, pair<int, int> > > vec; for (int i = 0; i < edge[x].size(); i++) par[edge[x][i].second.first] = par[edge[x][i].second.second] = -1, reset(edge[x][i].second.first), reset(edge[x][i].second.second); for (int i = 0; i < edge[x].size(); i++) { u = edge[x][i].second.first, v = edge[x][i].second.second; if (Get_par(u) == Get_par(v)) { if (col[u] == col[v]) { vec.push_back(edge[x][i]); break; } } else merge(u, v, col[u] == col[v]), vec.push_back(edge[x][i]); } edge[x].clear(); edge[x] = vec; } void merge_t(int u, int v, int an) { int p1 = 0, p2 = 0; while (p1 < edge[u].size() || p2 < edge[v].size()) { if (p2 == edge[v].size() || (p1 < edge[u].size() && edge[u][p1].first > edge[v][p2].first)) edge[an].push_back(edge[u][p1++]); else edge[an].push_back(edge[v][p2++]); } } void build() { for (int i = m - 1; i >= 1; i--) { merge_t(i * 2, i * 2 + 1, i); solve(i); } } void clear() { ans = -1, yal.clear(); fill(col, col + N, 0); fill(par, par + N, -1); for (int i = 1; i < n + 1; i++) reset(i); } int main() { cin >> n >> m >> q; for (int i = 0; i < m; i++) { scanf( %d%d , &u, &v); ; scanf( %d , &w); ; edge[i + m].push_back(make_pair(w, make_pair(u, v))); } build(); for (int io = 0; io < q; io++) { clear(); scanf( %d%d , &l, &r); ; --l, --r; query(l, r); sort(yal.begin(), yal.end()); reverse(yal.begin(), yal.end()); for (int i = 0; i < yal.size(); i++) { u = yal[i].second.first, v = yal[i].second.second; if (Get_par(u) == Get_par(v)) { if (col[u] == col[v]) { ans = yal[i].first; break; } } else merge(u, v, col[u] == col[v]); } cout << ans << n ; } } |
#include <bits/stdc++.h> using namespace std; int n, q, j, x[300000 + 10], a, b, sum, t, o[300000 + 10], p[300000 + 10], h = 1; int main() { cin >> n >> q; for (int i = 0; i < q; i++) { cin >> a >> b; if (a == 1) { j++; x[j] = b; o[b]++; p[b]++; sum++; cout << sum << endl; continue; } if (a == 2) { sum -= o[b]; o[b] = 0; cout << sum << endl; continue; } if (a == 3) { for (h; h <= b; h++) { int n1 = x[h]; if (p[n1] > 0) p[n1]--; if (p[n1] < o[n1]) { sum--; o[n1]--; } } cout << sum << endl; continue; } } } |
//愿你和你重要的人能够重逢！ #include<bits/stdc++.h> using namespace std; template<typename T>inline void read(T &x) { x=0;char c=getchar(),f=0; for(;c<48||c>57;c=getchar()) if(!(c^45)) f=1; for(;c>=48&&c<=57;c=getchar()) x=(x<<1)+(x<<3)+(c^48); f?x=-x:0; } long long l,r,st,t,x,y;set<long long>s; int main() { read(st),read(l),read(r),read(t),read(x),read(y); if(x>y) { if((x-y<2e18/t&&st-l>=t*(x-y))&&st+y<=r) puts( Yes ); else if(x-y<2e18/t&&st-l>=t*x-(t-1)*y) puts( Yes ); else puts( No ); return 0; } long long qwq=st,tp;qwq=l+(qwq-l)%x,t-=(st-qwq)/x; if(t<=0) return puts( Yes ),0;else if(qwq+y>r) return puts( No ),0; while(t>0) { qwq+=y;if(qwq>r) return puts( No ),0;else tp=qwq,qwq=l+(qwq-l)%x,t-=(tp-qwq)/x; if(t<=0) return puts( Yes ),0;else if(s.count(qwq)) return puts( Yes ),0;else s.insert(qwq); } return puts( Yes ),0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, t; cin >> t; while (t--) { cin >> n; vector<int> a(n); int mx = 0; for (auto &it : a) { cin >> it; mx = max(mx, it); } int r = n - 1; int ind = -1; for (int l = 0; l < n; l++) { if (a[l] != mx) continue; else if (l > 0 && a[l - 1] != mx) ind = l + 1; else if (r > l && a[l + 1] != mx) ind = l + 1; } cout << ind << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int maxn = 4e3 + 5; const int mod = 1e9 + 7; const double eps = 1e-8; const double pi = asin(1.0) * 2; const double e = 2.718281828459; bool Finish_read; template <class T> inline void read(T &x) { Finish_read = 0; x = 0; int f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) { f = -1; } if (ch == EOF) { return; } ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } x *= f; Finish_read = 1; }; int main(int argc, char *argv[]) { int n, m; read(n); read(m); vector<int> a; a.push_back(0); for (int i = 1, x; i <= n; ++i) { read(x); a.push_back(x); } a.push_back(m); vector<int> f[2]; f[0].assign(a.size(), 0); f[1].assign(a.size(), 0); for (int i = int(a.size()) - 2; i >= 0; --i) { f[0][i] = f[1][i + 1]; f[1][i] = (a[i + 1] - a[i]) + f[0][i + 1]; } int ans = f[1][0]; for (int i = 0; i + 1 < int(a.size()); ++i) { if (a[i + 1] - a[i] < 2) { continue; } int tp = (i & 1) ^ 1; int pSum = f[1][0] - f[tp][i]; ans = max(ans, pSum + (a[i + 1] - a[i] - 1) + f[tp][i + 1]); } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, k, x; long long eval(long long x) { long long ret = 0; if (x % 4 == 0) { return x / 4; } else { if (x % 4 == 3) { x -= 15; ret++; ret++; } else if (x % 4 == 2) { x -= 6; ret++; } else if (x % 4 == 1) { x -= 9; ret++; } if (x < 0) return -1; else return ret + x / 4; } } int main() { cin >> n; for (int i = 0; i < (n); ++i) { cin >> x; printf( %lld n , eval(x)); } } |
#include <bits/stdc++.h> using namespace std; int n; int a[200001]; vector<int> G[200001]; int res[200001]; vector<int> divisor; vector<int> now; int gcd(int x, int y) { if (y == 0) return x; return gcd(y, x % y); } void dfs(int v, int p) { for (int i = 0; i < G[v].size(); i++) { if (p != G[v][i]) { res[G[v][i]] = gcd(res[v], a[G[v][i]]); dfs(G[v][i], v); } } } void dfs2(int v, int p, int dist) { for (int i = 0; i < divisor.size(); i++) { now[i] += (a[v] % divisor[i] == 0); if (now[i] >= dist) { res[v] = max(res[v], divisor[i]); } } for (int i = 0; i < G[v].size(); i++) { if (p != G[v][i]) { dfs2(G[v][i], v, dist + 1); } } for (int i = 0; i < divisor.size(); i++) { now[i] -= (a[v] % divisor[i] == 0); } } int main(void) { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } for (int i = 0; i < n - 1; i++) { int f, t; scanf( %d%d , &f, &t); f--; t--; G[f].push_back(t); G[t].push_back(f); } int tmp = a[0]; a[0] = 0; dfs(0, -1); a[0] = tmp; for (int i = 1; i * i <= a[0]; i++) { if (a[0] % i == 0) { divisor.push_back(i); divisor.push_back(a[0] / i); if (i * i == a[0]) { divisor.pop_back(); } } } sort(divisor.begin(), divisor.end()); now.resize(divisor.size()); dfs2(0, -1, 0); for (int i = 0; i < n; i++) { printf( %d%c , res[i], i + 1 == n ? n : ); } return 0; } |
// wasca_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module wasca_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
output wire [26:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [19:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
wasca_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port), // custom_instruction_master.readra
.reset_req (1'b0) // (terminated)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 200001; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, k; cin >> n >> k; string s; cin >> s; int ans = 2e9; vector<int> can; vector<string> cand; for (int i = 0; i < 10; i++) { priority_queue<int> pq; int t = 0; for (int j = 0; j < s.length(); j++) { int alpha = s[j] - 0 ; int cost = abs(alpha - i); pq.push(-cost); } for (int j = 0; j < k; j++) { int cst = -pq.top(); pq.pop(); t += cst; } if (ans > t) { can.clear(); can.push_back(i); ans = t; } else if (ans == t) { can.push_back(i); } } for (int d = 0; d < can.size(); d++) { string temp = s; int num = can[d]; int need = k; vector<pair<int, int> > big; vector<pair<int, int> > small; vector<pair<int, int> > ord; int cnt[10]; memset(cnt, 0, sizeof(cnt)); priority_queue<int> pq; for (int j = 0; j < s.size(); j++) { int cst = abs(num - (s[j] - 0 )); if (cst) pq.push(-cst); if (s[j] - 0 == num) need--; if (s[j] - 0 > num) big.push_back({s[j] - 0 , j}); if (s[j] - 0 < num) small.push_back({s[j] - 0 , j}); } reverse(small.begin(), small.end()); for (int i = 0; i < big.size(); i++) { int cost = abs(big[i].first - num); ord.push_back({cost, big[i].second}); } for (int i = 0; i < small.size(); i++) { int cost = abs(small[i].first - num); ord.push_back({cost, small[i].second}); } if (need <= 0) { cout << 0 << endl << s; exit(0); } for (int i = 0; i < need; i++) { int cst = -pq.top(); pq.pop(); cnt[cst]++; } for (int i = 0; i < ord.size(); i++) { int cst = ord[i].first; int idx = ord[i].second; if (cnt[cst]) { cnt[cst]--; temp[idx] = (char)(num + 0 ); } } cand.push_back(temp); } cout << ans << n ; sort(cand.begin(), cand.end()); cout << cand[0]; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311O_SYMBOL_V
`define SKY130_FD_SC_LS__A311O_SYMBOL_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a311o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311O_SYMBOL_V
|
// LCD video synchronizer, generates X/Y coordinates, validity of
// current pixel RGB value.
// Copyright (c) 2013 Jared Boone, ShareBrained Technology, Inc.
//
// This file is part of the Medusa project.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
module lcd_sync (
input rst,
input [23:0] lcd_data_i,
input lcd_pclk_i,
input lcd_vsync_i,
input lcd_hsync_i,
input lcd_de_i,
output lcd_clk_o,
output [11:0] lcd_x_o,
output [11:0] lcd_y_o,
output [23:0] lcd_data_o,
output lcd_data_valid_o
);
reg [11:0] lcd_x_q;
reg [11:0] lcd_y_q;
reg [23:0] lcd_data_q;
reg lcd_hsync_q;
reg lcd_vsync_q;
reg lcd_de_q;
assign lcd_clk_o = lcd_pclk_i;
assign lcd_x_o = lcd_x_q;
assign lcd_y_o = lcd_y_q;
assign lcd_data_o = lcd_data_q;
assign lcd_data_valid_o = lcd_de_q;
wire lcd_hsync_end = (lcd_hsync_i == 0) && (lcd_hsync_q == 1);
wire lcd_vsync_end = (lcd_vsync_i == 1) && (lcd_vsync_q == 0);
always @(posedge lcd_pclk_i) begin
if (rst) begin
lcd_x_q <= 0;
lcd_y_q <= 0;
lcd_data_q <= 0;
lcd_hsync_q <= 0;
lcd_vsync_q <= 0;
lcd_de_q <= 0;
end
else begin
lcd_hsync_q <= lcd_hsync_i;
lcd_vsync_q <= lcd_vsync_i;
lcd_de_q <= lcd_de_i;
if (lcd_de_i) begin
lcd_data_q <= lcd_data_i;
end else begin
lcd_data_q <= 0;
end
if (lcd_vsync_end) begin
lcd_y_q <= 0;
end else begin
if (lcd_hsync_end) begin
lcd_y_q <= lcd_y_q + 12'h1;
end
end
if (lcd_hsync_end) begin
lcd_x_q <= 0;
end else begin
if (lcd_de_q) begin
lcd_x_q <= lcd_x_q + 12'h1;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> namespace FASTIO { char buf[1 << 21]; char *p1, *p2; template <typename T> inline void wt(T x, char c = n ) { if (x < 0) { x = -x; putchar( - ); } static char sta[sizeof(T) * 8]; T top = 0; do { sta[top++] = x % 10; x /= 10; } while (x); while (top) putchar(sta[--top] + 0 ); putchar(c); } template <typename T> inline T rd() { T sum = 0, fl = 1; char ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++); for (; ch < 0 || ch > 9 ; ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++)) if (ch == - ) fl = -1; else if (ch == EOF) exit(0); for (; 0 <= ch && ch <= 9 ; ch = (p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1 << 21, stdin), p1 == p2) ? EOF : *p1++)) sum = sum * 10 + ch - 0 ; return sum * fl; } } // namespace FASTIO using namespace FASTIO; const int N = 3e5 + 2, logN = 19; int dep[N], anc[N][logN]; inline int lca(int x, int y) { if (dep[x] < dep[y]) std::swap(x, y); { int dt = dep[x] - dep[y]; if (dt) for (int i = (31 - __builtin_clz(dt)); i >= 0; i--) if (dt & 1 << i) x = anc[x][i]; } if (x == y) return x; for (int i = (31 - __builtin_clz(dep[x])); i >= 0; i--) if (anc[x][i] != anc[y][i]) { x = anc[x][i]; y = anc[y][i]; } return anc[x][0]; } inline int dist(const int x, const int y) { return dep[x] + dep[y] - dep[lca(x, y)] * 2; } std::vector<int> s1, s2; int main() { const int n = rd<int>() + 1; s1.reserve(n + 1); s2.reserve(n + 1); s1.push_back(1); dep[1] = 1; for (int i = 2, maxd = 0, d1, d2; i <= n; i++) { dep[i] = dep[anc[i][0] = rd<int>()] + 1; for (int j = 1; 1 << j <= dep[i]; j++) anc[i][j] = anc[anc[i][j - 1]][j - 1]; d1 = s1.empty() ? 0 : dist(i, s1.back()); d2 = s2.empty() ? 0 : dist(i, s2.back()); if (std::max(d1, d2) > maxd) { maxd = std::max(d1, d2); if (maxd != d1) { s1.swap(s2); std::swap(d1, d2); } for (const int &x : s2) if (dist(x, i) == d1) s1.push_back(x); s2.clear(); } if (std::max(d1, d2) == maxd) (maxd == d1 ? s2 : s1).push_back(i); wt(s1.size() + s2.size()); } return 0; } |
#include <bits/stdc++.h> using namespace std; inline int read() { char c; int x = 0; int b = 1; do { c = getchar(); if (c == 45) b = -1; } while (c > 57 || c < 48); do x = x * 10 + c - 48, c = getchar(); while (c <= 57 && c >= 48); x *= b; return x; } int n, m, t; const int maxn = 300 + 5; const int logn = 10 + 5; int f[logn][maxn][maxn]; int g[maxn][maxn], w[maxn][maxn]; int main() { n = read(), m = read(); t = log2(n); memset(f, 0xcf, sizeof(f)); memset(w, 0xcf, sizeof(w)); for (int i = 1, x, y, z, l; i <= m; i++) { x = read(), y = read(); z = read(); l = read(); f[0][x][y] = z, f[0][y][x] = l; } for (int i = 1; i <= n; i++) w[i][i] = f[0][i][i] = 0; for (int s = 1; s <= 10; s++) { for (int k = 1; k <= n; k++) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { f[s][i][j] = max(f[s][i][j], f[s - 1][i][k] + f[s - 1][k][j]); } } } } int ans = 0; for (int s = 10; s >= 0; s--) { memset(g, 0xcf, sizeof(g)); for (int k = 1; k <= n; k++) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { g[i][j] = max(g[i][j], w[i][k] + f[s][k][j]); } } } int sig = 0; for (int i = 1; i <= n; i++) if (g[i][i] > 0) sig = 1; if (sig) continue; else { for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { w[i][j] = g[i][j]; } } ans += (1 << s); } } printf( %d n , ans >= n ? 0 : ans + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, l; cin >> n >> l; vector<int> a(n); vector<int> b(n); for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 0; i < n; ++i) cin >> b[i]; vector<int> c(n); for (int zsuv = 0; zsuv < l; ++zsuv) { for (int i = 0; i < n; ++i) { c[i] = (b[i] + zsuv) % l; } bool isequal = true; for (int i = 0; i < n; ++i) { bool iii = false; for (int j = 0; j < n; ++j) { if (c[i] == a[j]) { iii = true; break; } } if (!iii) { isequal = false; break; } } if (isequal) { cout << YES ; return 0; } } cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; inline int read() { int t = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) f = (ch == - ) ? -1 : f, ch = getchar(); while (ch >= 0 && ch <= 9 ) t = t * 10 + ch - 0 , ch = getchar(); return t * f; } struct orz { char s[16]; int x, y; void in() { scanf( %s , s), x = read(), y = read(); } friend bool operator<(orz a, orz b) { return (a.x == b.x) ? a.y > b.y : a.x < b.x; } } a[200105]; int main() { n = read(), m = read(); for (register int i = 1; i <= n; i++) a[i].in(); sort(a + 1, a + n + 1); int now = 1; for (register int i = 1; i <= m; i++) { while (a[now].x != i) now++; if (now + 2 <= n && a[now + 2].x == a[now + 1].x && a[now + 2].y == a[now + 1].y) puts( ? ); else printf( %s %s n , a[now].s, a[now + 1].s); now++; } return 0; } |
#include <bits/stdc++.h> using namespace std; inline long long in() { long long x = 0; int n = 1; char c = getchar(); while (!isdigit(c)) { n = (c == - ) ? -1 : 1; c = getchar(); } while (isdigit(c)) { x = x * 10 + c - 0 ; c = getchar(); } return x * n; } const int N = 80; int n, a[N], d[5]; int f[N][N][N][2]; string s; int NOR(int x) { if (x < 0) return -x; return 0; } void UPD(int &a, int b) { if (a == -1) a = b; else a = min(a, b); } int main() { n = in(); cin >> s; s = + s; for (int i = 1; i <= n; i++) { a[i] = (s[i] == V ) ? 1 : (s[i] == K ) ? 2 : 0; d[a[i]]++; } memset(f, -1, sizeof(f)); f[0][0][0][0] = f[0][0][0][1] = 0; for (int z = 0; z <= d[0]; z++) for (int v = 0; v <= d[1]; v++) for (int k = 0; k <= d[2]; k++) for (int ov = 0; ov <= 1; ov++) if (f[z][v][k][ov] >= 0) { for (int nd = 0; nd <= 2; nd++) { if (ov == 1 && nd == 2) continue; int Z = z + (nd == 0), V = v + (nd == 1), K = k + (nd == 2); int d[5]; d[0] = z, d[1] = v, d[2] = k; int left = 0; for (int i = 1; i <= n; i++) { if (a[i] == nd && d[a[i]] == 0) break; if (d[a[i]] == 0) left++; else d[a[i]]--; } UPD(f[Z][V][K][(nd == 1)], f[z][v][k][ov] + left); } } int res = -1; for (int ov = 0; ov <= 1; ov++) UPD(res, f[d[0]][d[1]][d[2]][ov]); if (res == -1) cout << 0; else cout << res; } |
////////////////////////////////////////////////////////
// RS-232 RX and TX module
// (c) fpga4fun.com & KNJN LLC - 2003 to 2013
// The RS-232 settings are fixed
// TX: 8-bit data, 1 stop, no-parity
// RX: 8-bit data, 1 stop, no-parity (the receiver can accept more stop bits of course)
//`define SIMULATION // in this mode, TX outputs one bit per clock cycle
// and RX receives one bit per clock cycle (for fast simulations)
////////////////////////////////////////////////////////
module async_transmitter(
input clk,
input TxD_start,
input [7:0] TxD_data,
output TxD,
output TxD_busy
);
// Assert TxD_start for (at least) one clock cycle to start transmission of TxD_data
// TxD_data is latched so that it doesn't have to stay valid while it is being sent
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;
/*
generate
if(ClkFrequency<Baud*8 && (ClkFrequency % Baud!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency incompatible with requested Baud rate");
endgenerate
*/
////////////////////////////////
`ifdef SIMULATION
wire BitTick = 1'b1; // output one bit per clock cycle
`else
wire BitTick;
BaudTickGen #(ClkFrequency, Baud) tickgen(.clk(clk), .enable(TxD_busy), .tick(BitTick));
`endif
reg [3:0] TxD_state = 0;
wire TxD_ready = (TxD_state==0);
assign TxD_busy = ~TxD_ready;
reg [7:0] TxD_shift = 0;
always @(posedge clk)
begin
if(TxD_ready & TxD_start)
TxD_shift <= TxD_data;
else
if(TxD_state[3] & BitTick)
TxD_shift <= (TxD_shift >> 1);
case(TxD_state)
4'b0000: if(TxD_start) TxD_state <= 4'b0100;
4'b0100: if(BitTick) TxD_state <= 4'b1000; // start bit
4'b1000: if(BitTick) TxD_state <= 4'b1001; // bit 0
4'b1001: if(BitTick) TxD_state <= 4'b1010; // bit 1
4'b1010: if(BitTick) TxD_state <= 4'b1011; // bit 2
4'b1011: if(BitTick) TxD_state <= 4'b1100; // bit 3
4'b1100: if(BitTick) TxD_state <= 4'b1101; // bit 4
4'b1101: if(BitTick) TxD_state <= 4'b1110; // bit 5
4'b1110: if(BitTick) TxD_state <= 4'b1111; // bit 6
4'b1111: if(BitTick) TxD_state <= 4'b0010; // bit 7
4'b0010: if(BitTick) TxD_state <= 4'b0000; // stop1
//4'b0010: if(BitTick) TxD_state <= 4'b0011; // stop1
//4'b0011: if(BitTick) TxD_state <= 4'b0000; // stop2
default: if(BitTick) TxD_state <= 4'b0000;
endcase
end
assign TxD = (TxD_state<4) | (TxD_state[3] & TxD_shift[0]); // put together the start, data and stop bits
endmodule
////////////////////////////////////////////////////////
module async_receiver(
input clk,
input RxD,
output reg RxD_data_ready = 0,
output reg [7:0] RxD_data = 0, // data received, valid only (for one clock cycle) when RxD_data_ready is asserted
// We also detect if a gap occurs in the received stream of characters
// That can be useful if multiple characters are sent in burst
// so that multiple characters can be treated as a "packet"
output RxD_idle, // asserted when no data has been received for a while
output reg RxD_endofpacket = 0 // asserted for one clock cycle when a packet has been detected (i.e. RxD_idle is going high)
);
parameter ClkFrequency = 25000000; // 25MHz
parameter Baud = 115200;
parameter Oversampling = 8; // needs to be a power of 2
// we oversample the RxD line at a fixed rate to capture each RxD data bit at the "right" time
// 8 times oversampling by default, use 16 for higher quality reception
/*
generate
if(ClkFrequency<Baud*Oversampling) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Frequency too low for current Baud rate and oversampling");
if(Oversampling<8 || ((Oversampling & (Oversampling-1))!=0)) ASSERTION_ERROR PARAMETER_OUT_OF_RANGE("Invalid oversampling value");
endgenerate
*/
////////////////////////////////
reg [3:0] RxD_state = 0;
`ifdef SIMULATION
wire RxD_bit = RxD;
wire sampleNow = 1'b1; // receive one bit per clock cycle
`else
wire OversamplingTick;
BaudTickGen #(ClkFrequency, Baud, Oversampling) tickgen(.clk(clk), .enable(1'b1), .tick(OversamplingTick));
// synchronize RxD to our clk domain
reg [1:0] RxD_sync = 2'b11;
always @(posedge clk) if(OversamplingTick) RxD_sync <= {RxD_sync[0], RxD};
// and filter it
reg [1:0] Filter_cnt = 2'b11;
reg RxD_bit = 1'b1;
always @(posedge clk)
if(OversamplingTick)
begin
if(RxD_sync[1]==1'b1 && Filter_cnt!=2'b11) Filter_cnt <= Filter_cnt + 1'd1;
else
if(RxD_sync[1]==1'b0 && Filter_cnt!=2'b00) Filter_cnt <= Filter_cnt - 1'd1;
if(Filter_cnt==2'b11) RxD_bit <= 1'b1;
else
if(Filter_cnt==2'b00) RxD_bit <= 1'b0;
end
// and decide when is the good time to sample the RxD line
function integer log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1; end endfunction
localparam l2o = log2(Oversampling);
reg [l2o-2:0] OversamplingCnt = 0;
always @(posedge clk) if(OversamplingTick) OversamplingCnt <= (RxD_state==0) ? 1'd0 : OversamplingCnt + 1'd1;
wire sampleNow = OversamplingTick && (OversamplingCnt==Oversampling/2-1);
`endif
// now we can accumulate the RxD bits in a shift-register
always @(posedge clk)
case(RxD_state)
4'b0000: if(~RxD_bit) RxD_state <= `ifdef SIMULATION 4'b1000 `else 4'b0001 `endif; // start bit found?
4'b0001: if(sampleNow) RxD_state <= 4'b1000; // sync start bit to sampleNow
4'b1000: if(sampleNow) RxD_state <= 4'b1001; // bit 0
4'b1001: if(sampleNow) RxD_state <= 4'b1010; // bit 1
4'b1010: if(sampleNow) RxD_state <= 4'b1011; // bit 2
4'b1011: if(sampleNow) RxD_state <= 4'b1100; // bit 3
4'b1100: if(sampleNow) RxD_state <= 4'b1101; // bit 4
4'b1101: if(sampleNow) RxD_state <= 4'b1110; // bit 5
4'b1110: if(sampleNow) RxD_state <= 4'b1111; // bit 6
4'b1111: if(sampleNow) RxD_state <= 4'b0010; // bit 7
4'b0010: if(sampleNow) RxD_state <= 4'b0000; // stop bit
default: RxD_state <= 4'b0000;
endcase
always @(posedge clk)
if(sampleNow && RxD_state[3]) RxD_data <= {RxD_bit, RxD_data[7:1]};
//reg RxD_data_error = 0;
always @(posedge clk)
begin
RxD_data_ready <= (sampleNow && RxD_state==4'b0010 && RxD_bit); // make sure a stop bit is received
//RxD_data_error <= (sampleNow && RxD_state==4'b0010 && ~RxD_bit); // error if a stop bit is not received
end
reg [l2o+1:0] GapCnt = 0;
always @(posedge clk) if (RxD_state!=0) GapCnt<=0; else if(OversamplingTick & ~GapCnt[log2(Oversampling)+1]) GapCnt <= GapCnt + 1'h1;
assign RxD_idle = GapCnt[l2o+1];
always @(posedge clk) RxD_endofpacket <= OversamplingTick & ~GapCnt[l2o+1] & &GapCnt[l2o:0];
endmodule
////////////////////////////////////////////////////////
// dummy module used to be able to raise an assertion in Verilog
module ASSERTION_ERROR();
endmodule
////////////////////////////////////////////////////////
module BaudTickGen(
input clk, enable,
output tick // generate a tick at the specified baud rate * oversampling
);
parameter ClkFrequency = 25000000;
parameter Baud = 115200;
parameter Oversampling = 1;
function integer
log2(input integer v); begin log2=0; while(v>>log2) log2=log2+1;
end endfunction
localparam AccWidth = log2(ClkFrequency/Baud)+8; // +/- 2% max timing error over a byte
reg [AccWidth:0] Acc = 0;
localparam ShiftLimiter = log2(Baud*Oversampling >> (31-AccWidth)); // this makes sure Inc calculation doesn't overflow
localparam Inc = ((Baud*Oversampling << (AccWidth-ShiftLimiter))+(ClkFrequency>>(ShiftLimiter+1)))/(ClkFrequency>>ShiftLimiter);
always @(posedge clk)
if(enable) Acc <= Acc[AccWidth-1:0] + Inc[AccWidth:0];
else Acc <= Inc[AccWidth:0];
assign tick = Acc[AccWidth];
endmodule
////////////////////////////////////////////////////////
|
#include <bits/stdc++.h> using namespace std; long long N, x, y, awal, centre, nb, a; bool visited[100005]; vector<long long> adj[100005]; vector<int> ans; void dfs(int x) { int s = adj[x].size(); visited[x] = 1; bool cek = 1; for (int i = 0; i < s; i++) { nb = adj[x][i]; if (!visited[nb]) { cek = 0; dfs(nb); } } if (cek) ans.push_back(x); } int main() { cin >> N; for (int i = 1; i < N; i++) { cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } for (int i = 1; i <= N; i++) { if (adj[i].size() >= 3) { awal = i; centre++; } } if (centre > 1) cout << No n ; else { if (centre == 0) { dfs(1); cout << Yes n << 1 << n ; for (int i = 1; i <= N; i++) { if (adj[i].size() == 1) { cout << i; a++; if (a == 1) cout << ; } } cout << n ; } if (centre == 1) { dfs(awal); cout << Yes n << ans.size() << n ; for (int i = 0; i < ans.size(); i++) { cout << awal << << ans[i] << n ; } } } } |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module pulse_gen_core #(
parameter ABUSWIDTH = 16
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
input wire BUS_RD,
input wire BUS_WR,
output reg [7:0] BUS_DATA_OUT,
input wire PULSE_CLK,
input wire EXT_START,
output reg PULSE
);
localparam VERSION = 3;
wire SOFT_RST;
wire START;
reg CONF_EN;
reg [31:0] CONF_DELAY;
reg [31:0] CONF_WIDTH;
reg [31:0] CONF_REPEAT;
reg CONF_DONE;
always @(posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= {7'b0, CONF_DONE};
else if(BUS_ADD == 2)
BUS_DATA_OUT <= {7'b0, CONF_EN};
else if(BUS_ADD == 3)
BUS_DATA_OUT <= CONF_DELAY[7:0];
else if(BUS_ADD == 4)
BUS_DATA_OUT <= CONF_DELAY[15:8];
else if(BUS_ADD == 5)
BUS_DATA_OUT <= CONF_DELAY[23:16];
else if(BUS_ADD == 6)
BUS_DATA_OUT <= CONF_DELAY[31:24];
else if(BUS_ADD == 7)
BUS_DATA_OUT <= CONF_WIDTH[7:0];
else if(BUS_ADD == 8)
BUS_DATA_OUT <= CONF_WIDTH[15:8];
else if(BUS_ADD == 9)
BUS_DATA_OUT <= CONF_WIDTH[23:16];
else if(BUS_ADD == 10)
BUS_DATA_OUT <= CONF_WIDTH[31:24];
else if(BUS_ADD == 11)
BUS_DATA_OUT <= CONF_REPEAT[7:0];
else if(BUS_ADD == 12)
BUS_DATA_OUT <= CONF_REPEAT[15:8];
else if(BUS_ADD == 13)
BUS_DATA_OUT <= CONF_REPEAT[23:16];
else if(BUS_ADD == 14)
BUS_DATA_OUT <= CONF_REPEAT[31:24];
else
BUS_DATA_OUT <= 8'b0;
end
end
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign START = (BUS_ADD==1 && BUS_WR);
wire RST;
assign RST = BUS_RST | SOFT_RST;
always @(posedge BUS_CLK) begin
if(RST) begin
CONF_EN <= 0;
CONF_DELAY <= 0;
CONF_WIDTH <= 0;
CONF_REPEAT <= 1;
end
else if(BUS_WR) begin
if(BUS_ADD == 2)
CONF_EN <= BUS_DATA_IN[0];
else if(BUS_ADD == 3)
CONF_DELAY[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 4)
CONF_DELAY[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 5)
CONF_DELAY[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 6)
CONF_DELAY[31:24] <= BUS_DATA_IN;
else if(BUS_ADD == 7)
CONF_WIDTH[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 8)
CONF_WIDTH[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 9)
CONF_WIDTH[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 10)
CONF_WIDTH[31:24] <= BUS_DATA_IN;
else if(BUS_ADD == 11)
CONF_REPEAT[7:0] <= BUS_DATA_IN;
else if(BUS_ADD == 12)
CONF_REPEAT[15:8] <= BUS_DATA_IN;
else if(BUS_ADD == 13)
CONF_REPEAT[23:16] <= BUS_DATA_IN;
else if(BUS_ADD == 14)
CONF_REPEAT[31:24] <= BUS_DATA_IN;
end
end
wire CONF_EN_SYNC;
three_stage_synchronizer conf_en_sync (
.CLK(PULSE_CLK),
.IN(CONF_EN),
.OUT(CONF_EN_SYNC)
);
wire [31:0] CONF_DELAY_SYNC;
three_stage_synchronizer #(
.WIDTH(32)
) conf_dely_sync (
.CLK(PULSE_CLK),
.IN(CONF_DELAY),
.OUT(CONF_DELAY_SYNC)
);
wire [31:0] CONF_WIDTH_SYNC;
three_stage_synchronizer #(
.WIDTH(32)
) conf_width_sync (
.CLK(PULSE_CLK),
.IN(CONF_WIDTH),
.OUT(CONF_WIDTH_SYNC)
);
wire [31:0] CONF_REPEAT_SYNC;
three_stage_synchronizer #(
.WIDTH(32)
) conf_repeat_sync (
.CLK(PULSE_CLK),
.IN(CONF_REPEAT),
.OUT(CONF_REPEAT_SYNC)
);
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(PULSE_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire START_SYNC;
cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(PULSE_CLK), .pulse_out(START_SYNC));
wire EXT_START_SYNC;
reg [2:0] EXT_START_FF;
always @(posedge PULSE_CLK) // first stage
begin
EXT_START_FF[0] <= EXT_START;
EXT_START_FF[1] <= EXT_START_FF[0];
EXT_START_FF[2] <= EXT_START_FF[1];
end
assign EXT_START_SYNC = !EXT_START_FF[2] & EXT_START_FF[1];
reg [31:0] CNT;
wire [32:0] LAST_CNT;
assign LAST_CNT = CONF_DELAY_SYNC + CONF_WIDTH_SYNC;
reg [31:0] REAPAT_CNT;
always @(posedge PULSE_CLK) begin
if (RST_SYNC)
REAPAT_CNT <= 0;
else if(START_SYNC || (EXT_START_SYNC && CONF_EN_SYNC))
REAPAT_CNT <= CONF_REPEAT_SYNC;
else if(REAPAT_CNT != 0 && CNT == 1)
REAPAT_CNT <= REAPAT_CNT - 1;
end
always @(posedge PULSE_CLK) begin
if (RST_SYNC)
CNT <= 0; //IS THIS RIGHT?
else if(START_SYNC || (EXT_START_SYNC && CONF_EN_SYNC))
CNT <= 1;
else if(CNT == LAST_CNT && REAPAT_CNT != 0)
CNT <= 1;
else if(CNT == LAST_CNT && CONF_REPEAT_SYNC == 0)
CNT <= 1;
else if(CNT == LAST_CNT && REAPAT_CNT == 0)
CNT <= 0;
else if(CNT != 0)
CNT <= CNT + 1;
end
always @(posedge PULSE_CLK) begin
if(RST_SYNC || START_SYNC || (EXT_START_SYNC && CONF_EN_SYNC))
PULSE <= 0;
else if(CNT == CONF_DELAY_SYNC && CNT > 0)
PULSE <= 1;
else if(CNT == LAST_CNT)
PULSE <= 0;
end
wire DONE;
assign DONE = (CNT == 0);
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(PULSE_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
wire EXT_START_SYNC_BUS;
cdc_pulse_sync ex_start_pulse_sync (.clk_in(PULSE_CLK), .pulse_in(EXT_START && CONF_EN), .clk_out(BUS_CLK), .pulse_out(EXT_START_SYNC_BUS));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START || EXT_START_SYNC_BUS)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; while (T > 0) { T--; string a, b; int d; cin >> a >> b; for (int i = 0; i < b.length(); i++) if (b[b.size() - i - 1] == 1 ) { d = i; break; } for (int i = d; i <= a.size() - 1; i++) { if (a[a.size() - i - 1] == 1 ) { cout << i - d << endl; d = 100005; break; } } if (d != 100005) { cout << a.size() - b.size() << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using ull = unsigned long long; using str = string; using srt = short; const int INF = (int)1e9 + 4; const int MOD = (int)1e9 + 7; const int N = 1005; const ll inf = (ll)4e18; const ll mod = 998244353; bool us[N][N]; set<pair<int, int>> ans; vector<pair<int, int>> arr(3); vector<pair<int, int>> dirs = {{-1, 0}, {1, 0}, {0, -1}, {0, 1}}; int dist(pair<int, int> a, pair<int, int> b) { return abs(a.first - b.first) + abs(a.second - b.second); } void vToV(int st, int en) { int x1 = arr[st].first, y1 = arr[st].second, x2 = arr[en].first, y2 = arr[en].second; ans.insert({x1, y1}); while (x1 != x2 || y1 != y2) { us[x1][y1] = 1; if (x1 < x2 && us[x1 + 1][y1]) { ans.insert({++x1, y1}); } else if (y1 < y2 && us[x1][y1 + 1]) { ans.insert({x1, ++y1}); } else if (y1 > y2 && us[x1][y1 - 1]) { ans.insert({x1, --y1}); } else { int dst = INF; pair<int, int> dir; for (auto it : dirs) { int now = dist({x1 + it.first, y1 + it.second}, {x2, y2}); if (now < dst) { dir = it; dst = now; } } x1 += dir.first; y1 += dir.second; ans.insert({x1, y1}); } } } int main() { ios::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); for (auto &it : arr) { cin >> it.first >> it.second; ans.insert(it); us[it.first][it.second] = 1; } sort(begin(arr), end(arr)); arr.emplace_back(arr.back()); vToV(0, 1); vToV(1, 2); cout << ans.size() << endl; for (auto &it : ans) cout << it.first << << it.second << endl; } |
#include <bits/stdc++.h> using namespace std; const long long MAX = 150004; const long long mod = 998244353; struct edge { long long next, to; } h[MAX << 1]; long long head[MAX], cnt, cnt_dfsn; long long n, q, ans, inv; inline void add(long long x, long long y) { h[++cnt] = edge{head[x], y}; head[x] = cnt; h[++cnt] = edge{head[y], x}; head[y] = cnt; } long long dfsn[MAX], size[MAX], son[MAX], fa[MAX], top[MAX], w[MAX]; long long tree[MAX]; inline long long lowbit(long long x) { return x & (-x); } inline void ad(long long x, long long y) { y %= mod; for (long long i = x; i <= n; i += lowbit(i)) tree[i] = (tree[i] + y) % mod; } inline long long sum(long long x) { long long ret = 0; for (long long i = x; i; i -= lowbit(i)) ret = (ret + tree[i]) % mod; return ret; } inline long long quick(long long x, long long y) { long long ret = 1ll; while (y) { if (y & 1) ret = (ret * x) % mod; y >>= 1; x = (x * x) % mod; } return ret; } void dfs1(long long now, long long father) { fa[now] = father; size[now] = 1; for (long long i = head[now]; i; i = h[i].next) { long long aim = h[i].to; if (aim != father) { dfs1(aim, now); size[now] += size[aim]; if (size[aim] > size[son[now]]) son[now] = aim; } } } void dfs2(long long now, long long start) { top[now] = start; dfsn[now] = ++cnt_dfsn; if (son[now]) dfs2(son[now], start); for (long long i = head[now]; i; i = h[i].next) { long long aim = h[i].to; if (aim != fa[now] && aim != son[now]) { dfs2(aim, aim); } } } signed main() { scanf( %lld %lld , &n, &q); inv = quick(n, mod - 2); for (long long x, y, i = 1; i < n; i++) scanf( %lld %lld , &x, &y), add(x, y); dfs1(1, 1), dfs2(1, 1); fa[1] = 0; for (long long op, x, y, i = 1; i <= q; i++) { scanf( %lld , &op); if (op == 1) { scanf( %lld %lld , &x, &y); w[x] = (w[x] + y) % mod; ad(1, size[x] * y % mod); ad(dfsn[x], (mod - size[x] * y % mod) % mod), ad(dfsn[x] + size[x], size[x] * y % mod); if (son[x]) ad(dfsn[son[x]], (n - size[son[x]]) * y % mod), ad(dfsn[son[x]] + size[son[x]], mod - (n - size[son[x]]) * y % mod); } else { scanf( %lld , &x); ans = (sum(dfsn[x]) + n * w[x] % mod) % mod; for (long long j = top[x]; fa[j]; j = top[fa[j]]) ans = (ans + (n - size[j]) * w[fa[j]] % mod) % mod; printf( %lld n , (ans * inv) % mod); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int read() { char c = getchar(); int t = 0, f = 1; while (c > 9 || c < 0 ) f = (c == - ) ? -1 : 1, c = getchar(); while (c >= 0 && c <= 9 ) t = t * 10 + c - 0 , c = getchar(); return t * f; } struct node { int L, R, po, id; bool operator<(const node &b) const { if (po == b.po) return R < b.R; return po < b.po; } } p[200005]; int n, Q, K, sq, a[200005], op[200005], id[200005], uid[200005], did[200005], cnt[200005]; long long sum[200005], st[200005], ans[200005], now; int main() { n = read(), K = read(), sq = sqrt(n); for (int i = 1; i <= n; i++) op[i] = (read() == 1) ? 1 : -1; for (int i = 1; i <= n; i++) a[i] = read(), st[i] = sum[i] = sum[i - 1] + a[i] * op[i]; st[n + 1] = 0, sort(st + 1, st + n + 2); int tp = unique(st + 1, st + n + 2) - st - 1; for (int i = 0; i <= n; i++) { id[i] = lower_bound(st + 1, st + tp + 1, sum[i]) - st; int up = lower_bound(st + 1, st + tp + 1, sum[i] + K) - st; if (st[up] == sum[i] + K) uid[i] = up; int down = lower_bound(st + 1, st + tp + 1, sum[i] - K) - st; if (st[down] == sum[i] - K) did[i] = down; } Q = read(); for (int i = 1, x, y, z; i <= Q; i++) x = read() - 1, y = read(), z = x / sq, p[i] = (node){x, y, z, i}; sort(p + 1, p + Q + 1); for (int i = p[1].L; i <= p[1].R; i++) now += cnt[did[i]], cnt[id[i]]++; ans[p[1].id] = now; for (int i = 2; i <= n; i++) { int L = p[i - 1].L, R = p[i - 1].R; while (R < p[i].R) R++, now += cnt[did[R]], cnt[id[R]]++; while (R > p[i].R) cnt[id[R]]--, now -= cnt[did[R]], R--; while (L > p[i].L) L--, now += cnt[uid[L]], cnt[id[L]]++; while (L < p[i].L) cnt[id[L]]--, now -= cnt[uid[L]], L++; ans[p[i].id] = now; } for (int i = 1; i <= Q; i++) printf( %lld n , ans[i]); } |
#include <bits/stdc++.h> using namespace std; struct E { int a, b, c; }; struct unionfind { vector<int> p, s; int c; unionfind(int n) : p(n, -1), s(n, 1), c(n) {} int find(int a) { return p[a] == -1 ? a : find(p[a]); } vector<pair<int *, int>> buf; void save(int &a) { buf.emplace_back(&a, a); } int snapshot() { return buf.size(); } void rollback(int w) { while (buf.size() > w) { int *a, b; tie(a, b) = buf.back(); buf.pop_back(); *a = b; } } bool unite(int a, int b) { a = find(a); b = find(b); if (a == b) return false; if (s[a] < s[b]) swap(a, b); save(p[b]); save(s[a]); p[b] = a; s[a] += s[b]; return true; } bool same(int a, int b) { return find(a) == find(b); } int sz(int a) { return s[find(a)]; } }; int main() { cin.tie(0); ios::sync_with_stdio(0); int n, m; cin >> n >> m; vector<E> raw(m); map<int, vector<pair<int, int>>> es; for (int i = 0; i < m; ++i) { int a, b, c; cin >> a >> b >> c; a--; b--; es[c].push_back({a, b}); raw[i] = {a, b, c}; } map<int, vector<pair<int, vector<int>>>> qs; int q; cin >> q; vector<int> ans(q, 1); for (int i = 0; i < q; ++i) { int k; cin >> k; vector<int> idx(k); for (int j = 0; j < k; ++j) { cin >> idx[j]; idx[j]--; } sort(idx.begin(), idx.end(), [&](int a, int b) { return raw[a].c < raw[b].c; }); for (int j = 0; j < k;) { vector<int> w; int r = j; while (r < k && raw[idx[r]].c == raw[idx[j]].c) { w.push_back(idx[r++]); } qs[raw[idx[j]].c].emplace_back(i, w); j = r; } } unionfind uf(n); for (auto kv : es) { for (auto z : qs[kv.first]) { int s = uf.snapshot(); for (auto i : z.second) { if (!uf.unite(raw[i].a, raw[i].b)) { ans[z.first] = 0; } } uf.rollback(s); } for (auto e : kv.second) { uf.unite(e.first, e.second); } } for (int i = 0; i < q; ++i) { if (ans[i]) cout << YES << n ; else cout << NO << n ; } } |
#include <bits/stdc++.h> using namespace std; const int inf = 1e6 + 7, Inf = 1e9 + 7; int n, m, k = Inf, x, l, r, f, a[inf], b[inf], c[inf], d[inf]; map<int, int> p[inf]; vector<int> v; string s; int main() { cin >> n >> s; for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = 1; i < n; ++i) if (s[i] == L && s[i - 1] == R ) k = min(k, (a[i] - a[i - 1]) / 2); if (k == Inf) cout << -1; else cout << k; } |
#include <bits/stdc++.h> using namespace std; const int N = 200 + 5; const int LEN = 1e6 + 10; int n, m, q; int a[N]; int b[N]; int f[N][N]; char ch[LEN]; int g[LEN], l; int xt[N * N], yt[N * N]; int dp[N][N]; int cnt, cir[N * N][10]; int lc[N * N]; int c0[N][N]; int bel[N][N]; int nx[N][N], ny[N][N]; int rd[N][N]; int v[N][N], cc; int pre[N][N]; bool check(int x, int y) { if (x <= 0 || y <= 0 || x >= n + 1 || y >= m + 1) return false; else return true; } void dfs_1(int x, int y) { v[x][y] = cc; int x0 = nx[x][y], y0 = ny[x][y]; if (v[x0][y0] > 0) { if (v[x0][y0] == cc) c0[x0][y0] = ++cnt; return; } dfs_1(x0, y0); } void dfs_2(int x, int y, int k) { v[x][y] = k; bel[x][y] = k; cir[k][f[x][y]] = true; int x0 = nx[x][y], y0 = ny[x][y]; if (v[x0][y0] > 0) return; dfs_2(x0, y0, k); } void init() { cin >> n >> m >> q; memset(v, 0, sizeof(v)); for (int i = 1; i <= n; i++) { scanf( %s , ch); for (int j = 1; j <= m; j++) f[i][j] = ch[j - 1] - 0 ; } for (int i = 0; i < 10; i++) scanf( %d %d , &a[i], &b[i]); cnt = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { nx[i][j] = i + a[f[i][j]]; ny[i][j] = j + b[f[i][j]]; if (!check(nx[i][j], ny[i][j])) { nx[i][j] = i; ny[i][j] = j; bel[i][j] = ++cnt; v[i][j] = cnt; cir[cnt][f[i][j]] = true; } rd[nx[i][j]][ny[i][j]]++; } cc = cnt; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (v[i][j] == 0) { cc++; dfs_1(i, j); } memset(v, 0, sizeof(v)); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (c0[i][j] > 0) { dfs_2(i, j, c0[i][j]); } } bool bfs() { int L, R, x1, y1, x2, y2; L = 1, R = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) if (rd[i][j] == 0) { R++; xt[R] = i, yt[R] = j; pre[i][j] = 0; } else pre[i][j] = rd[i][j]; while (L <= R) { x1 = xt[L], y1 = yt[L]; x2 = nx[x1][y1], y2 = ny[x1][y1]; if (dp[x1][y1] >= l) return true; if (g[dp[x1][y1] + 1] == f[x1][y1]) dp[x1][y1]++; dp[x2][y2] = max(dp[x1][y1], dp[x2][y2]); pre[x2][y2]--; if (pre[x2][y2] == 0) { R++; xt[R] = x2, yt[R] = y2; } if (bel[x2][y2] != 0) { if (lc[bel[x2][y2]] <= dp[x2][y2]) return true; } L++; } return false; } void work() { bool sign; for (int i = 1; i <= q; i++) { scanf( %s , ch); l = strlen(ch); memset(dp, 0, sizeof(dp)); for (int j = 1; j <= l; j++) g[j] = ch[j - 1] - 0 ; sign = false; for (int j = 1; j <= cnt; j++) { lc[j] = l; while (cir[j][g[lc[j]]] && lc[j] != 0) lc[j]--; if (lc[j] == 0) { sign = true; break; } } if (sign) { cout << YES << endl; continue; } if (bfs()) cout << YES << endl; else cout << NO << endl; } } int main() { init(); work(); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; int a[301]; int l[301], r[301]; void INPUT() { cin >> n >> m; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1; i <= m; i++) cin >> l[i] >> r[i]; } void SOLVE() { int res = 0; int ans[301], tam[301]; int sl = 0; int i, j, k; for (i = 1; i <= n; i++) for (j = 1; j <= n; j++) if (i == j) continue; else { int dem = 0; for (k = 1; k <= m; k++) if (l[k] <= j & j <= r[k] & (l[k] > i || r[k] < i)) { dem++; tam[dem] = k; } if (res < a[i] - a[j] + dem) { res = a[i] - a[j] + dem; sl = dem; for (k = 1; k <= sl; k++) ans[k] = tam[k]; } } cout << res << endl; cout << sl << endl; for (i = 1; i <= sl; i++) cout << ans[i] << ; } int main() { INPUT(); SOLVE(); } |
#include <bits/stdc++.h> using namespace std; const int MAXN = (int)1e6 + 5; const int INF = (int)1e9 + 7; int main() { ios_base ::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long int a, b, c, d; cin >> a >> b >> c >> d; if (a + b == c + d or a + c == b + d or a + d == c + b or a + b + c == d or a + c + d == b or a + b + d == c or a == b + c + d) { cout << YES ; return 0; } cout << NO ; } |
#include <bits/stdc++.h> using namespace std; long long t, n; int main() { cin >> t; vector<int> a; for (int i = 1; i <= 10000; i++) { n = i; vector<int> v; while (n > 0) { v.push_back(n % 10); n = n / 10; } reverse(v.begin(), v.end()); for (int j = 0; j < v.size(); j++) { a.push_back(v[j]); } } for (int i = 0; i < a.size(); i++) { if (i + 1 == t) { cout << a[i]; return 0; } } return 0; } |
// Hazard checking unit
module hazard_unit
(
input wire[4:0] rs1_ex_mem_hz_i,
input wire[4:0] rs2_ex_mem_hz_i,
input wire[4:0] rd_mem_wb_hz_i,
input wire[4:0] rd_wb_ret_hz_i,
input wire[1:0] op2sel_ex_mem_hz_i,
input wire rf_en_mem_wb_hz_i,
input wire rf_en_wb_ret_hz_i,
input wire branch_taken_ex_mem_hz_i,
input wire jump_iss_ex_hz_i,
input wire brn_pred_ex_mem_hz_i,
output wire stall_fetch_hz_o,
output wire stall_iss_hz_o,
output wire flush_ex_hz_o,
output wire flush_iss_hz_o,
output wire[1:0] fwd_p1_ex_mem_hz_o,
output wire[1:0] fwd_p2_ex_mem_hz_o
);
wire stall_fetch_hz;
wire stall_iss_hz;
wire flush_ex_hz;
wire flush_iss_hz;
wire[1:0] fwd_p1_ex_mem_hz;
wire[1:0] fwd_p2_ex_mem_hz;
assign stall_fetch_hz_o = stall_fetch_hz;
assign stall_iss_hz_o = stall_iss_hz;
assign flush_ex_hz_o = flush_ex_hz;
assign flush_iss_hz_o = flush_iss_hz;
assign fwd_p1_ex_mem_hz_o = fwd_p1_ex_mem_hz;
assign fwd_p2_ex_mem_hz_o = fwd_p2_ex_mem_hz;
// Forward the data only when we are writing to a non-zero register
// in the WB/MEM stage and the same register is being read at the
// EX stage
assign fwd_p1_ex_mem_hz = (rf_en_mem_wb_hz_i & |rd_mem_wb_hz_i &
(rd_mem_wb_hz_i == rs1_ex_mem_hz_i)) ? 2'b10
: (rf_en_wb_ret_hz_i & |rd_wb_ret_hz_i &
(rd_wb_ret_hz_i == rs1_ex_mem_hz_i)) ? 2'b01
: 2'b00;
assign fwd_p2_ex_mem_hz = (rf_en_mem_wb_hz_i & |rd_mem_wb_hz_i &
(rd_mem_wb_hz_i == rs2_ex_mem_hz_i)) ? 2'b10
: (rf_en_wb_ret_hz_i & |rd_wb_ret_hz_i &
(rd_wb_ret_hz_i == rs2_ex_mem_hz_i)) ? 2'b01
: 2'b00;
// All forwarding paths have been implemented
// There is no need to stall either Fetch or
// the Issue stage of the pipelines
assign stall_fetch_hz = 1'b0;
assign stall_iss_hz = 1'b0;
// Branches would be resolved in the EXECUTE stage
// the following signals should be based on those values
// This is required to flush the value in the EX Pipe register
// to a NO-OP.
assign flush_ex_hz = branch_taken_ex_mem_hz_i & ~brn_pred_ex_mem_hz_i;
// Jumps would be resolved in the ISSUE (DECODE) stage
// the following signals should be based on those values
assign flush_iss_hz = (branch_taken_ex_mem_hz_i & ~brn_pred_ex_mem_hz_i) | jump_iss_ex_hz_i;
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; int find_first_num_index(long long &k, long long n) { if (n == 1) { return 0; } n--; int first_num_index; long long n_partial_fact = n; while (k >= n_partial_fact && n > 1) { n_partial_fact *= (n - 1); n--; } first_num_index = k / n_partial_fact; k %= n_partial_fact; return first_num_index; } vector<long long> find_kth_permutation(long long n, long long k) { vector<long long> Ans; set<long long> S; for (int i = 1; i <= n; i++) { S.insert(i); } auto itr = S.begin(); k -= 1; for (int i = 0; i < n; i++) { int index = find_first_num_index(k, n - i); advance(itr, index); Ans.push_back((*itr)); S.erase(itr); itr = S.begin(); } return Ans; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); long long n, q, t, x = 1; cin >> n >> q; long long suff_len = min(14LL, n); long long pref_len = n - suff_len; long long Sil[20]; Sil[0] = 1; for (int i = 1; i <= suff_len; i++) { Sil[i] = Sil[i - 1] * i; } vector<long long> Suff = find_kth_permutation(suff_len, 1); while (q--) { cin >> t; if (t == 1) { long long l, r, ans = 0; cin >> l >> r; int r_pr = min(r, pref_len); if (l <= r_pr) { ans += 1ll * (l + r_pr) * (r_pr - l + 1) / 2; } r -= pref_len + 1; l -= pref_len + 1; r_pr = max(r_pr - pref_len - 1, 0LL); for (int i = max(l, 0LL); i <= r; i++) { ans += pref_len + Suff[i]; } cout << ans << endl; } else { int dx; cin >> dx; x += dx; x = min(x, Sil[suff_len]); Suff = find_kth_permutation(suff_len, x); } } return 0; } |
// DEFINES
`define BITS 2 // Bit width of the operands
module bm_if_common(clock,
reset_n,
a_in,
b_in,
c_in,
d_in,
out0,
out2,
out1);
// SIGNAL DECLARATIONS
input clock;
input reset_n;
input [`BITS-1:0] a_in;
input [`BITS-1:0] b_in;
input c_in;
input d_in;
output [`BITS-1:0] out0;
output [`BITS-1:0] out2;
output out1;
reg [`BITS-1:0] out0;
reg [`BITS-1:0] out2;
reg out1;
wire [`BITS-1:0] temp_a;
wire [`BITS-1:0] temp_b;
wire temp_c;
wire temp_d;
a top_a(clock, a_in, temp_a);
always @(posedge clock)
begin
if (c_in == 1'b0)
begin
out0 <= 2'b00;
out1 <= 1'b0;
end
else
begin
out0 <= a_in & b_in;
out1 <= c_in & d_in;
end
out2 <= temp_a;
end
endmodule
/*---------------------------------------------------------*/
module a(clock,
a_in,
out);
input clock;
input [`BITS-1:0] a_in;
output [`BITS-1:0] out;
reg [`BITS-1:0] out;
reg [`BITS-1:0] out1;
reg [`BITS-1:0] out2;
always @(posedge clock)
begin
case (a_in)
2'b00: out2 <= 2'b11 ;
2'b01: out1 <= 2'b10 ;
2'b10: out1 <= 2'b01 ;
2'b11: out1 <= 2'b00 ;
endcase
out <= out1 & out2;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:23:50 04/19/2016
// Design Name:
// Module Name: clock
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clock(
output [3:0] hourTens,hourMu, minTens,minMu,
output sig1s,
input clk10hz,
input setH,
input setM
);
parameter dGND = 4'b0000;
parameter h = 1'b1;
wire [3:0] qS___, qS__, qS_;
wire rcoS___, rcoS__, rcoS_, rcoM__, rcoM_, rcoH__, rcoH_;
wire qS__d1,qS__d2,qS__d3, qS_d0, qS_d1, qS_d2, qS_d3;
assign nand1 = !(qS_[0] & qS_[2] & rcoS__);
assign nand2 = !(nand1 & setM);
assign nand3 = !(minTens[0] & minTens[2] & rcoM__);
assign nand4 = !(((setM&nand3)|(!setM)) & setH);
assign nand5 = !(nand4 & hourMu[0] & hourMu[1] & hourTens[1]); //24 reset
assign sig1s = qS__[0];
c74160 s___(qS___, rcoS___, dGND, h, h, clk10hz,h);
c74160 s__(qS__, rcoS__, dGND, rcoS___, h, clk10hz,h);
c74160 s_(qS_, rcoS_, dGND, rcoS__, nand1, clk10hz, h);
c74160 m__(minMu, rcoM__, dGND, nand2, h, clk10hz, h);
c74160 m_(minTens, rcoM_, dGND, rcoM__, nand3, clk10hz, h);
c74160 h__(hourMu, rcoH__, dGND, nand4, nand5, clk10hz, h);
c74160 h_(hourTens, rcoH_, dGND, rcoH__, nand5, clk10hz, h);
endmodule
|
module OSERDESE2 ( /*AUTOARG*/
// Outputs
OFB, OQ, SHIFTOUT1, SHIFTOUT2, TBYTEOUT, TFB, TQ,
// Inputs
CLK, CLKDIV, D1, D2, D3, D4, D5, D6, D7, D8, OCE, RST, SHIFTIN1,
SHIFTIN2, T1, T2, T3, T4, TBYTEIN, TCE
);
parameter DATA_RATE_OQ=0;
parameter DATA_RATE_TQ=0;
parameter DATA_WIDTH=0;
parameter INIT_OQ=0;
parameter INIT_TQ=0;
parameter SERDES_MODE=0;
parameter SRVAL_OQ=0;
parameter SRVAL_TQ=0;
parameter TBYTE_CTL=0;
parameter TBYTE_SRC=0;
parameter TRISTATE_WIDTH=0;
output OFB; // output feedback port
output OQ; // data output port, D1 appears first
output SHIFTOUT1; // connect to shift in of master, example?
output SHIFTOUT2; // connect to shift in of master, example?
output TBYTEOUT; // byte group tristate output to IOB
output TFB; // 3-state control output for ODELAYE2
output TQ; // 3-state control output
input CLK; // high speed clock
input CLKDIV; // low speed clock (/8 for example)
input D1; //
input D2; //
input D3; //
input D4; //
input D5; //
input D6; //
input D7; //
input D8; //
input OCE; // active high clock enable for datapath
input RST; // async reset, all output flops driven low
input SHIFTIN1; // connect to shift out of other
input SHIFTIN2; // connect to shift out of other
input T1; // parallel 3-state signals
input T2; // ??why 4??
input T3; //
input T4; //
input TBYTEIN; // byte group tristate input
input TCE; // active high clock enable for 3-state
//Statemachine
reg [2:0] state;
reg [7:0] buffer;
reg [1:0] clkdiv_sample;
reg [3:0] even;
reg [3:0] odd;
//parallel sample
always @ (posedge CLKDIV)
buffer[7:0]<={D8,D7,D6,D5,D4,D3,D2,D1};
//sample clkdiv
always @ (negedge CLK)
clkdiv_sample[1:0] <= {clkdiv_sample[0],CLKDIV};
//shift on second consective clk rising edge that clkdi_sample==0
wire load_parallel = (clkdiv_sample[1:0]==2'b00);
always @ (negedge CLK)
if(load_parallel)
even[3:0]<={buffer[6],buffer[4],buffer[2],buffer[0]};
else
even[3:0]<={1'b0,even[3:1]};
always @ (negedge CLK)
if(load_parallel)
odd[3:0]<={buffer[7],buffer[5],buffer[3],buffer[1]};
else
odd[3:0]<={1'b0,odd[3:1]};
assign OQ = CLK ? even[0] : odd[0];
//setting other outputs
assign OFB = 1'b0;
assign TQ = 1'b0;
assign TBYTEOUT = 1'b0;
assign SHIFTOUT1 = 1'b0;
assign SHIFTOUT2 = 1'b0;
assign TFB = 1'b0;
endmodule // OSERDESE2
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_PP_SYMBOL_V
`define SKY130_FD_SC_HD__NOR4B_PP_SYMBOL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; string s; for (int j = 0; j < t; j++) { cin >> s; int n = s.size(); cout << s[0]; for (int i = 1; i < n - 1; i++) { if (s[i] == s[i + 1]) { cout << s[i]; i += 1; } } cout << s[n - 1]; cout << endl; } return 0; } |
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg pass;
reg [7:0] in;
reg [3:0] out;
initial begin
pass = 1'b1;
in = 8'b10100101;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in[7:'dx];
`else
out = 4'bxxxx;
`endif
if (out !== 4'bxxxx) begin
$display("FAILED: part select LSB is X, expected 4'bxxxx, got %b", out);
pass = 1'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in['dx:0];
`else
out = 4'bxxxx;
`endif
if (out !== 4'bxxxx) begin
$display("FAILED: part select MSB is X, expected 4'bxxxx, got %b", out);
pass = 1'b0;
end
out = 4'b0000;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out[0] = in['dx];
`else
out[0] = 1'bx;
`endif
if (out !== 4'b000x) begin
$display("FAILED: bit select is X, expected 4'b000x, got %b", out);
pass = 1'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in[7:'dz];
`else
out = 4'bxxxx;
`endif
if (out !== 4'bxxxx) begin
$display("FAILED: part select LSB is Z, expected 4'bxxxx, got %b", out);
pass = 1'b0;
end
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out = in['dz:0];
`else
out = 4'bxxxx;
`endif
if (out !== 4'bxxxx) begin
$display("FAILED: part select MSB is Z, expected 4'bxxxx, got %b", out);
pass = 1'b0;
end
out = 4'b0000;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
out[0] = in['dz];
`else
out[0] = 1'bx;
`endif
if (out !== 4'b000x) begin
$display("FAILED: bit select is Z, expected 4'b000x, got %b", out);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
//--------------------------------------------------------------------------------
// Logic_Sniffer.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Logic Analyzer top level module. It connects the core with the hardware
// dependend IO modules and defines all inputs and outputs that represent
// phyisical pins of the fpga.
//
// It defines two constants FREQ and RATE. The first is the clock frequency
// used for receiver and transmitter for generating the proper baud rate.
// The second defines the speed at which to operate the serial port.
//
//--------------------------------------------------------------------------------
//
// 12/29/2010 - Verilog Version + cleanups created by Ian Davis (IED) - mygizmos.org
//
`timescale 1ns/100ps
`define COMM_TYPE_SPI 1 // comment out for UART mode
module Logic_Sniffer #(
`ifdef COMM_TYPE_SPI
parameter [31:0] MEMORY_DEPTH=6,
parameter [31:0] CLOCK_SPEED=50,
parameter [1:0] SPEED=2'b00
`else
// Sets the speed for UART communications
// SYSTEM_JITTER = "1000 ps"
parameter FREQ = 100000000, // limited to 100M by onboard SRAM
parameter TRXSCALE = 28, // 100M / 28 / 115200 = 31 (5bit) --If serial communications are not working then try adjusting this number.
parameter RATE = 115200 // maximum & base rate
`endif
)(
// system signals
input wire bf_clock,
// logic analyzer signals
input wire extClockIn,
output wire extClockOut,
input wire extTriggerIn,
output wire extTriggerOut,
//
inout wire [31:0] extData,
//
output wire dataReady,
output wire armLEDnn,
output wire triggerLEDnn,
// host interface
`ifdef COMM_TYPE_SPI
input wire spi_sclk,
input wire spi_cs_n,
input wire spi_mosi,
output wire spi_miso
`else
input wire rx,
output wire tx
`endif
);
// system signals
wire sys_clk;
wire sys_clk_p;
wire sys_clk_n;
wire sys_rst = 1'b0;
// external signals
wire ext_clk_p;
wire ext_clk_n;
// data path signals
wire sti_clk_p;
wire sti_clk_n;
wire [31:0] sti_data;
wire [31:0] sti_data_p;
wire [31:0] sti_data_n;
wire extClock_mode;
wire extTestMode;
wire [39:0] cmd;
wire [31:0] sram_wrdata;
wire [31:0] sram_rddata;
wire [3:0] sram_rdvalid;
wire [31:0] stableInput;
wire [7:0] opcode;
wire [31:0] config_data;
assign {config_data,opcode} = cmd;
//--------------------------------------------------------------------------------
// clocking
//--------------------------------------------------------------------------------
wire sys_clk_ref;
wire sys_clk_buf;
wire ext_clk_ref;
wire ext_clk_buf;
// DCM: Digital Clock Manager Circuit for Virtex-II/II-Pro and Spartan-3/3E
// Xilinx HDL Language Template version 8.1i
DCM #(
.CLK_FEEDBACK("1X")
) dcm_sys_clk (
.CLKIN (bf_clock), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK (1'b 0), // Dynamic phase adjust clock input
.PSEN (1'b 0), // Dynamic phase adjust enable input
.PSINCDEC (1'b 0), // Dynamic phase adjust increment/decrement
.RST (1'b 0), // DCM asynchronous reset input
// clock outputs
.CLK2X (sys_clk),
.CLKFX (sys_clk_p),
.CLKFX180 (sys_clk_n),
// feedback
.CLK0 (sys_clk_ref),
.CLKFB (sys_clk_buf)
);
BUFG BUFG_sys_clk_fb (
.I (sys_clk_ref),
.O (sys_clk_buf)
);
DCM #(
.CLK_FEEDBACK("2X")
) dcm_ext_clk (
.CLKIN (extClockIn), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK (1'b 0), // Dynamic phase adjust clock input
.PSEN (1'b 0), // Dynamic phase adjust enable input
.PSINCDEC (1'b 0), // Dynamic phase adjust increment/decrement
.RST (1'b 0), // DCM asynchronous reset input
.CLK0 (ext_clk_p),
.CLK180 (ext_clk_n),
// feedback
.CLK2X (ext_clk_ref),
.CLKFB (ext_clk_buf)
);
BUFG BUFG_ext_clk_fb (
.I (ext_clk_ref),
.O (ext_clk_buf)
);
//
// Select between internal and external sampling clock...
//
//BUFGMUX bufmux_sti_clk [1:0] (
// .O ({sti_clk_p, sti_clk_n}), // Clock MUX output
// .I0 ({sys_clk_p, sys_clk_n}), // Clock0 input
// .I1 ({ext_clk_p, ext_clk_n}), // Clock1 input
// .S (extClock_mode) // Clock select
//);
assign sti_clk_p = sys_clk_p;
assign sti_clk_n = sys_clk_n;
//--------------------------------------------------------------------------------
// IO
//--------------------------------------------------------------------------------
// Use DDR output buffer to isolate clock & avoid skew penalty...
ODDR2 ODDR2 (
.Q (extClockOut),
.D0 (1'b0),
.D1 (1'b1),
.C0 (sti_clk_n),
.C1 (sti_clk_p),
.S (1'b0),
.R (1'b0)
);
//
// Configure the probe pins...
//
reg [10:0] test_counter;
always @ (posedge sys_clk, posedge sys_rst)
if (sys_rst) test_counter <= 'b0;
else test_counter <= test_counter + 'b1;
wire [15:0] test_pattern = {8{test_counter[10], test_counter[4]}};
IOBUF #(
.DRIVE (12), // Specify the output drive strength
.IBUF_DELAY_VALUE ("0"), // Specify the amount of added input delay for the buffer,
// "0"-"12" (Spartan-3E only)
.IFD_DELAY_VALUE ("AUTO"), // Specify the amount of added delay for input register,
// "AUTO", "0"-"6" (Spartan-3E only)
.IOSTANDARD ("DEFAULT"), // Specify the I/O standard
.SLEW ("SLOW") // Specify the output slew rate
) IOBUF [31:16] (
.O (sti_data[31:16]), // Buffer output
.IO (extData [31:16]), // Buffer inout port (connect directly to top-level port)
.I (test_pattern), // Buffer input
.T ({16{~extTestMode}}) // 3-state enable input, high=input, low=output
);
IBUF #(
.CAPACITANCE ("DONT_CARE"),
.IBUF_DELAY_VALUE ("0"),
.IBUF_LOW_PWR ("TRUE"),
.IFD_DELAY_VALUE ("AUTO"),
.IOSTANDARD ("DEFAULT")
) IBUF [15:0] (
.O (sti_data[15:0]), // Buffer output
.I (extData [15:0]) // Buffer input port (connect directly to top-level port)
);
IDDR2 #(
.DDR_ALIGNMENT ("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT_Q0 (1'b0), // Sets initial state of the Q0 output to 1'b0 or 1'b1
.INIT_Q1 (1'b0), // Sets initial state of the Q1 output to 1'b0 or 1'b1
.SRTYPE ("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) IDDR2 [31:0] (
.Q0 (sti_data_p), // 1-bit output captured with C0 clock
.Q1 (sti_data_n), // 1-bit output captured with C1 clock
.C0 (sti_clk_p), // 1-bit clock input
.C1 (sti_clk_n), // 1-bit clock input
.CE (1'b1), // 1-bit clock enable input
.D (sti_data), // 1-bit DDR data input
.R (1'b0), // 1-bit reset input
.S (1'b0) // 1-bit set input
);
//--------------------------------------------------------------------------------
// rtl instances
//--------------------------------------------------------------------------------
// Output dataReady to PIC (so it'll enable our SPI CS#)...
dly_signal dataReady_reg (sys_clk, busy, dataReady);
//
// Instantiate serial interface....
//
`ifdef COMM_TYPE_SPI
spi_slave spi_slave (
// system signals
.clk (sys_clk),
.rst (sys_rst),
// input stream
.dataIn (stableInput),
.send (send),
.send_data (sram_rddata),
.send_valid (sram_rdvalid),
// output configuration
.cmd (cmd),
.execute (execute),
.busy (busy),
// SPI signals
.spi_sclk (spi_sclk),
.spi_cs_n (spi_cs_n),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso)
);
`else
eia232 #(
.FREQ (FREQ),
.SCALE (TRXSCALE),
.RATE (RATE)
) eia232 (
.clock (sys_clk),
.reset (sys_rst),
.speed (SPEED),
.rx (rx),
.tx (tx),
.cmd (cmd),
.execute (execute),
.data (output),
.send (send),
.busy (busy)
);
`endif
//
// Instantiate core...
//
core #(
.SDW (32),
.MDW (32)
) core (
// system signsls
.sys_clk (sys_clk),
.sys_rst (sys_rst),
// input stream
.sti_clk (sti_clk_p),
.sti_data_p (sti_data_p),
.sti_data_n (sti_data_n),
//
.extTriggerIn (extTriggerIn),
.opcode (opcode),
.config_data (config_data),
.execute (execute),
.outputBusy (busy),
// outputs...
.sampleReady50 (),
.stableInput (stableInput),
.outputSend (send),
.extTriggerOut (extTriggerOut),
.armLEDnn (armLEDnn),
.triggerLEDnn (triggerLEDnn),
.wrFlags (wrFlags),
.extClock_mode (extClock_mode),
.extTestMode (extTestMode),
// memory interface
.memoryWrData (sram_wrdata),
.memoryRead (read),
.memoryWrite (write),
.memoryLastWrite (lastwrite)
);
//
// Instantiate the memory interface...
//
sram_interface sram_interface (
// system signals
.clk (sys_clk),
.rst (sys_rst),
// configuration/control signals
.wrFlags (wrFlags),
.config_data (config_data[5:2]),
// write interface
.write (write),
.lastwrite (lastwrite),
.wrdata (sram_wrdata),
// read interface
.rd_ready (read),
.rd_valid (),
.rd_keep (sram_rdvalid),
.rd_data (sram_rddata)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS_GTE2.v
// \ \ / \ Timestamp : Tue Jun 1 14:31:01 PDT 2010
// \___\/\___\
//
// Revision:
// 06/01/10 - Initial version.
// 09/29/11 - 627247 -- Changed CLKSWING_CFG from blooean to bits
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps/1 ps
`celldefine
module IBUFDS_GTE2 (
O,
ODIV2,
CEB,
I,
IB
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter CLKCM_CFG = "TRUE";
parameter CLKRCV_TRST = "TRUE";
parameter [1:0] CLKSWING_CFG = 2'b11;
output O;
output ODIV2;
input CEB;
input I;
input IB;
// Output signals
reg O_out=0, ODIV2_out=0;
// Counters and Flags
reg [2:0] ce_count = 1;
reg [2:0] edge_count = 0;
reg allEqual;
// Attribute settings
// Other signals
reg clkcm_cfg_int = 0;
reg clkrcv_trst_int = 0;
reg clkswing_cfg_int = 0;
reg [1:0] CLKSWING_CFG_BINARY;
reg notifier;
initial begin
allEqual = 0;
//-------------------------------------------------
//----- CLKCM_CFG check
//-------------------------------------------------
case (CLKCM_CFG)
"FALSE" : clkcm_cfg_int <= 1'b0;
"TRUE" : clkcm_cfg_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute CLKCM_CFG on IBUFDS_GTE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", CLKCM_CFG);
#1 $finish;
end
endcase // case(CLKCM_CFG)
//-------------------------------------------------
//----- CLKRCV_TRST check
//-------------------------------------------------
case (CLKRCV_TRST)
"FALSE" : clkrcv_trst_int <= 1'b0;
"TRUE" : clkrcv_trst_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute CLKRCV_TRST on IBUFDS_GTE2 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", CLKRCV_TRST);
#1 $finish;
end
endcase // case(CLKRCV_TRST)
end // initial begin
// =====================
// Count the rising edges of the clk
// =====================
always @(posedge I) begin
if(allEqual)
edge_count <= 3'b000;
else
if (CEB == 1'b0)
edge_count <= edge_count + 1;
end
// Generate synchronous reset after DIVIDE number of counts
always @(edge_count)
if (edge_count == ce_count)
allEqual = 1;
else
allEqual = 0;
// =====================
// Generate ODIV2
// =====================
always @(posedge I)
ODIV2_out <= allEqual;
// =====================
// Generate O
// =====================
always @(I)
O_out <= I & ~CEB;
// =====================
// Outputs
// =====================
assign O = O_out;
assign ODIV2 = ODIV2_out;
specify
`ifdef XIL_TIMING
$period (posedge I, 0:0:0, notifier);
$period (posedge IB, 0:0:0, notifier);
( I => O) = (100:100:100, 100:100:100);
( I => ODIV2) = (100:100:100, 100:100:100);
( IB => O) = (100:100:100, 100:100:100);
( IB => ODIV2) = (100:100:100, 100:100:100);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22OI_2_V
`define SKY130_FD_SC_HD__A22OI_2_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22oi_2 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22OI_2_V
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_triangle.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU triangle channel.
***************************************************************************************************/
module apu_triangle
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire en_in, // enable (via $4015)
input wire cpu_cycle_pulse_in, // 1 clk pulse on every cpu cycle
input wire lc_pulse_in, // 1 clk pulse for every length counter decrement
input wire eg_pulse_in, // 1 clk pulse for every env gen update
input wire [1:0] a_in, // control register addr (i.e. $400C - $400F)
input wire [7:0] d_in, // control register write value
input wire wr_in, // enable control register write
output wire [3:0] triangle_out, // triangle channel output
output wire active_out // triangle channel active (length counter > 0)
);
//
// Timer
//
reg [10:0] q_timer_period;
wire [10:0] d_timer_period;
wire timer_pulse;
always @(posedge clk_in)
begin
if (rst_in)
q_timer_period <= 11'h000;
else
q_timer_period <= d_timer_period;
end
apu_div #(.PERIOD_BITS(11)) timer(
.clk_in(clk_in),
.rst_in(rst_in),
.pulse_in(cpu_cycle_pulse_in),
.reload_in(1'b0),
.period_in(q_timer_period),
.pulse_out(timer_pulse)
);
assign d_timer_period = (wr_in && (a_in == 2'b10)) ? { q_timer_period[10:8], d_in[7:0] } :
(wr_in && (a_in == 2'b11)) ? { d_in[2:0], q_timer_period[7:0] } :
q_timer_period;
//
// Linear Counter
//
reg q_linear_counter_halt;
wire d_linear_counter_halt;
reg [7:0] q_linear_counter_cntl;
wire [7:0] d_linear_counter_cntl;
reg [6:0] q_linear_counter_val;
wire [6:0] d_linear_counter_val;
wire linear_counter_en;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_linear_counter_halt <= 1'b0;
q_linear_counter_cntl <= 8'h00;
q_linear_counter_val <= 7'h00;
end
else
begin
q_linear_counter_halt <= d_linear_counter_halt;
q_linear_counter_cntl <= d_linear_counter_cntl;
q_linear_counter_val <= d_linear_counter_val;
end
end
assign d_linear_counter_cntl = (wr_in && (a_in == 2'b00)) ? d_in : q_linear_counter_cntl;
assign d_linear_counter_val =
(eg_pulse_in && q_linear_counter_halt) ? q_linear_counter_cntl[6:0] :
(eg_pulse_in && (q_linear_counter_val != 7'h00)) ? q_linear_counter_val - 7'h01 :
q_linear_counter_val;
assign d_linear_counter_halt =
(wr_in && (a_in == 2'b11)) ? 1'b1 :
(eg_pulse_in && !q_linear_counter_cntl[7]) ? 1'b0 :
q_linear_counter_halt;
assign linear_counter_en = |q_linear_counter_val;
//
// Length Counter
//
reg q_length_counter_halt;
wire d_length_counter_halt;
wire length_counter_wr;
wire length_counter_en;
always @(posedge clk_in)
begin
if (rst_in)
q_length_counter_halt <= 1'b0;
else
q_length_counter_halt <= d_length_counter_halt;
end
apu_length_counter length_counter(
.clk_in(clk_in),
.rst_in(rst_in),
.en_in(en_in),
.halt_in(q_length_counter_halt),
.length_pulse_in(lc_pulse_in),
.length_in(d_in[7:3]),
.length_wr_in(length_counter_wr),
.en_out(length_counter_en)
);
assign d_length_counter_halt = (wr_in && (a_in == 2'b00)) ? d_in[7] : q_length_counter_halt;
assign length_counter_wr = wr_in && (a_in == 2'b11);
//
// Sequencer
//
reg [4:0] q_seq;
wire [4:0] d_seq;
wire [3:0] seq_out;
always @(posedge clk_in)
begin
if (rst_in)
q_seq <= 5'h0;
else
q_seq <= d_seq;
end
assign d_seq = (active_out && timer_pulse) ? q_seq + 5'h01 : q_seq;
assign seq_out = (q_seq[4]) ? q_seq[3:0] : ~q_seq[3:0];
assign active_out = linear_counter_en && length_counter_en;
assign triangle_out = seq_out;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long tree[4 * 1000005]; void update(int v, int l, int r, int ind) { if (l > r || l > ind || ind > r) return; if (l == r) { tree[v] = 1; return; } int mid = (l + r) / 2; update(2 * v, l, mid, ind); update(2 * v + 1, mid + 1, r, ind); tree[v] = tree[2 * v] + tree[2 * v + 1]; } long long query(int v, int l, int r, int lt, int rt) { if (l > r || l > rt || lt > r || lt > rt) return 0; if (lt <= l && r <= rt) return tree[v]; int mid = (l + r) / 2; return query(2 * v, l, mid, lt, rt) + query(2 * v + 1, mid + 1, r, lt, rt); } int n; int a; int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); long long inv = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a; inv += query(1, 1, n, a + 1, n); update(1, 1, n, a); } if (inv % 2 == n % 2) cout << Petr n ; else cout << Um_nik n ; return 0; } |
#include <bits/stdc++.h> using namespace std; using lli = long long int; lli mod = 1000000007.0; int main(void) { long long t; cin >> t; lli x; lli n; while (t--) { cin >> n; x = 1; for (lli i = 2 * n; i >= 3; i--) { x *= i; x = x % mod; } cout << x << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211OI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A211OI_FUNCTIONAL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a211oi (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211OI_FUNCTIONAL_V |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_uarttx(
input clock,
input reset,
input io_en,
output io_in_ready,
input io_in_valid,
input [7:0] io_in_bits,
output io_out,
input [15:0] io_div,
input io_nstop
);
reg [15:0] prescaler;
reg [31:0] GEN_6;
wire pulse;
reg [3:0] counter;
reg [31:0] GEN_7;
reg [8:0] shifter;
reg [31:0] GEN_8;
reg out;
reg [31:0] GEN_9;
wire busy;
wire T_32;
wire T_33;
wire T_34;
wire T_36;
wire [8:0] T_38;
wire T_40;
wire [3:0] T_46;
wire [3:0] T_48;
wire [3:0] T_50;
wire [3:0] T_51;
wire [8:0] GEN_0;
wire [3:0] GEN_1;
wire [16:0] T_53;
wire [15:0] T_54;
wire [15:0] T_55;
wire [15:0] GEN_2;
wire T_56;
wire [4:0] T_58;
wire [3:0] T_59;
wire [7:0] T_61;
wire [8:0] T_62;
wire T_63;
wire [3:0] GEN_3;
wire [8:0] GEN_4;
wire GEN_5;
assign io_in_ready = T_33;
assign io_out = out;
assign pulse = prescaler == 16'h0;
assign busy = counter != 4'h0;
assign T_32 = busy == 1'h0;
assign T_33 = io_en & T_32;
assign T_34 = io_in_ready & io_in_valid;
assign T_36 = reset == 1'h0;
assign T_38 = {io_in_bits,1'h0};
assign T_40 = io_nstop == 1'h0;
assign T_46 = T_40 ? 4'ha : 4'h0;
assign T_48 = io_nstop ? 4'hb : 4'h0;
assign T_50 = T_46 | T_48;
assign T_51 = T_50;
assign GEN_0 = T_34 ? T_38 : shifter;
assign GEN_1 = T_34 ? T_51 : counter;
assign T_53 = prescaler - 16'h1;
assign T_54 = T_53[15:0];
assign T_55 = pulse ? io_div : T_54;
assign GEN_2 = busy ? T_55 : prescaler;
assign T_56 = pulse & busy;
assign T_58 = counter - 4'h1;
assign T_59 = T_58[3:0];
assign T_61 = shifter[8:1];
assign T_62 = {1'h1,T_61};
assign T_63 = shifter[0];
assign GEN_3 = T_56 ? T_59 : GEN_1;
assign GEN_4 = T_56 ? T_62 : GEN_0;
assign GEN_5 = T_56 ? T_63 : out;
always @(posedge clock or posedge reset)
if (reset) begin
prescaler <= 16'h0;
end else begin
if (busy) begin
if (pulse) begin
prescaler <= io_div;
end else begin
prescaler <= T_54;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
counter <= 4'h0;
end else begin
if (T_56) begin
counter <= T_59;
end else begin
if (T_34) begin
counter <= T_51;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
shifter <= 9'b0;
end
else begin
if (T_56) begin
shifter <= T_62;
end else begin
if (T_34) begin
shifter <= T_38;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
out <= 1'h1;
end else begin
if (T_56) begin
out <= T_63;
end
end
//`ifndef SYNTHESIS
//`ifdef PRINTF_COND
// if (`PRINTF_COND) begin
//`endif
// if (T_34 & T_36) begin
// $fwrite(32'h80000002,"%c",io_in_bits);
// end
//`ifdef PRINTF_COND
// end
//`endif
//`endif
//synopsys translate_off
always @(posedge clock or posedge reset) begin
if (T_34 & T_36) begin
$fwrite(32'h80000002,"%c",io_in_bits);
end
end
//synopsys translate_on
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2006 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [63:0] crc;
wire [65:0] outData; // From fifo of fifo.v
wire [15:0] inData = crc[15:0];
wire [1:0] inWordPtr = crc[17:16];
wire wrEn = crc[20];
wire [1:0] wrPtr = crc[33:32];
wire [1:0] rdPtr = crc[34:33];
fifo fifo (
// Outputs
.outData (outData[65:0]),
// Inputs
.clk (clk),
.inWordPtr (inWordPtr[1:0]),
.inData (inData[15:0]),
.rdPtr (rdPtr),
.wrPtr (wrPtr),
.wrEn (wrEn));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%b q=%x\n", $time, cyc, crc, outData);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==90) begin
if (outData[63:0] != 64'hd9bcbc276f0984ea) $stop;
end
else if (cyc==91) begin
if (outData[63:0] != 64'hef77cd9b13a866f0) $stop;
end
else if (cyc==92) begin
if (outData[63:0] != 64'h2750cd9b13a866f0) $stop;
end
else if (cyc==93) begin
if (outData[63:0] != 64'h4ea0bc276f0984ea) $stop;
end
else if (cyc==94) begin
if (outData[63:0] != 64'h9d41bc276f0984ea) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module fifo (/*AUTOARG*/
// Outputs
outData,
// Inputs
clk, inWordPtr, inData, wrPtr, rdPtr, wrEn
);
parameter fifoDepthLog2 = 1;
parameter fifoDepth = 1<<fifoDepthLog2;
`define PTRBITS (fifoDepthLog2+1)
`define PTRBITSM1 fifoDepthLog2
`define PTRBITSM2 (fifoDepthLog2-1)
input clk;
input [1:0] inWordPtr;
input [15:0] inData;
input [`PTRBITSM1:0] wrPtr;
input [`PTRBITSM1:0] rdPtr;
output [65:0] outData;
input wrEn;
reg [65:0] outData;
// verilator lint_off VARHIDDEN
// verilator lint_off LITENDIAN
reg [65:0] fifo[0:fifoDepth-1];
// verilator lint_on LITENDIAN
// verilator lint_on VARHIDDEN
//reg [65:0] temp;
always @(posedge clk) begin
//$write ("we=%x PT=%x ID=%x D=%x\n", wrEn, wrPtr[`PTRBITSM2:0], {1'b0,~inWordPtr,4'b0}, inData[15:0]);
if (wrEn) begin
fifo[ wrPtr[`PTRBITSM2:0] ][{1'b0,~inWordPtr,4'b0}+:16] <= inData[15:0];
// Equivelent to:
//temp = fifo[ wrPtr[`PTRBITSM2:0] ];
//temp [{1'b0,~inWordPtr,4'b0}+:16] = inData[15:0];
//fifo[ wrPtr[`PTRBITSM2:0] ] <= temp;
end
outData <= fifo[rdPtr[`PTRBITSM2:0]];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const int mod = 1e9 + 7; const double eps = 1e-6; const int N = 1 << 17; char S[N], T[N]; int AS[N], AT[N], BS[N], BT[N]; int main() { cin >> (S + 1) >> (T + 1); int n = strlen(S + 1), m = strlen(T + 1); for (int i = 1; i <= n; i++) { AS[i] = S[i] == A ? AS[i - 1] + 1 : 0; BS[i] = BS[i - 1] + (S[i] == B || S[i] == C ); } for (int i = 1; i <= m; i++) { AT[i] = T[i] == A ? AT[i - 1] + 1 : 0; BT[i] = BT[i - 1] + (T[i] == B || T[i] == C ); } int q; cin >> q; while (q--) { static int a, b, c, d; cin >> a >> b >> c >> d; int ss = BS[b] - BS[a - 1]; int tt = BT[d] - BT[c - 1]; if (ss > tt || (ss & 1) ^ (tt & 1)) cout << 0; else { int x = min(b - a + 1, AS[b]), y = min(d - c + 1, AT[d]); if (x < y) cout << 0; else if (x > y && (x - y) % 3 && ss + 2 > tt) cout << 0; else if (x == y && x == b - a + 1 && y != d - c + 1) cout << 0; else cout << 1; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S4S_BLACKBOX_V
`define SKY130_FD_SC_HS__DLYMETAL6S4S_BLACKBOX_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlymetal6s4s (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S4S_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, k, m; int a[100000]; int base = int(1e9 + 7); int lucky[2000]; long long co[2000]; long long f[2000][2000]; long long unlucky; long long frac[100001]; long long c[100001]; int size = 1100; int r1, r2; int getBit(int, int); void create(); int find(int); long long inpow(long long, long long); void calCombination(); void dp(); int main() { cin >> n >> k; create(); for (int i = 0; i < n; i++) { fscanf(stdin, %d , &a[i]); int pos = find(a[i]); if (pos != -1) { co[pos]++; } else unlucky++; } calCombination(); dp(); long long res = 0; f[m - 1][0] = 1; for (int j = 0; j <= k; j++) { res = (res + f[m - 1][j] * c[k - j]) % base; } cout << res << endl; return 0; } int getBit(int x, int i) { return ((x & (1 << i)) != 0); } void create() { m = 0; for (int ndig = 1; ndig <= 9; ndig++) for (int i = 0; i < (1 << ndig); i++) { int cur = 0; for (int j = ndig - 1; j >= 0; j--) if (getBit(i, j) == 0) cur = cur * 10 + 4; else cur = cur * 10 + 7; lucky[m++] = cur; } } int find(int x) { int lo, hi; lo = 0; hi = m - 1; while (lo <= hi) { int mid = (lo + hi) / 2; if (x == lucky[mid]) return mid; if (x < lucky[mid]) hi = mid - 1; else lo = mid + 1; } return -1; } long long inpow(long long x, long long p) { if (p == 1) return x % base; if (p % 2 == 0) { long long t = inpow(x, p / 2); return (t * t) % base; } else return (x * inpow(x, p - 1)) % base; } void calCombination() { frac[0] = 1; for (int i = 1; i <= unlucky; i++) frac[i] = (frac[i - 1] * i) % base; c[0] = 1; c[1] = unlucky; for (long long i = 2; i <= unlucky; i++) { c[i] = frac[unlucky] * inpow((frac[i] * frac[unlucky - i]) % base, base - 2); c[i] = c[i] % base; } } void dp() { for (int i = 0; i < m; i++) f[i][0] = 1; f[0][1] = co[0]; for (int i = 1; i < m; i++) for (int j = 1; j <= (i + 1); j++) f[i][j] = (f[i - 1][j - 1] * co[i] + f[i - 1][j]) % base; } |
#include <bits/stdc++.h> using namespace std; int n, m, a[111], ans = 1e9; set<int> s[111]; int main() { ios_base ::sync_with_stdio(false); cin >> n >> m; for (int i = 1; i <= n; ++i) { cin >> a[i]; } for (int i = 0, x, y; i < m; ++i) { cin >> x >> y; s[x].insert(y); s[y].insert(x); } for (int i = 1; i < n - 1; ++i) { for (int j = i + 1; j < n; ++j) { if (s[i].count(j)) { for (int k = j + 1; k <= n; ++k) { if (s[i].count(k) && s[j].count(k)) { ans = min(a[i] + a[j] + a[k], ans); } } } } } if (ans == 1e9) { cout << -1; } else { cout << ans; } } |
#include <bits/stdc++.h> using namespace std; int n; vector<long long> S; vector<int> N, L, R; vector<bool> E; pair<long long, pair<int, int>> merge(int l, int r, int mid, pair<long long, pair<int, int>> L, pair<long long, pair<int, int>> R) { int ll = L.second.first, lr = L.second.second; int rl = R.second.first, rr = R.second.second; long long ls = L.first, rs = R.first; long long sum = ls + rs; int lw = ll, rw = rr; int lLength = mid - l + 1, rLength = r - (mid + 1) + 1; if (lr && rl && N[mid + 1] >= N[mid]) { if (ll == lLength) lw += rl; if (rr == rLength) rw += lr; if (ll != lLength && rl != rLength) sum += (long long)(lr + rl) * (lr + rl - 1) / 2; } else { if (ll != lLength) sum += (long long)(lr) * (lr - 1) / 2; if (rr != rLength) sum += (long long)(rl) * (rl - 1) / 2; } return {sum, {lw, rw}}; } pair<long long, pair<int, int>> getVal(int lq, int rq, int l = 0, int r = n - 1, int index = 0) { if (l == r) return {0, {1, 1}}; if (lq == l && rq == r && E[index]) return {S[index], {L[index], R[index]}}; int mid = (l + r) >> 1; if (rq <= mid) { return getVal(lq, rq, l, mid, 2 * index + 1); } else if (lq > mid) { return getVal(lq, rq, mid + 1, r, 2 * index + 2); } auto lv = getVal(lq, mid, l, mid, 2 * index + 1); auto rv = getVal(mid + 1, rq, mid + 1, r, 2 * index + 2); auto ret = merge(lq, rq, mid, lv, rv); if (l == lq && r == rq) { E[index] = true; S[index] = ret.first, L[index] = ret.second.first, R[index] = ret.second.second; } return ret; } void update(int lq, int rq, int l = 0, int r = n - 1, int index = 0) { if (l == r) return; E[index] = false; int mid = (l + r) >> 1; if (rq <= mid) { return update(lq, rq, l, mid, 2 * index + 1); } else if (lq > mid) { return update(lq, rq, mid + 1, r, 2 * index + 2); } update(lq, mid, l, mid, 2 * index + 1); update(mid + 1, rq, mid + 1, r, 2 * index + 2); return; } int main() { ios::sync_with_stdio(0); cin.tie(0); int q; cin >> n >> q; N = vector<int>(n); S = vector<long long>(4 * n + 1); L = R = vector<int>(4 * n + 1); E = vector<bool>(4 * n + 1, false); for (auto &it : N) cin >> it; int cmd, x, y; for (int qq = 0; qq < q; qq++) { cin >> cmd >> x >> y; if (cmd == 1) { N[x - 1] = y; update(x - 1, x - 1); } else { x--, y--; auto res = getVal(x, y); auto sum = res.first; int l = res.second.first, r = res.second.second; if (l == (y - x + 1)) sum += (long long)(l) * (l - 1) / 2; else sum += ((long long)(l) * (l - 1) + (long long)(r) * (r - 1)) / 2; sum += (y - x + 1); cout << sum << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n, k, a[N]; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + 1 + n); int p = n / 2 + 1, t = n / 2 + 1; for (int i = n / 2 + 2; i <= n; i++) if (1ll * (a[i] - a[i - 1]) * (i - t) > k) break; else { k -= 1ll * (a[i] - a[i - 1]) * (i - t); p = i; } printf( %d n , a[p] + k / (p - t + 1)); } |
#include <bits/stdc++.h> #pragma GCC target( avx2 ) #pragma GCC optimization( O3 ) #pragma GCC optimization( unroll-loops ) using namespace std; template <class T> using vec = std::vector<T>; bool __hack = std::ios::sync_with_stdio(false); auto __hack1 = cin.tie(nullptr); struct Input { Input(istream &in) : in(&in) {} template <class T> T next() const { T x; *in >> x; return x; } int ni() const { return next<int>(); } istream *in; }; Input in(cin); class Output { private: ostream *out; template <typename T> void printSingle(const T &value) { *out << value; } public: Output(ostream &out) : out(&out) {} inline void print() {} template <typename T, typename... Ts> inline void print(const T &f, const Ts &...args) { printSingle(f); if (sizeof...(args) != 0) { *out << ; print(args...); } } template <typename... Ts> inline void println(const Ts &...args) { print(args...); *out << n ; } template <typename... Ts> inline void operator()(const Ts &...args) { println(args...); } template <typename T> ostream &operator<<(const T &x) { *out << x; return *out; } }; Output out(cout); namespace template_util { constexpr int bytecount(uint64_t x) { return x ? 1 + bytecount(x >> 8) : 0; } template <int N> struct bytetype {}; template <uint64_t N> struct minimal_uint : bytetype<bytecount(N)> {}; } // namespace template_util void solveOne() { auto n = in.ni(); auto m = in.ni(); vec<pair<int, int>> edges(m); for (int i = 0; i < (m); ++i) { auto x = in.ni() - 1; auto y = in.ni() - 1; if (x > y) swap(x, y); edges[i] = {x, y}; } vec<int> used(3 * n, 0); vec<int> takenEdges; for (int i = 0; i < (m); ++i) { if (!used[edges[i].first] && !used[edges[i].second]) { takenEdges.push_back(i); used[edges[i].first] = true; used[edges[i].second] = true; } if (takenEdges.size() == n) { out( Matching ); for (const auto &e : takenEdges) { out << e + 1 << ; } out(); return; } } out( IndSet ); int cnt = 0; for (int i = 0; i < (3 * n); ++i) { if (!used[i]) { out << i + 1 << ; ++cnt; } if (cnt == n) break; } out(); } void solve(istream &inStream, ostream &outStream) { in = Input(inStream); out = Output(outStream); auto tests = in.ni(); while (tests--) { solveOne(); } } int main() { solve(cin, cout); return 0; } |
#include <bits/stdc++.h> using namespace std; int head[100005]; struct edge { int vet, next; } E[200005]; int i, j, k, n, m, s, t, tot, L; int top[100005]; int fa[100005]; int dep[100005]; int a[100005]; int dist[3005][3005]; double ans; int X, Y, all; int cyc[100005]; int getf(int x) { if (x != fa[x]) fa[x] = getf(fa[x]); return fa[x]; } void add(int u, int v) { E[++tot] = (edge){v, head[u]}; head[u] = tot; } void getroad(int u, int dad) { if (u == Y) { L = cyc[u] = 1; return; } for (int e = head[u]; e != -1; e = E[e].next) if (e != dad) { getroad(E[e].vet, e ^ 1); if (cyc[E[e].vet] > 0) { cyc[u] = cyc[E[e].vet] + 1; L = max(L, cyc[u]); } } } void dfs(int u, const int &anc, int dad, int deep) { dep[u] = deep; top[u] = anc; for (int e = head[u]; e != -1; e = E[e].next) if (e != dad && cyc[E[e].vet] == 0) dfs(E[e].vet, anc, e ^ 1, deep + 1); } void getdis(int u, const int &anc, int dad, int D) { dist[anc][u] = D; for (int e = head[u]; e != -1; e = E[e].next) if (e != dad) getdis(E[e].vet, anc, e ^ 1, D + 1); } void DO() { for (int i = 1; i <= n; i++) getdis(i, i, -1, 0); } int main() { tot = -1; memset(head, -1, sizeof(head)); scanf( %d , &n); for (int i = 1; i <= n; i++) fa[i] = i; for (int i = 1; i <= n; i++) { int x, y; scanf( %d%d , &x, &y); x++; y++; if (getf(x) == getf(y)) { X = x; Y = y; continue; } add(x, y); add(y, x); fa[getf(x)] = getf(y); } DO(); getroad(X, -1); for (int i = 1; i <= n; i++) if (cyc[i] > 0) dfs(i, i, -1, 0); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (i != j) { if (top[i] == top[j]) ans += 1.0 / (dist[i][j] + 1); else { int x = dep[i] + dep[j]; int y = abs(cyc[top[i]] - cyc[top[j]]); int z = L - y; ans += 1.0 / (x + y + 1) + 1.0 / (x + z + 1) - 1.0 / (x + L); } } ans += n; printf( %.14f n , ans); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__BUFINV_FUNCTIONAL_PP_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__bufinv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; struct atom { long long f, w, where; void scan() { scanf( %I64d%I64d , &f, &w); } } x[310000]; priority_queue<long long> A, B; int compare(atom k1, atom k2) { return k1.f > k2.f || (k1.f == k2.f && k1.where < k2.where); } int n, pre, ans, where; long long rem; void insert(long long k1) { if (!B.empty()) { long long k2 = B.top(); if (k2 > k1) { A.push(-k2); B.pop(); B.push(k1); rem += k2 - k1; return; } } A.push(-k1); pre++; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) x[i].scan(), x[i].where = i; n++; x[n] = (atom){0, 0, n}; sort(x + 1, x + n + 1, compare); pre = 0, ans = 0, where = 0; long long rem = 0; for (int i = 1; i <= n; i++) if (x[i].where == 1) where = i; ans = where; pre = where; for (int i = 1; i < where; i++) A.push(-(x[i].w - x[i].f + 1)); for (int i = where + 1; i <= n; i++) { rem += x[i - 1].f - x[i].f; if (i - 1 != where) insert(x[i - 1].w - x[i - 1].f + 1); while (!A.empty()) { long long k1 = -A.top(); if (k1 <= rem) { rem -= k1; pre--; A.pop(); } else break; } ans = min(ans, pre); } printf( %d n , ans); return 0; } |
module mac (input clock, input reset, input enable, input clear,
input signed [15:0] x, input signed [15:0] y,
input [7:0] shift, output [15:0] z );
reg signed [30:0] product;
reg signed [39:0] z_int;
reg signed [15:0] z_shift;
reg enable_d1;
always @(posedge clock)
enable_d1 <= #1 enable;
always @(posedge clock)
if(reset | clear)
z_int <= #1 40'd0;
else if(enable_d1)
z_int <= #1 z_int + {{9{product[30]}},product};
always @(posedge clock)
product <= #1 x*y;
always @* // FIXME full case? parallel case?
case(shift)
//8'd0 : z_shift <= z_int[39:24];
//8'd1 : z_shift <= z_int[38:23];
//8'd2 : z_shift <= z_int[37:22];
//8'd3 : z_shift <= z_int[36:21];
//8'd4 : z_shift <= z_int[35:20];
//8'd5 : z_shift <= z_int[34:19];
8'd6 : z_shift <= z_int[33:18];
8'd7 : z_shift <= z_int[32:17];
8'd8 : z_shift <= z_int[31:16];
8'd9 : z_shift <= z_int[30:15];
8'd10 : z_shift <= z_int[29:14];
8'd11 : z_shift <= z_int[28:13];
//8'd12 : z_shift <= z_int[27:12];
//8'd13 : z_shift <= z_int[26:11];
//8'd14 : z_shift <= z_int[25:10];
//8'd15 : z_shift <= z_int[24:9];
//8'd16 : z_shift <= z_int[23:8];
//8'd17 : z_shift <= z_int[22:7];
//8'd18 : z_shift <= z_int[21:6];
//8'd19 : z_shift <= z_int[20:5];
//8'd20 : z_shift <= z_int[19:4];
//8'd21 : z_shift <= z_int[18:3];
//8'd22 : z_shift <= z_int[17:2];
//8'd23 : z_shift <= z_int[16:1];
//8'd24 : z_shift <= z_int[15:0];
default : z_shift <= z_int[15:0];
endcase // case(shift)
// FIXME do we need to saturate?
//assign z = z_shift;
assign z = z_int[15:0];
endmodule // mac
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.2
//
// Date: $Date: 2004/11/08 16:19:22 $
// Tag: $Name: i+H-38+78751 $
// File: $RCSfile: aurora_lane_4byte.ejava,v $
// Rev: $Revision: 1.1.6.2 $
//
// Company: Xilinx
// Contributors: R. K. Awalt, B. L. Woodard, N. Gulstone
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// AURORA_LANE_4BYTE
//
// Author: Nigel Gulstone
// Xilinx - Embedded Networking System Engineering Group
//
// Description: the AURORA_LANE_4BYTE module provides a full duplex 4-byte aurora lane
// connection using a single MGT. The module handles lane initialization,
// symbol generation and decoding and error detection. It also decodes
// some of the channel bonding indicator signals needed by the Global
// logic.
//
// * Supports Virtex 2 Pro
//
`timescale 1 ns / 10 ps
module AURORA_LANE_4BYTE
(
// MGT Interface
RX_DATA,
RX_NOT_IN_TABLE,
RX_DISP_ERR,
RX_CHAR_IS_K,
RX_CHAR_IS_COMMA,
RX_BUF_STATUS,
TX_BUF_ERR,
TX_K_ERR,
RX_CLK_COR_CNT,
RX_REALIGN,
RX_POLARITY,
RX_RESET,
TX_CHAR_IS_K,
TX_DATA,
TX_RESET,
// Comma Detect Phase Align Interface
ENA_COMMA_ALIGN,
// TX_LL Interface
GEN_SCP,
GEN_ECP,
GEN_PAD,
TX_PE_DATA,
TX_PE_DATA_V,
GEN_CC,
// RX_LL Interface
RX_PAD,
RX_PE_DATA,
RX_PE_DATA_V,
RX_SCP,
RX_ECP,
// Global Logic Interface
GEN_A,
GEN_K,
GEN_R,
GEN_V,
LANE_UP,
SOFT_ERROR,
HARD_ERROR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
// System Interface
USER_CLK,
RESET
);
//***********************************Port Declarations*******************************
// MGT Interface
input [31:0] RX_DATA; // 4-byte data bus from the MGT.
input [3:0] RX_NOT_IN_TABLE; // Invalid 10-bit code was recieved.
input [3:0] RX_DISP_ERR; // Disparity error detected on RX interface.
input [3:0] RX_CHAR_IS_K; // Indicates which bytes of RX_DATA are control.
input [3:0] RX_CHAR_IS_COMMA; // Comma received on given byte.
input RX_BUF_STATUS; // Overflow/Underflow of RX buffer detected.
input TX_BUF_ERR; // Overflow/Underflow of TX buffer detected.
input [3:0] TX_K_ERR; // Attempt to send bad control byte detected.
input [2:0] RX_CLK_COR_CNT; // Value used to determine channel bonding status.
input RX_REALIGN; // SERDES was realigned because of a new comma.
output RX_POLARITY; // Controls interpreted polarity of serial data inputs.
output RX_RESET; // Reset RX side of MGT logic.
output [3:0] TX_CHAR_IS_K; // TX_DATA byte is a control character.
output [31:0] TX_DATA; // 4-byte data bus to the MGT.
output TX_RESET; // Reset TX side of MGT logic.
// Comma Detect Phase Align Interface
output ENA_COMMA_ALIGN; // Request comma alignment.
// TX_LL Interface
input [0:1] GEN_SCP; // SCP generation request from TX_LL.
input [0:1] GEN_ECP; // ECP generation request from TX_LL.
input [0:1] GEN_PAD; // PAD generation request from TX_LL.
input [0:31] TX_PE_DATA; // Data from TX_LL to send over lane.
input [0:1] TX_PE_DATA_V; // Indicates TX_PE_DATA is Valid.
input GEN_CC; // CC generation request from TX_LL.
// RX_LL Interface
output [0:1] RX_PAD; // Indicates lane received PAD.
output [0:31] RX_PE_DATA; // RX data from lane to RX_LL.
output [0:1] RX_PE_DATA_V; // RX_PE_DATA is data, not control symbol.
output [0:1] RX_SCP; // Indicates lane received SCP.
output [0:1] RX_ECP; // Indicates lane received ECP.
// Global Logic Interface
input GEN_A; // 'A character' generation request from Global Logic.
input [0:3] GEN_K; // 'K character' generation request from Global Logic.
input [0:3] GEN_R; // 'R character' generation request from Global Logic.
input [0:3] GEN_V; // Verification data generation request.
output LANE_UP; // Lane is ready for bonding and verification.
output [0:1] SOFT_ERROR; // Soft error detected.
output HARD_ERROR; // Hard error detected.
output CHANNEL_BOND_LOAD; // Channel Bongding done code recieved.
output [0:3] GOT_A; // Indicates lane recieved 'A character' bytes.
output GOT_V; // Verification symbols received.
// System Interface
input USER_CLK; // System clock for all non-MGT Aurora Logic.
input RESET; // Reset the lane.
//*********************************Wire Declarations**********************************
wire ena_comma_align_i;
wire gen_sp_i;
wire gen_spa_i;
wire rx_sp_i;
wire rx_spa_i;
wire rx_neg_i;
wire enable_error_detect_i;
wire do_word_align_i;
wire hard_error_reset_i;
//*********************************Main Body of Code**********************************
// Lane Initialization state machine
LANE_INIT_SM_4BYTE lane_init_sm_4byte_i
(
// MGT Interface
.RX_NOT_IN_TABLE(RX_NOT_IN_TABLE),
.RX_DISP_ERR(RX_DISP_ERR),
.RX_CHAR_IS_COMMA(RX_CHAR_IS_COMMA),
.RX_REALIGN(RX_REALIGN),
.RX_RESET(RX_RESET),
.TX_RESET(TX_RESET),
.RX_POLARITY(RX_POLARITY),
// Comma Detect Phase Alignment Interface
.ENA_COMMA_ALIGN(ENA_COMMA_ALIGN),
// Symbol Generator Interface
.GEN_SP(gen_sp_i),
.GEN_SPA(gen_spa_i),
// Symbol Decoder Interface
.RX_SP(rx_sp_i),
.RX_SPA(rx_spa_i),
.RX_NEG(rx_neg_i),
.DO_WORD_ALIGN(do_word_align_i),
// Error Detection Logic Interface
.HARD_ERROR_RESET(hard_error_reset_i),
.ENABLE_ERROR_DETECT(enable_error_detect_i),
// Global Logic Interface
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET)
);
// Channel Bonding Count Decode module
CHBOND_COUNT_DEC_4BYTE chbond_count_dec_4byte_i
(
.RX_CLK_COR_CNT(RX_CLK_COR_CNT),
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.USER_CLK(USER_CLK)
);
// Symbol Generation module
SYM_GEN_4BYTE sym_gen_4byte_i
(
// TX_LL Interface
.GEN_SCP(GEN_SCP),
.GEN_ECP(GEN_ECP),
.GEN_PAD(GEN_PAD),
.TX_PE_DATA(TX_PE_DATA),
.TX_PE_DATA_V(TX_PE_DATA_V),
.GEN_CC(GEN_CC),
// Global Logic Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// Lane Init SM Interface
.GEN_SP(gen_sp_i),
.GEN_SPA(gen_spa_i),
// MGT Interface
.TX_CHAR_IS_K(TX_CHAR_IS_K),
.TX_DATA(TX_DATA),
// System Interface
.USER_CLK(USER_CLK)
);
// Symbol Decode module
SYM_DEC_4BYTE sym_dec_4byte_i
(
// RX_LL Interface
.RX_PAD(RX_PAD),
.RX_PE_DATA(RX_PE_DATA),
.RX_PE_DATA_V(RX_PE_DATA_V),
.RX_SCP(RX_SCP),
.RX_ECP(RX_ECP),
// Lane Init SM Interface
.DO_WORD_ALIGN(do_word_align_i),
.LANE_UP(LANE_UP),
.RX_SP(rx_sp_i),
.RX_SPA(rx_spa_i),
.RX_NEG(rx_neg_i),
// Global Logic Interface
.GOT_A(GOT_A),
.GOT_V(GOT_V),
// MGT Interface
.RX_DATA(RX_DATA),
.RX_CHAR_IS_K(RX_CHAR_IS_K),
.RX_CHAR_IS_COMMA(RX_CHAR_IS_COMMA),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET)
);
// Error Detection module
ERROR_DETECT_4BYTE error_detect_4byte_i
(
// Lane Init SM Interface
.ENABLE_ERROR_DETECT(enable_error_detect_i),
.HARD_ERROR_RESET(hard_error_reset_i),
// Global Logic Interface
.SOFT_ERROR(SOFT_ERROR),
.HARD_ERROR(HARD_ERROR),
// MGT Interface
.RX_DISP_ERR(RX_DISP_ERR),
.TX_K_ERR(TX_K_ERR),
.RX_NOT_IN_TABLE(RX_NOT_IN_TABLE),
.RX_BUF_STATUS(RX_BUF_STATUS),
.TX_BUF_ERR(TX_BUF_ERR),
.RX_REALIGN(RX_REALIGN),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> void printArray(const T* a, int n, ostream& out = cerr); template <class T> void printArray(const vector<T>& arr, ostream& out = cerr); const long long mod = 1e9 + 7; const double PI = acos(-1); int n, i, j, k, t; int m; int a[200002]; int b[200002]; int c[200002]; int pos[200002]; int ac[200002]; int bc[200002]; int cc[200002]; int mab[200002]; int hitung(int st, int pem, int ed) { int total = ac[st]; total += (bc[pem] - bc[st]); total += (cc[ed] - cc[pem]); return total; } int hitung2(int st, int pem, int ed) { int total = ac[st]; total += (bc[pem] - bc[st]); total += (cc[ed] - cc[pem]); return total; } int main() { scanf( %d %d %d , &n, &m, &k); int tot = n + m + k; for (int i = 0; i < n; ++i) { scanf( %d , a + i); pos[a[i]] = 1; } for (int i = 0; i < m; ++i) { scanf( %d , b + i); pos[b[i]] = 2; } for (int i = 0; i < k; ++i) { scanf( %d , c + i); pos[c[i]] = 3; } for (int i = 1; i <= tot; ++i) { ac[i] = ac[i - 1] + (pos[i] == 1); bc[i] = bc[i - 1] + (pos[i] == 2); cc[i] = cc[i - 1] + (pos[i] == 3); } mab[tot] = bc[tot]; for (int i = tot - 1; i >= 0; --i) { mab[i] = max(mab[i + 1], bc[i] + cc[tot] - cc[i]); } int ans = 0; for (int i = 0; i <= tot; ++i) { ans = max(ans, ac[i] + mab[i] - bc[i]); } printf( %d n , tot - ans); return 0; } template <class T> void printArray(const T* a, int n, ostream& out) { for (int i = 0; i < n; ++i) { out << a[i] << ; } out << endl; } template <class T> void printArray(const vector<T>& arr, ostream& out) { for (const T& x : arr) { out << x << ; } out << endl; } |
module ramprog(input [11:0] adr, input we,
inout [31:0] data);
reg [31:0]ram[4095:0];
integer i = 0;
//Op Codes
parameter NOP = 4'b0000;
parameter LOAD = 4'b0001;
parameter STORE = 4'b0010;
parameter BRANCH = 4'b0011;
parameter XOR = 4'b0100;
parameter ADD = 4'b0101;
parameter ROTATE = 4'b0110;
parameter SHIFT = 4'b0111;
parameter HALT = 4'b1000;
parameter COMPLEMENT = 4'b1001;
parameter DISPLAY = 4'b1010;
//Condition Codes
parameter ALWAYS = 4'b0000;
parameter PARITY = 4'b0001;
parameter EVEN = 4'b0010;
parameter CARRY = 4'b0011;
parameter NEGATIVE = 4'b0100;
parameter ZERO = 4'b0101;
parameter NOCARRY = 4'b0110;
parameter POSITIVE = 4'b0111;
//first 8 regs
parameter reg0 = 12'b000000000_000;
parameter reg1 = 12'b000000000_001;
parameter reg2 = 12'b000000000_010;
parameter reg3 = 12'b000000000_011;
parameter reg4 = 12'b000000000_100;
parameter reg5 = 12'b000000000_101;
parameter reg6 = 12'b000000000_110;
parameter reg7 = 12'b000000000_111;
//first 8 data memory locations
parameter mem0 = 12'b000001_000000; //64
parameter mem1 = 12'b000001_000001;
parameter mem2 = 12'b000001_000010;
parameter mem3 = 12'b000001_000011;
parameter mem4 = 12'b000001_000100;
parameter mem5 = 12'b000001_000101;
parameter mem6 = 12'b000001_000110;
parameter mem7 = 12'b000001_000111;
//first 10 instruction memory locations
parameter is0 = 12'b000000_000000;
parameter is1 = 12'b000000_000001;
parameter is2 = 12'b000000_000010;
parameter is3 = 12'b000000_000011;
parameter is4 = 12'b000000_000100;
parameter is5 = 12'b000000_000101;
parameter is6 = 12'b000000_000110;
parameter is7 = 12'b000000_000111;
parameter is8 = 12'b000000_001000;
parameter is9 = 12'b000000_001001;
parameter is10 = 12'b000000_001010;
//source types
parameter REG = 1'b0;
parameter MEM = 1'b0;
parameter IMM = 1'b1;
//for bits 24 adn 25 when not using a branch op
parameter xx = 2'b00;
//for when destinaation address is not being used during a branch op
parameter addressx = 12'b000000_000000;
//common immediates
parameter imm0 = 12'b000000_000000;
parameter imm1 = 12'b000000_000001;
parameter imm1n = 12'b111111_111111;
assign data = (we) ? 'bz : ram[adr];
initial begin
for(i = 0; i< 4096; i = i +1) begin
ram[i] = 'd0;
end
/** Load store test
ram[is0] = {LOAD,MEM,REG,xx,mem0,reg0}; //load number in memory0 to reg 0
ram[is1] = {STORE,REG,MEM,xx,reg0,mem1}; //if it is 0 store answer from reg1 in mem1
**/
/**#4 ones in location mem0 (ram[64]) mem1 (ram[65])
ram[is0] = {LOAD,MEM,REG,xx,mem0,reg0}; //load number in memory0 to reg 0
ram[is1] = {BRANCH,ZERO,is5,addressx}; //if reg0 is 0 then branch to store/end of program
ram[is2] = {SHIFT,IMM,REG,xx,imm1,reg0}; //shift reg0 to the right by 1
ram[is3] = {BRANCH,CARRY,is8,addressx}; //if the shift carried out a 1 then branch to the add
ram[is4] = {BRANCH,ALWAYS,is1,addressx}; //else if it didn't shift again
ram[is5] = {STORE,REG,MEM,xx,reg1,mem1}; //if it is 0 store answer from reg1 in mem1
ram[is6] = {DISPLAY,1'b0,1'b0,xx,addressx,mem1}; //display the contents of MEM1
ram[is7] = {HALT,xx,xx,addressx,addressx}; //Halt
ram[is8] = {ADD,IMM,REG,xx,imm1,reg1}; //add 1 to answer (reg1)
ram[is9] = {BRANCH,ALWAYS,is1,addressx}; //branch/loop back to check if reg0 is 0
ram[mem0] = 'b0000_1111_0001_0001_0000_0000_0000_1111; //setting the memory lcoation to be counted
**/
//Multiplication following the algorithm described here: http://en.wikipedia.org/wiki/Multiplication_algorithm#Peasant_or_binary_multiplication
ram[mem0] = 'b0000_0000_0000_0000_0000_0000_0001_1111; //setting the memory location for the multiplicand
ram[mem1] = 'b0000_0000_0000_0000_0000_0000_0000_1111; //setting the memory location for the multiplier
ram[is0] = {LOAD,MEM,REG,xx,mem0,reg0}; //load the multiplicand from memory0 to reg 0
ram[is1] = {LOAD,MEM,REG,xx,mem1,reg1}; //load the multiplier from memory1 to reg 1
ram[is2] = {ADD,IMM,REG,xx,imm0,reg1}; //add 0 to the multiplier to set the psr for the value in that reg
ram[is3] = {BRANCH,ZERO,is8,addressx}; //if the multiplier is 0 branch to the end
ram[is4] = {ADD,REG,REG,xx,reg0,reg2}; //if it isn't then add the multiplicand to reg2
ram[is5] = {SHIFT,IMM,REG,xx,imm1,reg1}; //shift the multiplier by one to the right
ram[is6] = {SHIFT,IMM,REG,xx,imm1n,reg0}; //and shift the multiplicand by one to the left
ram[is7] = {BRANCH,ALWAYS,is2,addressx}; //Branch to check the multiplier
ram[is8] = {STORE,REG,MEM,xx,reg2,mem2}; //store the result from reg 2 in mem3
ram[is9] = {DISPLAY,1'b0,1'b0,xx,addressx,mem2}; //display the contents of mem2
ram[is10] = {HALT,xx,xx,addressx,addressx}; //Halt
/**
//convert a number to its negative twos compliment version
ram[mem0] = 'b0000_0000_0000_0000_0000_0000_0000_0110;
ram[is0] = {LOAD,MEM,REG,xx,mem0,reg0}; //Load the positive number from mem0
ram[is1] = {COMPLEMENT,xx,xx,reg0,reg0}; //compliment the number
ram[is2] = {ADD,IMM,REG,xx,imm1,reg0}; //add 1 to the number to finish the conversion
ram[is3] = {STORE,REG,MEM,xx,reg0,mem1}; //store it in mem1
ram[is4] = {DISPLAY,1'b0,1'b0,xx,addressx,mem1}; //display the contents of mem1
ram[is5] = {HALT,xx,xx,addressx,addressx}; //Halt
**/
end
always@(adr) begin
if(we) begin
ram[adr] = data;
end
end
endmodule
|
#include<bits/stdc++.h> using namespace std; typedef long double ld; typedef long long int ll; typedef pair<int, int> pi; typedef pair<long long, long long> pll; #define endl n #define ff first #define ss second #define pb push_back #define int long long #define sz(v) (int)v.size() #define inf 2147483647 #define llinf 9223372036854775807 #define all(v) v.begin(),v.end() #define bp(n) __builtin_popcountll(n) #define f(i,l,r) for(long long i=l;i<=r;i++) #define rf(i,r,l) for(long long i=r;i>=l;i--) #define fast ios_base::sync_with_stdio(false),cin.tie(NULL),cout.tie(NULL) template<typename T> ostream& operator<<(ostream &os, const vector<T> &v) { os << { ; string sep; for (const auto &x : v) os << sep << x, sep = , ; return os << } ; } template<typename T, size_t size> ostream& operator<<(ostream &os, const array<T, size> &arr) { os << { ; string sep; for (const auto &x : arr) os << sep << x, sep = , ; return os << } ; } template<typename A, typename B> ostream& operator<<(ostream &os, const pair<A, B> &p) { return os << ( << p.first << , << p.second << ) ; } void dbg_out() { cout << endl; } template<typename Head, typename... Tail> void dbg_out(Head H, Tail... T) { cout << << H; dbg_out(T...); } const int N = 3e5 + 5, mod = 1e9 + 7, bit = 61; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); int getRand(int l, int r) { uniform_int_distribution<int> uid(l, r); return uid(rng); } signed main() { fast; #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif int t = 1; cin >> t; f(tc, 1, t) { int n, m, x; cin >> n >> m >> x; int r = (x % n); if (r == 0) { r = n; } int c = ((x - r) / (n)) + 1; cout << (r - 1) * m + c << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; bool chk(string s) { int l = s.size(); for (int i = 0, j = l - 1; i <= j; i++, j--) { if (s[i] != s[j]) return false; } return true; } int main() { int t; cin >> t; while (t--) { string s; cin >> s; string ans; int mx = 0; string res; for (int i = 0; i < s.size(); i++) { ans += s[i]; if (chk(ans)) { int l = ans.size(); if (l > mx) { mx = ans.size(); res = ans; } } } ans = ; for (int i = s.size() - 1; i >= 0; i--) { ans += s[i]; if (chk(ans)) { int l = ans.size(); if (l > mx) { mx = ans.size(); res = ans; } } } int p1 = 0; int p2 = 0; for (int i = 0, j = s.size() - 1; i < j; i++, j--) { if (s[i] != s[j]) { p1 = i - 1; p2 = j + 1; break; } } ans = ; string rev = ; for (int i = 0; i <= p1; i++) ans += s[i]; for (int i = p2; i < s.size(); i++) rev += s[i]; string ss = ; for (int i = p1 + 1; i < p2; i++) { ss += s[i]; string tmp = ans + ss + rev; int l = tmp.size(); if (l <= mx) continue; if (chk(tmp)) { if (l > mx) { mx = l; res = tmp; } } } ss = ; for (int j = p2 - 1; j > p1; j--) { ss = s[j] + ss; string tmp = ans + ss + rev; int l = tmp.size(); if (chk(tmp)) { if (l > mx) { mx = l; res = tmp; } } } cout << res << endl; } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 31 03:26:46 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_buffer_1_0/system_vga_buffer_1_0_stub.v
// Design : system_vga_buffer_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_buffer,Vivado 2016.4" *)
module system_vga_buffer_1_0(clk_w, clk_r, wen, x_addr_w, y_addr_w, x_addr_r,
y_addr_r, data_w, data_r)
/* synthesis syn_black_box black_box_pad_pin="clk_w,clk_r,wen,x_addr_w[9:0],y_addr_w[9:0],x_addr_r[9:0],y_addr_r[9:0],data_w[23:0],data_r[23:0]" */;
input clk_w;
input clk_r;
input wen;
input [9:0]x_addr_w;
input [9:0]y_addr_w;
input [9:0]x_addr_r;
input [9:0]y_addr_r;
input [23:0]data_w;
output [23:0]data_r;
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:251700000 ) using namespace std; const int INF = 2e9; const double eps = 1e-6; const int M = 1e5 + 5; int n; string s[M]; bool us[M]; char SS[M]; string get_s() { scanf( %s , &SS); return string(SS); } int main() { scanf( %d , &n); vector<int> c(27); vector<int> dd(27, -1); for (int q = 0; q < n; ++q) { s[q] = get_s(); for (int i = 0; i < 27; ++i) c[i] = 0; for (int j = 0; j < s[q].size(); ++j) ++c[s[q][j] - a ]; for (int i = 0; i < 27; ++i) if (c[i] > 1) cout << NO , exit(0); for (int i = 0; i < 27; ++i) { if (dd[i] == -1 || !c[i] || us[dd[i]]) continue; int l, r, l1, r1; for (int j = 0; j < s[q].size(); ++j) if (s[q][j] - a == i) l = j; for (int j = 0; j < s[dd[i]].size(); ++j) if (s[dd[i]][j] - a == i) r = j; l1 = l, r1 = r; while (l >= 0 && r >= 0) { if (s[q][l] != s[dd[i]][r]) cout << NO , exit(0); --l, --r; } if (r >= 0) s[q] = s[dd[i]].substr(0, r + 1) + s[q], l1 += r + 1; l = l1, r = r1; while (l < s[q].size() && r < s[dd[i]].size()) { if (s[q][l] != s[dd[i]][r]) cout << NO , exit(0); ++l, ++r; } while (r < s[dd[i]].size()) { s[q] += s[dd[i]][r]; ++r; } us[dd[i]] = 1; } for (int i = 0; i < 27; ++i) c[i] = 0; for (int j = 0; j < s[q].size(); ++j) ++c[s[q][j] - a ], dd[s[q][j] - a ] = q; for (int i = 0; i < 27; ++i) if (c[i] > 1) cout << NO , exit(0); } vector<string> ab; for (int i = 0; i < n; ++i) if (!us[i]) ab.push_back(s[i]); sort((ab).begin(), (ab).end()); for (int i = 0; i < ab.size(); ++i) cout << ab[i]; } |
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
///** Reset logic for HIP +
//*/
module pcie_hip_s4gx_gen2_x4_128_rs_hip (
// inputs:
dlup_exit,
hotrst_exit,
l2_exit,
ltssm,
npor,
pld_clk,
test_sim,
// outputs:
app_rstn,
crst,
srst
)
;
output app_rstn;
output crst;
output srst;
input dlup_exit;
input hotrst_exit;
input l2_exit;
input [ 4: 0] ltssm;
input npor;
input pld_clk;
input test_sim;
reg any_rstn_r /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg any_rstn_rr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R102 ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg app_rstn;
reg app_rstn0;
reg crst;
reg crst0;
reg [ 4: 0] dl_ltssm_r;
reg dlup_exit_r;
reg exits_r;
reg hotrst_exit_r;
reg l2_exit_r;
wire otb0;
wire otb1;
reg [ 10: 0] rsnt_cntn;
reg srst;
reg srst0;
assign otb0 = 1'b0;
assign otb1 = 1'b1;
//pipe line exit conditions
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
dlup_exit_r <= otb1;
hotrst_exit_r <= otb1;
l2_exit_r <= otb1;
exits_r <= otb0;
end
else
begin
dlup_exit_r <= dlup_exit;
hotrst_exit_r <= hotrst_exit;
l2_exit_r <= l2_exit;
exits_r <= (l2_exit_r == 1'b0) | (hotrst_exit_r == 1'b0) | (dlup_exit_r == 1'b0) | (dl_ltssm_r == 5'h10);
end
end
//LTSSM pipeline
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
dl_ltssm_r <= 0;
else
dl_ltssm_r <= ltssm;
end
//reset Synchronizer
always @(posedge pld_clk or negedge npor)
begin
if (npor == 0)
begin
any_rstn_r <= 0;
any_rstn_rr <= 0;
end
else
begin
any_rstn_r <= 1;
any_rstn_rr <= any_rstn_r;
end
end
//reset counter
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
rsnt_cntn <= 0;
else if (exits_r == 1'b1)
rsnt_cntn <= 11'h3f0;
else if (rsnt_cntn != 11'd1024)
rsnt_cntn <= rsnt_cntn + 1;
end
//sync and config reset
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
app_rstn0 <= 0;
srst0 <= 1;
crst0 <= 1;
end
else if (exits_r == 1'b1)
begin
srst0 <= 1;
crst0 <= 1;
app_rstn0 <= 0;
end
else // synthesis translate_off
if ((test_sim == 1'b1) & (rsnt_cntn >= 11'd32))
begin
srst0 <= 0;
crst0 <= 0;
app_rstn0 <= 1;
end
else // synthesis translate_on
if (rsnt_cntn == 11'd1024)
begin
srst0 <= 0;
crst0 <= 0;
app_rstn0 <= 1;
end
end
//sync and config reset pipeline
always @(posedge pld_clk or negedge any_rstn_rr)
begin
if (any_rstn_rr == 0)
begin
app_rstn <= 0;
srst <= 1;
crst <= 1;
end
else
begin
app_rstn <= app_rstn0;
srst <= srst0;
crst <= crst0;
end
end
endmodule
|
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH UST
// Engineer: Wojciech Gredel, Hubert Górowski
//
// Create Date:
// Design Name:
// Module Name: Board
// Project Name: DOS_Mario
// Target Devices: Basys3
// Tool versions: Vivado 2016.1
// Description:
// This module displays board: blocks, special blocks, coins and everything saved in stage RAM.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - Module created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Board (
input wire [9:0] hcount_in,
input wire hsync_in,
input wire [9:0] vcount_in,
input wire vsync_in,
input wire pclk,
input wire [23:0] rgb_in,
input wire blnk_in,
input wire clk,
input wire rst,
input wire [7:0] plane_xpos,
input wire [5:0] plane_xpos_ofs,
input wire [5:0] block,
output reg [7:0] block_xpos,
output reg [3:0] block_ypos,
output reg [9:0] hcount_out,
output reg hsync_out,
output reg [9:0] vcount_out,
output reg vsync_out,
output reg [23:0] rgb_out,
output reg blnk_out
);
//Definition of blocks, makes it easier to use
localparam A = 1 ;
localparam B = 0 ;
localparam C = 2 ;
localparam D = 3 ;
localparam E = 4 ;
localparam F = 5 ;
localparam G = 6 ;
localparam H = 7 ;
localparam I = 8 ;
localparam J = 9 ;
localparam K = 10;
localparam L = 11;
localparam M = 12;
localparam N = 13;
localparam O = 14;
localparam P = 15;
localparam Q = 16;
localparam R = 17;
localparam S = 18;
localparam T = 19;
localparam U = 20;
localparam V = 21;
localparam W = 22;
localparam X = 23;
localparam Y = 24;
localparam Z = 25;
localparam AY = 26;
localparam IY = 27;
localparam GY = 28;
localparam KY = 29;
localparam PY = 30;
localparam TY = 31;
localparam UY = 32;
localparam WY = 33;
localparam DY = 34;
reg [23:0] rgb_nxt;
reg [7:0] block_xpos_nxt;
reg [3:0] block_ypos_nxt;
reg [11:0] ram_addr_nxt;
always @* begin
block_ypos_nxt = ((479 - vcount_in)>>2)/10;
block_xpos_nxt = plane_xpos + ((hcount_in + plane_xpos_ofs)>>2)/10;
end
always @* begin
case(block)//block colors
A : rgb_nxt = 24'h0_20_20 ;
B : rgb_nxt = rgb_in;
C : rgb_nxt = 24'h6A_3D_1E ;
D : rgb_nxt = 24'hBB_77_00 ;
E : rgb_nxt = 24'h00_00_00 ;
F : rgb_nxt = 24'h00_00_00 ;
G : rgb_nxt = 24'h10_50_10 ;
H : rgb_nxt = 24'h00_00_00 ;
I : rgb_nxt = 24'h00_00_00 ;
J : rgb_nxt = 24'h70_10_10 ;
K : rgb_nxt = 24'h00_00_00 ;
L : rgb_nxt = 24'h6A_3D_1E ;
M : rgb_nxt = 24'h6A_3D_1E ;
N : rgb_nxt = 24'h6A_3D_1E ;
O : rgb_nxt = 24'h50_30_20 ;
P : rgb_nxt = 24'h6A_3D_1E ;
Q : rgb_nxt = 24'h10_50_10 ;
R : rgb_nxt = rgb_in ;
S : rgb_nxt = 24'h6A_3D_1E ;
T : rgb_nxt = rgb_in ;
U : rgb_nxt = 24'h10_50_10 ;
V : rgb_nxt = 24'h10_50_10 ;
W : rgb_nxt = 24'h00_00_f0 ;
X : rgb_nxt = 24'h27_75_02 ;
Y : rgb_nxt = rgb_in ;
Z : rgb_nxt = 24'h30_30_f0 ;
AY: rgb_nxt = 24'h00_00_00 ;
GY: rgb_nxt = 24'hff_ff_00 ;
KY: rgb_nxt = 24'h00_00_00 ;
PY: rgb_nxt = 24'h00_00_00 ;
TY: rgb_nxt = 24'h00_00_00 ;
WY: rgb_nxt = 24'hb0_70_20 ;
DY: rgb_nxt = 24'h7A_4D_2E ;
default: rgb_nxt = rgb_in;
endcase
end
always @(posedge clk or posedge rst) begin
if(rst) begin
block_xpos <= #1 0;
block_ypos <= #1 0;
end
else begin
block_xpos <= #1 block_xpos_nxt;
block_ypos <= #1 block_ypos_nxt;
end
end
always @(posedge pclk or posedge rst) begin
if(rst) begin
rgb_out <= #1 0;
hcount_out <= #1 0;
hsync_out <= #1 0;
vcount_out <= #1 0;
vsync_out <= #1 0;
blnk_out <= #1 0;
end
else begin
rgb_out <= #1 rgb_nxt;
hcount_out <= #1 hcount_in;
hsync_out <= #1 hsync_in;
vcount_out <= #1 vcount_in;
vsync_out <= #1 vsync_in;
blnk_out <= #1 blnk_in;
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2.0
// \ \ Application : MIG
// / / Filename : wiredly.v
// /___/ /\ Date Last Modified : $Date: 2011/06/23 08:25:20 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7Series
// Design Name : DDR2 SDRAM
// Purpose :
// This module provide the definition of a zero ohm component (A, B).
//
// The applications of this component include:
// . Normal operation of a jumper wire (data flowing in both directions)
// This can corrupt data from DRAM to FPGA useful for verifying ECC function.
//
// The component consists of 2 ports:
// . Port A: One side of the pass-through switch
// . Port B: The other side of the pass-through switch
// The model is sensitive to transactions on all ports. Once a transaction
// is detected, all other transactions are ignored for that simulation time
// (i.e. further transactions in that delta time are ignored).
// Model Limitations and Restrictions:
// Signals asserted on the ports of the error injector should not have
// transactions occuring in multiple delta times because the model
// is sensitive to transactions on port A, B ONLY ONCE during
// a simulation time. Thus, once fired, a process will
// not refire if there are multiple transactions occuring in delta times.
// This condition may occur in gate level simulations with
// ZERO delays because transactions may occur in multiple delta times.
//
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ns / 1ps
module WireDelay # (
parameter Delay_g = 0,
parameter Delay_rd = 0,
parameter ERR_INSERT = "OFF"
)
(
inout A,
inout B,
input reset,
input phy_init_done
);
reg A_r;
reg B_r;
reg B_inv ;
reg line_en;
reg B_nonX;
assign A = A_r;
assign B = B_r;
always @ (*)
begin
if (B === 1'bx)
B_nonX <= $random;
else
B_nonX <= B;
end
always@(*)
begin
if((B_nonX == 'b1) || (B_nonX == 'b0))
B_inv <= #0 ~B_nonX ;
else
B_inv <= #0 'bz ;
end
always @(*) begin
if (!reset) begin
A_r <= 1'bz;
B_r <= 1'bz;
line_en <= 1'b0;
end else begin
if (line_en) begin
B_r <= 1'bz;
if ((ERR_INSERT == "ON") & (phy_init_done))
A_r <= #Delay_rd B_inv;
else
A_r <= #Delay_rd B_nonX;
end else begin
B_r <= #Delay_g A;
A_r <= 1'bz;
end
end
end
always @(A or B) begin
if (!reset) begin
line_en <= 1'b0;
end else if (A !== A_r) begin
line_en <= 1'b0;
end else if (B_r !== B) begin
line_en <= 1'b1;
end else begin
line_en <= line_en;
end
end
endmodule
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module vgabase(
input wire clk,
input wire clr,
output reg hsync,
output reg vsync,
output reg [11:0] hc,
output reg [11:0] vc,
output wire vidon
);
/* 1024x768@60MHz */
parameter hpixels = 12'd1344;
parameter vlines = 12'd806;
parameter hsp = 12'd136;
parameter hbp = 12'd160;
parameter hfp = 12'd24;
parameter vsp = 12'd6;
parameter vbp = 12'd29;
parameter vfp = 12'd3;
/* */
reg vsenable;
initial begin
hc <= hpixels - hsp - hbp;
vc <= vlines - vsp - vbp;
hsync <= 0;
vsync <= 0;
vsenable <= 0;
end
always @(posedge clk or posedge clr) begin
if(clr == 1)
hc <= hpixels - hsp - hbp;
else begin
if(hc == hpixels - 1) begin
hc <= 0;
vsenable <= 1;
end else begin
hc <= hc + 1'b1;
vsenable <= 0;
end
end
end
always @(*) begin
if(hpixels - hsp - hbp < hc && hc <= hpixels - hbp)
hsync = 0;
else
hsync = 1;
end
always @(posedge clk or posedge clr) begin
if(clr == 1)
vc <= vlines - vsp - vbp;
else if(vsenable == 1)
if(vc == vlines - 1)
vc <= 0;
else
vc <= vc + 1'b1;
end
always @(*) begin
if(vlines - vsp - vbp < vc && vc <= vlines - vbp)
vsync = 0;
else
vsync = 1;
end
assign vidon=(hc<hpixels-hfp-hsp-hbp)&&(vc<vlines-vfp-vsp-vbp);
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline void read(T &x) { x = 0; char c = getchar(), f = 0; for (; c < 0 || c > 9 ; c = getchar()) if (c == - ) f = 1; for (; c >= 0 && c <= 9 ; c = getchar()) x = (x << 1) + (x << 3) + (c ^ 48); if (f) x = -x; } int vl, wh, n, nx[1005], a[1005], m; char st[1005], dp[1005]; int main() { read(n), read(wh); for (int i = 1, x; i <= n; i++) read(x), x ? nx[x] = i, st[i] = 1 : 0; for (int i = 1, c, x; i <= n; i++) if (!st[i]) { char tag = (c = 0) * (x = i); while (x) c++, (x == wh ? tag = 1, vl = c : 0), x = nx[x]; if (!tag) a[++m] = c; } dp[0] = 1; for (int i = 1; i <= m; i++) for (int j = n; j >= a[i]; j--) dp[j] |= dp[j - a[i]]; for (int i = 0; i <= n; i++) if (dp[i]) printf( %d n , i + vl); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, cnt, ans, tot; unordered_map<long long, int> id; int op[400010], d[400010], fa[400010], rk[400010], lg[400010], hs[400010]; struct node { int u, v; long long h; void bb() { if (u > v) swap(u, v); h = (long long)u << 30 | v; } } e[400010], g[400010]; int getfa(int x) { return fa[x] == x ? x : getfa(fa[x]); } void uni(int x, int y, int z) { x = getfa(x), y = getfa(y); if (rk[x] <= rk[y]) { fa[x] = y; lg[++tot] = x; hs[tot] = z; if (rk[x] == rk[y]) rk[y]++; } else { fa[y] = x; lg[++tot] = y; hs[tot] = z; } } void del(int x) { int i; for (i = tot; hs[i] != x; i--) { fa[lg[i]] = lg[i]; } fa[lg[i]] = lg[i]; int u = tot; tot = i - 1; for (i++; i <= u; i++) uni(g[hs[i]].u, g[hs[i]].v, hs[i]); } void solve(int be, int en) { for (int i = 1; i <= n; i++) fa[i] = i, rk[i] = 0; tot = 0; vector<int> v(cnt + 3), vv(cnt + 3); for (int i = 1; i < be; i++) if (op[i] == 1) v[d[i]] ^= 1; for (int i = be; i <= en; i++) if (op[i] == 1) vv[d[i]] = vv[d[i + m]] = 1; for (int i = 1; i <= cnt; i++) if (v[i] && !vv[i]) uni(g[i].u, g[i].v, i); for (int i = 1; i <= cnt; i++) if (v[i] && vv[i]) uni(g[i].u, g[i].v, i); for (int i = be; i <= en; i++) { if (ans) e[i] = e[i + m], d[i] = d[i + m]; if (op[i] == 1) { v[d[i]] ^= 1; if (v[d[i]]) uni(e[i].u, e[i].v, d[i]); else del(d[i]); } else { int x = getfa(e[i].u), y = getfa(e[i].v); if (x != y) putchar( 0 ), ans = 0; else putchar( 1 ), ans = 1; } } } int main(int argc, char const *argv[]) { scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d , &op[i]); scanf( %d%d , &e[i].u, &e[i].v); e[i].bb(); op[i + m] = op[i]; e[i + m] = {e[i].u % n + 1, e[i].v % n + 1}; e[i + m].bb(); } for (int i = 1, tot = m * 2; i <= tot; i++) { long long t = e[i].h; if (!id[t]) id[t] = ++cnt, g[cnt] = e[i]; d[i] = id[t]; } int B = sqrt(m); for (int i = 1; i <= m; i += B) solve(i, min(i + B - 1, m)); return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module ll8_to_fifo19
(input clk, input reset, input clear,
input [7:0] ll_data,
input ll_sof,
input ll_eof,
input ll_src_rdy,
output ll_dst_rdy,
output [18:0] f19_data,
output f19_src_rdy_o,
input f19_dst_rdy_i );
// Short FIFO on input to guarantee no deadlock
wire [7:0] ll_data_int;
wire ll_sof_int, ll_eof_int, ll_src_rdy_int, ll_dst_rdy_int;
ll8_shortfifo head_fifo
(.clk(clk), .reset(reset), .clear(clear),
.datain(ll_data), .sof_i(ll_sof), .eof_i(ll_eof),
.error_i(0), .src_rdy_i(ll_src_rdy), .dst_rdy_o(ll_dst_rdy),
.dataout(ll_data_int), .sof_o(ll_sof_int), .eof_o(ll_eof_int),
.error_o(), .src_rdy_o(ll_src_rdy_int), .dst_rdy_i(ll_dst_rdy_int));
// Actual ll8_to_fifo19 which could deadlock if not connected to a shortfifo
localparam XFER_EMPTY = 0;
localparam XFER_HALF = 1;
localparam XFER_HALF_WRITE = 3;
wire [18:0] f19_data_int;
wire f19_sof_int, f19_eof_int, f19_occ_int, f19_src_rdy_int, f19_dst_rdy_int;
wire xfer_out = f19_src_rdy_int & f19_dst_rdy_int;
wire xfer_in = ll_src_rdy_int & ll_dst_rdy_int;
reg hold_sof;
reg [1:0] state;
reg [7:0] hold_reg;
always @(posedge clk)
if(ll_src_rdy_int & (state==XFER_EMPTY))
hold_reg <= ll_data_int;
always @(posedge clk)
if(ll_sof_int & (state==XFER_EMPTY))
hold_sof <= 1;
else if(xfer_out)
hold_sof <= 0;
always @(posedge clk)
if(reset | clear)
state <= XFER_EMPTY;
else
case(state)
XFER_EMPTY :
if(ll_src_rdy_int)
if(ll_eof_int)
state <= XFER_HALF_WRITE;
else
state <= XFER_HALF;
XFER_HALF :
if(ll_src_rdy_int & f19_dst_rdy_int)
state <= XFER_EMPTY;
XFER_HALF_WRITE :
if(f19_dst_rdy_int)
state <= XFER_EMPTY;
endcase // case (state)
assign ll_dst_rdy_int = (state==XFER_EMPTY) | ((state==XFER_HALF)&f19_dst_rdy_int);
assign f19_src_rdy_int= (state==XFER_HALF_WRITE) | ((state==XFER_HALF)&ll_src_rdy_int);
assign f19_sof_int = hold_sof | (ll_sof_int & (state==XFER_HALF));
assign f19_eof_int = (state == XFER_HALF_WRITE) | ll_eof_int;
assign f19_occ_int = (state == XFER_HALF_WRITE);
assign f19_data_int = {f19_occ_int,f19_eof_int,f19_sof_int,hold_reg,ll_data_int};
// Shortfifo on output to guarantee no deadlock
fifo_short #(.WIDTH(19)) tail_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain(f19_data_int), .src_rdy_i(f19_src_rdy_int), .dst_rdy_o(f19_dst_rdy_int),
.dataout(f19_data), .src_rdy_o(f19_src_rdy_o), .dst_rdy_i(f19_dst_rdy_i),
.space(),.occupied() );
endmodule // ll8_to_fifo19
|
`timescale 1ns / 1ns
`define HALT 10'b00_0000_0000
`define EXEC 3'b100
module opc6tb();
reg [15:0] mem [ 65535:0 ], iomem[65535:0];
reg clk, reset_b, interrupt_b, int_clk, m1, clken;
wire [15:0] addr, data1;
wire rnw, vda, vpa, vio;
wire ceb = 1'b0;
wire oeb = !rnw;
reg [15:0] data0 ;
wire mreq_b = !(vda||vpa);
integer seed = 10;
// OPC CPU instantiation
opc6cpu dut0_u (.address(addr), .din(data0), .dout(data1), .rnw(rnw), .clk(clk), .reset_b(reset_b), .int_b({1'b1, interrupt_b}), .clken(clken), .vpa(vpa), .vda(vda), .vio(vio));
initial begin
`ifdef _dumpvcd
$dumpvars;
`endif
$readmemh("test.hex", mem); // Problems with readmemb - use readmemh for now
iomem[16'hfe08] = 16'b0;
{ clk, int_clk, reset_b} = 0;
`ifndef POSEDGE_MEMORY
clken = 1'b1;
`endif
interrupt_b = 1;
#3005 reset_b = 1;
#50000000000000 ; // no timeout
$finish;
end
always @ (posedge clk or negedge reset_b)
if ( !reset_b)
m1 = 1'b0;
else if (mreq_b == 1)
m1 <= 0;
else
m1 <= !m1;
`ifdef POSEDGE_MEMORY
always @ (negedge clk or negedge reset_b)
if ( !reset_b)
clken = 1'b1;
else
clken <= (mreq_b | m1 | !reset_b) ;
always @ (posedge clk) begin
`else // Negedge memory
always @ (negedge clk) begin
`endif
if (!rnw && !ceb && oeb && reset_b)
if ( !mreq_b) begin
mem[addr] <= data1;
$display(" STORE: Address : 0x%04x ( %d ) : Data : 0x%04x ( %d)",addr,addr,data1,data1);
end
else begin
iomem[addr]<= data1;
$display(" OUT: Address : 0x%04x ( %6d ) : Data : 0x%04x ( %6d) %c ",addr,addr,data1,data1,data1);
end
data0 <= (!mreq_b) ? mem[addr]: iomem[addr];
if ( dut0_u.FSM_q == dut0_u.RDM )
$display(" LOAD: Address : 0x%04x ( %d ) : Data : 0x%04x ( %d)",addr,addr,data0,data0);
end
always @ (posedge int_clk)
if ( (($random(seed) %100)> 85) && interrupt_b ==1'b1)
interrupt_b = 1'b0;
else
interrupt_b = 1'b1;
always begin
#273 int_clk = !int_clk;
#5000 int_clk = !int_clk;
end
always begin
#500 clk = !clk;
end
// Always stop simulation on encountering the halt pseudo instruction
always @ (negedge clk) begin
if ( dut0_u.FSM_q == dut0_u.EXEC ) begin
$write("0x%04x : ", addr );
$write(" : %04x %04x %04x %04x", dut0_u.RF_q[0],dut0_u.RF_q[1],dut0_u.RF_q[2],dut0_u.RF_q[3]);
$write(" %04x %04x %04x %04x", dut0_u.RF_q[4],dut0_u.RF_q[5],dut0_u.RF_q[6],dut0_u.RF_q[7]);
$write(" %04x %04x %04x %04x", dut0_u.RF_q[8],dut0_u.RF_q[9],dut0_u.RF_q[10],dut0_u.RF_q[11]);
$write(" %04x %04x %04x %04x", dut0_u.RF_q[12],dut0_u.RF_q[13],dut0_u.RF_q[14],dut0_u.PC_q);
$display("");
end
if (dut0_u.IR_q[10:0]== `HALT && dut0_u.FSM_q==`EXEC) begin
$display("Simulation terminated with halt instruction at time", $time);
$writememh("test.vdump",mem);
$finish;
end
end
endmodule
|
// This is the Avalon slave for the IMU
//
// Registers 0-7 store ADC outputs
module imu_controller(
input chipselect,
input [3:0]addr,
input read,
output reg [31:0] readdata,
input spi_clk,
input sys_clk,
input ADC_SDAT,
output ADC_CS_N,
output ADC_SADDR,
output ADC_SCLK
);
wire [8*32-1:0] adc_channels;
imu imu(
.reset_n(1'b1),
.spi_clk(spi_clk),
.sys_clk(sys_clk),
.sda(),
.scl(),
.adc_channels(adc_channels),
.ADC_SDAT(ADC_SDAT),
.ADC_CS_N(ADC_CS_N),
.ADC_SADDR(ADC_SADDR),
.ADC_SCLK(ADC_SCLK)
);
always @(posedge sys_clk)
if (chipselect & read)
casex (addr)
4'b0000:
readdata <= adc_channels[1*32-1:0*32];
4'b0001:
readdata <= adc_channels[2*32-1:1*32];
4'b0010:
readdata <= adc_channels[3*32-1:2*32];
4'b0011:
readdata <= adc_channels[4*32-1:3*32];
4'b0100:
readdata <= adc_channels[5*32-1:4*32];
4'b0101:
readdata <= adc_channels[6*32-1:5*32];
4'b0110:
readdata <= adc_channels[7*32-1:6*32];
4'b0111:
readdata <= adc_channels[8*32-1:7*32];
default:
readdata <= 32'd0;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, ed, x, y; int l[200005], qd[200005], qn[200005], p[200005]; void bd(int x, int y) { qd[++ed] = y, qn[ed] = l[x], l[x] = ed; } int notinE(int x, int y) { for (int i = (l[x]); i; i = qn[i]) if (qd[i] == y) return 0; return 1; } int main() { scanf( %d%d , &n, &m); for (int i = (0); i < (m); i++) scanf( %d%d , &x, &y), bd(x - 1, y - 1), bd(y - 1, x - 1); for (int i = (0); i < (n); i++) p[i] = i; for (int i = (0); i < (75); i++) { random_shuffle(p, p + n); p[n] = p[0]; int ok = 1; for (int j = (1); j <= (m); j++) if (!notinE(p[j - 1], p[j])) { ok = 0; break; } if (ok) { for (int j = (1); j <= (m); j++) printf( %d %d n , p[j - 1] + 1, p[j] + 1); return 0; } } puts( -1 ); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; long long k; int res[1000]; long long dp[205][205]; int p[105][105]; pair<int, int> a[10005]; long long calc(int i, int j) { if (j < 0) return 0; if (i == n + m - 1) { return (j == 0); } if (dp[i][j] != -1) return dp[i][j]; long long &ans = dp[i][j]; ans = 0; if (res[i] != 0) ans = calc(i + 1, j + res[i]); else { ans = calc(i + 1, j + 1) + calc(i + 1, j - 1); } if (ans >= k) ans = k; return ans; } long long solve() { memset(dp, -1, sizeof(dp)); return calc(0, 0); } int main() { cin >> n >> m >> k; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { int x; cin >> x; a[x - 1] = make_pair(i, j); } } for (int l = 0; l < n * m; ++l) { int i = a[l].first; int j = a[l].second; if (res[i + j] == 0) { res[i + j] = 1; long long cur = solve(); if (cur >= k) continue; k -= cur; res[i + j] = -1; } } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (res[i + j] == 1) putchar( ( ); else putchar( ) ); } puts( ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD3_FUNCTIONAL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD3_FUNCTIONAL_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd3 (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD3_FUNCTIONAL_V |
/* -------------------- | LOSER | | ~NOOBOSS~ | -------------------- */ #include <bits/stdc++.h> using namespace std; #define mxx 1e18 #define mnn -1e18 #define Y() cout<< YES <<endl #define N() cout << NO <<endl #define endl n #define Ceil(x,y) ((x+y-1)/y) #define sz(s) (int)s.size() #define angle(x) double(x * acos(-1) / 180.0) #define max_3(a,b,c) max(a, max(b,c)) #define min_3(a,b,c) min(a, min(b,c)) #define gcd(a,b) __gcd(a,b) #define lcm(a,b) (a*b)/gcd(a,b) #define loser return 0 #define ll long long #define PI acos(-1) #define mem(a,v) memset(a,v,sizeof(a)) #define SORT(v) sort(v.begin(),v.end()) #define REV(v) reverse(v.begin(),v.end()) #define B begin() #define E end() #define V vector #define F first #define S second #define PSB push_back #define MP make_pair #define flash cout.flush() #define InTheNameOfGod ios::sync_with_stdio(0);cin.tie(0); cout.tie(0); constexpr ll MOD = 998244353; constexpr ll mod = 1e9 + 7; int dx[] = {0,0,1,-1}; int dy[] = {1,-1,0,0}; /*-----*/ #define bug1(a) cerr<<a<<endl; #define bug2(a,b) cerr<<a<< <<b<<endl; #define bug3(a,b,c) cerr<<a<< <<b<< <<c<<endl; /*----*/ const ll N=3e6+5; vector<ll> adj[N]; ll power(ll n,ll p){if(p==0) return 1;if(p==1)return n;if(p%2)return power(n,p-1)*n;else{ll x=power(n,p/2);return x*x;}} ll modpow(ll a,ll b,ll m){ll ans=1;while(b){if(b&1)ans=(ans*a)%m;b/=2;a=(a*a)%m;}return ans;} ll nsum(ll num){return (num*(num+1))/2;} void edge (ll u,ll v) {adj[u].PSB(v) ;adj[v].PSB(u);} /*------------------START---------------------*/ /*-----*/ void solve(){ ll n,k; string s; cin>>n>>k; if(n<3){ if(k) cout<<-1<<endl; else{ for(ll i=1;i<=n;i++) cout<<i<< ; cout<<endl; } return; } ll mx=1; ll bal=n-3; mx+=bal/2; if(k>mx){ cout<<-1<<endl; } else{ cout<<1<< ; ll ct=2; for(ll i=2;i<=n;i++){ if(k){ cout<<i+1<< <<i<< ; --k; i++; } else{ cout<<i<< ; } } cout<<endl; } //cout << fixed << setprecision(10); } /*-----*/ int main(){ InTheNameOfGod ll Test=1; cin>>Test; while(Test--){ solve(); } loser; } /////// C O D I N G I S L I F E /////// |
`timescale 1ns/1ps
module tb_cocotb #(
parameter DATA_WIDTH = 32,
parameter FIFO_WIDTH = 8
)(
input rst,
input [31:0] test_id,
//write side
input WR_CLK,
output WR_RDY,
input WR_ACT,
output [23:0] WR_SIZE,
input WR_STB,
input [DATA_WIDTH - 1: 0] WR_DATA,
output WR_STARVED,
//read side
input RD_CLK,
input RD_STB,
output RD_RDY,
input RD_ACT,
output [23:0] RD_SIZE,
output [DATA_WIDTH - 1: 0] RD_DATA,
output RD_INACTIVE
);
//Local Parameters
//Registers/Wires
reg r_rst;
//Submodules
block_fifo#(
.DATA_WIDTH (DATA_WIDTH ),
.ADDRESS_WIDTH (FIFO_WIDTH )
)pp(
//universal input
.reset (r_rst ),
//Write Path
.write_clock (WR_CLK ),
.write_ready (WR_RDY ),
.write_activate (WR_ACT ),
.write_fifo_size (WR_SIZE ),
.write_strobe (WR_STB ),
.write_data (WR_DATA ),
.starved (WR_STARVED ),
//Read Path
.read_clock (RD_CLK ),
.read_strobe (RD_STB ),
.read_ready (RD_RDY ),
.read_activate (RD_ACT ),
.read_count (RD_SIZE ),
.read_data (RD_DATA ),
.inactive (RD_INACTIVE )
);
//There is a timing thing in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_convert_from_half(clock, resetn, dataa, result, valid_in, valid_out, stall_in, stall_out, enable);
// Convert a floating-point number from half-precision to single-precision. No rounding is required.
// Half format is [sign, 5-bit exponent, 10-bit mantissa]
parameter HIGH_CAPACITY = 1;
input clock, resetn;
input [15:0] dataa;
output [31:0] result;
input valid_in, stall_in, enable;
output valid_out, stall_out;
wire c1_enable;
reg c1_valid;
wire c1_stall;
reg [7:0] c1_exponent;
reg [22:0] c1_mantissa;
reg c1_sign;
assign c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
wire [3:0] count;
wire [9:0] shifted_mantissa;
half_type_clz clz(.mantissa(dataa[9:0]), .count(count));
assign shifted_mantissa = dataa[9:0] << count;
always@(posedge clock or negedge resetn)
begin
if(~resetn)
begin
c1_valid <= 1'b0;
c1_exponent <= 8'dx;
c1_mantissa <= 23'dx;
c1_sign <= 1'bx;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
c1_sign <= dataa[15];
if (&dataa[14:10])
begin
c1_exponent <= 8'hff;
c1_mantissa <= {dataa[9:0], 13'd0};
end
else if (~(|dataa[14:10]))
begin
// in a case of exponent being 0, we only set exponent to zero if the mantissa is all zeros.
// Otherwise, we must shift the mantissa left and adjust the exponent accordingly.
if (~|dataa[9:0])
begin
c1_exponent <= 8'd0;
c1_mantissa <= 23'd0;
end
else
begin
c1_exponent <= 8'd112 - {1'b0, count};
c1_mantissa <= {shifted_mantissa[8:0], 14'd0};
end
end
else
begin
c1_exponent <= 8'd112 + {1'b0, dataa[14:10]};
c1_mantissa <= {dataa[9:0], 13'd0};
end
end
end
assign result = {c1_sign, c1_exponent, c1_mantissa};
assign valid_out = c1_valid;
assign c1_stall = stall_in;
endmodule
module half_type_clz(mantissa, count);
input [9:0] mantissa;
output [3:0] count;
assign count[3] = ~|mantissa[9:2];
assign count[2] = |mantissa[9:2] & ~|mantissa[9:6];
assign count[1] = count[3] & ~|mantissa[1:0] | ~count[3] & (~count[2] & ~|mantissa[9:8] | count[2] & ~|mantissa[5:4]);
assign count[0] = (mantissa[9:8] == 2'b01) |
(mantissa[9:6] == 4'b0001) |
(mantissa[9:4] == 6'b000001) |
(mantissa[9:2] == 8'b00000001) |
(mantissa == 10'b0000000001);
endmodule
|
// Single rail, 2-phase arbitrer
// From
// The Design and Implementation of an Asynchronous Microprocessor.
// PhD Thesis by Nigel Charles Paver
// From figure 3.16, page 42
// http://apt.cs.manchester.ac.uk/publications/thesis/paver94_phd.php
// Modified to get acknowledge signals on the input ports
module arbitrer_r1_2ph(/*AUTOARG*/
// Outputs
a1, a2, g1, g2,
// Inputs
r1, r2, d1, d2, rstn
);
input r1;
output a1;
input r2;
output a2;
output g1;
input d1;
output g2;
input d2;
input rstn;
wire mutex_r1, mutex_r2;
wire toogle_in1,toggle_in2;
wire cm1,cm2;
wire g1_released, g2_released;
muller2 U_MULLER_1(.a(!g1_released),
.b(r1),
.rstn(rstn),
.z(cm1));
muller2 U_MULLER_2(.a(!g2_released),
.b(r2),
.rstn(rstn),
.z(cm2));
xor2 U_XOR2_1 (.a(cm1),.b(d1),.z(mutex_r1));
xor2 U_XOR2_2 (.a(cm2),.b(d2),.z(mutex_r2));
mutex U_MUTEX(
.r1(mutex_r1),
.r2(mutex_r2),
.g1(toggle_in1),
.g2(toggle_in2)
);
`ifndef USE_TOGGLE_SIMPLE
toggle U_TOGGLE_1 (.in(toggle_in1),
.dot(g1),
.blank(g1_released),
.rstn(rstn));
toggle U_TOGGLE_2 (.in(toggle_in2),
.dot(g2),
.blank(g2_released),
.rstn(rstn));
`else
toggle_simple U_TOGGLE_1 (.in(toggle_in1),
.dot(g1),
.blank(g1_released),
.rstn(rstn));
toggle_simple U_TOGGLE_2 (.in(toggle_in2),
.dot(g2),
.blank(g2_released),
.rstn(rstn));
`endif
// ack feedback on input ports
muller2 U_MULLER_ACK1(.a(r1),.b(d1),.rstn(rstn),.z(a1));
muller2 U_MULLER_ACK2(.a(r2),.b(d2),.rstn(rstn),.z(a2));
`ifdef DEBUG
assign input_port1_ongoing_req = r1 ^ a1;
assign input_port2_ongoing_req = r2 ^ a2;
assign output_port1_unstable = g1 ^ d1;
assign output_port2_unstable = g2 ^ d2;
assign error = output_port1_unstable & output_port2_unstable;
initial begin
#1;
@(posedge error);
$display("-E arbitrer_r1_2ph : error found in protocol");
#100;
$finish;
end
`endif
endmodule //
|
#include <bits/stdc++.h> using namespace std; int main() { std::ios_base::sync_with_stdio(false); cin.tie(NULL); long long int a, b; cin >> a >> b; vector<long long int> m; vector<long long int> n; set<long long int> s; m.push_back(1); n.push_back(1); if (a == 1) s.insert(1); for (long long int i = 1; i <= b;) { i = i * 2; m.push_back(i); if (i >= a && i <= b) s.insert(i); } for (long long int i = 1; i <= b;) { i = i * 3; n.push_back(i); if (i >= a && i <= b) s.insert(i); } for (int i = 0; i < m.size(); i++) { for (int j = 0; j < n.size(); j++) { long long int x = m[i] * n[j]; if (x >= a && x <= b) { s.insert(x); } } } cout << s.size() << endl; } |
#include <bits/stdc++.h> using namespace std; int n, m, x, y, ans, f[200005]; char s[11]; int find(int k) { if (k == f[k]) return k; return f[k] = find(f[k]); } void add(int x, int y) { if (find(x) != find(y)) f[find(x)] = find(y); } int main() { scanf( %d%d , &n, &m); for (int i = 1; i <= 2 * n + 3; i++) f[i] = i; for (int i = 1; i <= m; i++) { scanf( %d%d%s , &x, &y, s); x -= y; y = min(x + 2 * y, 2 * n - x - 2 * y + 2); x = max(x, -x); if (s[0] == x ) { add(2 * y, 2 * x); add(2 * y + 1, 2 * x + 1); } else { add(2 * y + 1, 2 * x); add(2 * x + 1, 2 * y); } } for (int i = 0; i <= n + 1; i++) if (find(2 * i) == find(2 * i + 1)) { printf( 0 ); return 0; } int s = 0; for (int i = 0; i <= 2 * n + 3; i++) s += (find(i) == i); s = s / 2 - 2; ans = 1; for (int i = 1; i <= s; i++) ans = ans * 2 % 1000000007; printf( %d , ans); } |
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_int_mult32s_s5 (
enable,
clock,
dataa,
datab,
result);
parameter INPUT1_WIDTH = 32;
parameter INPUT2_WIDTH = 32;
localparam INPUT1_WIDTH_WITH_SIGN = INPUT1_WIDTH < 32 ? INPUT1_WIDTH + 1 : INPUT1_WIDTH;
localparam INPUT2_WIDTH_WITH_SIGN = INPUT2_WIDTH < 32 ? INPUT2_WIDTH + 1 : INPUT2_WIDTH;
input enable;
input clock;
input [INPUT1_WIDTH_WITH_SIGN - 1 : 0] dataa;
input [INPUT2_WIDTH_WITH_SIGN - 1 : 0] datab;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg [31:0] result;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH_WITH_SIGN - 1 : 0] reg_dataa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH_WITH_SIGN - 1 : 0] reg_datab;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH_WITH_SIGN - 1 : 0] reg_dataa2;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH_WITH_SIGN - 1 : 0] reg_datab2;
generate
if(INPUT1_WIDTH>=19 && INPUT1_WIDTH<=27 && INPUT2_WIDTH>=19 && INPUT2_WIDTH<=27)
begin
// Use a special WYSIWYG for the 27x27 multiplier mode
always@(posedge clock)
begin
if (enable)
begin
reg_dataa <= dataa;
reg_datab <= datab;
end
end
wire [53:0] mul_result;
wire [26:0] inp_a;
wire [26:0] inp_b;
assign inp_a = reg_dataa;
assign inp_b = reg_datab;
sv_mult27 the_multiplier(clock,enable,inp_a,inp_b,mul_result);
always@(*)
begin
result <= mul_result;
end
end
else
begin
// Default LPM_MULT inference
always@(posedge clock)
begin
if (enable)
begin
result <= reg_dataa2 * reg_datab2;
reg_dataa <= dataa;
reg_datab <= datab;
reg_dataa2 <= reg_dataa;
reg_datab2 <= reg_datab;
end
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 15:16:08 09/12/2015
// Design Name: Gate-level implementation of 4:3 encoder.
// Module Name: encoder43gates
//////////////////////////////////////////////////////////////////////////////////
module encoder43gates(A, B, C, D, Y2, Y1, Y0);
input A, B, C, D;
output Y2, Y1, Y0;
wire Ai, Bi, Ci, Di;
wire w2, w3, w4, w5, w6, w7, w8, w9, w10, w11, w12, w13, w14, w15;
not NotA(Ai, A);
not NotB(Bi, B);
not NotC(Ci, C);
not NotD(Di, D);
// Gates for Y2
and U1(Y2, A, B, C, D);
// Gates for Y1
and U2(w2, Ai, B, D);
and U3(w3, A, B, Ci);
and U4(w4, A, Bi, D);
and U5(w5, A, Bi, C);
and U6(w6, Ai, C, D);
and U7(w7, B, C, Di);
// Gates for Y0
and U8(w8, Ai, Bi, Ci, D);
and U9(w9, Ai, Bi, C, Di);
and U10(w10, Ai, B, Ci, Di);
and U11(w11, A, Bi, Ci, Di);
and U12(w12, Ai, B, C, D);
and U13(w13, A, Bi, C, D);
and U14(w14, A, B, Ci, D);
and U15(w15, A, B, C, Di);
or U16(Y1, w2, w3, w4, w5, w6, w7);
or U17(Y0, w8, w9, w10, w11, w12, w13, w14, w15);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int n; vector<int> v, lm, rm; class SegmentTreeMax { public: int n; vector<long long> vect; SegmentTreeMax(int _n) : n(_n) { vect.resize(2 * n); fill(vect.begin(), vect.end(), 0); } void modify(int p, long long value) { for (vect[p += n] = value; p > 1; p >>= 1) { int val = rm[vect[p]] > rm[vect[p ^ 1]] ? vect[p] : vect[p ^ 1]; vect[p >> 1] = val; } } long long query(int l, int r) { long long res = 0; for (l += n, r += n; l < r; l >>= 1, r >>= 1) { if (l & 1) { if (rm[res] < rm[vect[l]]) res = vect[l]; l++; } if (r & 1) { if (rm[res] < rm[vect[r - 1]]) res = vect[r - 1]; r--; } } return res; } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n; v.resize(n + 1); lm.resize(n + 1); rm.resize(n + 1); vector<int> v2; for (int i = 1; i <= n; i++) { cin >> v[i]; v2.push_back(v[i]); } v2.push_back(0); sort(v2.begin(), v2.end()); auto it = unique(v2.begin(), v2.end()); v2.resize(it - v2.begin()); int l = 1, r = 1; vector<int> ans; SegmentTreeMax stm(n + 1); vector<int> visited, ct(n + 1); vector<vector<int>> updates(n + 1); while (r <= n) { int id = lower_bound(v2.begin(), v2.end(), v[r]) - v2.begin(); if (!lm[id]) lm[id] = r; int val = stm.query(l, lm[id]); updates[id].push_back(r); rm[id] = r; ct[id]++; visited.push_back(id); if (rm[val] > lm[id] || ct[id] == 4) { if (ct[id] == 4) { for (int i = 0; i < 4; i++) ans.push_back(v[r]); } else { ans.push_back(v2[val]); ans.push_back(v[r]); ans.push_back(v2[val]); ans.push_back(v[r]); } for (int i : visited) { lm[i] = 0; rm[i] = 0; ct[i] = 0; updates[i].clear(); } visited.clear(); l = r + 1; r = l; } else { for (int i : updates[id]) { stm.modify(i, id); } r++; } } cout << ans.size() << n ; for (int i : ans) { cout << i << ; } return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( O2 ) using namespace std; const int MAXN = 1e6 + 10; const long long MOD = 1e9 + 7; const long long MOD2 = 998244353; const long long INF = 8e18; const int LOG = 22; long long pw(long long a, long long b, long long mod) { return (!b ? 1 : (b & 1 ? (a * pw(a * a % mod, b / 2, mod)) % mod : pw(a * a % mod, b / 2, mod))); } long long dp[2][MAXN]; int x[MAXN]; vector<int> G[MAXN]; void DFS(int v, int par) { dp[0][v] = 1; dp[1][v] = 0; for (auto u : G[v]) { if (u == par) { continue; } DFS(u, v); dp[1][v] = (dp[1][v] * dp[0][u]) % MOD; dp[1][v] = (dp[1][v] + dp[1][u] * dp[0][v]) % MOD; dp[0][v] = (dp[0][v] * dp[0][u]) % MOD; } if (x[v]) { dp[1][v] = dp[0][v]; } else { dp[0][v] = (dp[0][v] + dp[1][v]) % MOD; } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; int n; cin >> n; for (int i = 1; i < n; i++) { int a; cin >> a; G[a].push_back(i); G[i].push_back(a); } for (int i = 0; i < n; i++) { cin >> x[i]; } DFS(0, -1); cout << dp[1][0] << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long int v[300001], sol[300001], S; int cnt = 0, marked[300001], dp[300001][2]; vector<int> g[300001]; long long int dfs(int node, int p) { sol[node] = v[node]; long long int res = sol[node]; for (auto it : g[node]) if (it != p) { res = max(res, dfs(it, node)); if (sol[it] > 0) sol[node] += sol[it]; } res = max(res, sol[node]); return res; } void getcnt(int node, int p) { for (auto it : g[node]) if (it != p) { getcnt(it, node); if (sol[it] > 0 && marked[it]) marked[node] = 1; } if (!marked[node] && sol[node] == S) { cnt++; marked[node] = 1; } } int main() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, m, i, a, b, k; cin >> n; for (i = 0; i < n; i++) cin >> v[i]; for (i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; g[u - 1].push_back(v - 1); g[v - 1].push_back(u - 1); } S = dfs(0, 0); getcnt(0, 0); cout << S * cnt << << cnt << n ; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast,no-stack-protector ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( fast-math ) using namespace std; template <class T> ostream &operator<<(ostream &str, vector<T> &a) { for (auto &i : a) { str << i << ; } return str; } template <class T> istream &operator>>(istream &str, vector<T> &a) { for (auto &i : a) { str >> i; } return str; } template <class T> ostream &operator<<(ostream &str, pair<T, T> &a) { str << a.first << << a.second; return str; } template <class T> istream &operator>>(istream &str, pair<T, T> &a) { str >> a.first >> a.second; return str; } void solve(); signed main() { srand(time(0)); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout.setf(ios::fixed); cout.precision(6); solve(); return 0; } int n, m; int get_sum(vector<vector<int>> &b, int i1, int j1, int i2, int j2) { return b[i2][j2] - b[i1 - 1][j2] - b[i2][j1 - 1] + b[i1 - 1][j1 - 1]; } bool check(int k, vector<vector<int>> &a, vector<vector<int>> &b, vector<vector<int>> &tmp) { int len = 2 * k + 1; if (len > n || len > m) { return false; } vector<vector<int>> v(m + 2, vector<int>(n + 2)); for (int i = 1; i <= n - len + 1; ++i) { for (int j = 1; j <= m - len + 1; ++j) { int sum = get_sum(b, i, j, i + len - 1, j + len - 1); if (sum == len * len) { tmp[i + len / 2][j + len / 2] = 1; v[j][i] += 1, v[j][i + len] -= 1; v[j + len][i] -= 1, v[j + len][i + len] += 1; } } } for (int j = 1; j <= m; ++j) { for (int i = 1; i <= n; ++i) { v[j][i] = v[j][i - 1] + v[j][i]; } } vector<vector<int>> c(n + 1, vector<int>(m + 1)); for (int j = 1; j <= m; ++j) { for (int i = 1; i <= n; ++i) { c[i][j] = v[j][i]; } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { c[i][j] = c[i][j - 1] + c[i][j]; } } for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { if (a[i][j] && c[i][j] == 0) { return false; } } } return true; } void solve() { cin >> n >> m; vector<vector<int>> a(n + 1, vector<int>(m + 1)); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { char ch; cin >> ch; a[i][j] = (ch == X ? 1 : 0); } } vector<vector<int>> b = a; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { b[i][j] = b[i][j] + b[i - 1][j] + b[i][j - 1] - b[i - 1][j - 1]; } } vector<vector<int>> ans(n + 1, vector<int>(m + 1)); int l = 0, r = min(n, m); while (r - l > 1) { int k = (r + l) / 2; vector<vector<int>> tmp(n + 1, vector<int>(m + 1)); if (check(k, a, b, tmp)) { ans = tmp; l = k; } else { r = k; } } check(l, a, b, ans); cout << (l) << n ; ; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { cout << (ans[i][j] ? X : . ); } cout << n ; } } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module cf_csc_1 (
// csc inputs
// csc <= c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4;
clk,
vs,
hs,
de,
data,
C1,
C2,
C3,
C4,
// these are the delay matched versions of the inputs
csc_vs,
csc_hs,
csc_de,
csc_data_1);
// csc inputs
// csc <= c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4;
input clk;
input vs;
input hs;
input de;
input [23:0] data;
input [16:0] C1;
input [16:0] C2;
input [16:0] C3;
input [24:0] C4;
// these are the delay matched versions of the inputs
output csc_vs;
output csc_hs;
output csc_de;
output [ 7:0] csc_data_1;
wire [24:0] data_1_m_s;
wire [ 2:0] ddata_1_m_s;
wire [24:0] data_2_m_s;
wire [ 2:0] ddata_2_m_s;
wire [24:0] data_3_m_s;
wire [ 2:0] ddata_3_m_s;
wire [ 2:0] ddata_m_s;
assign ddata_m_s = ddata_1_m_s & ddata_2_m_s & ddata_3_m_s;
// c1*R
cf_csc_1_mul #(.DELAY_DATA_WIDTH(3)) i_mul_c1 (
.clk (clk),
.data_a (C1),
.data_b (data[23:16]),
.data_p (data_1_m_s),
.ddata_in ({vs, hs, de}),
.ddata_out (ddata_1_m_s));
// c2*G
cf_csc_1_mul #(.DELAY_DATA_WIDTH(3)) i_mul_c2 (
.clk (clk),
.data_a (C2),
.data_b (data[15:8]),
.data_p (data_2_m_s),
.ddata_in ({vs, hs, de}),
.ddata_out (ddata_2_m_s));
// c3*B
cf_csc_1_mul #(.DELAY_DATA_WIDTH(3)) i_mul_c3 (
.clk (clk),
.data_a (C3),
.data_b (data[7:0]),
.data_p (data_3_m_s),
.ddata_in ({vs, hs, de}),
.ddata_out (ddata_3_m_s));
// last stage addition
cf_csc_1_add #(.DELAY_DATA_WIDTH(3)) i_add_c4 (
.clk (clk),
.data_1 (data_1_m_s),
.data_2 (data_2_m_s),
.data_3 (data_3_m_s),
.data_4 (C4),
.data_p (csc_data_1),
.ddata_in (ddata_m_s),
.ddata_out ({csc_vs, csc_hs, csc_de}));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2B_2_V
`define SKY130_FD_SC_LP__NOR2B_2_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2b_2 (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2b_2 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2B_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__HA_PP_SYMBOL_V
`define SKY130_FD_SC_HS__HA_PP_SYMBOL_V
/**
* ha: Half adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__ha (
//# {{data|Data Signals}}
input A ,
input B ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__HA_PP_SYMBOL_V
|
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