text stringlengths 59 71.4k |
|---|
/*
* Copyright 2013-2021 Robert Newgard
*
* This file is part of fcs.
*
* fcs is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* fcs is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with fcs. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
`include "fcs32_8.v"
`include "fcs32_brev.v"
module uut_8_top
(
output wire [31:0] res_o,
output wire [31:0] exp_o,
output wire [31:0] obs_o,
output wire val_o,
input wire [7:0] data_i,
input wire sof_i,
input wire eof_i,
input wire pclk_i
);
/* -----------------------------------------------------------
parameters
------------------------------------------------------------*/
localparam LO = 1'b0;
localparam HI = 1'b1;
localparam [31:0] ZEROS = {32{LO}};
localparam [31:0] ONES = {32{HI}};
localparam FIRST = 7;
localparam LAST = 9;
/* -----------------------------------------------------------
net declarations
------------------------------------------------------------*/
reg [7:0] data_z1;
reg sof_z1;
reg [7:0] data_z2;
reg sof_z2;
reg [7:0] data_z3;
reg sof_z3;
reg [7:0] data_z4;
reg sof_z4;
reg val_z5;
reg [31:0] exp_z5;
reg [31:0] fcs_z5;
reg val_z6;
reg [31:0] exp_z6;
reg [31:0] fcs_z6;
reg [31:0] exp[FIRST:LAST];
reg [31:0] crc[FIRST:LAST];
reg val[FIRST:LAST];
/* -----------------------------------------------------------
input assignments
------------------------------------------------------------*/
/* -----------------------------------------------------------
Pipeline
------------------------------------------------------------*/
always @ (posedge pclk_i) begin
data_z1[7:0] <= data_i[7:0];
sof_z1 <= sof_i;
data_z2[7:0] <= data_z1[7:0];
sof_z2 <= sof_z1;
data_z3[7:0] <= data_z2[7:0];
sof_z3 <= sof_z2;
data_z4[7:0] <= data_z3[7:0];
sof_z4 <= sof_z3;
val_z5 <= eof_i;
if (eof_i == HI) begin
exp_z5[31:0] <= {data_z3[7:0], data_z2[7:0], data_z1[7:0], data_i[7:0]};
end
if (sof_z4 == HI) begin
fcs_z5[31:0] <= fcs32_8(data_z4[7:0], ONES[31:0]);
end else begin
fcs_z5[31:0] <= fcs32_8(data_z4[7:0], fcs_z5[31:0]);
end
val_z6 <= val_z5;
exp_z6[31:0] <= exp_z5[31:0];
fcs_z6[31:0] <= fcs32_brev(fcs_z5[31:0]);
end
generate
genvar i;
for (i = FIRST ; i <= LAST ; i = i + 1) begin : ppln_delay
always @ (posedge pclk_i) begin
if (i == FIRST) begin
exp[i][31:0] <= exp_z6[31:0];
crc[i][31:0] <= fcs_z6[31:0];
val[i] <= val_z6;
end else begin
exp[i][31:0] <= exp[i - 1][31:0];
crc[i][31:0] <= crc[i - 1][31:0];
val[i] <= val[i - 1];
end
end
end
endgenerate
/* -----------------------------------------------------------
output assignments
------------------------------------------------------------*/
always @ (*) begin
res_o[31:0] = fcs_z5[31:0];
exp_o[31:0] = exp[LAST][31:0];
obs_o[31:0] = crc[LAST][31:0];
val_o = val[LAST];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void fft(vector<complex<double> > &a, bool invert) { int n = a.size(), lg = 0; while (1 << lg < n) ++lg; assert(1 << lg == n); for (int i = 0; i < n; ++i) { int rev = 0; for (int j = 0; j < lg; ++j) if ((i & 1 << j) != 0) rev |= 1 << (lg - j - 1); if (i < rev) swap(a[i], a[rev]); } vector<complex<double> > roots(n); for (int i = 0; i < n; ++i) { double a = 2 * M_PI * i / n * (invert ? -1 : 1); roots[i] = complex<double>(cos(a), sin(a)); } for (int len = 2; len <= n; len *= 2) for (int i = 0; i < n; i += len) for (int j = 0; j < len / 2; ++j) { complex<double> u = a[i + j], v = a[i + j + len / 2] * roots[n / len * j]; a[i + j] = u + v; a[i + j + len / 2] = u - v; } if (invert) for (int i = 0; i < n; ++i) a[i] /= n; } vector<int> multiply(const vector<int> &a, const vector<int> &b) { int m = a.size(), n = b.size(), p = 2; while (p < m + n - 1) p <<= 1; vector<complex<double> > pa(p), pb(p); for (int i = 0; i < m; ++i) pa[i] = complex<double>(a[i], 0); for (int i = 0; i < n; ++i) pb[i] = complex<double>(b[i], 0); fft(pa, false); fft(pb, false); for (int i = 0; i < p; ++i) pa[i] *= pb[i]; fft(pa, true); vector<int> res(p); for (int i = 0; i < p; ++i) res[i] = (int)round(real(pa[i])); return res; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; vector<bool> hasBag(m + 1); vector<int> p(m + 1); for (int i = 0; i < n; ++i) { int w; cin >> w; p[w] = 1; hasBag[w] = true; } p = multiply(p, p); for (int i = 1; i <= m; ++i) if (p[i] > 0) { if (!hasBag[i]) return cout << NO , 0; hasBag[i] = false; } printf( YES n%d n , count(hasBag.begin(), hasBag.end(), 1)); for (int i = 1; i <= m; ++i) if (hasBag[i] == 1) printf( %d , i); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t, tc; cin >> t; for (tc = 0; tc < t; tc++) { int n, i; cin >> n; vector<int> v(n), mx(n + 1, 0), mn(n + 1, n + 5); for (i = 0; i < n; i++) { cin >> v[i]; mx[v[i]] = i; mn[v[i]] = i; } for (i = 2; i <= n; i++) { mx[i] = max(mx[i - 1], mx[i]); mn[i] = min(mn[i - 1], mn[i]); } for (i = 1; i <= n; i++) { if (mx[i] - mn[i] == i - 1) { cout << 1 ; } else { cout << 0 ; } } cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; using pll = pair<ll, ll>; using vpii = vector<pii>; using vpll = vector<pll>; template <typename T> ostream &operator<<(ostream &os, const vector<T> &v) { for (const auto &x : v) os << x << ; return os << endl; } ll ceil_div(ll a, ll b) { return (a + b - 1) / b; } void solve(int n) { if (n == 1) { cout << -1 << endl; return; } for (int i = 0; i < n; i++) { cout << (i == 0 ? 2 : 3); } cout << endl; } int main(int argc, char const *argv[]) { int T; cin >> T; for (int t = 0; t < T; t++) { int n; cin >> n; solve(n); } return 0; } |
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// track min and max peak values (envelope follower)
//
// NB: the min value (resp. max value) is updated only when the next high peak
// (resp. low peak) is reached/detected, since you can't know it isn't a
// local minima (resp. maxima) until then.
// This also means the peaks are detected with an unpredictable delay.
// This algorithm therefore can't be used directly for realtime peak detections,
// but it can be used as a simple envelope follower.
module min_max_tracker(input clk, input [7:0] adc_d, input [7:0] threshold,
output [7:0] min, output [7:0] max);
reg [7:0] min_val = 255;
reg [7:0] max_val = 0;
reg [7:0] cur_min_val = 255;
reg [7:0] cur_max_val = 0;
reg [1:0] state = 0;
always @(posedge clk)
begin
case (state)
0: // initialize
begin
if (cur_max_val >= ({1'b0, adc_d} + threshold))
state <= 2;
else if (adc_d >= ({1'b0, cur_min_val} + threshold))
state <= 1;
if (cur_max_val <= adc_d)
cur_max_val <= adc_d;
else if (adc_d <= cur_min_val)
cur_min_val <= adc_d;
end
1: // high phase
begin
if (cur_max_val <= adc_d)
cur_max_val <= adc_d;
else if (({1'b0, adc_d} + threshold) <= cur_max_val) begin
state <= 2;
cur_min_val <= adc_d;
max_val <= cur_max_val;
end
end
2: // low phase
begin
if (adc_d <= cur_min_val)
cur_min_val <= adc_d;
else if (adc_d >= ({1'b0, cur_min_val} + threshold)) begin
state <= 1;
cur_max_val <= adc_d;
min_val <= cur_min_val;
end
end
endcase
end
assign min = min_val;
assign max = max_val;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 2000000; char a[MAXN + 10], b[MAXN + 10]; int main(void) { int n; scanf( %d%s%s , &n, a, b); int cnt[2][2]; for (int i = 0; i < (2); ++i) { for (int j = 0; j < (2); ++j) { cnt[i][j] = 0; } } n *= 2; for (int i = 0; i < (n); ++i) { ++cnt[a[i] - 0 ][b[i] - 0 ]; } int sA = 0, sB = 0; for (int i = 0; i < (n); ++i) { if (cnt[1][1] > 0) { --cnt[1][1]; ++sA; } else if (cnt[1][0] > 0) { --cnt[1][0]; ++sA; } else if (cnt[0][1] > 0) { --cnt[0][1]; } else { --cnt[0][0]; } if (cnt[1][1] > 0) { --cnt[1][1]; ++sB; } else if (cnt[0][1] > 0) { --cnt[0][1]; ++sB; } else if (cnt[1][0] > 0) { --cnt[1][0]; } else { --cnt[0][0]; } } if (sA > sB) { puts( First ); } else if (sA < sB) { puts( Second ); } else { puts( Draw ); } return 0; } |
#include <bits/stdc++.h> using namespace std; string tobinary(long long x) { string ret; char ch; while (x) ch = 0 + (x % 2), ret = ch + ret, x /= 2; return ret; } long long todecimal(string s) { int sz = s.size(); long long ret = 0; for (int i = 0; i < sz; i++) ret = 2 * ret + (s[i] - 0 ); return ret; } bool _greater(string s, string t) { int n = s.size(), m = t.size(); if (n > m) return true; if (n < m) return false; for (int i = 0; i < n; i++) { if (s[i] > t[i]) return true; else if (s[i] < t[i]) return false; } return false; } long long eval(long long l, long long r) { string s = tobinary(l), t = tobinary(r), ret = s; while (1) { if (_greater(s, t)) break; ret = s; int sz = s.size(); bool ok = false; for (int i = sz - 1; i >= 0; i--) if (s[i] == 0 ) { s[i] = 1 ; ok = true; break; } if (!ok) { s = 1 + s; int n = s.size(), m = t.size(); if (n > m) break; } } return todecimal(ret); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; while (n--) { long long l, r; cin >> l >> r; cout << eval(l, r) << endl; } return 0; } |
module daala_idct4_stream_v1_0_M00_AXIS #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
parameter integer C_M_AXIS_TDATA_WIDTH = 32,
// Start count is the numeber of clock cycles the master will wait before initiating/issuing any transaction.
parameter integer C_M_START_COUNT = 32
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Global ports
input wire M_AXIS_ACLK,
//
input wire M_AXIS_ARESETN,
// Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
output wire M_AXIS_TVALID,
// TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
// TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
// TLAST indicates the boundary of a packet.
output wire M_AXIS_TLAST,
// TREADY indicates that the slave can accept a transfer in the current cycle.
input wire M_AXIS_TREADY
);
//Total number of output data.
// Total number of output data
localparam NUMBER_OF_OUTPUT_WORDS = 8;
// function called clogb2 that returns an integer which has the
// value of the ceiling of the log base 2.
function integer clogb2 (input integer bit_depth);
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction
// WAIT_COUNT_BITS is the width of the wait counter.
localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);
// bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.
localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS);
// Define the states of state machine
// The control state machine oversees the writing of input streaming data to the FIFO,
// and outputs the streaming data from the FIFO
parameter [1:0] IDLE = 2'b00, // This is the initial/idle state
INIT_COUNTER = 2'b01, // This state initializes the counter, ones
// the counter reaches C_M_START_COUNT count,
// the state machine changes state to INIT_WRITE
SEND_STREAM = 2'b10; // In this state the
// stream data is output through M_AXIS_TDATA
// State variable
reg [1:0] mst_exec_state;
// Example design FIFO read pointer
reg [bit_num-1:0] read_pointer;
// AXI Stream internal signals
//wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
reg [WAIT_COUNT_BITS-1 : 0] count;
//streaming data valid
wire axis_tvalid;
//streaming data valid delayed by one clock cycle
reg axis_tvalid_delay;
//Last of the streaming data
wire axis_tlast;
//Last of the streaming data delayed by one clock cycle
reg axis_tlast_delay;
//FIFO implementation signals
reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out;
wire tx_en;
//The master has issued all the streaming data stored in FIFO
reg tx_done;
// I/O Connections assignments
assign M_AXIS_TVALID = axis_tvalid_delay;
assign M_AXIS_TDATA = stream_data_out;
assign M_AXIS_TLAST = axis_tlast_delay;
assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
// Control state machine implementation
always @(posedge M_AXIS_ACLK)
begin
if (!M_AXIS_ARESETN)
// Synchronous reset (active low)
begin
mst_exec_state <= IDLE;
count <= 0;
end
else
case (mst_exec_state)
IDLE:
// The slave starts accepting tdata when
// there tvalid is asserted to mark the
// presence of valid streaming data
if ( count == 0 )
begin
mst_exec_state <= INIT_COUNTER;
end
else
begin
mst_exec_state <= IDLE;
end
INIT_COUNTER:
// The slave starts accepting tdata when
// there tvalid is asserted to mark the
// presence of valid streaming data
if ( count == C_M_START_COUNT - 1 )
begin
mst_exec_state <= SEND_STREAM;
end
else
begin
count <= count + 1;
mst_exec_state <= INIT_COUNTER;
end
SEND_STREAM:
// The example design streaming master functionality starts
// when the master drives output tdata from the FIFO and the slave
// has finished storing the S_AXIS_TDATA
if (tx_done)
begin
mst_exec_state <= IDLE;
end
else
begin
mst_exec_state <= SEND_STREAM;
end
endcase
end
//tvalid generation
//axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
//number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
// AXI tlast generation
// axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1
// (0 to NUMBER_OF_OUTPUT_WORDS-1)
assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);
// Delay the axis_tvalid and axis_tlast signal by one clock cycle
// to match the latency of M_AXIS_TDATA
always @(posedge M_AXIS_ACLK)
begin
if (!M_AXIS_ARESETN)
begin
axis_tvalid_delay <= 1'b0;
axis_tlast_delay <= 1'b0;
end
else
begin
axis_tvalid_delay <= axis_tvalid;
axis_tlast_delay <= axis_tlast;
end
end
//read_pointer pointer
always@(posedge M_AXIS_ACLK)
begin
if(!M_AXIS_ARESETN)
begin
read_pointer <= 0;
tx_done <= 1'b0;
end
else
if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)
begin
if (tx_en)
// read pointer is incremented after every read from the FIFO
// when FIFO read signal is enabled.
begin
read_pointer <= read_pointer + 1;
tx_done <= 1'b0;
end
end
else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)
begin
// tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
// has been out.
tx_done <= 1'b1;
end
end
//FIFO read enable generation
assign tx_en = M_AXIS_TREADY && axis_tvalid;
// Streaming output data is read from FIFO
always @( posedge M_AXIS_ACLK )
begin
if(!M_AXIS_ARESETN)
begin
stream_data_out <= 1;
end
else if (tx_en)// && M_AXIS_TSTRB[byte_index]
begin
stream_data_out <= read_pointer + 32'b1;
end
end
// Add user logic here
// User logic ends
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 08:26:59 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_rgb888_to_rgb565_0_0 -prefix
// system_rgb888_to_rgb565_0_0_ system_rgb888_to_rgb565_0_0_sim_netlist.v
// Design : system_rgb888_to_rgb565_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_rgb888_to_rgb565_0_0,rgb888_to_rgb565,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "rgb888_to_rgb565,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_rgb888_to_rgb565_0_0
(rgb_888,
rgb_565);
input [23:0]rgb_888;
output [15:0]rgb_565;
wire [23:0]rgb_888;
assign rgb_565[15:11] = rgb_888[23:19];
assign rgb_565[10:5] = rgb_888[15:10];
assign rgb_565[4:0] = rgb_888[7:3];
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DECAP_FUNCTIONAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__decap ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; using ull = unsigned long long; using ll = long long; using ld = long double; const int mod = 1e9 + 7; const double pi = acos(-1.0); const int inf = INT_MAX; const int N = (1 << 22); int h, g, a[N]; bool ok(int i) { while (true) { if (a[i << 1] == 0 && a[i << 1 | 1] == 0) { break; } if (a[i << 1] > a[i << 1 | 1]) { i = i << 1; } else { i = i << 1 | 1; } } int msb = 32 - __builtin_clz(i) - 1; return msb >= g; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int t; cin >> t; while (t--) { cin >> h >> g; for (int i = 1; i < (1 << h); i++) cin >> a[i]; fill(a + (1 << h), a + (1 << (h + 1)), 0); vector<int> ops; for (int i = 1; i < (1 << g); i++) { while (ok(i)) { ops.push_back(i); int j; for (j = i; a[j << 1] || a[j << 1 | 1];) { if (a[j << 1] > a[j << 1 | 1]) { a[j] = a[j << 1]; j = j << 1; } else { a[j] = a[j << 1 | 1]; j = j << 1 | 1; } } a[j] = 0; } } ll ans = 0; for (int i = 1; i < (1 << g); i++) { ans += a[i]; } cout << ans << n ; for (int i : ops) cout << i << ; cout << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__CLKBUF_FUNCTIONAL_PP_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__clkbuf (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long fp(long long x, long long y, long long m = 998244353) { long long ANS = 1; while (y) { if (y & 1) ANS = (ANS * x) % 998244353; x = (x * x) % 998244353; y >>= 1; } return ANS; } long long inv(long long x, long long m = 998244353) { return fp(x, m - 2); } long long testcases, arr[200001], n; string s; int32_t main() { iostream::sync_with_stdio(0), cin.tie(0); cin >> testcases; while (testcases--) { cin >> n; for (long long i = 0; i < n; i++) cin >> arr[i]; cin >> s; multiset<long long> L, S; for (long long i = 0; i < n; i++) { if (s[i] == R ) L.insert(arr[i]); else S.insert(arr[i]); } for (long long i = 1; i <= n; i++) { auto itr = S.lower_bound(i); if (itr == S.end()) { auto itr2 = L.upper_bound(i); if (itr2 == L.begin()) { cout << NO << n ; goto a; } itr2--; L.erase(itr2); } else S.erase(itr); } cout << YES << n ; a:; } } |
#include <bits/stdc++.h> using namespace std; struct node { int a, b; bool operator<(const node& r) const { return r.b < b; } } e[105]; int dp[10005][105]; int main() { int n, sum = 0, num = 0, sum2 = 0; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %d , &e[i].a); sum += e[i].a; } for (int i = 0; i < n; i++) { scanf( %d , &e[i].b); sum2 += e[i].b; } sort(e, e + n); for (int i = 0; i < n; i++) { num += e[i].b; if (num >= sum) { num = i + 1; break; } } for (int i = sum2; i >= 0; i--) { for (int k = num; k >= 0; k--) { dp[i][k] = -234723846; } } dp[0][0] = 0; for (int i = 0; i < n; i++) { for (int k = sum2; k >= e[i].b; k--) { for (int j = num; j >= 1; j--) { dp[k][j] = max(dp[k][j], dp[k - e[i].b][j - 1] + e[i].a); } } } int ans = 0; for (int i = sum; i <= sum2; i++) { ans = max(ans, dp[i][num]); } printf( %d %d n , num, sum - ans); } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); string s, t, p = ; cin >> s >> t; int n = s.size(); int c = 0; for (int i = 0; i < n; i++) if (s[i] != t[i]) c++; if (c % 2) { cout << impossible ; return 0; } for (int i = 0; i < n; i++) { if (s[i] == t[i]) { p += s[i]; continue; } if (c) p += s[i], c -= 2; else p += t[i]; } cout << p << endl; return 0; } |
`timescale 1ns/1ps
//-----------------------------------------------------------------------------
// Title : KPU interrupt controller
// Project : KPU
//-----------------------------------------------------------------------------
// File : kpu.v
// Author : acorallo <>
// Created : 12.3.2017
//-----------------------------------------------------------------------------
// Description :
// Interrupt controller for KPU
//-----------------------------------------------------------------------------
// This file is part of KPU.
// KPU is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// KPU is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY;
// without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with KPU. If not, see <http://www.gnu.org/licenses/>.
//
// Copyright (c) 2016 2017 by Andrea Corallo.
//------------------------------------------------------------------------------
// Modification history :
// 12.3.2017 : created
//-----------------------------------------------------------------------------
`ifndef _int_ctrl
`define _int_ctrl
`include "kpu_conf.v"
module int_ctrl(
input wire clk_i,
input wire rst_i,
input wire [`IO_INT_N-1:0] io_int_i, // we support 16 interrupt lines
output reg io_int_o, // interrupt line out
output reg [`N-1:0] int_num_o // interrupt number raised
);
initial begin
io_int_o <= 1'b0;
int_num_o <= `N'h0;
end
always @(posedge clk_i) begin
if (rst_i) begin
io_int_o <= 1'b0;
int_num_o <= `N'h0;
end
else if (!io_int_o && io_int_i != `IO_INT_N'h0) begin
io_int_o <= 1'b1;
if (io_int_i[0])
int_num_o <= `N'h0;
else if (io_int_i[1])
int_num_o <= `N'h1;
else if (io_int_i[2])
int_num_o <= `N'h2;
else if (io_int_i[3])
int_num_o <= `N'h3;
else if (io_int_i[4])
int_num_o <= `N'h4;
else if (io_int_i[5])
int_num_o <= `N'h5;
else if (io_int_i[6])
int_num_o <= `N'h6;
else if (io_int_i[7])
int_num_o <= `N'h7;
else if (io_int_i[8])
int_num_o <= `N'h8;
else if (io_int_i[9])
int_num_o <= `N'h9;
else if (io_int_i[10])
int_num_o <= `N'ha;
else if (io_int_i[11])
int_num_o <= `N'hb;
else if (io_int_i[12])
int_num_o <= `N'hc;
else if (io_int_i[13])
int_num_o <= `N'hd;
else if (io_int_i[14])
int_num_o <= `N'he;
else if (io_int_i[15])
int_num_o <= `N'hf;
end
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; int main() { int T, n, i, j, k; cin >> T; while (T--) { cin >> n; string str[51]; for (i = 0; i < n; i++) { cin >> str[i]; } if (n == 1) { cout << YES << endl; continue; } for (i = n - 1; i >= 0; i--) { for (j = n - 1; j >= 0; j--) { if (str[i][j] == 1 ) { if (i == n - 1 || j == n - 1) str[i][j] = * ; k = n - 1; int c = 0; while (k >= 0) { if (str[k][j] == * ) { c = 1; } else if (str[k][j] == 1 && c == 1) { str[k][j] = * ; } else if (str[k][j] == 0 ) c = 0; k--; } k = n - 1; c = 0; while (k >= 0) { if (str[i][k] == * ) { c = 1; } else if (str[i][k] == 1 && c == 1) { str[i][k] = * ; } else if (str[i][k] == 0 ) c = 0; k--; } } } } for (i = n - 1; i >= 0; i--) { for (j = n - 1; j >= 0; j--) { if (str[i][j] == 1 ) { if (i == n - 1 || j == n - 1) str[i][j] = * ; k = n - 1; int c = 0; while (k >= 0) { if (str[i][k] == * ) { c = 1; } else if (str[i][k] == 1 && c == 1) { str[i][k] = * ; } else if (str[i][k] == 0 ) c = 0; k--; } k = n - 1; c = 0; while (k >= 0) { if (str[k][j] == * ) { c = 1; } else if (str[k][j] == 1 && c == 1) { str[k][j] = * ; } else if (str[k][j] == 0 ) c = 0; k--; } } } } int cnt = 0; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) { if (str[i][j] == 1 ) { cnt++; } } } if (cnt == 0) cout << YES << endl; else cout << NO << endl; } return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module tri_intersect_fmul_32ns_32ns_32_5_max_dsp
#(parameter
ID = 23,
NUM_STAGE = 5,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
tri_intersect_ap_fmul_3_max_dsp_32 tri_intersect_ap_fmul_3_max_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
#include <bits/stdc++.h> int n, m; std::vector<std::vector<int> > gr; std::vector<int> par; std::vector<bool> vis; std::vector<int> lev; void dfsgr(int v) { vis[v] = true; for (auto& ch : (gr[v])) { if (vis[ch]) continue; lev[ch] = lev[v] + 1; par[ch] = v; dfsgr(ch); } } int lca(int a, int b) { if (lev[a] > lev[b]) std::swap(a, b); while (lev[b] != lev[a]) b = par[b]; while (a != b) { a = par[a]; b = par[b]; } return a; } int main() { std::ios_base::sync_with_stdio(false); std::cin.tie(0); std::cin >> n >> m; gr.resize(n); vis.resize(n); par.resize(n, -1); lev.resize(n); for (int i = 0; i < (m); ++i) { int a, b; std::cin >> a >> b; a--; b--; gr[a].push_back(b); gr[b].push_back(a); } dfsgr(0); int q; std::cin >> q; std::vector<int> dd(n); std::vector<std::vector<int> > paths; for (int _ = 0; _ < (q); ++_) { int a, b; std::cin >> a >> b; a--; b--; int lc = lca(a, b); int pos = a; std::vector<int> pth; while (pos != lc) { dd[pos] ^= 1; pth.push_back(pos); pos = par[pos]; } pth.push_back(lc); std::vector<int> nd; pos = b; while (pos != lc) { dd[pos] ^= 1; nd.push_back(pos); pos = par[pos]; } while (((int)(nd).size())) pth.push_back(nd.back()), nd.pop_back(); paths.push_back(std::move(pth)); } bool good = true; for (int i = 0; i < (n); ++i) { if (dd[i]) good = false; } if (good) { std::cout << YES n ; for (auto& p : (paths)) { std::cout << ((int)(p).size()) << n ; for (auto& i : (p)) std::cout << i + 1 << ; std::cout << n ; } } else { std::cout << NO n ; std::vector<std::vector<int> > ed(n); for (int i = 0; i < (n); ++i) if (dd[i]) { ed[i].push_back(par[i]); ed[par[i]].push_back(i); } std::fill(vis.begin(), vis.end(), false); int xd = 0; std::function<int(int)> dfs = [&](int v) { vis[v] = true; int mam = 0; for (auto& ch : (ed[v])) if (!vis[ch]) { dfs(ch); mam++; } xd += mam / 2; return mam % 2; }; int ans = 0; for (int i = 0; i < (n); ++i) if (!vis[i]) { xd = 0; if (dfs(i)) xd++; ans += xd; } std::cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int eet(long long int a, long long int b, long long int *x, long long int *y) { if (a == 0) { *x = 0; *y = 1; return b; } long long int x1, y1; long long int gcd = eet(b % a, a, &x1, &y1); *x = y1 - (b / a) * x1; *y = x1; return gcd; } int main() { long long int n, m, i, j, k, cnt = 0, sum = 0, mn = INT_MAX, ind, rem = 1000000007, ok = 0, size, lcm, mx = INT_MIN, diff, num, x, y, z, ee; int flag = 0, t = 1; string s, str, s1, s2, s3; char ch; ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); while (t--) { long long int a, b, c; cin >> a >> b >> c; c = -c; long long int GCD = eet(a, b, &x, &y); if (c % GCD != 0) { cout << -1; return 0; } long long int mul = c / GCD; cout << x * mul << << y * mul; cout << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, m; cin >> n >> m; long long t = 1; if (n < 30) { for (int i = 0; i < n; i++) { t *= 2; } cout << m % t; } else { cout << m; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxVal = 200005; int arr[maxVal]; int tree[4 * maxVal]; void build(int node, int start, int endd, int k) { if (start == endd) { if (arr[start] >= k) tree[node] = 1; else tree[node] = 0; } else { int mid = (start + endd) / 2; build(2 * node, start, mid, k); build(2 * node + 1, mid + 1, endd, k); tree[node] = tree[2 * node] + tree[2 * node + 1]; } } int query(int node, int start, int endd, int l, int r) { if (start > r || endd < l) { return 0; } else if (l <= start && endd <= r) { return tree[node]; } else { int mid = (start + endd) / 2; int a1 = query(2 * node, start, mid, l, r); int a2 = query(2 * node + 1, mid + 1, endd, l, r); return a1 + a2; } } int main() { int n, m, k; cin >> n >> k >> m; int a, b; for (int i = 0; i < n; i++) { cin >> a >> b; arr[a]++; arr[b + 1]--; } for (int i = 1; i < maxVal; i++) { arr[i] = arr[i] + arr[i - 1]; } build(1, 0, maxVal, k); for (int i = 0; i < m; i++) { cin >> a >> b; cout << query(1, 0, maxVal, a, b) << endl; } } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build Mon Oct 10 19:07:27 MDT 2016
// Date : Fri Sep 22 10:48:49 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[7:0],probe8[63:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[0:0],probe13[7:0],probe14[63:0],probe15[1:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[0:0],probe20[0:0],probe21[1:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [7:0]probe7;
input [63:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [0:0]probe12;
input [7:0]probe13;
input [63:0]probe14;
input [1:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [0:0]probe18;
input [0:0]probe19;
input [0:0]probe20;
input [1:0]probe21;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, k; vector<int> g[100005]; int siz[100005]; bool era[100005]; long long rans; int col[100005]; int calc(int v, int p) { int cnt = 1; for (int i = 0; i < (int)g[v].size(); i++) { int to = g[v][i]; if (to == p || era[to]) continue; cnt += calc(to, v); } siz[v] = cnt; return cnt; } pair<int, int> fnd(int v, int p, int t) { pair<int, int> res = make_pair(1e9, -1); int cnt = 1, mx = 0; for (int i = 0; i < (int)g[v].size(); i++) { int to = g[v][i]; if (to == p || era[to]) continue; res = min(res, fnd(to, v, t)); cnt += siz[to]; mx = max(mx, siz[to]); } mx = max(mx, t - cnt); res = min(res, make_pair(mx, v)); return res; } void solve(int v, int lev) { calc(v, -1); int s = fnd(v, -1, siz[v]).second; era[s] = 1; col[s] = lev; for (int i = 0; i < (int)g[s].size(); i++) { if (era[g[s][i]]) continue; solve(g[s][i], lev + 1); } era[s] = 0; } int main() { scanf( %d , &n); for (int i = 0; i < n - 1; i++) { int a, b; scanf( %d %d , &a, &b); g[a].push_back(b); g[b].push_back(a); } solve(1, 1); for (int i = 1; i <= n; i++) if (col[i] > 26) { puts( Impossible! ); return 0; } for (int i = 1; i <= n; i++) printf( %c , col[i] - 1 + A ); puts( ); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 200005; int n, q, a[N], c[N], l[N], r[N]; vector<int> s[N], p[N], b; set<int> s1, s2, s3, s4, s5, s6, s7; int main() { scanf( %d%d , &n, &q); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= q; i++) { scanf( %d%d , &l[i], &r[i]); p[l[i]].push_back(i); } for (int i = n; i; i--) { int x; while (s1.size() && a[x = *s1.begin()] < a[i]) { s6.insert(x); c[x]--; if (!c[x]) s5.insert(x); s1.erase(x); } while (s2.size() && a[x = *s2.begin()] > a[i]) { s7.insert(x); c[x]--; if (!c[x]) s5.insert(x); s2.erase(x); } while (s3.size() && a[x = *s3.begin()] <= a[i]) s3.erase(x); while (s4.size() && a[x = *s4.begin()] >= a[i]) s4.erase(x); if (s3.size() && s4.size()) { auto it = s5.lower_bound(max(*s3.begin(), *s4.begin())); if (it != s5.end() && (!b.size() || *it < b.back())) { b = {i, *it}; auto it2 = s1.lower_bound(*it); it2--; b.push_back(*it2); it2 = s2.lower_bound(*it); it2--; b.push_back(*it2); sort(b.begin(), b.end()); } } for (int j : p[i]) { if (b.size() && b.back() <= r[j]) s[j] = b; else { if (s3.size()) { auto it = s6.lower_bound(*s3.begin()); if (it != s6.end() && *it <= r[j]) s[j] = {i, *it - 1, *it}; } if (s4.size()) { auto it = s7.lower_bound(*s4.begin()); if (it != s7.end() && *it <= r[j]) s[j] = {i, *it - 1, *it}; } } } c[i] = 2; s1.insert(i), s2.insert(i), s3.insert(i), s4.insert(i); } for (int i = 1; i <= q; i++) { printf( %d n , s[i].size()); for (auto j : s[i]) printf( %d , j); puts( ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, j, s; int k[100000], a[100000], b[100000]; int main() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> k[i]; for (int i = 0; i < m; i++) { int x, y, z; cin >> x >> y; if (x == 1) { cin >> z; k[y - 1] = z; a[y - 1] = s; } if (x == 2) s += y; if (x == 3) { b[j] = k[y - 1] + s - a[y - 1]; j++; } } for (int i = 0; i < j; i++) cout << b[i] << endl; } |
#include <bits/stdc++.h> using namespace std; const int _ = 1e5 + 7; const int __ = 4e5 + 7; const int L = 11; int n, Q; long long a[_], pw[L + 7]; namespace SGT { long long num[__], minx[__], tag[__]; bool cov[__]; bool flag; void Build(int k, int l, int r) { if (l == r) { int j = 0; while (pw[j] < a[l]) ++j; minx[k] = pw[j] - a[l], num[k] = a[l]; return; } Build((k << 1), l, ((l + r) >> 1)); Build((k << 1 | 1), ((l + r) >> 1) + 1, r); minx[k] = min(minx[(k << 1)], minx[(k << 1 | 1)]); num[k] = minx[(k << 1)] < minx[(k << 1 | 1)] ? num[(k << 1)] : num[(k << 1 | 1)]; } void upd(int k, long long w) { minx[k] -= w, num[k] += w, tag[k] += w; } void Psd(int k) { if (cov[k]) { cov[(k << 1)] = 1, num[(k << 1)] = num[k], minx[(k << 1)] = minx[k]; cov[(k << 1 | 1)] = 1, num[(k << 1 | 1)] = num[k], minx[(k << 1 | 1)] = minx[k]; cov[k] = 0, tag[k] = 0; } else if (tag[k]) { upd((k << 1), tag[k]); upd((k << 1 | 1), tag[k]); tag[k] = 0; } } void Modify(int k, int l, int r, int x, int y, int w) { if (l >= x and r <= y) { if (minx[k] > w) { upd(k, w); return; } else if (l == r or cov[k]) { num[k] += w; int j = 1; while (pw[j] < num[k]) ++j; minx[k] = pw[j] - num[k]; if (!minx[k]) flag = 1; return; } } Psd(k); if (x <= ((l + r) >> 1)) Modify((k << 1), l, ((l + r) >> 1), x, y, w); if (y > ((l + r) >> 1)) Modify((k << 1 | 1), ((l + r) >> 1) + 1, r, x, y, w); minx[k] = min(minx[(k << 1)], minx[(k << 1 | 1)]); num[k] = minx[(k << 1)] < minx[(k << 1 | 1)] ? num[(k << 1)] : num[(k << 1 | 1)]; } void Cover(int k, int l, int r, int x, int y, int w) { if (l >= x and r <= y) { tag[k] = 0, num[k] = w, cov[k] = 1; int j = 1; while (pw[j] < w) ++j; minx[k] = pw[j] - w; return; } Psd(k); if (x <= ((l + r) >> 1)) Cover((k << 1), l, ((l + r) >> 1), x, y, w); if (y > ((l + r) >> 1)) Cover((k << 1 | 1), ((l + r) >> 1) + 1, r, x, y, w); minx[k] = min(minx[(k << 1)], minx[(k << 1 | 1)]); num[k] = minx[(k << 1)] < minx[(k << 1 | 1)] ? num[(k << 1)] : num[(k << 1 | 1)]; } long long Query(int k, int l, int r, int x) { if (l == r) return num[k]; Psd(k); if (x <= ((l + r) >> 1)) return Query((k << 1), l, ((l + r) >> 1), x); else return Query((k << 1 | 1), ((l + r) >> 1) + 1, r, x); } void Init() { Build(1, 1, n); } void Add(int l, int r, int w) { do { flag = 0; Modify(1, 1, n, l, r, w); } while (flag); } void Cover(int l, int r, int w) { Cover(1, 1, n, l, r, w); } long long Ask(int x) { return Query(1, 1, n, x); } } // namespace SGT int gi() { int x = 0; char c = getchar(); while (!isdigit(c)) c = getchar(); while (isdigit(c)) x = (x << 3) + (x << 1) + c - 0 , c = getchar(); return x; } void Init() { n = gi(), Q = gi(); for (int i = 1; i <= n; ++i) a[i] = gi(); pw[0] = 1; for (int i = 1; i <= L; ++i) pw[i] = (long long)pw[i - 1] * 42; SGT::Init(); } void Run() { int ty, l, r, x; while (Q--) { ty = gi(); if (ty == 1) printf( %lld n , SGT::Ask(gi())); else { l = gi(), r = gi(), x = gi(); if (ty == 2) SGT::Cover(l, r, x); else SGT::Add(l, r, x); } } } int main() { Init(); Run(); return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:28:48 05/31/2011
// Design Name: upd77c25
// Module Name: /home/ikari/prj/sd2snes/verilog/sd2snes/updtest.tf
// Project Name: sd2snes
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: upd77c25
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module updtest;
// Inputs
reg [7:0] DI;
reg A0;
reg nCS;
reg nRD;
reg nWR;
reg RST;
reg CLK;
reg PGM_WR;
reg [23:0] PGM_DI;
reg [10:0] PGM_WR_ADDR;
reg DAT_WR;
reg [15:0] DAT_DI;
reg [9:0] DAT_WR_ADDR;
// debug
wire [15:0] SR;
wire [15:0] DR;
wire [10:0] PC;
wire [15:0] A;
wire [15:0] B;
wire [5:0] FL_A;
wire [5:0] FL_B;
// Outputs
wire [7:0] DO;
// variables
integer i;
// Instantiate the Unit Under Test (UUT)
upd77c25 uut (
.DI(DI),
.DO(DO),
.A0(A0),
.nCS(nCS),
.nRD(nRD),
.nWR(nWR),
.DP_nCS(1'b1),
.RST(RST),
.CLK(CLK),
.PGM_WR(PGM_WR),
.PGM_DI(PGM_DI),
.PGM_WR_ADDR(PGM_WR_ADDR),
.DAT_WR(DAT_WR),
.DAT_DI(DAT_DI),
.DAT_WR_ADDR(DAT_WR_ADDR),
.SR(SR),
.DR(DR),
.PC(PC),
.A(A),
.B(B),
.FL_A(FL_A),
.FL_B(FL_B)
);
initial begin
// Initialize Inputs
DI = 0;
A0 = 0;
nCS = 0;
nRD = 1;
nWR = 1;
RST = 1;
CLK = 0;
PGM_WR = 0;
PGM_DI = 0;
PGM_WR_ADDR = 0;
DAT_WR = 0;
DAT_DI = 0;
DAT_WR_ADDR = 0;
// Wait 100 ns for global reset to finish
#1000;
// Add stimulus here
nRD = 0;
#100 nRD = 1;
for (i=0; i < 1; i = i + 1) begin
#200 nRD = 0;
#200 nRD = 1;
end
#1000 DI = 8'h02;
nWR = 0;
#200 nWR = 1;
#3000 DI = 8'hc2;
for (i=0; i < 6; i = i + 1) begin
#400 nWR = 0;
#400 nWR = 1;
#400 nWR = 0;
#400 nWR = 1;
end
#15000;
#200 nWR = 0;
#200 nWR = 1;
#200 nWR = 0;
#200 nWR = 1;
#50000;
for (i=0; i < 10; i = i + 1) begin
#200 nRD = 0;
#200 nRD = 1;
end
#200 DI = 8'h06;
nWR = 0;
#200 nWR = 1;
#200 DI = 8'h7f;
for (i=0; i < 3; i = i + 1) begin
#400 nWR = 0;
#400 nWR = 1;
#400 nWR = 0;
#400 nWR = 1;
end
#15000;
for (i=0; i < 10; i = i + 1) begin
#200 nRD = 0;
#200 nRD = 1;
end
end
always #6 CLK = ~CLK;
endmodule
|
`timescale 1ns/10ps
module PushBtnSim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
reg button;
wire button_status;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#10000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`PushBtn_RDBS,8'bxxxxxxxx};
inst_en = 1;
button = 0;
#4 inst = {`PushBtn_NOP,8'bxxxxxxxx};
inst_en = 1;
#5 button = 1;
#60 button = 0;
#7 inst = {`PushBtn_RDBS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`PushBtn_NOP,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`PushBtn_RDBS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`PushBtn_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 button = 1;
#60 button = 0;
#8 inst = {`PushBtn_RDBS,8'bxxxxxxxx};
inst_en = 0;
#4 inst = {`PushBtn_RDBS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`PushBtn_RDBS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`PushBtn_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,8'hAA};
inst_en = 1;
#4 inst = {`PushBtn_RDBS,8'bxxxxxxxx};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#4 inst = {`PushBtn_RDBS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`PushBtn_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test multiple presses before one read.
#4 button = 1;
#60 button = 0;
#8 button = 1;
#60 button = 0;
#8 button = 1;
#60 button = 0;
#8 inst = {`PushBtn_RDBS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`PushBtn_RDBS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`PushBtn_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test multiple presses before one read. Some of the presses are caused by bounces.
#4 button = 1;
#8 button = 0;
#4 button = 1;
#16 button = 0;
#4 button = 1;
#60 button = 0;
#8 button = 1;
#16 button = 0;
#4 inst = {`PushBtn_RDBS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`PushBtn_RDBS,8'bxxxxxxxx};
inst_en = 1;
#4 inst = {`PushBtn_NOP,8'bxxxxxxxx};
inst_en = 1;
end
PushBtn #(.DebounceWait(10),
.DebounceSize(4))
pushbtn (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.button(button),
.button_status(button_status));
endmodule // PushBtnSim
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: HeapRAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module HeapRAM (
address,
byteena,
clock,
data,
wren,
q);
input [11:0] address;
input [1:0] byteena;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC "byteena[1..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL HeapRAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL HeapRAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL HeapRAM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL HeapRAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL HeapRAM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL HeapRAM_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__INV_FUNCTIONAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INV_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; long long int dp[100000 + 5] = {0}; void fun(long long int *A, long long int N) { dp[0] = 0; long long int a = 0; for (long long int i = 1; i <= 100000; ++i) { while (a < N and A[a] <= i) ++a; dp[i] = a; } } void solve() { long long int N; cin >> N; long long int A[N]; for (long long int i = 0; i < N; ++i) cin >> A[i]; sort(A, A + N); fun(A, N); long long int Q; cin >> Q; while (Q--) { long long int M; cin >> M; if (M > 100000) cout << N << n ; else cout << dp[M] << n ; } } int main(void) { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int T = 1; while (T--) { solve(); } exit(0); } |
#include <bits/stdc++.h> using namespace std; int long long x, y, l, r, k, i, j, ans; vector<int long long> mex, mey, my; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); cin >> x >> y >> l >> r; for (k = 1; k <= 1e18 / x; k *= x) mex.push_back(k); if (k <= 1e18) mex.push_back(k); for (k = 1; k <= 1e18 / y; k *= y) mey.push_back(k); if (k <= 1e18) mey.push_back(k); for (i = 0; i < mex.size(); i++) { for (j = 0; j < mey.size(); j++) { if (mex[i] + mey[j] > r) break; if (mex[i] + mey[j] >= l) { my.push_back(mex[i] + mey[j]); } } } my.push_back(l - 1); x = l; sort(my.begin(), my.end()); my.push_back(r + 1); for (i = 1; i < my.size(); i++) { ans = max(ans, my[i] - my[i - 1] - 1); } cout << ans << endl; } |
//-----------------------------------------------------------------------------
//-- Baudrate generator
//-- It generates a square signal, with a frequency for communicating at the
//-- given baudrate
//-- The output is set to 1 only during one clock cycle. The rest of the
// time is 0
//-- Once enabled, the pulse is generated just in the middle of the period
//-- This is necessary for the implementation of the receptor
//------------------------------------------------------------------------------
//-- (c) Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`include "baudgen.vh"
//------------------------------------------------------------------------------
//-- baudgen module
//--
//-- INPUTS:
//-- -clk: System clock (12 MHZ in the iceStick board)
//-- -clk_ena: clock enable:
//-- 1. Normal working: The squeare signal is generated
//-- 0: stoped. Output always 0
//-- OUTPUTS:
//-- - clk_out: Output signal. Pulse width: 1 clock cycle.
//-- Output not registered
//-- It tells the uart_rx when to sample the next bit
//-- __ __
//-- _____| |________________________________________| |_____________________
//-- | -> <- 1 clock cycle |
//-- <------- Period ------------------------>
//--
//------------------------------------------------------------------------------
module baudgen_rx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire clk, //-- System clock
input wire clk_ena, //-- Clock enable
output wire clk_out //-- Bitrate Clock output
);
//-- Number of bits needed for storing the baudrate divisor
localparam N = $clog2(BAUDRATE);
//-- Value for generating the pulse in the middle of the period
localparam M2 = (BAUDRATE >> 1);
//-- Counter for implementing the divisor (it is a BAUDRATE module counter)
//-- (when BAUDRATE is reached, it start again from 0)
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk)
if (clk_ena)
//-- Normal working: counting. When the maximum count is reached, it starts from 0
divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
else
//-- Counter fixed to its maximum value
//-- When it is resumed it start from 0
divcounter <= BAUDRATE - 1;
//-- The output is 1 when the counter is in the middle of the period, if clk_ena is active
//-- It is 1 only for one system clock cycle
assign clk_out = (divcounter == M2) ? clk_ena : 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[110], b[110]; int main() { int n; cin >> n; for (int i = 1; i <= n; ++i) cin >> a[i]; sort(a + 1, a + 1 + n); int aa = a[n]; cin >> n; for (int i = 1; i <= n; ++i) cin >> b[i]; sort(b + 1, b + 1 + n); int bb = b[n]; cout << aa << << bb << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { const long long MOD = 1000003; int n; cin >> n; long long g = 1; for (int i = 1; i < n; i++) { g = (g * 3) % MOD; } cout << g; } |
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module ac97_transceiver(
input sys_clk,
input sys_rst,
input ac97_clk,
input ac97_rst_n,
/* to codec */
input ac97_sin,
output reg ac97_sout,
output reg ac97_sync,
/* to system, upstream */
output up_stb,
input up_ack,
output up_sync,
output up_data,
/* to system, downstream */
output down_ready,
input down_stb,
input down_sync,
input down_data
);
/* Upstream */
reg ac97_sin_r;
always @(negedge ac97_clk) ac97_sin_r <= ac97_sin;
reg ac97_syncfb_r;
always @(negedge ac97_clk) ac97_syncfb_r <= ac97_sync;
wire up_empty;
ac97_asfifo #(
.DATA_WIDTH(2),
.ADDRESS_WIDTH(6)
) up_fifo (
.Data_out({up_sync, up_data}),
.Empty_out(up_empty),
.ReadEn_in(up_ack),
.RClk(sys_clk),
.Data_in({ac97_syncfb_r, ac97_sin_r}),
.Full_out(),
.WriteEn_in(1'b1),
.WClk(~ac97_clk),
.Clear_in(sys_rst)
);
assign up_stb = ~up_empty;
/* Downstream */
/* Set SOUT and SYNC to 0 during RESET to avoid ATE/Test Mode */
wire ac97_sync_r;
always @(negedge ac97_rst_n, posedge ac97_clk) begin
if(~ac97_rst_n)
ac97_sync <= 1'b0;
else
ac97_sync <= ac97_sync_r;
end
wire ac97_sout_r;
always @(negedge ac97_rst_n, posedge ac97_clk) begin
if(~ac97_rst_n)
ac97_sout <= 1'b0;
else
ac97_sout <= ac97_sout_r;
end
wire down_full;
ac97_asfifo #(
.DATA_WIDTH(2),
.ADDRESS_WIDTH(6)
) down_fifo (
.Data_out({ac97_sync_r, ac97_sout_r}),
.Empty_out(),
.ReadEn_in(1'b1),
.RClk(ac97_clk),
.Data_in({down_sync, down_data}),
.Full_out(down_full),
.WriteEn_in(down_stb),
.WClk(sys_clk),
.Clear_in(sys_rst)
);
assign down_ready = ~down_full;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKDLYBUF4S50_1_V
`define SKY130_FD_SC_LP__CLKDLYBUF4S50_1_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog wrapper for clkdlybuf4s50 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkdlybuf4s50.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s50_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkdlybuf4s50 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkdlybuf4s50_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkdlybuf4s50 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKDLYBUF4S50_1_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int arr[N]; long long seg[N << 2], mn[N << 2], lazy[N << 2]; bool flag[N << 2]; int n, q; vector<long long> v; void push_down(int id) { if (flag[id]) { lazy[id] = lazy[((id << 1) + 1)] = lazy[((id << 1) + 2)] = 0; seg[((id << 1) + 1)] = seg[((id << 1) + 2)] = seg[id]; mn[((id << 1) + 1)] = mn[((id << 1) + 2)] = mn[id]; flag[((id << 1) + 1)] = flag[((id << 1) + 2)] = flag[id]; flag[id] = 0; } else { lazy[((id << 1) + 1)] += lazy[id]; lazy[((id << 1) + 2)] += lazy[id]; mn[((id << 1) + 1)] -= lazy[id]; mn[((id << 1) + 2)] -= lazy[id]; if (seg[((id << 1) + 1)] != -1) { seg[((id << 1) + 1)] += lazy[id]; } if (seg[((id << 1) + 2)] != -1) { seg[((id << 1) + 2)] += lazy[id]; } lazy[id] = 0; } } void push_up(int id) { mn[id] = min(mn[((id << 1) + 1)], mn[((id << 1) + 2)]); if (seg[((id << 1) + 1)] == seg[((id << 1) + 2)]) { seg[id] = seg[((id << 1) + 1)]; } else { seg[id] = -1; } } void build(int id = 0, int s = 0, int e = n) { if (s + 1 == e) { seg[id] = arr[s]; mn[id] = *upper_bound(v.begin(), v.end(), arr[s]) - arr[s]; return; } int mid = (s + e) >> 1; build(((id << 1) + 1), s, mid); build(((id << 1) + 2), mid, e); push_up(id); } void print(int id = 0, int s = 0, int e = n) { cout << [ << s + 1 << , << e << ] << id << == > << mn[id] << << seg[id] << endl; if (s + 1 == e) { return; } push_down(id); int mid = (s + e) >> 1; print(((id << 1) + 1), s, mid); print(((id << 1) + 2), mid, e); push_up(id); } long long query(int l, int r, int id = 0, int s = 0, int e = n) { if (l >= e || r <= s) return 0; if (s + 1 == e) return seg[id]; push_down(id); int mid = (s + e) >> 1; long long ret = query(l, r, ((id << 1) + 1), s, mid) + query(l, r, ((id << 1) + 2), mid, e); push_up(id); return ret; } void Set(int l, int r, int x, int id = 0, int s = 0, int e = n) { if (l >= e || r <= s) return; if (l <= s && r >= e) { seg[id] = x; flag[id] = true; mn[id] = (*lower_bound(v.begin(), v.end(), x)) - x; lazy[id] = 0; return; } push_down(id); int mid = (s + e) >> 1; Set(l, r, x, ((id << 1) + 1), s, mid); Set(l, r, x, ((id << 1) + 2), mid, e); push_up(id); } void add(int l, int r, int x, int id = 0, int s = 0, int e = n) { if (l >= e || r <= s) return; if (l <= s && r >= e) { if (seg[id] != -1) { seg[id] += x; mn[id] = (*lower_bound(v.begin(), v.end(), seg[id])) - seg[id]; flag[id] = true; lazy[id] = 0; return; } else if (mn[id] >= x) { mn[id] -= x; lazy[id] += x; return; } } push_down(id); int mid = (s + e) >> 1; add(l, r, x, ((id << 1) + 1), s, mid); add(l, r, x, ((id << 1) + 2), mid, e); push_up(id); } int main() { v.push_back(1); while (v.back() < 1e17) { v.push_back(v.back() * 42); } scanf( %d%d , &n, &q); for (int i = 0; i < n; i++) scanf( %d , &arr[i]); int type, a, b, x; build(); while (q--) { scanf( %d , &type); if (type == 1) { scanf( %d , &a); printf( %lld n , query(a - 1, a)); } else if (type == 2) { scanf( %d%d%d , &a, &b, &x); Set(a - 1, b, x); } else { scanf( %d%d%d , &a, &b, &x); do { add(a - 1, b, x); } while (mn[0] == 0); } } return 0; } |
/****************************************************************************
* Copyright (c) 2009 by Focus Robotics. All rights reserved.
*
* This program is an unpublished work fully protected by the United States
* copyright laws and is considered a trade secret belonging to the copyright
* holder. No part of this design may be reproduced stored in a retrieval
* system, or transmitted, in any form or by any means, electronic,
* mechanical, photocopying, recording, or otherwise, without prior written
* permission of Focus Robotics, Inc.
*
* Proprietary and Confidential
*
* Created By : Andrew Worcester
* Creation_Date: Tue Mar 10 2009
*
* Brief Description:
*
* Functionality:
*
* Issues:
*
* Limitations:
*
* Testing:
*
* Synthesis:
*
******************************************************************************/
module fric_client_slave
(
clk,
rst,
fric_in,
fric_out,
// FIXME: shouldn't I prepend something to these?
addr,
wdat,
wstb,
rdat
);
// In/Out declarations
input clk;
input rst;
input [7:0] fric_in;
output [7:0] fric_out;
output [7:0] addr;
output [15:0] wdat;
output wstb;
input [15:0] rdat;
// Parameters
parameter [3:0] fis_idle = 4'h0,
fis_rd_adr = 4'h1,
fis_wr_adr = 4'h2,
fis_wr_da0 = 4'h3,
fis_wr_da1 = 4'h4;
parameter [3:0] fos_idle = 4'h0,
fos_rd_ack = 4'h1,
fos_rd_adr = 4'h2,
fos_rd_da0 = 4'h3,
fos_rd_da1 = 4'h4,
fos_wr_ack = 4'h5,
fos_wr_adr = 4'h6;
// Regs and Wires
reg [3:0] fis_state, next_fis_state;
reg capt_port;
reg capt_addr;
reg capt_wdat_low;
reg capt_wdat_high;
reg wstb, wstb_pre;
reg init_rdack;
reg init_wrack;
reg [7:0] fric_inr;
reg [7:0] addr;
reg [15:0] wdat;
reg [3:0] port;
reg [3:0] fos_state, next_fos_state;
reg [2:0] fos_out_sel;
reg [7:0] fric_out;
// RTL
/****************************************************************************
* Fric In Sequencer (fis)
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
always @ (/*AS*/fis_state or fric_inr)
begin
// FSM default outputs
next_fis_state = fis_state;
capt_port = 0;
capt_addr = 0;
capt_wdat_low = 0;
capt_wdat_high = 0;
wstb_pre = 0;
init_rdack = 0;
init_wrack = 0;
case(fis_state)
fis_idle:
begin
if(fric_inr[7:4]==4'b0010) begin
capt_port = 1'b1;
next_fis_state = fis_wr_adr;
end else if(fric_inr[7:4]==4'b0011) begin
capt_port = 1'b1;
next_fis_state = fis_rd_adr;
end
end
fis_rd_adr:
begin
capt_addr = 1'b1;
init_rdack = 1'b1;
next_fis_state = fis_idle;
end
fis_wr_adr:
begin
capt_addr = 1'b1;
init_wrack = 1'b1;
next_fis_state = fis_wr_da0;
end
fis_wr_da0:
begin
capt_wdat_low = 1'b1;
next_fis_state = fis_wr_da1;
end
fis_wr_da1:
begin
capt_wdat_high = 1'b1;
wstb_pre = 1'b1;
next_fis_state = fis_idle;
end
default:
begin
end
endcase // case(fis_state)
end // always @ (...
always @ (posedge clk)
begin
if(rst==1'b1)
begin
fis_state <= fis_idle;
fric_inr <= 0;
port <= 0;
addr <= 0;
wdat <= 0;
wstb <= 0;
end
else
begin
fis_state <= next_fis_state;
fric_inr <= fric_in;
if(capt_port==1'b1)
port <= fric_inr[3:0];
if(capt_addr==1'b1)
addr <= fric_inr;
if(capt_wdat_low==1'b1)
wdat[7:0] <= fric_inr;
if(capt_wdat_high==1'b1)
wdat[15:8] <= fric_inr;
wstb <= wstb_pre;
end
end // always @ (posedge clk)
/****************************************************************************
* Fric Out Sequencer
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
always @ (/*AS*/fos_state or init_rdack or init_wrack)
begin
// FSM default outputs
next_fos_state = fos_state;
fos_out_sel = 0;
case(fos_state)
fos_idle:
begin
if(init_rdack==1'b1) begin
fos_out_sel = 2;
next_fos_state = fos_rd_adr;
end else if(init_wrack==1'b1) begin
fos_out_sel = 1;
next_fos_state = fos_wr_adr;
end
end
fos_rd_ack:
begin
end
fos_rd_adr:
begin
fos_out_sel = 3;
next_fos_state = fos_rd_da0;
end
fos_rd_da0:
begin
fos_out_sel = 4;
next_fos_state = fos_rd_da1;
end
fos_rd_da1:
begin
fos_out_sel = 5;
next_fos_state = fos_idle;
end
fos_wr_ack:
begin
end
fos_wr_adr:
begin
fos_out_sel = 3;
next_fos_state = fos_idle;
end
default:
begin
end
endcase // case(fos_state)
end // always @ (...
always @ (posedge clk)
begin
if(rst==1'b1)
begin
fos_state <= fos_idle;
fric_out <= 0;
end
else
begin
fos_state <= next_fos_state;
case(fos_out_sel)
3'h0: fric_out <= 0;
3'h1: fric_out <= {4'b0100, port};
3'h2: fric_out <= {4'b0101, port};
3'h3: fric_out <= addr;
3'h4: fric_out <= rdat[7:0];
3'h5: fric_out <= rdat[15:8];
default: fric_out <= 0;
endcase // case(fos_out_sel)
end
end // always @ (posedge clk)
/****************************************************************************
* Fric Reply Generator
*
* Inputs:
*
* Outputs:
*
* Todo/Fixme:
*
*/
endmodule // fric_client_slave
|
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 100; template <class nmsl> inline void read(nmsl &x) { x = 0; char ch = getchar(), w = 0; while (!isdigit(ch)) w = (ch == - ), ch = getchar(); while (isdigit(ch)) x = (x << 1) + (x << 3) + (ch ^ 48), ch = getchar(); x = w ? -x : x; } long long n, f[N], size[N], root[N], hd[N], bianshu, ans; struct abc { int nxt, to; } qwq[N * 2]; inline void addedg(int lai, int qu) { qwq[++bianshu].nxt = hd[lai]; qwq[bianshu].to = qu; hd[lai] = bianshu; } inline void first_dp(int u, int father) { size[u] = 1; for (register int i = hd[u]; i; i = qwq[i].nxt) { int v = qwq[i].to; if (v == father) continue; first_dp(v, u); size[u] += size[v]; f[u] += f[v]; } f[u] += size[u]; return; } inline void dp(int u, int father) { f[u] = 0; for (register int i = hd[u]; i; i = qwq[i].nxt) { int v = qwq[i].to; f[u] += f[v]; } long long tot = f[u] + n; ans = max(ans, tot); for (register int i = hd[u]; i; i = qwq[i].nxt) { int v = qwq[i].to; if (v == father) continue; size[u] = n - size[v]; f[u] = tot - f[v] - size[v]; dp(v, u); } } int main() { read(n); for (register int i = 1, qa, qb; i < n; i++) read(qa), read(qb), addedg(qa, qb), addedg(qb, qa); first_dp(1, 0); ans = f[1]; dp(1, 0); cout << ans; return 0; } |
//----------------------------------------------------------------------------
// bfm_system_tb.v - module
//----------------------------------------------------------------------------
//
// ***************************************************************************
// ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
// ** **
// ** Xilinx, Inc. **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
// ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
// ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
// ** FOR A PARTICULAR PURPOSE. **
// ** **
// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: bfm_system_tb.v
// Version: 1.00.a
// Description: Testbench logic.
// Date: Tue Jun 24 20:43:34 2014 (by Create and Import Peripheral Wizard)
// Verilog Standard: Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port: "*_i"
// device pins: "*_pin"
// ports: "- Names begin with Uppercase"
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------
`timescale 1 ns / 100 fs
//testbench defines
`define RESET_PERIOD 200
`define CLOCK_PERIOD 10
`define INIT_DELAY 400
//user slave defines
`define SLAVE_BASE_ADDR 32'h30000000
`define SLAVE_REG_OFFSET 32'h00000000
`define SLAVE_RESET_ADDR 32'h00000100
`define SLAVE_SOFT_RESET 32'h0000000A
//Response type defines
`define RESPONSE_OKAY 2'b00
//AMBA 4 defines
`define MAX_BURST_LENGTH 1
`define PROT_BUS_WIDTH 3
`define ADDR_BUS_WIDTH 32
`define RESP_BUS_WIDTH 2
module bfm_system_tb
(
); // bfm_system_tb
// -- ADD USER PARAMETERS BELOW THIS LINE ------------
// --USER parameters added here
// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_NUM_REG = 1;
parameter C_SLV_DWIDTH = 32;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------
// -- Testbench nets declartions added here, as needed for testbench logic
reg rst_n;
reg sys_clk;
integer number_of_bytes;
integer i;
integer j;
reg [C_SLV_DWIDTH-1 : 0] test_data;
reg [`ADDR_BUS_WIDTH-1 : 0] mtestAddr;
reg [`PROT_BUS_WIDTH-1 : 0] mtestProtection;
reg [C_SLV_DWIDTH-1 : 0] rd_data;
reg [`RESP_BUS_WIDTH-1 : 0] response;
//----------------------------------------------------------------------------
// Instantiate bfm_system
//----------------------------------------------------------------------------
bfm_system
dut(.sys_reset(rst_n),.sys_clk(sys_clk));
//----------------------------------------------------------------------------
// Reset block
//----------------------------------------------------------------------------
initial begin
rst_n = 1'b0;
#`RESET_PERIOD rst_n = 1'b1;
end
//----------------------------------------------------------------------------
// Simple Clock Generator
//----------------------------------------------------------------------------
initial sys_clk = 1'b0;
always #`CLOCK_PERIOD sys_clk = !sys_clk;
//----------------------------------------------------------------------------
// Simple testbench logic
//----------------------------------------------------------------------------
initial begin
//Wait for end of reset
wait(rst_n == 0) @(posedge sys_clk);
wait(rst_n == 1) @(posedge sys_clk);
#`INIT_DELAY mtestProtection = 0;
$display("----------------------------------------------------");
$display("Full Registers write followed by a full Registers read");
$display("----------------------------------------------------");
number_of_bytes = (C_SLV_DWIDTH/8);
for( i = 0 ; i <1; i = i+1) begin
for(j = 0 ; j < number_of_bytes ; j = j+1)
test_data[j*8 +: 8] = j+(i*number_of_bytes);
mtestAddr = `SLAVE_BASE_ADDR + `SLAVE_REG_OFFSET + i*number_of_bytes;
$display("Writing to Slave Register addr=0x%h",mtestAddr, " data=0x%h",test_data);
SINGLE_WRITE(mtestAddr,test_data,mtestProtection,4'b1111, response);
end
for( i = 0 ; i <1; i = i+1) begin
for(j=0 ; j < number_of_bytes ; j = j+1)
test_data[j*8 +: 8] = j+(i*number_of_bytes);
mtestAddr = `SLAVE_BASE_ADDR + `SLAVE_REG_OFFSET + i*number_of_bytes;
SINGLE_READ(mtestAddr,rd_data,mtestProtection,response);
$display("Reading from Slave Register addr=0x%h",mtestAddr, " data=0x%h",rd_data);
COMPARE_DATA(test_data,rd_data);
end
$display("----------------------------------------------------");
$display("Peripheral Verification Completed Successfully");
$display("----------------------------------------------------");
end
//----------------------------------------------------------------------------
// SINGLE_WRITE : SINGLE_WRITE(Address, Data,protection,strobe,response)
//----------------------------------------------------------------------------
task automatic SINGLE_WRITE;
input [`ADDR_BUS_WIDTH-1 : 0] address;
input [C_SLV_DWIDTH-1 : 0] data;
input [`PROT_BUS_WIDTH-1 : 0] prot;
input [3:0] strobe;
output[`RESP_BUS_WIDTH-1 : 0] response;
begin
fork
dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.SEND_WRITE_ADDRESS(address,prot);
dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.SEND_WRITE_DATA(strobe, data);
dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.RECEIVE_WRITE_RESPONSE(response);
join
CHECK_RESPONSE_OKAY(response);
end
endtask
//----------------------------------------------------------------------------
// SINGLE_READ : SINGLE_READ(Address, Data,Protection,strobe,respone)
//----------------------------------------------------------------------------
task automatic SINGLE_READ;
input [`ADDR_BUS_WIDTH-1 : 0] address;
output [C_SLV_DWIDTH-1 : 0] data;
input [`PROT_BUS_WIDTH-1 : 0] prot;
output[`RESP_BUS_WIDTH-1 : 0] response;
begin
dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.SEND_READ_ADDRESS(address,prot);
dut.bfm_processor.bfm_processor.cdn_axi4_lite_master_bfm_inst.RECEIVE_READ_DATA(data,response);
CHECK_RESPONSE_OKAY(response);
end
endtask
//----------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY(response)
//----------------------------------------------------------------------------
//Description: This task check if the return response is equal to OKAY
//----------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH FAILED! Response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h", response);
$stop;
end
end
endtask
//----------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_DATA(expected,actual)
//----------------------------------------------------------------------------
//Description: This task checks if the actual data is equal to the expected data
//----------------------------------------------------------------------
task automatic COMPARE_DATA;
input [(C_SLV_DWIDTH*(`MAX_BURST_LENGTH+1))-1:0] expected;
input [(C_SLV_DWIDTH*(`MAX_BURST_LENGTH+1))-1:0] actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH FAILED! COMPARE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
$stop;
end
if (actual !== expected) begin
$display("TESTBENCH FAILED! Data expected is not equal to actual.","\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
$stop;
end
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 4e5 + 100; const int D = 19; struct QUE { int l, r, len, id; QUE(int _l, int _r, int _len, int _id) { l = _l; r = _r; len = _len; id = _id; } }; struct OPT { int x, y; OPT(int _x, int _y) { x = _x; y = _y; } }; bool cmpx(OPT &a, OPT &b) { return a.x < b.x; } bool cmpy(OPT &a, OPT &b) { return a.x + a.y < b.x + b.y; } bool cmpl(QUE &a, QUE &b) { return a.l < b.l; } bool cmpr(QUE &a, QUE &b) { return a.r < b.r; } struct BIT { long long bit[N] = { 0, }, n; void add(int x, int v) { while (x <= n) { bit[x] += v; x += x & -x; } } long long sum(int x) { long long s = 0; while (x) { s += bit[x]; x -= x & -x; } return s; } } b1, b2; struct SAM { int next[N][26], fa[N], len[N], pos[N], n; int root, tot, last; vector<int> g[N]; vector<QUE> q[N]; vector<OPT> p[N]; long long ans[N]; int newnode(int l) { fa[tot] = -1; for (int i = 0; i < 26; ++i) next[tot][i] = -1; len[tot++] = l; return tot - 1; } void init() { tot = 0; last = root = newnode(0); } void extend(int x, int ep) { int p = last; int cur = newnode(len[p] + 1); while (p != -1 && next[p][x] == -1) { next[p][x] = cur; p = fa[p]; } if (p == -1) fa[cur] = root; else { int q = next[p][x]; if (len[q] == len[p] + 1) fa[cur] = q; else { int tmp = newnode(len[p] + 1); memcpy(next[tmp], next[q], sizeof(next[q])); fa[tmp] = fa[q]; fa[q] = fa[cur] = tmp; while (p != -1 && next[p][x] == q) { next[p][x] = tmp; p = fa[p]; } } } last = cur; pos[ep] = last; } int top[N], son[N], siz[N], par[N][D]; void dfs1(int u) { for (int i = 1; i < D; ++i) par[u][i] = par[par[u][i - 1]][i - 1]; son[u] = -1; siz[u] = 1; for (auto v : g[u]) { dfs1(v); siz[u] += siz[v]; if (son[u] == -1 || siz[v] > siz[son[u]]) son[u] = v; } } void dfs2(int u, int t) { top[u] = t; if (~son[u]) dfs2(son[u], t); for (auto v : g[u]) if (v != son[u]) dfs2(v, v); } void build() { for (int i = 0; i < tot; ++i) g[i].clear(); for (int i = 1; i < tot; ++i) g[fa[i]].push_back(i); for (int i = 0; i < tot; ++i) par[i][0] = fa[i]; for (auto v : g[0]) dfs1(v), dfs2(v, v); } int getpos(int l, int r) { r = r - l + 1; l = pos[l]; for (int i = D - 1; i >= 0; --i) if (len[par[l][i]] >= r) l = par[l][i]; return l; } void addque(int l, int r, int id) { int tp = r - l + 1, now = getpos(l, r); int up = top[now]; while (now) { q[up].push_back(QUE(l, r, min(len[now], tp) - len[fa[up]], id)); tp -= min(len[now], tp) - len[fa[up]]; now = fa[up]; up = top[now]; } } void addopt(int l) { int tp = n - l + 1, now = pos[l]; int up = top[now]; while (now) { p[up].push_back( OPT(l + len[fa[up]] + 1, min(len[now], tp) - len[fa[up]])); tp -= min(len[now], tp) - len[fa[up]]; now = fa[up]; up = top[now]; } } void solve() { memset(ans, 0, sizeof(ans)); for (int i = 1; i < tot; ++i) if (top[i] == i) { get(p[i], q[i], len[fa[i]] + 1); } } void get(vector<OPT> &p, vector<QUE> &q, int tp) { int i, j; sort(p.begin(), p.end(), cmpy); sort(q.begin(), q.end(), cmpr); for (i = 0, j = 0; i < q.size(); ++i) { while (j < p.size() && p[j].x + p[j].y <= q[i].r + 2) { b1.add(p[j].y, 1); b2.add(p[j].y, p[j].y); j++; } ans[q[i].id] += 1LL * q[i].len * (j - b1.sum(q[i].len)) + b2.sum(q[i].len); } while (j--) { b1.add(p[j].y, -1); b2.add(p[j].y, -p[j].y); } reverse(p.begin(), p.end()); reverse(q.begin(), q.end()); for (i = 0, j = 0; i < q.size(); ++i) { while (j < p.size() && p[j].x + p[j].y > q[i].r + 2) { b1.add(b1.n - p[j].x, 1); b2.add(b2.n - p[j].x, p[j].x); j++; } int c1 = b1.sum(b1.n - q[i].r - 2 + q[i].len), c2 = b1.sum(b2.n - q[i].r - 2); ans[q[i].id] += 1LL * (j - c1) * q[i].len; ans[q[i].id] += 1LL * (c1 - c2) * (q[i].r + 2) - (b2.sum(b2.n - q[i].r - 2 + q[i].len) - b2.sum(b2.n - q[i].r - 2)); } while (j--) { b1.add(b1.n - p[j].x, -1); b2.add(b2.n - p[j].x, -p[j].x); } for (i = 0; i < p.size(); ++i) p[i].x -= tp; sort(p.begin(), p.end(), cmpx); sort(q.begin(), q.end(), cmpl); for (i = 0, j = 0; i < q.size(); ++i) { while (j < p.size() && p[j].x < q[i].l) { b1.add(p[j].y, 1); b2.add(p[j].y, p[j].y); j++; } ans[q[i].id] -= 1LL * (j - b1.sum(q[i].len)) * q[i].len + b2.sum(q[i].len); } while (j--) { b1.add(p[j].y, -1); b2.add(p[j].y, -p[j].y); } } } sam; char s[N]; int n, m; int l[N], r[N]; int main() { scanf( %s , s + 1); n = strlen(s + 1); sam.init(); for (int i = n; i >= 1; --i) sam.extend(s[i] - a , i); sam.build(); b1.n = b2.n = 2 * n + 2; sam.n = n; for (int i = 1; i <= n; ++i) sam.addopt(i); scanf( %d , &m); for (int i = 1; i <= m; ++i) { scanf( %d %d , &l[i], &r[i]); sam.addque(l[i], r[i], i); } sam.solve(); for (int i = 1; i <= m; ++i) printf( %lld n , sam.ans[i]); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DECAP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DECAP_PP_SYMBOL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__decap (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DECAP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long double PI = 4 * atan((long double)1); const long long INF = 1e18; const long long NINF = -1e18; long long get_hash(string s) { long long N = 1000001; long long base[N], A = 11, MD = 1110111110111; base[0] = 1; for (long long i = (1); i < (N); ++i) base[i] = (base[i - 1] * A) % MD; long long hs = 0; for (long long i = (0); i < (s.size()); ++i) { hs += (s[i] * base[i]); hs %= MD; } return hs; } long long power(long long a, long long n) { long long res = 1; while (n) { if (n % 2) res *= a; a *= a; n /= 2; } return res; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long n; cin >> n; long long k = 1, m = 2; while (k != n + 1) { long long p = (k + 1) * k; long long u = k + 1; long long v = (k + 1) * (k + 1) * k; cout << v - (m) / k << n ; m = p; k++; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int kMaxN = 1000005; int aib[2 * kMaxN]; int x[kMaxN], poz[kMaxN]; int el[2 * kMaxN]; bool first[kMaxN]; void aib_update(int ind, int val) { while (ind < 2 * kMaxN) { aib[ind] += val; ind += ind & (-ind); } return; } int aib_search(int val) { int p = 20; int rez = 0; for (; p >= 0; --p) if ((1 << p) + rez < 2 * kMaxN) if (aib[(1 << p) + rez] < val) { val -= aib[(1 << p) + rez]; rez += (1 << p); } return rez + 1; } int main() { int n, m; ios_base::sync_with_stdio(false); cin >> n >> m; for (int i = 1; i <= m; ++i) cin >> x[i] >> poz[i]; int st = m + 2; for (int i = st; i < st + n; ++i) { el[i] = 0; aib_update(i, +1); } bool ok = true; for (int i = 1; i <= m and ok; ++i) { st--; int p = aib_search(poz[i]); if (first[x[i]] == false) { if (el[p] != false) ok = false; el[p] = x[i]; first[x[i]] = true; el[st] = x[i]; aib_update(p, -1); aib_update(st, +1); } else { if (el[p] != x[i]) ok = false; aib_update(p, -1); aib_update(st, +1); el[st] = x[i]; } } if (not ok) cout << -1 n ; else { int st = m + 2; int dr = 1; for (int i = st; i < st + n; ++i) if (el[i] == 0) { while (first[dr] != 0) ++dr; cout << dr << ; ++dr; } else { cout << el[i] << ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename A, typename B> string to_string(pair<A, B> p); template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p); template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p); string to_string(const string& s) { return + s + ; } string to_string(const char* s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } string to_string(vector<bool> v) { bool first = true; string res = { ; for (int i = 0; i < static_cast<int>(v.size()); i++) { if (!first) { res += , ; } first = false; res += to_string(v[i]); } res += } ; return res; } template <size_t N> string to_string(bitset<N> v) { string res = ; for (size_t i = 0; i < N; i++) { res += static_cast<char>( 0 + v[i]); } return res; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto& x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A, typename B, typename C> string to_string(tuple<A, B, C> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + ) ; } template <typename A, typename B, typename C, typename D> string to_string(tuple<A, B, C, D> p) { return ( + to_string(get<0>(p)) + , + to_string(get<1>(p)) + , + to_string(get<2>(p)) + , + to_string(get<3>(p)) + ) ; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } template <typename T> T inverse(T a, T m) { T u = 0, v = 1; while (a != 0) { T t = m / a; m -= t * a; swap(a, m); u -= t * v; swap(u, v); } assert(m == 1); return u; } template <typename T> class Modular { public: using Type = typename decay<decltype(T::value)>::type; constexpr Modular() : value() {} template <typename U> Modular(const U& x) { value = normalize(x); } template <typename U> static Type normalize(const U& x) { Type v; if (-mod() <= x && x < mod()) v = static_cast<Type>(x); else v = static_cast<Type>(x % mod()); if (v < 0) v += mod(); return v; } const Type& operator()() const { return value; } template <typename U> explicit operator U() const { return static_cast<U>(value); } constexpr static Type mod() { return T::value; } Modular& operator+=(const Modular& other) { if ((value += other.value) >= mod()) value -= mod(); return *this; } Modular& operator-=(const Modular& other) { if ((value -= other.value) < 0) value += mod(); return *this; } template <typename U> Modular& operator+=(const U& other) { return *this += Modular(other); } template <typename U> Modular& operator-=(const U& other) { return *this -= Modular(other); } Modular& operator++() { return *this += 1; } Modular& operator--() { return *this -= 1; } Modular operator++(int) { Modular result(*this); *this += 1; return result; } Modular operator--(int) { Modular result(*this); *this -= 1; return result; } Modular operator-() const { return Modular(-value); } template <typename U = T> typename enable_if<is_same<typename Modular<U>::Type, int>::value, Modular>::type& operator*=(const Modular& rhs) { value = normalize(static_cast<int64_t>(value) * static_cast<int64_t>(rhs.value)); return *this; } template <typename U = T> typename enable_if<is_same<typename Modular<U>::Type, int64_t>::value, Modular>::type& operator*=(const Modular& rhs) { int64_t q = static_cast<int64_t>(static_cast<long double>(value) * rhs.value / mod()); value = normalize(value * rhs.value - q * mod()); return *this; } template <typename U = T> typename enable_if<!is_integral<typename Modular<U>::Type>::value, Modular>::type& operator*=(const Modular& rhs) { value = normalize(value * rhs.value); return *this; } Modular& operator/=(const Modular& other) { return *this *= Modular(inverse(other.value, mod())); } template <typename U> friend const Modular<U>& abs(const Modular<U>& v) { return v; } template <typename U> friend bool operator==(const Modular<U>& lhs, const Modular<U>& rhs); template <typename U> friend bool operator<(const Modular<U>& lhs, const Modular<U>& rhs); template <typename U> friend std::istream& operator>>(std::istream& stream, Modular<U>& number); private: Type value; }; template <typename T> bool operator==(const Modular<T>& lhs, const Modular<T>& rhs) { return lhs.value == rhs.value; } template <typename T, typename U> bool operator==(const Modular<T>& lhs, U rhs) { return lhs == Modular<T>(rhs); } template <typename T, typename U> bool operator==(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) == rhs; } template <typename T> bool operator!=(const Modular<T>& lhs, const Modular<T>& rhs) { return !(lhs == rhs); } template <typename T, typename U> bool operator!=(const Modular<T>& lhs, U rhs) { return !(lhs == rhs); } template <typename T, typename U> bool operator!=(U lhs, const Modular<T>& rhs) { return !(lhs == rhs); } template <typename T> bool operator<(const Modular<T>& lhs, const Modular<T>& rhs) { return lhs.value < rhs.value; } template <typename T> Modular<T> operator+(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) += rhs; } template <typename T, typename U> Modular<T> operator+(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) += rhs; } template <typename T, typename U> Modular<T> operator+(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) += rhs; } template <typename T> Modular<T> operator-(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) -= rhs; } template <typename T, typename U> Modular<T> operator-(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) -= rhs; } template <typename T, typename U> Modular<T> operator-(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) -= rhs; } template <typename T> Modular<T> operator*(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) *= rhs; } template <typename T, typename U> Modular<T> operator*(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) *= rhs; } template <typename T, typename U> Modular<T> operator*(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) *= rhs; } template <typename T> Modular<T> operator/(const Modular<T>& lhs, const Modular<T>& rhs) { return Modular<T>(lhs) /= rhs; } template <typename T, typename U> Modular<T> operator/(const Modular<T>& lhs, U rhs) { return Modular<T>(lhs) /= rhs; } template <typename T, typename U> Modular<T> operator/(U lhs, const Modular<T>& rhs) { return Modular<T>(lhs) /= rhs; } template <typename T, typename U> Modular<T> power(const Modular<T>& a, const U& b) { assert(b >= 0); Modular<T> x = a, res = 1; U p = b; while (p > 0) { if (p & 1) res *= x; x *= x; p >>= 1; } return res; } template <typename T> bool IsZero(const Modular<T>& number) { return number() == 0; } template <typename T> string to_string(const Modular<T>& number) { return to_string(number()); } template <typename T> std::ostream& operator<<(std::ostream& stream, const Modular<T>& number) { return stream << number(); } template <typename T> std::istream& operator>>(std::istream& stream, Modular<T>& number) { typename common_type<typename Modular<T>::Type, int64_t>::type x; stream >> x; number.value = Modular<T>::normalize(x); return stream; } constexpr int md = (int)1e9 + 7; using Mint = Modular<std::integral_constant<decay<decltype(md)>::type, md>>; vector<Mint> fact(1, 1); vector<Mint> inv_fact(1, 1); Mint C(int n, int k) { if (k < 0 || k > n) { return 0; } while ((int)fact.size() < n + 1) { fact.push_back(fact.back() * (int)fact.size()); inv_fact.push_back(1 / fact.back()); } return fact[n] * inv_fact[k] * inv_fact[n - k]; } struct Point { int x; int y; int c; }; int main() { ios::sync_with_stdio(false); cin.tie(0); int n, k, L; cin >> n >> k >> L; vector<Point> p(n); for (int i = 0; i < n; i++) { cin >> p[i].x >> p[i].y >> p[i].c; --p[i].c; } sort(p.begin(), p.end(), [&](const Point& a, const Point& b) { return a.y < b.y; }); Mint c2 = Mint(L) * (L + 1) / 2; auto C2 = [&](int x, int y) -> long long { if (x >= y) { return 0; } return ((long long)(y - x) * (y - x + 1)) >> 1; }; Mint ans = 0; for (int start = 0; start <= n - k; start++) { int coeff = p[start].y - (start == 0 ? -1 : p[start - 1].y); if (coeff == 0) { continue; } vector<multiset<int>> s(k); for (int i = 0; i < k; i++) { s[i].insert(-1); s[i].insert(L); } for (int i = start; i < n; i++) { s[p[i].c].insert(p[i].x); } set<pair<int, int>> segs; long long value = 0; auto Modify = [&](set<pair<int, int>>::iterator it, int q) { if (it != segs.begin()) { value -= q * C2(it->first, abs(prev(it)->second)); } if (next(it) != segs.end()) { value -= q * C2(next(it)->first, abs(it->second)); } if (it != segs.begin() && next(it) != segs.end()) { value += q * C2(next(it)->first, abs(prev(it)->second)); } value += q * C2(it->first, abs(it->second)); }; auto Erase = [&](set<pair<int, int>>::iterator it) { Modify(it, -1); segs.erase(it); }; auto Add = [&](int from, int to) { if (from >= to) { return; } pair<int, int> seg = make_pair(from, -to); auto it = segs.lower_bound(seg); while (it != segs.end() && abs(it->second) <= to) { Erase(it); it = segs.lower_bound(seg); } if (it != segs.begin()) { it = prev(it); if (abs(it->second) >= to) { return; } } auto ret = segs.insert(seg); assert(ret.second); it = ret.first; Modify(it, 1); }; bool have_all = true; for (int i = 0; i < k; i++) { if (s[i].size() == 2) { have_all = false; break; } auto it = s[i].begin(); while (*it < L) { int me = *it; ++it; int nxt = *it; Add(me + 1, nxt); } } if (!have_all) { break; } for (int finish = n - 1; finish >= start; finish--) { int coeff2 = (finish == n - 1 ? L : p[finish + 1].y) - p[finish].y; ans += Mint(coeff) * coeff2 * (c2 - value); int col = p[finish].c; auto it = s[col].find(p[finish].x); assert(it != s[col].end()); auto pr = prev(it); auto nx = next(it); Add((*pr) + 1, *nx); s[col].erase(it); if (value == c2) { break; } } } cout << ans << n ; return 0; } |
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( avx,avx2,fma ) using namespace std; const int N = 207; const int K = 1007; const long long mod = 1e9 + 7; long long dp[2][N][K]; long long a[N]; int n, k; int main() { cin >> n >> k; for (int i = 1; i <= n; i++) scanf( %lld , &a[i]); dp[0][0][0] = 1; sort(a + 1, a + n + 1); int cur = 0, prv = 0; for (int i = 1; i <= n; i++) { int d = a[i] - a[i - 1]; prv = cur; cur ^= 1; for (int j = 0; j <= i; j++) { for (int c = 0; c <= k; c++) { dp[cur][j][c] = 0; if (j && c - (j - 1) * d >= 0) dp[cur][j][c] += dp[prv][j - 1][c - (j - 1) * d]; if (c - (j + 1) * d >= 0) dp[cur][j][c] += dp[prv][j + 1][c - (j + 1) * d] * (j + 1); if (c - j * d >= 0) dp[cur][j][c] += dp[prv][j][c - j * d] * (j + 1); dp[cur][j][c] %= mod; } } } long long ans = 0; for (int c = 0; c <= k; c++) ans += dp[cur][0][c]; cout << ans % mod; } |
#include <bits/stdc++.h> using namespace std; int N, K; string s; bool dp[1010][1010]; bool dfs(int i, int j) { if (i == N && abs(j) == K) return true; if (i != N && abs(j) == K) return false; if (i == N && abs(j) != K) return false; if (dp[i][j] == 1) return false; dp[i][j] = 1; if (s[i] == W ) return dfs(i + 1, j + 1); if (s[i] == L ) return dfs(i + 1, j - 1); if (s[i] == D ) return dfs(i + 1, j); if (dfs(i + 1, j + 1) == true) { s[i] = W ; return 1; } if (dfs(i + 1, j) == true) { s[i] = D ; return 1; } if (dfs(i + 1, j - 1) == true) { s[i] = L ; return 1; } return 0; } int main() { ios::sync_with_stdio(false); cin >> N >> K; cin >> s; if (dfs(0, 0) == true) cout << s << endl; else cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 500; const int LN = 21; const long long mod = 1e9 + 7; const long long INF = 1LL << 57; long long n, m, u, v, k, t, q, a, x, d; int tree[4 * N]; int sum[4 * N]; int lim = 1e6 + 2; int arr[N], brr[N]; bool print = false; void modify(int i, int l, int r, int index, int val) { if (l == r) { tree[i] += val; sum[i] = tree[i]; return; } int mid = (l + r) / 2; if (index <= mid) modify(i + 1 + i, l, mid, index, val); else modify(i + 2 + i, mid + 1, r, index, val); tree[i] = max(tree[i + 2 + i], tree[i + 1 + i] + sum[i + 2 + i]); sum[i] = sum[i + 1 + i] + sum[i + 2 + i]; } int find(int i, int l, int r, int sumx) { if (l == r) return l; int mid = (l + r) / 2; if (tree[i + 2 + i] + sumx > 0) { return find(i + 2 + i, mid + 1, r, sumx); } else return find(i + 1 + i, l, mid, sumx + sum[i + 2 + i]); } int main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n >> m; for (int i = 1; i <= n; ++i) { cin >> arr[i]; } for (int i = 1; i <= m; ++i) cin >> brr[i]; for (int i = 1; i <= n; ++i) { modify(0, 0, lim, arr[i], 1); } for (int i = 1; i <= m; ++i) { modify(0, 0, lim, brr[i], -1); } cin >> q; while (q--) { int type; cin >> type; if (type == 1) { int i, x; cin >> i >> x; modify(0, 0, lim, arr[i], -1); modify(0, 0, lim, x, 1); arr[i] = x; int price = find(0, 0, lim, 0); if (price == 0) cout << -1 << n ; else cout << price << n ; } else { int i, x; cin >> i >> x; modify(0, 0, lim, brr[i], 1); modify(0, 0, lim, x, -1); brr[i] = x; int price = find(0, 0, lim, 0); if (price == 0) cout << -1 << n ; else cout << price << n ; } } } |
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a buffer that can be used the transfer streaming data from *
* one clock domain to another. *
* *
******************************************************************************/
module soc_system_vga_dual_clock_FIFO (
// Inputs
clk_stream_in,
reset_stream_in,
clk_stream_out,
reset_stream_out,
stream_in_data,
stream_in_startofpacket,
stream_in_endofpacket,
stream_in_empty,
stream_in_valid,
stream_out_ready,
// Bi-Directional
// Outputs
stream_in_ready,
stream_out_data,
stream_out_startofpacket,
stream_out_endofpacket,
stream_out_empty,
stream_out_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 29; // Frame's data width
parameter EW = 1; // Frame's empty width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk_stream_in;
input reset_stream_in;
input clk_stream_out;
input reset_stream_out;
input [DW: 0] stream_in_data;
input stream_in_startofpacket;
input stream_in_endofpacket;
input [EW: 0] stream_in_empty;
input stream_in_valid;
input stream_out_ready;
// Bi-Directional
// Outputs
output stream_in_ready;
output [DW: 0] stream_out_data;
output stream_out_startofpacket;
output stream_out_endofpacket;
output [EW: 0] stream_out_empty;
output stream_out_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [ 6: 0] fifo_wr_used;
wire fifo_empty;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output assignments
assign stream_in_ready = ~(&(fifo_wr_used[6:4]));
assign stream_out_empty = 'h0;
assign stream_out_valid = ~fifo_empty;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
dcfifo Data_FIFO (
// Inputs
.wrclk (clk_stream_in),
.wrreq (stream_in_ready & stream_in_valid),
.data ({stream_in_data, stream_in_endofpacket, stream_in_startofpacket}),
.rdclk (clk_stream_out),
.rdreq (stream_out_ready & ~fifo_empty),
// Outputs
.wrusedw (fifo_wr_used),
.rdempty (fifo_empty),
.q ({stream_out_data, stream_out_endofpacket, stream_out_startofpacket})
// synopsys translate_off
,
.aclr (),
.wrfull (),
.wrempty (),
.rdfull (),
.rdusedw ()
// synopsys translate_on
);
defparam
Data_FIFO.intended_device_family = "Cyclone II",
Data_FIFO.lpm_hint = "MAXIMIZE_SPEED=7",
Data_FIFO.lpm_numwords = 128,
Data_FIFO.lpm_showahead = "ON",
Data_FIFO.lpm_type = "dcfifo",
Data_FIFO.lpm_width = DW + 3,
Data_FIFO.lpm_widthu = 7,
Data_FIFO.overflow_checking = "OFF",
Data_FIFO.rdsync_delaypipe = 5,
Data_FIFO.underflow_checking = "OFF",
Data_FIFO.use_eab = "ON",
Data_FIFO.wrsync_delaypipe = 5;
endmodule
|
#include <bits/stdc++.h> const int maxn = 1e5 + 100; const double eps = 1e-7; const int INF = 1e9; using namespace std; bool f[maxn]; int a[maxn]; struct Node { int i, num; bool operator<(const Node &rhs) const { return i < rhs.i || (i == rhs.i && num < rhs.num); } }; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { f[i] = true; a[i] = i; } set<Node> S1, S2; set<Node>::iterator it, it1; int cnt = n; char key[10]; int id; for (int i = 1; i <= m; i++) { scanf( %s %d , key, &id); if (key[0] == + ) { int d = S2.erase((Node){a[id], id}); if (S2.size() && d == 0) f[id] = false; if (S1.size()) f[id] = false; a[id] = ++cnt; S1.insert((Node){a[id], id}); for (it = S2.begin(); it != S2.end(); it++) { f[it->num] = false; } S2.clear(); } else { it1 = it = S1.upper_bound((Node){a[id], id}); if (it != S1.end()) { f[id] = false; f[it->num] = false; } S1.erase((Node){a[id], id}); for (it = S2.begin(); it != S2.end(); it++) { f[it->num] = false; } S2.clear(); S2.insert((Node){a[id], id}); } } int num = 0; for (int i = 1; i <= n; i++) if (f[i]) num++; cout << num << endl; for (int i = 1; i <= n; i++) if (f[i]) cout << i << ; cout << endl; } |
#include <bits/stdc++.h> using namespace std; const int inf = 1e5 + 9; int n; int mp[9]; bool done[109]; vector<pair<long long, pair<long long, long long> > > v[109]; void dfs(int node) { done[node] = 1; for (int i = 0; i < v[node].size(); i++) { int u = v[node][i].first; int e = v[node][i].second.first; int f = v[node][i].second.second; if (done[u]) continue; mp[f] += e, dfs(u); } } int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0), cin >> n; for (int i = 0; i < n; i++) { int a, b, c; cin >> a >> b >> c; a--; b--; v[a].push_back({b, {c, 1}}); v[b].push_back({a, {c, 0}}); } dfs(0); mp[1 - v[0][1].second.second] += v[0][1].second.first; cout << min(mp[1], mp[0]) << endl; } |
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( -ffloat-store ) #pragma GCC optimize( -fno-defer-pop ) long long int power(long long int a, long long int b, long long int m) { if (b == 0) return 1; if (b == 1) return a % m; long long int t = power(a, b / 2, m) % m; t = (t * t) % m; if (b & 1) t = ((t % m) * (a % m)) % m; return t; } long long int modInverse(long long int a, long long int m) { return power(a, m - 2, m); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int q; cin >> q; while (q--) { long long int i, j, k, l, n; cin >> n >> k; long long int ar[n + 1]; for (i = 1; i <= n; i++) { cin >> ar[i]; } vector<long long int> an; long long int s = 0; for (i = 1; i <= n; i++) { s += ar[i]; if (s % 2) { an.push_back(i); s = 0; } else if (i == n) { if (an.size() > 0) { an.pop_back(); an.push_back(i); } } } if (an.size() < k) { cout << NO << n ; } else { long long int v = (an.size() - k); if (v % 2 == 0) { cout << YES << n ; i = v; while (i < an.size()) { cout << an[i] << ; i++; } cout << n ; } else { cout << NO << n ; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 5 * 1000000 + 100; char str[maxn << 1], s[maxn]; int p[maxn << 1]; int ans; int n; int f[maxn << 1]; void Init(void) { str[0] = $ , str[1] = # ; for (int i = 0; i < n; i++) { str[i * 2 + 2] = s[i]; str[i * 2 + 3] = # ; } int nn = 2 * n + 2; str[nn] = 0; int mx = 0, id; for (int i = 1; i < nn; i++) { if (mx > i) { p[i] = min(p[2 * id - i], mx - i); } else p[i] = 1; while (str[i + p[i]] == str[i - p[i]]) p[i]++; if (i + p[i] > mx) mx = i + p[i], id = i; } } void solve(void) { long long ans = 0; for (int i = 1; i <= n; i++) { int l = 2, r = 2 * i; int m = (l + r) >> 1; if (p[m] * 2 - 1 >= r - l + 1) f[r] = f[m - 1 + ((m % 2) ? 0 : -1)] + 1; ans += f[r]; } printf( %I64d n , ans); } int main(void) { scanf( %s , s); n = strlen(s); Init(); solve(); return 0; } |
/*
* NAME
*
* cpu_tb.v - generic cpu test bench
*
* DESCRIPTION
*
* This generic cpu test bench can be used to run a program, which is in
* ASCII hex format, and output the results.
*
* Configuration is done by setting preprocessor defines at compile
* time. The result is an executable for that specific test.
*
* iverilog -DIM_DATA_FILE="\"t0001-no_hazard.hex\"" \
* -DNUM_IM_DATA=`wc -l t0001-no_hazard.hex | awk {'print $$1'}` \
* -DDUMP_FILE="\"t0001-no_hazard.vcd\"" \
* -I../ -g2005 \
* -o t0001-no_hazard \
* cpu_tb.v
*
* Then it can be run in the usual manner. $monitor variables will be
* output to STDOUT and a .vcd for use with Gtkwave will be output to
* 'DUMP_FILE'.
*
* ./t0001-no_hazard > t0001-no_hazard.out
*/
//`include "cpu.v"
module cpu_tb;
integer i = 0;
reg clk;
cpu #(.NMEM(12))
mips1(.clk(clk));
always begin
clk <= ~clk;
#5;
end
initial begin
// $dumpfile(`DUMP_FILE);
// $dumpvars(0, cpu_tb);
clk <= 1'b0;
/* cpu will $display output when `DEBUG_CPU_STAGES is on */
// Run all the lines, plus 5 extra to finish off the pipeline.
for (i = 0; i < 12 + 5; i = i + 1) begin
@(posedge clk);
end
$finish;
end
endmodule
|
// ----------------------------------------------------------------------
// HLS HDL: Verilog Netlister
// HLS Version: 2011a.126 Production Release
// HLS Date: Wed Aug 8 00:52:07 PDT 2012
//
// Generated by: fyq14@EEWS104A-002
// Generated date: Tue Mar 03 15:18:42 2015
// ----------------------------------------------------------------------
//
// ------------------------------------------------------------------
// Design Unit: dot_product_core
// ------------------------------------------------------------------
module dot_product_core (
clk, en, arst_n, input_a_rsc_mgc_in_wire_d, input_b_rsc_mgc_in_wire_d, output_rsc_mgc_out_stdreg_d
);
input clk;
input en;
input arst_n;
input [7:0] input_a_rsc_mgc_in_wire_d;
input [7:0] input_b_rsc_mgc_in_wire_d;
output [7:0] output_rsc_mgc_out_stdreg_d;
reg [7:0] output_rsc_mgc_out_stdreg_d;
// Interconnect Declarations for Component Instantiations
always @(*)
begin : core
// Interconnect Declarations
reg exit_MAC_lpi;
reg [7:0] acc_sva_1;
reg [2:0] i_1_sva_1;
reg exit_MAC_sva;
begin : mainExit
forever begin : main
// C-Step 0 of Loop 'main'
begin : waitLoop0Exit
forever begin : waitLoop0
@(posedge clk or negedge ( arst_n ));
if ( ~ arst_n )
disable mainExit;
if ( en )
disable waitLoop0Exit;
end
end
// C-Step 1 of Loop 'main'
acc_sva_1 = (acc_sva_1 & (signext_8_1(~ exit_MAC_lpi))) + conv_s2s_16_8(input_a_rsc_mgc_in_wire_d
* input_b_rsc_mgc_in_wire_d);
i_1_sva_1 = (i_1_sva_1 & (signext_3_1(~ exit_MAC_lpi))) + 3'b1;
exit_MAC_sva = ~ (readslicef_4_1_3((conv_u2s_3_4(i_1_sva_1) + 4'b1011)));
if ( exit_MAC_sva ) begin
output_rsc_mgc_out_stdreg_d <= acc_sva_1;
end
exit_MAC_lpi = exit_MAC_sva;
end
end
exit_MAC_sva = 1'b0;
i_1_sva_1 = 3'b0;
acc_sva_1 = 8'b0;
exit_MAC_lpi = 1'b0;
output_rsc_mgc_out_stdreg_d <= 8'b0;
exit_MAC_lpi = 1'b1;
end
function [7:0] signext_8_1;
input [0:0] vector;
begin
signext_8_1= {{7{vector[0]}}, vector};
end
endfunction
function [2:0] signext_3_1;
input [0:0] vector;
begin
signext_3_1= {{2{vector[0]}}, vector};
end
endfunction
function [0:0] readslicef_4_1_3;
input [3:0] vector;
reg [3:0] tmp;
begin
tmp = vector >> 3;
readslicef_4_1_3 = tmp[0:0];
end
endfunction
function signed [7:0] conv_s2s_16_8 ;
input signed [15:0] vector ;
begin
conv_s2s_16_8 = vector[7:0];
end
endfunction
function signed [3:0] conv_u2s_3_4 ;
input [2:0] vector ;
begin
conv_u2s_3_4 = {1'b0, vector};
end
endfunction
endmodule
// ------------------------------------------------------------------
// Design Unit: dot_product
// Generated from file(s):
// 3) //icnas3.cc.ic.ac.uk/fyq14/student_files_2015/student_files_2015/prj1/dot_product_source/dot_product.cpp
// ------------------------------------------------------------------
module dot_product (
input_a_rsc_z, input_b_rsc_z, output_rsc_z, clk, en, arst_n
);
input [7:0] input_a_rsc_z;
input [7:0] input_b_rsc_z;
output [7:0] output_rsc_z;
input clk;
input en;
input arst_n;
// Interconnect Declarations
wire [7:0] input_a_rsc_mgc_in_wire_d;
wire [7:0] input_b_rsc_mgc_in_wire_d;
wire [7:0] output_rsc_mgc_out_stdreg_d;
// Interconnect Declarations for Component Instantiations
mgc_in_wire #(.rscid(1),
.width(8)) input_a_rsc_mgc_in_wire (
.d(input_a_rsc_mgc_in_wire_d),
.z(input_a_rsc_z)
);
mgc_in_wire #(.rscid(2),
.width(8)) input_b_rsc_mgc_in_wire (
.d(input_b_rsc_mgc_in_wire_d),
.z(input_b_rsc_z)
);
mgc_out_stdreg #(.rscid(3),
.width(8)) output_rsc_mgc_out_stdreg (
.d(output_rsc_mgc_out_stdreg_d),
.z(output_rsc_z)
);
dot_product_core dot_product_core_inst (
.clk(clk),
.en(en),
.arst_n(arst_n),
.input_a_rsc_mgc_in_wire_d(input_a_rsc_mgc_in_wire_d),
.input_b_rsc_mgc_in_wire_d(input_b_rsc_mgc_in_wire_d),
.output_rsc_mgc_out_stdreg_d(output_rsc_mgc_out_stdreg_d)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, zz; string s; int a[28]; int main(void) { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int ntest; cin >> ntest; while (ntest--) { cin >> n >> m >> zz >> s; for (int i = 0; i < 28; ++i) a[i] = 0; for (int i = 0; i < s.size(); ++i) ++a[s[i] - A ]; int ans = 1e9; for (int i = 0; i < 27; ++i) { vector<bool> can(zz - a[i] + 1, 0); can[0] = 1; for (int j = 0; j < 26; ++j) if (j != i) { for (int k = zz - a[i]; k >= 0; --k) if (can[k]) can[k + a[j]] = 1; } for (int j = 0; j <= zz - a[i]; ++j) if (can[j]) { int need_n = max(0, n - j); int need_m = max(0, m - (zz - a[i] - j)); if (need_n + need_m > a[i]) continue; ans = min(ans, need_n * need_m); } } cout << ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long double EPS = 1e-9; const long double PI = 3.141592653589793238462643383279502884197; const int MOD = 666013; const int NMax = 350000; int N, C, D; int lastIndexForSearch; long long ans = 0LL; struct Punct; long long diferente[NMax], diferentePartiale[NMax]; long long sqr(const long long &x); long long Determinant(const Punct &A, const Punct &B, const Punct &C); long long Dist2(const Punct &A, const Punct &B); long double GetAngle(const Punct &A); int GetCadran(const Punct &A); long long CompareUnghiPolar(const Punct &A, const Punct &B); struct Punct { int x, y; Punct() { this->x = 0; this->y = 0; } Punct(const int x, const int y) { this->x = x; this->y = y; } inline bool operator<(const Punct &other) const { long long s = CompareUnghiPolar(*this, other); if (s == 0) return Dist2(Punct(0, 0), *this) < Dist2(Punct(0, 0), other); return s == -1; } }; Punct a[NMax]; enum InsertType { InsertCoord, InsertCntStrict, InsertCntNestrict, InsertIndexNestrict }; enum QueryType { QueryCoord, QueryCntStrict, QueryCntNestrict, QueryIndexNestrict }; struct HashNode { int x, y, indexNestrict; long long cntStrict, cntNestrict; HashNode() { x = y = indexNestrict = 0; cntStrict = cntNestrict = 0LL; } HashNode(const int &x, const int &y, const int &indexNestrict, const long long &cntStrict, const long long &cntNestrict) { this->x = x; this->y = y; this->indexNestrict = indexNestrict; this->cntStrict = cntStrict; this->cntNestrict = cntNestrict; } }; vector<HashNode> H[MOD]; struct CntEvidence { int x, y; long long cnt; CntEvidence() { x = y = 0; cnt = 0LL; } CntEvidence(const int &x, const int &y, const long long &cnt) { this->x = x; this->y = y; this->cnt = cnt; } inline bool operator<(const CntEvidence &other) const { long long s = CompareUnghiPolar(Punct(this->x, this->y), Punct(other.x, other.y)); if (s == 0) return Dist2(Punct(0, 0), Punct(this->x, this->y)) < Dist2(Punct(0, 0), Punct(other.x, other.y)); return s == -1; } }; CntEvidence maiMiciStrictVector[NMax]; CntEvidence maiMiciStrictVectorSumePartiale[NMax]; CntEvidence maiMiciSauEgaleVector[NMax]; CntEvidence maiMiciSauEgaleVectorSumePartiale[NMax]; int NmaiMiciStrictVector; int NmaiMiciSauEgaleVector; int gcd(int x, int y) { int r; while (y) { r = x % y; x = y; y = r; } return x; } void Insert(const int &x, const int &y, InsertType type, long long param = 0) { int codh = (abs(x) + abs(y)) % MOD; if (type == InsertCoord) { for (vector<HashNode>::iterator it = H[codh].begin(); it != H[codh].end(); ++it) { if (it->x == x && it->y == y) return; } H[codh].push_back(HashNode(x, y, 0, 0, 0)); return; } else if (type == InsertCntStrict) { for (vector<HashNode>::iterator it = H[codh].begin(); it != H[codh].end(); ++it) { if (it->x == x && it->y == y) { it->cntStrict = param; return; } } H[codh].push_back(HashNode(x, y, 0, param, 0)); return; } else if (type == InsertCntNestrict) { for (vector<HashNode>::iterator it = H[codh].begin(); it != H[codh].end(); ++it) { if (it->x == x && it->y == y) { it->cntNestrict = param; return; } } H[codh].push_back(HashNode(x, y, 0, 0, param)); return; } else if (type == InsertIndexNestrict) { for (vector<HashNode>::iterator it = H[codh].begin(); it != H[codh].end(); ++it) { if (it->x == x && it->y == y) { it->indexNestrict = param; return; } } H[codh].push_back(HashNode(x, y, param, 0, 0)); return; } } void FindMaiMiciStrict(int x, int y) { int st = 1, dr = lastIndexForSearch; int ret = 0; while (st <= dr) { int mij = (st + dr) / 2; if (CompareUnghiPolar(a[mij], Punct(x, y)) < 0) { ret = mij; st = mij + 1; } else dr = mij - 1; } Insert(x, y, InsertCntStrict, ret); maiMiciStrictVector[++NmaiMiciStrictVector] = CntEvidence(x, y, ret); } void FindMaiMiciSauEgale(int x, int y) { int st = 1, dr = lastIndexForSearch; int ret = 0; while (st <= dr) { int mij = (st + dr) / 2; if (CompareUnghiPolar(a[mij], Punct(x, y)) <= 0) { ret = mij; st = mij + 1; } else dr = mij - 1; } Insert(x, y, InsertCntNestrict, ret); maiMiciSauEgaleVector[++NmaiMiciSauEgaleVector] = CntEvidence(x, y, ret); } long long QueryHash(int x, int y, QueryType type) { x = -x; y = -y; if (y == 0) { if (x < 0) x = -1; else if (x > 0) x = 1; } else if (x == 0) { if (y < 0) y = -1; else if (y > 0) y = 1; } else { int semnx = 1; int semny = 1; if (x < 0) { x = -x; semnx = -1; } if (y < 0) { y = -y; semny = -1; } int cmmdc = gcd(x, y); x = x / cmmdc; y = y / cmmdc; x = x * semnx; y = y * semny; } int codh = (abs(x) + abs(y)) % MOD; for (vector<HashNode>::iterator it = H[codh].begin(); it != H[codh].end(); ++it) { if (it->x == x && it->y == y) { if (type == QueryCntStrict) return it->cntStrict; if (type == QueryCntNestrict) return it->cntNestrict; if (type == QueryIndexNestrict) return it->indexNestrict; } } return -1; } void Solve() { int loc; loc = 0; for (int i = 1; i <= N; ++i) { if (a[i].y > 0 || (a[i].y == 0 && a[i].x > 0)) { ++loc; swap(a[i], a[loc]); } } sort(a + 1, a + loc + 1); sort(a + loc + 1, a + N + 1); lastIndexForSearch = -1; NmaiMiciStrictVector = 0; NmaiMiciSauEgaleVector = 0; int specialIndex = -1; for (int i = 1; i <= N; ++i) { if (GetAngle(a[i]) >= PI) { if (a[i].y == 0) { Insert(1, 0, InsertCoord); FindMaiMiciStrict(1, 0); FindMaiMiciSauEgale(1, 0); continue; } if (a[i].x == 0) { Insert(0, 1, InsertCoord); FindMaiMiciStrict(0, 1); FindMaiMiciSauEgale(0, 1); continue; } int x, y; x = -a[i].x; y = -a[i].y; int semnx = 1, semny = 1; if (x < 0) { x = -x; semnx = -1; } if (y < 0) { y = -y; semny = -1; } int cmmdc = gcd(x, y); x = x / cmmdc; y = y / cmmdc; x = x * semnx; y = y * semny; Insert(x, y, InsertCoord); FindMaiMiciStrict(x, y); FindMaiMiciSauEgale(x, y); } else { lastIndexForSearch = i; } } bool foundOnRightOX = false; specialIndex = NmaiMiciSauEgaleVector; for (int i = 1; i <= N; ++i) { if (a[i].y == 0 && a[i].x > 0) { foundOnRightOX = true; Insert(-1, 0, InsertCoord); FindMaiMiciStrict(-1, 0); FindMaiMiciSauEgale(-1, 0); } } loc = 0; for (int i = 1; i <= NmaiMiciStrictVector; ++i) { if (maiMiciStrictVector[i].y > 0 || (maiMiciStrictVector[i].y == 0 && maiMiciStrictVector[i].x > 0)) { ++loc; swap(maiMiciStrictVector[i], maiMiciStrictVector[loc]); } } sort(maiMiciStrictVector + 1, maiMiciStrictVector + loc + 1); sort(maiMiciStrictVector + loc + 1, maiMiciStrictVector + NmaiMiciStrictVector + 1); for (int i = 1; i <= NmaiMiciStrictVector; ++i) { maiMiciStrictVectorSumePartiale[i].x = maiMiciStrictVector[i].x; maiMiciStrictVectorSumePartiale[i].y = maiMiciStrictVector[i].y; maiMiciStrictVectorSumePartiale[i].cnt = ((i > 1) ? (maiMiciStrictVectorSumePartiale[i - 1].cnt) : (0)) + maiMiciStrictVector[i].cnt; } loc = 0; for (int i = 1; i <= NmaiMiciSauEgaleVector; ++i) { if (maiMiciSauEgaleVector[i].y > 0 || (maiMiciSauEgaleVector[i].y == 0 && maiMiciSauEgaleVector[i].x > 0)) { ++loc; swap(maiMiciSauEgaleVector[i], maiMiciSauEgaleVector[loc]); } } sort(maiMiciSauEgaleVector + 1, maiMiciSauEgaleVector + loc + 1); sort(maiMiciSauEgaleVector + loc + 1, maiMiciSauEgaleVector + NmaiMiciSauEgaleVector + 1); for (int i = 1; i <= NmaiMiciSauEgaleVector; ++i) { maiMiciSauEgaleVectorSumePartiale[i].x = maiMiciSauEgaleVector[i].x; maiMiciSauEgaleVectorSumePartiale[i].y = maiMiciSauEgaleVector[i].y; maiMiciSauEgaleVectorSumePartiale[i].cnt = ((i > 1) ? (maiMiciSauEgaleVectorSumePartiale[i - 1].cnt) : (0)) + maiMiciSauEgaleVector[i].cnt; } for (int i = 1; i <= NmaiMiciSauEgaleVector; ++i) { int index = i; int x = maiMiciSauEgaleVectorSumePartiale[i].x; int y = maiMiciSauEgaleVectorSumePartiale[i].y; Insert(x, y, InsertIndexNestrict, index); } for (int i = 1; i <= NmaiMiciSauEgaleVector; ++i) diferente[i] = max(0LL, maiMiciSauEgaleVector[i].cnt - maiMiciStrictVector[i].cnt); for (int i = 1; i <= NmaiMiciSauEgaleVector; ++i) diferentePartiale[i] = diferentePartiale[i - 1] + diferente[i]; if (lastIndexForSearch != -1 && NmaiMiciSauEgaleVector != 0 && NmaiMiciStrictVector != 0) { for (int i = lastIndexForSearch + 1; i <= N; ++i) { if (a[i].y == 0 && a[i].x < 0) { int index; if (foundOnRightOX) { index = specialIndex; } else index = NmaiMiciSauEgaleVector; if (index <= 0) continue; long long total = maiMiciSauEgaleVectorSumePartiale[index].cnt; long long total2; int jndex = QueryHash(a[i].x, a[i].y, QueryIndexNestrict); if (jndex == -1) continue; total2 = maiMiciSauEgaleVectorSumePartiale[jndex].cnt + 1LL * (index - jndex) * maiMiciSauEgaleVector[jndex].cnt; long long inPlus = diferentePartiale[index]; if (foundOnRightOX) inPlus = inPlus - diferentePartiale[jndex]; ans += max(0LL, total - total2 - inPlus); } else { int index; index = NmaiMiciSauEgaleVector; if (index <= 0) continue; long long total = maiMiciSauEgaleVectorSumePartiale[index].cnt; long long total2; int jndex = QueryHash(a[i].x, a[i].y, QueryIndexNestrict); if (jndex == -1) continue; total2 = maiMiciSauEgaleVectorSumePartiale[jndex].cnt + 1LL * (index - jndex) * maiMiciSauEgaleVector[jndex].cnt; long long inPlus = diferentePartiale[index]; inPlus = inPlus - diferentePartiale[jndex]; ans += max(0LL, total - total2 - inPlus); } } } } void EliminaDuplicate() { int maiMici180, cnt; long long total; maiMici180 = 0; total = 0LL; for (int i = 1; i <= N; ++i) { int x = a[i].x, y = a[i].y; if (y > 0 || (y == 0 && x > 0)) ++maiMici180; } for (int i = 1; i <= N; ++i) { if (a[i].y < 0) { int x = -a[i].x; int y = -a[i].y; int st = 1, dr = maiMici180; int val = 0; while (st <= dr) { int mij = (st + dr) / 2; if (Determinant(Punct(0, 0), Punct(x, y), a[mij]) <= 0) { val = mij; st = mij + 1; } else dr = mij - 1; } total += max(0, maiMici180 - val); } } cnt = 0; for (int i = 1; i <= N; ++i) if (a[i].y == 0 && a[i].x > 0) ++cnt; ans = ans - 1LL * total * cnt; } int main() { std::ios_base::sync_with_stdio(false); cin >> N >> C >> D; for (int i = 1; i <= N; ++i) { int x, y; cin >> x >> y; a[i] = Punct(x - C, y - D); } Solve(); EliminaDuplicate(); for (int i = 0; i < MOD; ++i) H[i].clear(); for (int i = 1; i <= N; ++i) { a[i].x = -a[i].x; a[i].y = -a[i].y; } Solve(); EliminaDuplicate(); cout << ans << n ; return 0; } long long sqr(const long long &x) { return x * x; } long long Determinant(const Punct &A, const Punct &B, const Punct &C) { return 1LL * (A.x - C.x) * (B.y - C.y) - 1LL * (A.y - C.y) * (B.x - C.x); } long long Dist2(const Punct &A, const Punct &B) { return sqr(A.x - B.x) + sqr(A.y - B.y); } int GetCadran(const Punct &A) { if (A.x > 0 && A.y > 0) return 1; if (A.x < 0 && A.y > 0) return 2; if (A.x < 0 && A.y < 0) return 3; return 4; } long double GetAngle(const Punct &A) { long double ret = atan2(A.y, A.x); if (A.y < 0) ret = ret + PI * 2.0; return ret; } long long CompareUnghiPolar(const Punct &A, const Punct &B) { long long ret = Determinant(Punct(0, 0), A, B); if (ret > 0) return -1; if (ret < 0) return 1; if (A.y == 0 && B.y == 0) { if ((A.x > 0 && B.x > 0) || (A.x < 0 && B.x < 0)) return 0; if (A.x > 0 && B.x < 0) return -1; return 1; } if (A.x == 0 && B.x == 0) { if ((A.y > 0 && B.y > 0) || (A.y < 0 && B.y < 0)) return 0; if (A.y > 0 && B.y < 0) return -1; return 1; } int semnxA, semnxB, semnyA, semnyB; semnxA = semnxB = semnyA = semnyB = 1; if (A.x < 0) semnxA = -1; if (B.x < 0) semnxB = -1; if (A.y < 0) semnyA = -1; if (B.y < 0) semnyB = -1; if (semnxA == semnxB && semnyA == semnyB) return 0; if (semnyA == 1) return -1; return 1; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD2_BLACKBOX_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD2_BLACKBOX_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkdlyinv3sd2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD2_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { string x, y; cin >> x >> y; int sum = atoi(x.c_str()) + atoi(y.c_str()); int p = 0, now = 1; for (; sum; sum /= 10) { if (sum % 10 != 0) { p += (sum % 10) * now; now *= 10; } } x.erase(remove(x.begin(), x.end(), 0 ), x.end()); y.erase(remove(y.begin(), y.end(), 0 ), y.end()); int X = atoi(x.c_str()), Y = atoi(y.c_str()); if (X + Y == p) cout << YES << endl; else cout << NO << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const long double PI = 4 * atan((long double)1); long long power(long long a, long long n) { long long res = 1; while (n) { if (n % 2) res *= a; a *= a; n /= 2; } return res; } string bits(long long int n) { long long int m = n; string s; while (m != 0) { char x = (m % 2) + 0 ; s = s + x; m = m / 2; } reverse(s.begin(), s.end()); return s; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; string s; cin >> s; int e = 0; long long int ans = 0; for (int i = s.size() - 1; i > 0; i--) { if (s[i] == 1 ) { if (e == 0) { ans += 2; e = 1; } else ans += 1; } else { if (e == 0) ans += 1; else ans += 2; } } if (e == 1) ans += 1; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { fixed(cout); cout << setprecision(10); ; long long int n, h; cin >> n >> h; for (int i = 1; i <= n - 1; i++) { double x = (h * h * i) / double(n); x = sqrt(x); if (i == n) break; cout << x << ; } cout << endl; } |
#include <bits/stdc++.h> using namespace std; int n, m, p, len; int pos[500020]; int Left[500020]; int Right[500020]; string str; void Work() { int t = p; char op; int rt; for (int i = 0; i < m; i++) { cin >> op; if (op == L ) p = Left[p]; else if (op == R ) p = Right[p]; else { rt = pos[p]; if (rt > p) swap(rt, p); Right[Left[rt]] = Right[p]; Left[Right[p]] = Left[rt]; if (Right[p] > len) p = Left[rt]; else p = Right[p]; } } for (int i = 0; i <= len;) { if (i) cout << str[i - 1]; i = Right[i]; } cout << endl; } int main() { std::ios::sync_with_stdio(false); std::cin.tie(0); while (cin >> n >> m >> p) { stack<int> s; cin >> str; len = str.size(); Right[0] = 1; Left[1] = 0; Right[len] = len + 1; Left[len + 1] = len; for (int i = 1; i <= len; i++) { Right[i] = i + 1; Left[i] = i - 1; if (str[i - 1] == ( ) s.push(i); else { pos[i] = s.top(); pos[s.top()] = i; s.pop(); } } Work(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const unsigned long long hash1 = 201326611; const int inf = 0x3f3f3f3f; const int _inf = 0xc0c0c0c0; const long long INF = 0x3f3f3f3f3f3f3f3f; const long long _INF = 0xc0c0c0c0c0c0c0c0; const long long mod = (int)1e9 + 7; long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } long long ksm(long long a, long long b, long long mod) { int ans = 1; while (b) { if (b & 1) ans = (ans * a) % mod; a = (a * a) % mod; b >>= 1; } return ans; } long long inv2(long long a, long long mod) { return ksm(a, mod - 2, mod); } void exgcd(long long a, long long b, long long &x, long long &y, long long &d) { if (!b) { d = a; x = 1; y = 0; } else { exgcd(b, a % b, y, x, d); y -= x * (a / b); } } inline int read() { int date = 0, m = 1; char ch = 0; while (ch != - && (ch< 0 | ch> 9 )) ch = getchar(); if (ch == - ) { m = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { date = date * 10 + ch - 0 ; ch = getchar(); } return date * m; } const int MAX_N = 150025; int C[MAX_N << 1], arr[MAX_N], b[MAX_N]; void add(int x, int v) { for (; x < MAX_N; x += x & (-x)) C[x] += v; } int get(int x) { int res = 0; for (; x; x -= x & (-x)) res += C[x]; return res; } int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); for (int i = 1; i <= 2 * n + 2; ++i) C[i] = 0; for (int i = 1; i <= n; ++i) scanf( %d , &arr[i]), b[i] = arr[i]; sort(b + 1, b + 1 + n); int sz = unique(b + 1, b + 1 + n) - b - 1; int ans = 0; for (int i = n; i >= 1; --i) { arr[i] = lower_bound(b + 1, b + 1 + sz, arr[i]) - b; ans += min(get(arr[i]), 1); add(arr[i] + 1, 1); } printf( %d n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(double(-1)); const double INF = 1e10; const double EPS = 1e-8; inline double sqr(double x) { return x * x; } struct PT { double x, y; PT() {} PT(double x, double y) : x(x), y(y) {} void in() { double _x, _y; scanf( %lf%lf , &_x, &_y); x = _x, y = _y; } }; bool operator<(const PT &p1, const PT &p2) { if (fabs(p1.x - p2.x) > EPS) return p1.x < p2.x; return p1.y + EPS < p2.y; } bool operator==(const PT &p1, const PT &p2) { return fabs(p1.x - p2.x) < EPS && fabs(p1.y - p2.y) < EPS; } PT operator+(PT p1, PT p2) { return PT(p1.x + p2.x, p1.y + p2.y); } PT operator-(PT p1, PT p2) { return PT(p1.x - p2.x, p1.y - p2.y); } PT operator*(PT p, double c) { return PT(p.x * c, p.y * c); } PT operator/(PT p, double c) { return PT(p.x / c, p.y / c); } double dis(PT p) { return sqrt(sqr(p.x) + sqr(p.y)); } double dis2(PT p) { return sqr(p.x) + sqr(p.y); } PT rot(PT p, double t) { return PT(p.x * cos(t) - p.y * sin(t), p.x * sin(t) + p.y * cos(t)); } PT polar(PT p, double r, double t) { return PT(p.x + r * cos(t), p.y + r * sin(t)); } double dis2(PT p1, PT p2) { return sqr(p1.x - p2.x) + sqr(p1.y - p2.y); } double dis(PT p1, PT p2) { return sqrt(dis2(p1, p2)); } double vect(PT p1, PT p2) { return p1.x * p2.y - p2.x * p1.y; } double scal(PT p1, PT p2) { return p1.x * p2.x + p1.y * p2.y; } double getAngle(PT p1, PT p2) { return atan2(p2.y - p1.y, p2.x - p1.x); } double vect(PT p, PT p1, PT p2) { return vect(p1 - p, p2 - p); } double scal(PT p, PT p1, PT p2) { return scal(p1 - p, p2 - p); } double getAngle(PT p, PT p1, PT p2) { return getAngle(p, p2) - getAngle(p, p1); } double getAngle180(PT p, PT p1, PT p2) { return acos(scal(p, p1, p2) / dis(p, p1) / dis(p, p2)); } double disToLine(PT p, PT p1, PT p2) { return fabs(vect(p, p1, p2)) / dis(p1, p2); } double disToSeg(PT p, PT p1, PT p2) { if (scal(p1, p, p2) < 0) return dis(p, p1); if (scal(p2, p, p1) < 0) return dis(p, p2); return disToLine(p, p1, p2); } bool onLine(PT p, PT p1, PT p2) { return fabs(vect(p1 - p, p2 - p)) < EPS; } bool onSeg(PT p, PT p1, PT p2) { if (!onLine(p, p1, p2)) return 0; return (p1.x - p.x) * (p2.x - p.x) < EPS && (p1.y - p.y) * (p2.y - p.y) < EPS; } bool cross(PT p1, PT p2, PT p3, PT p4) { return vect(p1, p2, p3) * vect(p1, p2, p4) < -EPS && vect(p3, p4, p1) * vect(p3, p4, p2) < -EPS; } bool common(PT p1, PT p2, PT p3, PT p4) { if (max(p1.x, p2.x) + EPS < min(p3.x, p4.x) || max(p3.x, p4.x) + EPS < min(p1.x, p2.x)) return 0; if (max(p1.y, p2.y) + EPS < min(p3.y, p4.y) || max(p3.y, p4.y) + EPS < min(p1.y, p2.y)) return 0; return vect(p1, p2, p3) * vect(p1, p2, p4) < EPS && vect(p3, p4, p1) * vect(p3, p4, p2) < EPS; } PT projection(PT a, PT b, PT p) { return a + (a - b) * (scal(p - a, a - b) / dis2(a - b)); } int posLineLine(PT p1, PT p2, PT p3, PT p4, PT &p) { double s1 = vect(p1, p2, p3), s2 = vect(p1, p2, p4); if (fabs(s1 - s2) < EPS) { if (fabs(s1) < EPS) return 2; return 0; } p = p3 + (p4 - p3) * s1 / (s1 - s2); return 1; } int posCirLine(PT p, double r, PT p1, PT p2, PT *q) { double a, b, c, d2, d; a = dis2(p1, p2); b = scal(p1, p, p2); c = dis2(p, p1) - sqr(r); d2 = sqr(b) - a * c; if (d2 < -EPS) return 0; d = sqrt(fabs(d2)); q[0] = p1 + (p2 - p1) * (b + d) / a; if (d2 < EPS) return 1; q[1] = p1 + (p2 - p1) * (b - d) / a; return 2; } int posCirCir(PT p1, double r1, PT p2, double r2, PT *q) { double dx, dy, d, e, f2, f; dx = p2.x - p1.x, dy = p2.y - p1.y; d = dis(p1, p2); e = (sqr(r1) - sqr(r2) + sqr(d)) / 2 / d; f2 = sqr(r1) - sqr(e); if (f2 < -EPS) return 0; f = sqrt(fabs(f2)); q[0] = PT(p1.x + (e * dx - f * dy) / d, p1.y + (e * dy + f * dx) / d); if (f2 < EPS) return 1; q[1] = PT(p1.x + (e * dx + f * dy) / d, p1.y + (e * dy - f * dx) / d); return 2; } double calcArea(PT *p, int n) { double rlt = 0; for (int i = 0; i < n; i++) rlt += vect(p[i], p[(i + 1) % n]); return rlt / 2; } int inPolygon(PT p, PT *q, int m) { PT p1, p2; int k = 0; for (int i = 0; i < m; i++) { p1 = q[i], p2 = q[(i + 1) % m]; if (onSeg(p, p1, p2)) return 2; if (p1.y > p2.y) swap(p1, p2); if (p1.y < p.y + EPS && p.y + EPS < p2.y && vect(p, p1, p2) > 0) k++; } return k % 2; } inline int sgn(double a) { return a > EPS ? 1 : a < -EPS ? -1 : 0; } bool inCPolygon(PT *p, int n, PT q) { bool ccw = vect(p[1] - p[0], p[2] - p[1]) > EPS; int below = sgn(vect(q - p[0], p[n - 1] - p[0])); if (ccw && below < 0) return 0; if (!ccw && below > 0) return 0; int lo = 0, hi = n - 1; while (hi - lo > 1) { int mid = (hi + lo) >> 1; int s1 = sgn(vect(p[mid] - p[lo], q - p[lo])); int s2 = sgn(vect(q - p[hi], p[mid] - p[hi])); bool f1 = ccw ? (s1 >= 0) : (s1 <= 0); bool f2 = ccw ? (s2 >= 0) : (s2 <= 0); if (f1 && f2) return 1; if (!f1 && !f2) return 0; if (f1) lo = mid; else hi = mid; } return 0; } bool contact_convex(PT *p, int n, PT P, int &L, int &R) { if (inCPolygon(p, n, P)) return 0; for (int T = 0; T < 2; T++) { auto check = [&](int fir, int sec) { return vect(P, p[sec], p[fir]) > EPS; }; bool up = false; double cr = 0; if (n >= 2) { cr = vect(P, p[0], p[1]); } if (fabs(cr) < EPS && n >= 3) { cr = vect(P, p[0], p[2]); } up = (cr > EPS); int bd[] = {1, n - 1}; int ans = 0; while (bd[0] + 6 <= bd[1]) { int h[2]; for (int hh = 0; hh < 2; hh++) { h[hh] = (bd[0] + bd[1] + bd[hh]) / 3; } if (!check(h[up ^ T], 0) ^ T) { bd[up ^ T] = h[up ^ T]; } else { int gr = check(h[0], h[1]); bd[gr ^ T] = h[gr ^ T]; } } for (int i = bd[0]; i <= bd[1]; i++) { if (check(i, ans) ^ T) ans = i; } T ? R = ans : L = ans; } return 1; } int posLineSegEx(PT p1, PT p2, PT p3, PT p4, PT &p) { double s1 = vect(p1, p2, p3), s2 = vect(p1, p2, p4); p = p3 + (p4 - p3) * s1 / (s1 - s2); if (s1 * s2 > -EPS) return 0; return 1; } int cutPolygon(PT *p, int n, PT p1, PT p2, PT *q) { int m = 0; for (int i = 0; i < n; i++) { if (vect(p[i], p1, p2) > -EPS) q[m++] = p[i]; if (posLineSegEx(p1, p2, p[i], p[(i + 1) % n], q[m])) m++; } return m; } int cutConvex(PT *p, int n, PT p1, PT p2, PT *q) { assert(dis(p1, p2) > EPS); p1 = p1 + (p1 - p2) * 1e8; int L, R; assert(contact_convex(p, n, p1, L, R)); if (vect(p[R], p1, p2) > -EPS) { for (int i = 0; i < n; i++) q[i] = p[i]; return n; } if (vect(p[L], p1, p2) < -EPS) return 0; int st = L, en = R; if (en < st) en += n; while (st < en) { int md = (st + en) / 2; if (vect(p[md % n], p1, p2) > EPS) st = md + 1; else en = md; } int T = st % n; st = R, en = L; if (en < st) en += n; while (st < en) { int md = (st + en) / 2; if (vect(p[md % n], p1, p2) < EPS) st = md + 1; else en = md; } int F = st % n; int qn = 0; for (int i = F; i != T; i = (i + 1) % n) q[qn++] = p[i]; posLineSegEx(p1, p2, p[(T - 1 + n) % n], p[T], q[qn]), qn++; posLineSegEx(p1, p2, p[(F - 1 + n) % n], p[F], q[qn]); if (dis(q[qn], q[qn - 1]) > EPS) qn++; return qn; } double disToPolygon(PT p, PT *q, int m) { if (inPolygon(p, q, m)) return 0; double rlt = INF; for (int i = 0; i < m; i++) rlt = min(rlt, disToSeg(p, q[i], q[(i + 1) % m])); return rlt; } double dis(PT *p, int n, PT *q, int m) { double rlt; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (common(p[i], p[(i + 1) % n], q[j], q[(j + 1) % m])) return 0; } } if (inPolygon(p[0], q, m) || inPolygon(q[0], p, n)) return 0; rlt = INF; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { rlt = min(rlt, disToSeg(p[i], q[j], q[(j + 1) % m])); rlt = min(rlt, disToSeg(q[j], p[i], p[(i + 1) % n])); } } return rlt; } int convex_hull(PT *p, int n, PT *q) { sort(p, p + n); n = unique(p, p + n) - p; if (n == 1) { q[0] = p[0]; return 1; } int m = 0; for (int i = 0; i < n; i++) { while (m > 1 && vect(q[m - 2], q[m - 1], p[i]) < EPS) m--; q[m++] = p[i]; } int k = m; for (int i = n - 2; i >= 0; i--) { while (m > k && vect(q[m - 2], q[m - 1], p[i]) < EPS) m--; q[m++] = p[i]; } return --m; } PT innercenter(PT a, PT b, PT c) { double A = dis(b - c); double B = dis(c - a); double C = dis(a - b); return PT((A * a.x + B * b.x + C * c.x) / (A + B + C), (A * a.y + B * b.y + C * c.y) / (A + B + C)); } PT outercenter(PT a, PT b, PT c) { double c1 = (scal(a, a) - scal(b, b)) / 2, c2 = (scal(a, a) - scal(c, c)) / 2; double x0 = (c1 * (a.y - c.y) - c2 * (a.y - b.y)) / vect(a - b, a - c); double y0 = (c1 * (a.x - c.x) - c2 * (a.x - b.x)) / vect(a - c, a - b); return PT(x0, y0); } const int N = 1100000; double v[N]; PT P[N], Q[N], R[] = {PT(0, 0), PT(1e5, 0), PT(1e5, 1e5), PT(0, 1e5)}, T[22], S[22]; int dx[] = {0, 1, 0, -1}; int dy[] = {-1, 0, 1, 0}; void print(PT pt) { printf( %d %d n , (int)round(pt.x), (int)round(pt.y)); } int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) P[i].in(), scanf( %lf , &v[i]); int qn = 0; for (int i = 0; i < n; i++) { if (v[i] < EPS) { Q[qn++] = P[i]; continue; } int m = 4; for (int j = 0; j < m; j++) T[j] = P[i] + PT(v[i] * dx[j], v[i] * dy[j]); for (int j = 0; j < 4; j++) { m = cutPolygon(T, m, R[j], R[(j + 1) % 4], S); for (int k = 0; k < m; k++) T[k] = S[k]; } for (int j = 0; j < m; j++) Q[qn++] = T[j]; } qn = convex_hull(Q, qn, P); P[qn] = P[0], P[qn + 1] = P[1]; double ans = 0; int cur; for (int i = 0; i < qn; i++) { double ang = getAngle180(P[i], P[i + 1], P[i + 2]); double r = dis(P[i + 1], P[i + 2]) / sin(ang); if (ans < r) { ans = r; cur = i; } } for (int i = cur; i < cur + 3; i++) print(P[i]); } |
#include <bits/stdc++.h> using namespace std; int n, m, a[105]; int main() { int s = 0, t = 0; ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); for (int i = 0; i < n; i++) { if (s >= m) break; else { s += a[n - i - 1]; t++; } } cout << t; return 0; } |
#include<bits/stdc++.h> using namespace std; #define ll long long ll gcd(ll a, ll b){ return b?gcd(b,a%b):a; } ll a[200005],b[200005],c,d; int main(){ ll n,m; scanf( %lld%lld ,&n,&m); ll d=0; cin>>a[1]; for(ll i=2;i<=n;i++){ //从a[2]-a[1]开始 scanf( %lld ,&a[i]); d=gcd(d,a[i]-a[i-1]); //gcd(0,a)=a } for(ll i=1;i<=m;i++){ scanf( %lld ,&b[i]); ll dd=abs(gcd(d,a[1]+b[i])); printf( %lld ,dd); } return 0; } |
#include <bits/stdc++.h> int a[100006]; int vis[100006]; int visyu[100006]; int main() { int n, x; scanf( %d%d , &n, &x); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); vis[a[i]]++; if (vis[a[i]] == 2) { printf( 0 n ); return 0; } } int mans = -1; for (int i = 1; i <= n; i++) { visyu[a[i] & x]++; if (visyu[a[i] & x] && vis[a[i] & x] && ((a[i] & x) != a[i])) { printf( 1 n ); return 0; } else if (visyu[a[i] & x] == 2) { mans = 2; } } printf( %d n , mans); } |
#include <bits/stdc++.h> using namespace std; const int N = 2e6; int cost[N], n, a, b, T; string s; long long l[N], r[N]; bool check(int d) { --d; long long bst = min(l[d], r[d]); for (int i = 1; i < d; ++i) { bst = min(bst, l[i] + r[d - i] + a * i); bst = min(bst, r[i] + l[d - i] + a * i); } return bst + d + 1 + cost[0] <= T; } int main() { ios_base::sync_with_stdio(0); cin >> n >> a >> b >> T; cin >> s; for (int i = 0; i < s.size(); ++i) { cost[i] = (s[i] == w ? b : 0); } for (int i = 1; i < n; ++i) { r[i] = r[i - 1] + cost[i] + a; } for (int i = 1; i < n; ++i) { l[i] = l[i - 1] + cost[n - i] + a; } int L = 0, R = n + 1; while (R - L > 1) { int m = (L + R) >> 1; if (check(m)) L = m; else R = m; } cout << L; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAH_TB_V
`define SKY130_FD_SC_HD__FAH_TB_V
/**
* fah: Full adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__fah.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CI;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CI = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CI = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 CI = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 CI = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 CI = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 CI = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__fah dut (.A(A), .B(B), .CI(CI), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAH_TB_V
|
module BRAMInterconnect(rddata_bo,s1_addr_bo,s1_wrdata_bo,s1_en_o,s1_we_bo,s2_addr_bo,s2_wrdata_bo,s2_en_o,s2_we_bo,s3_addr_bo,s3_wrdata_bo,s3_en_o,s3_we_bo,addr_bi,clk_i,wrdata_bi,en_i,rst_i,we_bi,s1_rddata_bi,s2_rddata_bi,s3_rddata_bi);
output [31:0] rddata_bo;
output [12:0] s1_addr_bo;
output [31:0] s1_wrdata_bo;
output s1_en_o;
output [3:0] s1_we_bo;
output [12:0] s2_addr_bo;
output [31:0] s2_wrdata_bo;
output s2_en_o;
output [3:0] s2_we_bo;
output [12:0] s3_addr_bo;
output [31:0] s3_wrdata_bo;
output s3_en_o;
output [3:0] s3_we_bo;
input [12:0] addr_bi;
input clk_i;
input [31:0] wrdata_bi;
input en_i;
input rst_i;
input [3:0] we_bi;
input [31:0] s1_rddata_bi;
input [31:0] s2_rddata_bi;
input [31:0] s3_rddata_bi;
reg [31:0] rddata_bo;
reg [12:0] s1_addr_bo;
reg [31:0] s1_wrdata_bo;
reg s1_en_o;
reg [3:0] s1_we_bo;
reg [12:0] s2_addr_bo;
reg [31:0] s2_wrdata_bo;
reg s2_en_o;
reg [3:0] s2_we_bo;
reg [12:0] s3_addr_bo;
reg [31:0] s3_wrdata_bo;
reg s3_en_o;
reg [3:0] s3_we_bo;
reg next_en_o_reg;
reg en_o_reg;
//write:
always @(we_bi or en_i or wrdata_bi or addr_bi )
begin
if (en_i )
begin
case(addr_bi )
'h0, 'h4, 'h8 :
begin
s1_addr_bo =(addr_bi );
s1_wrdata_bo =(wrdata_bi );
s1_en_o =(en_i );
s1_we_bo =(we_bi );
end
'h0C, 'h10, 'h14 :
begin
s2_addr_bo =(addr_bi -'h0C );
s2_wrdata_bo =(wrdata_bi );
s2_en_o =(en_i );
s2_we_bo =(we_bi );
end
'h18, 'h1C :
begin
s3_addr_bo =(addr_bi -'h18);
s3_wrdata_bo =(wrdata_bi );
s3_en_o =(en_i );
s3_we_bo =(we_bi );
end
endcase
end
else
begin
s1_addr_bo =(0);
s1_wrdata_bo =(0);
s1_en_o =(0);
s1_we_bo =(0);
s2_addr_bo =(0);
s2_wrdata_bo =(0);
s2_en_o =(0);
s2_we_bo =(0);
s3_addr_bo =(0);
s3_wrdata_bo =(0);
s3_en_o =(0);
s3_we_bo =(0);
end
end
//read:
always @(s3_rddata_bi or s2_rddata_bi or s1_rddata_bi or en_o_reg )
begin
if (en_o_reg )
begin
case(addr_bi )
'h0, 'h4, 'h8 :
begin
rddata_bo =(s1_rddata_bi );
end
'h0C, 'h10, 'h14 :
begin
rddata_bo =(s2_rddata_bi );
end
'h18, 'h1C :
begin
rddata_bo =(s3_rddata_bi );
end
endcase
end
else
begin
rddata_bo =(0);
end
end
//neg_clk:
always @(negedge clk_i )
begin
next_en_o_reg <=(en_i &&!we_bi );
end
//registers:
always @(posedge clk_i or posedge rst_i )
begin
if (!rst_i &&clk_i )
begin
en_o_reg <=(next_en_o_reg );
end
else
begin
en_o_reg <=(0);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { long long int n; std::cin >> n; long long int ans[n]; for (long long int i = 0; i < n; i++) { std::cin >> ans[i]; } long long int count[n]; memset(count, 0, sizeof(count)); for (long long int i = 0; i < n; i++) { count[i] += (ans[i] * 15); for (long long int j = 0; j < ans[i]; j++) { long long int x; std::cin >> x; count[i] += (x * 5); } } long long int min = (*(std::min_element(count, count + n))); std::cout << min << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T x, T y) { if (x < y) swap(x, y); while (y > 0) { T f = x % y; x = y; y = f; } return x; } template <typename T> pair<T, T> exgcd(T x, T y) { int sw = 0; if (x < y) sw = true, swap(x, y); pair<T, T> r = make_pair(1, 0); while (y > 0) { T f = x % y; r = make_pair(r.second, r.first - (x / y) * r.second); x = y; y = f; }; if (sw) swap(r.first, r.second); return r; } int rot[][12] = { { 1, 2, 4, 3, 13, 14, 5, 6, 17, 18, 21, 22, }, { 9, 10, 11, 12, 15, 16, 7, 8, 19, 20, 23, 24, }, {13, 14, 16, 15, 1, 3, 5, 7, 9, 11, 24, 22}, {17, 18, 20, 19, 2, 4, 6, 8, 10, 12, 23, 21}, {5, 6, 8, 7, 3, 4, 17, 19, 10, 9, 16, 14}, {21, 22, 24, 23, 18, 20, 12, 11, 15, 13, 1, 2}, }; bool solved(int s[25]) { for (int i = 1; i < 24; i += 4) { if (s[i] != s[i + 1] || s[i] != s[i + 2] || s[i] != s[i + 3]) return false; } return true; } int main(int argc, char *argv[]) { std::cin.sync_with_stdio(false); std::cin.tie(nullptr); int s[25]; cin >> s[1]; { for (int i = 2; i <= 24; i++) cin >> s[i]; int t[25]; bool ok = false; for (int i = 0; i < 6; i++) { memcpy(t, s, sizeof(t)); for (int j = 0; j < 4; j++) t[rot[i][(j + 1) % 4]] = s[rot[i][j]]; for (int j = 0; j < 8; j++) t[rot[i][4 + ((j + 2) % 8)]] = s[rot[i][4 + j]]; if (solved(t)) { ok = true; break; } memcpy(t, s, sizeof(t)); for (int j = 0; j < 4; j++) t[rot[i][(j + 3) % 4]] = s[rot[i][j]]; for (int j = 0; j < 8; j++) t[rot[i][4 + ((j + 6) % 8)]] = s[rot[i][4 + j]]; if (solved(t)) { ok = true; break; } } cout << (ok ? YES : NO ) << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__O21AI_PP_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21AI_PP_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / VCC Connection
// /___/ /\ Filename : VCC.v
// \ \ / \ Timestamp : Thu Mar 25 16:43:41 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module VCC(P);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output P;
assign P = 1'b1;
endmodule
`endcelldefine
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:03:36 09/24/2013
// Design Name: Comparador
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab3/laboratorio3/test_comparador.v
// Project Name: laboratorio3
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Comparador
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_comparador;
// Inputs
reg clock;
reg reset;
reg [3:0] write_value;
reg [3:0] read_value;
reg read_value_reg_en;
// Outputs
wire led_success;
wire led_fail;
// Instantiate the Unit Under Test (UUT)
Comparador uut (
.clock(clock),
.reset(reset),
.write_value(write_value),
.read_value(read_value),
.read_value_reg_en(read_value_reg_en),
.led_success(led_success),
.led_fail(led_fail)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
write_value = 0;
read_value = 0;
read_value_reg_en = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: afifo.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $
// \ \ / \ Date Created: Oct 21 2008
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: A generic synchronous fifo.
//Reference:
//Revision History: 1.2 11/8/2010 Removed unused signals.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_afifo #
(
parameter TCQ = 100,
parameter DSIZE = 32,
parameter FIFO_DEPTH = 16,
parameter ASIZE = 4,
parameter SYNC = 1 // only has always '1' logic.
)
(
input wr_clk,
input rst,
input wr_en,
input [DSIZE-1:0] wr_data,
input rd_en,
input rd_clk,
output [DSIZE-1:0] rd_data,
output reg full,
output reg empty,
output reg almost_full
);
// memory array
reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1];
//Read Capture Logic
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
reg [ASIZE:0] rd_capture_ptr;
reg [ASIZE:0] pre_rd_capture_gray_ptr;
reg [ASIZE:0] rd_capture_gray_ptr;
reg [ASIZE:0] wr_capture_ptr;
reg [ASIZE:0] pre_wr_capture_gray_ptr;
reg [ASIZE:0] wr_capture_gray_ptr;
wire [ASIZE:0] buf_avail;
wire [ASIZE:0] buf_filled;
wire [ASIZE-1:0] wr_addr, rd_addr;
wire COutb,COutd;
reg COuta,COutc;
reg [ASIZE:0] wr_ptr, rd_ptr,rd_ptr_cp;
integer i,j,k;
always @ (rd_ptr)
rd_capture_ptr = rd_ptr;
//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers
// before do comparison.
always @ (wr_ptr)
wr_capture_ptr = wr_ptr;
// dualport ram
// Memory (RAM) that holds the contents of the FIFO
assign wr_addr = wr_ptr[ASIZE-1:0];
assign rd_data = mem[rd_addr];
always @(posedge wr_clk)
begin
if (wr_en && !full)
mem[wr_addr] <= #TCQ wr_data;
end
// Read Side Logic
assign rd_addr = rd_ptr_cp[ASIZE-1:0];
assign rd_strobe = rd_en && !empty;
integer n;
// change the binary pointer to gray pointer
always @(posedge rd_clk)
begin
if (rst)
begin
rd_ptr <= #TCQ 'b0;
rd_ptr_cp <= #TCQ 'b0;
end
else begin
if (rd_strobe) begin
{COuta,rd_ptr} <= #TCQ rd_ptr + 1'b1;
rd_ptr_cp <= #TCQ rd_ptr_cp + 1'b1;
end
// change the binary pointer to gray pointer
end
end
//generate empty signal
assign {COutb,buf_filled} = wr_capture_ptr - rd_ptr;
always @ (posedge rd_clk )
begin
if (rst)
empty <= #TCQ 1'b1;
else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe))
empty <= #TCQ 1'b1;
else
empty <= #TCQ 1'b0;
end
// write side logic;
reg [ASIZE:0] wbin;
wire [ASIZE:0] wgraynext, wbinnext;
always @(posedge rd_clk)
begin
if (rst)
begin
wr_ptr <= #TCQ 'b0;
end
else begin
if (wr_en)
{COutc, wr_ptr} <= #TCQ wr_ptr + 1'b1;
// change the binary pointer to gray pointer
end
end
// calculate how many buf still available
//assign {COutd,buf_avail }= (rd_capture_ptr + 5'd16) - wr_ptr;
assign {COutd,buf_avail }= rd_capture_ptr - wr_ptr + + 5'd16;
always @ (posedge wr_clk )
begin
if (rst)
full <= #TCQ 1'b0;
else if ((buf_avail == 0) || (buf_avail == 1 && wr_en))
full <= #TCQ 1'b1;
else
full <= #TCQ 1'b0;
end
always @ (posedge wr_clk )
begin
if (rst)
almost_full <= #TCQ 1'b0;
else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en))
almost_full <= #TCQ 1'b1;
else
almost_full <= #TCQ 1'b0;
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top (
input clk,
input cpu_reset,
input data_in,
output data_out
);
wire data_out;
wire builder_pll_fb;
wire main_locked;
PLLE2_ADV #(
.CLKFBOUT_MULT(4'd12),
.CLKIN1_PERIOD(10.0),
.CLKOUT0_DIVIDE(4'd12),
.CLKOUT0_PHASE(0.0),
.DIVCLK_DIVIDE(1'd1),
.REF_JITTER1(0.01),
.STARTUP_WAIT("FALSE")
) PLLE2_ADV (
.CLKFBIN(builder_pll_fb),
.CLKIN1(clk),
.RST(cpu_reset),
.CLKFBOUT(builder_pll_fb),
.CLKOUT0(main_clkout0),
.CLKOUT1(main_clkout1),
.CLKOUT2(main_clkout2),
.CLKOUT3(main_clkout3),
.CLKOUT4(main_clkout4),
.LOCKED(main_locked)
);
FDCE FDCE_PLLx1_PH0 (
.D (data_in),
.C (main_clkout0),
.CE (1'b1),
.CLR(1'b0),
.Q (data_out)
);
endmodule
|
`ifndef _sixbitdiv_incl
`define _sixbitdiv_incl
`include "sixbitsub.v"
module sixbitdiv (dividend, divisor, quotient, remainder, err);
input[5:0] dividend;
input[5:0] divisor;
output[5:0] quotient;
output[5:0] remainder;
output err;
wire[5:0] posdividend;
wire[5:0] posdivisor;
wire[5:0] posquotient;
wire[5:0] posremainder;
wire[5:0] sub1;
wire[5:0] sub2;
wire[5:0] sub3;
wire[5:0] sub4;
wire[5:0] sub5;
wire[5:0] sub6;
wire[5:0] div1;
wire[5:0] div2;
wire[5:0] div3;
wire[5:0] div4;
wire[5:0] div5;
wire[5:0] overflow;
wire divzero;
nor (divzero, divisor[5], divisor[4], divisor[3], divisor[2], divisor[1], divisor[0]);
assign posdividend = dividend[5] ? ~(dividend - 1) : dividend;
assign posdivisor = divisor[5] ? ~(divisor - 1) : divisor;
assign div1 = posdividend;
assign posquotient[5] = 0;
assign overflow[0] = 0;
sixbitsub sb2 (div1, (posdivisor << 4) & 'h1F, sub2, overflow[1]);
nor (posquotient[4], sub2[5], overflow[1], posdivisor[5], posdivisor[4], posdivisor[3], posdivisor[2], posdivisor[1]);
assign div2 = posquotient[4] ? sub2 : div1;
sixbitsub sb3 (div2, (posdivisor << 3) & 'h1F, sub3, overflow[2]);
nor (posquotient[3], sub3[5], overflow[2], posdivisor[5], posdivisor[4], posdivisor[3], posdivisor[2]);
assign div3 = posquotient[3] ? sub3 : div2;
sixbitsub sb4 (div3, (posdivisor << 2) & 'h1F, sub4, overflow[3]);
nor (posquotient[2], sub4[5], overflow[3], posdivisor[5], posdivisor[4], posdivisor[3]);
assign div4 = posquotient[2] ? sub4 : div3;
sixbitsub sb5 (div4, (posdivisor << 1) & 'h1F, sub5, overflow[4]);
nor (posquotient[1], sub5[5], overflow[4], posdivisor[5], posdivisor[4]);
assign div5 = posquotient[1] ? sub5 : div4;
sixbitsub sb6 (div5, (posdivisor) & 'h1F, sub6, overflow[5]);
nor (posquotient[0], sub6[5], overflow[5], posdivisor[5]);
assign posremainder = posquotient[0] ? sub6 : div5;
assign err = |overflow || divzero;
assign quotient = (dividend[5] ^ divisor[5]) ? ~posquotient + 1 : posquotient;
assign remainder = dividend[5] ? ~posremainder + 1 : posremainder;
endmodule
`endif |
#include <bits/stdc++.h> #pragma GCC optimize(3, Ofast , inline ) #pragma GCC target( avx,avx2 ) using namespace std; template <class t> inline t read(t &x) { char c = getchar(); bool f = 0; x = 0; while (!isdigit(c)) f |= c == - , c = getchar(); while (isdigit(c)) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); if (f) x = -x; return x; } template <class t> inline void write(t x) { if (x < 0) putchar( - ), write(-x); else { if (x > 9) write(x / 10); putchar( 0 + x % 10); } } const int mod = 1e9, N = 2e5 + 5; int tr0[N << 2], tr1[N << 2], tg[N << 2], n, m, f[N], sum[N]; int trans(int x, int len) { if (!len) return tr0[x]; if (len == 1) return tr1[x]; return (1ll * tr0[x] * f[len - 2] + 1ll * tr1[x] * f[len - 1]) % mod; } void pushup(int x, int l, int r) { int mid = l + r >> 1; tr0[x] = tr0[x << 1] + trans(x << 1 | 1, mid - l + 1); if (tr0[x] > mod) tr0[x] -= mod; tr1[x] = tr1[x << 1] + trans(x << 1 | 1, mid - l + 2); if (tr1[x] > mod) tr1[x] -= mod; } void build(int x, int l, int r) { if (l == r) { tr0[x] = read(tr1[x]); return; } int mid = l + r >> 1; build(x << 1, l, mid); build(x << 1 | 1, mid + 1, r); pushup(x, l, r); } void add(int x, int len, int v) { tg[x] += v; if (tg[x] > mod) tg[x] -= mod; tr0[x] = (tr0[x] + 1ll * sum[len - 1] * v) % mod; tr1[x] = (tr1[x] + 1ll * (sum[len] - 1 + mod) * v) % mod; } void pushdown(int x, int l, int r) { if (!tg[x]) return; int mid = l + r >> 1; add(x << 1, mid - l + 1, tg[x]); add(x << 1 | 1, r - mid, tg[x]); tg[x] = 0; } void mfy(int x, int l, int r, int p, int v) { if (l == r) { tr0[x] = tr1[x] = v; return; } pushdown(x, l, r); int mid = l + r >> 1; if (p <= mid) mfy(x << 1, l, mid, p, v); else mfy(x << 1 | 1, mid + 1, r, p, v); pushup(x, l, r); } void up(int x, int l, int r, int p, int q, int v) { if (p <= l && r <= q) { add(x, r - l + 1, v); return; } pushdown(x, l, r); int mid = l + r >> 1; if (p <= mid) up(x << 1, l, mid, p, q, v); if (q > mid) up(x << 1 | 1, mid + 1, r, p, q, v); pushup(x, l, r); } int que(int x, int l, int r, int p, int q) { if (p <= l && r <= q) return trans(x, l - p); pushdown(x, l, r); int mid = l + r >> 1, res = 0; if (p <= mid) res += que(x << 1, l, mid, p, q); if (q > mid) res += que(x << 1 | 1, mid + 1, r, p, q); if (res > mod) res -= mod; return res; } signed main() { read(n); read(m); f[0] = f[1] = 1; sum[0] = 1; sum[1] = 2; for (int i = 2; i <= n; i++) { f[i] = f[i - 1] + f[i - 2]; if (f[i] > mod) f[i] -= mod; sum[i] = sum[i - 1] + f[i]; if (sum[i] > mod) sum[i] -= mod; } build(1, 1, n); while (m--) { int op; read(op); if (op == 1) { int p, v; read(p); read(v); mfy(1, 1, n, p, v); } if (op == 2) { int l, r; read(l); read(r); write(que(1, 1, n, l, r)); puts( ); } if (op == 3) { int l, r, v; read(l); read(r); read(v); up(1, 1, n, l, r, v); } } } |
#include <bits/stdc++.h> using namespace std; int n, arr[3], ans, a, b, c, ma, t; multiset<int> s; int main() { scanf( %d , &n); for (int i = 0; i < 3; i++) scanf( %d , arr + i); for (int i = 0; i < n; i++) { scanf( %d , &t); s.insert(t); ma = max(t, ma); } sort(arr, arr + 3); a = arr[0]; b = arr[1]; c = arr[2]; if (a + b + c < ma) return 0 * printf( -1 n ); multiset<int>::iterator now, it = s.upper_bound(b + c); while (it != s.end()) s.erase(it++), ans++; it = s.upper_bound(a + c); while (it != s.end()) { ans++; s.erase(it++); now = s.upper_bound(a); now--; if (now != s.end()) s.erase(now); } it = s.upper_bound(max(a + b, c)); while (it != s.end()) { ans++; s.erase(it++); now = s.upper_bound(b); now--; if (now != s.end()) s.erase(now); } if (a + b > c) { now = it = s.upper_bound(c); now--; while (it != s.end()) { ans++; s.erase(it++); if (now != s.end()) s.erase(now--); } } while (!s.empty()) { ans++; it = s.end(); it--; s.erase(it); if (s.empty()) break; now = s.upper_bound(b); now--; if (now != s.end() && b >= *now) { s.erase(now); if (s.empty()) break; now = s.upper_bound(a); now--; if (now != s.end() && a >= *now) s.erase(now); } else { now = s.upper_bound(a + b); now--; if (now != s.end() && a + b >= *now) s.erase(now); } } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int getint() { unsigned int c; int x = 0; while (((c = getchar()) - 0 ) >= 10) { if (c == - ) return -getint(); if (!~c) exit(0); } do { x = (x << 3) + (x << 1) + (c - 0 ); } while (((c = getchar()) - 0 ) < 10); return x; } int getc_str(char str[]) { unsigned int c, n = 0; while ((c = getchar()) <= ) ; if (!~c) exit(0); do { str[n++] = c; } while ((c = getchar()) > ); str[n] = 0 ; return n; } const long long MOD = 1000000007; long long dp[123][2789]; int n; char in[123]; int main() { int i, j, k, tcc, tc = getint(); dp[0][0] = 1; for (i = 0; i < 111; i++) { for (j = 0; j <= 2600; j++) { for (k = 0; k < 26; k++) { (dp[i + 1][j + k] += dp[i][j]) %= MOD; } } } for (tcc = 0; tcc < tc; tcc++) { n = getc_str(in); int sum = 0; for (i = 0; i < n; i++) sum += in[i] - a ; int res = (dp[n][sum] - 1 + MOD) % MOD; printf( %d n , res); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2005, P = 998244353; using ll = long long; ll qpow(ll a, ll b) { ll ret = 1; while (b) { if (b & 1) ret = ret * a % P; a = a * a % P; b >>= 1; } return ret; } int n, a, b; ll pw[N * N], pw1[N * N]; ll dp[N][N], f[N], g[N], h[N]; int main() { ios::sync_with_stdio(false); cin >> n >> a >> b; ll p = a * qpow(b, P - 2) % P; if (n == 1) { cout << 0 << endl; return 0; } if (n == 2) { cout << 1 << endl; return 0; } pw[0] = pw1[0] = 1; for (int i = 1; i <= n * n; i++) { pw[i] = pw[i - 1] * p % P; pw1[i] = pw1[i - 1] * (P - p + 1) % P; } dp[0][0] = 1; for (int i = 1; i <= n; i++) { dp[i][0] = 1; for (int j = 1; j <= i; j++) dp[i][j] = (dp[i - 1][j] * pw1[j] + dp[i - 1][j - 1] * pw[i - j]) % P; } for (int i = 1; i <= n; i++) { f[i] = 1; for (int j = 1; j < i; j++) f[i] = (f[i] + P - f[j] * dp[i][j] % P) % P; } for (int i = 3; i <= n; i++) { ll tt = i * (i - 1) / 2; for (int j = 1; j < i; j++) { ll tmp = (g[j] + h[i - j]) * f[j] % P * dp[i][j] % P; tt = (tt + tmp) % P; } g[i] = tt * qpow(P + 1 - f[i], P - 2) % P; tt = f[i] * g[i] % P; for (int j = 1; j < i; j++) { ll tmp = (g[j] + h[i - j]) * f[j] % P * dp[i][j] % P; tt = (tt + tmp) % P; } h[i] = tt; } cout << g[n] << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Xilinx
// Engineer: bwiec
// Create Date: Mon Jun 05 07:43:03 MDT 2015
// Design Name: dma_controller
// Module Name: tlast_gen
// Project Name: DMA Controller
// Target Devices: All
// Tool Versions: 2015.1
// Description: Generate tlast based on configured packet length
//
// Dependencies: None
//
// Revision:
// - Rev 0.20 - Behavior verified in hardware testcase
// - Rev 0.10 - Behavior verified in behavioral simulation
// - Rev 0.01 - File created
//
// Known Issues:
// - Rev 0.20 - None
// - Rev 0.10 - None
// - Rev 0.01 - None
//
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tlast_gen
#(
parameter TDATA_WIDTH = 8,
parameter PKT_LENGTH = 1024*1024
)
(
// Clocks and resets
input aclk,
input resetn,
// Slave interface
input s_axis_tvalid,
output s_axis_tready,
input [TDATA_WIDTH-1:0] s_axis_tdata,
// Master interface
output m_axis_tvalid,
input m_axis_tready,
output m_axis_tlast,
output [TDATA_WIDTH-1:0] m_axis_tdata
);
// Internal signals
wire new_sample;
reg [$clog2(PKT_LENGTH):0] cnt = 0;
// Pass through control signals
assign s_axis_tready = m_axis_tready;
assign m_axis_tvalid = s_axis_tvalid;
assign m_axis_tdata = s_axis_tdata;
// Count samples
assign new_sample = s_axis_tvalid & s_axis_tready;
always @ (posedge aclk) begin
if (~resetn | (m_axis_tlast & new_sample))
cnt <= 0;
else
if (new_sample)
cnt <= cnt + 1'b1;
end
// Generate tlast
assign m_axis_tlast = (cnt == PKT_LENGTH-1);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2_PP_SYMBOL_V
`define SKY130_FD_SC_LS__AND2_PP_SYMBOL_V
/**
* and2: 2-input AND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41OI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A41OI_PP_BLACKBOX_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a41oi (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41OI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1000 + 10; long long par[maxn], t[maxn], c[maxn]; const long long inf = 1000000000000ll; long long dist[maxn][maxn], dis[maxn]; bool mark[maxn]; vector<int> v[maxn], u[maxn]; set<pair<long long, int> > s; vector<long long> cost1[maxn], cost2[maxn]; int main() { int n, m, x, y; cin >> n >> m >> x >> y; x--; y--; for (int i = 0; i < m; i++) { int a, b, z; cin >> a >> b >> z; a--; b--; v[a].push_back(b); v[b].push_back(a); cost1[a].push_back(z); cost1[b].push_back(z); } for (int i = 0; i < n; i++) { cin >> t[i] >> c[i]; } for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) dist[i][j] = inf; } for (int i = 0; i < n; i++) { for (int k = 0; k < n; k++) mark[k] = 0; dist[i][i] = 0; s.insert(make_pair(0, i)); while (!s.empty()) { int cur = s.begin()->second; s.erase(s.begin()); mark[cur] = true; for (int j = 0; j < v[cur].size(); j++) { int next = v[cur][j]; if (mark[next] == true) continue; long long ndist = dist[i][cur] + cost1[cur][j]; if (dist[i][next] > ndist) { par[next] = cur; s.erase(make_pair(dist[i][next], next)); dist[i][next] = min(ndist, dist[i][next]); s.insert(make_pair(dist[i][next], next)); } } } } for (int i = 0; i < n; i++) mark[i] = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (dist[i][j] > 0 && dist[i][j] <= t[i]) { u[i].push_back(j); cost2[i].push_back(c[i]); } } } for (int i = 0; i < n; i++) dis[i] = inf; dis[x] = 0; s.insert(make_pair(0, x)); while (!s.empty()) { int cur = s.begin()->second; s.erase(s.begin()); mark[cur] = true; for (int i = 0; i < u[cur].size(); i++) { int next = u[cur][i]; if (mark[next] == true) continue; long long ndist = dis[cur] + cost2[cur][i]; if (dis[next] > ndist) { s.erase(make_pair(dis[next], next)); dis[next] = min(ndist, dis[next]); s.insert(make_pair(dis[next], next)); } } } if (mark[y] == true) cout << dis[y]; else cout << -1; return 0; } |
#include <bits/stdc++.h> using namespace std; void out() { cout.flush(); cerr << endl << OUT << endl; int bred; cin >> bred; exit(0); } void updMax(int& x, int y) { if (y > x) x = y; } int sum10(int x, int y) { x += y; if (x >= 10) x -= 10; return x; } int cs[10]; int n, m; string a, bs[1024]; int dp[1024][1024], sorted[1024][1024], h[10], whereGo[1024][10], res[1024][10], curc[1024]; int getCipher(const string& s, int ind) { if (ind >= s.length()) return 0; return s[ind] - 0 ; } void buildSorted() { for (int j = 0; j < n; ++j) sorted[0][j] = j; for (int i = 0; i < 1002; ++i) { memset(h, 0, sizeof(h)); for (int j = 0; j < n; ++j) h[getCipher(bs[j], i)]++; for (int j = 1; j < 10; ++j) h[j] += h[j - 1]; for (int j = n - 1; j >= 0; --j) { int v = sorted[i][j]; sorted[i + 1][--h[getCipher(bs[v], i)]] = v; } } } int ps[1024], qs[1024], revps[1024], revqs[1024]; void calcWhereGo(int pos) { for (int i = 0; i < n; ++i) { ps[i] = sorted[pos][i]; qs[i] = sorted[pos + 1][i]; revps[ps[i]] = i; revqs[qs[i]] = i; } for (int c = 0; c <= 9; ++c) { int curper = n; for (int i = 0; i < n; ++i) if (getCipher(bs[ps[i]], pos) + c >= 10) curper = min(curper, revqs[ps[i]]); whereGo[n][c] = curper; for (int i = n - 1; i >= 0; --i) { if (getCipher(bs[ps[i]], pos) + c + 1 >= 10) curper = min(curper, revqs[ps[i]]); whereGo[i][c] = curper; } } } void calcRes(int pos) { for (int c = 0; c <= 9; ++c) { int sum = 0; for (int i = 0; i < n; ++i) { curc[i] = sum10(getCipher(bs[sorted[pos][i]], pos), c); if (curc[i] == 0 && pos >= bs[sorted[pos][i]].length()) curc[i] = 0; else curc[i] = cs[curc[i]]; sum += curc[i]; } res[n][c] = sum; int cc = sum10(c, 1); for (int i = n - 1; i >= 0; --i) { sum -= curc[i]; curc[i] = sum10(getCipher(bs[sorted[pos][i]], pos), cc); sum += cs[curc[i]]; res[i][c] = sum; } } } void calcDynamics() { for (int i = 0; i <= 1001; ++i) for (int j = 0; j <= n; ++j) dp[i][j] = -1000000000; dp[0][n] = 0; for (int i = 0; i <= 1000; ++i) { calcWhereGo(i); calcRes(i); int l, r; if (i >= m) l = r = 0; else if (a[i] == ? ) { r = 9; l = (i == m - 1); } else l = r = a[i] - 0 ; for (int j = 0; j <= n; ++j) for (int c = l; c <= r; ++c) updMax(dp[i + 1][whereGo[j][c]], dp[i][j] + res[j][c]); } } void solve() { cin >> a >> n; reverse(a.begin(), a.end()); m = a.length(); for (int i = 0; i < n; ++i) { cin >> bs[i]; reverse(bs[i].begin(), bs[i].end()); while (bs[i].length() < m) bs[i].push_back( 0 ); } for (int i = 0; i < 10; ++i) cin >> cs[i]; buildSorted(); calcDynamics(); int ans = 0; for (int i = 0; i <= n; ++i) ans = max(ans, dp[1001][i]); cout << ans << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); solve(); out(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long x, y, l, r; long long xx[105], yy[105]; vector<long long> ans; void readcase() { cin >> x >> y >> l >> r; xx[0] = 1; yy[0] = 1; int lena = 1; int lenb = 1; while (r / x >= xx[lena - 1]) { xx[lena] = xx[lena - 1] * x; lena++; } while (r / y >= yy[lenb - 1]) { yy[lenb] = yy[lenb - 1] * y; lenb++; } for (int i = 0; i < lena; i++) { for (int j = 0; j < lenb; j++) { long long temp = xx[i] + yy[j]; if (temp <= r && temp >= l) ans.push_back(temp); } } sort(ans.begin(), ans.end()); } int main() { readcase(); long long maxlen = 0; if (ans.size() == 0) maxlen = r - l + 1; else maxlen = max(ans[0] - l, r - ans[ans.size() - 1]); for (int i = 0; i < ans.size(); i++) { maxlen = max(maxlen, ans[i] - l - 1); l = ans[i]; } cout << maxlen << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; bool adj[110][110]; short color[110]; bool ok = true; int n, m; void dfs(int node, int ccolor) { color[node] = ccolor; for (int i = 0; i < m; i++) { if (adj[node][i]) { if (color[i] == 0) { dfs(i, ccolor * (-1)); } else if (color[i] == ccolor) { ok = false; } } } } int main() { cin >> n >> m; int ai[110], bi[110], a, b, i, j; for (i = 0; i < m; i++) { cin >> ai[i] >> bi[i]; if (bi[i] < ai[i]) swap(ai[i], bi[i]); } int x1, x2, y1, y2; for (i = 0; i < m; i++) { for (j = i + 1; j < m; j++) { if (ai[i] > ai[j] && ai[i] < bi[j] && bi[i] > bi[j]) adj[i][j] = adj[j][i] = 1; if (ai[j] > ai[i] && ai[j] < bi[i] && bi[j] > bi[i]) adj[i][j] = adj[j][i] = 1; } } for (i = 0; i < m; i++) { if (color[i] == 0) dfs(i, 1); } if (ok) { for (i = 0; i < m; i++) { if (color[i] == 1) cout << i ; else if (color[i] == -1) cout << o ; } } else { cout << Impossible << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; int main() { int a, b, c; cin >> a >> b >> c; if (!c) return cout << (a == b ? YES : NO ), 0; if (c > 0 && b < a || c < 0 && b > a) return cout << NO , 0; cout << ((a % c + c) % c == (b % c + c) % c ? YES : NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n; cin >> n; int arr[n]; for (int i = 0; i < n; i++) cin >> arr[i]; for (int i = n - 1; i >= 0; i--) cout << arr[i] << ; cout << endl; } return 0; } |
module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
parameter MEMID = "";
parameter SIZE = 256;
parameter OFFSET = 0;
parameter ABITS = 8;
parameter WIDTH = 8;
parameter signed INIT = 1'bx;
parameter RD_PORTS = 1;
parameter RD_CLK_ENABLE = 1'b1;
parameter RD_CLK_POLARITY = 1'b1;
parameter RD_TRANSPARENT = 1'b1;
parameter WR_PORTS = 1;
parameter WR_CLK_ENABLE = 1'b1;
parameter WR_CLK_POLARITY = 1'b1;
input [RD_PORTS-1:0] RD_CLK;
input [RD_PORTS-1:0] RD_EN;
input [RD_PORTS*ABITS-1:0] RD_ADDR;
output reg [RD_PORTS*WIDTH-1:0] RD_DATA;
input [WR_PORTS-1:0] WR_CLK;
input [WR_PORTS*WIDTH-1:0] WR_EN;
input [WR_PORTS*ABITS-1:0] WR_ADDR;
input [WR_PORTS*WIDTH-1:0] WR_DATA;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
parameter _TECHMAP_CONNMAP_RD_CLK_ = 0;
parameter _TECHMAP_CONNMAP_WR_CLK_ = 0;
parameter _TECHMAP_CONSTVAL_RD_EN_ = 0;
parameter _TECHMAP_BITS_CONNMAP_ = 0;
parameter _TECHMAP_CONNMAP_WR_EN_ = 0;
reg _TECHMAP_FAIL_;
integer k;
initial begin
_TECHMAP_FAIL_ <= 0;
// no initialized memories
if (INIT !== 1'bx)
_TECHMAP_FAIL_ <= 1;
// only map cells with only one read and one write port
if (RD_PORTS > 1 || WR_PORTS > 1)
_TECHMAP_FAIL_ <= 1;
// read enable must be constant high
if (_TECHMAP_CONSTVAL_RD_EN_[0] !== 1'b1)
_TECHMAP_FAIL_ <= 1;
// we expect positive read clock and non-transparent reads
if (RD_TRANSPARENT || !RD_CLK_ENABLE || !RD_CLK_POLARITY)
_TECHMAP_FAIL_ <= 1;
// we expect positive write clock
if (!WR_CLK_ENABLE || !WR_CLK_POLARITY)
_TECHMAP_FAIL_ <= 1;
// only one global write enable bit is supported
for (k = 1; k < WR_PORTS*WIDTH; k = k+1)
if (_TECHMAP_CONNMAP_WR_EN_[0 +: _TECHMAP_BITS_CONNMAP_] !=
_TECHMAP_CONNMAP_WR_EN_[k*_TECHMAP_BITS_CONNMAP_ +: _TECHMAP_BITS_CONNMAP_])
_TECHMAP_FAIL_ <= 1;
// read and write must be in same clock domain
if (_TECHMAP_CONNMAP_RD_CLK_ != _TECHMAP_CONNMAP_WR_CLK_)
_TECHMAP_FAIL_ <= 1;
// we don't do small memories or memories with offsets
if (OFFSET != 0 || ABITS < 4 || SIZE < 16)
_TECHMAP_FAIL_ <= 1;
end
genvar i;
generate
for (i = 0; i < WIDTH; i=i+1) begin:slice
\$__mem_4x1_generator #(
.ABITS(ABITS),
.SIZE(SIZE)
) bit_slice (
.CLK(RD_CLK),
.RD_ADDR(RD_ADDR),
.RD_DATA(RD_DATA[i]),
.WR_ADDR(WR_ADDR),
.WR_DATA(WR_DATA[i]),
.WR_EN(WR_EN[0])
);
end
endgenerate
endmodule
module \$__mem_4x1_generator (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN);
parameter ABITS = 4;
parameter SIZE = 16;
input CLK, WR_DATA, WR_EN;
input [ABITS-1:0] RD_ADDR, WR_ADDR;
output RD_DATA;
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
generate
if (ABITS > 4) begin
wire high_rd_data, low_rd_data;
if (SIZE > 2**(ABITS-1)) begin
\$__mem_4x1_generator #(
.ABITS(ABITS-1),
.SIZE(SIZE - 2**(ABITS-1))
) part_high (
.CLK(CLK),
.RD_ADDR(RD_ADDR[ABITS-2:0]),
.RD_DATA(high_rd_data),
.WR_ADDR(WR_ADDR[ABITS-2:0]),
.WR_DATA(WR_DATA),
.WR_EN(WR_EN && WR_ADDR[ABITS-1])
);
end else begin
assign high_rd_data = 1'bx;
end
\$__mem_4x1_generator #(
.ABITS(ABITS-1),
.SIZE(SIZE > 2**(ABITS-1) ? 2**(ABITS-1) : SIZE)
) part_low (
.CLK(CLK),
.RD_ADDR(RD_ADDR[ABITS-2:0]),
.RD_DATA(low_rd_data),
.WR_ADDR(WR_ADDR[ABITS-2:0]),
.WR_DATA(WR_DATA),
.WR_EN(WR_EN && !WR_ADDR[ABITS-1])
);
reg delayed_abit;
always @(posedge CLK)
delayed_abit <= RD_ADDR[ABITS-1];
assign RD_DATA = delayed_abit ? high_rd_data : low_rd_data;
end else begin
MEM4X1 _TECHMAP_REPLACE_ (
.CLK(CLK),
.RD_ADDR(RD_ADDR),
.RD_DATA(RD_DATA),
.WR_ADDR(WR_ADDR),
.WR_DATA(WR_DATA),
.WR_EN(WR_EN)
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int tata[2010], g[2010]; vector<pair<int, int>> edges; bitset<2001> secret[2001]; int find(int x) { return (tata[tata[x]] == tata[x] ? tata[x] : tata[x] = find(tata[x])); } void unite(int a, int b) { a = find(a); b = find(b); assert(a != b); if (g[a] >= g[b]) tata[b] = a, g[a] += g[b]; else tata[a] = b, g[b] += g[a]; } void test() { edges.clear(); int n, m; cin >> n >> m; for (int i = 0; i < n; i++) { tata[i] = i, g[i] = 1; secret[i] = bitset<2001>(); } for (int i = 0; i < m; i++) { string s; cin >> s; for (int j = 0; j < n; j++) secret[j][i] = s[j] - 0 ; } vector<pair<int, pair<int, int>>> ord; for (int i = 0; i < n; i++) for (int j = i + 1; j < n; j++) ord.push_back({(secret[i] & secret[j]).count(), {i, j}}); sort(ord.rbegin(), ord.rend()); for (auto i : ord) { if (find(i.second.first) == find(i.second.second)) continue; unite(i.second.first, i.second.second); edges.push_back({i.second.first, i.second.second}); } for (int i = 0; i < m; i++) { int nr = 0; for (int j = 0; j < n; j++) nr += secret[j][i]; for (auto j : edges) nr -= secret[j.first][i] & secret[j.second][i]; if (nr != 1) { cout << NO n ; return; } } cout << YES n ; for (auto i : edges) cout << i.first + 1 << << i.second + 1 << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) test(); return 0; } |
#include <bits/stdc++.h> using namespace std; using lld = int64_t; struct PT { lld x, y; PT() : x(0), y(0) {} PT(lld a, lld b) : x(a), y(b) {} PT operator-(const PT& a) const { return PT(x - a.x, y - a.y); } }; lld dot(const PT& a, const PT& b) { return a.x * b.x + a.y * b.y; } lld cross(const PT& a, const PT& b) { return a.x * b.y - a.y * b.x; } class ConvexHull_2D { private: vector<PT> dots; public: inline void init() { dots.clear(); } void insert(const PT& x) { dots.push_back(x); } void solve() { sort(begin(dots), end(dots), [](const PT& a, const PT& b) { return tie(a.x, a.y) < tie(b.x, b.y); }); vector<PT> stk((static_cast<int>((dots).size())) << 1); int top = 0; for (auto p : dots) { while (top >= 2 and cross(p - stk[top - 2], stk[top - 1] - stk[top - 2]) <= 0) top--; stk[top++] = p; } for (int i = (static_cast<int>((dots).size())) - 2, t = top + 1; i >= 0; i--) { while (top >= t and cross(dots[i] - stk[top - 2], stk[top - 1] - stk[top - 2]) <= 0) top--; stk[top++] = dots[i]; } stk.resize(top - 1); swap(stk, dots); } vector<PT> get() { return dots; } }; ConvexHull_2D cv; inline bool check(const vector<lld>&, const vector<lld>&); vector<lld> get_it(const vector<PT>& a) { vector<lld> ret; ret.push_back(dot(a.back() - a[0], a.back() - a[0])); ret.push_back(dot(a.back() - a[0], a[1] - a[0])); for (int i = 1; i < (static_cast<int>((a).size())) - 1; i++) { ret.push_back(dot(a[i - 1] - a[i], a[i - 1] - a[i])); ret.push_back(dot(a[i - 1] - a[i], a[i + 1] - a[i])); } ret.push_back(dot(a[(static_cast<int>((a).size())) - 2] - a[(static_cast<int>((a).size())) - 1], a[(static_cast<int>((a).size())) - 2] - a[(static_cast<int>((a).size())) - 1])); ret.push_back(dot(a[(static_cast<int>((a).size())) - 2] - a[(static_cast<int>((a).size())) - 1], a[0] - a[(static_cast<int>((a).size())) - 1])); return ret; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int n, m; cin >> n >> m; cv.init(); for (int i = 0; i < n; i++) { lld x, y; cin >> x >> y; cv.insert(PT(x, y)); } cv.solve(); vector<PT> one = cv.get(); cv.init(); for (int i = 0; i < m; i++) { lld x, y; cin >> x >> y; cv.insert(PT(x, y)); } cv.solve(); vector<PT> two = cv.get(); if ((static_cast<int>((one).size())) != (static_cast<int>((two).size())) or !check(get_it(one), get_it(two))) cout << NO << n ; else cout << YES << n ; return 0; } inline bool check(const vector<lld>& a, const vector<lld>& b) { for (int i = 0; i < (static_cast<int>((a).size())); i++) { bool flag = true; for (int j = 0; j < (static_cast<int>((b).size())); j++) { flag &= (a[(i + j) % (static_cast<int>((a).size()))] == b[j]); if (!flag) break; } if (flag) return true; } return false; } |
#include <bits/stdc++.h> using namespace std; struct item_t { int cost; int gain; int when; bool operator<(const item_t& other) const { return when < other.when; } bool operator<(const int t) const { return when < t; } } item[4000]; bool operator<(int v, const item_t& item) { return v < item.when; } struct dp_t { int maxgain[4000 + 1]; void update(int c, int g) { for (int b = 4000; b >= 0; b--) if (b + c <= 4000) maxgain[b + c] = max(maxgain[b + c], maxgain[b] + g); } } toleft[4000], toright[4000]; int main() { int n, window; scanf( %d %d , &n, &window); for (int i = 0; i < n; i++) { scanf( %d %d %d , &item[i].cost, &item[i].gain, &item[i].when); } sort(item, item + n); memset(toleft, 0, sizeof(toleft)); memset(toright, 0, sizeof(toright)); for (int i = 0; i < n; i++) { if (i - 1 >= 0 && item[i - 1].when / window == item[i].when / window) toleft[i] = toleft[i - 1]; toleft[i].update(item[i].cost, item[i].gain); } for (int i = n - 1; i >= 0; i--) { if (i + 1 < n && item[i + 1].when / window == item[i].when / window) toright[i] = toright[i + 1]; toright[i].update(item[i].cost, item[i].gain); } int nq; scanf( %d , &nq); for (int q = 0; q < nq; q++) { int vis_when, budget; scanf( %d %d , &vis_when, &budget); int b = vis_when; int a = b - window + 1; int lb = lower_bound(item, item + n, a) - item; int _ub = upper_bound(item, item + n, b) - item; int gain; if (lb == _ub) gain = 0; else { int ub1 = _ub - 1; if (item[lb].when / window != item[ub1].when / window) { gain = 0; for (int lbud = 0; lbud <= budget; lbud++) gain = max(gain, toright[lb].maxgain[lbud] + toleft[ub1].maxgain[budget - lbud]); } else { if (item[ub1].when / window == b / window) gain = toleft[ub1].maxgain[budget]; else gain = toright[lb].maxgain[budget]; } } printf( %d n , gain); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-9; const double EPS = 1e-9; int ar[] = {1, -1, 0, 0, 1, 1, -1, -1}; int ac[] = {0, 0, 1, -1, 1, -1, 1, -1}; int p[200005]; int q[200005]; void solve1(int n) { int k = 1; if (n & 1) { cout << NO n ; return; } cout << YES n ; while (k <= n) k *= 2; k /= 2; int last = n + 1; while (k != 0) { for (int i = k; i < last; i++) { p[i] = k - (i - k + 1); p[k - (i - k + 1)] = i; } last = min(last, k - (last - k)); k /= 2; } for (int i = 1; i <= n; i++) cout << p[i] << ; cout << n ; } void solve2(int n) { if (n < 6) { cout << NO n ; return; } int k = 1; while (2 * k <= n) k *= 2; if (n == k) { cout << NO n ; return; } cout << YES n ; if (n == 6) { cout << 3 6 2 5 1 4 n ; return; } for (int i = k; i < n; i++) q[i] = i + 1; q[n] = k; while (k != 4) { for (int i = k / 2; i < k - 1; i++) { q[i] = i + 1; } q[k - 1] = k / 2; k /= 2; } q[1] = 5; q[2] = 3; q[3] = 2; q[4] = 6; q[5] = 7; q[6] = 4; q[7] = 1; for (int i = 1; i <= n; i++) cout << q[i] << ; cout << n ; return; } int main() { ios_base::sync_with_stdio(false); int n; cin >> n; solve1(n); solve2(n); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, x, m, s; vector<int> f, t, f1; int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> k; for (int i = 0; i < n; i++) { cin >> x >> m; f.push_back(x); t.push_back(m); } for (int i = 0; i < n; i++) { if (t[i] < k) { f1.push_back(f[i]); } else { s = f[i] - (t[i] - k); f1.push_back(s); } } sort(f1.begin(), f1.end()); cout << f1.back(); } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; int n; int p[N]; pair<int, int> v[N]; void solve(int nx, int nnx) { int curr = 1; for (int i = 1; i <= n; i++) p[i] = 0; p[curr] = nx; p[nx] = nnx; curr = nx; bool okay = true; for (int i = 2; i <= n; i++) { if (v[curr].first == nnx) { if (!p[nnx]) p[nnx] = v[curr].second; nx = nnx; nnx = v[curr].second; curr = nx; } else if (v[curr].second == nnx) { if (!p[nnx]) p[nnx] = v[curr].first; nx = nnx; nnx = v[curr].first; curr = nx; } else { okay = false; break; } } curr = 1; for (int i = 1; i <= n; i++) { curr = p[curr]; } if (curr != 1) okay = false; if (okay) { curr = 1; for (int i = 1; i <= n; i++) { printf( %d , curr); curr = p[curr]; } exit(0); } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { int x, y; scanf( %d %d , &x, &y); v[i].first = x; v[i].second = y; } solve(v[1].first, v[1].second); solve(v[1].second, v[1].first); return 0; } |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.