text stringlengths 59 71.4k |
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#include <bits/stdc++.h> using namespace std; const long long mod = 998244353; const int maxn = 2e5 + 9; int a[maxn], b[maxn]; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); } for (int i = 1; i <= m; i++) { scanf( %d , &b[i]); } long long ans = 1; int l = n, r = n; for (int i = m; i >= 1; i--) { while (a[r] > b[i]) r--; if (a[r] != b[i] || r == 0) { ans = 0; break; } l = r; while (a[l] >= b[i]) l--; if (i != 1) ans = ans * (r - l) % mod; else if (l != 0) ans = 0; r = l; } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int k; cin >> k; char s[200]; vector<int> __v; __v.assign(1000000, 127); cin >> s; int n; cin >> n; set<int> n_del[ z - a + 1]; set<int>::iterator pos_n_del[ z - a + 1]; for (int i = 0; i < n; i++) { char c; int nc; cin >> nc >> c; set<int>::iterator it = n_del[c - a ].begin(); if (n_del[c - a ].empty() || nc <= *it) { n_del[c - a ].insert(nc - 1); continue; } nc -= *it; int pos = 0; while (it != n_del[c - a ].end() && nc > 0) { set<int>::iterator it0 = it; it++; if (it != n_del[c - a ].end()) { nc -= *it - *it0 - 1; } } if (nc > 0) { it--; pos = *it + nc; } else pos = *it + nc - 1; n_del[c - a ].insert(pos); } for (int i = 0; i < z - a + 1; ++i) { pos_n_del[i] = n_del[i].begin(); } int tSums[ z - a + 1] = {0}; for (int i = 0, len = strlen(s), j = 0; i < len * k; ++i, ++j) { if (j == len) j = 0; if (pos_n_del[s[j] - a ] != n_del[s[j] - a ].end() && *pos_n_del[s[j] - a ] == tSums[s[j] - a ]) { pos_n_del[s[j] - a ]++; } else cout << s[j]; tSums[s[j] - a ]++; } cout << endl; cerr << __v[rand() % __v.size()]; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 25; string str[maxn]; int a[maxn][maxn]; long long dp[1 << 20]; int mask[26], tot[26], big[26], cnt[26], candi[26]; int Min[maxn]; int main() { int n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> str[i]; } memset(Min, 0x3f, sizeof(Min)); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { cin >> a[i][j]; Min[i] = min(Min[i], a[i][j]); } } for (int i = 0; i < (1 << n); i++) { int tmp = 0; for (int j = 0; j < n; j++) { if (i >> j & 1) tmp += Min[j + 1]; } dp[i] = tmp; } for (int i = 1; i <= m; i++) { memset(mask, 0, sizeof(mask)); memset(tot, 0, sizeof(tot)); memset(big, 0, sizeof(big)); memset(cnt, 0, sizeof(cnt)); for (int j = 1; j <= n; j++) { int c = str[j][i - 1] - a ; cnt[c]++; mask[c] |= (1 << (j - 1)); tot[c] += a[j][i]; big[c] = max(big[c], a[j][i]); } int idx = 0; for (int j = 0; j < 26; j++) { if (cnt[j]) candi[idx++] = j; } for (int j = 0; j < (1 << n); j++) { for (int k = 0; k < idx; k++) { int u = candi[k]; dp[j | mask[u]] = min(dp[j | mask[u]], dp[j] + (tot[u] - big[u])); } } } cout << dp[(1 << n) - 1] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int w[40]; int main() { int m, n; cin >> m >> n; for (int i = 1; i <= n; i++) { cout << 1 << endl; cin >> w[i]; if (w[i] == 0) { return 0; } } int l = 1, r = m; int index = 1; while (l <= r) { int mid = (l + r) / 2; cout << mid << endl; int q; cin >> q; if (q == 0) return 0; if (q == w[(index - 1) % n + 1]) { l = mid + 1; } else { r = mid; } index++; } return 0; } |
#include <bits/stdc++.h> const int INF = 0x3f3f3f3f; const long long int INFLL = 0x3f3f3f3f3f3f3f3fll; long long int getint() { long long int ret = 0; bool f = 0; char c; while ((c = getchar()) < 0 || c > 9 ) if (c == - ) f ^= 1; while (c >= 0 && c <= 9 ) { ret = ret * 10 + c - 0 ; c = getchar(); } return f ? -ret : ret; } using namespace std; int k, p; long long int l, r; int mypow(int a, long long int b, int mod) { int ret = 1; for (; b; b >>= 1, a = (long long int)a * a % mod) if (b & 1) ret = (long long int)ret * a % mod; return ret; } int work() { k = getint(); l = getint(), r = getint(); p = getint(); if (p == 2) return (k & 1) ? 0 : 1; if (k % p == 0) return k & 1 ? mypow(mypow(2, p - 2, p), r - l, p) : 1; int t = mypow(2, l, p - 1), ans; t = mypow(k, t, p); if ((t - 1) % p == 0) ans = mypow(2, r - l + 1, p); else { int c = mypow(2, r - l + 1, p - 1); c = mypow(t, c, p); ans = (long long int)(c + p - 1) * mypow(t + p - 1, p - 2, p) % p; } if (k & 1) ans = (long long int)ans * mypow(mypow(2, p - 2, p), r - l, p) % p; return ans; } int main() { int T = getint(); while (T--) printf( %d n , work()); } |
#include <bits/stdc++.h> using namespace std; struct query { long long l, r, x; }; int n, a[109]; long long m; int main() { cin >> n >> m; vector<query> v; vector<long long> cp = {1LL << 60}; for (int i = 0; i < n; i++) { cin >> a[i]; int pr = sqrt(a[i]); for (int j = 1; j < pr; j++) { v.push_back(query{j, j + 1, (a[i] + j - 1) / j}); cp.push_back(j); } cp.push_back(pr); int r = (a[i] + pr - 1) / pr, ptr = pr; for (int j = r; j > 1; j--) { v.push_back(query{ptr, (a[i] + j - 2) / (j - 1), j}); ptr = v.back().r; cp.push_back(ptr); } v.push_back(query{ptr, 1LL << 60, 1}); } sort(cp.begin(), cp.end()); cp.erase(unique(cp.begin(), cp.end()), cp.end()); vector<long long> sum(cp.size()); for (query i : v) { int pl = lower_bound(cp.begin(), cp.end(), i.l) - cp.begin(); int pr = lower_bound(cp.begin(), cp.end(), i.r) - cp.begin(); sum[pl] += i.x; sum[pr] -= i.x; } for (int i = 1; i < cp.size(); i++) sum[i] += sum[i - 1]; long long ret = 0; for (int i = 0; i < cp.size() - 1; i++) { long long r = min(cp[i + 1] - 1, (m + sum[0]) / sum[i]); if (cp[i] <= r) ret = max(ret, r); } cout << ret << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t, m, n, z, s, q, p; cin >> t; while (t--) { cin >> n >> m; int a[n][m], z = 200, s = 0, p = 0; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { cin >> a[i][j]; if (a[i][j] < 0) { ++p; } z = min(z, abs(a[i][j])); s = s + abs(a[i][j]); } } if (p % 2 == 1) { s = s - 2 * z; cout << s << endl; } else cout << s << endl; } } |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rom_dispv.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.1.0 Build 196 10/24/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 2016 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
module rom_dispv (
address,
clock,
q);
input [5:0] address;
input clock;
output [5:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./mif/disp_v.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "36"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "6"
// Retrieval info: PRIVATE: WidthData NUMERIC "6"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./mif/disp_v.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "36"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "6"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 6 0 INPUT NODEFVAL "address[5..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 6 0 OUTPUT NODEFVAL "q[5..0]"
// Retrieval info: CONNECT: @address_a 0 0 6 0 address 0 0 6 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 6 0 @q_a 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_dispv.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_dispv.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_dispv.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_dispv.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_dispv_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_dispv_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
parameter UNCHANGE_START = 1'b0;
parameter UNCHANGE_CHECK = 1'b1;
reg [width-1:0] r_test_expr;
reg r_state;
integer i;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_start_event;
wire valid_test_expr;
assign valid_start_event = ~(start_event^start_event);
assign valid_test_expr = ~((^test_expr)^(^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=UNCHANGE_START;
end
`endif
`ifdef OVL_SHARED_CODE
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
case (r_state)
UNCHANGE_START: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if (start_event == 1'b1) begin
r_state <= UNCHANGE_CHECK;
r_test_expr <= test_expr;
i <= num_cks;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_open covered");
end
end
`endif // OVL_COVER_ON
end
end
UNCHANGE_CHECK: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (action_on_new_start != `OVL_IGNORE_NEW_START)
begin
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
end
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
// Count clock ticks
if (start_event == 1'b1) begin
if (action_on_new_start == `OVL_IGNORE_NEW_START && i > 0)
i <= i-1;
else if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
i <= num_cks;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
ovl_cover_t("window_resets covered");
end
end
end
`endif // OVL_COVER_ON
end
else if (action_on_new_start == `OVL_ERROR_ON_NEW_START) begin
i <= i-1;
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Illegal start event which has reoccured before completion of current window");
`endif // OVL_ASSERT_ON
end
end
else if (i > 0) begin
i <= i-1;
end
// go to start state on last check
if (i == 1 && !(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
r_state <= UNCHANGE_START;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_close covered");
end
end
`endif // OVL_COVER_ON
end
// Check that the property is true
`ifdef OVL_ASSERT_ON
if ((r_test_expr != test_expr) &&
!(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression changed value within num_cks from the start event asserted");
end
`endif // OVL_ASSERT_ON
r_test_expr <= test_expr;
end
endcase
end
else begin
r_state<=UNCHANGE_START;
i <= 0;
`ifdef OVL_INIT_REG
r_test_expr <= {width{1'b0}};
`endif
end
end // always
`endif // OVL_SHARED_CODE
|
#include <bits/stdc++.h> using namespace std; int Pow10(int deg) { int res = 1; while (deg-- > 0) res *= 10; return res; } int ToInt(const string& from) { int res = 0; for (int i = 0; i < ((int)(from).size()); ++i) res = 10 * res + from[i] - 0 ; return res; } void Solve() { string buf; do { getline(cin, buf); } while (((int)(buf).size()) < 4); string year = buf.substr(4); int lo = 1988; for (int i = ((int)(year).size()) - 1; i >= 0; --i) { int add = Pow10(((int)(year).size()) - i); int base = lo / add; int rem = ToInt(year.substr(i)); while (base * add + rem <= lo) ++base; lo = base * add + rem; } cout << lo << n ; } int main() { ios_base::sync_with_stdio(false); int q; cin >> q; while (q-- > 0) Solve(); return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:36:12 08/30/2017
// Design Name: messbauer_generator
// Module Name: E:/PLD/MessbauerTestEnvironment/messbaue_test_environment/tests/messbauer_generator_testbench_channelafter.v
// Project Name: messbaue_test_environment
// Target Device:
// Tool versions: Xilinx ISE 14.7
// Description:
//
// Verilog Test Fixture created by ISE for module: messbauer_generator
//
// Dependencies:
//
// Revision:
// Revision 1.0
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module messbauer_generator_testbench_channelafter;
// Inputs
reg aclk;
reg areset_n;
// Outputs
wire start;
wire channel;
// Instantiate the Unit Under Test (UUT)
messbauer_generator # (.CHANNEL_TYPE(2)) // channel after measurements
uut
(
.aclk(aclk),
.areset_n(areset_n),
.start(start),
.channel(channel)
);
initial begin
// Initialize Inputs
aclk = 0;
areset_n = 0;
// Wait 100 ns for global reset to finish
#100;
areset_n = 1;
// Add stimulus here
end
always
begin
#20 aclk = ~aclk;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Module: pci_userapp.v
// Project: CPCI (PCI Control FPGA)
// Description: PCI userapp module - implements the "user" section of the
// PCI interface
//
// Based upon userapp.v - generated by CoreGen
//
//
// Change history:
// 9/8/04 - Reduced from 3 BARs to 1 BAR
//
///////////////////////////////////////////////////////////////////////////////
module pci_userapp (
// Default PCI userapp ports
input FRAMEQ_N,
input TRDYQ_N,
input IRDYQ_N,
input STOPQ_N,
input DEVSELQ_N,
input [31:0] ADDR,
inout [31:0] ADIO,
input CFG_VLD,
input CFG_HIT,
output reg C_TERM,
output reg C_READY,
input ADDR_VLD,
input [7:0] BASE_HIT,
output reg S_TERM,
output reg S_READY,
output reg S_ABORT,
input S_WRDN,
input S_SRC_EN,
input S_DATA_VLD,
input [3:0] S_CBE,
input [15:0] PCI_CMD,
output REQUEST,
output REQUESTHOLD,
output COMPLETE,
output M_WRDN,
output reg M_READY,
input M_SRC_EN,
input M_DATA_VLD,
output [3:0] M_CBE,
input TIME_OUT,
output CFG_SELF,
input M_DATA,
input DR_BUS,
input I_IDLE,
input M_ADDR_N,
input IDLE,
input B_BUSY,
input S_DATA,
input BACKOFF,
output INTR_N,
input PERRQ_N,
input SERRQ_N,
output KEEPOUT,
input [39:0] CSR,
output [31:0] SUB_DATA,
input [255:0] CFG,
input RST,
input CLK,
// Additional ports
output reg reg_hit, // Indicates a hit on the CPCI registers
output reg cnet_hit, // Indicates a hit on the CNET address range
output reg reg_we, // Write enable signal for CPCI registers
output reg cnet_we, // Write enable signal for CNET
output [`PCI_ADDR_WIDTH-1:0] pci_addr, // The address of the current transaction
output [`PCI_DATA_WIDTH-1:0] pci_data, // The current data DWORD
output pci_data_vld, // Indicates data on pci_data is valid
output [`PCI_BE_WIDTH-1:0] pci_be, // Byte enables for current transaction
output pci_retry, // Retry signal from CSRs
output pci_fatal, // Fatal signal from CSRs
input [`PCI_DATA_WIDTH-1:0] reg_data, // Data to be read for registers
input [`PCI_DATA_WIDTH-1:0] cnet_data, // Data to be read for CNET
input cnet_retry, // Generate a retry for CNET
input cnet_reprog, // Is CNET being reprogrammed
input reg_vld, // Is the data on reg_data valid?
input cnet_vld, // Is the data on cnet_data valid?
input dma_vld, // Is the data on dma_data valid?
input intr_req, // Interrupt request
input dma_request, // Transaction request for DMA
input [`PCI_DATA_WIDTH-1:0] dma_data, // Data from DMA block
input [`PCI_BE_WIDTH-1:0] dma_cbe, // Command/byte enables for DMA block
output dma_data_vld, // Indicates data should be captured
output dma_src_en, // Next piece of data should be provided
// on dma_data
input dma_wrdn, // Logic high = Write, low = read
input dma_complete, // Complete signal
output dma_lat_timeout, // Latency timer has expired
output dma_addr_st, // Indicates that the core is
// currently in the address phase
output dma_data_st // Core in the data state
);
// synthesis syn_edif_bit_format = "%u<%i>"
// synthesis syn_edif_scalar_format = "%u"
// synthesis syn_noclockbuf = 1
// synthesis syn_hier = "hard"
/*******************************************************************
* This section contains the PCI interface decode.
*******************************************************************/
// ========================================
// Generate the xxx_hit and xxx_we signals
// ========================================
reg reg_hit_nxt, cnet_hit_nxt;
reg reg_we_nxt, cnet_we_nxt;
reg cnet_hit_d1;
always @(posedge CLK)
begin
cnet_hit_d1 <= cnet_hit;
end
always @(posedge CLK, posedge RST)
begin
if (RST)
begin
reg_hit <= 1'b0;
cnet_hit <= 1'b0;
reg_we <= 1'b0;
cnet_we <= 1'b0;
end
else
begin
reg_hit <= reg_hit_nxt;
cnet_hit <= cnet_hit_nxt;
reg_we <= reg_we_nxt;
cnet_we <= cnet_we_nxt;
end
end
always @*
begin
// Default to previous values
reg_hit_nxt = reg_hit;
reg_we_nxt = reg_we;
cnet_hit_nxt = cnet_hit;
cnet_we_nxt = cnet_we;
// Registers
// 4MB -- CPCI
if (BASE_HIT[0] && ADDR[`CPCI_CNET_ADDR_WIDTH-1:22] == 'h0)
begin
reg_hit_nxt = 1;
reg_we_nxt = S_WRDN;
end
else if (!S_DATA)
begin
reg_hit_nxt = 0;
reg_we_nxt = 0;
end
// CNET
if (BASE_HIT[0] && ADDR[26:22] != 5'b0)
begin
cnet_hit_nxt = 1;
cnet_we_nxt = S_WRDN;
end
else if (!S_DATA)
begin
cnet_hit_nxt = 0;
cnet_we_nxt = 0;
end
end
// ================================================================
// Generate the pci_addr, pci_data, pci_data_vld and pci_be signals
// ================================================================
assign pci_addr = ADDR;
assign pci_data = ADIO;
assign pci_data_vld = S_DATA_VLD;
assign pci_be = ~S_CBE;
// ================================================================
// Generate the pci_retry and pci_fatal signals
// ================================================================
assign pci_retry = CSR[36];
assign pci_fatal = CSR[39] | CSR[38];
// =================================================
// Generate the ADIO signal (and supporting signals)
// =================================================
wire [`PCI_DATA_WIDTH - 1:0] adio_nxt;
assign oe = (reg_hit && !reg_we && reg_vld) || (cnet_hit && !cnet_we && cnet_vld) || dma_vld;
//assign adio_nxt = reg_hit ? reg_data : (cnet_hit ? cnet_data : dma_data);
assign adio_nxt = (reg_hit & M_ADDR_N) ? reg_data : ((cnet_hit & M_ADDR_N) ? cnet_data : dma_data);
//assign adio_nxt = (/*!I_IDLE ||*/ !M_ADDR_N || (!cnet_hit && !reg_hit)) ? dma_data : (cnet_hit ? cnet_data : reg_data);
//assign adio_nxt = (!I_IDLE) ? dma_data : (cnet_hit ? cnet_data : reg_data);
assign ADIO = oe ? adio_nxt : 'bz;
// ===================================================
// Generate the dma_data_vld, dma_src_en, dma_lat_timeout,
// dma_addr_st and dma_data_st
// ===================================================
assign dma_data_vld = M_DATA_VLD;
assign dma_src_en = M_SRC_EN;
assign dma_lat_timeout = TIME_OUT;
assign dma_addr_st = !M_ADDR_N;
assign dma_data_st = M_DATA;
/*******************************************************************
* Target ABORT, READY and TERM signals
*******************************************************************/
reg s_ready_nxt;
reg s_term_nxt;
always @(posedge CLK or posedge RST)
begin : cannot_be_optimized_sa
if (RST) S_ABORT = 1'b1;
else S_ABORT = 1'b0;
end
always @(posedge CLK or posedge RST)
begin
if (RST) begin
S_READY <= 1'b0;
S_TERM <= 1'b0;
end
else begin
S_READY <= s_ready_nxt;
S_TERM <= s_term_nxt;
end
end
always @*
begin
s_ready_nxt = S_READY;
s_term_nxt = S_TERM;
if (RST || CSR[33]) begin
s_ready_nxt = 1'b0;
s_term_nxt = 1'b0;
end
else if (reg_hit_nxt && !reg_hit ||
cnet_hit_nxt && !cnet_hit && (cnet_we_nxt || cnet_reprog) ||
cnet_hit && !cnet_hit_d1) begin
// Generate a retry if the retry signal is asserted
s_ready_nxt = reg_hit_nxt | (cnet_hit_nxt & (!cnet_retry | cnet_reprog));
s_term_nxt = 1'b1;
end
end
/*******************************************************************
* Config READY and TERM signals
*******************************************************************/
always @(posedge CLK or posedge RST)
begin : cannot_be_optimized_ca
if (RST) C_READY = 1'b0;
else C_READY = 1'b1;
end
always @(posedge CLK or posedge RST)
begin : cannot_be_optimized_cb
if (RST) C_TERM = 1'b0;
else C_TERM = 1'b1;
end
/*******************************************************************
* Initiator signals
*******************************************************************/
assign REQUEST = dma_request;
assign REQUESTHOLD = 0;
assign COMPLETE = dma_complete;
assign M_WRDN = dma_wrdn;
assign M_CBE = dma_cbe;
always @(posedge CLK or posedge RST)
begin : cannot_be_optimized_f
if (RST) M_READY = 1'b0;
else M_READY = 1'b1;
end
/*******************************************************************
* Interrupt signals
*******************************************************************/
assign INTR_N = ~intr_req;
/*******************************************************************
* Miscelaneous unused signals
*******************************************************************/
assign CFG_SELF = 0;
assign KEEPOUT = 1'b0;
assign SUB_DATA = 'h0;
endmodule
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module feedforward_p_uOut_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1, clk);
parameter DWIDTH = 64;
parameter AWIDTH = 8;
parameter MEM_SIZE = 140;
input[AWIDTH-1:0] addr0;
input ce0;
input[DWIDTH-1:0] d0;
input we0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0];
always @(posedge clk)
begin
if (ce0)
begin
if (we0)
begin
ram[addr0] <= d0;
q0 <= d0;
end
else
q0 <= ram[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram[addr1];
end
end
endmodule
`timescale 1 ns / 1 ps
module feedforward_p_uOut(
reset,
clk,
address0,
ce0,
we0,
d0,
q0,
address1,
ce1,
q1);
parameter DataWidth = 32'd64;
parameter AddressRange = 32'd140;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
input we0;
input[DataWidth - 1:0] d0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
feedforward_p_uOut_ram feedforward_p_uOut_ram_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.d0( d0 ),
.we0( we0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; int dp[1000000 + 10], cnt[1000000 + 10]; int n; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { int a; scanf( %d , &a); int t = 0, temp = a; while (temp <= 1e6) { dp[temp] += t; cnt[temp]++; t++; temp = (temp << 1); } t = 0; while (a) { if (a & 1 && a != 1) { int nt = t + 2, temp = a - 1; while (temp <= 1e6) { dp[temp] += nt; cnt[temp]++; nt++; temp = (temp << 1); } } t++; a = (a >> 1); dp[a] += t; cnt[a]++; } } int ans = 0x3f3f3f3f; for (int i = 1; i <= 1e6; i++) { if (cnt[i] == n) ans = min(ans, dp[i]); } printf( %d n , ans); return 0; } |
//------------------------------------------------------------------
//-- Verilog template
//-- Top entity
//-- Board: icezum
//------------------------------------------------------------------
`default_nettype none
//-- Pwm circuit for the leds
//-- Just fade in and fade out the leds
module pwm_led(input wire clk, output wire [7:0] ledb);
//-- clk_1ms is 2**14 / 12000 ms = 1.37ms (not exactly 1ms)
wire clk_1ms;
wire clk_1s;
prescaler
#(.N(18))
T1S (
.clk_in(clk),
.ena(1'b1),
.clk_out(clk_1s)
);
prescaler
#(.N(6))
T1MS (
.clk_in(clk),
.ena(1'b1),
.clk_out(clk_1ms)
);
//-- 4 bits Counter.
reg [7:0] cont = 0;
always @ (posedge clk_1ms) begin
cont <= cont + 1;
end
//-- This register stores the pulse width (16 leves) in units of 1.37ms
wire [7:0] pulse_width;
reg [8:0] pulse_width_ud = 0;
always @ ( posedge clk_1s ) begin
pulse_width_ud <= pulse_width_ud + 9'b0_0000_1000;
end
wire a = pulse_width_ud[8];
assign pulse_width = pulse_width_ud[7:0] ^ {a,a,a,a,a,a,a,a};
//-- Comparator for generating the high and low states of the PWM signal
wire pwm;
assign pwm = (cont >= pulse_width) ? 0 : 1;
//-- The same pwm signal for all the leds
assign ledb[7:0] = { 8{pwm} };
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_nios2_qsys_0_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 12] <= 1'b0;
sr[11 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
`timescale 1ns/1ps
module tb(/*AUTOARG*/
// Outputs
hash_out, hash_done, fi_cnt,
// Inputs
m_endn
);
parameter LZF_WIDTH = 20;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input m_endn; // To data of data.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [LZF_WIDTH-1:0]fi_cnt; // From data of data.v
output hash_done; // From jhash_core of jhash_core.v
output [31:0] hash_out; // From jhash_core of jhash_core.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire ce; // From data of data.v
wire clk; // From data of data.v
wire [63:0] fi; // From data of data.v
wire fo_full; // From data of data.v
wire m_last; // From data of data.v
wire m_src_getn; // From jhash_in of jhash_in.v
wire rst; // From data of data.v
wire src_empty; // From data of data.v
wire stream_ack; // From jhash_core of jhash_core.v
wire [31:0] stream_data0; // From jhash_in of jhash_in.v
wire [31:0] stream_data1; // From jhash_in of jhash_in.v
wire [31:0] stream_data2; // From jhash_in of jhash_in.v
wire stream_done; // From jhash_in of jhash_in.v
wire [1:0] stream_left; // From jhash_in of jhash_in.v
wire stream_valid; // From jhash_in of jhash_in.v
// End of automatics
data data(/*AUTOINST*/
// Outputs
.clk (clk),
.rst (rst),
.src_empty (src_empty),
.ce (ce),
.fo_full (fo_full),
.m_last (m_last),
.fi (fi[63:0]),
.fi_cnt (fi_cnt[LZF_WIDTH-1:0]),
// Inputs
.m_src_getn (m_src_getn),
.m_endn (m_endn));
defparam data.LZF_FILE = "/tmp/decode.chk";
defparam data.LZF_DEBUG = 0;
defparam data.LZF_DELAY = 4;
defparam data.LZF_FIFO_AW = 5;
jhash_in jhash_in (/*AUTOINST*/
// Outputs
.m_src_getn (m_src_getn),
.stream_data0 (stream_data0[31:0]),
.stream_data1 (stream_data1[31:0]),
.stream_data2 (stream_data2[31:0]),
.stream_valid (stream_valid),
.stream_done (stream_done),
.stream_left (stream_left[1:0]),
// Inputs
.ce (ce),
.clk (clk),
.fi (fi[63:0]),
.fo_full (fo_full),
.m_last (m_last),
.rst (rst),
.src_empty (src_empty),
.stream_ack (stream_ack));
jhash_core jhash_core (/*AUTOINST*/
// Outputs
.stream_ack (stream_ack),
.hash_out (hash_out[31:0]),
.hash_done (hash_done),
// Inputs
.clk (clk),
.rst (rst),
.stream_data0 (stream_data0[31:0]),
.stream_data1 (stream_data1[31:0]),
.stream_data2 (stream_data2[31:0]),
.stream_valid (stream_valid),
.stream_done (stream_done),
.stream_left (stream_left[1:0]));
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0, tb);
@(posedge hash_done);
$write("out %h\n", hash_out);
$finish;
end
always @(posedge clk)
begin
if (jhash_core.round == 3'b101)
$write("%h, %h, %h\n", jhash_core.OA, jhash_core.OB, jhash_core.OC);
end
endmodule // top
// Local Variables:
// verilog-library-directories:("." "../../rtl/verilog/" "../../../encode/bench/verilog/")
// verilog-library-files:("")
// verilog-library-extensions:(".v" ".h")
// End: |
#include <bits/stdc++.h> using namespace std; int main() { cin.tie(0)->sync_with_stdio(0); string s; cin >> s; string t = s; int n = s.size(); auto check = [&]() { for (int i = 0; i <= 0; i++) { int mx0 = 0, mx1 = 0, mmx0 = 0, mmx1 = 0; for (int j = i; j < n; j++) { if (s[j] == 1 ) { mx1 = max(mx1 + 1, mx0 + 1); } else { mx0++; } if (t[j] == 1 ) { mmx1 = max(mmx1 + 1, mmx0 + 1); } else { mmx0++; } if (max(mx0, mx1) != max(mmx0, mmx1)) { return 0; } } } return 1; }; for (int i = 0; i < n; i++) { if (s[i] == 0 ) continue; s[i] = 0 ; if (!check()) { s[i] = 1 ; } } cout << s << n ; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr[n]; long long int w[n]; long long int h[n]; for (int i = 0; i < n; i++) { cin >> w[i]; cin >> h[i]; } arr[0] = max(w[0], h[0]); for (int i = 1; i < n; i++) { if (max(w[i], h[i]) > arr[i - 1]) { arr[i] = min(w[i], h[i]); } else { arr[i] = max(w[i], h[i]); } } for (int i = 1; i < n; i++) { if (arr[i] > arr[i - 1]) { cout << NO ; return 0; } } cout << YES ; return 0; } |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ae
//
// Generated
// by: wig
// on: Mon Oct 24 10:52:44 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ae.v,v 1.1 2005/10/25 13:15:36 wig Exp $
// $Date: 2005/10/25 13:15:36 $
// $Log: ent_ae.v,v $
// Revision 1.1 2005/10/25 13:15:36 wig
// Testcase result update
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.38 ,
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ae
//
// No `defines in this module
module ent_ae
//
// Generated module inst_ae
//
(
input wire [4:0] port_ae_2, // Use internally test2, no port generated
input wire [3:0] port_ae_5, // Bus, single bits go to outside
input wire [3:0] port_ae_6, // Conflicting definition
input wire [5:0] sig_07, // Conflicting definition, IN false!
input wire [8:2] sig_08, // VHDL intermediate needed (port name)
input wire [6:0] sig_i_ae, // Input Bus
output wire [7:0] sig_o_ae // Output Bus
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ae
//
//
//!End of Module/s
// --------------------------------------------------------------
|
#include <bits/stdc++.h> using namespace std; long long read() { long long ans = 0, f = 1; char c = getchar(); while (c > 9 || c < 0 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) { ans = ans * 10 + c - 0 ; c = getchar(); } return ans * f; } const long long N = 2e5 + 5; long long t, n, m, k, x[N], y[N], ans, mmax[N]; signed main() { t = read(); while (t--) { n = read(); k = read(); for (long long i = 1; i <= n; ++i) x[i] = read(); for (long long i = 1; i <= n; ++i) y[i] = read(); sort(x + 1, x + 1 + n); long long now = 0; ans = 0; for (long long i = 1; i <= n; ++i) { long long len = upper_bound(x + 1, x + 1 + n, x[i] + k) - x - 1; now = max(now, mmax[i]); ans = max(ans, len - i + 1 + now); mmax[len + 1] = max(mmax[len + 1], len - i + 1); } for (long long i = 1; i <= n + 1; ++i) mmax[i] = 0; printf( %lld n , ans); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int T; cin >> T; for (int i = 0; i < T; i++) { long long int n, x; cin >> n >> x; cout << 2 * x << endl; } } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; void solve() { int m, n; cin >> n >> m; vector<long long> v(n); for (int i = 0; i < n; i++) { string s; cin >> s; for (char c : s) { v[i] *= 2; v[i] += c - 0 ; } } long long need = ((1ll << m) - n - 1) / 2 + 1; long long cur = (1ll << (m - 1)) - 1; while (true) { long long left = cur + 1; bool flag = false; for (int i = 0; i < n; i++) { flag |= v[i] == cur; if (v[i] <= cur) { left--; } } if (left == need && !flag) { string s; for (int i = 0; i < m; i++) { s += (char)(cur % 2 + 0 ); cur /= 2; } reverse(s.begin(), s.end()); cout << s << endl; return; } else if (left < need) { cur++; } else { cur--; } } } int main() { int t; cin >> t; while (t--) { solve(); } } |
#include <bits/stdc++.h> using namespace std; int pen[2000005]; void update(int ind, int add) { while (ind < 2000005) { pen[ind] += add; ind += ind & (-ind); } } int query(int ind) { int ret = 0; while (ind > 0) { ret = ret + pen[ind]; ind = ind & (ind - 1); } return ret; } pair<int, int> r[2000005]; bool vis[2000005]; int getIndex(int y) { int sum = 0; int ind = 0; for (int i = 20; i >= 0; --i) { int nind = ind + (1 << i); if (nind < 2000005) { int nsum = sum + pen[nind]; if (nsum < y) { sum = nsum; ind = nind; } } } return ind + 1; } int out[2000005]; int mapping[2000005]; void solve() { int n, m; scanf( %d %d , &n, &m); int pos = m + 1; for (int i = 1; i <= n; ++i) { r[pos + i] = {-1, i}; update(pos + i, 1); } for (int i = 0; i < m; ++i) { int x, y; scanf( %d %d , &x, &y); int ind = getIndex(y); if (vis[x]) { if (r[ind].first != x) { printf( -1 n ); return; } } else { if (r[ind].first != -1) { printf( -1 n ); return; } } update(ind, -1); update(pos, 1); r[pos] = r[ind]; r[pos].first = x; vis[x] = true; --pos; } int p = 1; for (int i = 1; i <= n; ++i) { int ind = getIndex(i); if (r[ind].first == -1) { while (p <= n) { if (vis[p]) { ++p; } else { break; } } r[ind].first = p++; } out[r[ind].second] = r[ind].first; } for (int i = 1; i <= n; ++i) { printf( %d , out[i]); } } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int N = 300009; void swap(char *p, char *q) { char temp = *p; *p = *q; *q = temp; return; } long long int powxy(long long int x, long long int y) { if (y == 0) return 1; if (y % 2 == 1) return (x * powxy(x, y - 1)) % MOD; long long int t = powxy(x, y / 2) % MOD; return (t * t) % MOD; } vector<pair<int, int> > adj[N]; int dp[500005]; vector<int> ans[500001]; int main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { int ans = 1; string s; long long int n; cin >> n >> s; string temp = s; for (int i = 0; i < n; i++) { if ((i + 1) % 2 != 0) { string q = s.substr(0, i); if ((n - i + 1) % 2 == 0) reverse(q.begin(), q.end()); string p = s.substr(i, n - i) + q; if (p < temp) { temp = p; ans = i + 1; } } else { string q = s.substr(0, i); reverse(q.begin(), q.end()); if ((n - i + 1) % 2 != 0) reverse(q.begin(), q.end()); string p = s.substr(i, n - i) + q; if (p < temp) { temp = p; ans = i + 1; } } } cout << temp << n ; cout << ans << n ; } } |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module lab9_soc_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "lab9_soc_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 1: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 4,
the_altsyncram.numwords_a = 4,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 2;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; long long ans = t * (t + 1) / 2; if (ans % 2) cout << 1; else cout << 0; } |
/*
* 16-bit full adder
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_fulladd16 (
input [15:0] x,
input [15:0] y,
input ci,
output co,
output [15:0] z,
input s
);
// Continuous assignments
assign {co,z} = {1'b0, x} + {s, y} + ci;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long n, t, i, k, tam; int main() { while (scanf( %I64d , &n) > 0) { t = 0; tam = 0; for (i = 0; i < n; i++) { scanf( %I64d , &k); if (k % 2 != 0) { tam = k; } t += k; } if (t % 2 != 0) { printf( First n ); } else { if ((t - tam) % 2 != 0) printf( First n ); else printf( Second n ); } } return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pad_efc.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
//
// Module Name: pad_efc
// Description: Top level I/O Cluster
//
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which
// contains the time scale definition
module pad_efc (/*AUTOARG*/
// Inouts
vpp, vddo
);
inout vpp;
inout vddo;
endmodule // pad_misc
|
#include <bits/stdc++.h> using namespace std; const double eps(1e-8); int n, m; vector<long long> seq[100010]; long long a[100010]; int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %I64d , &a[i]); } long long initial = 0; a[0] = a[1]; a[m + 1] = a[m]; for (int i = 1; i <= m; i++) { initial += abs(a[i] - a[i - 1]); } for (int i = 1; i <= m; i++) { if (i - 1 != 0) { if (a[i] != a[i - 1]) seq[a[i]].push_back(a[i - 1]); } if (i != m) { if (a[i] != a[i + 1]) seq[a[i]].push_back(a[i + 1]); } } long long tmp; long long less; long long ini; long long answer = initial; for (int i = 1; i <= n; i++) { if (!seq[i].empty()) { sort(seq[i].begin(), seq[i].end()); less = 0; ini = 0; tmp = seq[i][(seq[i].size() + 1) / 2 - 1]; for (int j = 0; j <= seq[i].size() - 1; j++) { ini += abs(i - seq[i][j]); less += abs(tmp - seq[i][j]); } less = initial - ini + less; answer = min(answer, less); } } printf( %I64d n , answer); return 0; } |
#include <bits/stdc++.h> const long double pi = acos(-1); using namespace std; char a[105][105], row[105], col[105]; bool vis[105]; int main() { int n, m; cin >> n >> m; bool b = false; if (n == 1) { cout << 0 n ; return 0; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> a[i][j]; } } int res = 0, sum = 0; vector<char> ans; for (int k = 0; k < m; k++) { vector<string> ve; for (int i = 0; i < n; i++) { string s = ; for (int j = k; j >= 0; j--) { if (!vis[j]) s += a[i][j]; } reverse(s.begin(), s.end()); ve.push_back(s); } vector<string> vec; for (string s : ve) vec.push_back(s); sort(vec.begin(), vec.end()); if (ve == vec) { ans.push_back(a[0][k]); res++; sum++; continue; } vis[k] = true; sum = 0; } cout << m - res << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR2B_BLACKBOX_V
`define SKY130_FD_SC_HD__NOR2B_BLACKBOX_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor2b (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR2B_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int mxN = 5005; deque<deque<int> > Painter(mxN); vector<bool> Painted(mxN); vector<vector<int> > cnt(mxN, vector<int>(mxN, 0)); int main() { int n, q; cin >> n >> q; for (int i = 0; i < q; i++) { int l, r; cin >> l >> r; for (int j = l; j <= r; j++) { if ((int)Painter[j].size() < 3) { Painter[j].push_back(i); } Painted[j] = true; } } int total_sections = 0; for (int i = 1; i <= n; i++) { total_sections += (Painted[i] == true); } for (int i = 1; i <= n; i++) { if ((int)Painter[i].size() == 3 || (int)Painter[i].size() == 0) { continue; } assert((int)Painter[i].size() < 3); if ((int)Painter[i].size() == 1) { for (int j = 0; j < q; j++) { if (j == Painter[i].back()) { continue; } cnt[Painter[i].back()][j]++; cnt[j][Painter[i].back()]++; } } else { cnt[Painter[i].back()][Painter[i].front()]++; cnt[Painter[i].front()][Painter[i].back()]++; } } int Min = 1e9; for (int i = 0; i < q; i++) { for (int j = i + 1; j < q; j++) { Min = min(Min, cnt[i][j]); } } assert(Min != 1e9); cout << total_sections - Min << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int r, c, x, y; string s; cin >> r >> c >> x >> y; cin >> s; vector<int> visited(r * c + 1, 0); cout << 1 ; int t, n = s.size(); visited[c * (x - 1) + y] = 1; for (int i = 0; i < n - 1; i++) { if (s[i] == U && (x - 1 >= 1 && x - 1 <= r)) { x -= 1; t = c * (x - 1) + y; if (visited[t]) cout << 0 ; else { visited[t] = 1; cout << 1 ; } } else if (s[i] == U ) cout << 0 ; else if (s[i] == D && (x + 1 >= 1 && x + 1 <= r)) { x += 1; t = c * (x - 1) + y; if (visited[t]) cout << 0 ; else { visited[t] = 1; cout << 1 ; } } else if (s[i] == D ) cout << 0 ; else if (s[i] == L && (y - 1 >= 1 && y - 1 <= c)) { y -= 1; t = c * (x - 1) + y; if (visited[t]) cout << 0 ; else { visited[t] = 1; cout << 1 ; } } else if (s[i] == L ) cout << 0 ; else if (s[i] == R && (y + 1 >= 1 && y + 1 <= c)) { y += 1; t = c * (x - 1) + y; if (visited[t]) cout << 0 ; else { visited[t] = 1; cout << 1 ; } } else cout << 0 ; } t = 0; for (int i = 1; i <= r * c; i++) { if (visited[i] == 1) t++; } cout << r * c - t; return 0; } |
//======================================================================
//
// gcm_core.v
// ----------
// Galois Counter Mode core for AES.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2016, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module gcm_core(
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire done,
input wire enc_dec,
input wire keylen,
input wire [1 : 0] taglen,
output wire ready,
output wire valid,
output wire tag_correct,
input wire [255 : 0] key,
input wire [127 : 0] nonce,
input wire [127 : 0] block_in,
output wire [127 : 0] block_out,
input wire [127 : 0] tag_in,
output wire [127 : 0] tag_out
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam CTRL_IDLE = 3'h0;
localparam CTRL_INIT = 3'h1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [127 : 0] ctr_reg;
reg [127 : 0] ctr_new;
reg ctr_we;
reg [2 : 0] gcm_ctrl_reg;
reg [2 : 0] gcm_ctrl_new;
reg gcm_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg aes_init;
reg aes_next;
wire aes_encdec;
wire aes_ready;
wire aes_valid;
reg ctr_init;
reg ctr_next;
reg ghash_init;
reg ghash_next;
wire ghash_ready;
reg [127 : 0] ghash_h0;
reg [127 : 0] ghash_x;
wire [127 : 0] ghash_y;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
// We will only use the AES core for encryption. We hardwire
// the operation. This will allow the synthesis tool to remove
// the decryption datapath.
assign aes_encdec = 1;
//----------------------------------------------------------------
// Core instantiations.
//----------------------------------------------------------------
aes_core aes(
.clk(clk),
.reset_n(reset_n),
.encdec(aes_encdec),
.init(aes_init),
.next(aes_next),
.ready(aes_ready),
.key(key),
.keylen(keylen),
.block(block_in),
.result(block_out),
.result_valid(aes_valid)
);
gcm_ghash ghash(
.clk(clk),
.reset_n(reset_n),
.init(ghash_init),
.next(ghash_next),
.ready(ghash_ready),
.h0(ghash_h0),
.x(ghash_x),
.y(ghash_y)
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
integer i;
if (!reset_n)
begin
ctr_reg <= 64'h0;
gcm_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (ctr_we)
ctr_reg <= ctr_new;
if (gcm_ctrl_we)
gcm_ctrl_reg <= gcm_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// ctr_logic
//----------------------------------------------------------------
always @*
begin : ctr_logic
ctr_new = 128'h0;
ctr_we = 0;
if (ctr_init)
begin
ctr_new = nonce;
ctr_we = 1;
end
if (ctr_next)
begin
ctr_new = {ctr_reg[127 : 64], ctr_reg[63 : 0] + 1'b1};
ctr_we = 1;
end
end // ctr_logic
//----------------------------------------------------------------
// gcm_core_ctrl_fsm
//----------------------------------------------------------------
always @*
begin : gcm_core_ctrl_fsm
aes_init = 0;
aes_next = 0;
ctr_init = 0;
ctr_next = 0;
gcm_ctrl_new = CTRL_IDLE;
gcm_ctrl_we = 0;
case (gcm_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
gcm_ctrl_new = CTRL_INIT;
gcm_ctrl_we = 1;
end
end
CTRL_INIT:
begin
gcm_ctrl_new = CTRL_IDLE;
gcm_ctrl_we = 1;
end
default:
begin
end
endcase // case (gcm_ctrl_reg)
end // gcm_core_ctrl_fsm
endmodule // gcm_core
//======================================================================
// EOF gcm_core.v
//======================================================================
|
//==================================================================================================
// Filename : musb_exmem_register.v
// Created On : 2014-09-27 20:25:03
// Last Modified : 2015-05-31 13:04:37
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email :
//
// Description : Pipeline register: EX -> MEM
//==================================================================================================
module musb_exmem_register(
input clk, // main clock
input rst, // main reset
input [31:0] ex_alu_result, // ALU result
input [31:0] ex_mem_store_data, // data to memory
input [4:0] ex_gpr_wa, // GPR write address
input ex_gpr_we, // GPR write enable
input ex_mem_to_gpr_select, // Select MEM/ALU to GPR
input ex_mem_write, // Mem write operation
input ex_mem_byte, // byte access
input ex_mem_halfword, // halfword access
input ex_mem_data_sign_ext, // Sign/Zero extend data from memory
input [31:0] ex_exception_pc,
input ex_movn,
input ex_movz,
input ex_b_is_zero,
input ex_llsc,
input ex_kernel_mode,
input ex_is_bds,
input ex_trap,
input ex_trap_condition,
input ex_mem_exception_source,
input ex_flush, // clean
input ex_stall, // stall EX stage
input mem_stall, // stall MEM stage
output reg [31:0] mem_alu_result, // Same signals, but on mem stage
output reg [31:0] mem_mem_store_data, //
output reg [4:0] mem_gpr_wa, //
output reg mem_gpr_we, //
output reg mem_mem_to_gpr_select, //
output reg mem_mem_write, //
output reg mem_mem_byte, //
output reg mem_mem_halfword, //
output reg mem_mem_data_sign_ext, //
output reg [31:0] mem_exception_pc,
output reg mem_llsc,
output reg mem_kernel_mode,
output reg mem_is_bds,
output reg mem_trap,
output reg mem_trap_condition,
output reg mem_mem_exception_source
);
// Check for MOVN or MOVZ instruction
wire mov_reg_write = (ex_movn & ~ex_b_is_zero) | (ex_movz & ex_b_is_zero);
//--------------------------------------------------------------------------
// Propagate signals
// Clear WE and Write signals only, on EX stall.
//--------------------------------------------------------------------------
always @(posedge clk) begin
mem_alu_result <= (rst) ? 32'b0 : ((mem_stall) ? mem_alu_result : ex_alu_result);
mem_mem_store_data <= (rst) ? 32'b0 : ((mem_stall) ? mem_mem_store_data : ex_mem_store_data);
mem_gpr_wa <= (rst) ? 5'b0 : ((mem_stall) ? mem_gpr_wa : ex_gpr_wa);
mem_gpr_we <= (rst) ? 1'b0 : ((mem_stall) ? mem_gpr_we : ((ex_stall | ex_flush) ? 1'b0 : ((ex_movz | ex_movn) ? mov_reg_write : ex_gpr_we)));
mem_mem_to_gpr_select <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_to_gpr_select : ((ex_stall | ex_flush) ? 1'b0 : ex_mem_to_gpr_select)); // test
mem_mem_write <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_write : ((ex_stall | ex_flush) ? 1'b0 : ex_mem_write));
mem_mem_byte <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_byte : ex_mem_byte);
mem_mem_halfword <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_halfword : ex_mem_halfword);
mem_mem_data_sign_ext <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_data_sign_ext : ex_mem_data_sign_ext);
mem_exception_pc <= (rst) ? 32'b0 : ((mem_stall) ? mem_exception_pc : ex_exception_pc);
mem_llsc <= (rst) ? 1'b0 : ((mem_stall) ? mem_llsc : ex_llsc);
mem_kernel_mode <= (rst) ? 1'b0 : ((mem_stall) ? mem_kernel_mode : ex_kernel_mode);
mem_is_bds <= (rst) ? 1'b0 : ((mem_stall) ? mem_is_bds : ex_is_bds);
mem_trap <= (rst) ? 1'b0 : ((mem_stall) ? mem_trap : ((ex_stall | ex_flush) ? 1'b0 : ex_trap));
mem_trap_condition <= (rst) ? 1'b0 : ((mem_stall) ? mem_trap_condition : ex_trap_condition);
mem_mem_exception_source <= (rst) ? 1'b0 : ((mem_stall) ? mem_mem_exception_source : ((ex_stall | ex_flush) ? 1'b0 : ex_mem_exception_source));
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { stack<char> s; int n, count = 0; char c; cin >> n; for (int i = 0; i < n; i++) { cin >> c; if (s.empty()) s.push(c); else if (s.top() == c) { s.pop(); s.push(c); count++; } else s.push(c); } cout << count << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); string s; cin >> s; long long l = s.length(); long long ans = 0; for (long long i = l - 1; i >= 1; i--) { ans = ans + pow(2, i); } for (long long i = 0; i < l; i++) { if (s[i] == 7 ) { ans = ans + pow(2, l - i - 1); } } cout << ans + 1 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; map<int, int> sg; map<int, bool> us; int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { int x, d; cin >> x >> d; sg[x] = x + d; us[x] = true; if (us[x + d] && sg[x + d] == x && sg[x] == x + d) { cout << YES n ; return 0; } } cout << NO ; } |
#include <bits/stdc++.h> using namespace std; long long power(long long a, long long b) { long long x = 1, y = a; while (b > 0) { if (b % 2) { x = (x * y) % 1000000007; } y = (y * y) % 1000000007; b /= 2; } return x % 1000000007; } int main() { ios_base::sync_with_stdio(false), cin.tie(0), cout.tie(0); long long int t = 1, n, m, i, j, k, sum = 0; while (t--) { cin >> n; vector<long long int> v(n); for (i = 0; i < n; i++) cin >> v[i]; sort((v).begin(), (v).end()); for (i = 1; i < n; i++) { v[i] += v[i - 1]; } for (i = 1; i < n; i++) { sum = (sum + (power(2, i - 1) * ((v[n - 1] - v[i - 1] - v[n - i - 1]) % 1000000007)) % 1000000007) % 1000000007; sum = sum % 1000000007; } cout << sum; } return 0; } |
#include <bits/stdc++.h> using namespace std; int b[100]; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; b[a[i]]++; } int f = 0, h = -1; for (int i = 1; i <= 100; i++) { if (b[i] == 1) { f++; } else if (b[i] > 2) { h = i; } } if (f % 2 == 0) { cout << YES n ; int r = f / 2; for (int i = 0; i < n; i++) { if (b[a[i]] == 1) { if (r > 0) { cout << A ; r--; } else { cout << B ; } } else { cout << A ; } } } else { if (h == -1) { return cout << NO , 0; } int y = 0; cout << YES n ; int r = f / 2; for (int i = 0; i < n; i++) { if ((a[i] != h) || (a[i] == h && y != 0)) { if (b[a[i]] == 1) { if (r > 0) { cout << A ; r--; } else { cout << B ; } } else { cout << B ; } } else { cout << A ; y++; } } } } |
#include <bits/stdc++.h> using namespace std; int main() { string s1, s2, s3; long long a = 0, b = 0, c = 0; string unia; cin >> s1 >> s2 >> s3; long long *trm1, *trm2; string *uni; uni = &unia; if (s1[0] == A ) trm1 = &a; else if (s1[0] == B ) trm1 = &b; else if (s1[0] == C ) trm1 = &c; if (s1[2] == A ) trm2 = &a; else if (s1[2] == B ) trm2 = &b; else if (s1[2] == C ) trm2 = &c; if (s1[1] == > ) { *uni += s1[0]; *trm1 = *trm2 + 1 + *trm1; } else if (s1[1] == < ) { *uni += s1[2]; *trm2 = *trm1 + 1 + *trm2; } if (s2[0] == A ) trm1 = &a; else if (s2[0] == B ) trm1 = &b; else if (s2[0] == C ) trm1 = &c; if (s2[2] == A ) trm2 = &a; else if (s2[2] == B ) trm2 = &b; else if (s2[2] == C ) trm2 = &c; if (s2[1] == > ) { *uni += s2[0]; *trm1 = *trm2 + 1 + *trm1; } else if (s2[1] == < ) { *uni += s2[2]; *trm2 = *trm1 + 1 + *trm2; } if (s3[0] == A ) trm1 = &a; else if (s3[0] == B ) trm1 = &b; else if (s3[0] == C ) trm1 = &c; if (s3[2] == A ) trm2 = &a; else if (s3[2] == B ) trm2 = &b; else if (s3[2] == C ) trm2 = &c; if (s3[1] == > ) { *uni += s3[0]; *trm1 = *trm2 + 1 + *trm1; } else if (s3[1] == < ) { *uni += s3[2]; *trm2 = *trm1 + 1 + *trm2; } long long unicnt = 0; long long repcnt = 0; for (long long i = 0; i < 3; i++) { if (i == 0) unicnt++; else { long long j; for (j = i - 1; j >= 0; j = j - 1) { if (unia[i] == unia[j]) { repcnt++; break; } } if (j < 0) unicnt++; } } if (repcnt != 1) { cout << Impossible << endl; } else { vector<pair<long long, char>> m; m.push_back(make_pair(a, A )); m.push_back(make_pair(b, B )); m.push_back(make_pair(c, C )); sort(m.begin(), m.end()); for (long long i = 0; i < m.size(); i++) { cout << m[i].second; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DFSTP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfstp (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <typename T> T fact(T n) { return (n == 1 || n == 0) ? 1 : n * fact(n - 1); } bool sortbysec(const pair<int, int> &a, const pair<int, int> &b) { return (a.second < b.second); } int subarraysum(int arr[], int n, int sum) { int curr_sum = arr[0], start = 0, i; for (i = 1; i <= n; i++) { while (curr_sum > sum && start < i - 1) { curr_sum = curr_sum - arr[start]; start++; } if (curr_sum == sum) { if (start != i - 1) return 1; } if (i < n) curr_sum = curr_sum + arr[i]; } return 0; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; int c = 0; for (int i = 0; i < n; i++) { int x = a[i]; if (subarraysum(a, n, x)) c++; } cout << c << endl; } return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_adcfifo_dma (
axi_clk,
axi_drst,
axi_dvalid,
axi_ddata,
axi_dready,
axi_xfer_status,
dma_clk,
dma_wr,
dma_wdata,
dma_wready,
dma_xfer_req,
dma_xfer_status);
// parameters
parameter AXI_DATA_WIDTH = 512;
parameter DMA_DATA_WIDTH = 64;
parameter DMA_READY_ENABLE = 1;
localparam DMA_MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;
localparam DMA_ADDR_WIDTH = 8;
localparam AXI_ADDR_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDR_WIDTH - 1) :
((DMA_MEM_RATIO == 4) ? (DMA_ADDR_WIDTH - 2) : (DMA_ADDR_WIDTH - 3));
// adc write
input axi_clk;
input axi_drst;
input axi_dvalid;
input [AXI_DATA_WIDTH-1:0] axi_ddata;
output axi_dready;
input [ 3:0] axi_xfer_status;
// dma read
input dma_clk;
output dma_wr;
output [DMA_DATA_WIDTH-1:0] dma_wdata;
input dma_wready;
input dma_xfer_req;
output [ 3:0] dma_xfer_status;
// internal registers
reg [AXI_ADDR_WIDTH-1:0] axi_waddr = 'd0;
reg [ 2:0] axi_waddr_rel_count = 'd0;
reg axi_waddr_rel_t = 'd0;
reg [AXI_ADDR_WIDTH-1:0] axi_waddr_rel = 'd0;
reg [ 2:0] axi_raddr_rel_t_m = 'd0;
reg [DMA_ADDR_WIDTH-1:0] axi_raddr_rel = 'd0;
reg [DMA_ADDR_WIDTH-1:0] axi_addr_diff = 'd0;
reg axi_dready = 'd0;
reg dma_rst = 'd0;
reg [ 2:0] dma_waddr_rel_t_m = 'd0;
reg [AXI_ADDR_WIDTH-1:0] dma_waddr_rel = 'd0;
reg dma_rd = 'd0;
reg dma_rd_d = 'd0;
reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;
reg [DMA_ADDR_WIDTH-1:0] dma_raddr = 'd0;
reg [ 2:0] dma_raddr_rel_count = 'd0;
reg dma_raddr_rel_t = 'd0;
reg [DMA_ADDR_WIDTH-1:0] dma_raddr_rel = 'd0;
// internal signals
wire [DMA_ADDR_WIDTH:0] axi_addr_diff_s;
wire axi_raddr_rel_t_s;
wire [DMA_ADDR_WIDTH-1:0] axi_waddr_s;
wire dma_waddr_rel_t_s;
wire [DMA_ADDR_WIDTH-1:0] dma_waddr_rel_s;
wire dma_wready_s;
wire dma_rd_s;
wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;
// write interface
always @(posedge axi_clk) begin
if (axi_drst == 1'b1) begin
axi_waddr <= 'd0;
axi_waddr_rel_count <= 'd0;
axi_waddr_rel_t <= 'd0;
axi_waddr_rel <= 'd0;
end else begin
if (axi_dvalid == 1'b1) begin
axi_waddr <= axi_waddr + 1'b1;
end
axi_waddr_rel_count <= axi_waddr_rel_count + 1'b1;
if (axi_waddr_rel_count == 3'd7) begin
axi_waddr_rel_t <= ~axi_waddr_rel_t;
axi_waddr_rel <= axi_waddr;
end
end
end
assign axi_addr_diff_s = {1'b1, axi_waddr_s} - axi_raddr_rel;
assign axi_raddr_rel_t_s = axi_raddr_rel_t_m[2] ^ axi_raddr_rel_t_m[1];
assign axi_waddr_s = (DMA_MEM_RATIO == 2) ? {axi_waddr, 1'd0} :
((DMA_MEM_RATIO == 4) ? {axi_waddr, 2'd0} : {axi_waddr, 3'd0});
always @(posedge axi_clk) begin
if (axi_drst == 1'b1) begin
axi_raddr_rel_t_m <= 'd0;
axi_raddr_rel <= 'd0;
axi_addr_diff <= 'd0;
axi_dready <= 'd0;
end else begin
axi_raddr_rel_t_m <= {axi_raddr_rel_t_m[1:0], dma_raddr_rel_t};
if (axi_raddr_rel_t_s == 1'b1) begin
axi_raddr_rel <= dma_raddr_rel;
end
axi_addr_diff <= axi_addr_diff_s[DMA_ADDR_WIDTH-1:0];
if (axi_addr_diff >= 180) begin
axi_dready <= 1'b0;
end else if (axi_addr_diff <= 8) begin
axi_dready <= 1'b1;
end
end
end
// read interface
assign dma_waddr_rel_t_s = dma_waddr_rel_t_m[2] ^ dma_waddr_rel_t_m[1];
assign dma_waddr_rel_s = (DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} :
((DMA_MEM_RATIO == 4) ? {dma_waddr_rel, 2'd0} : {dma_waddr_rel, 3'd0});
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rst <= 1'b1;
dma_waddr_rel_t_m <= 'd0;
dma_waddr_rel <= 'd0;
end else begin
dma_rst <= 1'b0;
dma_waddr_rel_t_m <= {dma_waddr_rel_t_m[1:0], axi_waddr_rel_t};
if (dma_waddr_rel_t_s == 1'b1) begin
dma_waddr_rel <= axi_waddr_rel;
end
end
end
assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready;
assign dma_rd_s = (dma_raddr == dma_waddr_rel_s) ? 1'b0 : dma_wready_s;
always @(posedge dma_clk) begin
if (dma_xfer_req == 1'b0) begin
dma_rd <= 'd0;
dma_rd_d <= 'd0;
dma_rdata_d <= 'd0;
dma_raddr <= 'd0;
dma_raddr_rel_count <= 'd0;
dma_raddr_rel_t <= 'd0;
dma_raddr_rel <= 'd0;
end else begin
dma_rd <= dma_rd_s;
dma_rd_d <= dma_rd;
dma_rdata_d <= dma_rdata_s;
if (dma_rd_s == 1'b1) begin
dma_raddr <= dma_raddr + 1'b1;
end
dma_raddr_rel_count <= dma_raddr_rel_count + 1'b1;
if (dma_raddr_rel_count == 3'd7) begin
dma_raddr_rel_t <= ~dma_raddr_rel_t;
dma_raddr_rel <= dma_raddr;
end
end
end
// instantiations
ad_mem_asym #(
.ADDR_WIDTH_A (AXI_ADDR_WIDTH),
.DATA_WIDTH_A (AXI_DATA_WIDTH),
.ADDR_WIDTH_B (DMA_ADDR_WIDTH),
.DATA_WIDTH_B (DMA_DATA_WIDTH))
i_mem_asym (
.clka (axi_clk),
.wea (axi_dvalid),
.addra (axi_waddr),
.dina (axi_ddata),
.clkb (dma_clk),
.addrb (dma_raddr),
.doutb (dma_rdata_s));
ad_axis_inf_rx #(.DATA_WIDTH(DMA_DATA_WIDTH)) i_axis_inf (
.clk (dma_clk),
.rst (dma_rst),
.valid (dma_rd_d),
.last (1'd0),
.data (dma_rdata_d),
.inf_valid (dma_wr),
.inf_last (),
.inf_data (dma_wdata),
.inf_ready (dma_wready));
up_xfer_status #(.DATA_WIDTH(4)) i_xfer_status (
.up_rstn (~dma_rst),
.up_clk (dma_clk),
.up_data_status (dma_xfer_status),
.d_rst (axi_drst),
.d_clk (axi_clk),
.d_data_status (axi_xfer_status));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_b
//
// Generated
// by: wig
// on: Fri Jul 15 16:37:20 2005
// cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_b.v,v 1.4 2005/11/30 14:04:17 wig Exp $
// $Date: 2005/11/30 14:04:17 $
// $Log: ent_b.v,v $
// Revision 1.4 2005/11/30 14:04:17 wig
// Updated testcase references
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
//
// Generator: mix_0.pl Revision: 1.36 ,
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_b
//
// No `defines in this module
module ent_b
//
// Generated module inst_b
//
(
port_b_1,
port_b_3,
port_b_4,
port_b_5_1,
port_b_5_2,
port_b_6i,
port_b_6o,
sig_07,
sig_08
);
// Generated Module Inputs:
input port_b_1;
input port_b_3;
input port_b_5_1;
input port_b_5_2;
input [3:0] port_b_6i;
input [5:0] sig_07;
input [8:2] sig_08;
// Generated Module Outputs:
output port_b_4;
output [3:0] port_b_6o;
// Generated Wires:
wire port_b_1;
wire port_b_3;
wire port_b_4;
wire port_b_5_1;
wire port_b_5_2;
wire [3:0] port_b_6i;
wire [3:0] port_b_6o;
wire [5:0] sig_07;
wire [8:2] sig_08;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_ba
ent_ba inst_ba (
);
// End of Generated Instance Port Map for inst_ba
// Generated Instance Port Map for inst_bb
ent_bb inst_bb (
);
// End of Generated Instance Port Map for inst_bb
endmodule
//
// End of Generated Module rtl of ent_b
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`include "DEF.v"
module excute(clock,
in_op, in_src1, in_src2, in_dst, in_imm,
out_dst, out_dst_data, write_dst,
dmem_address, dmem_data, dmem_write, dmem_read,
cnt_ex, cnt_read, in_databus, in_databus2
);
input clock;
input [31:0] in_op;
input signed [31:0] in_src1, in_src2;
input [4:0] in_dst;
input [31:0] in_imm;
inout [31:0] dmem_data;
input [63:0] in_databus, in_databus2;
output [31:0] dmem_address;
output [4:0] out_dst;
output [31:0] out_dst_data;
output write_dst;
output dmem_write;
output dmem_read;
output cnt_read;
output cnt_ex;
reg [31:0] opcode;
reg signed [31:0] source1, source2;
reg [4:0] destination;
reg signed [31:0] immediate;
reg signed [31:0] result;
reg r_write_dst;
reg r_dmem_write, r_dmem_read;
reg r_cnt_read;
reg r_cnt_ex;
assign out_dst = destination;
assign out_dst_data = result;
assign write_dst = r_write_dst;
assign dmem_write = r_dmem_write;
assign dmem_read = r_dmem_read;
assign dmem_address = immediate;
assign dmem_data = r_dmem_read ? 32'hz : source2;
assign cnt_read = r_cnt_read;
assign cnt_ex = r_cnt_ex;
always @(posedge clock)
begin
r_cnt_read <= 0;
r_cnt_ex <= 0;
if(in_databus[63:48] !== 16'b100000_00000_00000 &&
in_databus2[63:48] !== 16'b100000_00000_00000)
begin
//$display("cycle=%d\ninstruction=%d\n", count_cycle, count_instr);
//$stop;
/*#0.001
$display("op:%d result:%d source1:%d source2:%d imm:%d dst:%d\n", opcode, result, source1, source2, immediate, destination);
*/
//$monitor("op:%d result:%d source1:%d source2:%d imm:%d dst:%d\n", opcode, result, source1, source2, immediate, destination);
//$display("r_dmem_write:%d %d\n", r_dmem_write, dmem_write);
//$monitor("r_dmem_write:%d %d\n", r_dmem_write, dmem_write);
#0.001
if(!(opcode === 1 && source2 === 0 && immediate === 0))
begin
r_cnt_ex <= 1;
end
casex(opcode)
1: /* sll */
begin
result <= source2 << immediate;
#0.010 r_write_dst <= 1;
end
2: /* addi */
begin
result <= immediate[15:15]===1 ? source1 - (~{16'b1111111111111111,immediate[15:0]}+1) : source1 + immediate;
#0.010 r_write_dst <= 1;
end
3: /* mul */
begin
result <= source1 * source2;
/*
#0.001 $display("MUL !!!! %d %d %d\n", result, source1, source2);
$stop;
*/
#0.010 r_write_dst <= 1;
end
4: /* move */
begin
result <= source1;
#0.010 r_write_dst <= 1;
end
5: /* movei */
begin
result <= immediate;
#0.010 r_write_dst <= 1;
end
6: /* add */
begin
result <= source1 + source2;
#0.010 r_write_dst <= 1;
end
9: /* lw */
begin
r_dmem_read <= 1;
//#0.010 $display("dmem_data:%d dmem_read:%d dmem_address:%d\n", dmem_data, dmem_read, dmem_address);
#0.010 result <= dmem_data;
/*
$display("dmem_data:%d dmem_read:%d dmem_address:%d\n", dmem_data, dmem_read, dmem_address);
$stop;
*/
#0.010 r_write_dst <= 1;
end
10: /* sw */
begin
#0.010 r_dmem_write <= 1;
//$display("r_dmem_write:%d %d\n", r_dmem_write, dmem_write);
//$monitor("r_dmem_write:%d %d\n", r_dmem_write, dmem_write);
end
12: /* halt */
begin
#0.001
r_cnt_read <= 1;
#0.498
$display("halt\n");
$stop;
end
13: /* muli */
begin
result <= source1 * (immediate[15:15]==1 ? -(~{16'b1111111111111111,immediate[15:0]}+1) : immediate);
#0.010 r_write_dst <= 1;
end
14: /* jal */
begin
result <= immediate;
#0.010 r_write_dst <= 1;
//$display("jal31: %d %d\n", destination, result);
//$stop;
end
15: /* ori */
begin
result <= source1 | immediate;
//$display("ori miao!!!!!!! %d %d %d\n", source1, immediate, source1 | immediate);
#0.010 r_write_dst <= 1;
end
16: /* lui */
begin
result <= immediate << 16;
//$display("lui miao!!!!!!! %d %d\n", immediate, immediate << 16);
#0.010 r_write_dst <= 1;
end
endcase
end
end
always @(negedge clock)
begin
#0.010
if(in_databus[63:48] !== 16'b100000_00000_00000)
begin
opcode <= in_op;
source1 <= in_src1;
source2 <= in_src2;
immediate <= in_imm;
destination <= in_dst;
r_write_dst <= 0;
r_dmem_write <= 0;
r_dmem_read <= 0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> T gcd(T first, T second) { while (second > 0) { first %= second; swap(first, second); } return first; } template <class T> T lcm(T a, T b) { return a / gcd(a, b) * b; } template <class _T> inline _T sqr(const _T &first) { return first * first; } template <class _T> inline string tostr(const _T &a) { ostringstream os( ); os << a; return os.str(); } const long double PI = 3.1415926535897932384626433832795L; template <typename T> inline void input(T &a) { static int ed; a = 0; while (!isdigit(ed = getchar()) && ed != - ) { } char neg = 0; if (ed == - ) { neg = 1; ed = getchar(); } while (isdigit(ed)) { a = 10 * a + ed - 0 ; ed = getchar(); } if (neg) a = -a; } template <typename T = int> inline T nxt() { T res; input(res); return res; } mt19937 generator; bool check(int v) { if (v < 2) return false; for (int i = 2; i * i <= v; ++i) { if (v % i == 0) { return false; } } return true; } long long pw(long long a, long long n, long long m) { long long res = 1; while (n) { if (n & 1ll) { res = res * a % m; } a = a * a % m; n >>= 1; } return res; } long long bin[5][5]; void pre() { for (int i = 0; i < 5; ++i) { bin[i][0] = 1; for (int j = 1; j <= i; ++j) { bin[i][j] = bin[i - 1][j] + bin[i - 1][j - 1]; } } } void read() {} void test() {} long long mod = 1000000007; vector<int> g[1 << 20]; int dp[1 << 20]; int solve(int v) { int &res = dp[v]; if (res != -1) { return res; } res = 1; for (int to : g[v]) { if (to < v) { res = max(res, solve(to) + 1); } } return res; } void solve() { int n = nxt(); int m = nxt(); for (int i = 0; i < m; ++i) { int u = nxt() - 1; int v = nxt() - 1; g[u].push_back(v); g[v].push_back(u); } memset(dp, 255, sizeof(dp)); long long ans = 0; for (int i = 0; i < n; ++i) { ans = max(ans, 1ll * solve(i) * (int)g[i].size()); } cout << ans << endl; } void solve2() {} int main() { int t = 1; pre(); while (t--) { read(); solve(); } return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_bram_7vx_rep_8k.v
// Version : 4.1
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_bram_7vx_rep_8k.v //
// Description : Implements 8 KB Single Ported Memory //
// - Output Regs are always enabled //
// - 2xRAMB36E1 Single Port Mode //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_rep_8k.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_bram_7vx_rep_8k #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [8:0] addr_i, // address
input [127:0] wdata_i, // write data
input [15:0] wdip_i, // write parity
input [1:0] wen_i, // write enable
output [127:0] rdata_o, // read data
output [15:0] rdop_o // read parity
);
genvar i;
wire [1:0] wen = {wen_i[1], wen_i[0]};
generate
for (i = 0; i < 2; i = i + 1) begin : RAMB36E1
RAMB36E1 #(
.SIM_DEVICE ("7SERIES"),
.RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ),
.DOA_REG ( 1 ),
.DOB_REG ( 1 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.RAM_EXTENSION_A ( "NONE" ),
.RAM_EXTENSION_B ( "NONE" ),
.RAM_MODE ( "TDP" ),
.READ_WIDTH_A ( 36 ),
.READ_WIDTH_B ( 36 ),
.RSTREG_PRIORITY_A ( "REGCE" ),
.RSTREG_PRIORITY_B ( "REGCE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.WRITE_WIDTH_A ( 36 ),
.WRITE_WIDTH_B ( 36 )
)
u_buffer (
.CASCADEINA (),
.CASCADEINB (),
.CASCADEOUTA (),
.CASCADEOUTB (),
.CLKARDCLK (clk_i),
.CLKBWRCLK (clk_i),
.DBITERR (),
.ENARDEN (1'b1),
.ENBWREN (1'b1),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0),
.REGCEAREGCE (1'b1 ),
.REGCEB (1'b1 ),
.RSTRAMARSTRAM (1'b0),
.RSTRAMB (1'b0),
.RSTREGARSTREG (1'b0),
.RSTREGB (1'b0),
.SBITERR (),
.ADDRARDADDR ({1'b1, addr_i[8:0], 6'b0}),
.ADDRBWRADDR ({1'b1, addr_i[8:0], 1'b1, 5'b0}),
.DIADI (wdata_i[(2*32*i)+31:(2*32*i)+0]),
.DIBDI (wdata_i[(2*32*i)+63:(2*32*i)+32]),
.DIPADIP (wdip_i[(2*4*i)+3:(2*4*i)+0]),
.DIPBDIP (wdip_i[(2*4*i)+7:(2*4*i)+4]),
.DOADO (rdata_o[(2*32*i)+31:(2*32*i)+0]),
.DOBDO (rdata_o[(2*32*i)+63:(2*32*i)+32]),
.DOPADOP (rdop_o[(2*4*i)+3:(2*4*i)+0]),
.DOPBDOP (rdop_o[(2*4*i)+7:(2*4*i)+4]),
.ECCPARITY (),
.RDADDRECC (),
.WEA ({4{wen[i]}}),
.WEBWE ({4'b0, {4{wen[i]}}})
);
end
endgenerate
endmodule // pcie_bram_7vx_rep_8k
|
#include <bits/stdc++.h> using namespace std; int N, A; vector<int> X; int main(void) { cin.sync_with_stdio(0); cin >> N; int Curr = 0, __Cnt = 0; for (int i = 0; i < N; i++) { cin >> A; if (A < 0) { if (__Cnt == 2) { __Cnt = 0; X.push_back(Curr); Curr = 0; } __Cnt++; } Curr++; } if (Curr) X.push_back(Curr); int Cnt = X.size(); cout << Cnt << endl; for (int i = 0; i < Cnt; i++) { if (i) cout << ; cout << X[i]; } cout << endl; return 0; } |
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 04:56:42 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_pointer_basic_0_0_stub.v
// Design : design_1_pointer_basic_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "pointer_basic,Vivado 2018.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(s_axi_pointer_basic_io_AWADDR,
s_axi_pointer_basic_io_AWVALID, s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_WDATA, s_axi_pointer_basic_io_WSTRB,
s_axi_pointer_basic_io_WVALID, s_axi_pointer_basic_io_WREADY,
s_axi_pointer_basic_io_BRESP, s_axi_pointer_basic_io_BVALID,
s_axi_pointer_basic_io_BREADY, s_axi_pointer_basic_io_ARADDR,
s_axi_pointer_basic_io_ARVALID, s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_RDATA, s_axi_pointer_basic_io_RRESP,
s_axi_pointer_basic_io_RVALID, s_axi_pointer_basic_io_RREADY, ap_clk, ap_rst_n, ap_start,
ap_done, ap_idle, ap_ready)
/* synthesis syn_black_box black_box_pad_pin="s_axi_pointer_basic_io_AWADDR[4:0],s_axi_pointer_basic_io_AWVALID,s_axi_pointer_basic_io_AWREADY,s_axi_pointer_basic_io_WDATA[31:0],s_axi_pointer_basic_io_WSTRB[3:0],s_axi_pointer_basic_io_WVALID,s_axi_pointer_basic_io_WREADY,s_axi_pointer_basic_io_BRESP[1:0],s_axi_pointer_basic_io_BVALID,s_axi_pointer_basic_io_BREADY,s_axi_pointer_basic_io_ARADDR[4:0],s_axi_pointer_basic_io_ARVALID,s_axi_pointer_basic_io_ARREADY,s_axi_pointer_basic_io_RDATA[31:0],s_axi_pointer_basic_io_RRESP[1:0],s_axi_pointer_basic_io_RVALID,s_axi_pointer_basic_io_RREADY,ap_clk,ap_rst_n,ap_start,ap_done,ap_idle,ap_ready" */;
input [4:0]s_axi_pointer_basic_io_AWADDR;
input s_axi_pointer_basic_io_AWVALID;
output s_axi_pointer_basic_io_AWREADY;
input [31:0]s_axi_pointer_basic_io_WDATA;
input [3:0]s_axi_pointer_basic_io_WSTRB;
input s_axi_pointer_basic_io_WVALID;
output s_axi_pointer_basic_io_WREADY;
output [1:0]s_axi_pointer_basic_io_BRESP;
output s_axi_pointer_basic_io_BVALID;
input s_axi_pointer_basic_io_BREADY;
input [4:0]s_axi_pointer_basic_io_ARADDR;
input s_axi_pointer_basic_io_ARVALID;
output s_axi_pointer_basic_io_ARREADY;
output [31:0]s_axi_pointer_basic_io_RDATA;
output [1:0]s_axi_pointer_basic_io_RRESP;
output s_axi_pointer_basic_io_RVALID;
input s_axi_pointer_basic_io_RREADY;
input ap_clk;
input ap_rst_n;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int oo = 0x3f3f3f3f; const double PI = acos(-1); const long long mod = 1e9 + 7; const long long OO = 2e18; const int N = 3e5 + 5; int parent[N]; set<int> st; set<int>::iterator it1, it2; int n, m, l, r, x; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); cin >> n >> m; for (int i = 1; i <= n; ++i) st.insert(i); st.insert(oo); while (m--) { cin >> l >> r >> x; it1 = st.lower_bound(l); while (*it1 <= r) { if (*it1 != x) { parent[*it1] = x; it2 = it1; it1++; st.erase(it2); } else it1++; } } for (int i = 1; i <= n; i++) { cout << parent[i] << ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_PP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_PP_V |
// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altrea Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email:
//
// --------------------------------------------------------------------
//
// Major Functions:i2c controller
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Joe Yang :| 05/07/10 :| Initial Revision
// V2.0 :| Joe Yang :| 12/12/16 :| Initial Revision
// --------------------------------------------------------------------
module I2C_Controller (
input CLOCK,
input [23:0]I2C_DATA,
input GO,
input RESET,
input W_R,
inout I2C_SDAT,
output I2C_SCLK,
output END,
output ACK
);
wire SDAO ;
assign I2C_SDAT = SDAO?1'bz :0 ;
I2C_WRITE_WDATA wrd(
.RESET_N ( RESET),
.PT_CK ( CLOCK),
.GO ( GO ),
.END_OK ( END ),
.ACK_OK ( ACK ),
.BYTE_NUM ( 2 ), //2byte
.SDAI ( I2C_SDAT ),//IN
.SDAO ( SDAO ),//OUT
.SCLO ( I2C_SCLK ),
.SLAVE_ADDRESS( I2C_DATA[23:16] ),
.REG_DATA ( I2C_DATA[15:0] )
);
endmodule
|
// -*- Mode: Verilog -*-
// Filename : wb_riscv_soc_top.v
// Description : Wishbone RiscV SoC Top Level
// Author : Philip Tracton
// Created On : Tue Dec 6 21:14:31 2016
// Last Modified By: Philip Tracton
// Last Modified On: Tue Dec 6 21:14:31 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module wb_riscv_soc_top (/*AUTOARG*/
// Outputs
tx_i,
// Inputs
clk_i, rst_i, rx_i
) ;
parameter ROM_FILE = "";
input clk_i;
input rst_i;
input rx_i;
output tx_i;
//
// Wires
//
wire wb_clk_i;
wire wb_rst_i;
wire wb_clk = wb_clk_i;
wire wb_rst = wb_rst_i;
`include "bus_matrix.vh"
//
// Clock and Reset Control
//
system_controller sys_con(
// Outputs
.wb_clk_o(wb_clk_i),
.wb_rst_o(wb_rst_i),
// Inputs
.clk_i(clk_i),
.rst_i(rst_i)
) ;
//
// Wishbone RiscV VScale CPU
//
wire [23:0] interrupts = 'b0;
// assign wb_s2m_dwmb_err = 0;
//assign wb_s2m_iwmb_err = 0;
wb_vscale riscv_cpu(
.clk(wb_clk_i),
.rst(wb_rst_i),
.ext_interrupts(interrupts),
.iwbm_adr_o(wb_m2s_iwmb_adr),
.iwbm_stb_o(wb_m2s_iwmb_stb),
.iwbm_cyc_o(wb_m2s_iwmb_cyc),
.iwbm_sel_o(wb_m2s_iwmb_sel),
.iwbm_we_o (wb_m2s_iwmb_we),
.iwbm_cti_o(wb_m2s_iwmb_cti),
.iwbm_bte_o(wb_m2s_iwmb_bte),
.iwbm_dat_o(wb_m2s_iwmb_dat),
.iwbm_err_i(wb_s2m_iwmb_err),
.iwbm_ack_i(wb_s2m_iwmb_ack),
.iwbm_dat_i(wb_s2m_iwmb_dat),
.iwbm_rty_i(wb_s2m_iwmb_rty),
.dwbm_adr_o(wb_m2s_dwmb_adr),
.dwbm_stb_o(wb_m2s_dwmb_stb),
.dwbm_cyc_o(wb_m2s_dwmb_cyc),
.dwbm_sel_o(wb_m2s_dwmb_sel),
.dwbm_we_o (wb_m2s_dwmb_we),
.dwbm_cti_o(wb_m2s_dwmb_cti),
.dwbm_bte_o(wb_m2s_dwmb_bte),
.dwbm_dat_o(wb_m2s_dwmb_dat),
.dwbm_err_i(wb_s2m_dwmb_err),
.dwbm_ack_i(wb_s2m_dwmb_ack),
.dwbm_dat_i(wb_s2m_dwmb_dat),
.dwbm_rty_i(wb_s2m_dwmb_rty)
);
//
// System RAM
//
`include "verilog_utils.vh"
assign wb_s2m_ram_rty = 0;
wb_ram #(.depth(1024)) ram(
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_adr_i(wb_m2s_ram_adr),
.wb_dat_i(wb_m2s_ram_dat),
.wb_sel_i(wb_m2s_ram_sel),
.wb_we_i(wb_m2s_ram_we),
.wb_bte_i(wb_m2s_ram_bte),
.wb_cti_i(wb_m2s_ram_cti),
.wb_cyc_i(wb_m2s_ram_cyc),
.wb_stb_i(wb_m2s_ram_stb),
.wb_ack_o(wb_s2m_ram_ack),
.wb_err_o(wb_s2m_ram_err),
.wb_dat_o(wb_s2m_ram_dat)
);
//
// System ROM
//
assign wb_s2m_rom_rty = 0;
wb_ram #( .depth(4096)) rom(
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_adr_i(wb_m2s_rom_adr),
.wb_dat_i(wb_m2s_rom_dat),
.wb_sel_i(wb_m2s_rom_sel),
.wb_we_i(wb_m2s_rom_we),
.wb_bte_i(wb_m2s_rom_bte),
.wb_cti_i(wb_m2s_rom_cti),
.wb_cyc_i(wb_m2s_rom_cyc),
.wb_stb_i(wb_m2s_rom_stb),
.wb_ack_o(wb_s2m_rom_ack),
.wb_err_o(wb_s2m_rom_err),
.wb_dat_o(wb_s2m_rom_dat)
);
//
// UART
//
assign wb_s2m_uart_err = 0;
assign wb_s2m_uart_rty = 0;
uart_wb uart(
.clk(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wb_we_i(wb_m2s_uart_we),
.wb_stb_i(wb_m2s_uart_stb),
.wb_cyc_i(wb_m2s_uart_cyc),
.wb_ack_o(wb_s2m_uart_ack),
.wb_adr_i(wb_m2s_uart_adr),
.wb_adr_int(),
.wb_dat_i(wb_m2s_uart_dat),
.wb_dat_o(wb_s2m_uart_dat),
.wb_dat8_i(wb_m2s_uart_dat[7:0]),
.wb_dat8_o(),
.wb_dat32_o(),
.wb_sel_i(wb_m2s_uart_sel),
.we_o(),
.re_o() // Write and read enable output for the core
);
endmodule // wb_riscv_soc_top
|
#include <bits/stdc++.h> using namespace std; signed long long int n, m, k, x, y; signed long long int ct[3], myct; int main() { cin >> n >> m >> k >> x >> y; signed long long int f1, q, val, rem = k; if (n == 1) { f1 = m; q = rem / f1; rem -= q * f1; myct = q; ct[1] = q; ct[2] = q; if (y <= rem) myct++; if (rem != 0) ct[1]++; cout << ct[1] << << ct[2] << << myct << n ; return 0; } else if (n == 2) { f1 = 2 * m; q = rem / f1; rem -= q * f1; myct = q; ct[1] = ct[2] = q; if (((x - 1) * m + y) <= rem) myct++; if (rem != 0) ct[1]++; cout << ct[1] << << ct[2] << << myct << n ; return 0; } f1 = ((n - 2) * m * 2) + (2 * m); q = rem / f1; rem -= q * f1; ct[0] = 2 * q; ct[1] = q; ct[2] = q; int grp = -1; if (x == 1) { myct = q; grp = 1; } else if (x == n) { myct = q; grp = 2; } else { myct = 2 * q; grp = 0; } int stp = 0; if (rem > 0 && rem <= m) { ct[1]++; if (((x - 1) * m + y) <= rem) myct++; } else if (rem > m && rem <= (n - 1) * m) { ct[0]++; ct[1]++; if (((x - 1) * m + y) <= rem) myct++; } else if (rem > (n - 1) * m && rem <= n * m) { ct[0]++; ct[1]++; stp = 3; if (rem == n * m) ct[2]++; if (((x - 1) * m + y) <= rem) myct++; } else if (rem > n * m && rem <= f1) { ct[0] += 2; ct[1]++; ct[2]++; myct++; stp = 4; if (x == 1 || x == n) { } else { rem -= n * m; val = (n - x - 1) * m + y; if (val <= rem) myct++; } } signed long long int mini = ct[0], maxi = ct[0]; for (int i = 1; i < 3; i++) { mini = min(mini, ct[i]); maxi = max(maxi, ct[i]); } cout << maxi << << mini << << myct << n ; } |
#include <bits/stdc++.h> using namespace std; const int N = 6000; int dp[N][N], len[N], dep[N], sz[N], n, k, val[N]; char S[N * 300]; char *s[N]; struct Edge { int L, len; int to; Edge(int L = 0, int len = 0, int to = 0) : L(L), len(len), to(to) {} } d[N][26]; inline int idx(int c) { return c - a ; } void dfs(int x) { sz[x] = val[x]; for (int i = 0; i <= sz[x]; i++) dp[x][i] = dep[x] * i * (i - 1) / 2; for (int i = 0; i < 26; i++) if (d[x][i].to) { int u = d[x][i].to; dep[u] = dep[x] + d[x][i].len; dfs(u); sz[x] += sz[u]; for (int i = sz[x]; i >= 0; i--) { int xx = 0; for (int j = 0; j <= sz[u] && j <= i; j++) xx = max(xx, dp[x][i - j] + dp[u][j] + j * (i - j) * dep[x]); dp[x][i] = xx; } } } int xb; int main() { scanf( %d%d , &n, &k); s[0] = S; xb = 1; for (int i = 1; i <= n; i++) { s[i] = s[i - 1] + len[i - 1]; scanf( %s , s[i]); len[i] = strlen(s[i]); int q = 1; for (int j = 0; j < len[i];) { int c = idx(s[i][j]); if (d[q][c].to) { for (int k = 0; k < d[q][c].len && j + k <= len[i]; k++) if (s[i][j + k] != S[d[q][c].L + k]) { int p = d[q][c].to; d[q][c].to = ++xb; int nq = xb; if (j + k < len[i]) d[nq][idx(s[i][j + k])].to = ++xb; d[nq][idx(S[d[q][c].L + k])].to = p; if (j + k < len[i]) { d[nq][idx(s[i][j + k])].L = (&s[i][j + k]) - S; d[nq][idx(s[i][j + k])].len = len[i] - j - k; } d[nq][idx(S[d[q][c].L + k])].L = d[q][c].L + k; d[nq][idx(S[d[q][c].L + k])].len = d[q][c].len - k; d[q][c].len = k; break; } } else { d[q][c].L = (&s[i][j]) - S; d[q][c].len = len[i] - j; d[q][c].to = ++xb; } j += d[q][c].len; q = d[q][c].to; } val[q]++; } dfs(1); printf( %d n , dp[1][k]); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_V |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
/**
* Import the design modules for other design submodules
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
`include "acs.v"
`include "bmu.v"
`include "pmsm.v"
`include "spd.v"
// Design of the Viterbi decoder
module viterbi_decoder (d, cx, clk, reset);
// Output signals for the design module
// Decoded output signal from the Viterbi decoder
output d;
// Input signals for the design module
// Received encoded signal that may have corrupted bits
input [1:0] cx;
// Input clock signal for the Viterbi decoder
input clk;
// Reset signal for the Viterbi decoder
input reset;
// Declare "reg" signals... that will be assigned values
// reg d;
// Set of branch metric outputs from the BMU
// reg [1:0] brch_met0,brch_met1,brch_met2,brch_met3;
// reg [1:0] brch_met4,brch_met5,brch_met6,brch_met7;
// Outputs from the ACS units
// Decision bit output from the ACS units
// reg d0,d1,d2,d3;
// Output from the ACS that indicates the new path metric
// reg [3:0] n_pm0,n_pm1,n_pm2,n_pm3;
// Outputs from the PMSM units
// reg [3:0] p_m0, p_m1, p_m2, p_m3;
// Declare "wire" signals...
wire d;
// Set of branch metric outputs from the BMU
wire [1:0] brch_met0,brch_met1,brch_met2,brch_met3;
wire [1:0] brch_met4,brch_met5,brch_met6,brch_met7;
// Outputs from the ACS units
// Decision bit output from the ACS units
wire d0,d1,d2,d3;
// Output from the ACS that indicates the new path metric
wire [3:0] n_pm0,n_pm1,n_pm2,n_pm3;
// Outputs from the PMSM units
wire [3:0] p_m0, p_m1, p_m2, p_m3;
// Defining constants: parameter [name_of_constant] = value;
/*******************************************************
*
* Connecting the modules of the Viterbi decoder together
* That is, link the following modules together:
* # Branch Metric calculation Unit (BMU)
* # Add-Compare-Select unit (ACS)
* # Survivor Path Decoding Unit (SPDU)
* # Survivor Path Decoder (SPD)
* # Path Metric State Memory (PMSM)
*
* Note that the SPD module includes the demux (2-to-4
* DEMUX/demultiplexer) and selector.
*
* The selector chooses the smallest path metric to
* create the control signal to select the smallest path
*
* In addition, note that the SPD module includes 15 SPDU
* units.
*
*
*
* Basic architecture of the Viterbi decoder:
*
* (1) (4) (1) (1)
* BMU->ACS->PMSM->SPD
* v ^ V ^
* | | | |
* | ----- |
* | |
* ------------|
*
*******************************************************
*/
// =====================================================
/**
* Instantiate the BMU to receive inputs for the Viterbi
* decoder, and produce outputs for the ACS units
*
* There is only one BMU for the Viterbi decoder
*/
bmu brch_met (cx[0], cx[1],
brch_met0,brch_met1,brch_met2,brch_met3,
brch_met4,brch_met5,brch_met6,brch_met7);
// =====================================================
/**
* Instantiate the 4 ACS units to receive inputs from
* the BMU and the PMSM, and produce outputs for the SPD
* and the PMSM
*
* The assignment of branch and path metrics to each
* state is based on the Trellis diagrams for different
* inputs for the input code(s), cx or cin
*
* See the BMU module for the interconnections.
*/
// Instantiate the 1st ACS unit
add_compare_select acs0 (n_pm0, d0,
p_m0, brch_met0, p_m1, brch_met2);
// Instantiate the 2nd ACS unit
add_compare_select acs1 (n_pm1, d1,
p_m2, brch_met4, p_m3, brch_met6);
// Instantiate the 3rd ACS unit
add_compare_select acs2 (n_pm2, d2,
p_m0, brch_met1, p_m1, brch_met3);
// Instantiate the 4th ACS unit
add_compare_select acs3 (n_pm3, d3,
p_m2, brch_met5, p_m3, brch_met7);
// =====================================================
/**
* Instantiate the PMSM that contains a set of 4
* registers, and circuitry to normalize the path metrics
* by subtracting the smallest path metric from all of
* the path metrics
*
* There is only one PMSM for the Viterbi decoder
*/
pmsm path_metric_sm (n_pm0, n_pm1, n_pm2, n_pm3,
p_m0, p_m1, p_m2, p_m3, clk, reset);
// =====================================================
/**
* Instantiate the SPD that uses the current path metric
* and the decision bits to determine the optimal path
* for Viterbi decoding using dynamic programming
*
* There is only one SPD for the Viterbi decoder
*/
spd survivor_path_dec (d0, d1, d2, d3, p_m0, p_m1, p_m2, p_m3,
d, clk, reset);
endmodule
|
module Barrel_Shifter
#(parameter SWR=26, parameter EWR=5)
(
input wire clk,
input wire rst,
input wire load_i,
input wire [EWR-1:0] Shift_Value_i,
input wire [SWR-1:0] Shift_Data_i,
input wire Left_Right_i,
input wire Bit_Shift_i,
/////////////////////////////////////////////7
output wire [SWR-1:0] N_mant_o
);
////ge
wire [SWR-1:0] Data_array[EWR+1:0];
//////////////////7
genvar k;//Level
///////////////////77777
Rotate_Mux_Array #(.SWR(SWR)) first_rotate(
.Data_i(Shift_Data_i),
.select_i(Left_Right_i),
.Data_o(Data_array [0][SWR-1:0])
);
generate for (k=0; k < EWR; k=k+1) begin : SHIFT_1LVLS
genvar j;
for (j=0; j<=SWR-1 ; j=j+1) begin
localparam integer sh=(2**LEVEL)+j; //value for second mux input. It changes in exponentation by 2 for each level
case (sh>SWR-1)
1'b1:begin
assign Data_array[k+1][j] = (Shift_Value_i[k]) ? Bit_Shift_i : Data_array[k][j];
end
1'b0:begin
assign Data_array[k+1][j] = (Shift_Value_i[k]) ? Data_array[k][sh] : Data_array[k][j];
end
endcase
end
endgenerate
genvar j;//Create a variable for the loop FOR
generate for (j=0; j <= SWR-1; j=j+1) begin : MUX_ARRAY
case (j)
SWR-1-j:begin : MUX_ARRAY11
assign Data_o[j]=Data_array[EWR+1][SWR-1-j];
end
default:begin : MUX_ARRAY12
Multiplexer_AC #(.W(1)) rotate_mux(
.ctrl(Left_Right_i),
.D0 (Data_array[EWR+1][j]),
.D1 (Data_array[EWR+1][SWR-1-j]),
.S (Data_o[j])
);
end
endcase
end
endgenerate
RegisterAdd #(.W(SWR)) Mid_Reg(
.clk(clk),
.rst(rst),
.load(load_i),
.D(Data_o),
.Q(N_mant_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxN = (int)1e5 + 10; int a[maxN]; int n; vector<pair<int, int> > ans; int cop[maxN]; bool solve_stupid(int n) { for (int i = 1; i <= n; i++) cop[i] = a[i]; vector<pair<int, int> > all; for (int i = 1; i <= n; i++) { for (int j = i + 1; j <= n; j++) { int k = 2 * j - i; if (k <= n) all.emplace_back(i, j); } } int m = all.size(); random_shuffle(all.begin(), all.end()); vector<pair<int, int> > nall; for (int i = 0; i < min(m, 22); i++) nall.push_back(all[i]); all = nall; m = all.size(); for (int mask = 0; mask < (1 << m); mask++) { bool ok = true; for (int i = 1; i <= n; i++) { a[i] = cop[i]; } for (int bit = 0; bit < m; bit++) { if (mask & (1 << bit)) { int x = all[bit].first; int y = all[bit].second; int z = 2 * y - x; a[x] ^= 1; a[y] ^= 1; a[z] ^= 1; } } for (int i = 1; i <= n; i++) { if (a[i] != 0) { ok = false; break; } } if (ok) { for (int bit = 0; bit < m; bit++) { if (mask & (1 << bit)) ans.push_back(all[bit]); } return true; } } return false; } int main() { ios_base::sync_with_stdio(false); srand(time(0)); cin >> n; for (int i = 1; i <= n; i++) { cin >> a[i]; } while (n > 13) { vector<pair<int, int> > possible; possible.emplace_back(0, 0); for (int i = n; i >= n - 5; i--) { for (int j = i - 1; j >= n - 5; j--) { int k = 2 * j - i; if (k <= 0) continue; possible.emplace_back(k, j); } } for (int i = n; i >= n - 5; i--) { int j = n - 6; int k = 2 * j - i; if (k >= 1) { possible.emplace_back(k, j); } } bool ok = false; int willi = -1; int willj = -1; for (int i = n - 5; i <= n; i++) { cop[i] = a[i]; } for (int i = 0; i < possible.size(); i++) { if (ok) break; for (int j = i; j < possible.size(); j++) { for (int q = n - 5; q <= n; q++) a[q] = cop[q]; int x = possible[i].first; int y = possible[i].second; int z = 2 * y - x; if (x >= n - 5) a[x] ^= 1; if (y >= n - 5) a[y] ^= 1; if (z >= n - 5) a[z] ^= 1; int xx = possible[j].first; int yy = possible[j].second; int zz = 2 * yy - xx; if (xx >= n - 5) a[xx] ^= 1; if (yy >= n - 5) a[yy] ^= 1; if (zz >= n - 5) a[zz] ^= 1; if (a[n - 5] == 0 && a[n - 4] == 0 && a[n - 3] == 0 && a[n - 2] == 0 && a[n - 1] == 0 && a[n] == 0) { ok = true; willi = i; willj = j; break; } } } assert(ok == true); int x = possible[willi].first; int y = possible[willi].second; int z = 2 * y - x; if (x >= 1) a[x] ^= 1; if (y >= 1) a[y] ^= 1; if (z >= 1) a[z] ^= 1; if (x != 0) ans.push_back(possible[willi]); int xx = possible[willj].first; int yy = possible[willj].second; int zz = 2 * yy - xx; if (xx >= 1) a[xx] ^= 1; if (yy >= 1) a[yy] ^= 1; if (zz >= 1) a[zz] ^= 1; if (xx != 0) ans.push_back(possible[willj]); n -= 6; } if (solve_stupid(n)) { cout << YES << n ; cout << ans.size() << n ; for (auto t : ans) { cout << t.first << << t.second << << 2 * t.second - t.first << n ; } } else { cout << NO << n ; } return 0; } |
// This counter counts up and is occasionally cleared.
// If up and clear are applied on the same cycle, the
// clear occurs first, and then the up.
//
`include "bsg_defines.v"
module bsg_counter_clear_up #(parameter `BSG_INV_PARAM(max_val_p)
// this originally had an "invalid" default value of -1
// which is a bad choice for a counter
,parameter init_val_p = `BSG_UNDEFINED_IN_SIM('0)
,parameter ptr_width_lp =
`BSG_SAFE_CLOG2(max_val_p+1)
,parameter disable_overflow_warning_p = 0
)
(input clk_i
, input reset_i
, input clear_i
, input up_i
// fixme: count_o should be renamed to count_r_o since some modules
// depend on this being a register and we want to indicate this at the interface level
, output logic [ptr_width_lp-1:0] count_o
);
// keeping track of number of entries and updating read and
// write pointers, and displaying errors in case of overflow
// or underflow
always_ff @(posedge clk_i)
begin
if (reset_i)
count_o <= init_val_p;
else
count_o <= clear_i ? (ptr_width_lp ' (up_i) ) : (count_o+(ptr_width_lp ' (up_i)));
end
//synopsys translate_off
always_ff @ (negedge clk_i)
begin
if ((count_o==ptr_width_lp '(max_val_p)) && up_i && (reset_i===0) && !disable_overflow_warning_p)
$display("%m error: counter overflow at time %t", $time);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_counter_clear_up)
|
/*
* Copyright (c) 2015, Ziliang Guo
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Wisconsin Robotics nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL WISCONSIN ROBOTICS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module camera_link_fmc_bridge
(
fmc_la00p_i,
fmc_la00n_i,
fmc_la02p_i,
fmc_la02n_i,
fmc_la03p_i,
fmc_la03n_i,
fmc_la04p_i,
fmc_la04n_i,
fmc_la05p_i,
fmc_la05n_i,
fmc_la14p_i,
fmc_la14n_i,
fmc_la15p_i,
fmc_la15n_i,
fmc_la18p_i,
fmc_la18n_i,
fmc_la19p_i,
fmc_la19n_i,
fmc_la20p_i,
fmc_la20n_i,
fmc_la21p_i,
fmc_la21n_i,
xclk,
x,
cc,
ser_tfg,
ser_tc
);
input fmc_la00p_i;
input fmc_la00n_i;
input fmc_la02p_i;
input fmc_la02n_i;
input fmc_la03p_i;
input fmc_la03n_i;
input fmc_la04p_i;
input fmc_la04n_i;
input fmc_la05p_i;
input fmc_la05n_i;
input fmc_la14p_i;
input fmc_la14n_i;
output fmc_la15p_i;
output fmc_la15n_i;
output fmc_la18p_i;
output fmc_la18n_i;
output fmc_la19p_i;
output fmc_la19n_i;
output fmc_la20p_i;
output fmc_la20n_i;
output fmc_la21p_i;
output fmc_la21n_i;
output xclk;
output [3:0] x;
input [3:0] cc;
output ser_tfg;
input ser_tc;
IBUFDS xclk_lvds (
.O(xclk),
.I(fmc_la00p_i),
.IB(fmc_la00n_i)
);
IBUFDS x0_lvds (
.O(x[0]),
.I(fmc_la02p_i),
.IB(fmc_la02n_i)
);
IBUFDS x1_lvds (
.O(x[1]),
.I(fmc_la03p_i),
.IB(fmc_la03n_i)
);
IBUFDS x2_lvds (
.O(x[2]),
.I(fmc_la04p_i),
.IB(fmc_la04n_i)
);
IBUFDS x3_lvds (
.O(x[3]),
.I(fmc_la05p_i),
.IB(fmc_la05n_i)
);
IBUFDS ser_tfg_lvds (
.O(ser_tfg),
.I(fmc_la14p_i),
.IB(fmc_la14n_i)
);
OBUFDS cc0_lvds (
.O(fmc_la18p_i),
.OB(fmc_la18n_i),
.I(cc[0])
);
OBUFDS cc1_lvds (
.O(fmc_la19p_i),
.OB(fmc_la19n_i),
.I(cc[1])
);
OBUFDS cc2_lvds (
.O(fmc_la20p_i),
.OB(fmc_la20n_i),
.I(cc[2])
);
OBUFDS cc3_lvds (
.O(fmc_la21p_i),
.OB(fmc_la21n_i),
.I(cc[3])
);
OBUFDS ser_tc_lvds (
.O(fmc_la15p_i),
.OB(fmc_la15n_i),
.I(ser_tc)
);
endmodule |
// Wrapper to store WS2812 pixels in a RAM block for independent
// read-out.
// Copyright (c) 2013 Jared Boone, ShareBrained Technology, Inc.
//
// This file is part of the Medusa project.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
module strip_ws2812 (
input rst_i,
input pixel_clk_i,
input [7:0] pixel_r_i,
input [7:0] pixel_g_i,
input [7:0] pixel_b_i,
input [8:0] led_address_i,
input led_address_valid_i,
input led_clk_i,
output led_data_o
);
parameter LED_COUNT;
parameter REVERSE = 0;
wire pixel_ram_wclk = pixel_clk_i;
wire [8:0] pixel_ram_waddr = led_address_i;
wire [23:0] pixel_ram_wdata = { pixel_r_i, pixel_g_i, pixel_b_i };
wire pixel_ram_we = led_address_valid_i;
wire pixel_ram_rclk = led_clk_i;
wire [8:0] pixel_ram_raddr;
wire [23:0] pixel_ram_rdata;
pixel_ram pixel_ram (
.clk_a(pixel_ram_wclk),
.addr_a(pixel_ram_waddr),
.data_a(pixel_ram_wdata),
.we_a(pixel_ram_we),
.clk_b(pixel_ram_rclk),
.addr_b(pixel_ram_raddr),
.q_b(pixel_ram_rdata)
);
ws2812
#(.LED_COUNT(LED_COUNT), .REVERSE(REVERSE))
ws2812 (
.rst_i(rst_i),
.address_o(pixel_ram_raddr),
.r_i(pixel_ram_rdata[23:16]),
.g_i(pixel_ram_rdata[15: 8]),
.b_i(pixel_ram_rdata[ 7: 0]),
.clk_i(led_clk_i),
.data_o(led_data_o)
);
endmodule
|
#include <bits/stdc++.h> const long long inf = 1000000000ll; const long long inf64 = inf * inf; const long long base = inf + 7; const long long MOD = inf + 9; const double pi = acos(-1.0); using namespace std; bool solve() { int n, q; scanf( %d %d , &n, &q); vector<long long> a(2 * n + 1); for (int i(1); i <= n; i++) scanf( %I64d , &a[i]), a[i + n] = a[i]; vector<int> from(2 * n + 1), dp(2 * n + 1), last(2 * n + 1), used(2 * n + 1); vector<long long> sum(2 * n + 1, 0); for (int i(1); i <= 2 * n; i++) sum[i] = sum[i - 1] + a[i]; for (int i(0); i < q; i++) { long long b; scanf( %I64d , &b); int j = -1; for (int z(1); z <= n; z++) { from[z] = dp[z] = used[z] = last[z] = 0; if (sum[z] > b) { if (j == -1) j = 1; while (sum[z] - sum[j - 1] > b) j++; from[z] = j - 1; } dp[z] = dp[from[z]] + 1; if (from[z]) { last[z] = last[from[z]]; } else last[z] = z; } int ans = n + 1; long long S = 0; for (int z(n); z >= 1; z--) { if (S > b) break; int tmp = dp[z]; if (sum[last[z]] + S > b) tmp++; ans = min(ans, tmp); S += a[z]; } printf( %d n , ans); } return true; } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, p, su; long long a[100005], b[100005]; long double ex[100005]; bool check(long double mid) { long double need = 0; for (int i = 0; i < n; i++) { long double ne = max(0.0L, a[i] * (mid - ex[i])); need += ne; } return (mid * p >= need); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> p; for (int i = 0; i < n; i++) { cin >> a[i] >> b[i]; su += a[i]; } if (p >= su) { cout << -1; } else { for (int i = 0; i < n; i++) { ex[i] = (b[i] * 1.0L) / a[i]; } long double l = 0; long double r = 1e18; for (int i = 0; i < 120; i++) { long double mid = (l + r) / 2; if (check(mid)) { l = mid; } else { r = mid; } } if (r > 1e18 - 100) { cout << -1; } else { cout << setprecision(9) << l; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; int n; int arr[26]; int arr2[26]; cin >> s; int value; int sum = 0; int add; int length = s.size(); cin >> n; for (int i = 0; i < 26; i++) { cin >> arr[i]; arr2[i] = arr[i]; } sort(arr2, arr2 + 26); int largest = arr2[25]; for (int i = 0; i < length; i++) { value = s[i]; int x = abs(97 - value); sum = sum + ((i + 1) * arr[x]); } int last = length + n; int sum1 = 0; for (int i = length + 1; i <= last; i++) { sum1 = sum1 + (i * largest); } cout << sum1 + sum; } |
#include <bits/stdc++.h> #pragma GCC optimization( O3 ) using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t) { int n, m; cin >> n >> m; vector<pair<int, int>> v; vector<int> orig; for (int i = 0; i < m; i++) { int a; cin >> a; orig.push_back(a); v.push_back({a, -i}); } sort(v.begin(), v.end()); vector<int> rank(m); for (int i = 0; i < m; i++) rank[-v[i].second] = i; int ans = 0; vector<int> s; for (int i = 0; i < m; i++) { int pos = rank[i]; for (int i = 0; i < s.size(); i++) { if (pos > s[i]) ans++; } s.push_back(pos); } cout << ans << n ; t--; } } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007LL; const long long MXSZ = 1000000LL; long long fpow(long long b, long long e) { long long ret = 1; while (e > 0) { if (e & 1) (ret *= b) %= mod; (b *= b) %= mod; e >>= 1; } return ret; } long long fac[MXSZ + 5]; void prec() { fac[0] = 1; for (long long i = 1; i <= MXSZ; i++) { fac[i] = fac[i - 1] * i; fac[i] %= mod; } } long long inv(long long u) { return fpow(fac[u], mod - 2); } inline long long comb(long long n, long long k) { long long ret = fac[n]; (ret *= inv(k)) %= mod; (ret *= inv(n - k)) %= mod; return ret; } inline long long perm(long long n, long long k) { long long ret = fac[n]; (ret *= inv(n - k)) %= mod; return ret; } long long n, m, a, b; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); prec(); cin >> n >> m >> a >> b; long long tot = 0LL; for (int btwn = 0; btwn < n - 2; btwn++) { if (m < btwn + 1) break; long long vleft = n - btwn - 2; long long k = btwn + 2; long long curr = comb(m - 1, btwn) * perm(n - 2, btwn); curr %= mod; curr *= k; curr %= mod; curr *= fpow(n, n - k - 1); curr %= mod; curr *= fpow(m, vleft); curr %= mod; tot += curr; tot %= mod; } if (m - 1 >= n - 2) { long long curr = comb(m - 1, n - 2) * perm(n - 2, n - 2); curr %= mod; tot += curr; tot %= mod; } cout << tot << n ; return 0; } |
/*
Copyright (C) {2014} {Ganesh Ajjanagadde} <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`default_nettype none
///////////////////////////////////////////////////////////////////////////////////////////////////
// A simple true dual-port bram module, with hardcoded sizes
// number of lines: 320*240 = 76800
// data word width: 12 bits (4 bits r, 4 bits g, 4 bits b, one pixel per line)
// use here is to store a (downsampled) 640x480 frame at reduced resolution
// that can fit in bram (approx 1 Mbit usage per instantiation)
// Xilinx ISE infers the correct synthesis, and thus this module avoids
// unnecessary Coregen usage
//
// credits: http://danstrother.com/2010/09/11/inferring-rams-in-fpgas/
///////////////////////////////////////////////////////////////////////////////////////////////////
module bram(input wire a_clk,
input wire a_wr,
input wire[16:0] a_addr,
input wire[11:0] a_din,
input wire b_clk,
input wire[16:0] b_addr,
output reg[11:0] b_dout);
// Shared memory
reg[11:0] mem[76799:0];
// Port A
always @(posedge a_clk) begin
if (a_wr) begin
mem[a_addr] <= a_din;
end
end
// Port B
always @(posedge b_clk) begin
b_dout <= mem[b_addr];
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221A_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O221A_PP_BLACKBOX_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221A_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int w = 26; int count = 0; char a[] = { a , b , c , d , e , f , g , h , i , j , k , l , m , n , o , p , q , r , s , t , u , v , w , x , y , z }; string b; cin >> b; for (char c : b) { for (int m = 0; m < w; m++) { if (c == a[m]) { a[m] = 1 ; count++; } } } if (count % 2 == 0) { cout << CHAT WITH HER! ; } else { cout << IGNORE HIM! ; } return 0; } |
/**
* Copyright (C) 2009 Ubixum, Inc.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
**/
// Author: Lane Brooks
// Date: 10/31/2009
// Desc: Implements a low level SPI master interface. Set the
// DATA_WIDTH parameter at instatiation. Put the data you want
// to send on the 'datai' port and strobe the 'go' signal. The
// bits of 'datai' will get serially shifted out to the device
// and the bits coming back from the device will get serially
// shifted into the 'datao' register. Hook up the 'csb',
// 'sclk', 'din', and 'dout' wires to the device. 'busy' is
// high while the shift is running and goes low when the shift
// is complete.
//
// The NUM_PORTS parameter can be used when the 'csb' and 'sclk'
// lines are shared with multiple devices and the 'din' and 'dout'
// lines are unique. For example, if you have two devices, the
// specify NUM_PORTS=2 and 'din' and 'dout' become width 2 ports
// and 'datai' and 'datao' become DATA_WIDTH*NUM_PORTS wide.
//
// Set the CLK_DIVIDER_WIDTH at instantiation. The rate of
// 'sclk' to the device is then set by the input 'clk_divider'.
// 'clk_divider' must be at least 2.
//
// The clock polarity and phasing of this master is set via the
// CPOL and CPHA inputs. See
// http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
// a description of these conventions.
//
//
// Modifications:
// Author: Kurt Snieckus, Eventide Inc.
// Date: 07/01/2014
// Desc: Hacked-in control signal to limit number of clock cycles to half
// DATA_WIDTH for a system which required 16 bit reads and 8 bit reads
`define SYNC_RESET
module spi_master
#(parameter DATA_WIDTH=16,
NUM_PORTS=1,
CLK_DIVIDER_WIDTH=8
)
(input clk,
input resetb,
input CPOL,
input CPHA,
input half_cycle_n,
input [CLK_DIVIDER_WIDTH-1:0] clk_divider,
input go,
input [(NUM_PORTS*DATA_WIDTH)-1:0] datai,
output [(NUM_PORTS*DATA_WIDTH)-1:0] datao,
output reg busy,
output reg done,
input [NUM_PORTS-1:0] dout,
output [NUM_PORTS-1:0] din,
output reg csb,
output reg sclk
);
reg [NUM_PORTS-1:0] dout_s;
reg [CLK_DIVIDER_WIDTH-1:0] clk_count;
wire [CLK_DIVIDER_WIDTH-1:0] next_clk_count = clk_count + 1;
wire pulse = next_clk_count == (clk_divider >> 1);
reg state;
`ifdef verilator
localparam LOG2_DATA_WIDTH = $clog2(DATA_WIDTH+1);
`else
function integer log2;
input integer value;
integer count;
begin
value = value-1;
for (count=0; value>0; count=count+1)
value = value>>1;
log2=count;
end
endfunction
localparam LOG2_DATA_WIDTH = log2(DATA_WIDTH+1);
`endif
reg [LOG2_DATA_WIDTH:0] shift_count;
wire start = shift_count == 0;
/* verilator lint_off WIDTH */
wire [31:0] stop_detect = ((half_cycle_n)+1)*DATA_WIDTH-1;
wire stop = shift_count >= stop_detect;
/* verilator lint_on WIDTH */
localparam IDLE_STATE = 0,
RUN_STATE = 1;
sro #(.DATA_WIDTH(DATA_WIDTH)) sro[NUM_PORTS-1:0]
(.clk(clk),
.resetb(resetb),
.shift(pulse && !csb && (shift_count[0] == 0)),
.dout(dout),
.datao(datao));
sri #(.DATA_WIDTH(DATA_WIDTH)) sri[NUM_PORTS-1:0]
(.clk(clk),
.resetb(resetb),
.datai(half_cycle_n ? datai : {datai[DATA_WIDTH/2-1:0], {DATA_WIDTH/2{1'b0}}}),
.sample(go && (state == IDLE_STATE)), // we condition on state so that if the user holds 'go' high, this will sample only at the start of the transfer
.shift(pulse && !csb && (shift_count[0] == 1)),
.din(din));
`ifdef SYNC_RESET
always @(posedge clk) begin
`else
always @(posedge clk or negedge resetb) begin
`endif
if(!resetb) begin
clk_count <= 0;
shift_count <= 0;
sclk <= 1;
csb <= 1;
state <= IDLE_STATE;
busy <= 0;
done <= 0;
end else begin
// generate the pulse train
if(pulse) begin
clk_count <= 0;
end else begin
clk_count <= next_clk_count;
end
// generate csb
if(state == IDLE_STATE) begin
csb <= 1;
shift_count <= 0;
done <= 0;
if(go && !busy) begin // the !busy condition here allows the user to hold go high and this will then run transactions back-to-back at maximum speed where busy drops at for at least one clock cycle but we stay in this idle state for two clock cycles. Staying in idle state for two cycles probably isn't a big deal since the serial clock is running slower anyway.
state <= RUN_STATE;
busy <= 1;
end else begin
busy <= 0;
end
end else begin
if(pulse) begin
if(stop) begin
csb <= 1;
state <= IDLE_STATE;
done <= 1;
end else begin
csb <= 0;
if(!csb) begin
shift_count <= shift_count + 1;
end
end
end
end
// generate sclk
if(pulse) begin
if((CPHA==1 && state==RUN_STATE && !stop) ||
(CPHA==0 && !csb)) begin
sclk <= !sclk;
end else begin
sclk <= CPOL;
end
end
end
end
endmodule // spi_master
module sri
// This is a shift register that sends data out to the di lines of
// spi slaves.
#(parameter DATA_WIDTH=16)
(input clk,
input resetb,
input [DATA_WIDTH-1:0] datai,
input sample,
input shift,
output din
);
reg [DATA_WIDTH-1:0] sr_reg;
assign din = sr_reg[DATA_WIDTH-1];
`ifdef SYNC_RESET
always @(posedge clk) begin
`else
always @(posedge clk or negedge resetb) begin
`endif
if(!resetb) begin
sr_reg <= 0;
end else begin
if(sample) begin
sr_reg <= datai;
end else if(shift) begin
sr_reg <= sr_reg << 1;
end
end
end
endmodule
module sro
// This is a shift register that receives data on the dout lines
// from spi slaves.
#(parameter DATA_WIDTH=16)
(input clk,
input resetb,
input shift,
input dout,
output reg [DATA_WIDTH-1:0] datao
);
reg dout_s;
`ifdef SYNC_RESET
always @(posedge clk) begin
`else
always @(posedge clk or negedge resetb) begin
`endif
if(!resetb) begin
dout_s <= 0;
datao <= 0;
end else begin
dout_s <= dout;
if(shift) begin
datao <= { datao[DATA_WIDTH-2:0], dout_s };
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(void) { long long a, b, c; cin >> a >> b >> c; long long flag = 1; if (a == b) flag = 0; cout << c * 2 + min(a, b) * 2 + flag << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int m, n; int mat[105][105]; int main() { cin >> m >> n; for (int i = 0; i < m; i++) { for (int j = 0; j < n; j++) { cin >> mat[i][j]; } } if (m % 2 != 0) { cout << m << endl; } else { int aux = m; bool flag = true; int cont = 0; bool flag2 = true; while (flag) { aux = aux / 2; if (aux == 1) { for (int j = 0; j < n; j++) { if (mat[0][j] != mat[1][j]) { flag2 = false; } } if (flag2) { cont++; } flag = false; break; } for (int i = 0; i < aux; i++) { for (int j = 0; j < n; j++) { if (mat[aux - i - 1][j] != mat[aux + i][j]) { flag = false; } } } if (flag) cont++; if (aux % 2 != 0) break; } for (int i = 0; i < cont; i++) { m = m / 2; } cout << m << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 20; const double eps = 1e-6; double p[maxn], ans[maxn], dp[1 << maxn], S[1 << maxn]; int Size[1 << maxn]; bool eq(const double &a, const double &b) { return abs(a - b) <= eps; } int main() { int n, k, zerCnt = 0; bool is0; scanf( %d %d , &n, &k); for (int i = (0); i < (n); ++i) { scanf( %lf , &p[i]); dp[i] = ans[i] = 0; Size[i] = 0; if (eq(p[i], 0)) ++zerCnt; } k = min(k, n - zerCnt); dp[0] = 1; for (int i = (1); i < (1 << n); ++i) { for (int j = (0); j < (n); ++j) if (i & (1 << j)) { Size[i] = Size[i - (1 << j)] + 1; S[i] = S[i - (1 << j)] + p[j]; } } for (int i = (1); i < (1 << n); ++i) { if (S[i] > 0) { for (int j = (0); j < (n); ++j) if ((i & (1 << j)) && (S[(1 << n) - 1 - i + (1 << j)] > 0)) dp[i] += dp[i - (1 << j)] * p[j] / S[(1 << n) - 1 - i + (1 << j)]; if (Size[i] == k) for (int j = (0); j < (n); ++j) if (i & (1 << j)) ans[j] += dp[i]; } else dp[i] = 0; } for (int i = (0); i < (n); ++i) printf( %.8f , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100005; const int P = 1e9 + 7; const int inf = 1e9; const long long Inf = 1e15; inline int IN() { char ch = getchar(); int x = 0, f = 0; while (ch < 0 || ch > 9 ) ch = getchar(), f = (ch == - ); while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + ch - 48; ch = getchar(); } return f ? (-x) : x; } inline int Pow(int x, int y, int p) { int an = 1; for (; y; y >>= 1, x = (long long)x * x % p) if (y & 1) an = (long long)an * x % p; return an; } void renew(int &x, int y) { x += y; if (x < 0) x += P; else if (x >= P) x -= P; } void setIO(string a) { freopen((a + .in ).c_str(), r , stdin); freopen((a + .out ).c_str(), w , stdout); } template <typename T> inline void chkmin(T &a, const T &b) { if (a > b) a = b; } template <typename T> inline void chkmax(T &a, const T &b) { if (a < b) a = b; } int n, k; int dp[1000005], g[1000005], fac[1000005], inv[1000005]; int main() { scanf( %d%d , &n, &k); fac[0] = 1; for (int i = (int)1; i <= (int)n; i++) fac[i] = (long long)fac[i - 1] * i % P; inv[0] = inv[1] = 1; for (int i = (int)2; i <= (int)n; i++) inv[i] = (long long)inv[P % i] * (P - P / i) % P; for (int i = (int)2; i <= (int)n; i++) inv[i] = (long long)inv[i - 1] * inv[i] % P; dp[1] = dp[0] = 1; for (int i = (int)2; i <= (int)k; i++) dp[i] = (long long)dp[i - 1] * i % P; for (int i = (int)1; i <= (int)k; i++) g[i] = (g[i - 1] + (long long)inv[i] * dp[i]) % P; for (int i = (int)k + 1; i <= (int)n; i++) { dp[i] = (g[i - 1] + P - g[i - k - 1]) % P; dp[i] = (long long)dp[i] * fac[i - 1] % P; g[i] = (g[i - 1] + (long long)inv[i] * dp[i]) % P; } int ans = 0; for (int i = (int)0; i <= (int)n - 1; i++) ans = (ans + (long long)dp[i] * fac[n - 1] % P * inv[i]) % P; ans = (0LL + fac[n] - ans) % P; ans = (ans + P) % P; printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using std::max; using std::min; const int inf = 0x3f3f3f3f, Inf = 0x7fffffff; const long long INF = 0x3f3f3f3f3f3f3f3f; std::mt19937 rnd(std::chrono::steady_clock::now().time_since_epoch().count()); template <typename _Tp> _Tp gcd(const _Tp &a, const _Tp &b) { return (!b) ? a : gcd(b, a % b); } template <typename _Tp> inline _Tp abs(const _Tp &a) { return a >= 0 ? a : -a; } template <typename _Tp> inline void chmax(_Tp &a, const _Tp &b) { (a < b) && (a = b); } template <typename _Tp> inline void chmin(_Tp &a, const _Tp &b) { (b < a) && (a = b); } template <typename _Tp> inline void read(_Tp &x) { char ch(getchar()); bool f(false); while (!isdigit(ch)) f |= ch == 45, ch = getchar(); x = ch & 15, ch = getchar(); while (isdigit(ch)) x = (((x << 2) + x) << 1) + (ch & 15), ch = getchar(); f && (x = -x); } template <typename _Tp, typename... Args> inline void read(_Tp &t, Args &...args) { read(t); read(args...); } inline int read_str(char *s) { char ch(getchar()); while (ch == || ch == r || ch == n ) ch = getchar(); char *tar = s; *tar++ = ch, ch = getchar(); while (ch != && ch != r && ch != n && ch != EOF) *tar++ = ch, ch = getchar(); return *tar = 0, tar - s; } const int max_len = 1 << 18; const int N = max_len + 9; const int mod = 998244353; int _inv_[N]; template <typename _Tp1, typename _Tp2> inline void add(_Tp1 &a, _Tp2 b) { (a += b) >= mod && (a -= mod); } template <typename _Tp1, typename _Tp2> inline void sub(_Tp1 &a, _Tp2 b) { (a -= b) < 0 && (a += mod); } template <typename _Tp> inline _Tp _sub(_Tp a, const _Tp &b) { (a += mod - b) >= mod && (a -= mod); return a; } long long ksm(long long a, long long b = mod - 2) { long long res = 1; while (b) { if (b & 1) res = res * a % mod; a = a * a % mod, b >>= 1; } return res; } void print(const std::vector<int> &a) { for (auto it : a) printf( %d , it); printf( n ); } std::vector<int> operator<<(const std::vector<int> &a, unsigned int b) { std::vector<int> o(a.size() + b); for (unsigned int i = 0; i < b; ++i) o[i] = 0; for (unsigned int i = 0; i < a.size(); ++i) o[i + b] = a[i]; return o; } inline std::vector<int> operator<<=(std::vector<int> &a, unsigned int b) { return a = a << b; } inline std::vector<int> operator>>(const std::vector<int> &a, unsigned int b) { return b >= a.size() ? std::vector<int>() : std::vector<int>{a.begin() + b, a.end()}; } inline std::vector<int> operator>>=(std::vector<int> &a, unsigned int b) { return a = b >= a.size() ? std::vector<int>() : std::vector<int>{a.begin() + b, a.end()}; } std::vector<int> operator+=(std::vector<int> &a, const std::vector<int> &b) { if (((int)b.size()) > ((int)a.size())) a.resize(((int)b.size())); for (unsigned int i = 0; i < b.size(); ++i) add(a[i], b[i]); return a; } inline std::vector<int> operator+(const std::vector<int> &a, const std::vector<int> &b) { std::vector<int> tmp(a); tmp += b; return tmp; } std::vector<int> operator-=(std::vector<int> &a, const std::vector<int> &b) { if (((int)b.size()) > ((int)a.size())) a.resize(((int)b.size())); for (unsigned int i = 0; i < b.size(); ++i) sub(a[i], b[i]); return a; } inline std::vector<int> operator-(const std::vector<int> &a, const std::vector<int> &b) { std::vector<int> tmp(a); tmp -= b; return tmp; } int Omgs[N], r[N]; const long long G = ksm(3, (mod - 1) / max_len); int calc(int len) { int limit = 1; while (limit < len) limit <<= 1; for (int i = 0; i < limit; ++i) r[i] = (r[i >> 1] >> 1) | ((i & 1) ? (limit >> 1) : 0); return limit; } void setup() { _inv_[0] = _inv_[1] = 1; for (int i = 2; i < N; ++i) _inv_[i] = 1ll * _inv_[mod % i] * (mod - mod / i) % mod; Omgs[max_len >> 1] = 1; for (int i = (max_len >> 1) + 1; i < max_len; ++i) Omgs[i] = 1LL * Omgs[i - 1] * G % mod; for (int i = (max_len >> 1) - 1; i >= 0; --i) Omgs[i] = Omgs[i << 1]; } void dft(std::vector<int> &a, int limit) { static int A[N]; for (int i = 0; i < limit; ++i) A[r[i]] = a[i]; for (int len = 2, hf = 1; len <= limit; len <<= 1, hf <<= 1) for (int pos = 0; pos < limit; pos += len) { int *w(Omgs + hf), *p(A + pos), *q(A + pos + hf); for (int i = 0; i < hf; ++i, ++p, ++q) { int tmp = 1LL * (*w++) * (*q) % mod; *q = _sub(*p, tmp), add(*p, tmp); } } for (int i = 0; i < limit; ++i) a[i] = A[i] % mod; } void idft(std::vector<int> &a, int limit) { std::reverse(&a[1], &a[limit]); dft(a, limit); unsigned long long inv = mod - (mod - 1) / limit; for (int i = 0; i < limit; ++i) a[i] = inv * a[i] % mod; } std::vector<int> operator*(std::vector<int> a, std::vector<int> b) { if (a.size() <= 40u || b.size() <= 40u) { std::vector<int> c(((int)a.size()) + ((int)b.size()) - 1); for (unsigned int i = 0; i < a.size(); ++i) for (unsigned int j = 0; j < b.size(); ++j) add(c[i + j], 1ull * a[i] * b[j] % mod); return c; } int tmp = ((int)a.size()) + ((int)b.size()), limit = calc(tmp); a.resize(limit), b.resize(limit), dft(a, limit), dft(b, limit); for (int i = 0; i < limit; ++i) a[i] = 1ull * a[i] * b[i] % mod; return idft(a, limit), a.resize(tmp - 1), a; } std::vector<int> sqr(std::vector<int> a) { if (a.size() <= 40u) { std::vector<int> c(((int)a.size()) + ((int)a.size()) - 1); for (unsigned int i = 0; i < a.size(); ++i) for (unsigned int j = 0; j < a.size(); ++j) add(c[i + j], 1ull * a[i] * a[j] % mod); return c; } int tmp = ((int)a.size()) << 1, limit = calc(tmp); a.resize(limit), dft(a, limit); for (int i = 0; i < limit; ++i) a[i] = 1ull * a[i] * a[i] % mod; return idft(a, limit), a.resize(tmp - 1), a; } inline std::vector<int> operator*=(std::vector<int> &a, const std::vector<int> &b) { return a = a * b; } template <typename _Tp> inline std::vector<int> operator*=(std::vector<int> &a, const _Tp &b) { for (auto &&it : a) it = 1ll * it * b % mod; return a; } template <typename _Tp> inline std::vector<int> operator*(std::vector<int> a, const _Tp &b) { return a *= b; } template <typename _Tp> inline std::vector<int> operator*(const _Tp &b, std::vector<int> a) { return a *= b; } template <typename _Tp> inline std::vector<int> operator/=(std::vector<int> &a, const _Tp &b) { long long inv = ksm(b); for (auto &&it : a) it = 1ll * it * inv % mod; return a; } template <typename _Tp> inline std::vector<int> operator/(std::vector<int> a, const _Tp &b) { return a /= b; } template <typename _Tp> inline std::vector<int> operator/(const _Tp &b, std::vector<int> a) { return a /= b; } std::vector<int> _inv(const std::vector<int> &F) { int len = ((int)F.size()); if (len == 1) return {(int)ksm(F[0])}; std::vector<int> H(_inv({F.begin(), F.begin() + (len >> 1)})), tmp(F * H), ans(H); tmp = std::vector<int>{tmp.begin() + (len >> 1), tmp.end()} * H; ans.resize(len); for (int i = 0; i < len >> 1; ++i) tmp[i] && (ans[(len >> 1) + i] = mod - tmp[i]); return ans; } std::vector<int> Inv(std::vector<int> F) { int tmp = ((int)F.size()), L = 1; for (; L < tmp; L <<= 1) ; F.resize(L); std::vector<int> ans(_inv(F)); return ans.resize(tmp), ans; } std::pair<std::vector<int>, std::vector<int> > divide( const std::vector<int> &f, const std::vector<int> &g) { int n = ((int)f.size()), m = ((int)g.size()); std::vector<int> F(f), G(g); std::reverse(F.begin(), F.end()), F.resize(n - m + 1); std::reverse(G.begin(), G.end()), G.resize(n - m + 1); std::vector<int> Q(F * Inv(G)); Q.resize(n - m + 1), std::reverse(Q.begin(), Q.end()); std::vector<int> R(f - Q * g); return R.resize(m - 1), std::make_pair(Q, R); } inline std::vector<int> Mod(const std::vector<int> &f, const std::vector<int> &g) { return divide(f, g).second; } std::vector<int> _sqrt(const std::vector<int> &F) { int len = ((int)F.size()); if (len == 1) return {1}; std::vector<int> H(_sqrt({F.begin(), F.begin() + (len >> 1)})); H.resize(len); return (H + F * _inv(H)) / 2; } std::vector<int> Sqrt(std::vector<int> F) { int tmp = ((int)F.size()), L = 1; for (; L < tmp; L <<= 1) ; F.resize(L); std::vector<int> ans(_sqrt(F)); return ans.resize(tmp), ans; } std::vector<int> deri(std::vector<int> a) { for (int i = 0; i + 1 < ((int)a.size()); ++i) a[i] = 1ll * (i + 1) * a[i + 1] % mod; return a.pop_back(), a; } std::vector<int> inte(std::vector<int> a) { a.resize(((int)a.size()) + 1); for (int i = ((int)a.size()) - 1; i >= 1; --i) a[i] = 1ll * a[i - 1] * _inv_[i] % mod; return a[0] = 0, a; } std::vector<int> Ln(std::vector<int> F) { std::vector<int> ans(inte(deri(F) * Inv(F))); return ans.resize(((int)F.size())), ans; } std::vector<int> _exp(const std::vector<int> &F) { int len = ((int)F.size()); if (len == 1) return {1}; std::vector<int> H(_exp({F.begin(), F.begin() + (len >> 1)})); H.resize(len); std::vector<int> ans(F - Ln(H)); add(ans[0], 1); H.resize(len >> 1); return ans *= H, ans.resize(len), ans; } std::vector<int> Exp(std::vector<int> F) { int tmp = ((int)F.size()), L = 1; for (; L < tmp; L <<= 1) ; F.resize(L); std::vector<int> ans(_exp(F)); return ans.resize(tmp), ans; } std::vector<int> ksm(std::vector<int> a, int b) { a = Ln(a); for (auto &&it : a) it = 1ll * it * b % mod; return Exp(a); } long long fac[N], inv[N], ifac[N]; int main() { setup(); fac[0] = fac[1] = inv[0] = inv[1] = ifac[0] = ifac[1] = 1; for (int i = 2; i < N; ++i) fac[i] = fac[i - 1] * i % mod, inv[i] = inv[mod % i] * (mod - mod / i) % mod, ifac[i] = ifac[i - 1] * inv[i] % mod; int n; read(n); std::vector<int> H(n + 5); for (int i = 0; i < n + 5; ++i) H[i] = i & 1 ? mod - inv[i + 1] : inv[i + 1]; H = Inv(H); std::vector<int> tp(Inv((std::vector<int>{1} - H) >> 1)), tmp(ksm(H, n + 1)), B(tmp * tp); B.resize(n + 5); std::vector<int> A(deri(H) * B); A.resize(n + 5), A *= tp, A.resize(n + 5); std::vector<int> C(n + 5); for (int i = 0; i <= n; ++i) C[i] = 1LL * inv[n + 1] * ((A[i + 1] + 1LL * B[i + 1] * (n - i + 1)) % mod) % mod; std::vector<int> D(n + 5); for (int i = 2; i < n + 5; ++i) D[i - 2] = mod - ifac[i]; D = Inv(D) >> 1; std::vector<int> F(D - C); sub(F[0], 1), F.resize(n + 1); for (int i = 0; i < ((int)F.size()); ++i) F[i] = fac[i] * F[i] % mod; std::vector<int> G(n + 5); for (int i = 0; i <= n; ++i) G[n - i] = i & 1 ? mod - ifac[i] : ifac[i]; F *= G; for (int i = 0; i < n; ++i) printf( %lld%c , 1LL * fac[n] * ifac[i] % mod * F[i + n] % mod, n [i == n]); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2B_LP_V
`define SKY130_FD_SC_LP__NOR2B_LP_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2b_lp (
Y ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2b_lp (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2B_LP_V
|
#include <bits/stdc++.h> using namespace std; struct point { long long x, y; point(long long _x, long long _y) { x = _x; y = _y; } point() {} }; struct cmp { bool operator()(point a, point b) { return (a.x < b.x); } }; struct vec { long long x, y; vec(long long _x, long long _y) { x = _x; y = _y; } vec() {} }; set<point, cmp> daftar; int q, jenis, last = 0; long long totalmana, a, b; bool ans; long double gradien(point p1, point p2) { return (long double)(p1.y - p2.y) / (p1.x - p2.x); } long double manacost(long double indeks) { set<point, cmp>::iterator it1, it2; it1 = daftar.lower_bound(point((long long)indeks, 0)); it2 = daftar.upper_bound(point((long long)indeks, 0)); if (it1 == it2) it1--; if (it2 == daftar.end()) return 1000000000001LL; return (long double)it1->y + gradien(*it1, *it2) * ((long double)indeks - it1->x); } vec toVec(point awal, point akhir) { return vec(akhir.x - awal.x, akhir.y - awal.y); } long double cross(vec v1, vec v2) { return (long double)v1.x * (long double)v2.y - (long double)v1.y * (long double)v2.x; } long double cross(point p1, point p2, point p3) { return cross(toVec(p1, p2), toVec(p1, p3)); } int keatas(int pembilang, int penyebut) { int ret = pembilang / penyebut; if ((pembilang % penyebut) != 0) ret++; return ret; } void seimbangkan(point baru) { auto it = daftar.find(baru); while (prev(it) != daftar.begin()) { auto it2 = prev(it); auto it3 = prev(it2); if (cross(*it3, *it2, *it) > 1e-9) break; daftar.erase(it2); } while (next(it) != daftar.end()) { auto it2 = next(it); auto it3 = next(it2); if (cross(*it, *it2, *it3) > 1e-9) break; daftar.erase(it2); } } int main() { daftar.insert(point(0, 0)); scanf( %d%lld , &q, &totalmana); for (int query = 1; query <= q; query++) { scanf( %d%lld%lld , &jenis, &a, &b); a = (a + last) % 1000000 + 1; b = (b + last) % 1000000 + 1; if (jenis == 1) { if (manacost(a) > (long double)b + 1e-9) { daftar.insert(point(a, b)); seimbangkan(point(a, b)); } } else { swap(a, b); auto it = daftar.lower_bound(point((a + b - 1) / b, 0)); ans = false; if (it != daftar.end()) { if (it->y * b <= totalmana) ans = true; else { auto it2 = prev(it); if ((cross(toVec(point(it2->x * b, it2->y * b), point(a, totalmana)), toVec(point(it2->x * b, it2->y * b), point(it->x * b, it->y * b)))) < 1e-9) ans = true; } } if (ans) printf( YES n ), last = query; else printf( NO n ); } } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_BLACKBOX_V
`define SKY130_FD_SC_HDLL__CLKINV_BLACKBOX_V
/**
* clkinv: Clock tree inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__clkinv (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/);
// Note these are NOT pure.
import "DPI-C" function int dpii_clear ();
import "DPI-C" function int dpii_count (input int ctr);
import "DPI-C" function bit dpii_inc0 (input int ctr);
import "DPI-C" function bit dpii_inc1 (input int ctr);
import "DPI-C" function bit dpii_incx (input int ctr, input bit value);
integer i;
integer j;
integer k;
bit b;
integer errors;
task check1(integer line, bit got, bit ex);
if (got != ex) begin
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
errors++;
end
endtask
task check(integer line, int got, int ex);
if (got != ex) begin
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
errors++;
end
endtask
// Test loop
initial begin
// bug963
// verilator lint_off IGNOREDRETURN
dpii_clear();
// verilator lint_on IGNOREDRETURN
j = 0;
for (i=0; i<64; i++) begin
if (i[0])
j = 0;
else
j = {31'b0, dpii_inc1(0)};
k = k + j;
end
$write("%x\n",k);
check (`__LINE__, dpii_count(0), 32);
if (|errors) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, i, x, y, ans = 0, t; bool p1[1010], p2[1010]; int main() { scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) p1[i] = p2[i] = 1; p1[1] = p2[1] = p1[n] = p2[n] = 0; for (i = 1; i <= m; i++) { scanf( %d%d , &x, &y); p1[x] = p2[y] = 0; } ans = 2 * (n - 2); for (i = 2; i < n; i++) { if (p1[i] == 0) ans--; if (p2[i] == 0) ans--; } if (n % 2) { t = n / 2 + 1; if (p1[t] == 0) ans++; if (p2[t] == 0) ans++; ans -= 2; if (p1[t] || p2[t]) ans++; } cout << ans << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DFSBP_BEHAVIORAL_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfsbp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSBP_BEHAVIORAL_V |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_increment (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter value = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_INCREMENT";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_increment_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_increment_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_increment_psl_logic.v"
`else
`endmodule // ovl_increment
`endif
|
`timescale 1ns / 10ps
`default_nettype none
module tb;
wire [7:0] led;
reg clk;
reg rst;
wire tx;
reg rx;
reg [31:0] parport_i;
wire [31:0] parport_o;
reg [63:0] tracein;
initial tracein = 0;
always @(posedge clk) begin
tracein <= tracein + 64'h1;
end
system mcu(
// Outputs
.tx_o (tx),
// Inputs
.clk_i (clk),
.rx_i (rx),
.tracein(tracein));
reg clockrunning;
initial begin
clockrunning = 1;
while(clockrunning) begin
clk = 0;
#50;
clk = 1;
#50;
end
end
parameter BAUDRATE = 100;
defparam mcu.mcu.io.uart.baudrate_r = BAUDRATE;
reg [7:0] tx_char;
task readchar;
output reg [7:0] read_char;
begin
@(posedge clk);
while(tx == 1) begin
@(posedge clk);
end
repeat (BAUDRATE / 2) @(posedge clk);
repeat (8) begin
repeat (BAUDRATE) @(posedge clk);
tx_char <= (tx_char >> 1) | (tx<< 7);
end
repeat (BAUDRATE) @(posedge clk);
read_char <= tx_char;
@(posedge clk);
end
endtask // readchar
task expect_char;
input [7:0] expectedchar;
reg [7:0] tmp;
begin
readchar(tmp);
if(expectedchar !== tmp) begin
$display("%m: Did not receive the expected character: expected '%c' (%x), got '%c' (%x)",expectedchar,expectedchar,tx_char,tx_char);
$stop;
end
end
endtask // expect_char
task wishbone_write;
input [63:0] addr;
input [63:0] data;
integer i;
begin
putch("m");
expect_char("m");
expect_char(" ");
for(i = 7; i >= 0; i = i - 1) begin
putch(addr[63:56]);
expect_char(addr[63:56]);
addr = addr << 8;
end
expect_char(" ");
// putch(" ");
for(i = 7; i >= 0; i = i - 1) begin
putch(data[63:56]);
expect_char(data[63:56]);
data = data << 8;
end
expect_char(8'h0d);
expect_char("\n");
expect_char(">");
end
endtask // wishbone_write
task parport_write;
input [63:0] data;
integer i;
begin
putch("o");
expect_char("o");
expect_char(" ");
for(i = 7; i >= 0; i = i - 1) begin
putch(data[63:56]);
expect_char(data[63:56]);
data = data << 8;
end
expect_char(8'h0d);
expect_char("\n");
expect_char(">");
end
endtask // parport_write
task putch;
input [7:0] char;
begin
$display("Trying to write out '%c'",char);
@(posedge clk);
rx <= 0;
repeat(BAUDRATE) @(posedge clk);
rx <= char[0];
repeat(BAUDRATE) @(posedge clk);
rx <= char[1];
repeat(BAUDRATE) @(posedge clk);
rx <= char[2];
repeat(BAUDRATE) @(posedge clk);
rx <= char[3];
repeat(BAUDRATE) @(posedge clk);
rx <= char[4];
repeat(BAUDRATE) @(posedge clk);
rx <= char[5];
repeat(BAUDRATE) @(posedge clk);
rx <= char[6];
repeat(BAUDRATE) @(posedge clk);
rx <= char[7];
repeat(BAUDRATE) @(posedge clk);
// stopbit
rx <= 1;
repeat(BAUDRATE) @(posedge clk);
end
endtask // putch
task bytetohex;
input wire [7:0] c;
output reg [3:0] x;
begin
if(c < 8'h30) begin
$display("%m: Unexpected character %x",c);
$stop;
end if(c <= 8'h39) begin
x = c - 8'h30;
end else if(c < 8'h41) begin
$display("%m: Unexpected character %x",c);
$stop;
end else if(c <= 8'h46) begin
x = c - 8'h41 + 10;
end else if(c < 8'h61) begin
$display("%m: Unexpected character %x",c);
$stop;
end else if(c <= 8'h66) begin
x = c - 8'h61 + 10;
end else begin
$display("%m: Unexpected character %x",c);
$stop;
end
end
endtask // bytetohex
task read_longword;
output reg [31:0] x;
reg [7:0] c;
reg [3:0] i;
begin
for(i = 0; i < 8; i = i + 1) begin
readchar(c);
x = x << 4;
bytetohex(c,x[3:0]);
end
end
endtask // read_longword
task parport_read;
output reg [31:0] readval;
reg [7:0] tmp;
begin
putch("i");
expect_char("i");
expect_char(8'h0d);
expect_char(8'h0a);
read_longword(readval);
expect_char(8'h0d);
expect_char(8'h0a);
expect_char(">");
end
endtask // parport_read
reg [7:0] thecharacter;
reg [31:0] readval;
task test_parport;
begin
parport_read(readval);
if(readval == 32'hf00f1234) begin
$display("%m: Success, read parport successfully");
end else begin
$display("%m: Failure, parport_i is 32'haf5596de, read %x",readval);
$stop;
end
end
endtask // test_parport
task test_display();
begin
putch("T");
expect_char("T");
expect_char(8'h0d);
expect_char(8'h0a);
expect_char(8'h41);
expect_char(8'h45);
expect_char(8'h0d);
expect_char(8'h0a);
expect_char(8'h54);
expect_char(8'h72);
expect_char(8'h69);
expect_char(8'h67);
expect_char(8'h76);
expect_char(8'h61);
expect_char(8'h6c);
expect_char(8'h3a);
expect_char(8'h09);
putch_and_expect("7");
putch_and_expect("a");
expect_char(8'h09);
putch_and_expect("3");
putch_and_expect("2");
expect_char(8'h09);
expect_char(8'h0d);
expect_char(8'h0a);
expect_char(8'h4d);
expect_char(8'h61);
expect_char(8'h73);
expect_char(8'h6b);
expect_char(8'h76);
expect_char(8'h61);
expect_char(8'h6c);
expect_char(8'h3a);
expect_char(8'h09);
putch_and_expect("f");
putch_and_expect("f");
expect_char(8'h09);
putch_and_expect("f");
putch_and_expect("f");
expect_char(8'h09);
expect_char(8'h0d);
expect_char("\n");
expect_char(">");
putch_and_expect("t");
expect_char(8'h0d);
expect_char("\n");
expect_char(">");
putch("D");
@(parport_i);
end
endtask // test_display
task putch_and_expect;
input [7:0] char;
begin
putch(char);
expect_char(char);
end
endtask // putch_and_expect
initial begin
rx = 1;
rst = 1;
repeat(100) @(posedge clk);
rst <= 0;
thecharacter = 0;
while(thecharacter != 8'h3e) begin
readchar(thecharacter);
$display("%m: Got %c",thecharacter);
end
test_display();
clockrunning = 0;
end
endmodule // tb_system
|
module transmit_test_model (
//input
input clk_100M ,
input reset_n ,
//output
output [7:0] Line_Num ,
output [1:0] Focus_Num,
output Pr_Gate ,
output RX_Gate ,
output End_Gate ,
output Envelop
);
//wire
wire [1:0] Focus_Num_Pre ;
//reg
reg [31:0] Line_Period ;
reg [31:0] Envelop_Counter ;
reg [31:0] Pulse_Counter ;
reg Pr_Gate_reg ;
reg RX_Gate_reg ;
reg End_Gate_reg ;
reg [1:0] Focus_Num_reg ;
reg Envelop_reg ;
always @(posedge End_Gate_reg)
begin //next foucus
Focus_Num_reg <= Focus_Num_Pre;
end
always @(posedge Pr_Gate_reg)
begin
case(Focus_Num_reg[1:0])
2'b00: //
Line_Period<=32'd12000; //120us
2'b01:
Line_Period<=32'd12000; //120us
2'b10:
Line_Period<=32'd29000; //290us
2'b11:
Line_Period<=32'd29000; //290us
endcase
end
always @(posedge clk_100M or posedge Envelop)
begin
if(Envelop)
begin
Pulse_Counter <= 32'd0;
end
else begin
if(Pulse_Counter < 32'd3000) //30us
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate_reg <= 1'b1;
RX_Gate_reg <= 1'b0;
End_Gate_reg <= 1'b0;
end
else if(Pulse_Counter < 32'd3250) //2.5us?
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate_reg <= 1'b0;
RX_Gate_reg <= 1'b1;
End_Gate_reg <= 1'b0;
end
else if(Pulse_Counter < Line_Period)
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate_reg <= 1'b0;
RX_Gate_reg <= 1'b0;
End_Gate_reg <= 1'b0;
end
else if(Pulse_Counter < (Line_Period + 8'd80)) //0.8us
begin
Pulse_Counter <= Pulse_Counter + 1'b1;
Pr_Gate_reg <= 1'b0;
RX_Gate_reg <= 1'b0;
End_Gate_reg <= 1'b1;
end
else begin
if(Focus_Num_Pre >2'b00)
Pulse_Counter <= 32'd0;
else
Pulse_Counter <= 32'd65536;
Pr_Gate_reg <= 1'b0;
RX_Gate_reg <= 1'b0;
End_Gate_reg <= 1'b0;
end
end
end
always@ (posedge clk_100M or negedge reset_n )
begin
if (!reset_n)
begin
Envelop_reg <= 0 ;
Envelop_Counter <= 0 ;
end
else if (Envelop_Counter < (Line_Period + 8'd90))
begin
Envelop_Counter <= Envelop_Counter + 1'b1;
Envelop_reg <= 1'b0 ;
end
else if (Envelop_Counter >= (Line_Period + 8'd90)&&Envelop_Counter <(Line_Period + 8'd95))
begin
Envelop_Counter <= Envelop_Counter + 1'b1;
Envelop_reg <= 1'b1 ;
end
else
begin
Envelop_reg <= 0 ;
Envelop_Counter <= 0 ;
end
end
cc3200_test_model cc3200_test_model (
//input
.clk_in (clk_100M) ,
.reset_n (reset_n) ,
.RX_Gate (RX_Gate_reg),
.Envelop (Envelop_reg),
//output
.line_num (Line_Num) ,
.focus_num (Focus_Num_Pre)
);
assign Pr_Gate = Pr_Gate_reg ;
assign RX_Gate = RX_Gate_reg ;
assign End_Gate = End_Gate_reg ;
assign Focus_Num = Focus_Num_reg;
assign Envelop = Envelop_reg ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFINV_8_V
`define SKY130_FD_SC_MS__BUFINV_8_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog wrapper for bufinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__bufinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__bufinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__bufinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__bufinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFINV_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21A_2_V
`define SKY130_FD_SC_MS__O21A_2_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21a_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21a_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21A_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:06:38 08/13/2013
// Design Name:
// Module Name: controlador
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module controlador(ent1,ent2,ent3,ent4,salA,salB,salC,salD,salE,salF,salG, clk, btn0, btn1, btn2, btn3, led0, led1, led2, led3);
input wire clk;
input wire btn0;
input wire btn1;
input wire btn2;
input wire btn3;
output reg led0;
output reg led1;
output reg led2;
output reg led3;
reg ledAux0;
reg ledAux1;
reg ledAux2;
reg ledAux3;
input wire ent1;
input wire ent2;
input wire ent3;
input wire ent4;
output salA;
output salB;
output salC;
output salD;
output salE;
output salF;
output salG;
modulo_A a (ent1,ent2,ent3,ent4,salA);
modulo_B b (ent1,ent2,ent3,ent4,salB);
modulo_C c (ent1,ent2,ent3,ent4,salC);
modulo_D d (ent1,ent2,ent3,ent4,salD);
modulo_E e (ent1,ent2,ent3,ent4,salE);
modulo_F f (ent1,ent2,ent3,ent4,salF);
modulo_G g (ent1,ent2,ent3,ent4,salG);
always @(posedge clk)
begin
if(btn0 == 1)
begin
ledAux0 = 0;
ledAux1 = 1;
ledAux2 = 1;
ledAux3 = 1;
end
else if (btn1 == 1)
begin
ledAux0 = 1;
ledAux1 = 0;
ledAux2 = 1;
ledAux3 = 1;
end
else if (btn2 == 1)
begin
ledAux0 = 1;
ledAux1 = 1;
ledAux2 = 0;
ledAux3 = 1;
end
else if (btn3 == 1)
begin
ledAux0 = 1;
ledAux1 = 1;
ledAux2 = 1;
ledAux3 = 0;
end
led0 = ledAux0;
led1 = ledAux1;
led2 = ledAux2;
led3 = ledAux3;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t(/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off NBAJAM
input clk;
reg [7:0] _ranit;
reg [2:0] a;
reg [7:0] vvector;
reg [7:0] vvector_flip;
// surefire lint_off STMINI
initial _ranit = 0;
always @ (posedge clk) begin
a <= a + 3'd1;
vvector[a] <= 1'b1; // This should use "old" value for a
vvector_flip[~a] <= 1'b1; // This should use "old" value for a
//
//========
if (_ranit==8'd0) begin
_ranit <= 8'd1;
$write("[%0t] t_select_index: Running\n", $time);
vvector <= 0;
vvector_flip <= 0;
a <= 3'b1;
end
else _ranit <= _ranit + 8'd1;
//
if (_ranit==8'd3) begin
$write("%x %x\n",vvector,vvector_flip);
if (vvector !== 8'b0000110) $stop;
if (vvector_flip !== 8'b0110_0000) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_sitofp_32ns_32_6
#(parameter
ID = 3,
NUM_STAGE = 6,
din0_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
//------------------------Instantiation------------------
ANN_ap_sitofp_4_no_dsp_32 ANN_ap_sitofp_4_no_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 110; int n, m, k; int h[MAXN]; void load() { scanf( %d%d%d , &n, &m, &k); for (int i = 0; i < n; i++) scanf( %d , h + i); } bool solve() { long long sum = m; int ind = 0; while (ind < n - 1) { if (h[ind] >= h[ind + 1] - k) { int nxt = max(h[ind + 1] - k, 0); sum += h[ind] - nxt; } else { if (sum + h[ind] < h[ind + 1] - k) return false; sum -= h[ind + 1] - k - h[ind]; } ind++; } return true; } int main() { int t; scanf( %d , &t); while (t--) { load(); if (solve()) printf( YES n ); else printf( NO n ); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAH_SYMBOL_V
`define SKY130_FD_SC_HS__FAH_SYMBOL_V
/**
* fah: Full adder.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fah (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT,
output SUM
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAH_SYMBOL_V
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) using namespace std; const double PI = 3.141592653589793238463; const int INF = 0x3f3f3f3f; const int INFS = 1000000000; const long long LLINF = 9223372036854775807; const int M = 1000000007; const double EPS = 1e-9; set<int> get(int n) { set<int> ans = {}; for (int i = 2; i * i <= n; ++i) { if (n % i == 0) { ans.insert(i); while (n % i == 0) n /= i; } } if (n != 1) ans.insert(n); return ans; } signed main() { ios_base::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int n, m; cin >> n >> m; vector<set<int> > a(n + 1); for (int i = 1; i < n + 1; i++) a[i] = get(i); map<int, int> curr; vector<bool> on(n + 1, false); char t; int i; while (m--) { cin >> t >> i; if (t == + ) { if (on[i]) cout << Already on << endl; else { bool ok = true; int j; for (auto x : a[i]) { if (curr[x] != 0) { ok = false; j = curr[x]; break; } } if (ok) { cout << Success << endl; for (auto x : a[i]) curr[x] = i; on[i] = true; } else { cout << Conflict with << j << endl; } } } else { if (!on[i]) cout << Already off << endl; else { cout << Success << endl; for (auto x : a[i]) curr[x] = 0; on[i] = false; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long fast_expo(long long base, long long exp, long long module) { long long ans = 1; while (exp) { if (exp & 1) ans = (ans * base) % module; base = (base * base) % module; exp >>= 1; } return ans; } bool primes[100001]; void seive() { memset(primes, true, sizeof(primes)); primes[0] = false; primes[1] = false; for (int i = 2; i * i <= 100000; i++) { if (primes[i]) { for (int j = i * i; j <= 100000; j += i) primes[j] = false; } } } bool isprime(int n) { if (n == 1) return false; if (n == 2) return true; if (n % 2 == 0) return false; for (int i = 3; i * i <= n; i += 2) if (n % i == 0) return false; return true; } long long gcd(long long a, long long b) { if (b == 0) return a; else return gcd(b, a % b); } long long f[100001]; long long fib(long long n) { if (n == 0) return 0; if (n == 1 || n == 2) return (f[n] = 1); if (f[n]) return f[n]; long long k = (n & 1) ? (n + 1) / 2 : n / 2; f[n] = (n & 1) ? (fib(k) * fib(k) + fib(k - 1) * fib(k - 1)) : (2 * fib(k - 1) + fib(k)) * fib(k); return f[n]; } int main() { ios_base::sync_with_stdio(false); int n; cin >> n; int t1 = n % 10; int t2 = t1; int cnt1 = 0, cnt2 = 0; if (t1 == 0) { cout << n << endl; return 0; } while (t1 <= 10) { cnt1++; t1++; } while (t2 > 0) { t2--; cnt2++; } if (cnt1 <= cnt2) cout << (n + cnt1 - 1) << endl; else cout << (n - cnt2) << endl; return 0; } |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="axi_stream_counter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.440000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=34,HLS_SYN_LUT=34}" *)
module axi_stream_counter (
ap_clk,
ap_rst_n,
ap_start,
ap_done,
ap_idle,
ap_ready,
counter_TDATA,
counter_TVALID,
counter_TREADY,
ap_return
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst_n;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output [31:0] counter_TDATA;
output counter_TVALID;
input counter_TREADY;
output [31:0] ap_return;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg counter_TVALID;
reg ap_rst_n_inv;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm = 1'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_19;
reg [31:0] counterValue = 32'b00000000000000000000000000000000;
wire [31:0] counterValue_assign_fu_34_p2;
reg ap_sig_ioackin_counter_TREADY;
reg ap_reg_ioackin_counter_TREADY = 1'b0;
reg [0:0] ap_NS_fsm;
reg ap_sig_bdd_60;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ioackin_counter_TREADY assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ioackin_counter_TREADY
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ioackin_counter_TREADY <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0)) begin
if (~((ap_start == ap_const_logic_0) | (ap_const_logic_0 == ap_sig_ioackin_counter_TREADY))) begin
ap_reg_ioackin_counter_TREADY <= ap_const_logic_0;
end else if (ap_sig_bdd_60) begin
ap_reg_ioackin_counter_TREADY <= ap_const_logic_1;
end
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~((ap_start == ap_const_logic_0) | (ap_const_logic_0 == ap_sig_ioackin_counter_TREADY)))) begin
counterValue <= counterValue_assign_fu_34_p2;
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0 or ap_sig_ioackin_counter_TREADY)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~((ap_start == ap_const_logic_0) | (ap_const_logic_0 == ap_sig_ioackin_counter_TREADY)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0 or ap_sig_ioackin_counter_TREADY)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~((ap_start == ap_const_logic_0) | (ap_const_logic_0 == ap_sig_ioackin_counter_TREADY)))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_19)
begin
if (ap_sig_bdd_19) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_ioackin_counter_TREADY assign process. ///
always @ (counter_TREADY or ap_reg_ioackin_counter_TREADY)
begin
if ((ap_const_logic_0 == ap_reg_ioackin_counter_TREADY)) begin
ap_sig_ioackin_counter_TREADY = counter_TREADY;
end else begin
ap_sig_ioackin_counter_TREADY = ap_const_logic_1;
end
end
/// counter_TVALID assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0 or ap_reg_ioackin_counter_TREADY)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0) & (ap_const_logic_0 == ap_reg_ioackin_counter_TREADY))) begin
counter_TVALID = ap_const_logic_1;
end else begin
counter_TVALID = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_start or ap_CS_fsm or ap_sig_ioackin_counter_TREADY)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_return = ap_const_lv32_0;
/// ap_rst_n_inv assign process. ///
always @ (ap_rst_n)
begin
ap_rst_n_inv = ~ap_rst_n;
end
/// ap_sig_bdd_19 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_19 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_60 assign process. ///
always @ (ap_start or counter_TREADY)
begin
ap_sig_bdd_60 = (~(ap_start == ap_const_logic_0) & (ap_const_logic_1 == counter_TREADY));
end
assign counterValue_assign_fu_34_p2 = (counterValue + ap_const_lv32_1);
assign counter_TDATA = (counterValue + ap_const_lv32_1);
endmodule //axi_stream_counter
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300005; const int SIGMA_SIZE = 26; int SZ = 0; struct Node { int sz, ch[SIGMA_SIZE]; Node() { memset(ch, 0, sizeof(ch)); } } nd[maxn << 1]; int newNode() { ++SZ; memset(nd[SZ].ch, 0, sizeof(nd[SZ].ch)); return SZ; } void maintain(int u) { nd[u].sz = 1; for (int i = 0; i < SIGMA_SIZE; i++) if (nd[u].ch[i]) nd[u].sz += nd[nd[u].ch[i]].sz; } void merge(int &a, int b) { if (a == 0) { a = b; } else { for (int i = 0; i < SIGMA_SIZE; i++) { if (nd[b].ch[i]) merge(nd[a].ch[i], nd[b].ch[i]); } } maintain(a); } int N; long long C[maxn]; char S[maxn]; vector<int> G[maxn]; void init() { scanf( %d , &N); for (int i = 1; i <= N; i++) { G[i].clear(); scanf( %lld , &C[i]); } scanf( %s , S + 1); int u, v; for (int i = 1; i < N; i++) { scanf( %d%d , &u, &v); G[u].push_back(v); G[v].push_back(u); } } int dfs(int u, int f) { int p = newNode(); for (int i = 0; i < G[u].size(); i++) { int v = G[u][i]; if (v == f) continue; merge(p, dfs(v, u)); } maintain(p); int r = newNode(); nd[r].ch[S[u] - a ] = p; maintain(r); C[u] += nd[r].sz - 1; return r; } int main() { init(); dfs(1, 0); long long ans = 0, cnt; for (int i = 1; i <= N; i++) { if (C[i] > ans) { ans = C[i]; cnt = 0; } if (C[i] == ans) { cnt++; } } printf( %I64d n%I64d n , ans, cnt); return 0; } |
/* note for avalon interface
bus type: nagtive
read legacy = 0 (to consistent to FIFO)
*/
module adc_ltc2308_fifo(
// avalon slave port
slave_clk,
slave_reset_n,
slave_chipselect_n,
slave_addr,
slave_read_n,
slave_wrtie_n,
slave_readdata,
slave_wriredata,
adc_clk, // max 40mhz
// adc interface
ADC_CONVST,
ADC_SCK,
ADC_SDI,
ADC_SDO
);
// avalon slave port
input slave_clk;
input slave_reset_n;
input slave_chipselect_n;
input slave_addr;
input slave_read_n;
input slave_wrtie_n;
output reg [15:0] slave_readdata;
input [15:0] slave_wriredata;
input adc_clk;
output ADC_CONVST;
output ADC_SCK;
output ADC_SDI;
input ADC_SDO;
////////////////////////////////////
// avalon slave port
`define WRITE_REG_START_CH 0
`define WRITE_REG_MEASURE_NUM 1
// write for control
reg measure_fifo_start;
reg [11:0] measure_fifo_num;
reg [2:0] measure_fifo_ch;
always @ (posedge slave_clk or negedge slave_reset_n)
begin
if (~slave_reset_n)
measure_fifo_start <= 1'b0;
else if (~slave_chipselect_n && ~slave_wrtie_n && slave_addr == `WRITE_REG_START_CH)
{measure_fifo_ch, measure_fifo_start} <= slave_wriredata[3:0];
else if (~slave_chipselect_n && ~slave_wrtie_n && slave_addr == `WRITE_REG_MEASURE_NUM)
measure_fifo_num <= slave_wriredata;
end
///////////////////////
// read
`define READ_REG_MEASURE_DONE 0
`define READ_REG_ADC_VALUE 1
wire slave_read_status;
wire slave_read_data;
assign slave_read_status = (~slave_chipselect_n && ~slave_read_n && slave_addr == `READ_REG_MEASURE_DONE) ?1'b1:1'b0;
assign slave_read_data = (~slave_chipselect_n && ~slave_read_n && slave_addr == `READ_REG_ADC_VALUE) ?1'b1:1'b0;
reg measure_fifo_done;
always @ (posedge slave_clk)
begin
if (slave_read_status)
slave_readdata <= {11'b0, measure_fifo_done};
else if (slave_read_data)
slave_readdata <= fifo_q;
end
reg pre_slave_read_data;
always @ (posedge slave_clk or negedge slave_reset_n)
begin
if (~slave_reset_n)
pre_slave_read_data <= 1'b0;
else
pre_slave_read_data <= slave_read_data;
end
// read ack for adc data. (note. Slave_read_data is read lency=2, so slave_read_data is assert two clock)
assign fifo_rdreq = (pre_slave_read_data & slave_read_data)?1'b1:1'b0;
////////////////////////////////////
// create triggle message: adc_reset_n
reg pre_measure_fifo_start;
always @ (posedge adc_clk)
begin
pre_measure_fifo_start <= measure_fifo_start;
end
wire adc_reset_n;
assign adc_reset_n = (~pre_measure_fifo_start & measure_fifo_start)?1'b0:1'b1;
////////////////////////////////////
// control measure_start
reg [11:0] measure_count;
reg config_first;
reg wait_measure_done;
reg measure_start;
wire measure_done;
wire [11:0] measure_dataread;
always @ (posedge adc_clk or negedge adc_reset_n)
begin
if (~adc_reset_n)
begin
measure_start <= 1'b0;
config_first <= 1'b1;
measure_count <= 0;
measure_fifo_done <= 1'b0;
wait_measure_done <= 1'b0;
end
else if (~measure_fifo_done & ~measure_start & ~wait_measure_done)
begin
measure_start <= 1'b1;
wait_measure_done <= 1'b1;
end
else if (wait_measure_done) // && measure_start)
begin
measure_start <= 1'b0;
if (measure_done)
begin
if (config_first)
config_first <= 1'b0;
else
begin // read data and save into fifo
if (measure_count < measure_fifo_num) // && ~fifo_wrfull)
begin
measure_count <= measure_count + 1;
wait_measure_done <= 1'b0;
end
else
measure_fifo_done <= 1'b1;
end
end
end
end
// write data into fifo
reg pre_measure_done;
always @ (posedge adc_clk or negedge adc_reset_n)
begin
if (~adc_reset_n)
pre_measure_done <= 1'b0;
else
pre_measure_done <= measure_done;
end
assign fifo_wrreq = (~pre_measure_done & measure_done & ~config_first)?1'b1:1'b0;
///////////////////////////////////////
// SPI
adc_ltc2308 adc_ltc2308_inst(
.clk(adc_clk), // max 40mhz
// start measure
.measure_start(measure_start), // posedge triggle
.measure_done(measure_done),
.measure_ch(measure_fifo_ch),
.measure_dataread(measure_dataread),
// adc interface
.ADC_CONVST(ADC_CONVST),
.ADC_SCK(ADC_SCK),
.ADC_SDI(ADC_SDI),
.ADC_SDO(ADC_SDO)
);
///////////////////////////////////////
// FIFO
wire fifo_wrfull;
wire fifo_rdempty;
wire fifo_wrreq;
wire [11:0] fifo_q;
wire fifo_rdreq;
adc_data_fifo adc_data_fifo_inst(
.aclr(~adc_reset_n),
.data(measure_dataread),
.rdclk(slave_clk),
.rdreq(fifo_rdreq),
.wrclk(adc_clk),
.wrreq(fifo_wrreq),
.q(fifo_q),
.rdempty(fifo_rdempty),
.wrfull(fifo_wrfull)
);
endmodule
|
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