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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_PS_TB_V
`define SKY130_FD_SC_LS__UDP_DFF_PS_TB_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__udp_dff_ps.v"
module top();
// Inputs are registered
reg D;
reg SET;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET = 1'bX;
#20 D = 1'b0;
#40 SET = 1'b0;
#60 D = 1'b1;
#80 SET = 1'b1;
#100 D = 1'b0;
#120 SET = 1'b0;
#140 SET = 1'b1;
#160 D = 1'b1;
#180 SET = 1'bx;
#200 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__udp_dff$PS dut (.D(D), .SET(SET), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_PS_TB_V
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the on board periphal devices *
* on the DE2-70 board. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_de2_70 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [26: 0] audio_rom_data;
wire [26: 0] video_rom_data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = audio_rom_data | video_rom_data;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_av_config_auto_init_ob_audio Auto_Init_Audio_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (audio_rom_data)
);
defparam
Auto_Init_Audio_ROM.AUD_LINE_IN_LC = AUD_LINE_IN_LC,
Auto_Init_Audio_ROM.AUD_LINE_IN_RC = AUD_LINE_IN_RC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_LC = AUD_LINE_OUT_LC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_RC = AUD_LINE_OUT_RC,
Auto_Init_Audio_ROM.AUD_ADC_PATH = AUD_ADC_PATH,
Auto_Init_Audio_ROM.AUD_DAC_PATH = AUD_DAC_PATH,
Auto_Init_Audio_ROM.AUD_POWER = AUD_POWER,
Auto_Init_Audio_ROM.AUD_DATA_FORMAT = AUD_DATA_FORMAT,
Auto_Init_Audio_ROM.AUD_SAMPLE_CTRL = AUD_SAMPLE_CTRL,
Auto_Init_Audio_ROM.AUD_SET_ACTIVE = AUD_SET_ACTIVE;
altera_up_av_config_auto_init_ob_adv7180 Auto_Init_Video_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (video_rom_data)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__OR4B_PP_BLACKBOX_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; template <class T> void show(const vector<T> &a) { for (T x : a) cout << x << ; cout << n ; } const long long N = 1e5 + 10, oo = 1e18 + 500; const long long mod = 1e9 + 7; const long double eps = 1e-9, PI = 2 * acos(0.0); long long n, m, k; long long cnt = 0; vector<long long> g[N]; vector<long long> rg[N]; vector<long long> visit(N, 0); vector<vector<long long> > dp(N, vector<long long>(150, -oo)); signed main() { ios::sync_with_stdio(0); cout.tie(0); cin.tie(0); cin >> n >> m >> k; vector<vector<long long> > a(n, vector<long long>(m + 1)); for (long long i = 0; i < n; i++) { cin >> a[i][0]; } for (long long i = 0; i < n; i++) { for (long long j = 0; j < m; j++) cin >> a[i][j + 1]; } sort(a.rbegin(), a.rend()); dp[0][0] = a[0][0]; for (long long j = 0; j < m; j++) { dp[0][(1 << j)] = a[0][j + 1]; } for (long long i = 1; i < n; i++) { for (long long mask = 0; mask < (1 << m); mask++) { long long ex = 0; for (long long j = 0; j < m; j++) { if (mask & (1 << j)) { ex++; } } long long add = 0; if (i < k + ex) add = a[i][0]; if (dp[i][mask] < dp[i - 1][mask] + add) { dp[i][mask] = dp[i - 1][mask] + add; } for (long long j = 0; j < m; j++) { if (!(mask & (1 << j))) { if (dp[i][mask | (1 << j)] < dp[i - 1][mask] + a[i][j + 1]) { dp[i][mask | (1 << j)] = dp[i - 1][mask] + a[i][j + 1]; } } } } } long long ans = dp[n - 1][(1 << m) - 1]; cout << ans; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3fll; const int MAXN = 510; char grid[MAXN][MAXN]; int n, k; int component[MAXN][MAXN]; int size[MAXN * MAXN]; int orig_size[MAXN * MAXN]; int last_taken[MAXN * MAXN]; int dr[] = {1, 0, -1, 0}; int dc[] = {0, 1, 0, -1}; inline bool valid(int r, int c) { return 0 <= r && r < n && 0 <= c && c < n; } void dfs(int r, int c, int cmp) { component[r][c] = cmp; size[cmp]++; for (int i = 0; i < 4; i++) { int nr = r + dr[i], nc = c + dc[i]; if (!valid(nr, nc)) continue; if (component[nr][nc] != -1 || grid[nr][nc] == X ) continue; dfs(nr, nc, cmp); } } int main() { scanf( %d%d , &n, &k); for (int r = 0; r < n; r++) for (int c = 0; c < n; c++) scanf( %c , &grid[r][c]); memset(component, -1, sizeof(component)); int cnt = 0; for (int r = 0; r < n; r++) { for (int c = 0; c < n; c++) { if (grid[r][c] == . && component[r][c] == -1) { dfs(r, c, cnt); orig_size[cnt] = size[cnt]; cnt++; } } } int best = 0; int t = 1; for (int r = 0; r + k - 1 < n; r++) { for (int i = 0; i < cnt; i++) size[i] = orig_size[i]; for (int rr = 0; rr < k; rr++) for (int cc = 0; cc < k; cc++) if (grid[r + rr][cc] == . ) size[component[r + rr][cc]]--; for (int c = 0; c + k - 1 < n; c++) { int got = k * k; for (int i = 0; i < k; i++) { int rr, cc; rr = r - 1, cc = c + i; if (valid(rr, cc) && grid[rr][cc] == . && last_taken[component[rr][cc]] != t) { got += size[component[rr][cc]]; last_taken[component[rr][cc]] = t; } rr = r + i, cc = c + k; if (valid(rr, cc) && grid[rr][cc] == . && last_taken[component[rr][cc]] != t) { got += size[component[rr][cc]]; last_taken[component[rr][cc]] = t; } rr = r + k, cc = c + i; if (valid(rr, cc) && grid[rr][cc] == . && last_taken[component[rr][cc]] != t) { got += size[component[rr][cc]]; last_taken[component[rr][cc]] = t; } rr = r + i, cc = c - 1; if (valid(rr, cc) && grid[rr][cc] == . && last_taken[component[rr][cc]] != t) { got += size[component[rr][cc]]; last_taken[component[rr][cc]] = t; } } best = max(best, got); for (int rr = r; rr < r + k; rr++) { if (grid[rr][c] == . ) size[component[rr][c]]++; if (c + k < n && grid[rr][c + k] == . ) size[component[rr][c + k]]--; } t++; } } printf( %d n , best); return 0; } |
/* Author: QAQAutoMaton Lang: C++ Code: C.cpp Mail: lk@qaq-am.com Blog: https://www.qaq-am.com/ */ #include<bits/stdc++.h> #define debug(...) fprintf(stderr,__VA_ARGS__) #define DEBUG printf( Passing [%s] in LINE %d n ,__FUNCTION__,__LINE__) #define Debug debug( Passing [%s] in LINE %d n ,__FUNCTION__,__LINE__) #define all(x) x.begin(),x.end() #define x first #define y second using namespace std; typedef unsigned uint; typedef long long ll; typedef unsigned long long ull; typedef complex<double> cp; typedef pair<int,int> pii; int inf; const double eps=1e-8; const double pi=acos(-1.0); template<class T,class T2>int chkmin(T &a,T2 b){return a>b?a=b,1:0;} template<class T,class T2>int chkmax(T &a,T2 b){return a<b?a=b,1:0;} template<class T>T sqr(T a){return a*a;} template<class T,class T2>T mmin(T a,T2 b){return a<b?a:b;} template<class T,class T2>T mmax(T a,T2 b){return a>b?a:b;} template<class T>T aabs(T a){return a<0?-a:a;} template<class T>int dcmp(T a,T b){return a>b;} template<int *a>int cmp_a(int x,int y){return a[x]<a[y];} template<class T>bool sort2(T &a,T &b){return a>b?swap(a,b),1:0;} #define min mmin #define max mmax #define abs aabs struct __INIT__{ __INIT__(){ fill((unsigned char*)&inf,(unsigned char*)&inf+sizeof(inf),0x3f); } }__INIT___; namespace io { const int SIZE = (1 << 21) + 1; char ibuf[SIZE], *iS, *iT, obuf[SIZE], *oS = obuf, *oT = oS + SIZE - 1, c, qu[55]; int f, qr; // getchar #define gc() (iS == iT ? (iT = (iS = ibuf) + fread (ibuf, 1, SIZE, stdin), (iS == iT ? EOF : *iS ++)) : *iS ++) // print the remaining part inline void flush () { fwrite (obuf, 1, oS - obuf, stdout); oS = obuf; } // putchar inline void putc (char x) { *oS ++ = x; if (oS == oT) flush (); } template<typename A> inline bool read (A &x) { for (f = 1, c = gc(); c < 0 || c > 9 ; c = gc()) if (c == - ) f = -1;else if(c==EOF)return 0; for (x = 0; c <= 9 && c >= 0 ; c = gc()) x = x * 10 + (c & 15); x *= f; return 1; } inline bool read (char &x) { while((x=gc())== ||x== n || x== r ); return x!=EOF; } inline bool read(char *x){ while((*x=gc())== n || *x== ||*x== r ); if(*x==EOF)return 0; while(!(*x== n ||*x== ||*x== r ||*x==EOF))*(++x)=gc(); *x=0; return 1; } template<typename A,typename ...B> inline bool read(A &x,B &...y){ return read(x)&&read(y...); } template<typename A> inline bool write (A x) { if (!x) putc ( 0 ); if (x < 0) putc ( - ), x = -x; while (x) qu[++ qr] = x % 10 + 0 , x /= 10; while (qr) putc (qu[qr --]); return 0; } inline bool write (char x) { putc(x); return 0; } inline bool write(const char *x){ while(*x){putc(*x);++x;} return 0; } inline bool write(char *x){ while(*x){putc(*x);++x;} return 0; } template<typename A,typename ...B> inline bool write(A x,B ...y){ return write(x)||write(y...); } //no need to call flush at the end manually! struct Flusher_ {~Flusher_(){flush();}}io_flusher_; } using io :: read; using io :: putc; using io :: write; char s[100005]; int p[1005],q[1005],rp[1005]; int t1,t2,t3,t4,t5,t6; int a[1005][1005],b[1005][1005]; int v[4]; signed main(){ #ifdef QAQAutoMaton freopen( C.in , r ,stdin); freopen( C.out , w ,stdout); #endif int t; read(t); for(;t;--t){ int n,m; read(n,m); for(int i=0;i<n;++i)for(int j=0;j<n;++j){ read(a[i][j]); --a[i][j]; } read(s+1); pii x={1,0},y={2,0},z={3,0}; for(int i=1;i<=m;++i){ switch(s[i]){ case R :++y.y;break; case L :--y.y;break; case D :++x.y;break; case U :--x.y;break; case I :swap(y,z);break; case C :swap(x,z);break; } } ((x.y%=n)+=n)%=n; ((y.y%=n)+=n)%=n; ((z.y%=n)+=n)%=n; for(int i=0;i<n;++i){ for(int j=0;j<n;++j){ v[1]=i;v[2]=j;v[3]=a[i][j]; b[(v[x.x]+x.y)%n][(v[y.x]+y.y)%n]=(v[z.x]+z.y)%n; } } for(int i=0;i<n;++i)for(int j=0;j<n;++j)write(b[i][j]+1,j==n-1? n : ); putc( n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename t> t in(t q) { cin >> q; return q; } template <typename T> ostream& operator<<(ostream& os, const vector<T>& v) { os << [ ; for (int i = 0; i < ((int)size(v)); ++i) { os << v[i]; if (i != ((int)size(v)) - 1) os << , ; } os << ] ; return os; } template <typename T, typename S> ostream& operator<<(ostream& os, const map<T, S>& v) { for (auto it : v) os << ( << it.first << : << it.second << ) ; return os; } template <typename T, typename S> ostream& operator<<(ostream& os, const pair<T, S>& v) { os << ( << v.first << , << v.second << ) ; return os; } const long double PI = acosl(-1); mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); mt19937_64 rng64(chrono::steady_clock::now().time_since_epoch().count()); inline int rand(int l, int r) { return uniform_int_distribution<int>(l, r)(rng); } inline long long rand(long long l, long long r) { return uniform_int_distribution<long long>(l, r)(rng); } int p; int i; int xw; long long ans = 0; int j; bool s1, s2; int n, k; struct node; node* last; struct node { int sum; node *lft, *rht; node() { sum = 0; lft = NULL; rht = NULL; } int query(int l) { if (l == 2) return sum; if (l) { if (!rht) rht = new node(); last = rht; if (!lft) return 0; return lft->sum; } if (!lft) lft = new node(); last = lft; if (!rht) return 0; return rht->sum; } void update(int l, int r) { if (l == r) { sum++; return; } int mid = (l + r) / 2; if (xw <= mid) { if (!lft) lft = new node(); lft->update(l, mid); } else { if (!rht) rht = new node(); rht->update(mid + 1, r); } sum++; } }; node* r = new node(); int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cout << setprecision(10); cin >> n >> k; xw = 0; r->update(0, 1073741823); for (i = 1; i < n + 1; ++i) { cin >> p; last = r; p ^= xw; for (j = 29; j >= 0; --j) { s1 = ((1 << j) & k); s2 = (1 << j) & p; if (s1 && s2) { if (!last->lft) break; last = last->lft; } else if (s1 && !s2) { if (!last->rht) break; last = last->rht; } else if (s2) { ans += last->query(1); } else { ans += last->query(0); } } if (j == -1) ans += last->query(2); xw = p; r->update(0, 1073741823); } cout << ans; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND2_BLACKBOX_V
`define SKY130_FD_SC_LS__NAND2_BLACKBOX_V
/**
* nand2: 2-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND2_BLACKBOX_V
|
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate NAND gate vector
//
module main;
reg globvar;
wire [15:0] out;
reg [15:0] a,b, rslt;
reg error;
// The test gate goes HERE!
nand foo [15:0] (out,a,b);
always @(a or b)
rslt = ~(a & b);
initial
begin // {
error = 0;
# 1;
for(a = 16'h1; a != 16'hffff; a = (a << 1) | 1)
begin // {
for(b = 16'hffff; b !== 16'h0; b = b >> 1)
begin // {
#1 ;
if(out !== rslt)
begin // {
$display("FAILED - GA NAND a=%h,b=%h,expct=%h - rcvd=%h",
a,b,rslt,out);
error = 1;
end // }
end // }
end // }
if( error == 0)
$display("PASSED");
end // }
endmodule // main
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DECAP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DECAP_FUNCTIONAL_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__decap ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DECAP_FUNCTIONAL_V |
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_bitcheck(
ck,
reset_n,
clear,
enable,
read_data,
reference_data,
mask,
error_word
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
localparam DATA_BUS_SIZE = DATA_WIDTH * NUMBER_OF_WORDS;
input ck;
input reset_n;
input clear;
input enable;
input [DATA_BUS_SIZE - 1 : 0] read_data;
input [DATA_BUS_SIZE - 1 : 0] reference_data;
input [NUMBER_OF_WORDS - 1 : 0] mask;
output [DATA_WIDTH - 1 : 0] error_word;
reg [DATA_BUS_SIZE - 1 : 0] read_data_r;
reg [DATA_WIDTH - 1 : 0] error_word;
reg enable_r;
wire [DATA_WIDTH - 1 : 0] error_compute;
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
error_word <= {DATA_WIDTH{1'b0}};
read_data_r <= {DATA_BUS_SIZE{1'b0}};
enable_r <= 1'b0;
end
else begin
if(clear) begin
error_word <= {DATA_WIDTH{1'b0}};
end
else if(enable_r) begin
error_word <= error_word | error_compute;
end
read_data_r <= read_data;
enable_r <= enable;
end
end
genvar b;
generate
for(b = 0; b < DATA_WIDTH; b = b + 1)
begin : bit_loop
if(AFI_RATIO == 2) begin
assign error_compute[b] =
((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]) |
((read_data_r[b + 2 * DATA_WIDTH] ^ reference_data[b + 2 * DATA_WIDTH]) & ~mask[2])|
((read_data_r[b + 3 * DATA_WIDTH] ^ reference_data[b + 3 * DATA_WIDTH]) & ~mask[3]);
end
else begin
assign error_compute[b] =
((read_data_r[b] ^ reference_data[b]) & ~mask[0]) |
((read_data_r[b + DATA_WIDTH] ^ reference_data[b + DATA_WIDTH]) & ~mask[1]);
end
end
endgenerate
endmodule
|
#include <bits/stdc++.h> int cmp(const void *a, const void *b) { return (*(int *)a - *(int *)b); } int main() { char str[100005]; int i, j, k; scanf( %s , str); int l = strlen(str); int cB = 0, cb = 0, cu = 0, ca = 0, cs = 0, cr = 0, cl = 0; for (i = 0; i < l; i++) { if (str[i] == B ) { cB++; } else if (str[i] == b ) { cb++; } else if (str[i] == u ) { cu++; } else if (str[i] == a ) { ca++; } else if (str[i] == s ) { cs++; } else if (str[i] == l ) { cl++; } else if (str[i] == r ) { cr++; } else { continue; } } int arry[5]; arry[0] = cB; arry[1] = cs; arry[2] = cr; arry[3] = cl; arry[4] = cb; qsort(arry, 5, sizeof(int), cmp); int m1 = arry[0]; int m2; if (cu <= ca) { m2 = cu; } else { m2 = ca; } int ans; if (m2 >= 2 * m1) { ans = m1; } else if (m2 < 2 * m1) { ans = m2 / 2; } printf( %d n , ans); return (0); } |
module autoinstparam_first ();
parameter BITSCHANGED;
parameter BITSA;
parameter type BITSB_t;
typedef [2:0] my_bitsb_t;
/* autoinstparam_first_sub AUTO_TEMPLATE (
.BITSA (BITSCHANGED),
); */
autoinstparam_first_sub
#(/*AUTOINSTPARAM*/
// Parameters
.BITSA (BITSCHANGED), // Templated
.BITSB_t (BITSB_t))
sub
(/*AUTOINST*/
// Inouts
.a (a[BITSA:0]),
.b (b));
autoinstparam_first_sub
#(
.BITSB_t (my_bitsb_t),
/*AUTOINSTPARAM*/
// Parameters
.BITSA (BITSCHANGED)) // Templated
sub1
(/*AUTOINST*/
// Inouts
.a (a[BITSA:0]),
.b (b));
autoinstparam_first_sub
#(
.BITSA (1),
.BITSB_t (my_bitsb_t)
/*AUTOINSTPARAM*/)
sub2
(/*AUTOINST*/
// Inouts
.a (a[BITSA:0]),
.b (b));
autoinstparam_first_sub
#(
/*AUTOINSTPARAM*/
// Parameters
.BITSA (BITSCHANGED), // Templated
.BITSB_t (BITSB_t))
sub3
(/*AUTOINST*/
// Inouts
.a (a[BITSA:0]),
.b (b));
endmodule
// Local Variables:
// verilog-auto-inst-param-value:nil
// verilog-typedef-regexp: "_t$"
// End:
|
#include <bits/stdc++.h> using namespace std; long long cyc[1000006][27], n, m; long long done[1000006]; string a, b; int main() { cin >> n >> m; cin >> a >> b; int s1 = a.size(); int s2 = b.size(); long long tot = s1 * n; memset(cyc, 0, sizeof(cyc)); memset(done, 0, sizeof(done)); long long ans = 0; for (int i = 0; i < s1; i++) { int st = i % s2; if (!done[st]) { int H[27]; memset(H, 0, sizeof(H)); H[b[st] - a ]++; done[st] = 1; int pos = 1; int en = (st + s1) % s2; while (en != st) { pos++; H[b[en] - a ]++; done[en] = pos; en = (en + s1) % s2; } done[st] = pos; for (int k = 0; k < 26; k++) cyc[st][k] = H[k]; en = (st + s1) % s2; while (en != st) { for (int k = 0; k < 26; k++) cyc[en][k] = H[k]; done[en] = pos; en = (en + s1) % s2; } } ans += (cyc[st][a[i] - a ] * ((tot) / (s1 * done[st]))); } cout << tot - ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 105; map<string, int> H1[maxn], H2[maxn]; vector<char> ans; char getA(string a, string b) { int c[30]; for (int i = 0; i < 26; i++) c[i] = 0; for (int i = 0; i < a.size(); i++) c[a[i] - a ]++; for (int i = 0; i < b.size(); i++) c[b[i] - a ]--; for (int i = 0; i < 26; i++) { if (c[i] > 0) return i + a ; } } int main() { int n; cin >> n; if (n == 1) { cout << ? 1 1 << endl; string sss; cin >> sss; cout << ! << sss << endl; } else { cout << ? 1 << n << endl; for (int i = 0; i < n * (n + 1) / 2; i++) { string s; cin >> s; sort(s.begin(), s.end()); H1[s.size()][s]++; } cout << ? 2 << n << endl; for (int i = 0; i < n * (n - 1) / 2; i++) { string s; cin >> s; sort(s.begin(), s.end()); H2[s.size()][s]++; } for (int i = 1; i <= n; i++) { for (auto p : H2[i]) { H1[i][p.first] -= H2[i][p.first]; } for (auto p : H1[i]) { if (p.second > 0) { string new1 = ; for (int j = 0; j < ans.size(); j++) new1 += ans[j]; ans.push_back(getA(p.first, new1)); } } } string new1 = ; for (int j = 0; j < ans.size(); j++) new1 += ans[j]; cout << ! << new1 << endl; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:16:57 02/26/2016
// Design Name:
// Module Name: Register
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Register(
input clock_in,
input regWrite,
input [4:0] readReg1, //address to be read1
input [4:0] readReg2,
input [4:0] writeReg, //address to be write
input [31:0] writeData,
output reg [31:0] readData1,
output reg [31:0] readData2
);
reg [31:0] regFile[31:0];
always @(readReg1 or readReg2 or posedge clock_in)
begin
readData1 = regFile[readReg1];
readData2 = regFile[readReg2];
end
always @(negedge clock_in)
begin
if(regWrite)
regFile[writeReg] = writeData;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5 * 1e5 + 5; const int M = 2e6 + 5; vector<int> a[M], b[M]; vector<int> c[M], d[M]; int vis[M]; int n, w, cnt; int main() { scanf( %d%d , &n, &w); w--; for (int i = 1; i <= n; i++) { int k; scanf( %d , &k); a[i].resize(k); for (int j = 0; j < k; j++) { int g; scanf( %d , &g); a[i][j] = g - 1; } } for (int i = 1; i < n; i++) { int up = min(a[i].size(), a[i + 1].size()); bool flag = false; for (int j = 0; j < up; j++) { if (a[i][j] > a[i + 1][j]) { b[a[i][j]].push_back(a[i + 1][j]); flag = true; break; } else if (a[i][j] < a[i + 1][j]) { b[a[i][j]].push_back(a[i + 1][j]), flag = true; break; } } if (!flag && a[i].size() > a[i + 1].size()) { puts( -1 ); return 0; } } for (int i = 0; i < 1e6; i++) { if (!b[i].size()) continue; int mx = -1, mn = 1e6 + 5, mx2 = -1, mn2 = 1e6 + 5, add = w - i + 1; for (int j : b[i]) { mx = max(mx, j); mn = min(mn, j); mx2 = max(mx2, (j + add) % (w + 1)); mn2 = min(mn2, (j + add) % (w + 1)); } cnt++; if (mn > i) { c[0].push_back(cnt); d[w - mx].push_back(cnt); c[w - i + 1].push_back(cnt); d[2 * w - mx].push_back(cnt); } else { c[add].push_back(cnt); d[add + w - mx2].push_back(cnt); } } int ans = 0; for (int i = 0; i < 1e6; i++) { for (int j : c[i]) { if (!vis[j]) ans++; vis[j]++; } if (ans == cnt) { printf( %d n , i); return 0; } for (int j : d[i]) { if (vis[j] == 1) ans--; vis[j]--; } } puts( -1 ); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<bool> prime(1001, true); void sieve() { prime[0] = false; prime[1] = false; for (int i = 2; i <= 1000; i++) { if (prime[i]) { int j = 2; while (i * j <= 1000) { prime[i * j] = false; j++; } } } } long long int ceil_sqrt(long long int a) { long long int i = 1; while (i * i < a) i++; return i; } void solve() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i += 2) cout << a[i + 1] << << -1 * a[i] << ; cout << endl; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 2e9; const int MAXN = 900; const int MAXM = 1900000; int N, edges; int last[MAXN], preve[MAXM], head[MAXM]; int Cap[MAXM], Flow[MAXM]; int dist[MAXN]; int nextEdge[MAXN]; queue<int> Q; void init(int N) { edges = 0; memset(last, -1, sizeof last); } set<int> namex, namey; vector<int> xx, yy; void handlex(int f) { if (namex.find(f) != namex.end()) return; namex.insert(f); xx.push_back(f); } void handley(int f) { if (namey.find(f) != namey.end()) return; yy.push_back(f); namey.insert(f); } inline void add_edge(int u, int v, int cap, int flow = 0) { head[edges] = v; preve[edges] = last[u]; Cap[edges] = cap; Flow[edges] = flow; last[u] = edges++; head[edges] = u; preve[edges] = last[v]; Cap[edges] = 0; Flow[edges] = 0; last[v] = edges++; } inline bool dinicBfs(int S, int E, int N) { int from = S, to, cap, flow; memset(dist, 0, sizeof(int) * N); dist[from] = 1; while (!Q.empty()) Q.pop(); Q.push(from); while (!Q.empty()) { from = Q.front(); Q.pop(); for (int e = last[from]; e >= 0; e = preve[e]) { to = head[e]; cap = Cap[e]; flow = Flow[e]; if (!dist[to] && cap > flow) { dist[to] = dist[from] + 1; Q.push(to); if (to == E) return true; } } } return (dist[E] != 0); } inline int dfs(int from, int minEdge, int E) { if (!minEdge) return 0; if (from == E) return minEdge; int to, e, cap, flow, ret; for (; nextEdge[from] >= 0; nextEdge[from] = preve[e]) { e = nextEdge[from]; to = head[e]; cap = Cap[e]; flow = Flow[e]; if (dist[to] != dist[from] + 1) continue; ret = dfs(to, min(minEdge, cap - flow), E); if (ret) { Flow[e] += ret; Flow[e ^ 1] -= ret; return ret; } } return 0; } int dinicUpdate(int S, int E) { int flow = 0; while (int minEdge = dfs(S, INF, E)) { if (minEdge == 0) break; flow += minEdge; } return flow; } int maxFlow(int S, int E, int N) { int totFlow = 0; while (dinicBfs(S, E, N)) { for (int i = 0; i <= N; i++) nextEdge[i] = last[i]; totFlow += dinicUpdate(S, E); } return totFlow; } int x1[60], y11[60], x2[60], y2[60]; int main() { int i, j, k, l, m, n; init(32); scanf( %d%d , &n, &m); for (int i = 1; i <= m; i++) { scanf( %d%d%d%d , &x1[i], &y11[i], &x2[i], &y2[i]); x2[i]++; y2[i]++; handlex(x1[i]); handlex(x2[i]); handley(y11[i]); handley(y2[i]); } sort(xx.begin(), xx.end()); sort(yy.begin(), yy.end()); int so = xx.size() + yy.size() + 1; int sink = so + 1; for (int i = 1; i <= m; i++) { for (int j = 1; j < xx.size(); j++) { if (xx[j] <= x1[i]) continue; if (xx[j] > x2[i]) break; for (int k = 1; k < yy.size(); k++) { if (yy[k] <= y11[i]) continue; if (yy[k] > y2[i]) break; int g = xx.size() + k; add_edge(j, g, INF); } } } for (int i = 1; i < xx.size(); i++) { add_edge(so, i, xx[i] - xx[i - 1]); } for (int i = 1; i < yy.size(); i++) { int g = xx.size() + i; add_edge(g, sink, yy[i] - yy[i - 1]); } int ans = maxFlow(so, sink, sink + 2); cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; string s1, s2; bool eq(int a1, int b1, int a2, int b2) { if ((b1 - a1) & 1) { while (a1 < b1) { if (s1[a1] != s2[a2]) return 0; ++a1; ++a2; } return 1; } int m1 = (a1 + b1) / 2; int m2 = (a2 + b2) / 2; return (eq(a1, m1, a2, m2) && eq(m1, b1, m2, b2)) || (eq(a1, m1, m2, b2) && eq(m1, b1, a2, m2)); } bool func() { if (s1.length() != s2.length()) return 0; if (eq(0, s1.length(), 0, s2.length())) { return 1; } } int main() { cin >> s1 >> s2; if (func()) cout << YES ; else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; map<int, int, greater<int> > g; int a; int gcd(int a, int b) { while (b != 0) { a %= b; swap(a, b); } return a; } int main() { ios::sync_with_stdio(0); cin.tie(0); ; cin >> n; for (int(i) = (0); (i) < int(n * n); ++(i)) { cin >> a; g[a]++; } vector<int> ans; while (1) { bool done = 0; for (auto& x : g) { if (x.second <= 0) continue; x.second--; done = 1; for (auto every : ans) { g[gcd(every, x.first)] -= 2; } ans.push_back(x.first); g[x.first]--; break; } if (!done) break; } for (auto y : ans) cout << y << ; cin.sync(); cin.get(); return 0; } |
#include <bits/stdc++.h> using namespace std; int Day12[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; int prime100[] = {2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97, 101, 103}; template <typename T> inline bool isLeap(T y) { return (y % 400 == 0) || (y % 100 ? y % 4 == 0 : false); } template <typename T> inline T GCD(T a, T b) { a = abs(a); b = abs(b); if (a < b) swap(a, b); while (b) { a = a % b; swap(a, b); } return a; } template <typename T> inline T LCM(T x, T y) { T tp = GCD(x, y); if ((x / tp) * 1. * y > 9e18) return 9e18; return (x / tp) * y; } template <typename T> inline T BIGMOD(T A, T B, T M = 1000000007) { T ret = 1; while (B) { if (B & 1) ret = (ret * A) % M; A = (A * A) % M; B = B >> 1; } return ret; } template <typename T> inline T BigMod(T A, T B, T M) { T ret = 1; while (B) { if (B & 1) ret = (ret * A) % M; A = (A * A) % M; B = B >> 1; } return ret; } long long int MySqrt(long long int n) { long long int p = sqrt(n); if ((p + 1) * (p + 1) <= n) return p + 1; else if (p * p <= n) return p; else return p - 1; } long long int MyPow(long long int x, long long int n) { if (n == 0) return 1; else if (n % 2 == 0) return MyPow(x * x, n / 2); else return x * MyPow(x * x, ((n - 1) / 2)); } long long int modInverse(long long int n) { return BIGMOD(n, (long long int)1000000007 - 2) % 1000000007; } void solve() { long long int ans = 1, n; cin >> n; if (n % 2 == 1) printf( 0 n ); else { n /= 2; for (int i = 1; i <= n; i++) ans *= 2; printf( %lld n , ans); } } char arr[505][505]; int Left[505][505]; int Right[505][505]; int Up[505][505]; int Low[505][505]; void Now() { int n, m, cnt = 0; cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { cin >> arr[i][j]; if (arr[i][j] == * ) cnt++; } } for (int i = 1; i < n; i++) { for (int j = 0; j < m; j++) { if (arr[i - 1][j] == * ) Up[i][j] += 1 + Up[i - 1][j]; } } for (int i = 0; i < n; i++) { for (int j = 1; j < m; j++) { if (arr[i][j - 1] == * ) Left[i][j] += 1 + Left[i][j - 1]; } } for (int i = n - 1; i >= 0; i--) { for (int j = m - 2; j >= 0; j--) { if (arr[i][j + 1] == * ) Right[i][j] += 1 + Right[i][j + 1]; } } for (int i = n - 2; i >= 0; i--) { for (int j = m - 1; j >= 0; j--) { if (arr[i + 1][j] == * ) Low[i][j] += 1 + Low[i + 1][j]; } } for (int i = 1; i < n - 1; i++) { for (int j = 1; j < m - 1; j++) { if (Left[i][j] > 0 && Up[i][j] > 0 && Right[i][j] > 0 && Low[i][j] > 0 && arr[i][j] == * ) { if (Left[i][j] + Up[i][j] + Right[i][j] + Low[i][j] + 1 == cnt) { printf( YES n ); exit(0); } } } } printf( NO n ); } int main() { solve(); } |
#include <bits/stdc++.h> using namespace std; struct Tans { long a; long b; }; struct mstr { long num; long val; }; bool operator<(mstr a, mstr b) { return a.val < b.val; } bool operator>(mstr a, mstr b) { return a.val > b.val; } bool operator==(mstr a, mstr b) { return a.val == b.val; } int main() { long n, s; cin >> n >> s; vector<mstr> cards(n); vector<Tans> ress; priority_queue<mstr> q; ress.reserve(n); for (long i = 0; i < n; i++) { cin >> cards[i].val; cards[i].num = i + 1; if (cards[i].val) q.push(cards[i]); } bool f = true; vector<mstr> temp; while (q.size() != 0 && f) { temp.resize(0); temp.reserve(q.size()); mstr now = q.top(); q.pop(); if (q.size() < now.val) f = false; else { mstr tt; Tans ttt; ttt.a = now.num; while (now.val != 0) { tt = q.top(); q.pop(); now.val--; tt.val--; ttt.b = tt.num; temp.push_back(tt); ress.push_back(ttt); } for (long j = 0; j < temp.size(); j++) if (temp[j].val > 0) q.push(temp[j]); } } if (f == false) cout << No ; else { cout << Yes n << ress.size() << n ; for (long i = 0; i < ress.size(); i++) cout << ress[i].a << << ress[i].b << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 100500; int a[maxn]; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; long long k; cin >> n >> k; long long sm = 0; priority_queue<pair<int, int> > pq; for (int i = 0; i < n; ++i) { cin >> a[i]; sm += a[i]; pq.push({-a[i], i}); } if (sm < k) return cout << -1 << n , 0; if (sm == k) return 0; long long it = 0, lft = n; while (true) { assert(!pq.empty()); auto u = pq.top(); u.first += it; lft = (int)pq.size(); if (lft * -1LL * u.first > k) break; pq.pop(); while (pq.top().first + it == u.first) pq.pop(); k -= lft * -1LL * u.first; it += u.first * -1LL; } for (int i = 0; i < n; ++i) a[i] = 0; it += k / lft; k %= lft; while (!pq.empty()) { a[pq.top().second] = (pq.top().first + it) * -1LL; pq.pop(); } queue<int> q; for (int i = 0; i < n; ++i) if (a[i]) q.push(i); while (k--) { auto u = q.front(); q.pop(); a[u]--; if (a[u]) q.push(u); } while (!q.empty()) { cout << q.front() + 1 << ; q.pop(); } return 0; } |
module ps2 (
input Rx,
input CLKOUT,
output reg Rx_error,
output [7:0] DATA,
output reg DONE
);
reg [8:0] regis;
reg [7:0] regis0;
reg [3:0] i;
reg [3:0] j;
reg [1:0] k;
reg init;
reg DoIt;
//reg NoDoIt;
//reg MakeIt=(DoIt && ~NoDoIt);
initial
begin
i=0;
j=0;
init=0;
regis=0;
regis0=0;
Rx_error=0;
DONE=0;
k=0;
DoIt=1;
//NoDoIt=0;
end
always@(posedge CLKOUT)
begin
if(!Rx&&!i)
begin
init<=1;
end
// lectura //
// lectura //
// lectura //
if(init)
begin
regis[i]=Rx;
i<=i+1;
if(regis[i]&&(i<8))
begin
j=j+1;
end
end
if(DoIt)
begin
k<=k+1;
end
if(k==3)
begin
DONE=0;
DoIt=0;
Rx_error=0;
end
if(!DoIt)
begin
k<=0;
end
if(i==9)
begin
DoIt=1;
end
else
begin
end
// finalizar //
// finalizar //
// finalizar //
if(i==9)
begin
if(((j%2)&&(regis[8]))||(!(j%2)&&(!regis[8])))
begin
Rx_error=0;
regis0={regis[7:0]};
DONE=1;
end
else
begin
Rx_error=1;
regis0=0;
DONE=0;
end
j=0;
i<=0;
init=0;
end
end
assign DATA=regis0;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; char c[2] = { w , b }; cin >> n; if (n % 2 == 1) cout << -1 ; else { for (int i = 1; i <= n; i++) { for (int j = 0; j < n; j++) { for (int k = 0; k < n; k++) { if ((j / 2) % 2 == 0) if ((k / 2) % 2 == 0) cout << c[i % 2]; else cout << c[!(i % 2)]; if ((j / 2) % 2 == 1) if ((k / 2) % 2 == 0) cout << c[!(i % 2)]; else cout << c[i % 2]; } cout << endl; } cout << endl; } } return 0; } |
/* HW4, Problem 24b */
module jerk_ct(output reg [7:0] count, input clk, reset);
reg [3:0] state; // 0 to 13 needed.
reg [7:0] icount;
always @(icount)
count <= { icount[0], icount[1], icount[2], icount[3],
icount[4], icount[5], icount[6], icount[7] };
always @(posedge clk) begin
if (reset == 1) begin
state = 13;
end
case(state)
0: begin icount <= 8'b00000010; state <= 1; end
1: begin icount <= 8'b00000001; state <= 2; end
2: begin icount <= 8'b00000100; state <= 3; end
3: begin icount <= 8'b00000001; state <= 4; end
4: begin icount <= 8'b00001000; state <= 5; end
5: begin icount <= 8'b00000001; state <= 6; end
6: begin icount <= 8'b00010000; state <= 7; end
7: begin icount <= 8'b00000001; state <= 8; end
8: begin icount <= 8'b00100000; state <= 9; end
9: begin icount <= 8'b00000001; state <= 10;end
10:begin icount <= 8'b01000000; state <= 11;end
11:begin icount <= 8'b00000001; state <= 12;end
12:begin icount <= 8'b10000000; state <= 13;end
13,14,15:
begin icount <= 8'b00000001; state <= 0; end
endcase
end
endmodule
module p24_tb();
reg clk, reset;
wire [7:0] count;
jerk_ct device(count, clk, reset);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
reset = 0;
reset = 1;
#10 reset = 0;
$dumpfile("p24b.vcd");
$dumpvars(0, device);
fork
#201 reset = 1;
#205 reset = 0;
#300 reset = 1;
#320 reset = 0;
#500 $finish;
join
end
endmodule
|
//-------------------------------------------------------------------
//-- echo_tb.v
//-- Testbench for the simulation of the echo.v
//-------------------------------------------------------------------
//-- (c) BQ December 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- GPL License
//-------------------------------------------------------------------
`timescale 100 ns / 10 ns
`include "baudgen.vh"
module echo_tb();
//-- Baudrate for the simulation
localparam BAUDRATE = `B115200;
//-- clock tics needed for sending one serial package
localparam SERIAL_PACK = (BAUDRATE * 10);
//-- Time between two characters
localparam WAIT = (BAUDRATE * 4);
//----------------------------------------
//-- Task for sending a character in serial
//----------------------------------------
task send_char;
input [7:0] char;
begin
rx <= 0; //-- Send the Start bit
#BAUDRATE rx <= char[0]; //-- Bit 0
#BAUDRATE rx <= char[1]; //-- Bit 1
#BAUDRATE rx <= char[2]; //-- Bit 2
#BAUDRATE rx <= char[3]; //-- Bit 3
#BAUDRATE rx <= char[4]; //-- Bit 4
#BAUDRATE rx <= char[5]; //-- Bit 5
#BAUDRATE rx <= char[6]; //-- Bit 6
#BAUDRATE rx <= char[7]; //-- Bit 7
#BAUDRATE rx <= 1; //-- stop bit
#BAUDRATE rx <= 1; //-- Wait until the bits stop is sent
end
endtask
//-- System clock
reg clk = 0;
//-- Wire connected to the rx port for transmiting to the receiver
reg rx = 1;
//-- Wire connected to tx for receiving the echo
wire tx;
//-- For connecting the leds
wire [3:0] leds;
//-- Instantiate the entity to test
echo #(.BAUDRATE(BAUDRATE))
dut(
.clk(clk),
.rx(rx),
.tx(tx)
);
//-- Clock generator
always
# 0.5 clk <= ~clk;
initial begin
//-- File where to store the simulation
$dumpfile("echo_tb.vcd");
$dumpvars(0, echo_tb);
//-- Sent some data
#BAUDRATE send_char(8'h55);
#WAIT send_char("K");
#(WAIT * 4) $display("END of the simulation");
$finish;
end
endmodule
|
// The MLAB
// --------
// In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic
// Modules (ALMs, see alm_sim.v), the Cyclone V/10GX also contain
// Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise
// the memory the ALM uses to store the look-up table data for general usage,
// producing a 32 address by 20-bit block of memory. MLABs are spread out
// around the chip, so they can be placed near where they are needed, rather than
// being comparatively limited in placement for a deep but narrow memory such as
// the M10K memory block.
//
// MLABs are used mainly for shallow but wide memories, such as CPU register
// files (which have perhaps 32 registers that are comparatively wide (16/32-bit))
// or shift registers (by using the output of the Nth bit as input for the N+1th
// bit).
//
// Oddly, instead of providing a block 32 address by 20-bit cell, Quartus asks
// synthesis tools to build MLABs out of 32 address by 1-bit cells, and tries
// to put these cells in the same MLAB during cell placement. Because of this
// a MISTRAL_MLAB cell represents one of these 32 address by 1-bit cells, and
// 20 of them represent a physical MLAB.
//
// How the MLAB works
// ------------------
// MLABs are poorly documented, so the following information is based mainly
// on the simulation model and my knowledge of how memories like these work.
// Additionally, note that the ports of MISTRAL_MLAB are the ones auto-generated
// by the Yosys `memory_bram` pass, and it doesn't make sense to me to use
// `techmap` just for the sake of renaming the cell ports.
//
// The MLAB can be initialised to any value, but unfortunately Quartus only
// allows memory initialisation from a file. Since Yosys doesn't preserve input
// file information, or write the contents of an `initial` block to a file,
// Yosys can't currently initialise the MLAB in a way Quartus will accept.
//
// The MLAB takes in data from A1DATA at the rising edge of CLK1, and if A1EN
// is high, writes it to the address in A1ADDR. A1EN can therefore be used to
// conditionally write data to the MLAB.
//
// Simultaneously, the MLAB reads data from B1ADDR, and outputs it to B1DATA,
// asynchronous to CLK1 and ignoring A1EN. If a synchronous read is needed
// then the output can be fed to embedded flops. Presently, Yosys assumes
// Quartus will pack external flops into the MLAB, but this is an assumption
// that needs testing.
// The vendor sim model outputs 'x for a very short period (a few
// combinational delta cycles) after each write. This has been omitted from
// the following model because it's very difficult to trigger this in practice
// as clock cycles will be much longer than any potential blip of 'x, so the
// model can be treated as always returning a defined result.
(* abc9_box, lib_whitebox *)
module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN,
(* clkbuf_sink *) input CLK1,
input [4:0] B1ADDR, output B1DATA);
reg [31:0] mem = 32'b0;
`ifdef cyclonev
specify
$setup(A1ADDR, posedge CLK1, 86);
$setup(A1DATA, posedge CLK1, 86);
$setup(A1EN, posedge CLK1, 86);
(B1ADDR[0] => B1DATA) = 487;
(B1ADDR[1] => B1DATA) = 475;
(B1ADDR[2] => B1DATA) = 382;
(B1ADDR[3] => B1DATA) = 284;
(B1ADDR[4] => B1DATA) = 96;
endspecify
`endif
`ifdef arriav
specify
$setup(A1ADDR, posedge CLK1, 62);
$setup(A1DATA, posedge CLK1, 62);
$setup(A1EN, posedge CLK1, 62);
(B1ADDR[0] => B1DATA) = 370;
(B1ADDR[1] => B1DATA) = 292;
(B1ADDR[2] => B1DATA) = 218;
(B1ADDR[3] => B1DATA) = 74;
(B1ADDR[4] => B1DATA) = 177;
endspecify
`endif
`ifdef cyclone10gx
// TODO: Cyclone 10 GX timings; the below timings are for Cyclone V
specify
$setup(A1ADDR, posedge CLK1, 86);
$setup(A1DATA, posedge CLK1, 86);
$setup(A1EN, posedge CLK1, 86);
(B1ADDR[0] => B1DATA) = 487;
(B1ADDR[1] => B1DATA) = 475;
(B1ADDR[2] => B1DATA) = 382;
(B1ADDR[3] => B1DATA) = 284;
(B1ADDR[4] => B1DATA) = 96;
endspecify
`endif
always @(posedge CLK1)
if (A1EN) mem[A1ADDR] <= A1DATA;
assign B1DATA = mem[B1ADDR];
endmodule
// The M10K
// --------
// TODO
module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
(* clkbuf_sink *) input CLK1;
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input A1EN, B1EN;
output reg [CFG_DBITS-1:0] B1DATA;
reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0;
`ifdef cyclonev
specify
$setup(A1ADDR, posedge CLK1, 125);
$setup(A1DATA, posedge CLK1, 97);
$setup(A1EN, posedge CLK1, 140);
$setup(B1ADDR, posedge CLK1, 125);
$setup(B1EN, posedge CLK1, 161);
if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 1004;
endspecify
`endif
`ifdef arriav
specify
$setup(A1ADDR, posedge CLK1, 97);
$setup(A1DATA, posedge CLK1, 74);
$setup(A1EN, posedge CLK1, 109);
$setup(B1ADDR, posedge CLK1, 97);
$setup(B1EN, posedge CLK1, 126);
if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 787;
endspecify
`endif
always @(posedge CLK1) begin
if (!A1EN)
mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA;
if (B1EN)
B1DATA <= mem[(B1ADDR + 1) * CFG_DBITS - 1 : B1ADDR * CFG_DBITS];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 100000 + 5; map<long long int, int> mp; queue<int> Q; int vis[M]; long long int dk[M]; vector<long long int> step; long long int a[M]; int rch[M]; struct TREE { int lc; int rc; long long int l; long long int r; long long int idx; long long int val; } tree[20 * M]; int tot = 1; void update(long long int l, long long int r, int node, long long int val, long long int idx) { if (l == r) { tree[node].val += val; tree[node].l = l; tree[node].r = r; tree[node].idx = idx; tree[node].lc = node; tree[node].rc = node; return; } long long int m = (l + r) / 2; if (tree[node].lc == 0) { tot++; tree[node].lc = tot; } if (tree[node].rc == 0) { tot++; tree[node].rc = tot; } if (idx <= m) { update(l, m, tree[node].lc, val, idx); } else { update(m + 1, r, tree[node].rc, val, idx); } int lc = tree[node].lc; int rc = tree[node].rc; if (tree[lc].val < tree[rc].val) { tree[node].idx = tree[rc].idx; tree[node].val = tree[rc].val; } else { tree[node].idx = tree[lc].idx; tree[node].val = tree[lc].val; } return; } int main() { time_t t_start, t_end; t_start = clock(); long long int h; cin >> h; int n, m, k; cin >> n >> m >> k; for (int i = 0; i < n; i++) { long long int ai; int ci; cin >> ai >> ci; a[i + 1] = ai; mp[ai] = ci; if (ai % k == 1) { rch[i + 1] = 1; update(1, M, 1, ci, i + 1); } } step.push_back(k); for (int q = 0; q < m; q++) { int ty; cin >> ty; if (ty == 1) { long long int x; cin >> x; step.push_back(x); for (int i = 0; i < M; i++) { vis[i] = 0; dk[i] = -1; } Q.push(1); dk[1] = 0; while (!Q.empty()) { int u = Q.front(); vis[u] = 0; Q.pop(); for (int i = 0; i < step.size(); i++) { long long int dx = step[i]; int nxtu = (u + dx) % k; long long int nxty = (u + dk[u] * k + dx) / k; if (dk[nxtu] == -1 || dk[nxtu] > nxty) { dk[nxtu] = nxty; if (vis[nxtu] == 0) { Q.push(nxtu); vis[nxtu] = 1; } } } } for (int i = 1; i <= n; i++) { long long int ai = a[i]; int u = ai % k; if (dk[u] != -1) { long long int yy = dk[u] * k + u; if (ai >= yy && rch[i] == 0) { rch[i] = 1; update(1, M, 1, mp[ai], i); } } } } if (ty == 2) { int x; long long int y; cin >> x >> y; long long int ai = a[x]; mp[ai] = mp[ai] - y; if (rch[x] == 1) { update(1, M, 1, -y, x); } } if (ty == 3) { long long int res = tree[1].val; cout << res << endl; update(1, M, 1, -res, tree[1].idx); } } t_end = clock(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211A_2_V
`define SKY130_FD_SC_HS__O211A_2_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o211a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o211a_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o211a_2 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o211a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211A_2_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:27:56 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_rgb565_to_rgb888_1_0 -prefix
// system_rgb565_to_rgb888_1_0_ system_rgb565_to_rgb888_0_0_sim_netlist.v
// Design : system_rgb565_to_rgb888_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_rgb565_to_rgb888_1_0_rgb565_to_rgb888
(rgb_888,
rgb_565,
clk);
output [15:0]rgb_888;
input [15:0]rgb_565;
input clk;
wire clk;
wire [15:0]rgb_565;
wire [15:0]rgb_888;
FDRE \rgb_888_reg[10]
(.C(clk),
.CE(1'b1),
.D(rgb_565[5]),
.Q(rgb_888[5]),
.R(1'b0));
FDRE \rgb_888_reg[11]
(.C(clk),
.CE(1'b1),
.D(rgb_565[6]),
.Q(rgb_888[6]),
.R(1'b0));
FDRE \rgb_888_reg[12]
(.C(clk),
.CE(1'b1),
.D(rgb_565[7]),
.Q(rgb_888[7]),
.R(1'b0));
FDRE \rgb_888_reg[13]
(.C(clk),
.CE(1'b1),
.D(rgb_565[8]),
.Q(rgb_888[8]),
.R(1'b0));
FDRE \rgb_888_reg[14]
(.C(clk),
.CE(1'b1),
.D(rgb_565[9]),
.Q(rgb_888[9]),
.R(1'b0));
FDRE \rgb_888_reg[15]
(.C(clk),
.CE(1'b1),
.D(rgb_565[10]),
.Q(rgb_888[10]),
.R(1'b0));
FDRE \rgb_888_reg[19]
(.C(clk),
.CE(1'b1),
.D(rgb_565[11]),
.Q(rgb_888[11]),
.R(1'b0));
FDRE \rgb_888_reg[20]
(.C(clk),
.CE(1'b1),
.D(rgb_565[12]),
.Q(rgb_888[12]),
.R(1'b0));
FDRE \rgb_888_reg[21]
(.C(clk),
.CE(1'b1),
.D(rgb_565[13]),
.Q(rgb_888[13]),
.R(1'b0));
FDRE \rgb_888_reg[22]
(.C(clk),
.CE(1'b1),
.D(rgb_565[14]),
.Q(rgb_888[14]),
.R(1'b0));
FDRE \rgb_888_reg[23]
(.C(clk),
.CE(1'b1),
.D(rgb_565[15]),
.Q(rgb_888[15]),
.R(1'b0));
FDRE \rgb_888_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_565[0]),
.Q(rgb_888[0]),
.R(1'b0));
FDRE \rgb_888_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_565[1]),
.Q(rgb_888[1]),
.R(1'b0));
FDRE \rgb_888_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_565[2]),
.Q(rgb_888[2]),
.R(1'b0));
FDRE \rgb_888_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_565[3]),
.Q(rgb_888[3]),
.R(1'b0));
FDRE \rgb_888_reg[7]
(.C(clk),
.CE(1'b1),
.D(rgb_565[4]),
.Q(rgb_888[4]),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "rgb565_to_rgb888,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_rgb565_to_rgb888_1_0
(clk,
rgb_565,
rgb_888);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [15:0]rgb_565;
output [23:0]rgb_888;
wire \<const0> ;
wire clk;
wire [15:0]rgb_565;
wire [20:3]\^rgb_888 ;
assign rgb_888[23:21] = \^rgb_888 [18:16];
assign rgb_888[20:16] = \^rgb_888 [20:16];
assign rgb_888[15:14] = \^rgb_888 [9:8];
assign rgb_888[13:3] = \^rgb_888 [13:3];
assign rgb_888[2] = \<const0> ;
assign rgb_888[1] = \<const0> ;
assign rgb_888[0] = \<const0> ;
GND GND
(.G(\<const0> ));
system_rgb565_to_rgb888_1_0_rgb565_to_rgb888 U0
(.clk(clk),
.rgb_565(rgb_565),
.rgb_888({\^rgb_888 [18:16],\^rgb_888 [20:19],\^rgb_888 [9:8],\^rgb_888 [13:10],\^rgb_888 [7:3]}));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module serial_rx #(
parameter CLK_PER_BIT = 50
)(
input clk,
input rst,
input rx,
output [7:0] data,
output new_data
);
// clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value
parameter CTR_SIZE = $clog2(CLK_PER_BIT);
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0,
WAIT_HALF = 2'd1,
WAIT_FULL = 2'd2,
WAIT_HIGH = 2'd3;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [2:0] bit_ctr_d, bit_ctr_q;
reg [7:0] data_d, data_q;
reg new_data_d, new_data_q;
reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
reg rx_d, rx_q;
assign new_data = new_data_q;
assign data = data_q;
always @(*) begin
rx_d = rx;
state_d = state_q;
ctr_d = ctr_q;
bit_ctr_d = bit_ctr_q;
data_d = data_q;
new_data_d = 1'b0;
case (state_q)
IDLE: begin
bit_ctr_d = 3'b0;
ctr_d = 1'b0;
if (rx_q == 1'b0) begin
state_d = WAIT_HALF;
end
end
WAIT_HALF: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == (CLK_PER_BIT >> 1)) begin
ctr_d = 1'b0;
state_d = WAIT_FULL;
end
end
WAIT_FULL: begin
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
data_d = {rx_q, data_q[7:1]};
bit_ctr_d = bit_ctr_q + 1'b1;
ctr_d = 1'b0;
if (bit_ctr_q == 3'd7) begin
state_d = WAIT_HIGH;
new_data_d = 1'b1;
end
end
end
WAIT_HIGH: begin
if (rx_q == 1'b1) begin
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
ctr_q <= 1'b0;
bit_ctr_q <= 3'b0;
new_data_q <= 1'b0;
state_q <= IDLE;
end else begin
ctr_q <= ctr_d;
bit_ctr_q <= bit_ctr_d;
new_data_q <= new_data_d;
state_q <= state_d;
end
rx_q <= rx_d;
data_q <= data_d;
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XOR2_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9; const long long MOD = 1e9 + 7; const int MAXN = 705; const int bignumlen = 17; const int Blen = 8; const long long base = 100000000; struct bignum { int len; long long data[bignumlen]; long long &operator[](int x) { return (data[x]); } const long long &operator[](int x) const { return (data[x]); } bignum() { memset(data, 0, sizeof(data)); len = 0; } void clear() { for (int i = len; i >= 1; --i) data[i] = 0; len = 0; } int check(const bignum &a, const bignum &b) { if (a.len > b.len) return (0); if (b.len > a.len) return (1); for (int i = a.len; i >= 1; --i) { if (a.data[i] < b.data[i]) return (1); if (b.data[i] < a.data[i]) return (0); } return 2; } bool operator<(const bignum &b) { return (check(*this, b) == 1); } bool operator>(const bignum &b) { return (check(*this, b) == 0); } bool operator<=(const bignum &b) { return (check(*this, b) >= 1); } bool operator>=(const bignum &b) { return (check(*this, b) % 2 == 0); } bool operator!=(const bignum &b) { return (check(*this, b) != 2); } bool operator==(const bignum &b) { return (check(*this, b) == 2); } bignum operator=(const bignum &x) { for (int i = x.len + 1; i <= len; ++i) data[i] = 0; for (int i = 1; i <= x.len; ++i) data[i] = x.data[i]; len = x.len; return *this; } bignum operator=(long long x) { for (int i = len; i >= 0; --i) data[i] = 0; len = 0; while (x) { data[++len] = x % base; x /= base; } return *this; } bignum(long long x) { memset(data, 0, sizeof(data)); len = 0; (*this) = x; } bignum operator*(const bignum &b) { int i, j; bignum tmp; for (i = 1; i <= len; ++i) if (data[i] != 0) for (j = 1; j <= b.len; ++j) if (b.data[j] != 0) { tmp.data[i + j - 1] += data[i] * b.data[j]; tmp.data[i + j] += tmp.data[i + j - 1] / base; tmp.data[i + j - 1] %= base; } tmp.len = len + b.len - 1; while (tmp.data[tmp.len + 1]) tmp.len++; return tmp; } bignum operator*(long long x) { int i; bignum tmp; for (i = 1; i <= len; ++i) tmp[i] = data[i] * x; tmp.len = len; for (i = 1; i <= len; ++i) { tmp[i + 1] += tmp[i] / base, tmp[i] %= base; if (tmp[i + 1] && i + 1 > tmp.len) tmp.len++; } return tmp; } bignum operator/(long long x) { int i; bignum tmp; long long y = 0; for (i = len; i >= 1; --i) { y = y * base + data[i]; tmp[i] = y / x; y %= x; } tmp.len = len; while (tmp[tmp.len] == 0 && tmp.len > 1) tmp.len--; return tmp; } bignum operator/(const bignum &b) { if (b.len <= 1 && b[1] == 0) { printf( error! ?0?! ); for (;;) ; } int i, l1 = (len - 1) * Blen, l2 = (b.len - 1) * Blen; long long x = data[len], y = b[b.len]; while (x) x /= 10, l1++; while (y) y /= 10, l2++; bignum tmp, chu, B; chu = *this; B = b; for (i = 1; i * Blen <= l1 - l2; ++i) B *= base; for (i = 1; i <= (l1 - l2) % Blen; ++i) B *= 10; for (i = l1 - l2; i >= 0; --i) { x = 0; while (chu >= B) chu -= B, x++; tmp[i / Blen + 1] = tmp[i / Blen + 1] * 10 + x; B /= 10; } tmp.len = (l1 - l2) / Blen + 1; while (tmp.len >= 1 && !tmp[tmp.len]) tmp.len--; return tmp; } bignum operator+(const bignum &b) { bignum tmp; int i, l = max(len, b.len); for (i = 1; i <= l; ++i) tmp[i] = data[i] + b[i]; for (i = 1; i <= l; ++i) tmp[i + 1] += tmp[i] / base, tmp[i] %= base; tmp.len = l; if (tmp[tmp.len + 1]) tmp.len++; return tmp; } bignum operator+(long long x) { bignum tmp; tmp = *this; tmp[1] += x; for (int i = 1; i <= len && tmp[i] >= base; ++i) tmp[i + 1] += tmp[i] / base, tmp[i] %= base; while (tmp[tmp.len + 1]) tmp.len++; return tmp; } bignum operator-(const bignum &b) { int i; bignum tmp; for (i = 1; i <= len; ++i) tmp.data[i] = data[i] - b.data[i]; for (i = 1; i <= len; ++i) { if (tmp[i] < 0) tmp.data[i] += base, tmp.data[i + 1]--; } tmp.len = len; while (tmp[tmp.len] == 0 && tmp.len > 1) tmp.len--; return tmp; } bignum operator-(long long x) { bignum tmp; tmp = *this; tmp[1] -= x; for (int i = 1; i <= len && tmp[i] < 0; ++i) { tmp[i + 1] += (tmp[i] + 1) / base - 1; tmp[i] = (tmp[i] + 1) % base + base - 1; } while (!tmp[tmp.len] && tmp.len > 1) tmp.len--; return tmp; } long long operator%(long long x) { int i; long long y = 0; for (i = len; i >= 1; --i) y = (y * base + data[i]) % x; return y; } bignum operator%(const bignum &b) { if (b.len <= 1 && b[1] == 0) { printf( error! ?0 mod! ); for (;;) ; } int i, l1 = (len - 1) * Blen, l2 = (b.len - 1) * Blen; long long x = data[len], y = b[b.len]; while (x) x /= 10, l1++; while (y) y /= 10, l2++; bignum chu, B; chu = *this; B = b; for (i = 1; i * Blen <= l1 - l2; ++i) B *= base; for (i = 1; i <= (l1 - l2) % Blen; ++i) B *= 10; for (i = l1 - l2; i >= 0; --i) { while (chu >= B) chu -= B; B /= 10; } return chu; } bignum operator+=(const bignum &b) { return *this = (*this + b); } bignum operator*=(const bignum &b) { return *this = (*this * b); } bignum operator-=(const bignum &b) { return *this = (*this - b); } bignum operator/=(const bignum &b) { return *this = (*this / b); } bignum operator%=(const bignum &b) { return *this = (*this % b); } bignum operator*=(long long x) { return (*this = (*this * x)); } bignum operator+=(long long x) { return (*this = (*this + x)); } bignum operator-=(long long x) { return (*this = (*this - x)); } bignum operator/=(long long x) { return (*this = (*this / x)); } void read() { char c[bignumlen * Blen + 10]; scanf( %s , c + 1); int l = strlen(c + 1); (*this).clear(); long long x; for (int i = 1; i <= (l - 1) / Blen + 1; ++i) { x = 0; for (int j = l - Blen * i + 1; j <= l - Blen * i + Blen; ++j) if (j >= 1) x = x * 10 + c[j] - 48; data[++len] = x; } } void write() { printf( %I64d , data[len]); for (int i = len - 1; i >= 1; --i) printf( %0*I64d , Blen, data[i]); } }; int n; vector<bignum> DP[MAXN]; vector<int> v[MAXN]; int sz[MAXN]; int dfs(int now, int p) { DP[now].push_back(0); DP[now].push_back(1); sz[now] = 1; for (int ea = 0; ea < v[now].size(); ea++) { int sek = v[now][ea]; if (sek == p) continue; sz[now] += dfs(sek, now); vector<bignum> ans(MAXN); for (int j = 0; j < MAXN; j++) ans[j] = -1; for (int i = 1; i <= DP[now].size() - 1; i++) { for (int j = 1; j <= DP[sek].size() - 1; j++) { bignum tmp = DP[now][i] / i * DP[sek][j] / j * (i + j); if (tmp > ans[i + j]) ans[i + j] = tmp; tmp = DP[now][i] * DP[sek][j]; if (tmp > ans[i]) ans[i] = tmp; } } ans[0] = 0; DP[now].clear(); for (int j = 0; j < MAXN; j++) { if (ans[j] == -1) break; DP[now].push_back(ans[j]); } } return sz[now]; } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; a--, b--; v[a].push_back(b); v[b].push_back(a); } dfs(0, -1); bignum res = DP[0][1]; for (int i = 2; i <= DP[0].size() - 1; i++) if (DP[0][i] > res) res = DP[0][i]; res.write(); } |
#include <bits/stdc++.h> using namespace std; long long n, k, q, a, b, ans, t; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> q; while (q--) { cin >> k >> n >> a >> b; ans = a * n; if (b * n >= k) cout << -1 << n ; else { if (ans < k) cout << n << n ; else { t = a - b; ans = (ans - k) / t + 1; cout << n - ans << n ; } } } return 0; } |
// NIOS_SYSTEMV3_tristate_bridge_ssram_pinSharer.v
// This file was auto-generated from altera_tristate_conduit_pin_sharer_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.0sp1 232 at 2015.10.23.09:55:04
`timescale 1 ps / 1 ps
module NIOS_SYSTEMV3_tristate_bridge_ssram_pinSharer (
input wire clk_clk, // clk.clk
input wire reset_reset, // reset.reset
output wire request, // tcm.request
input wire grant, // .grant
output wire [0:0] chipenable1_n_to_the_ssram, // .chipenable1_n_to_the_ssram_out
output wire [3:0] bw_n_to_the_ssram, // .bw_n_to_the_ssram_out
output wire [0:0] outputenable_n_to_the_ssram, // .outputenable_n_to_the_ssram_out
output wire [0:0] bwe_n_to_the_ssram, // .bwe_n_to_the_ssram_out
output wire [31:0] data_to_and_from_the_ssram, // .data_to_and_from_the_ssram_out
input wire [31:0] data_to_and_from_the_ssram_in, // .data_to_and_from_the_ssram_in
output wire data_to_and_from_the_ssram_outen, // .data_to_and_from_the_ssram_outen
output wire [20:0] address_to_the_ssram, // .address_to_the_ssram_out
output wire [0:0] reset_n_to_the_ssram, // .reset_n_to_the_ssram_out
output wire [0:0] adsc_n_to_the_ssram, // .adsc_n_to_the_ssram_out
input wire tcs0_request, // tcs0.request
output wire tcs0_grant, // .grant
input wire [0:0] tcs0_chipselect_n_out, // .chipselect_n_out
input wire [3:0] tcs0_byteenable_n_out, // .byteenable_n_out
input wire [0:0] tcs0_outputenable_n_out, // .outputenable_n_out
input wire [0:0] tcs0_write_n_out, // .write_n_out
input wire [31:0] tcs0_data_out, // .data_out
output wire [31:0] tcs0_data_in, // .data_in
input wire tcs0_data_outen, // .data_outen
input wire [20:0] tcs0_address_out, // .address_out
input wire [0:0] tcs0_reset_n_out, // .reset_n_out
input wire [0:0] tcs0_begintransfer_n_out // .begintransfer_n_out
);
wire [0:0] arbiter_grant_data; // arbiter:next_grant -> pin_sharer:next_grant
wire arbiter_grant_ready; // pin_sharer:ack -> arbiter:ack
wire pin_sharer_tcs0_arb_valid; // pin_sharer:arb_SSRAM_tcm -> arbiter:sink0_valid
NIOS_SYSTEMV3_tristate_bridge_ssram_pinSharer_pin_sharer pin_sharer (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // reset.reset
.request (request), // tcm.request
.grant (grant), // .grant
.chipenable1_n_to_the_ssram (chipenable1_n_to_the_ssram), // .chipenable1_n_to_the_ssram_out
.bw_n_to_the_ssram (bw_n_to_the_ssram), // .bw_n_to_the_ssram_out
.outputenable_n_to_the_ssram (outputenable_n_to_the_ssram), // .outputenable_n_to_the_ssram_out
.bwe_n_to_the_ssram (bwe_n_to_the_ssram), // .bwe_n_to_the_ssram_out
.data_to_and_from_the_ssram (data_to_and_from_the_ssram), // .data_to_and_from_the_ssram_out
.data_to_and_from_the_ssram_in (data_to_and_from_the_ssram_in), // .data_to_and_from_the_ssram_in
.data_to_and_from_the_ssram_outen (data_to_and_from_the_ssram_outen), // .data_to_and_from_the_ssram_outen
.address_to_the_ssram (address_to_the_ssram), // .address_to_the_ssram_out
.reset_n_to_the_ssram (reset_n_to_the_ssram), // .reset_n_to_the_ssram_out
.adsc_n_to_the_ssram (adsc_n_to_the_ssram), // .adsc_n_to_the_ssram_out
.tcs0_request (tcs0_request), // tcs0.request
.tcs0_grant (tcs0_grant), // .grant
.tcs0_tcm_chipselect_n_out (tcs0_chipselect_n_out), // .chipselect_n_out
.tcs0_tcm_byteenable_n_out (tcs0_byteenable_n_out), // .byteenable_n_out
.tcs0_tcm_outputenable_n_out (tcs0_outputenable_n_out), // .outputenable_n_out
.tcs0_tcm_write_n_out (tcs0_write_n_out), // .write_n_out
.tcs0_tcm_data_out (tcs0_data_out), // .data_out
.tcs0_tcm_data_in (tcs0_data_in), // .data_in
.tcs0_tcm_data_outen (tcs0_data_outen), // .data_outen
.tcs0_tcm_address_out (tcs0_address_out), // .address_out
.tcs0_tcm_reset_n_out (tcs0_reset_n_out), // .reset_n_out
.tcs0_tcm_begintransfer_n_out (tcs0_begintransfer_n_out), // .begintransfer_n_out
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.arb_SSRAM_tcm (pin_sharer_tcs0_arb_valid) // tcs0_arb.valid
);
NIOS_SYSTEMV3_tristate_bridge_ssram_pinSharer_arbiter arbiter (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // clk_reset.reset
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.sink0_valid (pin_sharer_tcs0_arb_valid) // sink0.valid
);
endmodule
|
#include <bits/stdc++.h> using namespace std; void solve() { string s; cin >> s; int arr[26] = {}; int n = s.length(); int count = 0; for (int i = 0; i < n; i++) { arr[s[i] - a ]++; if (arr[s[i] - a ] == 2) { arr[s[i] - a ] = 0; count--; } else count++; } if (count == 0 || count == 1) { cout << First << n ; } else { if (count % 2 == 0) { cout << Second << n ; } else cout << First << n ; } } int main() { long long t = 1; while (t--) solve(); } |
module alt_vipvfr131_common_avalon_mm_master
( clock,
reset,
// Avalon-MM master interface
av_clock,
av_reset,
av_address,
av_burstcount,
av_writedata,
av_readdata,
av_write,
av_read,
av_readdatavalid,
av_waitrequest,
// user algorithm interface
addr,
command,
is_burst,
is_write_not_read,
burst_length,
writedata,
write,
readdata,
read,
stall);
parameter ADDR_WIDTH = 16;
parameter DATA_WIDTH = 16;
parameter MAX_BURST_LENGTH_REQUIREDWIDTH = 11;
parameter READ_USED = 1;
parameter WRITE_USED = 1;
parameter READ_FIFO_DEPTH = 8;
parameter WRITE_FIFO_DEPTH = 8;
parameter COMMAND_FIFO_DEPTH = 8;
parameter WRITE_TARGET_BURST_SIZE = 5;
parameter READ_TARGET_BURST_SIZE = 5;
parameter CLOCKS_ARE_SAME = 1;
parameter BURST_WIDTH = 6;
input clock;
input reset;
// Avalon-MM master interface
input av_clock;
input av_reset;
output [ADDR_WIDTH-1 : 0] av_address;
output [BURST_WIDTH-1 : 0] av_burstcount;
output [DATA_WIDTH-1 : 0] av_writedata;
input [DATA_WIDTH-1 : 0] av_readdata;
output av_write;
output av_read;
input av_readdatavalid;
input av_waitrequest;
// user algorithm interface
input [ADDR_WIDTH-1 : 0] addr;
input command;
input is_burst;
input is_write_not_read;
input [MAX_BURST_LENGTH_REQUIREDWIDTH-1 : 0] burst_length;
input [DATA_WIDTH-1 : 0] writedata;
input write;
output [DATA_WIDTH-1 : 0] readdata;
input read;
output stall;
// instantiate FU
alt_vipvfr131_common_avalon_mm_bursting_master_fifo
#(.ADDR_WIDTH (ADDR_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.READ_USED (READ_USED),
.WRITE_USED (WRITE_USED),
.CMD_FIFO_DEPTH (COMMAND_FIFO_DEPTH),
.RDATA_FIFO_DEPTH (READ_FIFO_DEPTH),
.WDATA_FIFO_DEPTH (WRITE_FIFO_DEPTH),
.WDATA_TARGET_BURST_SIZE (WRITE_TARGET_BURST_SIZE),
.RDATA_TARGET_BURST_SIZE (READ_TARGET_BURST_SIZE),
.CLOCKS_ARE_SYNC (CLOCKS_ARE_SAME),
.BYTEENABLE_USED (0), // not used
.LEN_BE_WIDTH (MAX_BURST_LENGTH_REQUIREDWIDTH),
.BURST_WIDTH (BURST_WIDTH),
.INTERRUPT_USED (0), // not used
.INTERRUPT_WIDTH (8))
fu_inst
( .clock (clock),
.reset (reset),
// ena must go low when dependencies of this functional unit stall.
// right now it's only dependent is itself as no other stalls affect it.
.ena (!stall),
.ready (),
.stall (stall),
//These stalls dont work with the single ena signal. So they aren't any use right now
//.stall_read (stall_in), // new FU output
//.stall_write (stall_out), // new FU output
//.stall_command (stall_command), // new FU output
.addr (addr),
.write (is_write_not_read),
.burst (is_burst),
.len_be (burst_length),
.cenable (1'b1),
.cenable_en (command),
.wdata (writedata),
.wenable (1'b1),
.wenable_en (write),
.rdata (readdata),
.renable (1'b1),
.renable_en (read),
.activeirqs (), // not used
.av_address (av_address),
.av_burstcount (av_burstcount),
.av_writedata (av_writedata),
.av_byteenable (), // not used
.av_write (av_write),
.av_read (av_read),
.av_clock (av_clock), // not used if CLOCKS_ARE_SAME = 1
.av_reset (av_reset), // not used inside FU
.av_readdata (av_readdata),
.av_readdatavalid (av_readdatavalid),
.av_waitrequest (av_waitrequest),
.av_interrupt (8'd0)); // not used
endmodule
|
#include <bits/stdc++.h> using namespace std; int a, n, d, t, v; double ans[100001]; double gets_ans() { double t1 = v * 1.0 / a; if (0.5 * a * t1 * t1 <= d) return t + t1 + (d - 0.5 * a * t1 * t1) / v; return sqrt(2.0 * d / a) + t; } int main() { cin >> n >> a >> d; for (int i = 0; i < n; i++) { cin >> t >> v; ans[i] = gets_ans(); if (i != 0 && ans[i] < ans[i - 1]) ans[i] = ans[i - 1]; printf( %.10lf n , ans[i]); } } |
module bootloader
#(
parameter DATA_WIDTH = 32,
parameter ADDR_WIDTH = 20
)
(/*autoport*/
input clk,
input rst_n,
// boot memory ports interface
output reg boot_mem_rd_en,
output reg [ADDR_WIDTH-1:0] boot_mem_addr,
input [DATA_WIDTH-1:0] boot_mem_rd_data,
// inst memory ports interface
output reg inst_mem_wr_en,
output reg [DATA_WIDTH-1:0] inst_mem_wr_data,
output reg [ADDR_WIDTH-1:0] inst_mem_addr,
output reg boot_mode
);
//*******************************************************
//Internal
//*******************************************************
//Local Parameters
localparam INIT_BOOT = 0,
READ_BOOT = 1,
WRITE_INST = 2,
END_BOOT = 3;
localparam COUNT_WIDTH = ADDR_WIDTH;
localparam STATE_WIDTH = 2;
localparam SRAM_SIZE = 'h120;
//Wires
//Registers
reg [STATE_WIDTH-1:0] state,
next_state;
reg [COUNT_WIDTH-1:0] count;
//*******************************************************
//General Purpose Signals
//*******************************************************
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state = INIT_BOOT;
end
else begin
state = next_state;
end
end
always @(*) begin
next_state = state;
case (state)
INIT_BOOT:
next_state = READ_BOOT;
READ_BOOT:
next_state = WRITE_INST;
WRITE_INST:
if (count == SRAM_SIZE)
next_state = END_BOOT;
else begin
next_state = READ_BOOT;
end
default next_state = INIT_BOOT;
endcase
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
count <= {COUNT_WIDTH{1'b0}};
end
else begin
if (inst_mem_wr_en) begin
count <= count + 1'b1;
end
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
boot_mode <= 1'b1;
end
else begin
if (state == END_BOOT)
boot_mode <= 1'b0;
end
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
boot_mem_rd_en <= 1'b0;
end
else begin
if (state == READ_BOOT) begin
boot_mem_rd_en <= 1'b1;
end
else begin
boot_mem_rd_en <= 1'b0;
end
end
end
always @(*) begin
boot_mem_addr = count;
inst_mem_wr_data = boot_mem_rd_data;
end
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
inst_mem_addr <= {ADDR_WIDTH{1'b0}};
inst_mem_wr_en <= 1'b0;
end
else begin
if (state == WRITE_INST) begin
inst_mem_addr <= {count,2'b00};
inst_mem_wr_en <= 1'b1;
end
else begin
inst_mem_addr <= {ADDR_WIDTH{1'b0}};
inst_mem_wr_en <= 1'b0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; class point { public: int x, y; point(int _x, int _y) { x = _x; y = _y; } string str() { stringstream ss; ss << ( << x << , << y << ) ; return ss.str(); } }; int main() { int n; cin >> n; point min = point(31400, 31400), max = point(0, 0); int used_area = 0; for (int i = 0; i < n; i++) { int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; point p1 = point(x1, y1), p2 = point(x2, y2); if (x1 < min.x) min.x = x1; if (y1 < min.y) min.y = y1; if (x2 > max.x) max.x = x2; if (y2 > max.y) max.y = y2; used_area += (x2 - x1) * (y2 - y1); } int total_area = (max.x - min.x) * (max.y - min.y); if (used_area == total_area && (max.x - min.x) == (max.y - min.y)) cout << YES << endl; else cout << NO << endl; return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [7:0] cyc; initial cyc = 0;
reg [31:0] loops;
reg [31:0] loops2;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
if (cyc == 8'd1) begin
$write("[%0t] t_loop: Running\n", $time);
// Unwind <
loops = 0;
loops2 = 0;
for (int i=0; i<16; i=i+1) begin
loops = loops + i; // surefire lint_off_line ASWEMB
loops2 = loops2 + i; // surefire lint_off_line ASWEMB
end
if (loops !== 120) $stop;
if (loops2 !== 120) $stop;
// Check we can declare the same signal twice
loops = 0;
for (int i=0; i<=16; i=i+1) begin
loops = loops + 1;
end
if (loops !== 17) $stop;
// Check type is correct
loops = 0;
for (byte unsigned i=5; i>4; i=i+1) begin
loops = loops + 1;
end
if (loops !== 251) $stop;
// Check large loops
loops = 0;
for (int i=0; i<100000; i=i+1) begin
loops = loops + 1;
end
if (loops !== 100000) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#ifndef _MY #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) #pragma GCC target( sse,sse2,sse3,ssse3,abm,mmx,tune=native ) #endif #include bits/stdc++.h #define int ll #define all(x) (x).begin(), (x).end() using namespace std; typedef long long ll; typedef long double ld; const int64_t INF = (int64_t)(2e18); const int inf = (int)(1e9 + 7); const int maxn = 500 * 1000 + 100; chrono::time_point<chrono::steady_clock> cl; double current_time() { return (double)(chrono::steady_clock::now() - cl).count() / 1e9; } //------------------------------------------// int32_t main(){ cl = chrono::steady_clock::now(); ios_base::sync_with_stdio(false); cout << fixed << setprecision(10); cin.tie(nullptr); #ifdef _MY freopen( VimProject/input.txt , r , stdin); freopen( VimProject/output.txt , w , stdout); #endif int n, k; cin >> n >> k; if (k == 1) { cout << 0; return 0; } vector<int> a(n); vector<int> sieve(1300000, 1); sieve[0] = sieve[1] = 0; vector<int> primes; map<int, vector<int>> ma; vector<pair<int, vector<int>>> gen; for (int i = 2; i < (int)sieve.size(); ++i){ if (sieve[i] == 0) continue; primes.push_back(i); for (int j = 2*i; j < (int)sieve.size(); j += i) sieve[j] = 0; } auto isprime = [&](int aa)->bool{ if (aa > ll(100000)*ll(100000)) return false; if (aa == 1) return false; for (int i = 2; i * i <= aa; ++i){ if (aa % i == 0) return false; } return true; }; for (auto& it : a) cin >> it; for (auto& it : a){ int cur = it; int rt = (int)sqrt((double)cur+0.1); if (rt*rt == cur && isprime(rt)) ma[rt].push_back(cur); else{ //cout << cur << endl; map<int, int> dec; for (auto& p : primes){ if (p*p > cur) break; while(cur % p == 0) { dec[p]++; cur /= p; } } if (isprime(cur)) { dec[cur]++; cur = 1; } //for (auto& it : dec) cout << it.first << << it.second << endl; if (cur != 1) continue; if (dec.size() == 0) continue; if (dec.size() == 1) ma[dec.begin()->first].push_back(it); if (dec.size() >= 2) { gen.push_back(make_pair(it, vector<int>())); for (auto& itt : dec) gen.back().second.push_back(itt.first); } } } //for (auto& it : ma) { // cout << it.first << : ; // for (auto& itt : it.second) cout << itt << ; // cout << endl; //} vector<int> bad; for (auto& it : ma){ sort(all(it.second)); if (it.second.size() == 1) bad.push_back(it.first); } for (auto& it : bad) ma.erase(it); vector<int> res; int cnt = 0; for (auto& it : ma) cnt += (int)it.second.size(); if (cnt <= k){ for (auto& it : ma){ for (auto& itt : it.second) res.push_back(itt); } for (auto& it : gen){ if ((int)res.size() == k) break; bool good = true; for (auto& itt : it.second) if (ma.count(itt) == 0) good = false; if (good) res.push_back(it.first); } if ((int)res.size() != k) cout << 0; else for (auto& it : res) cout << it << ; return 0; } else{ for (auto& it : ma) reverse(all(it.second)); if (k % 2 == 0){ for (auto& it : ma) { if ((int)res.size() == k) break; for (int i = 0; i < 2; ++i){ res.push_back(it.second.back()); it.second.pop_back(); } } for (auto& it : ma){ for (auto& itt : it.second){ if ((int)res.size() == k) break; res.push_back(itt); it.second.pop_back(); } } for (auto& it: res) cout << it << ; return 0; } else { int ok = -1; for (auto& it : ma){ if (ok != -1) break; if (it.second.size() > 2) ok = it.first; } if (ok != -1){ for (int i = 0; i < 3; ++i){ res.push_back(ma[ok].back()); ma[ok].pop_back(); } for (auto& it : ma){ if (it.first == ok) continue; if ((int)res.size() == k) break; for (int i = 0; i < 2; ++i){ res.push_back(it.second.back()); it.second.pop_back(); } } for (auto& it : ma){ for (auto& itt : it.second){ if ((int)res.size() == k) break; res.push_back(itt); } } for (auto& it : res) cout << it << ; } else{ pair<int, vector<int>> fine(-1, vector<int>()); for (auto& it : gen){ bool good = true; for (auto& itt : it.second) if (ma.count(itt) == 0) good = false; if (!good) continue; if (fine.first == -1 || fine.second.size() > it.second.size()) fine = it; } if (fine.first == -1) { cout << 0; return 0; } res.push_back(fine.first); set<int> used; for (auto& it : fine.second){ used.insert(it); for (int i = 0; i < 2; ++i){ res.push_back(ma[it].back()); ma[it].pop_back(); } } if ((int)res.size() > k){ cout << 0; return 0; } for (auto& it : ma){ if (used.count(it.first)) continue; if ((int)res.size() == k) break; for (int i = 0; i < 2; ++i){ res.push_back(it.second.back()); it.second.pop_back(); } } for (auto& it : ma){ for (auto& itt : it.second){ if ((int)res.size() == k) break; res.push_back(itt); } } for (auto& it : res) cout << it << ; } } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_2_V
`define SKY130_FD_SC_LP__AND3_2_V
/**
* and3: 3-input AND.
*
* Verilog wrapper for and3 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__and3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_2 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__and3_2 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__and3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_2_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k; cin >> n >> k; k--; int a[n]; int sum = 0; for (int i = 0; i < n; ++i) { cin >> a[i]; } if (a[k] == 1) sum++; for (int i = 1; i < n; ++i) { if (k - i < 0) { for (int j = k + i; j < n; ++j) { sum += a[j]; } break; } if (k + i >= n) { for (int j = k - i; j >= 0; --j) { sum += a[j]; } break; } if (a[k - i] == 1 && a[k + i] == 1) sum += 2; } cout << sum; return 0; } |
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* PTP tag insert module
*/
module ptp_tag_insert #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = DATA_WIDTH/8,
parameter TAG_WIDTH = 16,
parameter TAG_OFFSET = 1,
parameter USER_WIDTH = TAG_WIDTH+TAG_OFFSET
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] s_axis_tdata,
input wire [KEEP_WIDTH-1:0] s_axis_tkeep,
input wire s_axis_tvalid,
output wire s_axis_tready,
input wire s_axis_tlast,
input wire [USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] m_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_axis_tkeep,
output wire m_axis_tvalid,
input wire m_axis_tready,
output wire m_axis_tlast,
output wire [USER_WIDTH-1:0] m_axis_tuser,
/*
* Tag input
*/
input wire [TAG_WIDTH-1:0] s_axis_tag,
input wire s_axis_tag_valid,
output wire s_axis_tag_ready
);
reg [TAG_WIDTH-1:0] tag_reg = {TAG_WIDTH{1'b0}};
reg tag_valid_reg = 1'b0;
reg [USER_WIDTH-1:0] user;
assign s_axis_tready = m_axis_tready && tag_valid_reg;
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tkeep = s_axis_tkeep;
assign m_axis_tvalid = s_axis_tvalid && tag_valid_reg;
assign m_axis_tlast = s_axis_tlast;
assign m_axis_tuser = user;
assign s_axis_tag_ready = !tag_valid_reg;
always @* begin
user = s_axis_tuser;
user[TAG_OFFSET +: TAG_WIDTH] = tag_reg;
end
always @(posedge clk) begin
if (tag_valid_reg) begin
if (s_axis_tvalid && s_axis_tready && s_axis_tlast) begin
tag_valid_reg <= 1'b0;
end
end else begin
tag_reg <= s_axis_tag;
tag_valid_reg <= s_axis_tag_valid;
end
if (rst) begin
tag_valid_reg <= 1'b0;
end
end
endmodule
`resetall
|
`timescale 1ns/1ps
module SensorFSM #(
parameter DataWidth = 8
) (
input Reset_n_i,
input Clk_i,
// top level
input Enable_i,
output reg CpuIntr_o,
output [2*DataWidth-1:0] SensorValue_o,
// to/from Measure-FSM
output reg MeasureFSM_Start_o,
input MeasureFSM_Done_i,
input MeasureFSM_Error_i,
input [DataWidth-1:0] MeasureFSM_Byte0_i,
input [DataWidth-1:0] MeasureFSM_Byte1_i,
// parameters
input [2*DataWidth-1:0] ParamThreshold_i,
input [2*DataWidth-1:0] ParamCounterPreset_i
);
// Sensor FSM
localparam stDisabled = 3'b000;
localparam stIdle = 3'b001;
localparam stXfer = 3'b010;
localparam stNotify = 3'b011;
localparam stError = 3'b100;
reg [2:0] SensorFSM_State;
reg [2:0] SensorFSM_NextState;
wire SensorFSM_TimerOvfl;
reg SensorFSM_TimerPreset;
reg SensorFSM_TimerEnable;
wire SensorFSM_DiffTooLarge;
reg SensorFSM_StoreNewValue;
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic
// interconnecting signals
wire [2*DataWidth-1:0] SensorValue;
reg [2*DataWidth-1:0] Word0;
wire [2*DataWidth-1:0] AbsDiffResult;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_State <= stDisabled;
end
else
begin
SensorFSM_State <= SensorFSM_NextState;
end
end
always @(SensorFSM_State, Enable_i, SensorFSM_TimerOvfl, MeasureFSM_Done_i, MeasureFSM_Error_i, SensorFSM_DiffTooLarge)
begin // process SensorFSM_CombProc
SensorFSM_NextState = SensorFSM_State;
// control signal default values
SensorFSM_TimerPreset = 1'b1;
SensorFSM_TimerEnable = 1'b0;
MeasureFSM_Start_o = 1'b0;
SensorFSM_StoreNewValue = 1'b0;
CpuIntr_o = 1'b0;
// next state and output logic
case (SensorFSM_State)
stDisabled: begin
if (Enable_i == 1'b1)
begin
SensorFSM_NextState = stIdle;
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // start timer
end
end
stIdle: begin
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // timer running
if (Enable_i == 1'b0)
begin
SensorFSM_NextState = stDisabled;
end
else
if (SensorFSM_TimerOvfl == 1'b1)
begin
SensorFSM_NextState = stXfer;
MeasureFSM_Start_o = 1'b1;
end
end
stXfer: begin
if (MeasureFSM_Error_i == 1'b1)
begin
// on I2C Error go to state "stError" and notify the CPU
SensorFSM_NextState = stError;
CpuIntr_o = 1'b1; // notify CPU
end
else if (MeasureFSM_Done_i == 1'b1)
begin
if (SensorFSM_DiffTooLarge == 1'b1)
begin
SensorFSM_NextState = stNotify;
SensorFSM_TimerPreset = 1'b0;
SensorFSM_TimerEnable = 1'b1; // timer running
SensorFSM_StoreNewValue = 1'b1; // store new value
end
else
begin
SensorFSM_NextState = stIdle;
end
end
end
stNotify: begin
SensorFSM_TimerPreset = 1'b1;
SensorFSM_TimerEnable = 1'b0; // preset timer
SensorFSM_NextState = stIdle;
CpuIntr_o = 1'b1; // notify CPU
end
stError: begin
// stay in this error state until the FSM is disabled
if (Enable_i == 1'b0)
begin
SensorFSM_NextState = stDisabled;
end
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [2*DataWidth-1:0] SensorFSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SensorFSM_Timer <= 16'd0;
end
else
begin
if (SensorFSM_TimerPreset)
begin
SensorFSM_Timer <= ParamCounterPreset_i;
end
else if (SensorFSM_TimerEnable)
begin
SensorFSM_Timer <= SensorFSM_Timer - 1'b1;
end
end
end
assign SensorFSM_TimerOvfl = (SensorFSM_Timer == 0) ? 1'b1 : 1'b0;
assign SensorValue = {MeasureFSM_Byte1_i, MeasureFSM_Byte0_i};
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Word0 <= 16'd0;
end
else
begin
if (SensorFSM_StoreNewValue)
begin
Word0 <= SensorValue;
end
end
end
wire [2*DataWidth : 0] DiffAB;
wire [2*DataWidth-1 : 0] DiffBA;
assign DiffAB = {1'b0, SensorValue} - {1'b0, Word0};
assign DiffBA = Word0 - SensorValue;
assign AbsDiffResult = DiffAB[2*DataWidth] ? DiffBA : DiffAB[2*DataWidth-1 : 0];
assign SensorFSM_DiffTooLarge = (AbsDiffResult > ParamThreshold_i) ? 1'b1 : 1'b0;
assign SensorValue_o = Word0;
endmodule // SensorFSM
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Josh Redford.
// SPDX-License-Identifier: CC0-1.0
interface my_if;
logic valid;
logic [7:0] data ;
modport slave_mp (
input valid,
input data
);
modport master_mp (
output valid,
output data
);
endinterface
module t
(
input wire in_valid,
input wire [7:0] in_data
);
my_if in_i ();
my_if out1_i ();
my_if out2_i ();
my_if out3_i ();
assign in_i.valid = in_valid;
assign in_i.data = in_data ;
my_module1 my_module1_i (
.in_i (in_i ),
.out_i (out1_i)
);
my_module2 my_module2_i (
.in_i (in_i ),
.out_i (out2_i)
);
my_module3 my_module3_i (
.in_i (in_i ),
.out_i (out3_i)
);
endmodule
module my_module1 (
my_if.slave_mp in_i,
my_if.master_mp out_i
);
// Gives ALWCOMBORDER warning
always_comb
begin
out_i.valid = in_i.valid;
out_i.data = in_i.data ;
end
endmodule
module my_module2 (
my_if.slave_mp in_i,
my_if.master_mp out_i
);
// Works if you initialise to non-interface signal first
always_comb
begin
out_i.valid = '0;
out_i.data = 'X;
out_i.valid = in_i.valid;
out_i.data = in_i.data ;
end
endmodule
module my_module3 (
my_if.slave_mp in_i,
my_if.master_mp out_i
);
// Works if you use assign signal
assign out_i.valid = in_i.valid;
assign out_i.data = in_i.data ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[114514]; int l[114514], r[114514]; bool solve(int n) { int curr = a[1]; l[1] = a[1]; for (int i = 2; i <= n; i++) { if (a[i] < a[i - 1]) curr -= a[i - 1] - a[i]; if (curr < 0) return false; l[i] = curr; } return true; } int main() { ios::sync_with_stdio(false); cin.tie(0); int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; if (solve(n)) cout << YES << endl; else cout << NO << endl; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
`define SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__fahcin (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Local signals
wire ci ;
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM, A, B, ci );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCIN_FUNCTIONAL_V |
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: memoria.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module memoria (
address,
clock,
data,
wren,
q);
input [15:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 65536,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 16,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memoria_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int n, k; vector<int> adj[(int)1e5 + 7]; int vis[(int)1e5 + 7]; int deg[(int)1e5 + 7]; int cnt[(int)1e5 + 7]; int main() { ios_base::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; scanf( %d %d , &n, &k); for (int i = 1; i <= n - 1; i++) { int u, v; scanf( %d %d , &u, &v); adj[u].push_back(v); adj[v].push_back(u); deg[v]++; deg[u]++; } int lvl = 0; queue<int> q; for (int i = 1; i <= n; i++) if (deg[i] == 1) q.push(i); while (q.size()) { set<int> kroots; int sz = q.size(); while (sz--) { int root = q.front(); q.pop(); vis[root] = 1; for (auto neighbour : adj[root]) { if (vis[neighbour]) { continue; } deg[neighbour]--; cnt[neighbour]++; kroots.insert(neighbour); } } for (auto val : kroots) { if (vis[val] || deg[val] > 1 || cnt[val] < 3) { puts( No ); return 0; } q.push(val); } if (kroots.size()) lvl++; else break; } if (lvl == k) puts( Yes ); else puts( No ); return 0; } |
`timescale 1ns / 1ps
`include "asserts.vh"
module tx_DS_SE_tb();
reg [11:0] story_tb;
reg TxClk, TxReset, Tx1, Tx0;
wire D_o, S_o;
`DEFIO(TxClk,1,0)
`DEFASSERT0(D,o)
`DEFASSERT0(S,o)
tx_DS_SE transmitter(
.TxClk(TxClk),
.TxReset(TxReset),
.Tx1(Tx1),
.Tx0(Tx0),
.D(D_o),
.S(S_o)
);
initial begin
$dumpfile("wtf.vcd");
$dumpvars;
// R -> O -> O -> R
story_tb <= 12'h000;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h001;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h002;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h003;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
// R -> O -> O -> O
story_tb <= 12'h010;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h011;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h012;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h013;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
// R -> O -> O -> Z
story_tb <= 12'h020;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h021;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h022;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h023;
{Tx1, Tx0} = 2'b01;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
// R -> Z -> O -> R
story_tb <= 12'h030;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h031;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h032;
{Tx0, Tx1} <= 2'b01;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h033;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
// R -> Z -> O -> O
story_tb <= 12'h040;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h041;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h042;
{Tx0, Tx1} <= 2'b01;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h043;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
// R -> Z -> O -> Z
story_tb <= 12'h050;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h051;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h052;
{Tx0, Tx1} = 2'b01;
TxClk0(); TxClk1();
assert_D(1); assert_S(1);
story_tb <= 12'h053;
{Tx1, Tx0} = 2'b01;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
// R -> Z -> R
story_tb <= 12'h060;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h061;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h062;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
// R -> Z -> Z
story_tb <= 12'h070;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h071;
Tx0 <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(1);
story_tb <= 12'h072;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
// R -> O -> R
story_tb <= 12'h080;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h081;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h082;
TxReset <= 1;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
// R -> O -> Z
story_tb <= 12'h090;
{TxClk,TxReset, Tx1, Tx0} = 0;
TxClk0(); TxClk1();
TxReset <= 1;
TxClk0(); TxClk1();
TxReset <= 0;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
story_tb <= 12'h091;
Tx1 <= 1;
TxClk0(); TxClk1();
assert_D(1); assert_S(0);
story_tb <= 12'h092;
{Tx1, Tx0} <= 2'b01;
TxClk0(); TxClk1();
assert_D(0); assert_S(0);
$display("@I Done.");
$stop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_1_V
`define SKY130_FD_SC_LS__CLKBUF_1_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkbuf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkbuf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_1_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; vector<long long> a(n); long long s = 0; long long l = 0; long long r = 1000000000000000; for (int i = 0; i < n; i++) { cin >> a[i]; s += a[i]; l = max(a[i], l); } long long is = r; while (l <= r) { long long mid = (l + r) / 2; if (n * mid - s > s) { is = min(is, mid); r = mid - 1; } else l = mid + 1; } cout << is << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_TB_V
`define SKY130_FD_SC_LP__ISO0N_TB_V
/**
* iso0n: ????.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__iso0n.v"
module top();
// Inputs are registered
reg A;
reg SLEEP_B;
reg VPWR;
reg KAGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAGND = 1'bX;
SLEEP_B = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 KAGND = 1'b0;
#60 SLEEP_B = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 KAGND = 1'b1;
#180 SLEEP_B = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 KAGND = 1'b0;
#300 SLEEP_B = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 SLEEP_B = 1'b1;
#460 KAGND = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 SLEEP_B = 1'bx;
#580 KAGND = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__iso0n dut (.A(A), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .KAGND(KAGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; vector<long long int> graph[100007]; long long int vis[100007]; long long int mxm; void dfs(long long int u, long long int p, long long int d) { vis[u] = 1; mxm = max(mxm, d); for (long long int v : graph[u]) { dfs(v, u, d + 1); } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ; long long int tc = 1; long long int cs = 0; while (tc--) { long long int n; cin >> n; mxm = 0; for (long long int i = 1; i <= n; i++) { long long int a; cin >> a; if (a != -1) graph[a].push_back(i); } long long int ans = 0; for (long long int i = 1; i <= n; i++) { if (!vis[i]) { dfs(i, -1, 1); ans = max(ans, mxm); mxm = 0; } } cout << ans << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_PP_SYMBOL_V
`define SKY130_FD_SC_HD__OR2_PP_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or2 (
//# {{data|Data Signals}}
input A ,
input B ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int SIZE = 640; int h, w; int matr[SIZE][SIZE]; int main() { int q; scanf( %d , &q); for (int tt = 0; tt < q; tt++) { scanf( %d%d , &h, &w); for (int i = 0; i < h; i++) for (int j = 0; j < w; j++) scanf( %d , &matr[i][j]); int cut = h / 2; int diffZero = 0; int diffSwap = 0; for (int j = 0; j < w; j++) { diffZero += abs(matr[cut - 1][j] - matr[cut][j]); diffSwap += abs(matr[0][j] - matr[h - 1][j]); } ((void)0); printf(diffZero < diffSwap ? NO n : YES n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; using namespace std; const int MaxN = 100005, NA = -1, MaxC = 0x3F3F3F3F; int a[MaxN]; int b[MaxN], c[MaxN]; bool f[MaxN]; int d, e, g, m, n; int main(void) { int i; while (scanf( %d %d , &n, &m) != EOF) { memset(b, 0, sizeof(b)); memset(c, 0, sizeof(c)); d = e = 0; for (i = 1; i <= n; i++) { scanf( %d , &a[i]); if (a[i] > 0) d++, b[abs(a[i])]++; else e++, c[abs(a[i])]++; } memset(f, 0, sizeof(f)); g = 0; for (i = 1; i <= n; i++) if (b[i] + e - c[i] == m) g++, f[i] = true; assert(g > 0); for (i = 1; i <= n; i++) if (a[i] > 0) { if (!f[abs(a[i])]) printf( Lie n ); else if (g > 1) printf( Not defined n ); else printf( Truth n ); } else { if (!f[abs(a[i])]) printf( Truth n ); else if (g > 1) printf( Not defined n ); else printf( Lie n ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int sum[1000100]; int main() { string a, b; cin >> a >> b; int cnt = 0; for (int i = 0; i < b.size(); i++) { if (b[i] == 1 ) cnt++; } sum[0] = a[0] - 0 ; for (int i = 1; i < a.size(); i++) { sum[i] = sum[i - 1] + a[i] - 0 ; } int l = 0, r = b.size() - 1; int ans = 0; while (r < a.size()) { if (cnt % 2 == 0 && (sum[r] - sum[l] + a[l] - 0 ) % 2 == 0) { ans++; } else if (cnt % 2 != 0 && (sum[r] - sum[l] + a[l] - 0 ) % 2 != 0) { ans++; } l++; r++; } cout << ans << endl; } |
`include "hi_read_tx.v"
/*
pck0 - input main 24MHz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
shallow_modulation - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_read_tx;
reg pck0;
reg [7:0] adc_d;
reg shallow_modulation;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_read_tx #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.shallow_modulation(shallow_modulation)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
//crank DUT
task crank_dut;
begin
@(posedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
adc_d = 0;
ssp_dout=0;
// shallow modulation off
shallow_modulation=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
shallow_modulation=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; int main() { int n, sum; cin >> n >> sum; if (n == 0 || (sum == 0 && n > 1)) cout << -1 << << -1 << endl; else { int ma; string t = ; int x = sum; while (x > 0 && t.length() != n) { if ((x - 9) >= 0) { t = t + 9 ; x = x - 9; } else { char c = x + 0 ; t = t + c; x = 0; } } if (t.length() == n && x != 0) cout << -1 << << -1 << endl; else { int ctr = 0; int x = (n - t.length()); if (t.length() != n) { for (int i = 1; i <= x; i++) { t = t + 0 ; } } int a[t.length()]; for (int i = 0; i < t.length(); i++) a[i] = ((int)t[i] - 48); int flag = 0; for (int i = t.length() - 1; i >= 0; i--) { if (t[t.length() - 1] == 0 && t.length() != 1) { t[t.length() - 1] = 1 ; flag = 1; } if (flag == 0) break; if (t[i] != 0 && i != t.length() - 1 && flag) { int r = (int)t[i] - 48; r = r - 1; char c = r + 0 ; t[i] = c; break; } } int y[t.length()]; for (int i = t.length() - 1; i >= 0; i--) { y[i] = (t[i] - 0 ); } for (int i = t.length() - 1; i >= 0; i--) cout << y[i]; cout << ; for (int i = 0; i < t.length(); i++) cout << a[i]; } } } |
#include <bits/stdc++.h> using namespace std; void swap(long long int arr[], long long int x, long long int y) { long long int temp = arr[x]; arr[x] = arr[y]; arr[y] = temp; } void print_arr(long long int arr[], long long int n) { cout << n ; for (long long int i = 0; i < n; i++) { cout << arr[i] << ; } cout << n ; } void input_arr(long long int arr[], long long int n) { for (long long int i = 0; i < n; i++) { cin >> arr[i]; } } bool primes[1000001]; int checkstring(string s) { int l = s.length(); string p = ; for (int i = 0; i < l; i++) { if (s[i] != - ) { p += s[i]; } } int same = 0; int dec = 0; for (int i = 1; i < p.length(); i++) { if (p[i] == p[i - 1]) { same++; } else if (p[i] <= p[i - 1]) { dec++; } } if (same == p.length() - 1) { return 2; } else if (dec == p.length() - 1) { return 1; } return 3; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int t; t = 1; while (t--) { long long int n; cin >> n; map<string, long long int> tx; map<string, long long int> cg; map<string, long long int> pz; string abc[n]; for (int i = 0; i < n; i++) { int N; string fname; cin >> N >> fname; abc[i] = fname; for (int j = 0; j < N; j++) { string s; cin >> s; int x = checkstring(s); if (x == 2) { tx[fname]++; } else if (x == 3) { cg[fname]++; } else { pz[fname]++; } } } int maxp = 0, maxt = 0, maxc = 0; vector<string> v[3]; for (int i = 0; i < n; i++) { if (tx[abc[i]] > maxt) { maxt = tx[abc[i]]; } if (pz[abc[i]] > maxp) { maxp = pz[abc[i]]; } if (cg[abc[i]] > maxc) { maxc = cg[abc[i]]; } } for (int i = 0; i < n; i++) { if (pz[abc[i]] == maxp) { v[0].push_back(abc[i]); } if (cg[abc[i]] == maxc) { v[1].push_back(abc[i]); } if (tx[abc[i]] == maxt) { v[2].push_back(abc[i]); } } cout << If you want to call a taxi, you should call: ; for (int i = 0; i < v[2].size(); i++) { if (i != v[2].size() - 1) cout << << v[2][i] << , ; else cout << << v[2][i] << . ; } cout << n ; cout << If you want to order a pizza, you should call: ; for (int i = 0; i < v[0].size(); i++) { if (i != v[0].size() - 1) cout << << v[0][i] << , ; else cout << << v[0][i] << . ; } cout << n ; cout << If you want to go to a cafe with a wonderful girl, you should call: ; for (int i = 0; i < v[1].size(); i++) { if (i != v[1].size() - 1) cout << << v[1][i] << , ; else cout << << v[1][i] << . ; } } return 0; } |
`include "top.vh"
`include "uart.vh"
module top_tb;
reg clk_i = 0;
reg rst_i = 1;
reg [4:0] rx_i_ctr = 0;
reg [19:0] rx_tmp = 20'b10100011101010010000;
reg tmp_rx_bit = 1;
wire [7:0] led_o;
wire clk_uart_tx;
wire clk_uart_rx, rs232_rx_i;
initial
begin
$dumpfile("./build/iverilog/chip8.vcd");
$dumpvars(0,top_tb);
rst_i <= 0;
# 1000 $finish;
end // initial begin
always #1 clk_i = ~clk_i;
top tb (
.ice_clk_i (clk_i),
.rstn_i(rst_i),
.rs232_rx_i(rs232_rx_i),
.led_o (led_o)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(`UART_CLK_RX_FREQ / `UART_RX_SAMPLE_RATE / 2)
)clk_uart_rx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_rx)
);
clks #(
.PLL_EN(0),
.GBUFF_EN(0),
.T(`UART_CLK_TX_FREQ / 2)
)clk_uart_tx_gen(
.clk_i (clk_i),
.clk_o (clk_uart_tx)
);
assign rs232_rx_i =tmp_rx_bit;
always @ (posedge (clk_uart_tx))
begin
tmp_rx_bit <= rst_i ? 1'b1 : rx_tmp[rx_i_ctr];
end
always @ (posedge clk_uart_tx)
begin
if (rx_i_ctr == 19 | rst_i)
begin
rx_i_ctr <= 0;
end
else
begin
rx_i_ctr <= rx_i_ctr + 1;
end
end
endmodule // top
|
module ForwardingJudgment(
input [1:0] twobeforeop1,
input [2:0] twobeforeop2,twobeforecond,
input [3:0] twobeforeop3,
input [1:0] beforeop1,
input [2:0] beforeop2,beforecond,
input [3:0] beforeop3,
input [1:0] op1,
input [2:0] op2,cond,
input [3:0] op3,
output one_A, one_B, two_A, two_B, MW_One, MW_Two);
reg oA, oB, tA, tB, mwo, mwt;
//one_A
always @ (op1 or op2 or cond or op3 or beforeop1 or beforeop2 or beforecond or beforeop3) begin
if (((beforeop1 == 2'b11
&& beforeop3 >= 4'b0000
&& beforeop3 <= 4'b1100
&& beforeop3 != 4'b0101
&& beforeop3 != 4'b0111)
|| (beforeop1 == 2'b10 && beforeop2 == 3'b001))
&& ((op1 == 2'b11 && ((op3 >= 4'b0000
&& op3 <= 4'b0110)
|| op3 == 4'b1101)))
&& op2 == beforecond)
oA <= 1'b1;
else
oA <= 1'b0;
end
//two_A
always @ (op1 or op2 or cond or op3 or twobeforeop1 or twobeforeop2 or twobeforecond or twobeforeop3) begin
if (((twobeforeop1 == 2'b11
&& twobeforeop3 >= 4'b0000
&& twobeforeop3 <= 4'b1100
&& twobeforeop3 != 4'b0101
&& twobeforeop3 != 4'b0111)
|| (twobeforeop1 == 2'b10 && twobeforeop2 == 3'b001))
&& ((op1 == 2'b11 && ((op3 >= 4'b0000
&& op3 <= 4'b0110)
|| op3 == 4'b1101)))
&& op2 == twobeforecond)
tA <= 1'b1;
else
tA <= 1'b0;
end
//one_B
always @ (op1 or op2 or cond or op3 or beforeop1 or beforeop2 or beforecond or beforeop3) begin
if (((beforeop1 == 2'b11
&& beforeop3 >= 4'b0000
&& beforeop3 <= 4'b1100
&& beforeop3 != 4'b0101
&& beforeop3 != 4'b0111)
|| (beforeop1 == 2'b10 && (beforeop2 == 3'b001 || beforeop2 == 3'b000)))
&& ((op1 == 2'b11 && ((op3 >= 4'b0000
&& op3 <= 4'b0101)
|| (op3 >= 4'b1000
&& op3 <= 4'b1011)))
|| (op1 == 2'b01)
|| (op1 == 2'b00)
|| (op1 == 2'b10 && (op2 == 3'b001
|| op2 == 3'b010
|| op2 == 3'b110)))
&& cond == beforecond)
oB <= 1'b1;
else
oB <= 1'b0;
end
//two_B
always @ (op1 or op2 or cond or op3 or twobeforeop1 or twobeforeop2 or twobeforecond or twobeforeop3) begin
if (((twobeforeop1 == 2'b11
&& twobeforeop3 >= 4'b0000
&& twobeforeop3 <= 4'b1100
&& twobeforeop3 != 4'b0101
&& twobeforeop3 != 4'b0111)
|| (twobeforeop1 == 2'b10 && (twobeforeop2 == 3'b001 || twobeforeop2 == 3'b000)))
&& ((op1 == 2'b11 && ((op3 >= 4'b0000
&& op3 <= 4'b0101)
|| (op3 >= 4'b1000
&& op3 <= 4'b1011)))
|| (op1 == 2'b01)
|| (op1 == 2'b00)
|| (op1 == 2'b10 && (op2 == 3'b001
|| op2 == 3'b010
|| op2 == 3'b110)))
&& cond == twobeforecond)
tB <= 1'b1;
else
tB <= 1'b0;
end
//MW_One
always @ (op1 or op2 or cond or op3 or beforeop1 or beforeop2 or beforecond or beforeop3) begin
if (((beforeop1 == 2'b11
&& beforeop3 >= 4'b0000
&& beforeop3 <= 4'b1100
&& beforeop3 != 4'b0101
&& beforeop3 != 4'b0111)
|| (beforeop1 == 2'b10 && (beforeop2 == 3'b001 || beforeop2 == 3'b000)))
&& (op1 == 2'b01 && op2 == beforecond)
|| (((op1 == 2'b10 && op2 == 3'b010)
|| (op1 == 2'b10 && op2 == 3'b110))
&& cond == beforecond))
mwo <= 1'b1;
else
mwo <= 1'b0;
end
//MW_Two
always @ (op1 or op2 or cond or op3 or twobeforeop1 or twobeforeop2 or twobeforecond or twobeforeop3) begin
if (((twobeforeop1 == 2'b11
&& twobeforeop3 >= 4'b0000
&& twobeforeop3 <= 4'b1100
&& twobeforeop3 != 4'b0101
&& twobeforeop3 != 4'b0111)
|| (twobeforeop1 == 2'b10 && (twobeforeop2 == 3'b001 || twobeforeop2 == 3'b000)))
&& (op1 == 2'b01 && op2 == twobeforecond)
|| (((op1 == 2'b10 && op2 == 3'b010)
|| (op1 == 2'b10 && op2 == 3'b110))
&& cond == twobeforecond))
mwt <= 1'b1;
else
mwt <= 1'b0;
end
assign one_A = oA;
assign one_B = oB;
assign two_A = tA;
assign two_B = tB;
assign MW_One = mwo;
assign MW_Two = mwt;
endmodule // ForwardingJudgement
|
//-----------------------------------------------------------------
// AltOR32
// Alternative Lightweight OpenRisc
// V2.1
// Ultra-Embedded.com
// Copyright 2011 - 2014
//
// Email:
//
// License: LGPL
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2014 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module: altor32_ram_dp - Dual port RAM (used in cache)
//-----------------------------------------------------------------
module altor32_ram_dp
#(
parameter WIDTH = 8,
parameter SIZE = 14
)
(
input aclk_i /*verilator public*/,
output [(WIDTH - 1):0] adat_o /*verilator public*/,
input [(WIDTH - 1):0] adat_i /*verilator public*/,
input [(SIZE - 1):0] aadr_i /*verilator public*/,
input awr_i /*verilator public*/,
input bclk_i /*verilator public*/,
output [(WIDTH - 1):0] bdat_o /*verilator public*/,
input [(WIDTH - 1):0] bdat_i /*verilator public*/,
input [(SIZE - 1):0] badr_i /*verilator public*/,
input bwr_i /*verilator public*/
);
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
/* verilator lint_off MULTIDRIVEN */
reg [(WIDTH - 1):0] ram [((2<< (SIZE-1)) - 1):0] /*verilator public*/;
/* verilator lint_on MULTIDRIVEN */
reg [(SIZE - 1):0] rd_addr_a_q;
reg [(SIZE - 1):0] rd_addr_b_q;
//-----------------------------------------------------------------
// Processes
//-----------------------------------------------------------------
always @ (posedge aclk_i)
begin
if (awr_i == 1'b1)
ram[aadr_i] <= adat_i;
rd_addr_a_q <= aadr_i;
end
always @ (posedge bclk_i)
begin
if (bwr_i == 1'b1)
ram[badr_i] <= bdat_i;
rd_addr_b_q <= badr_i;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
assign adat_o = ram[rd_addr_a_q];
assign bdat_o = ram[rd_addr_b_q];
//-----------------------------------------------------------------
// Init Memory
//-----------------------------------------------------------------
`ifdef ALTOR32_CLEAR_RAM
integer i;
initial
begin
for (i=0;i<((2<< (SIZE-1)) - 1);i=i+1)
begin
ram[i] = 0;
end
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000100; const int MOD = 1000000007; vector<long long> al[N], sum[N]; vector<pair<int, int> > adj[N]; pair<int, int> p[N]; int cnt(int u, long long ls) { return upper_bound(al[u].begin(), al[u].end(), ls) - al[u].begin(); } long long hp(int u, long long h, long long ls) { long long c1 = cnt(u, ls); if (c1 == 0) return 0; return h * c1 - sum[u][c1 - 1]; } int n, k, l[N], q, a, h; void dfs(int u, long long cost) { al[u].push_back(0); for (int i = 0; i < adj[u].size(); ++i) { int v = adj[u][i].first; dfs(v, cost + adj[u][i].second); for (int k = 0; k < al[v].size(); ++k) { al[u].push_back(al[v][k] + adj[u][i].second); } } sort(al[u].begin(), al[u].end()); for (int i = 0; i < al[u].size(); ++i) { sum[u].push_back((i ? sum[u].back() : 0) + (al[u][i])); } } int main() { memset(p, -1, sizeof p); scanf( %d%d , &n, &q); for (int i = 1; i <= n - 1; ++i) { scanf( %d , &l[i]); int u = (i + 1) / 2; int v = (i + 1); p[v] = make_pair(u, l[i]); adj[u].push_back(make_pair(v, l[i])); } dfs(1, 0); while (q--) { scanf( %d%d , &a, &h); long long cur = a, prev = -1, rem = h; long long add = 0; while (1) { add += hp(cur, rem, rem); if (prev != -1) { long long kk = rem - p[prev].second; add -= hp(prev, kk, kk); } prev = cur; rem = rem - p[cur].second; cur = p[cur].first; if (cur == -1 || rem < 0) break; } printf( %lld n , add); } return 0; } |
// P-K unit (control panel, heavily modified for the FPGA implementation)
`define FN_START 4'd0
`define FN_MODE 4'd1
`define FN_CLOCK 4'd2
`define FN_STOPN 4'd3
`define FN_STEP 4'd4
`define FN_FETCH 4'd5
`define FN_STORE 4'd6
`define FN_CYCLE 4'd7
`define FN_LOAD 4'd8
`define FN_BIN 4'd9
`define FN_OPRQ 4'd10
`define FN_CLEAR 4'd11
module pk(
input clk_sys,
input hlt_n,
input off,
output work,
output stop,
output start,
output mode,
output stop_n,
input p0,
output [0:15] kl,
output dcl,
output step,
output fetch,
output store,
output cycle,
output load,
output bin,
output oprq,
output reg zegar,
input p,
input mc_0,
input alarm,
input _wait,
input irq,
input q,
input run,
output wre,
output rsa,
output rsb,
output rsc,
output wic,
output wac,
output war,
output wir,
output wrs,
output wrz,
output wkb,
// to IOBUS
output [0:3] rotary_pos,
output [0:9] indicators,
// from IOBUS
input [0:3] rotary_in,
input rotary_trig,
input [0:15] keys,
input keys_trig,
input [0:3] fn,
input fn_v,
input fn_trig
);
parameter CLK_SYS_HZ;
parameter TIMER_CYCLE_MS;
// --- Input from IOBUS
reg [11:0] fnkey;
always @ (posedge clk_sys) begin
// reset all monostable switches
fnkey[`FN_STOPN] <= 1'b0;
fnkey[`FN_STEP] <= 1'b0;
fnkey[`FN_FETCH] <= 1'b0;
fnkey[`FN_STORE] <= 1'b0;
fnkey[`FN_CYCLE] <= 1'b0;
fnkey[`FN_LOAD] <= 1'b0;
fnkey[`FN_BIN] <= 1'b0;
fnkey[`FN_OPRQ] <= 1'b0;
fnkey[`FN_CLEAR] <= 1'b0;
if (keys_trig) kl <= keys;
if (rotary_trig) rotary_pos <= rotary_in;
if (fn_trig) begin
fnkey[fn] <= fn_v;
end
end
// --- To IOBUS
assign indicators = {mode, stop_n, zeg, q, p, ~mc_0, irq, run, _wait, alarm};
// --- Rotary switch position decoder
rot_dec ROT_DEC(
.in(rotary_pos),
.out({wre, rsc, rsb, rsa, wic, wac, war, wir, wrs, wrz, wkb})
);
// --- Virtual switches assignments
reg owork;
always @ (posedge clk_sys) begin
owork <= fnkey[`FN_START];
end
assign work = fnkey[`FN_START];
assign start = ~owork & work;
assign stop = owork & ~work;
assign mode = fnkey[`FN_MODE];
reg ostop_n;
always @ (posedge clk_sys, posedge hlt_n) begin
if (hlt_n) stop_n <= 1'b0;
else begin
ostop_n <= fnkey[`FN_STOPN];
if (~ostop_n & fnkey[`FN_STOPN]) stop_n <= ~stop_n;
end
end
assign dcl = fnkey[`FN_CLEAR];
assign step = fnkey[`FN_STEP];
assign fetch = fnkey[`FN_FETCH] & p0;
assign store = fnkey[`FN_STORE] & p0;
assign cycle = fnkey[`FN_CYCLE] & p0;
assign load = fnkey[`FN_LOAD] & p0;
assign bin = fnkey[`FN_BIN] & p0;
assign oprq = fnkey[`FN_OPRQ];
// --- Timer
wire zeg = fnkey[`FN_CLOCK];
timer #(
.TIMER_CYCLE_MS(TIMER_CYCLE_MS),
.CLK_SYS_HZ(CLK_SYS_HZ)
) TIMER(
.clk_sys(clk_sys),
.enable(zeg),
.zegar(zegar)
);
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFSBP_2_V
`define SKY130_FD_SC_HD__DFSBP_2_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog wrapper for dfsbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFSBP_2_V
|
module ibex_register_file (
clk_i,
rst_ni,
test_en_i,
raddr_a_i,
rdata_a_o,
raddr_b_i,
rdata_b_o,
waddr_a_i,
wdata_a_i,
we_a_i
);
parameter RV32E = 0;
parameter [31:0] DataWidth = 32;
input wire clk_i;
input wire rst_ni;
input wire test_en_i;
input wire [4:0] raddr_a_i;
output wire [(DataWidth - 1):0] rdata_a_o;
input wire [4:0] raddr_b_i;
output wire [(DataWidth - 1):0] rdata_b_o;
input wire [4:0] waddr_a_i;
input wire [(DataWidth - 1):0] wdata_a_i;
input wire we_a_i;
localparam [31:0] ADDR_WIDTH = (RV32E ? 4 : 5);
localparam [31:0] NUM_WORDS = (2 ** ADDR_WIDTH);
wire [(((NUM_WORDS - 1) >= 0) ? (((DataWidth - 1) >= 0) ? (((((NUM_WORDS - 1) >= 0) ? NUM_WORDS : (2 - NUM_WORDS)) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) + -1) : (((((NUM_WORDS - 1) >= 0) ? NUM_WORDS : (2 - NUM_WORDS)) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)) + ((DataWidth - 1) - 1))) : (((DataWidth - 1) >= 0) ? ((((0 >= (NUM_WORDS - 1)) ? (2 - NUM_WORDS) : NUM_WORDS) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) + (((NUM_WORDS - 1) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) - 1)) : ((((0 >= (NUM_WORDS - 1)) ? (2 - NUM_WORDS) : NUM_WORDS) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)) + (((DataWidth - 1) + ((NUM_WORDS - 1) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth))) - 1)))):(((NUM_WORDS - 1) >= 0) ? (((DataWidth - 1) >= 0) ? 0 : (DataWidth - 1)) : (((DataWidth - 1) >= 0) ? ((NUM_WORDS - 1) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) : ((DataWidth - 1) + ((NUM_WORDS - 1) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)))))] rf_reg;
reg [(((NUM_WORDS - 1) >= 1) ? (((DataWidth - 1) >= 0) ? (((((NUM_WORDS - 1) >= 1) ? (NUM_WORDS - 1) : (3 - NUM_WORDS)) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) + ((((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth)) - 1)) : (((((NUM_WORDS - 1) >= 1) ? (NUM_WORDS - 1) : (3 - NUM_WORDS)) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)) + (((DataWidth - 1) + ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)) - 1))) : (((DataWidth - 1) >= 0) ? ((((1 >= (NUM_WORDS - 1)) ? (3 - NUM_WORDS) : (NUM_WORDS - 1)) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) + (((NUM_WORDS - 1) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) - 1)) : ((((1 >= (NUM_WORDS - 1)) ? (3 - NUM_WORDS) : (NUM_WORDS - 1)) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)) + (((DataWidth - 1) + ((NUM_WORDS - 1) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth))) - 1)))):(((NUM_WORDS - 1) >= 1) ? (((DataWidth - 1) >= 0) ? (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth)) : ((DataWidth - 1) + ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth))) : (((DataWidth - 1) >= 0) ? ((NUM_WORDS - 1) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))) : ((DataWidth - 1) + ((NUM_WORDS - 1) * ((0 >= (DataWidth - 1)) ? (2 - DataWidth) : DataWidth)))))] rf_reg_tmp;
reg [(NUM_WORDS - 1):1] we_a_dec;
always @(*) begin : we_a_decoder
begin : sv2v_autoblock_2
reg [31:0] i;
for (i = 1; (i < NUM_WORDS); i = (i + 1))
we_a_dec[i] = ((waddr_a_i == sv2v_cast_5(i)) ? we_a_i : 1'b0);
end
end
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
rf_reg_tmp <= {(((NUM_WORDS - 1) >= 1) ? (NUM_WORDS - 1) : (3 - NUM_WORDS)) {1'sb0}};
else begin : sv2v_autoblock_3
reg signed [31:0] r;
for (r = 1; (r < NUM_WORDS); r = (r + 1))
if (we_a_dec[r])
rf_reg_tmp[((((DataWidth - 1) >= 0) ? 0 : (DataWidth - 1)) + ((((NUM_WORDS - 1) >= 1) ? r : (1 - (r - (NUM_WORDS - 1)))) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))))+:(((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))] <= wdata_a_i;
end
assign rf_reg[((((DataWidth - 1) >= 0) ? 0 : (DataWidth - 1)) + ((((NUM_WORDS - 1) >= 0) ? 0 : (NUM_WORDS - 1)) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))))+:(((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))] = 1'sb0;
assign rf_reg[(((((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth)) + ((((NUM_WORDS - 1) >= 1) ? (NUM_WORDS - 1) : (3 - NUM_WORDS)) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth)))) - 1):(((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))] = rf_reg_tmp[(((((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth)) + ((((NUM_WORDS - 1) >= 1) ? (NUM_WORDS - 1) : (3 - NUM_WORDS)) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth)))) - 1):(((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))];
assign rdata_a_o = rf_reg[((((DataWidth - 1) >= 0) ? 0 : (DataWidth - 1)) + ((((NUM_WORDS - 1) >= 0) ? raddr_a_i : (0 - (raddr_a_i - (NUM_WORDS - 1)))) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))))+:(((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))];
assign rdata_b_o = rf_reg[((((DataWidth - 1) >= 0) ? 0 : (DataWidth - 1)) + ((((NUM_WORDS - 1) >= 0) ? raddr_b_i : (0 - (raddr_b_i - (NUM_WORDS - 1)))) * (((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))))+:(((DataWidth - 1) >= 0) ? DataWidth : (2 - DataWidth))];
function automatic [4:0] sv2v_cast_5;
input reg [4:0] inp;
sv2v_cast_5 = inp;
endfunction
endmodule
|
#include <bits/stdc++.h> using namespace std; const int M = 998244353; const int N = 200005, E = 524288; int R[N * 4]; long long qpow(long long a, long long b) { long long ans = 1; while (b) { if (b & 1) ans = ans * a % M; a = a * a % M; b >>= 1; } return ans; } long long wn[N * 4], iwn[N * 4]; void init() { int i; iwn[E / 2] = wn[E / 2] = 1; long long s1 = qpow(3, (M - 1) / E); long long s2 = qpow(s1, M - 2); for (i = E / 2 + 1; i < E; ++i) { wn[i] = wn[i - 1] * s1 % M; iwn[i] = iwn[i - 1] * s2 % M; } for (i = E / 2 - 1; i; --i) { wn[i] = wn[i << 1]; iwn[i] = iwn[i << 1]; } } void NTT(long long *f, int lim, int op) { int i, j, k; for (i = 0; i < lim; ++i) { R[i] = (R[i >> 1] >> 1) | (i & 1 ? lim >> 1 : 0); if (R[i] < i) swap(f[R[i]], f[i]); } for (i = 1; i < lim; i <<= 1) for (j = 0; j < lim; j += (i << 1)) for (k = j; k < j + i; ++k) { long long a = f[k], b = f[k + i]; long long w = (op == 1 ? wn[k - j + i] : iwn[k - j + i]); f[k] = (a + b * w) % M; f[k + i] = (a - b * w) % M; } if (op == -1) { long long inv = qpow(lim, M - 2); for (i = 0; i < lim; ++i) f[i] = f[i] * inv % M; } } void mult(long long *a, int n, long long *b, int m) { int lim = 1; while (lim < n + m) lim <<= 1; for (int i = n; i < lim; ++i) a[i] = 0; for (int i = m; i < lim; ++i) b[i] = 0; NTT(a, lim, 1); NTT(b, lim, 1); for (int i = 0; i < lim; ++i) a[i] = a[i] * b[i] % M; NTT(a, lim, -1); } int p[66], k, i, n, m; char s[N], t[N]; long long a[N * 4], b[N * 4], sum, vis[66], pre[N]; int main() { init(); for (i = 0; i < 26; ++i) { scanf( %d , &p[i]); --p[i]; } mt19937 rnd(time(0)); for (i = 0; i < 26; ++i) for (int j = i; !vis[j]; j = p[j]) vis[j] = rnd() % M; scanf( %s , s); scanf( %s , t); n = strlen(s); m = strlen(t); reverse(s, s + n); for (i = 0; i < n; ++i) { a[i] = (-vis[s[i] - a ] - vis[p[s[i] - a ]]) % M; sum = (sum + vis[s[i] - a ] * vis[p[s[i] - a ]]) % M; } for (i = 0; i < m; ++i) { b[i] = vis[t[i] - a ]; pre[i] = vis[t[i] - a ] * vis[t[i] - a ] % M; } for (i = 1; i < m; ++i) pre[i] = (pre[i - 1] + pre[i]) % M; mult(a, n, b, m); for (i = n - 1; i < m; ++i) if ((a[i] + pre[i] - (i - n >= 0 ? pre[i - n] : 0) + sum) % M == 0) putchar( 1 ); else putchar( 0 ); } |
#include <bits/stdc++.h> using namespace std; const int N = 500005; int n, K, a[N]; long long checkl(int x) { long long sum = 0; for (int i = 0; i < n; ++i) { sum += max(0, x - a[i]); } return sum; } long long checkr(int x) { long long sum = 0; for (int i = 0; i < n; ++i) { sum += max(0, a[i] - x); } return sum; } int main() { scanf( %d%d , &n, &K); long long sum = 0; for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); sum += a[i]; } sort(a, a + n); int l = 0, r = 1e9; while (l < r) { int m = l + r + 1 >> 1; if (checkl(m) <= K) { l = m; } else { r = m - 1; } } int L = l; l = 0, r = 1e9; while (l < r) { int m = l + r >> 1; if (checkr(m) <= K) { r = m; } else { l = m + 1; } } int R = r; printf( %d n , max(R - L, sum % n == 0 ? 0 : 1)); } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7, mod2 = 998244353; unsigned long long base = 131; const int w = 5e5 + 5; long long n, m; struct node { int x, y, z; } s[w]; int cmp(node x, node y) { if (x.x != y.x) return x.x > y.x; else return x.y > y.y; } int main() { long long i, j, t; cin >> n; cout << n / 2 + 1 << endl; for (i = 1; i <= n; i++) scanf( %d , &s[i].x), s[i].z = i; for (i = 1; i <= n; i++) scanf( %d , &s[i].y); sort(s + 1, s + 1 + n, cmp); cout << s[1].z << ; for (i = 2; i <= n; i += 2) { if (s[i].y > s[i + 1].y) cout << s[i].z << ; else cout << s[i + 1].z << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> struct vect { private: T *memory = new T[0]; unsigned int length; unsigned int sz; public: vect() { length = 0; sz = 0; } inline void incsize(const int len) { T *temp = new T[len]; length = len; for (int i = 0; i < sz; ++i) temp[i] = memory[i]; swap(temp, memory); } inline void resize(const unsigned int v) { sz = v; if (v > length) incsize((1 << v) + 1); } inline void push_back(const T a) { const unsigned int len = length; if (length == sz) incsize((length << 1) + 1); memory[sz++] = a; } T &operator[](const unsigned int i) { return memory[i]; } unsigned int size() { return sz; } }; map<string, set<string> > v; map<set<string>, vect<string> > s1; int main() { ::ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; cin >> n; for (int i = 0; i < n; ++i) { string s; cin >> s; s = s.substr(7); string t; for (int i = 0; i < s.length(); ++i) if (s[i] == / ) t = s.substr(i), s = s.substr(0, i); v[s].insert(t); } for (auto x : v) s1[x.second].push_back(x.first); int cnt = 0; for (auto x : s1) if (x.second.size() > 1) ++cnt; cout << cnt << endl; for (auto x : s1) if (x.second.size() > 1) { for (int i = 0; i < x.second.size(); ++i) cout << http:// << x.second[i] << ; cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; bool dp[1001][1001]; int data[1001]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; if (n > m) { cout << YES << n ; return 0; } else { for (int i = 1; i <= n; i++) { cin >> data[i], data[i] %= m; if (!data[i]) { cout << YES << n ; return 0; } } dp[0][0] = true; for (int i = 1; i <= n; i++) { for (int j = 0; j <= m; j++) { dp[i][j] = dp[i - 1][j]; int var = j - data[i]; if (var < 0) var += m; dp[i][j] |= dp[i - 1][var]; } if (dp[i][m]) { cout << YES << n ; return 0; } } } cout << NO << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1000000007; const long long INF = 1000000000; template <class T> inline void read(T &x) { char c; int flag = 1; while ((c = getchar()) < 0 || c > 9 ) if (c == - ) flag *= -1; x = c - 0 ; while ((c = getchar()) >= 0 && c <= 9 ) x = x * 10 + c - 0 ; x *= flag; return; } int main() { ios::sync_with_stdio(false); cin.tie(0); int n, q; cin >> q; map<long long, long long> dp; while (q--) { long long op, u, v; cin >> op >> u >> v; if (op == 1) { long long w; cin >> w; while (u ^ v) { if (u < v) swap(u, v); dp[u] += w, u /= 2; } } else { long long ans = 0; while (u ^ v) { if (u < v) swap(u, v); ans += dp[u], u /= 2; } cout << ans << endl; } } } |
#include <bits/stdc++.h> using namespace std; inline bool EQ(double a, double b) { return fabs(a - b) < 1e-9; } const int INF = (((1 << 30) - 1) << 1) + 1; const int nINF = 1 << 31; string s; vector<int> v[2], ans; int n, t; void print(vector<int>& vec) { for (int x : vec) cout << x << ; cout << endl; } signed main() { ios::sync_with_stdio(false); cin >> t; while (t--) { v[0].clear(), v[1].clear(), ans.clear(); cin >> n >> s; bool good = true, two = false; int lo = 10; for (int i = 0; i < (n); i++) { if (two) { if (s[i] == lo && s[v[1].back()] == lo) { v[1].push_back(i); } else if (s[i] <= lo) { if (!v[0].empty() && s[i] < s[v[0].back()]) { good = false; break; } else { v[0].push_back(i); } } else { if (!v[1].empty() && s[i] < s[v[1].back()]) { good = false; break; } else { v[1].push_back(i); } } } else { if (!v[0].empty() && s[i] < s[v[0].back()]) { two = true; vector<int> temp; while (!v[0].empty() && s[i] < s[v[0].back()]) { temp.push_back(v[0].back()); v[0].pop_back(); } lo = s[temp.back()]; while (!temp.empty()) { v[1].push_back(temp.back()); temp.pop_back(); } } v[0].push_back(i); } } ans.resize(n, 1); for (int i = 0; i < (v[1].size()); i++) { ans[v[1][i]] = 2; } if (!good) cout << - << endl; else { for (int x : ans) cout << x; cout << endl; } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2B_BEHAVIORAL_V
`define SKY130_FD_SC_LP__AND2B_BEHAVIORAL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__and2b (
X ,
A_N,
B
);
// Module ports
output X ;
input A_N;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2B_BEHAVIORAL_V |
`include "ethmac_defines.v"
module ethmac
(
// WISHBONE common
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
// WISHBONE slave
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
`ifdef ETH_WISHBONE_B3
m_wb_cti_o, m_wb_bte_o,
`endif
//TX
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
//RX
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
// MIIM
mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
int_o
// Bist
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
parameter Tp = 1;
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output [31:0] wb_dat_o; // WISHBONE data output
output wb_err_o; // WISHBONE error output
// WISHBONE slave
input [11:2] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
output wb_ack_o; // WISHBONE acknowledge output
// WISHBONE master
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
input m_wb_err_i;
wire [29:0] m_wb_adr_tmp;
`ifdef ETH_WISHBONE_B3
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
`endif
// Tx
input mtx_clk_pad_i; // Transmit clock (from PHY)
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
output mtxen_pad_o; // Transmit enable (to PHY)
output mtxerr_pad_o; // Transmit error (to PHY)
// Rx
input mrx_clk_pad_i; // Receive clock (from PHY)
input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
input mrxdv_pad_i; // Receive data valid (from PHY)
input mrxerr_pad_i; // Receive data error (from PHY)
// Common Tx and Rx
input mcoll_pad_i; // Collision (from PHY)
input mcrs_pad_i; // Carrier sense (from PHY)
// MII Management interface
input md_pad_i; // MII data input (from I/O cell)
output mdc_pad_o; // MII Management data clock (to PHY)
output md_pad_o; // MII data output (to I/O cell)
output md_padoe_o; // MII data output enable (to I/O cell)
output int_o; // Interrupt output
// Bist
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SREGRBP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SREGRBP_FUNCTIONAL_V
/**
* sregrbp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr/sky130_fd_sc_lp__udp_dff_pr.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_lp__sregrbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
ASYNC
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input ASYNC;
// Local signals
wire buf_Q ;
wire reset ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (reset , ASYNC );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$PR `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, reset);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SREGRBP_FUNCTIONAL_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM 32-bit Byte-Write ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Author(s): ////
//// - Michael Unneback, ////
//// - Tadej Markovic, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dpram_32x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// New
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_32_bw
(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, ce, we, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 10;
parameter dw = 32;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input ce; // Chip enable input
input [3:0] we; // Write enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
`ifdef OR1200_GENERIC
reg [7:0] mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [7:0] mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [7:0] mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [7:0] mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`else
reg [7:0] mem0 [(1<<aw)-1:0];
reg [7:0] mem1 [(1<<aw)-1:0];
reg [7:0] mem2 [(1<<aw)-1:0];
reg [7:0] mem3 [(1<<aw)-1:0];
`endif
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = {mem0[addr_reg], mem1[addr_reg], mem2[addr_reg], mem3[addr_reg]};
//
// RAM read address register
//
always @(posedge clk)
if (ce)
addr_reg <= addr;
//
// RAM write - big endian selection
//
always @(posedge clk)
if (ce) begin
if (we[3])
mem0[addr] <= di[31:24];
if (we[2])
mem1[addr] <= di[23:16];
if (we[1])
mem2[addr] <= di[15:08];
if (we[0])
mem3[addr] <= di[07:00];
end
endmodule // or1200_spram
|
#include <bits/stdc++.h> using namespace std; int main() { long long int k, n, first = -1, sum = 0; cin >> n >> k; long long int a[n]; long long int ans = 0; for (long long int i = 0; i < n; ++i) cin >> a[i]; string s; cin >> s; int flag = 0; for (long long int i = 0; i < n; ++i) { if (s[i] == s[i + 1]) { if (first == -1) first = i; flag = 1; } else if (flag) { sort(a + first, a + i + 1); long long int mini = min(k, i - first + 1); for (long long int j = 0; j < mini; ++j) { sum += a[i - j]; } flag = 0; first = -1; } else { sum += a[i]; } } cout << sum << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int n; cin >> n; long long int h[n]; long long int d[n]; long long int sum = 0; for (long long int i = 0; i < n; i++) { cin >> h[i]; d[i] = h[i] - i; sum += d[i]; } long long int q = sum / n; long long int r = sum % n; for (int i = 0; i < n; i++) { long long int out = q + i; if (i < r) out++; cout << out << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 998244353; const int maxn = 1e3 + 10; int n, m, mp[maxn][maxn], cnt, dx[] = {0, 1, 0, -1}, dy[] = {-1, 0, 1, 0}; bool vis[maxn][maxn]; vector<int> ans; void dfs(int x, int y) { if (vis[x][y] || x <= 0 || x > n || y <= 0 || y > m) return; vis[x][y] = 1, ++cnt; for (int i = 0; i < 4; ++i) if (!(mp[x][y] & (1 << i))) dfs(x + dx[i], y + dy[i]); } void solve() { scanf( %d%d , &n, &m); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) scanf( %d , &mp[i][j]); for (int i = 1; i <= n; ++i) for (int j = 1; j <= m; ++j) if (!vis[i][j]) cnt = 0, dfs(i, j), ans.push_back(cnt); sort(ans.begin(), ans.end()); for (int i = ans.size() - 1; ~i; --i) printf( %d , ans[i]); } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long arr1[1000001]; template <typename T> T myMax(T x, T y) { return (x > y) ? x : y; } template <typename T> T myMin(T x, T y) { return (x < y) ? x : y; } template <typename T> T sum(T x, T y) { return (x + y); } template <typename T> T Mean(T x, T y) { return (x + ((y - x) / 2)); } void seive() { for (long long i = 0; i <= 1000000; i++) { arr1[i] = 1; } for (long long i = 2; i * i <= 1000000; i++) { if (arr1[i] == 1) { arr1[i] = 1; for (long long j = i * i; j <= 1000000; j = j + i) { arr1[j] = 0; } } } } long long find_occurances(string s) { string s1 = ; long long c = 0; for (long long i = 0; i < 3; i++) { s1 = s1 + s[i]; } if (s1 == abc ) { c++; } long long n = s.size(); long long l = 0; long long r = 2; while (r < n - 1) { s1.erase(s1.begin()); l++; r++; s1 += s[r]; if (s1 == abc ) { c++; } } return c; } bool check_power_of_2(long long x) { if ((x & (x - 1)) == 0) { return true; } return false; } bool cmp(pair<long long, pair<long long, long long>> x, pair<long long, pair<long long, long long>> y) { if (x.first == y.first) { return x.second.second < y.second.second; } return x.first < y.first; } bool cmp1(pair<long long, long long> p, pair<long long, long long> q) { return p.first < q.second; } bool check(vector<long long>& v) { if (v[0] == 1) { bool flag1 = true; for (long long i = 1; i < v.size(); i++) { if (v[i] != v[i - 1]) { flag1 = false; break; } } return flag1; } else { return false; } } bool check_prime(long long x) { if (x == 2) { return true; } if (x == 3) { return true; } if ((x % 2) == 0) { return false; } if ((x % 3) == 0) { return false; } for (long long i = 5; i * i <= x; i = i + 6) { if ((x % i) == 0) { return false; } if ((x % (i + 2)) == 0) { return false; } } return true; } bool check_array(vector<long long>& v) { for (long long i = 1; i < v.size(); i++) { if (v[i] == v[i - 1]) return false; } return true; } bool is_vowel(char x) { if ((x == a ) || (x == e ) || (x == o ) || (x == i ) || (x == u )) { return true; } return false; } signed main() { long long t; cin >> t; while (t--) { long long n; cin >> n; long long arr[n]; long long sum = 0; for (long long i = 0; i < n; i++) { cin >> arr[i]; sum += arr[i]; } if ((sum % n) == 0) { cout << 0 << n ; } else { cout << 1 << n ; } } return 0; } |
//--------------------------------------------------------------------------------
// Project : SWITCH
// File : reset_sync.v
// Version : 0.2
// Author : Shreejith S
//
// Description: Synchronous Reset Generation - XILINX
//
//-----------------------------------------------------------------------------
//
// (c) Copyright 2006-2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//------------------------------------------------------------------------------
// Description: Both flip-flops have the same asynchronous reset signal.
// Together the flops create a minimum of a 1 clock period
// duration pulse which is used for synchronous reset.
//
// The flops are placed, using RLOCs, into the same slice.
`timescale 1ps/1ps
module reset_sync #(
parameter INITIALISE = 2'b11
)
(
input reset_in,
input clk,
input enable,
output reset_out
);
wire reset_stage1;
wire reset_stage2;
(* ASYNC_REG = "TRUE", RLOC = "X0Y0", INIT = "1" *)
FDPE #(
.INIT (INITIALISE[0])
) reset_sync1 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (1'b0),
.Q (reset_stage1)
);
(* ASYNC_REG = "TRUE", RLOC = "X0Y0", INIT = "1" *)
FDPE #(
.INIT (INITIALISE[1])
) reset_sync2 (
.C (clk),
.CE (enable),
.PRE(reset_in),
.D (reset_stage1),
.Q (reset_stage2)
);
assign reset_out = reset_stage2;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int rlen = 1 << 18 | 1; inline char gc() { static char buf[rlen], *ib, *ob; (ib == ob) && (ob = (ib = buf) + fread(buf, 1, rlen, stdin)); return ib == ob ? -1 : *ib++; } inline int read() { int ans = 0; char ch = gc(); while (!isdigit(ch)) ch = gc(); while (isdigit(ch)) ans = ((ans << 2) + ans << 1) + (ch ^ 48), ch = gc(); return ans; } const int N = 1e5 + 5; vector<pair<int, int> > e[N]; int n, m, dis[N]; bool vis[N]; namespace xxj { int a[31]; inline void insert(int x) { if (!x) return; for (register int i = 30; ~i; --i) if ((x >> i) & 1) if (!a[i]) { a[i] = x; break; } else x ^= a[i]; } inline int query(int x) { for (register int i = 30; ~i; --i) x = min(x, x ^ a[i]); return x; } } // namespace xxj void dfs(int p, int fa) { vis[p] = 1; for (register int i = 0, v; i < e[p].size(); ++i) { if ((v = e[p][i].first) == fa) continue; if (!vis[v]) dis[v] = dis[p] ^ e[p][i].second, dfs(v, p); else xxj::insert(dis[v] ^ dis[p] ^ e[p][i].second); } } int main() { n = read(), m = read(); for (register int i = 1, u, v, w; i <= m; ++i) u = read(), v = read(), w = read(), e[u].push_back(pair<int, int>(v, w)), e[v].push_back(pair<int, int>(u, w)); dfs(1, 0), cout << xxj::query(dis[n]); return 0; } |
#include <bits/stdc++.h> using namespace std; double PI = 3.141592653589793; vector<complex<double> > duzywek; vector<complex<double> > duzyret[50][2]; void szykuj() { for (int j = 0; j < 22; j++) { for (int i = 1; i <= (1 << (21 - j)); i++) { duzyret[j][0].push_back(0); if (j) duzyret[j][1].push_back(0); } } } int potenga(int v) { for (int i = 1; 1; i <<= 1) { if (i >= v) { return i; } } } void dft(int nn, int kt, int coile, complex<double> omega, int gdzie, int poz) { if (nn == 1) { duzyret[poz][gdzie][0] = duzywek[kt]; return; } dft(nn >> 1, kt, coile << 1, omega * omega, 0, poz + 1); dft(nn >> 1, kt + coile, coile << 1, omega * omega, 1, poz + 1); complex<double> jeden(1.0, 0.0); int w = 0; int an = (nn >> 1) - 1; for (int i = 0; i < nn; i++) { duzyret[poz][gdzie][i] = duzyret[poz + 1][0][i & an] + jeden * duzyret[poz + 1][1][i & an]; jeden *= omega; } } vector<int> fft(vector<int> jed, vector<int> dwa) { int n1 = potenga(jed.size() + dwa.size()); while (jed.size() < n1) { jed.push_back(0); } while (dwa.size() < n1) { dwa.push_back(0); } complex<double> omega(cos(2.0 * PI / n1), sin(2.0 * PI / n1)); vector<complex<double> > pam; duzywek.clear(); for (int i = 0; i < n1; i++) { duzywek.push_back(complex<double>(jed[i], 0.0)); } dft(n1, 0, 1, omega, 0, 0); pam = duzyret[0][0]; for (int i = 0; i < n1; i++) { duzywek[i] = complex<double>(dwa[i], 0.0); } dft(n1, 0, 1, omega, 0, 0); for (int i = 0; i < n1; i++) { duzywek[i] = pam[i] * duzyret[0][0][i]; } omega = (complex<double>(1.0, 0.0)) / omega; dft(n1, 0, 1, omega, 0, 0); vector<int> retret; int dowrzucenia; for (int i = 0; i < n1; i++) { duzyret[0][0][i] /= n1; dowrzucenia = round(duzyret[0][0][i].real()); retret.push_back(dowrzucenia); } return retret; } int n, m; vector<int> dopo; vector<int> otrz; vector<int> wyn; int x; int main() { szykuj(); scanf( %d%d , &n, &m); while (dopo.size() <= m) { dopo.push_back(0); } dopo[0] = 1; for (int i = 1; i <= n; i++) { scanf( %d , &x); dopo[x] = 1; } otrz = fft(dopo, dopo); while (otrz.size() > m + 1) otrz.pop_back(); for (int i = 1; i < otrz.size(); i++) { if (otrz[i] && !dopo[i]) { printf( NO ); return 0; } if (otrz[i] == 2) { wyn.push_back(i); } } printf( YES n ); printf( %d n , (int)wyn.size()); for (int i = 0; i < wyn.size(); i++) { printf( %d , wyn[i]); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:09:25 11/06/2014
// Design Name:
// Module Name: addititon
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module addititon(
store000_0,
store001_0,
store010_0,
store100_0,
store101_0,
store110_0,
store000_1,
store001_1,
store010_1,
store100_1,
store101_1,
store110_1,
clock,
store000_0_out,
store001_0_out,
store010_0_out,
store100_0_out,
store101_0_out,
store110_0_out,
cout1,
cout2,
cout3,
cout4,
cout5,
cout6
);
// Input wire for the first number of DBNS Representation
input [3:0] store000_0;
input [3:0] store001_0;
input [3:0] store010_0;
input [3:0] store100_0;
input [3:0] store101_0;
input [3:0] store110_0;
// Input wire for the second number of the DBNS Representation
input [3:0] store000_1;
input [3:0] store001_1;
input [3:0] store010_1;
input [3:0] store100_1;
input [3:0] store101_1;
input [3:0] store110_1;
input clock;
// Output wires for the final representation in DBNS
output [3:0] store000_0_out;
output [3:0] store001_0_out;
output [3:0] store010_0_out;
output [3:0] store100_0_out;
output [3:0] store101_0_out;
output [3:0] store110_0_out;
// Output wires for the carry out from each stage
output [1:0] cout1;
output [1:0] cout2;
output [1:0] cout3;
output [1:0] cout4;
output [1:0] cout5;
output [1:0] cout6;
case1 case000(
.cin(2'b00),
.clock(clock),
.cout_w(cout1),
.input1(store000_0),
.input2(store000_1),
.out(store000_0_out));
case1 case001(
.cin(2'b00),
.clock(clock),
.cout_w(cout2),
.input1(store001_0),
.input2(store001_1),
.out(store001_0_out));
case1 case010(
.cin(2'b00),
.clock(clock),
.cout_w(cout3),
.input1(store010_0),
.input2(store010_1),
.out(store010_0_out));
case1 case100(
.cin(cout1),//_temp),
.clock(clock),
.cout_w(cout4),
.input1(store100_0),
.input2(store100_1),
.out(store100_0_out));
case1 case101(
.cin(cout2),//_temp),
.clock(clock),
.cout_w(cout5),
.input1(store101_0),
.input2(store101_1),
.out(store101_0_out));
case1 case110(
.cin(cout3),//_temp),
.clock(clock),
.cout_w(cout6),
.input1(store110_0),
.input2(store110_1),
.out(store110_0_out));
endmodule
|
// Implements a sinc^3 filter on a single-bit input. Useful for sigma-delta
// modulator outputs. Transfer function is:
//
// (1-z^-OSR)^3
// H(z) = ----------------
// (1-z^-1)^3
//
// This is very efficient for Xilinx FPGAs. Also near optimal for any device
// where long single-bit delay lines can be cheaply implemented. For any other
// device, it is almost certainly better to implement the 3 accumulators first,
// decimate, then implement the differentiator stages.
module sinc3Filter
#(
parameter OSR = 16 // Output width is 3*ceil(log2(OSR))+1
)
(
input clk,
input en, ///< Enable (use to clock at slower rate)
input in,
output reg signed [3*$clog2(OSR):0] out
);
// Parameters
///////////////////////////////////////////////////////////////////////////
localparam ACC_UP = $clog2(OSR)-1;
// Signal Declarations
///////////////////////////////////////////////////////////////////////////
wire signed [3:0] diff;
reg [(3*OSR)-1:0] shift;
reg signed [(3+1*ACC_UP):0] acc1 = 'd0;
reg signed [(3+2*ACC_UP):0] acc2 = 'd0;
integer i;
// Main Code
///////////////////////////////////////////////////////////////////////////
// Initialize delay line such that average of all bits in line is 0. Not doing
// this will result in a non-zero DC offset.
initial begin
shift[0] = 1'b1;
for (i=1; i<(3*OSR); i=i+1) shift[i] = ~shift[i-1];
out = 'd0;
end
// diff = (1-z^-OSR) ^ 3
// accumulators implement 1/(1-z^-1)^3
assign diff = in - 3*shift[OSR-1] + 3*shift[2*OSR-1] - shift[3*OSR-1];
always @(posedge clk) begin
if (en) begin
shift <= {shift[3*OSR-2:0], in};
acc1 <= acc1 + diff;
acc2 <= acc2 + acc1;
out <= out + acc2;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1000000 + 5; vector<int> g[N], revg[N], cur; bool used[N], isans[N]; set<int> all; int n, m; int main() { scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) { int u, v; scanf( %d %d , &u, &v); u--, v--; g[u].push_back(v); revg[v].push_back(u); } for (int i = 0; i < n; i++) { all.insert(i); } while (!all.empty()) { int k = *(all.begin()); for (auto x : g[k]) { if (!used[x]) { used[x] = true; all.erase(x); } } used[k] = true; all.erase(k); cur.push_back(k); } for (int i = cur.size() - 1; i >= 0; i--) { int node = cur[i]; isans[node] = true; for (auto x : revg[node]) { if (isans[x]) { isans[node] = false; } } } vector<int> ans; for (int i = 0; i < n; i++) { if (isans[i]) ans.push_back(i + 1); } printf( %d n , ans.size()); for (int i = 0; i < ans.size(); i++) { printf( %d , ans[i]); } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<long long, long long> > V1, V2; int n, s; int main() { while (~scanf( %d%d , &n, &s)) { V1.clear(); V2.clear(); long long sum1 = 0; long long sum2 = 0; long long ans = 0; for (int i = 0; i < n; i++) { long long a, b, c; scanf( %lld%lld%lld , &c, &a, &b); if (a > b) { sum1 += c; ans += c * a; V1.push_back(make_pair(a - b, c)); } else { sum2 += c; ans += c * b; V2.push_back(make_pair(b - a, c)); } } sum1 %= s; sum2 %= s; if (sum1 + sum2 > s) { cout << ans << endl; continue; } else { sort(V1.begin(), V1.end()); sort(V2.begin(), V2.end()); long long tmp1 = 0; long long tmp2 = 0; int len = V1.size(); for (int i = 0; i < len; i++) { tmp1 += min(sum1, V1[i].second) * V1[i].first; sum1 -= min(sum1, V1[i].second); } len = V2.size(); for (int i = 0; i < len; i++) { tmp2 += min(sum2, V2[i].second) * V2[i].first; sum2 -= min(sum2, V2[i].second); } cout << ans - min(tmp1, tmp2) << endl; } } } |
#include <bits/stdc++.h> using namespace std; int n, k, tab[70], p; int main() { scanf( %d %d , &n, &k); for (int i = 0; i < n; i++) scanf( %d , &tab[i]); sort(tab, tab + n); if (k > n) { printf( -1 n ); return 0; } printf( %d %d n , tab[n - k], tab[n - k]); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> using minheap = priority_queue<T, vector<T>, greater<T>>; template <typename T> using maxheap = priority_queue<T>; template <typename T> using dpair = pair<T, T>; template <class T1, class T2> istream &operator>>(istream &is, pair<T1, T2> &p) { return is >> p.first >> p.second; } template <class T1, class T2> void operator+=(vector<T1> &v, const T2 &obj) { v.push_back(obj); } template <class T1> void operator+=(vector<T1> &v, const T1 &obj) { v.push_back(obj); } long long get_millis() { using namespace std::chrono; return duration_cast<milliseconds>(system_clock::now().time_since_epoch()) .count(); } const int INF = 0x3f3f3f3f; const long long mod = 1e9 + 7; class xrange { public: xrange(int end) : _start(0), _end(end), _step(1) {} xrange(int start, int end) : _start(start), _end(end), _step(1) {} xrange(int start, int end, int step) : _start(start), _end(end), _step(step) {} class iterator { public: iterator(int v, xrange &par) : val(v), parent(par){}; int operator*() const { return val; } int operator++() { return (val += parent._step); } bool operator==(const xrange::iterator &iter) const { if (&parent != &iter.parent) return false; if (val == iter.val) return true; if (parent._step > 0) return val >= parent._end && iter.val >= parent._end; else return val <= parent._end && iter.val <= parent._end; } bool operator!=(const xrange::iterator &iter) const { return !(this->operator==(iter)); } private: int val; xrange &parent; }; xrange::iterator begin() { return {_start, *this}; } xrange::iterator end() { return {_end, *this}; } protected: int _start, _end, _step; private: }; struct irange : public xrange { irange(int i) : xrange(1, i + 1) {} irange(int i, int j) : xrange(i, j + 1) {} }; const int MAXN = 1e4 + 5; namespace std { template <> struct hash<dpair<int>> { size_t operator()(dpair<int> p) const { return p.first * 123456789 + p.second; } }; } // namespace std unordered_map<dpair<int>, int> ump; int N, M, K; struct dir { bool lit; int r, c; int dist; dir(int _l, int _r, int _c, int _d) { lit = _l; r = _r; c = _c; dist = _d; } bool operator>(const dir &d) const { return dist > d.dist; } }; minheap<dir> pq; set<int> availR[MAXN], availC[MAXN]; int best[MAXN]; int main() { cin.tie(0); cin.sync_with_stdio(0); cin >> N >> M >> K; for (int a = 0; a < K; a++) { int r, c; cin >> r >> c; availR[r].insert(c); availC[c].insert(r); ump[{r, c}] = a; } pq.push({false, 1, 1, 0}); pq.push({true, 1, 1, 1}); availR[1].erase(1); availC[1].erase(1); memset(best, 0x3f, sizeof(best)); best[ump[{1, 1}]] = 0; while (!pq.empty()) { dir top = pq.top(); pq.pop(); if (top.lit) { for (int r = max(1, top.r - 2); r <= top.r + 2; r++) { for (int i : availR[r]) { int id = ump[{r, i}]; best[id] = min(best[id], top.dist); pq.push(dir{false, r, i, top.dist}); pq.push(dir{true, r, i, top.dist + 1}); } availR[r].clear(); } for (int c = max(1, top.c - 2); c <= top.c + 2; c++) { for (int i : availC[c]) { int id = ump[{i, c}]; best[id] = min(best[id], top.dist); pq.push(dir{false, i, c, top.dist}); pq.push(dir{true, i, c, top.dist + 1}); } availC[c].clear(); } } else { int dr = 1, dc = 0; if (ump.count({top.r + dr, top.c + dc}) && best[ump[{top.r + dr, top.c + dc}]] > top.dist) { best[ump[{top.r + dr, top.c + dc}]] = top.dist; pq.push(dir{false, top.r + dr, top.c + dc, top.dist}); pq.push(dir{true, top.r + dr, top.c + dc, top.dist + 1}); availR[top.r + dr].erase(top.c + dc); availC[top.c + dc].erase(top.r + dr); } dr = -1; dc = 0; if (ump.count({top.r + dr, top.c + dc}) && best[ump[{top.r + dr, top.c + dc}]] > top.dist) { best[ump[{top.r + dr, top.c + dc}]] = top.dist; pq.push(dir{false, top.r + dr, top.c + dc, top.dist}); pq.push(dir{true, top.r + dr, top.c + dc, top.dist + 1}); availR[top.r + dr].erase(top.c + dc); availC[top.c + dc].erase(top.r + dr); } dr = 0; dc = 1; if (ump.count({top.r + dr, top.c + dc}) && best[ump[{top.r + dr, top.c + dc}]] > top.dist) { best[ump[{top.r + dr, top.c + dc}]] = top.dist; pq.push(dir{false, top.r + dr, top.c + dc, top.dist}); pq.push(dir{true, top.r + dr, top.c + dc, top.dist + 1}); availR[top.r + dr].erase(top.c + dc); availC[top.c + dc].erase(top.r + dr); } dr = 0; dc = -1; if (ump.count({top.r + dr, top.c + dc}) && best[ump[{top.r + dr, top.c + dc}]] > top.dist) { best[ump[{top.r + dr, top.c + dc}]] = top.dist; pq.push(dir{false, top.r + dr, top.c + dc, top.dist}); pq.push(dir{true, top.r + dr, top.c + dc, top.dist + 1}); availR[top.r + dr].erase(top.c + dc); availC[top.c + dc].erase(top.r + dr); } } } int ans = INF; for (auto au : ump) { if (au.first == dpair<int>{N, M}) { ans = min(ans, best[au.second]); } if (abs(au.first.first - N) <= 1 || abs(au.first.second - M) <= 1) { ans = min(ans, best[au.second] + 1); } } if (ans > 10000000) { cout << -1; } else { cout << ans; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTP_TB_V
`define SKY130_FD_SC_HS__DLRTP_TB_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlrtp.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 RESET_B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 RESET_B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 RESET_B = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 RESET_B = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hs__dlrtp dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTP_TB_V
|
#include <bits/stdc++.h> using namespace std; int cases(1), t; template <typename T> void binary(T n) { stack<int> st; while (n > 0) { st.push(n % 2); n /= 2; } while (!st.empty()) { cout << st.top(); st.pop(); } cout << n ; } vector<long long> factorize(long long x) { vector<long long> res; if (x % 2 == 0) { res.push_back(2); } while (x % 2 == 0) { x /= 2; } for (long long i = 3; i * i <= x; i += 2) { if (x % i == 0) { res.push_back(i); while (x % i == 0) { x /= i; } } } if (x > 2) res.push_back(x); return res; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; for (cin >> t; cases <= t; ++cases) { long long first, second; cin >> first >> second; long long ans = 0; if (first % second) { cout << first << n ; continue; } vector<long long> fac = factorize(second); for (long long i = 0; i < fac.size(); i++) { long long res = first; while (res % second == 0) { res /= fac[i]; } ans = max(res, ans); } cout << ans << n ; } return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 11.1i (L.12)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Static Single Port Synchronous RAM 64-Deep by 1-Wide
// /___/ /\ Filename : RAMS64E.v
// \ \ / \ Timestamp : Thu Mar 25 16:44:03 PST 2004
// \___\/\___\
//
// Revision:
// 07/02/10 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 03/21/12 - CR649330 - Add RAM_ADDRESS_MASK to allow floating WADR6/7
// 04/16/13 - PR683925 - add invertible pin support.
// End Revision
`timescale 1 ps/1 ps
`celldefine
module RAMS64E #(
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT = 64'h0000000000000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [1:0] RAM_ADDRESS_MASK = 2'b00,
parameter [1:0] RAM_ADDRESS_SPACE = 2'b00
)(
output O,
input ADR0,
input ADR1,
input ADR2,
input ADR3,
input ADR4,
input ADR5,
input CLK,
input I,
input WADR6,
input WADR7,
input WE
);
reg [63:0] mem;
wire [5:0] ADR_dly, ADR_in;
wire CLK_dly, I_dly;
wire CLK_in, I_in;
wire [1:0] WADR_dly, WADR_in;
wire WE_dly, WE_in;
localparam MODULE_NAME = "RAMS64E";
initial begin
mem = INIT;
`ifndef XIL_TIMING
$display("ERROR: SIMPRIM primitive %s instance %m is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the SIMPRIM library.", MODULE_NAME);
$finish;
`endif
end
always @(posedge CLK_in)
if (WE_in == 1'b1 &&
(RAM_ADDRESS_MASK[1] || WADR_in[1] == RAM_ADDRESS_SPACE[1]) &&
(RAM_ADDRESS_MASK[0] || WADR_in[0] == RAM_ADDRESS_SPACE[0]) )
mem[ADR_in] <= #100 I_in;
assign O = mem[ADR_in];
`ifdef XIL_TIMING
reg notifier;
always @(notifier)
mem[ADR_in] <= 1'bx;
`endif
`ifndef XIL_TIMING
assign I_dly = I;
assign CLK_dly = CLK;
assign ADR_dly = {ADR5, ADR4, ADR3, ADR2, ADR1, ADR0};
assign WADR_dly = {WADR7, WADR6};
assign WE_dly = WE;
`endif
assign CLK_in = IS_CLK_INVERTED ^ CLK_dly;
assign WE_in = WE_dly;
assign I_in = I_dly;
assign ADR_in = ADR_dly;
assign WADR_in = WADR_dly;
specify
(ADR0 => O) = (0:0:0, 0:0:0);
(ADR1 => O) = (0:0:0, 0:0:0);
(ADR2 => O) = (0:0:0, 0:0:0);
(ADR3 => O) = (0:0:0, 0:0:0);
(ADR4 => O) = (0:0:0, 0:0:0);
(ADR5 => O) = (0:0:0, 0:0:0);
(CLK => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge CLK &&& WE, 0:0:0, notifier);
$period (posedge CLK &&& WE, 0:0:0, notifier);
$setuphold (negedge CLK, negedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, negedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, negedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, negedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, negedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, negedge ADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (negedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, negedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (negedge CLK, negedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (negedge CLK, posedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (negedge CLK, posedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (negedge CLK, posedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (negedge CLK, posedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (negedge CLK, posedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (negedge CLK, posedge ADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (negedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (negedge CLK, posedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (negedge CLK, posedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (posedge CLK, negedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, negedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, negedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, negedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, negedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, negedge ADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (posedge CLK, negedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, negedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (posedge CLK, negedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$setuphold (posedge CLK, posedge ADR0 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[0]);
$setuphold (posedge CLK, posedge ADR1 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[1]);
$setuphold (posedge CLK, posedge ADR2 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[2]);
$setuphold (posedge CLK, posedge ADR3 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[3]);
$setuphold (posedge CLK, posedge ADR4 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[4]);
$setuphold (posedge CLK, posedge ADR5 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,ADR_dly[5]);
$setuphold (posedge CLK, posedge I &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,I_dly);
$setuphold (posedge CLK, posedge WADR6 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[0]);
$setuphold (posedge CLK, posedge WADR7 &&& WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WADR_dly[1]);
$setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier,,,CLK_dly,WE_dly);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; const int modulo = 1e9 + 7; template <class __Ty> bool mini(__Ty& a, __Ty b) { return a > b ? ((a = b) | 1) : (0); } template <class __Ty> bool maxi(__Ty& a, __Ty b) { return a < b ? ((a = b) | 1) : (0); } template <class __Ty> __Ty add(__Ty a, __Ty b) { return (a + b) % (__Ty(modulo)); } template <class __Ty> __Ty sub(__Ty a, __Ty b) { __Ty m(modulo); return ((a - b) % m + m) % m; } int a[int(1e6) + 3] = {0}; int main() { ios::sync_with_stdio(0); cin.tie(0); int n, m; cin >> n >> m; if ((n <= m + 1) && (m <= 2 * (n + 1))) { m -= n - 1; for (int i = 1; i < n; ++i) a[i] = 1; for (int i = 0; i <= n; ++i) while (m && a[i] < 2) { m--; a[i]++; } for (int i = 0; i <= n; ++i) { if (i > 0) cout << 0; while (a[i]--) cout << 1; } } else cout << -1; return 0; } |
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