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#include <bits/stdc++.h> const int N = 100010; const int M = 30; std::map<std::string, int> Hash; int fa[N << 1], n, m, q; char s[M]; int find(int u) { return fa[u] == u ? u : fa[u] = find(fa[u]); } void unite(int u, int v) { int _u = find(u), _v = find(v); fa[_u] = _v; find(u); } int main() { for (int i = 0; i < N << 1; ++i) { fa[i] = i; } scanf( %d%d%d , &n, &m, &q); for (int i = 0; i < n; ++i) { scanf( %s , s); std::string str = s; Hash[str] = i; } for (int i = 0, type; i < m; ++i) { scanf( %d%s , &type, s); std::string str = s; int u = Hash[str]; scanf( %s , s); str = s; int v = Hash[str]; find(u), find(v), find(v + n), find(u + n); if (type == 1) { if (fa[u] == fa[v + n] || fa[v] == fa[u + n]) { printf( NO n ); continue; } printf( YES n ); unite(u, v); unite(u + n, v + n); continue; } if (type == 2) { if (fa[u] == fa[v] || fa[u + n] == fa[v + n]) { printf( NO n ); continue; } printf( YES n ); unite(u, v + n); unite(u + n, v); } } for (int i = 0; i < q; ++i) { scanf( %s , s); std::string str = s; int u = Hash[str]; scanf( %s , s); str = s; int v = Hash[str]; find(u), find(v), find(u + n), find(v + n); if (fa[u] == fa[v] || fa[u + n] == fa[v + n]) { printf( 1 n ); } else if (fa[u] == fa[v + n] || fa[u + n] == fa[v]) { printf( 2 n ); } else { printf( 3 n ); } } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DFXTP_FUNCTIONAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p/sky130_fd_sc_ms__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ms__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXTP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int n, ar[200001], f[10001], g[21][21], f1[10001]; int main() { ios::sync_with_stdio(0), cin.tie(NULL), cout.tie(NULL); cin >> n; for (int i = 0; i < n * n; i++) { cin >> ar[i]; f[ar[i]]++; f1[ar[i]]++; } if (n & 1) { int wh = 0, ck = 0, od = 0; for (int i = 1; i <= 1000; i++) { while (f1[i] >= 4) { wh += 4; f1[i] -= 4; } if (f1[i] >= 2) { ck += 2; f1[i] -= 2; } if (f1[i] & 1) od++; } if ((n * n - 1) == wh + ck && od == 1) { for (int i = 1; i <= n / 2; i++) { for (int j = 1; j <= n / 2; j++) { bool b = 1; for (int x = 1; x <= 1000; x++) { if (f[x] >= 4) { f[x] -= 4; g[i][j] = g[n - i + 1][j] = x; g[i][n - j + 1] = g[n - i + 1][n - j + 1] = x; b = 0; break; } } if (b) { cout << NO n ; return 0; } } } int a = 1; for (int j = 1; j <= 1000; j++) { if (f[j] & 1) { g[n / 2 + 1][n / 2 + 1] = j; f[j]--; } while (f[j] && a <= n / 2) { g[a][n / 2 + 1] = g[n - a + 1][n / 2 + 1] = j; f[j] -= 2; a++; } } a = 1; for (int j = 1; j <= 1000; j++) { while (f[j] && a <= n / 2) { g[n / 2 + 1][a] = g[n / 2 + 1][n - a + 1] = j; f[j] -= 2; a++; } } cout << YES n ; for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { cout << g[i][j] << ; } cout << n ; } } else { cout << NO ; return 0; } } else { int wh = 0; for (int i = 1; i <= 1000; i++) { wh += f[i] / 4; } if (wh == n * n / 4) { cout << YES n ; for (int i = 1; i <= n / 2; i++) { for (int j = 1; j <= n / 2; j++) { for (int x = 1; x <= 1000; x++) { if (f[x]) { f[x] -= 4; g[i][j] = g[n - i + 1][j] = x; g[i][n - j + 1] = g[n - i + 1][n - j + 1] = x; break; } } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { cout << g[i][j] << ; } cout << n ; } } else { cout << NO n ; } } return 0; } |
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_geninterp18(
input sys_clk,
input load,
input next_point,
input signed [17:0] init,
input positive,
input [16:0] q,
input [16:0] r,
input [16:0] divisor,
output signed [17:0] o
);
reg positive_r;
reg [16:0] q_r;
reg [16:0] r_r;
reg [16:0] divisor_r;
always @(posedge sys_clk) begin
if(load) begin
positive_r <= positive;
q_r <= q;
r_r <= r;
divisor_r <= divisor;
end
end
reg [17:0] err;
reg correct;
reg signed [17:0] o_r;
assign o = o_r;
always @(posedge sys_clk) begin
if(load) begin
err = 18'd0;
o_r = init;
end else if(next_point) begin
err = err + r_r;
correct = (err[16:0] > {1'b0, divisor_r[16:1]}) & ~err[17];
if(positive_r) begin
o_r = o_r + {1'b0, q_r};
if(correct)
o_r = o_r + 18'd1;
end else begin
o_r = o_r - {1'b0, q_r};
if(correct)
o_r = o_r - 18'd1;
end
if(correct)
err = err - {1'b0, divisor_r};
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXBP_2_V
`define SKY130_FD_SC_MS__DFXBP_2_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfxbp_2 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfxbp_2 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXBP_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O32A_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__O32A_PP_BLACKBOX_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O32A_PP_BLACKBOX_V
|
/*
* Copyright (c) 2001 Stephan Boettcher <>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: mangle.v,v 1.1 2001/06/19 13:52:13 ka6s Exp $
// $Log: mangle.v,v $
// Revision 1.1 2001/06/19 13:52:13 ka6s
// Added 4 tests from Stephan Boettcher
//
//
// Test of \escaped identifiers
module mangle;
reg \abc ;
reg \`~!-_=+\|[]{};:'"",./<>? ;
reg cde ;
initial
begin
abc <= 1;
\`~!-_=+\|[]{};:'"",./<>? <= 1;
\cde <= 1;
$display("PASSED");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, q; int a[1000007]; int st[1000007]; int en[1000007]; vector<pair<int, int> > v_st[1000007]; long long ans[1000007]; class Tree { public: pair<long long, int> tr[6 * 1000007]; void init(int where, int IL, int IR) { tr[where] = {0, 0}; if (IL == IR) { return; } int mid = (IL + IR) / 2; init(2 * where, IL, mid); init(2 * where + 1, mid + 1, IR); } void update(int where, int IL, int IR, int CURL, int CURR, pair<long long, int> add) { if (CURR < CURL) { return; } if (IR < CURL || CURR < IL) { return; } if (CURL <= IL && IR <= CURR) { tr[where].first += add.first, tr[where].second += add.second; return; } int mid = (IL + IR) / 2; update(2 * where, IL, mid, CURL, CURR, add); update(2 * where + 1, mid + 1, IR, CURL, CURR, add); } pair<long long, int> query(int where, int IL, int IR, int pos) { if (IR < pos || pos < IL) { return {0, 0}; } if (IL == IR) { return tr[where]; } int mid = (IL + IR) / 2; pair<long long, int> ret; if (pos <= mid) { ret = query(2 * where, IL, mid, pos); } else { ret = query(2 * where + 1, mid + 1, IR, pos); } ret = {ret.first + tr[where].first, ret.second + tr[where].second}; return ret; } }; Tree w; void input() { scanf( %d%d , &n, &q); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); } for (int i = 1; i <= q; ++i) { scanf( %d , &st[i]); } for (int i = 1; i <= q; ++i) { scanf( %d , &en[i]); v_st[en[i]].push_back({st[i], i}); } } void calc() { stack<int> st; a[0] = n + 1; st.push(0); w.init(1, 1, n); for (int i = 1; i <= n; ++i) { while (a[st.top()] < a[i]) { st.pop(); } w.update(1, 1, n, 1, st.top(), {i - st.top() - 1, 0}); w.update(1, 1, n, st.top() + 1, i, {i, 1}); st.push(i); int sz = v_st[i].size(); for (int j = 0; j < sz; ++j) { pair<long long, int> ret = w.query(1, 1, n, v_st[i][j].first); ans[v_st[i][j].second] += ret.first - 1LL * ret.second * v_st[i][j].first; } } } void solve() { calc(); for (int i = 1; i <= (n >> 1); ++i) { swap(a[i], a[n - i + 1]); } for (int i = 1; i <= n; ++i) { v_st[i].clear(); } for (int i = 1; i <= q; ++i) { st[i] = (n - st[i] + 1); en[i] = (n - en[i] + 1); swap(st[i], en[i]); v_st[en[i]].push_back({st[i], i}); } calc(); for (int i = 1; i <= q; ++i) { printf( %I64d , ans[i] + (en[i] - st[i] + 1)); } printf( n ); } int main() { ios_base ::sync_with_stdio(false); cin.tie(NULL); input(); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const double INF = 1000000000; struct point { long long x, y; point() {} point(long long x, long long y) : x(x), y(y) {} point operator-(point P) { return point(x - P.x, y - P.y); } }; double abs(point P) { return sqrt(P.x * P.x + P.y * P.y); } double dist(point P, point Q) { return abs(Q - P); } long long dot(point P, point Q) { return P.x * Q.x + P.y * Q.y; } long long cross(point P, point Q) { return P.x * Q.y - P.y * Q.x; } int main() { cout << fixed << setprecision(20); int N, K; cin >> N >> K; K--; vector<point> P(N); for (int i = 0; i < N; i++) { cin >> P[i].x >> P[i].y; } if (N == 3) { int a = (K + 1) % 3; int b = (K + 2) % 3; cout << min(dist(P[K], P[a]), dist(P[K], P[b])) + dist(P[a], P[b]) << endl; } else { mt19937 mt(chrono::steady_clock::now().time_since_epoch().count()); int p; int x; point D; while (true) { int a = mt() % N; int b = mt() % N; int c = mt() % N; if (a != b && b != c && c != a) { if (cross(P[b] - P[a], P[c] - P[a]) == 0) { x = a; D = P[b] - P[a]; for (int i = 0; i < N; i++) { if (cross(P[i] - P[a], D) != 0) { p = i; } } break; } } } vector<pair<long long, int>> L; for (int i = 0; i < N; i++) { if (i != p) { L.push_back(make_pair(dot(P[i] - P[x], D), i)); } } sort(L.begin(), L.end()); vector<point> Q(N - 1); for (int i = 0; i < N - 1; i++) { Q[i] = P[L[i].second]; } if (p == K) { cout << min(dist(P[K], Q[0]), dist(P[K], Q[N - 2])) + dist(Q[0], Q[N - 2]) << endl; } else { int s; for (int i = 0; i < N - 1; i++) { if (L[i].second == K) { s = i; } } double ans = INF; ans = min(ans, dist(Q[s], Q[0]) + dist(Q[0], Q[N - 2]) + dist(Q[N - 2], P[p])); ans = min(ans, dist(Q[s], Q[N - 2]) + dist(Q[N - 2], Q[0]) + dist(Q[0], P[p])); for (int i = s; i < N - 2; i++) { double d11 = dist(Q[s], Q[i]) + dist(Q[i], Q[0]) + dist(Q[0], P[p]); double d12 = dist(Q[s], Q[0]) + dist(Q[0], Q[i]) + dist(Q[i], P[p]); double d1 = min(d11, d12); double d2 = min(dist(P[p], Q[i + 1]), dist(P[p], Q[N - 2])) + dist(Q[i + 1], Q[N - 2]); ans = min(ans, d1 + d2); } for (int i = 1; i <= s; i++) { double d11 = dist(Q[s], Q[i]) + dist(Q[i], Q[N - 2]) + dist(Q[N - 2], P[p]); double d12 = dist(Q[s], Q[N - 2]) + dist(Q[N - 2], Q[i]) + dist(Q[i], P[p]); double d1 = min(d11, d12); double d2 = min(dist(P[p], Q[i - 1]), dist(P[p], Q[0])) + dist(Q[i - 1], Q[0]); ans = min(ans, d1 + d2); } cout << ans << endl; } } } |
#include <bits/stdc++.h> using namespace std; int main() { long long int t = 1; while (t--) { long long int n; cin >> n; cout << 0 << << 0 << << n; } } |
#include <bits/stdc++.h> using namespace std; int main() { double a, b, c, d; cin >> a >> b >> c >> d; double mx; mx = (a / b) * (1 / (1 - (1 - a / b) * (1 - c / d))); std::cout << std::setprecision(9) << mx << n ; } |
#include <bits/stdc++.h> using namespace std; const int M = 3000; int n, m; pair<pair<int, int>, int> v[M]; map<pair<pair<int, int>, int>, vector<pair<pair<int, int>, int> > > Q; int gcd(int a, int b) { return !b ? a : gcd(b, a % b); } pair<pair<int, int>, int> get(int x1, int y1, int x2, int y2) { int x = x2 - x1, y = y2 - y1; if (x == 0) y = 1; else if (y == 0) x = 1; else { int d = gcd(x, y); x /= d, y /= d; } if (x < 0) x = -x, y = -y; return make_pair(make_pair(x, y), y1 * x - x1 * y); } int sign(double x) { if (fabs(x) < 1E-6) return 0; return (x > 0) ? 1 : -1; } double dist(int x1, int y1, int x2, int y2) { return sqrt((x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2)); } bool cmp(pair<pair<int, int>, int> a, pair<pair<int, int>, int> b) { if (a.first != b.first) return a.first < b.first; return a.second > b.second; } int main() { Q.clear(); scanf( %d%d , &n, &m); for (int i = 0; i < (n); i++) { int x1, y1, x2, y2; scanf( %d%d%d%d , &x1, &y1, &x2, &y2); x1 *= 2, y1 *= 2, x2 *= 2, y2 *= 2; if (make_pair(x1, y1) > make_pair(x2, y2)) { swap(x1, x2); swap(y1, y2); } pair<pair<int, int>, int> tmp = get(x1, y1, x2, y2); Q[tmp].push_back(make_pair(make_pair(x1, y1), 1)); Q[tmp].push_back(make_pair(make_pair(x2, y2), -1)); } for (int i = 0; i < (m); i++) { scanf( %d%d%d , &v[i].first.first, &v[i].first.second, &v[i].second); for (int j = 0; j < (i); j++) { if (v[i].second != v[j].second) continue; int x1 = v[i].first.first, y1 = v[i].first.second, r = v[i].second; int x2 = v[j].first.first, y2 = v[j].first.second; if (sign(2 * r - dist(x1, y1, x2, y2)) >= 0) continue; int x0 = x1 + x2, y0 = y1 + y2; int x = x2 * 2 - x0, y = y2 * 2 - y0; pair<pair<int, int>, int> tmp = get(x0, y0, x0 - y, y0 + x); if (Q.find(tmp) == Q.end()) continue; Q[tmp].push_back(make_pair(make_pair(x0, y0), 0)); } } int ret = 0; for (__typeof(Q.begin()) it = Q.begin(); it != Q.end(); it++) { sort(it->second.begin(), it->second.end(), cmp); int now = 0; for (__typeof(it->second.begin()) t = it->second.begin(); t != it->second.end(); t++) { if (t->second == 0) ret += now; now += t->second; } } printf( %d n , ret); return 0; } |
#include <bits/stdc++.h> using namespace std; const int max_n = 100000; int n, k; char s[max_n + 5]; void solve(void); int main(void) { int t; scanf( %d , &t); while (t--) solve(); return 0; } void solve(void) { scanf( %d%d , &n, &k); scanf( %s , s); int i, j, t, ans = 0; int lcnt = 0; for (i = 0; i < n; i++) { if (s[i] == W ) { if (i > 0 && s[i - 1] == W ) ans += 2; else ans++; } else lcnt++; } if (lcnt == n) { if (!k) printf( 0 n ); else printf( %d n , 2 * k - 1); return; } i = 0; vector<int> gap; while (i < n) { if (s[i] == L ) { i++; continue; } j = i; while (j < n && s[j] == W ) j++; t = j; while (t < n && s[t] == L ) t++; if (t >= n) break; gap.push_back(t - j); i = t; } sort(gap.begin(), gap.end()); for (i = 0; k && i < (int)gap.size(); i++) { if (gap[i] <= k) { k -= gap[i]; lcnt -= gap[i]; ans += 2 * gap[i] + 1; } else { lcnt -= k; ans += 2 * k; k = 0; } } if (k) { ans += min(k, lcnt) * 2; } printf( %d n , ans); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFRBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DFRBP_BEHAVIORAL_PP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ls__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_ls__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, RESET, notifier, VPWR, VGND);
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFRBP_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_M_V
`define SKY130_FD_SC_LP__NOR3B_M_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3b_m (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor3b_m (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_M_V
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, m, k, ans[5]; char s[N]; void solve(int l, int r) { while (l != r) { int mid = l + r >> 1; printf( 1 %d %d n , mid, mid + 1); fflush(stdout); scanf( %s , s); if (!strcmp(s, NIE )) l = mid + 1; else r = mid; } ans[++m] = l; } int main() { scanf( %d%d , &n, &k); solve(1, n); if (ans[1] > 1) solve(1, ans[1] - 1); if (ans[1] < n) solve(ans[1] + 1, n); if (m == 2) { printf( 2 %d %d n , ans[1], ans[2]); exit(0); } printf( 1 %d %d n , ans[2], ans[3]); fflush(stdout); scanf( %s , s); if (!strcmp(s, NIE )) ans[2] = ans[3]; printf( 2 %d %d n , ans[1], ans[2]); return 0; } |
/* SRAM implementation
*
* Implements an SRAM with each entry holding eight bits and eight entries
* total.
*
* Created By David Tran
* Version 0.1.0.0
* Last Modified:05-01-2014
*/
module SRAM(read, // Specifies if we want to read from the FIFO
write, // Specifies if we want to write form the FIFO
address, // Specifies the address for read/write
dataIn, // The input packet
dataOut, // The output packet
clk // Clock input
);
parameter bits = 8;
parameter depth = 3;
parameter ad_length = 1<<depth;
input read;
input write;
input [depth-1:0] address; //2^depth = address
input [bits-1:0] dataIn;
output [bits-1:0] dataOut;
reg [bits-1:0] dataOut;
input clk;
reg [bits-1:0] memArray [ad_length-1:0];
always @(posedge clk) begin
if(write)
memArray[address] <= dataIn;
if(read)
dataOut <= memArray[address];
if (read & write) begin
$display("ERROR: simultaneous read and write to memory");
dataOut <= {bits{1'bx}};
$stop;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:43:59 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_us_0/system_auto_us_0_stub.v
// Design : system_auto_us_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4" *)
module system_auto_us_0(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arregion, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rdata,
s_axi_rresp, s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awlen,
m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion,
m_axi_awqos, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast,
m_axi_wvalid, m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp,
m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[31:0],s_axi_arlen[7:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[0:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arregion[3:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[127:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready" */;
input s_axi_aclk;
input s_axi_aresetn;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output m_axi_arvalid;
input m_axi_arready;
input [127:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
// file: clk_divider_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module clk_divider_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_divider_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
// Freq Check
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND2_PP_SYMBOL_V
`define SKY130_FD_SC_HS__TAPVGND2_PP_SYMBOL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__tapvgnd2 (
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND2_PP_SYMBOL_V
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const int N = 1e5 + 10; int n, m, a[N]; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.setf(ios::fixed), cout.precision(9); cin >> n >> m; for (int i = 1; i <= n; ++i) cin >> a[i]; a[n + 1] = m; vector<int> pfs(n + 2, 0), pos(n + 2, 0); for (int i = 1; i <= n + 1; ++i) { if (i & 1) { if (i - 2 >= 0) pfs[i] = pfs[i - 2]; pfs[i] += a[i] - a[i - 1]; } else { pfs[i] = pfs[i - 1]; } } if (n & 1) { for (int i = n; i >= 0; --i) { if ((n - i) & 1) { pos[i] = pos[i + 1]; } else { if (i + 2 <= n) pos[i] = pos[i + 2]; pos[i] += a[i + 1] - a[i]; } } } else { for (int i = n; i >= 0; --i) { if ((n - i) & 1) { if (i + 2 <= n) pos[i] = pos[i + 2]; pos[i] += a[i + 1] - a[i]; } else { pos[i] = pos[i + 1]; } } } int ans = pfs[n + 1]; for (int i = 0; i <= n + 1; ++i) { if (a[i] - 1 > 0 and a[i] - 1 != a[i - 1]) { int now_ans; if (i & 1) { now_ans = pfs[i] - 1 + pos[i]; } else { now_ans = pfs[i - 1] + 1 + pos[i]; } ans = max(ans, now_ans); } if (a[i] + 1 < m and a[i] + 1 != a[i + 1]) { int now_ans; if (i & 1) { now_ans = pfs[i] + a[i + 1] - a[i] - 1 + pos[i + 1]; } else { now_ans = pfs[i] + 1 + pos[i + 1]; } ans = max(ans, now_ans); } } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; int main() { string s; long long t, j = 0; cin >> t; cin >> s; for (long long i = 0; i < s.size(); i++) { if (s[i] == F ) if (s[i + 1] == S ) j--; if (s[i] == S ) if (s[i + 1] == F ) j++; } if (j <= 0) cout << NO ; else if (j > 0) cout << YES ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int h, m; while (scanf( %d:%d , &h, &m) == 2) { int a; scanf( %d , &a); int t = (h * 60 + m + a) % (24 * 60); printf( %02d:%02d n , t / 60, t % 60); } } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1000000 + 50; const int maxm = 1300000 + 100; const int maxt = 3000000 + 100; const int maxk = 10 + 3; const int M = 2010; const long long unit = 1LL; const int INF = 0x3f3f3f3f; const long long Inf = 0x3f3f3f3f3f3f3f3fLL; const double eps = 1e-8; const double inf = 1e15; const double pi = acos(-1.0); const long long mod = 998244353LL, gg = 3LL, inv2 = 499122177LL; inline long long read() { long long x = 0; bool t = false; char ch = getchar(); while ((ch < 0 || ch > 9 ) && ch != - ) ch = getchar(); if (ch == - ) t = true, ch = getchar(); while (ch <= 9 && ch >= 0 ) x = x * 10 + ch - 48, ch = getchar(); return t ? -x : x; } struct Peo { int pos, id; bool operator<(const Peo &a) const { if (pos == a.pos) return id < a.id; return pos < a.pos; } } peo[maxn]; struct City { int pos, id; bool operator<(const City &a) const { if (pos == a.pos) return id < a.id; return pos < a.pos; } } city[maxn]; int m, n, a[maxn], b[maxn]; long long judge(int x) { long long ret = 0; if (x < 0) { for (int i = 0; i < -x; i++) ret += peo[i].pos + m - city[n + x + i].pos; for (int i = -x; i < n; i++) ret += abs(peo[i].pos - city[i + x].pos); } else { for (int i = 0; i < x; i++) ret += city[i].pos + m - peo[n - x + i].pos; for (int i = x; i < n; i++) ret += abs(city[i].pos - peo[i - x].pos); } return ret; } int main() { m = read(), n = read(); for (int i = 0; i < n; ++i) city[i].pos = read(), city[i].id = i; sort(city, city + n); for (int i = 0; i < n; ++i) peo[i].pos = read(), peo[i].id = i; sort(peo, peo + n); int l = -n, r = n; while (l < r) { int m = (l + r) >> 1; if (judge(m) < judge(m + 1)) r = m; else l = m + 1; } long long ans = Inf, anst = 0; for (int turn = l - 100; turn <= l + 100; ++turn) { int st = (turn % n + n) % n; long long res = 0; for (int i = 0; i < n; ++i) { res += min(abs(peo[i].pos - city[st].pos), m - abs(peo[i].pos - city[st].pos)); ++st; if (st >= n) st -= n; } if (res < ans) { ans = res; anst = turn; } } printf( %lld n , ans); int st = (anst % n + n) % n; for (int i = 0; i < n; ++i) { b[city[st].id] = peo[i].id; ++st; if (st >= n) st -= n; } for (int i = 0; i < n; ++i) printf( %d , b[i] + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; long long ans = 0; for (int i = (0); i < (n); ++i) { long long t, T, x, cost; cin >> t >> T >> x >> cost; if (t >= T) { ans += cost + m * x; continue; } long long aux1 = cost; if (m > (T - t)) aux1 += m * x; long long aux2 = (long long)ceil((double)(m - (T - t)) / (T - t)) + 1; aux2 *= cost; ans += min(aux1, aux2); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 1e5 + 10; const long long M = 1e7 + 1000; const long long mod = 1e9 + 7; const long long INF = 1e18; const long long inf = -1e18; bool isprime(long long x) { if (x == 1) return false; long long y = sqrt(x); for (int i = 2; i <= y; i++) { if (x % i == 0) { return false; } } return true; } long long bin_pow(long long a, long long b) { if (b == 0) return 1; if (b == 1) return a; if (a == 0) return 0; if (a == 1) return a; if (b % 2 == 0) { long long pw = bin_pow(a, b / 2); return pw * pw; } else { return bin_pow(a, b - 1) * a; } } const long double pi = acos(-1); long long n, m, x; long long us[5 * N]; vector<long long> ans; int main() { cin >> n >> x; us[0] = 1; ans.push_back(0); long long m = (1 << n); for (int i = 1; i < m; i++) { if (us[i ^ x] != 1) { us[i] = 1; ans.push_back(i); } } cout << ans.size() - 1 << n ; for (int i = 1; i < ans.size(); i++) cout << (ans[i] ^ ans[i - 1]) << ; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int N = 1e6 + 10; const int INF = 0x3f3f3f3f; const long long LINF = 0x3f3f3f3f3f3f3f3f; inline int read() { static char buf[1000000], *p1 = buf, *p2 = buf; register int x = false; register char ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; register bool sgn = false; while (ch != - && (ch < 0 || ch > 9 )) ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; if (ch == - ) sgn = true, ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; while (ch >= 0 && ch <= 9 ) x = (x << 1) + (x << 3) + (ch ^ 48), ch = p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 1000000, stdin), p1 == p2) ? EOF : *p1++; ; return sgn ? -x : x; } long long fpow(long long a, int b, int mod) { long long res = 1; for (; b > 0; b >>= 1) { if (b & 1) res = res * a % mod; a = a * a % mod; } return res; } long long d[N]; long long cnt[26]; long long fac[N]; char s[N]; int len; long long num[N]; long long calc(int x) { long long tot = 0; for (int i = 0; i < x; i++) tot += cnt[i]; return tot; } long long dfs(int d) { if (d == len + 1) return 0; long long tot = calc(s[d] - a ) * fac[len - d] % mod; if (cnt[s[d] - a ]) { cnt[s[d] - a ]--; long long u = dfs(d + 1); cnt[s[d] - a ]++; tot = (tot + cnt[s[d] - a ] * u % mod) % mod; } return tot; } int main() { fac[0] = 1; for (long long i = 1; i < N; i++) { fac[i] = (fac[i - 1] * i) % mod; } scanf( %s , s + 1); len = strlen(s + 1); for (int i = 1; i <= len; i++) cnt[s[i] - a ]++; long long ans = dfs(1); scanf( %s , s + 1); ans = (dfs(1) - ans + mod) % mod; for (int i = 0; i < 26; i++) { if (cnt[i] >= 1) ans = ans * fpow(fac[cnt[i]], mod - 2, mod) % mod; } cout << ans - 1 << endl; return 0; } |
module var17_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> ve[100005]; long long vis[100005] = {0}, z = 0, i; void solve() { vector<long long> v; vector<pair<long long, long long> > vp; map<long long, long long> mp, mpp; map<long long, long long>::iterator itr; long long n = 0, m = 0, i = 0, j = 0, k = 0, c = 0, l = 0, r = 0, p = 0, q = 0, x = 0, y = 0, z = 0, flag = 0, sum = 0; long long a[300005] = {0}, b[1005] = {0}, ans[25][25]; long long s, t; cin >> n; for (i = 0; i < pow(n, 2); i++) cin >> a[i]; for (i = 0; i < pow(n, 2); i++) b[a[i]]++; for (i = 0; i < 1001; i++) if (b[i] > 0) vp.push_back(make_pair(b[i], i)); sort(vp.begin(), vp.end()); z = vp.size() - 1; for (j = 0; j < n / 2; j++) { for (i = 0; i < n / 2; i++) { if (vp[z].first >= 4) { k = vp[z].second; vp[z].first -= 4; ans[i][j] = k; ans[n - i - 1][j] = k; ans[i][n - j - 1] = k; ans[n - i - 1][n - j - 1] = k; } else { z--; i--; } if (z == -1) { cout << No << endl; return; } } } if (n % 2 == 1) { s = (n - 1) / 2; sort(vp.begin(), vp.end()); z = vp.size() - 1; for (i = 0; i < n / 2; i++) { if (vp[z].first >= 2) { k = vp[z].second; vp[z].first -= 2; ans[s][i] = k; ans[s][n - i - 1] = k; } else { z--; i--; } if (z == -1) { cout << No << endl; return; } } sort(vp.begin(), vp.end()); z = vp.size() - 1; for (i = 0; i < n / 2; i++) { if (vp[z].first >= 2) { k = vp[z].second; vp[z].first -= 2; ans[i][s] = k; ans[n - i - 1][s] = k; } else { z--; i--; } if (z == -1) { cout << No << endl; return; } } sort(vp.begin(), vp.end()); z = vp.size() - 1; ans[s][s] = vp[z].second; } for (i = 0; i < n; i++) for (j = 0; j < n; j++) if (ans[i][j] == 0) { cout << No << endl; return; } cout << Yes << endl; for (i = 0; i < n; i++) { for (j = 0; j < n; j++) cout << ans[i][j] << ; cout << endl; } } bool imp = false; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t = 1; if (imp) cin >> t; while (t--) solve(); return 0; } |
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29755 $
// $Date: 2012-10-22 13:58:12 +0000 (Mon, 22 Oct 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
`ifdef BSV_ASYNC_RESET
`define BSV_ARESET_EDGE_META or `BSV_RESET_EDGE RST
`else
`define BSV_ARESET_EDGE_META
`endif
`ifdef BSV_RESET_FIFO_HEAD
`define BSV_ARESET_EDGE_HEAD `BSV_ARESET_EDGE_META
`else
`define BSV_ARESET_EDGE_HEAD
`endif
// Depth 2 FIFO
module FIFO2(CLK,
RST,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR);
parameter width = 1;
parameter guarded = 1;
input CLK ;
input RST ;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
output [width - 1 : 0] D_OUT;
reg full_reg;
reg empty_reg;
reg [width - 1 : 0] data0_reg;
reg [width - 1 : 0] data1_reg;
assign FULL_N = full_reg ;
assign EMPTY_N = empty_reg ;
assign D_OUT = data0_reg ;
// Optimize the loading logic since state encoding is not power of 2!
wire d0di = (ENQ && ! empty_reg ) || ( ENQ && DEQ && full_reg ) ;
wire d0d1 = DEQ && ! full_reg ;
wire d0h = ((! DEQ) && (! ENQ )) || (!DEQ && empty_reg ) || ( ! ENQ &&full_reg) ;
wire d1di = ENQ & empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
data0_reg = {((width + 1)/2) {2'b10}} ;
data1_reg = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0;
full_reg = 1'b1;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK `BSV_ARESET_EDGE_META)
begin
if (RST == `BSV_RESET_VALUE)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (RST == `BSV_RESET_VALUE)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (CLR)
else if ( ENQ && ! DEQ ) // just enq
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg ;
end
else if ( DEQ && ! ENQ )
begin
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg;
end // if ( DEQ && ! ENQ )
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
always@(posedge CLK `BSV_ARESET_EDGE_HEAD)
begin
`ifdef BSV_RESET_FIFO_HEAD
if (RST == `BSV_RESET_VALUE)
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
data1_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
`endif
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY
{width{d0di}} & D_IN | {width{d0d1}} & data1_reg | {width{d0h}} & data0_reg ;
data1_reg <= `BSV_ASSIGNMENT_DELAY
d1di ? D_IN : data1_reg ;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if (RST == ! `BSV_RESET_VALUE)
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1;
$display( "Warning: FIFO2: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! full_reg && ENQ && (!DEQ || guarded) )
begin
enqerror = 1;
$display( "Warning: FIFO2: %m -- Enqueuing to a full fifo" ) ;
end
end
end // always@ (posedge CLK)
// synopsys translate_on
endmodule
|
#include <bits/stdc++.h> using namespace std; int const N = 1e5 + 2; int n, m; void solve() { string n, m; cin >> n >> m; sort((n).begin(), (n).end()); if (n[0] == 0 && n.size() > 1) swap(n[0], n[1]); if (n == m) cout << OK << endl; else cout << WRONG_ANSWER << endl; } int main() { ios::sync_with_stdio(0); cin.tie(0); solve(); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__xnor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xnor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
xnor xnor0 (xnor0_out_Y , A, B );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, xnor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR2_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long power(long long a, long long b) { long long ret = 1; while (b) { if (b & 1) ret *= a; a *= a; if (ret >= MOD) ret %= MOD; if (a >= MOD) a %= MOD; b >>= 1; } return ret; } long long invmod(long long x) { return power(x, MOD - 2); } vector<long long> vp[100005]; int vis[100005] = {0}; int dfs(int n) { if (vp[n].size() < 2) return 10001; int a[4005] = {0}; vector<long long> vp1; for (int i = 0; i < vp[n].size(); i++) { vp1.push_back(vp[n][i]); a[vp[n][i]] = 1; } int min = 10001; for (int i = 0; i < vp1.size(); i++) { for (int j = 0; j < vp[vp1[i]].size(); j++) { if (a[vp[vp1[i]][j]] == 1) { if (min > vp[vp[vp1[i]][j]].size() + vp[n].size() + vp[vp1[i]].size() - 6) { min = vp[vp[vp1[i]][j]].size() + vp[n].size() + vp[vp1[i]].size() - 6; break; } } } } return min; } int main() { int n, m; cin >> m >> n; int x, y; for (int i = 0; i < n; i++) { cin >> x >> y; vp[x].push_back(y); vp[y].push_back(x); } int min1 = 10000; for (int i = 1; i <= m; i++) { min1 = min(dfs(i), min1); } if (min1 == 10000) { cout << -1 << endl; return 0; } cout << min1 << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INVLP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__INVLP_FUNCTIONAL_PP_V
/**
* invlp: Low Power Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__invlp (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INVLP_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_FUNCTIONAL_V
`define SKY130_FD_SC_LS__INV_FUNCTIONAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_FUNCTIONAL_V |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: CoarseDelay.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 132 02/25/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module CoarseDelay (
address,
clock,
q);
input [2:0] address;
input clock;
output [63:0] q;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "CDly"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "CoarseDelay.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "3"
// Retrieval info: PRIVATE: WidthData NUMERIC "64"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "CoarseDelay.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=CDly"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "64"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 3 0 INPUT NODEFVAL address[2..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: CONNECT: @address_a 0 0 3 0 address 0 0 3 0
// Retrieval info: CONNECT: q 0 0 64 0 @q_a 0 0 64 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL CoarseDelay_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHR_6 (
CLK,
RST_N,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3,
read_4,
write_4,
EN_write_4,
read_5,
write_5,
EN_write_5
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
input RST_N;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
output [DATA_SZ-1:0] read_3;
input [DATA_SZ-1:0] write_3;
input EN_write_3;
output [DATA_SZ-1:0] read_4;
input [DATA_SZ-1:0] write_4;
input EN_write_4;
output [DATA_SZ-1:0] read_5;
input [DATA_SZ-1:0] write_5;
input EN_write_5;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
wire [DATA_SZ-1:0] wire_4;
wire [DATA_SZ-1:0] wire_5;
wire [DATA_SZ-1:0] wire_6;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign wire_4 = EN_write_3 ? write_3 : wire_3;
assign wire_5 = EN_write_4 ? write_4 : wire_4;
assign wire_6 = EN_write_5 ? write_5 : wire_5;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
assign read_3 = wire_3;
assign read_4 = wire_4;
assign read_5 = wire_5;
always @(posedge CLK) begin
if (RST_N == 0) begin
r <= RESET_VAL;
end else begin
r <= wire_6;
end
end
endmodule
|
(* We want a dependently typed recursive function. The output type is itself
described by a recursive function. *)
Fixpoint bool_nat_type (n:nat) : Set :=
match n with 0 => nat | 1 => bool | S (S n) => bool_nat_type n end.
(* The difficult point is to describe the computation at each
recursive step, knowing that sometimes this computation deals with
boolean values, while at other times it deals with integer
values. The trick is to discover that computations can actually
always be described by the same function as for the
pre-predecessor.
A dependently typed pattern-matching construct is need. *)
Require Import Bool.
Fixpoint bool_nat_fun_aux (n:nat) : bool_nat_type n -> bool_nat_type n :=
match n return bool_nat_type n -> bool_nat_type n with
0 => S | 1 => negb | S (S n) => bool_nat_fun_aux n
end.
(* The function is then easy to describe. We can use "Eval compute"
to check that its value is always as required. *)
Fixpoint bool_nat_fun (n:nat) : bool_nat_type n :=
match n return bool_nat_type n with
0 => 0
| 1 => true
| S (S n) => bool_nat_fun_aux n (bool_nat_fun n)
end.
Eval compute in (bool_nat_fun 6).
Eval compute in (bool_nat_fun 7).
Eval compute in (bool_nat_fun 9).
Eval compute in (bool_nat_fun 7 : bool).
Eval compute in (bool_nat_fun 6 : nat).
(* Defining a function of this form was fun, but will it ever be
useful? *)
|
#include <bits/stdc++.h> int n; int main() { while (EOF != scanf( %d , &n)) { if (n == 5) printf( 1 n ); else printf( %d n , n % 3 + 1); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_TB_V
`define SKY130_FD_SC_HS__O41A_TB_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o41a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 A3 = 1'b1;
#220 A4 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 A3 = 1'b0;
#360 A4 = 1'b0;
#380 B1 = 1'b0;
#400 VGND = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VGND = 1'b1;
#480 B1 = 1'b1;
#500 A4 = 1'b1;
#520 A3 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VGND = 1'bx;
#620 B1 = 1'bx;
#640 A4 = 1'bx;
#660 A3 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hs__o41a dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_TB_V
|
#include <bits/stdc++.h> using namespace std; const long double epsilon = 1e-9; string minus1(const string& str) { string str1(str); for (int i = str.size() - 1; i >= 0; i--) { if (str1[i] != 0 ) { str1[i]--; break; } else str1[i] = 9 ; } return str1; } long long rem(const string& str, long long c) { long long temp = 0; for (int i = 0; i < str.size(); i++) { temp = (temp * 10LL + (long long)(str[i] - 0 )) % c; } return temp; } long long phi(long long c) { long long res = 1; for (long long i = 2; i * i <= c; i++) { if (c % i == 0) { c /= i; res *= (i - 1); while (c % i == 0) { c /= i; res *= i; } } } if (c > 1) res *= c - 1; return res; } long long rem2(const string& str, long long c) { long long temp = 0; long long t2; for (int i = 0; i < str.size(); i++) { t2 = (temp * 10LL + (long long)(str[i] - 0 )); temp = t2 % c + t2 / c; } return temp; } long long powe(long long a, long long p, long long c) { long long res = 1; long long mul = a; while (p > 0) { if (p & 1) { res = (res * mul) % c; } mul = (mul * mul) % c; p >>= 1; } return res; } long long bruteForce(string B, string N, long long c) { stringstream ss; ss << B << << N; long long b, n; ss >> b >> n; long long res = (b - 1) % c; for (int i = 1; i < n; i++) res = (res * b) % c; if (res == 0) res = c; return res; } long long nod(long long a, long long b) { if (a < b) swap(a, b); long long x; while (b) { x = a % b; a = b; b = x; } return a; } bool isPow(long long i, long long j) { if (j == 1) return false; while (i % j == 0) i /= j; return i == 1; } void fail() { long long nd; for (int i = 2; i < 10000; i++) { for (int j = 1; j < i; j++) { nd = nod(i, j); if (isPow(i, nd)) continue; if (powe(j, phi(i) + 1, i) != j) { cerr << Failed with: << i << << j << endl; return; } } } } int main() { string n, b; long long c; long long e; int o = 1; while (cin >> b >> n >> c) { long long a = rem(minus1(b), c); long long b2 = rem(b, c); n = minus1(n); long long mat[10]; for (int i = 0; i < 10; i++) mat[i] = 1LL; long long ge, ye; int idx; for (int i = n.size() - 1; i >= 0; i--) { idx = n[i] - 0 ; mat[idx] = (mat[idx] * b2) % c; ge = (b2 * b2) % c; ye = (ge * ge) % c; ye = (ye * ye) % c; b2 = (ye * ge) % c; } long long re = 1; for (int i = 0; i < 10; i++) { for (int j = 0; j < i; j++) re = (re * mat[i]) % c; } long long q = (a * re) % c; if (q == 0) q = c; cout << q << endl; o++; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, k, a[100005], vis[100005], cnt, t; void Solve() { scanf( %d %d , &n, &k); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); if (!vis[a[i]]) cnt++; ++vis[a[i]]; if (cnt == k) { t = 1; while (cnt == k) { --vis[a[t]]; if (!vis[a[t]]) --cnt; t++; } printf( %d %d n , t - 1, i); return; } } printf( -1 -1 n ); } int main(void) { Solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long q; cin >> q; while (q--) { long long n; cin >> n; vector<long long> vec(n, 0); vector<bool> vis(n, false); vector<pair<long long, long long>> p(n); for (long long i = 0; i < n; i++) cin >> vec[i]; for (long long i = 0; i < n; i++) { if (!vis[i]) { vis[i] = true; long long j = vec[i] - 1; long long days = 1; while (j != i) { p[j] = make_pair(1, i); vis[j] = true; j = vec[j] - 1; days++; } p[i] = make_pair(0, days); } } for (long long i = 0; i < n; i++) { if (p[i].first == 0) cout << p[i].second << ; else cout << p[p[i].second].second << ; } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n; while (n--) { cin >> m; if (m % 2 == 1) cout << (m + 1) / 2 << endl; else cout << 1 + m / 2 << endl; } } |
module etx(/*AUTOARG*/
// Outputs
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, txrd_wait, txwr_wait, txrr_wait, etx_cfg_access,
etx_cfg_packet,
// Inputs
etx_reset, sys_reset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4,
txi_wr_wait_p, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n,
txrd_access, txrd_packet, txwr_access, txwr_packet, txrr_access,
txrr_packet, etx_cfg_wait, etx90_reset
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h000;
parameter IOSTD_ELINK = "LVDS_25";
parameter ETYPE = 1;
//Synched resets
input etx_reset; // reset for core logic
input sys_reset; // reset for fifos
//Clocks
input sys_clk; // clock for fifos
input tx_lclk; // fast clock for io
input tx_lclk90; // 90 deg shifted lclk
input tx_lclk_div4; // slow clock for core logic
//Transmit signals for IO
output txo_lclk_p, txo_lclk_n; // tx clock output
output txo_frame_p, txo_frame_n; // tx frame signal
output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
input txi_wr_wait_p,txi_wr_wait_n; // tx async write pushback
input txi_rd_wait_p, txi_rd_wait_n; // tx async read pushback
//Read Request Channel Input
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Write Channel Input
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Read Response Channel Input
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
//Configuration Interface (for ERX)
output etx_cfg_access;
output [PW-1:0] etx_cfg_packet;
input etx_cfg_wait;
input etx90_reset;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire tx_access; // From etx_core of etx_core.v
wire tx_burst; // From etx_core of etx_core.v
wire tx_io_wait; // From etx_io of etx_io.v
wire [PW-1:0] tx_packet; // From etx_core of etx_core.v
wire tx_rd_wait; // From etx_io of etx_io.v
wire tx_wr_wait; // From etx_io of etx_io.v
wire txrd_fifo_access; // From etx_fifo of etx_fifo.v
wire [PW-1:0] txrd_fifo_packet; // From etx_fifo of etx_fifo.v
wire txrd_fifo_wait; // From etx_core of etx_core.v
wire txrr_fifo_access; // From etx_fifo of etx_fifo.v
wire [PW-1:0] txrr_fifo_packet; // From etx_fifo of etx_fifo.v
wire txrr_fifo_wait; // From etx_core of etx_core.v
wire txwr_fifo_access; // From etx_fifo of etx_fifo.v
wire [PW-1:0] txwr_fifo_packet; // From etx_fifo of etx_fifo.v
wire txwr_fifo_wait; // From etx_core of etx_core.v
/************************************************************/
/*FIFOs */
/************************************************************/
etx_fifo etx_fifo (/*AUTOINST*/
// Outputs
.txrd_wait (txrd_wait),
.txwr_wait (txwr_wait),
.txrr_wait (txrr_wait),
//.etx_cfg_access (etx_cfg_access),
//.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
.txrd_fifo_access (txrd_fifo_access),
.txrd_fifo_packet (txrd_fifo_packet[PW-1:0]),
.txrr_fifo_access (txrr_fifo_access),
.txrr_fifo_packet (txrr_fifo_packet[PW-1:0]),
.txwr_fifo_access (txwr_fifo_access),
.txwr_fifo_packet (txwr_fifo_packet[PW-1:0]),
// Inputs
.etx_reset (etx_reset),
.sys_reset (sys_reset),
.sys_clk (sys_clk),
.tx_lclk_div4 (tx_lclk_div4),
.txrd_access (txrd_access),
.txrd_packet (txrd_packet[PW-1:0]),
.txwr_access (txwr_access),
.txwr_packet (txwr_packet[PW-1:0]),
.txrr_access (txrr_access),
.txrr_packet (txrr_packet[PW-1:0]),
.etx_cfg_wait (etx_cfg_wait),
.txrd_fifo_wait (txrd_fifo_wait),
.txrr_fifo_wait (txrr_fifo_wait),
.txwr_fifo_wait (txwr_fifo_wait));
/***********************************************************/
/*ELINK CORE LOGIC */
/***********************************************************/
/*etx_core AUTO_TEMPLATE ( .tx_access (tx_access),
.tx_burst (tx_burst),
.tx_io_wait (tx_io_wait),
.tx_rd_wait (tx_rd_wait),
.tx_wr_wait (tx_wr_wait),
.tx_packet (tx_packet[PW-1:0]),
.etx_cfg_access (etx_cfg_access),
.etx_cfg_packet (etx_cfg_packet[PW-1:0]),
.etx_cfg_wait (etx_cfg_wait),
.\(.*\)_packet (\1_fifo_packet[PW-1:0]),
.\(.*\)_access (\1_fifo_access),
.\(.*\)_wait (\1_fifo_wait),
);
*/
defparam etx_core.ID=ID;
etx_core etx_core (.clk (tx_lclk_div4),
.reset (etx_reset),
/*AUTOINST*/
// Outputs
.tx_access (tx_access), // Templated
.tx_burst (tx_burst), // Templated
.tx_packet (tx_packet[PW-1:0]), // Templated
.txrd_wait (txrd_fifo_wait), // Templated
.txrr_wait (txrr_fifo_wait), // Templated
.txwr_wait (txwr_fifo_wait), // Templated
.etx_cfg_access (etx_cfg_access), // Templated
.etx_cfg_packet (etx_cfg_packet[PW-1:0]), // Templated
// Inputs
.tx_io_wait (tx_io_wait), // Templated
.tx_rd_wait (tx_rd_wait), // Templated
.tx_wr_wait (tx_wr_wait), // Templated
.txrd_access (txrd_fifo_access), // Templated
.txrd_packet (txrd_fifo_packet[PW-1:0]), // Templated
.txrr_access (txrr_fifo_access), // Templated
.txrr_packet (txrr_fifo_packet[PW-1:0]), // Templated
.txwr_access (txwr_fifo_access), // Templated
.txwr_packet (txwr_fifo_packet[PW-1:0]), // Templated
.etx_cfg_wait (etx_cfg_wait)); // Templated
/***********************************************************/
/*TRANSMIT I/O LOGIC */
/***********************************************************/
defparam etx_io.IOSTD_ELINK=IOSTD_ELINK;
etx_io etx_io (.reset (etx_reset),
.etx90_reset (etx90_reset),
/*AUTOINST*/
// Outputs
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.tx_io_wait (tx_io_wait),
.tx_wr_wait (tx_wr_wait),
.tx_rd_wait (tx_rd_wait),
// Inputs
.tx_lclk (tx_lclk),
.tx_lclk90 (tx_lclk90),
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.tx_packet (tx_packet[PW-1:0]),
.tx_access (tx_access),
.tx_burst (tx_burst));
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../edma/hdl/")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; int D[100010]; int TN[100010]; vector<int> G[100010]; vector<int> T[100010]; vector<long long int> TS[100010]; map<int, double> S[100010]; struct Furthest { int s, t, x, maxl, N; void DFS1(int u, int f, int l) { if (l > maxl) { x = u; maxl = l; } TN[u] = N; for (auto it = G[u].begin(); it != G[u].end(); ++it) { int v = *it; if (v != f) DFS1(v, u, l + 1); } } void DFS2(int u, int f, int l) { if (l > maxl) { x = u; maxl = l; } if (l > D[u]) D[u] = l; for (auto it = G[u].begin(); it != G[u].end(); ++it) { int v = *it; if (v != f) DFS2(v, u, l + 1); } } void DFS3(int u, int f, int l) { if (l > D[u]) D[u] = l; T[N].push_back(D[u]); for (auto it = G[u].begin(); it != G[u].end(); ++it) { int v = *it; if (v != f) DFS3(v, u, l + 1); } } void Find(int u, int n) { N = n; maxl = -1; DFS1(u, -1, 0); s = x; maxl = -1; DFS2(s, -1, 0); t = x; DFS3(t, -1, 0); sort(T[N].begin(), T[N].end()); TS[N].push_back(0); for (int i = 1; i <= T[N].size(); ++i) TS[N].push_back(T[N][i - 1] + TS[N][i - 1]); if (D[t] != D[s]) cout << Wrong! << endl; } }; Furthest fest; int main() { ios::sync_with_stdio(false); int n, m, q, i, j, k, x, y, cnt, u, v; cin >> n >> m >> q; for (i = 0; i < m; ++i) { cin >> u >> v; G[u].push_back(v); G[v].push_back(u); } cnt = 0; memset(D, 0xFF, sizeof(D)); for (i = 1; i <= n; ++i) if (D[i] < 0) fest.Find(i, cnt++); for (i = 0; i < q; ++i) { cin >> u >> v; x = TN[u]; y = TN[v]; if (x == y) cout << -1 << endl; else { if (T[x].size() > T[y].size()) swap(x, y); if (S[x].find(y) != S[x].end()) cout << S[x][y] << endl; else { int minv, maxl; double sum = 0; for (j = 0; j < T[x].size(); ++j) { u = T[x][j]; maxl = max(*T[x].rbegin(), *T[y].rbegin()); minv = maxl - u; k = lower_bound(T[y].begin(), T[y].end(), minv) - T[y].begin(); sum += (long long int)maxl * k + *TS[y].rbegin() - TS[y][k] + (T[y].size() - k) * (u + 1); } sum /= T[x].size() * T[y].size(); S[x][y] = sum; cout << fixed << setprecision(10) << sum << endl; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, s; cin >> n >> s; int a[n + 1]; int cnt = 0; for (int i = 1; i < n; ++i) { a[i] = 1; cnt++; } a[n] = s - cnt; s -= cnt; if (s - cnt < 2) { cout << NO << endl; } else { cout << YES << endl; for (int i = 1; i <= n; ++i) cout << a[i] << ; cout << endl; cout << (cnt + 1) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100; int l[N], r[N], t[N], c[N]; int main() { int n, m; scanf( %d %d , &n, &m); for (int i = 0; i < m; ++i) { scanf( %d %d %d %d , l + i, r + i, t + i, c + i); } int ans = 0; for (int i = 1; i <= n; ++i) { int win = 0, min = -1; for (int j = 0; j < m; ++j) { if (l[j] <= i && i <= r[j]) { if (min == -1 || min > t[j]) { min = t[j]; win = c[j]; } } } ans += win; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 100010; const int M = 310; int n, m, s, e0, E; pair<int, int> dp[N][M]; int a[N]; vector<int> elAtB[N]; inline int findj(int j0, int val) { if (j0 >= m) return -1; vector<int> &v = elAtB[val]; if (v.size() == 0) return -1; vector<int>::iterator it = lower_bound(v.begin(), v.end(), j0); if (it == v.end()) return -1; else return *it; } int main() { cin >> n >> m >> s >> e0; E = s / e0; int ost = s - E * e0; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int j = 0; j < m; j++) { int x; cin >> x; elAtB[x].push_back(j); } int ans = 0; for (int i = 0; i <= n; i++) { for (int e = 0; e <= E; e++) { dp[i][e] = make_pair(0, 0); } } for (int i = 0; i < n; i++) { for (int e = 1; e <= E; e++) { int dol = dp[i][e].first; int j0 = dp[i][e].second; int dolnxt = dp[i + 1][e].first; if (dol > dolnxt) { dp[i + 1][e] = make_pair(dol, j0); } int j = findj(j0, a[i]); if (j == -1) continue; else { } dolnxt = dp[i + 1][e - 1].first; int jnxt = dp[i + 1][e - 1].second; if (((dol + 1 > dolnxt) || (dol + 1 == dolnxt && j < jnxt)) && ((i + 1 + j + 1) <= (e - 1) * e0 + ost)) { dp[i + 1][e - 1] = make_pair(dol + 1, j + 1); ans = max(ans, dol + 1); } } } cout << ans << endl; return 0; } |
#include bits/stdc++.h using namespace std; typedef long long ll; typedef long double ld; typedef unsigned long long ull; #define int ll #define sz(a) int(a.size()) #define dbg(a) cout << #a << = << a << endl #define dbg1(a) cout << #a << = [ ; for (auto& _ : a) cout << _ << ; cout << ] << endl #define dbg2(a) cout << #a << = [ ; for (auto& _ : a) cout << ( << _.first << << _.second << ) ; cout << ] << endl const int inf = int(1e9) + 7; void solve() { int n; cin >> n; bool ok = false; for (int i = 0; i < n; ++i) { int q; cin >> q; ok |= q != int(sqrt(q)) * int(sqrt(q)); } cout << (ok ? YES n : NO n ); } signed main() { ios::sync_with_stdio(0); cin.tie(0); cout << fixed << setprecision(15); int tests = 1; cin >> tests; while (tests--) { solve(); } } |
#include <bits/stdc++.h> int find_min(int pos, int target) { int right = -1; for (int i = 0; right == -1; i++) if ((pos + i) % 26 == target) right = i; int left = -1; for (int i = 0; left == -1; i++) if ((pos - i + 26 * 2) % 26 == target) left = i; return std::min(right, left); } int main() { int n; std::cin >> n; std::string s; std::cin >> s; std::string genome = ACTG ; int min_moves = INT_MAX; for (int i = 0; i < n - 3; i++) { int min_temp = 0; for (int j = 0; j < 4; j++) min_temp += find_min(s[i + j] - A , genome[j] - A ); min_moves = std::min(min_moves, min_temp); } std::cout << min_moves << n ; return 0; } |
#include <iostream> #include <algorithm> using namespace std; int main() { int64_t k; int64_t n, x, t; cin >> k; while(k--) { cin >> n >> x >> t; int64_t zero = 0; int64_t ans = max(zero, n - t/x) * (t / x) + min(t/x, n) * min(t/x - 1, n - 1) / 2; cout << ans << endl; } return 0; } |
/*
* Wishbone Flash RAM core for Altera DE2 board (90ns registered)
* Copyright (c) 2009 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module flash8_r2 (
// Wishbone slave interface
input wb_clk_i,
input wb_rst_i,
input [15:0] wb_dat_i,
output reg [15:0] wb_dat_o,
input wb_we_i,
input wb_adr_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output reg wb_ack_o,
// Pad signals
output reg [22:0] flash_addr_,
input [ 7:0] flash_data_,
output flash_we_n_,
output reg flash_oe_n_,
output reg flash_ce_n_,
output flash_rst_n_
);
// Registers and nets
wire op;
wire wr_command;
wire flash_addr0;
reg [21:0] address;
wire word;
wire op_word;
reg [ 3:0] st;
reg [ 7:0] lb;
// Combinatorial logic
assign op = wb_stb_i & wb_cyc_i;
assign word = wb_sel_i==2'b11;
assign op_word = op & word & !wb_we_i;
assign flash_rst_n_ = 1'b1;
assign flash_we_n_ = 1'b1;
assign flash_addr0 = (wb_sel_i==2'b10) | (word & |st[2:1]);
assign wr_command = op & wb_we_i; // Wishbone write access Signal
// Behaviour
// flash_addr_
always @(posedge wb_clk_i)
flash_addr_ <= { address, flash_addr0 };
// flash_oe_n_
always @(posedge wb_clk_i)
flash_oe_n_ <= !(op & !wb_we_i);
// flash_ce_n_
always @(posedge wb_clk_i)
flash_ce_n_ <= !(op & !wb_we_i);
// wb_dat_o
always @(posedge wb_clk_i)
wb_dat_o <= wb_rst_i ? 16'h0
: (st[2] ? (wb_sel_i[1] ? { flash_data_, lb }
: { 8'h0, flash_data_ })
: wb_dat_o);
// wb_ack_o
always @(posedge wb_clk_i)
wb_ack_o <= wb_rst_i ? 1'b0
: (wb_ack_o ? 1'b0 : (op & (wb_we_i ? 1'b1 : st[2])));
// st - state
always @(posedge wb_clk_i)
st <= wb_rst_i ? 4'h0
: (op & st==4'h0 ? (word ? 4'b0001 : 4'b0100)
: { st[2:0], 1'b0 });
// lb - low byte
always @(posedge wb_clk_i)
lb <= wb_rst_i ? 8'h0 : (op_word & st[1] ? flash_data_ : 8'h0);
// --------------------------------------------------------------------
// Register addresses and defaults
// --------------------------------------------------------------------
`define FLASH_ALO 1'h0 // Lower 16 bits of address lines
`define FLASH_AHI 1'h1 // Upper 6 bits of address lines
always @(posedge wb_clk_i) // Synchrounous
if(wb_rst_i)
address <= 22'h000000; // Interupt Enable default
else
if(wr_command) // If a write was requested
case(wb_adr_i) // Determine which register was writen to
`FLASH_ALO: address[15: 0] <= wb_dat_i;
`FLASH_AHI: address[21:16] <= wb_dat_i[5:0];
default: ; // Default
endcase // End of case
endmodule
|
#include <bits/stdc++.h> using namespace std; bool compa(int i, int j) { return i > j; } long long int power(long long int a, long long int n) { if (n == 0) return 1; else if (n % 2) { long long int d1 = power(a, n / 2); return d1 * d1 * a; } else { long long int d1 = power(a, n / 2); return d1 * d1; } } int find_pivot(int a[], int l, int r) { while (l < r) { int mid = (l + r) / 2; if (a[l] > a[l + 1]) { return l; } else if (a[r] > a[r + 1]) return r; else if (a[mid] > a[mid + 1]) { return mid; } else if (a[mid] > a[r]) { l = mid + 1; cout << l << l; } else if (a[mid] < a[r]) { r = mid - 1; cout << r << r; } } return -1; } int main() { int n; cin >> n; string s; cin >> s; bool ans[4]; for (int i = 0; i < 4; i++) ans[i] = true; for (int i = 0; s[i] != 0 ; i++) { if (s[i] == 1 ) { ans[0] = false; ans[2] = false; } if (s[i] == 2 ) { ans[0] = false; } if (s[i] == 3 ) { ans[0] = false; ans[3] = false; } if (s[i] == 4 ) { ans[2] = false; } if (s[i] == 6 ) { ans[3] = false; } if (s[i] == 7 ) { ans[1] = false; ans[2] = false; } if (s[i] == 9 ) { ans[1] = false; ans[3] = false; } if (s[i] == 0 ) { ans[1] = false; ans[2] = false; ans[3] = false; } } if (ans[0] || ans[1] || ans[2] || ans[3]) cout << NO ; else cout << YES ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, s = 0, t = 0; string road; cin >> n >> road; for (int i = 1; i < n; ++i) { if (road[i] == L ) { t = i; for (int j = i + 1; j < n; ++j) { if (road[j] == . ) { s = j; break; } } break; } else if (road[i] == R ) { s = i + 1; for (int j = i + 1; j < n; ++j) { if (road[j] != R ) { t = (road[j] == . ? j + 1 : j); break; } } break; } } cout << s << << t << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void solve() { long long int n, k; cin >> n >> k; if (k > n) cout << -1 << n ; else if (n != 1 && k == 1) cout << -1 << n ; else if (k == n) { char x = a ; for (long long int i = 1; i <= (long long int)n; i++) { cout << x; x++; } } else if (k < n) { long long int t = n - (k - 2); for (long long int i = 1; i <= (long long int)t; i++) { if (i % 2 != 0) cout << a ; else cout << b ; } long long int q = n - t; char y = c ; if (q > 0) { for (long long int i = 1; i <= (long long int)q; i++) { cout << y; y++; } } } } int main() { std::ios::sync_with_stdio(false); int t = 1; while (t--) { solve(); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:50:04 07/21/2014
// Design Name:
// Module Name: divider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module divider(
input [7:0] div, // dividend switch [15:8]
input [7:0] dvr, // divisor switch [7:0]
input clk,
output [7:0] quotient, // quotient
output [7:0] remainder // remainder
);
integer i;
//reg [7:0] r_d_diff;
reg [7:0] diff; // remainder - divisor diff result
//reg [8:0] c0;
reg [7:0] qu;// quotient
reg [7:0] rem;// remainder
always @(posedge clk) begin
//c0[0] = 1'b1;
rem [7:0] = 8'b0; // assign reminader to all zeros initially
qu [7:0] = div[7:0]; // place dividend in Quotient
for (i=0;i<=7;i=i+1) begin
//repeat (8)
rem = rem<<1;// first iteration shift
rem[0] = qu[7];// first iteration shift
qu = qu<<1;// first iteration shift
qu[0] = 1'b0;// first iteration shift
if ( rem >= dvr) begin
rem = rem-dvr;
qu[0] = 1'b1;
end
end
end
assign remainder [7:0] = rem[7:0];
assign quotient [7:0] = qu[7:0];
endmodule
|
#include <bits/stdc++.h> using namespace std; const double eps = 1E-9; const double Exp = 2.718281828459045; const double pi = 3.14159; const double E = 2.7182818284590452354; int isRight(int x1, int x2) { if (x1 < x2) return 1; else return -1; } int main() { int arr[3][2]; for (int i = 0; i < 3; ++i) { cin >> arr[i][0] >> arr[i][1]; } int resultArr[3][2]; double xn = (arr[0][0] + arr[1][0]) / 2.0; double yn = (arr[0][1] + arr[1][1]) / 2.0; resultArr[0][0] = 2 * xn - arr[2][0]; resultArr[0][1] = 2 * yn - arr[2][1]; xn = (arr[1][0] + arr[2][0]) / 2.0; yn = (arr[1][1] + arr[2][1]) / 2.0; resultArr[1][0] = 2 * xn - arr[0][0]; resultArr[1][1] = 2 * yn - arr[0][1]; xn = (arr[0][0] + arr[2][0]) / 2.0; yn = (arr[0][1] + arr[2][1]) / 2.0; resultArr[2][0] = 2 * xn - arr[1][0]; resultArr[2][1] = 2 * yn - arr[1][1]; int number = 3; if (resultArr[0][0] == resultArr[1][0] && resultArr[0][1] == resultArr[1][1]) { number--; } if (resultArr[1][0] == resultArr[2][0] && resultArr[1][1] == resultArr[2][1]) { number--; } if (resultArr[2][0] == resultArr[0][0] && resultArr[2][1] == resultArr[0][1]) { number--; } cout << number << endl; for (int i = 0; i < 3; ++i) { cout << resultArr[i][0] << << resultArr[i][1] << endl; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2AI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O2BB2AI_BEHAVIORAL_PP_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire nand1_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2AI_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; unordered_set<int> S; int main() { int n; cin >> n; int A[n], dp[n + 1]; dp[0] = 0; S.clear(); for (int _n{n}, i{0}; i < _n; ++i) { cin >> A[i]; dp[i + 1] = dp[i]; if (!S.count(A[i])) { S.insert(A[i]); dp[i + 1]++; } } S.clear(); uint64_t ans = 0; for (int _n{n + 1}, i{1}; i < _n; ++i) { if (!S.count(A[n - i])) { ans += dp[n - i]; S.insert(A[n - i]); } } cout << ans << endl; } |
// UC Berkeley CS251
// Spring 2018
// Arya Reais-Parsi ()
// Stage #1: Fetch and Decode.
`include "const.vh"
module FetchDecodeStage #(
parameter ADDR_LEN = `CPU_ADDR_BITS
)(
input wire clk,
input wire reset,
// This is the address presented to the instruction memory. We expect it to
// take 1 cycle to read.
output wire [ADDR_LEN-1:0] s1_imem_addr,
// This is the address associated with the instruction presented to s1_inst,
// since it took 1 cycle to read.
output wire [ADDR_LEN-1:0] s1_pc,
input wire [ADDR_LEN-1:0] s3_pc,
input wire [ADDR_LEN-1:0] override_pc,
// Select source for next PC.
input wire [1:0] s1_pc_sel,
// Instruction from memory.
input wire [`CPU_INST_BITS-1:0] s1_inst,
// Decoded instruction parts.
output wire [4:0] s1_rs1,
output wire [4:0] s1_rs2,
output wire [4:0] s1_rd,
output wire [11:0] s1_imm_i,
output wire [19:0] s1_imm_uj,
output wire [11:0] s1_imm_bs,
output wire [6:0] s1_opcode,
output wire [2:0] s1_func,
output wire s1_add_rshift_type
);
reg [ADDR_LEN-1:0] pc;
reg [ADDR_LEN-1:0] next_pc;
always @(*) begin
case (s1_pc_sel)
`S1_PC_SEL_OVERRIDE: next_pc = override_pc;
`S1_PC_SEL_S3: next_pc = s3_pc;
`S1_PC_SEL_STALL: next_pc = pc;
default: next_pc = pc + 4;
endcase
end
assign s1_imem_addr = next_pc;
// NOTE(aryap): Tragedy. Instruction fetch takes a whole cycle. We need to
// associate the previous pc value with the current instruction.
// Set next cycle's PC value.
always @(posedge clk) begin
if (reset) pc <= 0;
// NOTE(aryap): No explicitly stall here; controller has to hold
// s1_pc_sel.
else pc <= next_pc;
end
// Decode instruction.
// TODO(aryap): These indices can be `defined in a header.
assign s1_rs1 = s1_inst[19:15];
assign s1_rs2 = s1_inst[24:20];
assign s1_rd = s1_inst[11:7];
assign s1_imm_i = s1_inst[31:20];
assign s1_imm_uj = s1_inst[31:12];
assign s1_imm_bs = {s1_inst[31:25], s1_inst[11:7]};
assign s1_opcode = s1_inst[6:0];
assign s1_func = s1_inst[14:12];
assign s1_add_rshift_type = s1_inst[30];
assign s1_pc = pc;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; int ans = 1; if (a > b) { for (int i = b; i >= 1; i--) { ans *= i; } } else { for (int i = a; i >= 1; i--) { ans *= i; } } cout << ans; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31O_1_V
`define SKY130_FD_SC_MS__A31O_1_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a31o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a31o_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31O_1_V
|
#include <bits/stdc++.h> using namespace std; struct data { int id, a; data() {} data(int id, int a) : id(id), a(a) {} bool operator<(const data &r) const { return a < r.a; } } da[100010]; int n, h; int main() { scanf( %d%d , &n, &h); for (int i = 0; i < n; i++) scanf( %d , &da[i].a), da[i].id = i; if (n == 2) { printf( 0 n ); for (int i = 0; i < n; i++) printf( 1 ); puts( ); return 0; } sort(da, da + n); int f1 = da[n - 1].a + da[n - 2].a - da[0].a - da[1].a; int f2 = max(da[n - 1].a + da[0].a + h, da[n - 1].a + da[n - 2].a) - min(da[0].a + da[1].a + h, da[1].a + da[2].a); if (f1 <= f2) { printf( %d n , f1); for (int i = 0; i < n; i++) printf( 1 ); puts( ); } else { printf( %d n , f2); for (int i = 0; i < n; i++) if (da[0].id == i) printf( 1 ); else printf( 2 ); puts( ); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long T, W, B, H, P; long long fpb(long long A, long long B) { if (A == 0) { return B; } return fpb(B % A, A); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> T >> W >> B; H = W / fpb(W, B); if (T / B < H) { P = min(W, B) - 1 - max((long long)0, min(W, B) - 1 - T); } else { H *= B; P = (T / H + 1) * min(W, B) - 1 - max((long long)0, min(W, B) - 1 - T % H); } H = fpb(P, T); cout << P / H << / << T / H << n ; } |
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
module test_axis_async_frame_fifo;
// Inputs
reg input_clk = 0;
reg input_rst = 0;
reg output_clk = 0;
reg output_rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg output_axis_tready = 0;
// Outputs
wire input_axis_tready;
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
initial begin
// myhdl integration
$from_myhdl(input_clk,
input_rst,
output_clk,
output_rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
output_axis_tready);
$to_myhdl(input_axis_tready,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast);
// dump file
$dumpfile("test_axis_async_frame_fifo.lxt");
$dumpvars(0, test_axis_async_frame_fifo);
end
axis_async_frame_fifo #(
.ADDR_WIDTH(9),
.DATA_WIDTH(8),
.DROP_WHEN_FULL(0)
)
UUT (
// AXI input
.input_clk(input_clk),
.input_rst(input_rst),
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
// AXI output
.output_clk(output_clk),
.output_rst(output_rst),
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tready(output_axis_tready),
.output_axis_tlast(output_axis_tlast)
);
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: bg.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bg (
address,
clock,
q);
input [9:0] address;
input clock;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({24{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "mifs/bg.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 24,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "mifs/bg.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "24"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "mifs/bg.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_a 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bg_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> int ans = 2, n, t; double m; struct T { int x, t; } a[1111]; bool my(T a, T b) { return (a.x < b.x); } int main() { scanf( %d%d , &n, &t); for (int i = 1; i <= n; i++) scanf( %d%d , &a[i].x, &a[i].t); std::sort(a + 1, a + n + 1, &my); for (int i = 2; i <= n; i++) { m = a[i].x - a[i - 1].x - (double)a[i].t / 2 - (double)a[i - 1].t / 2; if (m > t) ans += 2; else if (m == t) ++ans; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int Maxn = 4010; double num1[Maxn]; int num2[Maxn]; double dif[Maxn]; int main() { int n = 0, N = 0; int cnt = 0, cnt1 = 0, cnt2 = 0; double sum = 0; double ans = 100000000.0; scanf( %d , &n); N = 2 * n; for (int i = 0; i < N; i++) { scanf( %lf , &num1[i]); num2[i] = num1[i]; dif[i] = (double)num1[i] - (double)num2[i]; } for (int i = 0; i < N; i++) { if (dif[i] != 0) { cnt1++; sum += dif[i]; } else { cnt2++; } } cnt = min(cnt1, n); for (int i = 0; i <= cnt; i++) { if (i + cnt2 >= n) { ans = min(ans, fabs(sum - i * 1.0)); } } printf( %.3f , ans); return 0; } |
#include<bits/stdc++.h> #include<algorithm> #define ll long long using namespace std; int main(){ ios_base::sync_with_stdio(false); cin.tie(NULL); int testcases; cin>>testcases; while(testcases--){ int n,k; cin>>n>>k; unsigned ll sum = 0 ; cin>>sum; unsigned ll diff = 0; for (int i = 0; i < n-1; ++i) { ll current; cin>>current; double thiscase = (1.00*sum) / current ; if(thiscase < (100.00/k)){ ll currentdiff = ceil((100.00*current) / k) - sum; diff += currentdiff; sum += currentdiff; } sum+= current; } cout<<diff<< n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; using namespace std; using ll = long long; using ld = long double; const int MOD = 1e9 + 7, inf = 1e9, N = 2e5 + 1; const ll INF = 1e18; ld tic, tac; void solve() { string str, ans = ; cin >> str; int cr = 0, cs = 0, cp = 0; for (int i = 0; i < (str.size()); ++i) { if (str[i] == R ) cr++; else if (str[i] == P ) cp++; else cs++; } char ch; if (cr >= cp && cr >= cs) ch = P ; else if (cp >= cs && cp >= cr) ch = S ; else ch = R ; cout << string(str.size(), ch) << n ; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t = 1; cin >> t; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> #pragma gcc optimize(O3) using namespace std; long long INF = static_cast<long long>(2e18); long long inf = static_cast<long long>(1e9 + 7); long long gcd(long long a, long long b) { return b ? gcd(b, a % b) : a; } vector<vector<set<long long> > > dp; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n, k; cin >> n >> k; vector<long long> vals(n); dp.resize(k, vector<set<long long> >(n)); for (auto& it : vals) cin >> it; for (long long i = n - 2; i >= 0; --i) vals[i] += vals[i + 1]; for (long long i = n - 1; i >= 0; --i) dp[0][i].insert(vals[i]); if (k == 1) { cout << vals[0]; return 0; } long long res = 0; for (long long i = 1; i < k; i++) { for (long long j = n - 1 - i; j >= k - i - 1; --j) { for (long long q = j + 1; q < n - i + 1; ++q) { for (auto& it : dp[i - 1][q]) { if (i == (k - 1) && (!j)) { res = max(res, ((vals[j] - vals[q]) & it)); } else dp[i][j].insert((vals[j] - vals[q]) & it); } } } } cout << res; return 0; } |
`timescale 1ns / 1ns
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:28:18 02/06/2014
// Design Name:
// Module Name: test1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tld_zxuno (
input wire clk50mhz,
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire csync,
output wire stdn,
output wire stdnb,
output wire [20:0] sram_addr,
inout wire [7:0] sram_data,
output wire sram_we_n
);
assign stdn = 1'b0; // PAL
assign stdnb = 1'b1;
// Generación de relojes
reg [1:0] divs = 2'b00;
wire wssclk,sysclk;
wire clk14 = divs[0];
wire clk7 = divs[1];
always @(posedge sysclk)
divs <= divs + 1;
relojes los_relojes_del_sistema (
.CLKIN_IN(clk50mhz),
.CLKDV_OUT(wssclk),
.CLKFX_OUT(sysclk),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT(),
.LOCKED_OUT()
);
// Instanciación del sistema
zxuno la_maquina (
.clk(clk7),
.sramclk(sysclk),
.wssclk(wssclk),
.r(r),
.g(g),
.b(b),
.csync(csync),
.sram_addr(sram_addr),
.sram_data(sram_data),
.sram_we_n(sram_we_n)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } int count1 = 0; for (int i = 0; i < n; i++) { int sum = 0; for (int j = 0; j < n; j++) { if (i == j) { continue; } else { sum += a[j]; } } if (sum % 2 == 0) { count1++; } } cout << count1 << endl; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a21oi (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, B1, and0_out );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_BEHAVIORAL_V |
module arbiter(
// Inputs
input_arry,
issued_en,
issued_wf_id,
// Outputs
choosen_valid,
choosen_wf_id,
clk,
rst
);
input clk,rst;
input issued_en;
input[5:0] issued_wf_id;
input[39:0] input_arry;
output choosen_valid;
output[5:0] choosen_wf_id;
wire[5:0] last_issued_wf_id, last_issued_wf_id_corr_output, priority_encoder_out;
wire[39:0] priority_encoder_in, decoded_priority_encoder_out, choosen_wf_id_encoded;
reg_param #(6) last_wf_id_issued_reg(
.out(last_issued_wf_id),
.in(issued_wf_id),
.wr_en(issued_en),
.clk(clk),
.rst(rst)
);
circular_barrel_shift input_priority_shifter(
.output_val(priority_encoder_in),
.input_val(input_arry),
.shift_amt(last_issued_wf_id)
);
circular_barrel_shift output_priority_shifter(
.output_val(choosen_wf_id_encoded),
.input_val(decoded_priority_encoder_out),
.shift_amt(last_issued_wf_id_corr_output)
);
decoder_6b_40b_en decoder_6b_40b_en(
.addr_in(priority_encoder_out),
.out(decoded_priority_encoder_out),
.en(choosen_valid)
);
priority_encoder_40to6 priority_encoder(
.binary_out(priority_encoder_out),
.valid(choosen_valid),
.encoder_in(priority_encoder_in),
.enable(|priority_encoder_in)
);
encoder encoder(
.in(choosen_wf_id_encoded),
.out(choosen_wf_id)
);
assign last_issued_wf_id_corr_output = 6'd40 - last_issued_wf_id;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41A_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O41A_FUNCTIONAL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o41a (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41A_FUNCTIONAL_V |
module top(
input PACKAGEPIN,
output [1:0] PLLOUTCORE,
output [1:0] PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
//Test Pins
output SDO,
input SDI,
input SCLK
);
SB_PLL40_2_PAD #(
.FEEDBACK_PATH("DELAY"),
// .FEEDBACK_PATH("SIMPLE"),
// .FEEDBACK_PATH("PHASE_AND_DELAY"),
// .FEEDBACK_PATH("EXTERNAL"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
// .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
// .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
.PLLOUT_SELECT_PORTB("GENCLK"),
// .PLLOUT_SELECT_PORTB("GENCLK_HALF"),
// .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"),
// .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_FEEDBACK(4'b1111),
.FDA_RELATIVE(4'b1111),
.DIVR(4'b0000),
.DIVF(7'b0000000),
.DIVQ(3'b001),
.FILTER_RANGE(3'b000),
.ENABLE_ICEGATE_PORTA(1'b0),
.ENABLE_ICEGATE_PORTB(1'b0),
.TEST_MODE(1'b0)
) uut (
.PACKAGEPIN (PACKAGEPIN ),
.PLLOUTCOREA (PLLOUTCORE [0]),
.PLLOUTGLOBALA (PLLOUTGLOBAL[0]),
.PLLOUTCOREB (PLLOUTCORE [1]),
.PLLOUTGLOBALB (PLLOUTGLOBAL[1]),
.EXTFEEDBACK (EXTFEEDBACK ),
.DYNAMICDELAY (DYNAMICDELAY ),
.LOCK (LOCK ),
.BYPASS (BYPASS ),
.RESETB (RESETB ),
.LATCHINPUTVALUE(LATCHINPUTVALUE),
.SDO (SDO ),
.SDI (SDI ),
.SCLK (SCLK )
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:36:16 10/29/2011
// Design Name: M_uxa_ps2_shfreg
// Module Name: /Users/kc5tja/tmp/kestrel/2/nexys2/uxa/ps2io/T_uxa_ps2_shfreg.v
// Project Name: ps2io
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: M_uxa_ps2_shfreg
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module T_uxa_ps2_shfreg;
// Inputs
reg ps2_d_i;
reg ps2_c_i;
reg reset_i;
reg sys_clk_i;
// Outputs
wire [7:0] d_o;
wire frame_o;
// Instantiate the Unit Under Test (UUT)
M_uxa_ps2_shfreg uut (
.ps2_d_i(ps2_d_i),
.ps2_c_i(ps2_c_i),
.d_o(d_o),
.frame_o(frame_o),
.reset_i(reset_i),
.sys_clk_i(sys_clk_i)
);
always begin
#40 sys_clk_i <= 1;
#40 sys_clk_i <= 0;
end
initial begin
// Initialize Inputs
ps2_d_i = 1;
ps2_c_i = 1;
reset_i = 1;
sys_clk_i = 0;
#80 reset_i = 0;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#320 ;
if(d_o != 8'b01100100) begin
$display("Deserializer failed to grab byte correctly.");
$stop;
end
if(frame_o != 1) begin
$display("Deserializer failed to sync to the PS/2 frame.");
$stop;
end
reset_i = 1;
#80 reset_i = 0;
if(d_o != 8'b11111111) begin
$display("Deserializer didn't reset when instructed.");
$stop;
end
if(frame_o != 0) begin
$display("Frame indicator didn't reset when instructed.");
$stop;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSTP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DFSTP_BEHAVIORAL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfstp (
Q ,
CLK ,
D ,
SET_B
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSTP_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; inline int in() { int x; scanf( %d , &x); return x; } template <typename T> inline istream& operator>>(istream& i, vector<T>& v) { for (int j = 0; j < ((int)(v).size()); ++j) i >> v[j]; return i; } template <typename T> string join(const vector<T>& v) { stringstream s; for (int i = 0; i < ((int)(v).size()); ++i) s << << v[i]; return s.str().substr(1); } template <typename T> inline ostream& operator<<(ostream& o, const vector<T>& v) { if ((int)(v).size()) o << join(v); return o; } template <typename T1, typename T2> inline istream& operator>>(istream& i, pair<T1, T2>& v) { return i >> v.first >> v.second; } template <typename T1, typename T2> inline ostream& operator<<(ostream& o, const pair<T1, T2>& v) { return o << v.first << , << v.second; } template <typename T> inline long long int suma(const vector<T>& a) { long long int res(0); for (auto&& x : a) res += x; return res; } const double eps = 1e-10; const long long int LINF = 1001002003004005006ll; const int INF = 1001001001; const int MX = 200005; const int B = 9; inline long long int ten(int n) { return n ? ten(n - 1) * 10 : 1; } const int BS = ten(B); struct bint; istream& operator>>(istream& i, bint& a); ostream& operator<<(ostream& o, const bint& a); struct bint { vector<int> d; bool sg; bint(long long int n = 0) { sg = n < 0; if (sg) n = -n; while (n) { d.push_back(n % BS); n /= BS; } } bint(const string& s) { sg = s[0] == - ; int si = sg; for (int i = (int)(s).size(); i > si; i -= B) { d.push_back(0); for (int j = max(si, i - B); j < i; ++j) d.back() = d.back() * 10 + (s[j] - 0 ); } cut(); } bint(const vector<int>& d, bool sg = false) : d(d), sg(sg) {} inline bint& cut() { while ((int)(d).size() && !d.back()) d.pop_back(); sg &= !iszero(); return *this; } inline int size() const { return (int)(d).size(); } inline int& operator[](int i) { return d[i]; } inline const int& operator[](int i) const { return d[i]; } inline int len() const { if (!(int)(d).size()) return 0; int l = ((int)(d).size() - 1) * B; int b = d.back(); while (b) ++l, b /= 10; return l; } bint abs() const { bint a(*this); a.sg = false; return a; } inline bool iszero() const { return !(int)(d).size(); } long long int toLL() const { if (bint(INF) < abs()) return sg ? -INF : INF; long long int x = 0; for (int i = ((int)(d).size()) - 1; i >= 0; --i) x = x * BS + d[i]; if (sg) x = -x; return x; } bint& _add(const bint& a) { if ((int)(d).size() <= (int)(a).size()) d.resize((int)(a).size() + 1); else d.push_back(0); int i = 0; while (i < (int)(a).size()) { d[i] += a[i]; if (d[i] >= BS) d[i] -= BS, ++d[++i]; else ++i; } while (d[i] == BS) d[i] = 0, ++d[++i]; if (!d.back()) d.pop_back(); return *this; } bint& _asub(const bint& a) { int i = 0; while (i < (int)(a).size()) { d[i] -= a[i]; if (d[i] < 0) d[i] += BS, --d[++i]; else ++i; } if (i < (int)(d).size()) while (d[i] == -1) d[i] = BS - 1, --d[++i]; return cut(); } bint& _sub(const bint& a) { if (_cmp(a)) { bint b(a); swap(*this, b); return _asub(b); } return _asub(a); } bint& operator+=(const bint& a) { if (sg == a.sg) return _add(a); return _sub(a); } bint& operator-=(const bint& a) { if (sg != a.sg) return _add(a); sg ^= 1; _sub(a); if (!iszero()) sg ^= 1; return *this; } bint& operator*=(long long int a) { if (!a) return *this = 0; if (a < 0) sg ^= 1, a = -a; if (LINF / BS < a) return (*this) *= bint(a); long long int x = 0; for (int i = 0; i < ((int)(d).size()); ++i) { x += a * d[i]; d[i] = x % BS; x /= BS; } while (x) d.push_back(x % BS), x /= BS; return *this; } bint mult(const bint& a) const { if ((int)(a).size() == 1) return bint(*this) *= a[0]; if (a.iszero()) return 0; bint b = (*this) * a.d.back(); b.sg ^= a.sg; for (int i = ((int)(a).size() - 1) - 1; i >= 0; --i) { b.d.insert(b.d.begin(), 0); b += (*this) * a[i]; } return b; } long long int operator%(long long int a) const { assert(a > 0); long long int r = 0; for (int i = ((int)(d).size()) - 1; i >= 0; --i) r = (r * BS + d[i]) % a; if (sg) r = (a - r) % a; return r; } bint& operator/=(long long int a) { assert(a); if (a < 0) sg ^= 1, a = -a; assert(LINF / BS >= a); long long int x = 0; for (int i = ((int)(d).size()) - 1; i >= 0; --i) { x = x * BS + d[i]; d[i] = x / a; x %= a; } return cut(); } bint operator+(const bint& a) const { return bint(*this) += a; } bint operator-(const bint& a) const { return bint(*this) -= a; } bint operator*(long long int a) const { return bint(*this) *= a; } bint operator*(const bint& a) const; bint& operator*=(const bint& a) { return *this = (*this) * a; } bint operator/(long long int a) const { return bint(*this) /= a; } bint operator/(const bint& a) const { assert(false); return bint(); } bint operator%(const bint& a) const { assert(false); return bint(); } bint square() const; bint ex(long long int t) const { if (!t) return 1; bint a = ex(t >> 1).square(); if (t & 1) return a * (*this); return a; } bool _cmp(const bint& a) const { if ((int)(d).size() != (int)(a).size()) return (int)(d).size() < (int)(a).size(); for (int i = ((int)(d).size()) - 1; i >= 0; --i) if (d[i] != a[i]) return d[i] < a[i]; return false; } bool operator<(const bint& a) const { if (sg != a.sg) return sg; return sg ? a._cmp(*this) : _cmp(a); } bool operator<=(const bint& a) const { return !(a < (*this)); } bool operator==(const bint& a) const { return sg == a.sg && d == a.d; } string str() const { if (!(int)(d).size()) return 0 ; ostringstream os; if (sg) os << - ; os << d.back(); for (int i = ((int)(d).size() - 1) - 1; i >= 0; --i) os << setw(B) << setfill( 0 ) << d[i]; return os.str(); } }; long long int extgcd(long long int a, long long int b, long long int& x, long long int& y) { for (long long int u = y = 1, v = x = 0; a;) { long long int q = b / a; swap(x -= q * u, u); swap(y -= q * v, v); swap(b -= q * a, a); } return b; } long long int mod_inv(long long int a, long long int m) { long long int x, y; extgcd(a, m, x, y); return (m + x % m) % m; } long long int mod_pow(long long int a, long long int n, long long int mod) { long long int ret = 1; long long int p = a % mod; while (n) { if (n & 1) ret = ret * p % mod; p = p * p % mod; n >>= 1; } return ret; } template <int mod, int primitive_root> struct NTT { int get_mod() const { return mod; } void _ntt(vector<int>& a, int sign) { const int n = (int)(a).size(); int h = mod_pow(primitive_root, (mod - 1) / n, mod); if (sign == -1) h = mod_inv(h, mod); int i = 0; for (int j = 1; j < n - 1; ++j) { for (int k = n >> 1; k > (i ^= k); k >>= 1) ; if (j < i) swap(a[i], a[j]); } for (int m = 1; m < n; m *= 2) { const int m2 = m * 2; const long long int base = mod_pow(h, n / m2, mod); vector<long long int> w(m); w[0] = 1; for (int j = 1; j < m; ++j) w[j] = w[j - 1] * base % mod; for (int s = 0; s < n; s += m2) { for (int x = 0; x < (m); ++x) { int j = s + x; int d = a[j + m] * w[x] % mod; a[j + m] = a[j] - d; if (a[j + m] < 0) a[j + m] += mod; a[j] -= mod - d; if (a[j] < 0) a[j] += mod; } } } } void ntt(vector<int>& input) { _ntt(input, 1); } void intt(vector<int>& input) { _ntt(input, -1); const int n_inv = mod_inv((int)(input).size(), mod); for (auto& x : input) x = (long long int)x * n_inv % mod; } vector<int> convolution(const vector<int>& a, const vector<int>& b) { int ntt_size = 1; while (ntt_size < (int)(a).size() + (int)(b).size()) ntt_size *= 2; vector<int> _a = a, _b = b; _a.resize(ntt_size); _b.resize(ntt_size); ntt(_a); ntt(_b); for (int i = 0; i < (ntt_size); ++i) _a[i] = (long long int)_a[i] * _b[i] % mod; intt(_a); _a.resize((int)(a).size() + (int)(b).size()); return _a; } vector<int> square(const vector<int>& a) { int ntt_size = 1; while (ntt_size < (int)(a).size() * 2) ntt_size *= 2; vector<int> _a = a; _a.resize(ntt_size); ntt(_a); for (int i = 0; i < (ntt_size); ++i) _a[i] = (long long int)_a[i] * _a[i] % mod; intt(_a); _a.resize((int)(a).size() * 2); return _a; } }; const int P1 = 1811939329; const int P2 = 2013265921; const int P3 = 2113929217; const long long int P12 = (long long int)P1 * P2; const int IP1_2 = mod_inv(P1, P2); const int IP12_3 = mod_inv(P12, P3); const long long int P12_R = P12 % BS; const long long int P12_Q = P12 / BS; vector<int> _garner(vector<int>& x, vector<int>& y, vector<int>& z) { long long int c = 0; for (int i = 0; i < ((int)(x).size()); ++i) { y[i] = ((long long int)y[i] - x[i] + P2) * IP1_2 % P2; long long int s = x[i] + (long long int)y[i] * P1; z[i] = (z[i] - s % P3 + P3) * IP12_3 % P3; s += c + P12_R * z[i]; c = P12_Q * z[i] + s / BS; x[i] = s % BS; } return x; } bint bint::operator*(const bint& a) const { if ((int)(a).size() <= 10) return mult(a); NTT<P1, 13> ntt1; NTT<P2, 31> ntt2; NTT<P3, 5> ntt3; vector<int> x = ntt1.convolution(d, a.d); vector<int> y = ntt2.convolution(d, a.d); vector<int> z = ntt3.convolution(d, a.d); return bint(_garner(x, y, z), sg ^ a.sg).cut(); } bint bint::square() const { NTT<P1, 13> ntt1; NTT<P2, 31> ntt2; NTT<P3, 5> ntt3; vector<int> x = ntt1.square(d); vector<int> y = ntt2.square(d); vector<int> z = ntt3.square(d); return bint(_garner(x, y, z), false).cut(); } istream& operator>>(istream& i, bint& a) { string s; i >> s; a = bint(s); return i; } ostream& operator<<(ostream& o, const bint& a) { return o << a.str(); } long long int n; int cnt; int f(long long int i, long long int j) { i = n - i; j = n - j; cout << i << << j << endl; int res; cin >> res; ++cnt; return res; } bint area(pair<long long int, long long int> s, pair<long long int, long long int> t) { return bint(t.first - s.first) * (t.second - s.second); } int main() { cin >> n; pair<long long int, long long int> s(0, 0); pair<long long int, long long int> t(n, n); pair<long long int, long long int> x(0, 0); while (1) { bint a = (area(s, t) - area(s, x)) / 3 + 1; long long int i, j; { long long int l = x.first, r = t.first; while (l + 1 < r) { long long int c = (l + r) >> 1; if (area(pair<long long int, long long int>(c, s.second), t) < a) r = c; else l = c; } i = l; } { long long int l = x.second, r = t.second; while (l + 1 < r) { long long int c = (l + r) >> 1; if (area(pair<long long int, long long int>(s.first, c), t) < a) r = c; else l = c; } j = l; } int res = f(i, j); if (!res) break; if (res == 1) { t.first = i; } else if (res == 2) { t.second = j; } else { x = pair<long long int, long long int>(i + 1, j + 1); } if (x.first >= t.first) s.second = x.second, x = s; if (x.second >= t.second) s.first = x.first, x = s; } cerr << cnt << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a, b, n, i, j; int f[5001]; int dp[5001][5001]; char s[5003]; int main() { while (~scanf( %d%d%d , &n, &a, &b)) { scanf( %s , &s[1]); for (i = 1; i <= n; i++) f[i] = f[i - 1] + a; for (i = 1; i <= n; i++) { f[i] = min(f[i], f[i - 1] + a); for (j = 1; j < i; j++) { if (s[i] == s[j]) { dp[i][j] = dp[i - 1][j - 1] + 1; } else dp[i][j] = 0; if (j <= i - dp[i][j]) { f[i] = min(f[i], f[i - dp[i][j]] + b); } else { f[i] = min(f[i], f[j] + b); } } } printf( %d n , f[n]); } } |
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`include "functions.vh"
module offset_to_mask
#(parameter C_MASK_SWAP = 1,
parameter C_MASK_WIDTH = 4)
(
input OFFSET_ENABLE,
input [clog2s(C_MASK_WIDTH)-1:0] OFFSET,
output [C_MASK_WIDTH-1:0] MASK
);
reg [7:0] _rMask,_rMaskSwap;
wire [3:0] wSelect;
assign wSelect = {OFFSET_ENABLE,{{(3-clog2s(C_MASK_WIDTH)){1'b0}},OFFSET}};
assign MASK = (C_MASK_SWAP)? _rMaskSwap[7 -: C_MASK_WIDTH]: _rMask[C_MASK_WIDTH-1:0];
always @(*) begin
_rMask = 0;
_rMaskSwap = 0;
/* verilator lint_off CASEX */
casex(wSelect)
default: begin
_rMask = 8'b1111_1111;
_rMaskSwap = 8'b1111_1111;
end
4'b1000: begin
_rMask = 8'b0000_0001;
_rMaskSwap = 8'b1111_1111;
end
4'b1001: begin
_rMask = 8'b0000_0011;
_rMaskSwap = 8'b0111_1111;
end
4'b1010: begin
_rMask = 8'b0000_0111;
_rMaskSwap = 8'b0011_1111;
end
4'b1011: begin
_rMask = 8'b0000_1111;
_rMaskSwap = 8'b0001_1111;
end
4'b1100: begin
_rMask = 8'b0001_1111;
_rMaskSwap = 8'b0000_1111;
end
4'b1101: begin
_rMask = 8'b0011_1111;
_rMaskSwap = 8'b0000_0111;
end
4'b1110: begin
_rMask = 8'b0111_1111;
_rMaskSwap = 8'b0000_0011;
end
4'b1111: begin
_rMask = 8'b1111_1111;
_rMaskSwap = 8'b0000_0001;
end
endcase // casez ({OFFSET_MASK,OFFSET})
/* verilator lint_on CASEX */
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool comp(pair<long long, long long> &p1, pair<long long, long long> &p2) { if (p1.first == p2.first) { return p1.second < p2.second; } else { return p1.first < p2.first; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long a1, b1, a2, b2, a3, b3; map<pair<long long, long long>, long long> mp; cin >> a1 >> b1; cin >> a2 >> b2; cin >> a3 >> b3; vector<pair<long long, long long> > vect; vect.push_back({a1, b1}); vect.push_back({a2, b2}); vect.push_back({a3, b3}); sort(vect.begin(), vect.end(), comp); vector<pair<long long, long long> > vect1; for (long long i = vect[0].first; i <= vect[1].first; i++) { if (mp[{i, vect[0].second}] == 0) { mp[{i, vect[0].second}] = 1; vect1.push_back({i, vect[0].second}); } } if (vect[1].second > vect[0].second) { for (long long i = vect[0].second + 1; i <= vect[1].second; i++) { if (mp[{vect[1].first, i}] == 0) { mp[{vect[1].first, i}] = 1; vect1.push_back({vect[1].first, i}); } } } else if (vect[1].second < vect[0].second) { for (long long i = vect[0].second - 1; i >= vect[1].second; i--) { if (mp[{vect[1].first, i}] == 0) { mp[{vect[1].first, i}] = 1; vect1.push_back({vect[1].first, i}); } } } long long h1 = vect[0].second; long long h2 = vect[1].second; if (h2 >= h1) { if (vect[2].second >= h1 and vect[2].second <= h2) { for (long long i = vect[1].first + 1; i <= vect[2].first; i++) { if (mp[{i, vect[2].second}] == 0) { mp[{i, vect[2].second}] = 1; vect1.push_back({i, vect[2].second}); } } } else if (vect[2].second > h2) { for (long long i = vect[1].first + 1; i <= vect[2].first; i++) { if (mp[{i, vect[1].second}] == 0) { mp[{i, vect[1].second}] = 1; vect1.push_back({i, vect[1].second}); } } for (long long i = h2 + 1; i <= vect[2].second; i++) { if (mp[{vect[2].first, i}] == 0) { mp[{vect[2].first, i}] = 1; vect1.push_back({vect[2].first, i}); } } } else if (vect[2].second < h1) { for (long long i = vect[1].first + 1; i <= vect[2].first; i++) { if (mp[{i, vect[0].second}] == 0) { mp[{i, vect[0].second}] = 1; vect1.push_back({i, vect[0].second}); } } for (long long i = h1 - 1; i >= vect[2].second; i--) { if (mp[{vect[2].first, i}] == 0) { mp[{vect[2].first, i}] = 1; vect1.push_back({vect[2].first, i}); } } } } else { if (vect[2].second >= h2 and vect[2].second <= h1) { for (long long i = vect[1].first + 1; i <= vect[2].first; i++) { if (mp[{i, vect[2].second}] == 0) { mp[{i, vect[2].second}] = 1; vect1.push_back({i, vect[2].second}); } } } else if (vect[2].second > h1) { for (long long i = vect[1].first + 1; i <= vect[2].first; i++) { if (mp[{i, vect[0].second}] == 0) { mp[{i, vect[0].second}] = 1; vect1.push_back({i, vect[0].second}); } } for (long long i = h1 + 1; i <= vect[2].second; i++) { if (mp[{vect[2].first, i}] == 0) { mp[{vect[2].first, i}] = 1; vect1.push_back({vect[2].first, i}); } } } else if (vect[2].second < h2) { for (long long i = vect[1].first + 1; i <= vect[2].first; i++) { if (mp[{i, vect[1].second}] == 0) { mp[{i, vect[1].second}] = 1; vect1.push_back({i, vect[1].second}); } } for (long long i = h2 - 1; i >= vect[2].second; i--) { if (mp[{vect[2].first, i}] == 0) { mp[{vect[2].first, i}] = 1; vect1.push_back({vect[2].first, i}); } } } } cout << vect1.size() << n ; for (long long i = 0; i < vect1.size(); i++) { cout << vect1[i].first << << vect1[i].second << n ; } return 0; } |
# include <bits/stdc++.h> using namespace std; const int N=1e3+10; int n,m,a[N][N],sum1[N],sum2[N],c1[N],c2[N],c3[N]; map<int,int>mp,tt; signed main() { scanf( %d%d ,&n,&m); for (int i=1;i<=m;i++) for (int j=1;j<=n;j++) { scanf( %d ,&a[i][j]); sum1[i]+=a[i][j]; sum2[i]+=a[i][j]*a[i][j]; } for (int i=1;i<=m;i++) { c1[i]=sum1[i]-sum1[i-1]; c2[i]=sum2[i]-sum2[i-1]; if (i>1) mp[c1[i]]++,tt[c1[i]]=i; } int id=m; for (map<int,int>::iterator it=mp.begin();it!=mp.end();it++) { if ((it->second)==1) id=min(id,tt[it->first]); } for (int i=1;i<=m;i++) c3[i]=c2[i]-c2[i-1]; int res; if (id>=4) res=c3[3]; else res=c3[7]; if (id!=2) { for (int i=3;i<=m;i++) c3[i]=res; for (int i=1;i<=m;i++) c3[i]=c3[i-1]+c3[i]; for (int i=1;i<=m;i++) c3[i]=c3[i-1]+c3[i]; } else { int d=sum2[m]-sum2[m-1]-sum2[m-1]+sum2[m-2]; c3[m]=sum2[m]-sum2[m-1]; for (int i=m-1;i>=2;i--) c3[i]=c3[i+1]-d; for (int i=1;i<=m;i++) c3[i]=c3[i-1]+c3[i]; } if (id>=4) res=c1[3]; else res=c1[7]; if (id!=2) { for (int i=3;i<=m;i++) c1[i]=res; for (int i=1;i<=m;i++) c1[i]=c1[i-1]+c1[i]; } else { int d=sum1[m]-sum1[m-1]-sum1[m-1]+sum1[m-2]; c1[m]=sum1[m]-sum1[m-1]; for (int i=m-1;i>=2;i--) c1[i]=c1[i+1]-d; for (int i=1;i<=m;i++) c1[i]=c1[i-1]+c1[i]; } int ans1=id-1,ans2; for (int i=1;i<=n;i++) { int t=c1[id]-(sum1[id]-a[id][i]); if (t*t+sum2[id]-a[id][i]*a[id][i]==c3[id]) { ans2=t; break; } } printf( %d %d n ,ans1,ans2); fflush(stdout); return 0; } /* by maystern */ |
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.1 Date: 14- 4-2017
Version: 1.0 Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_acc(
input rst,
input clk,
input m1_enters,
input m2_enters,
input c1_enters,
input c2_enters,
input op31_acc,
input [1:0] rl_I,
input [2:0] con_I,
input signed [13:0] op_out,
input ne, // noise enable
input signed [10:0] noise,
output signed [15:0] left,
output signed [15:0] right,
output reg signed [15:0] xleft, // exact outputs
output reg signed [15:0] xright
);
reg signed [13:0] op_val;
always @(*) begin
if( ne && op31_acc ) // cambiar a OP 31
op_val = { {2{noise[10]}}, noise, 1'd0 };
else
op_val = op_out;
end
reg sum_en;
always @(*) begin
case ( con_I )
3'd0,3'd1,3'd2,3'd3: sum_en = m2_enters;
3'd4: sum_en = m1_enters | m2_enters;
3'd5,3'd6: sum_en = ~c1_enters;
3'd7: sum_en = 1'b1;
default: sum_en = 1'bx;
endcase
end
wire ren = rl_I[1];
wire len = rl_I[0];
reg signed [15:0] pre_left, pre_right;
wire signed [15:0] total;
reg sum_all;
wire rst_sum = c2_enters;
//wire rst_sum = c1_enters;
//wire rst_sum = m1_enters;
//wire rst_sum = m2_enters;
always @(posedge clk) begin
if( rst ) begin
sum_all <= 1'b0;
end
else begin
if( rst_sum ) begin
sum_all <= 1'b1;
if( !sum_all ) begin
pre_right <= ren ? total : 16'd0;
pre_left <= len ? total : 16'd0;
end
else begin
pre_right <= pre_right + (ren ? total : 16'd0);
pre_left <= pre_left + (len ? total : 16'd0);
end
end
if( c1_enters ) begin
sum_all <= 1'b0;
xleft <= pre_left;
xright <= pre_right;
end
end
end
reg signed [15:0] opsum;
wire signed [16:0] opsum10 = op_val+total;
always @(*) begin
if( rst_sum )
opsum = sum_en ? { {2{op_val[13]}}, op_val } : 16'd0;
else begin
if( sum_en )
if( opsum10[16]==opsum10[15] )
opsum = opsum10[15:0];
else begin
opsum = opsum10[16] ? 16'h8000 : 16'h7fff;
end
else
opsum = total;
end
end
jt51_sh #(.width(16),.stages(8)) u_acc(
.clk ( clk ),
.din ( opsum ),
.drop ( total )
);
wire signed [9:0] left_man, right_man;
wire [2:0] left_exp, right_exp;
jt51_exp2lin left_reconstruct(
.lin( left ),
.man( left_man ),
.exp( left_exp )
);
jt51_exp2lin right_reconstruct(
.lin( right ),
.man( right_man ),
.exp( right_exp )
);
jt51_lin2exp left2exp(
.lin( xleft ),
.man( left_man ),
.exp( left_exp ) );
jt51_lin2exp right2exp(
.lin( xright ),
.man( right_man ),
.exp( right_exp ) );
`ifdef DUMPLEFT
reg skip;
wire signed [15:0] dump = left;
initial skip=1;
always @(posedge clk)
if( c1_enters && (!skip || dump) ) begin
$display("%d", dump );
skip <= 0;
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int w, h; cin >> w >> h; int u1, d1, u2, d2; cin >> u1 >> d1 >> u2 >> d2; for (int i = h; i >= 0; i--) { w = w + i; if (i == d1 || i == d2) { if (i == d1) { w = w - u1; if (w < 0) { w = 0; } } else { w = w - u2; if (w < 0) { w = 0; } } } } cout << w << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int tree[N << 2], Max[N << 2], Min[N << 2], cnt; bool fu[N << 2]; pair<int, int> a[N]; void build(int l, int r, int rt) { if (l == r) { tree[rt] = a[l].first; Max[rt] = Min[rt] = tree[rt]; return; } int m = (l + r) >> 1; build(l, m, rt << 1); build(m + 1, r, rt << 1 | 1); Max[rt] = max(Max[rt << 1], Max[rt << 1 | 1]); Min[rt] = min(Min[rt << 1], Min[rt << 1 | 1]); } bool qu(int f, int x, int rt) { int ma, mi; ma = Max[rt], mi = Min[rt]; if ((f == > && mi > x) || (f == < && ma < x)) return true; else return false; } bool qu2(int f, int x, int rt) { int ma, mi; ma = Max[rt], mi = Min[rt]; if ((f == > && ma > x) || (f == < && mi < x)) return true; else return false; } void ff(int rt) { fu[rt] = !fu[rt]; swap(Max[rt], Min[rt]); Max[rt] *= -1; Min[rt] *= -1; } void updata(int l, int r, int rt, char f, int x) { if (qu(f, x, rt)) { ff(rt); return; } int m = (l + r) >> 1; if (fu[rt]) ff(rt << 1), ff(rt << 1 | 1), fu[rt] = 0; if (qu2(f, x, rt << 1)) updata(l, m, rt << 1, f, x); if (qu2(f, x, rt << 1 | 1)) updata(m + 1, r, rt << 1 | 1, f, x); Max[rt] = max(Max[rt << 1], Max[rt << 1 | 1]); Min[rt] = min(Min[rt << 1], Min[rt << 1 | 1]); } int ans[N]; void print(int l, int r, int rt) { if (l == r) { if (fu[rt]) tree[rt] *= -1; ans[a[l].second] = tree[rt]; return; } int m = (l + r) >> 1; if (fu[rt]) ff(rt << 1), ff(rt << 1 | 1), fu[rt] = 0; print(l, m, rt << 1); print(m + 1, r, rt << 1 | 1); } int main() { int n, q; cin >> n >> q; for (int i = 1; i <= n; i++) cin >> a[i].first, a[i].second = i; sort(a + 1, a + n + 1); build(1, n, 1); while (q--) { char f; int x; cin >> f >> x; updata(1, n, 1, f, x); } print(1, n, 1); for (int i = 1; i <= n; i++) printf( %d , ans[i]); printf( n ); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, a[200005], sum; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i], sum ^= a[i]; if (n % 2 == 0) { if (sum) { puts( NO ); return 0; } n--; } puts( YES ); printf( %d n , n - 1); for (int i = 1; i <= n - 2; i += 2) printf( %d %d %d n , i, i + 1, i + 2); for (int i = 1; i <= n - 2; i += 2) printf( %d %d %d n , i, i + 1, n); } |
#include <bits/stdc++.h> using namespace std; void fastio() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); } int main() { fastio(); long long int a, b; long long int mx = INT_MIN; long long int n, mn = INT_MAX; cin >> n; long long int ar[n]; for (int i = 0; i < n; i++) { cin >> ar[i]; mn = min(mn, ar[i]); mx = max(ar[i], mx); } long long int res = mx - mn + 1; cout << res - n; return 0; } |
#include <bits/stdc++.h> template <typename T> T sqr(T x) { return x * x; } template <typename T> bool exmax(T &a, T b) { return (b > a) ? (a = b) || 1 : 0; } template <typename T> bool exmin(T &a, T b) { return (b < a) ? (a = b) || 1 : 0; } using namespace std; int a[510], b[510], l; void print() { for (int i = l - 1; i >= 0; i--) cout << a[i]; cout << endl; } int getsum(int s, int t) { int ret = 0; for (int i = s; i < t; i++) ret += b[i]; return ret; } int main() { memset(a, 0x00, sizeof(a)); int n; cin >> n; n--; int m; cin >> m; l = 0; int t = m; while (m) { if (m > 9) a[l++] = 9, m -= 9; else a[l++] = m, m = 0; } print(); while (n--) { cin >> m; if (t < m) { for (int i = 0, j = m - t; j; i++) { if (j > 9 - a[i]) j -= 9 - a[i], a[i] = 9; else a[i] += j, j = 0; exmax(l, i + 1); } t = m; } else { t = m; for (int i = 0; true; i++) { memcpy(b, a, sizeof(a)); b[i]++; while (b[i] > 9) b[i] = 0, b[++i] += 1; for (int j = 0; j < i; j++) b[j] = 0; exmax(l, i + 1); int s = getsum(i, l); if (s > m) continue; if (i * 9 < m - s) continue; int k = 0; m -= s; while (m) { if (m > 9) b[k++] = 9, m -= 9; else b[k++] = m, m = 0; } break; } memcpy(a, b, sizeof(a)); } print(); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BOI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A21BOI_BLACKBOX_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21boi (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BOI_BLACKBOX_V
|
// Fast Multisource Pulse Registration System
// Module:
// Flexible, 3-fifo multidirectional FX2 USB-2 interface
// (c) Ben Gamari (2010)
module reg_manager(
clk,
cmd_wr, cmd_in,
reply_out, reply_rdy, reply_ack, reply_end,
reg_addr, reg_data, reg_wr
);
// fx2bidir interface
input clk;
input cmd_wr;
input [7:0] cmd_in;
output [7:0] reply_out;
output reply_rdy;
input reply_ack;
output reply_end;
// Internal interface
output [15:0] reg_addr;
inout [31:0] reg_data;
output reg_wr;
reg [15:0] addr;
reg [31:0] data;
reg [4:0] state;
reg wants_wr;
initial state = 0;
always @(posedge clk)
case (state)
0: if (cmd_wr && cmd_in == 8'hAA) // Read magic number
state <= 1;
1: if (cmd_wr) // Read message type (read/write)
begin
wants_wr <= cmd_in[0];
state <= 2;
end
// Read address
2: if (cmd_wr) // 1st byte
begin
addr[7:0] <= cmd_in;
state <= 3;
end
3: if (cmd_wr) // 2nd byte
begin
addr[15:8] <= cmd_in;
state <= 4;
end
// Read value
4: if (cmd_wr) // 1st byte
begin
data[7:0] <= cmd_in;
state <= 5;
end
5: if (cmd_wr) // 2nd byte
begin
data[15:8] <= cmd_in;
state <= 6;
end
6: if (cmd_wr) // 3rd byte
begin
data[23:16] <= cmd_in;
state <= 7;
end
7: if (cmd_wr) // 4th byte
begin
data[31:24] <= cmd_in;
state <= 8;
end
// Write new value to register (if needed)
8: state <= 9;
// Write reply to host
9: if (reply_ack) // 1st byte
state <= 10;
10: if (reply_ack) // 2nd byte
state <= 11;
11: if (reply_ack) // 3rd byte
state <= 12;
12: if (reply_ack) // 4th byte
state <= 0;
default:
state <= 0;
endcase
assign reg_addr = (state==8 || state==9 || state==10 || state==11 || state==12) ? addr : 16'hXX;
assign reg_data = (state==8) ? data : 32'hZZ;
assign reg_wr = (state==8) && wants_wr;
assign reply_out = (state==9) ? reg_data[7:0] :
(state==10) ? reg_data[15:8] :
(state==11) ? reg_data[23:16] :
(state==12) ? reg_data[31:24] : 8'hZZ;
assign reply_rdy = state==9 || state==10 || state==11 || state==12;
assign reply_end = state==12;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off LITENDIAN
// verilator lint_off BLKANDNBLK
// 3 3 4
reg [71:0] memw [2:0][1:3][5:2];
reg [7:0] memn [2:0][1:3][5:2];
// verilator lint_on BLKANDNBLK
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [71:0] wide;
reg [7:0] narrow;
reg [1:0] index0;
reg [1:0] index1;
reg [2:0] index2;
integer i0,i1,i2;
integer imem[2:0][1:3];
reg [2:0] cstyle[2];
// verilator lint_on LITENDIAN
initial begin
for (i0=0; i0<3; i0=i0+1) begin
for (i1=1; i1<4; i1=i1+1) begin
imem[i0[1:0]] [i1[1:0]] = i1;
for (i2=2; i2<6; i2=i2+1) begin
memw[i0[1:0]] [i1[1:0]] [i2[2:0]] = {56'hfe_fee0_fee0_fee0_,4'b0,i0[3:0],i1[3:0],i2[3:0]};
memn[i0[1:0]] [i1[1:0]] [i2[2:0]] = 8'b1000_0001;
end
end
end
end
reg [71:0] wread;
reg wreadb;
always @ (posedge clk) begin
//$write("cyc==%0d crc=%x i[%d][%d][%d] nar=%x wide=%x\n",cyc, crc, index0,index1,index2, narrow, wide);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
narrow <= 8'h0;
wide <= 72'h0;
index0 <= 2'b0;
index1 <= 2'b0;
index2 <= 3'b0;
end
else if (cyc<90) begin
index0 <= crc[1:0];
index1 <= crc[3:2];
index2 <= crc[6:4];
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
// We never read past bounds, or get unspecific results
// We also never read lowest indexes, as writing outside of range may corrupt them
if (index0>=0+1 && index0<=2 && index1>=1+1 /*&& index1<=3 CMPCONST*/ && index2>=2+1 && index2<=5) begin
narrow <= ({narrow[6:0], narrow[7]^narrow[0]}
^ {memn[index0][index1][index2]});
wread = memw[index0][index1][index2];
wreadb = memw[index0][index1][index2][2];
wide <= ({wide[70:0], wide[71]^wide[2]^wide[0]} ^ wread);
//$write("Get memw[%d][%d][%d] -> %x\n",index0,index1,index2, wread);
end
// We may write past bounds of memory
memn[index0][index1][index2] [crc[10:8]+:3] <= crc[2:0];
memn[index0][index1][index2] <= {~crc[6:0],crc[7]};
memw[index0][index1][index2] <= {~crc[7:0],crc};
//$write("Set memw[%d][%d][%d] <= %x\n",index0,index1,index2, {~crc[7:0],crc});
cstyle[cyc[0]] <= cyc[2:0];
if (cyc>20) if (cstyle[~cyc[0]] != (cyc[2:0]-3'b1)) $stop;
end
else if (cyc==90) begin
memn[0][1][3] <= memn[0][1][3] ^ 8'ha8;
end
else if (cyc==91) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x nar=%x wide=%x\n",$time, cyc, crc, narrow, wide);
if (crc != 64'h65e3bddcd9bc2750) $stop;
if (narrow != 8'hca) $stop;
if (wide != 72'h4edafed31ba6873f73) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/* Author: Sanskar Agarwal Nick: sanskaragarwal Birla Institute Of Technology, Mesra */ #include <bits/stdc++.h> using namespace std; #define ll long long int #define endl n #define fast ios::sync_with_stdio(0);cin.tie(0);cout.tie(0); #define F(i,a,b) for(ll i = (ll)(a); i <= (ll)(b); i++) #define RF(i,a,b) for(ll i = (ll)(a); i >= (ll)(b); i--) #define INF 100009 #define mod 1000000007 #define pb(x) push_back(x) #define mp(x,y) make_pair(x,y) #define ff first #define ss second #define test while(t--)solve(); void solve() { int n; cin >> n; int pos[32]; int arr[n]; memset(pos, 0, sizeof(pos)); int xo = 0; int pre[n]; for (int i = 0; i < n; ++i) { cin >> arr[i]; xo ^= arr[i]; pre[i] = xo; } bool flag = !xo; for (int i = 0; i < n; ++i) { for (int j = i + 1; j < n; ++j) { int sp1 = pre[i]; int sp2 = pre[j] ^ pre[i]; int sp3 = pre[n - 1] ^ pre[j]; flag |= (sp1 == sp2 && sp2 == sp3); } } if (flag) cout << YES << endl; else cout << NO << endl; } int main() { #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif fast int t; // t = 1; cin >> t; test; #ifndef ONLINE_JUDGE cout << nTime Elapsed : << 1.0 * clock() / CLOCKS_PER_SEC << s n ; #endif return 0; } |
#include <bits/stdc++.h> using namespace std; char b[1000050], a[1000050]; int n, m, p, P; bool c[2050], ans[2050], Ans; bool Calc(int x, int y, int z, int o, int u) { for (; o >= z; o--) { bool Flag = false; while (y >= x) { bool flag = true; for (int j = y, k = o; j <= n && k <= m; j += p, k += u) if (a[j] != b[k] || ((j + p > n) ^ (k + u > m))) { flag = false; break; } if (flag) { c[y] = 1; y--; Flag = true; break; } y--; } if (!Flag) return false; } return true; } void Put() { for (int i = 1; i <= P; i++) putchar(ans[i] ? 1 : 0 ); puts( ); } void PUUUUUT() { if (Ans) for (int i = 1; i <= p; i++) if (ans[i] && !c[i]) break; else if (!ans[i] && c[i]) return; for (int i = 1; i <= p; i++) ans[i] = c[i]; Ans = true; } void Solve() { int k = n / p, l = n % p; for (int i = 0; i <= l; i++) if ((m - i) % k == 0 && (m - i) / k - i <= p - l) { if (Calc(1, l, 1, i, (m - i) / k) && Calc(l + 1, p, i + 1, (m - i) / k, (m - i) / k)) PUUUUUT(); memset(c, 0, sizeof(c)); } return; } int main() { gets(a + 1); gets(b + 1); scanf( %d , &P); n = strlen(a + 1); m = strlen(b + 1); p = min(P, n); Solve(); if (!Ans) puts( 0 ); else Put(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__AND2B_FUNCTIONAL_V
`define SKY130_FD_SC_MS__AND2B_FUNCTIONAL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__and2b (
X ,
A_N,
B
);
// Module ports
output X ;
input A_N;
input B ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__AND2B_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; bool prime(long long n) { for (long long i = 2; i * i <= n; i++) { if (n % i == 0) return false; } return true; } int main() { long long n, ans; cin >> n; if (prime(n)) ans = 1; else if (n % 2 == 0) ans = 2; else if (prime(n - 2)) ans = 2; else ans = 3; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> long long int add(long long int a, long long int b) { return a + b - (a + b >= 1000000007) * 1000000007; } long long int sub(long long int a, long long int b) { return a - b + (a - b < 0) * 1000000007; } long long int mult(long long int a, long long int b) { return (1LL * a * b) % 1000000007; } inline long long int gcd(long long int a, long long int b) { long long int t; while (b) { a = a % b; t = a; a = b; b = t; } return a; } long long int powmod(long long int a, long long int b) { long long int res = 1; a %= 1000000007; assert(b >= 0); for (; b; b >>= 1) { if (b & 1) res = res * a % 1000000007; a = a * a % 1000000007; } return res; } using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); long long int k; cin >> k; long long int q = (1000000007 - 1) / 2; long long int d = 2; for (long long int i = 0; i < k; i++) { long long int x; cin >> x; q = powmod(q, x); d = powmod(d, x); } d = d * powmod(2, 1000000007 - 2) % 1000000007; q = (q * 2 + 1) % 1000000007 * powmod(3, 1000000007 - 2) % 1000000007; long long int p = q * d % 1000000007; cout << p << / << d; } |
#include <bits/stdc++.h> const int maxn = 3e5 + 7; int ch[maxn << 5][2], max[maxn << 5], n, q, k, l[maxn], r[maxn], id[maxn], rk[maxn], a, b, x, y, tl, rt[maxn]; int cmp(int x, int y) { return r[x] < r[y]; } int insert(int rt, int L, int R, int p, int v) { int nrt = ++tl; ch[nrt][0] = ch[rt][0]; ch[nrt][1] = ch[rt][1]; max[nrt] = max[rt]; if (L == R) { max[nrt] = std::max(max[nrt], v); return nrt; } int mid = (L + R) >> 1; if (p <= mid) ch[nrt][0] = insert(ch[rt][0], L, mid, p, v); else ch[nrt][1] = insert(ch[rt][1], mid + 1, R, p, v); max[nrt] = std::min(max[ch[nrt][0]], max[ch[nrt][1]]); return nrt; } int query(int rt, int l, int r, int L, int R) { if (l > R || r < L) return 1e9; if (l <= L && R <= r) return max[rt]; return std::min(query(ch[rt][0], l, r, L, (L + R) >> 1), query(ch[rt][1], l, r, ((L + R) >> 1) + 1, R)); } int main() { scanf( %d%d%d , &n, &q, &k); for (int i = 1; i <= k; ++i) { scanf( %d%d%d , &l[i], &r[i], &id[i]); rk[i] = i; } std::sort(rk + 1, rk + k + 1, cmp); for (int i = 1; i <= k; ++i) { rt[i] = insert(rt[i - 1], 1, n, id[rk[i]], l[rk[i]]); } while (q--) { scanf( %d%d%d%d , &a, &b, &x, &y); int L = 0, R = k, p; while (L <= R) { int mid = (L + R) >> 1; if (r[rk[mid]] <= y) { p = mid; L = mid + 1; } else R = mid - 1; } if (query(rt[p], a, b, 1, n) >= x) puts( yes ); else puts( no ); fflush(stdout); } return 0; } |
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