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#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; vector<vector<long long>> mul(vector<vector<long long>> A, vector<vector<long long>> B) { int n = A.size(); vector<vector<long long>> res(n, vector<long long>(n)); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { for (int k = 0; k < n; k++) { res[i][j] = (res[i][j] + A[i][k] * B[k][j]) % MOD; } } } return res; } vector<vector<long long>> mexp(vector<vector<long long>> M, long long e) { if (e == 1) return M; if (e % 2) return mul(M, mexp(M, e - 1)); vector<vector<long long>> R = mexp(M, e / 2); return mul(R, R); } int main() { long long n, m; cin >> n >> m; if (m > n) { cout << 1 << endl; return 0; } vector<vector<long long>> M(m, vector<long long>(m)); M[0][0] = M[0][m - 1] = 1; for (int i = 1; i < m; i++) M[i][i - 1] = 1; vector<vector<long long>> R = mexp(M, n - m + 1); long long res = 0; for (int i = 0; i < m; i++) res = (res + R[0][i]) % MOD; cout << res << endl; } |
#include <bits/stdc++.h> using namespace std; int cnt[1000000 + 1]; const int mod = 1e9 + 7; vector<int> v; void solve() { int n; cin >> n; int a[n]; for (int i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); int mx = a[n - 1]; deque<int> dq; int i = n - 1; for (i = n - 1; i >= 0; i--) { if (a[i] == mx) { dq.push_back(a[i]); } else break; } bool turn = true; for (i; i >= 0; i--) { if (turn == true) { dq.push_back(a[i]); turn = false; } else { dq.push_front(a[i]); turn = true; } } for (auto i : dq) cout << i << ; cout << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int t; t = 1; while (t--) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1010; const double oo = 1E7, eps = 1E-7; struct point { double x, y; } P[maxn]; int n; double ansl, ansr; point operator+(point a, point b) { return (point){a.x + b.x, a.y + b.y}; } point operator-(point a, point b) { return (point){a.x - b.x, a.y - b.y}; } double operator*(point a, point b) { return a.x * b.x + a.y * b.y; } double operator/(point a, point b) { return a.x * b.y - b.x * a.y; } double get(point A, point B) { double a, b, c, res; a = A.y - B.y; b = B.x - A.x; c = A / B; if (a) res = (-c - b * P[1].y) / a; else res = oo; return res; } int main() { int i, j; double x, sita; scanf( %d , &n); scanf( %lf%lf , &P[n].x, &P[n].y); for (i = 1; i < n; ++i) scanf( %lf%lf , &P[i].x, &P[i].y); ansl = min(P[1].x, P[n].x), ansr = max(P[1].x, P[n].x); for (i = 2; i < n; ++i) { j = i + 1; x = get(P[i], P[j]); sita = (P[1].y - P[i].y) * (P[j].x - P[i].x); if (sita > (P[j].y - P[i].y) * (ansl - P[i].x)) ansl = max(ansl, x); if (sita > (P[j].y - P[i].y) * (ansr - P[i].x)) ansr = min(ansr, x); } if (ansr >= ansl) printf( %.0lf , floor(ansr) - floor(ansl - eps)); else printf( 0 ); return 0; } |
#include <bits/stdc++.h> using namespace std; long long K, B, N, T; int main() { cin >> K >> B >> N >> T; if (K == 1 && 1 + N * B >= T) { cout << (int)ceil((1 + N * B - T) / (1.0 * B)) << endl; return 0; } if (K == 1) { cout << 0 << endl; return 0; } long long C = 1, counter = N + 1; double thres = 1.0 * (T * (K - 1) + B) / (K - 1 + B); for (int i = 1; i <= N; i++) { C *= K; if (C > thres) { counter = i; break; } } counter--; cout << N - counter << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XNOR3_PP_SYMBOL_V
`define SKY130_FD_SC_HD__XNOR3_PP_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xnor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XNOR3_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int a[] = {1, 2, 4, 3}; int b[] = {1, 3, 4, 2}; int c[] = {1, 4, 1, 4}; int d[] = {1, 1, 1, 1}; int main() { string s; cin >> s; int n = s.length(); int rem = 0; for (int i = 0; i < n; i++) { rem = (rem * 10 + s[i] - 0 ) % 4; } int ans = a[rem] + b[rem] + c[rem] + d[rem]; ans %= 5; cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; const int size = 1e5 + 10; int afx[size]; int dis[size]; int main() { int n, k; scanf( %d%d , &n, &k); int total = 0; int ans = 0; for (int i = 0; i < n; i++) { scanf( %d , afx + i); dis[i] = 10 - afx[i] % 10; total += dis[i]; ans += afx[i] / 10; } if (k <= total) { sort(dis, dis + n); int i = 0; while (k && i < n) { k -= dis[i]; if (k < 0) break; ans++; i++; } printf( %d n , min(10 * n, ans)); return 0; } k -= total; ans += n; ans += k / 10; printf( %d n , min(10 * n, ans)); return 0; } |
`default_nettype none
`timescale 1ns/1ns
module tb_mist1032isa_normal_test;
localparam PL_CORE_CYCLE = 20;
localparam PL_BUS_CYCLE = 20;
localparam PL_DPS_CYCLE = 18;
localparam PL_RESET_TIME = 20;
/****************************************
System
****************************************/
reg iCORE_CLOCK;
reg iBUS_CLOCK;
reg iDPS_CLOCK;
reg inRESET;
/****************************************
SCI
****************************************/
wire oSCI_TXD;
reg iSCI_RXD;
/****************************************
Memory BUS
****************************************/
//Req
wire oMEMORY_REQ;
reg iMEMORY_LOCK;
wire [1:0] oMEMORY_ORDER; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
wire oMEMORY_RW; //1:Write | 0:Read
wire [31:0] oMEMORY_ADDR;
//This -> Data RAM
wire [31:0] oMEMORY_DATA;
//Data RAM -> This
reg iMEMORY_VALID;
wire oMEMORY_BUSY;
reg [63:0] iMEMORY_DATA;
/****************************************
GCI BUS
****************************************/
//Request
wire oGCI_REQ; //Input
reg iGCI_BUSY;
wire oGCI_RW; //0=Read : 1=Write
wire [31:0] oGCI_ADDR;
wire [31:0] oGCI_DATA;
//Return
reg iGCI_REQ; //Output
wire oGCI_BUSY;
reg [31:0] iGCI_DATA;
//Interrupt
reg iGCI_IRQ_REQ;
reg [5:0] iGCI_IRQ_NUM;
wire oGCI_IRQ_ACK;
//Interrupt Controll
wire oIO_IRQ_CONFIG_TABLE_REQ;
wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY;
wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK;
wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID;
wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL;
wire [31:0] oDEBUG_PC;
wire [31:0] oDEBUG0;
/****************************************
Debug
****************************************/
reg iDEBUG_UART_RXD;
wire oDEBUG_UART_TXD;
reg iDEBUG_PARA_REQ;
wire oDEBUG_PARA_BUSY;
reg [7:0] iDEBUG_PARA_CMD;
reg [31:0] iDEBUG_PARA_DATA;
wire oDEBUG_PARA_VALID;
reg iDEBUG_PARA_BUSY;
wire oDEBUG_PARA_ERROR;
wire [31:0] oDEBUG_PARA_DATA;
/******************************************************
Target
******************************************************/
module mist1032isa(
/****************************************
System
****************************************/
.iCORE_CLOCK(iCORE_CLOCK),
.iBUS_CLOCK(),
.iDPS_CLOCK(),
.inRESET(),
/****************************************
SCI
****************************************/
.oSCI_TXD(),
.iSCI_RXD(),
/****************************************
Memory BUS
****************************************/
//Req
.oMEMORY_REQ(),
.iMEMORY_LOCK(),
.oMEMORY_ORDER(), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oMEMORY_RW(), //1:Write | 0:Read
.oMEMORY_ADDR(),
//This -> Data RAM
.oMEMORY_DATA(),
//Data RAM -> This
.iMEMORY_VALID(),
.oMEMORY_BUSY(),
.iMEMORY_DATA(),
/****************************************
GCI BUS
****************************************/
//Request
.oGCI_REQ(), //Input
.iGCI_BUSY(),
.oGCI_RW(), //0=Read : 1=Write
.oGCI_ADDR(),
.oGCI_DATA(),
//Return
.iGCI_REQ(), //Output
.oGCI_BUSY(),
.iGCI_DATA(),
//Interrupt
.iGCI_IRQ_REQ(),
.iGCI_IRQ_NUM(),
.oGCI_IRQ_ACK(),
//Interrupt Controll
.oIO_IRQ_CONFIG_TABLE_REQ(),
.oIO_IRQ_CONFIG_TABLE_ENTRY(),
.oIO_IRQ_CONFIG_TABLE_FLAG_MASK(),
.oIO_IRQ_CONFIG_TABLE_FLAG_VALID(),
.oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL(),
.oDEBUG_PC(),
.oDEBUG0(),
/****************************************
Debug
****************************************/
.iDEBUG_UART_RXD(),
.oDEBUG_UART_TXD(),
.iDEBUG_PARA_REQ(),
.oDEBUG_PARA_BUSY(),
.iDEBUG_PARA_CMD(),
.iDEBUG_PARA_DATA(),
.oDEBUG_PARA_VALID(),
.iDEBUG_PARA_BUSY(),
.oDEBUG_PARA_ERROR(),
.oDEBUG_PARA_DATA()
);
/******************************************************
Clock
******************************************************/
always#(PL_CORE_CYCLE/2)begin
iCORE_CLOCK = !iCORE_CLOCK;
end
always#(PL_BUS_CYCLE/2)begin
iBUS_CLOCK = !iBUS_CLOCK;
end
always#(PL_DPS_CYCLE/2)begin
iDPS_CLOCK = !iDPS_CLOCK;
end
/******************************************************
State
******************************************************/
initial begin
//Initial
iCORE_CLOCK = 1'b0;
iBUS_CLOCK = 1'b0;
iDPS_CLOCK = 1'b0;
inRESET = 1'b0;
iSCI_RXD = 1'b1;
//iMEMORY_LOCK =
//iMEMORY_VALID =
//iMEMORY_DATA =
iGCI_BUSY = 1'b0;
iGCI_REQ = 1'b0;
iGCI_DATA = 32'h0;
iGCI_IRQ_REQ = 1'b0;
iGCI_IRQ_NUM = 6'h0;
iDEBUG_UART_RXD = 1'b1;
iDEBUG_PARA_REQ = 1'b0;
iDEBUG_PARA_CMD = 8'h0;
iDEBUG_PARA_DATA = 32'h0;
iDEBUG_PARA_BUSY = 1'b0;
//Reset After
#(PL_RESET_TIME);
inRESET = 1'b1;
`default_nettype wire
|
`timescale 1ns / 1ps
module ADD #(parameter N = 8, M = N)( // N >= M
input [N-1:0] A,
input [M-1:0] B,
input CI,
output CO,
output [N-1:0] S
);
wire [N-1:0] BB;
generate
if (N > M) begin: FA_IF
assign BB = {{(N-M){1'b0}}, B};
end else begin: FA_IF_N
assign BB = B;
end
endgenerate
wire C[N:0];
assign C[0] = CI;
assign CO = C[N];
genvar g;
genvar h;
localparam MAX_LOOP = 512;
generate
if(N < MAX_LOOP) begin : FA_IF2
for(g=0;g<N;g=g+1) begin: FAINST
FA FA_ (
.A(A[g]),
.B(BB[g]),
.CI(C[g]),
.S(S[g]),
.CO(C[g+1])
);
end
end else begin: FA_IF2_N
for(h=0;h<N/MAX_LOOP;h=h+1) begin: FA_INST_0
for(g=0;g<MAX_LOOP;g=g+1) begin: FA_INST_1
FA FA_ (
.A(A[h*MAX_LOOP + g]),
.B(BB[h*MAX_LOOP + g]),
.CI(C[h*MAX_LOOP + g]),
.S(S[h*MAX_LOOP + g]),
.CO(C[h*MAX_LOOP + g +1])
);
end
end
for(g=(N/MAX_LOOP)*MAX_LOOP;g <N;g=g+1) begin:FA_INST_1
FA FA_ (
.A(A[g]),
.B(BB[g]),
.CI(C[g]),
.S(S[g]),
.CO(C[g+1])
);
end
end
endgenerate
endmodule
|
//======================================================================
//
// trng_avalanche_entropy.v
// ------------------------
// Wrapper for the avalanche entropy core to adapt it to the trng.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module trng_avalanche_entropy(
// Clock and reset.
input wire clk,
input wire reset_n,
input wire avalanche_noise,
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
//----------------------------------------------------------------
// core instantiations.
//----------------------------------------------------------------
avalance_entropy_core entropy1(
.clk(clk),
.reset_n(reset_n),
.enable(entropy1_enable),
.noise(avalanche_noise),
.raw_entropy(entropy1_raw),
.stats(entropy1_stats),
.enabled(entropy1_enabled),
.entropy_syn(entropy1_syn),
.entropy_data(entropy1_data),
.entropy_ack(entropy1_ack),
.led()
);
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
end
else
begin
end
end // reg_update
endmodule // trng_avalanche_entropy
//======================================================================
// EOF trng_avalanche_entropy.v
//======================================================================
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/20/2016 09:26:23 PM
// Design Name:
// Module Name: dstMgmt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "global.vh"
`ifdef CARPOOL_LK_AHEAD_RC_PS
`define DST_MGMT
`endif
`ifdef CARPOOL
`define DST_MGMT
`endif
`ifdef DST_MGMT
module dstMgmt(
allocPV,
dstList_in,
dstList_out
);
input [`NUM_PORT-1:0] allocPV;
input [`DST_LIST_WIDTH-1:0] dstList_in;
output [`DST_LIST_WIDTH-1:0] dstList_out;
parameter OUTDIR = 0;
wire [`DST_LIST_WIDTH-1:0] mask_out_port;
wire replica;
wire [`NUM_PORT-1:0] w_replica;
wire [`NUM_PORT-1:0] first;
assign w_replica[0] = 1'b0;
assign first[0] = 1'b1;
//assign forked[0] = 1'b0;
genvar i;
generate
for (i=0; i<`NUM_PORT-1; i=i+1) begin: flit_is_replica
// determine if the flit is a replica
// the flit on the first allocated port is not a replica
assign first [i+1] = first [i] ? ~allocPV[i] : 1'b0;
assign w_replica[i+1] = first [i+1] ? 1'b0 : (w_replica [i] || allocPV[i]);
end
endgenerate
assign replica = w_replica[OUTDIR];
// construct the mask for mc flit
assign mask_out_port =~((w_replica[0] ? `N_MASK : 'h0) |
(w_replica[1] ? `E_MASK : 'h0) |
(w_replica[2] ? `S_MASK : 'h0) |
(w_replica[3] ? `W_MASK : 'h0) |
(w_replica[4] ? `L_MASK : 'h0));
if (OUTDIR == 0)
assign dstList_out = dstList_in & (replica ? `N_MASK : mask_out_port);
else if (OUTDIR == 1)
assign dstList_out = dstList_in & (replica ? `E_MASK : mask_out_port);
else if (OUTDIR == 2)
assign dstList_out = dstList_in & (replica ? `S_MASK : mask_out_port);
else if (OUTDIR == 3)
assign dstList_out = dstList_in & (replica ? `W_MASK : mask_out_port);
endmodule
`endif // DST_MGMT |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUF_BLACKBOX_V
`define SKY130_FD_SC_LP__BUF_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__buf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUF_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( -O3 ) struct vertex { bool vis = false; vector<pair<long long int, long long int> > adj; long long int low = 1000000007; long long int dp = 0; long long int parent = -1; }; long long int tim = 0, n, m; vector<pair<long long int, long long int> > edges; bool flag = false; void dfs(vertex x[], long long int sor) { x[sor].vis = true; tim++; x[sor].dp = tim; x[sor].low = tim; for (auto y : x[sor].adj) { if (!x[y.first].vis) { x[y.first].parent = sor; dfs(x, y.first); x[sor].low = min(x[sor].low, x[y.first].low); if (x[y.first].low > x[sor].dp) flag = true; else edges[y.second] = {sor, y.first}; } else if (y.first != x[sor].parent) { x[sor].low = min(x[sor].low, x[y.first].dp); if (x[y.first].dp < x[sor].dp) { edges[y.second] = {sor, y.first}; } } } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; vertex x[n]; for (long long int a = 0; a < m; a++) { long long int u, v; cin >> u >> v; u--, v--; x[u].adj.push_back({v, a}); x[v].adj.push_back({u, a}); edges.push_back({u, v}); } dfs(x, 0); if (flag) cout << 0 << endl; else for (auto y : edges) cout << y.first + 1 << << y.second + 1 << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int k; cin >> k; int x; cin >> x; int* a; a = new int[n + 1]; for (int i = 1; i <= n; i++) { cin >> a[i]; } int index; index = n; while (k > 0) { a[index] = x; index--; k--; } int sum; sum = 0; for (int i = 1; i <= n; i++) { sum = sum + a[i]; } cout << sum; return 0; } |
// Copyright C(O) 2004 Burnell G West
// The following text may be utilized and / or reproduced by anybody for
// any reason.
//
// verr.v
//
module verr (clk, vout);
input clk;
output vout;
reg vout;
real start_edge;
real end_edge;
wire trigger_en;
wire [9:0] v_value;
initial vout = 1'b0;
always @( posedge clk)
begin
if (trigger_en)
begin
start_edge = ( v_value[0] * 1.95)
+ ( v_value[1] * 3.9 )
+ ( v_value[2] * 7.8 )
+ ( v_value[3] * 15.6 )
+ ( v_value[4] * 31.2 )
+ ( v_value[5] * 62.5 )
+ ( v_value[6] * 125 )
+ ( v_value[7] * 250 )
+ ( v_value[8] * 0 )
+ ( v_value[9] * 0 )
+ 0;
end_edge = start_edge + 100; // make pulse width = 1ns
end
else
begin
start_edge <= start_edge;
end_edge <= end_edge;
end
end
endmodule
module vtest;
wire vout0, vout1, vout2, vout3, vout4, vout5, vout6, vout7, vout8, vout9;
wire vout10, vout11, vout12, vout13, vout14, vout15, vout16, vout17,
vout18, vout19;
reg clk, bit0;
verr v0 (clk, vout0);
verr v1 (clk, vout1);
verr v2 (clk, vout2);
verr v3 (clk, vout3);
verr v4 (clk, vout4);
verr v5 (clk, vout5);
verr v6 (clk, vout6);
verr v7 (clk, vout7);
verr v8 (clk, vout8);
verr v9 (clk, vout9);
verr v10 (clk, vout10);
verr v11 (clk, vout11);
verr v12 (clk, vout12);
verr v13 (clk, vout13);
verr v14 (clk, vout14);
verr v15 (clk, vout15);
verr v16 (clk, vout16);
verr v17 (clk, vout17);
verr v18 (clk, vout18);
verr v19 (clk, vout19);
initial begin
#10000 $display("This test doesn't check itself.");
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long p = 1000000007; char s[100005]; long long w[100005]; long long te[100005] = {1}; void build() { for (int i = 1; i <= 100000; i++) { te[i] = (te[i - 1] * 10) % p; } } long long quick_mod(long long a, long long b) { long long ans = 1; a %= p; while (b) { if (b & 1) { ans = ans * a % p; b--; } b >>= 1; a = a * a % p; } return ans; } long long C(long long n, long long m) { if (m > n) return 0; long long ans = 1; for (int i = 1; i <= m; i++) { long long a = (n + i - m) % p; long long b = i % p; ans = ans * (a * quick_mod(b, p - 2) % p) % p; } return ans; } int main() { build(); long long n, k; scanf( %I64d%I64d , &n, &k); scanf( %s , s); long long ans = 0; w[n - 1] = C(n - 1, k); long long t = w[n - 1]; for (int i = n - 1; i >= 1; i--) { t = t * ((i - k) * quick_mod(i, p - 2) % p) % p; w[i - 1] = (w[i] + (te[n - i - 1] * t) % p * 9) % p; } for (int i = 0; i < n; i++) ans = (ans + w[i] * (s[i] - 0 )) % p; printf( %I64d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, sum, ans, a[100005]; inline long long read() { long long q = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = 0; ch = getchar(); } while (isdigit(ch)) { q = (q << 3) + (q << 1) + (ch ^ 48); ch = getchar(); } return f ? q : -q; } inline void print(long long x) { if (x < 0) { putchar( - ); x = -x; } if (x > 9) print(x / 10); putchar(x % 10 + 48); } signed main() { n = read(); for (register long long i = 1; i <= n; ++i) a[i] = read(), sum += a[i]; sort(a + 1, a + n + 1, greater<long long>()); for (register long long i = 1; i <= (sum % n); ++i) ans += abs(a[i] - sum / n - 1); for (register long long i = (sum % n) + 1; i <= n; ++i) ans += abs(a[i] - sum / n); print(ans >> 1); return 0; } |
#include <bits/stdc++.h> using namespace std; int a, ta, b, tb, x, y, sum, A, AA, B, BB; char ch; int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); ; cin >> a >> ta >> b >> tb >> x >> ch >> y; A = 60 * x + y; AA = A + ta; for (int i = 5 * 60; i <= 1439; i += b) { B = i; BB = B + tb; int maxx = max(A, B); int mini = min(AA, BB); if (maxx < mini) sum++; } cout << sum << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; long long a, b; int t; int main() { cin >> t; while (t--) { cin >> a >> b; cout << a + b << n ; } return 0; } |
/*cia b*/
module ciab
(
input clk, // clock
input clk7_en,
input aen, // adress enable
input rd, // read enable
input wr, // write enable
input reset, // reset
input [3:0] rs, // register select (address)
input [7:0] data_in, // bus data in
output [7:0] data_out, // bus data out
input tick, // tick (counter input for TOD timer)
input eclk, // eclk (counter input for timer A/B)
input flag, // flag (set FLG bit in ICR register)
output irq, // interrupt request out
input [5:3] porta_in, // input port
output [7:6] porta_out, // output port
output [7:0] portb_out // output port
);
// local signals
wire [7:0] icr_out;
wire [7:0] tmra_out;
wire [7:0] tmrb_out;
wire [7:0] tmrd_out;
reg [7:0] pa_out;
reg [7:0] pb_out;
wire alrm; // TOD interrupt
wire ta; // TIMER A interrupt
wire tb; // TIMER B interrupt
wire tmra_ovf; // TIMER A underflow (for Timer B)
reg [7:0] sdr_latch;
wire [7:0] sdr_out;
reg tick_del; // required for edge detection
//----------------------------------------------------------------------------------
// address decoder
//----------------------------------------------------------------------------------
wire pra,prb,ddra,ddrb,cra,talo,tahi,crb,tblo,tbhi,tdlo,tdme,tdhi,sdr,icrs;
wire enable;
assign enable = aen & (rd | wr);
// decoder
assign pra = (enable && rs==4'h0) ? 1'b1 : 1'b0;
assign prb = (enable && rs==4'h1) ? 1'b1 : 1'b0;
assign ddra = (enable && rs==4'h2) ? 1'b1 : 1'b0;
assign ddrb = (enable && rs==4'h3) ? 1'b1 : 1'b0;
assign talo = (enable && rs==4'h4) ? 1'b1 : 1'b0;
assign tahi = (enable && rs==4'h5) ? 1'b1 : 1'b0;
assign tblo = (enable && rs==4'h6) ? 1'b1 : 1'b0;
assign tbhi = (enable && rs==4'h7) ? 1'b1 : 1'b0;
assign tdlo = (enable && rs==4'h8) ? 1'b1 : 1'b0;
assign tdme = (enable && rs==4'h9) ? 1'b1 : 1'b0;
assign tdhi = (enable && rs==4'hA) ? 1'b1 : 1'b0;
assign sdr = (enable && rs==4'hC) ? 1'b1 : 1'b0;
assign icrs = (enable && rs==4'hD) ? 1'b1 : 1'b0;
assign cra = (enable && rs==4'hE) ? 1'b1 : 1'b0;
assign crb = (enable && rs==4'hF) ? 1'b1 : 1'b0;
//----------------------------------------------------------------------------------
// data_out multiplexer
//----------------------------------------------------------------------------------
assign data_out = icr_out | tmra_out | tmrb_out | tmrd_out | sdr_out | pb_out | pa_out;
// fake serial port data register
always @(posedge clk)
if (clk7_en) begin
if (reset)
sdr_latch[7:0] <= 8'h00;
else if (wr & sdr)
sdr_latch[7:0] <= data_in[7:0];
end
// sdr register read
assign sdr_out = (!wr && sdr) ? sdr_latch[7:0] : 8'h00;
//----------------------------------------------------------------------------------
// porta
//----------------------------------------------------------------------------------
reg [5:3] porta_in2;
reg [7:0] regporta;
reg [7:0] ddrporta;
// synchronizing of input data
always @(posedge clk)
if (clk7_en) begin
porta_in2[5:3] <= porta_in[5:3];
end
// writing of output port
always @(posedge clk)
if (clk7_en) begin
if (reset)
regporta[7:0] <= 8'd0;
else if (wr && pra)
regporta[7:0] <= data_in[7:0];
end
// writing of ddr register
always @(posedge clk)
if (clk7_en) begin
if (reset)
ddrporta[7:0] <= 8'd0;
else if (wr && ddra)
ddrporta[7:0] <= data_in[7:0];
end
// reading of port/ddr register
always @(*)
begin
if (!wr && pra)
pa_out[7:0] = {porta_out[7:6],porta_in2[5:3],3'b111};
else if (!wr && ddra)
pa_out[7:0] = ddrporta[7:0];
else
pa_out[7:0] = 8'h00;
end
// assignment of output port while keeping in mind that the original 8520 uses pull-ups
assign porta_out[7:6] = (~ddrporta[7:6]) | regporta[7:6];
//----------------------------------------------------------------------------------
// portb
//----------------------------------------------------------------------------------
reg [7:0] regportb;
reg [7:0] ddrportb;
// writing of output port
always @(posedge clk)
if (clk7_en) begin
if (reset)
regportb[7:0] <= 8'd0;
else if (wr && prb)
regportb[7:0] <= data_in[7:0];
end
// writing of ddr register
always @(posedge clk)
if (clk7_en) begin
if (reset)
ddrportb[7:0] <= 8'd0;
else if (wr && ddrb)
ddrportb[7:0] <= data_in[7:0];
end
// reading of port/ddr register
always @(*)
begin
if (!wr && prb)
pb_out[7:0] = portb_out[7:0];
else if (!wr && ddrb)
pb_out[7:0] = ddrportb[7:0];
else
pb_out[7:0] = 8'h00;
end
// assignment of output port while keeping in mind that the original 8520 uses pull-ups
assign portb_out[7:0] = (~ddrportb[7:0]) | regportb[7:0];
// deleyed tick signal for edge detection
always @(posedge clk)
if (clk7_en) begin
tick_del <= tick;
end
//----------------------------------------------------------------------------------
// instantiate cia interrupt controller
//----------------------------------------------------------------------------------
cia_int cnt
(
.clk(clk),
.clk7_en(clk7_en),
.wr(wr),
.reset(reset),
.icrs(icrs),
.ta(ta),
.tb(tb),
.alrm(alrm),
.flag(flag),
.ser(1'b0),
.data_in(data_in),
.data_out(icr_out),
.irq(irq)
);
//----------------------------------------------------------------------------------
// instantiate timer A
//----------------------------------------------------------------------------------
cia_timera tmra
(
.clk(clk),
.clk7_en(clk7_en),
.wr(wr),
.reset(reset),
.tlo(talo),
.thi(tahi),
.tcr(cra),
.data_in(data_in),
.data_out(tmra_out),
.eclk(eclk),
.tmra_ovf(tmra_ovf),
.irq(ta)
);
//----------------------------------------------------------------------------------
// instantiate timer B
//----------------------------------------------------------------------------------
cia_timerb tmrb
(
.clk(clk),
.clk7_en(clk7_en),
.wr(wr),
.reset(reset),
.tlo(tblo),
.thi(tbhi),
.tcr(crb),
.data_in(data_in),
.data_out(tmrb_out),
.eclk(eclk),
.tmra_ovf(tmra_ovf),
.irq(tb)
);
//----------------------------------------------------------------------------------
// instantiate timer D
//----------------------------------------------------------------------------------
cia_timerd tmrd
(
.clk(clk),
.clk7_en(clk7_en),
.wr(wr),
.reset(reset),
.tlo(tdlo),
.tme(tdme),
.thi(tdhi),
.tcr(crb),
.data_in(data_in),
.data_out(tmrd_out),
.count(tick & ~tick_del),
.irq(alrm)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = int(1e9) + 7; int main() { ios::sync_with_stdio(false); ios_base::sync_with_stdio(false); long long n, m; cin >> n >> m; vector<long long> a(n); for (int i = 0; i < n; ++i) { cin >> a[i]; } if (n >= 1001) { cout << 0; return 0; } long long res = 1; for (int i = 0; i < n; ++i) for (int j = i + 1; j < n; ++j) res = (res * (abs(a[i] - a[j]))) % m; cout << res; return 0; } |
#include<bits/stdc++.h> #define fast_io ios_base::sync_with_stdio(false);cin.tie(NULL); #define int long long #define ull unsigned long long #define FOR(i,a,b) for(int i=a;i<b;i++) #define all(x) (x).begin(), (x).end() #define pb push_back #define mp make_pair #define in insert #define ff first #define ss second #define endl n #define pi pair<int,int> #define deb1(a) cout<<a<< n ; #define deb2(a,b) cout<<a<< <<b<< n ; #define deb3(a,b,c) cout<<a<< <<b<< <<c<< n ; #define debp(a) cout<<a.ff<< <<a.ss<< n ; #define debvec(a) for(auto it: a)cout<<it<< ;cout<< ; cout<<endl; #define debvp(a) for(auto it: a)cout<<it.ff<< <<it.ss<<endl; #define debmap(a) for(auto it: a)cout<< { <<it.ff<< , <<it.ss<< }, ;newl; #define debarr(a,n) FOR(i,0,n)cout<<a[i]<< ;cout<<endl; #define inf ((int)1<<60) #define mod 1000000007 using namespace std; //int,char,float,double,bool,string,break,continue,endl,if,else,set,multiset,multimap,unordered_map,unordered_set,cout,cin,printf,scanf //strlen,strcmp,compar e,auto,while,return,true,false,sizeof,size,abs,INT_MAX,INT_MIN,itr,it,sort,YES,NO signed main() { #ifndef ONLINE_JUDGE freopen( input.txt , r , stdin); freopen( output.txt , w , stdout); #endif fast_io int test, i, j; // cin >> test; test = 1; while (test--) { int n, m; cin >> n >> m; string s, t; cin >> s >> t; int a[m], b[m]; j = 0; for (int i = 0; i < n; ++i) { if (s[i] == t[j]) { a[j] = i; j++; } } j = m - 1; for (int i = n - 1; i >= 0 ; i--) { if (s[i] == t[j]) { b[j] = i; j--; } } int ans = 0; for (int i = 0; i < m - 1; ++i) { ans = max(ans, b[i + 1] - a[i]); } cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; long long int ESP = 1e18; long long int FCB = 1e9 + 7; long long int dir[][2] = {{0, 1}, {0, -1}, {1, 0}, {-1, 0}}; const long long int N = 5005; long long int l[N], r[N]; vector<pair<long long int, long long int>> vv; bool fly(long long int x, long long int y) { if (l[x] >= r[y]) return false; if (r[x] <= l[y]) return false; return true; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; long long int n; cin >> n; for (long long int i = 1; i < n + 1; i++) cin >> l[i] >> r[i]; for (long long int i = 1; i < n + 1; i++) { for (long long int j = 1; j < n + 1; j++) { if (i != j && fly(i, j)) vv.push_back(make_pair(i, j)); } } map<long long int, long long int> mp; long long int zz = vv.size(); for (long long int i = 0; i < zz; i++) { mp[vv[i].first]++; mp[vv[i].second]++; } vector<long long int> ans; for (long long int i = 1; i <= n; i++) { if (mp[i] == zz) ans.push_back(i); } long long int dd = ans.size(); cout << dd << n ; for (long long int i = 0; i < dd; i++) cout << ans[i] << ; cout << n ; return 0; } |
/* -> Written by <- ----------- |K_A_Z_A_M_A| |___________| | ___ | | (^_^) | | /( | ) | |____|_|____| H O A N G */ #include <bits/stdc++.h> #define Task running #define F first #define S second #define pb push_back #define bit(x, i) ((x >> (i)) & 1) #define inf 1e9 + 7 #define INF 1e18 + 7 #define ll long long #define pii pair <int, int> #define debug(x) cerr << #x << is << x << n ; using namespace std; const int MOD = 1e9 + 7; const int maxn = 1e5 + 5; const int base = 3e5 + 1; int n, q; int a[300005]; vector <int> p[300005]; void Solve(int test_case) { cin >> n >> q; for (int i = 1; i <= n; ++ i) { cin >> a[i]; p[a[i]].pb(i); } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); for (int i = 1; i <= q; ++ i) { int l, r; cin >> l >> r; int ans = 1; for (int times = 1; times <= 40; ++ times) { int u = a[uniform_int_distribution<int>(l,r)(rng)]; int f = upper_bound(p[u].begin(), p[u].end(), r) - lower_bound(p[u].begin(), p[u].end(), l); ans = max(ans, 2 * f - (r - l + 1)); } cout << ans << n ; } } int main(){ ios_base::sync_with_stdio(false);cin.tie(NULL);cout.tie(NULL); if (fopen(Task .inp , r )) { freopen(Task .inp , r , stdin); freopen(Task .out , w , stdout); } // Prepare(); int test_case = 1; // cin >> test_case; for (int i = 1; i <= test_case; ++ i) { Solve(i); } return 0; } |
#include <bits/stdc++.h> int main() { using namespace std; ios_base::sync_with_stdio(false); cin.tie(nullptr); string b, b1, b2, e, e1, e2; cin >> b1 >> b2 >> e1 >> e2; swap(b2[0], b2[1]); swap(e2[0], e2[1]); b = b1 + b2; e = e1 + e2; b.erase(b.find( X ), 1); e.erase(e.find( X ), 1); if ((b + b).find(e) != string::npos) { cout << YES ; } else { cout << NO ; } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:19:57 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_StackPointer_0_0/RAT_StackPointer_0_0_stub.v
// Design : RAT_StackPointer_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "StackPointer,Vivado 2016.4" *)
module RAT_StackPointer_0_0(DATA, RST, LD, INCR, DECR, CLK, DOUT)
/* synthesis syn_black_box black_box_pad_pin="DATA[7:0],RST,LD,INCR,DECR,CLK,DOUT[7:0]" */;
input [7:0]DATA;
input RST;
input LD;
input INCR;
input DECR;
input CLK;
output [7:0]DOUT;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22OI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A22OI_BLACKBOX_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a22oi (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22OI_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:49:45 01/23/2017
// Design Name: mux2_1
// Module Name: /home/aaron/Git Repos/CSE311/lab1_reverse/mux2_1_tb.v
// Project Name: lab1_reverse
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: mux2_1
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module mux2_1_tb;
// Inputs
reg [7:0] input1;
reg [7:0] input2;
reg select;
// Outputs
wire [7:0] selected_out;
// Instantiate the Unit Under Test (UUT)
mux2_1 uut (
.input1(input1),
.input2(input2),
.select(select),
.selected_out(selected_out)
);
initial begin
// Initialize Inputs
input1 = 0;
input2 = 0;
select = 0;
// Wait 100 ns for global reset to finish
#100;
// First case: select input2 from mux
input1 = 8'b10000001;
input2 = 8'b10101010;
select = 1'b1;
#100;
// Second Case: select input1 from mux
select = 1'b0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int n = 0, temp1 = 0, temp2 = 0; cin >> n; std::vector<long long int> v1; std::vector<long long int> v2; long long int hash1[100001], hash2[100001]; for (long long int i = 0; i < 100001; ++i) { hash1[i] = 0; hash2[i] = 0; } for (long long int i = 0; i < n; ++i) { cin >> temp1 >> temp2; v1.push_back(temp1); v2.push_back(temp2); } for (long long int i = 0; i < n; ++i) { hash1[v1[i]]++; hash2[v2[i]]++; } for (long long int i = 0; i < n; ++i) { cout << (n - 1 + hash1[v2[i]]) << << (n - 1 - hash1[v2[i]]) << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKBUF_4_V
`define SKY130_FD_SC_MS__CLKBUF_4_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkbuf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkbuf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKBUF_4_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for ip_eth_tx_64
*/
module test_ip_eth_tx_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_ip_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [5:0] s_ip_dscp = 0;
reg [1:0] s_ip_ecn = 0;
reg [15:0] s_ip_length = 0;
reg [15:0] s_ip_identification = 0;
reg [2:0] s_ip_flags = 0;
reg [12:0] s_ip_fragment_offset = 0;
reg [7:0] s_ip_ttl = 0;
reg [7:0] s_ip_protocol = 0;
reg [31:0] s_ip_source_ip = 0;
reg [31:0] s_ip_dest_ip = 0;
reg [63:0] s_ip_payload_axis_tdata = 0;
reg [7:0] s_ip_payload_axis_tkeep = 0;
reg s_ip_payload_axis_tvalid = 0;
reg s_ip_payload_axis_tlast = 0;
reg s_ip_payload_axis_tuser = 0;
reg m_eth_hdr_ready = 0;
reg m_eth_payload_axis_tready = 0;
// Outputs
wire s_ip_hdr_ready;
wire s_ip_payload_axis_tready;
wire m_eth_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [63:0] m_eth_payload_axis_tdata;
wire [7:0] m_eth_payload_axis_tkeep;
wire m_eth_payload_axis_tvalid;
wire m_eth_payload_axis_tlast;
wire m_eth_payload_axis_tuser;
wire busy;
wire error_payload_early_termination;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_ip_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_ip_dscp,
s_ip_ecn,
s_ip_length,
s_ip_identification,
s_ip_flags,
s_ip_fragment_offset,
s_ip_ttl,
s_ip_protocol,
s_ip_source_ip,
s_ip_dest_ip,
s_ip_payload_axis_tdata,
s_ip_payload_axis_tkeep,
s_ip_payload_axis_tvalid,
s_ip_payload_axis_tlast,
s_ip_payload_axis_tuser,
m_eth_hdr_ready,
m_eth_payload_axis_tready
);
$to_myhdl(
s_ip_hdr_ready,
s_ip_payload_axis_tready,
m_eth_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_eth_payload_axis_tdata,
m_eth_payload_axis_tkeep,
m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast,
m_eth_payload_axis_tuser,
busy,
error_payload_early_termination
);
// dump file
$dumpfile("test_ip_eth_tx_64.lxt");
$dumpvars(0, test_ip_eth_tx_64);
end
ip_eth_tx_64
UUT (
.clk(clk),
.rst(rst),
// IP frame input
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_identification(s_ip_identification),
.s_ip_flags(s_ip_flags),
.s_ip_fragment_offset(s_ip_fragment_offset),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(s_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Status signals
.busy(busy),
.error_payload_early_termination(error_payload_early_termination)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100008; int n, a[N]; vector<pair<int, int> > ans; int main(void) { int i, j, k; scanf( %d , &n); for (i = 1; i <= n; i++) scanf( %d , a + i); for (i = 1; i + 2 <= n; i++) if (a[i]) { k = 1; for (j = 2; i + j <= n; j++) if (a[i + j]) { if (i + j + j <= n) k = j; else k = 1; break; } a[i] ^= 1; a[i + k] ^= 1; a[i + k + k] ^= 1; ans.push_back(make_pair(i, k)); } if (a[n - 1] == 0 && a[n] == 0) ; else if (a[n - 1] == 1 && a[n] == 0) { if (n >= 8) { ans.push_back(make_pair(n - 7, 1)); ans.push_back(make_pair(n - 7, 3)); ans.push_back(make_pair(n - 6, 1)); } else { printf( NO ); return 0; } } else if (a[n - 1] == 0 && a[n] == 1) { if (n >= 7) { ans.push_back(make_pair(n - 6, 1)); ans.push_back(make_pair(n - 6, 3)); ans.push_back(make_pair(n - 5, 1)); } else { printf( NO ); return 0; } } else { if (n >= 8) { ans.push_back(make_pair(n - 7, 1)); ans.push_back(make_pair(n - 7, 3)); ans.push_back(make_pair(n - 6, 1)); ans.push_back(make_pair(n - 6, 1)); ans.push_back(make_pair(n - 6, 3)); ans.push_back(make_pair(n - 5, 1)); } else { printf( NO ); return 0; } } printf( YES n%d n , (int)ans.size()); for (auto p : ans) printf( %d %d %d n , p.first, p.first + p.second, p.first + p.second + p.second); return 0; } |
#include <bits/stdc++.h> int star[100005]; int scnt; int pack[100005]; int pcnt; int unit(int x) { if (x > 0) return x; return 0; } int check(int time) { int i; int sat = 0; for (i = 1; i <= pcnt; i++) { if (sat >= star[scnt]) return 1; int l = 1, r = scnt, mid, idx; while (l <= r) { mid = (l + r) / 2; if (star[mid] > sat) { idx = mid; r = mid - 1; } else l = mid + 1; } if (star[idx] < pack[i]) { if (pack[i] - star[idx] > time) return 0; int t = pack[i] - star[idx]; sat = pack[i] + unit(time - 2 * t); if (sat < pack[i] + (time - t) / 2) sat = pack[i] + (time - t) / 2; } else sat = pack[i] + time; } if (sat >= star[scnt]) return 1; return 0; } int main(void) { int n; char tmp[100005]; scanf( %d , &n); scanf( %s , &tmp[1]); int i; for (i = 1; i <= n; i++) { if (tmp[i] == * ) star[++scnt] = i; if (tmp[i] == P ) pack[++pcnt] = i; } int l = 1, r = 2 * n - 1, mid, ans; while (l <= r) { mid = (l + r) / 2; if (check(mid)) { ans = mid; r = mid - 1; } else l = mid + 1; } printf( %d , ans); } |
//-----------------------------------------------------------------
// RISC-V Top
// V0.6
// Ultra-Embedded.com
// Copyright 2014-2019
//
//
//
// License: BSD
//-----------------------------------------------------------------
//
// Copyright (c) 2014, Ultra-Embedded.com
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the author nor the names of its contributors
// may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
// SUCH DAMAGE.
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module dcache_if_pmem
(
// Inputs
input clk_i
,input rst_i
,input [ 31:0] mem_addr_i
,input [ 31:0] mem_data_wr_i
,input mem_rd_i
,input [ 3:0] mem_wr_i
,input mem_cacheable_i
,input [ 10:0] mem_req_tag_i
,input mem_invalidate_i
,input mem_writeback_i
,input mem_flush_i
,input outport_accept_i
,input outport_ack_i
,input outport_error_i
,input [ 31:0] outport_read_data_i
// Outputs
,output [ 31:0] mem_data_rd_o
,output mem_accept_o
,output mem_ack_o
,output mem_error_o
,output [ 10:0] mem_resp_tag_o
,output [ 3:0] outport_wr_o
,output outport_rd_o
,output [ 7:0] outport_len_o
,output [ 31:0] outport_addr_o
,output [ 31:0] outport_write_data_o
);
//-------------------------------------------------------------
// Description:
// Bridges between dcache_if -> AXI4/AXI4-Lite.
// Allows 1 outstanding transaction, but can buffer upto
// REQUEST_BUFFER dcache_if requests before back-pressuring.
//-------------------------------------------------------------
//-------------------------------------------------------------
// Request FIFO
//-------------------------------------------------------------
// Accepts from both FIFOs
wire res_accept_w;
wire req_accept_w;
// Output accept
wire request_complete_w;
wire req_pop_w = request_complete_w;
wire req_valid_w;
wire [70-1:0] req_w;
// Cache requests are dropped
// NOTE: Should not actually end up here if configured correctly.
wire drop_req_w = mem_invalidate_i || mem_writeback_i || mem_flush_i;
wire request_w = drop_req_w || mem_rd_i || mem_wr_i != 4'b0;
// Push on transaction and other FIFO not full
wire req_push_w = request_w && res_accept_w;
dcache_if_pmem_fifo
#(
.WIDTH(32+32+4+1+1),
.DEPTH(2),
.ADDR_W(1)
)
u_req
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i({drop_req_w, mem_rd_i, mem_wr_i, mem_data_wr_i, mem_addr_i}),
.push_i(req_push_w),
.accept_o(req_accept_w),
// Outputs
.valid_o(req_valid_w),
.data_out_o(req_w),
.pop_i(req_pop_w)
);
assign mem_accept_o = req_accept_w & res_accept_w;
//-------------------------------------------------------------
// Response Tracking FIFO
//-------------------------------------------------------------
// Push on transaction and other FIFO not full
wire res_push_w = request_w && req_accept_w;
dcache_if_pmem_fifo
#(
.WIDTH(11),
.DEPTH(2),
.ADDR_W(1)
)
u_resp
(
.clk_i(clk_i),
.rst_i(rst_i),
// Input side
.data_in_i(mem_req_tag_i),
.push_i(res_push_w),
.accept_o(res_accept_w),
// Outputs
.valid_o(), // UNUSED
.data_out_o(mem_resp_tag_o),
.pop_i(mem_ack_o)
);
//-------------------------------------------------------------
// Request
//-------------------------------------------------------------
reg request_pending_q;
wire request_in_progress_w = request_pending_q & !mem_ack_o;
wire req_is_read_w = ((req_valid_w & !request_in_progress_w) ? req_w[68] : 1'b0);
wire req_is_write_w = ((req_valid_w & !request_in_progress_w) ? ~req_w[68] : 1'b0);
wire req_is_drop_w = ((req_valid_w & !request_in_progress_w) ? req_w[69] : 1'b0);
assign outport_wr_o = req_is_write_w ? req_w[67:64] : 4'b0;
assign outport_rd_o = req_is_read_w;
assign outport_len_o = 8'd0;
assign outport_addr_o = {req_w[31:2], 2'b0};
assign outport_write_data_o = req_w[63:32];
assign request_complete_w = req_is_drop_w || ((outport_rd_o || outport_wr_o != 4'b0) && outport_accept_i);
// Outstanding Request Tracking
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
request_pending_q <= 1'b0;
else if (request_complete_w)
request_pending_q <= 1'b1;
else if (mem_ack_o)
request_pending_q <= 1'b0;
//-------------------------------------------------------------
// Response
//-------------------------------------------------------------
reg dropped_q;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
dropped_q <= 1'b0;
else if (req_is_drop_w)
dropped_q <= 1'b1;
else
dropped_q <= 1'b0;
assign mem_ack_o = dropped_q || outport_ack_i;
assign mem_data_rd_o = outport_read_data_i;
assign mem_error_o = outport_error_i;
endmodule
module dcache_if_pmem_fifo
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
#(
parameter WIDTH = 8,
parameter DEPTH = 4,
parameter ADDR_W = 2
)
//-----------------------------------------------------------------
// Ports
//-----------------------------------------------------------------
(
// Inputs
input clk_i
,input rst_i
,input [WIDTH-1:0] data_in_i
,input push_i
,input pop_i
// Outputs
,output [WIDTH-1:0] data_out_o
,output accept_o
,output valid_o
);
//-----------------------------------------------------------------
// Local Params
//-----------------------------------------------------------------
localparam COUNT_W = ADDR_W + 1;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [WIDTH-1:0] ram_q[DEPTH-1:0];
reg [ADDR_W-1:0] rd_ptr_q;
reg [ADDR_W-1:0] wr_ptr_q;
reg [COUNT_W-1:0] count_q;
//-----------------------------------------------------------------
// Sequential
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
count_q <= {(COUNT_W) {1'b0}};
rd_ptr_q <= {(ADDR_W) {1'b0}};
wr_ptr_q <= {(ADDR_W) {1'b0}};
end
else
begin
// Push
if (push_i & accept_o)
begin
ram_q[wr_ptr_q] <= data_in_i;
wr_ptr_q <= wr_ptr_q + 1;
end
// Pop
if (pop_i & valid_o)
rd_ptr_q <= rd_ptr_q + 1;
// Count up
if ((push_i & accept_o) & ~(pop_i & valid_o))
count_q <= count_q + 1;
// Count down
else if (~(push_i & accept_o) & (pop_i & valid_o))
count_q <= count_q - 1;
end
//-------------------------------------------------------------------
// Combinatorial
//-------------------------------------------------------------------
/* verilator lint_off WIDTH */
assign valid_o = (count_q != 0);
assign accept_o = (count_q != DEPTH);
/* verilator lint_on WIDTH */
assign data_out_o = ram_q[rd_ptr_q];
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10, mod = 998244353; int add(int a, int b) { a += b; if (a >= mod) { a -= mod; } return a; } int sub(int a, int b) { a -= b; if (a < 0) { a += mod; } return a; } int mul(long long a, int b) { return (a * b) % mod; } int pwr(int x, int e) { int res = 1; while (e) { if (e & 1) { res = mul(res, x); } x = mul(x, x); e /= 2; } return res; } struct tournament { vector<int> p; int h = 0, i; }; vector<tournament> get_pairs(int a, int l, int r); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int k, a, h; cin >> k >> a >> h; vector<tournament> v1, v2; v1 = get_pairs(a, 1, (1 << (k - 1))); v2 = get_pairs(a, (1 << (k - 1)) + 1, (1 << k)); for (int tc = 0; tc < 2; ++tc) { int sz = v1.size(); map<int, int> mp; for (int i = 0; i < sz; ++i) { mp[sub(h, add(v1[i].h, mul(v1[i].i, a)))] = i; } for (int i = 0; i < sz; ++i) { int val = add(v2[i].h, mul(v2[i].i, mul(a, a))); if (mp.find(val) != mp.end()) { int ti = mp[val], tj = i; int winner = v1[ti].i; int second = v2[tj].i; if (tc == 1) { swap(ti, tj); } vector<int> ans = v1[ti].p; for (auto& pos : v2[tj].p) { ans.push_back(pos); } ans[winner - 1] = 1; ans[second - 1] = 2; for (auto& pos : ans) { cout << pos << ; } cout << n ; return 0; } } swap(v1, v2); } cout << -1 << n ; } vector<tournament> get_pairs(int a, int l, int r) { int n = (r - l + 1), tot = (1 << (n - 1)); vector<int> ids(n); vector<tournament> ans; iota(ids.begin(), ids.end(), l); for (int ch = 0; ch < tot; ++ch) { int mask = ch; tournament t; t.p.resize(n, 0); queue<int> q; for (int i = 0; i < n; ++i) { q.push(i); } int cur_rank = n + 1, rank_cnt = n / 2; while (q.size() > 1) { int p1 = q.front(); q.pop(); int p2 = q.front(); q.pop(); if (mask & 1) { t.p[p2] = cur_rank; t.h = add(t.h, mul(ids[p2], pwr(a, cur_rank))); q.push(p1); } else { t.p[p1] = cur_rank; t.h = add(t.h, mul(ids[p1], pwr(a, cur_rank))); q.push(p2); } mask /= 2; --rank_cnt; if (rank_cnt == 0) { cur_rank = ((cur_rank - 1) / 2) + 1; rank_cnt = (cur_rank - 1) / 2; } } t.i = ids[q.front()]; ans.push_back(t); } return ans; } |
#include <bits/stdc++.h> using namespace std; const int N = 5000 + 5; const int inf = 0x3f3f3f3f; const int Max = 200000; template <class T> inline void getin(T& num) { char c; bool flag = 0; num = 0; while ((c = getchar()) < 0 || c > 9 ) if (c == - ) flag = 1; while (c >= 0 && c <= 9 ) { num = num * 10 + c - 48; c = getchar(); } if (flag) num = -num; } int n, k, a, x, y, m; queue<int> num[N]; set<pair<int, int> > output; vector<pair<int, int> > Ans; int main() { getin(n); int sum = 0, ans = 0; for (int i = 1; i <= n; i++) { getin(k), getin(a), sum += k; getin(x), getin(y), getin(m); num[i].push(a); int ret = 0; for (int j = 2; j <= k; j++) { int nxt = (1ll * a * x % m + y) % m; if (nxt < a) ret++; num[i].push(a = nxt); } ans = max(ans, ret); } printf( %d n , ans); if (sum > Max) return 0; for (int i = 1; i <= n; i++) { output.insert(make_pair(num[i].front(), i)); num[i].pop(); } int last = -inf, p; for (int i = 1; i <= sum; i++) { set<pair<int, int> >::iterator it = output.lower_bound(make_pair(last, -inf)); if (it == output.end()) ans++, it = output.begin(); Ans.push_back(*it); last = (*it).first; p = (*it).second; output.erase(it); if (!num[p].empty()) { output.insert(make_pair(num[p].front(), p)); num[p].pop(); } } for (int i = 0; i < sum; i++) printf( %d %d n , Ans[i].first, Ans[i].second); } |
`timescale 1ns/1ns
module spi_slave_rxq
(input c,
input cs, input sclk, input mosi,
output [7:0] rxd, output rxdv, output rxe);
wire [7:0] spi_rxd;
wire spi_rxdv, spi_rxe;
spi_slave_rx spi_slave_rx_inst
(.clk(c), .cs(cs), .sclk(sclk), .mosi(mosi),
.rxd(spi_rxd), .rxdv(spi_rxdv), .rxe(spi_rxe));
wire dfifo_rdreq, dfifo_empty;
wire [7:0] dfifo_q;
wire [7:0] dfifo_usedw;
scfifo #(.lpm_width(8),
.lpm_numwords(256),
.lpm_widthu(8),
.lpm_showahead("ON"),
.use_eab("ON"),
.intended_device_family("CYCLONE V")) dfifo
(.clock(c),
.wrreq(spi_rxdv), .data(spi_rxd),
.rdreq(dfifo_rdreq), .q(dfifo_q),
.empty(dfifo_empty), .usedw(dfifo_usedw), .aclr(1'b0), .sclr(1'b0));
localparam SW = 3;
localparam ST_IDLE = 3'd0;
localparam ST_TX_HEADER = 3'd1;
localparam ST_DRAIN_FIFO = 3'd2;
localparam ST_DONE = 3'd3;
localparam CW = 4;
reg [SW+CW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_reg
(.c(c), .d(next_state), .rst(1'b0), .en(1'b1), .q(state));
assign rxdv = ctrl[0];
assign rxd = state == ST_TX_HEADER ? 8'h99 : dfifo_q;
assign rxe = rxdv & dfifo_usedw == 8'h1;
assign dfifo_rdreq = ctrl[1];
always @* begin
case (state)
ST_IDLE:
if (spi_rxe) ctrl = { ST_TX_HEADER , 4'b0000 };
else ctrl = { ST_IDLE , 4'b0000 };
ST_TX_HEADER: ctrl = { ST_DRAIN_FIFO, 4'b0001 };
ST_DRAIN_FIFO:
if (dfifo_usedw == 8'h1) ctrl = { ST_IDLE , 4'b0011 };
else ctrl = { ST_DRAIN_FIFO, 4'b0011 };
default: ctrl = { ST_IDLE , 4'b0000 };
endcase
end
endmodule
`ifdef test_spi_slave_rxq
module spi_slave_rxq_tb();
wire c;
sim_clk #(100) clk_inst(c);
localparam W = 8;
reg [W-1:0] master_txd;
wire [W-1:0] master_rxd;
reg master_txdv;
wire master_rxdv;
wire master_done, master_busy;
wire sclk, mosi, miso, cs;
spi_master #(.SCLK_DIV(50), .W(8)) spi_master_inst
(.c(c), .busy(master_busy), .done(master_done),
.txd(master_txd), .txdv(master_txdv),
.rxd(master_rxd), .rxdv(master_rxdv),
.sclk(sclk), .mosi(mosi), .miso(miso), .cs(cs));
wire [7:0] qrxd;
wire qrxdv, qrxe;
spi_slave_rxq dut
(.c(c), .cs(cs), .sclk(sclk), .mosi(mosi),
.rxd(qrxd), .rxdv(qrxdv), .rxe(qrxe));
initial begin
$dumpfile("spi_slave_rxq.lxt");
$dumpvars();
master_txd = 8'ha5;
master_txdv = 0;
#100
@(posedge c);
#1 master_txdv = 1;
@(posedge c);
#1 master_txd = 8'h7;
@(posedge c);
#1 master_txd = 8'h51;
@(posedge c);
#1 master_txdv = 0;
#40000
@(posedge c);
#1 master_txdv = 1;
@(posedge c);
#1 master_txdv = 0;
#40000
$finish;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__AND2_PP_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; long long a[200005]; long long b[200005]; int i; for (i = 0; i < n; i++) { cin >> a[i]; a[i] = a[i] * (i + 1) * (n - i); } for (i = 0; i < n; i++) { cin >> b[i]; } sort(a, a + n); sort(b, b + n); long long ans = 0; for (i = 0; i < n; i++) { ans = (ans + ((a[i] % 998244353) * b[n - i - 1]) % 998244353) % 998244353; } cout << ans << endl; } |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title :
// File :
// Author : Jim MacLeod
// Created : 01-Dec-2011
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module flt_mult_comb
(
input [31:0] afl,
input [31:0] bfl,
output reg [31:0] fl
);
reg [47:0] mfl_0; // Mantisa of the Float
reg sfl_0; // Sign of the Float
reg [7:0] efl_0; // Exponent of the Float
reg zero_out_0;
reg sfl_1; // Sign of the Float
reg [7:0] efl_1; // Exponent of the Float
reg zero_out_1;
reg mfl47_1; // Mantisa of the Float
reg [24:0] nmfl_1; // Normalized Mantisa of the Float
reg not_mfl_47;
always @* not_mfl_47 = (~mfl47_1 & ~nmfl_1[24]);
always @* begin
// Pipe 0.
// Multiply the mantisa.
mfl_0 = {1'b1,afl[22:0]} * {1'b1,bfl[22:0]};
// Calulate the Sign.
sfl_0 = afl[31] ^ bfl[31];
efl_0 = afl[30:23] + bfl[30:23] - 8'h7E;
// If a or b equals zero, return zero.
if((afl[30:0] == 0) || (bfl[30:0] == 0))zero_out_0 <= 1'b1;
else zero_out_0 <= 1'b0;
// Pipe 1.
efl_1 = efl_0;
sfl_1 = sfl_0;
zero_out_1 = zero_out_0;
mfl47_1 = mfl_0[47];
if(mfl_0[47]) nmfl_1 = mfl_0[47:24] + mfl_0[23];
else nmfl_1 = mfl_0[47:23] + mfl_0[22];
// Pipe 2.
if(zero_out_1) fl = 32'h0;
else fl = {sfl_1,(efl_1 - not_mfl_47),nmfl_1[22:0]};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, l, r, ql, qr; int w[100010]; int main() { cin >> n >> l >> r >> ql >> qr; for (int i = 1; i <= n; ++i) cin >> w[i]; int f[100010]; f[0] = 0; for (int i = 1; i <= n; ++i) f[i] = f[i - 1] + w[i]; int ans = INT_MAX; for (int i = 0; i <= n; ++i) { int v = f[i] * l + (f[n] - f[i]) * r; if (i < n / 2) v += qr * max(0, (n - 2 * i - 1)); else v += ql * max(0, (2 * i - n - 1)); ans = min(ans, v); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long t = 1, n, k, fact, a, b; cin >> t; while (t--) { cin >> a >> b; if (a == 1) cout << 0 n ; else if (a == 2) cout << b << n ; else cout << 2 * b << n ; } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NOR2_BEHAVIORAL_PP_V
/**
* nor2: 2-input NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR2_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBP_1_V
`define SKY130_FD_SC_LS__DFBBP_1_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog wrapper for dfbbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfbbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dfbbp_1 (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dfbbp base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.CLK(CLK),
.SET_B(SET_B),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBP_1_V
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller ECC Decoder
//
// File : alt_ddrx_decoder.v
//
// Abstract : Decode ECC information
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_ddrx_decoder #
( parameter
INPUT_DATA_WIDTH = 72,
OUTPUT_DATA_WIDTH = 64
)
(
ctl_clk,
input_data,
err_corrected,
err_detected,
err_fatal,
output_data
);
input ctl_clk;
input [INPUT_DATA_WIDTH - 1 : 0] input_data;
output [OUTPUT_DATA_WIDTH - 1 : 0] output_data;
output err_corrected;
output err_detected;
output err_fatal;
wire [OUTPUT_DATA_WIDTH - 1 : 0] output_data;
wire err_corrected;
wire err_detected;
wire err_fatal;
generate
if (INPUT_DATA_WIDTH == 40)
begin
// encoder only have 32/29 combination
alt_ddrx_decoder_40 decoder_40_inst
(
.clock (ctl_clk),
.data (input_data [INPUT_DATA_WIDTH - 2 : 0]),
.err_corrected (err_corrected),
.err_detected (err_detected),
.err_fatal (err_fatal),
.q (output_data)
);
end
else if (INPUT_DATA_WIDTH == 72)
begin
alt_ddrx_decoder_72 decoder_72_inst
(
.clock (ctl_clk),
.data (input_data),
.err_corrected (err_corrected),
.err_detected (err_detected),
.err_fatal (err_fatal),
.q (output_data)
);
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
`define SIMULATION
module peripheral_mult_TB;
reg clk;
reg rst;
reg reset;
reg start;
reg [15:0]d_in;
reg cs;
reg [1:0]addr;
reg rd;
reg wr;
wire [15:0]d_out;
peripheral uut (.clk(clk) , .rst(rst) , .d_in(d_in) , .cs(cs) , .addr(addr) , .rd(rd) , .wr(wr), .d_out(d_out) );
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
reg [20:0] i;
event reset_trigger;
initial begin // Initialize Inputs
clk = 0; reset = 1; start = 0; d_in = 16'd0035; addr = 16'h0000; cs=1; rd=0; wr=1;
end
initial begin // Process for clk
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin // Reset the system, Start the image capture process
forever begin
@ (reset_trigger);
@ (posedge clk);
start = 0;
@ (posedge clk);
start = 1;
for(i=0; i<2; i=i+1) begin
@ (posedge clk);
end
start = 0;
// stimulus here
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0005; //envio A
addr = 16'h0000;
cs=1; rd=0; wr=1;
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0002; //envio B
addr = 16'h0001;
cs=1; rd=0; wr=1;
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0001; //envio init
addr = 16'h0002;
cs=1; rd=0; wr=1;
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'd0000; //recibo dato
addr = 16'h0002;
cs=0; rd=1; wr=0;
end
end
initial begin: TEST_CASE
$dumpfile("peripheral_mult_TB.vcd");
$dumpvars(-1, uut);
#10 -> reset_trigger;
#((PERIOD*DUTY_CYCLE)*200) $finish;
end
endmodule
|
#include <bits/stdc++.h> using std::map; using std::max; using std::min; using std::set; using std::sort; using std::swap; using std::vector; inline int readInt() { int ans = 0; char c; do c = getchar(); while (!isdigit(c)); while (isdigit(c)) { ans = ans * 10 + c - 0 ; c = getchar(); } return ans; } const int N = 55; int A[N][N]; int main() { int n = readInt(); for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) A[i][j] = readInt(); for (int i = 0; i < n; ++i) for (int j = 0; j < n; ++j) if (A[i][j] != 1) { bool ok = false; for (int k = 0; k < n; ++k) if (i != k) { for (int l = 0; l < n; ++l) if (j != l && A[i][j] == A[k][j] + A[i][l]) { ok = true; break; } if (ok) break; } if (!ok) return puts( NO ), 0; } return puts( YES ), 0; } |
#include <bits/stdc++.h> using namespace std; int n; string s; long long rights[1000010], lefts[1000010], mins[1000010]; long long suml[1000010], sumr[1000010]; int min(int a, int b) { return a < b ? a : b; } int main() { scanf( %d , &n); cin >> s; lefts[0] = 0; rights[n - 1] = 0; for (int i = 1; i < n; i++) { if (s[i - 1] == U ) lefts[i]++; lefts[i] += lefts[i - 1]; } for (int i = n - 2; i >= 0; i--) { if (s[i + 1] == D ) rights[i]++; rights[i] += rights[i + 1]; } for (int i = 0; i < n; i++) mins[i] = min(lefts[i] + (s[i] == U ? 1 : 0), rights[i] + (s[i] == D ? 1 : 0)); long long t = 0; queue<long long> q; for (int i = 0; i < n; i++) { t += q.size(); if (q.size() <= mins[i]) { suml[i] = t; } else { while (q.size() > mins[i]) { t -= i - q.front(); q.pop(); } suml[i] = t; } if (s[i] == U ) q.push(i); } while (!q.empty()) q.pop(); t = 0; for (int i = n - 1; i >= 0; i--) { t += q.size(); if (q.size() <= mins[i]) { sumr[i] = t; } else { while (q.size() > mins[i]) { t -= q.front() - i; q.pop(); } sumr[i] = t; } if (s[i] == D ) q.push(i); } for (long long i = 0; i < n; i++) { if (rights[i] > lefts[i]) { cout << sumr[i] * 2 + suml[i] * 2 + i + 1 << ; } else if (rights[i] < lefts[i]) { cout << sumr[i] * 2 + suml[i] * 2 + n - i << ; } else { if (s[i] == D ) cout << sumr[i] * 2 + suml[i] * 2 + i + 1 << ; else cout << sumr[i] * 2 + suml[i] * 2 + n - i << ; } } cout << endl; return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_vuad_io.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
module sctag_vuad_io
(/*AUTOARG*/
// Outputs
data_out_io, array_data_in_buf_top, array_data_in_buf_bottom,
// Inputs
data_out_col1, data_out_col2, data_out_col3, data_out_col4,
array_data_in, mux_sel
) ;
input [25:0] data_out_col1; // from vuad_col_dp.
input [25:0] data_out_col2; // from vuad_col_dp.
input [25:0] data_out_col3; // from vuad_col_dp.
input [25:0] data_out_col4; // from vuad_col_dp.
input [25:0] array_data_in;
output [25:0] data_out_io ; // output to vuad dp.
output [25:0] array_data_in_buf_top;
output [25:0] array_data_in_buf_bottom;
input [3:0] mux_sel; // 4-1 mux output to vuad dp.
assign array_data_in_buf_top = array_data_in ; // use a 40x buffer
assign array_data_in_buf_bottom = array_data_in ; // use another 40x buffer
mux4ds #(26) mux_data_out_io (.dout (data_out_io[25:0]),
.in0(data_out_col1[25:0]),
.in1(data_out_col2[25:0]),
.in2(data_out_col3[25:0]),
.in3(data_out_col4[25:0]),
.sel0(mux_sel[0]),
.sel1(mux_sel[1]),
.sel2(mux_sel[2]),
.sel3(mux_sel[3]));
endmodule
|
/*
* Copyright (C) 2007 Onno Kortmann <>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
*/
/*
Bare simulavrxx AVR<->verilog interface 'testbench' without using any of
the gluecode in avr.v
*/
`timescale 1ns / 1ns
module test;
integer hd;
reg clk;
initial begin
// $display("%h",dfdf);
$dumpfile("baretest.vcd");
$dumpvars(0, test);
hd=8'h01;
#1 hd=8'h02;
#1 hd=8'h03;
hd=$avr_create("at90s4433", "toggle.elf");
$avr_reset(hd);
#100_000 $avr_destroy(hd);
$finish;
end
integer val;
// Pin state LOW is zero
wire pb0=val!=1'b0;
always @(posedge clk) begin
#10 $avr_tick(hd);
#10 val=$avr_get_pin(hd, "B0");
end
always begin
#125 clk<=0; //125000 -> 4MHz clock
#125 clk<=1;
end
endmodule // test
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); vector<long long> tmp; int n, k; cin >> n >> k; long long mas[n], ans = 0; for (int i = 0; i < (int)(n); ++i) cin >> mas[i]; vector<pair<long long, long long> > ext; string s; cin >> s; for (int i = 0; i < (int)(s.length()); ++i) { ext.push_back(make_pair(mas[i], s[i])); } for (long long i = 0; i < s.length(); i++) { long long start = i, loop = k; while (s[i] == s[i + 1] && i < s.length() - 1) i++; for (long long j = start; j <= i; j++) { tmp.push_back(ext[j].first); } sort(tmp.begin(), tmp.end()); for (long long i = tmp.size() - 1; i >= 0; i--) { ans += tmp[i]; loop--; if (loop <= 0) break; } tmp.clear(); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, x; cin >> n >> x; int arr[n + 5], brr[n + 5]; for (int i = 0; i < n; i++) { cin >> arr[i]; } for (int i = 0; i < n; i++) { cin >> brr[i]; } sort(arr, arr + n); sort(brr, brr + n, greater<int>()); int f = 1; for (int i = 0; i < n; i++) { if (arr[i] + brr[i] > x) { f = 0; break; } } if (f == 1) { cout << YES << endl; } else { cout << NO << endl; } if (t != 0) { cout << endl; } } return 0; } |
//-----------------------------------------------------------------------------
// File : spi_slave.v
// Creation date : 10.04.2017
// Creation time : 16:16:13
// Description : A minimalistic example for SPI slave IP-XACT document.
// Created by : TermosPullo
// Tool : Kactus2 3.4.20 32-bit
// Plugin : Verilog generator 2.0d
// This file was generated based on IP-XACT component tut.fi:template:spi_slave:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/template/spi_slave/1.0/spi_slave.1.0.xml
//-----------------------------------------------------------------------------
module spi_slave #(
parameter SLAVE_ID = 0
) (
// Interface: slave_if
input clk_in,
input data_in,
input slave_select_in,
output reg data_out,
// These ports are not in any interface
input rst_in // General reset, independent from master.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
localparam BYTE_SIZE = 8; // How many bits are transferred per transaction
localparam BYTE_INDEX_SIZE = $clog2(BYTE_SIZE); // How many bits are needed to index a byte.
// Input and output bytes.
reg [BYTE_SIZE-1:0] data_recv;
reg [BYTE_SIZE-1:0] data_send;
// Used to iterate through the bytes.
reg [BYTE_INDEX_SIZE-1:0] send_iterator;
reg [BYTE_INDEX_SIZE-1:0] recv_iterator;
reg transferring;
reg transferred;
always @(posedge clk_in or posedge rst_in) begin
if(rst_in == 1'b1) begin
data_recv <= 0;
data_send <= 8'hAA;
send_iterator <= 1;
recv_iterator <= 0;
data_out <= 1'bz;
transferring <= 1;
transferred <= 0;
end
else begin
if (transferring == 1'b0) begin
data_out <= data_send[send_iterator];
if (!transferred) begin
data_recv[recv_iterator] <= data_in;
recv_iterator <= recv_iterator + 1;
end
else
data_send <= data_recv;
if (send_iterator < BYTE_SIZE - 1) begin
send_iterator <= send_iterator + 1;
end
if (recv_iterator >= BYTE_SIZE - 1) begin
transferred <= 1;
end
end
else begin
if (slave_select_in == 1'b0) begin
data_out <= data_send[0];
transferred <= 0;
send_iterator <= 1;
recv_iterator <= 0;
end
else begin
data_out <= 1'bz;
end
end
transferring <= slave_select_in;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; long long rev2 = (mod + 1) / 2; long long mas[300300]; long long pow2[300300]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %lld , &mas[i]); sort(mas, mas + n); pow2[0] = 1; for (int i = 1; i < 300300; i++) pow2[i] = (pow2[i - 1] * 2LL) % mod; for (int i = 1; i < n; i++) { mas[i] -= mas[0]; } mas[0] = 0; long long sum = 0; long long mn = 1; for (int i = 1; i < n; i++) { sum += mas[i] * mn; sum %= mod; mn *= 2; mn %= mod; } long long res = 0; for (int i = 1; i < n; i++) { res += sum; res %= mod; sum -= (mas[i] - mas[i - 1]); sum %= mod; if (sum < 0) sum += mod; sum *= rev2; sum %= mod; sum -= (long long)(pow2[n - i - 1] - 1) * (mas[i] - mas[i - 1]); sum %= mod; if (sum < 0) sum += mod; } printf( %lld , res); return 0; } |
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH UST
// Engineer: Wojciech Gredel, Hubert Górowski
//
// Create Date:
// Design Name:
// Module Name: Clouds
// Project Name: DOS_Mario
// Target Devices: Basys3
// Tool versions: Vivado 2016.1
// Description:
// This module displays clouds
//
// Dependencies:
//
// Revision:
// Revision 0.01 - Module created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Clouds (
input wire clk,
input wire rst,
input wire [9:0] xoffset,
input wire [9:0] hcount_in,
input wire hsync_in,
input wire [9:0] vcount_in,
input wire vsync_in,
input wire [23:0] rgb_in,
input wire blnk_in,
output reg [9:0] hcount_out,
output reg hsync_out,
output reg [9:0] vcount_out,
output reg vsync_out,
output reg [23:0] rgb_out,
output reg blnk_out
);
localparam MAX_CLOUDS = 11;
localparam YOFFSET = 100;
localparam XRES = 640;
localparam YRES = 480;
localparam CLOUD_COLOR = 24'h88_99_cc;
localparam reg [10:0] CLOUD_MAP_X [0:10] = { 30, 90, 180, 220, 320, 450, 530, 590, 615, 0, 0};
localparam reg [10:0] CLOUD_MAP_Y [0:10] = {100,100, 100, 100, 50, 70, 100, 100, 80, 0, 0};
localparam reg [10:0] CLOUD_MAP_S [0:10] = { 30, 70, 25, 50, 100, 70, 25, 50, 40, 0, 0};
reg [23:0] rgb_nxt;
reg [3:0] i;
reg [10:0] xpos;
always @(posedge clk or posedge rst) begin
if(rst) begin
hcount_out <= #1 0;
hsync_out <= #1 0;
vcount_out <= #1 0;
vsync_out <= #1 0;
rgb_out <= #1 0;
blnk_out <= #1 0;
end
else begin
hcount_out <= #1 hcount_in;
hsync_out <= #1 hsync_in;
vcount_out <= #1 vcount_in;
vsync_out <= #1 vsync_in;
rgb_out <= #1 rgb_nxt;
blnk_out <= #1 blnk_in;
end
end
always @* begin
xpos = (hcount_in + xoffset) % (XRES - 1);
end
always @* begin
if((YRES -1 - vcount_in) < YOFFSET ) rgb_nxt = CLOUD_COLOR;
else begin
//REQUIRES CHANGE BECAUSE OF TAKING TOO MUCH LUTS AND DSP, IT IS JUST CIRCLE EQUATION
if(((xpos - CLOUD_MAP_X[0])*(xpos - CLOUD_MAP_X[0]) + (YRES -1 - vcount_in - CLOUD_MAP_Y[0])*(YRES -1 - vcount_in - CLOUD_MAP_Y[0]))< CLOUD_MAP_S[0]*CLOUD_MAP_S[0]) rgb_nxt = CLOUD_COLOR;
else if(((xpos - CLOUD_MAP_X[1])*(xpos - CLOUD_MAP_X[1]) + (YRES -1 - vcount_in - CLOUD_MAP_Y[1])*(YRES -1 - vcount_in - CLOUD_MAP_Y[1]))< CLOUD_MAP_S[1]*CLOUD_MAP_S[1]) rgb_nxt = CLOUD_COLOR;
else if(((xpos - CLOUD_MAP_X[2])*(xpos - CLOUD_MAP_X[2]) + (YRES -1 - vcount_in - CLOUD_MAP_Y[2])*(YRES -1 - vcount_in - CLOUD_MAP_Y[2]))< CLOUD_MAP_S[2]*CLOUD_MAP_S[2]) rgb_nxt = CLOUD_COLOR;
else if(((xpos - CLOUD_MAP_X[3])*(xpos - CLOUD_MAP_X[3]) + (YRES -1 - vcount_in - CLOUD_MAP_Y[3])*(YRES -1 - vcount_in - CLOUD_MAP_Y[3]))< CLOUD_MAP_S[3]*CLOUD_MAP_S[3]) rgb_nxt = CLOUD_COLOR;
else if(((xpos - CLOUD_MAP_X[4])*(xpos - CLOUD_MAP_X[4]) + (YRES -1 - vcount_in - CLOUD_MAP_Y[4])*(YRES -1 - vcount_in - CLOUD_MAP_Y[4]))< CLOUD_MAP_S[4]*CLOUD_MAP_S[4]) rgb_nxt = CLOUD_COLOR;
else if(((xpos - CLOUD_MAP_X[5])*(xpos - CLOUD_MAP_X[5]) + (YRES -1 - vcount_in - CLOUD_MAP_Y[5])*(YRES -1 - vcount_in - CLOUD_MAP_Y[5]))< CLOUD_MAP_S[5]*CLOUD_MAP_S[5]) rgb_nxt = CLOUD_COLOR;
else if(((xpos - CLOUD_MAP_X[6])*(xpos - CLOUD_MAP_X[6]) + (YRES -1 - vcount_in - CLOUD_MAP_Y[6])*(YRES -1 - vcount_in - CLOUD_MAP_Y[6]))< CLOUD_MAP_S[6]*CLOUD_MAP_S[6]) rgb_nxt = CLOUD_COLOR;
else if(((xpos - CLOUD_MAP_X[7])*(xpos - CLOUD_MAP_X[7]) + (YRES -1 - vcount_in - CLOUD_MAP_Y[7])*(YRES -1 - vcount_in - CLOUD_MAP_Y[7]))< CLOUD_MAP_S[7]*CLOUD_MAP_S[7]) rgb_nxt = CLOUD_COLOR;
else if(((xpos - CLOUD_MAP_X[8])*(xpos - CLOUD_MAP_X[8]) + (YRES -1 - vcount_in - CLOUD_MAP_Y[8])*(YRES -1 - vcount_in - CLOUD_MAP_Y[8]))< CLOUD_MAP_S[8]*CLOUD_MAP_S[8]) rgb_nxt = CLOUD_COLOR;
else if(((xpos - CLOUD_MAP_X[9])*(xpos - CLOUD_MAP_X[9]) + (YRES -1 - vcount_in - CLOUD_MAP_Y[9])*(YRES -1 - vcount_in - CLOUD_MAP_Y[9]))< CLOUD_MAP_S[9]*CLOUD_MAP_S[9]) rgb_nxt = CLOUD_COLOR;
else rgb_nxt = rgb_in;
end
end
endmodule
|
/*
:Project
FPGA-Imaging-Library
:Design
FrameController2
:Function
Controlling a frame(block ram etc.), writing or reading with counts.
For controlling a BlockRAM from xilinx.
Give the first output after mul_delay + 2 + ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-25
Copyright (C) 2015 Tianyu Dai (dtysky) <>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController2(
clk,
rst_n,
in_count_x,
in_count_y,
in_enable,
in_data,
out_ready,
out_data,
ram_addr);
/*
::description
This module's working mode.
::range
0 for Pipline, 1 for Req-ack
*/
parameter work_mode = 0;
/*
::description
This module's WR mode.
::range
0 for Write, 1 for Read
*/
parameter wr_mode = 0;
/*
::description
Data bit width.
*/
parameter data_width = 8;
/*
::description
Width of image.
::range
1 - 4096
*/
parameter im_width = 320;
/*
::description
Height of image.
::range
1 - 4096
*/
parameter im_height = 240;
/*
::description
The bits of width of image.
::range
Depend on width of image
*/
parameter im_width_bits = 9;
/*
::description
Address bit width of a ram for storing this image.
::range
Depend on im_width and im_height.
*/
parameter addr_width = 17;
/*
::description
RL of RAM, in xilinx 7-series device, it is 2.
::range
0 - 15, Depend on your using ram.
*/
parameter ram_read_latency = 2;
/*
::description
Delay for multiplier.
::range
Depend on your multilpliers' configurations
*/
parameter mul_delay = 3;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Input pixel count for width.
*/
input[im_width_bits - 1 : 0] in_count_x;
/*
::description
Input pixel count for height.
*/
input[im_width_bits - 1 : 0] in_count_y;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [data_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output[data_width - 1 : 0] out_data;
/*
::description
Address for ram.
*/
output[addr_width - 1 : 0] ram_addr;
reg[3 : 0] con_enable;
reg[im_width_bits - 1 : 0] reg_in_count_x;
reg[im_width_bits - 1 : 0] reg_in_count_y;
reg[addr_width - 1 : 0] reg_addr;
wire[11 : 0] mul_a, mul_b;
wire[23 : 0] mul_p;
assign mul_a = {{(12 - im_width_bits){1'b0}}, in_count_y};
assign mul_b = im_width;
genvar i;
generate
/*
::description
Multiplier for Unsigned 12bits x Unsigned 12bits, used for creating address for frame.
You can configure the multiplier by yourself, then change the "mul_delay".
You can not change the ports' configurations!
*/
Multiplier12x12FR2 Mul(.CLK(clk), .A(mul_a), .B(mul_b), .SCLR(~rst_n), .P(mul_p));
for (i = 0; i < mul_delay; i = i + 1) begin : conut_buffer
reg[im_width_bits - 1 : 0] b;
if(i == 0) begin
always @(posedge clk)
b <= in_count_x;
end else begin
always @(posedge clk)
b <= conut_buffer[i - 1].b;
end
end
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable) begin
reg_addr <= 0;
end else begin
reg_addr <= mul_p + conut_buffer[mul_delay - 1].b;
end
end
assign ram_addr = reg_addr;
if(wr_mode == 0) begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_enable <= 0;
else if(con_enable == mul_delay + 1)
con_enable <= con_enable;
else
con_enable <= con_enable + 1;
end
assign out_ready = con_enable == mul_delay + 1 ? 1 : 0;
if(work_mode == 0) begin
for (i = 0; i < mul_delay + 1; i = i + 1) begin : buffer
reg[data_width - 1 : 0] b;
if(i == 0) begin
always @(posedge clk)
b <= in_data;
end else begin
always @(posedge clk)
b <= buffer[i - 1].b;
end
end
assign out_data = out_ready ? buffer[mul_delay].b : 0;
end else begin
reg[data_width - 1 : 0] reg_out_data;
always @(posedge in_enable)
reg_out_data = in_data;
assign out_data = out_ready ? reg_out_data : 0;
end
end else begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_enable <= 0;
else if (con_enable == mul_delay + 1 + ram_read_latency)
con_enable <= con_enable;
else
con_enable <= con_enable + 1;
end
assign out_data = out_ready ? in_data : 0;
assign out_ready = con_enable == mul_delay + 1 + ram_read_latency ? 1 : 0;
end
endgenerate
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFSTP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__DFSTP_PP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFSTP_PP_BLACKBOX_V
|
//======================================================================
//
// online_tester.v
// ---------------
// Top level module in online random number generator tester.
// The module is basically a framework for instatiating and using
// specific test modules.
//
// The tests implemented are basically AIS31 with some additions.
// For more info, see the specific test modules.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2015 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module online_tester(
// Clock and reset.
input wire clk,
input wire reset_n,
// Control.
input wire cs,
input wire we,
// Data ports.
input wire [7 : 0] address,
input wire [31 : 0] write_data,
output wire [31 : 0] read_data,
output wire ready,
output wire warning,
output wire error
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam ADDR_NAME0 = 8'h00;
localparam ADDR_NAME1 = 8'h01;
localparam ADDR_VERSION = 8'h02;
localparam CORE_NAME0 = 32'h6f6c5f74; // "ol_t"
localparam CORE_NAME1 = 32'h65737420; // "est "
localparam CORE_VERSION = 32'h302e3130; // "0.10"
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Instantiations.
//----------------------------------------------------------------
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
end
else
begin
end
end // reg_update
endmodule // online_tester
//======================================================================
// EOF online_tester.v
//======================================================================
|
#include <bits/stdc++.h> template <class T> using pt = std::pair<T, T>; using namespace std; struct poledia { int lx, ly, rx, ry; int cnt = 0; poledia() : lx(- -1e9), ly(- -1e9), ry(-1e9), rx(-1e9){}; poledia(bool is_dw) : lx(- -1e9), ly(-1e9), ry(- -1e9), rx(-1e9){}; }; struct poleos { int x1, y1, x2, y2; int cnt = 0; poleos() : x1(0), x2(0), y1(-1e9), y2(- -1e9){}; poleos(bool is_vert) : x1(- -1e9), x2(-1e9), y1(0), y2(0){}; }; struct ferz { int x, y; }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; vector<ferz> a(m); vector<poledia> diag1(2 * 1e5 + 1); vector<poledia> diag2(2 * 1e5 + 1); vector<poleos> ossx(1e5 + 1); vector<poleos> ossy(1e5 + 1); for (int i = 0; i < m; i++) { cin >> a[i].x >> a[i].y; int k = a[i].x + a[i].y - 1; if (diag1[k].cnt == 0) { diag1[k] = poledia(true); } diag1[k].lx = min(a[i].x, diag1[k].lx); diag1[k].ly = max(a[i].y, diag1[k].ly); diag1[k].rx = max(a[i].x, diag1[k].rx); diag1[k].ry = min(a[i].y, diag1[k].ry); diag1[k].cnt++; k = n - a[i].x + a[i].y; diag2[k].lx = min(diag2[k].lx, a[i].x); diag2[k].ly = min(diag2[k].ly, a[i].y); diag2[k].rx = max(diag2[k].rx, a[i].x); diag2[k].ry = max(diag2[k].ry, a[i].y); diag2[k].cnt++; k = a[i].y; if (ossx[k].cnt == 0) { ossx[k] = poleos(true); } ossx[k].x1 = min(ossx[k].x1, a[i].x); ossx[k].x2 = max(ossx[k].x2, a[i].x); ossx[k].cnt++; k = a[i].x; ossy[k].y1 = max(ossy[k].y1, a[i].y); ossy[k].y2 = min(ossy[k].y2, a[i].y); ossy[k].cnt++; } vector<int> ans(9); for (int i = 0; i < m; i++) { int sum = 0; int k1 = a[i].x + a[i].y - 1, k2 = n - a[i].x + a[i].y; if (diag1[k1].cnt != 1) { if (a[i].x == diag1[k1].lx && a[i].y == diag1[k1].ly || a[i].x == diag1[k1].rx && a[i].y == diag1[k1].ry) sum++; else sum += 2; } if (diag2[k2].cnt != 1) { if (a[i].x == diag2[k2].lx && a[i].y == diag2[k2].ly || a[i].x == diag2[k2].rx && a[i].y == diag2[k2].ry) sum++; else sum += 2; } if (ossx[a[i].y].cnt != 1) { if (a[i].x == ossx[a[i].y].x1 || a[i].x == ossx[a[i].y].x2) sum++; else sum += 2; } if (ossy[a[i].x].cnt != 1) { if (a[i].y == ossy[a[i].x].y1 || a[i].y == ossy[a[i].x].y2) sum++; else sum += 2; } ans[sum]++; } for (int i = 0; i < 9; i++) { cout << ans[i] << ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char *argv[]) { vector<string> a; int n; cin >> n; a.resize(n); for (int i = 0; i < n; ++i) cin >> a[i]; for (int i = n - 2; i >= 0; --i) { const char *x = a[i].c_str(), *y = a[i + 1].c_str(); int j = 1; while (x[j] && x[j] == y[j]) ++j; if (x[j] > y[j]) { a[i].resize(j); } } for (string s : a) cout << s << n ; return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Tested against an IDT 71v65603s150 in simulation and a Cypress 7C1356C in the real world.
module nobl_if
#(parameter WIDTH=18,DEPTH=19)
(
input clk,
input rst,
input [WIDTH-1:0] RAM_D_pi,
output [WIDTH-1:0] RAM_D_po,
output reg RAM_D_poe,
output [DEPTH-1:0] RAM_A,
output reg RAM_WEn,
output RAM_CENn,
output RAM_LDn,
output RAM_OEn,
output reg RAM_CE1n,
input [DEPTH-1:0] address,
input [WIDTH-1:0] data_out,
output reg [WIDTH-1:0] data_in,
output reg data_in_valid,
input write,
input enable
);
reg enable_pipe1;
reg [DEPTH-1:0] address_pipe1;
reg write_pipe1;
reg [WIDTH-1:0] data_out_pipe1;
reg enable_pipe2;
reg write_pipe2;
reg [WIDTH-1:0] data_out_pipe2;
reg enable_pipe3;
reg write_pipe3;
reg [WIDTH-1:0] data_out_pipe3;
assign RAM_LDn = 0;
// ZBT/NoBL RAM actually manages its own output enables very well.
assign RAM_OEn = 0;
// gray code the address to reduce EMI
wire [DEPTH-1:0] address_gray;
bin2gray #(.WIDTH(DEPTH)) bin2gray (.bin(address),.gray(address_gray));
//
// Pipeline stage 1
//
always @(posedge clk)
if (rst)
begin
enable_pipe1 <= 0;
address_pipe1 <= 0;
write_pipe1 <= 0;
data_out_pipe1 <= 0;
RAM_WEn <= 1;
RAM_CE1n <= 1;
end
else
begin
enable_pipe1 <= enable;
RAM_CE1n <= ~enable; // Creates IOB flop
RAM_WEn <= ~write; // Creates IOB flop
if (enable)
begin
address_pipe1 <= address_gray;
write_pipe1 <= write;
// RAM_WEn <= ~write; // Creates IOB flop
if (write)
data_out_pipe1 <= data_out;
end
end // always @ (posedge clk)
// Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM
assign RAM_A = address_pipe1;
assign RAM_CENn = 1'b0;
// assign RAM_WEn = ~write_pipe1;
// assign RAM_CE1n = ~enable_pipe1;
//
// Pipeline stage2
//
always @(posedge clk)
if (rst)
begin
enable_pipe2 <= 0;
data_out_pipe2 <= 0;
write_pipe2 <= 0;
end
else
begin
data_out_pipe2 <= data_out_pipe1;
write_pipe2 <= write_pipe1;
enable_pipe2 <= enable_pipe1;
end
//
// Pipeline stage3
//
always @(posedge clk)
if (rst)
begin
enable_pipe3 <= 0;
data_out_pipe3 <= 0;
write_pipe3 <= 0;
RAM_D_poe <= 0;
end
else
begin
data_out_pipe3 <= data_out_pipe2;
write_pipe3 <= write_pipe2;
enable_pipe3 <= enable_pipe2;
RAM_D_poe <= ~(write_pipe2 & enable_pipe2); // Active low driver enable in Xilinx.
end
// Pipeline 3 drives write data on NoBL SRAM
assign RAM_D_po = data_out_pipe3;
//
// Pipeline stage4
//
always @(posedge clk)
if (rst)
begin
data_in_valid <= 0;
data_in <= 0;
end
else
begin
data_in <= RAM_D_pi;
if (enable_pipe3 & ~write_pipe3)
begin
// Read data now available to be registered.
data_in_valid <= 1'b1;
end
else
data_in_valid <= 1'b0;
end // always @ (posedge clk)
endmodule // nobl_if
|
/////////////////////////////////////////////////////////////////////
//// ////
//// JPEG Quantization & Rounding Core ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: jpeg_qnr.v,v 1.3 2002/10/31 12:52:55 rherveille Exp $
//
// $Date: 2002/10/31 12:52:55 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: jpeg_qnr.v,v $
// Revision 1.3 2002/10/31 12:52:55 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:07:03 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module jpeg_qnr(clk, ena, rst, dstrb, din, qnt_val, qnt_cnt, dout, douten);
//
// parameters
//
parameter d_width = 12;
parameter z_width = 2 * d_width;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input rst; // asynchronous active low reset
input dstrb; // present dstrb 1clk cycle before din
input [d_width-1:0] din; // data input
input [ 7:0] qnt_val; // quantization value
output [ 5:0] qnt_cnt; // sample number (get quantization value qnt_cnt)
output [10:0] dout; // data output
output douten;
//
// variables
//
wire [z_width-1:0] iz; // intermediate divident value
wire [d_width-1:0] id; // intermediate dividor value
wire [d_width :0] iq; // intermediate result divider
reg [d_width :0] rq; // rounded q-value
reg [d_width+3:0] dep;// data enable pipeline
// generate sample counter
reg [5:0] qnt_cnt;
wire dcnt = &qnt_cnt;
always @(posedge clk or negedge rst)
if (~rst)
qnt_cnt <= #1 6'h0;
else if (dstrb)
qnt_cnt <= #1 6'h0;
else if (ena)
qnt_cnt <= #1 qnt_cnt + 6'h1;
// generate intermediate dividor/divident values
assign id = { {(d_width - 8){1'b0}}, qnt_val};
assign iz = { {(z_width - d_width){din[d_width-1]}}, din};
// hookup division unit
div_su #(z_width)
divider (
.clk(clk),
.ena(ena),
.z(iz),
.d(id),
.q(iq),
.s(),
.div0(),
.ovf()
);
// round result to the nearest integer
always @(posedge clk)
if (ena)
if (iq[0])
if (iq[d_width])
rq <= #1 iq - 1'h1;
else
rq <= #1 iq + 1'h1;
else
rq <= #1 iq;
// assign dout signal
assign dout = rq[d_width -1: d_width-11];
// generate data-out enable signal
// This is a pipeline, data is not dependant on sample-count
integer n;
always @(posedge clk or negedge rst)
if (!rst)
dep <= #1 0;
else if(ena)
begin
dep[0] <= #1 dstrb;
for (n=1; n <= d_width +3; n = n +1)
dep[n] <= #1 dep[n-1];
end
assign douten = dep[d_width +3];
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, nrE; struct Dish { int p, s, b; } d[100002]; struct Person { int inc, pref; } v[100002]; struct Event { int x, y, z, t; bool operator<(const Event &ot) const { if (x == ot.x) return z > ot.z; return x < ot.x; } } E[100002 * 3]; unordered_map<int, int> Bit[2]; int ans[100002]; void Add(int t, int i, int val) { for (; i < 2 * 1000000005 && i > 0; i += (i & (-i))) Bit[t][i] += val; } int Sum(int t, int i) { int ret = 0; for (; i > 0; i -= (i & (-i))) ret += Bit[t][i]; return ret; } void readDish() { for (int i = 0; i < n; ++i) scanf( %d , &d[i].p); for (int i = 0; i < n; ++i) scanf( %d , &d[i].s); for (int i = 0; i < n; ++i) scanf( %d , &d[i].b); } void readPers() { for (int i = 0; i < m; ++i) scanf( %d , &v[i].inc); for (int i = 0; i < m; ++i) scanf( %d , &v[i].pref); } void solveEvents() { sort(E, E + nrE); for (int i = 0; i < nrE; ++i) { if (E[i].z <= 0) { int idx = -E[i].z; ans[idx] = Sum(0, v[idx].inc + v[idx].pref) + Sum(1, v[idx].pref - v[idx].inc + 1000000005); } else { Add(0, E[i].x + E[i].y, 1 * E[i].t); Add(1, E[i].z - E[i].x + 1000000005, -1 * E[i].t); } } } int main() { scanf( %d%d , &n, &m); readDish(); readPers(); for (int i = 0; i < n + m; ++i) { if (i < n) { E[nrE++] = {d[i].p, d[i].b, d[i].b + 1, 1}; E[nrE++] = {d[i].s + 1, d[i].b - (d[i].s - d[i].p + 1), d[i].b + (d[i].s - d[i].p + 1) + 1, -1}; } else E[nrE++] = {v[i - n].inc, v[i - n].pref, n - i, 0}; } solveEvents(); for (int i = 0; i < m; ++i) printf( %d , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> bool chmax(T &a, const T &b) { if (a < b) { a = b; return 1; } return 0; } template <class T> bool chmin(T &a, const T &b) { if (a > b) { a = b; return 1; } return 0; } template <class T> ostream &operator<<(ostream &os, const vector<T> &t) { os << [ ; for (__typeof((t).begin()) it = (t).begin(); it != (t).end(); it++) { if (it != t.begin()) os << , ; os << *it; } os << ] ; return os; } template <class T> ostream &operator<<(ostream &os, const set<T> &t) { os << { ; for (__typeof((t).begin()) it = (t).begin(); it != (t).end(); it++) { if (it != t.begin()) os << , ; os << *it; } os << } ; return os; } template <class S, class T> ostream &operator<<(ostream &os, const pair<S, T> &t) { return os << ( << t.first << , << t.second << ) ; } template <class S, class T> pair<S, T> operator+(const pair<S, T> &s, const pair<S, T> &t) { return pair<S, T>(s.first + t.first, s.second + t.second); } template <class S, class T> pair<S, T> operator-(const pair<S, T> &s, const pair<S, T> &t) { return pair<S, T>(s.first - t.first, s.second - t.second); } const int INF = 1 << 28; const double EPS = 1e-8; const int MOD = 1000000007; int n, m, t; int main() { ios::sync_with_stdio(0); cin.tie(0); scanf( %d%d%d , &n, &m, &t); deque<pair<int, int> > ends; int ans = 0, accept = 0; vector<int> idxs(n); for (int i = 0; i < (int)(n); i++) { int h, mm, s, x; scanf( %d:%d:%d , &h, &mm, &s); x = h * 3600 + mm * 60 + s; while (!ends.empty() && ends.front().first <= x) { idxs[ends.front().second] = 1; ans++; ends.pop_front(); } ends.emplace_back(x + t, i); if (ends.size() == m) accept = 1; while (ends.size() > m) { idxs[ends.back().second] = 0; ends.pop_back(); ends.back().first = x + t; } } while (!ends.empty()) { idxs[ends.back().second] = 1; ans++; ends.pop_back(); } if (!accept) { puts( No solution ); return 0; } int sum = 0; printf( %d n , ans); for (int i = 0; i < (int)(n); i++) printf( %d n , sum += idxs[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; char gc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } inline int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = (x << 3) + (x << 1) + ch - 0 , ch = getchar(); return x * f; } inline long long readll() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = (x << 3) + (x << 1) + ch - 0 , ch = getchar(); return x * f; } inline void write(int x) { if (!x) putchar( 0 ); if (x < 0) x = -x, putchar( - ); static int sta[20]; register int tot = 0; while (x) sta[tot++] = x % 10, x /= 10; while (tot) putchar(sta[--tot] + 48); } const int maxn = 2007, INF = 0x3f3f3f3f; const int MOD = 998244353; const long long LINF = 0x3f3f3f3f3f3f3f3fll; const long long P = 19260817; inline int mod1(int x) { return x < MOD ? x : x - MOD; } inline int mod2(int x) { return x < 0 ? x + MOD : x; } inline void add(int &x, int y) { x = mod1(x + y); } inline void sub(int &x, int y) { x = mod2(x - y); } struct node { int x, y, dis; friend bool operator<(const node &a, const node &b) { if (a.dis != b.dis) return a.dis < b.dis; if (a.x != b.x) return a.x < b.x; return a.y < b.y; } }; inline void chkmin(node &a, node b) { a = min(a, b); } int n, m, K; int fal[maxn][maxn]; int far[maxn][maxn]; int fau[maxn][maxn]; int fad[maxn][maxn]; int find(int x, int *fa) { return x == fa[x] ? x : fa[x] = find(fa[x], fa); } void solve(int x, int y) { if (fal[x][y] == y) { printf( %d %d n , x, y); fal[x][y] = y - 1; far[x][y] = y + 1; fau[y][x] = x - 1; fad[y][x] = x + 1; return; } node ans = (node){0, 0, INF}; for (int i = x; i <= min(x + (int)sqrt(K), n); i++) { int t = y; t = find(t, fal[i]); if (t) chkmin(ans, (node){i, t, abs(i - x) + abs(t - y)}); t = y; t = find(t, far[i]); if (t) chkmin(ans, (node){i, t, abs(i - x) + abs(t - y)}); if (y == fal[i][y]) break; } for (int i = x; i >= max(x - (int)sqrt(K), 1); i--) { int t = y; t = find(t, fal[i]); if (t) chkmin(ans, (node){i, t, abs(i - x) + abs(t - y)}); t = y; t = find(t, far[i]); if (t) chkmin(ans, (node){i, t, abs(i - x) + abs(t - y)}); if (y == fal[i][y]) break; } for (int i = y; i <= min(y + (int)sqrt(K), m); i++) { int t = x; t = find(t, fau[i]); if (t) chkmin(ans, (node){t, i, abs(t - x) + abs(i - y)}); t = x; t = find(t, fad[i]); if (t) chkmin(ans, (node){t, i, abs(t - x) + abs(i - y)}); if (x == fau[i][x]) break; } for (int i = y; i >= max(y - (int)sqrt(K), 1); i--) { int t = x; t = find(t, fau[i]); if (t) chkmin(ans, (node){t, i, abs(t - x) + abs(i - y)}); t = x; t = find(t, fad[i]); if (t) chkmin(ans, (node){t, i, abs(t - x) + abs(i - y)}); if (x == fau[i][x]) break; } printf( %d %d n , ans.x, ans.y); fal[ans.x][ans.y] = ans.y - 1; far[ans.x][ans.y] = ans.y + 1; fau[ans.y][ans.x] = ans.x - 1; fad[ans.y][ans.x] = ans.x + 1; } int main() { scanf( %d%d%d , &n, &m, &K); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { fal[i][j] = j, far[i][j] = j; fau[j][i] = i, fad[j][i] = i; } } for (int i = 1, x, y; i <= K; i++) { scanf( %d%d , &x, &y); solve(x, y); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMBOL_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMBOL_V
/**
* lsbuflv2hv: Level-shift buffer, low voltage-to-high voltage,
* isolated well on input buffer, double height cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbuflv2hv (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMBOL_V
|
#include <iostream> using namespace std; int main() { long long t; cin >> t; while(t--) { long long n, s = 0, mx = 0; cin >> n; long long a[n + 1]; for(long long i = 1; i <= n; ++i){ cin >> a[i]; s += a[i]; mx = max(mx, a[i]); } cout << max((n - 1) * mx, (s + n - 2) / (n - 1) *(n - 1)) - s << n ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 23, M = 2e4 + 1e3 + 7, P = 998244353; int n; int cnt[N][26], pw[M]; char s[M]; int f[1 << N]; int mn[26]; int main() { pw[0] = 1; for (int i = 1; i < M; i++) pw[i] = pw[i - 1] * 2 % P; scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %s , s); int m = strlen(s); for (int j = 0; j < m; j++) cnt[i][s[j] - a ]++; } for (int S = 1; S < (1 << n); S++) { for (int j = 0; j < 26; j++) mn[j] = 1e9; int flag = P - 1; for (int i = 0; i < n; i++) if (S & (1 << i)) { flag = P - flag; for (int j = 0; j < 26; j++) mn[j] = min(mn[j], cnt[i][j]); } f[S] = flag; for (int i = 0; i < 26; i++) f[S] = 1ll * f[S] * (mn[i] + 1) % P; } for (int i = 0; i < n; i++) for (int S = 0; S < (1 << n); S++) if (S & (1 << i)) f[S] = (f[S] + f[S ^ (1 << i)]) % P; long long ans = 0; for (int S = 0; S < (1 << n); S++) { int b = 0, a = 0; for (int i = 0; i < n; i++) if (S & (1 << i)) b++, a += i + 1; ans ^= 1ll * a * b * f[S]; } printf( %lld n , ans); } |
#include <bits/stdc++.h> using namespace std; double cal(int n, int *a, double x) { double ret = 0, t1 = 0, t2 = 0; for (int i = 0; i < n; i++) { t1 += a[i] - x; t2 += a[i] - x; t1 = max(0., t1); t2 = min(0., t2); ret = max(ret, t1); ret = max(ret, -t2); } return ret; } int main() { int n; scanf( %d , &n); static int a[200000]; for (int i = 0; i < n; i++) { scanf( %d , a + i); } double l = -10001, r = 10001, ans; for (int t = 0; t < 100; t++) { double d1 = (2 * l + r) / 3, d2 = (l + 2 * r) / 3; double e1 = cal(n, a, d1), e2 = cal(n, a, d2); if (e1 <= e2) { r = d2; ans = e1; } else { l = d1; ans = e2; } } printf( %.9lf n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR2B_BLACKBOX_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor2b (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o22ai (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire nor1_out ;
wire or0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y, nor1_out, nor0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O22AI_BEHAVIORAL_V |
`default_nettype none
`timescale 1ns / 1ps
module oled_spi(
input wire clock,
input wire reset,
input wire shutdown,
output wire cs,
output reg sdin,
output wire sclk,
output reg dc,
output reg res,
output reg vbatc,
output reg vddc
);
parameter WAIT = 1;
parameter SEND = 2; // send 1 byte
parameter SEND2 = 3; // send 2 bytes
parameter SEND3 = 4; // send 3 bytes
parameter SEND4 = 5; // send 4 bytes
parameter STARTUP_1 = 10;
parameter STARTUP_2 = 11;
parameter STARTUP_3 = 12;
parameter STARTUP_4 = 13;
parameter STARTUP_5 = 14;
parameter STARTUP_6 = 15;
parameter STARTUP_7 = 16;
parameter STARTUP_8 = 17;
parameter STARTUP_9 = 18;
parameter SHUTDOWN_1 = 6;
parameter SHUTDOWN_2 = 7;
parameter SHUTDOWN_3 = 8;
reg [31:0] send_buf;
reg [4:0] send_idx;
reg [1:0] send_ctr;
reg [1:0] send_max;
reg [31:0] wait_ctr;
reg [31:0] wait_max;
// TODO probably don't need 7 bits for state
reg [7:0] state;
reg [7:0] next_state;
always @(posedge clock) begin
// RESET
if (reset) begin
send_buf <= 32'b0;
send_idx <= 5'b0;
send_ctr <= 2'b0;
send_max <= 2'b0;
wait_ctr <= 32'b0;
wait_max <= 32'b0;
state <= STARTUP_1;
next_state <= 1'b0;
sdin <= 1'b0;
dc <= 1'b0;
res <= 1'b1;
vddc <= 1'b1;
vbatc <= 1'b1;
end
// SHUTDOWN
else if (shutdown) begin
if (state > 0 && state < 10) begin
next_state <= SHUTDOWN_1;
end else begin
state <= SHUTDOWN_1;
end
end
// STATES
else begin
// SEND - send up to four serial bytes
if (state == SEND) begin
sdin <= send_buf[(7 - send_idx) + (8 * send_ctr)];
if (send_idx == 7 && send_ctr == send_max) begin
send_idx <= 0;
send_ctr <= 0;
send_max <= 0;
state <= next_state;
end else if (send_idx == 7) begin
send_idx <= 0;
send_ctr <= send_ctr + 1;
end else begin
send_idx <= send_idx + 1;
end
end
// SEND2 - send two bytes
if (state == SEND2) begin
send_max = 1;
state <= SEND;
end
// SEND3 - send three bytes
else if (state == SEND3) begin
send_max = 2;
state <= SEND;
end
// SEND4 - send four bytes
else if (state == SEND4) begin
send_max = 3;
state <= SEND;
end
// WAIT - wait for # of cycles
else if (state == WAIT) begin
if (wait_ctr == wait_max) begin
wait_ctr <= 0;
state <= next_state;
end else begin
wait_ctr <= wait_ctr + 1;
end
end
// STARTUP_1 -- apply power to VDD
else if (state == STARTUP_1) begin
dc <= 0;
vddc <= 0;
wait_max <= 5000; // 1ms
state <= WAIT;
next_state <= STARTUP_2;
end
// STARTUP_2 -- send display off cmd
else if (state == STARTUP_2) begin
send_buf <= 8'hAE;
state <= SEND;
next_state <= STARTUP_3;
end
// STARTUP_3 -- clear screen
else if (state == STARTUP_3) begin
res <= 0;
wait_max <= 5000; // 1ms
state <= WAIT;
next_state <= STARTUP_4;
end
// STARTUP_4 -- set charge pump
else if (state == STARTUP_4) begin
res <= 1;
send_buf <= 16'h148D;
state <= SEND2;
next_state <= STARTUP_5;
end
// STARTUP_5 -- set pre-charge period
else if (state == STARTUP_5) begin
send_buf <= 16'hF1D9;
state <= SEND2;
next_state <= STARTUP_6;
end
// STARTUP_6 -- apply power to VBAT
else if (state == STARTUP_6) begin
vbatc <= 0;
wait_max <= 500000; // 100ms
state <= WAIT;
next_state <= STARTUP_7;
end
// STARTUP_7 -- invert the display
else if (state == STARTUP_7) begin
send_buf <= 16'hC8A1;
state <= SEND2;
next_state <= STARTUP_8;
end
// STARTUP_8 -- select squential COM configuration
else if (state == STARTUP_8) begin
send_buf <= 16'h20DA;
state <= SEND2;
next_state <= STARTUP_9;
end
// STARTUP_9 -- send display on cmd
else if (state == STARTUP_9) begin
send_buf <= 8'hAF;
state <= SEND;
next_state <= 0; // TODO
end
// SHUTDOWN_1 -- send display off cmd
else if (state == SHUTDOWN_1) begin
send_buf <= 8'hAE;
state <= SEND;
next_state <= SHUTDOWN_2;
end
// SHUTDOWN_2 -- turn off VBAT
else if (state == SHUTDOWN_2) begin
vbatc <= 1;
wait_max <= 500000; // 100ms
state <= WAIT;
next_state <= SHUTDOWN_3;
end
// SHUTDOWN_4 -- turn off VDD
else if (state == SHUTDOWN_3) begin
vddc <= 1;
state <= 0; // TODO
end
end
end
assign cs = 0;
assign sclk = !clock;
endmodule
|
module snoop_adapter (
clk,
reset,
kernel_clk,
kernel_reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
snoop_data,
snoop_valid,
snoop_ready,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
localparam DEVICE_BLOCKRAM_MIN_DEPTH = 256; //Stratix IV M9Ks
localparam FIFO_SIZE = DEVICE_BLOCKRAM_MIN_DEPTH;
localparam LOG2_FIFO_SIZE =$clog2(FIFO_SIZE);
input clk;
input reset;
input kernel_clk;
input kernel_reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output [1+WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data;
output snoop_valid;
input snoop_ready;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
reg snoop_overflow;
// Register snoop data first
reg [WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data_r; //word-address
reg snoop_valid_r;
wire snoop_fifo_empty;
wire overflow;
wire [ LOG2_FIFO_SIZE-1 : 0 ] rdusedw;
always@(posedge clk)
begin
snoop_data_r<={address,export_burstcount};
snoop_valid_r<=export_write && !export_waitrequest;
end
// 1) Fifo to store snooped accesses from host
dcfifo dcfifo_component (
.wrclk (clk),
.data (snoop_data_r),
.wrreq (snoop_valid_r),
.rdclk (kernel_clk),
.rdreq (snoop_valid & snoop_ready),
.q (snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0]),
.rdempty (snoop_fifo_empty),
.rdfull (overflow),
.aclr (1'b0),
.rdusedw (rdusedw),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Stratix IV",
dcfifo_component.lpm_numwords = FIFO_SIZE,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH,
dcfifo_component.lpm_widthu = LOG2_FIFO_SIZE,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
assign snoop_valid=~snoop_fifo_empty;
always@(posedge kernel_clk)
snoop_overflow = ( rdusedw >= ( FIFO_SIZE - 12 ) );
// Overflow piggy backed onto MSB of stream. Since overflow guarantees
// there is something to be read out, we can be sure that this will reach
// the cache.
assign snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH] = snoop_overflow;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign waitrequest = export_waitrequest;
endmodule
|
`define ADDER_WIDTH 008
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NAND4B_PP_SYMBOL_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand4b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
input D ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4B_PP_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////////////////
//
// Author : Praveen Kumar Pendyala
// Create Date : 30/10/13
// Modify Date : 11/11/13
// Module Name : simpleTestModuleOne
// Project Name : DDR2_Interface_Xilinx_XUPV5
// Target Devices : Xilinx Vertix 5, XUPV5 110T
// Tool versions : 13.2 ISE
//
// Description : This module is user end code for DDR2 interfacing. The logic is in accordance with the
//timing diagram given in the references.
//
//////////////////////////////////////////////////////////////////////////////////
module ddr_interfacing(
)
wire sys_clk;
wire idly_clk_200;
wire error_cmp;
wire rst0;
wire rst90;
wire rstdiv0;
wire rst200;
wire clk0;
wire clk90;
wire clkdiv0;
wire clk200;
wire idelay_ctrl_rdy;
wire app_wdf_afull;
wire app_af_afull;
wire rd_data_valid;
wire app_wdf_wren;
wire app_af_wren;
wire [30:0] app_af_addr;
wire [2:0] app_af_cmd;
wire [(APPDATA_WIDTH)-1:0] rd_data_fifo_out;
wire [(APPDATA_WIDTH)-1:0] app_wdf_data;
wire [(APPDATA_WIDTH/8)-1:0] app_wdf_mask_data;
reg [3:0] count = 0;
always @(posedge clk0) begin
//Write to DDR
app_af_cmd <= 3'b000; //Select write mode
//Wait for app_af_afull
if(!app_af_afull) begin
case (count)
0 : app_af_addr <= 32; //Selecting an address to write data before enabling address FIFO write
1 : app_af_wren <= 1; //Assert Address FIFO write enable
2 : app_af_wren <= 0; //Disabling addresss FIFO write enable
endcase
end
//Wait for adata FIFO almost full deassertion
if(!app_wdf_afull) begin
case (count)
0 : app_wdf_data <= 32; //Get data ready before enabling data FIFO
app_wdf_mask_data <= 0x1; //Data mask. Not being used here
1 : app_wdf_wren <= 1; //Enable data FIFO write
2 : app_wdf_wren <= 0; //Disable data FIFO write
endcase
end
count <= count+1;
end
endmodule |
/*
* sobel_cache.v
*
* Created on: 09/10/2012
* Author: Lord_Rafa
*/
`timescale 1 ps / 1 ps
module Sobel_cache (
input clk,
input rst,
input start,
input [ADD_WIDTH-1:0] base_add,
input [13:0] rdaddress,
output wire [12:0] valid_lines,
input free_line,
output wire [ 7:0] q,
output wire [ADD_WIDTH-1:0] ram_r_address,
input ram_r_waitrequest,
input ram_r_readdatavalid,
output wire [BYTE_ENABLE_WIDTH-1:0] ram_r_byteenable,
output wire ram_r_read,
input [DATA_WIDTH-1:0] ram_r_readdata,
output wire [BURST_WIDTH_R-1:0] ram_r_burstcount
);
parameter DATA_WIDTH=32;
parameter ADD_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4;
parameter BURST_WIDTH_R = 6;
parameter MAX_BURST_COUNT_R = 32;
reg [ADD_WIDTH-1:0] read_address;
reg [ADD_WIDTH-1:0] write_address;
reg [12:0] used_cache_pixels;
reg [31:0] in_n;
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n <= 0;
end else begin
if (start == 1) begin
in_n <= 384000;
end else begin
if (read_burst_end == 1) begin
in_n <= in_n - MAX_BURST_COUNT_R;
end
end
end
end
always @(posedge clk) begin
if (start == 1) begin
read_address <= base_add;
end else begin
if (read_burst_end == 1) begin
read_address <= read_address + MAX_BURST_COUNT_R * BYTE_ENABLE_WIDTH;
end
end
end
// reg [ 3:0] valid;
always @(posedge clk) begin
if (start == 1) begin
used_cache_pixels <= 0;
end else begin
if (read_complete == 1) begin
if (free_line == 0) begin
used_cache_pixels <= used_cache_pixels + 1;
end else begin
used_cache_pixels <= used_cache_pixels - 799;
end
end else begin
if (free_line == 1) begin
used_cache_pixels <= used_cache_pixels - 800;
end
end
end
end
assign valid_lines = used_cache_pixels;
reg [31:0] reads_pending;
always @ (posedge clk) begin
if (start == 1) begin
reads_pending <= 0;
end else begin
if(read_burst_end == 1) begin
if(read_complete == 0) begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R;
end else begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R - 1;
end
end else begin
if(read_complete == 0) begin
reads_pending <= reads_pending;
end else begin
reads_pending <= reads_pending - 1;
end
end
end
end
reg [31:0] next_r;
always @ (posedge clk) begin
if (start == 1) begin
next_r <= 0;
end else begin
if(read_burst_end == 1) begin
next_r <= 0;
end else begin
if (ram_r_read == 1) begin
next_r <= 1;
end
end
end
end
always @(posedge clk) begin
if (start == 1) begin
write_address <= 0;
end else begin
if (read_complete == 1) begin
if (write_address == 7999) begin
write_address <= 0;
end else begin
write_address <= write_address + 1;
end
end
end
end
altsyncram altsyncram_component (
.clock0 (clk),
.data_a (ram_r_readdata[7:0]),
.address_a (write_address),
.wren_a (read_complete),
.address_b (rdaddress),
.q_b (q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.numwords_b = 8192,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 13,
altsyncram_component.widthad_b = 13,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
assign read_complete = (ram_r_readdatavalid == 1);
assign read_burst_end = (ram_r_waitrequest == 0) & (next_r == 1);
assign too_many_reads_pending = (reads_pending + used_cache_pixels) > (8000 - MAX_BURST_COUNT_R);
assign ram_r_address = read_address;
assign ram_r_read = (too_many_reads_pending == 0) & (in_n != 0);
assign ram_r_byteenable = {BYTE_ENABLE_WIDTH{1'b1}};
assign ram_r_burstcount = MAX_BURST_COUNT_R;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EINVN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__EINVN_BEHAVIORAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EINVN_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; bool EulerianPathExists(const map<string, pair<int, int>>& in_out_degrees) { int different_in_out_count = 0; for (auto& key_val : in_out_degrees) { if (key_val.second.first != key_val.second.second) { ++different_in_out_count; if (different_in_out_count > 2) return false; } } return true; } void FindEulerianPath(string v, map<string, unordered_map<string, int>>& graph, vector<string>& res) { while (!graph[v].empty()) { auto adj_pair = graph[v].begin(); auto w = adj_pair->first; --adj_pair->second; if (adj_pair->second == 0) graph[v].erase(adj_pair); FindEulerianPath(w, graph, res); } res.push_back(v); } bool UntraversedEdgesLeft( const map<string, unordered_map<string, int>>& graph) { for (auto& key_val : graph) if (!key_val.second.empty()) return true; return false; } string RestorePassword(vector<string>& path) { reverse(path.begin(), path.end()); string password = path[0]; for (int i = 1; i < path.size(); ++i) password += path[i][1]; return password; } bool CheckCornerCases(const map<string, pair<int, int>>& in_out_degree, const map<string, unordered_map<string, int>>& graph) { if (in_out_degree.size() != 2) return true; auto first_adj_pair = graph.begin()->second; if (graph.size() == 1 && first_adj_pair.begin()->second == 1) return true; int num_of_outward_edges = 0; auto v = graph.begin()->first; auto w = v; reverse(w.begin(), w.end()); if (graph.begin()->second.count(w)) num_of_outward_edges = graph.begin()->second.at(w); int num_of_inward_edges = 0; if (graph.count(w) > 0 && graph.at(w).count(v) > 0) { num_of_inward_edges = graph.at(w).at(v); } if (abs(num_of_inward_edges - num_of_outward_edges) > 1 || (!num_of_inward_edges && !num_of_outward_edges)) { return false; } return true; } int main() { map<string, unordered_map<string, int>> graph; map<string, pair<int, int>> in_out_degree; int N; cin >> N; for (int i = 0, num = 0; i < N; ++i) { string s; cin >> s; string v = s.substr(0, 2); string w = s.substr(1, 2); ++in_out_degree[v].second; ++in_out_degree[w].first; ++graph[v][w]; } bool path_exists = EulerianPathExists(in_out_degree); if (!path_exists) { cout << NO ; return 0; } if (!CheckCornerCases(in_out_degree, graph)) { cout << NO ; return 0; } vector<string> eulerian_path; auto graph_cpy = graph; for (auto& key_val : in_out_degree) { if (key_val.second.second > key_val.second.first) { FindEulerianPath(key_val.first, graph_cpy, eulerian_path); break; } } bool untraversed_edges_left = UntraversedEdgesLeft(graph_cpy); for (auto& v : graph) { graph_cpy = graph; if (eulerian_path.empty() || untraversed_edges_left) { FindEulerianPath(v.first, graph_cpy, eulerian_path); untraversed_edges_left = UntraversedEdgesLeft(graph_cpy); break; } else break; } if (eulerian_path.empty() || untraversed_edges_left) cout << NO ; else { cout << YES << endl; cout << RestorePassword(eulerian_path); } return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { ios::sync_with_stdio(false); cin.tie(0); long long int n; cin >> n; map<int, int> mp; for (int i = 0; i < n; i++) { int a; cin >> a; mp[a] = i + 1; } for (int i = 1; i <= n; i++) { cout << mp[i] << ; } } |
`timescale 1ns / 1ps
module MAC #(
parameter N = 5,
parameter PIPE = 3,
parameter WIDTH = 16,
parameter M_WIDTH = 2*WIDTH+N-1
)(
input clk,
input sof,
input [WIDTH-1:0] A,
input [WIDTH-1:0] B,
output reg [M_WIDTH-1:0] C,
output reg valid
);
reg state;
reg [7:0] n,p;
wire [2*WIDTH-1:0] O;
parameter
IDLE = 1'b0,
MAC = 1'b1;
initial begin
n <= N;
p <= PIPE;
C <= 0;
valid <= 1'b0;
state <= IDLE;
end
always@(posedge clk) begin
case(state)
IDLE: begin
p <= PIPE;
n <= N;
C <= 0;
valid <= 1'b0;
if(sof) begin
if(p > 1)
p <= p-1;
else begin// if ((p == 1) || (p ==0))
p <= 0;
state <= MAC;
end
end
end
MAC: begin
C <= C + O;
n <= n-1;
valid <= 1'b0;
if(n == 1) begin
valid <= 1'b1;
if(!sof)
state <= IDLE;
else begin
n <= N;
//C <= 0;
end
end
if(n == N)
C <= O;
end
endcase
end
MULT mult_16W (
.clk (clk), // input clk
.a (A), // input [15 : 0] a
.b (B), // input [15 : 0] b
.p (O) // output [31 : 0] p
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { float a, b, c, d; float mpts; float vpts; cin >> a >> b >> c >> d; mpts = max((3 * a) / 10, a - ((a / 250) * c)); vpts = max((3 * b) / 10, b - ((b / 250) * d)); if (mpts == vpts) { cout << Tie n ; return 0; } mpts > vpts ? cout << Misha n : cout << Vasya n ; return 0; } |
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module dmac_src_axi_stream (
input s_axis_aclk,
input s_axis_aresetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [C_ID_WIDTH-1:0] request_id,
output [C_ID_WIDTH-1:0] response_id,
input eot,
output s_axis_ready,
input s_axis_valid,
input [C_S_AXIS_DATA_WIDTH-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
input fifo_ready,
output fifo_valid,
output [C_S_AXIS_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [C_BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_sync_transfer_start
);
parameter C_ID_WIDTH = 3;
parameter C_S_AXIS_DATA_WIDTH = 64;
parameter C_LENGTH_WIDTH = 24;
parameter C_BEATS_PER_BURST_WIDTH = 4;
reg needs_sync = 1'b0;
wire sync = s_axis_user[0];
wire has_sync = ~needs_sync | sync;
wire sync_valid = s_axis_valid & has_sync;
assign sync_id_ret = sync_id;
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
needs_sync <= 1'b0;
end else begin
if (s_axis_valid && s_axis_ready && sync) begin
needs_sync <= 1'b0;
end else if (req_valid && req_ready) begin
needs_sync <= req_sync_transfer_start;
end
end
end
dmac_data_mover # (
.C_ID_WIDTH(C_ID_WIDTH),
.C_DATA_WIDTH(C_S_AXIS_DATA_WIDTH),
.C_DISABLE_WAIT_FOR_ID(0),
.C_BEATS_PER_BURST_WIDTH(C_BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.enable(enable),
.enabled(enabled),
.sync_id(sync_id),
.xfer_req(s_axis_xfer_req),
.request_id(request_id),
.response_id(response_id),
.eot(eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_ready(s_axis_ready),
.s_axi_valid(sync_valid),
.s_axi_data(s_axis_data),
.m_axi_ready(fifo_ready),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data)
);
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/wram.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Work RAM module; implements 2KB of on-board WRAM as fpga block RAM.
***************************************************************************************************/
module wram(
input clk_in, // system clock
input en_in, // chip enable
input r_nw_in, // read/write select (read: 0, write: 1)
input [10:0] a_in, // memory address
input [ 7:0] d_in, // data input
output [ 7:0] d_out // data output
);
wire wram_bram_we;
wire [7:0] wram_bram_dout;
single_port_ram_sync #(.ADDR_WIDTH(11),
.DATA_WIDTH(8)) wram_bram(
.clk(clk_in),
.we(wram_bram_we),
.addr_a(a_in),
.din_a(d_in),
.dout_a(wram_bram_dout)
);
assign wram_bram_we = (en_in) ? ~r_nw_in : 1'b0;
assign d_out = (en_in) ? wram_bram_dout : 8'h00;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a[200], b[200]; int countA = 0; int countB = 0; int countC = 0; int n = 0; cin >> n; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < n; i++) { cin >> b[i]; } for (int i = 0; i < n; i++) { if (a[i] == 1 && b[i] == 0) countA++; if (a[i] == b[i]) countB++; if (a[i] < b[i]) countC++; } if (countA == 0) { countA = -1; } else { countA = (countC / countA) + 1; } printf( %d , countA); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> m >> n; vector<string> a(n); for (int i = 0; i < n; i++) { cin >> a[i]; } string s = ; for (int i = 0; i < n; i++) s += ; vector<string> ans(m, s); for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { ans[j][n - i - 1] = a[i][j]; } swap(n, m); for (int i = 0; i < n; i++) { for (int j = 0; j < m / 2; j++) { swap(ans[i][j], ans[i][m - j - 1]); } } string ss = ; for (int i = 0; i < 2 * m; i++) { ss += ; } vector<string> ansx2(2 * n, ss); for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { ansx2[2 * i][j] = ans[i][j]; ansx2[2 * i + 1][j] = ans[i][j]; } for (int j = 0; j < m; j++) { ansx2[2 * i][2 * j] = ans[i][j]; ansx2[2 * i][2 * j + 1] = ans[i][j]; ansx2[2 * i + 1][2 * j] = ans[i][j]; ansx2[2 * i + 1][2 * j + 1] = ans[i][j]; } } for (int i = 0; i < 2 * n; i++) { for (int j = 0; j < 2 * m; j++) { cout << ansx2[i][j]; } cout << endl; } return 0; } |
//Legal Notice: (C)2021 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_tester_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41O_TB_V
`define SKY130_FD_SC_LP__A41O_TB_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a41o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 A4 = 1'b1;
#280 B1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 A4 = 1'b0;
#460 B1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B1 = 1'b1;
#660 A4 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B1 = 1'bx;
#840 A4 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__a41o dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41O_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND_BEHAVIORAL_V
`define SKY130_FD_SC_LP__TAPVGND_BEHAVIORAL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tapvgnd ();
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int ALPHABETS = 30; const int maxN = 410; bitset<maxN> orig[ALPHABETS][maxN], ans[maxN]; int main() { ios::sync_with_stdio(false); cin.tie(0); int N, M; cin >> N >> M; string s; for (int i = 0; i < N; i++) { cin >> s; for (int j = 0; j < M; j++) { orig[s[j] - a ][i][j] = true; ans[i][j] = true; } } int R, C; cin >> R >> C; for (int i = 0; i < R; i++) { cin >> s; for (int j = 0; j < C; j++) { if (s[j] == ? ) continue; char ch = s[j] - a ; int goForward = j % M; for (int k = 0; k < N; k++) { int origR = (((k - i) % N) + N) % N; ans[origR] &= (orig[ch][k] >> goForward) | (orig[ch][k] << (M - goForward)); } } } for (int i = 0; i < N; i++) { for (int j = 0; j < M; j++) { if (ans[i][j]) cout << 1 ; else cout << 0 ; } cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const double EPS = 1e-9; const int INF = 1 << 29; int const NN = 5e3 + 3; int const MX = 1e9 + 9; int a[505][505]; int mx[505][505]; int main() { int n, m, K, q; cin >> n >> m >> K >> q; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) a[i][j] = MX; } while (q--) { int x, y, t; cin >> x >> y >> t; a[x][y] = t; } int ans = MX; for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { mx[i][j] = a[i][j]; for (int k = 2; i + k - 1 <= n && k <= K; ++k) { mx[i][j] = max(mx[i][j], a[i + k - 1][j]); } } } for (int i = 1; i + K - 1 <= n; ++i) { for (int j = 1; j + K - 1 <= m; ++j) { int mxx = -1; for (int jj = j; jj <= j + K - 1; ++jj) { mxx = max(mxx, mx[i][jj]); } ans = min(ans, mxx); } } if (ans < MX) { printf( %d , ans); ; putchar( n ); } else puts( -1 ); return 0; } |
/*
* Copyright (c) 2013 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
`include "defines.v"
module stage3_execute(
/* cpu global */
input clk_i,
input rst_i,
/* to stage 2 */
output stall_o,
/* from stage 4 */
input stall_i,
/* from stage 2 */
input [1:0] control_branch_i,
input control_load_i,
input control_store_i,
input [3:0] aluop_i,
input [31:0] alu_a_i,
input [31:0] alu_b_i,
input [31:0] branch_test_val_i,
input do_wb_i,
input [4:0] wb_reg_i,
/* to stage1 */
output reg take_branch_o,
output [29:0] branch_pc_o,
/* to stage 4 */
output [31:0] alu_o,
output reg control_load_o,
output reg control_store_o,
output reg do_wb_o,
output reg [4:0] wb_reg_o
);
assign stall_o = stall_i;
reg [3:0] aluop;
reg [31:0] alu_a;
reg [31:0] alu_b;
reg [31:0] branch_test_val;
reg [1:0] control_branch;
/*
initial begin
ir <= 0;
nextpc_o <= 0;
end
*/
always @(posedge clk_i)
begin
if (rst_i) begin
aluop <= 0;
alu_a <= 0;
alu_b <= 0;
branch_test_val <= 0;
control_branch <= `CONTROL_BRANCH_COND_NZ;
control_load_o <= 0;
control_store_o <= 0;
do_wb_o <= 0;
wb_reg_o <= 0;
end else if (!stall_i) begin
aluop <= aluop_i;
alu_a <= alu_a_i;
alu_b <= alu_b_i;
branch_test_val <= branch_test_val_i;
control_branch <= control_branch_i;
control_load_o <= control_load_i;
control_store_o <= control_load_i;
do_wb_o <= do_wb_i;
wb_reg_o <= wb_reg_i;
end
end
always @(control_branch or branch_test_val)
begin
case (control_branch)
default: begin
take_branch_o = 0;
end
`CONTROL_BRANCH_COND_NZ: begin
take_branch_o = (branch_test_val != 0);
end
`CONTROL_BRANCH_COND_Z: begin
take_branch_o = (branch_test_val == 0);
end
endcase
end
assign branch_pc_o = alu_o[29:0];
alu alu0(
.op(aluop),
.a(alu_a),
.b(alu_b),
.res(alu_o)
);
endmodule // stage3_execute
|
#include <bits/stdc++.h> using namespace std; int i, j, n; int a[1005]; string s; int main() { ios::sync_with_stdio(0); cin.tie(NULL); cin >> n; n--; cin >> s; for (i = 0; i <= n; i++) a[i] = 1; for (i = 0; i < n; i++) { if (s[i] == = ) a[i + 1] = a[i]; if (s[i] == R ) a[i + 1] = a[i] + 1; if (s[i] == L ) { for (j = i; j >= 0; j--) { if ((s[j] == L && a[j] > a[j + 1]) || (s[j] == R && a[j] < a[j + 1]) || (s[j] == = && a[j] == a[j + 1])) break; if ((s[j] == L )) a[j] = a[j + 1] + 1; if ((s[j] == = )) a[j] = a[j + 1]; } } } for (i = 0; i <= n; i++) cout << a[i] << ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int N; scanf( %d , &N); if (N == 1) { puts( 1 ); return 0; } int s = 0; for (int i = 0; i < N; ++i) { int t; scanf( %d , &t); s += t; } printf( %d n , s % N == 0 ? N : N - 1); } |
#include <bits/stdc++.h> using namespace std; using LL = long long; const int MAXN = 11; const int MAXM = 1e4 + 5; int n, m, ex[MAXN]; int cnt[30]; char w[MAXN][MAXM]; void solve() { scanf( %d %d , &n, &m); for (int i = 0; i < n; i++) scanf( %d , &ex[i]); for (int i = 0; i < n; i++) scanf( %s , w[i]); LL ans = 0; int pos; for (int i = 0; i < (1 << n); i++) { for (int j = 0; j <= 20; j++) cnt[j] = 0; for (int j = 0; j < m; j++) { int x[2] = {0, 0}; for (int k = 0; k < n; k++) if (w[k][j] == 1 ) x[((1 << k) & i) != 0]++; cnt[x[1] - x[0] + 10]++; } int mm = m; LL sum = 0; for (int j = 0; j < n; j++) if (((1 << j) & i) == 0) sum += ex[j]; else sum -= ex[j]; for (int j = 20; j >= 0; j--) { sum += 1ll * (j - 10) * (2 * mm - cnt[j] + 1) * cnt[j] / 2; mm -= cnt[j]; } if (sum >= ans) ans = sum, pos = i; } { for (int j = 0; j <= 20; j++) cnt[j] = 0; for (int j = 0; j < m; j++) { int x[2] = {0, 0}; for (int k = 0; k < n; k++) if (w[k][j] == 1 ) x[((1 << k) & pos) != 0]++; cnt[x[1] - x[0] + 10]++; } for (int j = 1; j <= 20; j++) cnt[j] += cnt[j - 1]; for (int j = 0; j < m; j++) { int x[2] = {0, 0}; for (int k = 0; k < n; k++) if (w[k][j] == 1 ) x[((1 << k) & pos) != 0]++; printf( %d , cnt[x[1] - x[0] + 10]); cnt[x[1] - x[0] + 10]--; } printf( n ); } } int main() { int T; scanf( %d , &T); for (int i = 1; i <= T; i++) { solve(); } return 0; } |
// State register (R0)
module r0 (
input clk_sys,
input strob1b,
// parallel input
input [0:15] w,
// flag inputs
input zs, s_1, s0, carry, vl, vg, exy, exx,
// flag set commands
input ust_z, ust_v, ust_mc, ust_y, ust_x, cleg,
// W->R0
input w_zmvc, w_legy, lrp,
// async resets
input _0_v,
input zer,
// register output
output reg [0:15] r0
);
wire c0 = ust_z & strob1b;
wire c1 = ust_mc & strob1b;
wire c2 = ust_v & strob1b;
wire c7 = ust_y & strob1b;
wire c8 = ust_x & strob1b;
always @ (posedge clk_sys, posedge zer) begin
if (zer) r0[0:15] <= 16'b0;
else begin
if (w_zmvc) {r0[0:1], r0[3]} <= {w[0:1], w[3]};
else begin
if (c0) r0[0] <= zs;
if (c1) {r0[1], r0[3]} <= {s_1, carry};
end
// NOTE: for JVS there is always 0->V and it has the priority (as a reset signal)
if (_0_v) r0[2] <= 1'b0;
else if (w_zmvc) r0[2] <= w[2];
else if (c2 & (s0 ^ s_1)) r0[2] <= 1'b1;
if (w_legy) r0[4:7] <= w[4:7];
else begin
if (cleg) r0[4:6] <= {vl, zs, vg};
if (c7) r0[7] <= exy;
end
if (lrp) r0[8:15] <= w[8:15];
else if (c8) r0[8] <= exx;
end
end
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
#include <bits/stdc++.h> using namespace std; const long long int inf = 1000000000; const long long int mod = 1000000000 + 7; inline void IO() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); } inline int dcmp(long double x) { return x < -1e-12 ? -1 : (x > 1e-12); } template <class T> inline int CHECK(T MASK, int i) { return (MASK >> i) & 1; } template <class T> inline T ON(T MASK, int i) { return MASK | (T(1) << i); } template <class T> inline T OFF(T MASK, int i) { return MASK & (~(T(1) << i)); } template <typename T> inline int CNT(T MASK) { if (numeric_limits<T>::digits <= numeric_limits<unsigned int>::digits) return __builtin_popcount(MASK); else return __builtin_popcountll(MASK); } template <class T> inline int RIGHT(T MASK) { return log2(MASK & -MASK); } int dx4[] = {0, 0, -1, +1}; int dy4[] = {+1, -1, 0, 0}; int dx8[] = {1, 1, 0, -1, -1, -1, 0, 1, 0}; int dy8[] = {0, 1, 1, 1, 0, -1, -1, -1, 0}; inline void I(int& a) { scanf( %d , &a); } inline void I(long long int& a) { scanf( %I64d , &a); } inline void I(unsigned long long int& a) { scanf( %I64u , &a); } inline void I(char* a) { scanf( %s , a); } char Iarr[2000010]; inline void I(string& a) { scanf( %s , Iarr); a = Iarr; } template <typename T, typename... Args> void I(T& a, Args&... args) { I(a); I(args...); } inline void OUT(int a) { printf( %d , a); } inline void OUT(long long int a) { printf( %I64d , a); } inline void OUT(const char* a) { printf( %s , a); } inline void OUT(char* a) { printf( %s , a); } inline void OUT(bool a) { printf( %d , a); } inline void OUT(string a) { for (__typeof(a.end()) it = (a.begin()) - ((a.begin()) > (a.end())); it != (a.end()) - ((a.begin()) > (a.end())); it += 1 - 2 * ((a.begin()) > (a.end()))) printf( %c , *it); } inline void OUT(unsigned long long int a) { printf( %I64u , a); } template <typename T, typename... Args> void OUT(T a, Args... args) { OUT(a); OUT( ); OUT(args...); } template <typename... Args> void O(Args... args) { OUT(args...); OUT( n ); } template <typename T1, typename T2> inline ostream& operator<<(ostream& os, pair<T1, T2> p) { os << { << p.first << , << p.second << } ; return os; } template <typename T> inline ostream& operator<<(ostream& os, vector<T>& a) { os << [ ; for (int i = 0; i < (int)a.size(); i++) { if (i) os << , ; os << a[i]; } os << ] ; return os; } void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cout << *it << = << a << endl; err(++it, args...); } const int M = 50010; int pre[M][26]; int query(int in, char c) { return pre[in][c - a ]; } int main() { string s; I(s); for (int i = 0; i < (int)s.size(); i++) { for (int j = 0; j < 26; j++) { if (i) pre[i][j] = pre[i - 1][j]; else pre[i][j] = -1; } pre[i][s[i] - a ] = i; } int dp[(int)s.size()][101]; for (int i = 0; i < (int)s.size(); i++) { for (int j = 1; j <= 100; j++) { dp[i][j] = -1; if (j == 1) dp[i][j] = i; else if (i) { dp[i][j] = dp[i - 1][j]; int in; if (j != 2) in = dp[i - 1][j - 2]; else in = i; if (in > 0) { int q = query(in - 1, s[i]); if (q != -1) { dp[i][j] = max(dp[i][j], q); } } } } } int len, st; for (int i = 100; i >= 1; i--) { if (dp[(int)s.size() - 1][i] != -1) { len = i; st = dp[(int)s.size() - 1][i]; break; } } string second; second.resize(len); for (int i = (int)s.size() - 1; i >= 0 && len > 0; i--) { if (s[st] == s[i]) { int u = ((int)second.size() - len) / 2; second[u] = s[st]; second[u + len - 1] = s[st]; len -= 2; if (len > 0 && i) st = dp[i - 1][len]; } } O(second); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0)
interface intf ();
integer value;
endinterface
module fanout
#(parameter int N = 1)
(
intf upstream,
intf downstream[N-1:0]
);
genvar i;
for (i = 0; i < N; i = i + 1)
assign downstream[i].value = upstream.value;
endmodule
module xbar
(
input logic clk,
input int cyc,
intf Masters[1:0]
);
localparam NUM_DEMUX_OUT = 2 * 4;
localparam NUM_MUX_IN = 2 * 4;
intf demuxOut[NUM_DEMUX_OUT-1:0]();
intf muxIn[NUM_MUX_IN-1:0]();
//fan out master connections to the crossbar matrix
fanout #(.N(4)) fanout_inst0
(.upstream(Masters[0]),
.downstream(demuxOut[3:0]));
fanout #(.N(4)) fanout_inst1
(.upstream(Masters[1]),
.downstream(demuxOut[7:4]));
//the crossbar matrix assignments, done as 1D arrays because verilator doesn't currently support >1D arrays of interfaces
genvar slv, mst;
for (slv = 0; slv < 4; slv = slv + 1) begin
for (mst = 0; mst < 2; mst = mst + 1) begin
localparam int muxIdx = (slv*2)+mst;
localparam int demuxIdx = slv+(mst*4);
assign muxIn[muxIdx].value = demuxOut[demuxIdx].value;
end
end
always @(posedge clk) begin
if (cyc == 5) begin
`checkh(Masters[0].value, 2);
`checkh(Masters[1].value, 1);
// The first 4 demuxOut values should have the value of the first Master
`checkh(demuxOut[0].value, Masters[0].value);
`checkh(demuxOut[1].value, Masters[0].value);
`checkh(demuxOut[2].value, Masters[0].value);
`checkh(demuxOut[3].value, Masters[0].value);
// The next 4 demuxOut values should have the value of the second Master
`checkh(demuxOut[4].value, Masters[1].value);
`checkh(demuxOut[5].value, Masters[1].value);
`checkh(demuxOut[6].value, Masters[1].value);
`checkh(demuxOut[7].value, Masters[1].value);
// Each 2 mux inputs should have one input from each master, in order from low to high
`checkh(muxIn[0].value, Masters[0].value);
`checkh(muxIn[1].value, Masters[1].value);
`checkh(muxIn[2].value, Masters[0].value);
`checkh(muxIn[3].value, Masters[1].value);
`checkh(muxIn[4].value, Masters[0].value);
`checkh(muxIn[5].value, Masters[1].value);
`checkh(muxIn[6].value, Masters[0].value);
`checkh(muxIn[7].value, Masters[1].value);
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module t
(
clk
);
input clk;
intf masters[1:0]();
int cyc;
xbar sub
(.clk,
.cyc,
.Masters(masters));
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 1) begin
masters[0].value <= 2;
masters[1].value <= 1;
end
end
endmodule
|
//
module ram_controller_ex_lfsr8 (
clk, reset_n, enable, pause, load, data, ldata);
parameter seed = 32;
input clk;
input reset_n;
input enable;
input pause;
input load;
output[8 - 1:0] data;
wire[8 - 1:0] data;
input[8 - 1:0] ldata;
reg[8 - 1:0] lfsr_data;
assign data = lfsr_data ;
always @(posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
// Reset - asynchronously reset to seed value
lfsr_data <= seed[7:0] ;
end
else
begin
if (!enable)
begin
lfsr_data <= seed[7:0];
end
else
begin
if (load)
begin
lfsr_data <= ldata ;
end
else
begin
// Registered mode - synchronous propagation of signals
if (!pause)
begin
lfsr_data[0] <= lfsr_data[7] ;
lfsr_data[1] <= lfsr_data[0] ;
lfsr_data[2] <= lfsr_data[1] ^ lfsr_data[7] ;
lfsr_data[3] <= lfsr_data[2] ^ lfsr_data[7] ;
lfsr_data[4] <= lfsr_data[3] ^ lfsr_data[7] ;
lfsr_data[5] <= lfsr_data[4] ;
lfsr_data[6] <= lfsr_data[5] ;
lfsr_data[7] <= lfsr_data[6] ;
end
end
end
end
end
endmodule
|
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