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/**
* bsg_cache_to_dram_ctrl_tx.v
*
* @author tommy
*
*/
`include "bsg_defines.v"
module bsg_cache_to_dram_ctrl_tx
#(parameter `BSG_INV_PARAM(num_cache_p)
, parameter `BSG_INV_PARAM(data_width_p)
, parameter `BSG_INV_PARAM(block_size_in_words_p)
, parameter `BSG_INV_PARAM(dram_ctrl_burst_len_p)
, localparam mask_width_lp=(data_width_p>>3)
, localparam num_req_lp=(block_size_in_words_p/dram_ctrl_burst_len_p)
, localparam lg_num_cache_lp=`BSG_SAFE_CLOG2(num_cache_p)
, localparam lg_dram_ctrl_burst_len_lp=`BSG_SAFE_CLOG2(dram_ctrl_burst_len_p)
)
(
input clk_i
, input reset_i
, input v_i
, input [lg_num_cache_lp-1:0] tag_i
, output logic ready_o
, input [num_cache_p-1:0][data_width_p-1:0] dma_data_i
, input [num_cache_p-1:0] dma_data_v_i
, output logic [num_cache_p-1:0] dma_data_yumi_o
, output logic app_wdf_wren_o
, output logic [data_width_p-1:0] app_wdf_data_o
, output logic [mask_width_lp-1:0] app_wdf_mask_o
, output logic app_wdf_end_o
, input app_wdf_rdy_i
);
// tag FIFO
//
logic [lg_num_cache_lp-1:0] tag_fifo_data_lo;
logic tag_fifo_v_lo;
logic tag_fifo_yumi_li;
bsg_fifo_1r1w_small #(
.width_p(lg_num_cache_lp)
,.els_p(num_cache_p*num_req_lp)
) tag_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.data_i(tag_i)
,.ready_o(ready_o)
,.v_o(tag_fifo_v_lo)
,.data_o(tag_fifo_data_lo)
,.yumi_i(tag_fifo_yumi_li)
);
// demux
//
logic [num_cache_p-1:0] cache_sel;
bsg_decode_with_v #(
.num_out_p(num_cache_p)
) demux (
.i(tag_fifo_data_lo)
,.v_i(tag_fifo_v_lo)
,.o(cache_sel)
);
assign dma_data_yumi_o = cache_sel & dma_data_v_i & {num_cache_p{app_wdf_rdy_i}};
assign app_wdf_wren_o = tag_fifo_v_lo & dma_data_v_i[tag_fifo_data_lo];
// burst counter
//
logic [lg_dram_ctrl_burst_len_lp-1:0] count_lo;
logic up_li;
logic clear_li;
bsg_counter_clear_up #(
.max_val_p(dram_ctrl_burst_len_p-1)
,.init_val_p(0)
) word_counter (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(clear_li)
,.up_i(up_li)
,.count_o(count_lo)
);
logic take_word;
assign take_word = app_wdf_wren_o & app_wdf_rdy_i;
always_comb begin
if (count_lo == dram_ctrl_burst_len_p-1) begin
clear_li = take_word;
up_li = 1'b0;
app_wdf_end_o = take_word;
tag_fifo_yumi_li = take_word;
end
else begin
clear_li = 1'b0;
up_li = take_word;
app_wdf_end_o = 1'b0;
tag_fifo_yumi_li = 1'b0;
end
end
assign app_wdf_data_o = dma_data_i[tag_fifo_data_lo];
assign app_wdf_mask_o = '0; // negative active! we always write the whole word.
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_to_dram_ctrl_tx)
|
#include <bits/stdc++.h> using namespace std; long long GCD(long long x, long long y) { if (y == 0) return x; return GCD(y, x % y); } long long LCM(long long x, long long y) { return (x * y) / (GCD(x, y)); } long long LOGK(long long x, long long k) { if (x >= k) return 1 + LOGK(x / k, k); return 0; } long long MPOW(long long a, long long b, long long m) { if (b == 0) return 1; long long x = MPOW(a, b / 2, m); x = (x * x) % m; if (b % 2 == 1) x = (x * a) % m; return x; } int main() { long long test = 1; while (test--) { long long n; cin >> n; long long ar[n + 1]; long long dp[n + 1]; dp[0] = 1; for (long long i = 1; i <= n; i++) dp[i] = 0; long long ans = 0; for (long long i = 1; i <= n; i++) { cin >> ar[i]; vector<long long> g; for (long long j = 1; j <= (long long)(sqrt(ar[i])); j++) { if (ar[i] % j == 0) { g.push_back(j); if (ar[i] / j != j) { g.push_back(ar[i] / j); } } } sort(g.begin(), g.end()); reverse(g.begin(), g.end()); for (auto it : g) { if (it <= n) { dp[it] += dp[it - 1]; dp[it] %= 1000000007; } } } for (long long i = 1; i <= n; i++) { ans += dp[i]; ans %= 1000000007; } cout << ans; } } |
#include <bits/stdc++.h> using namespace std; struct arc_t { int u, v, c; arc_t(int _u, int _v, int _c) : u(_u), v(_v), c(_c) {} bool operator<(const arc_t& rhs) const { return c < rhs.c; } }; int pa[2001]; void set_init(int n) { for (int i = 1; i <= n; i++) pa[i] = i; } int set_find(int x) { return pa[x] == x ? x : pa[x] = set_find(pa[x]); } int set_union(int x, int y) { x = set_find(x); y = set_find(y); if (x == y) { return -1; } pa[y] = x; return 0; } int f[2001][2001]; vector<pair<int, int> > G[2001]; long long d[2001][2001]; int root; vector<bool> mark; int dfs(int u) { mark[u] = true; for (vector<pair<int, int> >::iterator i = G[u].begin(); i != G[u].end(); i++) { int v = i->first; if (!mark[v]) { d[root][v] = d[root][u] + i->second; dfs(v); } } } int getd(int _r) { root = _r; mark.clear(); mark.resize(2001, false); d[_r][_r] = 0; dfs(_r); } int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) scanf( %d , &f[i][j]); vector<arc_t> arc; arc.reserve(n * n / 2 + 1); for (int i = 1; i <= n; i++) { if (f[i][i]) { puts( NO ); return 0; } for (int j = i + 1; j <= n; j++) { if (!f[i][j] || f[i][j] != f[j][i]) { puts( NO ); return 0; } arc.push_back(arc_t(i, j, f[i][j])); } } sort(arc.begin(), arc.end()); set_init(n); for (vector<arc_t>::iterator it = arc.begin(); it != arc.end(); it++) { if (!set_union(it->u, it->v)) { G[it->u].push_back(make_pair(it->v, it->c)); G[it->v].push_back(make_pair(it->u, it->c)); } } for (int i = 1; i <= n; i++) { getd(i); } for (int i = 1; i <= n; i++) for (int j = 1; j <= n; j++) if (d[i][j] != f[i][j]) { puts( NO ); return 0; } puts( YES ); return 0; } |
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013.
module t
(
input logic clk,
input logic daten,
input logic [8:0] datval,
output logic signed [3:0][3:0][35:0] datao
);
logic signed [3:0][3:0][3:0][8:0] datat;
genvar i;
generate
for (i=0; i<4; i++)begin
testio dut(.clk(clk), .arr3d_in(datat[i]), .arr2d_out(datao[i]));
end
endgenerate
genvar j;
generate
for (i=0; i<4; i++) begin
for (j=0; j<4; j++) begin
always_comb datat[i][j][0] = daten ? 9'h0 : datval;
always_comb datat[i][j][1] = daten ? 9'h1 : datval;
always_comb datat[i][j][2] = daten ? 9'h2 : datval;
always_comb datat[i][j][3] = daten ? 9'h3 : datval;
end
end
endgenerate
endmodule
module testio
(
input clk,
input logic signed [3:0] [3:0] [8:0] arr3d_in,
output logic signed [3:0] [35:0] arr2d_out
);
logic signed [3:0] [35:0] ar2d_out_pre;
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
always_ff @(posedge clk) begin
if (clk)
arr2d_out <= ar2d_out_pre;
end
endmodule
|
/*
* Copyright (c) 2009 Zeus Gomez Marmolejo <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module test_kotku;
// Registers and nets
reg clk_50;
wire [9:0] ledr;
wire [7:0] ledg;
reg [7:0] sw;
integer i;
wire [21:0] flash_addr;
wire [ 7:0] flash_data;
wire flash_we_n;
wire flash_oe_n;
wire flash_rst_n;
wire flash_ry;
wire [11:0] sdram_addr;
wire [15:0] sdram_data;
wire [ 1:0] sdram_ba;
wire [ 1:0] sdram_dqm;
wire sdram_ras_n;
wire sdram_cas_n;
wire sdram_ce;
wire sdram_clk;
wire sdram_we_n;
wire sdram_cs_n;
wire [16:0] sram_addr_;
wire [15:0] sram_data_;
wire sram_we_n_;
wire sram_oe_n_;
wire sram_ce_n_;
wire [ 1:0] sram_bw_n_;
// Module instantiations
kotku kotku (
.clk_50_ (clk_50),
.ledr_ (ledr),
.ledg_ (ledg),
.sw_ (sw),
// flash signals
.flash_addr_ (flash_addr),
.flash_data_ (flash_data),
.flash_oe_n_ (flash_oe_n),
// sdram signals
.sdram_addr_ (sdram_addr),
.sdram_data_ (sdram_data),
.sdram_ba_ (sdram_ba),
.sdram_ras_n_ (sdram_ras_n),
.sdram_cas_n_ (sdram_cas_n),
.sdram_ce_ (sdram_ce),
.sdram_clk_ (sdram_clk),
.sdram_we_n_ (sdram_we_n),
.sdram_cs_n_ (sdram_cs_n),
// sram signals
.sram_addr_ (sram_addr_),
.sram_data_ (sram_data_),
.sram_we_n_ (sram_we_n_),
.sram_oe_n_ (sram_oe_n_),
.sram_bw_n_ (sram_bw_n_)
);
s29al032d_00 flash (
.A21 (flash_addr[21]),
.A20 (flash_addr[20]),
.A19 (flash_addr[19]),
.A18 (flash_addr[18]),
.A17 (flash_addr[17]),
.A16 (flash_addr[16]),
.A15 (flash_addr[15]),
.A14 (flash_addr[14]),
.A13 (flash_addr[13]),
.A12 (flash_addr[12]),
.A11 (flash_addr[11]),
.A10 (flash_addr[10]),
.A9 (flash_addr[ 9]),
.A8 (flash_addr[ 8]),
.A7 (flash_addr[ 7]),
.A6 (flash_addr[ 6]),
.A5 (flash_addr[ 5]),
.A4 (flash_addr[ 4]),
.A3 (flash_addr[ 3]),
.A2 (flash_addr[ 2]),
.A1 (flash_addr[ 1]),
.A0 (flash_addr[ 0]),
.DQ7 (flash_data[7]),
.DQ6 (flash_data[6]),
.DQ5 (flash_data[5]),
.DQ4 (flash_data[4]),
.DQ3 (flash_data[3]),
.DQ2 (flash_data[2]),
.DQ1 (flash_data[1]),
.DQ0 (flash_data[0]),
.CENeg (1'b0),
.OENeg (flash_oe_n),
.WENeg (1'b1),
.RESETNeg (1'b1),
.ACC (1'b1),
.RY (flash_ry)
);
mt48lc16m16a2 sdram (
.Dq (sdram_data),
.Addr (sdram_addr),
.Ba (sdram_ba),
.Clk (sdram_clk),
.Cke (sdram_ce),
.Cs_n (sdram_cs_n),
.Ras_n (sdram_ras_n),
.Cas_n (sdram_cas_n),
.We_n (sdram_we_n),
.Dqm (2'b00)
);
is61lv25616 sram (
.A ({1'b0,sram_addr_}),
.IO (sram_data_),
.CE_ (1'b0),
.OE_ (sram_oe_n_),
.WE_ (sram_we_n_),
.LB_ (sram_bw_n_[0]),
.UB_ (sram_bw_n_[1])
);
// Behaviour
// Clock generation
always #10 clk_50 <= !clk_50;
initial
begin
$readmemh("../../../cores/flash/bios.dat",flash.Mem);
$readmemb("../../../cores/zet/rtl/micro_rom.dat",
kotku.zet.core.micro_data.micro_rom.rom);
$readmemh("../../../cores/vga/rtl/char_rom.dat",
kotku.vga.lcd.text_mode.char_rom.rom);
// $readmemh("../../../cores/ps2/rtl/xt_codes.dat",
// kotku.ps2.keyb.keyb_xtcodes.rom);
$readmemh("../../../cores/flash/bootrom.dat",
kotku.bootrom.rom);
clk_50 <= 1'b0;
sw <= 8'h1;
#300 sw <= 8'h0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void __print(int x) { cerr << x; } void __print(long x) { cerr << x; } void __print(long long x) { cerr << x; } void __print(unsigned x) { cerr << x; } void __print(unsigned long x) { cerr << x; } void __print(unsigned long long x) { cerr << x; } void __print(float x) { cerr << x; } void __print(double x) { cerr << x; } void __print(long double x) { cerr << x; } void __print(char x) { cerr << << x << ; } void __print(const char *x) { cerr << << x << ; } void __print(const string &x) { cerr << << x << ; } void __print(bool x) { cerr << (x ? true : false ); } template <typename T, typename V> void __print(const pair<T, V> &x) { cerr << { ; __print(x.first); cerr << , ; __print(x.second); cerr << } ; } template <typename T> void __print(const T &x) { int f = 0; cerr << { ; for (auto &i : x) cerr << (f++ ? , : ), __print(i); cerr << } ; } void _print() { cerr << ] n ; } template <typename T, typename... V> void _print(T t, V... v) { __print(t); if (sizeof...(v)) cerr << , ; _print(v...); } const int SIZE = 2e5 + 5; const int dx[8] = {1, 0, -1, 0, 1, -1, -1, 1}; const int dy[8] = {0, 1, 0, -1, 1, 1, -1, -1}; void fastio() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); } void solveTest() { long long n, m; cin >> n >> m; --m; vector<long long> a(n); long long mn = INT_MAX; for (int i = 0; i < n; i++) { cin >> a[i]; mn = min(mn, a[i]); } for (int i = 0; i < n; i++) { a[i] -= mn; } long long cnt = (1ll * mn) * n; while (a[m] != 0) { a[m]--; cnt++; if (m == 0) m = n - 1; else m--; } a[m] = cnt; for (int i = 0; i < n; i++) { cout << a[i] << ; } return; } int main() { fastio(); int t = 1; while (t--) { solveTest(); } return 0; } |
//Multiplier Functional Unit which multiplies 2 numbers
module multiplier (
clk, //clock
reset, //reset the Multiplier
x, //First Number to be multiplied
y, //Second Number to be multiplied
prod, //result of multiplication
ready //signals if the result is ready
);
parameter bits = 8;
//----Input Ports---
input clk;
input reset;
input [bits - 1:0] x;
input [bits - 1:0] y;
//---Output Ports--
output reg [(bits * 2) - 1:0] prod;
output reg ready;
//--Internal Data--
reg [7:0] rx;
reg [15:0] ry;
always @(posedge clk) begin
if (reset) begin
rx <= x;
ry <= 16'b0 + y;
prod <= 16'b0;
end else begin
rx <= rx >> 1;
ry <= ry << 1;
// If LSB of rx is 1 then "multiply" otherwise no change
if (rx & 8'b1) begin
prod <= prod + ry;
end else begin
prod <= prod;
end
end
// When one result reaches 0 nothing left to multiply
//$display("reset %b ready %b rx %d ry %d prod %d, x %d, y %d", reset, ready, rx, ry, prod, x ,y);
ready <= !rx || !ry;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/12/2015 06:11:28 PM
// Design Name:
// Module Name: system_controller
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module system_controller(
input CLK_IN,
input RESET_IN,
output CLK_OUT,
output RESET_OUT
);
reg [4:0] reset_count = 4'h00;
//
// Input buffer to make sure the XCLK signal is routed
// onto the low skew clock lines
//
wire xclk_buf;
IBUFG xclk_ibufg(.I(CLK_IN), .O(xclk_buf));
//
// Using our input clk buffer, we sample the input reset
// signal. if it is high, we hold the count to 1 (NOT 0!)
// Once the input reset is released, we will count until
// we wrap around to 0. While this counter is not 0,
// assert the reset signal to all other blocks. This is done
// to ensure we get a good clean synchronous reset of all flops
// in the device
//
// This is the ONLY place we use xclk_buf or XRESET!
//
wire LOCKED;
assign RESET_OUT = RESET_IN;
// assign dcm_reset = |reset_count;
/* -----\/----- EXCLUDED -----\/-----
assign RESET_OUT = !LOCKED || (|reset_count);
always @(posedge xclk_buf)
if (RESET_IN)
reset_count <= 'h01;
else
if ( (|reset_count) & LOCKED)
reset_count <= reset_count +1;
-----/\----- EXCLUDED -----/\----- */
//
// DCM Reset Logic. This is also off the xclk_buf since
// we want this to be synchronous and held for a few clocks
// in order for the DCM to get a good reset.
//
// This is the ONLY place we use xclk_buf or XRESET!
//
/* -----\/----- EXCLUDED -----\/-----
reg [3:0] dcm_reset_count = 4'h00;
assign dcm_reset = |dcm_reset_count;
always @(posedge xclk_buf)
if (RESET_IN)
dcm_reset_count <= 'h01;
else
if (dcm_reset_count)
dcm_reset_count <= dcm_reset_count + 1;
-----/\----- EXCLUDED -----/\----- */
//
// Clock buffer that ensures the clock going out to the hardware is on a low skew line
//
BUFG clk_bug (
.O(CLK_OUT), // 1-bit output Clock buffer output
.I(CLKFBOUT) // 1-bit input Clock buffer input (S=0)
);
// MMCME2_BASE: Base Mixed Mode Clock Manager
//
// Xilinx HDL Libraries Guide, version 14.2
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
// Jitter programming (OPTIMIZED, HIGH, LOW)
.CLKFBOUT_MULT_F(6.0),
// Multiply value for all CLKOUT (2.000-64.000).
.CLKFBOUT_PHASE(0.0),
// Phase offset in degrees of CLKFB (-360.000-360.000).
.CLKIN1_PERIOD(10.0),
// Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
// CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT6_DIVIDE(1),
.CLKOUT0_DIVIDE_F(1.0),
// Divide amount for CLKOUT0 (1.000-128.000).
// CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT6_DUTY_CYCLE(0.5),
// CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT6_PHASE(0.0),
.CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
.DIVCLK_DIVIDE(1),
// Master division value (1-106)
.REF_JITTER1(0.0),
// Reference input jitter in UI (0.000-0.999).
.STARTUP_WAIT("FALSE")
// Delays DONE until MMCM is locked (FALSE, TRUE)
)
MMCME2_BASE_inst (
// Clock Outputs: 1-bit (each) output: User configurable clock outputs
.CLKOUT0(),
// 1-bit output: CLKOUT0
.CLKOUT0B(),
// 1-bit output: Inverted CLKOUT0
.CLKOUT1(),
// 1-bit output: CLKOUT1
.CLKOUT1B(),
// 1-bit output: Inverted CLKOUT1
.CLKOUT2(),
// 1-bit output: CLKOUT2
.CLKOUT2B(),
// 1-bit output: Inverted CLKOUT2
.CLKOUT3(),
// 1-bit output: CLKOUT3
.CLKOUT3B(),
// 1-bit output: Inverted CLKOUT3
.CLKOUT4(),
// 1-bit output: CLKOUT4
.CLKOUT5(),
// 1-bit output: CLKOUT5
.CLKOUT6(),
// 1-bit output: CLKOUT6
// Feedback Clocks: 1-bit (each) output: Clock feedback ports
.CLKFBOUT(CLKFBOUT),
// 1-bit output: Feedback clock
.CLKFBOUTB(), // 1-bit output: Inverted CLKFBOUT
// Status Ports: 1-bit (each) output: MMCM status ports
.LOCKED(LOCKED),
// 1-bit output: LOCK
// Clock Inputs: 1-bit (each) input: Clock input
.CLKIN1(xclk_buf),
// 1-bit input: Clock
// Control Ports: 1-bit (each) input: MMCM control ports
.PWRDWN(1'b0),
// 1-bit input: Power-down
// .RST(dcm_reset),
.RST(RESET_IN),
// 1-bit input: Reset
// Feedback Clocks: 1-bit (each) input: Clock feedback ports
.CLKFBIN(CLK_OUT)
// 1-bit input: Feedback clock
);
// End of MMCME2_BASE_inst instantiation
endmodule // system_control
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 14:51:03 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Counter10bit_0_0/RAT_Counter10bit_0_0_sim_netlist.v
// Design : RAT_Counter10bit_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "RAT_Counter10bit_0_0,Counter10bit,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "Counter10bit,Vivado 2016.4" *)
(* NotValidForBitStream *)
module RAT_Counter10bit_0_0
(Din,
LOAD,
INC,
RESET,
CLK,
COUNT);
input [0:9]Din;
input LOAD;
input INC;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RESET RST" *) input RESET;
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK CLK" *) input CLK;
output [0:9]COUNT;
wire CLK;
wire [0:9]COUNT;
wire [0:9]Din;
wire INC;
wire LOAD;
wire RESET;
RAT_Counter10bit_0_0_Counter10bit U0
(.CLK(CLK),
.COUNT(COUNT),
.Din(Din),
.INC(INC),
.LOAD(LOAD),
.RESET(RESET));
endmodule
(* ORIG_REF_NAME = "Counter10bit" *)
module RAT_Counter10bit_0_0_Counter10bit
(COUNT,
CLK,
RESET,
LOAD,
INC,
Din);
output [0:9]COUNT;
input CLK;
input RESET;
input LOAD;
input INC;
input [0:9]Din;
wire CLK;
wire [0:9]COUNT;
wire [0:9]Din;
wire INC;
wire LOAD;
wire RESET;
wire [9:0]p_0_in;
wire \s_COUNT[0]_i_1_n_0 ;
wire \s_COUNT[0]_i_3_n_0 ;
wire \s_COUNT[1]_i_2_n_0 ;
wire \s_COUNT[4]_i_2_n_0 ;
wire \s_COUNT[5]_i_2_n_0 ;
LUT2 #(
.INIT(4'hE))
\s_COUNT[0]_i_1
(.I0(LOAD),
.I1(INC),
.O(\s_COUNT[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h8BBBB888))
\s_COUNT[0]_i_2
(.I0(Din[0]),
.I1(LOAD),
.I2(\s_COUNT[0]_i_3_n_0 ),
.I3(COUNT[1]),
.I4(COUNT[0]),
.O(p_0_in[9]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h80))
\s_COUNT[0]_i_3
(.I0(COUNT[2]),
.I1(\s_COUNT[1]_i_2_n_0 ),
.I2(COUNT[3]),
.O(\s_COUNT[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'h8BBBBBBBB8888888))
\s_COUNT[1]_i_1
(.I0(Din[1]),
.I1(LOAD),
.I2(COUNT[3]),
.I3(\s_COUNT[1]_i_2_n_0 ),
.I4(COUNT[2]),
.I5(COUNT[1]),
.O(p_0_in[8]));
LUT6 #(
.INIT(64'h8000000000000000))
\s_COUNT[1]_i_2
(.I0(COUNT[4]),
.I1(COUNT[6]),
.I2(COUNT[8]),
.I3(COUNT[9]),
.I4(COUNT[7]),
.I5(COUNT[5]),
.O(\s_COUNT[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h8BBBB888))
\s_COUNT[2]_i_1
(.I0(Din[2]),
.I1(LOAD),
.I2(\s_COUNT[1]_i_2_n_0 ),
.I3(COUNT[3]),
.I4(COUNT[2]),
.O(p_0_in[7]));
LUT4 #(
.INIT(16'h8BB8))
\s_COUNT[3]_i_1
(.I0(Din[3]),
.I1(LOAD),
.I2(\s_COUNT[1]_i_2_n_0 ),
.I3(COUNT[3]),
.O(p_0_in[6]));
LUT4 #(
.INIT(16'h8BB8))
\s_COUNT[4]_i_1
(.I0(Din[4]),
.I1(LOAD),
.I2(\s_COUNT[4]_i_2_n_0 ),
.I3(COUNT[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h80000000))
\s_COUNT[4]_i_2
(.I0(COUNT[5]),
.I1(COUNT[7]),
.I2(COUNT[9]),
.I3(COUNT[8]),
.I4(COUNT[6]),
.O(\s_COUNT[4]_i_2_n_0 ));
LUT4 #(
.INIT(16'h8BB8))
\s_COUNT[5]_i_1
(.I0(Din[5]),
.I1(LOAD),
.I2(\s_COUNT[5]_i_2_n_0 ),
.I3(COUNT[5]),
.O(p_0_in[4]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h8000))
\s_COUNT[5]_i_2
(.I0(COUNT[6]),
.I1(COUNT[8]),
.I2(COUNT[9]),
.I3(COUNT[7]),
.O(\s_COUNT[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h8BBBBBBBB8888888))
\s_COUNT[6]_i_1
(.I0(Din[6]),
.I1(LOAD),
.I2(COUNT[8]),
.I3(COUNT[9]),
.I4(COUNT[7]),
.I5(COUNT[6]),
.O(p_0_in[3]));
LUT5 #(
.INIT(32'h8BBBB888))
\s_COUNT[7]_i_1
(.I0(Din[7]),
.I1(LOAD),
.I2(COUNT[9]),
.I3(COUNT[8]),
.I4(COUNT[7]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8BB8))
\s_COUNT[8]_i_1
(.I0(Din[8]),
.I1(LOAD),
.I2(COUNT[9]),
.I3(COUNT[8]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h8B))
\s_COUNT[9]_i_1
(.I0(Din[9]),
.I1(LOAD),
.I2(COUNT[9]),
.O(p_0_in[0]));
FDCE \s_COUNT_reg[0]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[9]),
.Q(COUNT[0]));
FDCE \s_COUNT_reg[1]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[8]),
.Q(COUNT[1]));
FDCE \s_COUNT_reg[2]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[7]),
.Q(COUNT[2]));
FDCE \s_COUNT_reg[3]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[6]),
.Q(COUNT[3]));
FDCE \s_COUNT_reg[4]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[5]),
.Q(COUNT[4]));
FDCE \s_COUNT_reg[5]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[4]),
.Q(COUNT[5]));
FDCE \s_COUNT_reg[6]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[3]),
.Q(COUNT[6]));
FDCE \s_COUNT_reg[7]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[2]),
.Q(COUNT[7]));
FDCE \s_COUNT_reg[8]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[1]),
.Q(COUNT[8]));
FDCE \s_COUNT_reg[9]
(.C(CLK),
.CE(\s_COUNT[0]_i_1_n_0 ),
.CLR(RESET),
.D(p_0_in[0]),
.Q(COUNT[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; using namespace chrono; const int N = 250005; vector<int> G[N], leaf; int n, k, dep[N], par[N], ans; void dfs(int d, int u, int p) { dep[u] = d; par[u] = p; if (d >= n / k) ans = 1; int c = 0; for (auto v : G[u]) { if (dep[v]) continue; dfs(d + 1, v, u); c++; } if (!c) leaf.push_back(u); } int main() { time_point<steady_clock> start = steady_clock::now(); int m, u, v; scanf( %d%d%d , &n, &m, &k); while (m--) { scanf( %d%d , &u, &v); G[u].push_back(v); G[v].push_back(u); } dfs(1, 1, 0); if (ans) { ans = leaf[0]; for (auto u : leaf) if (dep[u] > dep[ans]) ans = u; printf( PATH n%d n , dep[ans]); while (ans) { printf( %d , ans); ans = par[ans]; } } else { printf( CYCLES n ); for (int i = 0; i < k; i++) { int x = leaf[i]; u = v = 0; for (int j = 0; j < G[x].size(); j++) { if (G[x][j] != par[x]) { if (!u) u = G[x][j]; else if (G[x][j] != u) { v = G[x][j]; break; } } } if (dep[u] < dep[v]) swap(u, v); if ((dep[x] - dep[u] + 1) % 3) { printf( %d n , dep[x] - dep[u] + 1); while (x != u) { printf( %d , x); x = par[x]; } printf( %d n , u); } else if ((dep[x] - dep[v] + 1) % 3) { printf( %d n , dep[x] - dep[v] + 1); while (x != v) { printf( %d , x); x = par[x]; } printf( %d n , v); } else { printf( %d n%d , dep[u] - dep[v] + 2, x); while (u != v) { printf( %d , u); u = par[u]; } printf( %d n , v); } } } cerr << endl << ------------------------------ << endl << Time: << duration<double, milli>(steady_clock::now() - start).count() << ms. << endl; return 0; } |
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// CLK I 1 clock
// RST_N I 1 reset
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkTop_HW_Side(CLK,
RST_N);
input CLK;
input RST_N;
// register rg_banner_printed
reg rg_banner_printed;
wire rg_banner_printed$D_IN, rg_banner_printed$EN;
// ports of submodule mem_model
wire [352 : 0] mem_model$mem_server_request_put;
wire [255 : 0] mem_model$mem_server_response_get;
wire mem_model$EN_mem_server_request_put,
mem_model$EN_mem_server_response_get,
mem_model$RDY_mem_server_request_put,
mem_model$RDY_mem_server_response_get;
// ports of submodule soc_top
wire [352 : 0] soc_top$to_raw_mem_request_get;
wire [255 : 0] soc_top$to_raw_mem_response_put;
wire [63 : 0] soc_top$set_verbosity_logdelay,
soc_top$set_watch_tohost_tohost_addr;
wire [7 : 0] soc_top$get_to_console_get,
soc_top$put_from_console_put,
soc_top$status;
wire [3 : 0] soc_top$set_verbosity_verbosity;
wire soc_top$EN_get_to_console_get,
soc_top$EN_put_from_console_put,
soc_top$EN_set_verbosity,
soc_top$EN_set_watch_tohost,
soc_top$EN_to_raw_mem_request_get,
soc_top$EN_to_raw_mem_response_put,
soc_top$RDY_get_to_console_get,
soc_top$RDY_to_raw_mem_request_get,
soc_top$RDY_to_raw_mem_response_put,
soc_top$set_watch_tohost_watch_tohost;
// rule scheduling signals
wire CAN_FIRE_RL_memCnx_ClientServerRequest,
CAN_FIRE_RL_memCnx_ClientServerResponse,
CAN_FIRE_RL_rl_relay_console_out,
CAN_FIRE_RL_rl_step0,
CAN_FIRE_RL_rl_terminate,
WILL_FIRE_RL_memCnx_ClientServerRequest,
WILL_FIRE_RL_memCnx_ClientServerResponse,
WILL_FIRE_RL_rl_relay_console_out,
WILL_FIRE_RL_rl_step0,
WILL_FIRE_RL_rl_terminate;
// declarations used by system tasks
// synopsys translate_off
reg TASK_testplusargs___d12;
reg TASK_testplusargs___d11;
reg [31 : 0] v__h536;
reg [31 : 0] v__h530;
// synopsys translate_on
// submodule mem_model
mkMem_Model mem_model(.CLK(CLK),
.RST_N(RST_N),
.mem_server_request_put(mem_model$mem_server_request_put),
.EN_mem_server_request_put(mem_model$EN_mem_server_request_put),
.EN_mem_server_response_get(mem_model$EN_mem_server_response_get),
.RDY_mem_server_request_put(mem_model$RDY_mem_server_request_put),
.mem_server_response_get(mem_model$mem_server_response_get),
.RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get));
// submodule soc_top
mkSoC_Top soc_top(.CLK(CLK),
.RST_N(RST_N),
.put_from_console_put(soc_top$put_from_console_put),
.set_verbosity_logdelay(soc_top$set_verbosity_logdelay),
.set_verbosity_verbosity(soc_top$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost),
.to_raw_mem_response_put(soc_top$to_raw_mem_response_put),
.EN_set_verbosity(soc_top$EN_set_verbosity),
.EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get),
.EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put),
.EN_get_to_console_get(soc_top$EN_get_to_console_get),
.EN_put_from_console_put(soc_top$EN_put_from_console_put),
.EN_set_watch_tohost(soc_top$EN_set_watch_tohost),
.RDY_set_verbosity(),
.to_raw_mem_request_get(soc_top$to_raw_mem_request_get),
.RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get),
.RDY_to_raw_mem_response_put(soc_top$RDY_to_raw_mem_response_put),
.get_to_console_get(soc_top$get_to_console_get),
.RDY_get_to_console_get(soc_top$RDY_get_to_console_get),
.RDY_put_from_console_put(),
.status(soc_top$status),
.RDY_set_watch_tohost());
// rule RL_rl_step0
assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ;
assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ;
// rule RL_rl_terminate
assign CAN_FIRE_RL_rl_terminate = soc_top$status != 8'd0 ;
assign WILL_FIRE_RL_rl_terminate = CAN_FIRE_RL_rl_terminate ;
// rule RL_rl_relay_console_out
assign CAN_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ;
assign WILL_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ;
// rule RL_memCnx_ClientServerRequest
assign CAN_FIRE_RL_memCnx_ClientServerRequest =
soc_top$RDY_to_raw_mem_request_get &&
mem_model$RDY_mem_server_request_put ;
assign WILL_FIRE_RL_memCnx_ClientServerRequest =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
// rule RL_memCnx_ClientServerResponse
assign CAN_FIRE_RL_memCnx_ClientServerResponse =
soc_top$RDY_to_raw_mem_response_put &&
mem_model$RDY_mem_server_response_get ;
assign WILL_FIRE_RL_memCnx_ClientServerResponse =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
// register rg_banner_printed
assign rg_banner_printed$D_IN = 1'd1 ;
assign rg_banner_printed$EN = CAN_FIRE_RL_rl_step0 ;
// submodule mem_model
assign mem_model$mem_server_request_put = soc_top$to_raw_mem_request_get ;
assign mem_model$EN_mem_server_request_put =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
assign mem_model$EN_mem_server_response_get =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
// submodule soc_top
assign soc_top$put_from_console_put = 8'h0 ;
assign soc_top$set_verbosity_logdelay = 64'd0 ;
assign soc_top$set_verbosity_verbosity =
TASK_testplusargs___d11 ?
4'd2 :
(TASK_testplusargs___d12 ? 4'd1 : 4'd0) ;
assign soc_top$set_watch_tohost_tohost_addr = 64'h0 ;
assign soc_top$set_watch_tohost_watch_tohost = 1'b0 ;
assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ;
assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ;
assign soc_top$EN_to_raw_mem_request_get =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
assign soc_top$EN_to_raw_mem_response_put =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
assign soc_top$EN_get_to_console_get = soc_top$RDY_get_to_console_get ;
assign soc_top$EN_put_from_console_put = 1'b0 ;
assign soc_top$EN_set_watch_tohost = 1'b0 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_banner_printed <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (rg_banner_printed$EN)
rg_banner_printed <= `BSV_ASSIGNMENT_DELAY rg_banner_printed$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_banner_printed = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("Bluespec RISC-V standalone system simulation v1.2");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
TASK_testplusargs___d12 = $test$plusargs("v1");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
TASK_testplusargs___d11 = $test$plusargs("v2");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
begin
v__h536 = $stime;
#0;
end
v__h530 = v__h536 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
$display("%0d: %m:.rl_terminate: soc_top status is 0x%0h (= 0d%0d)",
v__h530,
soc_top$status,
soc_top$status);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (soc_top$RDY_get_to_console_get)
$write("%c", soc_top$get_to_console_get);
if (RST_N != `BSV_RESET_VALUE)
if (soc_top$RDY_get_to_console_get) $fflush(32'h80000001);
end
// synopsys translate_on
endmodule // mkTop_HW_Side
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: player2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module player2 (
address,
clock,
q);
input [10:0] address;
input clock;
output [2:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [2:0] sub_wire0;
wire [2:0] q = sub_wire0[2:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({3{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "player2.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1190,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 3,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "player2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1190"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "3"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "player2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1190"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 3 0 OUTPUT NODEFVAL "q[2..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 3 0 @q_a 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL player2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL player2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL player2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL player2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL player2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL player2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//--------------------------------------------------------------------------------
// Project : SWITCH
// File : ethernet_top.v
// Version : 0.2
// Author : Shreejith S, Vipin K
//
// Description: Ethernet Controller Top File
//
//--------------------------------------------------------------------------------
module ethernet_top(
input i_rst,
input i_clk_125,
input i_clk_200,
output phy_resetn,
// V6 GMII I/F
output [7:0] gmii_txd,
output gmii_tx_en,
output gmii_tx_er,
output gmii_tx_clk,
input [7:0] gmii_rxd,
input gmii_rx_dv,
input gmii_rx_er,
input gmii_rx_clk,
input gmii_col,
input gmii_crs,
input mii_tx_clk,
// V7 SGMII I/F
// Commom I/F for V7 Enet - Not used here
input gtrefclk_p, // Differential +ve of reference clock for MGT: 125MHz, very high quality.
input gtrefclk_n, // Differential -ve of reference clock for MGT: 125MHz, very high quality.
output txp, // Differential +ve of serial transmission from PMA to PMD.
output txn, // Differential -ve of serial transmission from PMA to PMD.
input rxp, // Differential +ve for serial reception from PMD to PMA.
input rxn, // Differential -ve for serial reception from PMD to PMA.
output synchronization_done,
output linkup,
// PHY MDIO I/F
output mdio_out,
input mdio_in,
output mdc_out,
output mdio_t,
//Reg file
input i_enet_enable, // Enable the ethernet core
input i_enet_loopback, // Enable loopback mode
input [31:0] i_enet_ddr_source_addr, // Where is data for ethernet
input [31:0] i_enet_ddr_dest_addr, // Where to store ethernet data
input [31:0] i_enet_rcv_data_size, // How much data should be received from enet
input [31:0] i_enet_snd_data_size, // How much data should be sent through enet
output [31:0] o_enet_rx_cnt, // Ethernet RX Performance Counter
output [31:0] o_enet_tx_cnt, // Ethernet TX Performance Counter
output o_enet_rx_done, // Ethernet RX Completed
output o_enet_tx_done, // Ethernet TX Completed
//To DDR controller
output o_ddr_wr_req,
output o_ddr_rd_req,
output [255:0] o_ddr_wr_data,
output [31:0] o_ddr_wr_be,
output [31:0] o_ddr_wr_addr,
output [31:0] o_ddr_rd_addr,
input [255:0] i_ddr_rd_data,
input i_ddr_wr_ack,
input i_ddr_rd_ack,
input i_ddr_rd_data_valid
);
wire [63:0] enet_wr_data;
wire [63:0] enet_rd_data;
ethernet_controller_top ect (
.glbl_rst(i_rst),
.dcm_locked(1'b1),
.i_clk_125(i_clk_125),
.i_clk_200(i_clk_200),
.phy_resetn(phy_resetn),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.gmii_tx_clk(gmii_tx_clk),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_rx_clk(gmii_rx_clk),
.gmii_col(gmii_col),
.gmii_crs(gmii_crs),
.mii_tx_clk(mii_tx_clk),
.mdio_out (mdio_out),
.mdio_in (mdio_in),
.mdc_out (mdc_out),
.mdio_t (mdio_t),
.enet_loopback(i_enet_loopback),
.enet_wr_clk(i_clk_200),
.enet_wr_data_valid(enet_wr_data_valid),
.enet_wr_data(enet_wr_data),
.enet_wr_rdy(enet_wr_rdy),
.enet_rd_clk(i_clk_200),
.enet_rd_rdy(enet_rd_rdy),
.enet_rd_data(enet_rd_data),
.enet_rd_data_valid(enet_rd_data_valid),
.if_enable(enet_enable),
.o_tx_mac_count(tx_mac_count)
);
enet_ddr_ctrl edc (
.i_clk(i_clk_200),
.i_rst(i_rst),
.i_enet_enable(i_enet_enable),
.i_enet_ddr_source_addr(i_enet_ddr_source_addr),
.i_enet_ddr_dest_addr(i_enet_ddr_dest_addr),
.i_enet_rcv_data_size(i_enet_rcv_data_size),
.i_enet_snd_data_size(i_enet_snd_data_size),
.o_enet_enable(enet_enable),
.i_enet_data_avail(enet_rd_data_valid),
.o_enet_rx_cnt(o_enet_rx_cnt),
.o_enet_tx_cnt(o_enet_tx_cnt),
.o_enet_rx_done(o_enet_rx_done),
.o_enet_tx_done(o_enet_tx_done),
.o_core_ready(enet_rd_rdy),
.i_data(enet_rd_data),
.o_data(enet_wr_data),
.o_core_data_avail(enet_wr_data_valid),
.i_enet_ready(enet_wr_rdy),
.o_ddr_wr_req(o_ddr_wr_req),
.o_ddr_rd_req(o_ddr_rd_req),
.o_ddr_wr_data(o_ddr_wr_data),
.o_ddr_wr_be(o_ddr_wr_be),
.o_ddr_wr_addr(o_ddr_wr_addr),
.o_ddr_rd_addr(o_ddr_rd_addr),
.i_ddr_rd_data(i_ddr_rd_data),
.i_ddr_wr_ack(i_ddr_wr_ack),
.i_ddr_rd_ack(i_ddr_rd_ack),
.i_ddr_rd_data_valid(i_ddr_rd_data_valid),
.i_tx_mac_count(tx_mac_count)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<pair<long long, long long> > v, par; long long QN, cmd, nums = 0; map<long long, long long> ans; long long solve(long long l, long long r, long long x) { long long st = l, en = r; while (st <= en) { long long mid = (st + en) / 2; if (x < v[mid].first) { en = mid - 1; continue; } if (x > v[mid].second) { st = mid + 1; continue; } if (v[mid].first == v[mid].second && par[mid].first == -1) return ans[v[mid].first]; x = x - v[mid].first + 1; x %= par[mid].first; if (x == 0) x = par[mid].first; return solve(l, mid, x); } } long long x, l, r; int main() { cin >> QN; while (QN--) { cin >> cmd; if (cmd == 1) { cin >> x; ans[++nums] = x; v.push_back(make_pair(nums, nums)); par.push_back(make_pair(-1, -1)); } else { cin >> l >> r; nums++; v.push_back(make_pair(nums, nums + l * r - 1)); nums = nums + l * r - 1; par.push_back(make_pair(l, -1)); } } cin >> QN; while (QN--) { cin >> x; cout << solve(0, v.size() - 1, x) << ; } } |
#include <bits/stdc++.h> using namespace std; int main() { long long n, x, y; map<long long, long long> mx, my; map<tuple<long long, long long>, long long> mt; scanf( %lld , &n); for (int i = 0; i < n; i++) { scanf( %lld%lld , &x, &y); tuple<long long, long long> a = make_tuple(x, y); mx[x]++; my[y]++; mt[a]++; } long long ans = 0; for (auto a : mx) { long long b = a.second; ans += b * (b - 1) / 2; } for (auto a : my) { long long b = a.second; ans += b * (b - 1) / 2; } for (auto a : mt) { long long b = a.second; ans -= b * (b - 1) / 2; } printf( %lld n , ans); } |
module VgaSyncGenerator
(
input CLK ,
output reg VGA_HS ,
output reg VGA_VS ,
output wire [10:0] VGA_POS_X ,
output wire [9 :0] VGA_POS_Y ,
output wire VGA_ENABLE
);
// ------------------- Параметры синхрогенератора для выбранного разрешения ---------------------------
parameter HORIZONTAL_RESOLUTION = 10'd800;
parameter HORIZONTAL_FRONT_PORCH = 8'd40;
parameter HORIZONTAL_SYNC_PULSE = 8'd128;
parameter HORIZONTAL_BACK_PORCH = 8'd88;
parameter VERTICAL_RESOLUTION = 10'd600;
parameter VERTICAL_FRONT_PORCH = 1'd1;
parameter VERTICAL_SYNC_PULSE = 3'd4;
parameter VERTICAL_BACK_PORCH = 5'd23;
//-----------------------------------------------------------------------------------------------------
// -------------------- Границы видимого участка для выбранного разрешения ----------------------------
localparam SCREEN_LEFT_BORDER = HORIZONTAL_SYNC_PULSE + HORIZONTAL_BACK_PORCH;
localparam SCREEN_RIGHT_BORDER = HORIZONTAL_SYNC_PULSE + HORIZONTAL_BACK_PORCH + HORIZONTAL_RESOLUTION;
localparam SCREEN_UP_BORDER = VERTICAL_SYNC_PULSE + VERTICAL_BACK_PORCH;
localparam SCREEN_DOWN_BORDER = VERTICAL_SYNC_PULSE + VERTICAL_BACK_PORCH + VERTICAL_RESOLUTION;
//-----------------------------------------------------------------------------------------------------
reg [10:0]PosX = 0;
reg [9 :0]PosY = 0;
wire IsScreenX = ( PosX >= SCREEN_LEFT_BORDER ) && ( PosX < SCREEN_RIGHT_BORDER );
wire IsScreenY = ( PosY >= SCREEN_UP_BORDER ) && ( PosY < SCREEN_DOWN_BORDER );
assign VGA_POS_X = IsScreenX ? ( PosX - SCREEN_LEFT_BORDER ) : 10'd0;
assign VGA_POS_Y = IsScreenY ? ( PosY - SCREEN_UP_BORDER ) : 9'd0;
assign VGA_ENABLE = IsScreenX & IsScreenY;
reg Clk = 1'b0;
always @( posedge CLK )
begin
Clk <= ~ Clk;
end
always @( posedge Clk )
begin
VGA_HS <= (PosX > HORIZONTAL_SYNC_PULSE);
if( PosX > ( HORIZONTAL_SYNC_PULSE + HORIZONTAL_BACK_PORCH + HORIZONTAL_RESOLUTION + HORIZONTAL_FRONT_PORCH ) )
PosX <= 0;
else
PosX <= PosX + 1'b1;
end
always @( negedge VGA_HS )
begin
VGA_VS <= ( PosY > VERTICAL_SYNC_PULSE );
if( PosY > ( VERTICAL_SYNC_PULSE + VERTICAL_BACK_PORCH + VERTICAL_RESOLUTION + VERTICAL_FRONT_PORCH ) )
PosY <= 0;
else
PosY <= PosY + 1'b1;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__NAND3_BLACKBOX_V
`define SKY130_FD_SC_HVL__NAND3_BLACKBOX_V
/**
* nand3: 3-input NAND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__nand3 (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__NAND3_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1000000007; const int MAXN = 107; int A[50007]; int F[107][107]; unsigned long long b[107][107]; struct matrix { int n, m; int arr[MAXN][MAXN]; matrix() {} matrix(int x, int y, int V = 0) { n = x; m = y; for (int j = 0; j < n; j++) for (int i = 0; i < m; i++) arr[j][i] = V; } matrix(int x, int y, int A[MAXN][MAXN]) { n = x; m = y; for (int j = 0; j < n; j++) for (int i = 0; i < m; i++) arr[j][i] = A[j][i]; } matrix operator*(matrix &mat) { matrix res(n, mat.m, 0); long long theta; for (int j = 0; j < n; j++) { for (int i = 0; i < mat.m; i++) { theta = 0; for (int k = 0; k < m; k++) { theta += 1ll * arr[j][k] * mat.arr[k][i]; theta %= MOD; } res.arr[j][i] = theta; } } return res; } matrix power(long long K) { matrix res(n, m, 0), b(n, m, 0); for (int j = 0; j < n; j++) res.arr[j][j] = 1; b = (*this); while (K > 0) { if ((K & 1)) res = res * b; K /= 2; b = b * b; } return res; } }; int main() { int n, k, x; unsigned long long b; cin >> n >> b >> k >> x; for (int i = 0; i < n; i++) cin >> A[i]; for (int j = 0; j < x; j++) for (int i = 0; i < n; i++) F[j][(j * 10 + A[i]) % x]++; matrix M(x, x, F); matrix B(x, x, 0); B = M.power(b); cout << B.arr[0][k] << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 300 + 10; const int maxm = maxn * maxn; const int INF = 0x3f3f3f3f; int connect[maxn][maxn], edgecnt[maxn]; int price[maxn], vis[maxn * 2], match[maxn * 2]; int n; bool extend(int u) { vis[u] = true; for (int i = 1; i <= edgecnt[u]; i++) { int v = connect[u][i] + n; if (vis[v] || v == match[u]) continue; vis[v] = true; if (match[v] == 0 || extend(match[v])) { match[u] = v; match[v] = u; return true; } } return false; } void Match() { memset(match, 0, sizeof(match)); for (int i = 1; i <= n; i++) { if (match[i]) continue; memset(vis, 0, sizeof(vis)); extend(i); } for (int i = 1; i <= 2 * n; i++) { } } int S, T; struct Edge { Edge *n, *o; int v, c, w; void init(int _v, int _c, int _w) { v = _v; c = _c; w = _w; } }; Edge *E[maxn * 2], Er[maxn * maxn * 2]; int Es = 0; void addedge(int u, int v, int c, int w) { static Edge *P1, *P2; P1 = &Er[++Es]; P2 = &Er[++Es]; P1->init(v, c, w); P1->n = E[u]; P1->o = P2; E[u] = P1; P2->init(u, 0, -w); P2->n = E[v]; P2->o = P1; E[v] = P2; } int H[maxn * 2]; bool V[maxn * 2]; bool BFS() { static int Q[maxn * 20], bot, u, v; memset(H, INF, sizeof(H)); memset(V, true, sizeof(V)); H[Q[bot = 1] = S] = 0; V[S] = false; for (int top = 1; top <= bot; top++) { u = Q[top]; for (Edge *P = E[u]; P; P = P->n) if (P->c && H[P->v] > H[u] + 1) { H[P->v] = H[u] + 1; if (V[P->v]) { Q[++bot] = P->v; V[P->v] = false; } } V[u] = true; } return H[T] < INF; } int extend(int u, int lefts) { if (u == T) { return lefts; } V[u] = false; int ret = 0, t; for (Edge *P = E[u]; P && ret < lefts; P = P->n) { if (P->c && V[P->v] && H[u] + 1 == H[P->v]) { t = extend(P->v, min(lefts - ret, P->c)); ret += t; P->c -= t; P->o->c += t; } } V[u] = true; if (ret < lefts) H[u] = INF; return ret; } int maxflow() { int ret = 0, cnt = 0; while (BFS()) { ret += extend(S, INF); } return ret; } void build() { memset(E, 0, sizeof(E)); for (int i = 1; i <= n; i++) { if (price[i] >= 0) { addedge(S, i, price[i], 1); } else { addedge(i, T, -price[i], 1); } for (int j = 1; j <= edgecnt[i]; j++) { int t = match[connect[i][j] + n]; addedge(i, t, INF, 1); } } } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &edgecnt[i]); for (int j = 1; j <= edgecnt[i]; j++) { scanf( %d , &connect[i][j]); } } S = 0; T = 2 * n + 1; int ans = 0; for (int i = 1; i <= n; i++) { scanf( %d , price + i); price[i] *= -1; if (price[i] >= 0) ans += price[i]; } Match(); build(); ans = maxflow() - ans; cout << ans << endl; return 0; } |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Thu May 22 12:56:05 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/mono_radio/ip/fir_lp_15kHz/fir_lp_15kHz_stub.v
// Design : fir_lp_15kHz
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fir_compiler_v7_1,Vivado 2014.1" *)
module fir_lp_15kHz(aclk, s_axis_data_tvalid, s_axis_data_tready, s_axis_data_tdata, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[15:0],m_axis_data_tvalid,m_axis_data_tdata[47:0]" */;
input aclk;
input s_axis_data_tvalid;
output s_axis_data_tready;
input [15:0]s_axis_data_tdata;
output m_axis_data_tvalid;
output [47:0]m_axis_data_tdata;
endmodule
|
#include <bits/stdc++.h> using namespace std; int maps[501][501]; char str[501]; int dx[11] = {-1, 0, 1, 0, -1, -1, 1, 1, -1, -1}; int dy[11] = {0, 1, 0, -1, 0, 1, 1, -1, -1, 1}; int dp[550][550][10]; int n, m; int pan(int x, int y) { if (x < 1 || x > n || y < 1 || y > m) return 1; if (maps[x][y]) return 1; return 0; } int main() { while (~scanf( %d%d , &n, &m)) { for (int i = 1; i <= n; i++) { scanf( %s , str); for (int j = 1; j <= m; j++) { if (str[j - 1] == 0 ) maps[i][j] = 0; else maps[i][j] = 1; } } int ans = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (maps[i][j]) continue; for (int q = 0; q < 9; q++) { dp[i][j][q] = 1; if (q == 4) continue; for (int k = 1;; k++) { int xx = i + dx[q] * k; int yy = j + dy[q] * k; if (pan(xx, yy)) break; dp[i][j][q]++; } } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (maps[i][j]) continue; for (int q = 0; q < 9; q++) { if (q == 4) continue; for (int k = 1;; k++) { int xx = i + dx[q] * k; int yy = j + dy[q] * k; if (pan(xx, yy) || pan(i + dx[q + 1] * k, j + dy[q + 1] * k)) { break; } if (q == 0 && dp[xx][yy][6] >= k + 1) ans++; if (q == 1 && dp[xx][yy][7] >= k + 1) ans++; if (q == 2 && dp[xx][yy][8] >= k + 1) ans++; if (q == 3 && dp[xx][yy][5] >= k + 1) ans++; if (q == 5 && dp[xx][yy][2] >= k * 2) ans++; if (q == 6 && dp[xx][yy][3] >= k * 2) ans++; if (q == 7 && dp[xx][yy][0] >= k * 2) ans++; if (q == 8 && dp[xx][yy][1] >= k * 2) ans++; } } } } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const int INF = 0x3f3f3f3f; const long long INFLL = 0x3f3f3f3f3f3f3f3f; const int maxn = 1e6 + 10; struct Edge { int to, nxt; long long cost; Edge() {} Edge(int to, int nxt, long long cost) : to(to), nxt(nxt), cost(cost) {} } edge[maxn << 1]; int head[maxn], tot; long long dp[maxn]; void Init(int n) { tot = 0; for (int i = 1; i <= n; ++i) head[i] = -1; } void addedge(int u, int v, long long cost) { edge[tot] = Edge(v, head[u], cost); head[u] = tot++; edge[tot] = Edge(u, head[v], cost); head[v] = tot++; } int n; long long val[maxn]; long long ans; void DFS(int u, int pre) { dp[u] = val[u]; long long max1 = 0, max2 = 0; for (int i = head[u]; ~i; i = edge[i].nxt) { int v = edge[i].to; long long cost = edge[i].cost; if (v == pre) continue; DFS(v, u); long long tmp = dp[v] - cost; if (tmp > max1) swap(max1, tmp); max2 = max(tmp, max2); dp[u] = max(dp[u], dp[v] - cost + val[u]); } ans = max(ans, max(dp[u], max1 + max2 + val[u])); } void RUN() { while (~scanf( %d , &n)) { Init(n); for (int i = 1; i <= n; ++i) scanf( %lld , val + i); long long w; for (int i = 1, u, v; i < n; ++i) { scanf( %d %d %lld , &u, &v, &w); addedge(u, v, w); } ans = 0; DFS(1, -1); printf( %lld n , ans); } } int main() { RUN(); return 0; } |
`default_nettype none
`timescale 1ns / 1ps
module sia_receiver_tb();
reg [15:0] story;
reg clk_i = 0, reset_i = 0;
reg rxd_i = 1, rxc_i = 0;
reg rxreg_oe_i = 0, rxregr_oe_i = 0;
wire idle_o;
wire [63:0] dat_o;
wire sample_to;
sia_receiver #(
.SHIFT_REG_WIDTH(64),
.BAUD_RATE_WIDTH(32),
.BITS_WIDTH(5)
) x(
.clk_i(clk_i),
.reset_i(reset_i),
.bits_i(5'd11), // 8O1
.baud_i(32'd49), // 1Mbps when clocked at 50MHz.
.eedd_i(1'b1),
.eedc_i(1'b1),
.rxd_i(rxd_i),
.rxc_i(rxc_i),
.dat_o(dat_o),
.idle_o(idle_o),
.sample_to(sample_to)
);
always begin
#10 clk_i <= ~clk_i;
end
task assert_idle;
input expected;
begin
if (expected !== idle_o) begin
$display("@E %d idle_o Expected %d; got %d", story, expected, idle_o);
$stop;
end
end
endtask
task assert_dat;
input [63:0] expected;
begin
if (expected !== dat_o) begin
$display("@E %d dat_o Expected %064B; got %064B", story, expected, dat_o);
$stop;
end
end
endtask
initial begin
$dumpfile("sia_receiver.vcd");
$dumpvars;
story <= 1;
reset_i <= 1;
wait(clk_i); wait(~clk_i);
reset_i <= 0;
assert_idle(1);
assert_dat(64'hFFFFFFFFFFFFFFFF);
rxd_i <= 0; #1000; assert_dat({1'b0, ~(63'h0)});
rxd_i <= 1; #1000; assert_dat({2'b10, ~(62'h0)});
rxd_i <= 0; #1000; assert_dat({3'b010, ~(61'h0)});
rxd_i <= 1; #1000; assert_dat({4'b1010, ~(60'h0)});
rxd_i <= 0; #1000; assert_dat({5'b01010, ~(59'h0)});
rxd_i <= 0; #1000; assert_dat({6'b001010, ~(58'h0)});
rxd_i <= 0; #1000; assert_dat({7'b0001010, ~(57'h0)});
rxd_i <= 0; #1000; assert_dat({8'b00001010, ~(56'h0)});
rxd_i <= 1; #1000; assert_dat({9'b100001010, ~(55'h0)});
rxd_i <= 0; #1000; assert_dat({10'b0100001010, ~(54'h0)});
rxd_i <= 1; #1000; assert_dat({11'b10100001010, ~(53'h0)});
rxd_i <= 0; #1000; assert_dat({12'b010100001010, ~(52'h0)});
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 0; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
rxd_i <= 1; #1000;
story <= 2;
reset_i <= 1;
wait(clk_i); wait(~clk_i);
wait(clk_i); wait(~clk_i);
reset_i <= 0;
rxd_i <= 0;
wait(clk_i); wait(~clk_i);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{1'b0},{63{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{2'b0},{62{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{3'b0},{61{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{4'b0},{60{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{5'b0},{59{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{6'b0},{58{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{7'b0},{57{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{8'b0},{56{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{9'b0},{55{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{10'b0},{54{1'b1}}}); assert_idle(0);
rxc_i <= 1; #500; rxc_i <= 0; #500; assert_dat({{11'b0},{53{1'b1}}}); assert_idle(1);
$display("@I Done.");
$stop;
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_cpu_s1_jtag_debug_module_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { int n; char s[105][105]; while (~scanf( %d , &n)) { for (int i = 1; i <= n; ++i) scanf( %s , s[i] + 1); vector<pair<int, int> > r; bool rc = true; for (int i = 1; i <= n; ++i) { int j; for (j = 1; j <= n; ++j) if (s[i][j] == . ) { r.push_back(pair<int, int>(i, j)); break; } if (j > n) { rc = false; break; } } vector<pair<int, int> > c; bool cc = true; for (int j = 1; j <= n; ++j) { int i; for (i = 1; i <= n; ++i) if (s[i][j] == . ) { c.push_back(pair<int, int>(i, j)); break; } if (i > n) { cc = false; break; } } if (rc) { for (int i = 0; i < n; ++i) printf( %d %d n , r[i].first, r[i].second); } else if (cc) { for (int i = 0; i < n; ++i) printf( %d %d n , c[i].first, c[i].second); } else { puts( -1 ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, i, name[100], cnt; string str; char ch; cin >> n >> k; cnt = 0; for (i = 1; i <= k - 1; i++) { name[i] = ++cnt; } for (i = k; i <= n; i++) { cin >> str; if (str[0] == N ) { name[i] = name[i - k + 1]; } else { name[i] = ++cnt; } } for (i = 1; i <= n; i++) { if (name[i] <= 26) { ch = ( A - 1) + name[i]; str = ch; } else { ch = ( a ) + name[i] - 26; str = A ; str = str + ch; } cout << str << ; } } |
#include <bits/stdc++.h> int main() { std::ios_base::sync_with_stdio(0); std::cout.tie(0); std::cin.tie(0); int n; std::cin >> n; int a[n]; for (int i = 0; i < n; ++i) std::cin >> a[i]; std::sort(a, a + n); for (int i = n - 1; i >= 0; --i) { int t = sqrt(a[i]); if (t * t != a[i]) { std::cout << a[i] << n ; return 0; } } return 0; } |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// mwm20k.v: Altera's M20K mixed width RAM //
// //
// Author: Ameer M. S. Abdelhadi ( ; ) //
// SRAM-based Modular II-2D-BCAM ; The University of British Columbia , Sep. 2014 //
///////////////////////////////////////////////////////////////////////////////////
// M20K Block Mixed-Width Configurations (Simple Dual-Port RAM Mode)
// --------------------------------------------------------------------------------
// | Write | 16384 | 8192 | 4096 | 4096 | 2048 | 2048 | 1024 | 1024 | 512 | 512 |
// | Read | X 1 | X 2 | X 4 | X 5 | X 8 | X 10 | X 16 | X 20 | X32 | X40 |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// |16384 X 1 | Yes | Yes | Yes | | Yes | | Yes | | Yes | |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 8192 X 2 | Yes | Yes | Yes | | Yes | | Yes | | Yes | |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 4096 X 4 | Yes | Yes | Yes | | Yes | | Yes | | Yes | |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 4096 X 5 | | | | Yes | | Yes | | Yes | | Yes |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 2048 X 8 | Yes | Yes | Yes | | Yes | | Yes | | Yes | |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 2048 X 10 | | | | Yes | | Yes | | Yes | | Yes |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 1024 X 16 | Yes | Yes | Yes | | Yes | | Yes | | Yes | |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 1024 X 20 | | | | Yes | | Yes | | Yes | | Yes |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 512 X 32 | Yes | Yes | Yes | | Yes | | Yes | | Yes | |
// -----------|-------|------|------|------|------|------|------|------|-----|-----|
// | 512 X 40 | | | | Yes | | Yes | | Yes | | Yes |
// --------------------------------------------------------------------------------
`include "utils.vh"
module mwm20k
#( parameter WWID = 5 , // write width
parameter RWID = 40 , // read width
parameter WDEP = 4096, // write lines depth
parameter OREG = 0 , // read output reg
parameter INIT = 1 ) // initialize to zeros
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(WDEP)-1 :0] wAddr , // write address
input [WWID-1 :0] wData , // write data
input [`log2(WDEP/(RWID/WWID))-1:0] rAddr , // read address
output [RWID-1 :0] rData ); // read data
localparam RDEP = WDEP/(RWID/WWID); // read lines depth
localparam WAWID = `log2(WDEP) ; // write address width
localparam RAWID = `log2(RDEP) ; // read address width
// Altera's M20K mixed width RAM instantiation
altsyncram #( .address_aclr_b ("CLEAR0" ),
.address_reg_b ("CLOCK0" ),
.clock_enable_input_a ("BYPASS" ),
.clock_enable_input_b ("BYPASS" ),
.clock_enable_output_b ("BYPASS" ),
.intended_device_family ("Stratix V" ),
.lpm_type ("altsyncram" ),
.numwords_a (WDEP ),
.numwords_b (RDEP ),
.operation_mode ("DUAL_PORT" ),
.outdata_aclr_b ("CLEAR0" ),
.outdata_reg_b (OREG?"CLOCK0":"UNREGISTERED"),
.power_up_uninitialized (INIT?"FALSE":"TRUE"),
.ram_block_type ("M20K" ),
.read_during_write_mode_mixed_ports ("OLD_DATA" ),
.widthad_a (WAWID ),
.widthad_b (RAWID ),
.width_a (WWID ),
.width_b (RWID ),
.width_byteena_a (1 ))
altsyncm20k ( .aclr0 (rst ),
.address_a (wAddr ),
.clock0 (clk ),
.data_a (wData ),
.wren_a (wEnb ),
.address_b (rAddr ),
.q_b (rData ),
.aclr1 (1'b0 ),
.addressstall_a (1'b0 ),
.addressstall_b (1'b0 ),
.byteena_a (1'b1 ),
.byteena_b (1'b1 ),
.clock1 (1'b1 ),
.clocken0 (1'b1 ),
.clocken1 (1'b1 ),
.clocken2 (1'b1 ),
.clocken3 (1'b1 ),
.data_b ({RWID{1'b1}} ),
.eccstatus ( ),
.q_a ( ),
.rden_a (1'b1 ),
.rden_b (1'b1 ),
.wren_b (1'b0 ));
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ucb_bus_in.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: ucb_bus_in (ucb bus inbound interface block)
// Description: This interface block is instaniated by the
// UCB modules and IO Bridge to receive packets
// on the UCB bus.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module ucb_bus_in (/*AUTOARG*/
// Outputs
stall, indata_buf_vld, indata_buf,
// Inputs
rst_l, clk, vld, data, stall_a1
);
// synopsys template
parameter UCB_BUS_WIDTH = 32;
parameter REG_WIDTH = 64;
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
// Global interface
input rst_l;
input clk;
// UCB bus interface
input vld;
input [UCB_BUS_WIDTH-1:0] data;
output stall;
// Local interface
output indata_buf_vld;
output [REG_WIDTH+63:0] indata_buf;
input stall_a1;
// Internal signals
wire vld_d1;
wire stall_d1;
wire [UCB_BUS_WIDTH-1:0] data_d1;
wire skid_buf0_en;
wire vld_buf0;
wire [UCB_BUS_WIDTH-1:0] data_buf0;
wire skid_buf1_en;
wire vld_buf1;
wire [UCB_BUS_WIDTH-1:0] data_buf1;
wire skid_buf0_sel;
wire skid_buf1_sel;
wire vld_mux;
wire [UCB_BUS_WIDTH-1:0] data_mux;
wire [(REG_WIDTH+64)/UCB_BUS_WIDTH-1:0] indata_vec_next;
wire [(REG_WIDTH+64)/UCB_BUS_WIDTH-1:0] indata_vec;
wire [REG_WIDTH+63:0] indata_buf_next;
wire indata_vec0_d1;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
/************************************************************
* UCB bus interface flops
* This is to make signals going between IOB and UCB flop-to-flop
* to improve timing.
************************************************************/
dffrle_ns #(1) vld_d1_ff (.din(vld),
.rst_l(rst_l),
.en(~stall_d1),
.clk(clk),
.q(vld_d1));
dffe_ns #(UCB_BUS_WIDTH) data_d1_ff (.din(data),
.en(~stall_d1),
.clk(clk),
.q(data_d1));
dffrl_ns #(1) stall_ff (.din(stall_a1),
.clk(clk),
.rst_l(rst_l),
.q(stall));
dffrl_ns #(1) stall_d1_ff (.din(stall),
.clk(clk),
.rst_l(rst_l),
.q(stall_d1));
/************************************************************
* Skid buffer
* We need a two deep skid buffer to handle stalling.
************************************************************/
// Assertion: stall has to be deasserted for more than 1 cycle
// ie time between two separate stalls has to be
// at least two cycles. Otherwise, contents from
// skid buffer will be lost.
// Buffer 0
assign skid_buf0_en = stall_a1 & ~stall;
dffrle_ns #(1) vld_buf0_ff (.din(vld_d1),
.rst_l(rst_l),
.en(skid_buf0_en),
.clk(clk),
.q(vld_buf0));
dffe_ns #(UCB_BUS_WIDTH) data_buf0_ff (.din(data_d1),
.en(skid_buf0_en),
.clk(clk),
.q(data_buf0));
// Buffer 1
dffrl_ns #(1) skid_buf1_en_ff (.din(skid_buf0_en),
.clk(clk),
.rst_l(rst_l),
.q(skid_buf1_en));
dffrle_ns #(1) vld_buf1_ff (.din(vld_d1),
.rst_l(rst_l),
.en(skid_buf1_en),
.clk(clk),
.q(vld_buf1));
dffe_ns #(UCB_BUS_WIDTH) data_buf1_ff (.din(data_d1),
.en(skid_buf1_en),
.clk(clk),
.q(data_buf1));
/************************************************************
* Mux between skid buffer and interface flop
************************************************************/
// Assertion: stall has to be deasserted for more than 1 cycle
// ie time between two separate stalls has to be
// at least two cycles. Otherwise, contents from
// skid buffer will be lost.
assign skid_buf0_sel = ~stall_a1 & stall;
dffrl_ns #(1) skid_buf1_sel_ff (.din(skid_buf0_sel),
.clk(clk),
.rst_l(rst_l),
.q(skid_buf1_sel));
assign vld_mux = skid_buf0_sel ? vld_buf0 :
skid_buf1_sel ? vld_buf1 :
vld_d1;
assign data_mux = skid_buf0_sel ? data_buf0 :
skid_buf1_sel ? data_buf1 :
data_d1;
/************************************************************
* Assemble inbound data
************************************************************/
// valid vector
assign indata_vec_next = {vld_mux,
indata_vec[(REG_WIDTH+64)/UCB_BUS_WIDTH-1:1]};
dffrle_ns #((REG_WIDTH+64)/UCB_BUS_WIDTH) indata_vec_ff (.din(indata_vec_next),
.en(~stall_a1),
.rst_l(rst_l),
.clk(clk),
.q(indata_vec));
// data buffer
assign indata_buf_next = {data_mux,
indata_buf[REG_WIDTH+63:UCB_BUS_WIDTH]};
dffe_ns #(REG_WIDTH+64) indata_buf_ff (.din(indata_buf_next),
.en(~stall_a1),
.clk(clk),
.q(indata_buf));
// detect a new packet
dffrle_ns #(1) indata_vec0_d1_ff (.din(indata_vec[0]),
.rst_l(rst_l),
.en(~stall_a1),
.clk(clk),
.q(indata_vec0_d1));
assign indata_buf_vld = indata_vec[0] & ~indata_vec0_d1;
endmodule // ucb_bus_in
|
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << std::endl; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cerr.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } const long long maxn = (long long)2 * 1e5 + 10; const double EPS = 1e-9; const long long INF = 1e18 + 18; const long long mod = (long long)10; long long n, done[maxn], level[maxn], cnt = 0, parent[maxn]; vector<long long> graph[maxn]; set<pair<long long, long long> > seti; void bfs(long long root) { queue<long long> Q; Q.push(root); done[root] = 1, level[root] = 0; while (!Q.empty()) { long long top = Q.front(); Q.pop(); for (long long nb : graph[top]) { if (done[nb]) continue; done[nb] = 1; level[nb] = 1 + level[top]; if (level[nb] > 2) seti.insert({-level[nb], nb}); parent[nb] = top; Q.push(nb); } } } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; for (long long i = 1; i < n; i++) { long long u, v; cin >> u >> v; graph[u].push_back(v); graph[v].push_back(u); } bfs(1); while (!seti.empty()) { pair<long long, long long> top = *seti.begin(); long long tlevel = -top.first, tv = top.second; for (long long nb : graph[parent[tv]]) { auto it = seti.find({-level[nb], nb}); if (it != seti.end()) seti.erase(seti.find({-level[nb], nb})); } auto it = seti.find({-level[parent[tv]], parent[tv]}); if (it != seti.end()) seti.erase(seti.find({-level[parent[tv]], parent[tv]})); cnt++; } cout << cnt << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1.0); const double EPS = 1e-7; const int INF = 1000000000; char buf[100]; int maxl[2000000]; int maxr[2000000]; int minl[2000000]; int minr[2000000]; pair<int, int> g[2000000]; int n; int X = 0; void dfs(int, int); void add_dfs(int x, int mm) { if (X > mm) return; if (g[x].second == -1) { g[x].second = X; X++; dfs(g[x].second, mm); } add_dfs(g[x].second, mm); } bool OK = true; void dfs(int x, int mm) { if (X > minl[x]) OK = false; if (X <= maxl[x]) { g[x].first = X; X++; dfs(g[x].first, maxl[x]); } if (X > minr[x]) OK = false; if (X <= maxr[x]) { g[x].second = X; X++; dfs(g[x].second, maxr[x]); } add_dfs(x, mm); } vector<int> res; void dfs2(int x) { if (g[x].first != -1) dfs2(g[x].first); res.push_back(x); if (g[x].second != -1) dfs2(g[x].second); } int main() { int m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) { maxl[i] = 0; maxr[i] = 0; minl[i] = n; minr[i] = n; g[i] = make_pair(-1, -1); } for (int i = 0; i < m; i++) { int x, y; scanf( %d%d , &x, &y); x--; y--; scanf( %s , buf); if (buf[0] == L ) { maxl[x] = max(maxl[x], y); minl[x] = min(minl[x], y); } else { maxr[x] = max(maxr[x], y); minr[x] = min(minr[x], y); } } X = 1; dfs(0, n - 1); dfs2(0); if (!OK) printf( IMPOSSIBLE n ); else { for (int i = 0; i < res.size(); i++) { printf( %d , res[i] + 1); } printf( n ); } } |
//#############################################################################
//# Purpose: SPI master IO state-machine #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module spi_master_io
(
//clk, reset, cfg
input clk, // core clock
input nreset, // async active low reset
input cpol, // cpol
input cpha, // cpha
input lsbfirst, // send lsbfirst
input manual_mode,// sets automatic ss mode
input send_data, // controls ss in manual ss mode
input [7:0] clkdiv_reg, // baudrate
output reg [2:0] spi_state, // current spi tx state
// data to transmit
input [7:0] fifo_dout, // data payload
input fifo_empty, //
output fifo_read, // read new byte
// receive data (for sregs)
output [63:0] rx_data, // rx data
output rx_access, // transfer done
// IO interface
output reg sclk, // spi clock
output mosi, // slave input
output ss, // slave select
input miso // slave output
);
//###############
//# LOCAL WIRES
//###############
reg fifo_empty_reg;
reg load_byte;
wire rx_access;
reg ss_reg;
wire [7:0] data_out;
wire [15:0] clkphase0;
wire period_match;
wire phase_match;
wire clkout;
wire clkchange;
wire data_done;
wire spi_wait;
wire shift;
wire spi_active;
/*AUTOWIRE*/
//#################################
//# CLOCK GENERATOR
//#################################
assign clkphase0[7:0] = 'b0;
assign clkphase0[15:8] = (clkdiv_reg[7:0]+1'b1)>>1;
oh_clockdiv
oh_clockdiv (.clkdiv (clkdiv_reg[7:0]),
.clken (1'b1),
.clkrise0 (period_match),
.clkfall0 (phase_match),
.clkphase1 (16'b0),
.clkout0 (clkout),
//clocks not used ("single clock")
.clkout1 (),
.clkrise1 (),
.clkfall1 (),
.clkstable (),
//ignore for now, assume no writes while spi active
.clkchange (1'b0),
/*AUTOINST*/
// Inputs
.clk (clk),
.nreset (nreset),
.clkphase0 (clkphase0[15:0]));
//#################################
//# STATE MACHINE
//#################################
`define SPI_IDLE 3'b000 // set ss to 1
`define SPI_SETUP 3'b001 // setup time
`define SPI_DATA 3'b010 // send data
`define SPI_HOLD 3'b011 // hold time
`define SPI_MARGIN 3'b100 // pause
always @ (posedge clk or negedge nreset)
if(!nreset)
spi_state[2:0] <= `SPI_IDLE;
else
case (spi_state[2:0])
`SPI_IDLE :
spi_state[2:0] <= fifo_read ? `SPI_SETUP : `SPI_IDLE;
`SPI_SETUP :
spi_state[2:0] <= phase_match ? `SPI_DATA : `SPI_SETUP;
`SPI_DATA :
spi_state[2:0] <= data_done ? `SPI_HOLD : `SPI_DATA;
`SPI_HOLD :
spi_state[2:0] <= phase_match ? `SPI_MARGIN : `SPI_HOLD;
`SPI_MARGIN :
spi_state[2:0] <= phase_match ? `SPI_IDLE : `SPI_MARGIN;
endcase // case (spi_state[1:0])
//read fifo on phase match (due to one cycle pipeline latency
assign fifo_read = ~fifo_empty & ~spi_wait & phase_match;
//data done whne
assign data_done = fifo_empty & ~spi_wait & phase_match;
//load is the result of the fifo_read
always @ (posedge clk)
load_byte <= fifo_read;
//#################################
//# CHIP SELECT
//#################################
assign spi_active = ~(spi_state[2:0]==`SPI_IDLE | spi_state[2:0]==`SPI_MARGIN);
assign ss = ~((spi_active & ~manual_mode) | (send_data & manual_mode));
//#################################
//# DRIVE OUTPUT CLOCK
//#################################
always @ (posedge clk or negedge nreset)
if(~nreset)
sclk <= 1'b0;
else if (period_match & (spi_state[2:0]==`SPI_DATA))
sclk <= 1'b1;
else if (phase_match & (spi_state[2:0]==`SPI_DATA))
sclk <= 1'b0;
//#################################
//# TX SHIFT REGISTER
//#################################
//shift on falling edge
assign tx_shift = phase_match & (spi_state[2:0]==`SPI_DATA);
oh_par2ser #(.PW(8),
.SW(1))
par2ser (// Outputs
.dout (mosi), // serial output
.access_out (),
.wait_out (spi_wait),
// Inputs
.clk (clk),
.nreset (nreset), // async active low reset
.din (fifo_dout[7:0]), // 8 bit data from fifo
.shift (tx_shift), // shift on neg edge
.datasize (8'd7), // 8 bits at a time (0..7-->8)
.load (load_byte), // load data from fifo
.lsbfirst (lsbfirst), // serializer direction
.fill (1'b0), // fill with slave data
.wait_in (1'b0)); // no wait
//#################################
//# RX SHIFT REGISTER
//#################################
//shift in rising edge
assign rx_shift = (spi_state[2:0] == `SPI_DATA) & period_match;
oh_ser2par #(.PW(64),
.SW(1))
ser2par (//output
.dout (rx_data[63:0]), // parallel data out
//inputs
.din (miso), // serial data in
.clk (clk), // shift clk
.lsbfirst (lsbfirst), // shift direction
.shift (rx_shift)); // shift data
//generate access pulse at rise of ss
always @ (posedge clk or negedge nreset)
if(!nreset)
ss_reg <= 1'b1;
else
ss_reg <= ss;
assign rx_access = ss & ~ss_reg;
endmodule // spi_master_io
// Local Variables:
// verilog-library-directories:("." "../../common/hdl" "../../emesh/hdl")
// End:
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/15.1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2015/08/09 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= {DATA_WIDTH{1'b0}};
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= {DATA_WIDTH{1'b0}};
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_0_V
`define SKY130_FD_SC_LP__NOR2_0_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_0 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_0 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_0_V
|
/*
* Copyright (c) 2003 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
real x, y;
initial begin
$monitor("%t: x=%f, y=%f", $time, x, y);
#1 x = 1.0;
#1 y = 2.0;
#1 x = 1.5;
#1 y = 5.1;
#1 $finish(0);
end
endmodule // main
|
#include <bits/stdc++.h> using namespace std; inline int read() { int x = 0; char ch = getchar(); while (!isdigit(ch)) ch = getchar(); while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x; } struct Question { int x, l, r, dat; inline Question(int tmp1 = 0, int tmp2 = 0, int tmp3 = 0, int tmp4 = 0) { x = tmp1, l = tmp2, r = tmp3, dat = tmp4; } inline int operator<(const Question &a) const { return x < a.x; } } opt[100010]; int k; inline int lowbit(int l, int r) { int res = 0; --l; for (int i = 1; i <= k; i <<= 1) res |= (((r / i - l / i) - (((i << 1) <= k) ? (r / (i << 1) - l / (i << 1)) : (0))) & 1) * i; return res; } struct SegmentTree { int tot = 0, rot = 0; int L[100010 * 30], R[100010 * 30], tag[100010 * 30], val[100010 * 30], low[100010 * 30]; inline void upd(int k) { if (tag[k]) val[k] = low[k]; else val[k] = val[L[k]] ^ val[R[k]]; } inline void Mod(int &k, int l, int r, int x, int y, int dat) { if (y < l || r < x) return; if (!k) k = ++tot, low[k] = lowbit(l, r); if (x <= l && r <= y) return tag[k] += dat, upd(k); Mod(L[k], l, ((l + r) >> 1), x, y, dat), Mod(R[k], ((l + r) >> 1) + 1, r, x, y, dat), upd(k); } } T; int main() { int n = read(), m = read(), ans = 0; k = read(); int lim = 1, cnt = 0; for (; lim < k; lim <<= 1) ; while (m--) { int xl = read(), yl = read(); int xr = read(), yr = read(); opt[++cnt] = Question(xl, yl, yr, 1); opt[++cnt] = Question(xr + 1, yl, yr, -1); } sort(opt + 1, opt + cnt + 1); for (int i = 1; i <= cnt; i++) { if (opt[i].x != opt[i - 1].x) { int x = lowbit(opt[i - 1].x, opt[i].x - 1), y = T.val[T.rot]; int a = 0, b = 0, sum = 0; for (int j = lim; j; j >>= 1) { sum = -a * b, a += (x & j) > 0, b += (y & j) > 0, sum += a * b; if (sum & 1) ans ^= j; } } T.Mod(T.rot, 1, n, opt[i].l, opt[i].r, opt[i].dat); } if (ans) puts( Hamed ); else puts( Malek ); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const int N = 2e5 + 10; int per(int tot, int cur) { return (cur * 100 + tot / 2) / tot; } int main() { int n, k; cin >> n >> k; map<pair<int, int>, int> mc; queue<int> q; for (int i = 1; i <= n; i++) { int x; cin >> x; q.push(x); } int cur = 0; map<int, int> ans; while (!q.empty() || !mc.empty()) { while (mc.size() < k && !q.empty()) { mc[make_pair(q.front(), q.size())] = 0; q.pop(); } vector<pair<int, int>> vp; int key = per(n, cur); for (auto& p : mc) { p.second++; if (p.second == key) ans[p.first.second] = 1; if (p.second == p.first.first) vp.emplace_back(p.first); } for (auto& p : vp) mc.erase(p), cur++; } printf( %d n , ans.size()); return 0; } |
`include "../../../rtl/verilog/gfx/gfx_wbm_read.v"
module wbm_r_bench();
// wishbone signals
reg clk_i; // master clock reg
reg rst_i; // synchronous active high reset
wire cyc_o; // cycle wire
wire stb_o; // strobe output
wire [ 2:0] cti_o; // cycle type id
wire [ 1:0] bte_o; // burst type extension
wire we_o; // write enable wire
wire [31:0] adr_o; // address wire
wire [ 3:0] sel_o; // byte select wires (only 32bits accesses are supported)
reg ack_i; // wishbone cycle acknowledge
reg err_i; // wishbone cycle error
reg [31:0] dat_i; // wishbone data in
wire sint_o; // non recoverable error, interrupt host
// Renderer stuff
reg read_request_i;
reg [31:2] texture_addr_i;
reg [3:0] texture_sel_i;
wire [31:0] texture_dat_o;
wire texture_data_ack;
initial begin
$dumpfile("wbm_r.vcd");
$dumpvars(0,wbm_r_bench);
// init values
ack_i = 0;
clk_i = 1;
rst_i = 1;
read_request_i = 0;
err_i = 0;
texture_sel_i = 4'hf;
dat_i = 0;
texture_addr_i = 0;
//timing
#4 rst_i =0;
#2 read_request_i = 1;
#2 read_request_i = 0;
// end sim
#100 $finish;
end
always begin
#1 ack_i = !ack_i & cyc_o;
end
always begin
#1 clk_i = ~clk_i;
end
gfx_wbm_read wbm_r(
// WB signals
.clk_i (clk_i),
.rst_i (rst_i),
.cyc_o (cyc_o),
.stb_o (stb_o),
.cti_o (cti_o),
.bte_o (bte_o),
.we_o (we_o),
.adr_o (adr_o),
.sel_o (sel_o),
.ack_i (ack_i),
.err_i (err_i),
.dat_i (dat_i),
.sint_o (sint_o),
// Control signals
.read_request_i (read_request_i),
.texture_addr_i (texture_addr_i),
.texture_sel_i (texture_sel_i),
.texture_dat_o (texture_dat_o),
.texture_data_ack (texture_data_ack)
);
endmodule
|
/*
* Copyright (c) 2003 Stephen Williams ()
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module assignsigned();
parameter foo = 10;
reg signed [15:0] bar = -1;
wire baz;
assign baz = (bar < $signed(foo));
initial begin
#1 $display("bar=%h(%0d), foo=%0d, baz = %b", bar, bar, foo, baz);
if (baz !== 1'b1) begin
$display("FAILED -- Compare returns %b instead of 1.", baz);
$finish;
end
$display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int step[8][2] = {{1, 0}, {-1, 0}, {0, 1}, {0, -1}, {1, 1}, {1, -1}, {-1, 1}, {-1, -1}}; template <class T> inline T abs1(T a) { return a < 0 ? -a : a; } const int maxn = 100110; template <class t> struct segment_node { int be, en; t num, add; }; template <class t> struct segment_tree { int l; segment_node<t> tree[maxn * 4]; inline int gleft(int no) { return no << 1; } inline int gright(int no) { return (no << 1) + 1; } inline int gfa(int no) { return no >> 1; } inline segment_tree() { l = 0; } void build(int no, int l, int r) { if (l == r) { tree[no].be = tree[no].en = l; tree[no].num = -1; tree[no].add = -1; return; } tree[no].be = l; tree[no].en = r; int mid = (l + r) / 2; build(gleft(no), l, mid); build(gright(no), mid + 1, r); tree[no].add = -1; } inline void relax(int no) { tree[gleft(no)].add = tree[no].add; tree[gright(no)].add = tree[no].add; tree[no].add = -1; } void down(int l, int r, int no, t ranadd) { if (tree[no].be != tree[no].en && tree[no].add != -1) relax(no); if (l <= tree[no].be && r >= tree[no].en) { tree[no].add = ranadd; return; } int mid = (tree[no].be + tree[no].en) / 2; if (r >= tree[no].be && l <= mid) down(l, r, gleft(no), ranadd); if (r >= mid + 1 && l <= tree[no].en) down(l, r, gright(no), ranadd); } t getnum(int loc, int no) { if (tree[no].add != -1) { int ans = tree[no].add; if (tree[no].be != tree[no].en) relax(no); return ans; } if (tree[no].be == tree[no].en) return tree[no].num; int mid = (tree[no].be + tree[no].en) / 2; if (loc <= mid) return getnum(loc, gleft(no)); else return getnum(loc, gright(no)); } }; segment_tree<int> sgt[4]; struct segment { int from, to, no; segment(int a = 0, int b = 0, int no1 = 0) { from = min(a, b); to = max(a, b); no = no1; } }; vector<segment> orig[2][maxn]; pair<int, int> orig1[maxn * 2], origto[maxn]; long long origdir[maxn * 2], origstep[maxn]; struct vec { int no, loc; vec(int a = 0, int b = 0) : no(a), loc(b) {} }; vector<vec> she[4][maxn]; map<pair<int, int>, int> trans; long long narrow, b, nq; struct node { int fa, delta; long long dis; node(int a = 0, int b = 0, int c = 0) { fa = a, dis = b, delta = c; } } fa[60][maxn * 2]; inline int finddir(pair<int, int> from, pair<int, int> to) { to.first -= from.first; to.second -= from.second; if (to.first) to.first /= abs(to.first); if (to.second) to.second /= abs(to.second); for (int j = 0; j < 4; j++) if (to.first == step[j][0] && to.second == step[j][1]) return j; return 0; } inline long long cntdis(pair<int, int> co, pair<int, int> co1) { return abs(co.first - co1.first) + abs(co.second - co1.second); } inline pair<long long, long long> finddis(int from, int dir, int to) { pair<long long, long long> ans; if (to == -1) { ans = orig1[from]; if (dir > 1) swap(ans.first, ans.second); if (!(dir & 1)) ans.first = b - ans.first; ans.second = 0; return ans; } if ((origdir[to] ^ dir) < 2) { long long dis1 = orig1[from].first - orig1[to].first, dis2 = orig1[from].first - origto[to].first; if (orig1[to].first == orig1[from].first && orig1[to].first == origto[to].first) dis1 = orig1[from].second - orig1[to].second, dis2 = orig1[from].second - origto[to].second; if (dis1 * dis2 < 0) { ans.first = 0; ans.second = abs1(dis1); } else { ans.first = min(abs1(dis1), abs1(dis2)); ans.second = 0; if (abs1(dis1) > abs1(dis2)) ans.second = abs1(dis1) - abs1(dis2); } return ans; } ans = orig1[to]; ans.first -= orig1[from].first; ans.second -= orig1[from].second; if (dir > 1) swap(ans.first, ans.second); ans.first = abs1(ans.first); ans.second = abs1(ans.second); return ans; } int main() { scanf( %I64d%I64d , &narrow, &b); for (int i = 0; i < narrow; i++) { pair<int, int> from, to; scanf( %d%d%d%d , &from.first, &from.second, &to.first, &to.second); trans[from] = i; orig1[i] = from; origto[i] = to; if (from.first == to.first) { orig[0][from.first].push_back(segment(from.second, to.second, i)); orig[1][max(from.second, to.second)].push_back( segment(from.first, from.first, i)); orig[1][min(from.second, to.second)].push_back( segment(from.first, from.first, i)); } else { orig[1][from.second].push_back(segment(from.first, to.first, i)); orig[0][max(from.first, to.first)].push_back( segment(from.second, from.second, i)); orig[0][min(from.first, to.first)].push_back( segment(from.second, from.second, i)); } int randir = finddir(from, to); origdir[i] = randir; if (randir > 1) swap(to.first, to.second); she[randir][to.first].push_back(vec(i, to.second)); } scanf( %I64d , &nq); for (int i = 0; i < nq; i++) { pair<int, int> st; char randirc; long long step1, randir; scanf( %d %d %c %I64d , &st.first, &st.second, &randirc, &step1); orig1[i + narrow] = st; trans[st] = i + narrow; if (randirc == L ) randir = 1; if (randirc == R ) randir = 0; if (randirc == U ) randir = 2; if (randirc == D ) randir = 3; origdir[i + narrow] = randir, origstep[i] = step1; if (randir > 1) swap(st.first, st.second); she[randir][st.first].push_back(vec(i + narrow, st.second)); } for (int i = 0; i < 4; i++) { sgt[i].build(1, 0, b + 1); int from = 0, add = 1, to = b + 1; if (!(i & 1)) from = b, add = -1, to = -1; int biao = i / 2; for (int j = from; j != to; j += add) { for (int t = 0; t < (int)she[i][j].size(); t++) if (she[i][j][t].no < narrow) { fa[0][she[i][j][t].no].fa = sgt[i].getnum(she[i][j][t].loc, 1); pair<long long, long long> randis = finddis(she[i][j][t].no, i, fa[0][she[i][j][t].no].fa); fa[0][she[i][j][t].no].dis = randis.first; fa[0][she[i][j][t].no].delta = randis.second; } for (int t = 0; t < (int)orig[biao][j].size(); t++) sgt[i].down(orig[biao][j][t].from, orig[biao][j][t].to, 1, orig[biao][j][t].no); for (int t = 0; t < (int)she[i][j].size(); t++) if (she[i][j][t].no >= narrow) { fa[0][she[i][j][t].no].fa = sgt[i].getnum(she[i][j][t].loc, 1); pair<long long, long long> randis = finddis(she[i][j][t].no, i, fa[0][she[i][j][t].no].fa); fa[0][she[i][j][t].no].dis = randis.first; fa[0][she[i][j][t].no].delta = randis.second; } } } for (int i = 1; i < 60; i++) { for (int j = 0; j < narrow + nq; j++) { if (fa[i - 1][j].fa != -1) { fa[i][j].fa = fa[i - 1][fa[i - 1][j].fa].fa; fa[i][j].delta = fa[i - 1][fa[i - 1][j].fa].delta; fa[i][j].dis = fa[i - 1][fa[i - 1][j].fa].dis + fa[i - 1][j].dis - fa[i - 1][j].delta; } else fa[i][j] = fa[i - 1][j]; if (fa[i][j].dis > 1000000000000000ll) fa[i][j].dis = 1000000000000001ll; } } for (long long i1 = 0; i1 < nq; i1++) { long long no = i1 + narrow; int en = 59; for (; en != -1;) { int ranbe = -1, ranen = en; while (ranbe < ranen) { int mid = (ranbe + ranen + 1) / 2; if (fa[mid][no].dis > origstep[i1] || fa[mid][no].fa == -1) ranen = mid - 1; else ranbe = mid; } en = ranbe; if (en == -1) break; origstep[i1] -= fa[ranbe][no].dis - fa[ranbe][no].delta; no = fa[ranbe][no].fa; } printf( %I64d %I64d n , max(0ll, min(b, orig1[no].first + origstep[i1] * step[origdir[no]][0])), max(0ll, min(b, orig1[no].second + origstep[i1] * step[origdir[no]][1]))); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; int R[101]; double dp[100100], sum[100100]; int main() { scanf( %d%d , &n, &m); if (m == 1) { puts( 1 ); return 0; } int score = 0; dp[0] = 1; double f = 1. / (m - 1); for (int i = 0; i < n; ++i) { scanf( %d , R + i); score += R[i]; } for (int i = 0; i < n; ++i) { int r = R[i]; sum[0] = dp[0]; for (int j = 1; j <= min(score - 1, (i + 1) * m); ++j) { sum[j] = sum[j - 1] + dp[j]; } for (int j = min(score - 1, (i + 1) * m); j > 0; --j) { dp[j] = sum[j - 1]; if (j - m - 1 >= 0) dp[j] -= sum[j - m - 1]; if (j - r >= 0) dp[j] -= dp[j - r]; dp[j] *= f; } dp[0] = 0; } double res = 1; for (int i = 0; i < score; ++i) { res += dp[i] * (m - 1); } printf( %.15lf n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; vector<char> v; int n; string s; bool potR() { int freq[1000]; freq[ G ] = 0; freq[ B ] = 0; freq[ R ] = 0; for (int i = 0; i < s.size(); ++i) { ++freq[s[i]]; } int cnt1 = freq[ B ]; int cnt2 = freq[ G ]; if (cnt1 >= 1 && cnt2 >= 1) { return true; } if (cnt1 == 0 && cnt2 == 0) { return true; } if (cnt1 == 0 && cnt2 >= 2) { if (freq[ R ] >= 1) { return true; } else { return false; } } if (cnt1 >= 2 && cnt2 == 0) { if (freq[ R ] >= 1) { return true; } else { return false; } } return false; } bool potG() { int freq[1000]; freq[ G ] = 0; freq[ B ] = 0; freq[ R ] = 0; for (int i = 0; i < s.size(); ++i) { ++freq[s[i]]; } int cnt1 = freq[ R ]; int cnt2 = freq[ B ]; if (cnt1 >= 1 && cnt2 >= 1) { return true; } if (cnt1 == 0 && cnt2 == 0) { return true; } if (cnt1 == 0 && cnt2 >= 2) { if (freq[ G ] >= 1) { return true; } else { return false; } } if (cnt1 >= 2 && cnt2 == 0) { if (freq[ G ] >= 1) { return true; } else { return false; } } return false; } bool potB() { int freq[1000]; freq[ G ] = 0; freq[ B ] = 0; freq[ R ] = 0; for (int i = 0; i < s.size(); ++i) { ++freq[s[i]]; } int cnt1 = freq[ G ]; int cnt2 = freq[ R ]; if (cnt1 >= 1 && cnt2 >= 1) { return true; } if (cnt1 == 0 && cnt2 == 0) { return true; } if (cnt1 == 0 && cnt2 >= 2) { if (freq[ B ] >= 1) { return true; } else { return false; } } if (cnt1 >= 2 && cnt2 == 0) { if (freq[ B ] >= 1) { return true; } else { return false; } } return false; } int main() { ios::sync_with_stdio(false); cin >> n; cin.get(); cin >> s; v.push_back( R ); v.push_back( G ); v.push_back( B ); set<char> mySet; if (potR()) { mySet.insert( R ); } if (potB()) { mySet.insert( B ); } if (potG()) { mySet.insert( G ); } for (auto i : mySet) { cout << i; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 10; int dp[4][N]; string str2[N], str3[N]; set<string> ans; int n; int cal(int len, int idx) { if (dp[len][idx] != -1) return dp[len][idx]; if (idx == n - 1) return dp[len][idx] = 1; ; int x = 0; if (idx + 2 < n) { if (len == 2 && str2[idx] == str2[idx + 2]) { } else x |= cal(2, idx + 2); } if (idx + 3 < n) { if (len == 3 && str3[idx] == str3[idx + 3]) { } else x |= cal(3, idx + 3); } x = x ? 1 : 0; return dp[len][idx] = x; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); string s; cin >> s; n = s.length(); for (int i = 0; i < n - 1; ++i) { str2[i + 1] = s.substr(i, 2); if (i + 2 < n) str3[i + 2] = s.substr(i, 3); } for (int i = 0; i < 4; ++i) { for (int j = 0; j <= n; ++j) dp[i][j] = -1; } for (int i = 6; i < n; ++i) { if (dp[2][i] == -1) cal(2, i); if (i > 6 && dp[3][i] == -1) cal(3, i); } for (int i = 5; i < n; ++i) { if (dp[2][i] > 0) ans.insert(str2[i]); if (dp[3][i] > 0) ans.insert(str3[i]); } cout << ans.size() << endl; for (auto I : ans) cout << I << endl; } |
#include <bits/stdc++.h> using namespace std; char getc() { char c = getchar(); while ((c < A || c > Z ) && (c < a || c > z ) && (c < 0 || c > 9 )) c = getchar(); return c; } long long gcd(long long n, long long m) { return m == 0 ? n : gcd(m, n % m); } long long read() { long long x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 1) + (x << 3) + (c ^ 48), c = getchar(); return x * f; } int n, m; long long a[300010], b[300010]; signed main() { n = read(), m = read(); for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 1; i <= m; i++) b[i] = read(); sort(a + 1, a + n + 1); long long u = 0; for (int i = 2; i <= n; i++) u = gcd(u, a[i] - a[i - 1]); for (int i = 1; i <= m; i++) if (u % b[i] == 0) { cout << YES << endl; cout << a[1] << << i; return 0; } cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 10; bool prime[N]; int phi[N], deg[N]; void sieve(); int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); sieve(); int n, k; cin >> n >> k; priority_queue<pair<int, int>, vector<pair<int, int>>, greater<pair<int, int>>> q; for (int i = 3; i <= n; ++i) { if (deg[i] == 0) { q.push({phi[i], i}); } for (int j = 2 * i; j <= n; j += i) { ++deg[j]; } } long long ans = (k == 1 ? 1 : 2); while (k--) { auto cur = q.top(); q.pop(); int i = cur.second; ans += phi[i]; for (int j = 2 * i; j <= n; j += i) { --deg[j]; if (deg[j] == 0) { q.push({phi[j], j}); } } } cout << ans << n ; } void sieve() { for (int i = 2; i < N; ++i) { prime[i] = true; phi[i] = i; } for (int i = 2; i < N; ++i) { if (prime[i]) { for (int j = i; j < N; j += i) { prime[j] = false; phi[j] /= i; phi[j] *= (i - 1); } } } } |
// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
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// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
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// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
mig_7series_v4_0_ddr_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long int r, x, y, x1, y1, t, u; double ans = 0; cin >> r >> x >> y >> x1 >> y1; t = abs(x - x1); u = abs(y - y1); ans = t * t + u * u; ans = sqrt(ans); ans = ans / (2 * r); ans = ceil(ans); cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a; cin >> a; if (a == 1) { cout << 1 << << 1 << endl << 1 << endl; } else { cout << 2 * (a - 1) << << 2 << endl << 1 << << 2 << endl; } return 0; } |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The DTCM-SRAM module to implement DTCM SRAM
//
// ====================================================================
`include "e203_defines.v"
`ifdef E203_HAS_DTCM //{
module e203_dtcm_ram(
input sd,
input ds,
input ls,
input cs,
input we,
input [`E203_DTCM_RAM_AW-1:0] addr,
input [`E203_DTCM_RAM_MW-1:0] wem,
input [`E203_DTCM_RAM_DW-1:0] din,
output [`E203_DTCM_RAM_DW-1:0] dout,
input rst_n,
input clk
);
sirv_gnrl_ram #(
.FORCE_X2ZERO(1),//Always force X to zeros
.DP(`E203_DTCM_RAM_DP),
.DW(`E203_DTCM_RAM_DW),
.MW(`E203_DTCM_RAM_MW),
.AW(`E203_DTCM_RAM_AW)
) u_e203_dtcm_gnrl_ram(
.sd (sd ),
.ds (ds ),
.ls (ls ),
.rst_n (rst_n ),
.clk (clk ),
.cs (cs ),
.we (we ),
.addr(addr),
.din (din ),
.wem (wem ),
.dout(dout)
);
endmodule
`endif//}
|
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> inline void smin(T &a, U b) { if (a > b) a = b; } template <typename T, typename U> inline void smax(T &a, U b) { if (a < b) a = b; } template <class T> inline void gn(T &first) { char c, sg = 0; while (c = getchar(), (c > 9 || c < 0 ) && c != - ) ; for ((c == - ? sg = 1, c = getchar() : 0), first = 0; c >= 0 && c <= 9 ; c = getchar()) first = (first << 1) + (first << 3) + c - 0 ; if (sg) first = -first; } template <class T> inline void print(T first) { if (first < 0) { putchar( - ); return print(-first); } if (first < 10) { putchar( 0 + first); return; } print(first / 10); putchar(first % 10 + 0 ); } int power(int a, int b, int m, int ans = 1) { for (; b; b >>= 1, a = 1LL * a * a % m) if (b & 1) ans = 1LL * ans * a % m; return ans; } char s[100011]; pair<int, int> dp[100011]; int cnt[100011], mx[100011][2]; int main() { int n, m; cin >> n >> s + 1 >> m; for (int i = 1; i <= n; i++) { if (s[i] != b ) mx[i][0] = mx[i - 1][1] + 1; if (s[i] != a ) mx[i][1] = mx[i - 1][0] + 1; cnt[i] = cnt[i - 1] + (s[i] == ? ); dp[i] = dp[i - 1]; if (mx[i][!(m & 1)] >= m) { if (dp[i - m].first + 1 == dp[i].first) { smin(dp[i].second, dp[i - m].second + cnt[i] - cnt[i - m]); } if (dp[i - m].first + 1 > dp[i].first) { dp[i].first = dp[i - m].first + 1; dp[i].second = dp[i - m].second + cnt[i] - cnt[i - m]; } } } cout << dp[n].second << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[200005]; long double b[200005]; int n; long double dp1[200005], dp2[200005]; long double check(long double val) { int i; for (i = 0; i < n; i++) b[i + 1] = a[i] - val; dp1[1] = b[1]; long double ans = b[1]; for (i = 2; i <= n; i++) { dp1[i] = max(dp1[i - 1], (long double)0) + b[i]; ans = max(ans, dp1[i]); } for (i = 0; i <= n + 1; i++) b[i + 1] = -b[i + 1]; ans = max(ans, b[1]); dp2[1] = b[1]; for (i = 2; i <= n; i++) { dp2[i] = max(dp2[i - 1], (long double)0) + b[i]; ans = max(ans, dp2[i]); } return ans; } int main() { scanf( %d , &n); int i; for (i = 0; i < n; i++) scanf( %d , &a[i]); long double lo, hi; lo = -(1e4); hi = 1e4; long double eps = 1e-12; while (lo < hi - eps) { long double mid1, mid2; mid1 = (2 * lo + hi) / 3; mid2 = (lo + hi * 2) / 3; long double sol1, sol2; sol1 = check(mid1); sol2 = check(mid2); if (sol1 < sol2 - eps) { hi = mid2; } else { lo = mid1; } } cout << fixed << setprecision(9) << check(lo) << endl; } |
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("return.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("return_tb.vcd");
$dumpvars(0, cpu_tb);
if(USE_64B) begin
#12
`assert(result, 42);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else begin
#12
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long is_query = -(1LL << 62); struct line { long long m, b; mutable function<const line*()> succ; bool operator<(const line& rhs) const { if (rhs.b != is_query) return m < rhs.m; const line* s = succ(); if (!s) return 0; long long x = rhs.m; return b - s->b < (s->m - m) * x; } }; struct dynamic_hull : public multiset<line> { const long long inf = LLONG_MAX; bool bad(iterator y) { auto z = next(y); if (y == begin()) { if (z == end()) return 0; return y->m == z->m && y->b <= z->b; } auto x = prev(y); if (z == end()) return y->m == x->m && y->b <= x->b; long long v1 = (x->b - y->b); if (y->m == x->m) v1 = x->b > y->b ? inf : -inf; else v1 /= (y->m - x->m); long long v2 = (y->b - z->b); if (z->m == y->m) v2 = y->b > z->b ? inf : -inf; else v2 /= (z->m - y->m); return v1 >= v2; } void insert_line(long long m, long long b) { auto y = insert({m, b}); y->succ = [=] { return next(y) == end() ? 0 : &*next(y); }; if (bad(y)) { erase(y); return; } while (next(y) != end() && bad(next(y))) erase(next(y)); while (y != begin() && bad(prev(y))) erase(prev(y)); } __int128 eval(long long x) { auto l = *lower_bound(line{x, is_query}); return (__int128)l.m * x + l.b; } }; int main() { int n; long long s; cin >> n >> s; vector<pair<long long, long long>> buildings(n); for (int i = 0; i < n; ++i) { cin >> buildings[i].second >> buildings[i].first; } sort(buildings.begin(), buildings.end()); assert(buildings[0].first == 0); vector<long long> min_time(n + 1, s + 1); vector<long long> max_cookies(n + 1, 0); min_time[0] = 0; max_cookies[0] = 0; dynamic_hull dp_opt; dp_opt.insert_line(buildings[0].second, 0); for (int i = 1; i < n; ++i) { long long left = min_time[i - 1]; long long right = s + 50; while (left + 1 < right) { long long mid = (left + right) / 2; if (dp_opt.eval(mid) >= buildings[i].first) { right = mid; } else { left = mid; } } if (dp_opt.eval(left) - buildings[i].first < 0) { ++left; } min_time[i] = left; max_cookies[i] = dp_opt.eval(left) - buildings[i].first; dp_opt.insert_line( buildings[i].second, max_cookies[i] - 1LL * buildings[i].second * min_time[i]); } long long ans = s; for (int i = 0; i < n; ++i) { ans = min(ans, min_time[i] + (s - max_cookies[i] - 1) / buildings[i].second + 1); } cout << ans << endl; return 0; } |
module RAMB16_S18_S18(
input WEA,
input ENA,
input SSRA,
input CLKA,
input [9:0] ADDRA,
input [15:0] DIA,
input [1:0] DIPA,
// output [3:0] DOPA,
output [15:0] DOA,
input WEB,
input ENB,
input SSRB,
input CLKB,
input [9:0] ADDRB,
input [15:0] DIB,
input [1:0] DIPB,
// output [3:0] DOPB,
output [15:0] DOB);
parameter WRITE_MODE_A = "write_first";
parameter WRITE_MODE_B = "write_first";
parameter INIT_00=256'd0;
parameter INIT_01=256'd0;
parameter INIT_02=256'd0;
parameter INIT_03=256'd0;
parameter INIT_04=256'd0;
parameter INIT_05=256'd0;
parameter INIT_06=256'd0;
parameter INIT_07=256'd0;
parameter INIT_08=256'd0;
parameter INIT_09=256'd0;
parameter INIT_0A=256'd0;
parameter INIT_0B=256'd0;
parameter INIT_0C=256'd0;
parameter INIT_0D=256'd0;
parameter INIT_0E=256'd0;
parameter INIT_0F=256'd0;
parameter INIT_10=256'd0;
parameter INIT_11=256'd0;
parameter INIT_12=256'd0;
parameter INIT_13=256'd0;
parameter INIT_14=256'd0;
parameter INIT_15=256'd0;
parameter INIT_16=256'd0;
parameter INIT_17=256'd0;
parameter INIT_18=256'd0;
parameter INIT_19=256'd0;
parameter INIT_1A=256'd0;
parameter INIT_1B=256'd0;
parameter INIT_1C=256'd0;
parameter INIT_1D=256'd0;
parameter INIT_1E=256'd0;
parameter INIT_1F=256'd0;
parameter INIT_20=256'd0;
parameter INIT_21=256'd0;
parameter INIT_22=256'd0;
parameter INIT_23=256'd0;
parameter INIT_24=256'd0;
parameter INIT_25=256'd0;
parameter INIT_26=256'd0;
parameter INIT_27=256'd0;
parameter INIT_28=256'd0;
parameter INIT_29=256'd0;
parameter INIT_2A=256'd0;
parameter INIT_2B=256'd0;
parameter INIT_2C=256'd0;
parameter INIT_2D=256'd0;
parameter INIT_2E=256'd0;
parameter INIT_2F=256'd0;
parameter INIT_30=256'd0;
parameter INIT_31=256'd0;
parameter INIT_32=256'd0;
parameter INIT_33=256'd0;
parameter INIT_34=256'd0;
parameter INIT_35=256'd0;
parameter INIT_36=256'd0;
parameter INIT_37=256'd0;
parameter INIT_38=256'd0;
parameter INIT_39=256'd0;
parameter INIT_3A=256'd0;
parameter INIT_3B=256'd0;
parameter INIT_3C=256'd0;
parameter INIT_3D=256'd0;
parameter INIT_3E=256'd0;
parameter INIT_3F=256'd0;
RAMB16_RIGEL #(.WRITE_MODE_A(WRITE_MODE_A),.WRITE_MODE_B(WRITE_MODE_B),.BITS(16),.INIT_00(INIT_00),.INIT_01(INIT_01),.INIT_02(INIT_02),.INIT_03(INIT_03),.INIT_04(INIT_04),.INIT_05(INIT_05),.INIT_06(INIT_06),.INIT_07(INIT_07),.INIT_08(INIT_08),.INIT_09(INIT_09),.INIT_0A(INIT_0A),.INIT_0B(INIT_0B),.INIT_0C(INIT_0C),.INIT_0D(INIT_0D),.INIT_0E(INIT_0E),.INIT_0F(INIT_0F),.INIT_10(INIT_10),.INIT_11(INIT_11),.INIT_12(INIT_12),.INIT_13(INIT_13),.INIT_14(INIT_14),.INIT_15(INIT_15),.INIT_16(INIT_16),.INIT_17(INIT_17),.INIT_18(INIT_18),.INIT_19(INIT_19),.INIT_1A(INIT_1A),.INIT_1B(INIT_1B),.INIT_1C(INIT_1C),.INIT_1D(INIT_1D),.INIT_1E(INIT_1E),.INIT_1F(INIT_1F),.INIT_20(INIT_20),.INIT_21(INIT_21),.INIT_22(INIT_22),.INIT_23(INIT_23),.INIT_24(INIT_24),.INIT_25(INIT_25),.INIT_26(INIT_26),.INIT_27(INIT_27),.INIT_28(INIT_28),.INIT_29(INIT_29),.INIT_2A(INIT_2A),.INIT_2B(INIT_2B),.INIT_2C(INIT_2C),.INIT_2D(INIT_2D),.INIT_2E(INIT_2E),.INIT_2F(INIT_2F),.INIT_30(INIT_30),.INIT_31(INIT_31),.INIT_32(INIT_32),.INIT_33(INIT_33),.INIT_34(INIT_34),.INIT_35(INIT_35),.INIT_36(INIT_36),.INIT_37(INIT_37),.INIT_38(INIT_38),.INIT_39(INIT_39),.INIT_3A(INIT_3A),.INIT_3B(INIT_3B),.INIT_3C(INIT_3C),.INIT_3D(INIT_3D),.INIT_3E(INIT_3E),.INIT_3F(INIT_3F)) inner_ram(.WEA(WEA),.ENA(ENA),.SSRA(SSRA),.CLKA(CLKA),.ADDRA(ADDRA),.DIA(DIA),.DIPA(DIPA),.DOA(DOA),.WEB(WEB),.ENB(ENB),.SSRB(SSRB),.CLKB(CLKB),.ADDRB(ADDRB),.DIB(DIB),.DIPB(DIPB),.DOB(DOB));
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> v[300010]; int centroid[300010], Next[300010], par[300010], sz[300010]; void dfs(int cur) { sz[cur] = 1; int maxx = 0; Next[cur] = 0; for (int u : v[cur]) if (u != par[cur]) { dfs(u); sz[cur] += sz[u]; if (sz[u] > maxx) { maxx = sz[u]; Next[cur] = u; } } if (maxx == 0) { centroid[cur] = cur; return; } int u = centroid[Next[cur]]; while (u != cur) { if (sz[Next[u]] * 2 > sz[cur]) break; u = par[u]; } if (sz[Next[u]] * 2 > sz[cur]) u = Next[u]; centroid[cur] = u; } int main() { int n, m, i; scanf( %d , &n); scanf( %d , &m); for (i = 2; i <= n; ++i) { scanf( %d , &par[i]); v[i].push_back(par[i]); v[par[i]].push_back(i); } sz[0] = 0; dfs(1); for (i = 0; i < m; ++i) { int x; scanf( %d , &x); printf( %d n , centroid[x]); } } |
#include <bits/stdc++.h> using namespace std; set<int> si; int n, k; bool solve(set<int> &cands, vector<int> &chosen) { if (cands.empty()) { if (chosen.empty()) { return false; } for (int i = 0; i < k; ++i) { int cnt = 0; for (const int num : chosen) { cnt += (((num >> i) & 0x1) ? -1 : 1); } if (cnt < 0) { return false; } } return true; } int val = *cands.begin(); bool ok = false; cands.erase(val); ok |= solve(cands, chosen); chosen.push_back(val); ok |= solve(cands, chosen); chosen.pop_back(); cands.insert(val); return ok; } int main(int argc, char **argv) { std::ios::sync_with_stdio(false); cin >> n >> k; for (int i = 0; i < n; ++i) { int val = 0; for (int j = 0; j < k; ++j) { int t; cin >> t; val |= (t << j); } si.insert(val); } vector<int> chosen; cout << (solve(si, chosen) ? YES n : NO n ); } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using vi = vector<int>; using pii = pair<int, int>; int main() { ios::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<int> A(n); vector<int> P(n + 1); for (auto &x : A) cin >> x; for (int i = 0; i < n; ++i) P[A[i]] = i; int cnt = 0; vector<vector<int>> sol; for (int kk = 0; kk < n; ++kk) { if (is_sorted(A.begin(), A.end())) break; ++cnt; int goal = -1; for (int i = 1; i <= n - 1; ++i) { if (P[i] > P[i + 1]) { goal = i; break; } } vector<vector<int>> G; G.push_back({}); int state = 0; for (int i = 0; i < n; ++i) { if (state == 0) { if (A[i] != goal + 1) { G.back().push_back(A[i]); } else { G.push_back({A[i]}); state = 1; } } else if (state == 1) { if (A[i] == goal) { G.push_back({A[i]}); state = 3; G.push_back({}); } else if (A[i] == A[i - 1] + 1) G.back().push_back(A[i]); else { G.push_back({A[i]}); state = 2; } } else if (state == 2) { G.back().push_back(A[i]); if (A[i] == goal) { state = 3; G.push_back({}); } } else { G.back().push_back(A[i]); } } sol.push_back({}); for (auto &x : G) { if (!x.empty()) sol.back().push_back(x.size()); } reverse(G.begin(), G.end()); { int i = 0; for (auto &g : G) for (auto x : g) A[i++] = x; } for (int i = 0; i < n; ++i) P[A[i]] = i; } assert(is_sorted(A.begin(), A.end())); cout << cnt << n ; for (auto &s : sol) { cout << s.size() << ; for (auto &x : s) cout << x << ; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 200000; const long long mod = 1e9 + 7; long long fac[maxn + 5], inv[maxn + 5]; long long f[2005]; struct node { long long x, y; } data[2005]; long long qmod(long long a, long long b) { long long ans = 1; a = a % mod; while (b) { if (b & 1) { ans = (ans * a) % mod; } b = b / 2; a = (a * a) % mod; } return ans; } void init() { fac[0] = 1; for (long long i = 1; i <= maxn; i++) { fac[i] = (fac[i - 1] * i) % mod; } } long long com(long long n, long long m) { if (n < m) return 0; else if (n == m) return 1; else return (fac[n] * qmod(fac[m] * fac[n - m], mod - 2)) % mod; } long long Lucas(long long n, long long m) { if (m == 0) return 1; else return (com(n % mod, m % mod) * Lucas(n / mod, m / mod)) % mod; } bool cmp(node a, node b) { if (a.x < b.x) return true; else if (a.x == b.x) { if (a.y < b.y) return true; else return false; } else return false; } int main(int argc, char const *argv[]) { long long h, w, n; init(); scanf( %lld %lld %lld , &h, &w, &n); for (int i = 1; i <= n; i++) { scanf( %lld %lld , &data[i].x, &data[i].y); } sort(data + 1, data + 1 + n, cmp); memset(f, 0, sizeof(f)); n++; data[n].x = h; data[n].y = w; for (int i = 1; i <= n; i++) { long long dx, dy; dx = data[i].x - 1; dy = data[i].y - 1; f[i] = Lucas(dx + dy, dx); for (int j = 1; j < i; j++) { if (data[i].x >= data[j].x && data[i].y >= data[j].y) { dx = data[i].x - data[j].x; dy = data[i].y - data[j].y; f[i] = f[i] - (f[j] * Lucas(dx + dy, dx)) % mod; f[i] = (f[i] + mod) % mod; } } } cout << (f[n] + mod) % mod << endl; return 0; } |
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_cmd_fsm.v
//
// Description:
// Simple state machine to handle sending commands from AXI to MC. The flow:
// 1. A transaction can only be initiaited when axvalid is true and data_rdy
// is true. For writes, data_rdy means that one completed BL8 or BL4 write
// data has been pushed into the MC write FIFOs. For read operations,
// data_rdy indicates that there is enough room to push the transaction into
// the read FIF & read transaction fifo in the shim. If the FIFO's in the
// read channel module is full, then the state machine waits for the
// FIFO's to drain out.
//
// 2. When CMD_EN is asserted, it remains high until we sample CMD_FULL in
// a low state. When CMD_EN == 1'b1, and CMD_FULL == 1'b0, then the command
// has been accepted. When the command is accepted, if the next_pending
// signal is high we will incremented to the next transaction and issue the
// cmd_en again when data_rdy is high. Otherwise we will go to the done
// state.
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_0_axi_mc_cmd_fsm #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// MC burst length. = 1 for BL4 or BC4, = 2 for BL8
parameter integer C_MC_BURST_LEN = 1,
// parameter to identify rd or wr instantation
// = 1 rd , = 0 wr
parameter integer C_MC_RD_INST = 0
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output reg axready ,
input wire axvalid ,
output wire cmd_en ,
input wire cmd_full ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
input wire data_rdy ,
// status signal for w_channel when command is written.
output wire cmd_en_last
);
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
assign cmd_en = (axvalid & data_rdy);
assign next = (~cmd_full & cmd_en);
assign cmd_en_last = next & ~next_pending;
always @(posedge clk) begin
if (reset)
axready <= 1'b0;
else
axready <= ~axvalid | cmd_en_last;
end
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVGND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__TAPVGND2_FUNCTIONAL_PP_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__tapvgnd2 (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVGND2_FUNCTIONAL_PP_V |
/*
* Front-end instruction pre-fetch unit with wishbone master interface
* Copyright (C) 2013 Charley Picker <>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_front_prefetch_wb (
// Wishbone master signals
input clk_i,
input rst_i,
input [15:0] wb_dat_i,
output [19:1] wb_adr_o,
output [ 1:0] wb_sel_o,
//output reg wb_cyc_o,
output wb_cyc_o,
//output reg wb_stb_o,
output wb_stb_o,
input wb_ack_i,
// Invalidate current fetch cycle
input flush,
// Address stearing from back-end
input load_cs_ip,
input [15:0] requested_cs,
input [15:0] requested_ip,
// Output to instruction fifo stage
output reg [15:0] fifo_cs_o,
//output [15:0] fifo_cs_o,
output reg [15:0] fifo_ip_o,
//output [15:0] fifo_ip_o,
output reg [15:0] fetch_dat_o,
//output [15:0] fetch_dat_o,
output reg wr_fetch_fifo,
//output wr_fetch_fifo,
input fifo_full
);
// Registers and nets
wire abort_fetch;
wire stalled;
wire wb_cyc_complete;
reg valid_cyc;
reg wb_cyc;
reg [15:0] cs;
reg [15:0] ip;
// Continuous assignments
// The system reset, flush, load_cs_ip will cause fetch operations to be aborted
assign abort_fetch = rst_i || flush || load_cs_ip;
// The fifo_full signal will cause the fetch to be stalled
// Any other time, it should be ok to start another fetch cycle
assign stalled = fifo_full;
// Calculate address for wb_adr_o
assign wb_adr_o = (cs << 4) + ip;
// We are always fetching two bytes at a time
assign wb_sel_o = 2'b11;
// Wishbone cycle
assign wb_cyc_o = (!abort_fetch & !stalled) || wb_cyc;
// Wishbone strobe
assign wb_stb_o = (!abort_fetch & !stalled) || wb_cyc;
// This signals that a wishbone cycle has completed
assign wb_cyc_complete = wb_cyc_o & wb_stb_o & wb_ack_i;
// Pass wishbone data to fifo
//assign fetch_dat_o = wb_dat_i;
//assign fifo_cs_o = cs;
//assign fifo_ip_o = ip;
// Write fifo
//assign wr_fetch_fifo = valid_cyc;
// behaviour
// Is this an active wishbone cycle?
// Master devices MUST complete the wishbone cycle even if the request
// has been invalidated!!
always @(posedge clk_i)
if (rst_i) wb_cyc <= 1'b0;
else wb_cyc <= !abort_fetch & !stalled ? 1'b1
: wb_cyc_complete ? 1'b0
: wb_cyc;
// Does the wishbone cycle need to be invalidated?
// Master devices MUST complete the wishbone cycle even if the request
// has been invalidated!!
always @(posedge clk_i)
if (rst_i) valid_cyc <= 1'b0;
else valid_cyc <= abort_fetch ? 1'b0
: wb_cyc_complete ? 1'b1
: valid_cyc;
// cs and ip logic
always @(posedge clk_i)
if (rst_i) begin
cs <= 16'hf000;
ip <= 16'hfff0;
end
else begin
if (flush) begin
cs <= requested_cs;
ip <= requested_ip;
end
else if (load_cs_ip) begin
cs <= requested_cs;
ip <= requested_ip;
end
else if (!stalled & wb_cyc & valid_cyc & wb_cyc_complete)
ip <= ip + 1;
end
// wb_cyc_o
// When a stall condition is encountered at or during wb cycle,
// follow through until wishbone cycle completes. This essentially forces one
// complete wb cycle before the abort fetch or stall condition is acknowledge.
//always @(posedge clk_i)
// if (rst_i) wb_stb_o <= 1'b0;
// else wb_cyc_o <= (!abort_fetch & !stalled) ? 1'b1 : (wb_cyc_complete ? 1'b0 : wb_cyc_o);
// wb_stb_o
// When a stall condition is encountered at or during wb strobe,
// follow through until wishbone cycle completes. This essentially forces one
// complete wb cycle before the stall condition is acknowledge.
//always @(posedge clk_i)
// if (rst_i) wb_stb_o <= 1'b0;
// else wb_stb_o <= (!abort_fetch & !stalled) ? 1'b1 : (wb_cyc_complete ? 1'b0 : wb_stb_o);
// Pass wishbone data to fifo
// We MUST hold the data if the fifo becomes full
always @(posedge clk_i)
if (rst_i) begin
fetch_dat_o <= 16'b0;
fifo_cs_o <= 16'b0;
fifo_ip_o <= 16'b0;
end
else if (wb_cyc & valid_cyc & wb_cyc_complete) begin
fetch_dat_o <= wb_dat_i;
fifo_cs_o <= cs;
fifo_ip_o <= ip;
end
// write fifo
always @(posedge clk_i)
if (rst_i) wr_fetch_fifo <= 1'b0;
else wr_fetch_fifo <= !abort_fetch & !stalled & wb_cyc & valid_cyc & wb_cyc_complete;
endmodule |
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_crc.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// - Novan Hartadi () ////
//// - Mahmud Galela () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
`include "timescale.v"
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
input Clk;
input Reset;
input [3:0] Data;
input Enable;
input Initialize;
output [31:0] Crc;
output CrcError;
reg [31:0] Crc;
wire [31:0] CrcNext;
assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
assign CrcNext[20] = Crc[16];
assign CrcNext[21] = Crc[17];
assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
assign CrcNext[30] = Crc[26];
assign CrcNext[31] = Crc[27];
always @ (posedge Clk or posedge Reset)
begin
if (Reset)
Crc <= 32'hffffffff;
else
if(Initialize)
Crc <= 32'hffffffff;
else
Crc <= CrcNext;
end
assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; long long val[100000], dp[100000][2]; vector<int> g[100000]; void dfs(int v, int p) { long long c1 = 0, c2 = 0; for (int i = 0; i < (g[v].size()); i++) { int next = g[v][i]; if (next != p) { dfs(next, v); c1 = max(c1, dp[next][0]); c2 = max(c2, dp[next][1]); } } long long d = c1 - c2; if (val[v] + d > 0) c2 += val[v] + d; else c1 += -(val[v] + d); dp[v][0] = c1, dp[v][1] = c2; } int main() { std::ios::sync_with_stdio(false); cin >> n; for (int i = 0; i < n - 1; i++) { int a, b; cin >> a >> b; g[a - 1].push_back(b - 1); g[b - 1].push_back(a - 1); } for (int i = 0; i < n; i++) cin >> val[i]; dfs(0, -1); cout << dp[0][0] + dp[0][1]; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A21OI_PP_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21OI_PP_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 Wishbone Master model ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////
//// ////
///////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
///////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_master_model.v,v 1.1 2004-02-28 16:01:47 rherveille Exp $
//
// $Date: 2004-02-28 16:01:47 $
// $Revision: 1.1 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
//
`include "timescale.v"
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
parameter dwidth = 32;
parameter awidth = 32;
input clk, rst;
output [awidth:1] adr;
input [dwidth:1] din;
output [dwidth:1] dout;
output cyc, stb;
output we;
output [dwidth/8:1] sel;
input ack, err, rty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [awidth:1] adr;
reg [dwidth:1] dout;
reg cyc, stb;
reg we;
reg [dwidth/8:1] sel;
reg [dwidth:1] q;
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
initial
begin
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
cyc = 1'b0;
stb = 1'bx;
we = 1'hx;
sel = {dwidth/8{1'bx}};
#1;
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
end
////////////////////////////////////////////////////////////////////
//
// Wishbone write cycle
//
task wb_write;
input delay;
integer delay;
input [awidth:1] a;
input [dwidth:1] d;
begin
// wait initial delay
repeat(delay) @(posedge clk);
// assert wishbone signal
#1;
adr = a;
dout = d;
cyc = 1'b1;
stb = 1'b1;
we = 1'b1;
sel = {dwidth/8{1'b1}};
@(posedge clk);
// wait for acknowledge from slave
while(~ack) @(posedge clk);
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
end
endtask
////////////////////////////////////////////////////////////////////
//
// Wishbone read cycle
//
task wb_read;
input delay;
integer delay;
input [awidth:1] a;
output [dwidth:1] d;
begin
// wait initial delay
repeat(delay) @(posedge clk);
// assert wishbone signals
#1;
adr = a;
dout = {dwidth{1'bx}};
cyc = 1'b1;
stb = 1'b1;
we = 1'b0;
sel = {dwidth/8{1'b1}};
@(posedge clk);
// wait for acknowledge from slave
while(~ack) @(posedge clk);
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
d = din;
end
endtask
////////////////////////////////////////////////////////////////////
//
// Wishbone compare cycle (read data from location and compare with expected data)
//
task wb_cmp;
input delay;
integer delay;
input [awidth:1] a;
input [dwidth:1] d_exp;
begin
wb_read (delay, a, q);
if (d_exp !== q)
$display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
end
endtask
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF.v,v 1.9 2007/05/23 21:43:39 patrickp Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Bi-Directional Buffer
// /___/ /\ Filename : IOBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/22/06 - CR#226003 - Added integer, real parameter type
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 05/23/07 - Added wire declaration for internal signals.
`timescale 1 ps / 1 ps
module IOBUF (O, IO, I, T);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IBUF_DELAY_VALUE = "0";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
parameter SLEW = "SLOW";
output O;
inout IO;
input I, T;
wire ts;
//tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 T1 (IO, I, ts);
buf B1 (O, IO);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IOBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
$finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE);
$finish;
end
endcase
end // initial begin
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 200100; int n, l, r, m, a[N], b[N], c, pos, mi, ma; pair<int, int> t[4 * N]; void build(int v, int tl, int tr) { if (tl == tr) { t[v].first = a[tl]; t[v].second = b[tl]; return; } int tm = (tl + tr) / 2; build(2 * v, tl, tm); build(2 * v + 1, tm + 1, tr); t[v].first = max(t[2 * v].first, t[2 * v + 1].first); t[v].second = min(t[2 * v].second, t[2 * v + 1].second); return; } void get(int v, int tl, int tr, int l, int r) { if (l > r) return; if (tl == l && tr == r) { ma = max(ma, t[v].first); mi = min(mi, t[v].second); return; } int tm = (tl + tr) / 2; get(2 * v, tl, tm, l, min(r, tm)); get(2 * v + 1, tm + 1, tr, max(l, tm + 1), r); return; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; a[n + 1] = 1e9 - 2; for (int i = 1; i <= n; i++) cin >> b[i]; b[n + 1] = -1e9 - 2; build(1, 1, n); long long ans = 0; for (int i = 1; i <= n; i++) if (a[i] - b[i] < 1) { l = i; r = n + 1; while (l < r) { c = (l + r) / 2; mi = 1e9 + 2; ma = -1e9 - 2; get(1, 1, n, i, c); if (mi > ma) l = c + 1; else r = c; } pos = l; l = i; r = n + 1; while (l < r) { c = (l + r) / 2; mi = 1e9 + 2; ma = -1e9 - 2; get(1, 1, n, i, c); if (mi >= ma) l = c + 1; else r = c; } ans += max(l - pos, 0); } cout << ans << n ; return 0; } |
`timescale 1ns / 1ps
`define SIM_FULL
module async_fifo_t;
// ins
reg wclk;
reg wrst;
reg [7:0] data_i;
reg ack_i;
reg rclk;
reg rrst;
reg pop_i;
async_fifo uut(
.wclk(wclk), .wrst(wrst), .data_i(data_i), .ack_i(ack_i),
.rclk(rclk), .rrst(rrst), .pop_i(pop_i));
parameter T_WCLK = 10;
parameter T_RCLK = 24;
always #(T_WCLK/2) wclk = ~wclk;
always #(T_RCLK/2) rclk = ~rclk;
initial begin
$dumpfile("async_fifo_t.lxt");
$dumpvars(0, async_fifo_t);
#(3000);
$finish(2);
end
initial begin
wclk = 0;
wrst = 0;
ack_i = 0;
data_i = 8'h20;
#(T_WCLK);
wrst = 1;
#(T_WCLK);
wrst = 0;
end
always begin
#(T_WCLK*15);
data_i = data_i + 1;
ack_i = 1;
#(T_WCLK);
ack_i = 0;
end
initial begin
rclk = 0;
rrst = 0;
pop_i = 0;
#(T_RCLK);
rrst = 1;
#(T_RCLK);
rrst = 0;
end
`ifndef SIM_FULL
always @(posedge rclk) begin
pop_i <= 0;
if (!uut.empty_o) begin
$display("read %h", uut.data_o);
pop_i <= 1;
end
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; inline int ckmax(int &a, int b) { return a < b ? a = b, 1 : 0; } inline int ckmin(int &a, int b) { return a > b ? a = b, 1 : 0; } char s[500100], t[500100]; int n, m, wt, p[500100], sta[500100], pre[500100], nex[500100], top; int main() { scanf( %d%d%d , &n, &m, &wt); scanf( %s , s + 1); scanf( %s , t + 1); for (int i = 1; i <= n; ++i) { if (s[i] == ( ) sta[++top] = i; else { p[i] = sta[top]; p[sta[top--]] = i; } pre[i] = i - 1; nex[i] = i + 1; } nex[0] = 1; pre[n + 1] = n; for (int i = 1; i <= m; ++i) { if (t[i] == L ) wt = pre[wt]; else if (t[i] == R ) wt = nex[wt]; else { int ww = p[wt]; if (ww > wt) swap(ww, wt); nex[pre[ww]] = nex[wt]; pre[nex[wt]] = pre[ww]; if (nex[wt] <= n) wt = nex[wt]; else wt = pre[ww]; } } int w = nex[0]; while (w <= n) { printf( %c , s[w]); w = nex[w]; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int modulo = 1000000007; const int limite = 1000001; long long int elev[limite]; int ocupado[limite]; int main() { ios_base::sync_with_stdio(false); int n, m, k; cin >> n >> m >> k; elev[0] = 1; for (int i = 1; i < limite; i++) elev[i] = (elev[i - 1] * 2) % modulo; int ini = 0; int fin = n + 1; int inf = k + 2; int sup = n; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v; if (v == u + 1) ; else if (v == u + k + 1) { ocupado[v] = 1; ini = max(ini, u); fin = min(fin, v); inf = max(inf, u + 1); sup = min(sup, v + k); } else { cout << 0 << endl; exit(0); } } if (fin <= ini) { cout << 0 << endl; exit(0); } int libres = 0; long long int maneras = 1; for (int i = inf; i <= sup; i++) { if (not ocupado[i]) { maneras = (maneras + elev[libres]) % modulo; libres++; } if (i - k >= inf and not ocupado[i - k]) libres--; } cout << maneras << endl; } |
// It looks like for the models to be correctly annotated with timings from
// SDF in Icarus Verilog the timescale provided here must match the one in SDF.
// VPR writes SDFs in picoseconds hence here it is set to picoseconds as well.
`timescale 1ps/1ps
// VPR routing interconnect module
module fpga_interconnect(datain, dataout);
input datain;
output dataout;
// Behavioral model
assign dataout = datain;
// Timing paths. The values are dummy and are intended to be replaced by
// ones from a SDF file during simulation.
specify
(datain => dataout) = 0;
endspecify
endmodule
module frac_lut4_arith (\in[3] ,\in[2] ,\in[1] ,\in[0] ,cin, lut4_out, cout);
parameter [15:0] LUT = 16'd0;
parameter [0: 0] MODE = 0;
input [0:0] \in[3] ;
input [0:0] \in[2] ;
input [0:0] \in[1] ;
input [0:0] \in[0] ;
input [0:0] cin;
output [0:0] lut4_out;
output [0:0] cout;
// Mode bits of frac_lut4_arith are responsible for the LI2 mux which
// selects between the LI2 and CIN inputs.
wire [3:0] li = (MODE == 1'b1) ?
{\in[3] ,cin, \in[1] ,\in[0] } :
{\in[3] ,\in[2] ,\in[1] ,\in[0] };
// Output function
wire [7:0] s1 = li[0] ?
{LUT[14], LUT[12], LUT[10], LUT[8], LUT[6], LUT[4], LUT[2], LUT[0]} :
{LUT[15], LUT[13], LUT[11], LUT[9], LUT[7], LUT[5], LUT[3], LUT[1]};
wire [3:0] s2 = li[1] ?
{s1[6], s1[4], s1[2], s1[0]} :
{s1[7], s1[5], s1[3], s1[1]};
wire [1:0] s3 = li[2] ?
{s2[2], s2[0]} :
{s2[3], s2[1]};
assign lut4_out = li[3] ? s3[0] : s3[1];
// Carry out function
assign cout = s2[2] ? cin : s2[3];
// Timing paths. The values are dummy and are intended to be replaced by
// ones from a SDF file during simulation.
specify
(\in[0] => lut4_out) = 0;
(\in[1] => lut4_out) = 0;
(\in[2] => lut4_out) = 0;
(\in[3] => lut4_out) = 0;
(cin => lut4_out) = 0;
(\in[0] => cout) = 0;
(\in[1] => cout) = 0;
(\in[2] => cout) = 0;
(\in[3] => cout) = 0;
(cin => cout) = 0;
endspecify
endmodule
module scff (D, DI, clk, reset, Q); // QL_IOFF
parameter [0:0] MODE = 1; // The default
input [0:0] D;
input [0:0] DI;
input [0:0] clk;
input [0:0] reset;
output [0:0] Q;
scff_1 #(.MODE(MODE)) scff_1 (
.D (D),
.DI (DI),
.clk (clk),
.preset (1'b1),
.reset (reset),
.Q (Q)
);
endmodule
module scff_1 (D, DI, clk, preset, reset, Q); // QL_FF
parameter [0:0] MODE = 1; // The default
input [0:0] D;
input [0:0] DI;
input [0:0] clk;
input [0:0] preset;
input [0:0] reset;
output reg [0:0] Q;
initial Q <= 1'b0;
// Clock inverter
wire ck = (MODE == 1'b1) ? clk : !clk;
// FLip-flop behavioral model
always @(posedge ck or negedge reset or negedge preset) begin
if (!reset) Q <= 1'b0;
else if (!preset) Q <= 1'b1;
else Q <= D;
end
// Timing paths. The values are dummy and are intended to be replaced by
// ones from a SDF file during simulation.
specify
(posedge clk => (Q +: D)) = 0;
$setuphold(posedge clk, D, 0, 0);
$recrem(posedge reset, posedge clk, 0, 0);
$recrem(posedge preset, posedge clk, 0, 0);
endspecify
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t;
integer v = 19;
initial begin
if (v==1) begin end
else if (v==2) begin end
else if (v==3) begin end
else if (v==4) begin end
else if (v==5) begin end
else if (v==6) begin end
else if (v==7) begin end
else if (v==8) begin end
else if (v==9) begin end
else if (v==10) begin end
else if (v==11) begin end // Warn about this one
else if (v==12) begin end
end
initial begin
unique0 if (v==1) begin end
else if (v==2) begin end
else if (v==3) begin end
else if (v==4) begin end
else if (v==5) begin end
else if (v==6) begin end
else if (v==7) begin end
else if (v==8) begin end
else if (v==9) begin end
else if (v==10) begin end
else if (v==11) begin end // Warn about this one
else if (v==12) begin end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 300010; int dia, n; long long a[N], ans; map<long long, int> mp; int main() { cin >> dia >> n; ans = (long long)n * (n - 1LL) * (n - 2LL) / 6LL; for (int i = 1, s, f; i <= n; ++i) { cin >> s >> f; if (!s) f += dia; f %= 2 * dia; a[i] = f; } sort(a + 1, a + n + 1); for (int i = n + 1; i <= 2 * n; ++i) { a[i] = a[i - n] + 2 * dia; mp[a[i]]++; mp[a[i - n]]++; } for (int i = 1, ni = 1; i <= n; ++i) { for (; a[ni + 1] - a[i] < dia; ++ni) ; ans -= (long long)(ni - i) * (ni - i - 1LL) / 2LL; } if (ans) { cout << ans << n ; return 0; } long long l = 0; for (int i = 1, ni; i <= n; ++i) { for (; a[ni + 1] - a[i] < dia; ++ni) ; if (ni - i > 1) l = max(l, a[ni] - a[i]); } for (int i = 1, ni = 1; i <= n; ++i) { ni = max(ni, i); mp[a[i]]--; for (; a[ni + 1] - a[i] < l; ++ni) ; if (a[ni + 1] - a[i] == l) { if (ni + 1 - i > 1) ans += (long long)(ni - i) * mp[a[ni + 1]]; ans += (long long)mp[a[ni + 1]] * (mp[a[ni + 1]] - 1) / 2LL; } } cout << ans << n ; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 2e6 + 7; int n; long long dp[2][maxn]; int main() { cin >> n; int now = 1; dp[0][1] = 1; dp[0][2] = 1; long long ans = 0; ans += dp[0][n]; for (int i = 1; i <= 19; i++) { memset(dp[now], 0, sizeof(dp[now])); for (int j = (1 << (i)) - 1; j < (1 << (i + 1)) - 1; j++) { if (dp[now ^ 1][j] == 0) continue; for (int l = (1 << (i)) - 1; l < (1 << (i + 1)) - 1; l++) { if (j + l + 1 < maxn && l % 2 == 0) dp[now][j + l + 1] += dp[now ^ 1][j] * dp[now ^ 1][l]; } } ans += dp[now][n]; now ^= 1; } cout << ans << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_TB_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_TB_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlygate4sd1.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__dlygate4sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_TB_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08/01/2016 04:10:04 PM
// Design Name:
// Module Name: Convert_Fixed_To_Float_V
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Convert_Fixed_To_Float_V(
input wire CLK, //CLOCK
input wire [31:0] FIXED, // VALOR DEL NUMERO EN PUNTO FIJO
input wire EN_REG1, // ENABLE PARA EL REGISTRO 1 QUE GUARDA EL NUMERO EN PUNTO FIJO
input wire EN_REGmult, // ENABLE PARA EL REGISTRO MULT QUE GUARDA EL VALOR A TRUNCAR
input wire LOAD, // SELECCION CARGA REGISTRO DE DESPLAZAMIENTOS
input wire MS_1, // SELECCIONA EL MUX PARA UN VALOR DIFERENTE O IGUAL A 26 SEGUN SEA EL CASO
input wire RST,
input wire EN_REG2,
output wire Bandcomp, // INDICA SI EL EXPONENTE ES MAYOR QUE 26
output wire [31:0] FLOATOUT, // CONTIENE EL RESULTADO EN COMA FIJA
output wire [7:0] Encd // CONTIENE EL VALOR DEL PRIMER 1 SECUENCIA BINARIA
);
parameter P = 32;
parameter W = 8;
wire [31:0] fixed;
wire [31:0] complemento;
wire [31:0] MUXSIGN;
wire [31:0] P_RESULT;
wire [31:0] DESNORM;
wire [7:0] Encoder;
wire [31:0] mult;
FF_D #(.P(P)) REG_FIXED_I (
.CLK(CLK),
.RST(RST),
.EN(EN_REG1),
.D(FIXED),
.Q(fixed)
);
Complement COMPLEMENTO2 (
.a_i(fixed),
.twos_comp(complemento)
);
Mux_2x1_32Bits MUX2x1_0_I (
.MS(fixed[31]),
.D_0(fixed),
.D_1(complemento),
.D_out(MUXSIGN)
);
/*DESNORMALIZADOR_V DESNORMA_V(
.CLK(CLK),
.A(MUXSIGN), //entrada al desnormalizador
.Y(DESNORM) //salida de la desnormalizacion en coma fija, coma en el bit 56
); */
FF_D #(.P(P)) REG_FLOAT_mult (
.CLK(CLK),
.RST(RST),
.EN(EN_REGmult),
.D(MUXSIGN),
.Q(mult)
);
Priority_Encoder OUTONE (
.d_in(mult), //Valor truncado de la desnormalizaci�n [61:30]
.d_out(Encoder) //Posicion del primer 1 en la secuencia binaria
);
wire [31:0] FLOAT;
wire [7:0] FLOATEXPONENT;
wire [7:0] MUX1;
wire [7:0] SUBT_1;
wire [7:0] SUBT_2;
wire [7:0] MUXSal8bits;
assign Encd = Encoder[7:0];
Comparador_Mayor VALOR26_I(
.CLK(CLK),
.A(Encoder),
.B(8'b00011010),//00011010 -- >26
.Out(Bandcomp)
);
Barrel_Shifter #(.SWR(32),.EWR(8)) S_REG_I(
.clk(CLK),
.rst(RST),
.load_i(LOAD),
.Shift_Value_i(MUXSal8bits),
.Shift_Data_i(mult),
.Left_Right_i(~Bandcomp),
.Bit_Shift_i(1'b0),
.N_mant_o(P_RESULT)
);
S_SUBT #(.P(W),.W(W)) SUBT_EXP_1_I (
.A(Encoder),
.B(8'b00011010),
.Y(SUBT_1)
);
S_SUBT #(.P(W),.W(W)) SUBT_EXP_2_I (
.A(8'b00011010),
.B(Encoder),
.Y(SUBT_2)
);
Mux_2x1_8Bits MUX2x1_1_I (
.MS(Bandcomp),
.D_0(SUBT_2),
.D_1(SUBT_1),
.D_out(MUX1)
);
Mux_2x1_8Bits MUX2x1_2_I (
.MS(MS_1),
.D_0(8'b00000000),
.D_1(MUX1),
.D_out(MUXSal8bits)
);
ADDT_8Bits #(.P(W),.W(W)) ADDT_EXPONENTE_I (
.A(Encd),
.B(8'b01100101),
.Y(FLOATEXPONENT)
);
assign FLOAT [31] = fixed [31];
assign FLOAT [30:23] = FLOATEXPONENT [7:0];
assign FLOAT [22:0] = P_RESULT[25:3];
FF_D #(.P(P)) REG_FLOAT (
.CLK(CLK),
.RST(RST),
.EN(EN_REG2),
.D(FLOAT),
.Q(FLOATOUT)
);
endmodule
|
module env_io (/*AUTOARG*/
// Outputs
DI,
// Inputs
clk, iorq_n, rd_n, wr_n, addr, DO
);
input clk;
input iorq_n;
input rd_n;
input wr_n;
input [7:0] addr;
input [7:0] DO;
inout [7:0] DI;
reg [7:0] io_data;
reg [7:0] str_buf [0:255];
reg io_cs;
integer buf_ptr, i;
reg [7:0] timeout_ctl;
reg [15:0] cur_timeout;
reg [15:0] max_timeout;
reg [7:0] int_countdown;
reg [7:0] checksum;
reg [7:0] ior_value; // increment-on-read value
assign DI = (!iorq_n & !rd_n & io_cs) ? io_data : {8{1'bz}};
initial
begin
io_cs = 0;
buf_ptr = 0;
cur_timeout = 0;
max_timeout = 10000;
timeout_ctl = 1;
int_countdown = 0;
end
always @*
begin
if (!iorq_n & !rd_n)
begin
io_cs = (addr[7:5] == 3'b100);
case (addr)
8'h82 : io_data = timeout_ctl;
8'h83 : io_data = max_timeout[7:0];
8'h84 : io_data = max_timeout[15:8];
8'h90 : io_data = int_countdown;
8'h91 : io_data = checksum;
8'h93 : io_data = ior_value;
8'h94 : io_data = {$random};
default : io_data = 8'hzz;
endcase // case(addr)
end // if (!iorq_n & !rd_n)
end // always @ *
wire wr_stb;
reg last_iowrite;
assign wr_stb = (!iorq_n & !wr_n);
always @(posedge clk)
begin
last_iowrite <= #1 wr_stb;
if (!wr_stb & last_iowrite)
case (addr)
8'h80 :
begin
case (DO)
1 : tb_top.test_pass;
2 : tb_top.test_fail;
3 : tb_top.dumpon;
4 : tb_top.dumpoff;
default :
begin
$display ("%t: ERROR : Unknown I/O command %x", $time, DO);
end
endcase // case(DO)
end // case: :...
8'h81 :
begin
str_buf[buf_ptr] = DO;
buf_ptr = buf_ptr + 1;
//$display ("%t: DEBUG : Detected write of character %x", $time, DO);
if (DO == 8'h0A)
begin
$write ("%t: PROGRAM : ", $time);
for (i=0; i<buf_ptr; i=i+1)
$write ("%s", str_buf[i]);
buf_ptr = 0;
end
end // case: 8'h81
8'h82 :
begin
timeout_ctl = DO;
end
8'h83 : max_timeout[7:0] = DO;
8'h84 : max_timeout[15:8] = DO;
8'h90 : int_countdown = DO;
8'h91 : checksum = DO;
8'h92 : checksum = checksum + DO;
8'h93 : ior_value = DO;
endcase // case(addr)
end // always @ (posedge clk)
always @(posedge clk)
begin
if (timeout_ctl[1])
cur_timeout = 0;
else if (timeout_ctl[0])
cur_timeout = cur_timeout + 1;
if (cur_timeout >= max_timeout)
begin
$display ("%t: ERROR : Reached timeout %d cycles", $time, max_timeout);
tb_top.test_fail;
end
end // always @ (posedge clk)
always @(posedge clk)
begin
if (int_countdown == 1)
begin
tb_top.int_n <= #1 1'b0;
int_countdown = 0;
end
else if (int_countdown > 1)
begin
int_countdown = int_countdown - 1;
tb_top.int_n <= #1 1'b1;
end
end
endmodule // env_io
|
#include <bits/stdc++.h> using namespace std; const int N1[] = {1, -1}, NINF = (int)0x80808080u, MAXN = 30000, MAXK = 200; long long int dp[MAXN][MAXK + 1][2][2], mdp[MAXN][MAXK + 1][2]; int arr[MAXN], cs[MAXN], n, k; inline long long int max(long long int a, long long int b) { return a > b ? a : b; } int main() { scanf( %d%d , &n, &k); for (int i = 0; i < n; i++) { scanf( %d , &arr[i]); cs[i] = (i ? cs[i - 1] : 0) + arr[i]; } memset(dp, NINF, sizeof dp); memset(mdp, NINF, sizeof mdp); mdp[0][0][0] = mdp[0][0][1] = 0; for (int p = 0; p < 2; p++) for (int q = 0; q < 2; q++) { dp[0][1][p][q] = N1[q] * arr[0]; mdp[0][1][q] = max(mdp[0][1][q], dp[0][1][p][q]); } for (int i = 1; i < n; i++) { mdp[i][0][0] = mdp[i][0][1] = 0; mdp[i][1][0] = mdp[i - 1][1][0]; mdp[i][1][1] = mdp[i - 1][1][1]; for (int p = 0; p < 2; p++) for (int q = 0; q < 2; q++) { dp[i][1][p][q] = max(dp[i - 1][1][p][q], mdp[i - 1][0][p]) + N1[q] * arr[i]; mdp[i][1][q] = max(mdp[i][1][q], dp[i][1][p][q]); } for (int j = 2; j <= k - 1; j++) { mdp[i][j][0] = mdp[i - 1][j][0]; mdp[i][j][1] = mdp[i - 1][j][1]; for (int p = 0; p < 2; p++) for (int q = 0; q < 2; q++) { dp[i][j][p][q] = max(dp[i - 1][j][p][q], mdp[i - 1][j - 1][p]) + (N1[q] - N1[p]) * arr[i]; mdp[i][j][q] = max(mdp[i][j][q], dp[i][j][p][q]); } } mdp[i][k][0] = mdp[i - 1][k][0]; for (int p = 0; p < 2; p++) { dp[i][k][p][0] = max(dp[i - 1][k][p][0], mdp[i - 1][k - 1][p]) - N1[p] * arr[i]; mdp[i][k][0] = max(mdp[i][k][0], dp[i][k][p][0]); } } printf( %I64d n , mdp[n - 1][k][0]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; int calc(long long a, long long n) { long long res = 1; while (n > 0) { if (n & 1) res = (res * a) % MOD; a = (a * a) % MOD; n /= 2; } return res; } int main() { ios_base::sync_with_stdio(0); long long n; cin >> n; long long x = calc(2, n); cout << x * (x + 1) / 2 % MOD; return 0; } |
#include <bits/stdc++.h> using namespace std; const int B = 27397, MOD = 1e9 + 7; const int B1 = 33941, MOD1 = 1e9 + 9; int t; inline void solve() { int r, n; scanf( %d%d , &n, &r); --r; int sum = 0; for (int i = 0; i < n - 1; ++i) { int x; scanf( %d , &x); --x; sum += x; } for (int i = 0; i < n; ++i) if ((sum + i) % n == r) printf( %d n , i + 1); } int main(void) { scanf( %d , &t); while (t-- > 0) solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long niz[1000000]; long long kum[1000000]; int main() { ios_base::sync_with_stdio(false); cout.precision(10); cout << fixed; int n, s, f; cin >> n; for (int i = 1; i <= n; i++) { cin >> niz[i]; } cin >> s >> f; long long s1, f1; for (int i = 1; i <= n; i++) { s1 = s - i + 1; if (s1 <= 0) s1 += n; f1 = f - i + 1; ; if (f1 <= 0) f1 += n; if (s1 > f1) { kum[1] += niz[i]; kum[f1] -= niz[i]; kum[s1] += niz[i]; } else { kum[s1] += niz[i]; kum[f1] -= niz[i]; } } kum[0] = 0; long long maxi = 0; for (int i = 1; i <= n; i++) { kum[i] = kum[i] + kum[i - 1]; maxi = max(maxi, kum[i]); } for (int i = 1; i <= n; i++) { if (kum[i] == maxi) { cout << i; return 0; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int tag[10]; int main() { string a, b; while (cin >> a >> b) { memset(tag, 0, sizeof(tag)); ; int len = a.size(); int len1 = b.size(); for (int i = 0; i < len1; i++) { int num = b[i] - 0 ; tag[num]++; } for (int i = 0; i < len; i++) { int p = a[i] - 0 ; int j = 9; while (j > p) { if (!tag[j]) j--; if (tag[j] && j > p) { a[i] = j + 0 ; tag[j]--; break; } } } for (int i = 0; i < len; i++) cout << a[i]; cout << endl; } return 0; } |
#include <bits/stdc++.h> int main() { int t; scanf( %d , &t); while (t--) { int n; scanf( %d , &n); int a[n]; for (int i = 0; i < n; i++) { scanf( %d , &a[i]); } for (int i = 0; i < n; i++) { for (int j = 0; j < n - i - 1; j++) { if (a[j + 1] < a[j]) { int t = a[j]; a[j] = a[j + 1]; a[j + 1] = t; } } } int ans = INT_MAX; for (int i = 0; i < n - 1; i++) { if (a[i + 1] - a[i] < ans) { ans = a[i + 1] - a[i]; if (ans == 0) break; } } printf( %d n , ans); } return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// Phy_sim.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao () ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: Phy_sim.v,v $
// Revision 1.3 2006/11/17 17:53:07 maverickist
// no message
//
// Revision 1.2 2006/01/19 14:07:50 maverickist
// verification is complete.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
`timescale 1ns/100ps
module phy_sim(
input Gtx_clk, // Used only in GMII mode
output Rx_clk,
output Tx_clk, // Used only in MII mode
input Tx_er,
input Tx_en,
input [7:0] Txd,
output Rx_er,
output Rx_dv,
output [7:0] Rxd,
output Crs,
output Col,
input [2:0] Speed,
input Done
);
//////////////////////////////////////////////////////////////////////
// this file used to simulate Phy.
// generate clk and loop the Tx data to Rx data
// full duplex mode can be verified on loop mode.
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
// internal signals
//////////////////////////////////////////////////////////////////////
reg Clk_25m; // Used for 100 Mbps mode
reg Clk_2_5m; // Used for 10 Mbps mode
//wire Rx_clk;
//wire Tx_clk; // Used only in MII mode
initial
begin
#10;
while ( !Done )
begin
#20 Clk_25m = 0;
#20 Clk_25m = 1;
end
end
initial
begin
#10;
while ( !Done )
begin
#200 Clk_2_5m = 0;
#200 Clk_2_5m = 1;
end
end
assign Rx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0;
assign Tx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0;
assign Rx_dv = Tx_en;
assign Rxd = Txd;
assign Rx_er = Tx_er;
assign Crs = Tx_en;
assign Col = 0;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1010; int n, w, a[N]; int main() { cin >> n >> w; for (int i = 0; i < n; i++) { cin >> a[i]; } int lo = 0, hi = w, n_lo = 0, n_hi = w; for (int i = 0; i < n; i++) { n_lo += a[i]; n_hi += a[i]; if (n_lo > w || n_hi < 0) return cout << 0 << n , 0; if (n_lo < 0) { lo += -n_lo; n_lo = 0; } if (n_hi > w) { hi -= n_hi - w; n_hi = w; } } cout << (hi - lo + 1) << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4BB_2_V
`define SKY130_FD_SC_HD__NOR4BB_2_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog wrapper for nor4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4bb_2 (
Y ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4bb_2 (
Y ,
A ,
B ,
C_N,
D_N
);
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4bb base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4BB_2_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1000000007; long long pwr(long long a, long long b, long long mod) { if (b == 0) return 1; long long temp = pwr(a, b / 2, mod); temp = (temp * temp) % mod; if (b & 1) temp = (temp * a) % mod; return temp; } long long pwr(long long a, long long b) { if (b == 0) return 1; long long temp = pwr(a, b / 2); temp = (temp * temp); if (b & 1) temp = (temp * a); return temp; } long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return (a / gcd(a, b)) * b; } long long modularInverse(long long a, long long m) { return pwr(a, m - 2, m); } bool *isPrime; void generatePrimeSieve(const int lim) { isPrime = (bool *)malloc(lim + 1); memset(isPrime, true, lim + 1); isPrime[0] = false; isPrime[1] = false; for (int i = 2; i <= lim; ++i) if (isPrime[i]) for (int j = i + i; j <= lim; j += i) isPrime[j] = false; } vector<vector<int> > identityMatrix; vector<vector<int> > mul(const vector<vector<int> > &a, const vector<vector<int> > &b) { int n = a.size(); vector<vector<int> > ans(n, vector<int>(n)); for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { for (int k = 0; k < n; ++k) { ans[i][j] += ((long long)a[i][k] * b[k][j]) % mod; ans[i][j] %= mod; } } } return ans; } vector<vector<int> > pwr(const vector<vector<int> > &a, long long n) { if (n == 0) { assert(false); return identityMatrix; } if (n == 1) return a; vector<vector<int> > tmp = pwr(a, n / 2); tmp = mul(tmp, tmp); if (n & 1) tmp = mul(a, tmp); return tmp; } string str[435]; bool isRemoved[3123]; int main() { std::ios::sync_with_stdio(false); int n, m; cin >> n >> m; for (int i = 0; i < n; ++i) cin >> str[i]; int ans = 0; while (true) { bool encountered = false; for (int i = 0; i < n - 1; ++i) { if (str[i] > str[i + 1]) { encountered = true; for (int j = 0; j < m; ++j) { if (str[i][j] > str[i + 1][j]) { for (int k = 0; k < n; ++k) str[k][j] = * ; break; } } break; } } if (!encountered) break; } int removed = count(str[0].begin(), str[0].end(), * ); cout << removed; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a; cin >> b; cin >> c; int d = a + b - c; int e = b + c - a; int f = a + c - b; if (d < 0 || e < 0 || f < 0 || e % 2 || d % 2 || f % 2) { cout << Impossible ; return 0; } cout << d / 2 << << e / 2 << << f / 2 << endl; } |
Require Import List.
Import ListNotations.
Require Import Coq.Sets.Ensembles.
From OakIFC Require Import
Lattice
Parameters
GenericMap
State
ModelSemUtils.
(* This file is the top-level model of the Oak runtime *)
(* RecordUpdate is a conveninece feature that provides functional updates for
* records with notation: https://github.com/tchajed/coq-record-update *)
(* To work with record updates from this library in proofs "unfold set" quickly
* changes goals back to normal Coq built-in record updates *)
From RecordUpdate Require Import RecordSet.
Import RecordSetNotations.
Local Open Scope map_scope.
(* Ensembles don't have implicit type params and these lines fix that *)
Arguments Ensembles.In {U}.
Arguments Ensembles.Add {U}.
Arguments Ensembles.Subtract {U}.
Arguments Ensembles.Singleton {U}.
Arguments Ensembles.Union {U}.
Arguments Ensembles.Setminus {U}.
Arguments Ensembles.Included {U}.
(*============================================================================
* Single Call Semantics
============================================================================*)
(* step for a single node (which can be thought of as a thread) executing
* a particular call *)
(* It might be akwkard looking that the call of a node is a part of the object,
but that there is no premise checking that this call is really the one used
in the relation. This is checked in the global transition relation just below.
*)
Inductive step_node (id: node_id): call -> state -> state -> Prop :=
| SWriteChan s n nlbl han clbl msg:
(s.(nodes).[?id]) = Labeled node (Some n) nlbl ->
(* caller is a real node with label nlbl *)
(s.(chans).[? han]).(lbl) = clbl ->
(* the handle has label clbl, though the call does not
check whether or not a channel is allocated to the handle
to avoid leaks (it can be Some or None) *)
In n.(write_handles) han -> (* caller has write handle *)
nlbl <<L clbl -> (* label of caller flowsTo label of ch*)
Included msg.(rhs) n.(read_handles) ->
(* caller has read handles it is sending *)
Included msg.(whs) n.(write_handles) ->
(* caller has write handles it is sending *)
let n' := node_del_rhans msg.(rhs) n in
(* remove the read handles from the sender because read
* handles (but not write handles) are linear *)
let s0 := state_upd_node id n' s in
(* NOTE: throwing an error if the channel is not valid would cause
a leak. It might be possible to still prove NI if the write call
always proceeds regarldess of validity but only pushes to the
validity, but only append the message if *)
step_node id (WriteChannel han msg) s
(state_chan_append_labeled han msg (state_upd_node id n' s))
| SWriteChanDwn s n nlbl han clbl msg ell':
(s.(nodes).[? id]) = Labeled node (Some n) nlbl ->
(* caller is a real node with label nlbl *)
(s.(chans).[? han]).(lbl) = clbl ->
(* the handle has label clbl, though the call does not
check whether or not a channel is allocated to the handle
to avoid leaks (it can be Some or None) *)
In n.(write_handles) han -> (* caller has write handle *)
Included msg.(rhs) n.(read_handles) ->
(* caller has read handles it is sending *)
Included msg.(whs) n.(write_handles) ->
(* caller has write handles it is sending *)
let n' := node_del_rhans msg.(rhs) n in
(* remove the read handles from the sender because read
* handles (but not write handles) are linear *)
let s0 := state_upd_node id n' s in
(* NOTE: throwing an error if the channel is not valid would cause
a leak. It might be possible to still prove NI if the write call
always proceeds regarldess of validity but only pushes to the
validity, but only append the message if *)
step_node id (WriteChannelDown han msg ell') s
(state_chan_append_labeled han msg (state_upd_node id n' s))
| SReadChan s n nlbl han ch clbl msg:
(s.(nodes).[?id]) = Labeled node (Some n) nlbl ->
(* caller is a real node with label nlbl *)
(s.(chans).[?han]) = Labeled channel (Some ch) clbl ->
(* handle points to real channel ch with label clbl*)
In n.(read_handles) han -> (* caller has read handle *)
(* A channel read happens only when there is a message
available in the channel. TODO, re-check what really happens
when a message is not available, and possibly improve the model.
E.g., if an error is thrown, execute an error continuation instead
of the usual one if an error is _not_ thrown.
*)
(msg_is_head ch msg) ->
channel_valid s han ->
(* the channel being read is not closed *)
clbl <<L nlbl ->
(* label of channel flowsTo label of caller.
checks that reading the message is safe
*)
nlbl <<L clbl ->
(* label of caller flowsTo label of ch. This check is less intuitive than the above.
However, reads are destructive because the channel is popped, so the calling node
is effectively doing a write to the channel. Any node that does a subsequent read
can detect whether or not the channel has been read because its contents may have
been changed. This check rules out this more subtle leak *)
let n' := node_get_hans n msg in
(* node gets handles from channel *)
let ch' := chan_pop ch in
(* pop the message, clear the read/write handles in ch *)
step_node id (ReadChannel han) s
(state_upd_chan han ch' (state_upd_node id n' s))
| SCreateChan s n nlbl h clbl:
(s.(nodes).[?id]) = Labeled node (Some n) nlbl ->
(* caller is a real node with label nlbl *)
fresh_han s h ->
(* the target handle is not in use *)
nlbl = bot ->
(* only public/trusted nodes can create channels, for now *)
let s0 := (state_upd_chan_labeled h {|
obj := new_chan; lbl := clbl;
|} s) in
let s1 := state_upd_node id (node_add_rhan h n) s0 in
let s' := state_upd_node id (node_add_whan h n) s1 in
step_node id (CreateChannel clbl) s s'
| SCreateNode s n nlbl new_id new_lbl h:
(s.(nodes).[?id]) = Labeled node (Some n) nlbl ->
(* caller is a real node with label nlbl *)
fresh_nid s id ->
(* target nid is not in use *)
nlbl = bot ->
(* only public/trusted nodes can create nodes for now *)
(* create new node with read handle *)
let s0 := (state_upd_node_labeled new_id {|
obj := Some {|
read_handles := (Singleton h);
write_handles := Empty_set handle;
ncall := Internal;
|};
lbl := new_lbl;
|} s) in
let s' := state_upd_node id (node_add_rhan h n) s0 in
step_node id (CreateNode new_lbl h) s s'
| SWaitOnChannels s n hs h ms nlbl clbl:
(s.(nodes).[?id]) = Labeled node (Some n) nlbl ->
(* caller is a real node with label nlbl *)
In hs h->
(* there is some handle h in the list of handles s.t. ... *)
s.(chans).[?h] = Labeled channel (Some (Chan ValidChannel ms)) clbl ->
(* It points to a valid channel s.t. ... *)
length ms > 0 -> (* it has some pending message and ... *)
clbl <<L nlbl -> (* its label flows to the label of the node *)
(* an alternative way to do this would be to check that the
the labels of all the channels in the list flowTo the label
of the node before blocking. This specification is implied
by that other one. *)
step_node id (WaitOnChannels hs) s s
(*
This specification says that we can't step out of a
WaitOnChannels until there is a non-empty channel in the list.
A better model might be one that:
- marks the node as blocked if this is not true
- in the global scheduler: only un-blocked nodes get scheduled
*)
| SChannelClose s n ch han nlbl clbl:
(s.(nodes).[?id]) = Labeled node (Some n) nlbl ->
(* caller is a real node with label nlbl *)
(s.(chans).[?han]).(lbl) = clbl ->
(* handle has label clbl *)
nlbl <<L clbl ->
step_node id (ChannelClose han) s
(state_upd_chan han (chan_close ch) s)
| SNodeLabelRead s:
step_node id NodeLabelRead s s
| SChannelLabelRead s han:
step_node id (ChannelLabelRead han) s s
| SInternal s:
step_node id Internal s s.
(* step for the full system which (non-deterministically) picks a thread to
* execute. This is needed in addition to step_node, because
we should show that regardless of the thread scheduling, there are no information
leaks. *)
(* To be general and language agnostic, computation of code within nodes other
than the ABI calls is modeled as simply returning an arbitrary continuation
(c') of the node's choosing (for any call). *)
(* Errors might later be modeled by choosing a different continuation based
on whether or not a call was successful, in this case, the resulting
continuation likely needs to be moved into the local transition relation *)
Inductive step_system: state -> state -> Prop :=
(* possibly also a termination case *)
| SystemSkip s: step_system s s
| SystemStepNode id n c c' s s':
(s.(nodes) .[?id]).(obj) = Some n ->
n.(ncall) = c ->
step_node id c s s' ->
step_system s (s_set_call s id c').
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3B_BLACKBOX_V
`define SKY130_FD_SC_MS__NAND3B_BLACKBOX_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand3b (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3B_BLACKBOX_V
|
#include <bits/stdc++.h> char map[55][55]; int main() { int n, ans = 2147483647; std::pair<int, int> s, t; std::queue<std::pair<int, int> > q; std::vector<std::pair<int, int> > vec1, vec2; scanf( %d %d %d %d %d , &n, &s.first, &s.second, &t.first, &t.second); for (int i = 1; i <= n; ++i) scanf( %s , map[i] + 1); vec1.push_back(s), map[s.first][s.second] = 2 , q.push(s); while (!q.empty()) { std::pair<int, int> p = q.front(); q.pop(); std::pair<int, int> temp = std::make_pair(p.first, p.second + 1); if (temp.second <= n && map[temp.first][temp.second] == 0 ) map[temp.first][temp.second] = 2 , vec1.push_back(temp), q.push(temp); temp = std::make_pair(p.first, p.second - 1); if (temp.second >= 0 && map[temp.first][temp.second] == 0 ) map[temp.first][temp.second] = 2 , vec1.push_back(temp), q.push(temp); temp = std::make_pair(p.first + 1, p.second); if (temp.first <= n && map[temp.first][temp.second] == 0 ) map[temp.first][temp.second] = 2 , vec1.push_back(temp), q.push(temp); temp = std::make_pair(p.first - 1, p.second); if (temp.first >= 0 && map[temp.first][temp.second] == 0 ) map[temp.first][temp.second] = 2 , vec1.push_back(temp), q.push(temp); } if (map[t.first][t.second] == 2 ) { putchar( 0 ); return 0; } vec2.push_back(t), map[t.first][t.second] = 2 , q.push(t); while (!q.empty()) { std::pair<int, int> p = q.front(); q.pop(); std::pair<int, int> temp = std::make_pair(p.first, p.second + 1); if (temp.second <= n && map[temp.first][temp.second] == 0 ) map[temp.first][temp.second] = 2 , vec2.push_back(temp), q.push(temp); temp = std::make_pair(p.first, p.second - 1); if (temp.second >= 0 && map[temp.first][temp.second] == 0 ) map[temp.first][temp.second] = 2 , vec2.push_back(temp), q.push(temp); temp = std::make_pair(p.first + 1, p.second); if (temp.first <= n && map[temp.first][temp.second] == 0 ) map[temp.first][temp.second] = 2 , vec2.push_back(temp), q.push(temp); temp = std::make_pair(p.first - 1, p.second); if (temp.first >= 0 && map[temp.first][temp.second] == 0 ) map[temp.first][temp.second] = 2 , vec2.push_back(temp), q.push(temp); } for (auto x1 : vec1) for (auto x2 : vec2) ans = std::min(ans, (x2.first - x1.first) * (x2.first - x1.first) + (x2.second - x1.second) * (x2.second - x1.second)); printf( %d n , ans); return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "block" *) module Loop_loop_height_dEe_rom (
addr0, ce0, q0, addr1, ce1, q1, addr2, ce2, q2, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input[AWIDTH-1:0] addr2;
input ce2;
output reg[DWIDTH-1:0] q2;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_dEe_rom.dat", ram0);
$readmemh("./Loop_loop_height_dEe_rom.dat", ram1);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram0[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram0[addr1];
end
end
always @(posedge clk)
begin
if (ce2)
begin
q2 <= ram1[addr2];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_dEe(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
input[AddressWidth - 1:0] address2;
input ce2;
output[DataWidth - 1:0] q2;
Loop_loop_height_dEe_rom Loop_loop_height_dEe_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ),
.addr2( address2 ),
.ce2( ce2 ),
.q2( q2 ));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long k4, k7, i, l; char s[100]; long long n; gets(s); l = strlen(s); k4 = 0; k7 = 0; for (i = 0; i < l; i++) { if (s[i] == 4 ) k4++; if (s[i] == 7 ) k7++; } if (k4 == 0 && k7 == 0) cout << -1; else if (k7 > k4) cout << 7; else cout << 4; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 200005; int n, m, lim, p = 1, a[N], nex[N * 2], spot[N * 2], head[N], fa[N], f[N], g[N]; int maxcolor[N][2], c[N]; bool color[N], v[N]; void add(int x, int y) { nex[++p] = head[x], head[x] = p, spot[p] = y; nex[++p] = head[y], head[y] = p, spot[p] = x; } void dfs1(int x) { int tp, y, cnt = 0, m1 = 0, m2 = 0; v[x] = 1; for (tp = head[x]; y = spot[tp], tp; tp = nex[tp]) if (a[y] >= lim && y != fa[x]) { fa[y] = x; dfs1(y); if (!c[y]) cnt += f[y]; else { c[x]++; if (f[y] > m2) m2 = f[y]; if (m1 < m2) swap(m1, m2); } } maxcolor[x][0] = m1; maxcolor[x][1] = m2; f[x] = cnt + m1 + 1; c[x] += color[x]; } void dfs2(int x, int &ret) { if (fa[x]) { if (c[fa[x]] - (c[x] != 0) > 0) { if (c[x]) { if (f[x] < maxcolor[fa[x]][0]) { g[x] = f[x] - maxcolor[x][0] + max(maxcolor[x][0], g[fa[x]]); if (g[fa[x]] > maxcolor[x][1]) maxcolor[x][1] = g[fa[x]]; if (maxcolor[x][0] < maxcolor[x][1]) swap(maxcolor[x][0], maxcolor[x][1]); } else { g[x] = f[x] - maxcolor[x][0] + max(maxcolor[x][0], g[fa[x]] - maxcolor[fa[x]][0] + maxcolor[fa[x]][1]); if (g[fa[x]] - maxcolor[fa[x]][0] + maxcolor[fa[x]][1] > maxcolor[x][1]) maxcolor[x][1] = g[fa[x]] - maxcolor[fa[x]][0] + maxcolor[fa[x]][1]; if (maxcolor[x][0] < maxcolor[x][1]) swap(maxcolor[x][0], maxcolor[x][1]); } } else g[x] = f[x] - maxcolor[x][0] + max(maxcolor[x][0], g[fa[x]] - f[x]); } else { if (c[x]) { if (f[x] < maxcolor[fa[x]][0]) g[x] = f[x] + g[fa[x]]; else g[x] = f[x] + g[fa[x]] - maxcolor[fa[x]][0] + maxcolor[fa[x]][1]; } else g[x] = g[fa[x]]; } c[x] += ((c[fa[x]] - (c[x] != 0)) != 0); } else g[x] = f[x]; ret = max(ret, g[x]); for (int tp = head[x]; tp; tp = nex[tp]) if (a[spot[tp]] >= lim && spot[tp] != fa[x]) dfs2(spot[tp], ret); } int solve() { memset(v, 0, sizeof(v)); memset(fa, 0, sizeof(fa)); memset(c, 0, sizeof(c)); int maxn = 0; for (int i = 1; i <= n; i++) if (a[i] >= lim && v[i] == 0) { dfs1(i), dfs2(i, maxn); } return maxn >= m; } int main() { int i, x, y, l, r, tp; cin >> n >> m; for (i = 1; i <= n; i++) scanf( %d , &a[i]); for (i = 1; i < n; i++) { scanf( %d%d , &x, &y); add(x, y); } for (l = 1, r = 1000000; l < r;) { lim = l + r + 1 >> 1; memset(color, 0, sizeof(color)); for (i = 1; i <= n; i++) if (a[i] < lim) for (tp = head[i]; tp; tp = nex[tp]) color[spot[tp]] = 1; if (solve()) l = lim; else r = lim - 1; } cout << l; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long i, j, n, cnt = 0, flag = 0, k = 0; string str; cin >> n >> str; for (i = 0; i < n; i++) { if (str[i] == ( ) { cnt++; if (cnt == 2) j = i; } else cnt--; if ((cnt == -2) && (!k)) k = i; if (cnt < -2) break; if (cnt < 0) flag = 1; } if ((!cnt) || (flag && cnt == 2) || (i != n) || ((cnt != 2) && (cnt != -2))) { cout << 0 n ; return 0; } if (cnt == 2) { cnt = 0; for (i = j; i < n; i++) { if (str[i] == ( ) cnt++; } } else { cnt = 0; for (i = 0; i < k; i++) { if (str[i] == ( ) cnt++; else cnt--; if (cnt == -1) break; } cnt = 0; k = i; for (i = 0; i <= k; i++) { if (str[i] == ) ) cnt++; } } cout << cnt << endl; return 0; } |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_regfile_reg1 (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 31: 0] in_port;
input reset_n;
wire clk_en;
wire [ 31: 0] data_in;
wire [ 31: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {32 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long t, xiaoyud, dayu, n, x, pos, ans1, mo = 1e9 + 7, ans2, ans; int main() { cin >> n >> x >> pos; long long l = 0, r = n; while (l < r) { long long mid = (l + r) / 2; if (mid <= pos) { l = mid + 1; if (mid != pos) xiaoyud++; } else { r = mid; dayu++; } } ans1 = 1; for (long long i = 1; i <= xiaoyud; i++) { ans1 = (ans1 * (x - 1 - i + 1)) % mo; } ans2 = 1; for (long long i = 1; i <= dayu; i++) { ans2 = (ans2 * (n - x - i + 1)) % mo; } ans = (ans1 * ans2) % mo; for (long long i = 1; i <= n - xiaoyud - dayu - 1; i++) { ans = (ans * (n - xiaoyud - dayu - i)) % mo; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; string a, b, c; long long n, x, y, z; pair<long long, long long> f[2000]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> a >> b >> c; for (auto i : a) { f[i].first++; x = max(x, f[i].first); } for (auto i : b) { if (f[i].second != 2) f[i] = {0, 2}; f[i].first++; y = max(y, f[i].first); } for (auto i : c) { if (f[i].second != 3) f[i] = {0, 3}; f[i].first++; z = max(z, f[i].first); } if (n == 1) { if (a.size() == x) a.erase(0, 1); if (b.size() == y) b.erase(0, 1); if (c.size() == z) c.erase(0, 1); } x = min(x + n, (long long)a.size()); y = min(y + n, (long long)b.size()); z = min(z + n, (long long)c.size()); if (x > y && x > z) return cout << Kuro , 0; if (y > x && y > z) return cout << Shiro , 0; if (z > x && z > y) return cout << Katie , 0; cout << Draw ; return 0; } |
#include <bits/stdc++.h> using namespace std; inline int Int() { int x; scanf( %d , &x); return x; } inline long long Long() { long long x; scanf( %lld , &x); return x; } void err(istream_iterator<string> it) { cout << endl; } template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << ; err(++it, args...); } const int N = (int)2e5 + 5; const int maxN = (int)1e6 + 6; const long long Mod = (long long)1e9 + 7; const int inf = (int)2e9; const long long Inf = (long long)1e18; const int mod = (int)1e9 + 7; inline int add(int a, int b) { a += b; return a >= mod ? a - mod : a; } inline int sub(int a, int b) { a -= b; return a < 0 ? a + mod : a; } inline int mul(int a, int b) { return (long long)a * b % mod; } long long a[N], s[N], p[N]; struct CHT { vector<long long> m, c; bool bad(int f1, int f2, int f3, int tp) { if (tp == 1) return 1.0 * (c[f3] - c[f1]) * (m[f1] - m[f2]) >= 1.0 * (c[f2] - c[f1]) * (m[f1] - m[f3]); else return 1.0 * (c[f3] - c[f1]) * (m[f1] - m[f2]) <= 1.0 * (c[f2] - c[f1]) * (m[f1] - m[f3]); } void add(long long _m, long long _c, int tp) { m.push_back(_m), c.push_back(_c); int second = (int)m.size(); while (second >= 3 and bad(second - 3, second - 2, second - 1, tp)) { m.erase(m.end() - 2); c.erase(c.end() - 2); --second; } } long long f(long long x, int i) { return x * m[i] + c[i]; } long long query(long long x) { int l = 0, r = (int)m.size() - 1, id = 0; while (l <= r) { int del = (r - l) / 3; int mid1 = l + del, mid2 = r - del; if (f(x, mid1) > f(x, mid2)) id = mid1, r = mid2 - 1; else id = mid2, l = mid1 + 1; } return f(x, id); } } ds, ds1; int main() { int test = 1, tc = 0; while (test--) { int n = Int(); long long ans = 0; for (int i = 1; i <= n; ++i) { a[i] = Int(); p[i] = p[i - 1] + a[i]; ans += (1LL * i * a[i]); } long long res = 0; ds.add(n, -p[n], 1); for (int i = n - 1; i >= 1; --i) { res = max(res, ds.query(a[i]) + p[i] - i * a[i]); ds.add(i, -p[i], 1); } ds1.add(1, 0, 2); for (int i = 2; i <= n; ++i) { res = max(res, ds1.query(a[i]) + p[i] - (i + 1) * a[i]); ds1.add(i, -p[i - 1], 2); } cout << res + ans << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAX_N = 1505; const int dx[] = {-1, 0, 1, 0}; const int dy[] = {0, 1, 0, -1}; int visx[MAX_N][MAX_N]; int visy[MAX_N][MAX_N]; char A[MAX_N][MAX_N]; int sx, sy; int n, m; queue<pair<int, int> > q; bool in(int x, int y) { return x >= 0 && x < n && y >= 0 && y < m; } int main() { cin >> n >> m; for (int i = 0; i < n; i++) cin >> A[i]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (A[i][j] == S ) { A[i][j] = . ; sx = i, sy = j; } } } sx += n * m; sy += n * m; q.push(make_pair(sx, sy)); memset(visx, -1, sizeof(visx)); memset(visy, -1, sizeof(visy)); while (!q.empty()) { pair<int, int> t = q.front(); q.pop(); if (A[(t.first + n) % n][(t.second + m) % m] == # ) continue; if (visx[(t.first + n) % n][(t.second + m) % m] == t.first && visy[(t.first + n) % n][(t.second + m) % m] == t.second) continue; if (visx[(t.first + n) % n][(t.second + m) % m] == -1) visx[(t.first + n) % n][(t.second + m) % m] = t.first; if (visy[(t.first + n) % n][(t.second + m) % m] == -1) visy[(t.first + n) % n][(t.second + m) % m] = t.second; if (visx[(t.first + n) % n][(t.second + m) % m] != t.first || visy[(t.first + n) % n][(t.second + m) % m] != t.second) { cout << Yes << endl; return 0; } for (int i = 0; i < 4; i++) { int nx = dx[i] + t.first; int ny = dy[i] + t.second; q.push(make_pair(nx, ny)); } } cout << No << endl; return 0; } |
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