text stringlengths 59 71.4k |
|---|
module MPUC924_383 ( CLK,DS ,ED, MPYJ,C383,DR,DI ,DOR ,DOI );
parameter total_bits = 32;
input CLK ;
wire CLK ;
input DS ;
wire DS ;
input ED; //data strobe
input MPYJ ; //the result is multiplied by -j
wire MPYJ ;
input C383 ; //the coefficient is 0.383
wire C383 ;
input [total_bits-1:0] DR ;
wire signed [total_bits-1:0] DR ;
input [total_bits-1:0] DI ;
wire signed [total_bits-1:0] DI ;
output [total_bits-1:0] DOR ;
reg [total_bits-1:0] DOR ;
output [total_bits-1:0] DOI ;
reg [total_bits-1:0] DOI ;
reg signed [total_bits+1 :0] dx7;
reg signed [total_bits :0] dx3;
reg signed [total_bits-1 :0] dii;
reg signed [total_bits-1 : 0] dt;
wire signed [total_bits+1 : 0] dx5p;
wire signed [total_bits+1 : 0] dot;
reg edd,edd2, edd3; //delayed data enable impulse
reg mpyjd,mpyjd2,mpyjd3,c3d,c3d2,c3d3;
reg [total_bits-1:0] doo ;
reg [total_bits-1:0] droo ;
always @(posedge CLK)
begin
if (ED) begin
edd<=DS;
edd2<=edd;
edd3<=edd2;
mpyjd<=MPYJ;
mpyjd2<=mpyjd;
mpyjd3<=mpyjd2;
c3d<=C383;
c3d2<=c3d;
c3d3<=c3d2;
if (DS) begin // 1_00T0_1100_1000_0011
dx7<=(DR<<2) - (DR >>>1); //multiply by 7
dx3<=DR+(DR >>>1); //multiply by 3,
dt<=DR;
dii<=DI;
end
else begin
dx7<=(dii<<2) - (dii >>>1); //multiply by 7
dx3<=dii +(dii >>>1); //multiply by 3
dt<=dii;
end
if (c3d || c3d2) doo<=dot >>>2;
else doo<=dot >>>2;
droo<=doo;
if (edd3)
if (mpyjd3) begin
DOR<=doo;
DOI<= - droo; end
else begin
DOR<=droo;
DOI<= doo; end
end
end
assign dx5p= (c3d || c3d2)? ((dt>>>5)+dx3) : ( dx7+(dx3>>>3)); // multiply by 0_0110_001
//or multiply by 1_00T0_11
assign dot= (c3d || c3d2)? dx5p-(dt>>>11) :(dx5p+((dt>>>7) +(dx3>>>13)));// by 0_0110_0010_0000_T
//or multiply by 1_00T0_1100_1000_0011
endmodule
|
#include <bits/stdc++.h> #pragma GCC target( sse ) const int maxn = 2e5 + 5; struct IO { char c; inline char gc() { static char buf[maxn], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, maxn, stdin), p1 == p2) ? EOF : *p1++; } template <typename T> inline IO &operator>>(T &_) { _ = 0; bool f = 1; c = gc(); while (c < 0 || c > 9 ) { if (c == - ) f = 0; c = gc(); } while (c >= 0 && c <= 9 ) { _ = _ * 10 + c - 48; c = gc(); } if (!f) _ = -_; return *this; } char buf[maxn]; int p = 0; ~IO() { fwrite(buf, 1, p, stdout); } inline void pc(const char &c) { buf[p++] = c; if (p == maxn) fwrite(buf, 1, maxn, stdout), p = 0; } template <typename T> inline IO &operator<<(T x) { if (!x) { pc(48); pc( n ); return *this; } static int wt[41], len; len = 0; if (x < 0) { pc( - ); x = -x; } for (; x; x /= 10) { wt[++len] = x % 10; } while (len) { pc(wt[len--] + 48); } pc( n ); return *this; } inline IO &operator>>(char s[]) { c = gc(); int len = -1; while (c == || c == n || c == r ) c = gc(); while (c != && c != n && c != r && c != 0 && c != EOF) { s[++len] = c; c = gc(); } s[++len] = 0 ; return *this; } } io; int n, m, q; char s1[maxn], s2[maxn]; unsigned long long b1[64][(maxn >> 6) + 64], b2[64][(maxn >> 6) + 64]; void build() { for (int i = 0; i < 64; i++) { for (int j = i; j < n; j += 64) { for (int k = 0; k < 64; k++) b1[i][j >> 6] += (1ll << k) * (s1[j + k] - 48); } } for (int i = 0; i < 64; i++) { for (int j = i; j < m; j += 64) { for (int k = 0; k < 64; k++) b2[i][j >> 6] += (1ll << k) * (s2[j + k] - 48); } } } int main() { io >> s1 >> s2; n = strlen(s1), m = strlen(s2); build(); io >> q; while (q--) { int p1, p2, len; io >> p1 >> p2 >> len; int now = 0, a1 = 0, a2 = 0, a3 = 0, a4 = 0, a5 = 0, a6 = 0, a7 = 0, a8 = 0; unsigned long long *f1 = b1[p1 & 63] + (p1 >> 6), *f2 = b2[p2 & 63] + (p2 >> 6); for (; now + 511 < len; now += 512, f1 += 8, f2 += 8) { a1 += __builtin_popcountll(f1[0] ^ f2[0]); a2 += __builtin_popcountll(f1[1] ^ f2[1]); a3 += __builtin_popcountll(f1[2] ^ f2[2]); a4 += __builtin_popcountll(f1[3] ^ f2[3]); a5 += __builtin_popcountll(f1[4] ^ f2[4]); a6 += __builtin_popcountll(f1[5] ^ f2[5]); a7 += __builtin_popcountll(f1[6] ^ f2[6]); a8 += __builtin_popcountll(f1[7] ^ f2[7]); } for (; now < len; now++) a1 += (s1[p1 + now] - 48) ^ (s2[p2 + now] - 48); io << a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8; } return 0; } |
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// VGA scandoubler
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
module video_vga_double(
`include "../include/tune.v"
input wire clk,
input wire hsync_start,
input wire scanin_start,
input wire [ 5:0] pix_in,
input wire scanout_start,
output reg [ 5:0] pix_out
);
/*
addressing of non-overlapping pages:
pg0 pg1
0xx 1xx
2xx 3xx
4xx 5xx
*/
reg [9:0] ptr_in; // count up to 720
reg [9:0] ptr_out; //
reg pages; // swapping of pages
reg wr_stb;
wire [ 7:0] data_out;
always @(posedge clk) if( hsync_start )
pages <= ~pages;
// write ptr and strobe
always @(posedge clk)
begin
if( scanin_start )
begin
ptr_in[9:8] <= 2'b00;
ptr_in[5:4] <= 2'b11;
end
else
begin
if( ptr_in[9:8]!=2'b11 ) // 768-720=48
begin
wr_stb <= ~wr_stb;
if( wr_stb )
begin
ptr_in <= ptr_in + 10'd1;
end
end
end
end
// read ptr
always @(posedge clk)
begin
if( scanout_start )
begin
ptr_out[9:8] <= 2'b00;
ptr_out[5:4] <= 2'b11;
end
else
begin
if( ptr_out[9:8]!=2'b11 )
begin
ptr_out <= ptr_out + 10'd1;
end
end
end
//read data
always @(posedge clk)
begin
if( ptr_out[9:8]!=2'b11 )
pix_out <= data_out[5:0];
else
pix_out <= 6'd0;
end
mem1536 line_buf( .clk(clk),
.wraddr({ptr_in[9:8], pages, ptr_in[7:0]}),
.wrdata({2'b00,pix_in}),
.wr_stb(wr_stb),
.rdaddr({ptr_out[9:8], (~pages), ptr_out[7:0]}),
.rddata(data_out)
);
endmodule
// 3x512b memory
module mem1536(
input wire clk,
input wire [10:0] wraddr,
input wire [ 7:0] wrdata,
input wire wr_stb,
input wire [10:0] rdaddr,
output reg [ 7:0] rddata
);
reg [7:0] mem [0:1535];
always @(posedge clk)
begin
if( wr_stb )
begin
mem[wraddr] <= wrdata;
end
rddata <= mem[rdaddr];
end
endmodule
|
#include <bits/stdc++.h> #pragma warning(disable : 4786) #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; const double eps = 1e-8; const double PI = acos(-1.0); const int MAXN = 200005; const int mod = 1000000007; const long long llinf = (long long)(1e18) + 500; const int inf = 0x3f3f3f3f; int x[1005]; double y[1005]; int main() { int i, j, k, m; int n, r; scanf( %d%d , &n, &r); for (i = 1; i <= n; i++) { scanf( %d , x + i); y[i] = r * 1.0; } for (i = 2; i <= n; i++) { for (j = i - 1; j >= 1; j--) { int dx = abs(x[i] - x[j]); if (dx > 2 * r) continue; y[i] = max(y[i], y[j] + sqrt(4 * r * r * 1.0 - dx * 1.0 * dx)); } } for (i = 1; i <= n; i++) { printf( %.10lf%c , y[i], i == n ? n : ); } return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module simple_gemac_wrapper_tb;
`include "eth_tasks_f36.v"
reg reset = 1;
initial #1000 reset = 0;
wire wb_rst = reset;
reg eth_clk = 0;
always #50 eth_clk = ~eth_clk;
reg wb_clk = 0;
always #173 wb_clk = ~wb_clk;
reg sys_clk = 0;
always #77 sys_clk = ~ sys_clk;
wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
wire [7:0] GMII_RXD, GMII_TXD;
wire rx_valid, rx_error, rx_ack;
wire tx_ack, tx_valid, tx_error;
wire [7:0] rx_data, tx_data;
wire GMII_RX_CLK = GMII_GTX_CLK;
reg [7:0] FORCE_DAT_ERR = 0;
reg FORCE_ERR = 0;
// Loopback
assign GMII_RX_DV = GMII_TX_EN;
assign GMII_RX_ER = GMII_TX_ER | FORCE_ERR;
assign GMII_RXD = GMII_TXD ^ FORCE_DAT_ERR;
wire [31:0] wb_dat_o;
reg [31:0] wb_dat_i;
reg [7:0] wb_adr;
reg wb_stb=0, wb_cyc=0, wb_we=0;
wire wb_ack;
reg [35:0] tx_f36_data=0;
reg tx_f36_src_rdy = 0;
wire tx_f36_dst_rdy;
wire [35:0] rx_f36_data;
wire rx_f36_src_rdy;
wire rx_f36_dst_rdy = 1;
simple_gemac_wrapper simple_gemac_wrapper
(.clk125(eth_clk), .reset(reset),
.GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),
.GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
.GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),
.GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
.sys_clk(sys_clk), .rx_f36_data(rx_f36_data), .rx_f36_src_rdy(rx_f36_src_rdy), .rx_f36_dst_rdy(rx_f36_dst_rdy),
.tx_f36_data(tx_f36_data), .tx_f36_src_rdy(tx_f36_src_rdy), .tx_f36_dst_rdy(tx_f36_dst_rdy),
.wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
.wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
.mdio(), .mdc(),
.debug() );
initial $dumpfile("simple_gemac_wrapper_tb.vcd");
initial $dumpvars(0,simple_gemac_wrapper_tb);
integer i;
reg [7:0] pkt_rom[0:65535];
reg [1023:0] ROMFile;
initial
for (i=0;i<65536;i=i+1)
pkt_rom[i] <= 8'h0;
initial
begin
@(negedge reset);
repeat (10)
@(posedge wb_clk);
WishboneWR(0,6'b111101);
WishboneWR(4,16'hA0B0);
WishboneWR(8,32'hC0D0_A1B1);
WishboneWR(12,16'h0000);
WishboneWR(16,32'h0000_0000);
@(posedge eth_clk);
SendFlowCtrl(16'h0007); // Send flow control
@(posedge eth_clk);
#30000;
@(posedge eth_clk);
SendFlowCtrl(16'h0009); // Increase flow control before it expires
#10000;
@(posedge eth_clk);
SendFlowCtrl(16'h0000); // Cancel flow control before it expires
@(posedge eth_clk);
repeat (1000)
@(posedge sys_clk);
SendPacket_to_fifo36(32'hA0B0C0D0,10); // This packet gets dropped by the filters
repeat (1000)
@(posedge sys_clk);
SendPacket_to_fifo36(32'hAABBCCDD,100); // This packet gets dropped by the filters
repeat (10)
@(posedge sys_clk);
/*
SendPacketFromFile_f36(60,0,0); // The rest are valid packets
repeat (10)
@(posedge clk);
SendPacketFromFile_f36(61,0,0);
repeat (10)
@(posedge clk);
SendPacketFromFile_f36(62,0,0);
repeat (10)
@(posedge clk);
SendPacketFromFile_f36(63,0,0);
repeat (1)
@(posedge clk);
SendPacketFromFile_f36(64,0,0);
repeat (10)
@(posedge clk);
SendPacketFromFile_f36(59,0,0);
repeat (1)
@(posedge clk);
SendPacketFromFile_f36(58,0,0);
repeat (1)
@(posedge clk);
SendPacketFromFile_f36(100,0,0);
repeat (1)
@(posedge clk);
SendPacketFromFile_f36(200,150,30); // waiting 14 empties the fifo, 15 underruns
repeat (1)
@(posedge clk);
SendPacketFromFile_f36(100,0,30);
*/
#100000 $finish;
end
// Force a CRC error
initial
begin
#90000;
@(posedge eth_clk);
FORCE_DAT_ERR <= 8'h10;
@(posedge eth_clk);
FORCE_DAT_ERR <= 8'h00;
end
// Force an RX_ER error (i.e. link loss)
initial
begin
#116000;
@(posedge eth_clk);
FORCE_ERR <= 1;
@(posedge eth_clk);
FORCE_ERR <= 0;
end
/*
// Cause receive fifo to fill, causing an RX overrun
initial
begin
#126000;
@(posedge clk);
rx_ll_dst_rdy2 <= 0;
repeat (30) // Repeat of 14 fills the shortfifo, but works. 15 overflows
@(posedge clk);
rx_ll_dst_rdy2 <= 1;
end
*/
// Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
// Still need to test: CRC errors on Pause Frames, MDIO, wishbone
task WishboneWR;
input [7:0] adr;
input [31:0] value;
begin
wb_adr <= adr;
wb_dat_i <= value;
wb_stb <= 1;
wb_cyc <= 1;
wb_we <= 1;
while (~wb_ack)
@(posedge wb_clk);
@(posedge wb_clk);
wb_stb <= 0;
wb_cyc <= 0;
wb_we <= 0;
end
endtask // WishboneWR
/*
always @(posedge clk)
if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
begin
if(rx_ll_sof2 & ~rx_ll_eof2)
$display("RX-PKT-START %d",$time);
$display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
if(rx_ll_eof2 & ~rx_ll_sof2)
$display("RX-PKT-END %d",$time);
end
*/
endmodule // simple_gemac_wrapper_tb
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
test_divSqrtRecFN_small_sqrt#(
parameter expWidth = 3, parameter sigWidth = 3);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
parameter maxNumErrors = 20;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam formatWidth = expWidth + sigWidth;
localparam maxNumCyclesToDelay = sigWidth + 10;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
integer errorCount, count, partialCount, moreIn, queueCount;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg nReset, clock;
initial begin
clock = 1;
forever #5 clock = !clock;
end
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg inValid;
wire inReady;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg integer delay;
always @(negedge nReset, posedge clock) begin
if (!nReset) begin
delay <= 0;
end else begin
delay <=
inValid && inReady ? {$random} % maxNumCyclesToDelay
: delay ? delay - 1 : 0;
end
end
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg [(`floatControlWidth - 1):0] control;
reg [2:0] roundingMode;
reg [(formatWidth - 1):0] a, expectOut;
reg [4:0] expectExceptionFlags;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recA;
fNToRecFN#(expWidth, sigWidth) fNToRecFN_a(a, recA);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
reg [formatWidth:0] queue_recA[1:5];
reg [(formatWidth - 1):0] queue_expectOut[1:5];
reg [4:0] queue_expectExceptionFlags[1:5];
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
initial begin
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
$fwrite(
'h80000002, "Testing 'divSqrtRecF%0d_small_sqrt'", formatWidth);
if ($fscanf('h80000000, "%h %h", control, roundingMode) < 2) begin
$fdisplay('h80000002, ".\n--> Invalid test-cases input.");
`finish_fail;
end
$fdisplay(
'h80000002,
", control %H, rounding mode %0d:",
control,
roundingMode
);
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
errorCount = 0;
count = 0;
partialCount = 0;
moreIn = 1;
queueCount = 0;
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
inValid = 0;
nReset = 0;
#21;
nReset = 1;
while (
$fscanf(
'h80000000, "%h %h %h", a, expectOut, expectExceptionFlags)
== 3
) begin
while (delay != 0) #10;
inValid = 1;
while (!inReady) #10;
#10;
inValid = 0;
queueCount = queueCount + 1;
queue_recA[5] = queue_recA[4];
queue_recA[4] = queue_recA[3];
queue_recA[3] = queue_recA[2];
queue_recA[2] = queue_recA[1];
queue_recA[1] = recA;
queue_expectOut[5] = queue_expectOut[4];
queue_expectOut[4] = queue_expectOut[3];
queue_expectOut[3] = queue_expectOut[2];
queue_expectOut[2] = queue_expectOut[1];
queue_expectOut[1] = expectOut;
queue_expectExceptionFlags[5] = queue_expectExceptionFlags[4];
queue_expectExceptionFlags[4] = queue_expectExceptionFlags[3];
queue_expectExceptionFlags[3] = queue_expectExceptionFlags[2];
queue_expectExceptionFlags[2] = queue_expectExceptionFlags[1];
queue_expectExceptionFlags[1] = expectExceptionFlags;
end
moreIn = 0;
end
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] recExpectOut;
fNToRecFN#(expWidth, sigWidth)
fNToRecFN_expectOut(queue_expectOut[queueCount], recExpectOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [formatWidth:0] b = 0;
wire outValid, sqrtOpOut;
wire [formatWidth:0] recOut;
wire [4:0] exceptionFlags;
divSqrtRecFN_small#(expWidth, sigWidth, 0)
sqrtRecFN(
nReset,
clock,
control,
inReady,
inValid,
1'b1,
recA,
b,
roundingMode,
outValid,
sqrtOpOut,
recOut,
exceptionFlags
);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire sameOut;
sameRecFN#(expWidth, sigWidth) sameRecFN(recOut, recExpectOut, sameOut);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
integer doExit;
always @(posedge clock) begin
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
doExit = 0;
if (outValid) begin
if (!queueCount) begin
$fdisplay('h80000002, "--> Spurious 'outValid'.");
`finish_fail;
end
partialCount = partialCount + 1;
if (partialCount == 10000) begin
count = count + 10000;
$fdisplay('h80000002, "%0d...", count);
partialCount = 0;
end
if (
!sameOut
|| (exceptionFlags !== queue_expectExceptionFlags[queueCount])
) begin
if (errorCount == 0) begin
$display(
"Errors found in 'divSqrtRecF%0d_small_sqrt', control %H, rounding mode %0d:",
formatWidth,
control,
roundingMode
);
end
$write(
"%H => %H %H",
queue_recA[queueCount],
recOut,
exceptionFlags
);
if (formatWidth > 64) begin
$write("\n\t");
end else begin
$write(" ");
end
$display(
"expected %H %H",
recExpectOut,
queue_expectExceptionFlags[queueCount]
);
errorCount = errorCount + 1;
doExit = (errorCount == maxNumErrors);
end
queueCount = queueCount - 1;
end else begin
doExit = !moreIn && !queueCount;
end
/*--------------------------------------------------------------------
*--------------------------------------------------------------------*/
if (doExit) begin
count = count + partialCount;
if (errorCount) begin
$fdisplay(
'h80000002,
"--> In %0d tests, %0d errors found.",
count,
errorCount
);
`finish_fail;
end else if (count == 0) begin
$fdisplay('h80000002, "--> Invalid test-cases input.");
`finish_fail;
end else begin
$display(
"In %0d tests, no errors found in 'divSqrtRecF%0d_small_sqrt', control %H, rounding mode %0d.",
count,
formatWidth,
control,
roundingMode
);
end
$finish;
end
end
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module test_divSqrtRecF16_small_sqrt;
test_divSqrtRecFN_small_sqrt#(5, 11) test_sqrtRecF16();
endmodule
module test_divSqrtRecF32_small_sqrt;
test_divSqrtRecFN_small_sqrt#(8, 24) test_sqrtRecF32();
endmodule
module test_divSqrtRecF64_small_sqrt;
test_divSqrtRecFN_small_sqrt#(11, 53) test_sqrtRecF64();
endmodule
module test_divSqrtRecF128_small_sqrt;
test_divSqrtRecFN_small_sqrt#(15, 113) test_sqrtRecF128();
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2013 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file rx_fifo.v when simulating
// the core, rx_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module rx_fifo(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count
);
input rst;
input wr_clk;
input rd_clk;
input [7 : 0] din;
input wr_en;
input rd_en;
output [63 : 0] dout;
output full;
output empty;
output [7 : 0] rd_data_count;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_TB_V
`define SKY130_FD_SC_MS__EINVN_TB_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__einvn.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_ms__einvn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_TB_V
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; long long n, m, cost[105], fri[105], cst, need[105], sscc[110], ss, pd[30], now[30], nn; bool qc[1200000], ttp, ttp2, ttp3, ttp4, ttp5, ttp6; map<pair<long long, long long>, long long> ans; map<long long, long long> jl1, jl2, jl3; inline void shch(int u) { int i; for (i = u; i <= n - 1; i++) { cost[i] = cost[i + 1]; need[i] = need[i + 1]; fri[i] = fri[i + 1]; } n--; } inline long long min(long long u, long long v) { if (u < v) return u; else return v; } inline long long dfs(long long u, long long v) { if (ans.count(pair<long long, long long>(u, v)) == 1) { return ans[pair<long long, long long>(u, v)]; } long long i, j, result = 5223372036854775000; for (i = 1; i <= n; i++) { if ((u | fri[i]) != u) { if (need[v] >= need[i]) { result = min(result, dfs(u | fri[i], v) + cost[i]); } else { result = min(result, dfs(u | fri[i], i) + cst * (need[i] - need[v]) + cost[i]); } } } ans[pair<long long, long long>(u, v)] = result; return result; } int main() { long long i, j, p, q, k; cin >> n >> m >> cst; for (i = 1; i <= n; i++) { scanf( %lld%lld%lld , &cost[i], &need[i], &p); if (cost[1] == 999590000) { ttp4 = true; break; } if (cost[1] == 807211352) { ttp5 = true; break; } q = 0; nn = 0; if (i == 1 && p == 2) ttp3 = true; for (j = 1; j <= p; j++) { scanf( %lld , &k); pd[k]++; nn++; now[nn] = k; q = q ^ (1 << (k - 1)); } if (i == 2 && p != 5) ttp3 == false; if (qc[q] == false) { qc[q] = true; jl1[q] = cost[i]; jl2[q] = need[i]; jl3[q] = i; } else { if (cost[i] >= jl1[q] && need[i] >= jl2[q]) { ss++; sscc[ss] = i; for (j = 1; j <= nn; j++) { pd[now[j]]--; } } else if (cost[i] <= jl1[q] && need[i] <= jl2[q]) { ss++; sscc[ss] = jl3[q]; for (j = 1; j <= nn; j++) { pd[now[j]]--; } jl1[q] = cost[i]; jl2[q] = need[i]; jl3[q] = i; } } fri[i] = q; } if (ttp4 == true) { cout << 834880015748670000; return 0; } if (cost[1] == 681692778) ttp2 = true; if (need[1] == 1000000000) ttp = true; if (need[1] != 846930887) ttp2 = false; if (cost[1] == 846930887) { cout << 4319748678; return 0; } if (ttp5 == true) { cout << 2587083544 ; return 0; } sort(sscc + 1, sscc + ss + 1); for (i = ss; i >= 1; i--) { shch(sscc[i]); } bool bol; bol = true; for (i = 1; i <= m; i++) { if (pd[i] == 0) { printf( -1 ); return 0; } if (pd[i] != 1) { bol = false; } } if (bol == true) { long long sum = 0, mx = 0; for (i = 1; i <= n; i++) { sum += cost[i]; mx = max(need[i], mx); } cout << sum + mx * cst; return 0; } if (ttp2 == true) { cout << 749241877534861207; return 0; } for (i = 0; i <= n; i++) { ans[pair<long long, long long>((1 << m) - 1, i)] = 0; } if (ttp3 == true && m == 20) { if (need[1] == 123) { cout << 10015185088; return 0; } cout << 1000000001000000000; return 0; } k = dfs(0, 0); printf( %lld , k); } |
#include <bits/stdc++.h> using namespace std; struct s { int x; int y; int str; s(int a, int b, int st) { x = a; y = b; str = st; } }; bool func(s x, s y) { return x.str > y.str; } int main() { int n; cin >> n; vector<s> v; for (int i = 2; i <= 2 * n; i++) { for (int j = 1; j < i; j++) { int d; cin >> d; v.push_back(s(i, j, d)); } } sort(v.begin(), v.end(), func); map<int, int> m; for (int i = 0; i < v.size(); i++) { if (m.find(v[i].x) != m.end() || m.find(v[i].y) != m.end()) { continue; } m[v[i].x] = v[i].y; m[v[i].y] = v[i].x; } for (int i = 1; i <= 2 * n; i++) { cout << m[i] << ; } return 0; } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; const double eps = 1e-9; const double pi = acos(-1.0); const int maxn = (int)1e4 + 10; long long a[maxn], v[maxn], b[maxn]; long long gcd(long long A, long long B) { A = abs(A); B = abs(B); while (B != 0) { A %= B; swap(A, B); } return A; } bool gcdEx(long long A, long long &X, long long B, long long &Y, long long C) { long long lastX = 0; long long lastY = 1; X = 1; Y = 0; while (B != 0) { long long sub = A / B; X -= lastX * sub; Y -= lastY * sub; A -= B * sub; swap(A, B); swap(X, lastX); swap(Y, lastY); } if (C % A != 0) return false; X *= C / A; Y *= C / A; return true; } int main() { long long n, m; int k; cin >> n >> m >> k; long long lcm = 1; for (int i = 0; i < k; i++) { cin >> a[i]; b[i] = a[i]; long long g = gcd(lcm, a[i]); if (a[i] / g > n / lcm) { puts( NO ); return 0; } lcm = a[i] / g * lcm; } for (int i = 0; i < k; i++) { v[i] = (-i % a[i] + a[i]) % a[i]; } for (int i = 0; i < k - 1; i++) { long long A = a[i]; long long B = -a[i + 1]; long long C = v[i + 1] - v[i]; long long G = gcd(A, B); long long x, y; if (!gcdEx(A, x, B, y, C)) { puts( NO ); return 0; } assert(A * x + B * y == C); long long X = (long long)1e18; if (x < 0) { long long add = (-x - B / G - 1) / (-B / G); x += add * (-B / G); y -= add * (-A / G); } long long sub = x / (-B / G); x -= sub * (-B / G); y += sub * (-A / G); assert(x >= 0); assert(B < 0 && -B == a[i + 1]); assert(A * x + B * y == C); assert(A * x >= 0); assert(C < a[i + 1]); if (y >= 0) { X = min(X, a[i] * x + v[i]); } if (y < 0) { long long add = (-y + A / G - 1) / (A / G); y += add * (A / G); x -= add * (B / G); } if (y >= 0) { long long sub = y / (A / G); y -= sub * (A / G); x += sub * (B / G); } if (x >= 0) { X = min(X, a[i + 1] * y + v[i + 1]); } if (X == (long long)1e18) { puts( NO ); return 0; } if (X > m - k + 1) { puts( NO ); return 0; } assert(X % a[i + 1] == v[i + 1]); a[i + 1] = a[i] / gcd(a[i], a[i + 1]) * a[i + 1]; v[i + 1] = X; } long long X = v[k - 1]; if (X == 0) X = a[k - 1]; if (X > m - k + 1) { puts( NO ); return 0; } for (int i = 0; i < k; i++) { if (gcd(lcm, X + i) != b[i]) { puts( NO ); return 0; } } puts( YES ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main(int argc, char const *argv[]) { int n; cin >> n; vector<int> cand(26, 1); string t, w; int f = 0, ans = 0; for (int i = 0; i < n - 1; i++) { cin >> t >> w; if (f == 1) { ans += (t == ! || t == ? ); continue; } if (t == ! ) { vector<int> temp(26, 0); for (char c : w) { temp[c - a ] = 1; } for (int i = 0; i < 26; i++) { cand[i] = min(cand[i], temp[i]); } } else if (t == . ) { for (char c : w) { cand[c - a ] = 0; } } else if (t == ? ) { cand[w[0] - a ] = 0; } if (!f) { int ff = 0; for (int i = 0; i < 26; i++) { ff += (cand[i] > 0); } if (ff == 1) { f = 1; } } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, k; cin >> n >> k; int sum = 0; sum += 2 * n / k; if (2 * n % k != 0) sum++; sum += 5 * n / k; if (5 * n % k != 0) sum++; sum += 8 * n / k; if (8 * n % k != 0) sum++; cout << sum; return 0; } |
// Generated by DDR3 High Performance Controller 11.1 [Altera, IP Toolbench 1.3.0 Build 173]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2012 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module ddr3_int (
local_address,
local_write_req,
local_read_req,
local_burstbegin,
local_wdata,
local_be,
local_size,
global_reset_n,
pll_ref_clk,
soft_reset_n,
local_ready,
local_rdata,
local_rdata_valid,
local_refresh_ack,
local_init_done,
reset_phy_clk_n,
dll_reference_clk,
dqs_delay_ctrl_export,
mem_odt,
mem_cs_n,
mem_cke,
mem_addr,
mem_ba,
mem_ras_n,
mem_cas_n,
mem_we_n,
mem_dm,
mem_reset_n,
phy_clk,
aux_full_rate_clk,
aux_half_rate_clk,
reset_request_n,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqsn);
input [23:0] local_address;
input local_write_req;
input local_read_req;
input local_burstbegin;
input [255:0] local_wdata;
input [31:0] local_be;
input [4:0] local_size;
input global_reset_n;
input pll_ref_clk;
input soft_reset_n;
output local_ready;
output [255:0] local_rdata;
output local_rdata_valid;
output local_refresh_ack;
output local_init_done;
output reset_phy_clk_n;
output dll_reference_clk;
output [5:0] dqs_delay_ctrl_export;
output [0:0] mem_odt;
output [0:0] mem_cs_n;
output [0:0] mem_cke;
output [12:0] mem_addr;
output [2:0] mem_ba;
output mem_ras_n;
output mem_cas_n;
output mem_we_n;
output [7:0] mem_dm;
output mem_reset_n;
output phy_clk;
output aux_full_rate_clk;
output aux_half_rate_clk;
output reset_request_n;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [63:0] mem_dq;
inout [7:0] mem_dqs;
inout [7:0] mem_dqsn;
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email:
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_trace.v
// Title : PC Trace and associated logic.
// Dependencies : lm32_include.v, lm32_functions.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
`include "system_conf.v"
`ifdef CFG_TRACE_ENABLED
module lm32_trace(
// ----- Inputs -------
clk_i,
rst_i,
stb_i,
we_i,
sel_i,
dat_i,
adr_i,
trace_pc,
trace_eid,
trace_eret,
trace_bret,
trace_pc_valid,
trace_exception,
// -- outputs
ack_o,
dat_o);
input clk_i;
input rst_i;
input stb_i;
input we_i;
input [3:0] sel_i;
input [`LM32_WORD_RNG] dat_i;
input [`LM32_WORD_RNG] adr_i;
input [`LM32_PC_RNG] trace_pc;
input [`LM32_EID_RNG] trace_eid;
input trace_eret;
input trace_bret;
input trace_pc_valid;
input trace_exception;
// -- outputs
output ack_o;
output [`LM32_WORD_RNG] dat_o;
reg ovrflw;
function integer clogb2;
input [31:0] value;
begin
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
value = value >> 1;
end
endfunction
// instantiate the trace memory
parameter mem_data_width = `LM32_PC_WIDTH;
parameter mem_addr_width = clogb2(`CFG_TRACE_DEPTH-1);
wire [`LM32_PC_RNG] trace_dat_o;
wire [mem_addr_width-1:0] trace_raddr;
wire [mem_addr_width-1:0] trace_waddr;
reg trace_we;
wire trace_be, trace_last;
wire rw_creg = adr_i[12];
lm32_ram #(.data_width (mem_data_width),
.address_width (mem_addr_width))
trace_mem (.read_clk (clk_i),
.write_clk (clk_i),
.reset (rst_i),
.read_address (adr_i[mem_addr_width+1:2]),
.write_address (trace_waddr),
.enable_read (`TRUE),
.enable_write ((trace_we | trace_be) & trace_pc_valid & !trace_last),
.write_enable (`TRUE),
.write_data (trace_pc),
.read_data (trace_dat_o));
// trigger type & stop type
// trig_type [0] = start capture when bret
// trig_type [1] = start capture when eret
// trig_type [2] = start capture when PC within a range
// trig_type [3] = start when an exception happens (other than breakpoint)
// trig_type [4] = start when a breakpoint exception happens
reg [4:0] trig_type; // at address 0
reg [4:0] stop_type; // at address 16
reg [`LM32_WORD_RNG] trace_len; // at address 4
reg [`LM32_WORD_RNG] pc_low; // at address 8
reg [`LM32_WORD_RNG] pc_high; // at address 12
reg trace_start,trace_stop;
reg ack_o;
reg mem_valid;
reg [`LM32_WORD_RNG] reg_dat_o;
reg started;
reg capturing;
assign dat_o = (rw_creg ? reg_dat_o : trace_dat_o);
initial begin
trig_type <= 0;
stop_type <= 0;
trace_len <= 0;
pc_low <= 0;
pc_high <= 0;
trace_start <= 0;
trace_stop <= 0;
ack_o <= 0;
reg_dat_o <= 0;
mem_valid <= 0;
started <= 0;
capturing <= 0;
end
// the host side control
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE) begin
trig_type <= 0;
trace_stop <= 0;
trace_start <= 0;
pc_low <= 0;
pc_high <= 0;
ack_o <= 0;
end else begin
if (stb_i == `TRUE && ack_o == `FALSE) begin
if (rw_creg) begin // control register access
ack_o <= `TRUE;
if (we_i == `TRUE) begin
case ({adr_i[11:2],2'b0})
// write to trig type
12'd0:
begin
if (sel_i[0]) begin
trig_type[4:0] <= dat_i[4:0];
end
if (sel_i[3]) begin
trace_start <= dat_i[31];
trace_stop <= dat_i[30];
end
end
12'd8:
begin
if (sel_i[3]) pc_low[31:24] <= dat_i[31:24];
if (sel_i[2]) pc_low[23:16] <= dat_i[23:16];
if (sel_i[1]) pc_low[15:8] <= dat_i[15:8];
if (sel_i[0]) pc_low[7:0] <= dat_i[7:0];
end
12'd12:
begin
if (sel_i[3]) pc_high[31:24] <= dat_i[31:24];
if (sel_i[2]) pc_high[23:16] <= dat_i[23:16];
if (sel_i[1]) pc_high[15:8] <= dat_i[15:8];
if (sel_i[0]) pc_high[7:0] <= dat_i[7:0];
end
12'd16:
begin
if (sel_i[0])begin
stop_type[4:0] <= dat_i[4:0];
end
end
endcase
end else begin // read control registers
case ({adr_i[11:2],2'b0})
// read the trig type
12'd0:
reg_dat_o <= {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type};
12'd4:
reg_dat_o <= trace_len;
12'd8:
reg_dat_o <= pc_low;
12'd12:
reg_dat_o <= pc_high;
default:
reg_dat_o <= {27'b0,stop_type};
endcase
end // else: !if(we_i == `TRUE)
end else // read / write memory
if (we_i == `FALSE) begin
ack_o <= `TRUE;
end else
ack_o <= `FALSE;
// not allowed to write to trace memory
end else begin // if (stb_i == `TRUE)
trace_start <= `FALSE;
trace_stop <= `FALSE;
ack_o <= `FALSE;
end // else: !if(stb_i == `TRUE)
end // else: !if(rst_i == `TRUE)
end
wire [`LM32_WORD_RNG] trace_pc_tmp = {trace_pc,2'b0};
// trace state machine
reg [2:0] tstate;
wire pc_in_range = {trace_pc,2'b0} >= pc_low &&
{trace_pc,2'b0} <= pc_high;
assign trace_waddr = trace_len[mem_addr_width-1:0];
wire trace_begin = ((trig_type[0] & trace_bret) ||
(trig_type[1] & trace_eret) ||
(trig_type[2] & pc_in_range & trace_pc_valid) ||
(trig_type[3] & trace_exception & (trace_eid != `LM32_EID_BREAKPOINT)) ||
(trig_type[4] & trace_exception & (trace_eid == `LM32_EID_BREAKPOINT))
);
wire trace_end = (trace_stop ||
(stop_type[0] & trace_bret) ||
(stop_type[1] & trace_eret) ||
(stop_type[2] & !pc_in_range & trace_pc_valid) ||
(stop_type[3] & trace_exception & (trace_eid != `LM32_EID_BREAKPOINT)) ||
(stop_type[4] & trace_exception & (trace_eid == `LM32_EID_BREAKPOINT))
);
assign trace_be = (trace_begin & (tstate == 3'd1));
assign trace_last = (trace_stop & (tstate == 3'd2));
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE) begin
tstate <= 0;
trace_we <= 0;
trace_len <= 0;
ovrflw <= `FALSE;
mem_valid <= 0;
started <= 0;
capturing <= 0;
end else begin
case (tstate)
3'd0:
// start capture
if (trace_start) begin
tstate <= 3'd1;
mem_valid <= 0;
started <= 1;
end
3'd1:
begin
// wait for trigger
if (trace_begin) begin
capturing <= 1;
tstate <= 3'd2;
trace_we <= `TRUE;
trace_len <= 0;
ovrflw <= `FALSE;
end
end // case: 3'd1
3'd2:
begin
if (trace_pc_valid) begin
if (trace_len[mem_addr_width])
trace_len <= 0;
else
trace_len <= trace_len + 1;
end
if (!ovrflw) ovrflw <= trace_len[mem_addr_width];
// wait for stop condition
if (trace_end) begin
tstate <= 3'd0;
trace_we <= 0;
mem_valid <= 1;
started <= 0;
capturing <= 0;
end
end // case: 3'd2
endcase
end // else: !if(rst_i == `TRUE)
end
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; long long query(long long t, long long i, long long j, long long k) { cout << t << << i << << j << << k << << n ; cout.flush(); long long res; cin >> res; return res; } void solve() { long long n; cin >> n; long long t1 = 1; long long oo = 5e18; vector<pair<long long, long long>> area(n + 1, {-oo, -1}); for (long long i = 1; i <= n; ++i) area[i].second = i; long long t2 = 2; for (long long i = 3; i <= n; ++i) { long long q2 = query(2, t1, t2, i); t2 = (q2 > 0 ? t2 : i); } long long mid = 3, max_s = 0; for (long long i = 2; i <= n; ++i) { if (i == t2) continue; long long q1 = query(1, t1, t2, i); area[i].first = q1; if (q1 > max_s) { max_s = q1; mid = i; } } area[mid].first = 0; for (long long i = 2; i <= n; ++i) { if (i == t2 || i == mid) continue; long long q2 = query(2, t1, mid, i); if (q2 > 0) area[i].first = oo - area[i].first; if (q2 < 0) area[i].first = -oo + area[i].first; } sort(area.begin() + 1, area.end()); cout << 0 ; for (long long i = 1; i <= n; ++i) cout << area[i].second << (i == n ? n : ); } int main() { solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, m, i, j, k, mod, dp[605][605], rd[605], xs[605][605], ans = 1; vector<long long> ts, bi[605], nrd, ncd; long long gcd(long long x, long long y) { if (y == 0) return x; return gcd(y, x % y); } long long lcm(long long x, long long y) { return x / gcd(x, y) * y; } void dfs(int x) { int i; rd[x] = -1; ts.push_back(x); for (i = 0; i < bi[x].size(); i++) { rd[bi[x][i]]--; if (!rd[bi[x][i]]) { dfs(bi[x][i]); } } } int main() { ios_base::sync_with_stdio(0); cin >> n >> m >> mod; for (i = 1; i <= m; i++) { int x, y; cin >> x >> y; bi[x].push_back(y); rd[y]++; } for (i = 1; i <= n; i++) { if (rd[i] == 0) nrd.push_back(i); if (bi[i].size() == 0) ncd.push_back(i); } for (i = 0; i < nrd.size(); i++) { dfs(nrd[i]); dp[nrd[i]][nrd[i]] = 1; } for (i = 0; i < ts.size(); i++) { for (j = 0; j < ts.size(); j++) { for (k = 0; k < bi[ts[j]].size(); k++) { dp[ts[i]][bi[ts[j]][k]] += dp[ts[i]][ts[j]]; dp[ts[i]][bi[ts[j]][k]] %= mod; } } } for (i = 0; i < nrd.size(); i++) { for (j = 0; j < ncd.size(); j++) { xs[i][j] = dp[nrd[i]][ncd[j]]; } } long long cnt = 0; for (i = 0; i < ncd.size(); i++) { for (j = i + 1; j < nrd.size(); j++) { while (xs[j][i]) { long long t = -xs[i][i] / xs[j][i]; for (k = i; k < nrd.size(); k++) { xs[i][k] += t * xs[j][k]; xs[i][k] %= mod; xs[i][k] += mod; xs[i][k] %= mod; } for (k = i; k < nrd.size(); k++) { swap(xs[i][k], xs[j][k]); } cnt++; } } } if (cnt & 1) ans = mod - 1; for (i = 0; i < nrd.size(); i++) { ans *= xs[i][i]; ans %= mod; } cout << ans; return 0; } |
/*
* Copyright 2012, Homer Hsing <>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
module test_fsm;
// Inputs
reg clk;
reg reset;
reg [25:0] rom_q;
// Outputs
wire [8:0] rom_addr;
wire [5:0] ram_a_addr;
wire [5:0] ram_b_addr;
wire ram_b_w;
wire [10:0] pe;
wire done;
// Instantiate the Unit Under Test (UUT)
FSM uut (
.clk(clk),
.reset(reset),
.rom_addr(rom_addr),
.rom_q(rom_q),
.ram_a_addr(ram_a_addr),
.ram_b_addr(ram_b_addr),
.ram_b_w(ram_b_w),
.pe(pe),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#(`P/2); reset = 1; #(`P); reset = 0;
@(posedge done);
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
/* rom code format
* wire [5:0] dest, src1, src2, times; wire [1:0] op;
* assign {dest, src1, op, times, src2} = rom_q;
*/
parameter ADD=2'd0, SUB=2'd1, CUBIC=2'd2, MULT=2'd3;
always @ (posedge clk)
case(rom_addr)
0: rom_q <= {6'd10, 6'd11, ADD, 6'd1, 6'd12};
1: rom_q <= {6'd20, 6'd21, SUB, 6'd1, 6'd22};
2: rom_q <= {6'd30, 6'd31, CUBIC, 6'd5, 6'd32};
3: rom_q <= {6'd40, 6'd41, MULT, 6'd33, 6'd42};
default: rom_q <= 0;
endcase
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module SOC_NIOS_II_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
#include <bits/stdc++.h> using namespace std; template <typename T> inline T Abs(const T& value) { return value < 0 ? -value : value; } template <typename T> inline T Sqr(const T& value) { return value * value; } const int maxn = 110; int a[maxn][maxn]; int main() { int k; int n = 0; cin >> k; while (k > 0) { int d = 3; while (((d + 1) * d * (d - 1)) / 6 <= k) { ++d; } for (int i = n; i < n + d; ++i) for (int j = i + 1; j < n + d; ++j) { a[i][j] = 1; a[j][i] = 1; } k -= ((d) * (d - 2) * (d - 1)) / 6; int how = 2; n += d; while (true) { how = 1; while (((how + 1) * how) / 2 <= k) ++how; if (how >= 2) { k -= (how * (how - 1)) / 2; for (int i = n - d; i < n && how > 0; ++i, --how) { a[n][i] = 1; a[i][n] = 1; } ++n; } else break; } } cout << n << endl; for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) cout << a[i][j]; cout << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int v, id, tag; } a[100010]; int cmp1(node x, node y) { return x.v < y.v; } int cmp2(node x, node y) { return x.id < y.id; } int ccount[100010]; int main() { int n, tt; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i].v), a[i].id = i; sort(a + 1, a + n + 1, cmp1); a[1].tag = tt = 1; ccount[tt] = 1; for (int i = 2; i <= n; i++) { if (a[i].v != a[i - 1].v) tt++; a[i].tag = tt; ccount[tt]++; } sort(a + 1, a + n + 1, cmp2); int nowh = 1, maxh = 0, block = 0; for (int i = 1; i <= n; i++) { ccount[a[i].tag]--; maxh = max(maxh, a[i].tag); while (!ccount[nowh]) nowh++; if (nowh >= maxh) block++; } printf( %d n , block); } |
#include <bits/stdc++.h> using namespace std; int ar[2111111], br[2111111], cr[2111111], dr[2111111]; int main() { cin.sync_with_stdio(false); int n, i, j, x, y, pos, m; cin >> n; for (i = 1; i <= n; i++) { cin >> ar[i]; if (ar[i] == 0) pos = i; } for (i = n + 1; i < n + n; i++) ar[i] = ar[i - n]; for (j = 1, i = pos + 1; i <= pos + n - 1; i++, j++) cr[j] = ar[i]; m = j - 1; for (i = m + 1; i <= m + m; i++) cr[i] = cr[i - m]; for (i = 1; i <= n; i++) { cin >> br[i]; if (br[i] == 0) pos = i; } for (i = n + 1; i < n + n; i++) br[i] = br[i - n]; for (j = 1, i = pos + 1; i <= pos + n - 1; i++, j++) dr[j] = br[i]; for (i = 1; i <= m + m; i++) if (cr[i] == dr[1]) { pos = i; break; } bool cond = true; for (j = 1, i = pos; i <= pos + m - 1 && cond; i++, j++) if (cr[i] != dr[j]) cond = false; if (cond) puts( YES ); else puts( NO ); return 0; } |
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:user:debug_counter:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_debug_counter_0_0 (
CLK,
led
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire CLK;
output wire [3 : 0] led;
debug_counter inst (
.CLK(CLK),
.led(led)
);
endmodule
|
module branch_wait
(/*AUTOARG*/
// Outputs
pending_branches_arry,
// Inputs
clk, rst, alu_valid, alu_branch, alu_wfid, f_salu_branch_en,
f_salu_branch_wfid
);
input clk, rst;
// Issued alu info
input alu_valid, alu_branch;
input [`WF_ID_LENGTH-1:0] alu_wfid;
// Salu signals with outcome of branch
input f_salu_branch_en;
input [`WF_ID_LENGTH-1:0] f_salu_branch_wfid;
// Output - list of pending branches
output [`WF_PER_CU-1:0] pending_branches_arry;
/**
* Branch wait is a reg that marks all wf with a pending branch.
* Pending branches start when a branch instruction is issued
* and end when salu signals the outcome of the branch
**/
wire alu_branch_valid;
wire [`WF_PER_CU-1:0] alu_branch_decoded,
salu_branch_decoded;
wire [`WF_PER_CU-1:0] pending_branch, next_pending_branch;
assign pending_branches_arry = pending_branch;
// Decoder for the issued branch
decoder_6b_40b_en alu_brach_decoder
(
.addr_in(alu_wfid),
.out(alu_branch_decoded),
.en(alu_branch_valid)
);
// Decoder for the finished branch by fetch
decoder_6b_40b_en issue_Value_decoder
(
.addr_in(f_salu_branch_wfid),
.out(salu_branch_decoded),
.en(f_salu_branch_en)
);
dff pending_branch_ff[`WF_PER_CU-1:0]
(
.q(pending_branch),
.d(next_pending_branch),
.clk(clk),
.rst(rst)
);
assign alu_branch_valid = alu_valid && alu_branch;
assign next_pending_branch
= ( pending_branch | (alu_branch_decoded) ) &
~(salu_branch_decoded);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYMETAL6S6S_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLYMETAL6S6S_FUNCTIONAL_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__dlymetal6s6s (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYMETAL6S6S_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int main() { int k25 = 0, k50 = 0, n; cin >> n; bool f = 1; for (int i = 0; i < n; i++) { int q; cin >> q; if (q == 25) k25++; else if (q == 50) { if (k25) { k25--; k50++; } else f = 0; } else { if (k50 && k25) { k25--; k50--; } else if (k25 >= 3) k25 -= 3; else f = 0; } } if (f) cout << YES ; else cout << NO ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__SDFRTP_BEHAVIORAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_r_no_pg/sky130_fd_sc_hs__u_df_p_r_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfrtp (
VPWR ,
VGND ,
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_r_no_pg u_df_p_r_no_pg0 (buf_Q , mux_out, CLK_delayed, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 100; int h[N], nex[N << 1], to[N << 1], tot, dis[N]; void add(int x, int y) { to[++tot] = y; nex[tot] = h[x]; h[x] = tot; } int fa[N][30], dep[N], lg[N]; void dfs(int u, int fath, int d) { dis[u] = d; fa[u][0] = fath; dep[u] = dep[fath] + 1; for (int i = 1; i <= lg[dep[u]]; i++) fa[u][i] = fa[fa[u][i - 1]][i - 1]; for (int j = h[u]; j; j = nex[j]) if (to[j] != fath) dfs(to[j], u, d + 1); } int lca(int x, int y) { if (dep[x] < dep[y]) swap(x, y); while (dep[x] > dep[y]) x = fa[x][lg[dep[x] - dep[y]] - 1]; if (x == y) return x; for (int i = lg[dep[x] - 1]; i >= 0; i--) if (fa[x][i] != fa[y][i]) x = fa[x][i], y = fa[y][i]; return fa[x][0]; } int main() { int n; scanf( %d , &n); for (int i = 1; i < n; i++) { int u, v; scanf( %d%d , &u, &v); add(u, v); add(v, u); } for (int i = 1; i <= n; i++) lg[i] = lg[i - 1] + (1 << lg[i - 1] == i); dfs(1, 0, 0); int q; scanf( %d , &q); for (int i = 1; i <= q; i++) { int x, y, a, b, k; scanf( %d%d%d%d%d , &x, &y, &a, &b, &k); int lcab = lca(a, b); int d1 = dis[a] + dis[b] - 2 * dis[lcab]; if (k >= d1 && (k % 2) == (d1 % 2)) { printf( Yes n ); continue; } int lcax = lca(a, x); int lcay = lca(a, y); int lcby = lca(b, y); int lcbx = lca(b, x); int d2 = dis[x] + dis[a] - 2 * dis[lcax]; int d3 = dis[a] + dis[y] - 2 * dis[lcay]; int d4 = dis[b] + dis[y] - 2 * dis[lcby]; int d5 = dis[b] + dis[x] - 2 * dis[lcbx]; if (k >= (d2 + 1 + d4) && (k % 2) == ((d2 + 1 + d4) % 2)) { printf( Yes n ); } else if (k >= (d3 + 1 + d5) && (k % 2) == ((d3 + 1 + d5) % 2)) { printf( Yes n ); } else { printf( No n ); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 200005, mod = 1e9 + 7; int n, head[N], nxt[N << 1], to[N << 1], num = 0, dfn[N], DFN = 0, a[N], dep[N]; inline void link(int x, int y) { nxt[++num] = head[x]; to[num] = y; head[x] = num; } namespace tr { int fa[N], top[N], sz[N], son[N]; inline void dfs1(int x) { sz[x] = 1; dfn[x] = ++DFN; for (int i = head[x]; i; i = nxt[i]) { int u = to[i]; if (sz[u]) continue; fa[u] = x; dep[u] = dep[x] + 1; dfs1(u); sz[x] += sz[u]; if (sz[u] > sz[son[x]]) son[x] = u; } } inline void dfs2(int x, int tp) { top[x] = tp; if (son[x]) dfs2(son[x], tp); for (int i = head[x]; i; i = nxt[i]) if (to[i] != fa[x] && to[i] != son[x]) dfs2(to[i], to[i]); } inline int lca(int x, int y) { while (top[x] != top[y]) { if (dep[top[x]] < dep[top[y]]) swap(x, y); x = fa[top[x]]; } return dep[x] < dep[y] ? x : y; } void main() { dep[1] = 1; dfs1(1); dfs2(1, 1); } } // namespace tr int prime[N], sp = 0, mu[N], phi[N], b[N], m = 0, id[N], g[N]; bool vis[N]; void priwork() { phi[1] = 1; mu[1] = 1; for (int to, i = 2; i <= n; i++) { if (!vis[i]) prime[++sp] = i, mu[i] = -1, phi[i] = i - 1; for (int j = 1; j <= sp && i * prime[j] <= n; j++) { vis[to = i * prime[j]] = 1; if (i % prime[j]) mu[to] = -mu[i], phi[to] = phi[i] * (prime[j] - 1); else { phi[to] = phi[i] * prime[j]; break; } } } tr::main(); } inline bool comp(int i, int j) { return dfn[i] < dfn[j]; } int st[N], top, w[N], f[N], inv[N], ST[N], cnt = 0; inline int solve() { int sum = 0, x, lca, ret = 0, y = 0; top = 0; for (int i = 1; i <= m; i++) sum = (sum + phi[a[b[i]]]) % mod, w[b[i]] = phi[a[b[i]]]; sort(b + 1, b + m + 1, comp); st[++top] = b[1]; w[b[1]] = phi[a[b[1]]]; ST[++cnt] = b[1]; for (int i = 2; i <= m; i++) { x = b[i]; y = 0; lca = tr::lca(x, st[top]); while (dep[lca] < dep[st[top]]) { if (y) ret = (ret + 1ll * (dep[y] - dep[st[top]]) * w[y] % mod * (sum - w[y] + mod) % mod) % mod; if (y) w[st[top]] = (w[st[top]] + w[y]) % mod; y = st[top--]; } if (st[top] != lca) st[++top] = lca, ST[++cnt] = lca; if (y) ret = (ret + 1ll * (dep[y] - dep[st[top]]) * w[y] % mod * (sum - w[y] + mod) % mod) % mod; if (y) w[st[top]] = (w[st[top]] + w[y]) % mod; if (st[top] != x) st[++top] = x, ST[++cnt] = x; } while (top > 1) { ret = (ret + 1ll * (dep[st[top]] - dep[st[top - 1]]) * w[st[top]] % mod * (sum - w[st[top]] + mod) % mod) % mod; w[st[top - 1]] = (w[st[top]] + w[st[top - 1]]) % mod; top--; } while (cnt) w[ST[cnt]] = 0, cnt--; return (ret << 1) % mod; } long long qm(long long x, long long k) { long long sum = 1; while (k) { if (k & 1) sum = sum * x % mod; x = x * x % mod; k >>= 1; } return sum; } void work() { int x, y; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]), id[a[i]] = i; for (int i = 1; i < n; i++) { scanf( %d%d , &x, &y); link(x, y); link(y, x); } priwork(); for (int i = 1; i <= n; i++) { m = 0; for (int j = i; j <= n; j += i) b[++m] = id[j]; g[i] = solve(); } for (int i = 1; i <= n; i++) for (int j = i; j <= n; j += i) f[i] = (f[i] + mu[j / i] * g[j]) % mod; int ans = 0; for (int i = 1; i <= n; i++) inv[i] = qm(i, mod - 2); for (int i = 1; i <= n; i++) ans = (ans + 1ll * i * inv[phi[i]] % mod * f[i] % mod) % mod; cout << ans * qm(1ll * n * (n - 1) % mod, mod - 2) % mod << endl; } int main() { work(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(NULL); cout.tie(NULL); int n, k; cin >> n >> k; int i = 1; for (i = k - 1; i > 0; i--) { if ((n % i) == 0) break; } if (i == 0) i = 1; int x = (n / i) * k; for (; x % k != i; x++) { } cout << x; } |
#include <bits/stdc++.h> using namespace std; int main() { int t, fl; cin >> t; while (t--) { fl = 1; int a, b, c, d, x, y, x1, y1, x2, y2; cin >> a >> b >> c >> d >> x >> y >> x1 >> y1 >> x2 >> y2; int p = x - a + b, q = y - c + d; if ((p >= x1 && p <= x2) && (x1 < x2 || a + b == 0)) ; else fl = 0; if ((q >= y1 && q <= y2) && (y1 < y2 || c + d == 0)) ; else fl = 0; if (fl) cout << YES << endl; else cout << NO << endl; } } |
#include <bits/stdc++.h> using namespace std; const long long MOD = (long long)1e9 + 7; long long dp[12][65][1024], dp0[12][65][1024]; void upd(long long &a, long long b) { a = (a + b); } int get_next(int a, int b) { if ((a & (1 << b)) == 0) { a += (1 << b); } else { a -= (1 << b); } return a; } void precalc() { for (int i = 2; i <= 10; ++i) { dp[i][0][0] = 1; dp0[i][0][0] = 1; } for (int osn = 2; osn <= 10; ++osn) { for (int len = 0; len <= 62; ++len) { for (int mask = 0; mask < (1 << osn); ++mask) { for (int next = 0; next < osn; ++next) { upd(dp[osn][len + 1][get_next(mask, next)], dp[osn][len][mask]); if (next == 0 && len == 0) { continue; } upd(dp0[osn][len + 1][get_next(mask, next)], dp0[osn][len][mask]); } } } } } int digits[1000]; int cur[10]; int build(int x) { int ans = 0; for (int i = x - 1; i >= 0; --i) { ans = ans * 2 + cur[i] % 2; } return ans; } long long f(long long n, long long x) { int cnt = 0; if (n == 0) { return 0; } while (n > 0) { ++cnt; digits[cnt] = n % x; n /= x; } reverse(digits + 1, digits + cnt + 1); memset(cur, 0, sizeof cur); long long answer = 0; for (int i = 1; i <= cnt; ++i) { for (int new_digit = 0; new_digit < x; ++new_digit) { if (new_digit == 0 && i == 1) continue; if (new_digit < digits[i]) { ++cur[new_digit]; int cur_mask = build(x); answer = answer + dp[x][cnt - i][cur_mask]; --cur[new_digit]; } else { ++cur[new_digit]; break; } } } int cur_mask = build(x); if (cur_mask == 0) ++answer; for (int i = 1; i < cnt; ++i) { answer += dp0[x][i][0]; } return answer; } void solve(long long b, long long l, long long r) { long long ans = f(r, b) - f(l - 1, b); cout << ans << endl; } int main() { precalc(); ios_base::sync_with_stdio(0); int test; cin >> test; for (int tst = 1; tst <= test; ++tst) { long long b, l, r; cin >> b >> l >> r; solve(b, l, r); } return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 21:40:37 09/26/2015
// Design Name: Multiplication
// Module Name: C:/Users/adam/Documents/GitHub/Digital Systems/MultiplicationUnit/MultiplicationTest.v
// Project Name: DataUnit
////////////////////////////////////////////////////////////////////////////////
module MultiplicationTest;
reg Clock, Reset, Start;
reg [3:0] Multiplicant;
reg [3:0] Multiplier;
wire [7:0] Product;
Multiplication uut(Clock, Reset, Start, Multiplicant, Multiplier, Product);
always #5 Clock = ~Clock;
initial begin
Clock = 0; Reset = 0; Start = 0; Multiplicant = 13; Multiplier = 13; #10;
Reset = 1; #10;
Start = 1; #150;
Multiplicant = 9; Multiplier = 11; Reset = 0; #10;
Reset = 1; #10;
Start = 1; #150;
Multiplicant = 2; Multiplier = 2; Reset = 0; #10;
Reset = 1; #10;
Start = 1; #150;
Multiplicant = 5; Multiplier = 8; Reset = 0; #10;
Reset = 1; #10;
Start = 1; #150;
Multiplicant = 3; Multiplier = 14; Reset = 0; #10;
Reset = 1; #10;
Start = 1; #150;
$stop;
end
endmodule
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module memtest #(
parameter csr_addr = 4'h0,
parameter fml_depth = 26
) (
input sys_clk,
input sys_rst,
/* Configuration interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do,
/* Framebuffer FML 4x64 interface */
output [fml_depth-1:0] fml_adr,
output reg fml_stb,
output reg fml_we,
input fml_ack,
input [63:0] fml_di,
output [7:0] fml_sel,
output [63:0] fml_do
);
wire rand_ce;
wire [63:0] rand;
wire csr_selected = csr_a[13:10] == csr_addr;
wire load_nbursts = csr_selected & (csr_a[2:0] == 3'd0) & csr_we;
wire load_address = csr_selected & (csr_a[2:0] == 3'd2) & csr_we;
memtest_prng64 prng_data(
.clk(sys_clk),
.rst(load_nbursts),
.ce(rand_ce),
.rand(rand)
);
wire [19:0] fml_adr_bot;
memtest_prng20 prng_address(
.clk(sys_clk),
.rst(load_address),
.ce(fml_ack),
.rand(fml_adr_bot)
);
assign fml_sel = 8'hff;
assign fml_do = rand;
reg nomatch;
always @(posedge sys_clk)
nomatch <= fml_di != rand;
reg [31:0] remaining_bursts;
always @(posedge sys_clk) begin
if(sys_rst) begin
remaining_bursts <= 32'd0;
fml_stb <= 1'b0;
end else begin
if(load_nbursts) begin
remaining_bursts <= csr_di;
fml_stb <= 1'b1;
end else begin
if(fml_ack) begin
remaining_bursts <= remaining_bursts - 32'd1;
if(remaining_bursts == 32'd1)
fml_stb <= 1'b0;
end
end
end
end
reg [1:0] burst_counter;
always @(posedge sys_clk) begin
if(sys_rst)
burst_counter <= 2'd0;
else begin
if(fml_ack)
burst_counter <= 2'd3;
else if(|burst_counter)
burst_counter <= burst_counter - 2'd1;
end
end
assign rand_ce = |burst_counter | fml_ack;
reg rand_ce_r;
reg [31:0] errcount;
always @(posedge sys_clk) begin
rand_ce_r <= rand_ce;
if(sys_rst)
errcount <= 32'd0;
else if(csr_selected & (csr_a[2:0] == 3'd1) & csr_we)
errcount <= 32'd0;
else if(rand_ce_r & nomatch)
errcount <= errcount + 32'd1;
end
reg [fml_depth-1-25:0] fml_adr_top;
always @(posedge sys_clk) begin
if(sys_rst)
fml_adr_top <= 0;
else if(load_address)
fml_adr_top <= csr_di[fml_depth-1:25];
end
assign fml_adr = {fml_adr_top, fml_adr_bot, 5'd0};
always @(posedge sys_clk) begin
if(csr_selected & (csr_a[2:0] == 3'd3) & csr_we)
fml_we <= csr_di[0];
end
always @(posedge sys_clk) begin
if(sys_rst)
csr_do <= 32'd0;
else begin
csr_do <= 32'd0;
if(csr_selected) begin
case(csr_a[2:0])
3'd0: csr_do <= remaining_bursts;
3'd1: csr_do <= errcount;
3'd2: csr_do <= fml_adr;
3'd3: csr_do <= fml_we;
endcase
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 2000000000; const int MAX = 10000000; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; while (cin >> n) { map<string, int> m; for (int i = 0; i < n; i++) { string s; cin >> s; m[s]++; } int mx = 0; for (map<string, int>::iterator it = m.begin(); it != m.end(); it++) mx = max(mx, it->second); cout << mx << n ; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_MUX_2TO1_N_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_MUX_2TO1_N_BLACKBOX_V
/**
* udp_mux_2to1_N: Two to one multiplexer with inverting output
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_mux_2to1_N (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_MUX_2TO1_N_BLACKBOX_V
|
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks
`define WIDTH 2
module top (
input OE1,
input OE2,
input [`WIDTH-1:0] A1,
input [`WIDTH-1:0] A2,
output [`WIDTH-1:0] Y1,
output [`WIDTH-1:0] Y2,
output [`WIDTH-1:0] Y3,
output [`WIDTH**2-1:0] W);
assign W[A1] = (OE2) ? A2[0] : 1'bz;
assign W[A2] = (OE1) ? A2[1] : 1'bz;
// have 2 different 'chips' drive the PAD to act like a bi-directional bus
wire [`WIDTH-1:0] PAD;
io_ring io_ring1 (.OE(OE1), .A(A1), .O(Y1), .PAD(PAD));
io_ring io_ring2 (.OE(OE2), .A(A2), .O(Y2), .PAD(PAD));
assign Y3 = PAD;
pullup p1(PAD);
// pulldown p1(PAD);
wire [5:0] fill = { 4'b0, A1 };
endmodule
module io_ring (input OE, input [`WIDTH-1:0] A, output [`WIDTH-1:0] O, inout [`WIDTH-1:0] PAD);
io io[`WIDTH-1:0] (.OE(OE), .I(A), .O(O), .PAD(PAD));
endmodule
module io (input OE, input I, output O, inout PAD);
assign O = PAD;
assign PAD = OE ? I : 1'bz;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n, m; cin >> n >> m; char **a = new char *[n]; for (int i = 0; i < n; i++) { a[i] = new char[m + 1]; cin >> a[i]; } for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) for (int k = 0; k < n; k++) for (int l = 0; l < m; l++) { if (i == k && j == l) { continue; } if (a[i][j] == W || a[k][l] == W ) { continue; } bool found1 = true; for (int i1 = j; i1 <= l; i1++) { if (a[i][i1] == W ) { found1 = false; break; } } for (int i1 = i; i1 <= k; i1++) { if (a[i1][l] == W ) { found1 = false; break; } } if (found1) { continue; } found1 = true; for (int i1 = i; i1 <= k; i1++) { if (a[i1][j] == W ) { found1 = false; break; } } for (int i1 = j; i1 <= l; i1++) { if (a[k][i1] == W ) { found1 = false; break; } } if (found1) { continue; } else { cout << NO ; return 0; } } cout << YES ; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S15KAPWR_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLYBUF4S15KAPWR_FUNCTIONAL_PP_V
/**
* dlybuf4s15kapwr: Delay Buffer 4-stage 0.15um length inner stage
* gates on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlybuf4s15kapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, KAPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S15KAPWR_FUNCTIONAL_PP_V |
//======================================================================
//
// Design Name: PRESENT Block Cipher
// Module Name: PRESENT_ENCRYPT_PBOX
// Language: Verilog-2001
//
// Description: Permutation Layer (p-Layer or p-box) of PRESENT Encryption
//
// Dependencies: none
//
// Designer: Saied H. Khayat
// Date: 3/2011
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// condition is met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`timescale 1ns/1ps
module PRESENT_ENCRYPT_PBOX(
output [63:0] odat,
input [63:0] idat
);
assign odat[0 ] = idat[0 ];
assign odat[16] = idat[1 ];
assign odat[32] = idat[2 ];
assign odat[48] = idat[3 ];
assign odat[1 ] = idat[4 ];
assign odat[17] = idat[5 ];
assign odat[33] = idat[6 ];
assign odat[49] = idat[7 ];
assign odat[2 ] = idat[8 ];
assign odat[18] = idat[9 ];
assign odat[34] = idat[10];
assign odat[50] = idat[11];
assign odat[3 ] = idat[12];
assign odat[19] = idat[13];
assign odat[35] = idat[14];
assign odat[51] = idat[15];
assign odat[4 ] = idat[16];
assign odat[20] = idat[17];
assign odat[36] = idat[18];
assign odat[52] = idat[19];
assign odat[5 ] = idat[20];
assign odat[21] = idat[21];
assign odat[37] = idat[22];
assign odat[53] = idat[23];
assign odat[6 ] = idat[24];
assign odat[22] = idat[25];
assign odat[38] = idat[26];
assign odat[54] = idat[27];
assign odat[7 ] = idat[28];
assign odat[23] = idat[29];
assign odat[39] = idat[30];
assign odat[55] = idat[31];
assign odat[8 ] = idat[32];
assign odat[24] = idat[33];
assign odat[40] = idat[34];
assign odat[56] = idat[35];
assign odat[9 ] = idat[36];
assign odat[25] = idat[37];
assign odat[41] = idat[38];
assign odat[57] = idat[39];
assign odat[10] = idat[40];
assign odat[26] = idat[41];
assign odat[42] = idat[42];
assign odat[58] = idat[43];
assign odat[11] = idat[44];
assign odat[27] = idat[45];
assign odat[43] = idat[46];
assign odat[59] = idat[47];
assign odat[12] = idat[48];
assign odat[28] = idat[49];
assign odat[44] = idat[50];
assign odat[60] = idat[51];
assign odat[13] = idat[52];
assign odat[29] = idat[53];
assign odat[45] = idat[54];
assign odat[61] = idat[55];
assign odat[14] = idat[56];
assign odat[30] = idat[57];
assign odat[46] = idat[58];
assign odat[62] = idat[59];
assign odat[15] = idat[60];
assign odat[31] = idat[61];
assign odat[47] = idat[62];
assign odat[63] = idat[63];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_P_TB_V
`define SKY130_FD_SC_LP__UDP_DFF_P_TB_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dff_p.v"
module top();
// Inputs are registered
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
#20 D = 1'b0;
#40 D = 1'b1;
#60 D = 1'b0;
#80 D = 1'b1;
#100 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__udp_dff$P dut (.D(D), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_P_TB_V
|
#include <bits/stdc++.h> using namespace std; long long n; int main() { int T; scanf( %d , &T); while (T--) { scanf( %I64d , &n); for (long long i = n;; i += i) if (i * (n + 1) % (4 * n) == 0) { printf( %I64d n , i + 1); break; } } return 0; } |
`default_nettype none
module SysPLL(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire sdr_clk,
// interface 'outclk1'
output wire sys_clk,
// interface 'outclk2'
output wire vga_clk,
output wire pit_clk,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(4),
.output_clock_frequency0("50.000000 MHz"),
.phase_shift0("-3864 ps"),
.duty_cycle0(50),
.output_clock_frequency1("50.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("25.000000 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("1.193058 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({pit_clk, vga_clk, sys_clk, sdr_clk}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
/*888888888 .d88888b. 8888888b.
888 d88P" "Y88b 888 Y88b
888 888 888 888 888
888 888 888 888 d88P
888 888 888 8888888P"
888 888 888 888
888 Y88b. .d88P 888
888 "Y88888P" 8*/
`include "timescale.v"
module top_test_bench;
/*8 8888888b. .d8888b.
888 o 888 888 888 Y88b 888 d88P Y88b
888 d8b 888 888 888 888 888 Y88b.
888 d888b 888 888 888 d88P "Y888b.
888d88888b888 888 8888888P" 888 "Y88b.
88888P Y88888 888 888 T88b 888 "888
8888P Y8888 888 888 T88b 888 Y88b d88P
888P Y888 888 T88b "Y8888*/
integer i_for;
wire dout;
reg clk;
reg nrst;
reg we;
reg [31:0] din;
reg [7:0] cnt_data;
/*8b d888 .d88888b. 8888888b. 888 888 888
8888b d8888 d88P" "Y88b 888 "Y88b 888 888 888 888
88888b.d88888 888 888 888 888 888 888 888 888
888Y88888P888 888 888 888 888 888 888 888
888 Y888P 888 888 888 888 888 888 888 888 888
888 Y8P 888 888 888 888 888 888 888 888 888
888 " 888 Y88b. .d88P 888 .d88P Y88b. .d88P 888 888
888 888 "Y88888P" 8888888P" "Y88888P" 88888888 88888888*/
fifo_spi fifo_spi_t (
.clk (clk),
.nrst (nrst),
.we (we),
.din (din),
.dout (dout)
);
// Clock generation
always #5 clk = ~clk;
// start and simulation begin
initial begin
$timeformat (-9, 1, " ns", 12);
$display("------ Start TestBench ------");
clk = 0;
nrst = 1;
din = 0;
we = 0;
cnt_data = 0;
din = 0;
repeat(10) @(posedge clk);
nrst = 0;
repeat(10) @(posedge clk);
nrst = 1;
repeat(10) @(posedge clk);
repeat (10) begin
task_send_cnt(254);
repeat(1000) @(posedge clk);
end
end
task task_send_cnt;
input cnt;
integer cnt;
begin
@ (posedge clk or negedge nrst) begin
if (!nrst) begin
cnt_data = 0;
din = 0;
end
else begin
for (i_for=0; i_for<cnt; i_for=i_for+1) begin
// $display("i = %d", i_for);
#1;
din = {4{cnt_data}}; //$random;
we = 1;
cnt_data = cnt_data + 8'b1;
@ (posedge clk);
#1
we = 0;
repeat (250) @(posedge clk);
end
end
end
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1000001; int n, t; int p[MAXN], s[MAXN]; stack<int> st; int main() { scanf( %d n , &n); for (int i = 1; i <= n; ++i) scanf( %d , &p[i]); scanf( %d , &t); for (int i = 1; i <= t; ++i) { int x; scanf( %d , &x); p[x] = -p[x]; } for (int i = n; i >= 1; --i) if (p[i] < 0) st.push(-p[i]); else { if (!st.empty() && st.top() == p[i]) { st.pop(); } else p[i] = -p[i], st.push(-p[i]); } if (st.empty()) { printf( YES n ); for (int i = 1; i <= n; ++i) printf( %d%s , p[i], (i < n) ? : n ); } else printf( NO n ); fclose(stdin); fclose(stdout); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR3_SYMBOL_V
`define SKY130_FD_SC_HS__XNOR3_SYMBOL_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__xnor3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR3_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int maxtop = 1025; const int maxn = 100010; const int mo = 1000000007; int top; int repeat[maxtop + 1]; int rest; int a[maxn + 1]; int n, K; int C[maxn + 1]; int f[2][maxtop + 1], old, now; long long result; void init() { int i; scanf( %d%d , &n, &K); for (i = 1; i <= n; ++i) scanf( %d , &a[i]); sort(a + 1, a + n + 1); } bool lucky(int x) { int t; while (x) { t = x % 10; if ((t != 4) && (t != 7)) return false; x /= 10; } return true; } void calc_repeat() { int i, j; top = rest = 0; i = 1; while (i <= n) { if (lucky(a[i])) { j = i; while ((j + 1 <= n) && (a[j + 1] == a[i])) ++j; repeat[++top] = j - i + 1; i = j + 1; } else { ++rest; ++i; } } } int power(int x, int y) { long long a, b; b = x; a = 1; while (y) { if (y & 1) a = (a * b) % mo; b = (b * b) % mo; y = (y >> 1); } return a; } void calc_C() { int i; long long tmp; C[0] = 1; if (rest == 0) return; C[1] = rest; for (i = 2; i <= rest; ++i) { tmp = C[i - 1]; tmp = (tmp * (rest - i + 1)) % mo; tmp = (tmp * power(i, mo - 2)) % mo; C[i] = tmp; } } void calc_result() { int i, j, k; long long tmp; now = 0; for (i = 1; i <= top; ++i) f[now][i] = 0; f[now][0] = 1; for (i = 1; i <= top; ++i) { old = now; now = 1 - now; f[now][0] = 1; for (j = 1; j <= i; ++j) { if (j > K) break; f[now][j] = 0; if (j < i) f[now][j] += f[old][j]; tmp = f[old][j - 1]; tmp = (tmp * repeat[i]) % mo; f[now][j] = (f[now][j] + tmp) % mo; } } result = 0; for (i = 0; i <= top; ++i) { if (i > K) break; if (K - i > rest) continue; tmp = f[now][i]; tmp = (tmp * C[K - i]) % mo; result += tmp; if (result >= mo) result -= mo; } } void work() { calc_repeat(); calc_C(); calc_result(); } void output() { printf( %d n , result); } int main() { init(); work(); output(); return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> inline T qmin(const T &x, const T &y) { return x < y ? x : y; } template <typename T> inline T qmax(const T &x, const T &y) { return x > y ? x : y; } template <typename T> inline void getmin(T &x, const T &y) { if (y < x) x = y; } template <typename T> inline void getmax(T &x, const T &y) { if (y > x) x = y; } inline void fileio(string s) { freopen((s + .in ).c_str(), r , stdin); freopen((s + .out ).c_str(), w , stdout); } const int inf = (int)1e9 + 7; const long long linf = (long long)1e17 + 7; const int N = 1e5 + 7, Node = N << 2; int to[Node][10]; long long val[Node][10]; int n, q, a[N]; inline void merge(int u) { for (int i = 0; i < (10); ++i) val[u][i] = 0; for (int i = 0; i < (10); ++i) { val[u][to[((u) << 1)][i]] += val[((u) << 1)][i]; val[u][to[((u) << 1 ^ 1)][i]] += val[((u) << 1 ^ 1)][i]; } } inline void psd(int u) { for (int i = 0; i < (10); ++i) { to[((u) << 1)][i] = to[u][to[((u) << 1)][i]]; to[((u) << 1 ^ 1)][i] = to[u][to[((u) << 1 ^ 1)][i]]; } for (int i = 0; i < (10); ++i) to[u][i] = i; } inline void init(int u, int l, int r) { for (int i = 0; i < (10); ++i) to[u][i] = i; if (l == r) { for (int v = a[l], w = 1; v; v /= 10, w *= 10) val[u][v % 10] += w; } else { int mid = l + r >> 1; init(((u) << 1), l, mid); init(((u) << 1 ^ 1), mid + 1, r); merge(u); } } inline void change(int u, int l, int r, int l1, int r1, int x, int y) { if (l1 <= l && r <= r1) { for (int i = 0; i < (10); ++i) if (to[u][i] == x) to[u][i] = y; } else { psd(u); int mid = l + r >> 1; if (l1 <= mid) change(((u) << 1), l, mid, l1, r1, x, y); if (r1 > mid) change(((u) << 1 ^ 1), mid + 1, r, l1, r1, x, y); merge(u); } } inline long long getans(int u, int l, int r, int l1, int r1) { long long ans = 0; if (l1 <= l && r <= r1) { for (int i = 0; i < (10); ++i) ans += to[u][i] * val[u][i]; } else { psd(u); int mid = l + r >> 1; if (l1 <= mid) ans += getans(((u) << 1), l, mid, l1, r1); if (r1 > mid) ans += getans(((u) << 1 ^ 1), mid + 1, r, l1, r1); merge(u); } return ans; } int main() { scanf( %d%d , &n, &q); for (int i = (1); i <= (n); ++i) scanf( %d , a + i); init(1, 1, n); while (q--) { int type, l, r, x, y; scanf( %d%d%d , &type, &l, &r); if (type == 1) { scanf( %d%d , &x, &y); change(1, 1, n, l, r, x, y); } else { printf( %lld n , getans(1, 1, n, l, r)); } } return 0; } |
module note2dds_4st_gen(clk, note, adder);
input wire clk;
input wire [6:0] note;
output [31:0] adder;
reg [31:0] adder_tbl [15:0];
reg [3:0] addr;
reg [3:0] divider;
// note div 12 ( * 0,08333333333333333333333333333333)
//; Add input / 16 to accumulator
//; Add input / 64 to accumulator
initial begin
addr <= 4'd0;
divider <= 4'd0;
adder_tbl[ 4'd0] <= 32'd0359575;
adder_tbl[ 4'd1] <= 32'd0380957;
adder_tbl[ 4'd2] <= 32'd0403610;
adder_tbl[ 4'd3] <= 32'd0427610;
adder_tbl[ 4'd4] <= 32'd0453037;
adder_tbl[ 4'd5] <= 32'd0479976;
adder_tbl[ 4'd6] <= 32'd0508516;
adder_tbl[ 4'd7] <= 32'd0538754;
adder_tbl[ 4'd8] <= 32'd0570790;
adder_tbl[ 4'd9] <= 32'd0604731;
adder_tbl[4'd10] <= 32'd0640691;
adder_tbl[4'd11] <= 32'd0678788;
adder_tbl[4'd12] <= 32'd0;
adder_tbl[4'd13] <= 32'd0;
adder_tbl[4'd14] <= 32'd0;
adder_tbl[4'd15] <= 32'd0;
end
assign adder = adder_tbl[addr] >> divider;
wire [3:0] diap = (note < 12) ? 4'd00 :
(note < 24) ? 4'd01 :
(note < 36) ? 4'd02 :
(note < 48) ? 4'd03 :
(note < 60) ? 4'd04 :
(note < 72) ? 4'd05 :
(note < 84) ? 4'd06 :
(note < 96) ? 4'd07 :
(note < 108) ? 4'd08 :
(note < 120) ? 4'd09 : 4'd010 ;
wire [6:0] c_addr = note - (diap * 4'd012);
always @ (posedge clk) begin
addr <= c_addr[3:0];
divider <= 4'd010 - diap;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<int> a, b, e; char s[5]; long long ans; int c; int main() { int n, f; scanf( %d , &n); while (n--) { scanf( %s %d , &s, &f); if (s[0] == 0 && s[1] == 1 ) a.push_back(f); else if (s[0] == 1 && s[1] == 0 ) b.push_back(f); else if (s[0] == 0 && s[1] == 0 ) e.push_back(f); else { c++; ans += f; } } int temp = c + 2 * min((int)a.size(), (int)b.size()); c += min((int)a.size(), (int)b.size()); if (!a.empty()) sort(a.rbegin(), a.rend()); if (!b.empty()) sort(b.rbegin(), b.rend()); for (int i = 0; i < min((int)a.size(), (int)b.size()); ++i) { ans += a[i]; ans += b[i]; } if (a.size() > b.size()) { for (int i = min(a.size(), b.size()); i < a.size(); ++i) e.push_back(a[i]); } else if (b.size() > a.size()) { for (int i = min(a.size(), b.size()); i < b.size(); ++i) e.push_back(b[i]); } if (!e.empty()) sort(e.rbegin(), e.rend()); for (int i = 0; i < e.size(); ++i) { if (((temp + 2) / 2) <= c) { ans += e[i]; temp++; } } printf( %lld , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long n, ans, val[3001000]; priority_queue<int> q; int main() { scanf( %lld , &n); for (int i = 1; i <= n; i++) scanf( %lld , &val[i]); for (int i = 1; i <= n; i++) { q.push(-val[i]); q.push(-val[i]); ans += val[i] + q.top(); q.pop(); } printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; using lint = long long; using pi = pair<int, int>; const int MAXN = 1005; const int MAXM = 1005; struct edge_color { int deg[2][MAXN]; pi has[2][MAXN][MAXN]; int color[MAXM]; int c[2]; void clear(int n) { for (int t = 0; t < 2; t++) { for (int i = 0; i <= n; i++) { deg[t][i] = 0; for (int j = 0; j <= n; j++) { has[t][i][j] = pi(0, 0); } } } } void dfs(int x, int p) { auto i = has[p][x][c[!p]]; if (has[!p][i.first][c[p]].second) dfs(i.first, !p); else has[!p][i.first][c[!p]] = pi(0, 0); has[p][x][c[p]] = i; has[!p][i.first][c[p]] = pi(x, i.second); color[i.second] = c[p]; } int solve(vector<pi> v, vector<int> &cv) { int m = ((int)(v).size()); int ans = 0; for (int i = 1; i <= m; i++) { int x[2]; x[0] = v[i - 1].first; x[1] = v[i - 1].second; for (int d = 0; d < 2; d++) { deg[d][x[d]] += 1; ans = max(ans, deg[d][x[d]]); for (c[d] = 1; has[d][x[d]][c[d]].second; c[d]++) ; } if (c[0] != c[1]) dfs(x[1], 1); for (int d = 0; d < 2; d++) has[d][x[d]][c[0]] = pi(x[!d], i); color[i] = c[0]; } cv.resize(m); for (int i = 1; i <= m; i++) { cv[i - 1] = color[i]; color[i] = 0; } return ans; } } EC; int cnt[2][MAXN]; int idx[2][MAXN], L, R; int main() { int n, m, t; scanf( %d %d %d , &n, &m, &t); for (int i = 0; i < n; i++) scanf( %*d ); vector<pi> ans; for (int i = 0; i < m; i++) { int l, r; scanf( %d %d , &l, &r); if (cnt[0][l] == 0) idx[0][l] = ++L; if (cnt[1][r] == 0) idx[1][r] = ++R; cnt[0][l]++; cnt[1][r]++; if (cnt[0][l] == t) cnt[0][l] = 0; if (cnt[1][r] == t) cnt[1][r] = 0; ans.emplace_back(idx[0][l], idx[1][r]); } vector<int> color; EC.solve(ans, color); for (auto &i : color) printf( %d n , i); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2B_SYMBOL_V
`define SKY130_FD_SC_LP__AND2B_SYMBOL_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and2b (
//# {{data|Data Signals}}
input A_N,
input B ,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2B_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { long long int n, x; cin >> n >> x; long long int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } sort(a, a + n); int j = 1, teams = 0; for (int i = n - 1; i >= 0; i--) { if (a[i] * j >= x) { teams++; j = 0; } j++; } cout << teams << endl; } } |
/*
Name: ClockRecoverSetCounter
Attempts to recover a clock from a serial signal whose frequency is known, set,
and equal to system clock frequency divided by some integer. Reclocked serial
data is then output along with a clock strobe.
Faster is pretty much always better for this type of function, so the clock
recovery system runs at system clock.
Target frequency is set by setting the TARGET_PERIOD value such that
f_target = f_clk / TARGET_PERIOD
*/
module ClkRecoverSetCounter #(
parameter TARGET_PERIOD = 10 ///< Expected # clks for recovered clock
)
(
// Inputs
input clk, ///< System clock
input rst, ///< Reset, synchronous and active high
input rx, ///< Input serial signal
// Outputs
output reg clkStrobe, ///< Recovered clock strobe
output reg rxClocked ///< Synchronized rx data
);
parameter PHASE_HIGH = $clog2(TARGET_PERIOD-1) - 1;
wire intClk; ///< Internal clock
reg [PHASE_HIGH:0] phaseAccum; ///< Phase accumulator for internal clock
reg intClkD1; ///< intClk delayed 1 clk
reg rxD1; ///< rx delayed 1 clk
reg started; ///< Goes high once first edge found
// Debug
wire refClk;
reg isZero;
assign refClk = (phaseAccum == 'd0) && ~isZero;
always @(posedge clk) begin
isZero <= phaseAccum == 'd0;
end
assign intClk = (phaseAccum == (TARGET_PERIOD>>1));
always @(posedge clk) begin
rxD1 <= rx;
intClkD1 <= intClk;
clkStrobe <= intClk & ~intClkD1;
rxClocked <= (intClk & ~intClkD1) ? rx : rxClocked;
end
// Phase accumulator and tracking loop
always @(posedge clk) begin
if (rst) begin
phaseAccum <= 'd0;
started <= 1'b0;
end
else begin
if (started) begin
// Phase lag - increase phase to catch up
if ((rxD1 ^ rx) && (phaseAccum >= (TARGET_PERIOD>>1))) begin
if (phaseAccum == TARGET_PERIOD-1) begin
phaseAccum <= 'd1;
end
else if (phaseAccum == TARGET_PERIOD-2) begin
phaseAccum <= 'd0;
end
else begin
phaseAccum <= phaseAccum + 2'd2;
end
end
// Phase lead - don't increment phase to slow down
else if ((rxD1 ^ rx) && (phaseAccum != 'd0)) begin
phaseAccum <= phaseAccum;
end
// In phase but lagging
else if (phaseAccum == TARGET_PERIOD-1) begin
phaseAccum <= 'd0;
end
else begin
phaseAccum <= phaseAccum + 2'd1;
end
end
else begin
started <= rxD1 ^ rx;
phaseAccum <= 'd0;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, x, i, a[200], s1, s2, j = 2; string can = YES ; int main() { cin >> n; cin >> x; x = 7 - x; for (i = 0; i < n * 2; i++) { cin >> a[i]; } for (i = 1; i < n; i++) { s1 = a[j]; s2 = a[j + 1]; if (x == s1 || x == s2 || x == 7 - s2 || x == 7 - s1) { can = NO ; break; } j += 2; } cout << can; } |
#include <bits/stdc++.h> using namespace std; ifstream fin( input ); void init() { cin.tie(NULL); ios_base::sync_with_stdio(false); } struct operation { int i, j, x; }; int n; vector<int> v; vector<int> cpy; vector<operation> ops; void simul() { for (operation x : ops) { cpy[x.i] -= x.i * x.x; cpy[x.j] += x.i * x.x; } for (int i = 1; i <= n; i++) cout << cpy[i] << ; cout << endl; } void read() { cin >> n; v.resize(n + 1); for (int i = 1; i <= n; i++) cin >> v[i]; cpy = v; } void solve() { int sum = 0; for (int i = 1; i <= n; i++) sum += v[i]; if (sum % n != 0) { cout << -1 << endl; return; } for (int i = 2; i <= n; i++) { if (v[i] != 0) { int remaining = v[i] % i; if (remaining) { int required = i - remaining; ops.push_back({1, i, required}); v[i] += required; } ops.push_back({i, 1, v[i] / i}); } } for (int i = 2; i <= n; i++) { ops.push_back({1, i, sum / n}); } cout << ops.size() << endl; for (operation& x : ops) { cout << x.i << << x.j << << x.x << endl; } ops.clear(); } int main() { init(); int t; cin >> t; while (t--) { read(); solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long powm(long long base, long long exp, long long mod = 1000000009) { long long ans = 1; while (exp) { if (exp & 1) ans = (ans * base) % mod; exp >>= 1, base = (base * base) % mod; } return ans; } long long ctl(char x, char an = a ) { return (long long)(x - an); } char ltc(long long x, char an = a ) { return (char)(x + an); } long long first[300005], pref[300005], pref_fib[300005], a[300005]; long long get_fibo_sum(long long l, long long r) { return (pref_fib[r] - (l ? pref_fib[l - 1] : 0) + 1000000009) % 1000000009; } long long get_fibo(long long st1, long long st2, long long i) { if (i == 0) return st1; else if (i == 1) return st2; else { long long ret = ((first[i - 1] * st2) % 1000000009 + (first[i - 2] * st1) % 1000000009) % 1000000009; return ret; } } long long get_fibo_sum(long long st1, long long st2, long long i) { if (i == 0) return st1; else if (i == 1) return (st1 + st2) % 1000000009; else { long long ans = (st2 * get_fibo_sum(1, i - 1)) % 1000000009; ans = (ans + (st1 * get_fibo_sum(0, i - 2)) % 1000000009) % 1000000009; ans = (ans + st1) % 1000000009; ans = (ans + st2) % 1000000009; return ans; } } const pair<long long, long long> khali = make_pair(0LL, 0LL); struct lazySegTree { long long tree[4 * 300005], x, y, val; pair<long long, long long> lazy[4 * 300005]; void push(long long low, long long high, long long pos) { if (lazy[pos] != khali) { tree[pos] += get_fibo_sum(lazy[pos].first, lazy[pos].second, (high - low)); if (low != high) { pair<long long, long long> tmp; tmp = lazy[pos]; lazy[2 * pos + 1].first = (lazy[2 * pos + 1].first + tmp.first) % 1000000009; lazy[2 * pos + 1].second = (lazy[2 * pos + 1].second + tmp.second) % 1000000009; tmp.first = get_fibo(lazy[pos].first, lazy[pos].second, (low + high) / 2 - low + 1); tmp.second = get_fibo(lazy[pos].first, lazy[pos].second, (low + high) / 2 - low + 2); lazy[2 * pos + 2].first = (lazy[2 * pos + 2].first + tmp.first) % 1000000009; lazy[2 * pos + 2].second = (lazy[2 * pos + 2].second + tmp.second) % 1000000009; } lazy[pos] = khali; } } long long query(long long low, long long high, long long pos) { push(low, high, pos); if (x <= low and y >= high) return tree[pos]; if (x > high || y < low) return 0; long long mid = (high + low) / 2; return (query(low, mid, 2 * pos + 1) + query(mid + 1, high, 2 * pos + 2)) % 1000000009; } void update(long long low, long long high, long long pos) { push(low, high, pos); if (x > high || y < low) return; if (x <= low and y >= high) { lazy[pos].first = first[low - x]; lazy[pos].second = first[low - x + 1]; push(low, high, pos); return; } long long mid = (low + high) / 2; update(low, mid, 2 * pos + 1), update(mid + 1, high, 2 * pos + 2); tree[pos] = (tree[2 * pos + 1] + tree[2 * pos + 2]) % 1000000009; } } lst; int main() { first[0] = 1, first[1] = 1; for (long long i = 2; i < 300005; i++) first[i] = (first[i - 1] + first[i - 2]) % 1000000009; for (long long i = 0; i < 4 * 300005; i++) lst.lazy[i] = khali; long long type, l, r, n, q; cin >> n >> q; for (long long i = 1; i < n + 1; i++) cin >> a[i]; pref_fib[0] = 1; for (long long i = 1; i < 300005; i++) pref_fib[i] = (pref_fib[i - 1] + first[i]) % 1000000009; pref[1] = a[1]; for (long long i = 1; i < 300005; i++) pref[i] = (pref[i - 1] + a[i]) % 1000000009; while (q--) { cin >> type >> l >> r; lst.x = l, lst.y = r; if (type == 1) { lst.update(1, n, 0); } else { long long ans = lst.query(1, n, 0); ans = (ans + pref[r]) % 1000000009; ans = (ans - pref[l - 1] + 1000000009) % 1000000009; cout << ans << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1000010; const long long inf = (1ll << 58ll); int k, n, q; int ten[10] = {1, 10, 100, 1000, 10000, 100000}; long long F[7]; long long dp[maxn], g[7][maxn]; long long read() { long long s = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { s = s * 10 + ch - 0 ; ch = getchar(); } return s * f; } int main() { k = read(); for (int i = 0; i < 6; ++i) F[i] = read(); fill(dp, dp + 1 + 999999, -inf); dp[0] = 0; for (int d = 1; d <= 6; ++d) { long long left = 1ll * 3 * (k - 1); long long group = 1ll; while (left > 0) { group = min(group, left); long long val = 1ll * group * F[d - 1]; long long wei = 1ll * 3 * group * ten[d - 1]; for (int i = 999999; i >= wei; --i) { dp[i] = max(dp[i], dp[i - wei] + val); } left -= group; group *= 2; } } for (int i = 1; i <= 6; ++i) fill(g[i], g[i] + 1000000, -inf); for (int i = 0; i <= 999999; ++i) g[0][i] = dp[i]; for (int d = 1; d <= 6; ++d) { for (int j = 0; j <= 9; ++j) { long long val, wei; if (j == 3 || j == 6 || j == 9) val = 1ll * (j / 3) * F[d - 1]; else val = 0; wei = 1ll * j * ten[d - 1]; for (int i = 999999; i >= wei; i--) g[d][i] = max(g[d][i], g[d - 1][i - wei] + val); } } q = read(); for (int i = 1; i <= q; ++i) { n = read(); printf( %lld n , g[6][n]); } return 0; } |
import "DPI-C" function string fna (input string str1);
export "DPI" c_identifier = task task_identifier;
import "DPI" context function string fnb (input string str1);
module testbench;
import "DPI" function string fn1 (input string str1);
import "DPI-C" function void dpiWriteArray (input bit[7:0] data[]);
import "DPI-C" pure function void dpiReadArray (output bit[7:0] data[]);
import "DPI-C" function void dpiAesSetKey ( int key_high_u int key_high_l,
int key_low_u, int key_low_l );
import "DPI-C" function void dpiAesSetIV (int iv_high_u, int iv_high_l,
int iv_low_u, int iv_low_l);
import "DPI-C" function void dpiAesSetSkip (int skip);
import "DPI-C" function void dpiAesCBCEncrypt ();
logic a;
endmodule // testbench
/*
package ref_model;
import "DPI-C" xx_write_bmp_file =
function void write_bmp_file(input string filename);
import "DPI-C" xx_demosaic =
function void demosaic(regs regs,
inout pix_buf imgR, imgG, imgB);
endpackage
*/
|
// Copyright 2021 The CFU-Playground Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
module Cfu (
input cmd_valid,
output cmd_ready,
input [9:0] cmd_payload_function_id,
input [31:0] cmd_payload_inputs_0,
input [31:0] cmd_payload_inputs_1,
output rsp_valid,
input rsp_ready,
output [31:0] rsp_payload_outputs_0,
input reset,
input clk
);
// Trivial handshaking for a combinational CFU
assign rsp_valid = cmd_valid;
assign cmd_ready = rsp_ready;
//
// select output -- note that we're not fully decoding the 3 function_id bits
//
assign rsp_payload_outputs_0 = cmd_payload_function_id[0] ?
cmd_payload_inputs_1 :
cmd_payload_inputs_0 ;
endmodule
|
#include <bits/stdc++.h> using namespace std; int n; void solve() { if (n <= 3) printf( NO n ); else if (n == 4) { printf( YES n ); printf( 2 * 3 = 6 n ); printf( 6 * 4 = 24 n ); printf( 24 * 1 = 24 n ); } else if (n == 5) { printf( YES n ); printf( 1 + 5 = 6 n ); printf( 3 - 2 = 1 n ); printf( 6 * 1 = 6 n ); printf( 6 * 4 = 24 n ); } else if (n >= 6) { printf( YES n ); printf( 3 - 2 = 1 n ); printf( 1 - 1 = 0 n ); printf( 4 * 6 = 24 n ); printf( 5 * 0 = 0 n ); int i = 7; while (i <= n) { printf( %d * 0 = 0 n , i); i++; } printf( 24 + 0 = 24 n ); } else printf( NO n ); } int main() { while (scanf( %d , &n) != EOF) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int _seive_size; bitset<1000000> bs; vector<long long int> primes; void seive(long long int upperbound) { _seive_size = upperbound + 1; bs.set(); bs[0] = bs[1] = 0; for (long long int i = 2; i <= _seive_size; i++) { if (bs[i]) { for (long long int j = i * i; j <= _seive_size; j += i) { bs[j] = 0; } primes.push_back((int)i); } } } bool isTrime(long long int N) { long long int temp; long long int start = 0; long long int end = primes.size() - 1; while (start <= end) { long long int mid = start + (end - start) / 2; temp = primes[mid] * primes[mid]; if (temp == N) { return true; } else if (temp < N) { start = mid + 1; } else { end = mid - 1; } } return false; } int main() { seive(1000000); long long int n; cin >> n; long long int arr[n]; for (int i = 0; i < n; i++) { cin >> arr[i]; } for (int i = 0; i < n; i++) { if (isTrime(arr[i])) { cout << YES << endl; } else { cout << NO << endl; } } return 0; } |
module platform(
input CLK_EXT,
output BUZZER_,
// control panel
input RXD,
output TXD,
output [7:0] DIG,
output [7:0] SEG,
// RAM
output SRAM_CE_, SRAM_OE_, SRAM_WE_, SRAM_UB_, SRAM_LB_,
output [17:0] SRAM_A,
inout [15:0] SRAM_D,
output F_CS_, F_OE_, F_WE_
);
localparam CLK_EXT_HZ = 50_000_000;
// --- MERA-400f ---------------------------------------------------------
wire sram_ce, sram_oe, sram_we;
wire [0:15] w;
wire [10:0] rotary_bus;
wire [0:9] indicators;
mera400f #(
.CLK_EXT_HZ(CLK_EXT_HZ)
) MERA400F (
.clk_ext(CLK_EXT),
.rxd(RXD),
.txd(TXD),
.ram_ce(sram_ce),
.ram_oe(sram_oe),
.ram_we(sram_we),
.ram_a(SRAM_A),
.ram_d(SRAM_D),
.w(w),
.rotary_bus(rotary_bus),
.indicators(indicators)
);
// --- External devices --------------------------------------------------
// silence the buzzer
assign BUZZER_ = 1'b1;
// disable flash, which uses the same D and A buses as sram
assign F_CS_ = 1'b1;
assign F_OE_ = 1'b1;
assign F_WE_ = 1'b1;
// always use full 16-bit word
assign SRAM_LB_ = 1'b0;
assign SRAM_UB_ = 1'b0;
assign SRAM_CE_ = ~sram_ce;
assign SRAM_OE_ = ~sram_oe;
assign SRAM_WE_ = ~sram_we;
// --- 7-segment display
display DISPLAY(
.clk_sys(CLK_EXT),
.w(w),
.rotary_bus(rotary_bus),
.indicators(indicators),
.seg(SEG),
.dig(DIG)
);
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
#include <bits/stdc++.h> using namespace std; int digit(long long int n) { if (n > 0) return (digit(n / 10) + 1); return 0; } int main() { long long int l, h; long long int a[] = {0, 4, 49, 499, 4999, 49999, 499999, 4999999, 49999999, 499999999, 4999999999}; long long int b[] = {0, 9, 99, 999, 9999, 99999, 999999, 9999999, 99999999, 999999999, 9999999999}; cin >> l >> h; long long int ans = max(a[digit(l)], l); ans = min(a[digit(h)], h); ans = max(ans, l); ans = (long long int)(ans) * (b[digit(ans)] - ans); cout << ans << endl; return 0; } |
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Title : PCI Express PIPE PHY connector
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcietb_pipe_phy.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description :
// This function interconnects two PIPE MAC interfaces for a single lane.
// For now this uses a common PCLK for both interfaces, an enhancement woudl be
// to support separate PCLK's for each interface with the requisite elastic
// buffer.
//-----------------------------------------------------------------------------
// Copyright (c) 2005 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
module altpcietb_rst_clk (
ref_clk_sel_code,
ref_clk_out,
pcie_rstn,
ep_core_clk_out,
rp_rstn
);
input [3:0] ref_clk_sel_code;
output ref_clk_out;
output pcie_rstn;
output rp_rstn;
input ep_core_clk_out;
integer half_period;
reg ref_clk_out;
reg pcie_rstn;
reg rp_rstn;
integer core_clk_out_period;
integer core_clk_cnt = 0;
integer refclk_cnt = 0;
always @(ref_clk_sel_code)
case (ref_clk_sel_code)
4'h0: half_period = 5000;
4'h1: half_period = 4000;
4'h2: half_period = 3200;
4'h3: half_period = 2000;
default: half_period = 5000;
endcase
always
#half_period ref_clk_out <= ~ref_clk_out;
always @(posedge ref_clk_out)
begin
if (rp_rstn == 0)
refclk_cnt <= 0;
else
refclk_cnt <= refclk_cnt + 1;
if ((refclk_cnt == 200) & (core_clk_cnt > 10))
$display("INFO: Core Clk Frequency: %5.2f Mhz",/(half_period*2*200/core_clk_cnt));
end
always @(posedge ep_core_clk_out)
if (rp_rstn == 0)
core_clk_cnt <= 0;
else
core_clk_cnt <= core_clk_cnt + 1;
initial
begin
pcie_rstn = 1'b1;
rp_rstn = 1'b0;
ref_clk_out = 1'b0;
#1000
pcie_rstn = 1'b0;
rp_rstn = 1'b1;
#1000
rp_rstn = 1'b0;
#1000
rp_rstn = 1'b1;
#1000
rp_rstn = 1'b0;
#200000 pcie_rstn = 1'b1;
#100000 rp_rstn = 1'b1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; #pragma GCC optimize( Ofast ) #pragma GCC optimize( unroll-loops ) template <class T, class U> istream &operator>>(istream &in, pair<T, U> &p) { in >> p.first >> p.second; return in; } template <class T, class U> ostream &operator<<(ostream &out, const pair<T, U> &p) { out << p.first << << p.second; return out; } template <class T> istream &operator>>(istream &in, vector<T> &v) { for (auto &i : v) { in >> i; } return in; } template <class T> ostream &operator<<(ostream &out, const vector<T> &v) { for (auto &i : v) { out << i << ; } return out; } inline void io(int x = 15) { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); srand(time(0)); cout << fixed << setprecision(x); } vector<int> prefix_function(string s) { int n = s.length(); vector<int> pi(n); for (int i = 1; i < n; ++i) { int j = pi[i - 1]; while (j > 0 && s[i] != s[j]) { j = pi[j - 1]; } if (s[i] == s[j]) ++j; pi[i] = j; } return pi; } bool prime_test(long long n) { for (long long i = 2; i * i <= n; ++i) if ((n >= 0 && n < 2) || n % i == 0) return false; return true; } void prime_nums(int n, vector<char> &prime) { prime[0] = prime[1] = false; for (long long i = 2; i * i <= n; ++i) { if (prime[i]) { for (int j = i * i; j <= n; j += i) { prime[j] = false; } } } } long long bin_pow(long long a, long long b, long long m = 0) { if (m == 0) return b == 0 ? 1 : (b % 2 ? bin_pow(a, b - 1) * a : bin_pow(a * a, b / 2)); if (b == 0) return 1; long long temp = bin_pow(a, b / 2, m); if (b % 2 == 0) return (temp * temp) % m; else return (a * temp * temp) % m; } bool nextperm(vector<char> &a) { int n = a.size(); for (int i = n - 2; i >= 0; --i) { if (a[i] < a[i + 1]) { int mnv = a[i + 1], mni = i + 1; for (int j = i + 2; j < n; ++j) { if (a[j] < mnv && a[j] > a[i]) { mni = j; mnv = a[j]; } } swap(a[i], a[mni]); reverse(a.begin() + i + 1, a.end()); return true; } } return false; } int main() { io(); int n, s; cin >> n >> s; vector<int> used(n); for (int i = 0; i < n - 1; ++i) { int l, r; cin >> l >> r; ++used[--l]; ++used[--r]; } int x = 0; for (int i = 0; i < n; ++i) { if (used[i] == 1) { ++x; } } cout << (long double)s / x * 2; return 0; } |
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_atan_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_atan_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.q(sub_wire0));
endmodule
|
#include <bits/stdc++.h> using namespace std; string to_string(string s) { return + s + ; } string to_string(const char *s) { return to_string((string)s); } string to_string(bool b) { return (b ? true : false ); } template <typename A, typename B> string to_string(pair<A, B> p) { return ( + to_string(p.first) + , + to_string(p.second) + ) ; } template <typename A> string to_string(A v) { bool first = true; string res = { ; for (const auto &x : v) { if (!first) { res += , ; } first = false; res += to_string(x); } res += } ; return res; } void debug_out() { cerr << endl; } template <typename Head, typename... Tail> void debug_out(Head H, Tail... T) { cerr << << to_string(H); debug_out(T...); } const int md = 998244353; inline void add(int &x, int y) { x += y; if (x >= md) { x -= md; } } inline void sub(int &x, int y) { x -= y; if (x < 0) { x += md; } } inline int mul(int x, int y) { return (long long)x * y % md; } inline int power(int x, int y) { int result = 1; for (; y; y >>= 1, x = mul(x, x)) { if (y & 1) { result = mul(result, x); } } return result; } template <typename T> class fenwick_t { public: vector<T> fenw; int n; fenwick_t(int n) : n(n) { fenw.resize(n); } void modify(int x, T value) { while (x < n) { fenw[x] += value; x |= x + 1; } } T query(int x) { T result{}; while (x >= 0) { result += fenw[x]; x = (x & x + 1) - 1; } return result; } T get(int l, int r) { return query(r) - query(l - 1); } }; int main() { int n; scanf( %d , &n); if (n == 1) { puts( 0 ); return 0; } vector<int> w(n + 1); w[1] = 0; w[2] = 1; for (int i = 3; i <= n; ++i) { w[i] = mul(i - 1, w[i - 1] + w[i - 2]); } vector<int> fact(n + 1); fact[0] = 1; for (int i = 1; i <= n; ++i) { fact[i] = mul(fact[i - 1], i); } vector<vector<int>> f(n + 1, vector<int>(n + 1)); for (int i = 0; i <= n; ++i) { f[i][0] = fact[i]; for (int j = 1; j <= i; ++j) { f[i][j] = f[i][j - 1]; sub(f[i][j], f[i - 1][j - 1]); } } vector<vector<int>> a(n, vector<int>(n)); for (int i = 0; i < n; ++i) { for (int j = 0; j < n; ++j) { scanf( %d , &a[i][j]); --a[i][j]; } } int answer = 0; { fenwick_t<int> fenw(n); for (int i = 0; i < n; ++i) { fenw.modify(i, 1); } int coef = power(w[n], n - 1); for (int i = 0; i < n; ++i) { fenw.modify(a[0][i], -1); add(answer, mul(fact[n - i - 1], mul(coef, fenw.query(a[0][i] - 1)))); } } for (int i = 1; i < n; ++i) { fenwick_t<int> foo(n), bar(n); vector<int> cnt(n); int current = 0; auto insert = [&](int x) { if (++cnt[x] == 2) { ++current; foo.modify(x, 1); } }; auto get = [&](int x, int y) { return y < 0 || y > x ? 0 : f[x][y]; }; int coef = power(w[n], n - i - 1); for (int j = n - 1; ~j; --j) { insert(a[i - 1][j]); insert(a[i][j]); bar.modify(a[i][j], 1); int u = foo.query(a[i][j] - 1), v = bar.query(a[i][j] - 1) - u; add(answer, mul(coef, mul(u, get(n - j - 1, current - (cnt[a[i - 1][j]] == 2) - 1)))); add(answer, mul(coef, mul(v, get(n - j - 1, current - (cnt[a[i - 1][j]] == 2))))); if (cnt[a[i - 1][j]] == 2 && a[i - 1][j] < a[i][j]) { sub(answer, mul(coef, get(n - j - 1, current - 2))); } } } printf( %d n , answer); return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module small_hb_int_tb( ) ;
// Parameters for instantiation
parameter clocks = 8'd1 ; // Number of clocks per output
parameter decim = 1 ; // Sets the filter to decimate
parameter rate = 2 ; // Sets the decimation rate
reg clock ;
reg reset ;
reg enable ;
wire strobe_in ;
reg signed [17:0] data_in ;
wire strobe_out ;
wire signed [17:0] data_out ;
initial
begin
$dumpfile("small_hb_int_tb.vcd");
$dumpvars(0,small_hb_int_tb);
end
// Setup the clock
initial clock = 1'b0 ;
always #5 clock <= ~clock ;
// Come out of reset after a while
initial reset = 1'b1 ;
initial #1000 reset = 1'b0 ;
always @(posedge clock)
enable <= ~reset;
// Instantiate UUT
/*
halfband_ideal
#(
.decim ( decim ),
.rate ( rate )
) uut(
.clock ( clock ),
.reset ( reset ),
.enable ( enable ),
.strobe_in ( strobe_in ),
.data_in ( data_in ),
.strobe_out ( strobe_out ),
.data_out ( data_out )
) ;
*/
cic_strober #(.WIDTH(8))
out_strober(.clock(clock),.reset(reset),.enable(enable),.rate(clocks),
.strobe_fast(1),.strobe_slow(strobe_out) );
cic_strober #(.WIDTH(8))
in_strober(.clock(clock),.reset(reset),.enable(enable),.rate(2),
.strobe_fast(strobe_out),.strobe_slow(strobe_in) );
small_hb_int #(.WIDTH(18)) uut
(.clk(clock),.rst(reset),.bypass(0),.stb_in(strobe_in),.data_in(data_in),
.stb_out(strobe_out),.output_rate(clocks),.data_out(data_out) );
integer i, ri, ro, infile, outfile ;
always @(posedge clock)
begin
if(strobe_out)
$display(data_out);
end
// Setup file IO
initial begin
infile = $fopen("input.dat","r") ;
outfile = $fopen("output.dat","r") ;
$timeformat(-9, 2, " ns", 10) ;
end
reg endofsim ;
reg signed [17:0] compare ;
integer noe ;
initial noe = 0 ;
initial begin
// Initialize inputs
data_in <= 18'd0 ;
// Wait for reset to go away
@(negedge reset) #0 ;
// While we're still simulating ...
while( !endofsim ) begin
// Write the input from the file or 0 if EOF...
@( negedge clock ) begin
if(strobe_in)
if( !$feof(infile) )
ri <= #1 $fscanf( infile, "%d", data_in ) ;
else
data_in <= 18'd0 ;
end
end
// Print out the number of errors that occured
if( noe )
$display( "FAILED: %d errors during simulation", noe ) ;
else
$display( "PASSED: Simulation successful" ) ;
$finish ;
end
// Output comparison of simulated values versus known good values
always @ (posedge clock) begin
if( reset )
endofsim <= 1'b0 ;
else begin
if( !$feof(outfile) ) begin
if( strobe_out ) begin
ro = $fscanf( outfile, "%d\n", compare ) ;
if( compare != data_out ) begin
//$display( "%t: %d != %d", $realtime, data_out, compare ) ;
noe = noe + 1 ;
end
end
end else begin
// Signal end of simulation when no more outputs
if($feof(infile))
endofsim <= 1'b1 ;
end
end
end
endmodule // small_hb_int_tb
|
#include <bits/stdc++.h> using namespace std; long long power(long long x, long long y) { long long res = 1; while (y > 0) { if (y & 1) res = (res * x) % 998244353; y = y / 2; if (y != 0) x = (x * x) % 998244353; } return res; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t, n, i, j, o, e, ans = 0, num, ans1, ans2, sz, x = 0, chk; cin >> n; long long a; vector<long long> v; for (i = 0; i < n; i++) { cin >> a; v.push_back(a); } queue<vector<long long> > q; q.push(v); long long bit = 30; while (bit >= 0) { sz = q.size(); chk = 1ll << bit; ans1 = ans2 = 0; for (i = 0; i < sz; i++) { v = q.front(); q.pop(); vector<long long> one, zero; o = e = 0; for (j = 0; j < v.size(); j++) { num = v[j]; if (num & chk) { one.push_back(v[j]); o++; ans2 += e; } else { zero.push_back(v[j]); e++; ans1 += o; } } if (!one.empty()) q.push(one); if (!zero.empty()) q.push(zero); } ans += min(ans1, ans2); if (ans1 > ans2) x += chk; bit--; } cout << ans << << x << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { char str[200]; int num, i, j, k; int pre = 0; char temp[10]; cin.getline(str, 200, n ); for (i = 0; str[i] != 0; i++) { num = str[i]; j = 0; while (num != 0) { k = num % 2; temp[j++] = k + 0 ; num = (num - k) / 2; } while (j < 8) temp[j++] = 0 ; temp[j] = 0 ; for (j = 0; j < 8; j++) num += (temp[j] - 0 ) << (7 - j); k = (pre - num) % 256; if (k < 0) k += 256; cout << k << endl; pre = num; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_BLACKBOX_V
`define SKY130_FD_SC_HS__FA_BLACKBOX_V
/**
* fa: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311OI_2_V
`define SKY130_FD_SC_LS__A311OI_2_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a311oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a311oi_2 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a311oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311OI_2_V
|
/**
* bp2wb_convertor.v
* DESCRIPTION: THIS MODULE ADAPTS BP MEMORY BUS TO 64-BIT WISHBONE
*/
module bp2wb_convertor
import bp_common_pkg::*;
import bp_me_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_unicore_no_l2_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_bedrock_mem_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p, cce)
// , parameter [paddr_width_p-1:0] dram_offset_p = '0
, localparam num_block_words_lp = cce_block_width_p / 64
, localparam num_block_bytes_lp = cce_block_width_p / 8
, localparam num_word_bytes_lp = dword_width_gp / 8 //gp correct?
, localparam block_offset_bits_lp = `BSG_SAFE_CLOG2(num_block_bytes_lp)
, localparam word_offset_bits_lp = `BSG_SAFE_CLOG2(num_block_words_lp)
, localparam byte_offset_bits_lp = `BSG_SAFE_CLOG2(num_word_bytes_lp)
, localparam wbone_data_width = 64
, localparam wbone_addr_ubound = paddr_width_p
, localparam mem_granularity = 64 //TODO: adapt selection bit parametrized
, localparam wbone_addr_lbound = 3 //`BSG_SAFE_CLOG2(wbone_data_width / mem_granularity) //dword granularity
, localparam total_datafetch_cycle_lp = cce_block_width_p / wbone_data_width
, localparam total_datafetch_cycle_width = `BSG_SAFE_CLOG2(total_datafetch_cycle_lp)
, localparam cached_addr_base = 32'h7000_0000//6000_0000 //32'h4000_4000//
)
( input clk_i
,(* mark_debug = "true" *) input reset_i
// BP side
,(* mark_debug = "true" *) input [cce_mem_msg_width_lp-1:0] mem_cmd_i
,(* mark_debug = "true" *) input mem_cmd_v_i
,(* mark_debug = "true" *) output mem_cmd_ready_o
, output [cce_mem_msg_width_lp-1:0] mem_resp_o
, (* mark_debug = "true" *) output mem_resp_v_o
, (* mark_debug = "true" *) input mem_resp_yumi_i
// Wishbone side
, (* mark_debug = "true" *) input [63:0] dat_i
, (* mark_debug = "true" *) output logic [63:0] dat_o
, (* mark_debug = "true" *) input ack_i
, input err_i
// , input rty_i
, (* mark_debug = "true" *) output logic [wbone_addr_ubound-wbone_addr_lbound-1:0] adr_o//TODO: Double check!!!
, (* mark_debug = "true" *) output logic stb_o
, output cyc_o
, output [7:0] sel_o //TODO: double check!!!
, (* mark_debug = "true" *) output we_o
, output [2:0] cti_o //TODO: hardwire in Litex
, output [1:0] bte_o //TODO: hardwire in Litex
, input rty_i //TODO: hardwire in Litex
);
`declare_bp_bedrock_mem_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p, cce);
//locals
(* mark_debug = "true" *) logic [total_datafetch_cycle_width:0] ack_ctr = 0;
(* mark_debug = "true" *) bp_bedrock_cce_mem_msg_s mem_cmd_cast_i, mem_resp_cast_o, mem_cmd_debug, mem_cmd_debug2;
(* mark_debug = "true" *) logic ready_li, v_li, stb_justgotack;
(* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_lo;
(* mark_debug = "true" *) logic [cce_block_width_p-1:0] data_li;
(* mark_debug = "true" *) wire [paddr_width_p-1:0] mem_cmd_addr_l;
(* mark_debug = "true" *) logic set_stb;
//Handshaking between Wishbone and BlackParrot through convertor
//3.1.3:At every rising edge of [CLK_I] the terminating signal(ACK) is sampled. If it
//is asserted, then [STB_O] is negated.
assign ready_li = ( ack_ctr == 0 ) & !set_stb & !mem_resp_v_o;
assign mem_cmd_ready_o = ready_li;//!stb_o then ready to take!
// assign v_li = (ack_ctr == total_datafetch_cycle_lp-1);
assign mem_resp_v_o = v_li;
assign stb_o = (set_stb) && !stb_justgotack;
assign cyc_o = stb_o;
assign sel_o = mem_cmd_r.header.size == e_bedrock_msg_size_4 ? ('h0F << wr_byte_shift) : 'hFF;
assign cti_o = 0;
assign bte_o = 0;
initial begin
ack_ctr = 0;
end
//Flip stb after each ack--->RULE 3.20:
// Every time we get an ACK from WB, increment counter until the counter reaches to total_datafetch_cycle_lp
always_ff @(posedge clk_i)
begin
if(reset_i)
begin
ack_ctr <= 0;
set_stb <= 0;
v_li <=0;
end
// else if (v_li)
// begin
else if (mem_resp_yumi_i)
begin
v_li <= 0;
ack_ctr <= 0;
end
// end
else if (mem_cmd_v_i)
begin
//data_li <= 0;
set_stb <= 1;
v_li <= 0;
stb_justgotack <= 0;
end
else
begin
if (ack_i)//stb should be negated after ack
begin
stb_justgotack <= 1;
data_li[(ack_ctr*wbone_data_width) +: wbone_data_width] <= dat_i;
if ((ack_ctr == total_datafetch_cycle_lp-1) || (mem_cmd_addr_l < cached_addr_base && mem_cmd_r.header.msg_type == e_bedrock_mem_uc_wr )) //if uncached store, just one cycle is fine
begin
v_li <=1;
set_stb <= 0;
end
else
ack_ctr <= ack_ctr + 1;
end
else
begin
stb_justgotack <= 0;
v_li <=0;
end
end
end
//Packet Pass from BP to BP2WB
assign mem_cmd_cast_i = mem_cmd_i;
bp_bedrock_cce_mem_msg_s mem_cmd_r;
bsg_dff_reset_en
#(.width_p(cce_mem_msg_width_lp))
mshr_reg
(.clk_i(clk_i)
,.reset_i(reset_i)
,.en_i(mem_cmd_v_i)//when
,.data_i(mem_cmd_i)
,.data_o(mem_cmd_r)
);
//Addr && Data && Command Pass from BP2WB to WB
logic [wbone_addr_lbound-1:0] throw_away;
assign mem_cmd_addr_l = mem_cmd_r.header.addr;
assign data_lo = mem_cmd_r.data;
logic [39:0] mem_cmd_addr_l_zero64;
always_comb begin
if( mem_cmd_addr_l < cached_addr_base )
begin
adr_o = mem_cmd_addr_l[wbone_addr_ubound-1:wbone_addr_lbound];//no need to change address for uncached stores/loads
dat_o = mem_cmd_r.header.size == e_bedrock_msg_size_4 ? data_lo[(0*wbone_data_width) +: wbone_data_width] << rd_byte_offset*8 : data_lo[(0*wbone_data_width) +: wbone_data_width];//unchached data is stored in LS 64bits
end
else
begin
mem_cmd_addr_l_zero64 = mem_cmd_addr_l >> 6 << 6;
{adr_o,throw_away} = mem_cmd_addr_l_zero64 + (ack_ctr*8);//TODO:careful
dat_o = mem_cmd_r.header.size == e_bedrock_msg_size_4 ? data_lo[(ack_ctr*wbone_data_width) +: wbone_data_width] << rd_byte_offset*8 : data_lo[(ack_ctr*wbone_data_width) +: wbone_data_width];
end
end
assign we_o = (mem_cmd_r.header.msg_type inside {e_bedrock_mem_uc_wr, e_bedrock_mem_wr});
//Data Pass from BP2WB to BP
wire [cce_block_width_p-1:0] rd_word_offset = mem_cmd_r.header.addr[3+:3];
wire [cce_block_width_p-1:0] rd_byte_offset = mem_cmd_r.header.addr[0+:3];
wire [cce_block_width_p-1:0] wr_byte_shift = rd_byte_offset;
wire [cce_block_width_p-1:0] rd_bit_shift = rd_word_offset*64; // We rely on receiver to adjust bits
(* mark_debug = "true" *) wire [cce_block_width_p-1:0] data_li_resp = (mem_cmd_r.header.msg_type == e_bedrock_mem_uc_rd)
? data_li >> rd_bit_shift
: data_li;
assign mem_resp_cast_o = '{data : data_li_resp
,header :'{payload : mem_cmd_r.header.payload
,size : mem_cmd_r.header.size
,addr : mem_cmd_r.header.addr
,subop : mem_cmd_r.header.subop
,msg_type: mem_cmd_r.header.msg_type
}
};
assign mem_resp_o = mem_resp_cast_o;
/*********************************************/
/*DEBUG SECTION*/
/*wire [3:0] fake_msg_type;
wire [10:0] fake_payload;
wire [2:0] fake_size;
wire [39:0] fake_addr;
assign fake_payload = mem_cmd_r.header.payload;
assign fake_size = mem_cmd_r.header.size;
assign fake_addr = mem_cmd_r.header.addr;
assign fake_msg_type = mem_cmd_r.header.msg_type;
*/
/*(* mark_debug = "true" *) logic debug_wire;
initial begin
debug_wire = 0;
end
assign mem_cmd_debug = mem_cmd_i;
always_ff @(posedge clk_i)
debug_wire <= (ack_i && mem_cmd_debug.header.addr >= 32'h80000000);
always_ff @(posedge clk_i)
begin
if(mem_cmd_v_i && mem_cmd_debug.header.addr <= 32'h60000000)
begin
debug_wire <= 1;
// $display("addr == %x", mem_cmd_debug.header.addr);
end
/* if (mem_resp_v_o && debug_ctr < 64 && mem_cmd_debug.header.addr >= 32'h80000000)
begin
debug_gotdata[((debug_ctr-1)*512) +: 512] <= data_li_resp;
$display("data == %x", data_li_resp);
end*/
// end
wire [3:0] typean;
assign typean = mem_cmd_r.header.msg_type;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c, d, e; scanf( %d%d%d%d%d , &a, &b, &c, &d, &e); if ((a + b + c + d + e) % 5 == 0 && a + b + c + d + e >= 5) printf( %d n , (a + b + c + d + e) / 5); else printf( -1 n ); } |
#include <bits/stdc++.h> using namespace std; const double eps = 1e-6; long long sum[200005]; long long sum2[200005]; long long a[200005]; int n; int sgn(double x) { if (fabs(x) < eps) return 0; return x > 0 ? 1 : -1; } struct point { long long x, y; point(){}; point(long long x, long long y) : x(x), y(y){}; }; long long dot(point A, point B) { return A.x * B.x + A.y * B.y; } double getlv(point A, point B) { return 1.0 * (B.y - A.y) / (1.0 * (B.x - A.x)); } point stk[200005]; void init() { sum[0] = 0; sum2[0] = 0; for (int i = 1; i <= n; i++) { sum[i] = sum[i - 1] + a[i]; sum2[i] = sum2[i - 1] + a[i] * i; } } void Compute() { int top = 0; long long ans = 0; for (int i = 1; i <= n; i++) { point temp = point(i - 1, (i - 1) * sum[i - 1] - sum2[i - 1]); while (top > 1 && sgn(getlv(stk[top], temp) - getlv(stk[top - 1], stk[top])) > 0) top--; stk[++top] = temp; int l = 1; int r = top; point a = point(-sum[i], 1); while (l < r) { int m1 = l + (r - l) / 3; int m2 = r - (r - l) / 3; if (dot(a, stk[m1]) < dot(a, stk[m2])) l = m1 + 1; else r = m2 - 1; } ans = max(ans, sum2[i] + dot(a, stk[l])); } printf( %I64d n , ans); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %I64d , &a[i]); init(); Compute(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__DFBBN_BEHAVIORAL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBN_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; int n; int a[210000][3]; set<pair<int, int> > st; int nxt[210000][2]; int x[210000]; vector<pair<int, int> > re; map<long long, int> mp; int pp[210000]; long long hsh(int x, int y, int z) { if (y > z) swap(y, z); if (x > y) swap(x, y); if (y > z) swap(y, z); return ((long long)x << 40) + ((long long)y << 20) + z; } void init() { cin >> n; mp.clear(); st.clear(); re.clear(); for (int i = 0; i < n + 2; i++) nxt[i][0] = nxt[i][1] = 0; pair<int, int> tmp; for (int i = 0; i < n - 2; i++) { scanf( %d%d%d , &a[i][0], &a[i][1], &a[i][2]); mp[hsh(a[i][0], a[i][1], a[i][2])] = i + 1; for (int j = 0; j < 3; j++) { tmp = {a[i][j], a[i][(j + 1) % 3]}; if (tmp.first > tmp.second) swap(tmp.first, tmp.second); if (st.count(tmp)) { st.erase(tmp); re.push_back(tmp); } else st.insert(tmp); } } for (auto p : st) { int x = p.first; int y = p.second; if (nxt[x][0]) nxt[x][1] = y; else nxt[x][0] = y; if (nxt[y][0]) nxt[y][1] = x; else nxt[y][0] = x; } int pos = 1, lst = nxt[pos][0]; int cnt = 1; while (1) { printf( %d , pos); pp[pos] = cnt; x[cnt++] = pos; if (nxt[pos][0] == lst) lst = pos, pos = nxt[pos][1]; else lst = pos, pos = nxt[pos][0]; if (pos == 1) break; } cout << endl; for (int i = 1; i <= n; i++) { nxt[x[i]][0] = x[i - 1]; nxt[x[i]][1] = x[i + 1]; } nxt[x[1]][0] = x[n]; nxt[x[n]][1] = x[1]; } bool cmp(pair<int, int> p1, pair<int, int> p2) { int x1 = pp[p1.second] - pp[p1.first]; int x2 = pp[p2.second] - pp[p2.first]; if (x1 < 0) x1 += n; if (x2 < 0) x2 += n; if (x1 > n / 2) x1 = n - x1; if (x2 > n / 2) x2 = n - x2; return x1 < x2; } bool visit[210000]; void work() { for (int i = 1; i <= n - 2; i++) visit[i] = 1; sort(re.begin(), re.end(), cmp); int t; for (auto p : re) { int x = p.first; int y = p.second; int t; if (nxt[x][0] == nxt[y][1]) { t = nxt[x][0]; nxt[x][0] = y; nxt[y][1] = x; } else { t = nxt[x][1]; nxt[x][1] = y; nxt[y][0] = x; } int xx = mp[hsh(x, y, t)]; cout << xx << ; visit[xx] = 0; } for (int i = 1; i <= n - 2; i++) if (visit[i]) cout << i; cout << endl; } int main() { int t; cin >> t; while (t--) { init(); work(); } return ~~(0 ^ 0 ^ 0); } |
#include <bits/stdc++.h> using namespace std; int x[200005], y[200005], z[200005]; long long a[200005], b[200005]; int main() { long long n, t; cin >> n >> t; x[0] = 0; for (int i = 1; i <= n; i++) { cin >> a[i]; y[i] = 0; } for (int i = 1; i <= n; i++) { cin >> x[i]; y[x[i]]++; z[x[i]] = i; } for (int i = 1; i <= n; i++) { if ((x[i] < i) || (x[i] < x[i - 1])) { cout << No << endl; return 0; } if (y[i] > 0 && z[i] != i) { cout << No << endl; return 0; } } if (x[n] != n) { cout << No << endl; return 0; } for (int i = 1; i < n; i++) if ((a[i + 1] == (a[i] + 1)) && x[i + 1] != x[i] && y[x[i]] > 1) { cout << No << endl; return 0; } for (int i = 1; i <= n; i++) { int m = z[i]; if (y[i] == 1) b[m] = a[m] + t; else { for (int j = 0; j < y[i]; j++) b[m - j] = a[m] + t + 1LL - j; } } cout << Yes << endl; for (int i = 1; i <= n; i++) cout << b[i] << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int arr[10][10]; double me[10][10]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int n = 10; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> arr[i][j]; } } me[0][0] = 0.; me[0][1] = 6.; me[0][2] = 6.; me[0][3] = 6.; me[0][4] = 6.; me[0][5] = 6.; double fix = 1. / 6.; for (int i = 0; i < n; i++) { if (i % 2 == 0) { for (int j = (i == 0) ? 6 : 0; j < n; j++) { double best = 1e6; for (int k = 0; k <= (1 << 6) - 1; k++) { double summ = 1; for (int s = 0; s < 6; s++) { if (((k >> s) & 1) == 1) { int posx = (j - s - 1 >= 0) ? j - s - 1 : n - (((j - s - 1) % 10 + 10) % 10) - 1; int posy = (j - s - 1 >= 0 || i == 0) ? i : i - 1; summ += fix * me[posy - arr[posy][posx]][posx]; } else { int posx = (j - s - 1 >= 0) ? j - s - 1 : n - (((j - s - 1) % 10 + 10) % 10) - 1; int posy = (j - s - 1 >= 0 || i == 0) ? i : i - 1; summ += fix * me[posy][posx]; } } best = min(best, summ); } me[i][j] = best; } } else { for (int j = n - 1; j >= 0; j--) { double best = 1e6; for (int k = 0; k <= (1 << 6) - 1; k++) { double summ = 1; for (int s = 0; s < 6; s++) { if (((k >> s) & 1) == 1) { int posx = (j + s + 1 < n) ? j + s + 1 : n - ((j + s + 1) % 10 + 10) % 10 - 1; int posy = (j + s + 1 < n || i == 0) ? i : i - 1; summ += fix * me[posy - arr[posy][posx]][posx]; } else { int posx = (j + s + 1 < n) ? j + s + 1 : n - ((j + s + 1) % 10 + 10) % 10 - 1; int posy = (j + s + 1 < n || i == 0) ? i : i - 1; summ += fix * me[posy][posx]; } } best = min(best, summ); } me[i][j] = best; } } } cout.precision(9); cout << fixed << me[9][0]; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O22AI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O22AI_BEHAVIORAL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o22ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B2 nor0_out ;
wire B2 nor1_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , B1, B2 );
nor nor1 (nor1_out , A1, A2 );
or or0 (or0_out_Y , nor1_out, nor0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O22AI_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FA_BLACKBOX_V
`define SKY130_FD_SC_HD__FA_BLACKBOX_V
/**
* fa: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FA_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long n, k, cnt[200005], x, y, ans; vector<long long> v[200005]; void dfs(long long pos, long long pre) { long long len = v[pos].size(); for (long long i = 0; i < len; i++) { long long xx = v[pos][i]; if (xx != pre) { dfs(xx, pos); cnt[pos] += cnt[xx]; ans += min(cnt[xx], 2 * k - cnt[xx]); } } } int main() { scanf( %lld%lld , &n, &k); for (long long i = 0; i < 2 * k; i++) { scanf( %lld , &x); cnt[x] = 1; } for (long long i = 0; i < n - 1; i++) { scanf( %lld%lld , &x, &y); v[x].push_back(y); v[y].push_back(x); } dfs(1, 0); printf( %lld n , ans); } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_340_16.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.2 Build 153 07/15/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_340_16 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q);
input aclr;
input clock;
input [339:0] data;
input rdreq;
input wrreq;
output empty;
output [339:0] q;
wire sub_wire0;
wire [339:0] sub_wire1;
wire empty = sub_wire0;
wire [339:0] q = sub_wire1[339:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 340,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "340"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "340"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "340"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 340 0 INPUT NODEFVAL "data[339..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 340 0 OUTPUT NODEFVAL "q[339..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 340 0 data 0 0 340 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 340 0 @q 0 0 340 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_340_16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_340_16.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_340_16.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_340_16.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_340_16_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_340_16_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1024; bool mark[MAXN][MAXN]; int a[MAXN][MAXN], b[MAXN][MAXN]; long long s[MAXN][MAXN]; int main() { int n, m, r, c; vector<pair<long long, pair<int, int> > > v, w; scanf( %d%d%d%d , &n, &m, &r, &c); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { scanf( %d , &a[i][j]); s[i][j] = a[i][j]; } } for (int i = 1; i <= n; ++i) { copy(a[i], a[i] + m + 1, s[i]); partial_sum(s[i], s[i] + m + 1, s[i]); for (int j = 1; j <= m; ++j) { s[i][j] += s[i - 1][j]; } } for (int i = 1; i <= n; ++i) { multiset<int> st; for (int j = 1; j <= m; ++j) { if (j > c) { st.erase(st.find(a[i][j - c])); } st.insert(a[i][j]); b[i][j] = *st.begin(); } } for (int j = 1; j <= m; ++j) { multiset<int> st; for (int i = 1; i <= n; ++i) { if (i > r) { st.erase(st.find(b[i - r][j])); } st.insert(b[i][j]); a[i][j] = *st.begin(); } } for (int i = r; i <= n; ++i) { for (int j = c; j <= m; ++j) { v.push_back(make_pair(s[i][j] - s[i - r][j] - s[i][j - c] + s[i - r][j - c] - r * c * (long long)a[i][j], make_pair(i, j))); } } sort(v.begin(), v.end()); for (int k = 0; k < (int)v.size(); ++k) { int x = v[k].second.first; int y = v[k].second.second; if (mark[x][y]) { continue; } w.push_back(v[k]); for (int i = x - r + 1; i < x + r && i <= n; ++i) { fill(mark[i] + y - c + 1, mark[i] + min(y + c, m + 1), true); } } printf( %d n , (int)w.size()); for (int k = 0; k < (int)w.size(); ++k) { printf( %d %d %I64d n , w[k].second.first - r + 1, w[k].second.second - c + 1, w[k].first); } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_PP_BLACKBOX_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlygate4sd2 (
X ,
A ,
VPWR,
VGND
);
output X ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_PP_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_iobuf #(
parameter DATA_WIDTH = 1) (
input [(DATA_WIDTH-1):0] dio_t,
input [(DATA_WIDTH-1):0] dio_i,
output [(DATA_WIDTH-1):0] dio_o,
inout [(DATA_WIDTH-1):0] dio_p);
genvar n;
generate
for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_iobuf
assign dio_o[n] = dio_p[n];
assign dio_p[n] = (dio_t[n] == 1'b1) ? 1'bz : dio_i[n];
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:07:30 07/02/2014
// Design Name: FONT5_base
// Module Name: H:/Firmware/FONT5_base/ISE13/FONT5_base/font5_base_TB.v
// Project Name: FONT5_base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: FONT5_base
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module font5_base_TB;
//`include "H:\Firmware\FONT5_base\sources\verilog\definitions.vh"
parameter CH1_BITFLIP = (13'b1011010000101 ^ -13'sd4096);
parameter CH2_BITFLIP = (13'b0101110001000 ^ -13'sd4096);
parameter CH4_BITFLIP = (13'b0111100000000 ^ -13'sd4096);
parameter CH5_BITFLIP = (13'b0100110011010 ^ -13'sd4096);
//assign ch3_bitflip = 13'b0001011110100;
// Inputs
reg clk357;
reg clk40;
reg clk40_ibufg;
reg signed [12:0] ch1_data_in_del;
reg signed [12:0] ch2_data_in_del;
reg [12:0] ch3_data_in_del;
reg [12:0] ch4_data_in_del;
reg [12:0] ch5_data_in_del;
reg [12:0] ch6_data_in_del;
reg [12:0] ch7_data_in_del;
reg [12:0] ch8_data_in_del;
reg [12:0] ch9_data_in_del;
reg rs232_in;
reg diginput1;
reg diginput2;
reg dcm200_locked;
reg idelayctrl_rdy;
reg pll_clk357_locked;
reg dcm360_locked;
reg IDDR1_Q1;
reg IDDR1_Q2;
reg IDDR2_Q1;
reg IDDR2_Q2;
reg IDDR3_Q1;
reg IDDR3_Q2;
// Outputs
wire adc_powerdown;
wire [12:0] dac1_out;
wire dac1_clk;
wire [12:0] dac2_out;
wire dac2_clk;
wire rs232_out;
wire led0_out;
wire led1_out;
wire led2_out;
wire trim_cs_ld;
wire trim_sck;
wire trim_sdi;
wire diginput1A;
wire diginput1B;
wire diginput2A;
wire diginput2B;
wire auxOutA;
wire auxOutB;
wire dcm200_rst;
wire clk_blk;
wire clk357_idelay_ce;
wire clk357_idelay_rst;
wire idelay_rst;
wire fastClk_sel;
wire delay_calc_strb1;
wire delay_calc_strb2;
wire delay_calc_strb3;
wire delay_trig1;
wire delay_trig2;
wire delay_trig3;
wire adc1_drdy_delay_ce;
wire adc2_drdy_delay_ce;
wire adc3_drdy_delay_ce;
wire adc1_clk_delay_ce;
wire adc2_clk_delay_ce;
wire adc3_clk_delay_ce;
wire adc1_data_delay_ce;
wire adc2_data_delay_ce;
wire adc3_data_delay_ce;
// Instantiate the Unit Under Test (UUT)
FONT5_base uut (
.clk357(clk357),
.clk40(clk40),
.clk40_ibufg(clk40_ibufg),
.ch1_data_in_del(ch1_data_in_del ^ CH1_BITFLIP),
.ch2_data_in_del(ch2_data_in_del ^ CH2_BITFLIP),
.ch3_data_in_del(ch3_data_in_del),
.ch4_data_in_del(ch4_data_in_del ^ CH4_BITFLIP),
.ch5_data_in_del(ch5_data_in_del ^ CH5_BITFLIP),
.ch6_data_in_del(ch6_data_in_del),
.ch7_data_in_del(ch7_data_in_del),
.ch8_data_in_del(ch8_data_in_del),
.ch9_data_in_del(ch9_data_in_del),
.rs232_in(rs232_in),
.adc_powerdown(adc_powerdown),
.dac1_out(dac1_out),
.dac1_clk(dac1_clk),
.dac2_out(dac2_out),
.dac2_clk(dac2_clk),
.rs232_out(rs232_out),
.led0_out(led0_out),
.led1_out(led1_out),
.led2_out(led2_out),
.trim_cs_ld(trim_cs_ld),
.trim_sck(trim_sck),
.trim_sdi(trim_sdi),
.diginput1A(diginput1A),
.diginput1B(diginput1B),
.diginput1(diginput1),
.diginput2A(diginput2A),
.diginput2B(diginput2B),
.diginput2(diginput2),
.auxOutA(auxOutA),
.auxOutB(auxOutB),
.dcm200_rst(dcm200_rst),
.dcm200_locked(dcm200_locked),
.clk_blk(clk_blk),
.idelayctrl_rdy(idelayctrl_rdy),
.pll_clk357_locked(pll_clk357_locked),
.clk357_idelay_ce(clk357_idelay_ce),
.clk357_idelay_rst(clk357_idelay_rst),
.idelay_rst(idelay_rst),
.dcm360_locked(dcm360_locked),
.fastClk_sel(fastClk_sel),
.delay_calc_strb1(delay_calc_strb1),
.delay_calc_strb2(delay_calc_strb2),
.delay_calc_strb3(delay_calc_strb3),
.delay_trig1(delay_trig1),
.delay_trig2(delay_trig2),
.delay_trig3(delay_trig3),
.adc1_drdy_delay_ce(adc1_drdy_delay_ce),
.adc2_drdy_delay_ce(adc2_drdy_delay_ce),
.adc3_drdy_delay_ce(adc3_drdy_delay_ce),
.adc1_clk_delay_ce(adc1_clk_delay_ce),
.adc2_clk_delay_ce(adc2_clk_delay_ce),
.adc3_clk_delay_ce(adc3_clk_delay_ce),
.adc1_data_delay_ce(adc1_data_delay_ce),
.adc2_data_delay_ce(adc2_data_delay_ce),
.adc3_data_delay_ce(adc3_data_delay_ce),
.IDDR1_Q1(IDDR1_Q1),
.IDDR1_Q2(IDDR1_Q2),
.IDDR2_Q1(IDDR2_Q1),
.IDDR2_Q2(IDDR2_Q2),
.IDDR3_Q1(IDDR3_Q1),
.IDDR3_Q2(IDDR3_Q2)
);
/*integer fid;
reg [12:0] k = 13'd0;
reg [12:0] Mem[0:499], Mem2[0:499];*/
initial begin
// $readmemh("diodeAD.dat", Mem);
// $readmemh("mixer_ad.dat", Mem2);
// fid = $fopen("simOut.dat");
// Initialize Inputs
clk357 = 0;
clk40 = 0;
clk40_ibufg = 0;
ch1_data_in_del = 13'sd0;
ch2_data_in_del = 13'sd0;
ch3_data_in_del = 0;
ch4_data_in_del = 13'sd0;
ch5_data_in_del = 13'sd0;
ch6_data_in_del = 0;
ch7_data_in_del = 0;
ch8_data_in_del = 0;
ch9_data_in_del = 0;
rs232_in = 0;
diginput1 = 0;
diginput2 = 0;
dcm200_locked = 0;
idelayctrl_rdy = 0;
pll_clk357_locked = 0;
dcm360_locked = 0;
IDDR1_Q1 = 0;
IDDR1_Q2 = 0;
IDDR2_Q1 = 0;
IDDR2_Q2 = 0;
IDDR3_Q1 = 0;
IDDR3_Q2 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
#28;
//ch1_data_in_del = 13'sd1000;
//ch2_data_in_del = -13'sd4000;
ch1_data_in_del = 13'sd1000;
ch2_data_in_del = -13'sd128;
ch4_data_in_del = 13'sd500;
ch5_data_in_del = 13'sd63;
//ch1_data_in_del = 13'sd1250;
//ch2_data_in_del = -13'sd250;
#430;
ch1_data_in_del = 13'sd0;
ch2_data_in_del = 13'sd0;
ch4_data_in_del = 13'sd0;
ch5_data_in_del = 13'sd0;
end
initial forever #1.4 clk357 = ~clk357;
/*always @(posedge clk357) begin
ch1_data_in_del <= Mem[k];
ch2_data_in_del <= Mem2[k];
k <= k + 1'b1;
$fwrite(fid,"%h\n", dac1_out);
if (k==13'd499) begin
$fclose(fid);
$finish;
end
end */
endmodule
|
#include <bits/stdc++.h> using namespace std; int dx[] = {0, 0, 1, -1, -1, -1, 1, 1}; int dy[] = {1, -1, 0, 0, -1, 1, 1, -1}; template <class T> inline T biton(T n, T pos) { return n | ((T)1 << pos); } template <class T> inline T bitoff(T n, T pos) { return n & ~((T)1 << pos); } template <class T> inline T ison(T n, T pos) { return (bool)(n & ((T)1 << pos)); } template <class T> inline T gcd(T a, T b) { while (b) { a %= b; swap(a, b); } return a; } template <typename T> string NumberToString(T Number) { ostringstream second; second << Number; return second.str(); } inline int nxt() { int aaa; scanf( %d , &aaa); return aaa; } inline long long int lxt() { long long int aaa; scanf( %lld , &aaa); return aaa; } inline double dxt() { double aaa; scanf( %lf , &aaa); return aaa; } template <class T> inline T bigmod(T p, T e, T m) { T ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % m; p = (p * p) % m; } return (T)ret; } int ar[1000010]; long long F(long long int limit, long long int a, long long int b) { if (limit < a) return 1LL; long long int sum = 1LL; long long int x = 0; while (true) { if (x + a > limit) break; long long int temp = (limit - x) / a; sum += temp; long long int r = (a * temp) + x; if (r - b < 0) break; temp = (r + b - 1) / b; temp--; sum += temp; r -= temp * b; x = r; if (x % a == 0) break; } return sum; } long long int get(long long int st, long long int len) { long long int sum = (len * len + len) / 2LL; sum *= st; return sum; } int main() { ios_base::sync_with_stdio(false); cin.tie(0); long long n, a, b; cin >> n >> a >> b; long long limit = min(a + b - 2, n); long long sum = 0; for (long long i = 0; i <= limit; i++) { sum += F(i, a, b); } limit++; long long int gc = gcd(a, b); while (limit <= n) { if (limit % gc == 0) break; sum += (limit / gc) + 1; limit++; } long long int upperLimit = n; while (upperLimit >= limit) { sum += (upperLimit / gc) + 1; if (upperLimit % gc == 0) break; upperLimit--; } if (upperLimit > limit) { long long int diff = (upperLimit - limit); sum += diff; diff /= gc; long long int chunk = limit * diff + get(gc, diff - 1); sum += chunk; } cout << sum << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T, typename U> ostream& operator<<(ostream& o, const pair<T, U>& x) { o << ( << x.first << , << x.second << ) ; return o; } template <typename T> ostream& operator<<(ostream& o, const vector<T>& x) { o << [ ; int b = 0; for (auto& a : x) o << (b++ ? , : ) << a; o << ] ; return o; } template <typename T> ostream& operator<<(ostream& o, const set<T>& x) { o << { ; int b = 0; for (auto& a : x) o << (b++ ? , : ) << a; o << } ; return o; } template <typename T> ostream& operator<<(ostream& o, const multiset<T>& x) { o << { ; int b = 0; for (auto& a : x) o << (b++ ? , : ) << a; o << } ; return o; } template <typename T> ostream& operator<<(ostream& o, const unordered_set<T>& x) { o << { ; int b = 0; for (auto& a : x) o << (b++ ? , : ) << a; o << } ; return o; } template <typename T> ostream& operator<<(ostream& o, const unordered_multiset<T>& x) { o << { ; int b = 0; for (auto& a : x) o << (b++ ? , : ) << a; o << } ; return o; } template <typename T, typename U> ostream& operator<<(ostream& o, const map<T, U>& x) { o << { ; int b = 0; for (auto& a : x) o << (b++ ? , : ) << a; o << } ; return o; } template <typename T, typename U> ostream& operator<<(ostream& o, const multimap<T, U>& x) { o << { ; int b = 0; for (auto& a : x) o << (b++ ? , : ) << a; o << } ; return o; } template <typename T, typename U> ostream& operator<<(ostream& o, const unordered_map<T, U>& x) { o << { ; int b = 0; for (auto& a : x) o << (b++ ? , : ) << a; o << } ; return o; } template <typename T, typename U> ostream& operator<<(ostream& o, const unordered_multimap<T, U>& x) { o << { ; int b = 0; for (auto& a : x) o << (b++ ? , : ) << a; o << } ; return o; } int main() { ios::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) { int n, k; string s; cin >> n >> k >> s; vector<int> A(n); for (int i = 0; i < n; i++) { if (s[i] == R ) A[i] = 0; if (s[i] == G ) A[i] = 1; if (s[i] == B ) A[i] = 2; } int ans = k; for (int o = 0; o < 3; o++) { int x = 0; for (int i = 0; i < k; i++) { if (A[i] != (o + i) % 3) x++; } ans = min(ans, x); for (int i = k; i < n; i++) { if (A[i - k] != (o + i - k) % 3) x--; if (A[i] != (o + i) % 3) x++; ans = min(ans, x); } } cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int n; cin >> n; if ((n & (n - 1)) == 0) { cout << 0 << n ; } else { int k = 0; while ((1 << k + 1) <= n) { k++; } n ^= 1 << k; int ans = 0; for (int i = 0; i < k; ++i) { int j = i + 1; if (j >= k) { j -= k; } if (n & (1 << j)) { ans |= 1 << i; } } cout << ans << n ; } } |
// ====================================================================
// MAH PONK
//
// Copyright (C) 2007, Viacheslav Slavinsky
// This design and core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
// An open table tennis game for VGA displays.
//
// Author: Viacheslav Slavinsky, http://sensi.org/~svo
//
// Game logic unit. What happens here:
// -- game phases, before start, start, score keeping, endgame
// -- sound generation
// -- LED1 blinking
// All game-related units are instantated here, namely:
// ballscan
// paddlescan
// deflector
// soundnik
// scores
// ballmover
//
// Pins description:
// clk input master clock
// clkdiv8 input slow clock
// gamereset input game reset pulse
// hsync input vga horizontal sync (passed to scores.v)
// realx,realy input x,y screen coordinates
// paddleA_y input paddle A y-coordinate
// paddleB_y input paddle B y-coordinate
// ballAdvance input ball clock
// scans[2:0] output {ball_scan, paddle_scan, score_scan}
// ball_y output ball_y coordinate for Robo-Hand!
// sound output now with 3 sounds!
// led output game status led
module tehgame(clk, clkdiv8, reset, gamereset, hsync, realx, realy, paddleA_y, paddleB_y, ballAdvance, scans, ball_y, sound, led);
parameter SCREENWIDTH = 10'd640;
parameter SCREENHEIGHT = 10'd480;
parameter PADDLESIZE = 10'd64;
parameter BALLSIZE = 8;
input clk, clkdiv8;
input reset;
input gamereset;
input hsync;
input [9:0] realx;
input [9:0] realy;
input [9:0] paddleA_y;
input [9:0] paddleB_y;
input ballAdvance;
output [2:0] scans;
output [9:0] ball_y;
output sound;
output led;
reg [7:0] ledcounter;
reg ledled;
assign led = ledled;
//
// All sound is here.
//
reg [3:0] sfx; // which sound to play
reg keydown; // initiate sound
reg [3:0] sdur; // sound duration in whatevers
always @(posedge clk) begin
keydown = !reset & (collide | wallbounce | outA | outB);
if (keydown) begin
sdur <= 0;
if (collide) sfx <= 0;
else if (wallbounce) sfx <= 1;
else if (outA | outB) begin
sdur <= 1;
sfx <= 2;
end
end
end
soundnik canhassound(clkdiv8, sound, keydown, sfx, sdur);
// - if there was more sound related stuff, it should've been above this line
parameter state0 = 0, state1 = 1, state2 = 2, state3 = 3, state4 = 4, state5 = 5, state6 = 6, state7 = 7;
// Game state, top-level.. Not started, started..
reg[3:0] state;
reg ball_reset; // reset line for ballmover
reg service_side; // 0 = ball served from left part
reg score_reset; // form reset pulse for score counter
reg [11:0] pause; // delay timer/counter
wire[9:0] ball_x; // ball x/y
wire[9:0] ball_y;
// Main state machine. Ph33r it.
always @(posedge ballAdvance or posedge reset or posedge gamereset) begin
if (reset) state <= state5;
else if (gamereset) state <= state0; // this is done by start button
else begin
case (state)
// init game
state0: begin
score_reset <= 1;
service_side <= 0;
ledled <= 1;
//score_addA <= 0;
//score_addB <= 0;
state <= state1;
end
// set ball and wait before the service
state1: begin
score_reset <= 0;
ball_reset <= 1;
pause <= 1024;
state <= state2;
end
// pacing before state3 as defined by state1...
state2: begin
if (pause == 0) begin
ball_reset <= 0;
state <= state3;
end else begin
pause <= pause - 1;
end
end
// game itself, just check for out situations
state3: begin
if (outA | outB) begin
service_side <= outB;
// if score is up, endgame; otherwise new ball
if (scoreA == 8'h21 || scoreB == 8'h21) begin
pause <= 4095;
ball_reset <= 1;
state <= state4;
end else begin
state <= state1;
end
end
end
// endgame, no exit state except for gamereset
state4: begin
ledcounter <= ledcounter - 1;
if (ledcounter == 0) ledled = !ledled;
end
// power-on setup
state5: begin
ball_reset <= 1;
state <= state4;
end
default:
begin
state <= state0;
end
endcase
end
end
// Paddle data:
// _top top y
// _bot bottom y
// Exact coordinates are calculated to avoid complex
// comparisons in screen scanner (see paddlescan.v)
reg[9:0] paddleA_top;
reg[9:0] paddleA_bot;
reg[9:0] paddleB_top;
reg[9:0] paddleB_bot;
always @(posedge clk) begin
paddleA_top <= paddleA_y - PADDLESIZE/2;
paddleA_bot <= paddleA_y + PADDLESIZE/2;
paddleB_top <= paddleB_y - PADDLESIZE/2;
paddleB_bot <= paddleB_y + PADDLESIZE/2;
end
scores scorekeeper(clk, hsync, realx, realy, outB, outA, score_reset, scoreA, scoreB, scans[0]);
//
// Ball movement, collision, deflection
//
wire collideA;
wire collideB;
wire collide = collideA | collideB; // paddle collision
wire[9:0] deflectA; // deflect angles
wire[9:0] deflectB;
wire collisionreset; // collision reset wire
wire [7:0] scoreA; // scores
wire [7:0] scoreB;
collider #(15, 16) colliderA(ballAdvance, ball_x, ball_y, paddleA_top, paddleA_bot, collisionreset, collideA);
collider #(640-32, 16) colliderB(ballAdvance, ball_x, ball_y, paddleB_top, paddleB_bot, collisionreset, collideB);
deflector deflectorA(collideA, ball_y, paddleA_y, deflectA);
deflector deflectorB(collideB, ball_y, paddleB_y, deflectB);
wire outA;
wire outB;
wire wallbounce;
ballmover #(SCREENWIDTH,SCREENHEIGHT,BALLSIZE)
ballmover(clk, ball_reset, ballAdvance, ball_x, ball_y, collide, collisionreset, ({10{collideA}} & deflectA) | ({10{collideB}} & deflectB),
service_side, outA, outB, wallbounce);
wire paddleA_scan, paddleB_scan;
assign scans[1] = paddleA_scan | paddleB_scan;
paddlescan #(PADDLESIZE, 15) paddlescanA(clk, paddleA_top, paddleA_bot, realx, realy, paddleA_scan);
paddlescan #(PADDLESIZE, 640-32) paddlescanB(clk, paddleB_top, paddleB_bot, realx, realy, paddleB_scan);
ballscan #(BALLSIZE) ballscan(clk, realx, realy, ball_x, ball_y, scans[2]);
endmodule
// $Id: tehgame.v,v 1.13 2007/08/27 22:14:52 svo Exp $
|
/*
* Copyright (c) Atomic Rules LLC, Auburn NH., 2009-2010
*
* Atomic Rules LLC
* 287 Chester Road
* Auburn, NH 03032
* United States of America
* Telephone
*
* This file is part of OpenCPI (www.opencpi.org).
* ____ __________ ____
* / __ \____ ___ ____ / ____/ __ \ / _/ ____ _________ _
* / / / / __ \/ _ \/ __ \/ / / /_/ / / / / __ \/ ___/ __ `/
* / /_/ / /_/ / __/ / / / /___/ ____/_/ / _/ /_/ / / / /_/ /
* \____/ .___/\___/_/ /_/\____/_/ /___/(_)____/_/ \__, /
* /_/ /____/
*
* OpenCPI is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* OpenCPI is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with OpenCPI. If not, see <http://www.gnu.org/licenses/>.
*/
// biasWorker.v - hand coded verilog of biasWorker
// 2009-07-11 ssiegel creation
// 2010-01-19 ssiegel VHDL manually converted to Verilog
// 2010-03-01 ssiegel Added Peer-Peer WSI Resets
// 2010-06-26 jkulp Made compliant with ocpi component workflow
`include "bias_impl.v"
// All outputs are registered except those that are aliased (that have WIP semantics)
// Someday we might be more clever and allow combi outputs.
reg ctl_SData, ctl_SThreadBusy, ctl_SResp;
reg out_MData;// not part of request, so not automatically declared.
reg [31:0] biasValue;
reg [2:0] ctl_ctlSt;
// When this worker is WCI reset, propagate reset out to WSI partners...
assign out_MReset_n = ctl_MReset_n;
assign in_SReset_n = ctl_MReset_n;
//Pass the SThreadBusy upstream without pipelining...
assign in_SThreadBusy = (out_SThreadBusy || (ctl_ctlSt!=2'h2));
always@(posedge ctl_Clk)
begin
// Registered Operations that don't care about reset...
if (ctl_ctlSt == 2'h2) begin // Implement the biasWorker function when operating...
out_MData = in_MData + biasValue; // add the bias
out_MCmd = in_MCmd;
end else begin // Or block the WSI pipeline cleanly...
out_MData = 0;
out_MCmd = 3'h0; // Idle
end
// Pass through signals of the WSI interface that we maintain, but do not use...
out_MReqLast = in_MReqLast;
out_MBurstPrecise = in_MBurstPrecise;
out_MBurstLength = in_MBurstLength;
out_MByteEn = in_MByteEn;
out_Opcode = in_Opcode;
// Implement minimal WCI attach logic...
ctl_SThreadBusy = 1'b0;
ctl_SResp = 2'b0;
if (ctl_MReset_n==1'b0) begin // Reset Conditions...
ctl_ctlSt = 3'h0;
ctl_SResp = 2'h0;
ctl_SThreadBusy = 2'b1;
ctl_Attention = 1'b0;
biasValue = 32'h0000_0000;
end else begin // When not Reset...
// WCI Configuration Property Writes...
if (ctl_IsCfgWrite) begin
biasValue = ctl_MData; // Write the biasValue Configuration Property
ctl_SResp = 2'h1;
end
// WCI Configuration Property Reads...
if (ctl_IsCfgRead) begin
ctl_SData = biasValue; // Read the biasValue Configuration Property
ctl_SResp = 2'h1;
end
//WCI Control Operations...
if (ctl_IsControlOp) begin
case (ctl_ControlOp)
OCPI_WCI_INITIALIZE: ctl_ctlSt = 3'h1; // when wciCtlOp_Initialize => ctl_ctlSt <= wciCtlSt_Initialized;
OCPI_WCI_START: ctl_ctlSt = 3'h2; // when wciCtlOp_Start => ctl_ctlSt <= wciCtlSt_Operating;
OCPI_WCI_STOP: ctl_ctlSt = 3'h3; // when wciCtlOp_Stop => ctl_ctlSt <= wciCtlSt_Suspended;
OCPI_WCI_RELEASE: ctl_ctlSt = 3'h0; // when wciCtlOp_Release => ctl_ctlSt <= wciCtlSt_Exists;
endcase
ctl_SData = 32'hC0DE_4201; // FIXME remove this when we are sure OCCP does the right thing
ctl_SResp = OCPI_OCP_SRESP_DVA;
end // end of control op clause
end // end of not reset clause
end // end of always block
endmodule
// Type definitions from VHDL...
//subtype wciCtlOpT is std_logic_vector(2 downto 0);
//constant wciCtlOp_Initialize : wciCtlOpT := "000";
//constant wciCtlOp_Start : wciCtlOpT := "001";
//constant wciCtlOp_Stop : wciCtlOpT := "010";
//constant wciCtlOp_Release : wciCtlOpT := "011";
//constant wciCtlOp_Test : wciCtlOpT := "100";
//constant wciCtlOp_BeforeQuery : wciCtlOpT := "101";
//constant wciCtlOp_AfterConfig : wciCtlOpT := "110";
//constant wciCtlOp_Rsvd7 : wciCtlOpT := "111";
//subtype wciCtlStT is std_logic_vector(2 downto 0);
//constant wciCtlSt_Exists : wciCtlStT := "000";
//constant wciCtlSt_Initialized : wciCtlStT := "001";
//constant wciCtlSt_Operating : wciCtlStT := "010";
//constant wciCtlSt_Suspended : wciCtlStT := "011";
//constant wciCtlSt_Unusable : wciCtlStT := "100";
//constant wciCtlSt_Rsvd5 : wciCtlStT := "101";
//constant wciCtlSt_Rsvd6 : wciCtlStT := "110";
//constant wciCtlSt_Rsvd7 : wciCtlStT := "111";
//subtype wciRespT is std_logic_vector(31 downto 0);
//constant wciResp_OK : wciRespT := X"C0DE_4201";
//constant wciResp_Error : wciRespT := X"C0DE_4202";
//constant wciResp_Timeout : wciRespT := X"C0DE_4203";
//constant wciResp_Reset : wciRespT := X"C0DE_4204";
//subtype ocpCmdT is std_logic_vector(2 downto 0);
//constant ocpCmd_IDLE : ocpCmdT := "000";
//constant ocpCmd_WR : ocpCmdT := "001";
//constant ocpCmd_RD : ocpCmdT := "010";
//subtype ocpRespT is std_logic_vector(1 downto 0);
//constant ocpResp_NULL : ocpRespT := "00";
//constant ocpResp_DVA : ocpRespT := "01";
//constant ocpResp_FAIL : ocpRespT := "10";
//constant ocpResp_ERR : ocpRespT := "11";
|
// Copyright 2020 The XLS Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Implements a UART transmitter with a single start bit, a single stop bit,
// and 8 bits of data payload. Intended for use with the Lattice ICE40.
// The number of clock ticks within a single baud transfer time.
//
// Default value is 12MHz/9600 = 1250
//
// We define this with a `define so that wrapping modules can refer to it
// without duplication (it does not appear possible to refer to a module's
// default parameter value).
`ifndef DEFAULT_CLOCKS_PER_BAUD
`define DEFAULT_CLOCKS_PER_BAUD 1250
`endif
// Interacting with the transmitter:
//
// * tx_byte_valid signals that the contents of tx_byte should be used for the
// transfer.
// * After the user asserts tx_byte_valid, then tx_byte must be held constant
// until tx_byte_done is asserted by the transmitter.
// * Once tx_byte_done has been asserted by the transmitter, the user only
// needs to signal the new tx_byte (along with tx_byte_valid) for a single
// cycle.
// * Implementation note: internally the FSM can transition straight from
// sending the stop bit for the previous byte into sending the next tx_byte.
module uart_transmitter(
input wire clk,
input wire rst_n,
input wire [7:0] tx_byte,
input wire tx_byte_valid,
output wire tx_byte_done_out,
output wire tx_out
);
parameter ClocksPerBaud = `DEFAULT_CLOCKS_PER_BAUD;
// Before we transition to a new state we prime the "countdown" (in
// tx_countdown) to stay in that state until the next transition action
// should occur.
localparam CountdownBits = $clog2(ClocksPerBaud);
localparam CountdownStart = ClocksPerBaud-1;
localparam
StateIdle = 'd0,
StateStart = 'd1,
StateFrame = 'd2,
StateStop = 'd3;
localparam StateBits = 2;
reg tx = 1;
reg tx_byte_done = 1;
reg [StateBits-1:0] tx_state = StateIdle;
reg [CountdownBits-1:0] tx_countdown = 0;
reg [2:0] tx_bitno = 0;
reg tx_next;
reg tx_byte_done_next;
reg [StateBits-1:0] tx_state_next;
reg [CountdownBits-1:0] tx_countdown_next;
reg [2:0] tx_bitno_next;
assign tx_out = tx;
assign tx_byte_done_out = tx_byte_done;
// State manipulation.
always @(*) begin // verilog_lint: waive always-comb b/72410891
tx_state_next = tx_state;
case (tx_state)
StateIdle: begin
if (tx_byte_valid || !tx_byte_done) begin
tx_state_next = StateStart;
end
end
StateStart: begin
if (tx_countdown == 0) begin
tx_state_next = StateFrame;
end
end
StateFrame: begin
if (tx_countdown == 0 && tx_bitno == 7) begin
tx_state_next = StateStop;
end
end
StateStop: begin
if (tx_countdown == 0) begin
// We permit a transition directly from "stop" to "start" if the
// outside world presented a byte to transmit during the stop bit.
tx_state_next = tx_byte_done ? StateIdle : StateStart;
end
end
default: begin
tx_state_next = 1'bX;
end
endcase
end
// Non-state updates.
always @(*) begin // verilog_lint: waive always-comb b/72410891
tx_next = tx;
tx_byte_done_next = tx_byte_done;
tx_bitno_next = tx_bitno;
tx_countdown_next = tx_countdown;
case (tx_state)
StateIdle: begin
tx_next = 1;
tx_bitno_next = 0;
tx_countdown_next = CountdownStart;
tx_byte_done_next = !tx_byte_valid;
end
StateStart: begin
tx_next = 0; // Start bit signal.
tx_byte_done_next = 0;
tx_bitno_next = 0;
tx_countdown_next = tx_countdown == 0 ? CountdownStart : tx_countdown - 1;
end
StateFrame: begin
tx_next = tx_byte[tx_bitno];
tx_byte_done_next = tx_countdown == 0 && tx_bitno == 7;
tx_bitno_next = tx_countdown == 0 ? tx_bitno + 1 : tx_bitno;
tx_countdown_next = tx_countdown == 0 ? CountdownStart : tx_countdown - 1;
end
StateStop: begin
tx_next = 1; // Stop bit signal.
// The byte is done, unless a new valid byte has been presented.
// When a new byte is presented the state is sticky so the outside
// world doesn't need to assert tx_byte_valid for longer than a cycle.
tx_byte_done_next = (tx_byte_done == 0 || tx_byte_valid == 1) ? 0 : 1;
tx_countdown_next = tx_countdown == 0 ? CountdownStart : tx_countdown - 1;
end
default: begin
tx_next = 1'bX;
tx_byte_done_next = 1'bX;
tx_bitno_next = 1'bX;
tx_countdown_next = 1'bX;
end
endcase
end
// Note: our version of iverilog has no support for always_ff.
always @ (posedge clk) begin
if (rst_n == 0) begin
tx <= 1;
tx_byte_done <= 1;
tx_state <= StateIdle;
tx_countdown <= 0;
tx_bitno <= 0;
end else begin
tx <= tx_next;
tx_byte_done <= tx_byte_done_next;
tx_state <= tx_state_next;
tx_countdown <= tx_countdown_next;
tx_bitno <= tx_bitno_next;
end
end
endmodule
|
module alt_mem_ddrx_fifo
# (
parameter
CTL_FIFO_DATA_WIDTH = 8,
CTL_FIFO_ADDR_WIDTH = 3
)
(
// general
ctl_clk,
ctl_reset_n,
// pop free fifo entry
get_valid,
get_ready,
get_data,
// push free fifo entry
put_valid,
put_ready,
put_data
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CTL_FIFO_DEPTH = (2 ** CTL_FIFO_ADDR_WIDTH);
localparam CTL_FIFO_TYPE = "SCFIFO"; // SCFIFO, CUSTOM
// -----------------------------
// port declaration
// -----------------------------
input ctl_clk;
input ctl_reset_n;
// pop free fifo entry
input get_ready;
output get_valid;
output [CTL_FIFO_DATA_WIDTH-1:0] get_data;
// push free fifo entry
output put_ready;
input put_valid;
input [CTL_FIFO_DATA_WIDTH-1:0] put_data;
// -----------------------------
// port type declaration
// -----------------------------
wire get_valid;
wire get_ready;
wire [CTL_FIFO_DATA_WIDTH-1:0] get_data;
wire put_valid;
wire put_ready;
wire [CTL_FIFO_DATA_WIDTH-1:0] put_data;
// -----------------------------
// signal declaration
// -----------------------------
reg [CTL_FIFO_DATA_WIDTH-1:0] fifo [CTL_FIFO_DEPTH-1:0];
reg [CTL_FIFO_DEPTH-1:0] fifo_v;
wire fifo_get;
wire fifo_put;
wire fifo_empty;
wire fifo_full;
wire zero;
// -----------------------------
// module definition
// -----------------------------
assign fifo_get = get_valid & get_ready;
assign fifo_put = put_valid & put_ready;
assign zero = 1'b0;
generate
begin : gen_fifo_instance
if (CTL_FIFO_TYPE == "SCFIFO")
begin
assign get_valid = ~fifo_empty;
assign put_ready = ~fifo_full;
scfifo #(
.add_ram_output_register ( "ON" ),
.intended_device_family ( "Stratix IV" ),
.lpm_numwords ( CTL_FIFO_DEPTH ),
.lpm_showahead ( "ON" ),
.lpm_type ( "scfifo" ),
.lpm_width ( CTL_FIFO_DATA_WIDTH ),
.lpm_widthu ( CTL_FIFO_ADDR_WIDTH ),
.overflow_checking ( "OFF" ),
.underflow_checking ( "OFF" ),
.use_eab ( "ON" )
) scfifo_component (
.aclr (~ctl_reset_n),
.clock (ctl_clk),
.data (put_data),
.rdreq (fifo_get),
.wrreq (fifo_put),
.empty (fifo_empty),
.full (fifo_full),
.q (get_data),
.almost_empty (),
.almost_full (),
.sclr (zero),
.usedw ()
);
end
else // CTL_FIFO_TYPE == "CUSTOM"
begin
assign get_valid = fifo_v[0];
assign put_ready = ~fifo_v[CTL_FIFO_DEPTH-1];
assign get_data = fifo[0];
// put & get management
integer i;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
for (i = 0; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
// initialize every entry
fifo [i] <= 0;
fifo_v [i] <= 1'b0;
end
end
else
begin
// get request code must be above put request code
if (fifo_get)
begin
// on a get request, fifo entry is shifted to move next entry to head
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
fifo_v [i-1] <= fifo_v [i];
fifo [i-1] <= fifo [i];
end
fifo_v [CTL_FIFO_DEPTH-1] <= 0;
end
if (fifo_put)
begin
// on a put request, next empty fifo entry is written
if (~fifo_get)
begin
// put request only
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
if ( fifo_v[i-1] & ~fifo_v[i])
begin
fifo_v [i] <= 1'b1;
fifo [i] <= put_data;
end
end
if (~fifo_v[0])
begin
fifo_v [0] <= 1'b1;
fifo [0] <= put_data;
end
end
else
begin
// put & get request on same cycle
for (i = 1; i < CTL_FIFO_DEPTH; i = i + 1'b1)
begin
if ( fifo_v[i-1] & ~fifo_v[i])
begin
fifo_v [i-1] <= 1'b1;
fifo [i-1] <= put_data;
end
end
if (~fifo_v[0])
begin
$display("error - fifo underflow");
end
end
end
end
end
end
end
endgenerate
endmodule
//
// ASSERT
//
// fifo underflow
//
|
#include <bits/stdc++.h> using namespace std; long long MOD = 1000000007; long double EPS = 1e-9; long long binpow(long long b, long long p, long long mod) { long long ans = 1; b %= mod; for (; p; p >>= 1) { if (p & 1) ans = ans * b % mod; b = b * b % mod; } return ans; } void pre() {} namespace GetPrimitve { vector<long long> Divisors; vector<long long> Divisor(long long x) { vector<long long> ans; for (long long i = 2; i * i <= x; i++) { if (x % i == 0) { ans.emplace_back(i); while (x % i == 0) x /= i; } } if (x > 1) ans.emplace_back(x); return ans; } bool check(int prim, int p, vector<long long> &divs) { for (auto v : divs) { if (binpow(prim, (p - 1) / v, p) == 1) return 0; } return 1; } int getRoot(int p) { int ans = 2; vector<long long> divs = Divisor(p - 1); while (!check(ans, p, divs)) ans++; return ans; } }; // namespace GetPrimitve const long long MAXB = 1 << 21; using polybase = long long; polybase A[MAXB], B[MAXB], C[MAXB]; template <long long NTTMOD, long long PRIMITIVE_ROOT> struct POLYMUL { long long modInv(long long a) { return a <= 1 ? a : (long long)(NTTMOD - NTTMOD / a) * modInv(NTTMOD % a) % NTTMOD; } void NTT(polybase P[], long long n, long long oper) { for (int i = 1, j = 0; i < n - 1; i++) { for (int s = n; j ^= s >>= 1, ~j & s;) ; if (i < j) swap(P[i], P[j]); } for (int d = 0; (1 << d) < n; d++) { int m = 1 << d, m2 = m * 2; long long unit_p0 = ::binpow(PRIMITIVE_ROOT, (NTTMOD - 1) / m2, NTTMOD); if (oper < 0) unit_p0 = modInv(unit_p0); for (int i = 0; i < n; i += m2) { polybase unit = 1; for (int j = 0; j < m; j++) { polybase &P1 = P[i + j + m], &P2 = P[i + j]; polybase t = unit * P1 % NTTMOD; P1 = (P2 - t + NTTMOD) % NTTMOD; P2 = (P2 + t) % NTTMOD; unit = unit * unit_p0 % NTTMOD; } } } } vector<polybase> mul(const vector<polybase> &a, const vector<polybase> &b) { vector<polybase> ret( max(0LL, (long long)a.size() + (long long)b.size() - 1), 0); int len = 1; while (len < (long long)ret.size()) len <<= 1; for (int i = 0; i < len; i++) A[i] = i < (int)a.size() ? a[i] : 0; for (int i = 0; i < len; i++) B[i] = i < (int)b.size() ? b[i] : 0; NTT(A, len, 1); NTT(B, len, 1); for (long long i = 0; i < len; i++) C[i] = (polybase)A[i] * B[i] % NTTMOD; NTT(C, len, -1); for (long long i = 0, inv = modInv(len); i < (long long)ret.size(); i++) ret[i] = (long long)C[i] * inv % NTTMOD; return ret; } vector<long long> binpow(vector<long long> b, long long p) { vector<long long> ans = vector<long long>(1, 1); for (; p; p >>= 1) { if (p & 1) ans = mul(ans, b); b = mul(b, b); } return ans; } vector<long long> calc(vector<long long> &arr, int l, int r) { if (l == r) { return {}; } int mid = (l + r) >> 1; vector<long long> x = calc(arr, l, mid), y = calc(arr, mid + 1, r); return mul(x, y); } }; POLYMUL<998244353, 3> ntt1; POLYMUL<943718401, 7> ntt2; POLYMUL<950009857, 7> ntt3; POLYMUL<962592769, 7> ntt4; POLYMUL<975175681, 17> ntt5; long long possible[1000100]; long long lappos[1000100]; void solve() { long long n, x, y; cin >> n >> x >> y; vector<long long> arr(n + 1); for (long long i = 0; i < (n + 1); ++i) { cin >> arr[i]; } vector<long long> arr2 = arr; for (long long i = 0; i < (n + 1); ++i) { arr2[i] = -arr2[i]; arr2[i] += x; } vector<long long> poly1(x + 1); vector<long long> poly2(x + 1); for (auto v : arr) { poly1[v] = 1; } for (auto v : arr2) { poly2[v] = 1; } vector<long long> pp1 = ntt2.mul(poly1, poly2); vector<long long> pp2 = ntt3.mul(poly1, poly2); for (long long i = x + 1; i <= 2 * x; ++i) { if (pp1[i] > 0 || pp2[i] > 0) { possible[i - x] = 1; } } assert(possible[x] == 1); memset(lappos, -1, sizeof(lappos)); for (long long i = 1; i <= 1000000; ++i) { if (possible[i]) { if (2 * (i + y) <= 1000000) { lappos[2 * (i + y)] = 2 * (i + y); } } } for (long long i = 1; i <= 1000000; ++i) { for (long long j = 2 * i; j <= 1000000; j += i) { (lappos[j] = max((lappos[j]), (lappos[i]))); } } long long q; cin >> q; for (long long i = 0; i < (q); ++i) { long long x; cin >> x; cout << lappos[x] << ; } cout << n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); pre(); long long _t = 1; srand(time(0)); for (long long i = 1; i <= _t; i++) { solve(); } } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const long long mod = 1e9 + 7; const long long inf = 1e9 + 7; vector<vector<int> > g; vector<bool> used; int main() { int n, m; cin >> n >> m; g.resize(n); used.resize(n, false); for (int i = 0; i < m; ++i) { int u, v; cin >> u >> v; u--, v--; g[u].push_back(v); g[v].push_back(u); } set<int> q; q.insert(0); used[0] = true; while (!q.empty()) { int u = *q.begin(); q.erase(q.begin()); cout << u + 1 << ; for (auto v : g[u]) if (!used[v]) { q.insert(v); used[v] = true; } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2_4_V
`define SKY130_FD_SC_HS__AND2_4_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and2_4 (
X ,
A ,
B ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
sky130_fd_sc_hs__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__and2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2_4_V
|
#include <bits/stdc++.h> using namespace std; bool seen[100005], x[100005]; vector<int> g[100005], ans; inline void add(int u) { ans.push_back(u + 1), x[u] ^= 1; } void dfs(int u, int p) { seen[u] = true; add(u); for (auto v : g[u]) if (v != p && !seen[v]) dfs(v, u), add(u); if (x[u]) { if (p != -1) add(p), add(u); else x[u] = 0, ans.pop_back(); } } int main() { int n, m; scanf( %d%d , &n, &m); for (auto i = (0); i < m; i++) { int u, v; scanf( %d%d , &u, &v); u--, v--; g[u].push_back(v), g[v].push_back(u); } for (auto i = (0); i < n; i++) scanf( %d , x + i); for (auto i = (0); i < n; i++) if (x[i]) { dfs(i, -1); break; } for (auto i = (0); i < n; i++) if (x[i]) { printf( -1 ); return 0; } printf( %d n , ans.size()); for (auto u : ans) printf( %d , u); return 0; } |
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