text stringlengths 59 71.4k |
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`define RegBankP4_NOP 4'h0
`define RegBankP4_LD0 4'h1
`define RegBankP4_LD1 4'h2
`define RegBankP4_LD2 4'h3
`define RegBankP4_LD3 4'h4
`define RegBankP4_State_Reset 2'h0
`define RegBankP4_State_Ready 2'h1
`define RegBankP4_State_Error 2'h2
module RegBankP4(clock,reset,inst,inst_en,out_0,out_1,out_2,out_3);
input wire clock;
input wire reset;
input wire [11:0] inst;
input wire inst_en;
output wire [7:0] out_0;
output wire [7:0] out_1;
output wire [7:0] out_2;
output wire [7:0] out_3;
reg [1:0] s_State;
reg [7:0] s_Reg0;
reg [7:0] s_Reg1;
reg [7:0] s_Reg2;
reg [7:0] s_Reg3;
wire [3:0] w_InstCode;
wire [7:0] w_InstImm;
reg [256*8-1:0] d_Input;
reg [256*8-1:0] d_State;
assign out_0 = s_Reg0;
assign out_1 = s_Reg1;
assign out_2 = s_Reg2;
assign out_3 = s_Reg3;
assign w_InstCode = inst[11:8];
assign w_InstImm = inst[7:0];
always @ (posedge clock) begin
if (reset) begin
s_State <= `RegBankP4_State_Reset;
s_Reg0 <= 0;
s_Reg1 <= 0;
s_Reg2 <= 0;
s_Reg3 <= 0;
end
else begin
case (s_State)
`RegBankP4_State_Reset: begin
s_State <= `RegBankP4_State_Ready;
s_Reg0 <= 0;
s_Reg1 <= 0;
s_Reg2 <= 0;
s_Reg3 <= 0;
end
`RegBankP4_State_Ready: begin
if (inst_en) begin
case (w_InstCode)
`RegBankP4_NOP: begin
s_State <= `RegBankP4_State_Ready;
s_Reg0 <= s_Reg0;
s_Reg1 <= s_Reg1;
s_Reg2 <= s_Reg2;
s_Reg3 <= s_Reg3;
end
`RegBankP4_LD0: begin
s_State <= `RegBankP4_State_Ready;
s_Reg0 <= w_InstImm;
s_Reg1 <= s_Reg1;
s_Reg2 <= s_Reg2;
s_Reg3 <= s_Reg3;
end
`RegBankP4_LD1: begin
s_State <= `RegBankP4_State_Ready;
s_Reg0 <= s_Reg0;
s_Reg1 <= w_InstImm;
s_Reg2 <= s_Reg2;
s_Reg3 <= s_Reg3;
end
`RegBankP4_LD2: begin
s_State <= `RegBankP4_State_Ready;
s_Reg0 <= s_Reg0;
s_Reg1 <= s_Reg1;
s_Reg2 <= w_InstImm;
s_Reg3 <= s_Reg3;
end
`RegBankP4_LD3: begin
s_State <= `RegBankP4_State_Ready;
s_Reg0 <= s_Reg0;
s_Reg1 <= s_Reg1;
s_Reg2 <= s_Reg2;
s_Reg3 <= w_InstImm;
end
default: begin
s_State <= `RegBankP4_State_Error;
s_Reg0 <= 0;
s_Reg1 <= 0;
s_Reg2 <= 0;
s_Reg3 <= 0;
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
s_State <= `RegBankP4_State_Ready;
s_Reg0 <= s_Reg0;
s_Reg1 <= s_Reg1;
s_Reg2 <= s_Reg2;
s_Reg3 <= s_Reg3;
end // else: !if(inst_en)
end // case: `RegBankP4_State_Ready
`RegBankP4_State_Error: begin
s_State <= `RegBankP4_State_Error;
s_Reg0 <= 0;
s_Reg1 <= 0;
s_Reg2 <= 0;
s_Reg3 <= 0;
end
default: begin
s_State <= `RegBankP4_State_Error;
s_Reg0 <= 0;
s_Reg1 <= 0;
s_Reg2 <= 0;
s_Reg3 <= 0;
end
endcase // case (s_State)
end // else: !if(reset)
end // always @ (posedge clock)
`ifdef SIM
always @ * begin
if (inst_en) begin
case (w_InstCode)
`RegBankP4_NOP: begin
$sformat(d_Input,"EN NOP");
end
`RegBankP4_LD0: begin
$sformat(d_Input,"EN (LD0 %2X)",w_InstImm);
end
`RegBankP4_LD1: begin
$sformat(d_Input,"EN (LD1 %2X)",w_InstImm);
end
`RegBankP4_LD2: begin
$sformat(d_Input,"EN (LD2 %2X)",w_InstImm);
end
`RegBankP4_LD3: begin
$sformat(d_Input,"EN (LD3 %2X)",w_InstImm);
end
default: begin
$sformat(d_Input,"EN (? %2X)",w_InstImm);
end
endcase // case (w_InstCode)
end // if (inst_en)
else begin
$sformat(d_Input,"NN");
end // else: !if(inst_en)
end // always @ *
always @ * begin
case (s_State)
`RegBankP4_State_Reset: begin
$sformat(d_State,"X");
end
`RegBankP4_State_Ready: begin
$sformat(d_State,"R %2X %2X %2X %2X",s_Reg0,s_Reg1,s_Reg2,s_Reg3);
end
`RegBankP4_State_Error: begin
$sformat(d_State,"E");
end
default: begin
$sformat(d_State,"?");
end
endcase // case (s_State)
end // always @ *
`endif // `ifdef SIM
endmodule // RegBankP4
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; if (n % 47 == 0 || n % 744 == 0 || n % 4 == 0 || n % 7 == 0 || n % 44 == 0 || n % 444 == 0 || n % 777 == 0 || n % 74 == 0 || n % 447 == 0 || n % 474 == 0 || n % 477 == 0) { cout << YES ; } else { cout << NO ; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:55:21 04/14/2015
// Design Name:
// Module Name: BCD7segment
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module BCD7segment(
input [3:0] IN,
input select,
output reg [6:0] OUT
);
always @ (IN or select)
begin
if(select)
begin
case (IN)
0: OUT = 7'b0000001;
1: OUT = 7'b1001111;
2: OUT = 7'b0010010;
3: OUT = 7'b0000110;
4: OUT = 7'b1001100;
5: OUT = 7'b0100100;
6: OUT = 7'b0100000;
7: OUT = 7'b0001111;
8: OUT = 7'b0000000;
9: OUT = 7'b0000100;
10: OUT = 7'b0001000;
11: OUT = 7'b0000000;
12: OUT = 7'b0110001;
13: OUT = 7'b0000001;
14: OUT = 7'b0110000;
15: OUT = 7'b0111000;
endcase
end
else
OUT = 7'b1111110;
end
// 4 enable switches //
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long inf = (long long)1e18; const long long mod = (long long)1e9 + 7; const double eps = (double)1e-9; const double pi = acos(-1.0); const int dx[] = {0, 0, 1, 0, -1}; const int dy[] = {0, 1, 0, -1, 0}; const int N = 300500; int n, dp[N]; vector<int> g[N], l; vector<pair<int, int> > gr, G, ga[N]; void dfs(int v, int pr = -1) { dp[v] = 1; for (int to : g[v]) { if (to != pr) { dfs(to, v); dp[v] += dp[to]; } } } int dfs1(int v) { for (int to : g[v]) { if (dp[to] * 2 > n) { dp[v] -= dp[to]; dp[to] += dp[v]; return dfs1(to); } } return v; } void dfs2(int v, int pr, int gl = 0) { gr.push_back(make_pair(gl, v)); for (int to : g[v]) { if (to != pr) { dfs2(to, v, gl + 1); } } } void checkv(int st) { gr.clear(); dfs2(st, -1, 0); sort(gr.begin(), gr.end()); for (int i = 0; i + 1 < n; ++i) { if (gr[i].first == gr[i + 1].first && (int)g[gr[i].second].size() != (int)g[gr[i + 1].second].size()) return; } cout << st << endl; exit(0); } int main() { cin.tie(NULL); cout.tie(NULL); ios_base::sync_with_stdio(false); cin >> n; for (int i = 1; i < n; ++i) { int x, y; cin >> x >> y; g[x].push_back(y); g[y].push_back(x); } dfs(1); int centroid = dfs1(1); checkv(centroid); for (int i = 1; i <= n; ++i) if ((int)g[i].size() == 1) l.push_back(i); for (int x : l) { int last = x; int cur = g[x][0]; int dist = 1; while ((int)g[cur].size() == 2) { int nxt = g[cur][0]; if (nxt == last) nxt = g[cur][1]; dist++; last = cur; cur = nxt; } if (dist == n - 1) { checkv(x); cout << -1; return 0; } ga[cur].push_back(make_pair(x, dist)); G.push_back(make_pair(dist, x)); } for (int i = 1; i <= n; ++i) { if ((int)ga[i].size() == 1) { checkv(ga[i][0].first); cout << -1; return 0; } } for (int i = 0; i + 1 < (int)G.size(); ++i) if (G[i].first != G[i + 1].first) { checkv(G[i].second); checkv(G[i + 1].second); cout << -1; return 0; } cout << -1 << endl; return 0; return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_ps/sky130_fd_sc_hd__udp_dff_ps.v"
`celldefine
module sky130_fd_sc_hd__sdfsbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_hd__udp_dff$PS `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, SET);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSBP_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int main() { long long t; cin >> t; while (t--) { long long n; cin >> n; long long k = (n + 1) / 2; k = k - 1; long long ans = 0; for (long long i = 1; i <= k; ++i) { ans += 8 * i * i; } cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 5; long long INF = 1e18; int n, s; vector<int> ans; long long ansV = 0; long long dis[N]; int edge[N], val[N]; vector<pair<int, int> > adj[N]; void solve() { for (int i = 1; i <= n; i++) dis[i] = INF; priority_queue<pair<long long, int>, vector<pair<long long, int> >, greater<pair<long long, int> > > pq; dis[s] = 0; pq.push({dis[s], s}); while (!pq.empty()) { int u = pq.top().second; long long Cost = pq.top().first; pq.pop(); if (Cost > dis[u]) continue; if (u != s) { ans.push_back(edge[u]); ansV += val[edge[u]]; } for (auto P : adj[u]) { int v = P.first, idx = P.second; if (Cost + val[idx] < dis[v]) { dis[v] = Cost + val[idx]; edge[v] = idx; pq.push({dis[v], v}); } else if (Cost + val[idx] == dis[v] && val[idx] < val[edge[v]]) edge[v] = idx; } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int m; cin >> n >> m; for (int i = 0; i < m; i++) { int u, v; cin >> u >> v >> val[i]; adj[u].push_back({v, i}); adj[v].push_back({u, i}); } cin >> s; solve(); sort(ans.begin(), ans.end()); cout << ansV << endl; for (auto v : ans) cout << v + 1 << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n; bool check(vector<vector<char>>& v, int x, int y) { if (x + 2 >= 0 && y - 1 >= 0 && y + 1 < n && v[x + 1][y] == # && v[x + 2][y] == # && v[x + 1][y + 1] == # && v[x + 1][y - 1] == # ) { v[x][y] = v[x + 1][y] = v[x + 2][y] = v[x + 1][y + 1] = v[x + 1][y - 1] = . ; return true; } if (y + 2 < n && x - 1 >= 0 && x + 1 < n && v[x][y + 1] == # && v[x][y + 2] == # && v[x - 1][y + 1] == # && v[x + 1][y + 1] == # ) { v[x][y] = v[x][y + 1] = v[x][y + 2] = v[x - 1][y + 1] = v[x + 1][y + 1] = . ; return true; } return false; } void print(vector<vector<char>> v) { for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cout << v[i][j]; } cout << endl; } } int main() { cin >> n; vector<vector<char>> v(n, vector<char>(n)); for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { cin >> v[i][j]; } } if (v[0][0] == # || v[n - 1][0] == # || v[0][n - 1] == # || v[n - 1][n - 1] == # ) { cout << NO ; return 0; } int x, y; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) { if (v[i][j] == # ) { if (!check(v, i, j)) { cout << NO ; return 0; } } } } cout << YES ; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dff$PS_pp$PG$N (
Q ,
D ,
CLK ,
SET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input SET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PS_PP_PG_N_BLACKBOX_V
|
module main;
wire [7:0] bus;
reg [7:0] HiZ;
assign bus = HiZ;
reg E;
reg D;
reg CLK;
BUFT drv (bus[0], D, E, CLK);
bufif0 drv0 (bus[0], D, E);
initial begin
HiZ = 8'hzz;
D = 1;
E = 1;
CLK = 0;
#1 CLK = 1;
#1 if (bus !== 8'bzzzzzzz1) begin
$display("FAILED");
$finish;
end
if (drv.D !== D) begin
$display("FAILED (D)");
$finish;
end
E = 0;
#1 if (bus !== 8'bzzzzzzz1) begin
$display("FAILED");
$finish;
end
D = 0;
CLK = 0;
#1 CLK = 1;
if (drv.D !== D) begin
$display("FAILED (D)");
$finish;
end
#1 D = 1;
#1 if (bus !== 8'bzzzzzzz1) begin
$display("FAILED");
$finish;
end
if (drv.D !== D) begin
$display("FAILED (D)");
$finish;
end
$display("bus=%b, D=%b, drv.D=%b, E=%b, drv.save=%b", bus, D, drv.D, E, drv.save);
$display("PASSED");
end // initial begin
endmodule // main
module BUFT(inout wire TO, input wire D, input wire E, input wire CLK);
reg save;
assign TO = E? save : 2'bz;
always @(posedge CLK)
save <= D;
endmodule // BUFT
|
#include <bits/stdc++.h> using namespace std; int kmp(string s) { vector<int> lps(s.size(), 0); for (int i = 1; i < s.size(); ++i) { int index = lps[i - 1]; while (index > 0 && s[i] != s[index]) index = lps[index - 1]; if (s[i] == s[index]) lps[i] = index + 1; else lps[i] = index; } return lps[lps.size() - 1]; } int func(string s) { string t = s + # ; reverse(s.begin(), s.end()); t += s; return kmp(t); } int main() { int t; cin >> t; while (t--) { string s; cin >> s; int l = 0, n = s.length(); for (int i = 0, j = n - 1; i < j; i++, j--) { if (s[i] == s[j]) l++; else break; } string remaining = s.substr(l, n - 2 * l); string ans = s.substr(0, l); if (remaining.size()) { int lp = func(remaining); reverse(remaining.begin(), remaining.end()); int ls = func(remaining); if (lp > ls) { reverse(remaining.begin(), remaining.end()); ans += remaining.substr(0, lp); } else ans += remaining.substr(0, ls); } ans += s.substr(n - l, l); cout << ans << endl; } } |
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_tfifo.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// - Igor Mohor () ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
end
else
if (fifo_reset) begin
top <= #1 0;
bottom <= #1 1'b0;
count <= #1 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= #1 top_plus_1;
count <= #1 count + 1'b1;
end
2'b01 : if(count>0)
begin
bottom <= #1 bottom + 1'b1;
count <= #1 count - 1'b1;
end
2'b11 : begin
bottom <= #1 bottom + 1'b1;
top <= #1 top_plus_1;
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= #1 1'b0;
else
if(fifo_reset | reset_status)
overrun <= #1 1'b0;
else
if(push & (count==fifo_depth))
overrun <= #1 1'b1;
end // always
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFRTN_SYMBOL_V
`define SKY130_FD_SC_MS__DFRTN_SYMBOL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFRTN_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; const int Maxn = 1005; int n, m, k; long long s[Maxn][Maxn], sl[Maxn][Maxn], sr[Maxn][Maxn]; inline int get() { char ch; while (!isdigit(ch = getchar())) ; int v = ch - 48; while (isdigit(ch = getchar())) v = v * 10 + ch - 48; return v; } int main() { n = get(); m = get(); k = get(); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) s[i][j] = get() + s[i][j - 1] + s[i - 1][j] - s[i - 1][j - 1]; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { sl[i][j] = sl[i - 1][j - 1] + s[i][j] - (i > k && j > k ? s[i - k][j - k] : 0); sr[i][j] = sr[i - 1][j + 1] + s[i][j] - (i > k && j + k <= m ? s[i - k][j + k] : 0); } sr[i][0] = sr[i - 1][1] + s[i][0] - (i > k ? s[i - k][k] : 0); } int wx = 0, wy = 0; long long maxv = -1; for (int i = k; i <= n - k + 1; i++) for (int j = k; j <= m - k + 1; j++) { long long v = sr[i + k - 1][j] + sr[i - 1][j - k] - sl[i - 1][j + k - 1] - sl[i + k - 1][j - 1]; if (maxv < v) maxv = v, wx = i, wy = j; } cout << wx << << wy << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; #define int long long void solve() { int n, m, k; cin >> n >> m >> k; vector<tuple<int, int, int>> edges(m + 2), edges_large, edges_small; vector<int> values; for (int i = 1; i <= m; i++) { int a, b, c; cin >> a >> b >> c; edges[i] = {a, b, c}; if (c > k) edges_large.push_back(edges[i]); else edges_small.push_back(edges[i]); values.push_back(c); } sort(values.begin(), values.end()); vector<int> fa(n + 2); for (int i = 1; i <= n; i++) fa[i] = i; function<int(int)> find = [&](int x) -> int { return x == fa[x] ? x : fa[x] = find(fa[x]); }; int tot = 1; function<void(int, int)> merge = [&](int x, int y) -> void { x = find(x); y = find(y); if (x != y) fa[x] = y, tot++; }; for (auto [u, v, w] : edges_small) merge(u, v); int flag = tot == n; if (flag) { int i = lower_bound(values.begin(), values.end(), k) - values.begin(); int j = i - 1; int ans = 1e18; if (i >= 0 && i < m) ans = min(ans, abs(k - values[i])); if (j >= 0 && j < m) ans = min(ans, abs(k - values[j])); cout << ans << endl; } else { int ans = 0; vector<pair<int, pair<int, int>>> ve; for (auto [x, y, z] : edges_large) ve.push_back({z, {x, y}}); sort(ve.begin(), ve.end()); for (int i = 0; i < ve.size(); i++) { auto [w, pr] = ve[i]; auto [u, v] = pr; if (find(u) != find(v)) merge(u, v), ans += w - k; if (tot == n) break; } cout << ans << endl; } } signed main() { ios::sync_with_stdio(false); int t; cin >> t; while (t--) { solve(); } } |
module demo_text
(
input wire clk,
input wire [10:0] pix_x, pix_y,
output wire [3:0] text_on,
output reg [2:0] text_rgb
);
// signal declaration
wire [10:0] rom_addr;
reg [6:0] char_addr, char_addr_s, char_addr_l,
char_addr_r, char_addr_o;
reg [3:0] row_addr;
wire [3:0] row_addr_s, row_addr_l, row_addr_r, row_addr_o;
reg [2:0] bit_addr;
wire [2:0] bit_addr_s, bit_addr_l,bit_addr_r, bit_addr_o;
wire [7:0] font_word;
wire font_bit, logo_on;
// instantiate font ROM
font_rom font_unit
(.clk(clk), .addr(rom_addr), .data(font_word));
//-------------------------------------------
// logo region:
// - display logo "PONG"
// - used as background
// - scale to 64-by-128 font
//-------------------------------------------
assign logo_on = (pix_y[9:7]==2) &&
(3<=pix_x[9:6]) && (pix_x[9:6]<=6);
assign row_addr_l = pix_y[6:3];
assign bit_addr_l = pix_x[5:3];
always @*
case (pix_x[8:6])
3'o3: char_addr_l = 7'h50; // P
3'o4: char_addr_l = 7'h4f; // O
3'o5: char_addr_l = 7'h4e; // N
default: char_addr_l = 7'h47; // G
endcase
//-------------------------------------------
// mux for font ROM addresses and rgb
//-------------------------------------------
always @*
begin
text_rgb = 3'b000;
if (logo_on) begin
char_addr = char_addr_l;
row_addr = row_addr_l;
bit_addr = bit_addr_l;
if (font_bit)
text_rgb = 3'b111;
end else begin
char_addr = 0;
row_addr = 0;
bit_addr = 0;
end
end
assign text_on = logo_on;
//-------------------------------------------
// font rom interface
//-------------------------------------------
assign rom_addr = {char_addr, row_addr};
assign font_bit = font_word[~bit_addr];
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cordic_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cordic_ram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef SIMULATION
altsyncram_component.init_file = "../../dgn/rtl/altera/cordic_ram.mif",
`else //for syn
altsyncram_component.init_file = "../rtl/altera/cordic_ram.mif",
`endif
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "cordic_ram.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "cordic_ram.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cordic_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cordic_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cordic_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cordic_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cordic_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cordic_ram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long mod = 1e9 + 7; long long min(long long a, long long b) { return (a < b) ? a : b; } long long max(long long a, long long b) { return (a > b) ? a : b; } long long fp(long long a, long long b) { if (b == 0) return 1; long long x = fp(a, b / 2); x = (x * x) % mod; if (b & 1) x = (x * a) % mod; return x; } const long long N = 2000; long long bit[4 * N]; void update(long long id, long long l, long long r, long long point, long long val) { if (point < l || point > r) return; if (l == r) { bit[id] += val; return; } long long mid = (l + r) / 2; update(2 * id, l, mid, point, val); update(2 * id + 1, mid + 1, r, point, val); bit[id] = bit[2 * id] + bit[2 * id + 1]; } long long get(long long id, long long l, long long r, long long point) { if (point < l) { return 0; } if (r <= point) { return bit[id]; } long long mid = (l + r) / 2; return get(2 * id, l, mid, point) + get(2 * id + 1, mid + 1, r, point); } signed main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n; cin >> n; long long a[n + 1]; for (long long i = 1; i <= n; i++) { cin >> a[i]; } map<long long, vector<array<long long, 2>>> mp; for (long long i = 1; i <= n; i++) { long long sm = 0; for (long long j = i; j <= n; j++) { sm += a[j]; mp[sm].push_back({i, j}); } } vector<array<long long, 2>> ans; for (auto i : mp) { vector<array<long long, 2>> tmp; sort(i.second.begin(), i.second.end()); for (long long j = 0; j < i.second.size(); j++) { update(1, 1, n, i.second[j][1], 1); } long long st = 1; for (long long j = 0; j < i.second.size(); j++) { update(1, 1, n, i.second[j][1], -1); if (i.second[j][0] < st) continue; if (i.second[j][0] == i.second[j][1]) { tmp.push_back(i.second[j]); st = i.second[j][1] + 1; } else { long long x = get(1, 1, n, i.second[j][1] - 1) - get(1, 1, n, i.second[j][0]); if (x > 0) { continue; } else { tmp.push_back(i.second[j]); st = i.second[j][1] + 1; } } } if (tmp.size() > ans.size()) ans = tmp; } cout << ans.size() << n ; for (auto i : ans) cout << i[0] << << i[1] << n ; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2(clk, reset, ce, a, b, s);
// ---- input/output ports list here ----
input clk;
input reset;
input ce;
input [16 - 1 : 0] a;
input [16 - 1 : 0] b;
output [16 - 1 : 0] s;
// ---- register and wire type variables list here ----
// wire for the primary inputs
wire [16 - 1 : 0] a_reg;
wire [16 - 1 : 0] b_reg;
// wires for each small adder
wire [4 - 1 : 0] a0_cb;
wire [4 - 1 : 0] b0_cb;
wire [8 - 1 : 4] a1_cb;
wire [8 - 1 : 4] b1_cb;
wire [12 - 1 : 8] a2_cb;
wire [12 - 1 : 8] b2_cb;
wire [16 - 1 : 12] a3_cb;
wire [16 - 1 : 12] b3_cb;
// registers for input register array
reg [4 - 1 : 0] a1_cb_regi1[1 - 1 : 0];
reg [4 - 1 : 0] b1_cb_regi1[1 - 1 : 0];
reg [4 - 1 : 0] a2_cb_regi2[2 - 1 : 0];
reg [4 - 1 : 0] b2_cb_regi2[2 - 1 : 0];
reg [4 - 1 : 0] a3_cb_regi3[3 - 1 : 0];
reg [4 - 1 : 0] b3_cb_regi3[3 - 1 : 0];
// wires for each full adder sum
wire [16 - 1 : 0] fas;
// wires and register for carry out bit
wire faccout_ini;
wire faccout0_co0;
wire faccout1_co1;
wire faccout2_co2;
wire faccout3_co3;
reg faccout0_co0_reg;
reg faccout1_co1_reg;
reg faccout2_co2_reg;
// registers for output register array
reg [4 - 1 : 0] s0_ca_rego0[2 - 0 : 0];
reg [4 - 1 : 0] s1_ca_rego1[2 - 1 : 0];
reg [4 - 1 : 0] s2_ca_rego2[2 - 2 : 0];
// wire for the temporary output
wire [16 - 1 : 0] s_tmp;
// ---- RTL code for assignment statements/always blocks/module instantiations here ----
assign a_reg = a;
assign b_reg = b;
// small adder input assigments
assign a0_cb = a_reg[4 - 1 : 0];
assign b0_cb = b_reg[4 - 1 : 0];
assign a1_cb = a_reg[8 - 1 : 4];
assign b1_cb = b_reg[8 - 1 : 4];
assign a2_cb = a_reg[12 - 1 : 8];
assign b2_cb = b_reg[12 - 1 : 8];
assign a3_cb = a_reg[16 - 1 : 12];
assign b3_cb = b_reg[16 - 1 : 12];
// input register array
always @ (posedge clk) begin
if (ce) begin
a1_cb_regi1 [0] <= a1_cb;
b1_cb_regi1 [0] <= b1_cb;
a2_cb_regi2 [0] <= a2_cb;
b2_cb_regi2 [0] <= b2_cb;
a3_cb_regi3 [0] <= a3_cb;
b3_cb_regi3 [0] <= b3_cb;
a2_cb_regi2 [1] <= a2_cb_regi2 [0];
b2_cb_regi2 [1] <= b2_cb_regi2 [0];
a3_cb_regi3 [1] <= a3_cb_regi3 [0];
b3_cb_regi3 [1] <= b3_cb_regi3 [0];
a3_cb_regi3 [2] <= a3_cb_regi3 [1];
b3_cb_regi3 [2] <= b3_cb_regi3 [1];
end
end
// carry out bit processing
always @ (posedge clk) begin
if (ce) begin
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end
end
// small adder generation
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder u0 (
.faa ( a0_cb ),
.fab ( b0_cb ),
.facin ( faccout_ini ),
.fas ( fas[3:0] ),
.facout ( faccout0_co0 )
);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder u1 (
.faa ( a1_cb_regi1[0] ),
.fab ( b1_cb_regi1[0] ),
.facin ( faccout0_co0_reg),
.fas ( fas[7:4] ),
.facout ( faccout1_co1 )
);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder u2 (
.faa ( a2_cb_regi2[1] ),
.fab ( b2_cb_regi2[1] ),
.facin ( faccout1_co1_reg),
.fas ( fas[11:8] ),
.facout ( faccout2_co2 )
);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder_f u3 (
.faa ( a3_cb_regi3[2] ),
.fab ( b3_cb_regi3[2] ),
.facin ( faccout2_co2_reg ),
.fas ( fas[15 :12] ),
.facout ( faccout3_co3 )
);
assign faccout_ini = 1'b0;
// output register array
always @ (posedge clk) begin
if (ce) begin
s0_ca_rego0 [0] <= fas[4-1 : 0];
s1_ca_rego1 [0] <= fas[8-1 : 4];
s2_ca_rego2 [0] <= fas[12-1 : 8];
s0_ca_rego0 [1] <= s0_ca_rego0 [0];
s0_ca_rego0 [2] <= s0_ca_rego0 [1];
s1_ca_rego1 [1] <= s1_ca_rego1 [0];
end
end
// get the s_tmp, assign it to the primary output
assign s_tmp[4-1 : 0] = s0_ca_rego0[2];
assign s_tmp[8-1 : 4] = s1_ca_rego1[1];
assign s_tmp[12-1 : 8] = s2_ca_rego2[0];
assign s_tmp[16 - 1 : 12] = fas[15 :12];
assign s = s_tmp;
endmodule
// short adder
module nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder
#(parameter
N = 4
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
// the final stage short adder
module nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_fadder_f
#(parameter
N = 4
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_16ns_16ns_16_4(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2 nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_AddSubnS_2_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.s( dout ));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 5000; const int B = 33; const int P = 1e6 + 3; string s[2]; int ans, Max[2][maxn], dp1[maxn][maxn], dp2[maxn][maxn], dp3[maxn][maxn]; inline void make(const string &x, const string &y, int dp[maxn][maxn]) { for (int i = 0; i < x.size(); i++) for (int j = 0; j < y.size(); j++) if (x[i] == y[j]) dp[i][j] = 1 + (i && j ? dp[i - 1][j - 1] : 0); } int main() { ios_base ::sync_with_stdio(0); for (int i = 0; i < 2; i++) cin >> s[i]; make(s[0], s[0], dp1); make(s[0], s[1], dp2); make(s[1], s[1], dp3); for (int i = 0; i < s[0].size(); i++) for (int j = 0; j < s[0].size(); j++) if (i != j) Max[0][i] = max(Max[0][i], dp1[i][j]); for (int i = 0; i < s[1].size(); i++) for (int j = 0; j < s[1].size(); j++) if (i != j) Max[1][i] = max(Max[1][i], dp3[i][j]); ans = INT_MAX; for (int i = 0; i < s[0].size(); i++) for (int j = 0; j < s[1].size(); j++) if (dp2[i][j] > Max[0][i] && dp2[i][j] > Max[1][j]) ans = min(ans, max(Max[0][i], Max[1][j]) + 1); cout << (ans == INT_MAX ? -1 : ans) << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 40; const long long INFLL = 1e18; long long dp[N][3][2][2]; signed main() { srand(time(NULL)); ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int n; long long r1, r2, r3, d; cin >> n >> r1 >> r2 >> r3 >> d; vector<long long> a(n); for (int(i) = 0; (i) != (n); (i)++) cin >> a[i]; for (int(i) = 0; (i) != (n); (i)++) { for (int(j) = 0; (j) != (3); (j)++) { for (int(k) = 0; (k) != (2); (k)++) { dp[i][j][k][0] = dp[i][j][k][1] = INFLL; } } } dp[0][2][0][0] = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < 30; j++) { dp[i][2][0][0] = min(dp[i][2][0][0], dp[i][2][1][0] + 2 * d + r1); dp[i][2][0][0] = min(dp[i][2][0][0], dp[i][2][1][1] + 2 * d + r1); dp[i][1][0][0] = min(dp[i][1][0][0], dp[i][1][1][0] + 2 * d + r1); dp[i][1][0][0] = min(dp[i][1][0][0], dp[i][1][1][1] + 2 * d + r1); dp[i][0][0][0] = min(dp[i][0][0][0], dp[i][0][1][0] + 2 * d + r1); dp[i][0][0][0] = min(dp[i][0][0][0], dp[i][0][1][1] + 2 * d + r1); dp[i][0][0][0] = min(dp[i][0][0][0], dp[i][2][0][0] + a[i] * r1 + r3); dp[i][0][1][0] = min(dp[i][0][1][0], dp[i][2][1][0] + a[i] * r1 + r3); dp[i][1][0][1] = min(dp[i][1][0][1], dp[i][2][0][0] + min(r2, a[i] * r1 + r1)); dp[i][1][1][1] = min(dp[i][1][1][1], dp[i][2][1][0] + min(r2, a[i] * r1 + r1)); dp[i][0][0][0] = min(dp[i][0][0][0], dp[i][1][0][0] + r1); dp[i][0][1][0] = min(dp[i][0][1][0], dp[i][1][1][0] + r1); dp[i + 1][2][0][0] = min(dp[i + 1][2][0][0], dp[i][0][0][0] + d); dp[i + 1][2][0][0] = min(dp[i + 1][2][0][0], dp[i][0][0][1] + d); dp[i + 1][2][1][0] = min(dp[i + 1][2][1][0], dp[i][1][0][0] + d); dp[i + 1][2][1][0] = min(dp[i + 1][2][1][0], dp[i][1][0][1] + d); } } cout << min(dp[n - 1][0][0][0], dp[n - 1][0][1][0] + d + r1); } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSHOLD_1_V
`define SKY130_FD_SC_LP__BUSHOLD_1_V
/**
* bushold: Bus signal holder (back-to-back inverter) with
* noninverting reset (gates output driver).
*
* Verilog wrapper for bushold with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bushold.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bushold_1 (
X ,
RESET,
VPWR ,
VGND ,
VPB ,
VNB
);
inout X ;
input RESET;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__bushold base (
.X(X),
.RESET(RESET),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bushold_1 (
X ,
RESET
);
inout X ;
input RESET;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__bushold base (
.X(X),
.RESET(RESET)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSHOLD_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_P_SYMBOL_V
`define SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_P_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_pwrgood_pp$P (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input VPWR
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_PWRGOOD_PP_P_SYMBOL_V
|
/**
* bsg_cache_non_blocking_pkt_decode.v
*
* @author tommy
*
*/
`include "bsg_defines.v"
module bsg_cache_non_blocking_decode
import bsg_cache_non_blocking_pkg::*;
(
input bsg_cache_non_blocking_opcode_e opcode_i
, output bsg_cache_non_blocking_decode_s decode_o
);
always_comb begin
case (opcode_i)
LD, SD: decode_o.size_op = 2'b11;
LW, SW, LWU: decode_o.size_op = 2'b10;
LH, SH, LHU: decode_o.size_op = 2'b01;
LB, SB, LBU: decode_o.size_op = 2'b00;
default: decode_o.size_op = 2'b00;
endcase
end
assign decode_o.sigext_op = (opcode_i == LB)
| (opcode_i == LH)
| (opcode_i == LW)
| (opcode_i == LD);
assign decode_o.ld_op = (opcode_i == LB)
| (opcode_i == LH)
| (opcode_i == LW)
| (opcode_i == LD)
| (opcode_i == LBU)
| (opcode_i == LHU)
| (opcode_i == LWU);
assign decode_o.st_op = (opcode_i == SB)
| (opcode_i == SH)
| (opcode_i == SW)
| (opcode_i == SD)
| (opcode_i == SM);
assign decode_o.mask_op = (opcode_i == SM);
assign decode_o.block_ld_op = (opcode_i == BLOCK_LD);
assign decode_o.tagst_op = (opcode_i == TAGST);
assign decode_o.tagfl_op = (opcode_i == TAGFL);
assign decode_o.taglv_op = (opcode_i == TAGLV);
assign decode_o.tagla_op = (opcode_i == TAGLA);
assign decode_o.afl_op = (opcode_i == AFL);
assign decode_o.aflinv_op = (opcode_i == AFLINV);
assign decode_o.ainv_op = (opcode_i == AINV);
assign decode_o.alock_op = (opcode_i == ALOCK);
assign decode_o.aunlock_op = (opcode_i == AUNLOCK);
assign decode_o.mgmt_op = ~(decode_o.ld_op | decode_o.st_op | decode_o.block_ld_op);
endmodule
|
#include <bits/stdc++.h> using namespace std; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << n ; err(++it, args...); } long long powMod(long long x, long long y) { long long p = 1; while (y) { if (y % 2) { p = (p * x) % ((long long)1e9 + 7); } y /= 2; x = (x * x) % ((long long)1e9 + 7); } return p; } long long CpowMod(long long x, long long y, long long w) { long long p = 1; while (y) { if (y % 2) { p = (p * x) % w; } y /= 2; x = (x * x) % w; } return p; } long long invMod(long long x) { return powMod(x, ((long long)1e9 + 7) - 2); } long long CinvMod(long long x, long long w) { return CpowMod(x, w - 2, w); } long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long exGcd(long long a, long long b, long long &x, long long &y) { if (b == 0) { y = 0; x = 1; return a; } long long xtmp, ytmp; long long g = exGcd(b, a % b, xtmp, ytmp); x = ytmp; y = xtmp - (a / b) * ytmp; return g; } void solve() { long long t; cin >> t; while (t--) { long long n; long long x; cin >> n >> x; long long cnt = 0, eve = 0; for (long long i = 0; i <= n - 1; i++) { long long y; cin >> y; if (y % 2) cnt++; else eve++; } if (cnt == 0) { cout << NO << n ; continue; } long long mn; if (x % 2 == 1) { mn = 0; } else mn = 1; if (cnt % 2 == 0) { x -= (cnt - 1); } else x -= cnt; x = max(mn, x); if (eve >= x) { cout << YES << n ; } else cout << NO << n ; } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2AI_TB_V
`define SKY130_FD_SC_HDLL__O2BB2AI_TB_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o2bb2ai.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_hdll__o2bb2ai dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2AI_TB_V
|
#include <bits/stdc++.h> using namespace std; const long long N = 505, M = 1e9 + 7; long long K, m, n, a[N], H[N], num[N], F[N], G[N], x, ans[N], C[N]; inline long long ksm(long long x, long long y) { long long ans = 1; for (; y; y >>= 1, x = x * x % M) if (y & 1) (ans *= x) %= M; return ans; } inline void cf1(long long A[]) { memset(C, 0, sizeof C); for (long long i = 0; i < 250; i++) for (long long j = 0; j < 250; j++) (C[i + j] += A[i] * A[j]) %= M; long long Inv = ksm(num[250], M - 2); for (long long i = 499; i >= 250; i--) { long long t = Inv * C[i] % M; for (long long j = 0; j <= 250; j++) (C[-250 + j + i] += M - t * num[j] % M) %= M; } for (long long i = 0; i < N; i++) A[i] = C[i]; } inline void cf(long long A[], long long B[]) { memset(C, 0, sizeof C); for (long long i = 0; i < 250; i++) for (long long j = 0; j < 250; j++) (C[i + j] += A[i] * B[j]) %= M; long long Inv = ksm(num[250], M - 2); for (long long i = 499; i >= 250; i--) { long long t = Inv * C[i] % M; for (long long j = 0; j <= 250; j++) (C[-250 + j + i] += M - t * num[j] % M) %= M; } for (long long i = 0; i < N; i++) A[i] = C[i]; } signed main() { scanf( %lld%lld%lld , &K, &m, &n); for (long long i = 1; i <= K; i++) scanf( %lld , &a[i]); while (m--) { scanf( %lld , &x); (num[250 - x] += M - 1) %= M; } num[250]++; ans[0] = 1; for (long long i = 1; i < 250; i++) for (long long j = 1; j <= i; j++) (ans[i] += M - ans[i - j] * num[250 - j] % M) %= M; for (long long i = 1; i <= K; i++) { memset(F, 0, sizeof F); memset(G, 0, sizeof G); F[1] = 1; long long y = a[i]; G[0] = 1; for (; y; y >>= 1, cf1(F)) if (y & 1) cf(G, F); for (long long j = 0; j < 250; j++) (H[j] += G[j]) %= M; } memset(G, 0, sizeof G); G[0] = 1; for (; n; n >>= 1, cf1(H)) if (n & 1) cf(G, H); long long Ans = 0; for (long long i = 0; i < 250; i++) (Ans += G[i] * ans[i]) %= M; printf( %lld n , Ans); } |
#include <bits/stdc++.h> using namespace std; int gcd(int a, int b) { if (b == 0) return a; else return gcd(b, a % b); } void dv(vector<int> v) { for (int i = 0; i < v.size(); i++) cout << v[i] << ; } bool check_prime(int a) { for (int i = sqrt(a); i > 1; i--) { if (a % i == 0) return false; } return true; } int ctoil(char c) { return (int)c - 97; } int ctoiu(char c) { return (int)c - 65; } void dv_2d(vector<vector<int>> v) { for (int i = 0; i < v.size(); i++) { for (int j = 0; j < v[i].size(); j++) { cout << v[i][j] << ; } cout << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long n, m; cin >> n >> m; long long a, b; if (n <= 2 * m) { a = 0; } else { a = n - 2 * m; } if (m == 0) { b = n; } else { b = n - ceil((sqrt(1 + 8 * m) + 1) / 2); } cout << a << << b << endl; } |
#include <bits/stdc++.h> using namespace std; int N, M; int main() { cin >> M >> N; if (M == N) { cout << N << 1 << << N << 2 ; return 0; } if (N - M == 1) { cout << M << 9 << << N << 0 ; return 0; } if (M == 9 && N == 1) { cout << 9 10 ; return 0; } cout << -1; } |
#include <bits/stdc++.h> using namespace std; int n, m; vector<pair<int, int> > a; long long sum, ans; int e, deg; int get_e(int num, int deg) { if (num == 1) return 0; if (num == 2) return 1; int res = num * (num - 1) / 2; if (deg & 1) { int bad = num - 2; res += bad / 2; } return res; } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= m; i++) { int q, w; scanf( %d %d , &q, &w); a.push_back(make_pair(w, q)); } sort(a.rbegin(), a.rend()); for (int i = 1; i <= min(3000, m); i++) { sum += a[i - 1].first; deg = i - 1; e = get_e(i, deg); if (e + 1 <= n) ans = max(ans, sum); } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; ifstream input; ofstream output; int main(int argc, char *argv[]) { input.sync_with_stdio(false); output.sync_with_stdio(false); int n, tmp, tmp2; priority_queue<int> y; set<int> used; cin >> n; for (int i = 0; i < n; i++) { cin >> tmp; y.push(tmp); used.insert(tmp); } while (1) { tmp = y.top(); tmp2 = tmp; y.pop(); while (tmp > 1) { if (used.find(tmp / 2) == used.end()) { used.insert(tmp / 2); used.erase(tmp2); y.push(tmp / 2); break; } tmp /= 2; } if (tmp == 1) { y.push(tmp2); break; } } while (y.size()) { cout << y.top() << ; y.pop(); } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 50, INF = 0, MOD = 0; long long n, m, a[N], tmp; vector<long long> v; int32_t main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cin >> m >> n; for (long long i = 0; i < n; i++) { cout << 1 << endl; fflush(stdout); cin >> tmp; if (tmp == 0 || tmp == -2) return 0; if (tmp == -1) a[i] = 0; if (tmp == 1) a[i] = 1; } long long l = 0, r = m + 1, cnt = 0; while (r - l > 2 && cnt + n < 60) { long long mid = (l + r) / 2; cout << mid << endl; fflush(stdout); cin >> tmp; if (tmp == 0 || tmp == -2) return 0; if (a[cnt] == 0) tmp *= -1; if (tmp == -1) r = mid; if (tmp == 1) l = mid; v.push_back(tmp); cnt = (cnt + 1) % n; } cout << r - 1 << endl; fflush(stdout); cin >> tmp; return 0; } |
//-------------------------------------------------------------------
//-- prescaler_tb.v
//-- Banco de pruebas para el prescaler
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
module prescaler_tb();
//-- Numero de bits del prescaler a comprobar
parameter N = 2;
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Salida del prescaler
wire clk_out;
//-- Registro para comprobar si el prescaler funciona
reg [N-1:0] counter_check = 0;
//-- Instanciar el prescaler de N bits
prescaler #(.N(N)) //-- Parámetro N
Pres1(
.clk_in(clk),
.clk_out(clk_out)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk = ~clk;
//-- Comprobacion del valor del contador
//-- En cada flanco de bajada se comprueba la salida del contador
//-- y se incrementa el valor esperado
always @(negedge clk) begin
//-- Incrementar variable del contador de prueba
counter_check = counter_check + 1;
//-- El bit de mayor peso debe coincidir con clk_out
if (counter_check[N-1] != clk_out) begin
$display("--->ERROR! Prescaler no funciona correctamente");
$display(
"Clk out: %d, counter_check[2]: %d", clk_out, counter_check[N-1]);
end
end
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("prescaler_tb.vcd");
$dumpvars(0, prescaler_tb);
# 99 $display("FIN de la simulacion");
# 100 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; const int N = 100005; long long f[N]; long long inverse(long long x) { if (x >= mod) return inverse(x % mod); assert(x != 0); if (x == 1) return 1; return inverse(mod % x) * (mod - mod / x) % mod; } int main() { ios::sync_with_stdio(false); cin.tie(NULL); int n; cin >> n; vector<long long> a(n); long long sum = 0; for (auto &x : a) { cin >> x; sum += x; } f[0] = 0; f[1] = ((sum - 1) * (sum - 1) % mod) * inverse(sum) % mod; for (int m = 2; m < N && m < sum; m++) { f[m] = 2 * f[m - 1] - f[m - 2] - ((sum - 1) * inverse(sum - m + 1) % mod); f[m] %= mod; if (f[m] < 0) f[m] += mod; } long long ans = 0; for (auto x : a) { ans += f[x]; } ans %= mod; cout << ans << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__FILL_BLACKBOX_V
`define SKY130_FD_SC_HDLL__FILL_BLACKBOX_V
/**
* fill: Fill cell.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__fill ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__FILL_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m, a[10], b[10]; cin >> n >> m; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int i = 0; i < m; i++) { cin >> b[i]; } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (a[i] == b[j]) { printf( %d , a[i]); if (i != n - 1) printf( ); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int a, b, c, d, n, i, cnt = 0, snt = 0; float f, flo, fload = 0; string s, h, o, name; int main() { ios_base::sync_with_stdio(0); setlocale(LC_ALL, Russian ); ; string t; size_t i; getline(cin, t, n ); while ((i = t.find( )) != string::npos) t.erase(i, 1); s = t; reverse(s.begin(), s.end()); for (int i = 0; i < s.size(); i++) s[i] = tolower(s[i]); for (int i = 0; i < s.size(); i++) { if (s[i] >= 65 and s[i] <= 122) { if (s[i] == a or s[i] == e or s[i] == u or s[i] == i or s[i] == y or s[i] == o ) { cout << YES ; ; return 0; ; } else { cout << NO ; ; return 0; ; } } } } |
// test_simulation_mod_1_xx.v
module f1_test(in1, in2, out);
input in1;
input in2;
output out;
wire synth_net_0;
wire synth_net_1;
BUF synth_BUF_0(.in(synth_net_1), .out(out
));
DIV1 synth_DIV(.in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1
));
endmodule
// test_simulation_always_31_tt.v
module f2_test(clk, cond, data);
input cond;
input clk;
output data;
wire synth_net;
wire synth_net_0;
wire synth_net_1;
wire synth_net_2;
wire synth_net_3;
wire synth_net_4;
wire synth_net_5;
wire synth_net_6;
wire synth_net_7;
wire synth_net_8;
wire synth_net_9;
wire synth_net_10;
wire synth_net_11;
wire tmp;
AND2 synth_AND(.in({synth_net_0, synth_net_1}), .
out(synth_net_2));
AND2 synth_AND_0(.in({synth_net_3, synth_net_4}), .out(
synth_net_5));
AND2 synth_AND_1(.in({synth_net_6, synth_net_7}), .out(
synth_net_8));
AND2 synth_AND_2(.in({synth_net_9, synth_net_10}), .out(
synth_net_11));
BUF synth_BUF(.in(synth_net), .out(synth_net_0));
BUF
synth_BUF_0(.in(data), .out(synth_net_3));
BUF synth_BUF_1(.in(synth_net_8)
, .out(tmp));
BUF synth_BUF_2(.in(tmp), .out(synth_net_9));
MUX2 synth_MUX(.
in({synth_net_2, synth_net_5}), .select(cond), .out(synth_net_6));
MUX2
synth_MUX_0(.in({synth_net_1, synth_net_4}), .select(cond), .out(synth_net_7
));
FF synth_FF(.d(synth_net_11), .clk(clk), .q(data));
VCC synth_VCC(.out(
synth_net));
VCC synth_VCC_0(.out(synth_net_1));
VCC synth_VCC_1(.out(
synth_net_4));
VCC synth_VCC_2(.out(synth_net_10));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int a1, a2, k1, k2; int n; cin >> a1 >> a2 >> k1 >> k2 >> n; int n1 = n, n2 = n; n1 -= (a1 * (k1 - 1)); n1 -= (a2 * (k2 - 1)); if (n1 <= 0) cout << 0 << ; else cout << n1 << ; if (k1 > k2) { if (n2 < k2) { cout << 0; return 0; } else { n2 /= k2; if (n2 >= a2) { n -= (a2 * k2); if (n >= k1) { n /= k1; if (n >= a1) { cout << a1 + a2 << ; } else { cout << a2 + n << ; } } else { cout << a2 << ; } } else { cout << n2 << ; } } } else { if (n2 < k1) { cout << 0; return 0; } else { n2 /= k1; if (n2 >= a1) { n -= (a1 * k1); if (n >= k2) { n /= k2; if (n >= a2) { cout << a1 + a2 << ; } else { cout << a1 + n << ; } } else { cout << a1 << ; } } else { cout << n2 << ; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 20009; int INF = 2e9; struct edge { int to, cap, rev; edge() {} edge(int tt, int cc, int rr) { to = tt; cap = cc; rev = rr; } }; vector<edge> Graph[N]; int level[N]; int iter[N]; void add_edge(int from, int to, int cap) { Graph[from].push_back(edge(to, cap, Graph[to].size())); Graph[to].push_back(edge(from, 0, Graph[from].size() - 1)); } void bfs(int s) { memset(level, -1, sizeof(level)); queue<int> que; level[s] = 0; que.push(s); while (que.size()) { int v = que.front(); que.pop(); for (int i = 0; i < Graph[v].size(); i++) { edge &e = Graph[v][i]; if (e.cap > 0 && level[e.to] < 0) { level[e.to] = level[v] + 1; que.push(e.to); } } } } int dfs(int v, int t, int f) { if (v == t) return f; for (int &i = iter[v]; i < Graph[v].size(); i++) { edge &e = Graph[v][i]; if (e.cap > 0 && level[v] < level[e.to]) { int d = dfs(e.to, t, min(f, e.cap)); if (d > 0) { e.cap -= d; Graph[e.to][e.rev].cap += d; return d; } } } return 0; } int max_flow(int s, int t) { int flow = 0; while (1) { bfs(s); if (level[t] < 0) return flow; memset(iter, 0, sizeof(iter)); int f; while ((f = dfs(s, t, INF)) > 0) { flow += f; } } return flow; } int a[105], b[105], res[105][105], SumIn, SumOut; int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %d , &a[i]), add_edge(0, i + 1, a[i]), SumIn += a[i]; for (int i = 0; i < n; i++) scanf( %d , &b[i]), add_edge(i + 1 + n, 2 * n + 1, b[i]), SumOut += b[i]; for (int i = 0; i < n; i++) add_edge(i + 1, i + 1 + n, 1e6); for (int i = 0; i < m; i++) { int u, v; scanf( %d%d , &u, &v); add_edge(u, v + n, 1e6); add_edge(v, u + n, 1e6); } if (SumIn != SumOut || SumIn != max_flow(0, 2 * n + 1)) return 0 * printf( NO n ); printf( YES n ); for (int i = 1; i <= n; i++) for (auto &e : Graph[i]) if (e.to > n) res[i - 1][e.to - n - 1] = Graph[e.to][e.rev].cap; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) printf( %d , res[i][j]); printf( n ); } return 0; } |
/**
* Module: arbiter
*
* Description:
* A look ahead, round-robing parametrized arbiter.
*
* <> request
* each bit is controlled by an actor and each actor can 'request' ownership
* of the shared resource by bring high its request bit.
*
* <> grant
* when an actor has been given ownership of shared resource its 'grant' bit
* is driven high
*
* <> active
* is brought high by the arbiter when (any) actor has been given ownership
* of shared resource.
*
*
* Created: Sat Jun 1 20:26:44 EDT 2013
*
* Author: Berin Martini //
*/
`ifndef _arbiter_ `define _arbiter_
module arbiter
#(parameter
NUM_PORTS = 6)
(input clk,
input rst,
input [NUM_PORTS-1:0] request,
output reg [NUM_PORTS-1:0] grant,
output reg active
);
/**
* Local parameters
*/
localparam WRAP_LENGTH = 2*NUM_PORTS;
`ifdef VERBOSE
initial $display("Bus arbiter with %d units", NUM_PORTS);
`endif
/**
* Internal signals
*/
integer yy;
wire next;
wire [NUM_PORTS-1:0] order;
reg [NUM_PORTS-1:0] token;
wire [NUM_PORTS-1:0] token_lookahead [NUM_PORTS-1:0];
wire [WRAP_LENGTH-1:0] token_wrap;
/**
* Implementation
*/
assign token_wrap = {token, token};
assign next = ~|(token & request);
always @(posedge clk)
grant <= token & request;
always @(posedge clk)
active <= |(token & request);
always @(posedge clk)
if (rst) token <= 'b1;
else if (next) begin
for (yy = 0; yy < NUM_PORTS; yy = yy + 1) begin : TOKEN_
if (order[yy]) begin
token <= token_lookahead[yy];
end
end
end
genvar xx;
generate
for (xx = 0; xx < NUM_PORTS; xx = xx + 1) begin : ORDER_
assign token_lookahead[xx] = token_wrap[xx +: NUM_PORTS];
assign order[xx] = |(token_lookahead[xx] & request);
end
endgenerate
endmodule
`endif // `ifndef _arbiter_
|
#include <bits/stdc++.h> using namespace std; int size_n, size_m; set<int> result; vector<char> marks(0); vector<string> mrk(0); int main() { int ii, jj; string str; cin >> size_n >> size_m; marks.resize(size_m); mrk.resize(size_n); cin.ignore(); for (ii = 0; ii < size_m; ii++) marks[ii] = n ; for (ii = 0; ii < size_n; ii++) { getline(cin, str); mrk[ii] = str; for (jj = 0; jj < size_m; jj++) { if ((marks[jj] == n ) || (str[jj] >= marks[jj])) marks[jj] = str[jj]; } } for (ii = 0; ii < size_m; ii++) { for (jj = 0; jj < size_n; jj++) { if (mrk[jj][ii] == marks[ii]) result.insert(jj); } } cout << result.size() << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; bool comp(int x, int y) { return x > y; } int main() { int t = 1; cin >> t; int n; while (t--) { cin >> n; if (n == 1 || n == 2) { cout << 1 << n ; continue; } if (n & 1) cout << n / 2 + 1 << n ; else cout << n / 2 << n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLYGATE4SD3_PP_SYMBOL_V
`define SKY130_FD_SC_MS__DLYGATE4SD3_PP_SYMBOL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlygate4sd3 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLYGATE4SD3_PP_SYMBOL_V
|
module premuat_4(
i_0,
i_1,
i_2,
i_3,
o_0,
o_1,
o_2,
o_3
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input signed [27:0] i_0;
input signed [27:0] i_1;
input signed [27:0] i_2;
input signed [27:0] i_3;
output signed [27:0] o_0;
output signed [27:0] o_1;
output signed [27:0] o_2;
output signed [27:0] o_3;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign o_0=i_0;
assign o_1=i_2;
assign o_2=i_1;
assign o_3=i_3;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O221A_PP_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o221a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_PP_SYMBOL_V
|
// -*- Mode: Verilog -*-
// Filename : pb_display.v
// Description : Seven Segment Display
// Author : Philip Tracton
// Created On : Thu May 28 23:25:10 2015
// Last Modified By: Philip Tracton
// Last Modified On: Thu May 28 23:25:10 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module pb_display (/*AUTOARG*/
// Outputs
data_out, anode, cathode,
// Inputs
clk, reset, port_id, data_in, read_strobe, write_strobe
) ;
parameter BASE_ADDRESS = 8'h00;
input clk;
input reset;
input [7:0] port_id;
input [7:0] data_in;
output [7:0] data_out;
input read_strobe;
input write_strobe;
output [3:0] anode;
output [7:0] cathode;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] segment0; // From regs of display_regs.v
wire [7:0] segment1; // From regs of display_regs.v
wire [7:0] segment2; // From regs of display_regs.v
wire [7:0] segment3; // From regs of display_regs.v
// End of automatics
/*AUTOREG*/
//
// Registers
//
display_regs #(.BASE_ADDRESS(BASE_ADDRESS))
regs (/*AUTOINST*/
// Outputs
.data_out (data_out[7:0]),
.segment0 (segment0[7:0]),
.segment1 (segment1[7:0]),
.segment2 (segment2[7:0]),
.segment3 (segment3[7:0]),
// Inputs
.clk (clk),
.reset (reset),
.port_id (port_id[7:0]),
.data_in (data_in[7:0]),
.read_strobe (read_strobe),
.write_strobe (write_strobe));
//
// Displays
//
display seven_segments(/*AUTOINST*/
// Outputs
.anode (anode[3:0]),
.cathode (cathode[7:0]),
// Inputs
.clk (clk),
.segment0 (segment0[3:0]),
.segment1 (segment1[3:0]),
.segment2 (segment2[3:0]),
.segment3 (segment3[3:0]));
endmodule // pb_display
|
#include <bits/stdc++.h> using namespace std; double dist(long long int a, long long int b, long long int c, long long int d) { return sqrt(((a - c) * (a - c)) + (b - d) * (b - d)); } struct p { double val; long long int index; }; int comp(const void* a, const void* b) { if (((struct p*)a)->val - ((struct p*)b)->val < 0) return -1; if (((struct p*)a)->val - ((struct p*)b)->val > 0) return 1; if (((struct p*)a)->val - ((struct p*)b)->val == 0) return 0; } int main() { long long int ax, ay, bx, by, tx, ty, n; cin >> ax; cin >> ay; cin >> bx; cin >> by; cin >> tx; cin >> ty; cin >> n; long long int i, x, y; struct p a[n], b[n], c[n]; double sum = 0; for (i = 0; i < n; i++) { cin >> x; cin >> y; sum += 2 * dist(tx, ty, x, y); a[i].val = dist(ax, ay, x, y) - dist(tx, ty, x, y); a[i].index = i; b[i].val = dist(bx, by, x, y) - dist(tx, ty, x, y); b[i].index = i; } qsort(a, n, sizeof(struct p), comp); qsort(b, n, sizeof(struct p), comp); if (a[0].index == b[0].index) { sum += min(a[0].val, min(b[0].val, min(a[0].val + b[1].val, b[0].val + a[1].val))); } else { if (a[0].val < b[0].val) { sum += a[0].val; if (b[0].val < 0) sum += b[0].val; } else { sum += b[0].val; if (a[0].val < 0) sum += a[0].val; } } cout << setprecision(12) << fixed << sum << endl; return 0; } |
module top;
reg passed = 1'b1;
wire out, cout0, cout1;
reg sel, in_1, in_0;
reg pout;
assign cout0 = sel ? 1'bz : in_0;
assign cout1 = sel ? in_1: 1'bz;
assign out = sel ? in_1: in_0;
task automatic check;
input bit, in_1, in_0;
input [63:0] comment;
reg z2x;
begin
if (sel === 1'b1) begin
if (bit !== in_1) begin
$display("FAILED: %0s sel = 1'b1, expected %b, got %b",
comment, in_1, bit);
passed = 1'b0;
end
end else if (sel === 1'b0) begin
if (bit !== in_0) begin
$display("FAILED: %0s sel = 1'b0, expected %b, got %b",
comment, in_0, bit);
passed = 1'b0;
end
end else begin
z2x = (in_0 === 1'bz) ? 1'bx : in_0;
if (in_0 === in_1 && bit !== z2x) begin
$display("FAILED: %0s sel = 1'bx/z & ins = %b, expected 1'b%b, got %b",
comment, in_0, z2x, bit);
passed = 1'b0;
end else if (in_0 !== in_1 && bit !== 1'bx) begin
$display("FAILED: %0s sel = 1'bx/z & %b %b, expected 1'bx, got %b",
comment, in_1, in_0, bit);
passed = 1'b0;
end
end
end
endtask
// Check the 1 case as a constant Z
always @(cout0) begin
check(cout0, 1'bz, in_0, "CZ 1");
end
// Check the 0 case as a constant Z
always @(cout1) begin
check(cout1, in_1, 1'bz, "CZ 0");
end
// Check the continuous assign
always @(out) begin
check(out, in_1, in_0, "CA");
end
// Check procedural assign.
always @(sel, in_1, in_0) begin
check(sel ? in_1 : in_0, in_1, in_0, "PR");
end
initial begin
#1 sel = 1'b1;
#1 in_1 = 1'b0;
#1 in_1 = 1'b1;
#1 in_1 = 1'bz;
#1 in_1 = 1'bx;
#1 sel = 1'b0;
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 sel = 1'bx;
#1 in_1 = 1'b0; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'b1; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bz; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bx; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 sel = 1'bz;
#1 in_1 = 1'b0; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'b1; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bz; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bx; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 if (passed) $display("PASSED");
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( Ofast ) #pragma GCC optimization( unroll-loops, no-stack-protector ) #pragma GCC target( avx,avx2,fma ) using namespace std; using pii = pair<int, int>; using pll = pair<long long, long long>; using vb = vector<bool>; using vi = vector<int>; using vl = vector<long long>; using vvb = vector<vector<bool>>; using vvi = vector<vector<int>>; using vvl = vector<vector<long long>>; using vpii = vector<pair<int, int>>; using mii = map<int, int>; using umii = unordered_map<int, int>; using seti = set<int>; using useti = unordered_set<int>; template <typename... ArgTypes> void print(ArgTypes... args); template <typename... ArgTypes> void input(ArgTypes &...args); template <> void print() {} template <> void input() {} template <typename T, typename... ArgTypes> void print(T t, ArgTypes... args) { cout << t; print(args...); } template <typename T, typename... ArgTypes> void input(T &t, ArgTypes &...args) { cin >> t; input(args...); } template <class T> T OP(T a, T b) { if (a.first > b.first) return b; if (a.first == b.first && b.second > a.second) return b; return a; } template <class T> class SegmentTree { private: void propagate(int node, T val, int nodes) { tree[node].first += val.first; lazy[node].first += val.first; } T buildUtil(vector<T> &a, int node, int l, int r) { if (l == r) { tree[node] = a[l]; return tree[node]; } int mid = (l + r) >> 1; int leftNode = (node << 1) + 1; int rightNode = leftNode + 1; return tree[node] = OP(buildUtil(a, leftNode, l, mid), buildUtil(a, rightNode, mid + 1, r)); } T queryUtil(int node, int l, int r, int ql, int qr) { if (ql > r || qr < l) return (T)make_pair(1000000005, -1); if (l >= ql && r <= qr) return tree[node]; int mid = (l + r) >> 1; int leftNode = (node << 1) + 1; int rightNode = leftNode + 1; if (lazy[node].first) { propagate(leftNode, lazy[node], mid - l + 1); propagate(rightNode, lazy[node], r - mid); lazy[node].first = 0; } return OP(queryUtil(leftNode, l, mid, ql, qr), queryUtil(rightNode, mid + 1, r, ql, qr)); } T updateUtil(int node, int l, int r, int ql, int qr, T val) { if (ql > r || qr < l) return tree[node]; if (l >= ql && r <= qr) { tree[node].first += val.first; lazy[node].first += val.first; return tree[node]; } int mid = (l + r) >> 1; int leftNode = (node << 1) + 1; int rightNode = leftNode + 1; if (lazy[node].first) { propagate(leftNode, lazy[node], mid - l + 1); propagate(rightNode, lazy[node], r - mid); lazy[node].first = 0; } return tree[node] = OP(updateUtil(leftNode, l, mid, ql, qr, val), updateUtil(rightNode, mid + 1, r, ql, qr, val)); } public: int n; vector<T> tree; vector<T> lazy; SegmentTree(int n) { this->n = n; tree = vector<T>(4 * n); lazy = vector<T>(4 * n); } void build(vector<T> &a) { buildUtil(a, 0, 0, n - 1); } SegmentTree(vector<T> &a) { this->n = a.size(); tree = vector<T>(4 * n); lazy = vector<T>(4 * n); build(a); } T query(int l, int r) { return queryUtil(0, 0, n - 1, l, r); } void update(int l, int r, T val) { updateUtil(0, 0, n - 1, l, r, val); } }; template <class T, class OP> class FST { vector<T> t; void build() { for (int i = n - 1; i > 0; --i) t[i] = OP()(t[i << 1], t[i << 1 | 1]); } public: int n; FST(int nn) { n = nn; t = vector<T>(n << 1); } FST(vector<T> v) { n = v.size(); t = vector<T>(n << 1); for (int i = 0; i < n; ++i) t[i + n] = v[i]; build(); } void update(int p, T value) { value += query(p, p); for (t[p += n] = value; p > 1; p >>= 1) t[p >> 1] = OP()(t[p], t[p ^ 1]); } T query(int l, int r) { r++; T res = OP::initVal; for (l += n, r += n; l < r; l >>= 1, r >>= 1) { if (l & 1) res = OP()(res, t[l++]); if (r & 1) res = OP()(res, t[--r]); } return res; } }; template <class T> class Add { public: static const T initVal = T(0); T operator()(T x, T y) { return x + y; } }; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n, q; cin >> n >> q; vpii a(n); for (int i = 0; i < (n); (i)++) { cin >> a[i].first; a[i].second = i + 1; a[i].first = a[i].second - a[i].first; if (a[i].first < 0) a[i].first = 1000000005; } SegmentTree<pii> st(a); vi seq(n, -1); vi taken(n); int parent = n; while (1) { auto d = st.query(0, n - 1); if (d.first != 0) break; seq[d.second - 1] = parent; parent = min(parent, d.second - 1); taken[d.second - 1] = 1; st.update(d.second - 1, n - 1, {-1, 0}); st.update(d.second - 1, d.second - 1, {1000000005 + 1, 0}); } FST<int, Add<int>> track(n + 3); vector<pair<pii, pii>> queries; for (int qq = 0; qq < (q); (qq)++) { int x, y; cin >> x >> y; int l = x; int r = n - 1 - y; queries.push_back({{l, r}, {qq, 0}}); } int sq = (int)sqrt(q); sort((queries).begin(), (queries).end(), [=](pair<pii, pii> x, pair<pii, pii> y) -> bool { int blockX = x.first.first / sq; int blockY = y.first.first / sq; if (blockX < blockY) return true; if (blockX == blockY) return (blockX & 1) ^ (x.first.second < y.first.second); return false; }); int l = 0, r = 0; if (seq[0] != -1) track.update(seq[0], 1); for (pair<pii, pii> &qq : queries) { int x = qq.first.first; int y = qq.first.second; while (l < x) { int d = seq[l]; l++; if (d != -1) track.update(d, -1); } while (l > x) { int d = seq[l - 1]; l--; if (d != -1) track.update(d, 1); } while (r < y) { int d = seq[r + 1]; r++; if (d != -1) track.update(d, 1); } while (r > y) { int d = seq[r]; r--; if (d != -1) track.update(d, -1); } int temp = 0; if (x != 0) temp = track.query(0, x - 1); qq.second.second = track.query(0, n + 1) - temp; } sort((queries).begin(), (queries).end(), [=](pair<pii, pii> x, pair<pii, pii> y) -> bool { return x.second.first < y.second.first; }); for (auto qq : queries) cout << qq.second.second << n ; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; long long x; cin >> x; for (long long i = 0; i <= 1000; i++) { for (long long j = 0; j <= 10000; j++) { long long g = i * 1234567 + j * 123456; long long m = (x - g) / 1234; double l = (double)((x - g) / 1234); long long d = (long long)(l); if (m == d && m >= 0 && g + m * 1234 == x) { cout << YES << endl; return 0; } } } cout << NO << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$PR_pp$PG$N: D-latch, gated clear direct / gate active
* high (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dlatch$PR_pp$PG$N (
Q ,
D ,
GATE ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_PR_PP_PG_N_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O32A_SYMBOL_V
`define SKY130_FD_SC_HS__O32A_SYMBOL_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o32a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O32A_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NAND4BB_BEHAVIORAL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out;
wire or0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, D, C );
or or0 (or0_out_Y, B_N, A_N, nand0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4BB_BEHAVIORAL_V |
#include <bits/stdc++.h> const int N = int(1e5 + 3); using namespace std; bool is_prime(int n) { if (n == 2) return true; if (n % 2 == 0) return false; for (int i = 2; i * i <= n; ++i) if (n % i == 0) return false; return true; } void solve() { long long n; cin >> n; long long t = n / 3; long long t1 = (t - 1) + t * 2; long long t2 = (t) + (t + 1) * 2; long long t3 = (t) + t * 2; if (t1 == n) { cout << (t - 1) << << t << n ; ; } else if (t2 == n) { cout << t << << t + 1 << n ; ; } else if (t3 == n) { cout << t << << t << n ; ; } else { cout << t + 1 << << t << n ; ; } return; } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; string s; long long fastpow(int b, int e) { if (!e) return 1; if (e & 1) return b * fastpow(b, e - 1); long long temp = fastpow(b, e / 2); return temp * temp; } int notwork(char a, char b) { set<char> s; s.insert(a); s.insert(b); if (a == b && a == o ) return 0; if (a == b && a == A ) return 0; if (a == b && a == v ) return 0; if (a == b && a == V ) return 0; if (a == b && a == I ) return 0; if (a == b && a == H ) return 0; if (a == b && a == O ) return 0; if (a == b && a == M ) return 0; if (a == b && a == x ) return 0; if (a == b && a == X ) return 0; if (a == b && a == Y ) return 0; if (a == b && a == w ) return 0; if (a == b && a == W ) return 0; if (a == b && a == U ) return 0; if (a == b && a == T ) return 0; if (s.count( b ) && s.count( d )) return 0; if (s.count( p ) && s.count( q )) return 0; return 1; } int midwork(char a) { char arr[] = { U , T , W , w , Y , x , X , M , o , O , H , I , v , V , A }; for (int i = 0; i < 15; i++) if (arr[i] == a) return 1; return 0; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> s; int len = s.length(); int mid = len / 2; if (s.length() & 1 == 0) mid++; if (len & 1) { if (!midwork(s[mid])) return cout << NIE , 0; } for (int i = 0, j = len - 1; i < mid; i++, j--) { if (notwork(s[i], s[j])) return cout << NIE , 0; } cout << TAK ; return 0; } |
#include <bits/stdc++.h> using namespace std; struct Number { array<int, 4> x = {{0, 0, 0, 0}}; Number() {} Number(int a) { if (a != -1) x[a]++; } long double log_value() const { if (x[0] > 0) return -INFINITY; return x[2] * log(2L) + x[3] * log(3L); } int mod() const { long long result = 1; for (int i = 0; i < 4; i++) for (int j = 0; j < x[i]; j++) result = (result * i) % (int)(1e9 + 7); return result; } bool is_zero() const { return x[0] > 0; } }; bool operator<(const Number& a, const Number& b) { return a.log_value() < b.log_value(); } Number operator*(const Number& a, const Number& b) { Number result; for (int i = 0; i < 4; i++) result.x[i] = a.x[i] + b.x[i]; return result; } Number operator/(const Number& a, const Number& b) { Number result; for (int i = 0; i < 4; i++) result.x[i] = a.x[i] - b.x[i]; return result; } template <typename T> using Matrix = vector<vector<T>>; template <typename T> Matrix<T> matrix(int R, int C, T x = T()) { return Matrix<T>(R, vector<T>(C, x)); } struct RangeProduct { int N; Matrix<int> grid; Matrix<Number> hprod; Matrix<Number> vprod; bool valid(int r, int c) { return 0 <= r && r < N && 0 <= c && c < N; } RangeProduct(int N, Matrix<int> grid) : N(N), grid(grid) { hprod = matrix<Number>(N + 1, N + 1); vprod = matrix<Number>(N + 1, N + 1); for (int r = 0; r < N; r++) for (int c = 0; c < N; c++) { hprod[r][c + 1] = hprod[r][c] * Number(grid[r][c]); vprod[r + 1][c] = vprod[r][c] * Number(grid[r][c]); } } Number hquery(int r, int c, int radius) { int c1 = c - radius, c2 = c + radius; if (!valid(r, c1) || !valid(r, c2)) return Number(0); return hprod[r][c2 + 1] / hprod[r][c1]; } Number vquery(int r, int c, int radius) { int r1 = r - radius, r2 = r + radius; if (!valid(r1, c) || !valid(r2, c)) return Number(0); return vprod[r2 + 1][c] / vprod[r1][c]; } Number cross(int r, int c, int radius) { return hquery(r, c, radius) * vquery(r, c, radius) / Number(grid[r][c]); } Number max_cross(int r, int c) { int a = 0, b = N; while (a < b) { int mid = (a + b + 1) / 2; if (cross(r, c, mid).is_zero()) b = mid - 1; else a = mid; } return cross(r, c, a); } }; Number solve(int N, Matrix<int> grid) { RangeProduct rp(N, grid); Number result(0); for (int r = 0; r < N; r++) for (int c = 0; c < N; c++) result = max(result, rp.max_cross(r, c)); return result; } Matrix<int> rotate(int N, const Matrix<int>& grid, int shift) { auto ngrid = matrix<int>(N, N); for (int r = 0; r < N; r++) for (int c = 0; c < N; c++) if ((r + c) % 2 == shift) ngrid[(r + c) / 2][(r - c + N) / 2] = grid[r][c]; return ngrid; } int main() { int N; cin >> N; auto grid = matrix<int>(N, N); for (int i = 0; i < N; i++) { string s; cin >> s; for (int j = 0; j < N; j++) grid[i][j] = s[j] - 0 ; } auto rgrid0 = rotate(N, grid, 0); auto rgrid1 = rotate(N, grid, 1); Number answer = max({solve(N, grid), solve(N, rgrid0), solve(N, rgrid1)}); cout << answer.mod() << endl; } |
#include <bits/stdc++.h> using namespace std; int n, r; vector<pair<int, int> > pos, L, R; vector<int> ans; map<pair<int, int>, int> vis; bool cmp(pair<int, int> a, pair<int, int> b) { return a.first + a.second < b.first + b.second; } int main() { cin >> n >> r; for (int i = 0; i < n; i++) { int x, y; cin >> x >> y; vis[{x, y}]++; if (y >= 0) pos.push_back({x, y}); else R.push_back({y, x}), L.push_back({x, y}); } sort(pos.begin(), pos.end()); sort(L.rbegin(), L.rend(), cmp); vector<pair<int, int> > aux; for (pair<int, int> x : pos) { while (aux.size() && r >= aux.back().first) { r += aux.back().second; aux.pop_back(); } if (r < x.first) { aux.push_back(x); } else { r += x.second; } } if (aux.size()) { cout << NO << endl; return 0; } for (pair<int, int> x : L) { if (r < x.first) { cout << NO << endl; return 0; } r += x.second; } if (r < 0) cout << NO << endl; else cout << YES << endl; } |
#include <bits/stdc++.h> using namespace std; struct graph { int n; vector<vector<int>> adj; graph(int n) : n(n), adj(n) {} void add_edge(int u, int v) { adj[u].push_back(v); } vector<int> &operator[](int u) { return adj[u]; } }; vector<vector<int>> scc_gabow(graph &adj) { int n = adj.n; vector<vector<int>> scc; vector<int> S, B, I(n); function<void(int)> dfs = [&](int u) { B.push_back(I[u] = S.size()); S.push_back(u); for (int v : adj[u]) if (!I[v]) dfs(v); else while (I[v] < B.back()) B.pop_back(); if (I[u] == B.back()) { scc.push_back({}); for (B.pop_back(); I[u] < S.size(); S.pop_back()) { scc.back().push_back(S.back()); I[S.back()] = n + scc.size(); } } }; for (int u = 0; u < n; ++u) if (!I[u]) dfs(u); return scc; } const long long mod = 1000000007; int main() { ios_base::sync_with_stdio(0); cin.tie(0); int n; cin >> n; vector<long long> a(n); for (int i = 0; i < n; ++i) cin >> a[i]; graph adj(n); int m; cin >> m; for (int i = 0; i < m; ++i) { int u, v; cin >> u >> v; adj.add_edge(--u, --v); } auto scc = scc_gabow(adj); long long mn = 0, ways = 1; for (auto &comp : scc) { long long best = a[comp[0]], total = 0; for (int u : comp) if (a[u] == best) ++total; else if (a[u] < best) best = a[u], total = 1; mn += best; ways = ways * total % mod; } cout << mn << << ways << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<long long> primes; bool vis[20000000]; vector<long long> a, b; long long v[20000000]; void genp() { for (long long i = 2; i < 20000000; i++) { if (!vis[i]) { primes.push_back(i); for (long long j = 1; j * i < 20000000; j++) vis[j * i] = 1; } } } void mark(long long x) { for (long long i = 2; i <= sqrt(x); i++) { long long z = i; if (x % z == 0) { long long f = x / z; for (long long j = 1; j * z < 20000000; j++) v[j * z] = 1; for (long long j = 1; j * f < 20000000; j++) v[j * f] = 1; } } long long z = x; for (long long j = 1; j * z < 20000000; j++) v[j * z] = 1; } int main() { ios_base::sync_with_stdio(0); genp(); v[0] = 1; v[1] = 1; long long n; cin >> n; for (long long i = 0; i < n; i++) { long long x; cin >> x; a.push_back(x); } bool ok = 0; long long s = 2; for (long long i = 0; i < n; i++) { if (!ok) { long long x = a[i]; if (!v[x]) { b.push_back(x); mark(x); } else { ok = 1; for (long long k = x + 1; k <= 1e9; k++) { if (!v[k]) { b.push_back(k); mark(k); break; } } } } else { for (s = s; s <= 1e9; s++) { if (!v[s]) { b.push_back(s); mark(s); break; } } } } for (long long i = 0; i < n; i++) cout << b[i] << ; cout << endl; } |
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_lin2exp(
input [15:0] lin,
output reg [9:0] man,
output reg [2:0] exp
);
always @(*) begin
casex( lin[15:9] )
// negative numbers
7'b10XXXXX: begin
man = lin[15:6];
exp = 3'd7;
end
7'b110XXXX: begin
man = lin[14:5];
exp = 3'd6;
end
7'b1110XXX: begin
man = lin[13:4];
exp = 3'd5;
end
7'b11110XX: begin
man = lin[12:3];
exp = 3'd4;
end
7'b111110X: begin
man = lin[11:2];
exp = 3'd3;
end
7'b1111110: begin
man = lin[10:1];
exp = 3'd2;
end
7'b1111111: begin
man = lin[ 9:0];
exp = 3'd1;
end
// positive numbers
7'b01XXXXX: begin
man = lin[15:6];
exp = 3'd7;
end
7'b001XXXX: begin
man = lin[14:5];
exp = 3'd6;
end
7'b0001XXX: begin
man = lin[13:4];
exp = 3'd5;
end
7'b00001XX: begin
man = lin[12:3];
exp = 3'd4;
end
7'b000001X: begin
man = lin[11:2];
exp = 3'd3;
end
7'b0000001: begin
man = lin[10:1];
exp = 3'd2;
end
7'b0000000: begin
man = lin[ 9:0];
exp = 3'd1;
end
default: begin
man = lin[9:0];
exp = 3'd1;
end
endcase
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:54:10 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_1_0/system_vga_gaussian_blur_1_0_stub.v
// Design : system_vga_gaussian_blur_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_gaussian_blur,Vivado 2016.4" *)
module system_vga_gaussian_blur_1_0(clk_25, hsync_in, vsync_in, rgb_in, hsync_out,
vsync_out, rgb_blur, rgb_pass)
/* synthesis syn_black_box black_box_pad_pin="clk_25,hsync_in,vsync_in,rgb_in[23:0],hsync_out,vsync_out,rgb_blur[23:0],rgb_pass[23:0]" */;
input clk_25;
input hsync_in;
input vsync_in;
input [23:0]rgb_in;
output hsync_out;
output vsync_out;
output [23:0]rgb_blur;
output [23:0]rgb_pass;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pcie_pipe_misc.v
// Version : 3.2
//
// Description: Misc PIPE module for 7-Series PCIe Block
//
//
//
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_pcie_pipe_misc #
(
parameter PIPE_PIPELINE_STAGES = 0, // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
parameter TCQ = 1 // synthesis warning solved: parameter declaration becomes local
)
(
input wire pipe_tx_rcvr_det_i , // PIPE Tx Receiver Detect
input wire pipe_tx_reset_i , // PIPE Tx Reset
input wire pipe_tx_rate_i , // PIPE Tx Rate
input wire pipe_tx_deemph_i , // PIPE Tx Deemphasis
input wire [2:0] pipe_tx_margin_i , // PIPE Tx Margin
input wire pipe_tx_swing_i , // PIPE Tx Swing
output wire pipe_tx_rcvr_det_o , // Pipelined PIPE Tx Receiver Detect
output wire pipe_tx_reset_o , // Pipelined PIPE Tx Reset
output wire pipe_tx_rate_o , // Pipelined PIPE Tx Rate
output wire pipe_tx_deemph_o , // Pipelined PIPE Tx Deemphasis
output wire [2:0] pipe_tx_margin_o , // Pipelined PIPE Tx Margin
output wire pipe_tx_swing_o , // Pipelined PIPE Tx Swing
input wire pipe_clk , // PIPE Clock
input wire rst_n // Reset
);
//******************************************************************//
// Reality check. //
//******************************************************************//
// parameter TCQ = 1; // clock to out delay model
generate
if (PIPE_PIPELINE_STAGES == 0) begin : pipe_stages_0
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
end // if (PIPE_PIPELINE_STAGES == 0)
else if (PIPE_PIPELINE_STAGES == 1) begin : pipe_stages_1
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
end // if (PIPE_PIPELINE_STAGES == 1)
else if (PIPE_PIPELINE_STAGES == 2) begin : pipe_stages_2
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
always @(posedge pipe_clk) begin
if (rst_n)
begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
pipe_tx_rcvr_det_qq <= #TCQ 0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 0;
pipe_tx_swing_qq <= #TCQ 0;
end
else
begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
end // if (PIPE_PIPELINE_STAGES == 2)
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; struct pt { double x, y; }; pt a[1005]; long long n; double kv(double g) { return g * g; } double dist(pt a, pt b) { return sqrt(kv(a.x - b.x) + kv(a.y - b.y)); } double visina(pt a, pt b, pt c) { return abs((b.y - a.y) * c.x - (b.x - a.x) * c.y + b.x * a.y - b.y * a.x) / (dist(a, b)); } int main() { cout.precision(15); cout << fixed; cin >> n; for (long i = 0; i < n; i++) { cin >> a[i].x >> a[i].y; } double d = 1e17; for (long i = 0; i < n; i++) { pt x = a[i], y = a[(i + 1) % n], z = a[(i + 2) % n]; d = min(d, visina(x, y, z)); d = min(d, visina(y, z, x)); d = min(d, visina(z, x, y)); } cout << d / 2 << endl; } |
#include <bits/stdc++.h> using namespace std; void code() { int n; cin>>n; string s; cin>>s; set<char> used; char last= - ; bool possible=true; for(char& c:s) { if(c!=last) { if(used.find(c)!=used.end()) { possible=false; break; } } last=c; used.insert(c); } if(possible) cout<< YES ; else cout<< NO ; cout<< n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int t=1; cin>>t; for(int tt=1;tt<=t;++tt) { code(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long n, m, i, j; char x[2], y[2], t; cin >> n >> m; cin >> x[0]; for (i = 2; i < n; i++) cin >> t; cin >> x[1] >> y[0]; y[0] = (y[0] == ^ ) ? > : < ; for (j = 2; j < m; j++) cin >> t; cin >> y[1]; y[1] = (y[1] == ^ ) ? > : < ; if (x[0] == y[0] && x[1] == y[1] && x[0] != x[1]) cout << YES ; else cout << NO ; } |
#include <bits/stdc++.h> using std ::vector; template <typename Tp> Tp Max(const Tp &a, const Tp &b) { return a > b ? a : b; } template <typename Tp> Tp Min(const Tp &a, const Tp &b) { return a < b ? a : b; } template <typename Tp> Tp Abs(const Tp &a) { return a > 0 ? a : -a; } template <typename Tp> void Read(Tp &x) { Tp in = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { in = in * 10 + ch - 0 ; ch = getchar(); } x = in * f; } const int SN = 200000 + 10; vector<int> G[SN]; int a[SN], b[SN], c[SN], min[SN], n; int res0[SN], res1[SN]; long long ans; void pre(int u, int fa) { for (auto v : G[u]) if (v != fa) min[v] = Min(min[v], min[u]); for (auto v : G[u]) if (v != fa) pre(v, u); } void Dfs(int u, int fa) { if (b[u] != c[u]) if (b[u] == 0) res0[u]++; else res1[u]++; for (auto v : G[u]) if (v != fa) Dfs(v, u), res1[u] += res1[v], res0[u] += res0[v]; int K = Min(res0[u], res1[u]); ans += 2LL * K * min[u]; res0[u] -= K, res1[u] -= K; } int main(int argc, const char *argv[]) { Read(n); for (int i = 1; i <= n; i++) Read(a[i]), Read(b[i]), Read(c[i]), min[i] = a[i]; int u, v; for (int i = 1; i < n; i++) { Read(u), Read(v); G[u].push_back(v); G[v].push_back(u); } u = 0, v = 0; for (int i = 1; i <= n; i++) { if (b[i] == 0) u++; if (c[i] == 0) v++; } if (u != v) { printf( -1 n ); return 0; } pre(1, 0); Dfs(1, 0); printf( %lld n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { long long int c, hr, hb, wr, wb; cin >> c >> hr >> hb >> wr >> wb; long long int ret = 0, ret1 = 0; int cnt = 0; for (long long int i = 0; i <= (c / wr); i++) { long long int r = i * wr; long long int l = c - r; long long int b = l / wb; ret1 = i * hr + b * hb; ret = max(ret, ret1); cnt++; if (cnt > 1e7) break; } cnt = 0; for (long long int i = 0; i <= (c / wb); i++) { long long int r = i * wb; long long int l = c - r; long long int b = l / wr; ret1 = i * hb + b * hr; ret = max(ret, ret1); cnt++; if (cnt > 1e7) break; } cout << ret << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 1000000000; int main() { ios_base::sync_with_stdio(0); int n; cin >> n; vector<string> a(n); map<string, int> M; for (int i = 0; i < n; ++i) { cin >> a[i]; M[a[i]] = i; } vector<vector<int> > Inv(1 << n, vector<int>(n, 0)); for (int mask = 1; mask < (1 << n); ++mask) for (int j = 0; j < n; ++j) if ((mask & (1 << j)) == 0) for (int l = 0; l < n; ++l) if ((mask & (1 << l)) > 0 && M[a[j]] < M[a[l]]) ++Inv[mask][j]; int m; cin >> m; int p = -1, nr; for (int i = 0; i < m; ++i) { int k; cin >> k; vector<string> b(k); for (int j = 0; j < k; ++j) cin >> b[j]; vector<vector<int> > nast(k, vector<int>(n, INF)); if (M.find(b[k - 1]) != M.end()) nast[k - 1][M[b[k - 1]]] = k - 1; for (int j = k - 2; j >= 0; --j) { for (int l = 0; l < n; ++l) nast[j][l] = nast[j + 1][l]; if (M.find(b[j]) != M.end()) nast[j][M[b[j]]] = j; } vector<vector<int> > dp((1 << n), vector<int>(n * (n - 1) / 2 + 1, INF)); for (int j = 0; j < n; ++j) if (nast[0][j] != INF) dp[1 << j][0] = nast[0][j]; for (int mask = 1; mask < (1 << n); ++mask) { for (int inv = 0; inv <= n * (n - 1) / 2; ++inv) { if (dp[mask][inv] == INF) continue; for (int j = 0; j < n; ++j) { if ((mask & (1 << j)) == 0) { int noweInv = inv + Inv[mask][j]; if (dp[mask][inv] + 1 < k && nast[dp[mask][inv] + 1][j] != INF) dp[mask | (1 << j)][noweInv] = min(dp[mask | (1 << j)][noweInv], nast[dp[mask][inv] + 1][j]); } } } } for (int j = 0; j <= n * (n - 1) / 2; ++j) { if (dp[(1 << n) - 1][j] != INF && n * (n - 1) / 2 - j + 1 > p) { p = n * (n - 1) / 2 - j + 1; nr = i; } } } if (p == -1) cout << Brand new problem! ; else { cout << nr + 1 << endl; cout << [: ; for (int i = 0; i < p; ++i) cout << | ; cout << :] ; } return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> T gcd(T a, T b) { return b ? gcd(b, a % b) : a; } const int maxn = 1000100; char s[maxn]; vector<int> a[maxn]; void solve() { cin >> s; int n = strlen(s); int c = 0; for (int i = 0; i < n; i++) { c += s[i] == 0 ? 1 : -1; if (c < 0) { puts( -1 ); return; } } c = 0; for (int i = n - 1; i >= 0; i--) { c += s[i] == 0 ? 1 : -1; if (c < 0) { puts( -1 ); return; } } int nol = 0, bir = 0; for (int i = 0; i < n; i++) { if (s[i] == 0 ) { if (bir) { a[bir - 1].push_back(i + 1); bir--; } else { nol++; a[nol - 1].push_back(i + 1); } } else { a[bir].push_back(i + 1); bir++; } } cout << nol << endl; for (int i = 0; i < nol; i++) { printf( %d , a[i].size()); for (int j = 0; j < a[i].size(); j++) printf( %d , a[i][j]); cout << endl; } } int main() { int t = 1; while (t--) { solve(); } } |
// This module performs a rounding of a floating-point number. This rounding is expected to happen after the barrel shifter
// shifts the data to a position with leading 1 in the most significant bit of the input.
module acl_fp_custom_round_post(
clock, resetn, mantissa, exponent, sign, mantissa_out, exponent_out, sign_out,
valid_in, valid_out, stall_in, stall_out, enable);
parameter HIGH_CAPACITY = 1;
parameter FLUSH_DENORMS = 0;
parameter HIGH_LATENCY = 1;
parameter ROUNDING_MODE = 0;
parameter REMOVE_STICKY = 0;
parameter FINITE_MATH_ONLY = 0;
input clock, resetn;
input stall_in, valid_in;
output stall_out, valid_out;
input enable;
// Data in
input [26:0] mantissa;
input [8:0] exponent; // Exponent with MSB set to 1 is an exception.
input sign;
// Data output
output [26:0] mantissa_out; // When mantissa_out[25] = 1 and exponent_out[8] == 1 then the number is NaN.
output [8:0] exponent_out; // Exponent with MSB set to 1 is an exception.
output sign_out;
reg c1_valid;
reg c2_valid;
wire c1_stall;
wire c2_stall;
wire c1_enable;
wire c2_enable;
// Cycle 1 - first check for overflow. Shift data right by one bit if this is the case.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [27:0] c1_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c1_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_sign;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_exponent_is_max;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_exponent_is_nonzero;
assign c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
wire [25:0] rounding = mantissa[26:2] + 1'b1;
generate
if (HIGH_LATENCY == 1)
begin
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_mantissa <= 28'dx;
c1_exponent <= 9'dx;
c1_sign <= 1'bx;
c1_exponent_is_max <= 1'bx;
c1_exponent_is_nonzero <= 1'bx;
c1_valid <= 1'b0;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
c1_sign <= sign;
c1_exponent_is_max <= (&exponent[7:1]) & ~exponent[0];
c1_exponent_is_nonzero <= |exponent[7:0];
c1_exponent <= exponent;
if (FINITE_MATH_ONLY == 1)
begin
if ((&mantissa[3:2] || (mantissa[2] & (|mantissa[1:0]))))
c1_mantissa <= {rounding, 2'b00}; // Also clear the least significant bits since you just rounded them up.
else
c1_mantissa <= {1'b0, mantissa};
end
else
begin
if (~exponent[8] & (&mantissa[3:2] || (mantissa[2] & (|mantissa[1:0]))))
c1_mantissa <= {rounding, 2'b00}; // Also clear the least significant bits since you just rounded them up.
else
c1_mantissa <= {1'b0, mantissa};
end
end
end
end
else
begin
// In low-latency mode do not register this stage.
always@(*)
begin
c1_valid <= valid_in;
c1_sign <= sign;
c1_exponent_is_max <= (&exponent[7:1]) & ~exponent[0];
c1_exponent_is_nonzero <= |exponent[7:0];
c1_exponent <= exponent;
if (FINITE_MATH_ONLY == 1)
begin
if ((&mantissa[3:2] || (mantissa[2] & (|mantissa[1:0]))))
c1_mantissa <= {rounding, 2'b00}; // Also clear the least significant bits since you just rounded them up.
else
c1_mantissa <= {1'b0, mantissa};
end
else
begin
if (~exponent[8] & (&mantissa[3:2] || (mantissa[2] & (|mantissa[1:0]))))
c1_mantissa <= {rounding, 2'b00}; // Also clear the least significant bits since you just rounded them up.
else
c1_mantissa <= {1'b0, mantissa};
end
end
end
endgenerate
// Cycle 2 - Compute any necessary rounding and apply it.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [26:0] c2_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c2_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_sign;
assign c2_enable = (HIGH_CAPACITY == 1) ? (~c2_valid | ~c2_stall) : enable;
assign c1_stall = c2_valid & c2_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c2_mantissa <= 28'dx;
c2_exponent <= 9'dx;
c2_sign <= 1'bx;
c2_valid <= 1'b0;
end
else if (c2_enable)
begin
c2_valid <= c1_valid;
c2_sign <= c1_sign;
if ((FINITE_MATH_ONLY == 0) && (c1_mantissa[27] & ~c1_exponent[8]))
begin
if (c1_exponent_is_max)
c2_mantissa <= 27'h4000000;
else
begin
if (REMOVE_STICKY == 1)
c2_mantissa <= c1_mantissa[27:1];
else
c2_mantissa <= {c1_mantissa[27:2], |c1_mantissa[1:0]};
end
end
else
begin
if (FLUSH_DENORMS == 1)
c2_mantissa <= c1_mantissa[26:0] & {27{c1_exponent_is_nonzero}};
else
c2_mantissa <= c1_mantissa[26:0];
end
if ((FINITE_MATH_ONLY == 0) && (c1_exponent[8] | c1_mantissa[27] & c1_exponent_is_max))
c2_exponent <= 9'h1ff;
else
c2_exponent <= c1_exponent + {1'b0, c1_mantissa[27] & ~c1_exponent_is_nonzero,
c1_mantissa[27] & c1_exponent_is_nonzero | ~c1_mantissa[27] & c1_mantissa[26] & ~c1_exponent_is_nonzero};
end
end
assign mantissa_out = c2_mantissa;
assign exponent_out = c2_exponent;
assign sign_out = c2_sign;
assign valid_out = c2_valid;
assign c2_stall = stall_in;
endmodule
|
#include <bits/stdc++.h> using namespace std; int m, n, cnt = 0; vector<vector<int> > g; vector<int> outgroup; int main() { cin >> n >> m; vector<int> emptyg; g.push_back(emptyg); for (int i = 1; i <= n; i++) { vector<int> subg; g.push_back(subg); } for (int i = 0; i < m; i++) { int fr, to; cin >> fr >> to; g[fr].push_back(to); g[to].push_back(fr); } while (true) { outgroup.clear(); cerr << cnt == << cnt << endl; for (int i = 1; i <= n; i++) { int deg = g[i].size(); cerr << node << i << has degree << deg << n ; if (deg == 1) { outgroup.push_back(i); } cerr.flush(); } if (outgroup.empty()) { cout << cnt << endl; return 0; } vector<int>::iterator it = outgroup.begin(); for (; it != outgroup.end(); it++) { int nodetodelete = *it; cerr << deleting node << nodetodelete << ... << endl; int onlyconnectednode; if (!g[nodetodelete].empty()) { onlyconnectednode = g[nodetodelete][0]; } else { continue; } vector<int>::iterator adjit = g[onlyconnectednode].begin(); for (; adjit != g[onlyconnectednode].end(); adjit++) { if (*adjit == nodetodelete) { g[onlyconnectednode].erase(adjit); break; } } g[nodetodelete].clear(); } cnt = cnt + 1; cerr << has the thread reached here? << endl; bool isEnd = true; vector<vector<int> >::iterator ggit = g.begin(); for (; ggit != g.end(); ggit++) { vector<int> thissubg = *ggit; isEnd = thissubg.size() == 1 ? false : isEnd; } if (isEnd) { break; } } cout << cnt << endl; return 0; } |
// https://coredocs.s3.amazonaws.com/Libero/12_0_0/Tool/sf2_mlg.pdf
module ADD2 (
input A, B,
output Y
);
assign Y = A & B;
endmodule
module ADD3 (
input A, B, C,
output Y
);
assign Y = A & B & C;
endmodule
module ADD4 (
input A, B, C, D,
output Y
);
assign Y = A & B & C & D;
endmodule
module CFG1 (
output Y,
input A
);
parameter [1:0] INIT = 2'h0;
assign Y = INIT >> A;
endmodule
module CFG2 (
output Y,
input A,
input B
);
parameter [3:0] INIT = 4'h0;
assign Y = INIT >> {B, A};
endmodule
module CFG3 (
output Y,
input A,
input B,
input C
);
parameter [7:0] INIT = 8'h0;
assign Y = INIT >> {C, B, A};
endmodule
module CFG4 (
output Y,
input A,
input B,
input C,
input D
);
parameter [15:0] INIT = 16'h0;
assign Y = INIT >> {D, C, B, A};
endmodule
module BUFF (
input A,
output Y
);
assign Y = A;
endmodule
module BUFD (
input A,
output Y
);
assign Y = A;
endmodule
module CLKINT (
input A,
(* clkbuf_driver *)
output Y
);
assign Y = A;
endmodule
module CLKINT_PRESERVE (
input A,
(* clkbuf_driver *)
output Y
);
assign Y = A;
endmodule
module GCLKINT (
input A, EN,
(* clkbuf_driver *)
output Y
);
assign Y = A & EN;
endmodule
module RCLKINT (
input A,
(* clkbuf_driver *)
output Y
);
assign Y = A;
endmodule
module RGCLKINT (
input A, EN,
(* clkbuf_driver *)
output Y
);
assign Y = A & EN;
endmodule
module SLE (
output Q,
input ADn,
input ALn,
(* clkbuf_sink *)
input CLK,
input D,
input LAT,
input SD,
input EN,
input SLn
);
reg q_latch, q_ff;
always @(posedge CLK, negedge ALn) begin
if (!ALn) begin
q_ff <= !ADn;
end else if (EN) begin
if (!SLn)
q_ff <= SD;
else
q_ff <= D;
end
end
always @* begin
if (!ALn) begin
q_latch <= !ADn;
end else if (CLK && EN) begin
if (!SLn)
q_ff <= SD;
else
q_ff <= D;
end
end
assign Q = LAT ? q_latch : q_ff;
endmodule
// module AR1
// module FCEND_BUFF
// module FCINIT_BUFF
// module FLASH_FREEZE
// module OSCILLATOR
// module SYSRESET
// module SYSCTRL_RESET_STATUS
// module LIVE_PROBE_FB
(* blackbox *)
module GCLKBUF (
(* iopad_external_pin *)
input PAD,
input EN,
(* clkbuf_driver *)
output Y
);
endmodule
(* blackbox *)
module GCLKBUF_DIFF (
(* iopad_external_pin *)
input PADP,
(* iopad_external_pin *)
input PADN,
input EN,
(* clkbuf_driver *)
output Y
);
endmodule
(* blackbox *)
module GCLKBIBUF (
input D,
input E,
input EN,
(* iopad_external_pin *)
inout PAD,
(* clkbuf_driver *)
output Y
);
endmodule
// module DFN1
// module DFN1C0
// module DFN1E1
// module DFN1E1C0
// module DFN1E1P0
// module DFN1P0
// module DLN1
// module DLN1C0
// module DLN1P0
module INV (
input A,
output Y
);
assign Y = !A;
endmodule
module INVD (
input A,
output Y
);
assign Y = !A;
endmodule
module MX2 (
input A, B, S,
output Y
);
assign Y = S ? B : A;
endmodule
module MX4 (
input D0, D1, D2, D3, S0, S1,
output Y
);
assign Y = S1 ? (S0 ? D3 : D2) : (S0 ? D1 : D0);
endmodule
module NAND2 (
input A, B,
output Y
);
assign Y = !(A & B);
endmodule
module NAND3 (
input A, B, C,
output Y
);
assign Y = !(A & B & C);
endmodule
module NAND4 (
input A, B, C, D,
output Y
);
assign Y = !(A & B & C & D);
endmodule
module NOR2 (
input A, B,
output Y
);
assign Y = !(A | B);
endmodule
module NOR3 (
input A, B, C,
output Y
);
assign Y = !(A | B | C);
endmodule
module NOR4 (
input A, B, C, D,
output Y
);
assign Y = !(A | B | C | D);
endmodule
module OR2 (
input A, B,
output Y
);
assign Y = A | B;
endmodule
module OR3 (
input A, B, C,
output Y
);
assign Y = A | B | C;
endmodule
module OR4 (
input A, B, C, D,
output Y
);
assign Y = A | B | C | D;
endmodule
module XOR2 (
input A, B,
output Y
);
assign Y = A ^ B;
endmodule
module XOR3 (
input A, B, C,
output Y
);
assign Y = A ^ B ^ C;
endmodule
module XOR4 (
input A, B, C, D,
output Y
);
assign Y = A ^ B ^ C ^ D;
endmodule
module XOR8 (
input A, B, C, D, E, F, G, H,
output Y
);
assign Y = A ^ B ^ C ^ D ^ E ^ F ^ G ^ H;
endmodule
// module UJTAG
module BIBUF (
input D,
input E,
(* iopad_external_pin *)
inout PAD,
output Y
);
assign PAD = E ? D : 1'bz;
assign Y = PAD;
endmodule
(* blackbox *)
module BIBUF_DIFF (
input D,
input E,
(* iopad_external_pin *)
inout PADP,
(* iopad_external_pin *)
inout PADN,
output Y
);
endmodule
module CLKBIBUF (
input D,
input E,
(* iopad_external_pin *)
inout PAD,
(* clkbuf_driver *)
output Y
);
assign PAD = E ? D : 1'bz;
assign Y = PAD;
endmodule
module CLKBUF (
(* iopad_external_pin *)
input PAD,
(* clkbuf_driver *)
output Y
);
assign Y = PAD;
endmodule
(* blackbox *)
module CLKBUF_DIFF (
(* iopad_external_pin *)
input PADP,
(* iopad_external_pin *)
input PADN,
(* clkbuf_driver *)
output Y
);
endmodule
module INBUF (
(* iopad_external_pin *)
input PAD,
output Y
);
assign Y = PAD;
endmodule
(* blackbox *)
module INBUF_DIFF (
(* iopad_external_pin *)
input PADP,
(* iopad_external_pin *)
input PADN,
output Y
);
endmodule
module OUTBUF (
input D,
(* iopad_external_pin *)
output PAD
);
assign PAD = D;
endmodule
(* blackbox *)
module OUTBUF_DIFF (
input D,
(* iopad_external_pin *)
output PADP,
(* iopad_external_pin *)
output PADN
);
endmodule
module TRIBUFF (
input D,
input E,
(* iopad_external_pin *)
output PAD
);
assign PAD = E ? D : 1'bz;
endmodule
(* blackbox *)
module TRIBUFF_DIFF (
input D,
input E,
(* iopad_external_pin *)
output PADP,
(* iopad_external_pin *)
output PADN
);
endmodule
// module DDR_IN
// module DDR_OUT
// module RAM1K18
// module RAM64x18
// module MACC
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, l, x, y; set<long long> Set; while (cin >> n >> l >> x >> y) { for (int i = 1; i <= n; ++i) { long long t; scanf( %I64d , &t); Set.insert(t); } bool checkx = 0; bool checky = 0; for (set<long long>::iterator it = Set.begin(); it != Set.end(); it++) { if (Set.find(*it + x) != Set.end()) { checkx = 1; } if (Set.find(*it + y) != Set.end()) { checky = 1; } if (checkx && checky) { break; } } if (checkx && checky) { cout << 0 << endl; break; } if (checkx) { cout << 1 << endl; cout << y << endl; break; } if (checky) { cout << 1 << endl; cout << x << endl; break; } bool find = 0; long long ans = 0; for (set<long long>::iterator it = Set.begin(); it != Set.end(); it++) { if ((*it + x <= l) && Set.find(*it + x + y) != Set.end()) { find = 1; ans = *it + x; break; } if ((*it + x <= l) && Set.find(*it + x - y) != Set.end()) { find = 1; ans = *it + x; break; } if ((*it - x >= 0) && Set.find(*it - x + y) != Set.end()) { find = 1; ans = *it - x; break; } if ((*it - x >= 0) && Set.find(*it - x - y) != Set.end()) { find = 1; ans = *it - x; break; } } if (find) { cout << 1 << endl; cout << ans << endl; break; } cout << 2 << endl; cout << x << << y << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; char s[2000]; int n, len, ans; int dpmin[120][55][2], dpmax[120][55][2]; bool u[120][55][2]; int inf = 10005000; bool go(int i, int n, int d) { if (i == len) { if (n % 2 == 0) return 1; return 0; } if (u[i][n][d]) return 1; u[i][n][d] = 1; dpmin[i][n][d] = inf; dpmax[i][n][d] = -inf; if (s[i] == F ) { if (go(i + 1, n, d)) { dpmin[i][n][d] = min(dpmin[i][n][d], (d ? -1 : 1) + dpmin[i + 1][n][d]); dpmax[i][n][d] = max(dpmax[i][n][d], (d ? -1 : 1) + dpmax[i + 1][n][d]); } if (n > 0 && go(i + 1, n - 1, d ^ 1)) { dpmin[i][n][d] = min(dpmin[i][n][d], dpmin[i + 1][n - 1][d ^ 1]); dpmax[i][n][d] = max(dpmax[i][n][d], dpmax[i + 1][n - 1][d ^ 1]); } } else { if (n > 0 && go(i + 1, n - 1, d)) { dpmin[i][n][d] = min(dpmin[i][n][d], (d ? -1 : 1) + dpmin[i + 1][n - 1][d]); dpmax[i][n][d] = max(dpmax[i][n][d], (d ? -1 : 1) + dpmax[i + 1][n - 1][d]); } if (go(i + 1, n, d ^ 1)) { dpmin[i][n][d] = min(dpmin[i][n][d], dpmin[i + 1][n][d ^ 1]); dpmax[i][n][d] = max(dpmax[i][n][d], dpmax[i + 1][n][d ^ 1]); } } return 1; } int main() { scanf( %s%d , s, &n); len = strlen(s); go(0, n, 0); ans = max(-dpmin[0][n][0], dpmax[0][n][0]); printf( %d n , ans); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 14:56:48
// Design Name:
// Module Name: sandbox
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sandbox
(
input wire GCLK,
output wire [7:0] LD,
input wire [7:0] SW,
output wire [7:0] JA,
input wire [7:0] JB,
input wire BTNC,
input wire BTND,
input wire BTNL,
input wire BTNR,
input wire BTNU
);
wire SS;
wire SCLK;
reg SS_REG = 1'b0;
reg SCLK_REG = 1'b0;
reg LDAC_REG = 1'b1;
reg MOSI_REG = 1'b0;
reg GCLK;
reg snd;
reg set;
reg LEFT;
reg RST;
wire LDAC;
wire LCLK;
wire pulse;
reg [11:0] TX = 12'd0;
reg cstate = 0;
reg ostate = 0;
assign JA[1] = SS_REG;
assign JA[2] = SCLK_REG;
assign JA[3] = MOSI_REG;
assign JA[4] = LDAC_REG;
assign JA[5] = LCLK;
assign JA[6] = pulse;
assign JA[7] = set;
always @(posedge GCLK) begin
SS_REG <= SS;
SCLK_REG <= SCLK;
MOSI_REG <= MOSI;
LDAC_REG <= LDAC;
set <= pulse;
snd <= pulse;
end
always @(posedge LCLK) begin
TX <= 16'd771;
end
DAC dac
(
.CLK(GCLK),
.DIV(64'd1000),
.DATA(TX),
.SEND(snd),
.SET(set),
.SCK(SCLK),
.MOSI(MOSI),
.CS(SS),
.LDAC(LDAC)
);
CLK_DIV clk_div
(
.GCLK(GCLK),
.out(LCLK),
.T(64'd100000),
.PULSE(pulse)
);
MEMORY memory
(
.ADDR(10'd123),
.CLK(GCLK),
.RE(1'b1),
.INIT(1'b1)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; char g[10][10]; int ax[10 * 10], n; bool use[10 * 10]; int q[2][100], ct[2], vst[8][8]; int dx[9] = {0, 0, 0, 1, -1, 1, 1, -1, -1}; int dy[9] = {0, 1, -1, 0, 0, -1, 1, -1, 1}; bool check(int x, int y) { if (x < 0 || y < 0 || x >= 8 || y >= 8) return 0; if (vst[x][y]) return 0; for (int i = 0; i < n; i++) if (ax[i] % 8 == y && (ax[i] / 8 == x || ax[i] / 8 == x - 1)) return 0; return 1; } int bfs() { q[0][0] = 7 * 8; ct[0] = 1; for (int i = 0; i < 10; i++) { int id = i & 1, nid = id ^ 1; ct[nid] = 0; memset(vst, 0, sizeof(vst)); for (int j = 0; j < ct[id]; j++) { int u = q[id][j]; int x = u / 8, y = u % 8; for (int d = 0; d < 9; d++) { int nx = x + dx[d], ny = y + dy[d]; if (check(nx, ny)) q[nid][ct[nid]++] = nx * 8 + ny, vst[nx][ny] = 1; if (nx == 0 && ny == 7) return 1; } } for (int j = 0; j < n; j++) ax[j] = (ax[j] / 8 + 1) * 8 + ax[j] % 8; } if (ct[0]) return 1; return 0; } int main() { n = 0; for (int i = 0; i < 8; i++) { scanf( %s , g[i]); for (int j = 0; j < 8; j++) if (g[i][j] == S ) ax[n++] = i * 8 + j; } if (bfs()) puts( WIN ); else puts( LOSE ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { set<char> s; char a[100005]; s.insert( A ); s.insert( H ); s.insert( I ); s.insert( M ); s.insert( O ); s.insert( T ); s.insert( U ); s.insert( V ); s.insert( W ); s.insert( X ); s.insert( Y ); scanf( %s , &a); int n = strlen(a); for (int i = 0; i < n; i++) { if (s.find(a[i]) == s.end() || a[i] != a[n - 1 - i]) { cout << NO ; return 0; } } cout << YES ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 5 * 105000; int n; int a[MAXN]; bool can(int x) { if (x == 0) return true; if (n - x < x) return false; int r = n; for (int i = x; i >= 1; i--) { if (r <= x) return false; while (a[r] < 2 * a[i]) { r--; if (r <= x) return false; } r--; } return true; } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); int l = 0, r = n; while (l < r) { int m = (l + r + 1) / 2; if (can(m)) l = m; else r = m - 1; } printf( %d , n - l); return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, a[5001], i, j, b[5001], ans; int main() { scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) { scanf( %d , &a[i]); b[i] = a[i]; } for (i = 1; i <= n; i++) if (a[i] == b[i]) for (j = 1; j <= n; j++) if (a[i] != b[j] && b[i] != a[j]) swap(b[i], b[j]); for (i = 1; i <= n; i++) if (a[i] != b[i]) ans++; printf( %d n , ans); for (i = 1; i <= n; i++) printf( %d %d n , a[i], b[i]); } |
#include <bits/stdc++.h> using namespace std; const int maxn = (int)3e5 + 10; const int inf = (int)1e9 + 5; const long long llinf = (long long)1e18 + 5; long long a[maxn]; long long d, i, n, k, l, query, first, second, pruf, pruf2, j, m, p, last, sum, h, z, r; int main() { cin >> n; for (i = 1; i < n + 1; i++) cin >> a[i]; string x; for (i = 0; i < n + 1; i++) { getline(cin, x); k = 0; if (i != 0) { for (int re = 0; re < x.size(); re++) { if ((x[re] == a ) or (x[re] == e ) or (x[re] == i ) or (x[re] == o ) or (x[re] == u ) or (x[re] == y )) k++; } if (k != a[i]) { cout << NO ; return 0; } } } cout << YES ; return 0; } |
#include <bits/stdc++.h> using namespace std; long long mod = 1e9; void err(istream_iterator<string> it) {} template <typename T, typename... Args> void err(istream_iterator<string> it, T a, Args... args) { cerr << *it << = << a << endl; err(++it, args...); } long long powm(long long a, long long b, long long mod) { long long res = 1; while (b) { if (b & 1) res = (res * a) % mod; a = (a * a) % mod; b >>= 1; } return res; } bool sortinrev(const pair<int, int> &a, const pair<int, int> &b) { return (a.first > b.first); } void solve() { long long n; cin >> n; vector<long long> a(n); for (long long i = 0; i < (n); i++) { cin >> a[i]; }; if (n == 1) { cout << YES n ; cout << 1 << << a[0] << endl; return; } long long x = 0, y = 0, m = 0; for (long long i = 0; i < (n - 1); i++) { m = max({m, a[i], a[i + 1]}); if (abs(a[i] - a[i + 1]) == 0) { cout << NO n ; return; } if (abs(a[i] - a[i + 1]) != 1 and y == 0) { y = abs(a[i] - a[i + 1]); } else if (abs(a[i] - a[i + 1]) != 1 and y != 0) { if (y != abs(a[i] - a[i + 1])) { cout << NO n ; return; } } } if (y == 0) { cout << YES n ; cout << (mod) << << (mod) << endl; return; } for (long long i = 0; i < (n - 1); i++) { if (abs(a[i] - a[i + 1]) == 1) { if (a[i] % y == 0 and a[i + 1] == a[i] + 1) { cout << NO n ; return; } if (a[i + 1] % y == 0 and a[i] == a[i + 1] + 1) { cout << NO n ; return; } } } cout << YES n ; cout << (m / y) + 1 << << y << endl; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); solve(); } |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Calculate_Rotor_Velocity.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Calculate_Rotor_Velocity
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity/Calculate_Rotor_Velocity
// Hierarchy Level: 3
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Calculate_Rotor_Velocity
(
CLK_IN,
reset,
enb_1_2000_0,
valid,
position,
rotor_velocity
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input valid;
input signed [17:0] position; // sfix18_En14
output signed [17:0] rotor_velocity; // sfix18_En8
reg signed [17:0] Delay1_out1; // sfix18_En14
wire signed [18:0] Add_sub_cast; // sfix19_En14
wire signed [18:0] Add_sub_cast_1; // sfix19_En14
wire signed [18:0] Add_out1; // sfix19_En14
wire signed [17:0] position_delta; // sfix18_En15
wire [17:0] time_delta_1; // ufix18_En3
wire signed [18:0] Product_cast; // sfix19_En3
wire signed [36:0] Product_mul_temp; // sfix37_En18
wire signed [35:0] velocity; // sfix36_En18
wire signed [17:0] Data_Type_Conversion2_out1; // sfix18_En8
wire signed [17:0] Constant1_out1; // sfix18_En8
wire signed [35:0] Product1_out1; // sfix36_En16
wire signed [17:0] Constant2_out1; // sfix18_En8
wire signed [17:0] Data_Type_Conversion1_out1; // sfix18_En8
reg signed [17:0] Delay4_out1; // sfix18_En8
wire signed [35:0] Product2_out1; // sfix36_En16
wire signed [36:0] Add1_add_cast; // sfix37_En16
wire signed [36:0] Add1_add_cast_1; // sfix37_En16
wire signed [36:0] Add1_out1; // sfix37_En16
// First two velocity calculations are not valid
//
// If detect positive rise in valid, this is a bad sample
// since encoder index just reset. In this case hold the last value
//
// Calculate Velocity
// <S6>/Delay1
always @(posedge CLK_IN)
begin : Delay1_process
if (reset == 1'b1) begin
Delay1_out1 <= 18'sb000000000000000000;
end
else if (enb_1_2000_0) begin
Delay1_out1 <= position;
end
end
// <S6>/Add
assign Add_sub_cast = position;
assign Add_sub_cast_1 = Delay1_out1;
assign Add_out1 = Add_sub_cast - Add_sub_cast_1;
// <S6>/Wrap_NegPi_To_Pi
controllerHdl_Wrap_NegPi_To_Pi u_Wrap_NegPi_To_Pi (.position(Add_out1), // sfix19_En14
.wrap(position_delta) // sfix18_En15
);
// <S6>/Time_Delta
assign time_delta_1 = 18'b110000110101000000;
// <S6>/Product
//
// <S6>/Switch
//
// <S6>/Delay
assign Product_cast = time_delta_1;
assign Product_mul_temp = position_delta * Product_cast;
assign velocity = Product_mul_temp[35:0];
// <S6>/Data Type Conversion2
assign Data_Type_Conversion2_out1 = velocity[27:10];
// <S6>/Constant1
assign Constant1_out1 = 18'sb000000000000000010;
// <S6>/Product1
assign Product1_out1 = Data_Type_Conversion2_out1 * Constant1_out1;
// <S6>/Constant2
assign Constant2_out1 = 18'sb000000000011111110;
// <S6>/Delay4
//
// <S6>/Delay3
//
// <S6>/Detect_Rise
always @(posedge CLK_IN)
begin : Delay4_process
if (reset == 1'b1) begin
Delay4_out1 <= 18'sb000000000000000000;
end
else if (enb_1_2000_0) begin
Delay4_out1 <= Data_Type_Conversion1_out1;
end
end
// <S6>/Product2
assign Product2_out1 = Constant2_out1 * Delay4_out1;
// <S6>/Add1
assign Add1_add_cast = Product1_out1;
assign Add1_add_cast_1 = Product2_out1;
assign Add1_out1 = Add1_add_cast + Add1_add_cast_1;
// <S6>/Data Type Conversion1
assign Data_Type_Conversion1_out1 = Add1_out1[25:8];
assign rotor_velocity = Data_Type_Conversion1_out1;
endmodule // controllerHdl_Calculate_Rotor_Velocity
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n, k; scanf( %d , &t); while (t-- && scanf( %d %d , &n, &k)) { if ((k & 1) == (n & 1) && (long long)(k)*k <= n && n >= k) printf( YES n ); else printf( NO n ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, q; pair<int, int> a[400004]; long long ans[200004], d[400004], sum; int fa[400004], l[400004], r[400004], s[400004]; vector<pair<int, int> > v, ask; int F(int x) { return fa[x] == x ? x : fa[x] = F(fa[x]); } long long got(int v) { return d[r[v]] - d[r[v] - s[v]]; } int main() { scanf( %d%d%d , &n, &m, &q); for (int i = 1; i <= n + m; i++) scanf( %d , &a[i].first), a[i].second = i; sort(a + 1, a + n + m + 1); for (int i = 1; i <= n + m; i++) { d[i] = d[i - 1] + a[i].first; fa[i] = i, s[i] = (a[i].second <= n), l[i] = r[i] = i; if (s[i] == 1) sum += a[i].first; if (i > 1) v.push_back({a[i].first - a[i - 1].first, i}); } for (int i = 1; i <= q; i++) { int k; scanf( %d , &k); ask.push_back({k, i}); } sort(v.begin(), v.end()); sort(ask.begin(), ask.end()); int it = 0; for (auto qr : ask) { while (it < v.size() && v[it].first <= qr.first) { int p = v[it].second; int U = F(p - 1), V = F(p); sum -= got(U) + got(V); fa[U] = V, s[V] += s[U], l[V] = l[U]; sum += got(V); it++; } ans[qr.second] = sum; } for (int i = 1; i <= q; i++) printf( %lld n , ans[i]); } |
//======================================================================
//
// sha256_w_mem_regs.v
// -------------------
// The W memory. This version uses 16 32-bit registers as a sliding
// window to generate the 64 words.
//
//======================================================================
module sha256_w_mem(
input wire clk,
input wire reset_n,
input wire [511 : 0] block,
input wire init,
input wire next,
output wire [31 : 0] w
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CTRL_IDLE = 0;
parameter CTRL_UPDATE = 1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] w_mem [0 : 15];
reg [31 : 0] w_mem00_new;
reg [31 : 0] w_mem01_new;
reg [31 : 0] w_mem02_new;
reg [31 : 0] w_mem03_new;
reg [31 : 0] w_mem04_new;
reg [31 : 0] w_mem05_new;
reg [31 : 0] w_mem06_new;
reg [31 : 0] w_mem07_new;
reg [31 : 0] w_mem08_new;
reg [31 : 0] w_mem09_new;
reg [31 : 0] w_mem10_new;
reg [31 : 0] w_mem11_new;
reg [31 : 0] w_mem12_new;
reg [31 : 0] w_mem13_new;
reg [31 : 0] w_mem14_new;
reg [31 : 0] w_mem15_new;
reg w_mem_we;
reg [5 : 0] w_ctr_reg;
reg [5 : 0] w_ctr_new;
reg w_ctr_we;
reg w_ctr_inc;
reg w_ctr_rst;
reg [1 : 0] sha256_w_mem_ctrl_reg;
reg [1 : 0] sha256_w_mem_ctrl_new;
reg sha256_w_mem_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] w_tmp;
reg [31 : 0] w_new;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign w = w_tmp;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
w_mem[00] <= 32'h0;
w_mem[01] <= 32'h0;
w_mem[02] <= 32'h0;
w_mem[03] <= 32'h0;
w_mem[04] <= 32'h0;
w_mem[05] <= 32'h0;
w_mem[06] <= 32'h0;
w_mem[07] <= 32'h0;
w_mem[08] <= 32'h0;
w_mem[09] <= 32'h0;
w_mem[10] <= 32'h0;
w_mem[11] <= 32'h0;
w_mem[12] <= 32'h0;
w_mem[13] <= 32'h0;
w_mem[14] <= 32'h0;
w_mem[15] <= 32'h0;
w_ctr_reg <= 6'h00;
sha256_w_mem_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (w_mem_we)
begin
w_mem[00] <= w_mem00_new;
w_mem[01] <= w_mem01_new;
w_mem[02] <= w_mem02_new;
w_mem[03] <= w_mem03_new;
w_mem[04] <= w_mem04_new;
w_mem[05] <= w_mem05_new;
w_mem[06] <= w_mem06_new;
w_mem[07] <= w_mem07_new;
w_mem[08] <= w_mem08_new;
w_mem[09] <= w_mem09_new;
w_mem[10] <= w_mem10_new;
w_mem[11] <= w_mem11_new;
w_mem[12] <= w_mem12_new;
w_mem[13] <= w_mem13_new;
w_mem[14] <= w_mem14_new;
w_mem[15] <= w_mem15_new;
end
if (w_ctr_we)
w_ctr_reg <= w_ctr_new;
if (sha256_w_mem_ctrl_we)
sha256_w_mem_ctrl_reg <= sha256_w_mem_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// select_w
//
// Mux for the external read operation. This is where we exract
// the W variable.
//----------------------------------------------------------------
always @*
begin : select_w
if (w_ctr_reg < 16)
begin
w_tmp = w_mem[w_ctr_reg[3 : 0]];
end
else
begin
w_tmp = w_new;
end
end // select_w
//----------------------------------------------------------------
// w_new_logic
//
// Logic that calculates the next value to be inserted into
// the sliding window of the memory.
//----------------------------------------------------------------
always @*
begin : w_mem_update_logic
reg [31 : 0] w_0;
reg [31 : 0] w_1;
reg [31 : 0] w_9;
reg [31 : 0] w_14;
reg [31 : 0] d0;
reg [31 : 0] d1;
w_mem00_new = 32'h0;
w_mem01_new = 32'h0;
w_mem02_new = 32'h0;
w_mem03_new = 32'h0;
w_mem04_new = 32'h0;
w_mem05_new = 32'h0;
w_mem06_new = 32'h0;
w_mem07_new = 32'h0;
w_mem08_new = 32'h0;
w_mem09_new = 32'h0;
w_mem10_new = 32'h0;
w_mem11_new = 32'h0;
w_mem12_new = 32'h0;
w_mem13_new = 32'h0;
w_mem14_new = 32'h0;
w_mem15_new = 32'h0;
w_mem_we = 0;
w_0 = w_mem[0];
w_1 = w_mem[1];
w_9 = w_mem[9];
w_14 = w_mem[14];
d0 = {w_1[6 : 0], w_1[31 : 7]} ^
{w_1[17 : 0], w_1[31 : 18]} ^
{3'b000, w_1[31 : 3]};
d1 = {w_14[16 : 0], w_14[31 : 17]} ^
{w_14[18 : 0], w_14[31 : 19]} ^
{10'b0000000000, w_14[31 : 10]};
w_new = d1 + w_9 + d0 + w_0;
if (init)
begin
w_mem00_new = block[511 : 480];
w_mem01_new = block[479 : 448];
w_mem02_new = block[447 : 416];
w_mem03_new = block[415 : 384];
w_mem04_new = block[383 : 352];
w_mem05_new = block[351 : 320];
w_mem06_new = block[319 : 288];
w_mem07_new = block[287 : 256];
w_mem08_new = block[255 : 224];
w_mem09_new = block[223 : 192];
w_mem10_new = block[191 : 160];
w_mem11_new = block[159 : 128];
w_mem12_new = block[127 : 96];
w_mem13_new = block[95 : 64];
w_mem14_new = block[63 : 32];
w_mem15_new = block[31 : 0];
w_mem_we = 1;
end
else if (w_ctr_reg > 15)
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
w_mem02_new = w_mem[03];
w_mem03_new = w_mem[04];
w_mem04_new = w_mem[05];
w_mem05_new = w_mem[06];
w_mem06_new = w_mem[07];
w_mem07_new = w_mem[08];
w_mem08_new = w_mem[09];
w_mem09_new = w_mem[10];
w_mem10_new = w_mem[11];
w_mem11_new = w_mem[12];
w_mem12_new = w_mem[13];
w_mem13_new = w_mem[14];
w_mem14_new = w_mem[15];
w_mem15_new = w_new;
w_mem_we = 1;
end
end // w_mem_update_logic
//----------------------------------------------------------------
// w_ctr
// W schedule adress counter. Counts from 0x10 to 0x3f and
// is used to expand the block into words.
//----------------------------------------------------------------
always @*
begin : w_ctr
w_ctr_new = 0;
w_ctr_we = 0;
if (w_ctr_rst)
begin
w_ctr_new = 6'h00;
w_ctr_we = 1;
end
if (w_ctr_inc)
begin
w_ctr_new = w_ctr_reg + 6'h01;
w_ctr_we = 1;
end
end // w_ctr
//----------------------------------------------------------------
// sha256_w_mem_fsm
// Logic for the w shedule FSM.
//----------------------------------------------------------------
always @*
begin : sha256_w_mem_fsm
w_ctr_rst = 0;
w_ctr_inc = 0;
sha256_w_mem_ctrl_new = CTRL_IDLE;
sha256_w_mem_ctrl_we = 0;
case (sha256_w_mem_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
w_ctr_rst = 1;
sha256_w_mem_ctrl_new = CTRL_UPDATE;
sha256_w_mem_ctrl_we = 1;
end
end
CTRL_UPDATE:
begin
if (next)
begin
w_ctr_inc = 1;
end
if (w_ctr_reg == 6'h3f)
begin
sha256_w_mem_ctrl_new = CTRL_IDLE;
sha256_w_mem_ctrl_we = 1;
end
end
endcase // case (sha256_ctrl_reg)
end // sha256_ctrl_fsm
endmodule // sha256_w_mem
//======================================================================
// sha256_mem.v
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_PP_BLACKBOX_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdrivernovlp (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:40:46 05/12/2015
// Design Name:
// Module Name: ID_EX
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ID_EX(
clk,rst,stall,
id_a, id_b, id_td, id_d2, id_Aluc, id_WREG, id_WMEM, id_LW,id_instr,id_pc,
ex_a, ex_b, ex_td, ex_d2, ex_Aluc, ex_WREG, ex_WMEM, ex_LW,ex_instr,ex_pc
);
input clk,rst,stall;
input wire [31:0] id_a,id_b,id_d2,id_instr,id_pc;
input wire [4:0] id_td,id_Aluc;
input wire id_WREG,id_WMEM,id_LW;
output reg [31:0] ex_a,ex_b,ex_d2,ex_instr,ex_pc;
output reg [4:0] ex_td,ex_Aluc;
output reg ex_WREG,ex_WMEM,ex_LW;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
ex_a <= 0;
ex_b <= 0;
ex_d2 <= 0;
ex_td <= 0;
ex_Aluc <= 0;
ex_WREG <= 0;
ex_WMEM <= 0;
ex_LW <= 0;
ex_instr<=32'b100000;
ex_pc<=32'b0;
end
else if(stall)
begin
ex_a <= 0;
ex_b <= 0;
ex_d2 <= 0;
ex_td <= 0;
ex_Aluc <= 0;
ex_WREG <= 0;
ex_WMEM <= 0;
ex_LW <= 0;
ex_instr<=32'b100000;
ex_pc <= id_pc;
end
else
begin
ex_a <= id_a;
ex_b <= id_b;
ex_d2 <= id_d2;
ex_td <= id_td;
ex_Aluc <= id_Aluc;
ex_WREG <= id_WREG;
ex_WMEM <= id_WMEM;
ex_LW <= id_LW;
ex_instr<=id_instr;
ex_pc <= id_pc;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__AND2B_BEHAVIORAL_PP_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and2b (
VPWR,
VGND,
X ,
A_N ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B ;
// Local signals
wire X not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2B_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_PP_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD3_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int main() { int t, x, y, z; cin >> t; while (t--) { cin >> x >> y >> z; if ((x != y && y != z && x != z) || ((x == y && x < z) || (y == z && y < x) || (z == x && z < y))) { cout << NO n ; continue; } else { cout << YES n ; if (x == y && y == z) { cout << x << << x << << x << n ; } else { if (x == y) { cout << x << << z << << z << n ; } else if (y == z) { cout << y << << x << << x << n ; } else { cout << z << << y << << y << n ; } } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 300010; const long long inf = 4e18; int n, k, x1[N], var[N], x2[N], y2[N], x[N], y[N]; pair<pair<int, int>, int> px[N], py[N], py1[N]; long long ans; long long solve(pair<pair<int, int>, int> *p, int n, int k, int w) { int j = n - k; long long res = inf; for (int i = 1; i <= k + 1; i++) { int yl = p[i].first.first; int yr = p[j].first.first; int h = yr - yl; if (h & 1) { h >>= 1; h++; } else { h >>= 1; } if (h == 0) h++; res = min(res, 1ll * w * h); j++; } return res; } void remove(pair<pair<int, int>, int> *p, int n, int val) { int j = -1; for (int i = 1; i <= n; i++) if (p[i].second == val) { j = i; break; } for (int i = j; i < n; i++) p[i] = p[i + 1]; } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d%d%d%d , &x1[i], &var[i], &x2[i], &y2[i]); for (int i = 1; i <= n; i++) { x[i] = x1[i] + x2[i]; y[i] = var[i] + y2[i]; } for (int i = 1; i <= n; i++) py[i] = make_pair(make_pair(y[i], x[i]), i); sort(py + 1, py + n + 1); for (int i = 1; i <= n; i++) px[i] = make_pair(make_pair(x[i], y[i]), i); sort(px + 1, px + n + 1); int n1 = n; ans = inf; for (int i = 1; i <= k + 1; i++) { int n2 = n1; for (int j = 1; j <= n2; j++) py1[j] = py[j]; for (int j = n; j >= n - (k - (i - 1)); j--) { int xl = px[i].first.first; int xr = px[j].first.first; int w = xr - xl; if (w & 1) { w >>= 1; w++; } else { w >>= 1; } if (w == 0) w++; ans = min(ans, solve(py1, n2, k - (i - 1) - (n - j), w)); remove(py1, n2, px[j].second); n2--; } remove(py, n1, px[i].second); n1--; } cout << ans; return 0; } |
`include "top.vh"
module top(
input ice_clk_i,
output [7:0] led_o,
output vs_o,
output hs_o,
output [3 : 0] red_o,
output [3 : 0] blue_o,
output [3 : 0] green_o
);
reg [31:0] ctr;
reg vs = 0, hs = 0;
reg [9 : 0] ctr_x = 0;
reg [8 : 0] ctr_y = 0;
wire clk_vga;
wire locked;
clks#(
.PLL_EN(1),
.GBUFF_EN(1),
.DIVR(4'b0000),
.DIVF(7'b1000010),
.DIVQ(3'b100)
) clks(
.clk_i(ice_clk_i),
.clk_o(clk_vga)
);
always @(posedge clk_vga)
begin
ctr <= ctr +1;
end
genvar i;
generate
for (i = 0; i<8; i = i + 1) begin
assign led_o[i] = ctr[i + 18];
end
endgenerate
// 640 x 480
wire pix_clk;
// pixel clock: 25Mhz = 40ns (clk/2)
reg pcount = 0; // used to generate pixel clock
wire en = (pcount == 0);
always @ (posedge clk_vga) pcount <= ~pcount;
assign pix_clk = en;
reg hsync = 0,vsync = 0,hblank = 0,vblank = 0;
reg [9:0] hcount = 0; // pixel number on current line
reg [9:0] vcount = 0; // line number
// horizontal: 794 pixels = 31.76us
// display 640 pixels per line
wire hsyncon,hsyncoff,hreset,hblankon;
assign hblankon = en & (hcount == 639);
assign hsyncon = en & (hcount == 652-4);
assign hsyncoff = en & (hcount == 746-4);
assign hreset = en & (hcount == 793-4);
wire blank = (vblank | (hblank & ~hreset)); // blanking => black
// vertical: 528 lines = 16.77us
// display 480 lines
wire vsyncon,vsyncoff,vreset,vblankon;
assign vblankon = hreset & (vcount == 479);
assign vsyncon = hreset & (vcount == 492-4);
assign vsyncoff = hreset & (vcount == 494-4);
assign vreset = hreset & (vcount == 527-4);
// sync and blanking
always @(posedge clk_vga) begin
hcount <= en ? (hreset ? 0 : hcount + 1) : hcount;
hblank <= hreset ? 0 : hblankon ? 1 : hblank;
hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync; // hsync is active low
vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;
vblank <= vreset ? 0 : vblankon ? 1 : vblank;
vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync; // vsync is active low
end
assign hs_o = hsync;
assign vs_o = vsync;
// assign red_o = hsync ? hcount[8 : 5] & vcount[4:1] : 0;
//assign blue_o = hsync ? hcount[8 : 5] & vcount[4:1]: 0;
//assign green_o = hsync ? 1 : 0;//hsync ? hcount[8: 5] & vcount[4:1] : 0;
reg [9 : 0] h_bx_ctr = 0;
reg [9 : 0] v_bx_ctr = 0;
wire draw;
wire h_bx, v_vx;
always @ (posedge pix_clk)
begin
if (draw)
begin
h_bx_ctr <= h_bx_ctr + 1;
end
else
begin
h_bx_ctr <= 0;
end
end // always @ (posedge clk)
always @ (posedge pix_clk)
begin
if (vblankon)
begin
v_bx_ctr <= v_bx_ctr + 1;
end
else if(v_bx_ctr == 479)
begin
v_bx_ctr <= 0;
end
end // always @ (posedge clk)
assign draw = (hsync & ~hblank) & (vsync & ~vblank);
assign h_bx = (h_bx_ctr > 310) & (h_bx_ctr < 330);
assign v_bx = 1;//(v_bx_ctr > 220) & (v_bx_ctr > 240);
assign red_o = draw & h_bx & v_bx ? 4'b1111 : 0;
assign blue_o = draw & h_bx & v_bx ? 4'b1111 : 0;
assign green_o = draw & h_bx & v_bx ? 4'b1111 : 0;
endmodule // top
|
#include <bits/stdc++.h> using namespace std; int main() { int t; cin >> t; while (t--) { int n, m, k; cin >> n >> m >> k; vector<int> lx(n), ly(m); vector<int> x(k), y(k); for (int& i : lx) cin >> i; for (int& i : ly) cin >> i; for (int i = 0; i < k; i++) { cin >> x[i] >> y[i]; } sort(lx.begin(), lx.end()), sort(ly.begin(), ly.end()); vector<int> ind(k); iota(ind.begin(), ind.end(), 0); auto solve = [&](vector<int>& lx, vector<int>& y, vector<int>& x) { long long ans = 0; for (int i = 0, j = 0; i + 1 < lx.size(); i++) { int c = 0; map<int, int> com; int l = lx[i], r = lx[i + 1]; while (j < k && x[ind[j]] <= l) j++; while (j < k && x[ind[j]] < r) { ans += c++; ans -= com[y[ind[j]]]++; j++; } } return ans; }; sort(ind.begin(), ind.end(), [&](int i, int j) { return x[i] < x[j]; }); long long ans = solve(lx, y, x); sort(ind.begin(), ind.end(), [&](int i, int j) { return y[i] < y[j]; }); ans += solve(ly, x, y); cout << ans << n ; } } |
///////////////////////////////////////////////////////////////////////////////
//
// Module: dma_engine_rr_arb.v
// Project: CPCI (PCI Control FPGA)
// Description: Arbiter for choosing from input queues
//
// Note: read and write are from the perspective of the driver.
// Read means retrieve a packet from the CNET and place in memory.
// Write means send a packet from memory to CNET.
//
// Change history: 12/10/07 - Split from dma_engine
//
// Issues to address:
//
///////////////////////////////////////////////////////////////////////////////
module dma_engine_rr_arb (
// CPCI register interface signals
input [3:0] dma_wr_mac, // Which MAC to write data to
// CNET DMA interface signals
input [15:0] dma_pkt_avail, // Packets available in which buffers in CNET
input dma_rd_request, // Request packet from buffer
// DMA engine signals
output reg [3:0] dma_rd_request_q,
output [15:0] dma_wr_mac_one_hot,
output reg dma_rd_request_q_vld,
input ctrl_done,
input dma_in_progress,
input xfer_is_rd,
// Miscelaneous signals
input cnet_reprog, // Indicates that the CNET is
// currently being reprogrammed
input reset,
input clk
);
// ==================================================================
// Local
// ==================================================================
// Round robin lookup for reads
reg [3:0] pref_to_read;
reg [3:0] mac_search;
wire [15:0] mac_search_one_hot;
// ==================================================================
// Round robin allocator
// ==================================================================
always @(posedge clk)
begin
// On either reset or the CNET being reprogrammed, reset to MAC0
if (reset || cnet_reprog)
pref_to_read <= 4'h0;
// Rotate to the next MAC when this one is done
else if (ctrl_done && xfer_is_rd)
pref_to_read <= pref_to_read + 'h1;
// Work out which MAC is being read
else if (dma_rd_request)
pref_to_read <= dma_rd_request_q;
end
always @(posedge clk)
begin
// On either reset or the CNET being reprogrammed, reset to MAC0
if (reset || cnet_reprog) begin
dma_rd_request_q <= 4'hf;
mac_search <= 4'hf;
dma_rd_request_q_vld <= 1'b0;
end
else if (dma_rd_request && xfer_is_rd) begin
dma_rd_request_q_vld <= 1'b0;
end
else if (ctrl_done && xfer_is_rd) begin
dma_rd_request_q <= pref_to_read;
mac_search <= pref_to_read;
dma_rd_request_q_vld <= 1'b0;
end
// Work out which mac to request a packet from
else begin
// Keep searching until the mac we're requesting from is the one we'd
// prefer to read next
if (dma_rd_request_q != pref_to_read) begin
// Search between the current best match and pref_to_read
// Don't need to consider matches that aren't as good.
if (mac_search == pref_to_read)
mac_search <= dma_rd_request_q;
else
mac_search <= mac_search - 'h1;
// If we find a match, then update the dma_rd_request_q signal to
// reflect this
if (mac_search_one_hot & dma_pkt_avail) begin
dma_rd_request_q <= mac_search;
dma_rd_request_q_vld <= 1'b1;
end
end
end
end
// Work out which MAC to request the next packet from
assign dma_wr_mac_one_hot = {dma_wr_mac == 4'h f,
dma_wr_mac == 4'h e,
dma_wr_mac == 4'h d,
dma_wr_mac == 4'h c,
dma_wr_mac == 4'h b,
dma_wr_mac == 4'h a,
dma_wr_mac == 4'h 9,
dma_wr_mac == 4'h 8,
dma_wr_mac == 4'h 7,
dma_wr_mac == 4'h 6,
dma_wr_mac == 4'h 5,
dma_wr_mac == 4'h 4,
dma_wr_mac == 4'h 3,
dma_wr_mac == 4'h 2,
dma_wr_mac == 4'h 1,
dma_wr_mac == 4'h 0};
assign mac_search_one_hot = {mac_search == 4'h f,
mac_search == 4'h e,
mac_search == 4'h d,
mac_search == 4'h c,
mac_search == 4'h b,
mac_search == 4'h a,
mac_search == 4'h 9,
mac_search == 4'h 8,
mac_search == 4'h 7,
mac_search == 4'h 6,
mac_search == 4'h 5,
mac_search == 4'h 4,
mac_search == 4'h 3,
mac_search == 4'h 2,
mac_search == 4'h 1,
mac_search == 4'h 0};
endmodule // dma_engine_rr_arb
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211O_1_V
`define SKY130_FD_SC_LS__A211O_1_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211o_1 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a211o_1 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211O_1_V
|
#include <bits/stdc++.h> using namespace std; inline long long read() { long long x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = (x << 1) + (x << 3) + (ch ^ 48); ch = getchar(); } return x * f; } long long n; long long fa[1010000], lg[1010000]; long long cnt[1010000], maxx = 0; long long a[1010000]; long long find(long long x) { if (x == fa[x]) return x; return fa[x] = find(fa[x]); } signed main() { n = read(); long long ans = 0; for (long long i = 1; i <= n; i++) a[i] = read(), maxx = max(maxx, a[i]), ans -= a[i], cnt[a[i]]++; for (long long i = 1; i <= maxx; i++) fa[i] = i, lg[i] = lg[i >> 1] + 1; cnt[0]++; long long m = 1 << (lg[maxx] + 1); for (register long long i = m - 1; ~i; i--) { for (long long j = i; j * 2 > i; j = (j - 1) & i) { long long x = j, y = i ^ j; if (!cnt[x] || !cnt[y]) continue; x = find(x), y = find(y); if (x != y) { ans += i * (cnt[x] + cnt[y] - 1); fa[x] = y; cnt[y] = 1; } } } cout << ans << endl; return 0; } |
// file: out_skew_dcm.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___120.005______0.000______50.0______200.000_____60.000
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________120.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "out_skew_dcm,clk_wiz_v3_2,{component_name=out_skew_dcm,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO_OFFCHIP,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=8.333,clkin2_period=8.333,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}" *)
module out_skew_dcm
(// Clock in ports
input CLK_IN1,
input CLKFB_IN,
// Clock out ports
output CLK_OUT1,
output CLKFB_OUT,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
assign clkin1 = CLK_IN1;
wire clkfb_ibuf2bufio2fb;
wire clkfb_in_buf_out;
// feedback clock input buffer
IBUFG clkfb_ibufg
(.O (clkfb_ibuf2bufio2fb),
.I (CLKFB_IN));
// bufio2fb instantiation
BUFIO2FB #(.DIVIDE_BYPASS("TRUE")) clkfb_bufio2fb
(.O(clkfb_in_buf_out),
.I(clkfb_ibuf2bufio2fb));
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire psdone_unused;
wire locked_int;
wire [7:0] status_int;
wire clkfb;
wire clk0;
DCM_SP
#(.CLKDV_DIVIDE (2.000),
.CLKFX_DIVIDE (1),
.CLKFX_MULTIPLY (4),
.CLKIN_DIVIDE_BY_2 ("FALSE"),
.CLKIN_PERIOD (8.333),
.CLKOUT_PHASE_SHIFT ("NONE"),
.CLK_FEEDBACK ("1X"),
.DESKEW_ADJUST ("SYSTEM_SYNCHRONOUS"),
.PHASE_SHIFT (0),
.STARTUP_WAIT ("FALSE"))
dcm_sp_inst
// Input clock
(.CLKIN (clkin1),
.CLKFB (clkfb_in_buf_out),
// Output clocks
.CLK0 (clk0),
.CLK90 (),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLKFX (),
.CLKFX180 (),
.CLKDV (),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (locked_int),
.STATUS (status_int),
.RST (RESET),
// Unused pin- tie low
.DSSEN (1'b0));
assign LOCKED = locked_int;
// Output buffering
//-----------------------------------
wire clkfb_bufg_out;
wire clkfb_bufg_out_n;
wire clkfb_oddr_out;
// Instantiate bufg on fbout
BUFG clkfbout_bufg
(.O (clkfb_bufg_out),
.I (clk0));
// Locally invert clkfb_bufg_out for use in ODDR2
assign clkfb_bufg_out_n = ~clkfb_bufg_out;
// Forward the feedback clock off-chip
ODDR2 clkfbout_oddr
(.Q (clkfb_oddr_out),
.C0 (clkfb_bufg_out),
.C1 (clkfb_bufg_out_n),
.CE (1'b1),
.D0 (1'b1),
.D1 (1'b0),
.R (1'b0),
.S (1'b0));
assign CLKFB_OUT = clkfb_oddr_out;
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clk0));
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MX = 1e5 + 10; int n, a[MX], out[MX], mn[MX]; int bs(int L, int R, int val) { if (R - L == 1) return L; int mid = (R + L) / 2; if (val <= mn[mid]) return bs(L, mid, val); else return bs(mid, R, val); } int main() { cin >> n; for (int i = 0; i < n; ++i) cin >> a[i]; mn[n - 1] = a[n - 1]; for (int i = n - 2; i >= 0; --i) mn[i] = min(mn[i + 1], a[i]); for (int i = n - 1; i >= 0; --i) { if (mn[i] == a[i]) out[i] = -1; else { int x = bs(i + 1, n, a[i]); out[i] = x - i - 1; } } for (int i = 0; i < n; ++i) cout << out[i] << ; } |
#include <bits/stdc++.h> using namespace std; int main() { int t; double a, b, Zero = 0.5, One = 1.0; scanf( %d , &t); while (t--) { scanf( %lf%lf , &a, &b); if (a == 0 && b == 0) printf( %.10lf n , One); else if (a == 0) printf( %.10lf n , Zero); else if (b == 0) printf( %.10lf n , One); else if (a >= 4 * b) { float area = 0.5 * 4 * b * b; area = 2 * a * b - area; area /= 2 * a * b; printf( %.10lf n , area); } else { float area = 0.5 * a * a * 0.25 + a * b; area /= 2 * a * b; printf( %.10lf n , area); } } return 0; } |
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