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#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); const long long int N = 1e5 + 5; long long int a[N], b[N], n, d, x; long long int getNextX() { x = (x * 37 + 10007) % 1000000007; return x; } void initAB() { for (long long int i = 0; i < n; i++) { a[i] = i + 1; } for (long long int i = 0; i < n; i++) { swap(a[i], a[getNextX() % (i + 1)]); } for (long long int i = 0; i < n; i++) { if (i < d) b[i] = 1; else b[i] = 0; } for (long long int i = 0; i < n; i++) { swap(b[i], b[getNextX() % (i + 1)]); } } long long int pos[N]; vector<long long int> bb; long long int c[N]; void solve() { cin >> n >> d >> x; initAB(); for (long long int i = 0; i <= n - 1; i++) { if (b[i]) bb.push_back(i); } for (long long int i = 0; i <= n - 1; i++) { pos[a[i]] = i; } if (bb.size() <= 500) { for (long long int i = 0; i <= n - 1; i++) { for (long long int j : bb) { if (j > i) break; c[i] = max(c[i], a[i - j]); } } } else { for (long long int i = 0; i <= n - 1; i++) for (long long int j = n; j >= 1; j--) { long long int p = pos[j]; if (p <= i && b[i - p]) { c[i] = j; break; } } } for (long long int i = 0; i <= n - 1; i++) cout << c[i] << ; } signed main() { ios ::sync_with_stdio(0), cin.tie(0), cout.tie(0); clock_t clk = clock(); long long int t; t = 1; while (t--) { solve(); } cerr << (double)(clock() - clk) / CLOCKS_PER_SEC; return 0; } |
#include <bits/stdc++.h> using namespace std; const long double eps = 1e-9; const long double pi = acos(-1.0); const int inf = 1e+9; long long gcd(long long a, long long b) { return (b == 0) ? a : gcd(b, a % b); } int xabs(int a) { return a >= 0 ? a : -a; } int sign(int a) { return (a < 0) ? -1 : 1; } int sqr(int a) { return a * a; } int main() { string s; cin >> s; int n = s.size(); stack<pair<char, int> > q; set<pair<char, char> > sp; sp.insert(make_pair( [ , ] )); sp.insert(make_pair( ( , ) )); for (int i = 0; i < n; i++) { if (q.size() == 0) { q.push(make_pair(s[i], i)); } else { if (sp.count(make_pair(q.top().first, s[i]))) { q.pop(); } else { q.push(make_pair(s[i], i)); } } } vector<int> ans; while (q.size() != 0) { ans.push_back(q.top().second); q.pop(); } reverse(ans.begin(), ans.end()); ans.push_back(n); int cnt = 0; int j = 0; int ma = 0; string res; while (j < ans.size()) { int cnt = 0; int start = (j > 0) ? ans[j - 1] + 1 : 0; for (int i = start; i < ans[j]; i++) { if (s[i] == [ ) cnt++; } if (cnt > ma) { ma = cnt; res = s.substr(start, ans[j] - start); } j++; } cout << ma << endl; cout << res << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, t[200005], ans = 0; bool chk[200005]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , t + i); chk[0] = true; for (int i = n; i >= 1; i--) if (!chk[i]) { int x = i; ans++; while (!chk[x]) chk[x] = true, x = t[x]; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int m, e[10][10] = {}, a, b; scanf( %d , &m); while (m--) { scanf( %d%d , &a, &b); e[a][b] = e[b][a] = 1; } for (int i = 1; i <= 5; i++) for (int j = i + 1; j <= 5; j++) for (int k = j + 1; k <= 5; k++) if (e[i][j] == e[j][k] && e[j][k] == e[k][i]) { puts( WIN ); return 0; } puts( FAIL ); return 0; } |
module etx_io (/*AUTOARG*/
// Outputs
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, tx_wr_wait, tx_rd_wait,
// Inputs
tx_lclk_io, tx_lclk_div4, tx_lclk90, txi_wr_wait_p, txi_wr_wait_n,
txi_rd_wait_p, txi_rd_wait_n, tx_data_slow, tx_frame_slow
);
parameter PLATFORM = `CFG_PLATFORM;
parameter IOSTD_ELINK = "LVDS_25";
parameter PW = 104;
parameter ETYPE = 0; // 0 = parallella
// 1 = ephycard
//###########
//# reset, clocks
//##########
input tx_lclk_io; //fast ODDR
input tx_lclk_div4; //slow clock
input tx_lclk90; //fast 90deg shifted lclk
//###########
//# eLink pins
//###########
output txo_lclk_p, txo_lclk_n; // tx clock output
output txo_frame_p, txo_frame_n; // tx frame signal
output [7:0] txo_data_p, txo_data_n; // tx data (dual data rate)
input txi_wr_wait_p,txi_wr_wait_n; // tx write pushback
input txi_rd_wait_p, txi_rd_wait_n; // tx read pushback
//#############
//# Fabric interface
//#############
input [63:0] tx_data_slow; //data for burst or transaction
input [3:0] tx_frame_slow; //framing signal
output tx_wr_wait;
output tx_rd_wait;
//############
//# REGS
//############
reg [63:0] tx_data;
reg [3:0] tx_frame;
wire [15:0] tx_data16;
wire tx_frame16;
reg tx_wr_wait_sync;
reg tx_rd_wait_sync;
reg tx_wr_wait_reg;
reg tx_rd_wait_reg;
reg tx_wr_wait_reg2;
reg tx_rd_wait_reg2;
//############
//# WIRES
//############
wire [15:0] tx_data_mux;
wire txo_frame_ddr;
wire txo_lclk90;
wire tx_wr_wait_async;
wire tx_rd_wait_async;
wire [7:0] txo_data_ddr;
wire invert_pins;
//#########################################
//# Pins inverted for 64-core board
//#########################################
`ifdef TARGET_E64
assign invert_pins=1'b1;
`else
assign invert_pins=1'b0;
`endif
//#########################################
//# Synchronizatsion to fast domain
//#########################################
//Find the aligned edge
oh_edgealign edgealign0 (.firstedge (firstedge),
.fastclk (tx_lclk_io),
.slowclk (tx_lclk_div4)
);
//Data shift registers
always @ (posedge tx_lclk_io)
if(firstedge) //"load"
begin
tx_data[63:0] <= tx_data_slow[63:0]; //changes every 4 cycles
tx_frame[3:0] <= tx_frame_slow[3:0];
end
else //"shift"
begin
tx_data[63:0] <= {16'b0,tx_data[63:16]};
tx_frame[3:0] <= {tx_frame[2:0],1'b0};
end
assign tx_data16[15:0] = tx_data[15:0];
assign tx_frame16 = tx_frame[3];
//##############################################
//# Wait signal synchronization
//##############################################
always @ (negedge tx_lclk_io)
begin
tx_wr_wait_sync <= tx_wr_wait_async ^ invert_pins;
tx_rd_wait_sync <= tx_rd_wait_async ^ invert_pins;
end
//Looks like legacy elink puts out short wait pulses.
//Let's make sure they don't sneak through
always @ (posedge tx_lclk_div4)
begin
tx_wr_wait_reg <= tx_wr_wait_sync;
tx_wr_wait_reg2 <= tx_wr_wait_reg;
tx_rd_wait_reg <= tx_rd_wait_sync;
tx_rd_wait_reg2 <= tx_rd_wait_reg;
end
assign tx_wr_wait = tx_wr_wait_reg | tx_wr_wait_reg2;
assign tx_rd_wait = tx_rd_wait_reg | tx_rd_wait_reg2;
//############################################
//# IO DRIVER STUFF
//############################################
generate
genvar i;
if(PLATFORM=="ULTRASCALE")
begin : ultrascale
//DATA
for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDRE1 oddr_data (.Q (txo_data_ddr[i]),
.C (tx_lclk_io),
.D1 (tx_data16[i+8] ^ invert_pins),
.D2 (tx_data16[i] ^ invert_pins));
end
//FRAME
ODDRE1 oddr_frame (.Q (txo_frame_ddr),
.C (tx_lclk_io),
.D1 (tx_frame16 ^ invert_pins),
.D2 (tx_frame16 ^ invert_pins));
//LCLK
ODDRE1 oddr_lclk (.Q (txo_lclk90),
.C (tx_lclk90),
.D1 (1'b1 ^ invert_pins),
.D2 (1'b0 ^ invert_pins));
end // block: ultrascale
else
begin : zynq
for(i=0; i<8; i=i+1)
begin : gen_oddr
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_data (
.Q (txo_data_ddr[i]),
.C (tx_lclk_io),
.CE (1'b1),
.D1 (tx_data16[i+8] ^ invert_pins),
.D2 (tx_data16[i] ^ invert_pins),
.R (1'b0),
.S (1'b0)
);
end
//FRAME
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_frame (
.Q (txo_frame_ddr),
.C (tx_lclk_io),
.CE (1'b1),
.D1 (tx_frame16 ^ invert_pins),
.D2 (tx_frame16 ^ invert_pins),
.R (1'b0), //reset
.S (1'b0)
);
//LCLK
ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
oddr_lclk (
.Q (txo_lclk90),
.C (tx_lclk90),
.CE (1'b1),
.D1 (1'b1 ^ invert_pins),
.D2 (1'b0 ^ invert_pins),
.R (1'b0),//should be no reason to reset clock, static input
.S (1'b0)
);
end
endgenerate
//Buffer drivers
OBUFDS obufds_data[7:0] (.O (txo_data_p[7:0]),
.OB (txo_data_n[7:0]),
.I (txo_data_ddr[7:0]));
OBUFDS obufds_frame (.O (txo_frame_p),
.OB (txo_frame_n),
.I (txo_frame_ddr));
OBUFDS obufds_lclk (.O (txo_lclk_p),
.OB (txo_lclk_n),
.I (txo_lclk90));
//Wait inputs
generate
if(ETYPE==1)
begin
assign tx_wr_wait_async = txi_wr_wait_p;
end
else if (ETYPE==0)
begin
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_wrwait
(.I (txi_wr_wait_p),
.IB (txi_wr_wait_n),
.O (tx_wr_wait_async));
end
endgenerate
//TODO: Come up with cleaner defines for this
`define ZYNQMP
`ifdef ZYNQMP
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rdwait
(.I (txi_rd_wait_p),
.IB (txi_rd_wait_n),
.O (tx_rd_wait_async));
`else
//On Parallella this signal comes in single-ended
assign tx_rd_wait_async = txi_rd_wait_p;
`endif
endmodule // etx_io
// Local Variables:
// verilog-library-directories:("." "../../emesh/hdl" "../../common/hdl")
// End:
|
#include <bits/stdc++.h> using namespace std; int n, m, k; char s[2010][1010]; int a[1010][1010]; int main() { scanf( %d%d%d n , &n, &m, &k); if (k == 1) { int cnt = 0; int tot = 0; for (int i = 0; i < 2 * n - 1; ++i) { gets(s[0]); for (int j = 0; j < m - ((i + 1) & 1); ++j, ++tot) if (s[0][j] == E ) cnt++; } if (cnt * 4 >= tot * 3) { puts( YES ); for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (j != 0) printf( ); printf( 1 ); } printf( n ); } } else puts( NO ); return 0; } puts( YES ); for (int i = 0; i < 2 * n - 1; ++i) gets(s[i]); if (n < m) { for (int i = 0; i < n; ++i) { int ii = 2 * i; a[i][0] = 0; for (int j = 1; j < m; ++j) if (s[ii][j - 1] == E ) a[i][j] = a[i][j - 1]; else a[i][j] = 1 - a[i][j - 1]; } for (int i = 1; i < n; ++i) { int cnt = 0; for (int j = 0; j < m; ++j) if (s[2 * i - 1][j] == E ) cnt += a[i][j] == a[i - 1][j]; else cnt += a[i][j] != a[i - 1][j]; if (cnt < m - cnt) for (int j = 0; j < m; ++j) a[i][j] = 1 - a[i][j]; } } else { for (int i = 0; i < m; ++i) { a[0][i] = 0; for (int j = 1; j < n; ++j) if (s[2 * j - 1][i] == E ) a[j][i] = a[j - 1][i]; else a[j][i] = 1 - a[j - 1][i]; } for (int i = 1; i < m; ++i) { int cnt = 0; for (int j = 0; j < n; ++j) if (s[2 * j][i - 1] == E ) cnt += a[j][i] == a[j][i - 1]; else cnt += a[j][i] != a[j][i - 1]; if (cnt < n - cnt) for (int j = 0; j < n; ++j) a[j][i] = 1 - a[j][i]; } } for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { if (j != 0) printf( ); printf( %d , a[i][j] + 1); } printf( n ); } } |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
// Date : Thu Jul 24 13:40:01 2014
// Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_stub.v
// Design : fifo_generator_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2014.1" *)
module fifo_generator_0(wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, dout, full, empty, valid)
/* synthesis syn_black_box black_box_pad_pin="wr_clk,wr_rst,rd_clk,rd_rst,din[9:0],wr_en,rd_en,dout[9:0],full,empty,valid" */;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [9:0]din;
input wr_en;
input rd_en;
output [9:0]dout;
output full;
output empty;
output valid;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int inf = 1e9; const double eps = 1e-9; const int INF = inf; const double EPS = eps; struct __timestamper {}; class fenv_tree { static int f(int x) { return x & -x; } vector<int> tr; public: fenv_tree(int n) : tr(n + 1, -inf) {} void relax(int x, int v) { for (x++; x < ((int)(tr).size()); x += f(x)) tr[x] = max(tr[x], v); } int get(int x) { int res = -inf; for (x++; x > 0; x -= f(x)) res = max(res, tr[x]); return res; } }; vector<vector<pair<int, int>>> rests; int n; vector<int> rig, spl; vector<int> ans; void restore(int v) { if (v + 1 < spl[v]) { rig[v + 1] = spl[v] - 1; restore(v + 1); } ans.push_back(v); if (spl[v] <= rig[v]) { rig[spl[v]] = rig[v]; restore(spl[v]); } } bool check() { rig = vector<int>(n); for (int i = 0; i < (n); i++) rig[i] = i; spl = vector<int>(n); fenv_tree tr(n); for (int i = 0; i < (n); i++) tr.relax(i, rig[i]); for (int i = n - 1; i >= 0; i--) { for (pair<int, int> r : rests[i]) { if (r.first <= i) return false; rig[i] = max(rig[i], rig[r.first]); } rig[i] = tr.get(rig[i]); tr.relax(i, rig[i]); vector<pair<int, int>> seq; for (int i2 = i + 1; i2 <= rig[i];) { seq.push_back(make_pair(i2, rig[i2])); i2 = rig[i2] + 1; } int b1 = 0, b2 = ((int)(seq).size()); for (pair<int, int> r : rests[i]) { int id = upper_bound(seq.begin(), seq.end(), make_pair(r.first, inf)) - seq.begin() - 1; if (r.second == 0) { b1 = max(b1, id + 1); } else { b2 = min(b2, id); } } if (b1 > b2) return false; if (seq.empty()) { spl[i] = i + 1; } else { spl[i] = b1 == ((int)(seq).size()) ? rig[i] + 1 : seq[b1].first; } } ans.clear(); rig[0] = n - 1; restore(0); for (int i = 0; i < (n); i++) printf( %d%c , ans[i] + 1, n [i + 1 < n]); return true; } int main() { int m; while (scanf( %d%d , &n, &m) == 2) { rests = vector<vector<pair<int, int>>>(n); for (int i = 0; i < (m); i++) { int a, b; char ty[10]; scanf( %d%d%s , &a, &b, ty), a--, b--; rests[a].push_back(make_pair(b, !strcmp(ty, LEFT ) ? 0 : 1)); } if (!check()) { printf( IMPOSSIBLE n ); } } return 0; } |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module hb_dec_tb( ) ;
// Parameters for instantiation
parameter clocks = 9'd12 ; // Number of clocks per input
parameter decim = 1 ; // Sets the filter to decimate
parameter rate = 2 ; // Sets the decimation rate
reg clock ;
reg reset ;
reg enable ;
reg strobe_in ;
reg signed [23:0] data_in ;
wire strobe_out ;
wire signed [23:0] data_out ;
initial
begin
$dumpfile("hb_dec_tb.vcd");
$dumpvars(0,hb_dec_tb);
end
// Setup the clock
initial clock = 1'b0 ;
always #5 clock <= ~clock ;
// Come out of reset after a while
initial reset = 1'b1 ;
initial #1000 reset = 1'b0 ;
// Enable the entire system
initial enable = 1'b1 ;
// Instantiate UUT
/*
halfband_ideal
#(
.decim ( decim ),
.rate ( rate )
) uut(
.clock ( clock ),
.reset ( reset ),
.enable ( enable ),
.strobe_in ( strobe_in ),
.data_in ( data_in ),
.strobe_out ( strobe_out ),
.data_out ( data_out )
) ;
*/
hb_dec #(.WIDTH(24)) uut
(.clk(clock),.rst(reset),.bypass(0),.run(1),.cpi(clocks),.stb_in(strobe_in),.data_in(data_in),
.stb_out(strobe_out),.data_out(data_out) );
integer i, ri, ro, infile, outfile ;
always @(posedge clock)
begin
if(strobe_out)
$display(data_out);
end
// Setup file IO
initial begin
infile = $fopen("input.dat","r") ;
outfile = $fopen("output.dat","r") ;
$timeformat(-9, 2, " ns", 10) ;
end
reg endofsim ;
reg signed [17:0] compare ;
integer noe ;
initial noe = 0 ;
initial begin
// Initialize inputs
strobe_in <= 1'd0 ;
data_in <= 18'd0 ;
// Wait for reset to go away
@(negedge reset) #0 ;
// While we're still simulating ...
while( !endofsim ) begin
// Write the input from the file or 0 if EOF...
@( posedge clock ) begin
//#1 ;
strobe_in <= 1'b1 ;
if( !$feof(infile) )
ri = $fscanf( infile, "%d", data_in ) ;
else
data_in <= 18'd0 ;
end
// Clocked in - set the strobe to 0 if the number of
// clocks per sample is greater than 1
if( clocks > 1 ) begin
@(posedge clock) begin
strobe_in <= 1'b0 ;
end
// Wait for the specified number of cycles
for( i = 0 ; i < (clocks-2) ; i = i + 1 ) begin
@(posedge clock) #1 ;
end
end
end
// Print out the number of errors that occured
if( noe )
$display( "FAILED: %d errors during simulation", noe ) ;
else
$display( "PASSED: Simulation successful" ) ;
$finish ;
end
// Output comparison of simulated values versus known good values
always @ (posedge clock) begin
if( reset )
endofsim <= 1'b0 ;
else begin
if( !$feof(outfile) ) begin
if( strobe_out ) begin
ro = $fscanf( outfile, "%d\n", compare ) ;
if( compare != data_out ) begin
//$display( "%t: %d != %d", $realtime, data_out, compare ) ;
noe = noe + 1 ;
end
end
end else begin
// Signal end of simulation when no more outputs
endofsim <= 1'b1 ;
end
end
end
endmodule // hb_dec_tb
|
#include <bits/stdc++.h> using namespace std; int read() { char ch = getchar(); int x = 0, f = 1; while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) { x = x * 10 + ch - 0 ; ch = getchar(); } return x * f; } const int N = 2e5 + 5; long long a[N]; long long n, m, k; bool check(int x) { long long now = 0, cnt = 1; for (int i = n - x + 1; i <= n; i++) { if (now + a[i] > k) { cnt++, now = a[i]; } else now += a[i]; } return cnt <= m; } int upp(int l, int r) { while (l < r) { int mid = (l + r + 1) >> 1; if (check(mid)) l = mid; else r = mid - 1; } return l; } int main() { n = read(), m = read(), k = read(); for (int i = 1; i <= n; i++) a[i] = read(); printf( %d n , upp(1, n)); return 0; } |
// This is a component of pluto_step_spi, a stepper driver for linuxcnc over SPI.
// based on the main.v from Jeff Epler <>
// Copyright 2013 by Matsche <>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//**********************************************************************
module pluto_spi_stepper(clk, SCK, MOSI, MISO, SSEL, nRESET, nPE, LED, nConfig, dout, din, step, dir);
parameter W=10;
parameter F=11;
parameter T=4;
input clk;
input SCK, SSEL, MOSI, nRESET;
output MISO, nConfig = 1'bZ, nPE;
output LED;
input [15:0] din;
assign nConfig = nRESET;
//assign nConfig = 1'b1;
assign nPE = 1'b1;
reg Spolarity;
reg[13:0] real_dout; output [13:0] dout = do_tristate ? 14'bZ : real_dout;
wire[3:0] real_step; output [3:0] step = do_tristate ? 4'bZ : real_step ^ {4{Spolarity}};
wire[3:0] real_dir; output [3:0] dir = do_tristate ? 4'bZ : real_dir;
wire [W+F-1:0] pos0, pos1, pos2, pos3;
reg [F:0] vel0, vel1, vel2, vel3;
reg [T-1:0] dirtime, steptime;
reg [1:0] tap;
reg [10:0] div2048;
wire stepcnt = ~|(div2048[5:0]);
always @(posedge clk) begin
div2048 <= div2048 + 1'd1;
end
wire do_enable_wdt, do_tristate;
wdt w(clk, do_enable_wdt, &div2048, do_tristate);
stepgen #(W,F,T) s0(clk, stepcnt, pos0, vel0, dirtime, steptime, real_step[0], real_dir[0], tap);
stepgen #(W,F,T) s1(clk, stepcnt, pos1, vel1, dirtime, steptime, real_step[1], real_dir[1], tap);
stepgen #(W,F,T) s2(clk, stepcnt, pos2, vel2, dirtime, steptime, real_step[2], real_dir[2], tap);
stepgen #(W,F,T) s3(clk, stepcnt, pos3, vel3, dirtime, steptime, real_step[3], real_dir[3], tap);
//**********************************************************************
// SPI zeugs
// synchronizing the handshakes
//
reg [2:0] SCKr;
always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
wire SCK_risingedge = (SCKr[2:1]==2'b01); // now we can detect SCK rising edges
wire SCK_fallingedge = (SCKr[2:1]==2'b10); // and falling edges
wire SCK_high = SCKr[1]; // SCK is high
// same thing for SSEL
reg [2:0] SSELr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
wire MOSI_data = MOSI;
// we handle SPI in 8-bits format, so we need a 3 bits counter to count the bits as they come in
reg [2:0] bitcnt;
reg byte_received; // high when 8 bit has been received
reg [4:0] spibytecnt;
reg [7:0] data_recvd;
reg [7:0] data_sent;
reg [7:0] data_outbuf;
always @(posedge clk) begin
if(SSEL_startmessage) begin
//data_sent <= data_outbuf;
bitcnt <= 3'b000;
spibytecnt <= 5'b00000;
end
if(SSEL_active) begin
if(SCK_risingedge) begin
data_recvd <= {data_recvd[6:0], MOSI_data};
bitcnt <= bitcnt + 3'b001;
if(bitcnt==3'b000)
data_sent <= data_outbuf;
end
else if(SCK_fallingedge) begin
data_sent <= {data_sent[6:0], 1'b0};
if(bitcnt==3'b000) begin
spibytecnt <= spibytecnt + 5'b00001;
end
end
byte_received <= SCK_risingedge && (bitcnt==3'b111);
end
end
assign MISO = data_sent[7]; // send MSB first
// we assume that there is only one slave on the SPI bus
// so we don't bother with a tri-state buffer for MISO
// otherwise we would need to tri-state MISO when SSEL is inactive
reg [7:0] data_inbuf;
always @(posedge clk) begin
if(SSEL_active) begin
//------------------------------------------------- word 0
if(spibytecnt == 5'b00000) begin // 0
data_outbuf <= pos0[7:0];
if(byte_received)
data_inbuf <= data_recvd; //vel0[7:0]
end
else if(spibytecnt == 5'b00001) begin // 1
data_outbuf <= pos0[15:8];
if(byte_received)
vel0 <= {data_recvd,data_inbuf}; //vel0
end
else if(spibytecnt == 5'b00010) begin // 2
data_outbuf <= pos0[W+F-1:16];
if(byte_received)
data_inbuf <= data_recvd; //vel1[7:0]
end
else if(spibytecnt == 5'b00011) begin // 3
data_outbuf <= 8'b0;
if(byte_received)
vel1 <= {data_recvd,data_inbuf}; //vel1
end
//------------------------------------------------- word 1
else if(spibytecnt == 5'b00100) begin // 4
data_outbuf <= pos1[7:0];
if(byte_received)
data_inbuf <= data_recvd; //vel2[7:0]
end
else if(spibytecnt == 5'b00101) begin // 5
data_outbuf <= pos1[15:8];
if(byte_received)
vel2 <= {data_recvd,data_inbuf}; //vel2
end
else if(spibytecnt == 5'b00110) begin // 6
data_outbuf <= pos1[W+F-1:16];
if(byte_received)
data_inbuf <= data_recvd; //vel3[7:0]
end
else if(spibytecnt == 5'b00111) begin // 7
data_outbuf <= 8'b0;
if(byte_received)
vel3 <= {data_recvd,data_inbuf}; //vel3
end
//------------------------------------------------- word 2
else if(spibytecnt == 5'b01000) begin // 8
data_outbuf <= pos2[7:0];
if(byte_received)
data_inbuf <= data_recvd; //real_dout[7:0]
end
else if(spibytecnt == 5'b01001) begin // 9
data_outbuf <= pos2[15:8];
if(byte_received) begin
real_dout <= {data_recvd[5:0],data_inbuf}; //real_dout
end
end
else if(spibytecnt == 5'b01010) begin // 10
data_outbuf <= pos2[W+F-1:16];
if(byte_received)
data_inbuf <= data_recvd;
end
else if(spibytecnt == 5'b01011) begin // 11
data_outbuf <= 8'b0;
if(byte_received) begin
tap <= data_recvd[7:6];
steptime <= data_recvd[T-1:0];
Spolarity <= data_inbuf[7];
dirtime <= data_inbuf[T-1:0];
end
end
//------------------------------------------------- word 3
else if(spibytecnt == 5'b01100) data_outbuf <= pos3[7:0];
else if(spibytecnt == 5'b01101) data_outbuf <= pos3[15:8];
else if(spibytecnt == 5'b01110) data_outbuf <= pos3[W+F-1:16];
else if(spibytecnt == 5'b01111) data_outbuf <= 8'b0;
//------------------------------------------------- word 4
else if(spibytecnt == 5'b10000) data_outbuf <= din[7:0];
else if(spibytecnt == 5'b10001) data_outbuf <= din[15:8];
else if(spibytecnt == 5'b10010) data_outbuf <= 8'b0;
else if(spibytecnt == 5'b10011) data_outbuf <= 8'b0;
else data_outbuf <= spibytecnt;
end
end
assign LED = do_tristate ? 1'bZ : (real_step[0] ^ real_dir[0]);
assign do_enable_wdt = data_recvd[6] & (spibytecnt == 5'b01001) & byte_received;
endmodule
|
#include <bits/stdc++.h> using namespace std; struct node { int hx, hy; int tx, ty; int dep; long dir; int zt[15]; }; queue<node> q; int n, m, len; int dx[4] = {-1, 0, 1, 0}, dy[4] = {0, 1, 0, -1}; bool v[15][15][262144]; char c[30][30]; bool init(int a, int b) { if (a < 0 || a >= n || b < 0 || b >= m) return 0; return 1; } int update(int d, int nd) { d = d | (nd << ((len - 1) * 2)); d >>= 2; return d; } void out(int d) { for (int i = 1; i < len; i++) { int t = d % 4; if (t == 0) cout << w ; if (t == 1) cout << d ; if (t == 2) cout << s ; if (t == 3) cout << a ; d /= 4; } } void zut(int x) { for (int i = 1; i <= m; i++) { cout << x % 2; x /= 2; } } int ax, ay; node fst; int main() { cin >> n >> m; int fhx, fhy, ftx, fty; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) { cin >> c[i][j]; if (c[i][j] >= 1 && c[i][j] <= 9 ) len = max(len, c[i][j] - 0 ); if (c[i][j] == 1 ) { fhx = i; fhy = j; } if (c[i][j] == len + 0 ) { ftx = i; fty = j; } if (c[i][j] == @ ) { ax = i; ay = j; } } int fdir = 0; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (c[i][j] >= 1 && c[i][j] <= 9 ) { for (int k = 0; k < 4; k++) { int nx = i + dx[k], ny = j + dy[k]; if (init(nx, ny) && c[nx][ny] == c[i][j] - 1) { int nk = k; fdir = fdir | (nk << ((len - (c[i][j] - 0 )) * 2)); break; } } fst.zt[i] |= (1 << j); } fst.dir = fdir, fst.hx = fhx, fst.hy = fhy, fst.tx = ftx, fst.ty = fty, fst.dep = 0; q.push(fst); while (!q.empty()) { node f = q.front(); q.pop(); if (f.hx == ax && f.hy == ay) { cout << f.dep; return 0; } else { for (int i = 0; i < 4; i++) { int nx = f.hx + dx[i], ny = f.hy + dy[i]; if (!init(nx, ny)) continue; if (c[nx][ny] == # ) continue; if (f.zt[nx] & (1 << ny) && !(nx == f.tx && ny == f.ty)) continue; node nf = f; nf.hx = nx; nf.hy = ny; nf.tx = dx[f.dir & (3)] + f.tx; nf.ty = dy[f.dir & (3)] + f.ty; nf.zt[f.tx] ^= (1 << f.ty); nf.zt[nx] |= (1 << ny); nf.dir = update(f.dir, i); nf.dep++; if (v[nx][ny][nf.dir]) continue; v[nx][ny][nf.dir] = 1; q.push(nf); } } } cout << -1; return 0; } |
// Ethernet_v6.v -
// Contains
// i) block-level-wrapper
// ii) EMAC wrapper
// iii) GMII code
//-----------------------------------------------------------------------------
// Title : Block-level Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : v6_emac_v1_3_block.v
// Version : 1.3
//-----------------------------------------------------------------------------
// Description: This is the block-level wrapper for the Virtex-6 Embedded
// Tri-Mode Ethernet MAC. It is intended that this example design
// can be quickly adapted and downloaded onto an FPGA to provide
// a hardware test environment.
//
// The block-level wrapper:
//
// * instantiates appropriate PHY interface modules (GMII, MII,
// RGMII, SGMII or 1000BASE-X) as required per the user
// configuration;
//
// * instantiates some clocking and reset resources to operate
// the EMAC and its example design.
//
// Please refer to the Datasheet, Getting Started Guide, and
// the Virtex-6 Embedded Tri-Mode Ethernet MAC User Gude for
// further information.
//-----------------------------------------------------------------------------
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Module declaration for the block-level wrapper
//-----------------------------------------------------------------------------
(* box_type="user_black_box" *)
module v6_emac_v1_3_block
(
// TX clock output
TX_CLK_OUT,
// TX clock input from BUFG
TX_CLK,
// Client receiver interface
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
// Client transmitter interface
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
// MAC control interface
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
// Receive-side PHY clock on regional buffer, to EMAC
PHY_RX_CLK,
// Clock signal
GTX_CLK,
// GMII interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
// Asynchronous reset
RESET
);
//-----------------------------------------------------------------------------
// Port declarations
//-----------------------------------------------------------------------------
// TX clock output
output TX_CLK_OUT;
// TX clock input from BUFG
input TX_CLK;
// Client receiver interface
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
// Client transmitter interface
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
// MAC control interface
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
// Receive-side PHY clock on regional buffer, to EMAC
input PHY_RX_CLK;
// Clock signal
input GTX_CLK;
// GMII interface
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
// Asynchronous reset
input RESET;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; bool flag = true; while (cin >> n >> m) { for (int i = 0; i < n; i++) { for (int j = 1; j <= m; j++) { if (i % 2 && j < m && flag) cout << . ; else if (i % 2 && j == m && flag) cout << # ; else if (i % 2 && j == 1 && !flag) cout << # ; else if (i % 2 && j > 1 && !flag) cout << . ; else cout << # ; } if (i % 2) flag = !flag; cout << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; signed main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t; cin >> t; while (t--) { long long n, sum = 0; cin >> n; vector<long long> v(n), ans, odd; for (long long i = 0; i < n; i++) { cin >> v[i]; if (v[i] % 2 == 0) { ans.push_back(i); } else odd.push_back(i); sum += v[i]; } long long count = 0; for (long long i = 2; i * i <= sum; i++) { if (sum % i == 0) count++; } if (count > 0) { cout << n << endl; for (long long i = 0; i < n; i++) cout << i + 1 << ; } else { cout << n - 1 << endl; odd.pop_back(); for (long long i = 0; i < ans.size(); i++) { cout << ans[i] + 1 << ; } for (long long i = 0; i < odd.size(); i++) { cout << odd[i] + 1 << ; } } cout << endl; } } |
/*
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| eg_comb/ | | 49/49 | 0/0 | 153/153 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | eg_comb |
| eg_comb/ | | 42/42 | 0/0 | 134/134 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | eg_comb |
| eg_comb/ | | 39/39 | 0/0 | 129/129 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | eg_comb |
| eg_comb/ | | 43/43 | 0/0 | 122/122 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | eg_comb |
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
This module represents all the envelope generator calculations.
Everything is combinational. The testbench ver/eg2 checks the
functionality of this module.
*/
module eg_comb(
input attack,
input [ 4:0] base_rate,
input [ 4:0] keycode,
input [14:0] eg_cnt,
input cnt_in,
input [ 1:0] ks,
input [ 9:0] eg_in,
input [ 6:0] lfo_mod,
input amsen,
input [ 1:0] ams,
input [ 6:0] tl,
output cnt_lsb,
output reg [9:0] eg_limited,
output reg [9:0] eg_pure
);
reg [6:0] pre_rate;
reg [5:0] rate;
always @(*) begin : pre_rate_calc
if( base_rate == 5'd0 )
pre_rate = 7'd0;
else
case( ks )
2'd3: pre_rate = { base_rate, 1'b0 } + { 1'b0, keycode };
2'd2: pre_rate = { base_rate, 1'b0 } + { 2'b0, keycode[4:1] };
2'd1: pre_rate = { base_rate, 1'b0 } + { 3'b0, keycode[4:2] };
2'd0: pre_rate = { base_rate, 1'b0 } + { 4'b0, keycode[4:3] };
endcase
end
always @(*)
rate = pre_rate[6] ? 6'd63 : pre_rate[5:0];
reg [2:0] cnt;
reg [4:0] mux_sel;
always @(*) begin
mux_sel = attack ? (rate[5:2]+4'd1): {1'b0,rate[5:2]};
end // always @(*)
always @(*)
case( mux_sel )
5'h0: cnt = eg_cnt[14:12];
5'h1: cnt = eg_cnt[13:11];
5'h2: cnt = eg_cnt[12:10];
5'h3: cnt = eg_cnt[11: 9];
5'h4: cnt = eg_cnt[10: 8];
5'h5: cnt = eg_cnt[ 9: 7];
5'h6: cnt = eg_cnt[ 8: 6];
5'h7: cnt = eg_cnt[ 7: 5];
5'h8: cnt = eg_cnt[ 6: 4];
5'h9: cnt = eg_cnt[ 5: 3];
5'ha: cnt = eg_cnt[ 4: 2];
5'hb: cnt = eg_cnt[ 3: 1];
default: cnt = eg_cnt[ 2: 0];
endcase
////////////////////////////////
reg step;
reg [7:0] step_idx;
always @(*) begin : rate_step
if( rate[5:4]==2'b11 ) begin // 0 means 1x, 1 means 2x
if( rate[5:2]==4'hf && attack)
step_idx = 8'b11111111; // Maximum attack speed, rates 60&61
else
case( rate[1:0] )
2'd0: step_idx = 8'b00000000;
2'd1: step_idx = 8'b10001000; // 2
2'd2: step_idx = 8'b10101010; // 4
2'd3: step_idx = 8'b11101110; // 6
endcase
end
else begin
if( rate[5:2]==4'd0 && !attack)
step_idx = 8'b11111110; // limit slowest decay rate
else
case( rate[1:0] )
2'd0: step_idx = 8'b10101010; // 4
2'd1: step_idx = 8'b11101010; // 5
2'd2: step_idx = 8'b11101110; // 6
2'd3: step_idx = 8'b11111110; // 7
endcase
end
// a rate of zero keeps the level still
step = rate[5:1]==5'd0 ? 1'b0 : step_idx[ cnt ];
end
reg sum_up;
assign cnt_lsb = cnt[0];
always @(*) begin
sum_up = cnt[0] != cnt_in;
end
//////////////////////////////////////////////////////////////
// cnt/cnt_lsb/cnt_in not used below this point
reg [3:0] dr_sum;
reg [10:0] dr_result;
always @(*) begin
case( rate[5:2] )
4'b1100: dr_sum = { 2'b0, step, ~step }; // 12
4'b1101: dr_sum = { 1'b0, step, ~step, 1'b0 }; // 13
4'b1110: dr_sum = { step, ~step, 2'b0 }; // 14
4'b1111: dr_sum = 4'd8;// 15
default: dr_sum = { 2'b0, step, 1'b0 };
endcase
dr_result = {6'd0, dr_sum} + eg_in;
end
reg [ 7:0] ar_sum0;
reg [ 8:0] ar_sum1;
reg [10:0] ar_result;
reg [ 9:0] ar_sum;
always @(*) begin : ar_calculation
casez( rate[5:2] )
default: ar_sum0 = {2'd0, eg_in[9:4]};
4'b1101: ar_sum0 = {1'd0, eg_in[9:3]};
4'b111?: ar_sum0 = eg_in[9:2];
endcase
ar_sum1 = ar_sum0+9'd1;
if( rate[5:4] == 2'b11 )
ar_sum = step ? { ar_sum1, 1'b0 } : { 1'b0, ar_sum1 };
else
ar_sum = step ? { 1'b0, ar_sum1 } : 10'd0;
ar_result = rate[5:1]==5'h1F ? 11'd0 : eg_in-ar_sum;
end
///////////////////////////////////////////////////////////
// rate not used below this point
always @(*) begin
if(sum_up) begin
if( attack )
eg_pure = ar_result[10] ? 10'd0: ar_result[9:0];
else
eg_pure = dr_result[10] ? 10'h3FF : dr_result[9:0];
end
else eg_pure = eg_in;
end
//////////////////////////////////////////////////////////////
reg [ 8:0] am_final;
reg [10:0] sum_eg_tl;
reg [11:0] sum_eg_tl_am;
reg [ 5:0] am_inverted;
always @(*) begin
am_inverted = lfo_mod[6] ? ~lfo_mod[5:0] : lfo_mod[5:0];
end
always @(*) begin
casez( {amsen, ams } )
default: am_final = 9'd0;
3'b1_01: am_final = { 5'd0, am_inverted[5:2] };
3'b1_10: am_final = { 3'd0, am_inverted };
3'b1_11: am_final = { 2'd0, am_inverted, 1'b0 };
endcase
sum_eg_tl = { tl, 3'd0 } + eg_pure;
sum_eg_tl_am = sum_eg_tl + { 3'd0, am_final };
end
always @(*)
eg_limited = sum_eg_tl_am[11:10]==2'd0 ? sum_eg_tl_am[9:0] : 10'h3ff;
endmodule // eg_comb |
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Wishbone module for spi communications with an SD Card
// The programming interface is simple --
// Write the desired clock divider to address 1 (should be 1 or higher)
// Status is in address 0. A 1 indicates the last transaction is done and it is safe to
// send another
// Writing a byte to address 2 sends that byte over SPI. When it is done,
// status (addr 0) goes high again, and the received byte can be read from address 3.
module sd_spi_wb
(input clk,
input rst,
// SD Card interface
output sd_clk,
output sd_csn,
output sd_mosi,
input sd_miso,
input wb_cyc_i,
input wb_stb_i,
input wb_we_i,
input [1:0] wb_adr_i,
input [7:0] wb_dat_i,
output reg [7:0] wb_dat_o,
output reg wb_ack_o);
localparam ADDR_STATUS = 0;
localparam ADDR_CLKDIV = 1;
localparam ADDR_WRITE = 2;
localparam ADDR_READ = 3;
wire [7:0] status, rcv_dat;
reg [7:0] clkdiv;
wire ready;
reg ack_d1;
reg cs_reg;
assign sd_csn = ~cs_reg; // FIXME
always @(posedge clk)
if(rst) ack_d1 <= 0;
else ack_d1 <= wb_ack_o;
always @(posedge clk)
if(rst) wb_ack_o <= 0;
else wb_ack_o <= wb_cyc_i & wb_stb_i & ~ack_d1;
always @(posedge clk)
case(wb_adr_i)
ADDR_STATUS : wb_dat_o <= {7'd0,ready};
ADDR_CLKDIV : wb_dat_o <= clkdiv;
ADDR_READ : wb_dat_o <= rcv_dat;
default : wb_dat_o <= 0;
endcase // case(wb_adr_i)
always @(posedge clk)
if(rst)
begin
clkdiv <= 200;
cs_reg <= 0;
end
else if(wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o)
case(wb_adr_i)
ADDR_STATUS : cs_reg <= wb_dat_i;
ADDR_CLKDIV : clkdiv <= wb_dat_i;
endcase // case(wb_adr_i)
wire go = wb_we_i & wb_stb_i & wb_cyc_i & wb_ack_o & (wb_adr_i == ADDR_WRITE);
sd_spi sd_spi(.clk(clk),.rst(rst),
.sd_clk(sd_clk),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
.clk_div(clkdiv),.send_dat(wb_dat_i),.rcv_dat(rcv_dat),
.go(go),.ready(ready) );
endmodule // sd_spi_wb
|
#include <bits/stdc++.h> using namespace std; int main() { int a, b; cin >> a >> b; int ans = 0; while ((a >= 1 && b > 1) || (a > 1 && b >= 1)) { if (a < b) { ans++; a--; b -= 2; } else { ans++; a -= 2; b--; } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const double PI = acos(-1); const double EPS = 1e-6; const int INF = 0x3f3f3f3f; inline int readint() { int sum = 0; char c = getchar(); bool f = 0; while (c < 0 || c > 9 ) { if (c == - ) f = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { sum = sum * 10 + c - 0 ; c = getchar(); } if (f) return -sum; return sum; } inline long long readLL() { long long sum = 0; char c = getchar(); bool f = 0; while (c < 0 || c > 9 ) { if (c == - ) f = 1; c = getchar(); } while (c >= 0 && c <= 9 ) { sum = sum * 10 + c - 0 ; c = getchar(); } if (f) return -sum; return sum; } const int maxn = 250015; long long inv[maxn], p[maxn]; void CNumberInit(int MAXNUM, long long mod) { inv[0] = inv[1] = 1; p[0] = p[1] = 1; for (int i = 2; i <= MAXNUM; i++) { inv[i] = (mod - mod / i) * inv[mod % i] % mod; p[i] = p[i - 1] * i % mod; } for (int i = 2; i <= MAXNUM; i++) inv[i] = inv[i - 1] * inv[i] % mod; } long long qmod(long long a, long long b, long long c) { long long ret = 1; for (; b; b >>= 1) { if (b & 1) ret = ret * a % c; a = a * a % c; } return ret; } vector<int> megumi; long long mod; int k; long long dp[20][250005]; int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long n; cin >> n >> k >> mod; CNumberInit(n + 5, mod); if (n % 2) { cout << qmod(k, n, mod) << endl; } else { for (int i = 2; i <= n; i += 2) { if ((i & n) == i) megumi.push_back(i); } long long ans = 0; dp[0][n] = 1; for (int i = 1; i <= min(17, k); i++) { int tmpans = 0; for (int j = 0; j < megumi.size(); j++) { if (!dp[i - 1][megumi[j]]) continue; int Megumi = megumi[j] & (megumi[j] - 1); int step = Megumi ^ megumi[j]; for (int k = step; k <= Megumi; k += step) { if ((k & Megumi) == k) { dp[i][k] += dp[i - 1][megumi[j]] * p[megumi[j]] % mod * inv[k] % mod * inv[megumi[j] - k] % mod; dp[i][k] %= mod; } } tmpans = (tmpans + dp[i - 1][megumi[j]]) % mod; } ans += tmpans * inv[k - i] % mod; } ans = ans * p[k] % mod; ans = qmod(k, n, mod) - ans; ans = (ans % mod + mod) % mod; cout << ans << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; struct node { int x, y; } A[10005], B[10005], CA[10005], CB[10005]; int tim, qim; node operator+(node a, node b) { return node{a.x + b.x, a.y + b.y}; } node operator-(node a, node b) { return node{a.x - b.x, a.y - b.y}; } int operator*(node a, node b) { return a.x * b.x + a.y * b.y; } int operator/(node a, node b) { return a.x * b.y - a.y * b.x; } bool operator<(node a, node b) { if (a.x == b.x) return a.y > b.y; return a.x < b.x; } void convex_hull(node p[], node c[], int n, int &tp) { sort(p + 1, p + n + 1); tp = 0; for (int i = 1; i <= n; i++) { while (tp > 1 && (c[tp] - p[i]) / (c[tp - 1] - p[i]) >= 0) tp--; c[++tp] = p[i]; } int k = tp--; for (int i = n; i >= 1; i--) { while (tp > k && (c[tp] - p[i]) / (c[tp - 1] - p[i]) >= 0) tp--; c[++tp] = p[i]; } tp--; } bool solve(node a[], node b[], int na, int nb) { random_shuffle(a + 1, a + na + 1); random_shuffle(b + 1, b + nb + 1); for (int i = 1; i <= na; i++) for (int j = i + 1, k; j <= na; j++) { node pa = a[i], pb = a[j]; double lp = -1e100, rp = 1e100, inf = 1e100; for (k = 1; k <= na; k++) { if (k == i) continue; if (k == j) continue; int ta = (a[k] - pa) * (a[k] - pb); int tb = (pa - a[k]) / (pa - pb); assert(tb != 0); if (tb == 0) { if (ta > 0) break; else continue; } double r = (double)ta / tb; if (tb < 0) rp = min(rp, r); else if (tb > 0) lp = max(lp, r); if (lp > rp) break; } if (k <= na || lp > rp) continue; for (k = 1; k <= nb; k++) { int ta = (b[k] - pa) * (b[k] - pb); int tb = (pa - b[k]) / (pa - pb); if (tb == 0) { if (ta <= 0) break; else continue; } double r = (double)ta / tb; if (tb > 0) rp = min(rp, r); else if (tb < 0) lp = max(lp, r); if (lp >= rp) break; } if (k > nb && lp < rp) return 1; } return 0; } int main() { srand(time(NULL)); clock_t st, ed; double totaltime; st = clock(); int n, m, cn, cm, i; scanf( %d%d , &n, &m); for (i = 1; i <= n; i++) scanf( %d%d , &A[i].x, &A[i].y); for (i = 1; i <= m; i++) scanf( %d%d , &B[i].x, &B[i].y); if (n == 1 || m == 1) return puts( YES ), 0; convex_hull(A, CA, n, cn); convex_hull(B, CB, m, cm); if (solve(CA, B, cn, m) || solve(CB, A, cm, n)) puts( YES ); else puts( NO ); ed = clock(); totaltime = (double)(ed - st) / CLOCKS_PER_SEC; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; scanf( %d , &n); vector<int> p(n); for (int i = 0; i < n; ++i) cin >> p[i]; double ans = 0; int cnt[102] = {0}; double loser[102] = {0}; for (int i = 0; i < n; ++i) loser[i] = 1.0; for (int i = 1; i < n; ++i) { ++cnt[i]; loser[i] *= 1.0 - p[i] / 100.0; } for (int st = n; st <= 300004; ++st) { int bi = -1; double pw = 0; double win[102] = {0}, pref[102] = {0}, suf[102] = {0}; for (int i = 0; i < n; ++i) { win[i] = 1.0 - loser[i]; } pref[0] = win[0]; for (int i = 1; i < n; ++i) pref[i] = pref[i - 1] * win[i]; suf[n - 1] = win[n - 1]; for (int i = n - 2; i >= 0; --i) suf[i] = suf[i + 1] * win[i]; for (int i = 0; i < n; ++i) { double curP = 1.0 * p[i] / 100 * loser[i]; if (i) curP *= pref[i - 1]; if (i + 1 < n) curP *= suf[i + 1]; if (curP > pw) { pw = curP; bi = i; } } ans += st * pw; cnt[bi]++; loser[bi] *= 1.0 - p[bi] / 100.0; } printf( %.10lf n , ans); return 0; } |
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH UST
// Engineer: Wojciech Gredel, Hubert Górowski
//
// Create Date:
// Design Name:
// Module Name: DrawBackground
// Project Name: DOS_Mario
// Target Devices: Basys3
// Tool versions: Vivado 2016.1
// Description:
// This module displays background
//
// Dependencies:
//
// Revision:
// Revision 0.01 - Module created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DrawBackground (
input wire [9:0] hcount_in,
input wire hsync_in,
input wire [9:0] vcount_in,
input wire vsync_in,
input wire blnk_in,
input wire [9:0] xoffset,
input wire clk,
input wire rst,
output reg [9:0] hcount_out,
output reg hsync_out,
output reg [9:0] vcount_out,
output reg vsync_out,
output reg [23:0] rgb_out,
output reg blnk_out
);
//Colors
localparam BLACK = 24'h00_00_00;
localparam WHITE = 24'hff_ff_ff;
//Cords
localparam OFFSET = 100;
localparam YRES = 480;
reg [7:0] r, g, b;
reg [23:0] rgb_cl;
reg [9:0] hcount_cl, vcount_cl;
reg hsync_cl, vsync_cl, blnk_cl;
wire [9:0] hcount_cl_out, vcount_cl_out;
wire [23:0] rgb_cl_out;
Clouds My_Clouds(
.clk(clk),
.rst(rst),
.xoffset(xoffset),
.hcount_in(hcount_cl),
.hsync_in(hsync_cl),
.vcount_in(vcount_cl),
.vsync_in(vsync_cl),
.rgb_in(rgb_cl),
.blnk_in(blnk_cl),
.hcount_out(hcount_cl_out),
.hsync_out(hsync_cl_out),
.vcount_out(vcount_cl_out),
.vsync_out(vsync_cl_out),
.rgb_out(rgb_cl_out),
.blnk_out(blnk_cl_out)
);
always @(posedge clk or posedge rst) begin
if(rst) begin
hcount_cl <= #1 0;
hsync_cl <= #1 0;
vcount_cl <= #1 0;
vsync_cl <= #1 0;
rgb_cl <= #1 0;
blnk_cl <= #1 0;
hcount_out <= #1 0;
hsync_out <= #1 0;
vcount_out <= #1 0;
vsync_out <= #1 0;
rgb_out <= #1 0;
blnk_out <= #1 0;
end
else begin
hcount_cl <= #1 hcount_in;
hsync_cl <= #1 hsync_in;
vcount_cl <= #1 vcount_in;
vsync_cl <= #1 vsync_in;
rgb_cl <= #1 {r,g,b};
blnk_cl <= #1 blnk_in;
hcount_out <= #1 hcount_cl_out;
hsync_out <= #1 hsync_cl_out;
vcount_out <= #1 vcount_cl_out;
vsync_out <= #1 vsync_cl_out;
rgb_out <= #1 rgb_cl_out;
blnk_out <= #1 blnk_cl_out;
end
end
//Display gradiented sky
always @* begin
if((YRES - vcount_in - 1) < OFFSET) {r,g,b} = WHITE; // any color, will be overwritten
else begin
{b} = 8'hff;
{r} = (vcount_in >> 1);
{g} = (vcount_in >> 1);
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; template <class T> bool ckmin(T& a, const T& b) { return a > b ? a = b, 1 : 0; } template <class T> bool ckmax(T& a, const T& b) { return a < b ? a = b, 1 : 0; } const int N = 1 << 7, M = 1 << 14; int a[M], b[M], c[M]; bool val[N], vis[N]; vector<int> g[N]; int n, m; bool dfs(int u, bool x) { val[u] = x; vis[u] = true; for (int e : g[u]) { int v = a[e] ^ b[e] ^ u; bool new_x = c[e] ^ 1 ^ x; if (!vis[v]) { if (!dfs(v, new_x)) return false; } else if (new_x != val[v]) return false; } return true; } bool solve(bool init) { fill(vis, vis + n, false); fill(val, val + n, false); for (auto u = (0); u < (n); ++u) if (!vis[u] && !dfs(u, init)) return false; return true; } signed main() { ios::sync_with_stdio(false); cin.tie(nullptr); cin >> n >> m; for (auto e = (0); e < (m); ++e) { cin >> a[e] >> b[e] >> c[e], --a[e], --b[e]; g[a[e]].push_back(e); g[b[e]].push_back(e); } if (solve(0) || solve(1)) { int cnt = 0; for (auto u = (0); u < (n); ++u) cnt += val[u]; cout << cnt << n ; for (auto e = (0); e < (m); ++e) assert(c[e] ^ val[a[e]] ^ val[b[e]]); for (auto u = (0); u < (n); ++u) if (val[u]) cout << u + 1 << ; } else cout << Impossible ; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// adbg_or1k_status_reg.v ////
//// ////
//// ////
//// This file is part of the SoC Debug Interface. ////
//// ////
//// Author(s): ////
//// Igor Mohor () ////
//// Nathan Yawn () ////
//// ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2011 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: adbg_or1k_status_reg.v,v $
// Revision 1.3 2011-10-24 02:25:11 natey
// Removed extraneous '#1' delays, which were a holdover from the original
// versions in the previous dbg_if core.
//
// Revision 1.2 2010-01-10 22:54:10 Nathan
// Update copyright dates
//
// Revision 1.1 2008/07/22 20:28:31 Nathan
// Changed names of all files and modules (prefixed an a, for advanced). Cleanup, indenting. No functional changes.
//
// Revision 1.3 2008/07/06 20:02:54 Nathan
// Fixes for synthesis with Xilinx ISE (also synthesizable with
// Quartus II 7.0). Ran through dos2unix.
//
// Revision 1.2 2008/06/26 20:52:32 Nathan
// OR1K module tested and working. Added copyright / license info
// to _define files. Other cleanup.
//
//
//
//
`include "adbg_or1k_defines.v"
module adbg_or1k_status_reg (
data_i,
we_i,
tck_i,
bp_i,
rst_i,
cpu_clk_i,
ctrl_reg_o,
cpu_stall_o,
cpu_rst_o
);
input [`DBG_OR1K_STATUS_LEN - 1:0] data_i;
input we_i;
input tck_i;
input bp_i;
input rst_i;
input cpu_clk_i;
output [`DBG_OR1K_STATUS_LEN - 1:0] ctrl_reg_o;
output cpu_stall_o;
output cpu_rst_o;
reg cpu_reset;
wire [2:1] cpu_op_out;
reg stall_bp, stall_bp_csff, stall_bp_tck;
reg stall_reg, stall_reg_csff, stall_reg_cpu;
reg cpu_reset_csff;
reg cpu_rst_o;
// Breakpoint is latched and synchronized. Stall is set and latched.
// This is done in the CPU clock domain, because the JTAG clock (TCK) is
// irregular. By only allowing bp_i to set (but not reset) the stall_bp
// signal, we insure that the CPU will remain in the stalled state until
// the debug host can read the state.
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if(rst_i)
stall_bp <= 1'b0;
else if(bp_i)
stall_bp <= 1'b1;
else if(stall_reg_cpu)
stall_bp <= 1'b0;
end
// Synchronizing
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
begin
stall_bp_csff <= 1'b0;
stall_bp_tck <= 1'b0;
end
else
begin
stall_bp_csff <= stall_bp;
stall_bp_tck <= stall_bp_csff;
end
end
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
begin
stall_reg_csff <= 1'b0;
stall_reg_cpu <= 1'b0;
end
else
begin
stall_reg_csff <= stall_reg;
stall_reg_cpu <= stall_reg_csff;
end
end
// bp_i forces a stall immediately on a breakpoint
// stall_bp holds the stall until the debug host acts
// stall_reg_cpu allows the debug host to control a stall.
assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
// Writing data to the control registers (stall)
// This can be set either by the debug host, or by
// a CPU breakpoint. It can only be cleared by the host.
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
stall_reg <= 1'b0;
else if (stall_bp_tck)
stall_reg <= 1'b1;
else if (we_i)
stall_reg <= data_i[0];
end
// Writing data to the control registers (reset)
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
cpu_reset <= 1'b0;
else if(we_i)
cpu_reset <= data_i[1];
end
// Synchronizing signals from registers
always @ (posedge cpu_clk_i or posedge rst_i)
begin
if (rst_i)
begin
cpu_reset_csff <= 1'b0;
cpu_rst_o <= 1'b0;
end
else
begin
cpu_reset_csff <= cpu_reset;
cpu_rst_o <= cpu_reset_csff;
end
end
// Value for read back
assign ctrl_reg_o = {cpu_reset, stall_reg};
endmodule
|
// Blitter address generator
// It can increment or decrement selected pointer register or add or substract any selected modulo register
module agnus_blitter_adrgen
(
input clk, // bus clock
input clk7_en,
input reset, // reset
input first_line_pixel,
input [1:0] ptrsel, // pointer register selection
input [1:0] modsel, // modulo register selection
input enaptr, // enable pointer selection and update
input incptr, // increase selected pointer register
input decptr, // decrease selected pointer register
input addmod, // add selected modulo register to selected pointer register
input submod, // substract selected modulo register from selected pointer register
output sign_out, // sign output (used for line mode)
input [15:0] data_in, // bus data in
input [8:1] reg_address_in, // register address input
output [20:1] address_out // generated address out
);
//register names and addresses
parameter BLTAMOD = 9'h064;
parameter BLTBMOD = 9'h062;
parameter BLTCMOD = 9'h060;
parameter BLTDMOD = 9'h066;
parameter BLTAPTH = 9'h050;
parameter BLTAPTL = 9'h052;
parameter BLTBPTH = 9'h04c;
parameter BLTBPTL = 9'h04e;
parameter BLTCPTH = 9'h048;
parameter BLTCPTL = 9'h04a;
parameter BLTDPTH = 9'h054;
parameter BLTDPTL = 9'h056;
//channel select codes
parameter CHA = 2'b10; // channel A
parameter CHB = 2'b01; // channel B
parameter CHC = 2'b00; // channel C
parameter CHD = 2'b11; // channel D
//local signals
wire [1:0] bltptr_sel; // blitter pointer select
wire [20:1] bltptr_in; // blitter pointer registers input
reg [20:16] bltpth [3:0]; // blitter pointer register bank (high)
wire [20:16] bltpth_out; // blitter pointer register bank output (high)
reg [15:1] bltptl [3:0]; // blitter pointer register bank (low)
wire [15:1] bltptl_out; // blitter pointer register bank output (low)
wire [20:1] bltptr_out; // blitter pointer register bank output
wire [1:0] bltmod_sel; // blitter modulo register select
reg [15:1] bltmod [3:0]; // blitter modulo register bank
wire [15:1] bltmod_out; // blitter modulo register bank output
reg [20:1] newptr; // new pointer value
reg [20:1] t_newptr; // temporary pointer value
//--------------------------------------------------------------------------------------
//pointer register bank
assign bltptr_in[20:1] = enaptr ? newptr[20:1] : {data_in[4:0], data_in[15:1]};
assign bltptr_sel = enaptr ? ptrsel : {reg_address_in[4],reg_address_in[2]};
always @(posedge clk)
if (clk7_en) begin
if (enaptr || reg_address_in[8:1]==BLTAPTH[8:1] || reg_address_in[8:1]==BLTBPTH[8:1] || reg_address_in[8:1]==BLTCPTH[8:1] || reg_address_in[8:1]==BLTDPTH[8:1])
bltpth[bltptr_sel] <= bltptr_in[20:16];
end
assign bltpth_out = bltpth[bltptr_sel];
always @(posedge clk)
if (clk7_en) begin
if (enaptr || reg_address_in[8:1]==BLTAPTL[8:1] || reg_address_in[8:1]==BLTBPTL[8:1] || reg_address_in[8:1]==BLTCPTL[8:1] || reg_address_in[8:1]==BLTDPTL[8:1])
bltptl[bltptr_sel] <= bltptr_in[15:1];
end
assign bltptl_out = bltptl[bltptr_sel];
assign bltptr_out = {bltpth_out, bltptl_out};
assign address_out = enaptr && first_line_pixel ? {bltpth[CHD], bltptl[CHD]} : bltptr_out;
//--------------------------------------------------------------------------------------
//modulo register bank
assign bltmod_sel = enaptr ? modsel : reg_address_in[2:1];
always @(posedge clk)
if (clk7_en) begin
if (reg_address_in[8:3]==BLTAMOD[8:3])
bltmod[bltmod_sel] <= data_in[15:1];
end
assign bltmod_out = bltmod[modsel];
//--------------------------------------------------------------------------------------
// pointer arithmetic unit
// increment or decrement selected pointer
always @(*)
if (incptr && !decptr)
t_newptr = bltptr_out + 20'h1; // increment selected pointer
else if (!incptr && decptr)
t_newptr = bltptr_out - 20'h1; // decrement selected pointer
else
t_newptr = bltptr_out;
// add or substract modulo
always @(*)
if (addmod && !submod)
newptr = t_newptr + {{5{bltmod_out[15]}},bltmod_out[15:1]}; // add modulo (sign extended)
else if (!addmod && submod)
newptr = t_newptr - {{5{bltmod_out[15]}},bltmod_out[15:1]}; // substract modulo (sign extended)
else
newptr = t_newptr;
//sign output
assign sign_out = newptr[15]; // used in line mode as the sign of Bresenham's error accumulator (channel A pointer acts as an accumulator)
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EBUFN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__EBUFN_FUNCTIONAL_PP_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EBUFN_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; int min(int a, int b) { if (a < b) return a; return b; } double min(double a, double b) { if (a < b) return a; return b; } int max(int a, int b) { if (a > b) return a; return b; } int ABS(int a) { if (a < 0) return -a; return a; } int parent[100004], h[100005]; void make_set(int v) { parent[v] = v; } int find_set(int v) { if (v == parent[v]) return v; return parent[v] = find_set(parent[v]); } void union_sets(int a, int b) { a = find_set(a); b = find_set(b); if (a != b) { if (h[a] > h[b]) swap(a, b); parent[b] = a; } } pair<int, int> getCharHash(int p1, int p2, char c) { return make_pair(p1 * (c - a ), p2 * (c - a )); } vector<pair<int, int> > p; int double_area(int x1, int y1, int x2, int y2, int x3, int y3) { return (x1 - x2) * (y2 + y1) + (x2 - x3) * (y3 + y2) + (x3 - x1) * (y1 + y3); } int tree[4000000]; int c[1000004]; int pref_xors[1000004]; int next_pos[1000004]; int pref_unique_xors[1000006]; map<int, int> M; set<int> uniques; vector<pair<pair<int, int>, int> > q; vector<pair<int, int> > ans; int suf_sum(int l, int r, int nl, int nr, int node) { if (l == nl && r == nr) { return tree[node]; } int m = (nr + nl) / 2; if (r <= m) { return suf_sum(l, r, nl, m, node * 2); } if (l > m) { return suf_sum(l, r, m + 1, nr, node * 2 + 1); } return suf_sum(l, m, nl, m, node * 2) ^ suf_sum(m + 1, r, m + 1, nr, node * 2 + 1); } void update(int l, int r, int node, int pos, int value) { if (l == r) { tree[node] ^= value; return; } int m = (l + r) / 2; if (pos <= m) { update(l, m, node * 2, pos, value); } else { update(m + 1, r, node * 2 + 1, pos, value); } tree[node] = tree[node * 2] ^ tree[node * 2 + 1]; return; } int XOR(int i, int j) { if (i == 0) { return pref_xors[j]; } return pref_xors[j] ^ pref_xors[i - 1]; } int main() { int n; int p = 1; scanf( %d , &n); while (p <= n) p *= 2; for (int i = 0; i < n; ++i) { scanf( %d , c + i); if (i == 0) pref_xors[0] = c[0]; else pref_xors[i] = pref_xors[i - 1] ^ c[i]; } for (int i = n - 1; i >= 0; --i) { if (M[c[i]]) { next_pos[i] = M[c[i]]; } else { next_pos[i] = n; } M[c[i]] = i; } int m; scanf( %d , &m); int a, b; for (int i = 0; i < m; ++i) { scanf( %d%d , &a, &b); a--; b--; q.push_back(make_pair(make_pair(a, b), i)); } sort(q.begin(), q.end()); for (int i = q[0].first.first; i < n; ++i) { if (i == 0) { pref_unique_xors[0] = c[0]; uniques.insert(c[0]); } else { if (uniques.find(c[i]) != uniques.end()) { pref_unique_xors[i] = pref_unique_xors[i - 1]; } else { pref_unique_xors[i] = pref_unique_xors[i - 1] ^ c[i]; uniques.insert(c[i]); } } } int j = q[0].first.first; for (int i = 0; i < m; ++i) { a = q[i].first.first; b = q[i].first.second; if (a != j) { for (int k = j; k < a; ++k) { update(0, p - 1, 1, next_pos[k], c[k]); } j = a; } int answer = XOR(a, b) ^ pref_unique_xors[b] ^ suf_sum(b + 1, p - 1, 0, p - 1, 1); ans.push_back(make_pair(q[i].second, answer)); } sort(ans.begin(), ans.end()); for (int i = 0; i < m; ++i) { printf( %d n , ans[i].second); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__O221AI_FUNCTIONAL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o221ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
// Local signals
wire B2 or0_out ;
wire B2 or1_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; const int N = 200005; const int M = 400005; inline int read() { int x = 0, f = 1; char ch = getchar(); while (!isdigit(ch)) { if (ch == - ) f = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + ch - 0 ; ch = getchar(); } return f * x; } int n, m, q, num; int hd[N], nxt[M], to[M], tot; inline void add(int x, int y) { to[++tot] = y; nxt[tot] = hd[x]; hd[x] = tot; } int dfn[N], low[N], dfn_cnt; int st[N], tp; bool vis[N]; vector<int> G[N]; void tarjan(int x) { vis[x] = 1; st[++tp] = x; dfn[x] = low[x] = ++dfn_cnt; for (int i = hd[x]; i; i = nxt[i]) { int y = to[i]; if (!dfn[y]) { tarjan(y); low[x] = min(low[x], low[y]); if (low[y] == dfn[x]) { ++num; while (st[tp + 1] != y) { G[num].push_back(st[tp]); G[st[tp]].push_back(num); vis[st[tp--]] = 0; } G[num].push_back(x); G[x].push_back(num); } } else if (vis[y]) low[x] = min(low[x], dfn[y]); } } multiset<int> s[N]; int siz[N], fa[N], dep[N], son[N]; void dfs_son(int x, int f) { fa[x] = f; siz[x] = 1; dep[x] = dep[f] + 1; for (int i = 0; i < G[x].size(); i++) { int y = G[x][i]; if (y == f) continue; dfs_son(y, x); siz[x] += siz[y]; if (siz[y] > siz[son[x]]) son[x] = y; } } int rev[N], top[N]; void dfs_chain(int x, int tp) { top[x] = tp; dfn[x] = ++dfn_cnt; rev[dfn_cnt] = x; if (son[x]) dfs_chain(son[x], tp); for (int i = 0; i < G[x].size(); i++) { int y = G[x][i]; if (y == fa[x] || y == son[x]) continue; dfs_chain(y, y); } } int val[N << 2]; int w[N]; void build(int l, int r, int p) { if (l == r) { val[p] = w[rev[l]]; return; } build(l, ((l + r) >> 1), (p << 1)); build(((l + r) >> 1) + 1, r, (p << 1 | 1)); val[p] = min(val[(p << 1)], val[(p << 1 | 1)]); } void modify(int l, int r, int t, int v, int p) { if (l == r) { val[p] = v; return; } if (t <= ((l + r) >> 1)) modify(l, ((l + r) >> 1), t, v, (p << 1)); else modify(((l + r) >> 1) + 1, r, t, v, (p << 1 | 1)); val[p] = min(val[(p << 1)], val[(p << 1 | 1)]); } int query(int l, int r, int L, int R, int p) { if (L <= l && r <= R) return val[p]; int ans = 0x3f3f3f3f; if (L <= ((l + r) >> 1)) ans = min(ans, query(l, ((l + r) >> 1), L, R, (p << 1))); if (R > ((l + r) >> 1)) ans = min(ans, query(((l + r) >> 1) + 1, r, L, R, (p << 1 | 1))); return ans; } int get_min(int x, int y) { int ans = 0x3f3f3f3f; while (top[x] != top[y]) { if (dep[top[x]] < dep[top[y]]) swap(x, y); ans = min(ans, query(1, num, dfn[top[x]], dfn[x], 1)); x = fa[top[x]]; } if (dfn[x] > dfn[y]) swap(x, y); ans = min(ans, query(1, num, dfn[x], dfn[y], 1)); if (x > n) ans = min(ans, w[fa[x]]); return ans; } int main() { n = read(); m = read(); q = read(); for (int i = 1; i <= n; i++) w[i] = read(); num = n; for (int i = 1, x, y; i <= m; i++) { x = read(); y = read(); add(x, y), add(y, x); } tarjan(1); dfn_cnt = 0; dfs_son(1, 0); dfs_chain(1, 1); for (int i = 1; i <= n; i++) if (fa[i]) s[fa[i]].insert(w[i]); for (int i = n + 1; i <= num; i++) w[i] = *s[i].begin(); memset(val, 0x3f, sizeof(val)); build(1, num, 1); char op; int x, y; while (q--) { cin >> op; x = read(); y = read(); if (op == C ) { modify(1, num, dfn[x], y, 1); if (fa[x]) { s[fa[x]].erase(s[fa[x]].lower_bound(w[x])); s[fa[x]].insert(y); if (w[fa[x]] != *s[fa[x]].begin()) { w[fa[x]] = *s[fa[x]].begin(); modify(1, num, dfn[fa[x]], w[fa[x]], 1); } } w[x] = y; } else printf( %d n , get_min(x, y)); } return 0; } |
`default_nettype none
`timescale 1ns/100ps
module vga_controller(
input wire clock_ref, // 50 MHz
input wire reset,
input wire [2:0] iRGB,
output wire h_sync,
output wire v_sync,
output wire [8:0] row,
output wire [9:0] column,
output reg [2:0] oRGB
);
wire reset_h_counter, reset_v_counter;
wire enable_v_counter;
wire [9:0] h_counter;
wire [9:0] v_counter;
wire clock; // 25 MHz
UPCOUNTER_POSEDGE #(1) clock_divisor(
.Clock(clock_ref),
.Reset(reset),
.Initial(1'b1),
.Enable(1'b1),
.Q(clock)
);
UPCOUNTER_POSEDGE #(10) horizontal_counter(
.Clock(clock),
.Reset(reset_h_counter),
.Initial(10'b0),
.Enable(1'b1),
.Q(h_counter)
);
UPCOUNTER_POSEDGE #(10) vertical_counter(
.Clock(clock),
.Reset(reset_v_counter),
.Initial(10'b0),
.Enable(enable_v_counter),
.Q(v_counter)
);
assign reset_h_counter = reset | (h_counter == 10'd799);
assign reset_v_counter = reset | (v_counter == 10'd521); // 520 ó 521??
assign enable_v_counter = reset_h_counter;
assign h_sync = h_counter < 10'd96 ? 1'b0 : 1'b1;
assign v_sync = v_counter < 10'd2 ? 1'b0 : 1'b1;
assign row = (v_counter > 10'd11 & v_counter < 10'd491) ? (v_counter - 10'd11) : 10'b0 ;
assign column = (h_counter > 10'd143 & h_counter < 10'd783) ? (h_counter - 10'd143) : 10'b0 ;
always @ (posedge clock)
oRGB <= 3'b010;
endmodule |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; string s; cin >> s; long long n = s.length(); s = 1 + s; long long x[n + 1], y[n + 1], z[n + 1]; x[0] = 0; y[0] = 0; z[0] = 0; for (long long i = 1; i <= n; i++) { x[i] = x[i - 1]; y[i] = y[i - 1]; z[i] = z[i - 1]; if (s[i] == x ) x[i]++; if (s[i] == y ) y[i]++; if (s[i] == z ) z[i]++; } long long m; cin >> m; for (long long i = 0; i < m; i++) { long long l, r; cin >> l >> r; long long len = r - l + 1; long long cx = x[r] - x[l - 1]; long long cy = y[r] - y[l - 1]; long long cz = z[r] - z[l - 1]; if (len < 3) { cout << YES << n ; continue; } if (abs(cx - cy) > 1 || abs(cx - cz) > 1 || abs(cz - cy) > 1) cout << NO << n ; else cout << YES << n ; } } |
#include <bits/stdc++.h> int main() { int n, m, t; scanf( %d %d , &n, &m); t = (n / 2); t -= (t & 1); for (int i = 1; i < n; i++) { if (i == 1) printf( > ); else printf( ^ ); if (i & 1) { for (int j = 2; j <= (n - t < n - 2 ? n - t : n - 2); j++) printf( > ); for (int j = n - t + 1; j < n - 2; j += 2) printf( .> ); printf( .v ); } else { printf( v. ); for (int j = 4; j <= 3 + t; j += 2) printf( .< ); for (int j = 3 + t + 1; j <= n; j++) printf( < ); } printf( n ); } printf( ^<< ); for (int j = 4; j <= 3 + t; j += 2) printf( .< ); for (int j = 3 + t + 1; j <= n; j++) printf( < ); printf( n1 1 n ); return 0; } |
///////////////// ** iodelay_incrementor ** //////////////////////////////////////////
//
// This module is clocked at 40MHz. It waits for a trigger pulse synchronous to 40Mhz,
// at which point it counts up to the spec_delay input in units of 40MHz using its
// internal 6 bit counter. During this time, it outputs an inc_en strobe which is to be
// connected to an idelay element's ce. In this way, the idelay's tap is set to the value
// of spec_delay. The module exposes the counter value as actual_delay for debugging/monitoring
//
// Notes: This element must be reset together with its associated idelay!!!!!
// The 6-bit counter will wrap around with the idelay's 6-bit tap count
//
module iodelay_incrementor(
input clk40,
input rst,
input count_trig,
input [5:0] spec_delay,
output reg inc_en,
output reg [5:0] actual_delay
);
always @(posedge clk40) begin
if (rst) begin
inc_en <= 0;
actual_delay <= 0;
end else begin
if (inc_en) begin
//Triggered
if (actual_delay == spec_delay) begin
inc_en <= 0;
end else begin
actual_delay <= actual_delay + 1;
end
end else begin
if (count_trig) begin
//Trigger idelay count
inc_en <= 1;
end
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int p[200005], q[200005]; int fa[200005], top[200005], sz[200005], dep[200005]; vector<int> E[200005]; void dfs1(int root); void dfs2(int root, int toproot); int lca(int node1, int node2); int dis(int node1, int node2); pair<int, int> merge(int node1, int node2, int node3); pair<int, int> merge(pair<int, int> path1, pair<int, int> path2); void modify(int index, int lboundary, int rboundary, int position, pair<int, int> path); int query(int index, int lboundary, int rboundary, pair<int, int> path); pair<int, int> tr[4 * 200005]; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , p + i), q[p[i]] = i; for (int i = 2; i <= n; i++) scanf( %d , fa + i); for (int i = 2; i <= n; i++) { E[i].push_back(fa[i]); E[fa[i]].push_back(i); } dfs1(1); dfs2(1, 1); int k; scanf( %d , &k); for (int i = 1; i <= n; i++) { modify(1, 0, n - 1, p[i], make_pair(q[p[i]], q[p[i]])); } while (k--) { int t, u, v; scanf( %d , &t); if (t == 1) { scanf( %d %d , &u, &v); swap(p[u], p[v]); swap(q[p[u]], q[p[v]]); modify(1, 0, n - 1, p[u], make_pair(q[p[u]], q[p[u]])); modify(1, 0, n - 1, p[v], make_pair(q[p[v]], q[p[v]])); } else if (t == 2) { if (tr[1].first) cout << n << endl; else cout << query(1, 0, n - 1, make_pair(q[0], q[0])) << endl; } } } void dfs1(int r) { sz[r] = 1; for (int u : E[r]) if (u != fa[r]) { dfs1(u); sz[r] += sz[u]; } } void dfs2(int r, int t) { top[r] = t; dep[r] = dep[fa[r]] + 1; int tid = -1, msz = 0; for (int u : E[r]) if (u != fa[r] && sz[u] > msz) { msz = sz[u]; tid = u; } if (tid == -1) return; dfs2(tid, t); for (int u : E[r]) if (u != fa[r] && u != tid) dfs2(u, u); } int lca(int a, int b) { while (top[a] != top[b]) { if (dep[top[a]] < dep[top[b]]) swap(a, b); a = fa[top[a]]; } return dep[a] < dep[b] ? a : b; } int dis(int a, int b) { return dep[a] + dep[b] - 2 * dep[lca(a, b)]; } pair<int, int> merge(int a, int b, int c) { int ab = dis(a, b), ac = dis(a, c), bc = dis(b, c); if (ab == bc + ac) return make_pair(a, b); else if (ac == ab + bc) return make_pair(a, c); else if (bc == ab + ac) return make_pair(b, c); else return make_pair(0, 0); } pair<int, int> merge(pair<int, int> a, pair<int, int> b) { if (!a.first || !b.first) return make_pair(0, 0); pair<int, int> tmp = merge(a.first, a.second, b.first); if (tmp.first) tmp = merge(tmp.first, tmp.second, b.second); return tmp; } void modify(int o, int l, int r, int p, pair<int, int> v) { if (l == r) { tr[o] = v; return; } int mid = (l + r) >> 1; if (p <= mid) modify((o << 1), l, mid, p, v); else modify((o << 1 | 1), mid + 1, r, p, v); tr[o] = merge(tr[(o << 1)], tr[(o << 1 | 1)]); } int query(int o, int l, int r, pair<int, int> p) { if (l == r) return l; int mid = (l + r) >> 1; pair<int, int> q = merge(p, tr[(o << 1)]); if (!q.first) return query((o << 1), l, mid, p); else return query((o << 1 | 1), mid + 1, r, q); } |
#include <bits/stdc++.h> using namespace std; inline void read(int &x) { x = 0; int f = 1; char ch = getchar(); while (ch != 45 && (ch > 9 || ch < 0 )) ch = getchar(); if (ch == 45) { f = -1, ch = getchar(); } while (ch <= 9 && ch >= 0 ) { x = x * 10 + ch - 48; ch = getchar(); } x *= f; } int i, j, k, n, s, t, m, flag = 1, ans; const int N = 2e5 + 10, mod = 1e9 + 7; int fa[N], e[N][3], col[N], p[N], type[N]; int find(int x) { if (x == fa[x]) return x; return fa[x] = find(fa[x]); } void merge(int u, int v) { u = find(u), v = find(v); if (v > u) swap(u, v); if (u == v) return; fa[u] = v; } signed main() { memset(type, -1, sizeof(type)); read(n), read(m); for (i = 1; i <= n; i++) fa[i] = i, fa[i + n] = i + n; for (i = 1; i <= m; i++) { read(e[i][1]), read(e[i][2]), read(col[i]); if (e[i][1] > e[i][2]) swap(e[i][1], e[i][2]); if (e[i][1] == 1) { type[e[i][2]] = col[i]; continue; } if (col[i] == 1) merge(e[i][1], e[i][2]), merge(e[i][1] + n, e[i][2] + n); else merge(e[i][1], e[i][2] + n), merge(e[i][1] + n, e[i][2]); } for (i = 1; i <= n; i++) { if (type[i] == -1) continue; if (type[find(i + n)] == -1) type[find(i + n)] = type[i] ^ 1; if (type[find(i + n)] == type[i]) flag = 0; if (type[find(i)] == -1) type[find(i)] = type[i]; if (type[find(i)] != type[i]) flag = 0; } for (i = 1; i <= n; i++) { if (find(i) == find(i + n)) flag = 0; } for (i = 2; i <= n; i++) { if (find(i) != i) continue; ans++; if (type[find(i + n)] != -1 || type[i] != -1) ans--; type[i] = 1; } if (flag == 0) { printf( 0 n ); return 0; } int now = 1; for (i = 1; i <= ans; i++) now = now * 2 % mod; cout << now << endl; return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:module_ref:frequency_analyzer_manager:1.0
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_frequency_analyzer_manager_0_1 (
data,
pixel_clock,
start,
stop,
clear,
irq,
s00_axi_aclk,
s00_axi_aresetn,
s00_axi_awaddr,
s00_axi_awprot,
s00_axi_awvalid,
s00_axi_awready,
s00_axi_wdata,
s00_axi_wstrb,
s00_axi_wvalid,
s00_axi_wready,
s00_axi_bresp,
s00_axi_bvalid,
s00_axi_bready,
s00_axi_araddr,
s00_axi_arprot,
s00_axi_arvalid,
s00_axi_arready,
s00_axi_rdata,
s00_axi_rresp,
s00_axi_rvalid,
s00_axi_rready
);
input wire [7 : 0] data;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 pixel_clock CLK" *)
input wire pixel_clock;
input wire start;
input wire stop;
input wire clear;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 irq INTERRUPT" *)
output wire irq;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK" *)
input wire s00_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST" *)
input wire s00_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWADDR" *)
input wire [3 : 0] s00_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWPROT" *)
input wire [2 : 0] s00_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWVALID" *)
input wire s00_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi AWREADY" *)
output wire s00_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WDATA" *)
input wire [31 : 0] s00_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WSTRB" *)
input wire [3 : 0] s00_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WVALID" *)
input wire s00_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi WREADY" *)
output wire s00_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BRESP" *)
output wire [1 : 0] s00_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BVALID" *)
output wire s00_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi BREADY" *)
input wire s00_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARADDR" *)
input wire [3 : 0] s00_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARPROT" *)
input wire [2 : 0] s00_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARVALID" *)
input wire s00_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi ARREADY" *)
output wire s00_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RDATA" *)
output wire [31 : 0] s00_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RRESP" *)
output wire [1 : 0] s00_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RVALID" *)
output wire s00_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s00_axi RREADY" *)
input wire s00_axi_rready;
frequency_analyzer_manager #(
.C_S00_AXI_DATA_WIDTH(32),
.C_S00_AXI_ADDR_WIDTH(4)
) inst (
.data(data),
.pixel_clock(pixel_clock),
.start(start),
.stop(stop),
.clear(clear),
.irq(irq),
.s00_axi_aclk(s00_axi_aclk),
.s00_axi_aresetn(s00_axi_aresetn),
.s00_axi_awaddr(s00_axi_awaddr),
.s00_axi_awprot(s00_axi_awprot),
.s00_axi_awvalid(s00_axi_awvalid),
.s00_axi_awready(s00_axi_awready),
.s00_axi_wdata(s00_axi_wdata),
.s00_axi_wstrb(s00_axi_wstrb),
.s00_axi_wvalid(s00_axi_wvalid),
.s00_axi_wready(s00_axi_wready),
.s00_axi_bresp(s00_axi_bresp),
.s00_axi_bvalid(s00_axi_bvalid),
.s00_axi_bready(s00_axi_bready),
.s00_axi_araddr(s00_axi_araddr),
.s00_axi_arprot(s00_axi_arprot),
.s00_axi_arvalid(s00_axi_arvalid),
.s00_axi_arready(s00_axi_arready),
.s00_axi_rdata(s00_axi_rdata),
.s00_axi_rresp(s00_axi_rresp),
.s00_axi_rvalid(s00_axi_rvalid),
.s00_axi_rready(s00_axi_rready)
);
endmodule
|
// From: "Ma, Zhenqiang" <>
module test (
// Ports for module A
input i_A_outsidei,
output o_A_outsideo,
// Ports for module B
input i_B_outsidei,
output o_B_outsideo );
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire A_internal; // From u0 of moduleA.v
wire B_internal; // From u1 of moduleB.v
// End of automatics
//-----------------------------------------------------------------------------
// instantiate module A
//-----------------------------------------------------------------------------
/* moduleA AUTO_TEMPLATE (
.[iot]_\(.*\) (@"(vl-prefix-i-o \\"\1\\")"\1[]),
); */
moduleA u0(
/*AUTOINST*/
// Outputs
.o_A_outsideo (o_A_outsideo), // Templated
.o_A_internal (A_internal), // Templated
// Inputs
.i_A_outsidei (i_A_outsidei), // Templated
.i_B_internal (B_internal)); // Templated
//-----------------------------------------------------------------------------
// instantiate module B
//-----------------------------------------------------------------------------
/* moduleB AUTO_TEMPLATE (
.[iot]_\(.*\) (@"(vl-prefix-i-o \\"\1\\")"\1[]),
); */
moduleB u1(
/*AUTOINST*/
// Outputs
.o_B_outsideo (o_B_outsideo), // Templated
.o_B_internal (B_internal), // Templated
// Inputs
.i_B_outsidei (i_B_outsidei), // Templated
.i_A_internal (A_internal)); // Templated
endmodule
module moduleA (
input i_A_outsidei,
output o_A_outsideo,
input i_B_internal,
output o_A_internal
);
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire o_A_internal = 1'h0;
wire o_A_outsideo = 1'h0;
// End of automatics
endmodule
module moduleB (
input i_B_outsidei,
output o_B_outsideo,
input i_A_internal,
output o_B_internal
);
/*AUTOTIEOFF*/
// Beginning of automatic tieoffs (for this module's unterminated outputs)
wire o_B_internal = 1'h0;
wire o_B_outsideo = 1'h0;
// End of automatics
endmodule
/*
Local Variables:
eval:
(defun vl-prefix-i-o (basename)
(cond ((assoc (concat "i_" basename)
(verilog-decls-get-inputs moddecls))
"i_")
((assoc (concat "o_" basename)
(verilog-decls-get-outputs moddecls))
"o_")
((assoc (concat "t_" basename)
(verilog-decls-get-inouts moddecls))
"t_")
(t "")))
End:
*/
|
#include <bits/stdc++.h> using namespace std; int a[5]; int main() { scanf( %d%d%d%d , &a[0], &a[1], &a[2], &a[3]); while (a[0] != 1 || a[1] != 1 || a[2] != 1 || a[3] != 1) { bool f = 1; for (int i = 0; i < 4; i++) if (a[i] % 2 == 0 && a[(i + 1) % 4] % 2 == 0) { printf( /%d n , i + 1); a[i] >>= 1; a[(i + 1) % 4] >>= 1; f = 0; break; } if (f) { for (int i = 0; i < 4; i++) if (a[i] % 2 == 1 && a[(i + 1) % 4] % 2 == 1 && !(a[i] == 1 && a[(i + 1) % 4] == 1)) { a[i]++; a[(i + 1) % 4]++; printf( +%d n , i + 1); f = 0; break; } if (f) for (int i = 0; i < 4; i++) if (a[i] % 2 == 1 && a[(i + 1) % 4] % 2 == 0 && a[(i + 2) % 4] % 2 == 1) { printf( +%d n+%d n , i + 1, (i + 1) % 4 + 1); a[i]++; a[(i + 2) % 4]++; a[(i + 1) % 4] += 2; break; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MN = 1000111; int n; pair<int, int> a[MN], b[MN]; int main() { ios ::sync_with_stdio(0); cin.tie(0); while (scanf( %d , &n) == 1) { for (int i = (1), _b = (n); i <= _b; ++i) { scanf( %d , &a[i].first); a[i].second = i; } for (int i = (1), _b = (n); i <= _b; ++i) { scanf( %d , &b[i].first); b[i].second = i; } try { while (true) { map<int, pair<int, int> > id; id[0] = make_pair(0, 0); int ia = 0, ib = 0; int diff = 0; while (ia < n || ib < n) { if (ia == n) { diff -= b[++ib].first; } else if (ib == n) { diff += a[++ia].first; } else if (diff <= 0) { diff += a[++ia].first; } else { diff -= b[++ib].first; } if (id.count(diff)) { int ja = id[diff].first; int jb = id[diff].second; printf( %d n , ia - ja); for (int x = (ja + 1), _b = (ia); x <= _b; ++x) printf( %d , a[x].second); puts( ); printf( %d n , ib - jb); for (int x = (jb + 1), _b = (ib); x <= _b; ++x) printf( %d , b[x].second); puts( ); puts( ); throw 1; } id[diff] = make_pair(ia, ib); } throw 2; random_shuffle(a + 1, a + n + 1); random_shuffle(b + 1, b + n + 1); } } catch (int e) { } } } |
#include <bits/stdc++.h> using namespace std; string str[1005]; int tim[1005][1005]; int n, m, t; int fx[] = {-1, +1, 0, 0}; int fy[] = {0, 0, -1, +1}; vector<pair<int, int> > cur; bool okay(int x, int y) { return (x >= 0 && x < n && y >= 0 && y < m); } void dfs(int x, int y, int curr) { tim[x][y] = curr; cur.push_back(make_pair(x, y)); for (int k = 0; k < 4; k++) { int tx = x + fx[k]; int ty = y + fy[k]; if (okay(tx, ty) == false || tim[tx][ty] != -1 || str[tx][ty] != str[x][y]) continue; dfs(tx, ty, curr); } } char alt(char x) { if (x == 0 ) return 1 ; else return 0 ; } char query(int x, int y, long long curr) { if (tim[x][y] == -1) return str[x][y]; long long diff = curr - 1LL * tim[x][y]; if (diff % 2LL == 1LL) return alt(str[x][y]); else return str[x][y]; } int main() { scanf( %d %d %d , &n, &m, &t); for (int i = 0; i < n; i++) { cin >> str[i]; } memset(tim, -1, sizeof tim); vector<pair<int, int> > last; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) last.push_back(make_pair(i, j)); } for (int curTim = 0; curTim <= n * m; curTim++) { for (int i = 0; i < last.size(); i++) { int x = last[i].first, y = last[i].second; char col = query(x, y, curTim); for (int k = 0; k < 4; k++) { int tx = x + fx[k]; int ty = y + fy[k]; if (okay(tx, ty) == false || tim[tx][ty] != -1 || str[tx][ty] != col) continue; dfs(tx, ty, curTim); } } last = cur; cur.clear(); if (last.empty()) break; } while (t--) { int x, y; long long q; scanf( %d %d %lld , &x, &y, &q); x--, y--; char ans = query(x, y, q); cout << ans << endl; } } |
`define STATE_IDLE 4'h0
`define STATE_START_BIT 4'h1
`define STATE_BIT_0 4'h2
`define STATE_BIT_1 4'h3
`define STATE_BIT_2 4'h4
`define STATE_BIT_3 4'h5
`define STATE_BIT_4 4'h6
`define STATE_BIT_5 4'h7
`define STATE_BIT_6 4'h8
`define STATE_BIT_7 4'h9
`define STATE_STOP_BIT 4'ha
`define STATE_STOPPED 4'hb
module uart(
input clk,
input reset,
input [7:0] data,
input dataReady,
output reg busy,
output reg tx);
parameter CLK_FREQ = 50000000;
parameter BAUD = 9600;
parameter BAUD_GEN_ACC_WIDTH = 16;
parameter BAUD_GEN_INC = ((BAUD << (BAUD_GEN_ACC_WIDTH - 4)) + (CLK_FREQ >> 5)) / (CLK_FREQ >> 4);
reg [BAUD_GEN_ACC_WIDTH:0] baudGenAcc;
always @(posedge clk or posedge reset)
if (reset)
baudGenAcc <= 0;
else
baudGenAcc <= baudGenAcc[BAUD_GEN_ACC_WIDTH - 1 : 0] + BAUD_GEN_INC;
wire baudClk = baudGenAcc[BAUD_GEN_ACC_WIDTH];
reg [3:0] state;
reg [7:0] dataBuf;
always @(posedge clk or posedge reset)
if (reset) begin
state <= `STATE_IDLE;
end else
case (state)
`STATE_IDLE:
if (dataReady) begin
state <= `STATE_START_BIT;
dataBuf <= data;
end
`STATE_START_BIT: if (baudClk) state <= `STATE_BIT_0;
`STATE_BIT_0: if (baudClk) state <= `STATE_BIT_1;
`STATE_BIT_1: if (baudClk) state <= `STATE_BIT_2;
`STATE_BIT_2: if (baudClk) state <= `STATE_BIT_3;
`STATE_BIT_3: if (baudClk) state <= `STATE_BIT_4;
`STATE_BIT_4: if (baudClk) state <= `STATE_BIT_5;
`STATE_BIT_5: if (baudClk) state <= `STATE_BIT_6;
`STATE_BIT_6: if (baudClk) state <= `STATE_BIT_7;
`STATE_BIT_7: if (baudClk) state <= `STATE_STOP_BIT;
`STATE_STOP_BIT: if (baudClk) state <= `STATE_IDLE;
default: if(baudClk) state <= `STATE_STOPPED;
endcase
always @(state or dataBuf)
case (state)
`STATE_START_BIT: tx <= 0;
`STATE_BIT_0: tx <= dataBuf[0];
`STATE_BIT_1: tx <= dataBuf[1];
`STATE_BIT_2: tx <= dataBuf[2];
`STATE_BIT_3: tx <= dataBuf[3];
`STATE_BIT_4: tx <= dataBuf[4];
`STATE_BIT_5: tx <= dataBuf[5];
`STATE_BIT_6: tx <= dataBuf[6];
`STATE_BIT_7: tx <= dataBuf[7];
default: tx <= 1;
endcase
always @(state)
case (state)
`STATE_IDLE: busy <= 0;
`STATE_STOPPED: busy <= 0;
default: busy <= 1;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; int L = 1; int R = 0; int cnt[300005]; int a[300005]; int big[300005][2]; int is1 = 0; int ap[300005]; vector<int> st; void in(int id) { id = a[id]; if (++cnt[id] == 1) is1++; else if (cnt[id] == 2) is1--; } void out(int id) { id = a[id]; if (--cnt[id] == 1) is1++; else if (cnt[id] == 0) is1--; } void update(int l, int r) { while (R < r) in(++R); while (L > l) in(--L); while (L < l) out(L++); while (R > r) out(R--); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; a[0] = n + 1; a[n + 1] = n + 1; int res = 0; st.push_back(n + 1); for (int i = 1; i <= n; i++) { cin >> a[i]; while (st.back() < a[i]) st.pop_back(); big[i][0] = ap[st.back()]; st.push_back(a[i]); ap[a[i]] = i; } st.clear(); st.push_back(n + 1); ap[n + 1] = n + 1; for (int i = n; i >= 1; i--) { while (st.back() < a[i]) st.pop_back(); big[i][1] = ap[st.back()]; st.push_back(a[i]); ap[a[i]] = i; } for (int i = 1; i <= n; i++) { int l = max(i - a[i] + 1, big[i][0] + 1); int r = min(l + a[i] - 1, big[i][1] - 1); if (l + a[i] - 1 != r) continue; for (; l <= i; l++) { update(l, r); if (is1 == a[i]) res++; if (++r == big[i][1]) break; } } cout << res; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__udp_dff$PR_pp$PG$N (
Q ,
D ,
CLK ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_tfifo.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core transmitter FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - ////
//// - Jacob Gorban ////
//// - Igor Mohor () ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// Modified for use in the ZAP project by Revanth Kamaraj ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
`include "uart_defines.v"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 1'b0;
count <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 1'b0;
count <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= top_plus_1;
count <= count + 1'b1;
end
2'b01 : if(count>0)
begin
bottom <= bottom + 1'b1;
count <= count - 1'b1;
end
2'b11 : begin
bottom <= bottom + 1'b1;
top <= top_plus_1;
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & (count==fifo_depth))
overrun <= 1'b1;
end // always
endmodule
|
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_sp
#(
parameter DWIDTH=8,
parameter AWIDTH=12,
parameter CONTENT="./memory.mif"
) (
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
input tri1 clock,
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
input wire wren,
input wire [AWIDTH-1:0] address,
input wire [DWIDTH-1:0] data,
output wire [DWIDTH-1:0] q
);
altsyncram altsyncram_component
(
.address_a ( address ),
.clock0 ( clock ),
.data_a ( data ),
.wren_a ( wren ),
.q_a ( q ),
.aclr0 ( 1'b0 ),
.aclr1 ( 1'b0 ),
.address_b ( 1'b1 ),
.addressstall_a ( 1'b0 ),
.addressstall_b ( 1'b0 ),
.byteena_a ( 1'b1 ),
.byteena_b ( 1'b1 ),
.clock1 ( 1'b1 ),
.clocken0 ( 1'b1 ),
.clocken1 ( 1'b1 ),
.clocken2 ( 1'b1 ),
.clocken3 ( 1'b1 ),
.data_b ( 1'b1 ),
.rden_a ( 1'b1 ),
.rden_b ( 1'b1 ),
.wren_b ( 1'b0 )
);
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = CONTENT,
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2**AWIDTH,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = AWIDTH,
altsyncram_component.width_a = DWIDTH,
altsyncram_component.width_byteena_a = 1;
endmodule
|
#include <bits/stdc++.h> using namespace std; int solve() { int N; cin >> N; if (N % 2) { N -= 9; if (N < 0 || N == 2) return -1; return 1 + N / 4; } else { if (N < 4) return -1; return N / 4; } } int main() { int Q; cin >> Q; while (Q--) cout << solve() << endl; return 0; } |
// cog_ram
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module cog_ram
(
input clk,
input ena,
input w,
input [8:0] a,
input [31:0] d,
output reg [31:0] q
);
// 512 x 32 ram
reg [511:0] [31:0] r;
always @(posedge clk)
begin
if (ena && w)
r[a] <= d;
if (ena)
q <= r[a];
end
endmodule
|
#include <bits/stdc++.h> using namespace std; struct debugger { template <typename T> debugger& operator,(const T& v) { cerr << v << ; return *this; } } debug; template <typename T1, typename T2> inline ostream& operator<<(ostream& os, const pair<T1, T2>& p) { return os << ( << p.first << , << p.second << ) ; } template <typename T> inline ostream& operator<<(ostream& os, const vector<T>& v) { bool first = true; os << [ ; for (typename vector<T>::const_iterator ii = v.begin(); ii != v.end(); ++ii) { if (!first) os << , ; os << *ii; first = false; } return os << ] ; } const int NN = (1 << 18); int seg[NN], dp[NN]; int od[NN], ans[NN]; bool vowel(char ch) { ch = tolower(ch); if (ch == a or ch == e or ch == i or ch == o or ch == u ) return true; return false; } bool cmp(int x, int y) { if (dp[x] == dp[y]) return (x < y); return (dp[x] < dp[y]); } void update(int i, int v) { for (i += 5; i < NN; i += i & -i) seg[i] += v; } int findcum(int cum) { int id = 0, bitmask = NN >> 1; while (bitmask != 0) { int tid = id + bitmask; if (seg[tid] < cum) cum -= seg[tid], id = tid; bitmask >>= 1; } return id + 1 - 5; } void solve() { string msg; cin >> msg; int n = (int)msg.size(); dp[0] = od[0] = 0; for (int i = 1; i <= n; ++i) dp[i] = dp[i - 1] + ((vowel(msg[i - 1])) ? -1 : 2), od[i] = i; sort(od, od + n + 1, cmp); int res = numeric_limits<int>::min(); for (int i = 0; i <= n; ++i) { update(od[i], 1); int id = findcum(1); if (id < od[i]) res = max(res, od[i] - id), ++ans[od[i] - id]; } if (res <= 0) puts( No solution ); else cout << res << << ans[res] << endl; } int main() { ios_base::sync_with_stdio(0); solve(); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkinvlp (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINVLP_FUNCTIONAL_V |
`include "senior_defines.vh"
module program_counter
#(parameter nat_w = `SENIOR_NATIVE_WIDTH)
(
input wire clk_i,
input wire reset_i,
input wire [nat_w-1:0] ise_i,
input wire [nat_w-1:0] lc_pc_loopb_i,
input wire [nat_w-1:0] ta_i,
input wire pfc_pcadd_opa_sel_i,
input wire [2:0] pfc_pc_sel_i,
input wire [nat_w-1:0] stack_address_i,
output wire [nat_w-1:0] pc_addr_bus_o
);
`include "std_messages.vh"
// Internal Declarations
reg [nat_w-1:0] pc_op_add_sig;
reg [nat_w-1:0] pc_addr_sig;
reg [nat_w-1:0] pc_addr_reg;
assign pc_addr_bus_o=pc_addr_sig;
// compute the next PC
// mux for OPA adder
always @(*) begin
case (pfc_pcadd_opa_sel_i)
1'b0: pc_op_add_sig={15'd0,1'b1};
1'b1: pc_op_add_sig= 16'b1111111111111111;
endcase
end
// mux for selecting operation on PC value
always @(*) begin
case (pfc_pc_sel_i)
3'b000: pc_addr_sig=pc_addr_reg;
3'b001: pc_addr_sig=pc_addr_reg+pc_op_add_sig;
3'b010: pc_addr_sig=16'd0;
3'b011: pc_addr_sig=ta_i;
3'b100: pc_addr_sig=lc_pc_loopb_i;
3'b101: pc_addr_sig=ise_i;
3'b110: pc_addr_sig=stack_address_i;
default: begin
pc_addr_sig=0;
if(defined_but_illegal(pfc_pc_sel_i,3,"pfc_pc_sel_i")) begin
$stop;
end
end
endcase
end
// register the PC value
always @(posedge clk_i) begin
if (!reset_i) begin
pc_addr_reg<=0;
end
else begin
pc_addr_reg<=pc_addr_sig;
end
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
module RCB_FRL_fifo_MSG(ALMOSTEMPTY, ALMOSTFULL, DO, EMPTY, FULL, DI, RDCLK, RDEN, WRCLK, WREN, RST);
output ALMOSTEMPTY, ALMOSTFULL, EMPTY, FULL;
output [39:0] DO;
input [39:0] DI;
input RDCLK, RDEN, WRCLK, WREN, RST;
wire [63:40] zero;
FIFO36_72 #(
.ALMOST_FULL_OFFSET(9'h080), // Sets almost full threshold
.ALMOST_EMPTY_OFFSET(9'h080), // Sets the almost empty threshold
.DO_REG(1), // Enable output register (0 or 1)
// Must be 1 if EN_SYN = "FALSE"
.EN_ECC_READ("FALSE"), // Enable ECC decoder, "TRUE" or "FALSE"
.EN_ECC_WRITE("FALSE"), // Enable ECC encoder, "TRUE" or "FALSE"
.EN_SYN("FALSE"), // Specifies FIFO as Asynchronous ("FALSE")
// or Synchronous ("TRUE")
.FIRST_WORD_FALL_THROUGH("FALSE") // Sets the FIFO FWFT to "TRUE" or "FALSE"
) FIFO36_72_inst (
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
.DBITERR(), // 1-bit double bit error status output
.DO({zero[63:40],DO[39:0]}), // 32-bit data output
.DOP(), // 4-bit parity data output
.ECCPARITY(), // 8-bit generated error correction parity
.EMPTY(EMPTY), // 1-bit empty output flag
.FULL(FULL), // 1-bit full output flag
.RDCOUNT(), // 9-bit read count output
.RDERR(), // 1-bit read error output
.SBITERR(), // 1-bit single bit error status output
.WRCOUNT(), // 9-bit write count output
.WRERR(), // 1-bit write error
.DI({24'h000,DI}), // 32-bit data input
.DIP(), // 4-bit parity input
.RDCLK(RDCLK), // 1-bit read clock input
.RDEN(RDEN), // 1-bit read enable input
.RST(RST), // 1-bit reset input
.WRCLK(WRCLK), // 1-bit write clock input
.WREN(WREN) // 1-bit write enable input
);
endmodule
|
`include "project_defines.v"
`timescale 1ps / 1ps
module rgb_vga_generator #(
parameter CLOCK_RATE = 100
)(
input clk, // 100MHz system clock signal
input rst, // reset signal
//Generated Signals to Drive Display
output [9:0] o_image_width,
output [9:0] o_image_height,
output o_vsync,
output o_hsync,
output [2:0] o_r_out, // vga red signal
output [2:0] o_g_out, // vga green signal
output [1:0] o_b_out, // vga blue signal
//From the below control signal, the PPU returns this value
input [5:0] i_sys_palette_idx_in, // system palette index (selects output color)
//X, Y, Y Next, pixel clock and a vblank
output [9:0] o_nes_x_out, // nes x coordinate
output [9:0] o_nes_y_out, // nes y coordinate
output [9:0] o_nes_y_next_out, // next line's nes y coordinate
output reg o_pix_pulse_out, // 1 clk pulse prior to o_nes_x update
output o_vblank // indicates a vblank is occuring (no PPU vram access)
);
//local parameters
// NES screen dimensions (256x240).
localparam FRAME_WIDTH = 400;
localparam FRAME_HEIGHT = 260;
//localparam FRAME_HEIGHT = 3;
localparam VBLANK_START_X = 365;
localparam VBLANK_START_Y = 238;
localparam VBLANK_END_X = 32;
localparam VBLANK_END_Y = 259;
localparam X_FRONT_PORCH = 32;
localparam X_FRONT_PORCH = 32;
localparam IMAGE_Y_FP = 0; //XXX: This doesn't work when IMAGE_Y_FP > 0
localparam IMAGE_Y_BP = 0;
localparam IMAGE_WIDTH = 256;
localparam IMAGE_HEIGHT = 240;
//localparam IMAGE_HEIGHT = 2;
localparam FPS = 60;
localparam CLK_DIV = CLOCK_RATE / (FPS * FRAME_WIDTH * FRAME_HEIGHT);
//localparam VBLANK_TIMEOUT = `CLOCK_RATE / FPS;
reg [8:0] r_x_pos;
reg [8:0] r_y_pos;
reg [7:0] r_rgb;
wire [8:0] w_x_pos;
wire [8:0] w_y_pos;
wire [31:0] w_clk_div = CLK_DIV;
reg [7:0] r_clk_div_count;
//Submodules
//Asynchronous Logic
assign o_r_out = r_rgb[7:5];
assign o_g_out = r_rgb[4:2];
assign o_b_out = r_rgb[1:0];
//synchronous logic
always @ (posedge clk) begin
if (rst) begin
r_clk_div_count <= 4;
o_pix_pulse_out <= 0;
end
else begin
//Stobe
o_pix_pulse_out <= 0;
if (r_clk_div_count < w_clk_div - 1) begin
r_clk_div_count <= r_clk_div_count + 1;
end
else begin
r_clk_div_count <= 0;
o_pix_pulse_out <= 1;
end
end
end
always @ (*) begin
if (o_hsync == 0) begin
r_rgb = 0;
end
else begin
// Lookup RGB values based on sys_palette_idx. Table is an approximation of the NES
// system palette. Taken from http://nesdev.parodius.com/NESTechFAQ.htm#nessnescompat.
case (i_sys_palette_idx_in)
6'h00: r_rgb = { 3'h3, 3'h3, 2'h1 };
6'h01: r_rgb = { 3'h1, 3'h0, 2'h2 };
6'h02: r_rgb = { 3'h0, 3'h0, 2'h2 };
6'h03: r_rgb = { 3'h2, 3'h0, 2'h2 };
6'h04: r_rgb = { 3'h4, 3'h0, 2'h1 };
6'h05: r_rgb = { 3'h5, 3'h0, 2'h0 };
6'h06: r_rgb = { 3'h5, 3'h0, 2'h0 };
6'h07: r_rgb = { 3'h3, 3'h0, 2'h0 };
6'h08: r_rgb = { 3'h2, 3'h1, 2'h0 };
6'h09: r_rgb = { 3'h0, 3'h2, 2'h0 };
6'h0a: r_rgb = { 3'h0, 3'h2, 2'h0 };
6'h0b: r_rgb = { 3'h0, 3'h1, 2'h0 };
6'h0c: r_rgb = { 3'h0, 3'h1, 2'h1 };
6'h0d: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h0e: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h0f: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h10: r_rgb = { 3'h5, 3'h5, 2'h2 };
6'h11: r_rgb = { 3'h0, 3'h3, 2'h3 };
6'h12: r_rgb = { 3'h1, 3'h1, 2'h3 };
6'h13: r_rgb = { 3'h4, 3'h0, 2'h3 };
6'h14: r_rgb = { 3'h5, 3'h0, 2'h2 };
6'h15: r_rgb = { 3'h7, 3'h0, 2'h1 };
6'h16: r_rgb = { 3'h6, 3'h1, 2'h0 };
6'h17: r_rgb = { 3'h6, 3'h2, 2'h0 };
6'h18: r_rgb = { 3'h4, 3'h3, 2'h0 };
6'h19: r_rgb = { 3'h0, 3'h4, 2'h0 };
6'h1a: r_rgb = { 3'h0, 3'h5, 2'h0 };
6'h1b: r_rgb = { 3'h0, 3'h4, 2'h0 };
6'h1c: r_rgb = { 3'h0, 3'h4, 2'h2 };
6'h1d: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h1e: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h1f: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h20: r_rgb = { 3'h7, 3'h7, 2'h3 };
6'h21: r_rgb = { 3'h1, 3'h5, 2'h3 };
6'h22: r_rgb = { 3'h2, 3'h4, 2'h3 };
6'h23: r_rgb = { 3'h5, 3'h4, 2'h3 };
6'h24: r_rgb = { 3'h7, 3'h3, 2'h3 };
6'h25: r_rgb = { 3'h7, 3'h3, 2'h2 };
6'h26: r_rgb = { 3'h7, 3'h3, 2'h1 };
6'h27: r_rgb = { 3'h7, 3'h4, 2'h0 };
6'h28: r_rgb = { 3'h7, 3'h5, 2'h0 };
6'h29: r_rgb = { 3'h4, 3'h6, 2'h0 };
6'h2a: r_rgb = { 3'h2, 3'h6, 2'h1 };
6'h2b: r_rgb = { 3'h2, 3'h7, 2'h2 };
6'h2c: r_rgb = { 3'h0, 3'h7, 2'h3 };
6'h2d: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h2e: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h2f: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h30: r_rgb = { 3'h7, 3'h7, 2'h3 };
6'h31: r_rgb = { 3'h5, 3'h7, 2'h3 };
6'h32: r_rgb = { 3'h6, 3'h6, 2'h3 };
6'h33: r_rgb = { 3'h6, 3'h6, 2'h3 };
6'h34: r_rgb = { 3'h7, 3'h6, 2'h3 };
6'h35: r_rgb = { 3'h7, 3'h6, 2'h3 };
6'h36: r_rgb = { 3'h7, 3'h5, 2'h2 };
6'h37: r_rgb = { 3'h7, 3'h6, 2'h2 };
6'h38: r_rgb = { 3'h7, 3'h7, 2'h2 };
6'h39: r_rgb = { 3'h7, 3'h7, 2'h2 };
6'h3a: r_rgb = { 3'h5, 3'h7, 2'h2 };
6'h3b: r_rgb = { 3'h5, 3'h7, 2'h3 };
6'h3c: r_rgb = { 3'h4, 3'h7, 2'h3 };
6'h3d: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h3e: r_rgb = { 3'h0, 3'h0, 2'h0 };
6'h3f: r_rgb = { 3'h0, 3'h0, 2'h0 };
endcase
end
end
assign o_vblank = ((r_x_pos == VBLANK_START_X) && (r_y_pos == VBLANK_START_Y)) ? 1 :
((r_x_pos == VBLANK_END_X) && (r_y_pos == VBLANK_END_Y)) ? 0 : o_vblank;
assign w_x_pos = r_x_pos - X_FRONT_PORCH;
assign w_y_pos = r_y_pos - IMAGE_Y_FP;
assign o_nes_x_out = {1'b0, w_x_pos};
assign o_nes_y_out = {1'b0, w_y_pos};
assign o_nes_y_next_out = (r_x_pos == (FRAME_WIDTH / 2)) ? o_nes_y_out + 1 :
!rst ? o_nes_y_next_out :
10'h000;
assign o_hsync = (o_vsync) &&
((o_nes_x_out >= X_FRONT_PORCH) &&
(o_nes_x_out <= X_FRONT_PORCH + IMAGE_WIDTH + X_BACK_PORCH));
assign o_vsync = ((o_nes_y_out == IMAGE_Y_FP) ) ? 1'b1 :
((o_nes_y_out == (IMAGE_Y_FP + IMAGE_HEIGHT + IMAGE_Y_BP))) ? 1'b0:
!rst ? o_vsync :
1'b0;
assign o_image_width = (X_FRONT_PORCH + IMAGE_WIDTH + X_BACK_PORCH);
assign o_image_height = (IMAGE_Y_FP + IMAGE_HEIGHT + IMAGE_Y_BP);
//Positional data
always @ (posedge clk) begin
if (rst) begin
/*
r_x_pos <= VBLANK_START_X;
r_y_pos <= VBLANK_START_Y;
*/
r_x_pos <= 0;
r_y_pos <= 0;
end
else begin
//Increment Position
if (o_pix_pulse_out) begin
if (r_x_pos < (FRAME_WIDTH - 1)) begin
r_x_pos <= r_x_pos + 1;
end
else begin
r_x_pos <= 0;
if (r_y_pos < (FRAME_HEIGHT - 1)) begin
r_y_pos <= r_y_pos + 1;
end
else begin
r_y_pos <= 0;
end
end
end
end
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: read_posted_fifo.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module instantiated by read_data_path module and sits between
// mcb_flow_control module and read_data_gen module to buffer up the
// commands that has sent to memory controller.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module read_posted_fifo #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_BURST_LEN = 4,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6
)
(
input clk_i,
input rst_i,
output reg cmd_rdy_o,
input memc_cmd_full_i,
input cmd_valid_i,
input data_valid_i,
input cmd_start_i,
input [ADDR_WIDTH-1:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
output gen_valid_o,
output [ADDR_WIDTH-1:0] gen_addr_o,
output [BL_WIDTH-1:0] gen_bl_o,
output rd_mdata_en
);
//reg empty_r;
reg [10:0] INC_COUNTS;
reg rd_en_r;
wire full;
wire empty;
wire wr_en;
reg mcb_rd_fifo_port_almost_full;
reg [6:0] buf_avail_r;
reg [6:0] rd_data_received_counts;
reg [6:0] rd_data_counts_asked;
reg dfifo_has_enough_room;
reg [1:0] wait_cnt;
reg wait_done;
assign rd_mdata_en = rd_en_r;
generate
if (FAMILY == "SPARTAN6")
begin: gen_sp6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room ;//& wait_done;
end
// if ((FAMILY == "VIRTEX7") || (FAMILY == "7SERIES") || (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") ||
// (FAMILY == "VIRTEX6") )
else
begin: gen_v6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & wait_done & dfifo_has_enough_room;
end
endgenerate
always @ (posedge clk_i)
begin
if (rst_i)
wait_cnt <= #TCQ 'b0;
else if (cmd_rdy_o && cmd_valid_i)
wait_cnt <= #TCQ 2'b10;
else if (wait_cnt > 0)
wait_cnt <= #TCQ wait_cnt - 1'b1;
end
always @(posedge clk_i)
begin
if (rst_i)
wait_done <= #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i)
wait_done <= #TCQ 1'b0;
else if (wait_cnt == 0)
wait_done <= #TCQ 1'b1;
else
wait_done <= #TCQ 1'b0;
end
reg dfifo_has_enough_room_d1;
always @ (posedge clk_i)
begin
dfifo_has_enough_room <= #TCQ (buf_avail_r >= 32 ) ? 1'b1: 1'b0;
dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ;
end
// remove the dfifo_has_enough_room term. Just need to push pressure to the front to stop
// sending more read commands but still accepting it if there is one coming.
assign wr_en = cmd_valid_i & !full & wait_done;
/*localparam MEM_BURST_INT = MEM_BURST_LEN ;
generate
if (FAMILY == "VIRTEX6" ) begin : INC_COUNTS_V
always @ (posedge clk_i) begin
if ( (NUM_DQ_PINS >= 128 && NUM_DQ_PINS <= 144)) //256
INC_COUNTS <= #TCQ 64 * (MEM_BURST_INT/4);
else if ( (NUM_DQ_PINS >= 64 && NUM_DQ_PINS < 128)) //256
INC_COUNTS <= #TCQ 32 * (MEM_BURST_INT/4);
else if ((NUM_DQ_PINS >= 32) && (NUM_DQ_PINS < 64)) //128
INC_COUNTS <= #TCQ 16 * (MEM_BURST_INT/4) ;
else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24)) //64
INC_COUNTS <= #TCQ 8 * (MEM_BURST_INT/4);
else if ((NUM_DQ_PINS == 8) )
INC_COUNTS <= #TCQ 4 * (MEM_BURST_INT/4);
end
end
endgenerate
*/
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_counts_asked <= #TCQ 'b0;
end
else if (cmd_en_i && cmd_sent[0] == 1 && ~memc_cmd_full_i) begin
// if (FAMILY == "SPARTAN6)
// rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ;
// else
// begin
// if (MEM_BURST_LEN == 8)
rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ;
end
end
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_received_counts <= #TCQ 'b0;
end
else if (data_valid_i) begin
rd_data_received_counts <= #TCQ rd_data_received_counts + 1'b1;
end
end
// calculate how many buf still available
always @ (posedge clk_i)
if (rd_data_received_counts[6] == rd_data_counts_asked[6])
buf_avail_r <= #TCQ (rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] + 7'd64 );
else
buf_avail_r <= #TCQ ( rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] );
always @ (posedge clk_i) begin
rd_en_r <= #TCQ cmd_start_i;
end
assign gen_valid_o = !empty;
afifo #
(
.TCQ (TCQ),
.DSIZE (BL_WIDTH+ADDR_WIDTH),
.FIFO_DEPTH (16),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_fifo
(
.wr_clk (clk_i),
.rst (rst_i),
.wr_en (wr_en),
.wr_data ({bl_i,addr_i}),
.rd_en (rd_en_r),
.rd_clk (clk_i),
.rd_data ({gen_bl_o,gen_addr_o}),
.full (full),
.empty (empty),
.almost_full ()
);
endmodule
|
module top;
reg pass = 1'b1;
integer count;
reg [2:0] icount;
reg clk = 0;
reg [3:0] in = 4'h0;
reg [7:0] result [1:0];
always #10 clk = ~clk;
always #20 in = in + 4'h1;
initial begin
count = 3;
result[0][3:0] <= repeat(count) @(posedge clk) in;
if ($simtime != 0 || result[0] !== 8'bx) begin
$display("Failed repeat(3) blocked at %0t, expected 8'hxx, got %h",
$simtime, result[0]);
pass = 1'b0;
end
@(result[0]);
if ($simtime != 50 || result[0] !== 8'hx0) begin
$display("Failed repeat(3) at %0t, expected 8'hx0, got %h",
$simtime, result[0]);
pass = 1'b0;
end
#15;
count = 0;
result[0][7:4] <= repeat(count) @(posedge clk) in;
@(result[0]); // Reals happen faster so they can use an #0, vectors are slower.
if ($simtime != 65 || result[0] !== 8'h30) begin
$display("Failed repeat(0) at %0t, expected 8'h30, got %h",
$simtime, result[0]);
pass = 1'b0;
end
#20;
count = -1;
result[0][8:5] <= repeat(count) @(posedge clk) in;
@(result[0]); // Reals happen faster so they can use an #0, vectors are slower.
if ($simtime != 85 || result[0] !== 8'h90) begin
$display("Failed repeat(-1) at %0t, expected 8'h80, got %h",
$simtime, result[0]);
pass = 1'b0;
end
#20;
result[0][7:4] <= @(posedge clk) 4'h0;
result[0][7:4] <= @(posedge clk) in; // This one sets the final value.
@(result[0]);
if ($simtime != 110 || result[0] !== 8'h50) begin
$display("Failed @ at %0t, expected 8'h50, got %h",
$simtime, result[0]);
pass = 1'b0;
end
icount = 3'd2;
result[0][3:0] <= @(posedge clk) 4'h1;
result[0][7:4] <= repeat(icount) @(posedge clk) 4'h2;
result[0][1:-2] <= repeat(3) @(posedge clk) 4'h3;
@(result[0]);
if ($simtime != 130 || result[0] !== 8'h51) begin
$display("Failed first @ at %0t, expected 8'h51, got %h",
$simtime, result[0]);
pass = 1'b0;
end
@(result[0]);
if ($simtime != 150 || result[0] !== 8'h21) begin
$display("Failed second @ at %0t, expected 8'h21, got %h",
$simtime, result[0]);
pass = 1'b0;
end
@(result[0]);
if ($simtime != 170 || result[0] !== 8'h20) begin
$display("Failed third @ at %0t, expected 8'h20, got %h",
$simtime, result[0]);
pass = 1'b0;
end
if (pass) $display("PASSED");
$finish;
end
endmodule
|
// file: clk_200_400_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module clk_200_400_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 5.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_200_400_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
endmodule
|
#include <bits/stdc++.h> using namespace std; int get(char *s) { if (s[0] == 8 && s[1] == < ) return 1; if (s[0] == [ && s[1] == ] ) return 2; if (s[0] == ( && s[1] == ) ) return 3; } int check(int a, int b) { if (a == 1 && b == 2 || a == 2 && b == 3 || a == 3 && b == 1) return 1; if (a == 2 && b == 1 || a == 3 && b == 2 || a == 1 && b == 3) return 2; return 0; } int main() { char a[100] = {0}, b[100] = {0}; scanf( %s , a); scanf( %s , b); int x = 0, y = 0; for (int i = 0; i < strlen(a); i += 2) { int t = check(get(a + i), get(b + i)); if (t == 1) x++; if (t == 2) y++; } if (x == y) printf( TIE ); else if (x < y) printf( TEAM 2 WINS ); else printf( TEAM 1 WINS ); } |
#include <bits/stdc++.h> using namespace std; const long long N = 200001; std::vector<long long> g[N]; long long s[N]; long long h[N]; long long a[N] = {0}; bool visited[N] = {false}; void dfs1(long long n, long long parent, long long depth) { h[n] = depth; for (long long v : g[n]) { if (v != parent) { dfs1(v, n, depth + 1); } } } void dfs2(long long n, long long parent) { if (h[n] % 2 == 0) { for (long long v : g[n]) { if (v != parent) { a[n] = s[v] - s[parent]; } } for (long long v : g[n]) { if (v != parent) { a[n] = min(s[v] - s[parent], a[n]); } } s[n] = a[n] + s[parent]; } else { a[n] = s[n] - s[parent]; } for (long long v : g[n]) { if (v != parent) { dfs2(v, n); } } } int main() { long long n; cin >> n; for (long long i = 2; i <= n; i++) { long long parent; cin >> parent; g[parent].push_back(i); g[i].push_back(parent); } for (long long i = 1; i <= n; i++) { cin >> s[i]; } dfs1(1, -1, 1); a[1] = s[1]; dfs2(1, n + 1); long long sum = 0; for (long long i = 1; i <= n; i++) { if (a[i] < 0) { cout << -1 << endl; return 0; } sum += a[i]; } cout << sum << endl; } |
// #####################################################################################
// # Copyright (C) 1991-2008 Altera Corporation
// # Any megafunction design, and related netlist (encrypted or decrypted),
// # support information, device programming or simulation file, and any other
// # associated documentation or information provided by Altera or a partner
// # under Altera's Megafunction Partnership Program may be used only
// # to program PLD devices (but not masked PLD devices) from Altera. Any
// # other use of such megafunction design, netlist, support information,
// # device programming or simulation file, or any other related documentation
// # or information is prohibited for any other purpose, including, but not
// # limited to modification, reverse engineering, de-compiling, or use with
// # any other silicon devices, unless such use is explicitly licensed under
// # a separate agreement with Altera or a megafunction partner. Title to the
// # intellectual property, including patents, copyrights, trademarks, trade
// # secrets, or maskworks, embodied in any such megafunction design, netlist,
// # support information, device programming or simulation file, or any other
// # related documentation or information provided by Altera or a megafunction
// # partner, remains with Altera, the megafunction partner, or their respective
// # licensors. No other licenses, including any licenses needed under any third
// # party's intellectual property, are provided herein.
// #####################################################################################
// #####################################################################################
// # Loopback module for SOPC system simulation with
// # Altera Triple Speed Ethernet (TSE) Megacore
// #
// # Generated at Tue Mar 5 15:22:31 2013 as a SOPC Builder component
// #
// #####################################################################################
// # This is a module used to provide external loopback on the TSE megacore by supplying
// # necessary clocks and default signal values on the network side interface
// # (GMII/MII/TBI/Serial)
// #
// # - by default this module generate clocks for operation in Gigabit mode that is
// # of 8 ns clock period
// # - no support for forcing collision detection and carrier sense in MII mode
// # the mii_col and mii_crs signal always pulled to zero
// # - you are recomment to set the the MAC operation mode using register access
// # rather than directly pulling the control signals
// #
// #####################################################################################
`timescale 1ns / 1ps
module tse_mac_loopback (
ref_clk,
txp,
rxp
);
output ref_clk;
input txp;
output rxp;
reg clk_tmp;
initial
clk_tmp <= 1'b0;
always
#4 clk_tmp <= ~clk_tmp;
reg reconfig_clk_tmp;
initial
reconfig_clk_tmp <= 1'b0;
always
#20 reconfig_clk_tmp <= ~reconfig_clk_tmp;
assign ref_clk = clk_tmp;
assign rxp=txp;
endmodule
|
#include <bits/stdc++.h> using namespace std; bool ok[100010]; int a[100010]; int b[100010]; int c[100010]; vector<int> ans; int main() { int n; scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) scanf( %d , &b[i]); memset(ok, false, sizeof(ok)); long long now, min_value; for (int i = 1; i <= n; i++) c[i] = a[i] - b[i]; now = 0; min_value = 0; for (int i = 1; i <= n; i++) { now += c[i]; min_value = min(min_value, now); } for (int i = 1; i <= n; i++) { if (min_value == 0) ok[i] = true; min_value -= c[i]; min_value = min((long long)0, min_value); } c[n] = a[1] - b[n]; for (int i = n; i >= 2; i--) c[n - i + 1] = a[i] - b[i - 1]; now = 0; min_value = 0; for (int i = 1; i <= n; i++) { now += c[i]; min_value = min(min_value, now); } for (int i = 1; i <= n; i++) { if (min_value == 0) ok[n - i + 1] = true; min_value -= c[i]; min_value = min((long long)0, min_value); } ans.clear(); for (int i = 1; i <= n; i++) if (ok[i]) ans.push_back(i); int len = ans.size(); printf( %d n , len); for (int i = 0; i < len; i++) { printf( %d , ans[i]); if (i == len - 1) printf( n ); else printf( ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int i; int n, d, l; cin >> n >> d >> l; int pos = (n + 1) / 2; int neg = n / 2; int a[n + 1]; if (d > (pos * l - neg) || d < (pos - neg * l)) { cout << -1 ; return 0; } if (d > 0) { for (i = 1; i <= n; i++) a[i] = 1; i = 1; if (n & 1) d--; while (d) { a[2 * i - 1] += min(l - 1, d); d -= min(l - 1, d); i++; } } else { for (i = 1; i <= n; i++) a[i] = 1; i = 1; d = -d; if (n & 1) d++; while (d) { a[2 * i] += min(l - 1, d); d -= min(l - 1, d); i++; } } for (i = 1; i <= n; i++) cout << a[i] << ; return 0; } |
module vid_score #(parameter POSITION = 114 )
(clk,
rst_n,
score,
vid_time,
x,
y,
num
);
//Where to display the number of the score
localparam NUM_LOW = POSITION;
localparam NUM_HI = POSITION+3;
input clk;
input rst_n;
input wire[3:0] score;
input wire vid_time;
input wire[8:0] x;
input wire[7:0] y;
output reg num;
always @(posedge clk) begin
if(~rst_n) begin
num <= 0; //data used to display player 0 score
end else begin
case(score)
0: begin
num <= (vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==19 || y==20 ) ) ||
(vid_time==1 && (x==NUM_LOW || x==NUM_HI ) && (y>=19 && y<=32 ) ) ||
(vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==31 || y==32 ) ) ;
end
1: begin
num <= (vid_time==1 && ( x==NUM_HI ) && (y>=19 && y<=32 ) ) ;
end
2: begin
num <= (vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==19 || y==20 ) ) ||
(vid_time==1 && (x==NUM_HI ) && (y>=19 && y<=26 ) ) ||
(vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==25 || y==26 ) ) ||
(vid_time==1 && (x==NUM_LOW ) && (y>=25 && y<=32 ) ) ||
(vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==31 || y==32 ) ) ;
end
3: begin
num <= (vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==19 || y==20 ) ) ||
(vid_time==1 && (x>=(NUM_LOW+1) && x<=NUM_HI ) && (y==25 || y==26 ) ) ||
(vid_time==1 && ( x==NUM_HI ) && (y>=19 && y<=32 ) ) ||
(vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==31 || y==32 ) ) ;
end
4: begin
num <= (vid_time==1 && (x==NUM_LOW ) && (y>=19 && y<=26 ) ) ||
(vid_time==1 && ( x==NUM_HI ) && (y>=19 && y<=32 ) ) ||
(vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==25 || y==26 ) ) ;
end
5: begin
num <= (vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==19 || y==20 ) ) ||
(vid_time==1 && (x==NUM_LOW ) && (y>=19 && y<=26 ) ) ||
(vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==25 || y==26 ) ) ||
(vid_time==1 && (x==NUM_HI ) && (y>=25 && y<=32 ) ) ||
(vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==31 || y==32 ) ) ;
end
6: begin
num <= (vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==19 || y==20 ) ) ||
(vid_time==1 && (x==NUM_LOW ) && (y>=19 && y<=32 ) ) ||
(vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==25 || y==26 ) ) ||
(vid_time==1 && (x==NUM_HI ) && (y>=25 && y<=32 ) ) ||
(vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==31 || y==32 ) ) ;
end
7: begin
num <= (vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==19 || y==20 ) ) ||
(vid_time==1 && (x==NUM_HI ) && (y>=19 && y<=32 ) ) ;
end
8: begin
num <= (vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==19 || y==20 ) ) ||
(vid_time==1 && (x==NUM_LOW ) && (y>=19 && y<=32 ) ) ||
(vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==25 || y==26 ) ) ||
(vid_time==1 && (x==NUM_HI ) && (y>=19 && y<=32 ) ) ||
(vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==31 || y==32 ) ) ;
end
9: begin
num <= (vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==19 || y==20 ) ) ||
(vid_time==1 && (x==NUM_LOW ) && (y>=19 && y<=26 ) ) ||
(vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==25 || y==26 ) ) ||
(vid_time==1 && (x==NUM_HI ) && (y>=19 && y<=32 ) ) ||
(vid_time==1 && (x>=NUM_LOW && x<=NUM_HI ) && (y==31 || y==32 ) ) ;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_TB_V
`define SKY130_FD_SC_LP__XNOR2_TB_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xnor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__xnor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_TB_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_monitor_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Detects transaction open/close events from the stream
// of data from the tx_port_channel_gate. Filters out events and passes data
// onto the tx_port_buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTMON64_NEXT 6'b00_0001
`define S_TXPORTMON64_EVT_2 6'b00_0010
`define S_TXPORTMON64_TXN 6'b00_0100
`define S_TXPORTMON64_READ 6'b00_1000
`define S_TXPORTMON64_END_0 6'b01_0000
`define S_TXPORTMON64_END_1 6'b10_0000
`timescale 1ns/1ns
module tx_port_monitor_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_VALID_HIST = 1
)
(
input RST,
input CLK,
input [C_DATA_WIDTH:0] EVT_DATA, // Event data from tx_port_channel_gate
input EVT_DATA_EMPTY, // Event data FIFO is empty
output EVT_DATA_RD_EN, // Event data FIFO read enable
output [C_DATA_WIDTH-1:0] WR_DATA, // Output data
output WR_EN, // Write enable for output data
input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Output FIFO count
output TXN, // Transaction parameters are valid
input ACK, // Transaction parameter read, continue
output LAST, // Channel last write
output [31:0] LEN, // Channel write length (in 32 bit words)
output [30:0] OFF, // Channel write offset
output [31:0] WORDS_RECVD, // Count of data words received in transaction
output DONE, // Transaction is closed
input TX_ERR // Transaction encountered an error
);
`include "functions.vh"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [5:0] rState=`S_TXPORTMON64_NEXT, _rState=`S_TXPORTMON64_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
reg [63:0] rReadData=64'd0, _rReadData=64'd0;
reg [31:0] rWordsRecvd=0, _rWordsRecvd=0;
reg [31:0] rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
reg rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
reg rAlmostFull=0, _rAlmostFull=0;
reg rLenEQ0Hi=0, _rLenEQ0Hi=0;
reg rLenEQ0Lo=0, _rLenEQ0Lo=0;
reg rLenLE2Lo=0, _rLenLE2Lo=0;
reg rTxErr=0, _rTxErr=0;
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[3]); // S_TXPORTMON64_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE2Lo)) & wPayloadData);
assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData; // S_TXPORTMON64_READ
assign TXN = rState[2]; // S_TXPORTMON64_TXN
assign LAST = rReadData[0];
assign OFF = rReadData[31:1];
assign LEN = rReadData[63:32];
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[3]; // !S_TXPORTMON64_READ
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
end
always @ (*) begin
_rTxErr = TX_ERR;
end
// Transaction monitoring FSM.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXPORTMON64_NEXT : _rState);
end
always @ (*) begin
_rState = rState;
case (rState)
`S_TXPORTMON64_NEXT: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON64_EVT_2;
end
`S_TXPORTMON64_EVT_2: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON64_TXN;
end
`S_TXPORTMON64_TXN: begin // Don't read, wait until transaction has been acknowledged
if (ACK)
_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON64_END_0 : `S_TXPORTMON64_READ);
end
`S_TXPORTMON64_READ: begin // Continue reading, wait for end of transaction event or all expected data
if (rEvent)
_rState = `S_TXPORTMON64_END_1;
else if (wAllWordsRecvd | rTxErr)
_rState = `S_TXPORTMON64_END_0;
end
`S_TXPORTMON64_END_0: begin // Continue reading, wait for first end of transaction event
if (rEvent)
_rState = `S_TXPORTMON64_END_1;
end
`S_TXPORTMON64_END_1: begin // Continue reading, wait for second end of transaction event
if (rEvent)
_rState = `S_TXPORTMON64_NEXT;
end
default: begin
_rState = `S_TXPORTMON64_NEXT;
end
endcase
end
// Manage reading from the FIFO and tracking amounts read.
always @ (posedge CLK) begin
rRead <= #1 (RST ? 1'd0 : _rRead);
rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
rEvent <= #1 (RST ? 1'd0 : _rEvent);
rReadData <= #1 _rReadData;
rWordsRecvd <= #1 _rWordsRecvd;
rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
rAlmostFull <= #1 _rAlmostFull;
rLenEQ0Hi <= #1 _rLenEQ0Hi;
rLenEQ0Lo <= #1 _rLenEQ0Lo;
rLenLE2Lo <= #1 _rLenLE2Lo;
end
always @ (*) begin
// Don't get to the full point in the output FIFO
_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
// Track read history so we know when data is valid
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON64_TXN
// Track detected events
_rEvent = wEventData;
// Save event data when valid
if (wEventData)
_rReadData = EVT_DATA[C_DATA_WIDTH-1:0];
else
_rReadData = rReadData;
// If LEN == 0, we don't want to send any data to the output
_rLenEQ0Hi = (LEN[31:16] == 16'd0);
_rLenEQ0Lo = (LEN[15:0] == 16'd0);
// If LEN <= 2, we want to trigger the almost all received flag
_rLenLE2Lo = (LEN[15:0] <= 16'd2);
// Count received non-event data
_rWordsRecvd = (ACK ? 0 : rWordsRecvd + (wPayloadData<<1));
_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + (wPayloadData<<1));
_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({TXN, wPayloadData, wEventData, rState}),
.DATA({297'd0,
WR_COUNT, // 10
wPayloadData, // 1
EVT_DATA_RD_EN, // 1
RST, // 1
rTxErr, // 1
wEventData, // 1
rReadData, // 64
OFF, // 31
LEN, // 32
LAST, // 1
TXN, // 1
EVT_DATA_EMPTY, // 1
EVT_DATA, // 65
rState}) // 5
);
*/
endmodule
|
#include <bits/stdc++.h> using namespace std; const int INF = 522133279; const int MAXN = 100000; const int TOTN = 100 + 100; const long long MOD = 1000000007; bool _su[MAXN]; vector<int> su; vector<int> suc; int n, k; void shai() { memset((_su), true, sizeof(_su)); for (int i = (2); i < (MAXN); i++) { if (k <= 1) break; if (_su[i] && k % i == 0) { su.push_back(i); suc.push_back(0); while (k && k % i == 0) { k /= i; suc.back()++; } for (int j = 2; j * i < MAXN; j++) _su[j * i] = false; } } if (k != 1) { su.push_back(k); suc.push_back(1); } } vector<int> fen(int x) { vector<int> cnt; cnt.resize(su.size()); for (int i = (0); i < (su.size()); i++) { while (x && x % su[i] == 0) { x /= su[i]; cnt[i]++; } } return cnt; } vector<vector<int> > lis; bool divisible(vector<int> cnt) { bool ok = true; for (int i = (0); i < (cnt.size()); i++) { if (cnt[i] < suc[i]) { ok = false; break; } } return ok; } vector<int> getCnt(int l, int r) { if (l == 0) return lis[r]; vector<int> res; for (int i = (0); i < (lis[l].size()); i++) { res.push_back(lis[r][i] - lis[l - 1][i]); } return res; } int main() { ios::sync_with_stdio(false); cin >> n >> k; shai(); for (int i = (0); i < (n); i++) { int a; cin >> a; lis.push_back(fen(a)); } for (int i = (1); i < (n); i++) { for (int j = (0); j < (lis[i].size()); j++) { lis[i][j] += lis[i - 1][j]; } } int l = 0, r = 0; long long ans = 0; while (r < n) { while (r < n && !divisible(getCnt(l, r))) r++; if (r >= n) break; ans += n - r; l++; if (l > r) r = l; } cout << ans << endl; return 0; } |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file Font.v when simulating
// the core, Font. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module Font(
a,
spo
);
input [11 : 0] a;
output [7 : 0] spo;
// synthesis translate_off
DIST_MEM_GEN_V7_2 #(
.C_ADDR_WIDTH(12),
.C_DEFAULT_DATA("0"),
.C_DEPTH(4096),
.C_FAMILY("spartan6"),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_SPRA(0),
.C_HAS_WE(0),
.C_MEM_INIT_FILE("Font.mif"),
.C_MEM_TYPE(0),
.C_PARSER_TYPE(1),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(8)
)
inst (
.A(a),
.SPO(spo),
.D(),
.DPRA(),
.SPRA(),
.CLK(),
.WE(),
.I_CE(),
.QSPO_CE(),
.QDPO_CE(),
.QDPO_CLK(),
.QSPO_RST(),
.QDPO_RST(),
.QSPO_SRST(),
.QDPO_SRST(),
.DPO(),
.QSPO(),
.QDPO()
);
// synthesis translate_on
endmodule
|
#include <bits/stdc++.h> inline int Get() { char ch; while ((ch = getchar()) < 0 || ch > 9 ) ; int Num = ch - 0 ; while ((ch = getchar()) >= 0 && ch <= 9 ) Num = (Num << 3) + (Num << 1) + ch - 0 ; return Num; } const int N = 1e3 + 5; const int M = 1600; int n, m, gA[N], gB[N], tA[N], tB[N], id[N]; long double prob[N]; std ::pair<long double, long double> dp[N][M]; inline bool cmp(const int &a, const int &b) { return (1 - prob[b]) * prob[a] * tB[a] < (1 - prob[a]) * prob[b] * tB[b]; } int main() { n = Get(), m = Get(); for (int i = 1; i <= n; ++i) { gA[i] = Get(), gB[i] = Get(), tA[i] = Get(), tB[i] = Get(); double res; scanf( %lf , &res); prob[i] = res; } for (int i = 1; i <= n; ++i) id[i] = i; std ::sort(id + 1, id + n + 1, cmp); for (int i = 1, k; k = id[i], i <= n; ++i) for (int j = m; j >= 0; --j) { std ::pair<long double, long double> nxt; dp[i][j] = dp[i - 1][j]; if (j >= tA[k]) { nxt = std ::make_pair(dp[i - 1][j - tA[k]].first + gA[k], dp[i - 1][j - tA[k]].second - tA[k]); dp[i][j] = std ::max(dp[i][j], nxt); } if (j >= tA[k] + tB[k]) { nxt.first = dp[i - 1][j - tA[k] - tB[k]].first + gA[k] + (1 - prob[k]) * gB[k]; nxt.second = prob[k] * dp[i - 1][j - tA[k] - tB[k]].second - (1 - prob[k]) * (j - tA[k]) - tA[k]; dp[i][j] = std ::max(dp[i][j], nxt); } } std ::pair<long double, long double> ans = std ::make_pair(0, 0); for (int j = 0; j <= m; ++j) ans = std ::max(ans, dp[n][j]); printf( %.10lf %.10lf n , (double)ans.first, -(double)ans.second); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a2bb2oi (
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire nor1_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y, nor0_out, and0_out);
buf buf0 (Y , nor1_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A2BB2OI_FUNCTIONAL_V |
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: stage2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module stage2 (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/masters.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/masters.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL stage2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL stage2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/13.0sp1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2013/03/07 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\" ; -name SDC_STATEMENT \"set_false_path -from [get_registers *altera_avalon_st_clock_crosser:*|in_data_buffer*] -to [get_registers *altera_avalon_st_clock_crosser:*|out_data_buffer*]\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= 'b0;
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= 'b0;
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the 2-bit pipe
/**
* Import the modules that will be tested for in this testbench
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
//`include "pipe2.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_pipe2();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the 2-bit pipe
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [1:0] op; // Output signal out
// Declare "reg" signals: inputs to the DUT
reg [1:0] ip; // Input signal - in
reg clk; // Input signal - clock
reg rst; // Input signal - reset
/**
* Instantiate an instance of the pipe
* so that inputs can be passed to the Device Under Test (DUT)
* Given instance name is "pp"
*/
pipeline_buffer_2bit pp (
// instance_name(signal name),
// Signal name can be the same as the instance name
ip,op,clk,rst);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clk = 0;
#5 clk = 1;
// Period = 10 ns
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
ip = 2'd0;
rst = 1'd0;
// @t=9,
#9
ip = 2'd1;
rst = 1'd0;
// @t=19,
#10
ip = 2'd0;
rst = 1'd0;
// @t=29,
#10
ip = 2'd2;
rst = 1'd0;
// @t=39,
#10
ip = 2'd1;
rst = 1'd0;
// @t=49,
#10
ip = 2'd3;
rst = 1'd0;
// @t=59,
#10
ip = 2'd0;
rst = 1'd0;
// @t=69,
#10
ip = 2'd1;
rst = 1'd0;
// @t=79,
#10
ip = 2'd0;
rst = 1'd0;
// @t=89,
#10
ip = 2'd1;
rst = 1'd0;
// @t=99,
#10
ip = 2'd0;
rst = 1'd0;
// @t=109,
#10
ip = 2'd3;
rst = 1'd0;
// @t=119,
#10
ip = 2'd0;
rst = 1'd0;
// @t=129,
#10
ip = 2'd1;
rst = 1'd0;
// @t=139,
#10
ip = 2'd0;
rst = 1'd0;
// @t=149,
#10
ip = 2'd1;
rst = 1'd0;
// @t=159,
#10
ip = 2'd2;
rst = 1'd0;
// @t=169,
#10
ip = 2'd1;
rst = 1'd0;
// @t=179,
#10
ip = 2'd0;
rst = 1'd0;
// @t=189,
#10
ip = 2'd2;
rst = 1'd0;
// @t=199,
#10
ip = 2'd0;
rst = 1'd0;
// @t=209,
#10
ip = 2'd3;
rst = 1'd0;
// @t=219,
#10
ip = 2'd3;
rst = 1'd0;
// @t=229,
#10
ip = 2'd1;
rst = 1'd0;
// @t=239,
#10
ip = 2'd2;
rst = 1'd0;
// @t=249,
#10
ip = 2'd1;
rst = 1'd0;
// @t=259,
#10
ip = 2'd0;
rst = 1'd0;
// @t=269,
#10
ip = 2'd1;
rst = 1'd0;
// @t=279,
#10
ip = 2'd2;
rst = 1'd1;
// @t=289,
#10
ip = 2'd1;
rst = 1'd0;
// @t=299,
#10
ip = 2'd0;
rst = 1'd0;
// @t=309,
#10
ip = 2'd2;
rst = 1'd0;
// @t=319,
#10
ip = 2'd1;
rst = 1'd0;
// @t=329,
#10
ip = 2'd0;
rst = 1'd0;
// @t=339,
#10
ip = 2'd2;
rst = 1'd0;
// @t=349,
#10
ip = 2'd0;
rst = 1'd0;
// @t=359,
#10
ip = 2'd3;
rst = 1'd0;
// @t=369,
#10
ip = 2'd1;
rst = 1'd0;
// @t=379,
#10
ip = 2'd2;
rst = 1'd0;
// @t=389,
#10
ip = 2'd1;
rst = 1'd0;
// @t=399,
#10
ip = 2'd0;
rst = 1'd0;
// @t=409,
#10
ip = 2'd1;
rst = 1'd0;
// @t=419,
#10
ip = 2'd2;
rst = 1'd0;
// @t=429,
#10
ip = 2'd1;
rst = 1'd0;
// @t=439,
#10
ip = 2'd3;
rst = 1'd0;
// @t=449,
#10
ip = 2'd1;
rst = 1'd0;
// @t=459,
#10
ip = 2'd0;
rst = 1'd0;
// @t=469,
#10
ip = 2'd2;
rst = 1'd0;
// @t=479,
#10
ip = 2'd0;
rst = 1'd0;
// @t=489,
#10
ip = 2'd0;
rst = 1'd0;
// @t=499,
#10
ip = 2'd0;
rst = 1'd0;
// @t=509,
#10
ip = 2'd0;
rst = 1'd0;
// @t=519,
#10
ip = 2'd2;
rst = 1'd0;
// @t=529,
#10
ip = 2'd1;
rst = 1'd0;
// @t=539,
#10
ip = 2'd0;
rst = 1'd0;
// @t=549,
#10
ip = 2'd1;
rst = 1'd0;
// @t=559,
#10
ip = 2'd3;
rst = 1'd0;
// @t=569,
#10
ip = 2'd1;
rst = 1'd0;
// @t=579,
#10
ip = 2'd1;
rst = 1'd0;
// @t=589,
#10
ip = 2'd0;
rst = 1'd0;
// @t=599,
#10
ip = 2'd1;
rst = 1'd0;
// @t=609,
#10
ip = 2'd0;
rst = 1'd0;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; const long double EPS = 0.000000001; const long long INF64 = 1000000000000000000; const long long INF32 = 2000000000; bool iss_pt_in_triangle(pair<long long, long long> a, pair<long long, long long> b, pair<long long, long long> c, pair<long long, long long> point) { long long x1 = a.first, x2 = b.first, x3 = c.first, x0 = point.first; long long y1 = a.second, y2 = b.second, y3 = c.second, y0 = point.second; long long aa = (x1 - x0) * (y2 - y1) - (x2 - x1) * (y1 - y0); long long bb = (x2 - x0) * (y3 - y2) - (x3 - x2) * (y2 - y0); long long cc = (x3 - x0) * (y1 - y3) - (x1 - x3) * (y3 - y0); if (aa == 0 || bb == 0 || cc == 0) return 1; if (aa >= 0 && bb >= 0 && cc >= 0) return 1; if (aa <= 0 && bb <= 0 && cc <= 0) return 1; return 0; } bool iss_ll(long long &__1, long long &__2) { return INF64 / __1 >= __2; } bool equal(long double _1, long double _2) { return (abs(_1 - _2) < EPS); } bool iss_sqr(long long &__1) { long long __2 = sqrt((long double)__1); return __2 * __2 == __1; }; bool iss_prime(long long __1) { for (long long i = 2; i * i <= __1; ++i) if (!(__1 % i)) return 0; return 1; } long long gcd(long long __1, long long __2) { while (__1 && __2) if (__1 > __2) __1 = __1 % __2; else __2 = __2 % __1; return __1 + __2; } long long lcm(long long &__1, long long &__2) { return __1 * __2 / (gcd(__1, __2)); } long long sq_cube(long long x) { if (x == 0) return 1; long long l = 0, r = 2e6; while (l + 1 < r) { long long m = (l + r) / 2; if (m * m * m > x) r = m; else l = m; } return l; } set<long long> G[100100]; vector<long long> GR[100100]; bool used[100100]; void dfs(long long v) { if (used[v]) return; used[v] = 1; for (long long i : G[v]) dfs(i); } long long n, k; long long step(long long k) { long long res = 1; for (long long i = 0; i < k; ++i) res *= 3; return res; } long long dfss(long long v, long long deep) { long long ans = deep; used[v] = 1; if (deep != k) { if ((GR[v].size() < 4 && deep > 0 && deep != k) || (deep == 0 && GR[v].size() < 3)) { cout << No << n ; exit(0); } } for (long long i : GR[v]) { if (used[i]) continue; ans = max(dfss(i, deep + 1), ans); } if (ans != k) { cout << No << n ; exit(0); } return ans; } signed main(signed argc, const char *argv[]) { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> k; if (k > 20) { cout << No << n ; return 0; } for (long long i = 1; i < n; ++i) { long long x, y; cin >> x >> y; G[x].insert(y); G[y].insert(x); GR[x].push_back(y); GR[y].push_back(x); } dfs(1); for (long long i = 1; i <= n; ++i) { if (!used[i]) { cout << No << n ; return 0; } } vector<long long> VEC; long long k1 = k; long long pos = 0; for (long long i = 1; i <= n; ++i) if (G[i].size() == 1) VEC.push_back(i); while (k--) { if (VEC.size() == 0) { cout << No << n ; return 0; } if (k == 0) { pos = *G[VEC.front()].begin(); } for (long long i : VEC) { G[*G[i].begin()].erase(i); G[i].clear(); } VEC.clear(); for (long long i = 1; i <= n; ++i) { if (G[i].size() == 1) VEC.push_back(i); if (G[i].size() == 2) { cout << No << n ; return 0; } } } memset(used, 0, sizeof(used)); k = k1; dfss(pos, 0); cout << Yes << n ; } |
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the user's design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// (other locations)
//
// web: http://www.latticesemi.com/
// email:
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_debug.v
// Title : Hardware debug registers and associated logic.
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// Version : 3.2
// : Fixed simulation bug which flares up when number of
// : watchpoints is zero.
// =============================================================================
`include "lm32_include.v"
`ifdef CFG_DEBUG_ENABLED
// States for single-step FSM
`define LM32_DEBUG_SS_STATE_RNG 2:0
`define LM32_DEBUG_SS_STATE_IDLE 3'b000
`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET 3'b001
`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN 3'b010
`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT 3'b011
`define LM32_DEBUG_SS_STATE_RESTART 3'b100
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_debug (
// ----- Inputs -------
clk_i,
rst_i,
pc_x,
load_x,
store_x,
load_store_address_x,
csr_write_enable_x,
csr_write_data,
csr_x,
`ifdef CFG_HW_DEBUG_ENABLED
jtag_csr_write_enable,
jtag_csr_write_data,
jtag_csr,
`endif
`ifdef LM32_SINGLE_STEP_ENABLED
eret_q_x,
bret_q_x,
stall_x,
exception_x,
q_x,
`ifdef CFG_DCACHE_ENABLED
dcache_refill_request,
`endif
`endif
// ----- Outputs -------
`ifdef LM32_SINGLE_STEP_ENABLED
dc_ss,
`endif
dc_re,
bp_match,
wp_match
);
/////////////////////////////////////////////////////
// Parameters
/////////////////////////////////////////////////////
parameter breakpoints = 0; // Number of breakpoint CSRs
parameter watchpoints = 0; // Number of watchpoint CSRs
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input [`LM32_PC_RNG] pc_x; // X stage PC
input load_x; // Load instruction in X stage
input store_x; // Store instruction in X stage
input [`LM32_WORD_RNG] load_store_address_x; // Load or store effective address
input csr_write_enable_x; // wcsr instruction in X stage
input [`LM32_WORD_RNG] csr_write_data; // Data to write to CSR
input [`LM32_CSR_RNG] csr_x; // Which CSR to write
`ifdef CFG_HW_DEBUG_ENABLED
input jtag_csr_write_enable; // JTAG interface CSR write enable
input [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to CSR
input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
`endif
`ifdef LM32_SINGLE_STEP_ENABLED
input eret_q_x; // eret instruction in X stage
input bret_q_x; // bret instruction in X stage
input stall_x; // Instruction in X stage is stalled
input exception_x; // An exception has occured in X stage
input q_x; // Indicates the instruction in the X stage is qualified
`ifdef CFG_DCACHE_ENABLED
input dcache_refill_request; // Indicates data cache wants to be refilled
`endif
`endif
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
`ifdef LM32_SINGLE_STEP_ENABLED
output dc_ss; // Single-step enable
reg dc_ss;
`endif
output dc_re; // Remap exceptions
reg dc_re;
output bp_match; // Indicates a breakpoint has matched
wire bp_match;
output wp_match; // Indicates a watchpoint has matched
wire wp_match;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
genvar i; // Loop index for generate statements
// Debug CSRs
reg [`LM32_PC_RNG] bp_a[0:breakpoints-1]; // Instruction breakpoint address
reg bp_e[0:breakpoints-1]; // Instruction breakpoint enable
wire [0:breakpoints-1]bp_match_n; // Indicates if a h/w instruction breakpoint matched
reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1]; // Watchpoint enable
reg [`LM32_WORD_RNG] wp[0:watchpoints-1]; // Watchpoint address
wire [0:watchpoints-1]wp_match_n; // Indicates if a h/w data watchpoint matched
wire debug_csr_write_enable; // Debug CSR write enable (from either a wcsr instruction of external debugger)
wire [`LM32_WORD_RNG] debug_csr_write_data; // Data to write to debug CSR
wire [`LM32_CSR_RNG] debug_csr; // Debug CSR to write to
`ifdef LM32_SINGLE_STEP_ENABLED
// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
//reg [`LM32_DEBUG_SS_STATE_RNG] state; // State of single-step FSM
integer state; // State of single-step FSM
`endif
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
// Check for breakpoints
generate
for (i = 0; i < breakpoints; i = i + 1)
begin : bp_comb
assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
end
endgenerate
generate
`ifdef LM32_SINGLE_STEP_ENABLED
if (breakpoints > 0)
assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
else
assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
`else
if (breakpoints > 0)
assign bp_match = |bp_match_n;
else
assign bp_match = `FALSE;
`endif
endgenerate
// Check for watchpoints
generate
for (i = 0; i < watchpoints; i = i + 1)
begin : wp_comb
assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
end
endgenerate
generate
if (watchpoints > 0)
assign wp_match = |wp_match_n;
else
assign wp_match = `FALSE;
endgenerate
`ifdef CFG_HW_DEBUG_ENABLED
// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs
assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE);
assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
`else
assign debug_csr_write_enable = csr_write_enable_x;
assign debug_csr_write_data = csr_write_data;
assign debug_csr = csr_x;
`endif
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// Breakpoint address and enable CSRs
generate
for (i = 0; i < breakpoints; i = i + 1)
begin : bp_seq
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
bp_e[i] <= `FALSE;
end
else
begin
if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
begin
bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
bp_e[i] <= debug_csr_write_data[0];
end
end
end
end
endgenerate
// Watchpoint address and control flags CSRs
generate
for (i = 0; i < watchpoints; i = i + 1)
begin : wp_seq
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
wpc_c[i] <= `LM32_WPC_C_DISABLED;
end
else
begin
if (debug_csr_write_enable == `TRUE)
begin
if (debug_csr == `LM32_CSR_DC)
wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
if (debug_csr == `LM32_CSR_WP0 + i)
wp[i] <= debug_csr_write_data;
end
end
end
end
endgenerate
// Remap exceptions control bit
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
dc_re <= `FALSE;
else
begin
if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
dc_re <= debug_csr_write_data[1];
end
end
`ifdef LM32_SINGLE_STEP_ENABLED
// Single-step control flag
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
state <= `LM32_DEBUG_SS_STATE_IDLE;
dc_ss <= `FALSE;
end
else
begin
if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
begin
dc_ss <= debug_csr_write_data[0];
if (debug_csr_write_data[0] == `FALSE)
state <= `LM32_DEBUG_SS_STATE_IDLE;
else
state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
end
case (state)
`LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
begin
// Wait for eret or bret instruction to be executed
if ( ( (eret_q_x == `TRUE)
|| (bret_q_x == `TRUE)
)
&& (stall_x == `FALSE)
)
state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
end
`LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
begin
// Wait for an instruction to be executed
if ((q_x == `TRUE) && (stall_x == `FALSE))
state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
end
`LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
begin
// Wait for exception to be raised
`ifdef CFG_DCACHE_ENABLED
if (dcache_refill_request == `TRUE)
state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
else
`endif
if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
begin
dc_ss <= `FALSE;
state <= `LM32_DEBUG_SS_STATE_RESTART;
end
end
`LM32_DEBUG_SS_STATE_RESTART:
begin
// Watch to see if stepped instruction is restarted due to a cache miss
`ifdef CFG_DCACHE_ENABLED
if (dcache_refill_request == `TRUE)
state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
else
`endif
state <= `LM32_DEBUG_SS_STATE_IDLE;
end
endcase
end
end
`endif
endmodule
`endif
|
#include <bits/stdc++.h> using namespace std; const long long inf = (long long)3e18; struct data { long long x, flag, id; int operator<(const data& d) const { return x < d.x; } } d[200010 << 2]; long long dp[200010 << 2][2], c[200010 << 2], s[200010 << 2], v[200010 << 2], nw, ans; long long _s[200010 << 2], n, np, m, C, tp, pre; bool is2[200010 << 2]; struct zkw { long long zkwm, s[2100000], atg[2100000]; void init(int len) { zkwm = 1; while (zkwm <= len + 2) zkwm <<= 1; for (int i = 1; i <= zkwm + zkwm; ++i) s[i] = -inf; } long long query(int l, int r) { if (l > r || r <= 0 || l > np) return -inf; l = max(l, 1), r = min((long long)r, np); long long lans = -inf, rans = -inf; for (l += zkwm - 1 - 1, r += zkwm + 1 - 1; l ^ r ^ 1; l >>= 1, r >>= 1) { if (lans != -inf) lans += atg[l]; if (rans != -inf) rans += atg[r]; if (~l & 1) lans = max(lans, s[l ^ 1]); if (r & 1) rans = max(rans, s[r ^ 1]); } if (lans != -inf) lans += atg[l]; if (rans != -inf) rans += atg[r]; lans = max(lans, rans); if (lans != -inf) for (l >>= 1; l; l >>= 1) lans += atg[l]; return lans; } void mdy(int l, int r, long long a) { if (l > r || r <= 0 || l > np) return; l = max(l, 1), r = min((long long)r, np); int f = 0; for (l += zkwm - 1 - 1, r += zkwm + 1 - 1; l ^ r ^ 1; l >>= 1, r >>= 1, f = 1) { if (~l & 1) atg[l ^ 1] += a, s[l ^ 1] += a; if (r & 1) atg[r ^ 1] += a, s[r ^ 1] += a; if (f) s[l] = max(s[l << 1], s[l << 1 | 1]) + atg[l], s[r] = max(s[r << 1], s[r << 1 | 1]) + atg[r]; } s[l] = max(s[l << 1], s[l << 1 | 1]) + atg[l], s[r] = max(s[r << 1], s[r << 1 | 1]) + atg[r]; for (l >>= 1; l; l >>= 1) s[l] = max(s[l << 1], s[l << 1 | 1]) + atg[l]; } void _mdy(int l, long long a) { l += zkwm - 1; atg[l] = 0; for (int _l = l >> 1; _l; _l >>= 1) a -= atg[_l]; if (s[l] < a) s[l] = a; else return; for (l >>= 1; l; l >>= 1) s[l] = max(s[l << 1], s[l << 1 | 1]) + atg[l]; } } A[4]; int main() { scanf( %lld%lld%lld , &n, &m, &C); for (long long i = 1, L, R; i <= n; ++i) scanf( %lld%lld , &L, &R), d[++tp] = data{L, 1ll, 0ll}, d[++tp] = data{R, -1ll, 0ll}; for (long long i = 1, L, R; i <= m; ++i) scanf( %lld%lld , &L, &R), d[++tp] = data{L, 1ll, 1ll}, d[++tp] = data{R, -1ll, 1ll}; sort(d + 1, d + tp + 1); int tg = 0, ch = 0; for (int i = 1; i <= tp; ++i) { if (i > 1) { long long x = d[i].x - d[i - 1].x; if (tg == 2) v[i] = x, s[i] = 0, is2[i - 1] = true; else if (tg == 1) v[i] = (ch == 0 ? 1 : 0) * x, s[i] = (ch == 0 ? 1 : -1) * x; else v[i] = s[i] = 0; s[i] += s[i - 1], c[i] = v[i] + c[i - 1]; } if (d[i].flag > 0) tg++, ch = d[i].id; else if (d[i].flag < 0) tg--, ch = 1 - d[i].id; _s[i] = s[i]; } sort(_s + 1, _s + tp + 1); np = unique(_s + 1, _s + tp + 1) - _s - 1; for (int i = 0; i < 4; ++i) A[i].init(np); for (int i = 0; i <= tp + 1; ++i) dp[i][0] = dp[i][1] = -inf; for (int i = 1; i < tp; ++i) { if (is2[i]) { if (s[i] >= C) dp[i][0] = max(dp[i][0], pre - s[i] + C + v[i + 1] * 2); else if (s[i] <= -C) dp[i][1] = max(dp[i][1], pre + v[i + 1] * 2); } if (abs(nw) <= C && is2[i]) pre += v[i + 1] * 2; else pre += v[i + 1], nw += s[i + 1] - s[i]; if (!is2[i]) continue; dp[i][0] = max(dp[i][0], A[0].query(1, upper_bound(_s + 1, _s + np + 1, s[i]) - _s - 1) + c[i + 1] - s[i] + v[i + 1]); dp[i][1] = max( dp[i][1], A[1].query(lower_bound(_s + 1, _s + np + 1, s[i] + 2 * C) - _s, np) + c[i + 1] + v[i + 1]); dp[i][0] = max( dp[i][0], A[2].query(1, upper_bound(_s + 1, _s + np + 1, s[i] - 2 * C) - _s - 1) - s[i] + v[i + 1] + c[i + 1] + 2 * C); dp[i][1] = max(dp[i][1], A[3].query(lower_bound(_s + 1, _s + np + 1, s[i]) - _s, np) + c[i + 1] + v[i + 1]); int l = lower_bound(_s + 1, _s + np + 1, s[i]) - _s, r = upper_bound(_s + 1, _s + np + 1, s[i] + 2 * C) - _s - 1; if (A[0].s[1] >= (long long)(-2e18)) A[0].mdy(l, r, v[i + 1]); if (A[1].s[1] >= (long long)(-2e18)) A[1].mdy(l, r, v[i + 1]); l = lower_bound(_s + 1, _s + np + 1, s[i] - 2 * C) - _s, r = upper_bound(_s + 1, _s + np + 1, s[i]) - _s - 1; if (A[2].s[1] >= (long long)(-2e18)) A[2].mdy(l, r, v[i + 1]); if (A[3].s[1] >= (long long)(-2e18)) A[3].mdy(l, r, v[i + 1]); int x = lower_bound(_s + 1, _s + np + 1, s[i + 1]) - _s; if (dp[i][0] >= 0) A[0]._mdy(x, dp[i][0] + s[i + 1] - c[i + 1]), A[1]._mdy(x, dp[i][0] - c[i + 1]); if (dp[i][1] >= 0) A[2]._mdy(x, dp[i][1] + s[i + 1] - c[i + 1]), A[3]._mdy(x, dp[i][1] - c[i + 1]); } ans = max(ans, pre); ans = max(ans, A[1].query(1, np) + c[tp]); ans = max(ans, A[3].query(1, np) + c[tp]); printf( %lld , ans); } |
#include <bits/stdc++.h> using namespace std; long long n, i, rs, j; vector<long long> ball; vector<long long>::iterator pos; int main() { scanf( %lld , &n); for (i = 0; i < n; i++) scanf( %lld , &j), ball.push_back(j); sort(ball.begin(), ball.end()); rs = 0; i = 0; if (n % 2 == 0) { j = ball[0] + ball[1]; pos = lower_bound(ball.begin() + 2, ball.end(), j); ball.insert(pos, j); rs += j; i = 2; } for (; i < n - 1; i += 3) { j = ball[i] + ball[i + 1] + ball[i + 2]; pos = lower_bound(ball.begin() + i + 3, ball.end(), j); ball.insert(pos, j); rs += j; n++; } printf( %lld , rs); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31AI_BEHAVIORAL_V
`define SKY130_FD_SC_LP__O31AI_BEHAVIORAL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__o31ai (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31AI_BEHAVIORAL_V |
#include <bits/stdc++.h> using namespace std; const int maxn = 16, inf = 2e8 + 10; ; int n, m, dis[maxn][maxn], deg[maxn], ans, dp[1024 * 33]; vector<int> veci; void find(int a) { int cnt = 0; for (int i = 0; i < n; i++) if ((a >> i) & 1) cnt++; if (cnt % 2 == 1) return; for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) if (i != j && (a >> i) & 1 && (a >> j) & 1) { int ki = a; ki ^= (1 << i); ki ^= (1 << j); dp[a] = min(dp[a], dp[ki] + dis[veci[i]][veci[j]]); } } int main() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); fill_n(dis[0], maxn * maxn, inf); fill_n(dp, 1024 * 33, inf); cin >> n >> m; for (int i = 0; i < n; i++) dis[i][i] = 0; for (int i = 0; i < m; i++) { int u, v, w; cin >> u >> v >> w; u--, v--; deg[u]++, deg[v]++; ans += w; dis[u][v] = dis[v][u] = min(dis[u][v], w); } for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) for (int k = 0; k < n; k++) dis[j][k] = min(dis[j][k], dis[j][i] + dis[i][k]); for (int i = 0; i < n; i++) if (deg[i] > 0 && dis[i][0] == inf) return cout << -1, 0; else if (deg[i] % 2 == 1) veci.push_back(i); dp[0] = 0; for (int i = 0; i < (1 << (veci.size())); i++) find(i); cout << ans + dp[(1 << (veci.size())) - 1]; } |
#include <bits/stdc++.h> using namespace std; inline void pisz(int n) { printf( %d n , n); } template <typename T, typename TT> ostream &operator<<(ostream &s, pair<T, TT> t) { return s << ( << t.first << , << t.second << ) ; } template <typename T> ostream &operator<<(ostream &s, vector<T> t) { for (int(i) = 0; (i) < (((int)(t.size()))); ++(i)) s << t[i] << ; return s; } template <typename T, typename Aug> struct AugTreap { struct Node { T v; int pr; Node *le, *ri; Aug al, ag; }; Node *root; AugTreap() : root(0) {} inline static void recalc(Node *&n) { Aug left = n->le ? n->le->ag + n->al : n->al; n->ag = n->ri ? left + n->ri->ag : left; } inline void rotle(Node *&n) { Node *syn = n->le; n->le = syn->ri; syn->ri = n; n = syn; recalc(n->ri); recalc(n); } inline void rotri(Node *&n) { Node *syn = n->ri; n->ri = syn->le; syn->le = n; n = syn; recalc(n->le); recalc(n); } void insert_aux(Node *&n, const T &x, const Aug &aug) { if (!n) { n = new Node; n->v = x; n->pr = rand(); n->le = n->ri = 0; n->al = n->ag = aug; } else if (x < n->v) { insert_aux(n->le, x, aug); if (n->pr > n->le->pr) rotle(n); else recalc(n); } else if (x > n->v) { insert_aux(n->ri, x, aug); if (n->pr > n->ri->pr) rotri(n); else recalc(n); } else { n->al = n->al + aug; recalc(n); } } void insert(const T &x, const Aug &aug) { insert_aux(root, x, aug); } Aug sumgeq_aux(const T &x, Node *n) { if (!n) return Aug(); if (x > n->v) return sumgeq_aux(x, n->ri); if (x < n->v) { Aug left = sumgeq_aux(x, n->le) + n->al; return n->ri ? left + n->ri->ag : left; } return n->ri ? n->al + n->ri->ag : n->al; } Aug sumgeq(const T &x) { return sumgeq_aux(x, root); } }; long long a[100007], prefsum[100007]; int main() { long long n, k; cin >> n >> k; for (int(i) = 1; (i) <= (n); ++(i)) cin >> a[i]; prefsum[0] = 0; for (int(i) = 1; (i) <= (n); ++(i)) prefsum[i] = prefsum[i - 1] + a[i]; long long best = -1000000000; best *= 100000; long long from = best + 1, to = -best; while (from <= to) { long long x = (from + to) / 2; long long dobrychsum = 0, zab = 0; AugTreap<long long, int> tr; for (int(i) = 1; (i) <= (n); ++(i)) tr.insert(prefsum[i], 1); for (int(st) = 1; (st) <= (n); ++(st)) { dobrychsum += tr.sumgeq(x + zab); zab += a[st]; tr.insert(zab, -1); } if (dobrychsum >= k) { best = x; from = x + 1; } else { to = x - 1; } } cout << best; } |
/*******************************************************************************
* Module: simul_axi_read
* Date:2014-04-06
* Author: Andrey Filippov
* Description: simulation of read data through maxi channel
*
* Copyright (c) 2014 Elphel, Inc.
* simul_axi_read.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_axi_read.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module simul_axi_read #(
parameter ADDRESS_WIDTH=10
)(
input clk,
input reset,
input last, // last data word in burst
input data_stb, // data strobe (RVALID & RREADY) genearted externally
input [ADDRESS_WIDTH-1:0] raddr, // read burst address as written by axi master, 10 significant bits [11:2], valid at rcmd
input [ 3:0] rlen, // burst length as written by axi master, valid at rcmd
input rcmd, // read command (address+length) strobe
output [ADDRESS_WIDTH-1:0] addr_out, // output address
output burst, // burst in progress
output reg err_out); // data last does not match predicted or FIFO over/under run
wire [ADDRESS_WIDTH-1:0] raddr_fifo; // raddr after fifo
wire [ 3:0] rlen_fifo; // rlen after fifo
wire fifo_valid; // fifo out valid
reg burst_r=0;
reg [ 3:0] left_plus_1;
wire start_burst=fifo_valid && data_stb && !burst_r;
wire generated_last= burst?(left_plus_1==1): ( fifo_valid && (rlen_fifo==0)) ;
wire fifo_in_rdy;
wire error_w= (data_stb && (last != generated_last)) || (rcmd && !fifo_in_rdy) || (start_burst && !fifo_valid);
reg [ADDRESS_WIDTH-1:0] adr_out_r;
assign burst=burst_r || start_burst;
assign addr_out=start_burst?raddr_fifo:adr_out_r;
always @ (posedge reset or posedge clk) begin
if (reset) burst_r <= 0;
else if (start_burst) burst_r <= rlen_fifo!=0;
// else if (last && data_stb) burst_r <= 0;
else if (generated_last && data_stb) burst_r <= 0;
if (reset) left_plus_1 <= 0;
else if (start_burst) left_plus_1 <= rlen_fifo;
else if (data_stb) left_plus_1 <= left_plus_1-1;
if (reset) err_out <= 0;
else err_out <= error_w;
// if (reset) was_last <= 0;
// else if (data_stb) was_last <= last;
end
always @ (posedge clk) begin
if (start_burst) adr_out_r <= raddr_fifo+1; // simulating only address incremental mode
else if (data_stb) adr_out_r <= adr_out_r + 1;
end
simul_fifo
#(
.WIDTH(ADDRESS_WIDTH+4),
.DEPTH(64)
)simmul_fifo_i(
.clk(clk),
.reset(reset),
// .data_in({rlen[3:0],raddr[11:2]}), // did not detect raddr[11:2] for input [ 9:0] raddr
.data_in({rlen[3:0],raddr}),
.load(rcmd),
.input_ready(fifo_in_rdy),
.data_out({rlen_fifo, raddr_fifo}),
.valid(fifo_valid),
.ready(start_burst));
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: mast_new.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module mast_new (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites-new/masters_new.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites-new/masters_new.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mast_new.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mast_new.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mast_new.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mast_new.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mast_new_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mast_new_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int dp[2][505][505]; char mp[505][505]; const int mod = 1000000007; int dis(int a, int b, int c, int d) { return abs(a - c) + abs(b - d) <= 1; } int main() { int n, m; scanf( %d%d , &n, &m); for (int i = 0; i < n; i++) scanf( %s , mp[i]); if (mp[0][0] != mp[n - 1][m - 1]) { printf( 0 n ); return 0; } memset(dp, 0, sizeof(dp)); dp[0][0][n - 1] = 1; int t = n + m; t /= 2; int ans = 0; for (int i = 1; i < t; i++) { for (int j = 0; j < n; j++) { for (int k = n - 1; k >= j; k--) dp[i & 1][j][k] = 0; } for (int j = 0; j < n; j++) { for (int k = n - 1; k >= j; k--) { int m1 = i - j; int m2 = (n + m - 2 - k - i); if (m1 > m - 1) continue; if (m2 > m - 1) continue; if (mp[j][m1] != mp[k][m2]) continue; if (j > 0 && k < n - 1) dp[i & 1][j][k] += dp[!(i & 1)][j - 1][k + 1]; if (j > 0 && m2 < m - 1) dp[i & 1][j][k] += dp[!(i & 1)][j - 1][k]; if (dp[i & 1][j][k] >= mod) dp[i & 1][j][k] -= mod; if (m1 > 0 && k < n - 1) dp[i & 1][j][k] += dp[!(i & 1)][j][k + 1]; if (dp[i & 1][j][k] >= mod) dp[i & 1][j][k] -= mod; if (m1 > 0 && m2 < m - 1) dp[i & 1][j][k] += dp[!(i & 1)][j][k]; if (dp[i & 1][j][k] >= mod) dp[i & 1][j][k] -= mod; if (i == t - 1 && dis(j, m1, k, m2)) ans += dp[i & 1][j][k]; if (ans >= mod) ans -= mod; } } } printf( %d n , ans); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [19:0] in = crc[19:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [19:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[19:0]),
// Inputs
.in (in[19:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {44'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hdb7bc61592f31b99
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
typedef struct packed {
logic [7:0] cn;
logic vbfval;
logic vabval;
} rel_t;
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [19:0] in;
output [19:0] out;
rel_t [1:0] i; // From ifb0 of ifb.v, ...
rel_t [1:0] o; // From ifb0 of ifb.v, ...
assign i = in;
assign out = o;
sub sub
(
.i (i[1:0]),
.o (o[1:0]));
endmodule
module sub (/*AUTOARG*/
// Outputs
o,
// Inputs
i
);
input rel_t [1:0] i;
output rel_t [1:0] o;
assign o = i;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, nums[2201], ans = 0; cin >> n >> k; for (int i = 0; i < n; i++) { cin >> nums[i]; } sort(nums, nums + n); for (int i = 0; i < k; i++) { ans += nums[i]; } cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; long long int mod = 1e9 + 7; const double error = 1e-10; const double PI = acos(-1); inline long long int MOD(long long int x, long long int m = mod) { long long int y = x % m; return (y >= 0) ? y : y + m; } const int inf = INT_MAX; const long long int infl = LLONG_MAX; const int nmax = 1e5 + 3; int grundy[nmax], best[nmax]; vector<int> reach[nmax]; void dp() { for (int i = 1; i < nmax; i++) { sort(reach[i].begin(), reach[i].end()); int j, k; for (k = 0, j = 0; k < nmax; k++) { while (j < reach[i].size()) { if (reach[i][j] >= k) break; j++; } if (reach[i].size() == j || reach[i][j] > k) break; } grundy[i] = k; reach[i].clear(); int sum = 0, xorval = 0; for (int j = i; j > 0 && sum < nmax; j--) { sum += j; if (sum >= nmax) continue; xorval ^= grundy[j]; reach[sum].push_back(xorval); if (xorval == 0) best[sum] = i - j + 1; } } } int main() { int n; scanf( %d , &n); dp(); if (grundy[n] == 0) printf( -1 ); else printf( %d , best[n]); } |
#include <bits/stdc++.h> using namespace std; int n; vector<int> V; int solve() { V.clear(); cin >> n; for (int i = 0; i < n; ++i) { int a; cin >> a; V.emplace_back(a); } sort(V.begin(), V.end()); V.erase(unique(V.begin(), V.end()), V.end()); return V.size(); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); int t; cin >> t; while (t--) cout << solve() << n ; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_7_2 (
Din,
Dout
);
input wire [47 : 0] Din;
output wire [15 : 0] Dout;
xlslice #(
.DIN_WIDTH(48),
.DIN_FROM(44),
.DIN_TO(29)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.1.0 Build 185 10/21/2015 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [15:0] q;
output [7:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [15:0] sub_wire2;
wire [7:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [15:0] q = sub_wire2[15:0];
wire [7:0] usedw = sub_wire3[7:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.usedw (sub_wire3),
.aclr (),
.almost_empty (),
.almost_full (),
.eccstatus (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone V",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int n, x, y; vector<vector<int> > adjList(100009, vector<int>()); bool vis[100009]; vector<int> ans; bool check_valid_edges(vector<vector<int> > &a, int n) { for (size_t i = 1; i <= n; i++) if (a[i].size() != 4) return false; return true; } int comp(int node1, int node2) { int c = 0; for (int i = 0; i < adjList[node1].size(); i++) { for (int j = 0; j < adjList[node2].size(); j++) { if (adjList[node1][i] == adjList[node2][j]) c++; } } return c; } void dfs(int node) { vis[node] = true; bool f = true; for (int i = 0; i < adjList[node].size() && f; i++) { if (comp(node, adjList[node][i]) == 2 && !vis[adjList[node][i]]) ans.push_back(adjList[node][i]), dfs(adjList[node][i]), f = false; } } int main() { cin >> n; for (int i = 1; i <= (2 * n); i++) { cin >> x >> y; adjList[x].push_back(y); adjList[y].push_back(x); } if (!check_valid_edges(adjList, n)) return cout << -1 << endl, 0; if (n == 5) return cout << 1 2 3 4 5 n << endl, 0; else if (n == 6) { int s_node = 21; for (int i = 0; i < adjList[1].size(); i++) s_node -= adjList[1][i]; s_node--; cout << 1 << adjList[1][0] << << adjList[1][1] << << s_node << << adjList[1][2] << << adjList[1][3] << endl; ; } else { dfs(1); ans.push_back(1); if (ans.size() == n) for (int i = 0; i < ans.size(); i++) cout << ans[i] << ; else cout << -1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long N = 2e6 + 10; const long long mod = 1e9 + 7; struct Dsu { long long fa[N << 1], d[N << 1]; struct Tmp { long long x, y, add; }; stack<Tmp> s; long long find(long long x) { while (x != fa[x]) x = fa[x]; return x; } void init(long long n) { while (!s.empty()) s.pop(); for (long long i = 1; i <= n; i++) fa[i] = i, d[i] = 0; } void merge(long long x, long long y) { long long xx = find(x); long long yy = find(y); if (xx == yy) return; if (d[xx] > d[yy]) swap(xx, yy); s.push((Tmp){xx, yy, d[xx] == d[yy]}); fa[xx] = yy; d[yy] += (d[xx] == d[yy]); } void ret(long long o) { while (s.size() > o) { Tmp x = s.top(); fa[x.x] = x.x; d[x.y] -= x.add; s.pop(); } } } t; long long read() { long long x = 0, f = 1; char c = getchar(); while (c < 0 || c > 9 ) { if (c == - ) f = -1; c = getchar(); } while (c >= 0 && c <= 9 ) x = (x << 1) + (x << 3) + c - 0 , c = getchar(); return x * f; } long long c[N]; map<pair<long long, long long>, vector<pair<long long, long long>>> mp; int main() { long long n = read(), m = read(), k = read(); for (long long i = 1; i <= n; i++) c[i] = read(); vector<pair<long long, long long>> e(m + 1); t.init(2 * n); for (long long i = 1; i <= m; i++) e[i].first = read(), e[i].second = read(); vector<long long> z(k + 1); for (long long i = 1; i <= m; i++) { long long u = e[i].first, v = e[i].second; if (c[u] == c[v]) { long long x = t.find(u); long long y = t.find(v); if (x == y) { z[c[u]] = 1; } else { t.merge(u, v + n); t.merge(u + n, v); } } else { pair<long long, long long> tmp = {min(c[u], c[v]), max(c[v], c[u])}; mp[tmp].push_back({u, v}); } } long long res = 1ll * k * (k - 1) / 2; long long gg = 0; for (long long i = 1; i <= k; i++) if (z[i] == 1) gg++; res -= (gg) * (gg - 1) / 2 + gg * (k - gg); for (auto now : mp) { if (z[now.first.first] || z[now.first.second]) continue; auto tmp = now.second; long long o = t.s.size(); for (pair<long long, long long> qwq : tmp) { long long u = qwq.first; long long v = qwq.second; long long x = t.find(u); long long y = t.find(v); if (x == y) { res -= 1; break; } else { t.merge(u, v + n); t.merge(u + n, v); } } t.ret(o); } cout << res << endl; } |
#include <bits/stdc++.h> using namespace std; constexpr int MAXN = 3e5 + 5; constexpr int MAXW = 1e4 + 5; constexpr int MOD = 998244353; constexpr long long INF = 2e10; constexpr int LOG = 11; string s; vector<int> ans; int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> s; reverse(s.begin(), s.end()); while (!s.empty()) { if (s.back() == . ) { ans.push_back(0); s.pop_back(); } else { s.pop_back(); if (s.back() == - ) { ans.push_back(2); } else { ans.push_back(1); } s.pop_back(); } } for (auto p : ans) { cout << p; } return 0; } |
//
// Copyright (c) 1999 Steven Wilson ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always fork : id block_decl parallel_statements join
module main ;
reg [3:0] value1,value2,value3;
always fork : fork_id
reg [3:0] value4 ;
#5 begin
value4 = 0;
value1 = value4 + 1 ;
end
#10 value1 = value4 + 2;
join
initial
begin
value1 = 0;
value2 = 0;
#4 ;
if(value1 != 0)
begin
$display("FAILED - 3.1.12C always fork : id block_decl statements join (0)");
value2 = 1;
end
#2 ;
if(value1 != 1)
begin
$display("FAILED - 3.1.12C always fork : id block_decl statements join (1)");
value2 = 1;
end
#5 ;
if(value1 != 2)
begin
$display("FAILED - 3.1.12C always fork : id block_decl statements join (2)");
value2 = 1;
end
#5 ;
if(value1 != 1)
begin
$display("FAILED - 3.1.12C always fork : id block_decl statements join (3)");
value2 = 1;
end
if(value2 == 0) $display("PASSED");
$finish ;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, m, a, b; cin >> n >> m >> a >> b; if (n % m == 0) { cout << 0; } else { long long j = n % m; cout << min(j * b, (m - j) * a); } return 0; } |
`timescale 1ns / 1ps
/*
-- Module Name: test_engine_nic_output_block
-- Description: Bloque de salida de la interfaz de red. Se encarga de la
interaccion entre el elemento de procesamiento y el
router.
Este modulo toma el resultado del elemento de
procesamiento y lo empaquete en flits para su transporte
a travez de la red.
-- Dependencies: -- system.vh
-- test_engine_nic_output_control_unit.v
-- Parameters: -- CHANNEL_WIDTH: Numero de lineas de comunicacion
entre la interfaz de red y el
router.
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- 30 de noviembre 2015: Creacion
*/
`include "system.vh"
module test_engine_nic_output_block
(
input wire clk,
input wire reset,
// -- inputs from pn ----------------------------------------- >>>>>
input wire done_strobe_din,
input wire [(2* `CHANNEL_WIDTH)-1:0] wordC_din,
input wire [(2* `CHANNEL_WIDTH)-1:0] wordD_din,
input wire [`CHANNEL_WIDTH-1:0] shifted_header_din,
// -- to input block ----------------------------------------- >>>>>
output wire zero_credits_dout,
// -- output port -------------------------------------------- >>>>>
input wire credit_in_din,
output reg [`CHANNEL_WIDTH-1:0] output_channel_dout
);
/*
-- Instancia: test_engine_nic_output_control_unit
-- Descripcion: Unidad de control para el bloque de salida de la
interfaz de red. Este bloque se encarga de organizar la
salida de flits para su transporte por medio del router
de un nodo.
El control de creditos se encuentra implementado dentro
de este modulo.
*/
wire [2:0] output_selector;
test_engine_nic_output_control_unit test_engine_nic_output_control_unit
(
.clk (clk),
.reset (reset),
// -- inputs --------------------------------------------- >>>>>
.credit_in_din (credit_in_din),
.done_strobe_din (done_strobe_din),
// -- outputs -------------------------------------------- >>>>>
.zero_credits_dout (zero_credits_dout),
.output_selector_dout (output_selector)
);
/*
-- Registros
-- Descripcion: Registros de captura del resultado del elemento de
procesamiento. Estos registros (64 bits c/u)
almacenan el resultado del procesamiento, previo a
su liberacion a la red.
*/
reg [(2* `CHANNEL_WIDTH)-1:0] wordC_reg;
reg [(2* `CHANNEL_WIDTH)-1:0] wordD_reg;
always @(posedge clk)
if (done_strobe_din)
wordC_reg <= wordC_din;
always @(posedge clk)
if (done_strobe_din)
wordD_reg <= wordD_din;
/*
-- Multiplexor
-- Descripcion: Multiplexor para la seleccion del flit que saldra
a la red durante el siguiente ciclo de reloj.
Los datos de entrada para el multiplexor, son los
registros de resultado del PE y el flit de cabecera
modificado.
Si no existe transito de flits el multiplexor, este
mantiene el canal de salida en un valor de 0.
*/
always @(*)
begin
output_channel_dout = {`CHANNEL_WIDTH{1'b0}};
case (output_selector)
3'b101: output_channel_dout = shifted_header_din;
3'b100: output_channel_dout = wordC_reg[`CHANNEL_WIDTH-1:0]; //-- Flit de datos 1
3'b011: output_channel_dout = wordC_reg[(2 * `CHANNEL_WIDTH)-1:`CHANNEL_WIDTH]; //-- Flit de datos 2
3'b010: output_channel_dout = wordD_reg[`CHANNEL_WIDTH-1:0]; //-- Flit de datos 3
3'b001: output_channel_dout = wordD_reg[(2 * `CHANNEL_WIDTH)-1:`CHANNEL_WIDTH]; //-- Flit de datos 4
3'b000: output_channel_dout = {`CHANNEL_WIDTH{1'b0}};
endcase
end
endmodule
/* -- Plantilla de instancia ------------------------------------- >>>>>
test_engine_nic_output_block nic_output_block
(
.clk (clk),
.reset (reset),
// -- inputs from PE ----------------------------------------- >>>>>
.done_strobe_din (done_strobe_din),
.wordC_din (wordC_din),
.wordD_din (wordD_din),
.shifted_header_din (shifted_header_din),
// -- to input block ----------------------------------------- >>>>>
.zero_credits_dout (zero_credits_dout),
// -- output port -------------------------------------------- >>>>>
.credit_in_din (credit_in_din),
.output_channel_dout (output_channel_dout)
);
*/ |
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6; int N; long long A[MAXN + 10], B[MAXN + 10], S; vector<long long> prime; int main() { long long i, j; scanf( %d , &N); for (i = 1; i <= N; i++) scanf( %d , &A[i]), S += A[i]; for (i = 2; i * i <= S; i++) { if (S % i == 0) { prime.push_back(i); while (S % i == 0) S /= i; } } if (S != 1) prime.push_back(S); long long ans = 1e18; for (auto now : prime) { long long aaa = 0; for (i = 1; i <= N; i++) B[i] = A[i]; vector<long long> V; long long S = 0; for (i = 1; i <= N; i++) B[i] %= now; for (i = 1; i <= N; i++) { if (S + B[i] >= now) V.push_back(now - S), S += now - S; else V.push_back(B[i]), S += B[i]; B[i] -= V.back(); if (S == now) { long long t = 0; for (j = 0; j < V.size(); j++) { t += V[j]; if (t >= (now + 1) / 2) break; } long long pos = j; for (j = 0; j < V.size(); j++) aaa += abs(pos - j) * V[j]; V.clear(); V.push_back(B[i]); S = B[i]; } } ans = min(ans, aaa); } if (ans == 1e18) ans = -1; printf( %lld , ans); } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__OR4_FUNCTIONAL_V
/**
* or4: 4-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__or4 (
X,
A,
B,
C,
D
);
// Module ports
output X;
input A;
input B;
input C;
input D;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, D, C, B, A );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_PP_BLACKBOX_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; using pii = pair<int, int>; using ll = long long; using llu = long long unsigned; using ld = long double; const ld EPS = 1e-9; inline int cmp(ld first, ld second = 0, ld tol = EPS) { return (first <= second + tol) ? (first + tol < second) ? -1 : 0 : 1; } const int MOD = 1; inline int mod(ll first, int m = MOD) { return (int)(((first % m) + m) % m); } const int N = 2e5 + 10; int n, m; ll first[N], chg[N], one[N]; int main() { scanf( %d %d , &n, &m); for (int i = 0; i < m; i++) scanf( %lld , &first[i]); ll base = 0; for (int i = 1; i < m; i += 2) { base += abs(first[i] - first[i - 1]); if (i < m - 1) base += abs(first[i] - first[i + 1]); } for (int i = 0; i < m; i++) { if (i < m - 1) { if (first[i + 1] > first[i]) { chg[first[i]]--; one[first[i]] += first[i] - 1; } if (first[i + 1] < first[i]) { chg[first[i]]++; ll dBef = abs(first[i] - (first[i + 1] + 1)); ll dNow = abs(1 - (first[i + 1] + 1)); one[first[i]] += (dNow - dBef); } } if (i) { if (first[i - 1] > first[i]) { chg[first[i]]--; one[first[i]] += first[i] - 1; } if (first[i - 1] < first[i]) { chg[first[i]]++; ll dBef = abs(first[i] - (first[i - 1] + 1)); ll dNow = abs(1 - (first[i - 1] + 1)); one[first[i]] += (dNow - dBef); } } } for (int i = 1; i <= n; i++) { printf( %lld , base); base -= one[i]; base += chg[i] + one[i + 1]; } putchar( n ); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBN_TB_V
`define SKY130_FD_SC_MS__SDFBBN_TB_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfbbn.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 SET_B = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 D = 1'b1;
#220 RESET_B = 1'b1;
#240 SCD = 1'b1;
#260 SCE = 1'b1;
#280 SET_B = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 D = 1'b0;
#400 RESET_B = 1'b0;
#420 SCD = 1'b0;
#440 SCE = 1'b0;
#460 SET_B = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 SET_B = 1'b1;
#660 SCE = 1'b1;
#680 SCD = 1'b1;
#700 RESET_B = 1'b1;
#720 D = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 SET_B = 1'bx;
#840 SCE = 1'bx;
#860 SCD = 1'bx;
#880 RESET_B = 1'bx;
#900 D = 1'bx;
end
// Create a clock
reg CLK_N;
initial
begin
CLK_N = 1'b0;
end
always
begin
#5 CLK_N = ~CLK_N;
end
sky130_fd_sc_ms__sdfbbn dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK_N(CLK_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBN_TB_V
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; int main() { ios_base::sync_with_stdio(0); cin.tie(0); ; int n, k; cin >> n >> k; vector<int> a(n); for (int &x : a) cin >> x; bool can = true; for (int i = k; i < n; ++i) { if (a[i] != a[k - 1]) { can = false; break; } } if (can) { int head = k - 2; while (head >= 0 && a[head] == a[k - 1]) head--; cout << head + 1; } else cout << -1; return 0; } |
module register_file
(
input clk, rst, w_en,
input [3:0] addr_a, addr_b, addr_c, addr_d,
input [15:0] data_c,
output reg [15:0] data_a, data_b, data_d
);
//`define addr_size 4
wire w_en0, w_en1, w_en2, w_en3, w_en4, w_en5, w_en6, w_en7, w_en8, w_en9, w_enA, w_enB, w_enC, w_enD, w_enE, w_enF;
wire [15:0] data0, data1, data2, data3, data4, data5, data6, data7, data8, data9, dataA, dataB, dataC, dataD, dataE, dataF;
register register0(clk, rst ,w_en0, data_c, data0);
register register1(clk, rst ,w_en1, data_c, data1);
register register2(clk, rst ,w_en2, data_c, data2);
register register3(clk, rst ,w_en3, data_c, data3);
register register4(clk, rst ,w_en4, data_c, data4);
register register5(clk, rst ,w_en5, data_c, data5);
register register6(clk, rst ,w_en6, data_c, data6);
register register7(clk, rst ,w_en7, data_c, data7);
register register8(clk, rst ,w_en8, data_c, data8);
register register9(clk, rst ,w_en9, data_c, data9);
register register10(clk, rst ,w_enA, data_c, dataA);
register register11(clk, rst ,w_enB, data_c, dataB);
register register12(clk, rst ,w_enC, data_c, dataC);
register register13(clk, rst ,w_enD, data_c, dataD);
register register14(clk, rst ,w_enE, data_c, dataE);
register register15(clk, rst ,w_enF, data_c, dataF);
assign w_en0 = (addr_c == 4'h0) & w_en ? 1'b1 : 1'b0;
assign w_en1 = (addr_c == 4'h1) & w_en ? 1'b1 : 1'b0;
assign w_en2 = (addr_c == 4'h2) & w_en ? 1'b1 : 1'b0;
assign w_en3 = (addr_c == 4'h3) & w_en ? 1'b1 : 1'b0;
assign w_en4 = (addr_c == 4'h4) & w_en ? 1'b1 : 1'b0;
assign w_en5 = (addr_c == 4'h5) & w_en ? 1'b1 : 1'b0;
assign w_en6 = (addr_c == 4'h6) & w_en ? 1'b1 : 1'b0;
assign w_en7 = (addr_c == 4'h7) & w_en ? 1'b1 : 1'b0;
assign w_en8 = (addr_c == 4'h8) & w_en ? 1'b1 : 1'b0;
assign w_en9 = (addr_c == 4'h9) & w_en ? 1'b1 : 1'b0;
assign w_enA = (addr_c == 4'ha) & w_en ? 1'b1 : 1'b0;
assign w_enB = (addr_c == 4'hb) & w_en ? 1'b1 : 1'b0;
assign w_enC = (addr_c == 4'hc) & w_en ? 1'b1 : 1'b0;
assign w_enD = (addr_c == 4'hd) & w_en ? 1'b1 : 1'b0;
assign w_enE = (addr_c == 4'he) & w_en ? 1'b1 : 1'b0;
assign w_enF = (addr_c == 4'hf) & w_en ? 1'b1 : 1'b0;
always@(*) begin
case(addr_a)
4'h0:
data_a = data0;
4'h1:
data_a = data1;
4'h2:
data_a = data2;
4'h3:
data_a = data3;
4'h4:
data_a = data4;
4'h5:
data_a = data5;
4'h6:
data_a = data6;
4'h7:
data_a = data7;
4'h8:
data_a = data8;
4'h9:
data_a = data9;
4'ha:
data_a = dataA;
4'hb:
data_a = dataB;
4'hc:
data_a = dataC;
4'hd:
data_a = dataD;
4'he:
data_a = dataE;
4'hf:
data_a = dataF;
endcase
case(addr_b)
4'h0:
data_b = data0;
4'h1:
data_b = data1;
4'h2:
data_b = data2;
4'h3:
data_b = data3;
4'h4:
data_b = data4;
4'h5:
data_b = data5;
4'h6:
data_b = data6;
4'h7:
data_b = data7;
4'h8:
data_b = data8;
4'h9:
data_b = data9;
4'ha:
data_b = dataA;
4'hb:
data_b = dataB;
4'hc:
data_b = dataC;
4'hd:
data_b = dataD;
4'he:
data_b = dataE;
4'hf:
data_b = dataF;
endcase
case(addr_d)
4'h0:
data_d = data0;
4'h1:
data_d = data1;
4'h2:
data_d = data2;
4'h3:
data_d = data3;
4'h4:
data_d = data4;
4'h5:
data_d = data5;
4'h6:
data_d = data6;
4'h7:
data_d = data7;
4'h8:
data_d = data8;
4'h9:
data_d = data9;
4'ha:
data_d = dataA;
4'hb:
data_d = dataB;
4'hc:
data_d = dataC;
4'hd:
data_d = dataD;
4'he:
data_d = dataE;
4'hf:
data_d = dataF;
endcase
end
endmodule
|
//---------------------------------------------------------------------//
// Name: am_put_fpga.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Computes the exercise price.
//---------------------------------------------------------------------//
module compute_vex(
clk,
nrst,
start,
log_lambda_up,
log_lambda_down,
K_over_S,
v_ex,
wraddr,
wren,
done
);
input clk;
input nrst;
input start;
input [63:0] log_lambda_up;
input [63:0] log_lambda_down;
input [63:0] K_over_S;
output [63:0] v_ex;
output [9:0] wraddr;
output [63:0]wren;
output done;
//---------------------------------------------------------------------//
// Wires
//---------------------------------------------------------------------//
reg [63:0] latched_log_lambda_up;
reg [63:0] latched_log_lambda_down;
reg [63:0] v_ex;
wire [63:0] mult_result;
wire [63:0] exp_result;
wire [63:0] sub_result;
wire [63:0] index_fp;
reg clk_en;
reg cnt_en;
reg [12:0] timer1;
reg [6:0] timer2;
reg [13:0] counter1;
reg [13:0] counter2;
reg [63:0] wren;
wire t1_expire = timer1[12];
wire t2_expire = timer2[6];
reg second_half;
wire first_half_done = (timer1 == 0); // Pulse signal.
assign wraddr[9:0] = counter2[12:3];
// Delay the 'second half' signal by 5 cycles to select for multiply.
reg [4:0]delay;
always@(posedge clk) delay <= {delay[3:0], second_half};
//---------------------------------------------------------------------//
// Instantiations
//---------------------------------------------------------------------//
int_to_fp int_to_fp_inst (
.clk_en(clk_en),
.clock(clk ),
.dataa({20'b0, second_half ? timer1[11:0] : counter1[11:0]}),
.result (index_fp)
);
fp_mult_slow stage1_multiply(
.clk_en(clk_en),
.clock(clk),
.dataa( delay[4] ? latched_log_lambda_down:latched_log_lambda_up ),
.datab(index_fp),
.result(mult_result)
);
fp_exp stage1_exponent (
.clk_en(clk_en),
.clock(clk),
.data(mult_result),
.result(exp_result)
);
fp_sub stage1_sub (
.clk_en(clk_en),
.clock(clk ),
.dataa(K_over_S),
.datab(exp_result),
.result(sub_result)
);
//---------------------------------------------------------------------//
// Control Logic.
//---------------------------------------------------------------------//
// Latch log_lambda_up.
always@(posedge clk)
if(~nrst) latched_log_lambda_up <= 64'h0;
else if(start) latched_log_lambda_up <= log_lambda_up;
else latched_log_lambda_up <= latched_log_lambda_up;
// Latch log_lambda_down.
always@(posedge clk)
if(~nrst) latched_log_lambda_down <= 64'h0;
else if(start) latched_log_lambda_down <= log_lambda_down;
else latched_log_lambda_down <= latched_log_lambda_down;
// Latch for clock enable.
always@(posedge clk)
if(~nrst) clk_en <= 1'b0;
else if(start) clk_en <= 1'b1;
else if(counter2 == 14'd8000) clk_en <= 1'b0;
// else if(counter2 == 14'd160) clk_en <= 1'b0;
// Latch for count enable.
always@(posedge clk)
if(~nrst) cnt_en <= 1'b0;
else if(start) cnt_en <= 1'b1;
else if(counter1 == 14'd3999) cnt_en <= 1'b0;
// else if(counter1 == 14'd79) cnt_en <= 1'b0;
// Latch first_half_done.
always@(posedge clk)
if(~nrst) second_half <= 1'b1;
else if(start) second_half <= 1'b1;
else if(first_half_done) second_half <= 1'b0;
// Assign output based on sign of subtraction result.
always@(posedge clk)
begin
if(sub_result[63]) v_ex[63:0] <= 64'h0000000000000000; // Negative.
else v_ex[63:0] <= sub_result[63:0]; // Positive or 0.
// Debug code, to put incremental into memory.
// if(start) v_ex[63:0] <= 63'd0;
// else v_ex <= v_ex + 1;
end
// One-hot counter for write enable.
always@(posedge clk)
if (~nrst) wren <= 64'h0000000000000000;
else if(~clk_en) wren <= 64'h0000000000000000;
else if(timer2 == 0) wren <= 64'h0000000000000001;
else begin
wren <= {wren[62:0], wren[63]};
end
//---------------------------------------------------------------------//
// Timers and Counters
//---------------------------------------------------------------------//
// Timer T1
// - Counts down from 4000, then back up.
// - Stops counting when it reaches -1.
always @(posedge clk)
if (~nrst) timer1 <= -1;
else if(start) timer1 <= {1'b0,12'd4000};
//else if(start) timer1 <= {1'b0,12'd80};
else if(cnt_en && !t1_expire) timer1 <= timer1 - 1;
// Timer T2
// - Counts down from 47 (for 48 cycle latency).
// - Stops counting when it reaches -1.
always @(posedge clk)
if (~nrst) timer2 <= -1;
else if(start) timer2 <= {1'b0,6'b101110};
else if(clk_en && !t2_expire) timer2 <= timer2 - 1;
// Counter C1
// Count up from 0 to 4000;
always @(posedge clk)
if(~nrst) counter1 <= -1;
else if(first_half_done) counter1 <= 1;
else if(cnt_en && t1_expire) counter1 <= counter1 + 1;
// Counter C2
// - Counts from 0 to 8000;
// - Output is used as address + channel selection.
always @(posedge clk)
if (~nrst) counter2 <= 0;
else if(start) counter2 <= 0;
else if(clk_en && t2_expire) counter2 <= counter2 + 1;
// State machine to pulse 'done' when finished.
reg [1:0] state;
assign done = state[1];
always@(posedge clk)
if(!nrst) state <= 2'b00;
else if(start) state <= 2'b01;
else if((state == 2'b01) && ~clk_en) state <= 2'b10;
else if(state == 2'b10) state <= 2'b00;
endmodule |
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