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// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// one-way bidirectional connection:
// altera message_off 10665
module acl_ic_master_endpoint
#(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
parameter integer TOTAL_NUM_MASTERS = 1, // > 0
parameter integer ID = 0 // [0..2^ID_W-1]
)
(
input logic clock,
input logic resetn,
acl_ic_master_intf m_intf,
acl_arb_intf arb_intf,
acl_ic_wrp_intf wrp_intf,
acl_ic_rrp_intf rrp_intf
);
// Pass-through arbitration data.
assign arb_intf.req = m_intf.arb.req;
assign m_intf.arb.stall = arb_intf.stall;
generate
if( TOTAL_NUM_MASTERS > 1 )
begin
// There shouldn't be any truncation, but be explicit about the id width.
logic [ID_W-1:0] id = ID;
// Write return path.
assign m_intf.wrp.ack = wrp_intf.ack & (wrp_intf.id == id);
// Read return path.
assign m_intf.rrp.datavalid = rrp_intf.datavalid & (rrp_intf.id == id);
assign m_intf.rrp.data = rrp_intf.data;
end
else // TOTAL_NUM_MASTERS == 1
begin
// Only one master driving the entire interconnect, so there's no need
// to check the id.
// Write return path.
assign m_intf.wrp.ack = wrp_intf.ack;
// Read return path.
assign m_intf.rrp.datavalid = rrp_intf.datavalid;
assign m_intf.rrp.data = rrp_intf.data;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 5; const int M = 1e7 + 1; const long long INF = 1LL << 61; long long a[N], t[N], cost[N]; inline long long bs(long long bytes, long long maxt) { long long res = -1; if (t[0] <= t[2]) { if ((t[0] * bytes) <= maxt) { res = 0; } return res; } if (bytes <= 0) { return 0; } int l = 0; int r = M; while (l <= r) { int mid = l + (r - l) / 2; long long b_left = bytes - mid * a[2]; long long t_left = maxt - mid * a[2] * t[2]; if (b_left < 0) { if (llabs(b_left) < a[2]) { t_left += (b_left * (-t[2])); b_left = 0; } else { r = mid - 1; continue; } } t_left -= (b_left * t[0]); if (t_left >= 0) { res = mid; r = mid - 1; } else { l = mid + 1; } } return res; } int main() { ios_base::sync_with_stdio(false); long long size, maxt; cin >> size >> maxt; cin >> t[0]; for (int i = int(1); i < int(3); i++) { cin >> a[i] >> t[i] >> cost[i]; } if (t[2] < t[1]) { swap(a[1], a[2]); swap(t[1], t[2]); swap(cost[1], cost[2]); } long long ans = INF; for (int i = int(0); i < int(M); i++) { long long money = i * cost[1]; long long bytes = size - i * a[1]; long long tt = maxt - (i * a[1] * t[1]); if (bytes > 0) { long long use2 = bs(bytes, tt); money += (use2 * cost[2]); if (use2 >= 0) { ans = min(ans, money); } } else if (bytes < 0) { tt += (bytes * (-t[1])); } if (bytes <= 0 and tt >= 0) { ans = min(ans, money); } } if (ans >= INF) { ans = -1; } cout << ans << n ; return 0; } |
#include <algorithm> #include <cassert> #include <iostream> #include <queue> #include <vector> using namespace std; typedef long long ll; typedef pair<int, int> Pii; typedef vector<Pii> VPii; typedef vector<int> Vi; typedef vector<Vi> VVi; typedef vector<ll> Vll; typedef vector<Vll> VVll; const ll INF = 1000000000000000000LL; Vi toposort(const VVi& g) { int n = g.size(); Vi deg(n); for (auto& others : g) { for (int other : others) { ++deg[other]; } } queue<int> q; for (int i = 0; i < n; ++i) { if (deg[i] == 0) { q.push(i); } } Vi result; while (!q.empty()) { int x = q.front(); q.pop(); result.push_back(x); for (int other : g[x]) { if (--deg[other] == 0) { q.push(other); } } } return result; } Vi findPath(int start, const VVi& rg, Vi& target, const VVi& ban) { int n = rg.size(); VVi prev(2, Vi(n, -1)); prev[0][start] = start; queue<Pii> q; q.push(make_pair(0, start)); int finish = -1; while (!q.empty()) { int d = q.front().first; int x = q.front().second; q.pop(); if (d == 0) { if (ban[0][x] == 1) { continue; } for (int y : rg[x]) { if (ban[1][y] == 1) { continue; } if (target[y] != x && prev[1][y] == -1) { prev[1][y] = x; q.push(make_pair(1, y)); } } } else { int y = target[x]; if (y == -1) { finish = x; break; } if (prev[0][y] == -1) { prev[0][y] = x; q.push(make_pair(0, y)); } } } if (finish == -1) { return Vi(); } Vi path; for (int d = 1, x = finish; x != start; x = prev[d][x], d = 1 - d) { path.push_back(x); } path.push_back(start); reverse(path.begin(), path.end()); return path; } int minSeeds(const VVi& g, const VVi& rg, const VVi& ban) { int n = g.size(); int seeds = 0; Vi target(n, -1); Vi order = toposort(g); for (int x : order) { auto path = findPath(x, rg, target, ban); if (path.empty()) { ++seeds; } assert(path.size() % 2 == 0); for (int i = 0; i + 1 < path.size(); i += 2) { int a = path[i]; int b = path[i + 1]; target[b] = a; } } return seeds; } Pii nextBan(int currentSeeds, const VVi& g, const VVi& rg, VVi ban) { int n = g.size(); for (int d = 0; d < 2; ++d) { for (int x = 0; x < n; ++x) { if (ban[d][x] == 1) { continue; } ban[d][x] = 1; int t = minSeeds(g, rg, ban); if (t == currentSeeds + 1) { return make_pair(d, x); } ban[d][x] = 0; } } assert(false); } VPii optimalSequence(const VVi& g, const VVi& rg) { int n = g.size(); VVi ban(2, Vi(n, 0)); int m = minSeeds(g, rg, ban); VPii result; for (int i = 0; i < n - m; ++i) { auto t = nextBan(m + i, g, rg, ban); result.push_back(t); ban[t.first][t.second] = 1; } return result; } Vi optimalPattern(int initial, int n, VPii& cost) { int k = cost.size(); VVll dp(k + 1, Vll(n + 1)); VVi next(k + 1, Vi(n + 1)); for (int r = k - 1; r >= 0; --r) { for (int s = initial; s <= n; ++s) { ll bestScore = 0; int bestT = -1; for (int t = max(s, r + 2); t <= n; ++t) { int c = t - s; ll score = max(0LL, cost[r].first - ll(c) * cost[r].second) + dp[r + 1][t]; if (bestT == -1 || score > bestScore) { bestT = t; bestScore = score; } } dp[r][s] = bestScore; next[r][s] = bestT; } } Vi pattern; for (int r = 0, s = initial; r < k; s = next[r][s], ++r) { pattern.push_back(next[r][s] - s); } return pattern; } int main() { int n, m, k; cin >> n >> m >> k; VVi g(n), rg(n); for (int i = 0; i < m; ++i) { int x, y; cin >> x >> y; --x; --y; g[x].push_back(y); rg[y].push_back(x); } VPii cost(k); for (int i = 0; i < k; ++i) { cin >> cost[i].first >> cost[i].second; } auto seq = optimalSequence(g, rg); int initial = n - seq.size(); auto patt = optimalPattern(initial, n, cost); Vi solution; int used = 0; for (int p : patt) { for (int i = 0; i < p; ++i) { auto s = seq[used++]; int sign = s.first == 0 ? -1 : 1; solution.push_back(sign * (s.second + 1)); } solution.push_back(0); } cout << solution.size() << endl; for (int i = 0; i < solution.size(); ++i) { if (i != 0) { cout << ; } cout << solution[i]; } cout << endl; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__NAND3_BEHAVIORAL_PP_V
/**
* nand3: 3-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y , B, A, C );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_BEHAVIORAL_PP_V |
#include<bits/stdc++.h> using namespace std; typedef long long int ll; void solve(void); int main(){ int t; cin>>t; while(t--){ solve(); } return 0;} void solve(){ ll n,i; cin>>n; ll a[n+1]; for(i=1;i<=n;i++) {cin>>a[i]; } cout<<3*n<<endl; for(i=1;i<n;i++) { cout<< 1 << <<i<< <<i+1<<endl; cout<< 2 << <<i<< <<i+1<<endl; cout<< 1 << <<i<< <<i+1<<endl; cout<< 2 << <<i<< <<i+1<<endl; cout<< 1 << <<i<< <<i+1<<endl; cout<< 2 << <<i<< <<i+1<<endl; i++; } } |
/*!
btcminer -- BTCMiner for ZTEX USB-FPGA Modules: HDL code: hash pipelines
Copyright (C) 2011 ZTEX GmbH
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
`define E0(x) ( {{x}[1:0],{x}[31:2]} ^ {{x}[12:0],{x}[31:13]} ^ {{x}[21:0],{x}[31:22]} )
`define E1(x) ( {{x}[5:0],{x}[31:6]} ^ {{x}[10:0],{x}[31:11]} ^ {{x}[24:0],{x}[31:25]} )
`define CH(x,y,z) ( (z) ^ ((x) & ((y) ^ (z))) )
`define MAJ(x,y,z) ( ((x) & (y)) | ((z) & ((x) | (y))) )
`define S0(x) ( { {x}[6:4] ^ {x}[17:15], {{x}[3:0], {x}[31:7]} ^ {{x}[14:0],{x}[31:18]} ^ {x}[31:3] } )
`define S1(x) ( { {x}[16:7] ^ {x}[18:9], {{x}[6:0], {x}[31:17]} ^ {{x}[8:0],{x}[31:19]} ^ {x}[31:10] } )
module sha256_pipe2_base ( clk, i_state, i_data, out );
parameter STAGES = 64;
input clk;
input [255:0] i_state;
input [511:0] i_data;
output [255:0] out;
localparam Ks = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'h243185be, 32'h550c7dc3,
32'h72be5d74, 32'h80deb1fe, 32'h9bdc06a7, 32'hc19bf174,
32'he49b69c1, 32'hefbe4786, 32'h0fc19dc6, 32'h240ca1cc,
32'h2de92c6f, 32'h4a7484aa, 32'h5cb0a9dc, 32'h76f988da,
32'h983e5152, 32'ha831c66d, 32'hb00327c8, 32'hbf597fc7,
32'hc6e00bf3, 32'hd5a79147, 32'h06ca6351, 32'h14292967,
32'h27b70a85, 32'h2e1b2138, 32'h4d2c6dfc, 32'h53380d13,
32'h650a7354, 32'h766a0abb, 32'h81c2c92e, 32'h92722c85,
32'ha2bfe8a1, 32'ha81a664b, 32'hc24b8b70, 32'hc76c51a3,
32'hd192e819, 32'hd6990624, 32'hf40e3585, 32'h106aa070,
32'h19a4c116, 32'h1e376c08, 32'h2748774c, 32'h34b0bcb5,
32'h391c0cb3, 32'h4ed8aa4a, 32'h5b9cca4f, 32'h682e6ff3,
32'h748f82ee, 32'h78a5636f, 32'h84c87814, 32'h8cc70208,
32'h90befffa, 32'ha4506ceb, 32'hbef9a3f7, 32'hc67178f2
};
genvar i;
generate
for (i = 0; i <= STAGES; i = i + 1) begin : S
reg [511:0] data;
reg [223:0] state;
reg [31:0] t1_p1;
if(i == 0)
begin
always @ (posedge clk)
begin
data <= i_data;
state <= i_state[223:0];
t1_p1 <= i_state[`IDX(7)] + i_data[`IDX(0)] + Ks[`IDX(63)];
end
end else
begin
reg [511:0] data_buf;
reg [223:0] state_buf;
reg [31:0] data15_p1, data15_p2, data15_p3, t1;
always @ (posedge clk)
begin
data_buf <= S[i-1].data;
data[479:0] <= data_buf[511:32];
data15_p1 <= `S1( S[i-1].data[`IDX(15)] ); // 3
data15_p2 <= data15_p1; // 1
data15_p3 <= ( ( i == 1 ) ? `S1( S[i-1].data[`IDX(14)] ) : S[i-1].data15_p2 ) + S[i-1].data[`IDX(9)] + S[i-1].data[`IDX(0)]; // 3
data[`IDX(15)] <= `S0( data_buf[`IDX(1)] ) + data15_p3; // 4
state_buf <= S[i-1].state; // 2
t1 <= `CH( S[i-1].state[`IDX(4)], S[i-1].state[`IDX(5)], S[i-1].state[`IDX(6)] ) + `E1( S[i-1].state[`IDX(4)] ) + S[i-1].t1_p1; // 6
state[`IDX(0)] <= `MAJ( state_buf[`IDX(0)], state_buf[`IDX(1)], state_buf[`IDX(2)] ) + `E0( state_buf[`IDX(0)] ) + t1; // 7
state[`IDX(1)] <= state_buf[`IDX(0)]; // 1
state[`IDX(2)] <= state_buf[`IDX(1)]; // 1
state[`IDX(3)] <= state_buf[`IDX(2)]; // 1
state[`IDX(4)] <= state_buf[`IDX(3)] + t1; // 2
state[`IDX(5)] <= state_buf[`IDX(4)]; // 1
state[`IDX(6)] <= state_buf[`IDX(5)]; // 1
t1_p1 <= state_buf[`IDX(6)] + data_buf[`IDX(1)] + Ks[`IDX((127-i) & 63)]; // 2
end
end
end
endgenerate
reg [31:0] state7, state7_buf;
always @ (posedge clk)
begin
state7_buf <= S[STAGES-1].state[`IDX(6)];
state7 <= state7_buf;
end
assign out[223:0] = S[STAGES].state;
assign out[255:224] = state7;
endmodule
module sha256_pipe130 ( clk, state, state2, data, hash );
input clk;
input [255:0] state, state2;
input [511:0] data;
output reg [255:0] hash;
wire [255:0] out;
sha256_pipe2_base #( .STAGES(64) ) P (
.clk(clk),
.i_state(state),
.i_data(data),
.out(out)
);
always @ (posedge clk)
begin
hash[`IDX(0)] <= state2[`IDX(0)] + out[`IDX(0)];
hash[`IDX(1)] <= state2[`IDX(1)] + out[`IDX(1)];
hash[`IDX(2)] <= state2[`IDX(2)] + out[`IDX(2)];
hash[`IDX(3)] <= state2[`IDX(3)] + out[`IDX(3)];
hash[`IDX(4)] <= state2[`IDX(4)] + out[`IDX(4)];
hash[`IDX(5)] <= state2[`IDX(5)] + out[`IDX(5)];
hash[`IDX(6)] <= state2[`IDX(6)] + out[`IDX(6)];
hash[`IDX(7)] <= state2[`IDX(7)] + out[`IDX(7)];
end
endmodule
module sha256_pipe123 ( clk, data, hash );
parameter state = 256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667;
input clk;
input [511:0] data;
output [31:0] hash;
wire [255:0] out;
sha256_pipe2_base #( .STAGES(61) ) P (
.clk(clk),
.i_state(state),
.i_data(data),
.out(out)
);
assign hash = out[`IDX(4)];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/26/2016 07:00:53 AM
// Design Name:
// Module Name: Adder_Round
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Adder_Round
#(parameter SW=26) (
input wire clk,
input wire rst,
input wire load_i,//Reg load input
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
/////////////////////////////////////////////////////////////
output wire [SW-1:0] Data_Result_o,
output wire FSM_C_o
);
wire [SW:0] result_A_adder;
adder #(.W(SW)) A_operation (
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.Data_S_o(result_A_adder)
);
RegisterAdd #(.W(SW)) Add_Subt_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (result_A_adder[SW-1:0]),
.Q (Data_Result_o)
);
RegisterAdd #(.W(1)) Add_overflow_Result(
.clk (clk),
.rst (rst),
.load (load_i),
.D (result_A_adder[SW]),
.Q (FSM_C_o)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; using ll = long long; using ld = long double; template <typename T> T &chmin(T &a, const T &b) { return a = min(a, b); } template <typename T> T &chmax(T &a, const T &b) { return a = max(a, b); } template <typename T> T inf; template <> constexpr int inf<int> = 1e9; template <> constexpr ll inf<ll> = 1e18; template <> constexpr ld inf<ld> = 1e30; struct yes_no : numpunct<char> { string_type do_truename() const { return Yes ; } string_type do_falsename() const { return No ; } }; int res[300010]; bool visited[300010]; vector<int> s[300010]; vector<int> g[300010]; void get_col(vector<int> &vec, int &pos, int &res) { ++res; while (pos < int(vec.size()) && vec[pos] == res) ++pos, ++res; } void dfs(int v) { vector<int> vec; for (int i : s[v]) { if (res[i] == 0) continue; vec.push_back(res[i]); } sort((vec).begin(), (vec).end()); int pos = 0, col = 0; for (int i : s[v]) { if (res[i] != 0) continue; get_col(vec, pos, col); res[i] = col; } visited[v] = true; for (int i : g[v]) { if (visited[i]) continue; dfs(i); } } int main() { locale loc(locale(), new yes_no); cout << boolalpha; cout.imbue(loc); int n, k; scanf( %d%d , &n, &k); for (int i = 0; i < (int)(n); i++) { int sz, in; scanf( %d , &sz); for (int j = 0; j < (int)(sz); j++) { scanf( %d , &in); s[i].push_back(in - 1); } } for (int i = 0; i < (int)(n - 1); i++) { int from, to; scanf( %d%d , &from, &to); --from; --to; g[from].push_back(to); g[to].push_back(from); } dfs(0); for (int i = 0; i < (int)(k); i++) chmax(res[i], 1); int num = *max_element(res, res + k); cout << num << endl; for (int i = 0; i < (int)(k); i++) { printf( %d , res[i]); if (i == k - 1) printf( n ); else printf( ); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, ans = 0, ans1 = 0, ans2 = 0, tar; cin >> n; tar = n / 3; string s; cin >> s; for (int i = 0; i < n; i++) { int val = s[i] - 0 ; if (val == 0) ans++; else if (val == 1) ans1++; else ans2++; } for (int i = 0; tar > ans; i++) { if (i == n) break; if (s[i] == 1 and tar < ans1) { s[i] = 0 ; ans++; ans1--; continue; } if (s[i] == 2 and tar < ans2) { s[i] = 0 ; ans++; ans2--; continue; } } for (int i = n - 1; (tar < ans1) and ans2 < tar; i--) { if (i < 0) break; if (s[i] == 1 ) { s[i] = 2 ; ans2++; ans1--; } } for (int i = n - 1; (tar < ans) and ans2 < tar; i--) { if (i < 0) break; if (s[i] == 0 ) { s[i] = 2 ; ans2++; ans--; } } for (int i = 0; (tar < ans2) and ans1 < tar; i++) { if (i == n) break; if (s[i] == 2 ) { s[i] = 1 ; ans1++; ans2--; } } for (int i = n - 1; (tar < ans) and ans1 < tar; i--) { if (i < 0) break; if (s[i] == 0 ) { s[i] = 1 ; ans1++; ans--; } } cout << s << endl; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRTP_1_V
`define SKY130_FD_SC_HS__DFRTP_1_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfrtp_1 (
RESET_B,
CLK ,
D ,
Q ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dfrtp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dfrtp_1 (
RESET_B,
CLK ,
D ,
Q
);
input RESET_B;
input CLK ;
input D ;
output Q ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dfrtp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRTP_1_V
|
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; int main() { int n; cin >> n; long long int x = 2; double d; long long int p; for (long long int i = 1; i <= n; i++) { long long int B = i * (i + 1) * (i + 1) - x / i; cout << B << n ; x = i * (i + 1); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSTP_1_V
`define SKY130_FD_SC_HD__SDFSTP_1_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__sdfstp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSTP_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2006 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
reg [4:0] out2;
sub sub (.in(crc[23:0]), .out1(out1), .out2(out2));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x sum=%x out=%x,%x\n", $time, cyc, crc, sum, out1,out2);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {58'h0,out1,out2};
if (cyc==0) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'hf0afc2bfa78277c5) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1, out2,
// Inputs
in
);
input [23:0] in;
output reg out1;
output reg [4:0] out2;
always @* begin
// Test empty cases
casez (in[0])
endcase
casez (in)
24'b0000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b0,5'h00};
24'b????_????_????_????_????_???1 : {out1,out2} = {1'b1,5'h00};
24'b????_????_????_????_????_??10 : {out1,out2} = {1'b1,5'h01};
24'b????_????_????_????_????_?100 : {out1,out2} = {1'b1,5'h02};
24'b????_????_????_????_????_1000 : {out1,out2} = {1'b1,5'h03};
24'b????_????_????_????_???1_0000 : {out1,out2} = {1'b1,5'h04};
24'b????_????_????_????_??10_0000 : {out1,out2} = {1'b1,5'h05};
24'b????_????_????_????_?100_0000 : {out1,out2} = {1'b1,5'h06};
24'b????_????_????_????_1000_0000 : {out1,out2} = {1'b1,5'h07};
// Same pattern, but reversed to test we work OK.
24'b1000_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h17};
24'b?100_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h16};
24'b??10_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h15};
24'b???1_0000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h14};
24'b????_1000_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h13};
24'b????_?100_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h12};
24'b????_??10_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h11};
24'b????_???1_0000_0000_0000_0000 : {out1,out2} = {1'b1,5'h10};
24'b????_????_1000_0000_0000_0000 : {out1,out2} = {1'b1,5'h0f};
24'b????_????_?100_0000_0000_0000 : {out1,out2} = {1'b1,5'h0e};
24'b????_????_??10_0000_0000_0000 : {out1,out2} = {1'b1,5'h0d};
24'b????_????_???1_0000_0000_0000 : {out1,out2} = {1'b1,5'h0c};
24'b????_????_????_1000_0000_0000 : {out1,out2} = {1'b1,5'h0b};
24'b????_????_????_?100_0000_0000 : {out1,out2} = {1'b1,5'h0a};
24'b????_????_????_??10_0000_0000 : {out1,out2} = {1'b1,5'h09};
24'b????_????_????_???1_0000_0000 : {out1,out2} = {1'b1,5'h08};
endcase
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_xfer_cntrl (
// up interface
up_rstn,
up_clk,
up_data_cntrl,
up_xfer_done,
// device interface
d_rst,
d_clk,
d_data_cntrl);
// parameters
parameter DATA_WIDTH = 8;
localparam DW = DATA_WIDTH - 1;
// up interface
input up_rstn;
input up_clk;
input [DW:0] up_data_cntrl;
output up_xfer_done;
// device interface
input d_rst;
input d_clk;
output [DW:0] d_data_cntrl;
// internal registers
reg up_xfer_state_m1 = 'd0;
reg up_xfer_state_m2 = 'd0;
reg up_xfer_state = 'd0;
reg [ 5:0] up_xfer_count = 'd0;
reg up_xfer_done = 'd0;
reg up_xfer_toggle = 'd0;
reg [DW:0] up_xfer_data = 'd0;
reg d_xfer_toggle_m1 = 'd0;
reg d_xfer_toggle_m2 = 'd0;
reg d_xfer_toggle_m3 = 'd0;
reg d_xfer_toggle = 'd0;
reg [DW:0] d_data_cntrl = 'd0;
// internal signals
wire up_xfer_enable_s;
wire d_xfer_toggle_s;
// device control transfer
assign up_xfer_enable_s = up_xfer_state ^ up_xfer_toggle;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_xfer_state_m1 <= 'd0;
up_xfer_state_m2 <= 'd0;
up_xfer_state <= 'd0;
up_xfer_count <= 'd0;
up_xfer_done <= 'd0;
up_xfer_toggle <= 'd0;
up_xfer_data <= 'd0;
end else begin
up_xfer_state_m1 <= d_xfer_toggle;
up_xfer_state_m2 <= up_xfer_state_m1;
up_xfer_state <= up_xfer_state_m2;
up_xfer_count <= up_xfer_count + 1'd1;
up_xfer_done <= (up_xfer_count == 6'd1) ? ~up_xfer_enable_s : 1'b0;
if ((up_xfer_count == 6'd1) && (up_xfer_enable_s == 1'b0)) begin
up_xfer_toggle <= ~up_xfer_toggle;
up_xfer_data <= up_data_cntrl;
end
end
end
assign d_xfer_toggle_s = d_xfer_toggle_m3 ^ d_xfer_toggle_m2;
always @(posedge d_clk or posedge d_rst) begin
if (d_rst == 1'b1) begin
d_xfer_toggle_m1 <= 'd0;
d_xfer_toggle_m2 <= 'd0;
d_xfer_toggle_m3 <= 'd0;
d_xfer_toggle <= 'd0;
d_data_cntrl <= 'd0;
end else begin
d_xfer_toggle_m1 <= up_xfer_toggle;
d_xfer_toggle_m2 <= d_xfer_toggle_m1;
d_xfer_toggle_m3 <= d_xfer_toggle_m2;
d_xfer_toggle <= d_xfer_toggle_m3;
if (d_xfer_toggle_s == 1'b1) begin
d_data_cntrl <= up_xfer_data;
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
#include <bits/stdc++.h> using namespace std; int key(int x); int main() { int t; cin >> t; int str[t]; for (int u = 0; u < t; u++) { str[u] = key(u); } for (int u = 0; u < t; u++) cout << str[u] << n ; return 0; } int key(int x) { int n, k, d, mini = 1000, m = 0; cin >> n >> k >> d; int arr[n], c = 0; for (int i = 0; i < n; i++) cin >> arr[i]; for (int j = 0; j < n - d + 1; j++) { for (int a = 0; a < d; a++) { m = 0; for (int b = 0; b <= a; b++) { if (arr[j + a] == arr[j + b]) m++; else continue; } if (m <= 1) c++; } mini = min(mini, c); c = 0; } return mini; } |
#include <bits/stdc++.h> using namespace std; struct node { int num; long long x; } tmp; bool cmp(node a, node b) { return a.x > b.x; } int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); int t; vector<node> v; cin >> t; while (t--) { v.clear(); long long n, w; long long x; cin >> n >> w; for (int i = 1; i <= n; i++) { cin >> x; if (x > w) continue; else { tmp.x = x; tmp.num = i; v.push_back(tmp); } } if (v.empty()) { cout << -1 n ; continue; } sort(v.begin(), v.end(), cmp); int flag = 0; for (int i = 0; i < v.size(); i++) { if (v[i].x >= w / 2 + w % 2) { cout << 1 n ; cout << v[i].num << n ; flag = 1; break; } } if (flag == 0) { long long ssum = 0; int k; for (k = v.size() - 1; k >= 0; k--) { ssum += v[k].x; if (ssum >= w / 2 + w % 2) break; } if (k >= 0) { cout << v.size() - k << n ; for (int i = v.size() - 1; i >= k; i--) { cout << v[i].num << ; } cout << n ; } else cout << -1 n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; string h, v; cin >> h >> v; bool flag = true; if (h[0] == > && v[0] == v ) flag = false; if (h[0] == < && v[m - 1] == v ) flag = false; if (h[n - 1] == > && v[0] == ^ ) flag = false; if (h[n - 1] == < && v[m - 1] == ^ ) flag = false; if (flag) puts( YES ); else puts( NO ); return 0; } |
#include <bits/stdc++.h> int a[1005]; int main() { int x, i, j; while (scanf( %d%*c , &x) != EOF) a[x] = 1; bool flag = false; for (i = j = 1; i < 1001; i = ++j) if (a[i]) { for (j = i; a[j]; ++j) ; --j; if (!flag) flag = true; else printf( , ); if (i == j) printf( %d , i); else printf( %d-%d , i, j); } printf( n ); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int e = 0; int d; int a[15], b[15], l[10]; for (int f = 0; f < n; f++) cin >> a[f]; for (int j = 0; j < m; j++) cin >> b[j]; int rr = 0, tt = 0; for (int g = 0; g < n; g++) { if (a[g] < 0 || a[g] > 9) { for (int r = g; r < n; r++) a[r] = a[r + 1]; rr++; } } for (int h = 0; h < m; h++) { if (b[h] < 0 || b[h] > 9) { for (int t = h; t < m; t++) b[t] = b[t + 1]; tt++; } } if (n >= 0 && n <= 10 && m >= 0 && m <= 10) { for (int c = 0; c < n - rr; c++) { for (int d = 0; d < m - tt; d++) { if (a[c] == b[d]) { l[e] = a[c]; e++; } } } for (int k = 0; k < e; k++) cout << l[k] << ; } } |
#include <bits/stdc++.h> using namespace std; struct Counter { static int k; Counter() { k++; } ~Counter() { k--; } }; int Counter::k = 0; template <typename T> void pr(const string& name, T t) { cout << name << = << t << endl; } template <typename T, typename... Types> void pr(const string& names, T t, Types... rest) { auto comma_pos = names.find( , ); cout << names.substr(0, comma_pos) << = << t << , ; auto next_name_pos = names.find_first_not_of( t n , comma_pos + 1); pr(string(names, next_name_pos), rest...); } void mod(long long& a, long long b) { a %= b; if (a < 0) a += b; } const long long MOD = 1000000007; deque<long long> DQ; long long Days[15], N, M; int main() { cin >> N >> M; string line; Days[1] = 0; Days[2] = 31; Days[3] = 59; Days[4] = 90; Days[5] = 120; Days[6] = 151; Days[7] = 181; Days[8] = 212; Days[9] = 243; Days[10] = 273; Days[11] = 304; Days[12] = 334; getline(cin, line); while (true) { getline(cin, line); if (cin.eof()) break; long long year = 0, month = 0, day = 0; for (int i = (0); i <= (3); i++) year = 10 * year + line[i] - 0 ; for (int i = (5); i <= (6); i++) month = 10 * month + line[i] - 0 ; for (int i = (8); i <= (9); i++) day = 10 * day + line[i] - 0 ; long long days = 365 * (year - 1) + Days[month] + day - 1; days += (year - 1) / 4; if (year % 4 == 0 && month > 2) days++; long long hr = 10 * (line[11] - 0 ) + line[12] - 0 ; long long mn = 10 * (line[14] - 0 ) + line[15] - 0 ; long long sc = 10 * (line[17] - 0 ) + line[18] - 0 ; long long sec = days * 60 * 60 * 24 + 3600 * hr + 60 * mn + sc; if (!DQ.empty() && sec - DQ.front() >= N) DQ.pop_front(); DQ.push_back(sec); if (DQ.size() >= M) { cout << line.substr(0, 19) << n ; return 0; } } cout << -1 ; } |
#include <bits/stdc++.h> using namespace std; int cmp(char a, char b) { return a > b; } int main() { char s[300050]; char str[300050]; char ans[300050]; scanf( %s%s , s, str); int len = strlen(s); sort(s, s + len); sort(str, str + len, cmp); if (len == 1) { printf( %s n , s); return 0; } int l, r, L, R; l = L = 0; r = (len + 1) / 2 - 1; if (len & 1) { R = len / 2 - 1; } else R = r; int sum = 0; int i = 0; int j = len - 1; while (i <= j) { if ((sum & 1) == 0) { if (s[l] < str[L]) { ans[i++] = s[l++]; } else { ans[j--] = s[r--]; } sum++; } else { if (s[l] >= str[L]) { ans[j--] = str[R--]; } else { ans[i++] = str[L++]; } sum++; } } ans[len] = 0 ; printf( %s n , ans); return 0; } |
#include <iostream> #include <vector> #include <algorithm> #include <string> #include <ctype.h> #include <deque> #include <cstring> #include <set> #include <bitset> #include <map> #include <chrono> #include <random> #include <unordered_map> #include <stdio.h> using namespace std; typedef long long ll; typedef long double ld; typedef std::vector<int> vi; typedef std::vector<bool> vb; typedef std::vector<string> vs; typedef std::vector<double> vd; typedef std::vector<long long> vll; typedef std::vector<std::vector<int> > vvi; typedef vector<vll> vvll; typedef std::vector<std::pair<int, int> > vpi; typedef vector<vpi> vvpi; typedef std::pair<int, int> pi; typedef std::pair<ll, ll> pll; typedef std::vector<pll> vpll; const long long mod = 1000000007; const unsigned gen_seed = std::chrono::system_clock::now().time_since_epoch().count(); std::mt19937_64 gen(gen_seed); #define all(c) (c).begin(),(c).end() #define srt(c) sort(all(c)) #define srtrev(c) sort(all(c)); reverse(all(c)) #define forn(i, a, b) for(int i = a; i < b; i++) #define read(x) scanf( %d , &x) #define readv(x, n) vi x(n); forn(i,0,n) scanf( %d , &x[i]) #define pb push_back #define mp make_pair void mul(vi & a, int k) { vi b(k,0); for(auto x : a) b.pb(x); forn(i,0,a.size()) b[i] = (b[i] + mod-a[i])%mod; a.resize(b.size() - 1); for(int i = b.size() - 1; i > 0; i--) { a[i-1] = b[i]; b[i-1] = (b[i] + b[i-1])%mod; } } vi c, b; int n; int get(int x) { vi p(1,1); int sb = 0; int sbt = 0; int add = 0; forn(i,0,n) { mul(p, c[i]+1); int cur = x*(i+1) + sbt - add; if(cur > (int)p.size()) { return 0; } if(cur>0) { forn(j,0,p.size() - cur) p[j] = p[j + cur]; p.resize(p.size() - cur); add += cur; } sb+=b[i]; sbt+=sb; } ll ans = 0; forn(i,0,p.size()) ans = ans+p[i]; return ans % mod; } set<int> cool; int death = 1000; void getcool() { int sb = 0; int sbt = 0; int dp = 0; forn(i,0,n) { dp += c[i]; forn(x,-sbt/(i+1),(dp-sbt)/(i+1)+2) { int cur = x*(i+1) + sbt; if(cur >0 && cur <= dp) { cool.insert(x); } else if(cur > dp) { death = min(death, x); } } sb+=b[i]; sbt+=sb; } } int main() { #ifndef ONLINE_JUDGE freopen( input.txt , rt , stdin); freopen( output.txt , wt , stdout); #endif scanf( %d , &n); // readv(c,n); // readv(b,n-1); c.resize(n); b.resize(n-1); forn(i,0,n) scanf( %d , &c[i]); forn(i,0,n-1) scanf( %d , &b[i]); int q; read(q); getcool(); map<int, int> ans; for(auto x : cool) { if(x < death) ans[x] = get(x); else ans[x] = 0; } ll full = 1; forn(i,0,n) full = (full * (c[i]+1))%mod; while(q--) { int x; read(x); if(cool.find(x) != cool.end()) printf( %d n , ans[x]); else if(x >= death) printf( 0 n ); else printf( %d n , full); } } |
#include <bits/stdc++.h> using namespace std; const int MaxN = 1; int n, sol, counter; bool mark[20]; void check(long long x) { if (x > n) return; if (x != 0) sol++; for (int i = 0; i <= 9; i++) { if (mark[i]) { if (i != 0 || (i == 0 && x != 0)) check(x * 10 + i); } else { if (counter < 2) { counter++; mark[i] = true; if (i != 0 || (i == 0 && x != 0)) check(x * 10 + i); mark[i] = false; counter--; } } } } int main() { scanf( %d , &n); sol = 0; counter = 0; for (int i = 0; i <= 9; i++) mark[i] = false; long long x = 0; check(x); printf( %d n , sol); return 0; } |
#include <bits/stdc++.h> using namespace std; int dcmp(double a, double b) { return fabs(a - b) <= 0.0000000001 ? 0 : (a > b) ? 1 : -1; } int main() { int x1, y1, x2, y2, r1, r2, R1, R2; cin >> x1 >> y1 >> r1 >> R1 >> x2 >> y2 >> r2 >> R2; double dis = sqrt((y2 - y1) * (y2 - y1) + (x2 - x1) * (x2 - x1)); int ans = 0; if (dcmp(abs(dis - r1), R2) != -1 || dcmp(dis + r1, r2) != 1) ans++; if (dcmp(abs(dis - R1), R2) != -1 || dcmp(dis + R1, r2) != 1) ans++; if (dcmp(abs(dis - r2), R1) != -1 || dcmp(dis + r2, r1) != 1) ans++; if (dcmp(dis + R2, r1) != 1 || dcmp(abs(dis - R2), R1) != -1) ans++; cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5, base = 2333, mod = 20030731; int n, m, a[N], b[N], pw[N], h1[N], h2[N], ans[N]; void init() { pw[0] = 1; for (int i = (1); i <= (n - 1); i++) pw[i] = (long long)base * pw[i - 1] % mod, h1[i] = (((long long)h1[i - 1] * base + b[i]) % mod + mod) % mod; for (int i = n - 1; i; i--) h2[i] = (((long long)h2[i + 1] * base + b[i]) % mod + mod) % mod; } int get1(int x, int y) { return (h1[y] + mod - (long long)h1[x - 1] * pw[y - x + 1] % mod) % mod; } int get2(int x, int y) { return (h2[x] + mod - (long long)h2[y + 1] * pw[y - x + 1] % mod) % mod; } bool chk(int x, int y) { return get1(x, y) == get2(x, y); } int main() { scanf( %d%d , &n, &m); for (int i = (1); i <= (n); i++) scanf( %d , &a[i]); for (int i = (1); i <= (n - 1); i++) b[i] = a[i + 1] - a[i]; init(); for (int i = (1); i <= (n); i++) { bool flag = 1; if (i > 1) flag &= chk(1, i - 1); if (i < n) { flag &= a[1] + a[i] + m == a[i + 1] + a[n]; if (i < n - 1) flag &= chk(i + 1, n - 1); } if (flag) ans[++*ans] = (a[1] + a[i]) % m; } sort(ans + 1, ans + 1 + *ans); printf( %d n , *ans); for (int i = (1); i <= (*ans); i++) printf( %d , ans[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 305; int a[maxn][maxn], b[maxn][maxn]; int main(int argc, char const *argv[]) { int t; scanf( %d , &t); while (t--) { int n, m; scanf( %d %d , &n, &m); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { scanf( %d , &a[i][j]); } } bool good = 1; b[1][1] = b[1][m] = b[n][1] = b[n][m] = 2; if (a[1][1] > 2 or a[1][m] > 2 or a[n][1] > 2 or a[n][m] > 2) { printf( NO n ); continue; } for (int i = 2; i < m; ++i) { if (a[1][i] > 3 or a[n][i] > 3) { good = 0; } b[1][i] = b[n][i] = 3; } for (int i = 2; i < n; ++i) { if (a[i][1] > 3 or a[i][m] > 3) { good = 0; } b[i][1] = b[i][m] = 3; } if (!good) { printf( NO n ); continue; } for (int i = 2; i < n; ++i) { for (int j = 2; j < m; ++j) { if (a[i][j] > 4) { good = 0; } b[i][j] = 4; } } if (!good) { printf( NO n ); } else { printf( YES n ); for (int i = 1; i <= n; ++i) { for (int j = 1; j <= m; ++j) { printf( %d , b[i][j]); } printf( n ); } } } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__DFXBP_PP_SYMBOL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFXBP_PP_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; struct bus { double t, v; double cost, time; }; bus bus[100000]; int main() { int n, a, d; scanf( %d%d%d , &n, &a, &d); double fastest = 0.0; double x, y; for (int i = 0; i < n; i++) { scanf( %lf%lf , &bus[i].t, &bus[i].v); x = (d - bus[i].v * bus[i].v / (2.0 * a)) / bus[i].v; y = bus[i].t + (bus[i].v / a) + x; if (x < 0) { y = bus[i].t + sqrt(2.0 * d / (double)a); } if (fastest <= y) fastest = y; printf( %.10f n , fastest); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_PP_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__a21oi (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21OI_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:35:02 01/05/2015
// Design Name:
// Module Name: wb_rom
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module wb_rom #(
parameter depth = 65536,
parameter aw = $clog2(depth),
parameter memfile = "rom.dat"
) (
input wb_clk,
input wb_rst,
input [31:0] wb_adr_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
input wb_we_i,
input wb_cyc_i,
input wb_stb_i,
output [31:0] wb_dat_o,
output reg wb_ack_o,
output wb_err_o,
output wb_rty_o
);
`include "wb_common.v"
assign wb_err_o = 0;
assign wb_rty_o = 0;
wire valid = (wb_cyc_i & wb_stb_i);
reg valid_r;
wire new_cycle = valid & ~valid_r;
reg [aw - 1:0] adr_r;
wire [aw - 1:0] next_adr = wb_next_adr(adr_r, wb_cti_i, wb_bte_i, 32);
wire [aw - 1:0] wb_adr = new_cycle ? wb_adr_i : next_adr;
always @(posedge wb_clk)
begin
adr_r <= wb_adr;
valid_r <= valid;
wb_ack_o <= valid & (!((wb_cti_i == 3'b000) | (wb_cti_i == 3'b111)) | !wb_ack_o);
if(wb_rst)
begin
adr_r <= 0;
valid_r <= 0;
wb_ack_o <= 0;
end
end
dp_rom #(
.memfile(memfile),
.aw(aw - 2)
) rom_inst (
.clk1(wb_clk),
.en1(valid),
.adr1(wb_adr[aw - 1:2]),
.dat1(wb_dat_o),
.clk2(1'b0),
.en2(1'b0),
.adr2(0),
.dat2()
);
endmodule
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_tan_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_tan_s5 inst(
.en (enable),
.clk (clock),
.a (dataa),
.q (sub_wire0),
.areset(1'b0));
endmodule
|
#include <bits/stdc++.h> int R, C; int ER, EC; int SR, SC; char field[1010][1010]; int dist[1010][1010]; int Q[1010 * 1010], Qb, Qe; int dr[4] = {-1, +1, 0, 0}; int dc[4] = {0, 0, -1, +1}; int main(void) { scanf( %d %d , &R, &C); for (int r = 0; r < R; ++r) { scanf( %s , field[r]); for (int c = 0; c < C; ++c) { if (field[r][c] == E ) { ER = r; EC = c; } if (field[r][c] == S ) { SR = r; SC = c; } } } memset(dist, -1, sizeof dist); Q[0] = ER * 10000 + EC; Qe = 1; dist[ER][EC] = 0; while (Qb != Qe) { int r = Q[Qb] / 10000; int c = Q[Qb] % 10000; Qb += 1; for (int d = 0; d < 4; ++d) { int rr = r + dr[d]; int cc = c + dc[d]; if (rr < 0 || cc < 0 || rr >= R || cc >= C) continue; if (field[rr][cc] == T ) continue; if (dist[rr][cc] != -1) continue; dist[rr][cc] = dist[r][c] + 1; Q[Qe++] = rr * 10000 + cc; } } int battles = 0; int mydist = dist[SR][SC]; for (int r = 0; r < R; ++r) { for (int c = 0; c < C; ++c) { if (!isdigit(field[r][c])) continue; if (dist[r][c] == -1 || dist[r][c] > mydist) continue; int cnt = field[r][c] - 0 ; battles += cnt; } } printf( %d n , battles); return 0; } |
#include <bits/stdc++.h> const int N = (int)3e5 + 2; int n; bool a[N << 1]; int ans, ansl, ansr; inline long long read() { long long x = 0; char ch = getchar(); for (; ch > 9 || ch < 0 ; ch = getchar()) ; for (; ch >= 0 && ch <= 9 ; ch = getchar()) x = (x << 1) + (x << 3) + (ch ^ 48); return x; } int main() { n = read(); int cnt = 0, mn = 0, pos = -1; for (int i = 0; i < n; ++i) { char ch = getchar(); if (ch == ( ) ++cnt; else a[i] = a[i + n] = 1, --cnt; if (mn > cnt) mn = cnt, pos = i, ans = 1; else if (mn == cnt) ++ans; } if (cnt) { printf( 0 n1 1 ); return 0; } int I = n + ++pos, num[2] = {0, 0}, l[2], tmp = ans; for (int i = pos; i < I; ++i) { if (!a[i]) { ++cnt; if (cnt == 1) ++num[0], l[0] = i; else if (cnt == 2) ++num[1], l[1] = i; } else { --cnt; if (!cnt) { if (num[0] > ans) { ans = num[0]; ansl = l[0]; ansr = i; } num[0] = 0; } else if (cnt == 1) { if (tmp + num[1] > ans) { ans = tmp + num[1]; ansl = l[1]; ansr = i; } ++num[0]; num[1] = 0; } else if (cnt == 2) ++num[1]; } } printf( %d n%d %d , ans, ansl % n + 1, ansr % n + 1); return 0; } |
#include <bits/stdc++.h> using namespace std; int32_t main() { int n, m; char x; cin >> n >> m; cin >> x; vector<vector<char> > c(n + 1); char gar; vector<char> u1(m + 1, . ); for (int j = 0; j < (n + 1); ++j) c[j] = u1; bool b[n][m]; stack<pair<int, int> > s, t; for (int i = 0; i < (n); ++i) { scanf( %c , &gar); for (int j = 0; j < (m); ++j) { scanf( %c , &c[i][j]); if (c[i][j] == x) s.push({i, j}); b[i][j] = false; } } while (!s.empty()) { auto k = s.top(); int u = k.first; int v = k.second; s.pop(); if (u > 0 && c[u - 1][v] != x) t.push({u - 1, v}); if (v > 0 && c[u][v - 1] != x) t.push({u, v - 1}); if (u + 1 < n && c[u + 1][v] != x) t.push({u + 1, v}); if (v + 1 < m && c[u][v + 1] != x) t.push({u, v + 1}); } int cou = 0; while (!t.empty()) { auto k = t.top(); t.pop(); int u = k.first; int v = k.second; if (c[u][v] == . ) continue; if ((u > 0 && b[u - 1][v] == 1 && c[u - 1][v] == c[u][v]) || (v > 0 && c[u][v - 1] == c[u][v] && b[u][v - 1] == 1) || (u + 1 < n && c[u + 1][v] == c[u][v] && b[u + 1][v] == 1) || (v + 1 < m && c[u][v + 1] == c[u][v] && b[u][v + 1] == 1)) b[u][v] = 1; else { cou++; b[u][v] = 1; } } cout << cou << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 1000010; int n, m, tot, ans; int mx[maxn], mn[maxn], fir[maxn]; struct edge { int a, b, l, r; } p[maxn << 1]; queue<int> q; vector<int> v[maxn]; inline void add(int a, int b, int c, int d) { p[++tot].a = a, p[tot].b = b, p[tot].l = c + ((c ^ a) & 1), p[tot].r = d - ((d ^ b) & 1); } bool cmp(const edge &a, const edge &b) { return a.l < b.l; } inline void solve(int x) { int a = p[x].a, b = p[x].b, l = p[x].l = max(p[x].l, mn[a]), r = p[x].r; if (mx[a] < l) { v[a].push_back(x); return; } q.push(x); while (!q.empty()) { x = q.front(), q.pop(), a = p[x].a, b = p[x].b, l = p[x].l, r = p[x].r; if (l >= r) continue; if (mx[b] + 2 < l) mn[b] = l + 1, mx[b] = r; else mx[b] = max(mx[b], r); if ((b >> 1) == n) ans = min(ans, mn[b]); while (fir[b] < (int)v[b].size()) { int t = v[b][fir[b]]; if (mx[b] >= p[t].l) fir[b]++, q.push(t), p[t].l = mn[b]; else break; } } } inline int rd() { int ret = 0, f = 1; char gc = getchar(); while (gc < 0 || gc > 9 ) { if (gc == - ) f = -f; gc = getchar(); } while (gc >= 0 && gc <= 9 ) ret = ret * 10 + (gc ^ 0 ), gc = getchar(); return ret * f; } int main() { n = rd(), m = rd(); if (n == 1) { puts( 0 ); return 0; } int i, a, b, c, d; for (i = 1; i <= m; i++) { a = rd(), b = rd(), c = rd(), d = rd(); add(a << 1, b << 1 | 1, c, d); add(a << 1 | 1, b << 1, c, d); add(b << 1, a << 1 | 1, c, d); add(b << 1 | 1, a << 1, c, d); } sort(p + 1, p + tot + 1, cmp); memset(mx, 0xc0, sizeof(mx)), memset(mn, 0xc0, sizeof(mn)); mn[2] = mx[2] = 0, ans = 1 << 30; for (i = 1; i <= tot; i++) solve(i); if (ans == (1 << 30)) puts( -1 ); else printf( %d , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int P = 10, N = 1e5 + 10; int inverse(int a, int m) { int m0 = m, t, q; int x0 = 0, x1 = 1; if (m == 1) return 0; while (a > 1) { q = a / m; t = m; m = a % m, a = t; t = x0; x0 = x1 - q * x0; x1 = t; } if (x1 < 0) x1 += m0; return x1; } int fact[N], ifact[N], pot[N][P]; vector<int> primes(int n) { vector<int> ans; for (int d = 2; d * d <= n; d++) if (n % d == 0) { ans.push_back(d); while (n % d == 0) { n /= d; } } if (n > 1) ans.push_back(n); return ans; } int mod; vector<int> p; int expomod(long long int a, long long int e) { int ans = 1; while (e) { if (e & 1) ans = ans * a % mod; e /= 2; a = a * a % mod; } return ans; } int comb(int m, int n) { int ans = (long long int)fact[m] * ifact[n] % mod * ifact[m - n] % mod; for (int i = 0; i < (int)(((int)(p).size())); i++) { int pp = pot[m][i] - pot[n][i] - pot[m - n][i]; if (pp) ans = (long long int)ans * expomod(p[i], pp) % mod; } return ans; } int go(int n, int bal) { long long int ans = 0; for (int x = 0, y = bal; x + y <= n; x++, y++) { ans += (long long int)comb(n, x) * comb(n - x, y) % mod; if (ans >= mod) ans -= mod; } return ans; } int main() { int n, l, r; cin >> n >> mod >> l >> r; p = primes(mod); fact[0] = ifact[0] = 1; for (int i = 1; i <= n; i++) { int d = -1; for (int j = 0; j < (int)(((int)(p).size())); j++) if (i % p[j] == 0) { d = j; break; } if (d == -1) fact[i] = i; else { fact[i] = fact[i / p[d]]; for (int j = 0; j < (int)(((int)(p).size())); j++) pot[i][j] = pot[i / p[d]][j] + (j == d); } ifact[i] = inverse(fact[i], mod); } for (int i = 0; i < (int)(n); i++) { fact[i + 1] = (long long int)fact[i] * fact[i + 1] % mod; ifact[i + 1] = (long long int)ifact[i] * ifact[i + 1] % mod; for (int j = 0; j < (int)(((int)(p).size())); j++) pot[i + 1][j] += pot[i][j]; } long long int ans = 0; for (int i = 0; i < (int)(2); i++) { ans += go(n, l + i); ans -= go(n, r + 1 + i); } ans %= mod; if (ans < 0) ans += mod; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 2e9; const long long LINF = 2e18; void inv(bool e); template <typename T> void die(T& a); bool brute, alter; int cnt_tests = 1; const int N = (1 << 17) + 1; int degree[N], xr[N]; int n; void inp() { cin >> n; for (int i = 0; i < n; i++) { cin >> degree[i] >> xr[i]; } } set<int> friends[N]; void solve() { for (int i = 0; i < n; i++) { friends[degree[i]].insert(i); } int newbie, parent; auto& cur = friends[1]; vector<pair<int, int> > ans; while (!cur.empty()) { newbie = *cur.begin(); cur.erase(cur.begin()); parent = xr[newbie]; friends[degree[parent]].erase(parent); friends[degree[parent] - 1].insert(parent); degree[parent]--; ans.push_back({newbie, parent}); xr[parent] ^= newbie; } cout << ((int)(ans).size()) << endl; for (auto x : ans) { cout << x.first << << x.second << endl; } } void stress() {} void naive() {} void run(); int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); if (0) { freopen( stack.in , r , stdin); freopen( stack.out , w , stdout); } brute = false; for (int i = 0; (i < cnt_tests); i++) { run(); } cerr << endl << Time: << clock() / 1000.0 << ms ; return 0; } void run() { if (!brute) { inp(); } else { stress(); } solve(); } template <typename T> void die(T& a) { cout << a; exit(0); } void inv(bool e) { if (!e) { vector<int> a; a[-1] += 1; } } |
//
// Copyright (c) 2000 Stephen Williams ()
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// single bit positive events
//
module main ();
reg flag1;
reg event_1;
always @ (posedge event_1) flag1 = ~flag1;
initial begin
event_1 = 1'b0;
#1 flag1 = 0;
#1 event_1 = 1'b1;
#1
if (flag1 !== 1'b1) begin
$display("FAILED -- 0->1 didn't trigger flag1");
$finish;
end
event_1 = 1'b0;
#1
if (flag1 !== 1'b1) begin
$display("FAILED -- 1->0 DID trigger flag1");
$finish;
end
$display("PASSED");
end
endmodule
|
/**
* bsg_nonsynth_mem_1rw_sync_assoc.v
*
* bsg_mem_1rw_sync implementation using associative array.
*
* This is for simulating arbitrarily large memories.
*
*/
`include "bsg_defines.v"
module bsg_nonsynth_mem_1rw_sync_assoc
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(addr_width_p)
)
(
input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_p-1:0] addr_i
, input v_i
, input w_i
, output logic [width_p-1:0] data_o
);
wire unused = reset_i;
// associative array
//
`ifdef VERILATOR
// Verilator 4.024 supports associative array, but not wildcard indexed.
logic [width_p-1:0] mem [longint];
`else
logic [width_p-1:0] mem [*];
`endif
// write logic
//
always_ff @ (posedge clk_i) begin
if (~reset_i & v_i & w_i) begin
mem[addr_i] <= data_i;
end
end
// read logic
//
always_ff @ (posedge clk_i) begin
if (~reset_i & v_i & ~w_i) begin
data_o <= mem[addr_i];
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_nonsynth_mem_1rw_sync_assoc)
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-2-2017
*/
`timescale 1ns / 1ps
module jt12_testdata
#(parameter rand_wait=0)
(
input rst,
input clk,
output reg cs_n,
output reg wr_n,
output reg [1:0] addr,
output reg [7:0] dout,
input [7:0] din,
output reg prog_done
);
// CFG configuration
// { addr[1], reg[7:0], value[7:0] }
reg [16:0] cfg[0:65535];
initial begin
`include "inputs.vh"
end
reg [15:0] data_cnt;
reg [ 3:0] state, next;
reg [15:0] waitcnt;
localparam WAIT_FREE=0, WR_ADDR=1, WR_VAL=2, DONE=3, WRITE=4,
BLANK=5, WAIT_CNT=6;
localparam BUSY_TIMEOUT=500;
integer rnd_count, timeout;
always @(posedge clk or posedge rst) begin
if( rst ) begin
data_cnt <= 0;
prog_done <= 0;
next <= WR_ADDR;
state <= WAIT_FREE;
addr <= 2'b0;
wr_n <= 1'b1;
dout <= 8'h0;
rnd_count <= 0;
waitcnt <= 16'h0;
timeout <= BUSY_TIMEOUT;
end
else begin
case( state )
BLANK: begin
if( rnd_count>0 )
rnd_count <= rnd_count -1;
else begin
state <= WAIT_FREE;
timeout <= BUSY_TIMEOUT;
end
wr_n <= 1'b1;
end
WAIT_FREE: begin
// a0 <= 1'b0;
{ cs_n, wr_n } <= 2'b01;
timeout <= timeout-1;
if(timeout==0) begin
$display("ERROR: timeout while waiting for BUSY\n");
$finish;
end
if( !din[7] ) begin
case( cfg[data_cnt][15:8] )
8'h0: state <= DONE;
8'h1: begin
waitcnt <= { cfg[data_cnt][7:0], 8'h0 };
state <= WAIT_CNT;
end
// Wait for timer flag:
8'h3: if( (din[1:0]&cfg[data_cnt][1:0])!=2'd0 ) state<=next;
default: state <= next;
endcase
end
end
WAIT_CNT: begin
if( waitcnt==16'd0 ) begin
data_cnt <= data_cnt + 1'b1;
timeout <= BUSY_TIMEOUT;
state <= WAIT_FREE;
end
else waitcnt <= waitcnt-1'b1;
end
WRITE: begin
{ cs_n, wr_n } <= 2'b00;
`ifndef VERILATOR
rnd_count <= rand_wait ? ($urandom%100) : 0;
`else
rnd_count <= 0;
`endif
state<= BLANK;
end
WR_ADDR: begin
addr <= { cfg[data_cnt][16], 1'b0 };
dout <= cfg[data_cnt][15:8];
next <= WR_VAL;
state<= WRITE;
end
WR_VAL: begin
addr[0] <= 1'b1;
dout <= cfg[data_cnt][7:0];
state <= WRITE;
if( &data_cnt == 1'b1 ) begin
$display("data_cnt overflow! jt12_testdata.v");
next <= DONE;
end
else begin
data_cnt <= data_cnt + 1'b1;
next <= WR_ADDR;
end
end
DONE: prog_done <= 1'b1;
endcase
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 1e6 + 5; string name[maxn], s; vector<int> G[maxn]; int tot, a[maxn], maxd, dep[maxn]; int dfs(int &p, int d) { maxd = max(maxd, d); int ret = ++tot; dep[ret] = d; while (s[p] != , ) { name[ret].push_back(s[p++]); } ++p; int son = 0; while (s[p] != , ) { son = son * 10 + s[p++] - 0 ; } ++p; for (int i = 0; i < son; ++i) G[ret].push_back(dfs(p, d + 1)); return ret; } void bfs() { queue<int> que; cout << maxd; int t = 0; for (int i = 0; i < G[0].size(); ++i) que.push(G[0][i]); while (!que.empty()) { int p = que.front(); que.pop(); if (dep[p] != t) { ++t; cout << endl; } else cout << ; cout << name[p]; for (int i = 0; i < G[p].size(); ++i) que.push(G[p][i]); } cout << endl; } int main() { cin >> s; s.push_back( , ); maxd = 0; int p = 0; while (p < s.size()) G[0].push_back(dfs(p, 1)); bfs(); return 0; } |
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_10g_fifo
*/
module test_eth_mac_10g_fifo_ptp_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH/8);
parameter AXIS_DATA_WIDTH = DATA_WIDTH;
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8);
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 4096;
parameter TX_FIFO_PIPELINE_OUTPUT = 2;
parameter TX_FRAME_FIFO = 1;
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
parameter TX_DROP_WHEN_FULL = 0;
parameter RX_FIFO_DEPTH = 4096;
parameter RX_FIFO_PIPELINE_OUTPUT = 2;
parameter RX_FRAME_FIFO = 1;
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
parameter LOGIC_PTP_PERIOD_NS = 4'h6;
parameter LOGIC_PTP_PERIOD_FNS = 16'h6666;
parameter PTP_PERIOD_NS = 4'h6;
parameter PTP_PERIOD_FNS = 16'h6666;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter TX_PTP_TS_ENABLE = 1;
parameter RX_PTP_TS_ENABLE = 1;
parameter TX_PTP_TS_FIFO_DEPTH = 64;
parameter RX_PTP_TS_FIFO_DEPTH = 64;
parameter PTP_TS_WIDTH = 96;
parameter TX_PTP_TAG_ENABLE = 1;
parameter PTP_TAG_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg logic_clk = 0;
reg logic_rst = 0;
reg ptp_sample_clk = 0;
reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag = 0;
reg s_axis_tx_ptp_ts_valid = 0;
reg m_axis_tx_ptp_ts_ready = 0;
reg rx_axis_tready = 0;
reg m_axis_rx_ptp_ts_ready = 0;
reg [DATA_WIDTH-1:0] xgmii_rxd = 0;
reg [CTRL_WIDTH-1:0] xgmii_rxc = 0;
reg [PTP_TS_WIDTH-1:0] ptp_ts_96 = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire tx_axis_tready;
wire s_axis_tx_ptp_ts_ready;
wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96;
wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag;
wire m_axis_tx_ptp_ts_valid;
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [PTP_TS_WIDTH-1:0] m_axis_rx_ptp_ts_96;
wire m_axis_rx_ptp_ts_valid;
wire [DATA_WIDTH-1:0] xgmii_txd;
wire [CTRL_WIDTH-1:0] xgmii_txc;
wire tx_error_underflow;
wire tx_fifo_overflow;
wire tx_fifo_bad_frame;
wire tx_fifo_good_frame;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire rx_fifo_overflow;
wire rx_fifo_bad_frame;
wire rx_fifo_good_frame;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
logic_clk,
logic_rst,
ptp_sample_clk,
tx_axis_tdata,
tx_axis_tkeep,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
s_axis_tx_ptp_ts_tag,
s_axis_tx_ptp_ts_valid,
m_axis_tx_ptp_ts_ready,
rx_axis_tready,
m_axis_rx_ptp_ts_ready,
xgmii_rxd,
xgmii_rxc,
ptp_ts_96,
ifg_delay
);
$to_myhdl(
tx_axis_tready,
s_axis_tx_ptp_ts_ready,
m_axis_tx_ptp_ts_96,
m_axis_tx_ptp_ts_tag,
m_axis_tx_ptp_ts_valid,
rx_axis_tdata,
rx_axis_tkeep,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
m_axis_rx_ptp_ts_96,
m_axis_rx_ptp_ts_valid,
xgmii_txd,
xgmii_txc,
tx_error_underflow,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame
);
// dump file
$dumpfile("test_eth_mac_10g_fifo_ptp_64.lxt");
$dumpvars(0, test_eth_mac_10g_fifo_ptp_64);
end
eth_mac_10g_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
.TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.RX_FRAME_FIFO(RX_FRAME_FIFO),
.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL),
.LOGIC_PTP_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.LOGIC_PTP_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH)
)
UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.logic_clk(logic_clk),
.logic_rst(logic_rst),
.ptp_sample_clk(ptp_sample_clk),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.s_axis_tx_ptp_ts_tag(s_axis_tx_ptp_ts_tag),
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready),
.m_axis_tx_ptp_ts_96(m_axis_tx_ptp_ts_96),
.m_axis_tx_ptp_ts_tag(m_axis_tx_ptp_ts_tag),
.m_axis_tx_ptp_ts_valid(m_axis_tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(m_axis_tx_ptp_ts_ready),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.m_axis_rx_ptp_ts_96(m_axis_rx_ptp_ts_96),
.m_axis_rx_ptp_ts_valid(m_axis_rx_ptp_ts_valid),
.m_axis_rx_ptp_ts_ready(m_axis_rx_ptp_ts_ready),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.tx_error_underflow(tx_error_underflow),
.tx_fifo_overflow(tx_fifo_overflow),
.tx_fifo_bad_frame(tx_fifo_bad_frame),
.tx_fifo_good_frame(tx_fifo_good_frame),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_fifo_overflow(rx_fifo_overflow),
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
.ptp_ts_96(ptp_ts_96),
.ifg_delay(ifg_delay)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int a[105]; int n, k; char s[105]; int main(void) { int i, j, x, y, z; scanf( %d %d , &n, &k); scanf( %s , s); x = 0; for (i = 0; i < s[i]; i++) { a[x++] = s[i] - a + 1; } sort(a, a + n); x = 1; y = a[0]; z = 0; if (x == k) { printf( %d n , y); return 0; } for (i = 1; i < n; i++) { if (a[i] - a[z] > 1) { x++; y += a[i]; z = i; if (x == k) break; } } if (i >= n) { printf( -1 ); return 0; } printf( %d n , y); return 0; } |
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
FrameController2
:Function
Controlling a frame(block ram etc.), writing or reading with counts.
For controlling a BlockRAM from xilinx.
Give the first output after mul_delay + 2 + ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-25
Copyright (C) 2015 Tianyu Dai (dtysky) <>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController2(
clk,
rst_n,
in_count_x,
in_count_y,
in_enable,
in_data,
out_ready,
out_data,
ram_addr);
/*
::description
This module's working mode.
::range
0 for Pipline, 1 for Req-ack
*/
parameter work_mode = 0;
/*
::description
This module's WR mode.
::range
0 for Write, 1 for Read
*/
parameter wr_mode = 0;
/*
::description
Data bit width.
*/
parameter data_width = 8;
/*
::description
Width of image.
::range
1 - 4096
*/
parameter im_width = 320;
/*
::description
Height of image.
::range
1 - 4096
*/
parameter im_height = 240;
/*
::description
The bits of width of image.
::range
Depend on width of image
*/
parameter im_width_bits = 9;
/*
::description
Address bit width of a ram for storing this image.
::range
Depend on im_width and im_height.
*/
parameter addr_width = 17;
/*
::description
RL of RAM, in xilinx 7-series device, it is 2.
::range
0 - 15, Depend on your using ram.
*/
parameter ram_read_latency = 2;
/*
::description
Delay for multiplier.
::range
Depend on your multilpliers' configurations
*/
parameter mul_delay = 3;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Input pixel count for width.
*/
input[im_width_bits - 1 : 0] in_count_x;
/*
::description
Input pixel count for height.
*/
input[im_width_bits - 1 : 0] in_count_y;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [data_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output[data_width - 1 : 0] out_data;
/*
::description
Address for ram.
*/
output[addr_width - 1 : 0] ram_addr;
reg[3 : 0] con_enable;
reg[im_width_bits - 1 : 0] reg_in_count_x;
reg[im_width_bits - 1 : 0] reg_in_count_y;
reg[addr_width - 1 : 0] reg_addr;
wire[11 : 0] mul_a, mul_b;
wire[23 : 0] mul_p;
assign mul_a = {{(12 - im_width_bits){1'b0}}, in_count_y};
assign mul_b = im_width;
genvar i;
generate
/*
::description
Multiplier for Unsigned 12bits x Unsigned 12bits, used for creating address for frame.
You can configure the multiplier by yourself, then change the "mul_delay".
You can not change the ports' configurations!
*/
Multiplier12x12FR2 Mul(.CLK(clk), .A(mul_a), .B(mul_b), .SCLR(~rst_n), .P(mul_p));
for (i = 0; i < mul_delay; i = i + 1) begin : conut_buffer
reg[im_width_bits - 1 : 0] b;
if(i == 0) begin
always @(posedge clk)
b <= in_count_x;
end else begin
always @(posedge clk)
b <= conut_buffer[i - 1].b;
end
end
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable) begin
reg_addr <= 0;
end else begin
reg_addr <= mul_p + conut_buffer[mul_delay - 1].b;
end
end
assign ram_addr = reg_addr;
if(wr_mode == 0) begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_enable <= 0;
else if(con_enable == mul_delay + 1)
con_enable <= con_enable;
else
con_enable <= con_enable + 1;
end
assign out_ready = con_enable == mul_delay + 1 ? 1 : 0;
if(work_mode == 0) begin
for (i = 0; i < mul_delay + 1; i = i + 1) begin : buffer
reg[data_width - 1 : 0] b;
if(i == 0) begin
always @(posedge clk)
b <= in_data;
end else begin
always @(posedge clk)
b <= buffer[i - 1].b;
end
end
assign out_data = out_ready ? buffer[mul_delay].b : 0;
end else begin
reg[data_width - 1 : 0] reg_out_data;
always @(posedge in_enable)
reg_out_data = in_data;
assign out_data = out_ready ? reg_out_data : 0;
end
end else begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_enable <= 0;
else if (con_enable == mul_delay + 1 + ram_read_latency)
con_enable <= con_enable;
else
con_enable <= con_enable + 1;
end
assign out_data = out_ready ? in_data : 0;
assign out_ready = con_enable == mul_delay + 1 + ram_read_latency ? 1 : 0;
end
endgenerate
endmodule |
#include <bits/stdc++.h> using namespace std; const int maxn = 1e5; int n, k, cnt[111111], a[111111], mxx, prime[111111], ct, mx[111111], cnr; long long cur, ans, ts, fuck, fk; bool f, fl[111111]; void Init() { for (int i = 2; i <= maxn; i++) { if (!fl[i]) { prime[++ct] = i; } for (int j = 1; j <= ct && i * prime[j] <= maxn; j++) { fl[i * prime[j]] = 1; if (i % prime[j] == 0) break; } } for (int i = 1; i <= ct; i++) { for (int j = prime[i]; j <= maxn; j += prime[i]) { mx[j] = i; } } } int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) cnt[a[i]]++; for (int i = 2; i <= maxn; i++) { cur = 1; for (int j = 1; j <= k; j++) { if (cur > 100000) { f = 1; break; } cur = cur * i; } if (cur > 100000) { mxx = i - 1; break; } } Init(); for (int i = 1; i <= n; i++) { cur = a[i]; fuck = 1; while (cur > 1) { int x = mx[cur]; cnr = 0; while (cur % prime[x] == 0) { cnr++; cur /= prime[x]; } cnr = (cnr - 1) % k + 1; for (int j = 1; fuck != -1 && j <= k - cnr; j++) { fuck *= prime[x]; if (fuck > maxn) fuck = -1; } } if (fuck == -1) continue; for (int j = 1; j <= mxx; j++) { fk = fuck; for (int h = 1; fk != -1 && h <= k; h++) { fk *= j; if (fk > maxn) fk = -1; } if (~fk) { if (fk == a[i]) ans += (cnt[fk] - 1); else ans += cnt[fk]; } else break; } } printf( %lld n , ans / 2); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DFSTP_FUNCTIONAL_PP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
wire SET ;
// Delay Name Output Other arguments
not not0 (SET , SET_B );
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, SET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSTP_FUNCTIONAL_PP_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iop_fpga.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module iop_fpga(reset_l, gclk,
cpu_id,
spc_pcx_req_pq,
spc_pcx_atom_pq,
spc_pcx_data_pa,
pcx_spc_grant_px,
cpx_spc_data_rdy_cx2,
cpx_spc_data_cx2
);
output [4:0] spc_pcx_req_pq;
output spc_pcx_atom_pq;
output [123:0] spc_pcx_data_pa;
input [4:0] pcx_spc_grant_px;
input cpx_spc_data_rdy_cx2;
input [144:0] cpx_spc_data_cx2;
input reset_l;
input gclk;
input [1:0] cpu_id;
parameter C_EXT_RESET_HIGH = 0;
// WIRE Definitions for unused outputs
wire spc_sscan_so;
wire spc_scanout0;
wire spc_scanout1;
wire tst_ctu_mbist_done;
wire tst_ctu_mbist_fail;
wire spc_efc_ifuse_data;
wire spc_efc_dfuse_data;
// WIRE Definitions for constraint
wire [3:0] const_cpuid;
wire [7:0] const_maskid = 8'h20;
wire ctu_tck = 1'b0;
wire ctu_sscan_se = 1'b0;
wire ctu_sscan_snap = 1'b0;
wire [3:0] ctu_sscan_tid = 4'h1;
wire ctu_tst_mbist_enable = 1'b0;
wire efc_spc_fuse_clk1 = 1'b0;
wire efc_spc_fuse_clk2 = 1'b0;
wire efc_spc_ifuse_ashift = 1'b0;
wire efc_spc_ifuse_dshift = 1'b0;
wire efc_spc_ifuse_data = 1'b0;
wire efc_spc_dfuse_ashift = 1'b0;
wire efc_spc_dfuse_dshift = 1'b0;
wire efc_spc_dfuse_data = 1'b0;
wire ctu_tst_macrotest = 1'b0;
wire ctu_tst_scan_disable = 1'b0;
wire ctu_tst_short_chain = 1'b0;
wire global_shift_enable = 1'b0;
wire ctu_tst_scanmode = 1'b0;
wire spc_scanin0 = 1'b0;
wire spc_scanin1 = 1'b0;
// Reset Related Signals
wire cluster_cken;
wire cmp_grst_l;
wire cmp_arst_l;
wire ctu_tst_pre_grst_l;
wire adbginit_l;
wire gdbginit_l;
reg reset_l_sync;
wire reset_l_int;
reg sync;
// CPU ID
assign const_cpuid = {2'b00, cpu_id};
// Reset Logic
assign cmp_arst_l = reset_l_int;
assign adbginit_l = reset_l_int;
reg [7:0] reset_delay;
// Synchronize the incoming reset net into the gclk domain
always @(posedge gclk) begin
{reset_l_sync, sync} <= {sync, reset_l};
end
assign reset_l_int = C_EXT_RESET_HIGH ? ~reset_l_sync : reset_l_sync;
always @(posedge gclk) begin
if(~reset_l_int) begin
reset_delay <= 8'b0;
end else
if(reset_delay != 8'hff)
reset_delay <= reset_delay + 8'b1;
end
assign cluster_cken = (reset_delay > 8'd20) ? 1'b1 : 1'b0;
assign ctu_tst_pre_grst_l = (reset_delay > 8'd60) ? 1'b1 : 1'b0;
assign gdbginit_l = (reset_delay > 8'd120) ? 1'b1 : 1'b0;
assign cmp_grst_l = (reset_delay > 8'd120) ? 1'b1 : 1'b0;
sparc sparc0 (
.spc_pcx_req_pq (spc_pcx_req_pq),
.spc_pcx_atom_pq (spc_pcx_atom_pq),
.spc_pcx_data_pa (spc_pcx_data_pa),
.spc_sscan_so (spc_sscan_so),
.spc_scanout0 (spc_scanout0),
.spc_scanout1 (spc_scanout1),
.tst_ctu_mbist_done (tst_ctu_mbist_done),
.tst_ctu_mbist_fail (tst_ctu_mbist_fail),
.spc_efc_ifuse_data (spc_efc_ifuse_data),
.spc_efc_dfuse_data (spc_efc_dfuse_data),
.pcx_spc_grant_px (pcx_spc_grant_px),
.cpx_spc_data_rdy_cx2 (cpx_spc_data_rdy_cx2),
.cpx_spc_data_cx2 (cpx_spc_data_cx2),
.const_cpuid (const_cpuid),
.const_maskid (const_maskid),
.ctu_tck (ctu_tck),
.ctu_sscan_se (ctu_sscan_se),
.ctu_sscan_snap (ctu_sscan_snap),
.ctu_sscan_tid (ctu_sscan_tid),
.ctu_tst_mbist_enable (ctu_tst_mbist_enable),
.efc_spc_fuse_clk1 (efc_spc_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc_fuse_clk2),
.efc_spc_ifuse_ashift (efc_spc_ifuse_ashift),
.efc_spc_ifuse_dshift (efc_spc_ifuse_dshift),
.efc_spc_ifuse_data (efc_spc_ifuse_data),
.efc_spc_dfuse_ashift (efc_spc_dfuse_ashift),
.efc_spc_dfuse_dshift (efc_spc_dfuse_dshift),
.efc_spc_dfuse_data (efc_spc_dfuse_data),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (spc_scanin0),
.spc_scanin1 (spc_scanin1),
.cluster_cken (cluster_cken),
.gclk (gclk),
.cmp_grst_l (cmp_grst_l),
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (adbginit_l),
.gdbginit_l (gdbginit_l)
);
endmodule
|
// -*- Mode: Verilog -*-
// Filename : equation_sum.v
// Description : Equation Sum
// Author : Philip Tracton
// Created On : Wed Jan 13 16:03:27 2016
// Last Modified By: Philip Tracton
// Last Modified On: Wed Jan 13 16:03:27 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module equation_sum (/*AUTOARG*/
// Outputs
wb_adr_o, wb_dat_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o,
wb_cti_o, wb_bte_o, equation_done,
// Inputs
wb_clk, wb_rst, wb_dat_i, wb_ack_i, wb_err_i, wb_rty_i,
base_address, equation_enable
) ;
parameter dw = 32;
parameter aw = 32;
parameter DEBUG = 0;
input wb_clk;
input wb_rst;
output wire [aw-1:0] wb_adr_o;
output wire [dw-1:0] wb_dat_o;
output wire [3:0] wb_sel_o;
output wire wb_we_o;
output wire wb_cyc_o;
output wire wb_stb_o;
output wire [2:0] wb_cti_o;
output wire [1:0] wb_bte_o;
input [dw-1:0] wb_dat_i;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
input [aw-1:0] base_address;
input equation_enable;
output equation_done;
assign wb_adr_o = 0 & {aw{equation_enable}};
assign wb_dat_o = 0 & {dw{equation_enable}};
assign wb_sel_o = 0 & equation_enable;
assign wb_we_o = 0 & equation_enable;
assign wb_cyc_o = 0 & equation_enable;
assign wb_stb_o = 0 & equation_enable;
assign wb_cti_o = 0 & equation_enable;
assign wb_bte_o = 0 & equation_enable;
assign equation_done = 0;
endmodule // equation_sum
|
#include <bits/stdc++.h> using namespace std; long long dp[5000010], f[5000010]; int main() { long long t, l, r, i, j, a, b, mod, ans, k = 1, final = 0; mod = 1e9 + 7; scanf( %lld %lld %lld , &t, &l, &r); for (i = 2; i <= r; i++) { if (dp[i] == 0) { for (j = i; j <= r; j += i) if (!dp[j]) dp[j] = i; } a = dp[i]; b = i / dp[i]; if (b == 1) f[i] = (i * (i - 1) / 2) % mod; else f[i] = (b * f[a] + f[b]) % mod; if (i >= l) { final = (final + k * f[i]) % mod; k = (k * t) % mod; } } printf( %lld n , final); return 0; } |
// Copyright (c) 2014 Takashi Toyoshima <>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
module SerialTransmitter(
clk_x4,
rst_x,
i_data,
i_valid,
o_tx,
o_busy,
o_error);
input clk_x4;
input rst_x;
input [7:0] i_data;
input i_valid;
output o_tx;
output o_busy;
output o_error;
reg r_tx;
reg [1:0] r_phase;
reg [3:0] r_state;
reg [7:0] r_data;
wire w_phase_next;
wire w_phase_shift;
localparam S_IDLE = 4'b0000;
localparam S_START = 4'b0001;
localparam S_BIT0 = 4'b0011;
localparam S_BIT1 = 4'b0010;
localparam S_BIT2 = 4'b0110;
localparam S_BIT3 = 4'b0111;
localparam S_BIT4 = 4'b0101;
localparam S_BIT5 = 4'b0100;
localparam S_BIT6 = 4'b1100;
localparam S_BIT7 = 4'b1101;
localparam S_STOP = 4'b1111;
assign w_phase_next = r_phase == 2'b10;
assign w_phase_shift = r_phase == 2'b11;
assign o_tx = r_tx;
assign o_busy = (r_state != S_IDLE) | i_valid;
assign o_error = (r_state != S_IDLE) & i_valid;
always @ (posedge clk_x4 or negedge rst_x) begin
if (!rst_x) begin
r_phase <= 2'b00;
end else begin
if (r_state == S_IDLE) begin
r_phase <= 2'b00;
end else begin
r_phase <= r_phase + 2'b01;
end
end // else (!rst_x)
end // always @ (posedge clk_x4 or negedge rst_x)
always @ (posedge clk_x4 or negedge rst_x) begin
if (!rst_x) begin
r_state <= S_IDLE;
r_data <= 8'h00;
r_tx <= 1'b1;
end else begin
case (r_state)
S_IDLE: begin
if (i_valid == 1'b1) begin
r_data <= i_data;
r_state <= S_START;
r_tx <= 1'b0;
end else if (r_tx == 1'b0) begin
r_tx <= 1'b1;
end
end // S_IDLE
S_START: begin
if (w_phase_shift) begin
r_state <= S_BIT0;
r_tx <= r_data[0];
end
end // S_START
S_BIT0: begin
if (w_phase_shift) begin
r_state <= S_BIT1;
r_tx <= r_data[1];
end
end // S_BIT0
S_BIT1: begin
if (w_phase_shift) begin
r_state <= S_BIT2;
r_tx <= r_data[2];
end
end // S_BIT1
S_BIT2: begin
if (w_phase_shift) begin
r_state <= S_BIT3;
r_tx <= r_data[3];
end
end // S_BIT2
S_BIT3: begin
if (w_phase_shift) begin
r_state <= S_BIT4;
r_tx <= r_data[4];
end
end // S_BIT3
S_BIT4: begin
if (w_phase_shift) begin
r_state <= S_BIT5;
r_tx <= r_data[5];
end
end // S_BIT4
S_BIT5: begin
if (w_phase_shift) begin
r_state <= S_BIT6;
r_tx <= r_data[6];
end
end // S_BIT5
S_BIT6: begin
if (w_phase_shift) begin
r_state <= S_BIT7;
r_tx <= r_data[7];
end
end // S_BIT6
S_BIT7: begin
if (w_phase_shift) begin
r_state <= S_STOP;
r_tx <= 1'b1;
end
end // S_BIT7
S_STOP: begin
if (w_phase_next) begin
r_state <= S_IDLE;
end
end // S_STOP
endcase // case (r_state)
end // else (!rst_x)
end // always @ (posedge clk_x4 or negedge rst_x)
endmodule // SerialTransmitter
|
#include <bits/stdc++.h> long long expow(long long a, long long b, long long p) { long long v = 1; for (; b; b >>= 1, a = a * a % p) if (b & 1) v = v * a % p; return v; } long long inv(long long a, long long p) { return expow(a, p - 2, p); } using namespace std; const int N = 1000 + 11; const int M = 1000000007; struct node { int a, b, c, d, e; } p[N]; node sub(node a, node b) { return (node){a.a - b.a, a.b - b.b, a.c - b.c, a.d - b.d, a.e - b.e}; } double mix(node a, node b) { return 1.0 * a.a * b.a + a.b * b.b + a.c * b.c + a.d * b.d + a.e * b.e; } vector<int> ans; int main() { int k; scanf( %d , &k); for (int i = 0; i < k; i++) { scanf( %d%d%d%d%d , &p[i].a, &p[i].b, &p[i].c, &p[i].d, &p[i].e); } for (int j = 0; j < k; j++) { bool f = false; for (int i = 0; i < k; i++) if (i != j) { for (int l = 0; l < k; l++) if (l != i && l != j) { node cha = sub(p[j], p[i]), cha2 = sub(p[j], p[l]); double ding = mix(cha, cha2), di = sqrt(mix(cha, cha)) * sqrt(mix(cha2, cha2)); double xx = ding / di; if (xx > 0 && xx <= 1) { f = true; break; } } if (f) break; } if (!f) ans.push_back(j + 1); } int sz = ans.size(); printf( %d n , sz); for (int j = 0; j < sz; j++) printf( %d n , ans[j]); return 0; } |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the convolutional encoder
// Import the modules that will be tested for in this testbench
`include "cencoder.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_cencoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [1:0] cout;
// Declare "reg" signals: inputs to the DUT
reg bin; // Input signal - b
reg ck; // Input clk signal
reg rset; // Input signal - reset
/**
* Set the clock signal, and its frequency
*
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/*
* Clock frequency is arbitrarily chosen
* Period = 10 ns, frequency = 100MHz
*/
#5 ck = 0;
#5 ck = 1;
end
/**
* Instantiate an instance of a convolutional encoder so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "enc"
*/
conv_encoder enc (
// instance_name(signal name),
// Signal name can be the same as the instance name
cout,bin,ck,rset);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
// @t=0,
bin = 1'b0;
rset=0;
// @ t=3,
#3;
bin = 1'b1;
rset=0;
// @ t=10,
#7;
bin = 1'b0;
rset=0;
// @ t=19,
#9;
bin = 1'b1;
rset=0;
// @ t=29,
#10;
bin = 1'b0;
rset=0;
// @ t=39,
#10;
bin = 1'b1;
rset=0;
// @ t=50-1,
#10;
bin = 1'b0;
rset=0;
// @ t=60-1,
#10;
bin = 1'b1;
rset=0;
// @ t=70-1,
#10;
bin = 1'b0;
rset=0;
// @ t=80-1,
#10;
bin = 1'b0;
rset=0;
// @ t=90-1,
#10;
bin = 1'b1;
rset=0;
// @ t=100-1,
#10;
bin = 1'b1;
rset=1;
// @ t=110-1,
#9;
bin = 1'b0;
rset=0;
// @ t=120-1,
#10;
bin = 1'b1;
rset=0;
// @ t=130-1,
#10;
bin = 1'b0;
rset=0;
// @ t=140-1,
#10;
bin = 1'b1;
rset=1;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; using uint = unsigned int; using ll = long long; using ull = unsigned long long; template <class T = ll> constexpr T TEN(int n) { return (n == 0) ? 1 : 10 * TEN<T>(n - 1); } ll calc(string s) { int n = int(s.size()); if (n == 1) { if (s[0] == 9 ) { return 1989; } else { return 1990 + s[0] - 0 ; } } ll u = calc(s.substr(1)); u += TEN(n - 1); while (true) { if (u / TEN(n - 1) % 10 == s[0] - 0 ) break; u += TEN(n - 1); } return u; } int main() { int n; cin >> n; for (int i = 0; i < n; i++) { string s; cin >> s; s = s.substr(4); cout << calc(s) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; int v[1010][1010], v1[1010][1010], tip[100], n, m; char sir[2010][1010], sir1[2010][1010]; void transpune() { for (int i = 1; i < 2 * m; i++) if (i % 2) for (int j = 1; j < n; j++) sir1[i][j] = sir[2 * j][i / 2 + 1]; else for (int j = 1; j <= n; j++) sir1[i][j] = sir[2 * j - 1][i / 2]; swap(n, m); for (int i = 1; i < 2 * n; i++) for (int j = 1; j <= m - i % 2; j++) sir[i][j] = sir1[i][j]; } int solve1() { int sol = 0; for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { if (j < m) sol += sir[2 * i - 1][j] == E ; if (i < n) sol += sir[2 * i][j] == E ; } return 4 * sol >= 3 * (2 * n * m - n - m); } int solve2() { int transpus = 0; if (n > m) { transpune(); transpus = 1; } for (int i = 1; i <= n; i++) { v[i][1] = 0; for (int j = 2; j <= m; j++) v[i][j] = v[i][j - 1] ^ tip[sir[2 * i - 1][j - 1]]; if (i > 1) { int nr = 0; for (int j = 1; j <= m; j++) nr += (v[i][j] == v[i - 1][j]) ^ tip[sir[2 * i - 2][j]]; if (2 * nr < m) for (int j = 1; j <= m; j++) v[i][j] ^= 1; } } if (transpus) { for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) v1[j][i] = v[i][j]; swap(n, m); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) v[i][j] = v1[i][j]; } return 1; } int main() { int k, ok; scanf( %d%d%d , &n, &m, &k); for (int i = 1; i < 2 * n; i++) scanf( n%s , sir[i] + 1); tip[ E ] = 0; tip[ N ] = 1; if (k == 1) ok = solve1(); else ok = solve2(); if (ok) { printf( YES n ); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) printf( %d , v[i][j] + 1); printf( n ); } } else printf( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; string s; cin >> s; int a[n], i, j, k, cnt = 1e9, tmp = 0; for (i = 0; i < n; i++) cin >> a[i]; for (i = 0; i < s.size() - 1; i++) { if (s[i] == R && s[i + 1] == L ) { tmp = (a[i + 1] - a[i]) / 2; if (tmp < cnt) cnt = tmp; } } if (cnt == 1e9) cout << -1 << endl; else cout << cnt << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10, P = 998244353; const double Pi = acos(-1); inline int read() { int x = 0, f = 1, ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 48, ch = getchar(); return x * f; } inline int Add(int a, int b) { return a + b >= P ? a + b - P : a + b; } inline int Sub(int a, int b) { return a - b < 0 ? a - b + P : a - b; } inline int Mul(int a, int b) { long long res = 1ll * a * b; return res >= P ? res % P : res; } inline int qpow(int a, int b) { int res = 1; while (b) { if (b & 1) res = Mul(res, a); a = Mul(a, a); b >>= 1; } return res; } int n; int dp[3][N]; int cnt, head[N]; struct Edge { int to, nxt; } edge[N << 1]; inline void AddEdge(int u, int v) { edge[++cnt] = (Edge){v, head[u]}; head[u] = cnt; return; } void solve(int u, int fa) { dp[0][u] = dp[2][u] = 1; for (int i = head[u], v; i; i = edge[i].nxt) { v = edge[i].to; if (v == fa) continue; solve(v, u); dp[0][u] = Mul(dp[0][u], Add(dp[0][v], dp[1][v])); dp[1][u] = Add(dp[1][u], Mul(dp[2][v], qpow(Add(dp[0][v], Mul(2, dp[1][v])), P - 2))); dp[2][u] = Mul(dp[2][u], Add(dp[0][v], Mul(2, dp[1][v]))); } dp[1][u] = Mul(dp[1][u], dp[2][u]); } signed main() { n = read(); for (register int i = 2; i <= n; ++i) { int a = read(), b = read(); AddEdge(a, b), AddEdge(b, a); } solve(1, 0); printf( %d n , Add(dp[0][1], dp[1][1])); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:06:52 06/28/2009
// Design Name:
// Module Name: dcm
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module my_dcm (
input CLKIN,
output CLKFX,
output LOCKED,
input RST,
output[7:0] STATUS
);
// DCM: Digital Clock Manager Circuit
// Spartan-3
// Xilinx HDL Language Template, version 11.1
DCM #(
.SIM_MODE("SAFE"), // Simulation: "SAFE" vs. "FAST", see "Synthesis and Simulation Design Guide" for details
.CLKDV_DIVIDE(2.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
// 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
.CLKFX_DIVIDE(1), // Can be any integer from 1 to 32
.CLKFX_MULTIPLY(4), // Can be any integer from 2 to 32
.CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
.CLKIN_PERIOD(41.667), // Specify period of input clock
.CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift of NONE, FIXED or VARIABLE
.CLK_FEEDBACK("NONE"), // Specify clock feedback of NONE, 1X or 2X
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
// an integer from 0 to 15
.DFS_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for frequency synthesis
.DLL_FREQUENCY_MODE("LOW"), // HIGH or LOW frequency mode for DLL
.DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
.FACTORY_JF(16'hFFFF), // FACTORY JF values
// .LOC("DCM_X0Y0"),
.PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 255
.STARTUP_WAIT("TRUE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
) DCM_inst (
.CLK0(CLK0), // 0 degree DCM CLK output
.CLK180(CLK180), // 180 degree DCM CLK output
.CLK270(CLK270), // 270 degree DCM CLK output
.CLK2X(CLK2X), // 2X DCM CLK output
.CLK2X180(CLK2X180), // 2X, 180 degree DCM CLK out
.CLK90(CLK90), // 90 degree DCM CLK output
.CLKDV(CLKDV), // Divided DCM CLK out (CLKDV_DIVIDE)
.CLKFX(CLKFX), // DCM CLK synthesis out (M/D)
.CLKFX180(CLKFX180), // 180 degree CLK synthesis out
.LOCKED(LOCKED), // DCM LOCK status output
.PSDONE(PSDONE), // Dynamic phase adjust done output
.STATUS(STATUS), // 8-bit DCM status bits output
.CLKFB(CLKFB), // DCM clock feedback
.CLKIN(CLKIN), // Clock input (from IBUFG, BUFG or DCM)
.PSCLK(PSCLK), // Dynamic phase adjust clock input
.PSEN(PSEN), // Dynamic phase adjust enable input
.PSINCDEC(PSINCDEC), // Dynamic phase adjust increment/decrement
.RST(RST) // DCM asynchronous reset input
);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MOD = 998244353; vector<vector<int>> edges; long long DP[200010]; long long fac[200010]; void solve(const int u, const int p) { DP[u] = 1; int tot = 0; for (auto& e : edges[u]) { if (e != p) { tot++; solve(e, u); DP[u] = (DP[u] * DP[e]) % MOD; } } DP[u] = (DP[u] * fac[tot]) % MOD; if (u != 1 && tot) DP[u] = ((tot + 1) * DP[u]) % MOD; } int main() { fac[0] = 1; for (int i = 1; i <= 200000; i++) fac[i] = (fac[i - 1] * i) % MOD; int N, t, f; scanf( %d , &N); edges.assign(N + 5, vector<int>()); for (int i = 0; i < N - 1; i++) { scanf( %d %d , &t, &f); edges[t].push_back(f); edges[f].push_back(t); } solve(1, 1); printf( %d n , int((N * DP[1]) % MOD)); return 0; } |
//rgmii-gmii,gmii-139,rx check,rx gen
`timescale 1ns/1ns
module sfp_rx_tx_1000(
clk,
sfp_clk,
reset,
gmii_rx_clk,
gmii_tx_clk,
sfp_rxp,
sfp_txp,
l_link_sfp,
r_act_sfp,
crc_data_valid,//rx data fifo
crc_data,
pkt_usedw,
pkt_valid_wrreq,
pkt_valid,
crc_gen_to_txfifo_wrreq,//tx fifo;
crc_gen_to_txfifo_data,
txfifo_data_usedw,
pkt_output_valid_wrreq,
pkt_output_valid,
port_receive,
port_discard,
port_send,
port_pream
);
input clk;
input sfp_clk;
input reset;
output gmii_rx_clk;
output gmii_tx_clk;
input sfp_rxp;
output sfp_txp;
output l_link_sfp;
output r_act_sfp;
output crc_data_valid;//to data fifo(crc check module);
output [138:0] crc_data;
input [7:0]pkt_usedw;
output pkt_valid_wrreq;//a full pkt,to flag fifo;
output pkt_valid;
input crc_gen_to_txfifo_wrreq;//data to txfifo;
input [138:0]crc_gen_to_txfifo_data;
output [7:0]txfifo_data_usedw;//data fifo usedw;
input pkt_output_valid_wrreq;//flag to flagfifo;
input pkt_output_valid;
output port_receive;
output port_discard;
output port_send;
output port_pream;
wire [7:0]gmii_txd;
wire gmii_txen;
wire gmii_txer;
wire [7:0]gmii_rxd;
wire gmii_rxen;
wire gmii_rxer;
wire gmii_rx_clk;//gmii rx clk;
wire gmii_tx_clk;//gmii tx clk;
wire crc_data_valid;//to data fifo(crc check module);
wire [138:0] crc_data;
wire pkt_valid_wrreq;//a full pkt,to flag fifo;
wire pkt_valid;
wire [7:0]txfifo_data_usedw;
wire port_receive;
wire port_discard;
wire port_send;
wire port_pream;
gmii_139_1000 gmii_139(
.clk(gmii_rx_clk),
.reset(reset),
.gmii_rxd(gmii_rxd),
.gmii_rxdv(gmii_rxen),
.gmii_rxer(gmii_rxer),
.crc_data_valid(crc_data_valid),
.crc_data(crc_data),
.pkt_usedw(pkt_usedw),
.pkt_valid_wrreq(pkt_valid_wrreq),
.pkt_valid(pkt_valid),
.port_receive(port_receive),
.port_discard(port_discard),
.port_pream(port_pream)
);
tx139_gmii_1000 tx139_gmii(
.clk(clk),//system clk;
.reset(reset),
.gmii_txclk(gmii_tx_clk),
.crc_gen_to_txfifo_wrreq(crc_gen_to_txfifo_wrreq),
.crc_gen_to_txfifo_data(crc_gen_to_txfifo_data),
.pkt_output_valid_wrreq(pkt_output_valid_wrreq),
.pkt_output_valid(pkt_output_valid),
.gmii_txd(gmii_txd),
.gmii_txen(gmii_txen),
.gmii_txer(gmii_txer),
.txfifo_data_usedw(txfifo_data_usedw),//output_data_usedw0;
.port_send(port_send)
);
wire l_link_sfp0;
wire l_link_sfp;
assign l_link_sfp = ~l_link_sfp0;
sfp2gmii sfp2gmii(
.gmii_rx_d(gmii_rxd),
.gmii_rx_dv(gmii_rxen),
.gmii_rx_err(gmii_rxer),
.tx_clk(gmii_tx_clk),
.rx_clk(gmii_rx_clk),
.readdata(),
.waitrequest(),
.txp(sfp_txp),
.reconfig_fromgxb(),
.led_an(),
.led_disp_err(),
.led_char_err(),
.led_link(l_link_sfp0),
.gmii_tx_d(gmii_txd),
.gmii_tx_en(gmii_txen),
.gmii_tx_err(gmii_txer),
.reset_tx_clk(~reset),
.reset_rx_clk(~reset),
.address(5'b0),
.read(1'b0),
.writedata(16'b0),
.write(1'b0),
.clk(clk),
.reset(~reset),
.rxp(sfp_rxp),
.ref_clk(sfp_clk),
.reconfig_clk(1'b0),
.reconfig_togxb(3'b010),
.gxb_cal_blk_clk(sfp_clk)
);
act_led act_led(
.clk(clk),
.reset(reset),
.gmii_rxen(gmii_rxen),
.gmii_txen(gmii_txen),
.r_act_sfp(r_act_sfp)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int t; cin >> t; while (t--) { int n, max = 0, count1 = 0; cin >> n; vector<int> v; for (int i = 0; i < n; i++) { int x; cin >> x; v.push_back(x); if (max < x) { max = x; } } int c = v[0]; for (int i = 0; i < v.size(); i++) { if (v[i] == c) { count1++; } c = v[i]; } if (count1 == n) { cout << 0 << endl; } else { vector<int> v1(10000); map<int, int> mp; long long int sum; for (int i = 0; i < n; i++) { sum = v[i]; for (int j = i + 1; j < n; j++) { sum = sum + v[j]; if (sum <= 8000) { v1[sum] = 1; } } } int count = 0; for (int i = 0; i < n; i++) { if (v1[v[i]]) { count++; } } cout << count << endl; } } } |
#include <bits/stdc++.h> const int INF = 0x3f3f3f3f; const int MAXN = 1e3 + 10; using namespace std; char str[MAXN][MAXN]; int data[MAXN]; int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) cin >> str[i]; for (int i = 0; i < m; i++) cin >> data[i]; long long ans = 0; for (int i = 0; i < m; i++) { int temp[10] = {0}, tmp = -1; for (int j = 0; j < n; j++) temp[str[j][i] - A ]++; for (int j = 0; j < 5; j++) tmp = max(tmp, temp[j]); ans += (long long)tmp * data[i]; } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, a[1111][1111]; int main() { scanf( %d , &n); for (int i = 0; i < n - 1; i++) for (int j = 0; j < n - 1; j++) a[i][j] = 1 + (i + j) % (n - 1); for (int i = 0; i < n - 1; i++) a[n - 1][i] = a[i][n - 1] = a[i][i], a[i][i] = 0; for (int i = 0; i < n; i++) { for (int j = 0; j < n; j++) printf( %d , a[i][j]); printf( n ); } return 0; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: font.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module font (
address,
clock,
q);
input [10:0] address;
input clock;
output [5:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] sub_wire0;
wire [5:0] q = sub_wire0[5:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({6{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "font.mif",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 6,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "font.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
// Retrieval info: PRIVATE: WidthData NUMERIC "6"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "font.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "6"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 6 0 OUTPUT NODEFVAL "q[5..0]"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 6 0 @q_a 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL font.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL font.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL font.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL font.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL font_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL font_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL font_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL font_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( unroll-loops ) using namespace std; template <class T> inline T bigmod(T p, T e, T M) { long long ret = 1; for (; e > 0; e >>= 1) { if (e & 1) ret = (ret * p) % M; p = (p * p) % M; } return (T)ret; } template <class T> inline T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> inline T modinverse(T a, T M) { return bigmod(a, M - 2, M); } template <class T> inline T lcm(T a, T b) { a = abs(a); b = abs(b); return (a / gcd(a, b)) * b; } template <class T, class X> inline bool getbit(T a, X i) { T t = 1; return ((a & (t << i)) > 0); } template <class T, class X> inline T setbit(T a, X i) { T t = 1; return (a | (t << i)); } template <class T, class X> inline T resetbit(T a, X i) { T t = 1; return (a & (~(t << i))); } inline long long getnum() { char c = getchar(); long long num, sign = 1; for (; c < 0 || c > 9 ; c = getchar()) if (c == - ) sign = -1; for (num = 0; c >= 0 && c <= 9 ;) { c -= 0 ; num = num * 10 + c; c = getchar(); } return num * sign; } inline long long power(long long a, long long b) { long long multiply = 1; for (int i = (0); i < (b); i++) { multiply *= a; } return multiply; } struct MagicComponents { struct edge { long long u, v, id; }; long long num, n, edges; vector<long long> dfs_num, low, vis; vector<long long> cuts; vector<edge> bridges; vector<vector<edge>> adj; vector<vector<edge>> bccs; deque<edge> e_stack; MagicComponents(const long long& _n) : n(_n) { adj.assign(n, vector<edge>()); edges = 0; } void add_edge(const long long& u, const long long& v) { adj[u].push_back({u, v, edges}); adj[v].push_back({v, u, edges++}); } void run(void) { vis.assign(n, 0); dfs_num.assign(n, 0); low.assign(n, 0); bridges.clear(); cuts.clear(); bccs.clear(); e_stack = deque<edge>(); num = 0; for (long long i = 0; i < n; ++i) { if (vis[i]) continue; dfs(i, -1); } } void dfs(const long long& node, const long long& par) { dfs_num[node] = low[node] = num++; vis[node] = 1; long long n_child = 0; for (edge& e : adj[node]) { if (e.v == par) continue; if (vis[e.v] == 0) { ++n_child; e_stack.push_back(e); dfs(e.v, node); low[node] = min(low[node], low[e.v]); if (low[e.v] >= dfs_num[node]) { if (dfs_num[node] > 0 || n_child > 1) cuts.push_back(node); if (low[e.v] > dfs_num[node]) { bridges.push_back(e); pop(node); } else pop(node); } } else if (vis[e.v] == 1) { low[node] = min(low[node], dfs_num[e.v]); e_stack.push_back(e); } } vis[node] = 2; } void pop(const long long& u) { vector<edge> list; for (;;) { edge e = e_stack.back(); e_stack.pop_back(); list.push_back(e); if (e.u == u) break; } bccs.push_back(list); } }; int n, m, q; vector<int> bcc_nodes[100005], tree[100005 * 2]; int L[2 * 100005], table[2 * 100005][19]; void buildTree(int sz, int& _n) { for (int i = (0); i < (sz); i++) { _n++; for (auto it : bcc_nodes[i]) { tree[_n].push_back(it); tree[it].push_back(_n); } } } int query(int p, int q) { if (L[p] < L[q]) swap(p, q); int x = 1; while (true) { if ((1 << (x + 1)) > L[p]) break; x++; } for (int i = (x); i >= (0); i--) { if (L[p] - (1 << i) >= L[q]) p = table[p][i]; } if (p == q) return p; for (int i = (x); i >= (0); i--) { if (table[p][i] != -1 && table[p][i] != table[q][i]) { p = table[p][i]; q = table[q][i]; } } return table[p][0]; } void dfs2(int u, int p = -1, int d = 0) { L[u] = d; table[u][0] = p; for (auto v : tree[u]) { if (v == p) continue; dfs2(v, u, d + 1); } } void build(int _n) { memset(table, -1, sizeof(table)); dfs2(1); for (int j = 1; 1 << j < _n; j++) { for (int i = 1; i <= _n; i++) { if (table[i][j - 1] != -1) table[i][j] = table[table[i][j - 1]][j - 1]; } } } int getdist(int u, int v) { int lca = query(u, v); int ret = L[u] + L[v] - 2 * L[lca]; return ret; } int main() { int test, cases = 1; scanf( %d%d%d , &n, &m, &q); MagicComponents magic(n + 2); int u, v; for (int i = (0); i < (m); i++) { scanf( %d%d , &u, &v); magic.add_edge(u, v); } magic.run(); int sz = magic.bccs.size(); for (int i = (0); i < (sz); i++) { for (auto it : magic.bccs[i]) { bcc_nodes[i].push_back(it.u); bcc_nodes[i].push_back(it.v); } sort(bcc_nodes[i].begin(), bcc_nodes[i].end()); bcc_nodes[i].erase(unique(bcc_nodes[i].begin(), bcc_nodes[i].end()), bcc_nodes[i].end()); } int _n = n; buildTree(sz, _n); build(_n); while (q--) { scanf( %d%d , &u, &v); int out = getdist(u, v); printf( %d n , out / 2); } return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_bram_top_v6.v
// Version : 1.7
//--
//-- Description: BlockRAM top level module for Virtex6 PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_bram_top_v6
#(
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0,
parameter VC0_TX_LASTPACKET = 31,
parameter TLM_TX_OVERHEAD = 24,
parameter TL_TX_RAM_RADDR_LATENCY = 1,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_WRITE_LATENCY = 1,
parameter VC0_RX_LIMIT = 'h1FFF,
parameter TL_RX_RAM_RADDR_LATENCY = 1,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_RX_RAM_WRITE_LATENCY = 1
)
(
input user_clk_i,
input reset_i,
input mim_tx_wen,
input [12:0] mim_tx_waddr,
input [71:0] mim_tx_wdata,
input mim_tx_ren,
input mim_tx_rce,
input [12:0] mim_tx_raddr,
output [71:0] mim_tx_rdata,
input mim_rx_wen,
input [12:0] mim_rx_waddr,
input [71:0] mim_rx_wdata,
input mim_rx_ren,
input mim_rx_rce,
input [12:0] mim_rx_raddr,
output [71:0] mim_rx_rdata
);
// TX calculations
localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 :
1024 );
localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
localparam ROWS_TX = 1;
localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 :
(BYTES_TX <= 8192) ? 2 :
(BYTES_TX <= 16384) ? 4 :
(BYTES_TX <= 32768) ? 8 :
18
);
// RX calculations
localparam ROWS_RX = 1;
localparam COLS_RX = ((VC0_RX_LIMIT < 'h0200) ? 1 :
(VC0_RX_LIMIT < 'h0400) ? 2 :
(VC0_RX_LIMIT < 'h0800) ? 4 :
(VC0_RX_LIMIT < 'h1000) ? 8 :
18
);
initial begin
$display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX);
$display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX);
end
pcie_brams_v6 #(.NUM_BRAMS (COLS_TX),
.RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY))
pcie_brams_tx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_tx_waddr),
.wen(mim_tx_wen),
.ren(mim_tx_ren),
.rce(mim_tx_rce),
.wdata(mim_tx_wdata),
.raddr(mim_tx_raddr),
.rdata(mim_tx_rdata)
);
pcie_brams_v6 #(.NUM_BRAMS (COLS_RX),
.RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY))
pcie_brams_rx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_rx_waddr),
.wen(mim_rx_wen),
.ren(mim_rx_ren),
.rce(mim_rx_rce),
.wdata(mim_rx_wdata),
.raddr(mim_rx_raddr),
.rdata(mim_rx_rdata)
);
endmodule // pcie_bram_top
|
#include <bits/stdc++.h> using namespace std; char oda[3500]; int y; void PuLe(int x) { int j; j = x; while (oda[j - 1] == . ) { oda[j - 1] = @ ; j--; } if (oda[j - 1] == R ) { if ((x - j) % 2 != 0) oda[x - ((x - j) / 2 + 1)] = . ; } } void PuRi(int x) { int j; j = x; while (oda[j + 1] == . ) { oda[j + 1] = @ ; j++; } if (oda[j + 1] == L ) { if ((j - x) % 2 != 0) oda[(j - x) / 2 + 1 + x] = . ; } } int main() { int n; while (cin >> n) { int i, count = 0; cin >> oda; for (i = 0; i < n; i++) { if (oda[i] == L ) PuLe(i); if (oda[i] == R ) PuRi(i); } for (i = 0; i < n; i++) if (oda[i] == . ) count++; cout << count; cout << endl; } } |
#include <bits/stdc++.h> using namespace std; int main() { int t, n; cin >> t; for (int l = 0; l < t; l++) { cin >> n; int k; k = 0; int c; c = 0; char arr[n][5]; for (int i = 0; i < n; i++) { for (int j = 0; j < 5; j++) { cin >> arr[i][j]; } } for (int j = 0; j < 5; j++) { k = 0; for (int m = j + 1; m < 5; m++) { int first = 0; int second = 0; int tie = 0; for (int n1 = 0; n1 < n; n1++) { if (arr[n1][j] == 1 && arr[n1][m] == 1 ) { tie++; } else { if (arr[n1][j] == 1 ) { second++; } if (arr[n1][m] == 1 ) { first++; } } } if (first + second + tie == n && second + tie >= n / 2 && first + tie >= n / 2) { c = 1; } } } if (c == 0) { cout << NO << endl; } else { cout << YES << endl; } } return 0; } |
module constmuldivmod(input [7:0] A, input [5:0] mode, output reg [7:0] Y);
always @* begin
case (mode)
0: Y = A / 8'd0;
1: Y = A % 8'd0;
2: Y = A * 8'd0;
3: Y = A / 8'd1;
4: Y = A % 8'd1;
5: Y = A * 8'd1;
6: Y = A / 8'd2;
7: Y = A % 8'd2;
8: Y = A * 8'd2;
9: Y = A / 8'd4;
10: Y = A % 8'd4;
11: Y = A * 8'd4;
12: Y = A / 8'd8;
13: Y = A % 8'd8;
14: Y = A * 8'd8;
15: Y = $signed(A) / $signed(8'd0);
16: Y = $signed(A) % $signed(8'd0);
17: Y = $signed(A) * $signed(8'd0);
18: Y = $signed(A) / $signed(8'd1);
19: Y = $signed(A) % $signed(8'd1);
20: Y = $signed(A) * $signed(8'd1);
21: Y = $signed(A) / $signed(8'd2);
22: Y = $signed(A) % $signed(8'd2);
23: Y = $signed(A) * $signed(8'd2);
24: Y = $signed(A) / $signed(8'd4);
25: Y = $signed(A) % $signed(8'd4);
26: Y = $signed(A) * $signed(8'd4);
27: Y = $signed(A) / $signed(8'd8);
28: Y = $signed(A) % $signed(8'd8);
29: Y = $signed(A) * $signed(8'd8);
30: Y = $signed(A) / $signed(-8'd0);
31: Y = $signed(A) % $signed(-8'd0);
32: Y = $signed(A) * $signed(-8'd0);
33: Y = $signed(A) / $signed(-8'd1);
34: Y = $signed(A) % $signed(-8'd1);
35: Y = $signed(A) * $signed(-8'd1);
36: Y = $signed(A) / $signed(-8'd2);
37: Y = $signed(A) % $signed(-8'd2);
38: Y = $signed(A) * $signed(-8'd2);
39: Y = $signed(A) / $signed(-8'd4);
40: Y = $signed(A) % $signed(-8'd4);
41: Y = $signed(A) * $signed(-8'd4);
42: Y = $signed(A) / $signed(-8'd8);
43: Y = $signed(A) % $signed(-8'd8);
44: Y = $signed(A) * $signed(-8'd8);
default: Y = 8'd16 * A;
endcase
end
endmodule
|
#include <bits/stdc++.h> #pragma GCC optimize(2) using namespace std; namespace IO_Optimization { inline int read() { int X = 0, w = 0; char ch = 0; while (!isdigit(ch)) { w |= ch == - ; ch = getchar(); } while (isdigit(ch)) { X = (X << 3) + (X << 1) + (ch ^ 48); ch = getchar(); } return w ? -X : X; } inline void write(long long x) { if (x < 0) putchar( - ), x = -x; if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } } // namespace IO_Optimization using namespace IO_Optimization; int n, k; double sum; struct Node { int num, pos; } a[2000 + 2], b[2000 + 2]; struct Trans { int s[2000 + 2]; } ans[2000 + 2]; int tot1, tot2; inline bool cmp(Node x, Node y) { return x.num > y.num; } int main() { n = read(), k = read(); for (register int i = 1; i <= n; ++i) { int x = read(), y = read(); if (y == 1) a[++tot1].num = x, a[tot1].pos = i; else b[++tot2].num = x, b[tot2].pos = i; } sort(a + 1, a + 1 + tot1, cmp); int noww = k - 1 < tot1 ? k - 1 : tot1; for (register int i = 1; i <= noww; ++i) { ans[i].s[++ans[i].s[0]] = a[i].pos; sum += a[i].num * 0.5; } if (tot1 <= k - 1) { for (register int i = 1; i <= tot2; ++i) { int nowww = tot1 + i < k ? tot1 + i : k; sum += b[i].num; ans[nowww].s[++ans[nowww].s[0]] = b[i].pos; } } else { int minn = 1e9; for (register int i = k; i <= tot1; ++i) { sum += a[i].num; ans[k].s[++ans[k].s[0]] = a[i].pos; minn = a[i].num < minn ? a[i].num : minn; } for (register int i = 1; i <= tot2; ++i) { sum += b[i].num; ans[k].s[++ans[k].s[0]] = b[i].pos; minn = b[i].num < minn ? b[i].num : minn; } sum -= minn * 0.5; } printf( %.1lf n , sum); for (register int i = 1; i <= k; ++i, puts( )) { write(ans[i].s[0]); cout << ; for (register int j = 1; j <= ans[i].s[0]; ++j) { write(ans[i].s[j]); cout << ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; using uint = unsigned; using ll = long long; using ull = unsigned long long; using vi = vector<int>; using vvi = vector<vi>; using vl = vector<ll>; using vvl = vector<vl>; using vd = vector<double>; using vvd = vector<vd>; using vs = vector<string>; template <typename T1, typename T2> ostream& operator<<(ostream& os, const pair<T1, T2>& p) { return os << ( << p.first << , << p.second << ) ; } template <typename Tuple> void print_tuple(ostream&, const Tuple&) {} template <typename Car, typename... Cdr, typename Tuple> void print_tuple(ostream& os, const Tuple& t) { print_tuple<Cdr...>(os, t); os << (sizeof...(Cdr) ? , : ) << get<sizeof...(Cdr)>(t); } template <typename... Args> ostream& operator<<(ostream& os, const tuple<Args...>& t) { print_tuple<Args...>(os << ( , t); return os << ) ; } template <typename Ch, typename Tr, typename C> basic_ostream<Ch, Tr>& operator<<(basic_ostream<Ch, Tr>& os, const C& c) { os << [ ; for (auto i = begin(c); i != end(c); ++i) os << (i == begin(c) ? : ) << *i; return os << ] ; } constexpr int INF = 1e9; constexpr int MOD = 1e9 + 7; constexpr double EPS = 1e-9; int main() { for (int n; cin >> n && n;) { vi a(n); for (int i = int(0); i < int(n); i++) cin >> a[i]; ll mx = *max_element(begin(a), end(a)), sum = accumulate(begin(a), end(a), 0ll); cout << max<ll>(2 * mx - sum, 0) + 1 << endl; } } |
//#############################################################################
//# Function: CRC combinatorial encoder wrapper #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_crc #( parameter TYPE = "ETH", // type: "ETH", "OTHER"
parameter DW = 8) // width of data
(
input [DW-1:0] data_in, // input data
input [CW-1:0] crc_state, // input crc state
output [CW-1:0] crc_next // next crc state
);
localparam CW = 32; // width of polynomial
generate
if(TYPE=="ETH")
begin
if(DW==8)
oh_crc32_8b crc(/*AUTOINST*/
// Outputs
.crc_next (crc_next[31:0]),
// Inputs
.data_in (data_in[7:0]),
.crc_state (crc_state[31:0]));
else if(DW==64)
oh_crc32_64b crc(/*AUTOINST*/
// Outputs
.crc_next (crc_next[31:0]),
// Inputs
.data_in (data_in[63:0]),
.crc_state (crc_state[31:0]));
end // if (TYPE=="ETH")
endgenerate
endmodule // oh_crc
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_generic_ddio(
datain,
halfratebypass,
dataout,
clk_hr,
clk_fr
);
parameter WIDTH = 1;
localparam DATA_IN_WIDTH = 4 * WIDTH;
localparam DATA_OUT_WIDTH = WIDTH;
input [DATA_IN_WIDTH-1:0] datain;
input halfratebypass;
input [WIDTH-1:0] clk_hr;
input [WIDTH-1:0] clk_fr;
output [DATA_OUT_WIDTH-1:0] dataout;
generate
genvar pin;
for (pin = 0; pin < WIDTH; pin = pin + 1)
begin:acblock
wire fr_data_hi;
wire fr_data_lo;
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_hi (
.datainhi(datain[pin * 4]),
.datainlo(datain[pin * 4 + 2]),
.dataout(fr_data_hi),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_lo (
.datainhi(datain[pin * 4 + 1]),
.datainlo(datain[pin * 4 + 3]),
.dataout(fr_data_lo),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.async_mode("none"),
.half_rate_mode("false"),
.sync_mode("none"),
.use_new_clocking_model("true")
) ddio_out (
.datainhi(fr_data_hi),
.datainlo(fr_data_lo),
.dataout(dataout[pin]),
.clkhi (clk_fr[pin]),
.clklo (clk_fr[pin]),
.muxsel (clk_fr[pin])
);
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { vector<long long> v; set<long long> myset; set<long long>::iterator it; long long n, k, q, t; map<long long, int> mp; cin >> n >> k; for (long long i = 0; i < n; i++) { scanf( %I64d , &t); v.push_back(t); myset.insert(t); mp[t]++; } sort(v.begin(), v.end()); if (v.size() == myset.size()) { if (k % n != 0 && n < k) { long long m = k / n; long long p = m * n; long long u = v[m]; long long x = 0; for (long long i = p + 1; i <= k; i++) { q = v[x]; ++x; } cout << u << << q << endl; return 0; } if (k % n == 0 && n <= k) { cout << v[(k / n) - 1] << << v[n - 1] << endl; return 0; } if (k < n) { cout << v[0] << << v[k - 1] << endl; return 0; } } else { long long sum = 0, b; for (it = myset.begin(); it != myset.end(); ++it) { sum += (mp[*it] * n); if (k <= sum) { b = *it; sum -= (mp[*it] * n); break; } } long long cnt = sum; for (long long i = 0; i < n; i++) { cnt += mp[b]; if (cnt >= k) { cout << b << << v[i] << endl; break; } } } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:13:57 01/01/2017
// Design Name:
// Module Name: Random
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Random(
input wire clk,
input wire [3:0] direction,
input wire [4:0] road_on, car_on,
output reg [4:0] path,
output reg [1:0] speed_data0, speed_data1, speed_data2, speed_data3, speed_data4,
output reg [2:0] obstacle_num
);
reg [ 2:0] x;
reg [10:0] cnt;
wire [2:0] temp_num;
initial
begin
x <= 3'b0;
cnt <= 11'b0;
end
assign temp_num = (path + 233) % 5;
always @ (posedge clk)
begin
if (direction != 4'b0)
begin
x <= (x + 1023) % 5;
cnt <= cnt + 1023;
end
else
begin
x <= (x + 1) % 5;
cnt <= cnt + 1;
end
case (temp_num)
3'b000:
begin
if (car_on[0] != 1'b1)
begin
obstacle_num <= temp_num;
end
end
3'b001:
begin
if (car_on[1] != 1'b1)
begin
obstacle_num <= temp_num;
end
end
3'b010:
begin
if (car_on[2] != 1'b1)
begin
obstacle_num <= temp_num;
end
end
3'b011:
begin
if (car_on[3] != 1'b1)
begin
obstacle_num <= temp_num;
end
end
3'b100:
begin
if (car_on[4] != 1'b1)
begin
obstacle_num <= temp_num;
end
end
endcase
case (x)
3'b000:
begin
if (road_on[0] != 1'b1)
begin
path <= 5'b00001;
end
end
3'b001:
begin
if (road_on[1] != 1'b1)
begin
path <= 5'b00010;
end
end
3'b010:
begin
if (road_on[2] != 1'b1)
begin
path <= 5'b00100;
end
end
3'b011:
begin
if (road_on[3] != 1'b1)
begin
path <= 5'b01000;
end
end
3'b100:
begin
if (road_on[4] != 1'b1)
begin
path <= 5'b10000;
end
end
endcase
case (obstacle_num)
3'b000:
begin
speed_data0 <= 1;
end
3'b001:
begin
speed_data1 <= 2;
end
3'b010:
begin
speed_data2 <= 2;
end
3'b011:
begin
speed_data3 <= 3;
end
3'b100:
begin
speed_data4 <= 3;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long i, a[3333]; int t, n; cin >> t; while (t--) { cin >> n; for (i = 0; i < n; i++) cin >> a[i]; sort(a, a + n); long long x; x = a[0] * a[n - 1]; int flag = 1, ans = 0; for (i = 0; i < n; i++) { if (x % a[i] != 0) flag = 0; } if (flag) { for (i = 2; i <= sqrt(x); i++) { if (x % i == 0) { if (x == i * i) ans++; else ans += 2; } } } if (flag && ans == n) cout << x << endl; else cout << -1 << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_BLACKBOX_V
`define SKY130_FD_SC_LP__O21BA_BLACKBOX_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21ba (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 21:00:31
// Design Name:
// Module Name: D_ff_with_ce_and_synch_reset_behavior_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module D_ff_with_ce_and_synch_reset_behavior_tb(
);
reg D, Clk, reset, ce;
wire Q;
D_ff_with_ce_and_synch_reset_behavior DUT (.D(D), .Clk(Clk), .reset(reset), .ce(ce), .Q(Q));
initial begin
#300 $finish;
end
initial begin
D = 0; Clk = 0; reset = 0; ce = 0;
#10 Clk = 1;
#10 Clk = 0; D = 1;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; ce = 1;
#10 Clk = 1;
#10 Clk = 0; ce = 0;
#10 Clk = 1;
#10 Clk = 0; D = 0;
#10 Clk = 1;
#10 Clk = 0; reset = 1;
#10 Clk = 1;
#10 Clk = 0; reset = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; ce = 1;
#10 Clk = 1;
#10 Clk = 0; ce = 0;
#10 Clk = 1;
#10 Clk = 0; D = 1;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; ce = 1;
#10 Clk = 1;
#10 Clk = 0; ce = 0;
#10 Clk = 1;
#10 Clk = 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int arr[10005]; bool readl[10005]; int read_pages(int ini) { int curr = ini; readl[ini] = 1; while (curr != arr[curr]) { curr = arr[curr]; readl[curr] = true; } return curr; } int main() { int n; cin >> n; for (int i = 1; i <= n; i++) { cin >> arr[i]; } int days = 0; for (int i = 1; i <= n; i++) { int curr = read_pages(i); for (int j = i; j <= curr; j++) { if (!readl[j]) { curr = max(read_pages(j), curr); } } i = curr; days++; } cout << days; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFXBP_TB_V
`define SKY130_FD_SC_HD__DFXBP_TB_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dfxbp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__dfxbp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFXBP_TB_V
|
#include <bits/stdc++.h> using namespace std; template <class T> inline T bigmod(T p, T e, T M) { if (e == 0) return 1; if (e % 2 == 0) { long long t = bigmod(p, e / 2, M); return (T)((t * t) % M); } return (T)(((long long)bigmod(p, e - 1, M) * (long long)(p)) % M); } template <class T> inline T gcd(T a, T b) { if (b == 0) return a; return gcd(b, a % b); } template <class T> inline T modinverse(T a, T M) { return bigmod(a, M - 2, M); } long long seg[4000001], ar[1000001], val[1000001]; void insert(int idx, int s, int e, int p, int v) { if (s == e) { seg[idx] = v; return; } int mid = (s + e) / 2; if (p <= mid) insert(idx * 2 + 1, s, mid, p, v); else insert(idx * 2 + 2, mid + 1, e, p, v); seg[idx] = seg[idx * 2 + 1] + seg[idx * 2 + 2]; } long long query(int idx, int s, int e, int p) { if (seg[idx] < p) return -1; if (s == e) return s; int mid = (s + e) / 2; if (p <= seg[idx * 2 + 1]) return query(idx * 2 + 1, s, mid, p); else return query(idx * 2 + 2, mid + 1, e, p - seg[idx * 2 + 1]); } int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long a, b, c, d, e, f, g, h = 1, x, y, z; cin >> a >> b; for (int i = (0); i < (b); ++i) cin >> ar[i]; c = 0; for (int i = (0); i < (a); ++i) { cin >> d; if (d == -1) { for (int j = (0); j < (b); ++j) { e = query(0, 1, 1000000, ar[j] - j); if (e == -1) break; insert(0, 1, 1000000, e, 0); } } else { c++; val[c] = d; insert(0, 1, 1000000, c, 1); } } if (seg[0] == 0) cout << Poor stack! << endl; else { for (int i = (1); i < (seg[0] + 1); ++i) { e = query(0, 1, 1000000, i); cout << val[e]; } } } |
#include <bits/stdc++.h> using namespace std; int main() { string a, b, c; bool yes = true; int length, i; cin >> a >> b; length = a.length(); for (i = 0; i < length; i++) { if (a[i] < b[i]) { yes = false; break; } } if (yes == false) { cout << -1 << endl; } else { cout << b << endl; } return 0; } |
//-------------------------------------------------------------------
//-- mpres_tb.v
//-- Banco de pruebas para los prescalers multiples
//-------------------------------------------------------------------
//-- BQ August 2015. Written by Juan Gonzalez (Obijuan)
//-------------------------------------------------------------------
//-- No se comprueba el correcto funcionamiento por software. Se
//-- colocan los elementos necesarios para comprobarlo visualmente
//-------------------------------------------------------------------
module mpres_tb();
//-- Numero de bits de los prescalers
parameter N0 = 1;
parameter N1 = 1;
parameter N2 = 2;
parameter N3 = 3;
parameter N4 = 4;
//-- Registro para generar la señal de reloj
reg clk = 0;
//-- Cables de salida
wire D1, D2, D3, D4;
//-- Instanciar el componente
mpres
//-- Establecer parametros
#(
.N0(N0),
.N1(N1),
.N2(N2),
.N3(N3),
.N4(N4)
)
//-- Conectar los puertos
dut(
.clk_in(clk),
.D1(D1),
.D2(D2),
.D3(D3),
.D4(D4)
);
//-- Generador de reloj. Periodo 2 unidades
always #1 clk = ~clk;
//-- Proceso al inicio
initial begin
//-- Fichero donde almacenar los resultados
$dumpfile("mpres_tb.vcd");
$dumpvars(0, mpres_tb);
# 99 $display("FIN de la simulacion");
# 100 $finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool isPrime(int N) { for (int i = 2; i * i <= N; ++i) { if (N % i == 0) return false; } return true; } bool sortinrev(const pair<int, int> &a, const pair<int, int> &b) { return (a.first > b.first); } int gcd(int a, int b) { if (b == 0) return a; return gcd(b, a % b); } bool comp(const pair<int, int> &a, const pair<int, int> &b) { if (a.first == b.first) return a.second < b.second; else return a.first > b.first; } int main() { int n; cin >> n; int flag = 0; char a[5][5]; int max = 11; int digit[11] = {0}; for (int i = 0; i < 4; i++) { for (int j = 0; j < 4; j++) { cin >> a[i][j]; if (a[i][j] != . ) { digit[a[i][j] - 48]++; } } } for (int i = 0; i < 10; i++) { if (digit[i] > 2 * n) { cout << NO ; flag = 1; break; } } if (flag == 0) { cout << YES ; } return 0; } |
#include <bits/stdc++.h> using namespace std; auto start = std::chrono::system_clock::now(); inline void skj() { std::chrono::time_point<std::chrono::system_clock> end; end = std::chrono::system_clock::now(); std::chrono::duration<double> elapsed_seconds = end - start; std::time_t end_time = std::chrono::system_clock::to_time_t(end); cerr << Time taken << elapsed_seconds.count() * 1000 << n ; } mt19937 rng(chrono::steady_clock::now().time_since_epoch().count()); struct custom_hash { static uint64_t splitmix64(uint64_t x) { x += 0x9e3779b97f4a7c15; x = (x ^ (x >> 30)) * 0xbf58476d1ce4e5b9; x = (x ^ (x >> 27)) * 0x94d049bb133111eb; return x ^ (x >> 31); } size_t operator()(uint64_t x) const { static const uint64_t FIXED_RANDOM = chrono::steady_clock::now().time_since_epoch().count(); return splitmix64(x + FIXED_RANDOM); } }; inline long long binexp(long long a, long long b, long long m) { if (a == 0) { return 0; } long long res = 1; a %= m; while (b) { if (b & 1) res = (res * 1ll * a) % m; a = (a * 1ll * a) % m; b >>= 1; } return res; } inline long long binmul(long long a, long long b, long long m) { a %= m; long long res = 0; while (b) { if (b & 1) { res = (res + a) % m; } a = (a + a) % m; b >>= 1; } return res; } const long long N = 3e5 + 5; long long seg[4 * N], lazy[4 * N]; void updateRange(long long node, long long start, long long end, long long l, long long r, long long val) { if (lazy[node] != 0) { seg[node] += lazy[node]; if (start != end) { lazy[node * 2] += lazy[node]; lazy[node * 2 + 1] += lazy[node]; } lazy[node] = 0; } if (start > end or start > r or end < l) return; if (start >= l and end <= r) { seg[node] += val; if (start != end) { lazy[node * 2] += val; lazy[node * 2 + 1] += val; } return; } long long mid = (start + end) / 2; updateRange(node * 2, start, mid, l, r, val); updateRange(node * 2 + 1, mid + 1, end, l, r, val); seg[node] = min(seg[node * 2], seg[node * 2 + 1]); } long long queryRange(long long node, long long start, long long end, long long l, long long r) { if (start > end or start > r or end < l) return 0; if (lazy[node] != 0) { seg[node] += lazy[node]; if (start != end) { lazy[node * 2] += lazy[node]; lazy[node * 2 + 1] += lazy[node]; } lazy[node] = 0; } if (start >= l and end <= r) return seg[node]; long long mid = (start + end) / 2; long long p1 = queryRange(node * 2, start, mid, l, r); long long p2 = queryRange(node * 2 + 1, mid + 1, end, l, r); return min(p1, p2); } inline void solve_me_senpai() { long long n, m; cin >> n >> m; long long a = 5, b = 4; string as = 5 , bs = 5 ; while (a <= n or b <= n) { a += 5, b += 4; as.push_back( 5 ); bs.push_back( 4 ); } reverse(as.begin(), as.end()); reverse(bs.begin(), bs.end()); cout << as << << bs << n ; } int32_t main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long t = 1; long long a = 1; while (t--) { solve_me_senpai(); a++; } return 0; } |
#include <bits/stdc++.h> using namespace std; long long mod = 1000000007; long long max(long long a, long long b) { return a > b ? a : b; } bool r(long long p1, long long p2) { return (p2 < p1); } long long min(long long a, long long b) { return a < b ? a : b; } long long gcd(long long a, long long b) { if (a == 0) return b; return gcd(b % a, a); } const int N = 9; long long power(long long a, long long b) { long long ans = 1; while (b > 0) { if (b & 1) { ans = (ans * a); } a = (a * a); b >>= 1; } return ans; } void solve() { int n; cin >> n; int a[n], b[n], c[n]; for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; for (int i = 0; i < n; i++) cin >> c[i]; int p[n]; p[0] = a[0]; for (int i = 1; i < n; i++) { p[i] = a[i]; if (p[i] == p[i - 1]) p[i] = b[i]; } if (p[n - 1] == p[0]) p[n - 1] = c[n - 1]; if (p[n - 1] == p[n - 2]) p[n - 1] = b[n - 1]; for (int i = 0; i < n; i++) cout << p[i] << ; cout << n ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long t; cin >> t; while (t--) { solve(); } return 0; } |
module tb;
import "DPI-C" context task c_main();
export "DPI-C" task read;
`include "parameter.v"
// System Signals
reg ACLK;
reg ARESETN;
// Slave Interface Write Address Ports
reg [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_AWID;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR;
reg [8-1 : 0] S_AXI_AWLEN;
reg [3-1 : 0] S_AXI_AWSIZE;
reg [2-1 : 0] S_AXI_AWBURST;
// input S_AXI_AWLOCK [2-1 : 0];
reg [1 : 0] S_AXI_AWLOCK;
reg [4-1 : 0] S_AXI_AWCACHE;
reg [3-1 : 0] S_AXI_AWPROT;
reg [4-1 : 0] S_AXI_AWQOS;
reg [C_S_AXI_AWUSER_WIDTH-1 :0] S_AXI_AWUSER;
reg S_AXI_AWVALID;
wire S_AXI_AWREADY;
// Slave Interface Write Data Ports
reg [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA;
reg [C_S_AXI_DATA_WIDTH/8-1 : 0]S_AXI_WSTRB;
reg S_AXI_WLAST;
reg [C_S_AXI_WUSER_WIDTH-1 : 0] S_AXI_WUSER;
reg S_AXI_WVALID;
wire S_AXI_WREADY;
// Slave Interface Write Response Ports
wire [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_BID;
wire [2-1 : 0] S_AXI_BRESP;
wire [C_S_AXI_BUSER_WIDTH-1 : 0] S_AXI_BUSER;
wire S_AXI_BVALID;
reg S_AXI_BREADY;
// Slave Interface Read Address Ports
reg [C_S_AXI_ID_WIDTH-1 : 0] S_AXI_ARID;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR;
reg [8-1 : 0] S_AXI_ARLEN;
reg [3-1 : 0] S_AXI_ARSIZE;
reg [2-1 : 0] S_AXI_ARBURST;
reg [2-1 : 0] S_AXI_ARLOCK;
reg [4-1 : 0] S_AXI_ARCACHE;
reg [3-1 : 0] S_AXI_ARPROT;
reg [4-1 : 0] S_AXI_ARQOS;
reg [C_S_AXI_ARUSER_WIDTH-1 : 0]S_AXI_ARUSER;
reg S_AXI_ARVALID;
wire S_AXI_ARREADY;
// Slave Interface Read Data Ports
wire [C_S_AXI_ID_WIDTH-1: 0] S_AXI_RID;
wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA;
wire [2-1 : 0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_S_AXI_RUSER_WIDTH-1 : 0] S_AXI_RUSER;
wire S_AXI_RVALID;
reg S_AXI_RREADY;
axi_slave_bfm U1 (
.ACLK(ACLK),
.ARESETN(ARESETN),
.S_AXI_AWID(S_AXI_AWID),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWLEN(S_AXI_AWLEN),
.S_AXI_AWSIZE(S_AXI_AWSIZE),
.S_AXI_AWBURST(S_AXI_AWBURST),
.S_AXI_AWLOCK(S_AXI_AWLOCK),
.S_AXI_AWCACHE(S_AXI_AWCACHE),
.S_AXI_AWPROT(S_AXI_AWPROT),
.S_AXI_AWQOS(S_AXI_AWQOS),
.S_AXI_AWUSER(S_AXI_AWUSER),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WLAST(S_AXI_WLAST),
.S_AXI_WUSER(S_AXI_WUSER),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BID(S_AXI_BID),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BUSER(S_AXI_BUSER),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_ARID(S_AXI_ARID),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARSIZE(S_AXI_ARSIZE),
.S_AXI_ARBURST(S_AXI_ARBURST),
.S_AXI_ARLOCK(S_AXI_ARLOCK),
.S_AXI_ARCACHE(S_AXI_ARCACHE),
.S_AXI_ARPROT(S_AXI_ARPROT),
.S_AXI_ARQOS(S_AXI_ARQOS),
.S_AXI_ARUSER(S_AXI_ARUSER),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RID(S_AXI_RID),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RUSER(S_AXI_RUSER),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY)
);
`include "init.v"
task read(
input int t_s_axi_arid,
input int t_s_axi_araddr,
input int t_s_axi_arlen,
input int t_s_axi_arsize,
input int t_s_axi_arburst,
input int t_s_axi_arlock,
input int t_s_axi_arcache,
input int t_s_axi_arprot,
input int t_s_axi_arqos,
input int t_s_axi_aruser,
input int t_s_axi_arvalid);
begin
S_AXI_ARID = t_s_axi_arid;
S_AXI_ARADDR = t_s_axi_araddr;
S_AXI_ARLEN = t_s_axi_arlen;
S_AXI_ARSIZE = t_s_axi_arsize;
S_AXI_ARBURST = t_s_axi_arburst;
S_AXI_ARLOCK = t_s_axi_arlock;
S_AXI_ARCACHE = t_s_axi_arcache;
S_AXI_ARPROT = t_s_axi_arprot;
S_AXI_ARQOS = t_s_axi_arqos;
S_AXI_ARUSER = t_s_axi_aruser;
S_AXI_ARVALID = t_s_axi_arvalid;
S_AXI_RREADY = 0;
while(S_AXI_ARREADY === 1'b1) begin
@(posedge ACLK);
end
@ (posedge ACLK);
S_AXI_RREADY = 1;
S_AXI_ARID = 0;
S_AXI_ARADDR = 0;
S_AXI_ARLEN = 0;
S_AXI_ARSIZE = 0;
S_AXI_ARBURST = 0;
S_AXI_ARLOCK = 0;
S_AXI_ARCACHE = 0;
S_AXI_ARPROT = 0;
S_AXI_ARQOS = 0;
S_AXI_ARUSER = 0;
S_AXI_ARVALID = 0;
while(S_AXI_RLAST !== 1'b1) begin
@ (posedge ACLK);
end
@ (posedge ACLK);
end
endtask
`include "init.v"
initial begin
ACLK = 0;
forever begin
#1 ACLK = ~ACLK;
end
end
initial begin
@(posedge ACLK);
#10;
ARESETN = 0;
@(posedge ACLK);
ARESETN = 1;
repeat(10) @(posedge ACLK);
c_main;
$finish;
end
endmodule
// vim: set ts=4 autoindent shiftwidth=4 expandtab number:
|
/*
* HIFIFO: Harmon Instruments PCI Express to FIFO
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*/
`timescale 1ns/1ps
module hififo_tpc_fifo
(
input clock,
input reset,
output [31:0] status,
output interrupt,
// writes and read completions
input [63:0] rx_data,
input rx_data_valid,
// to PCI TX
output reg wr_valid = 0,
input wr_ready,
output [63:0] wr_data,
output [63:0] wr_addr,
output reg wr_last,
// FIFO
input fifo_clock,
input fifo_write,
input [63:0] fifo_data,
output fifo_ready
);
reg [4:0] state = 0;
wire o_almost_empty;
wire request_valid;
wire fifo_read = (wr_ready && wr_valid)
|| ((state != 0) && (state < 30));
always @ (posedge clock)
begin
if(reset)
wr_valid <= 1'b0;
else
wr_valid <= ((state == 0) || (state > 29))
&& request_valid && ~o_almost_empty;
wr_last <= state == 29;
if(reset)
state <= 1'b0;
else if(state == 0)
state <= wr_ready ? 5'd15 : 5'd0;
else
state <= state + 1'b1;
end
fwft_fifo #(.NBITS(64)) data_fifo
(
.reset(reset),
.i_clock(fifo_clock),
.i_data(fifo_data),
.i_valid(fifo_write),
.i_ready(fifo_ready),
.o_clock(clock),
.o_read(fifo_read),
.o_data(wr_data),
.o_valid(),
.o_almost_empty(o_almost_empty)
);
hififo_fetch_descriptor #(.BS(3)) fetch_descriptor
(
.clock(clock),
.reset(reset),
.request_addr(wr_addr),
.request_valid(request_valid),
.request_ack(fifo_read),
.wvalid(rx_data_valid),
.wdata(rx_data),
.status(status),
.interrupt(interrupt)
);
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
// Design of the pipe
module pipeline_buffer (in,out,clock,reset);
// Output signal for the design module
output out; // Output data signal
// Input signals for the design module
input in; // Input data signal
input clock; // Input clock signal
input reset; // Input reset signal
// Declare "reg" signals... that will be assigned values
reg out;
reg o1; // Output of flip-flop #1
reg o2; // Output of flip-flop #2
reg o3; // Output of flip-flop #3
reg o4; // Output of flip-flop #4
reg o5; // Output of flip-flop #5
reg o6; // Output of flip-flop #6
reg o7; // Output of flip-flop #7
reg o8; // Output of flip-flop #8
reg o9; // Output of flip-flop #9
reg o10; // Output of flip-flop #10
reg o11; // Output of flip-flop #11
reg o12; // Output of flip-flop #12
reg o13; // Output of flip-flop #13
reg o14; // Output of flip-flop #14
reg o15; // Output of flip-flop #15
reg o16; // Output of flip-flop #16
reg o17; // Output of flip-flop #17
reg o18; // Output of flip-flop #18
reg o19; // Output of flip-flop #19
reg o20; // Output of flip-flop #20
reg o21; // Output of flip-flop #21
reg o22; // Output of flip-flop #22
reg o23; // Output of flip-flop #23
reg o24; // Output of flip-flop #24
reg o25; // Output of flip-flop #25
reg o26; // Output of flip-flop #26
reg o27; // Output of flip-flop #27
reg o28; // Output of flip-flop #28
reg o29; // Output of flip-flop #29
reg o30; // Output of flip-flop #30
reg o31; // Output of flip-flop #31
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
// Create the 1st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o1 = 1'd0;
else
o1 = in;
end
// Create the 2nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o2 = 1'd0;
else
o2 = o1;
end
// Create the 3rd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o3 = 1'd0;
else
o3 = o2;
end
// Create the 4th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o4 = 1'd0;
else
o4 = o3;
end
// Create the 5th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o5 = 1'd0;
else
o5 = o4;
end
// Create the 6th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o6 = 1'd0;
else
o6 = o5;
end
// Create the 7th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o7 = 1'd0;
else
o7 = o6;
end
// Create the 8th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o8 = 1'd0;
else
o8 = o7;
end
// Create the 9th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o9 = 1'd0;
else
o9 = o8;
end
// Create the 10th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o10 = 1'd0;
else
o10 = o9;
end
// Create the 11th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o11 = 1'd0;
else
o11 = o10;
end
// Create the 12th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o12 = 1'd0;
else
o12 = o11;
end
// Create the 13th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o13 = 1'd0;
else
o13 = o12;
end
// Create the 14th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o14 = 1'd0;
else
o14 = o13;
end
// Create the 15th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o15 = 1'd0;
else
o15 = o14;
end
// Create the 16th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o16 = 1'd0;
else
o16 = o15;
end
// Create the 17th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o17 = 1'd0;
else
o17 = o16;
end
// Create the 18th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o18 = 1'd0;
else
o18 = o17;
end
// Create the 19th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o19 = 1'd0;
else
o19 = o18;
end
// Create the 20th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o20 = 1'd0;
else
o20 = o19;
end
// Create the 21st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o21 = 1'd0;
else
o21 = o20;
end
// Create the 22nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o22 = 1'd0;
else
o22 = o21;
end
// Create the 23rd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o23 = 1'd0;
else
o23 = o22;
end
// Create the 24th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o24 = 1'd0;
else
o24 = o23;
end
// Create the 25th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o25 = 1'd0;
else
o25 = o24;
end
// Create the 26th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o26 = 1'd0;
else
o26 = o25;
end
// Create the 27th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o27 = 1'd0;
else
o27 = o26;
end
// Create the 28th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o28 = 1'd0;
else
o28 = o27;
end
// Create the 29th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o29 = 1'd0;
else
o29 = o28;
end
// Create the 30th flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o30 = 1'd0;
else
o30 = o29;
end
// Create the 31st flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
o31 = 1'd0;
else
o31 = o30;
end
// Create the 32nd flip-flop of the 15 flip-flop pipeline buffer
always @(posedge clock)
begin
if(reset)
out = 1'd0;
else
out = o31;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__NAND2B_FUNCTIONAL_PP_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nand2b (
VPWR,
VGND,
Y ,
A_N ,
B
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A_N ;
input B ;
// Local signals
wire Y not0_out ;
wire or0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out , B );
or or0 (or0_out_Y , not0_out, A_N );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2B_FUNCTIONAL_PP_V |
#include <vector> #include <iostream> #include <algorithm> #include <string> #include <cmath> #include <map> #define ll long long using namespace std; int main() { ll t; cin >> t; while (t--) { ll n, m; cin >> n >> m; string s; vector<ll> a(n, 0); vector<ll> b(n, 0); vector<ll> c(m, 0); vector<ll> result(m, 0); vector<vector<ll>> bucket(n + 1, vector<ll>(0)); for (auto& e : a)cin >> e; for (auto& e : b)cin >> e; for (auto& e : c)cin >> e; for (ll i = 0; i < n; i++) { if (b[i] != a[i]) { bucket[b[i]].push_back(i); } } ll lastC = -1; if (bucket[c[m - 1]].size() > 0) { lastC = bucket[c[m - 1]].back(); bucket[c[m - 1]].pop_back(); } else { for (ll i = 0; i < n; i++) { if (b[i] == c[m - 1]) { lastC = i; break; } } } if (lastC == -1) { cout << NO << endl; } else { result[m - 1] = lastC; for (ll i = 0; i < m - 1; i++) { if (bucket[c[i]].size() == 0) { result[i] = lastC; } else { result[i] = bucket[c[i]].back(); bucket[c[i]].pop_back(); } } auto res = true; for (ll i = 0; i < n + 1; i++) { if (bucket[i].size() > 0) { res = false; } } if (res == false) { cout << NO << endl; } else { cout << YES << endl; for (ll i = 0; i < m; i++) { cout << result[i] + 1; if (i < m - 1) { cout << ; } else { cout << endl; } } } } } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<int> graph[200002]; int visited[200002], sub[200002]; int subsize(int root) { visited[root] = 1; for (int child : graph[root]) { if (!visited[child]) sub[root] += subsize(child); } return sub[root]; } void destroy(int root, int par) { for (int child : graph[root]) { if (child != par && (sub[child] % 2 == 0)) destroy(child, root); } printf( %d n , root); for (int child : graph[root]) { if (child != par && (sub[child] & 1)) destroy(child, root); } } int main() { for (int i = 0; i < 200002; i++) sub[i] = 1; int n, x; scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %d , &x); if (x) { graph[x].push_back(i); graph[i].push_back(x); } } if (n % 2 == 0) printf( NO ); else { subsize(1); printf( YES n ); destroy(1, 0); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__OR3B_FUNCTIONAL_PP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const int Maxn = 500010; const int inf = 2147483647; const double pi = acos(-1.0); int read() { int x = 0, f = 1; char ch = getchar(); while (ch < 0 || ch > 9 ) { if (ch == - ) f = -1; ch = getchar(); } while (ch >= 0 && ch <= 9 ) x = x * 10 + ch - 0 , ch = getchar(); return x * f; } int n, m, k, a[Maxn]; long long ans, rest; bool del[Maxn]; struct Edge { int x, y; } e[Maxn]; int fa[Maxn << 1], dep[Maxn << 1]; int findfa(int x) { return ((fa[x] == x) ? x : findfa(fa[x])); } int top = 0, sta[Maxn << 1], o, fa1[Maxn << 1], dep1[Maxn << 1]; void merge(int x, int y) { int fx = findfa(x), fy = findfa(y); if (dep[fx] < dep[fy]) swap(fx, fy); sta[++top] = fy; fa1[top] = fa[fy], dep1[top] = dep[fx]; fa[fy] = fx; dep[fx] = max(dep[fx], dep[fy] + 1); } void resume() { while (top > o) { int fy = sta[top]; dep[fa[fy]] = dep1[top]; fa[fy] = fa1[top]; --top; } } vector<pair<int, int> > g[Maxn]; int tot = 0; map<int, map<int, int> > mp; int main() { memset(dep, 0, sizeof(dep)); memset(del, false, sizeof(del)); n = read(), m = read(), k = read(); ans = (long long)k * (k - 1ll) / 2ll; rest = k - 1; for (int i = 1; i <= n; i++) a[i] = read(); for (int i = 1; i <= m; i++) e[i].x = read(), e[i].y = read(); for (int i = 1; i <= n * 2; i++) fa[i] = i; for (int i = 1; i <= m; i++) if (!del[a[e[i].x]] && a[e[i].x] == a[e[i].y]) { int fx = findfa(e[i].x), fy = findfa(e[i].y); if (fx == fy) del[a[e[i].x]] = true, ans -= rest, rest--; else merge(e[i].x, e[i].y + n), merge(e[i].y, e[i].x + n); } o = top; for (int i = 1; i <= m; i++) if (a[e[i].x] != a[e[i].y] && !del[a[e[i].x]] && !del[a[e[i].y]]) { int cx = a[e[i].x], cy = a[e[i].y]; if (cx > cy) swap(cx, cy); if (!mp[cx][cy]) mp[cx][cy] = ++tot; g[mp[cx][cy]].push_back(make_pair(e[i].x, e[i].y)); } for (int i = 1; i <= tot; i++) { for (int j = 0; j < g[i].size(); j++) { int x = g[i][j].first, y = g[i][j].second; int fx = findfa(x), fy = findfa(y); if (fx == fy) { ans--; break; } merge(x, y + n); merge(y, x + n); } resume(); } printf( %lld , ans); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, ans, final = 0, play = 0, study = 0, big, small, i, j; cin >> n >> m; int a[n + 1]; for (i = 1; i <= n; i++) { cin >> a[i]; if (a[i] == 1) { study++; } else { play++; } } for (i = 1; i <= m; i++) { j = i; big = study; small = play; while (j <= n) { if (a[j] == 1) { big--; } else { small--; } j += m; } ans = abs(big - small); if (ans > final) { final = ans; } } cout << final; } |
#include <bits/stdc++.h> using namespace std; int main() { char s[3]; cin >> s; int a; char b; b = s[0]; a = s[1]; if ((b == a || b == h ) && (a == 1 || a == 8 )) cout << 3; else if ((b == a || b == h ) && (a > 1 && a < 8 )) cout << 5; else if ((a == 1 || a == 8 ) || (a > a && a < h )) cout << 5; else cout << 8; return 0; } |
/* wb_cdc. Part of wb_intercon
*
* ISC License
*
* Copyright (C) 2016 Olof Kindgren <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*Wishbone Clock-domain crossing core.
TODO:
- Bursts
- Pipelining
*/
module wb_cdc
#(parameter AW = 32)
(input wbm_clk,
input wbm_rst,
input [AW-1:0] wbm_adr_i,
input [31:0] wbm_dat_i,
input [3:0] wbm_sel_i,
input wbm_we_i,
input wbm_cyc_i,
input wbm_stb_i,
output [31:0] wbm_dat_o,
output wbm_ack_o,
input wbs_clk,
input wbs_rst,
output [AW-1:0] wbs_adr_o,
output [31:0] wbs_dat_o,
output [3:0] wbs_sel_o,
output wbs_we_o,
output wbs_cyc_o,
output wbs_stb_o,
input [31:0] wbs_dat_i,
input wbs_ack_i);
wire wbm_m2s_en;
reg wbm_busy = 1'b0;
wire wbm_cs;
wire wbm_done;
wire wbs_m2s_en;
reg wbs_cs = 1'b0;
cc561
#(.DW (AW+32+4+1))
cdc_m2s
(.aclk (wbm_clk),
.arst (wbm_rst),
.adata ({wbm_adr_i, wbm_dat_i, wbm_sel_i, wbm_we_i}),
.aen (wbm_m2s_en),
.bclk (wbs_clk),
.bdata ({wbs_adr_o, wbs_dat_o, wbs_sel_o, wbs_we_o}),
.ben (wbs_m2s_en));
assign wbm_cs = wbm_cyc_i & wbm_stb_i;
assign wbm_m2s_en = wbm_cs & ~wbm_busy;
always @(posedge wbm_clk) begin
if (wbm_ack_o | wbm_rst)
wbm_busy <= 1'b0;
else if (wbm_cs)
wbm_busy <= 1'b1;
end
always @(posedge wbs_clk) begin
if (wbs_ack_i)
wbs_cs <= 1'b0;
else if (wbs_m2s_en)
wbs_cs <= 1'b1;
end
assign wbs_cyc_o = wbs_m2s_en | wbs_cs;
assign wbs_stb_o = wbs_m2s_en | wbs_cs;
cc561
#(.DW (32))
cdc_s2m
(.aclk (wbs_clk),
.arst (wbs_rst),
.adata (wbs_dat_i),
.aen (wbs_ack_i),
.bclk (wbm_clk),
.bdata (wbm_dat_o),
.ben (wbm_ack_o));
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, k, m = 1e9 + 7; cin >> n >> k; int a[100005]; a[0] = 1; for (int i = 1; i < 100005; ++i) { if (i >= k) { a[i] = (a[i - k] + a[i - 1]) % m; } else { a[i] = a[i - 1]; } } for (int i = 1; i < 100005; ++i) { a[i] = (a[i] + a[i - 1]) % m; } while (n--) { int x, y; scanf( %d %d , &x, &y); printf( %d n , (a[y] - a[x - 1] + m) % m); } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311A_PP_SYMBOL_V
`define SKY130_FD_SC_LP__O311A_PP_SYMBOL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o311a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311A_PP_SYMBOL_V
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/sprdma.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Sprite DMA control block.
***************************************************************************************************/
module sprdma
(
input wire clk_in, // 100MHz system clock signal
input wire rst_in, // reset signal
input wire [15:0] cpumc_a_in, // cpu address bus in (to snoop cpu writes of 0x4014)
input wire [ 7:0] cpumc_din_in, // cpumc din bus in (to snoop cpu writes of 0x4014)
input wire [ 7:0] cpumc_dout_in, // cpumc dout bus in (to receive sprdma read data)
input wire cpu_r_nw_in, // cpu write enable (to snoop cpu writes of 0x4014)
output wire active_out, // high when sprdma is active (de-assert cpu ready signal)
output reg [15:0] cpumc_a_out, // cpu address bus out (for dma cpu mem reads/writes)
output reg [ 7:0] cpumc_d_out, // cpu data bus out (for dma mem writes)
output reg cpumc_r_nw_out // cpu r_nw signal out (for dma mem writes)
);
// Symbolic state representations.
localparam [1:0] S_READY = 2'h0,
S_ACTIVE = 2'h1,
S_COOLDOWN = 2'h2;
reg [ 1:0] q_state, d_state; // current fsm state
reg [15:0] q_addr, d_addr; // current cpu address to be copied to sprite ram
reg [ 1:0] q_cnt, d_cnt; // counter to manage stages of dma copies
reg [ 7:0] q_data, d_data; // latch for data read from cpu mem
// Update FF state.
always @(posedge clk_in)
begin
if (rst_in)
begin
q_state <= S_READY;
q_addr <= 16'h0000;
q_cnt <= 2'h0;
q_data <= 8'h00;
end
else
begin
q_state <= d_state;
q_addr <= d_addr;
q_cnt <= d_cnt;
q_data <= d_data;
end
end
always @*
begin
// Default regs to current state.
d_state = q_state;
d_addr = q_addr;
d_cnt = q_cnt;
d_data = q_data;
// Default to no memory action.
cpumc_a_out = 16'h00;
cpumc_d_out = 8'h00;
cpumc_r_nw_out = 1'b1;
if (q_state == S_READY)
begin
// Detect write to 0x4014 to begin DMA.
if ((cpumc_a_in == 16'h4014) && !cpu_r_nw_in)
begin
d_state = S_ACTIVE;
d_addr = { cpumc_din_in, 8'h00 };
end
end
else if (q_state == S_ACTIVE)
begin
case (q_cnt)
2'h0:
begin
cpumc_a_out = q_addr;
d_cnt = 2'h1;
end
2'h1:
begin
cpumc_a_out = q_addr;
d_data = cpumc_dout_in;
d_cnt = 2'h2;
end
2'h2:
begin
cpumc_a_out = 16'h2004;
cpumc_d_out = q_data;
cpumc_r_nw_out = 1'b0;
d_cnt = 2'h0;
if (q_addr[7:0] == 8'hff)
d_state = S_COOLDOWN;
else
d_addr = q_addr + 16'h0001;
end
endcase
end
else if (q_state == S_COOLDOWN)
begin
if (cpu_r_nw_in)
d_state = S_READY;
end
end
assign active_out = (q_state == S_ACTIVE);
endmodule
|
//========================================================================================
//============================= SCRAMLBER =============================
//========================================================================================
module scrambler #
(
parameter TX_DATA_WIDTH = 64
)
(
input [0:(TX_DATA_WIDTH-1)] data_in,
output [(TX_DATA_WIDTH+1):0] data_out,
input enable,
input [1:0] sync_info,
input clk,
input rst
);
integer i;
reg [((TX_DATA_WIDTH*2)-7):0] poly;
reg [((TX_DATA_WIDTH*2)-7):0] scrambler;
reg [0:(TX_DATA_WIDTH-1)] tempData = {TX_DATA_WIDTH{1'b0}};
reg xorBit;
always @(scrambler,data_in)
begin
poly = scrambler;
for (i=0;i<=(TX_DATA_WIDTH-1);i=i+1)
begin
xorBit = data_in[i] ^ poly[38] ^ poly[57];
poly = {poly[((TX_DATA_WIDTH*2)-8):0],xorBit};
tempData[i] = xorBit;
end
end
always @(posedge clk)
begin
if (rst) begin
//scrambler <= 122'h155_5555_5555_5555_5555_5555_5555_5555;
scrambler <= 122'hFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF_FFFF;
end
else if (enable) begin
scrambler <= poly;
end
end
assign data_out = {sync_info, tempData};
endmodule
|
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