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#include <bits/stdc++.h> using namespace std; struct state { int i, j, dp, cp; }; int di[] = {0, 1, 0, -1}; int dj[] = {1, 0, -1, 0}; state n[50][50][4][2]; state current; char b[50][51]; int r, c; int moves; void read() { cin >> r >> moves; for (int i = 0; i < r; i++) { cin >> b[i]; } c = strlen(b[0]); } void write() { cout << b[current.i][current.j] << n ; } inline bool valid(int i, int j) { return i > -1 && i < r && j > -1 && j < c && b[i][j] != 0 ; } void preprocess(int i, int j, int dp, int cp) { int ni = i, nj = j; while (valid(ni, nj) && b[ni][nj] == b[i][j]) { ni += di[dp]; nj += dj[dp]; } ni -= di[dp]; nj -= dj[dp]; int p = (dp + (cp ? +1 : -1) + 4) % 4; while (valid(ni, nj) && b[ni][nj] == b[i][j]) { ni += di[p]; nj += dj[p]; } ni -= di[p]; nj -= dj[p]; ni += di[dp]; nj += dj[dp]; if (valid(ni, nj)) { n[i][j][dp][cp].i = ni; n[i][j][dp][cp].j = nj; n[i][j][dp][cp].dp = dp; n[i][j][dp][cp].cp = cp; } else { n[i][j][dp][cp].i = i; n[i][j][dp][cp].j = j; n[i][j][dp][cp].dp = !cp ? dp : (dp + 1) % 4; n[i][j][dp][cp].cp = !cp; } } void preprocess() { for (int i = 0; i < r; i++) { for (int j = 0; j < c; j++) { for (int dp = 0; dp < 4; dp++) { for (int cp = 0; cp < 2; cp++) { preprocess(i, j, dp, cp); } } } } } void move() { for (int i = 0; i < moves; i++) { current = n[current.i][current.j][current.dp][current.cp]; } } int main() { current.i = current.j = current.dp = current.cp = 0; read(); preprocess(); move(); write(); return 0; } |
module lc3_pipeline_cpu(
input clk,
input reset,
input INT,
output [15:0] pc,
output [15:0] PSR,
output EXC,
output [5:0] state,
output [5:0] stall,
output [15:0] memA,
inout [15:0] memD,
output rc,
output wc,
output [5:0] state_next,
output [15:0] aluout,
output [19:0] dr2,
output [19:0] dr3,
output [19:0] dr4,
output [19:0] dr5
);
wire [15:0] memdata;
assign memdata=memD;
wire [15:0] ExtINTvec;
wire [15:0] IntINTvec;
assign ExtINTvec=16'h0040;
wire [2:0] memapply;
wire memtype;
wire [2:0] memload;
wire [15:0] memaddrin0;
wire [15:0] memaddrin1;
wire [15:0] memaddrin2;
wire mem_rw;
wire [15:0] memdatain;
assign rc=~mem_rw;
assign wc=mem_rw;
wire [3:2] setCC;
wire NeedCC;
wire [2:0] CCin;
wire [2:0] CCinM;
wire [1:0] Errtype;
wire [4:3] inst_ld;
wire [19:0] sr1;
wire [19:0] sr2;
// wire [19:0] dr2;
// wire [19:0] dr3;
// wire [19:0] dr4;
// wire [19:0] dr5;
wire Forcast_fail;
wire [15:0] Checked_pc;
wire [1:0] ld_pc;
wire [19:0] fsm_regctl;
wire [15:0] SP;
lc3_pipeline_fsm fsm0(
.clk (clk),
.reset (reset),
.INT (INT),
.ExtINTvec (ExtINTvec),
.IntINTvec (IntINTvec),
.stall (stall),
.state (state),
.state_next (state_next),
.pc (pc),
.memapply (memapply),
.memtype (memtype),
.memload (memload),
.memaddrin0 (memaddrin0),
.memaddrin1 (memaddrin1),
.memaddrin2 (memaddrin2),
.memaddrout (memA),
.mem_rw (mem_rw),
.memdatain (memdatain),
.memdataout (memD),
.PSR (PSR),
.SP (SP),
.setCC (setCC),
.NeedCC (NeedCC),
.CCin (CCin),
.CCinM (CCinM),
.Errtype (Errtype),
.inst_ld (inst_ld),
.aluout (aluout),
.sr1 (sr1),
.sr2 (sr2),
.dr2 (dr2),
.dr3 (dr3),
.dr4 (dr4),
.Forcast_fail (Forcast_fail),
.Checked_pc (Checked_pc),
.ld_pc (ld_pc),
.fsm_regctl (fsm_regctl)
);
wire [15:0] forcast_pc0;
wire [15:0] npc0;
wire [15:0] inst;
lc3_pipeline_stage0 stage0(
.reset (reset),
.clk (clk),
.stall (stall[0]),
.state (state),
.memdata (memdata),
.memload (memload[0]),
.memapply (memapply[0]),
.ld_pc (ld_pc),
.alu_out (aluout),
.forcast_pc (forcast_pc0),
.pc (memaddrin0),
.npc (npc0),
.inst (inst)
);
wire [15:0] npc1;
wire [19:0] SR11;
wire [19:0] SR21;
wire [19:0] DR1;
wire [1:0] WBtype1;
wire [1:0] ALUopr1;
wire SetCC1;
wire [4:0] BRtype1;
wire [15:0] Forcast_pc1;
wire [2:0] Memtype1;
wire [1:0] Errtype1;
lc3_pipeline_stage1 stage1(
.reset (reset),
.clk (clk),
.stall (stall[1]),
.state (state),
.I_inst (inst),
.I_npc (npc0),
.I_Forcast_pc (forcast_pc0),
.I_WBctl (dr5),
.fsm_regctl (fsm_regctl),
.O_npc (npc1),
.O_SR1 (SR11),
.O_SR2 (SR21),
.O_DR (DR1),
.O_WBtype (WBtype1),
.O_ALUopr (ALUopr1),
.O_SetCC (SetCC1),
.O_BRtype (BRtype1),
.O_Forcast_pc (Forcast_pc1),
.O_Memtype (Memtype1),
.O_Errtype (Errtype1),
.SP (SP)
);
wire [1:0] WBtype2;
wire [2:0] Memtype2;
lc3_pipeline_stage2 stage2(
.reset (reset),
.clk (clk),
.stall (stall[2]),
.state (state),
.I_npc (npc1),
.I_SR1 (SR11),
.I_SR2 (SR21),
.I_DR (DR1),
.I_WBtype (WBtype1),
.I_ALUopr (ALUopr1),
.I_SetCC (SetCC1),
.I_BRtype (BRtype1),
.I_Forcast_pc (Forcast_pc1),
.I_Memtype (Memtype1),
.I_Errtype (Errtype1),
.O_DR (dr2),
.O_WBtype (WBtype2),
.O_Memtype (Memtype2),
.O_aluout (aluout),
.PSR (PSR),
.SetCC (setCC[2]),
.NeedCC (NeedCC),
.CC (CCin),
.Errtype (Errtype),
.Checked_pc (Checked_pc),
.Forcast_fail (Forcast_fail),
.IntINTvec (IntINTvec),
.sr1 (sr1),
.sr2 (sr2),
.dr3 (dr3),
.dr4 (dr4),
.dr5 (dr5)
);
wire [1:0] WBtype3;
wire [2:0] Memtype3;
wire [15:0] Res3;
lc3_pipeline_stage3 stage3(
.reset (reset),
.clk (clk),
.stall (stall[3]),
.state (state),
.I_DR (dr2),
.I_WBtype (WBtype2),
.I_Memtype (Memtype2),
.I_aluout (aluout),
.I_setCC (setCC[2]),
.O_DR (dr3),
.O_WBtype (WBtype3),
.O_Memtype (Memtype3),
.O_Res (Res3),
.memdata (memdata),
.memaddr (memaddrin1),
.memapply (memapply[1]),
.setCC (setCC[3]),
.inst_ld (inst_ld[3])
);
wire [1:0] WBtype4;
wire [15:0] Res4;
lc3_pipeline_stage4 stage4(
.reset (reset),
.clk (clk),
.stall (stall[4]),
.state (state),
.I_DR (dr3),
.I_WBtype (WBtype3),
.I_Memtype (Memtype3),
.I_Res (Res3),
.O_DR (dr4),
.O_WBtype (WBtype4),
.O_Res (Res4),
.memdata (memdata),
.memaddr (memaddrin2),
.memtype (memtype),
.memdatawr (memdatain),
.memapply (memapply[2]),
.CC (CCinM),
.inst_ld (inst_ld[4])
);
lc3_pipeline_stage5 stage5(
.reset (reset),
.clk (clk),
.stall (stall[5]),
.state (state),
.I_DR (dr4),
.I_WBtype (WBtype4),
.I_Res (Res4),
.O_WBctl (dr5)
);
endmodule |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9 + 7; const int N = 5e3 + 10; vector<double> vd; int flag = 0; vector<int> check(double x, int sz) { vector<int> v; int cur = 0; double tot = x; while (v.size() < sz) { int o = tot / 10; cur += o; v.push_back(cur); tot -= o * 10; if (v.size() == sz) break; tot += x; } if (flag) vd.push_back(tot); return v; } double solve(vector<int>& v1, int o = 0) { double l = 10 + 1e-10; double r = INF; int cnt = 200; while (cnt--) { double mid = (l + r) / 2; auto v2 = check(mid, v1.size()); for (int i = 0; i < v1.size(); i++) { if (v1[i] < v2[i]) { r = mid; break; } if (v1[i] > v2[i]) { l = mid; break; } } if (v1 != v2) continue; if (o == 0) l = mid; else r = mid; } return l; } int main() { int n; cin >> n; vector<int> v(n); for (auto& x : v) cin >> x; double key1 = solve(v, 0); double key2 = solve(v, 1); flag = 1; if (key1 > key2) swap(key1, key2); int ans1 = check(key1, n + 1).back(); int ans2 = check(key2, n + 1).back(); if (abs(vd[0] - 10) <= 1e-8) ans1++; if (ans1 == ans2) puts( unique ), printf( %d n , ans1), exit(0); else puts( not unique ); return 0; } |
#include <bits/stdc++.h> using namespace std; char grid[10][10]; bool colW[10], colB[10]; int main() { int Case = 1; int l, p, q; char dump[2]; while (gets(grid[1])) { for (int i = 2; i <= 8; i++) { gets(grid[i]); } memset(colB, false, sizeof(colB)); memset(colW, false, sizeof(colW)); bool found = false; int white, black; for (int i = 1; i <= 8 && !found; i++) { for (int j = 0; j < 8 && !found; j++) { if (grid[i][j] == W ) { if (!colB[j]) { found = true; white = i - 1; } } else if (grid[i][j] == B ) { colB[j] = true; } } } found = false; for (int i = 8; i >= 1 && !found; i--) { for (int j = 0; j < 8 && !found; j++) { if (grid[i][j] == B ) { if (!colW[j]) { found = true; black = 8 - i; } } else if (grid[i][j] == W ) { colW[j] = true; } } } if (white <= black) puts( A ); else puts( B ); } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:10:34 02/25/2014
// Design Name:
// Module Name: Decode_Int
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ARM_INT(input wire clk,
input wire reset,
input wire INT,
input wire eret,
input wire[31:0] pc_next,
output reg [31:0] pc
);
reg int_act=0,int_req_r=0,int_en=1;
reg [31:0] EPC;
//interrupt Trigger
assign int_clr = reset|int_act; //clear interrupt Request
always @(posedge INT or //interrupt Request
posedge int_clr )begin //clear interrupt Request
if(int_clr==1 )int_req_r<=0; //clear interrupt Request
else int_req_r<=1; //set interrupt Request
end
always @(posedge clk or posedge reset ) begin
if (reset)begin EPC <= 0; //EPC=32'h00000000;
int_act <= 0;
int_en <= 1;
end
else if(int_req_r & int_en)begin //int_req_r: interrupt Request reg
EPC <= pc_next; //interrupt return PC
int_act<=1; //interrupt Service
int_en<=0; //interrupt disable
end
else begin int_act<=0;
if(eret) int_en<=1; //interrupt enable if pc<=EPC;
end
end
//PC Out
always @* begin
if (reset==1)pc <= 32'h00000000;
else if(int_req_r & int_en )
pc <= 32'h00000004; //interrupt Vector
else if(eret)pc <= EPC; //interrupt return
else pc <= pc_next; //next instruction
end
endmodule
|
#include <bits/stdc++.h> using namespace std; ifstream inp( inp.txt ); ofstream out( out.txt ); const int N = 1e5 + 5; const long long B = 73; int builtin_popcount(int &mask) { int kol = 0; for (int bit = 0; bit < 20; bit++) kol += int(bool(mask & (1 << bit))); return kol; } signed main() { ios::sync_with_stdio(0); ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); string a; cin >> a; int up = (1 << 20); vector<int> dp(up, 0); vector<int> masks; for (int i = 0; i < ((int)a.size()); i++) { int mask = 0; for (int j = i; j < min(((int)a.size()), i + 20); j++) { int bit = a[j] - a ; if (mask & (1 << bit)) break; mask |= (1 << bit); masks.push_back(mask); dp[mask] = builtin_popcount(mask); } } for (int mask = 1; mask < up; mask++) for (int bit = 0; bit < 20; bit++) if (mask & (1 << bit)) dp[mask] = max(dp[mask], dp[mask ^ (1 << bit)]); int ans = 0; for (auto &mask : masks) ans = max(ans, builtin_popcount(mask) + dp[mask ^ (up - 1)]); cout << ans; return 0; } |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module init_config_rom (
clka,
addra,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [9 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [31 : 0] douta;
blk_mem_gen_v8_3_4 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(3),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("init_config_rom.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_READ_WIDTH_A(32),
.C_WRITE_DEPTH_A(1024),
.C_READ_DEPTH_A(1024),
.C_ADDRA_WIDTH(10),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(32),
.C_READ_WIDTH_B(32),
.C_WRITE_DEPTH_B(1024),
.C_READ_DEPTH_B(1024),
.C_ADDRB_WIDTH(10),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("0"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.622 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(1'B0),
.addra(addra),
.dina(32'B0),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(10'B0),
.dinb(32'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(32'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVERNOVLP_TB_V
`define SKY130_FD_SC_LP__BUSDRIVERNOVLP_TB_V
/**
* busdrivernovlp: Bus driver, enable gates pulldown only (pmoshvt
* devices).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busdrivernovlp.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 TE_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 TE_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 TE_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 TE_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__busdrivernovlp dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVERNOVLP_TB_V
|
#include <bits/stdc++.h> const long long int mrx = 1e6 + 5, M = 1e9 + 7, dm = 1e3 + 5; const long double pi = 3.1415926535897932384626433832795028841971693993751; long long int mx = -1e18, mn = 1e18; using namespace std; long long int q, n[mrx]; int main() { ios_base::sync_with_stdio(NULL); cin.tie(NULL); cin >> q; for (int i = 0; i < q; i++) { cin >> n[i]; } for (int i = 0; i < q; i++) { if (n[i] == 1 || n[i] == 2 || n[i] == 3 || n[i] == 5 || n[i] == 7 || n[i] == 11) { cout << -1 n ; } else if (n[i] == 6) { cout << 1 n ; } else if (n[i] % 4 == 0) { cout << n[i] / 4 << n ; } else if (n[i] % 2 == 0) { cout << (n[i] - 6) / 4 + 1 << n ; } else if (n[i] % 2 != 0) { if ((n[i] - 9) % 4 == 0) { cout << (n[i] - 9) / 4 + 1 << n ; } else { cout << (n[i] - 15) / 4 + 2 << n ; } } } return 0; } |
#include <bits/stdc++.h> using namespace std; const double PI = 3.14159265389793238462643383279502884197169; const long long MOD = 1e9 + 7; const int MAXN = 1e6 + 5; const int oo = 1e9; int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); int t, p; cin >> t; while (t--) { cin >> p; cout << 2 << << p - 1 << n ; } } |
#include <bits/stdc++.h> using namespace std; const long long maxn = 1e5 + 10; int to[maxn << 1], nex[maxn << 1], head[maxn << 1], e, cnt; int u[maxn << 1], v[maxn << 1]; int dep[maxn << 1], siz[maxn << 1], son[maxn << 1], top[maxn << 1], fa[maxn << 1], id[maxn << 1]; int sum[maxn << 2]; int n; void add(int x, int y) { to[++e] = y; nex[e] = head[x]; head[x] = e; } int ls(int p) { return p << 1; } int rs(int p) { return p << 1 | 1; } void push_up(int p) { sum[p] = sum[ls(p)] + sum[rs(p)]; } int query(int p, int l, int r, int qx, int qy) { if (qx <= l && qy >= r) { return sum[p]; } int res = 0; int mid = (l + r) >> 1; if (qx <= mid) res = res + query(ls(p), l, mid, qx, qy); if (qy > mid) { res = res + query(rs(p), mid + 1, r, qx, qy); } return res; } void update(int p, int l, int r, int pos, int val) { if (l == r) { sum[p] = val; return; } int mid = (l + r) >> 1; if (pos <= mid) { update(ls(p), l, mid, pos, val); } if (pos > mid) update(rs(p), mid + 1, r, pos, val); push_up(p); } int getrange(int x, int y) { int ans = 0; while (top[x] != top[y]) { if (dep[top[x]] < dep[top[y]]) swap(x, y); ans = ans + query(1, 1, n, id[top[x]], id[x]); x = fa[top[x]]; } if (dep[x] > dep[y]) swap(x, y); ans = ans + query(1, 1, n, id[x] + 1, id[y]); return ans; } void dfs1(int x, int f, int deep) { fa[x] = f; siz[x] = 1; dep[x] = deep; int maxson = -1; for (int i = head[x]; i; i = nex[i]) { int y = to[i]; if (y == f) continue; dfs1(y, x, deep + 1); siz[x] += siz[y]; if (maxson < siz[y]) { maxson = siz[y]; son[x] = y; } } } void dfs2(int x, int topf) { id[x] = ++cnt; top[x] = topf; if (!son[x]) return; dfs2(son[x], topf); for (int i = head[x]; i; i = nex[i]) { int y = to[i]; if (y == fa[x] || y == son[x]) continue; dfs2(y, y); } } int lca(int x, int y) { while (top[x] != top[y]) { if (dep[top[x]] < dep[top[y]]) { swap(x, y); } x = fa[top[x]]; } if (dep[x] > dep[y]) swap(x, y); return x; } int main() { memset(sum, 0, sizeof(sum)); scanf( %d , &n); for (int i = 1; i < n; i++) { scanf( %d%d , &u[i], &v[i]); add(u[i], v[i]); add(v[i], u[i]); } dfs1(1, 0, 1); dfs2(1, 0); int m; scanf( %d , &m); while (m--) { int op; scanf( %d , &op); if (op == 1) { int x; scanf( %d , &x); if (dep[u[x]] > dep[v[x]]) update(1, 1, n, id[u[x]], 0); else update(1, 1, n, id[v[x]], 0); } if (op == 2) { int x; scanf( %d , &x); if (dep[u[x]] > dep[v[x]]) { update(1, 1, n, id[u[x]], 1); } else { update(1, 1, n, id[v[x]], 1); } } if (op == 3) { int x, y; scanf( %d%d , &x, &y); if (getrange(x, y)) { printf( -1 n ); } else { printf( %d n , dep[x] + dep[y] - 2 * dep[lca(x, y)]); } } } } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 31 20:17:20 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_auto_us_2/system_auto_us_2_stub.v
// Design : system_auto_us_2
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_11_top,Vivado 2016.4" *)
module system_auto_us_2(s_axi_aclk, s_axi_aresetn, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awregion, s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb,
s_axi_wlast, s_axi_wvalid, s_axi_wready, s_axi_bresp, s_axi_bvalid, s_axi_bready,
m_axi_awaddr, m_axi_awlen, m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache,
m_axi_awprot, m_axi_awregion, m_axi_awqos, m_axi_awvalid, m_axi_awready, m_axi_wdata,
m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_wready, m_axi_bresp, m_axi_bvalid,
m_axi_bready)
/* synthesis syn_black_box black_box_pad_pin="s_axi_aclk,s_axi_aresetn,s_axi_awaddr[31:0],s_axi_awlen[7:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[0:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awregion[3:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready" */;
input s_axi_aclk;
input s_axi_aresetn;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output m_axi_awvalid;
input m_axi_awready;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10, M = 1 << 20 | 10; const int mod = 1e9 + 7; long long n, m, sum; int a[M]; int main() { scanf( %lld%lld , &n, &m); for (int i = 1; i <= n; i++) a[i] = i, sum += i; if (sum > m) return puts( -1 ), 0; for (int i = 1, j = n; i <= j;) { if (sum + j - i <= m) swap(a[i], a[j]), sum += j - i, i++, j--; else j--; } printf( %lld n , sum); for (int i = 1; i <= n; i++) printf( %d , i); puts( ); for (int i = 1; i <= n; i++) printf( %d , a[i]); puts( ); } |
#include <bits/stdc++.h> using namespace std; const int N = 1111111; int a[N]; int n, k; vector<int> prime, p; void Getprime() { for (int i = 2; i <= 1000; i++) { bool bo = 1; for (int j = 2; j * j <= i; j++) { if (i % j == 0) { bo = 0; break; } } if (bo) { prime.push_back(i); } } } int main() { Getprime(); scanf( %d%d , &n, &k); for (int i = 1; i <= n; ++i) { scanf( %d , &a[i]); } int K = k; for (int i = 0; i < prime.size() && prime[i] * prime[i] <= k; ++i) { int t = prime[i]; if (k % t == 0) { int m = 1; while (K % t == 0 && K) { m *= t; K /= t; } p.push_back(m); } } if (K != 1) { p.push_back(K); } for (int i = 0; i < p.size(); ++i) { int pr = p[i]; bool flag = false; for (int j = 1; j <= n; ++j) { if (a[j] % pr == 0) { flag = true; break; } } if (!flag) { puts( No ); return 0; } } puts( Yes ); } |
#include <bits/stdc++.h> using namespace std; int main() { long long int a, b, c, p, k; cin >> a >> b >> c; if (c != 0) { p = b - a; k = p / c; if (p % c == 0) { if (k >= 0) cout << YES << endl; else cout << NO << endl; } else cout << NO << endl; } else if (c == 0) { if (a == b) cout << YES << endl; else cout << NO << endl; } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: ITCR
// Engineer: Yermy Benvaides
//
// Create Date: 20:33:46 02/29/2016
// Design Name:
// Module Name: Traductor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Traductor(in,out,clk,rst);
input wire clk,rst;
input wire [3:0]in;
output reg [10:0]out;
always@(posedge clk, posedge rst)
if (rst)
begin
out <= 11'd0;
end
else
case(in)
4'b0000: out <= 11'd1666;
4'b0001: out <= 11'd999;
4'b0010: out <= 11'd666;
4'b0011: out <= 11'd499;
4'b0100: out <= 11'd399;
4'b0101: out <= 11'd332;
4'b0110: out <= 116'd285;
4'b0111: out <= 11'd249;
4'b1000: out <= 11'd221;
4'b1001: out <= 11'd199;
4'b1010: out <= 11'd181;
4'b1011: out <= 11'd165;
4'b1100: out <= 11'd152;
4'b1101: out <= 11'd141;
4'b1110: out <= 11'd132;
4'b1111: out <= 11'd124;
default out <= 11'd0;
endcase
endmodule
|
#include <bits/stdc++.h> using namespace std; template <class T> bool remin(T &a, const T &b) { if (a > b) { a = b; return true; } return false; } template <class T> bool remax(T &a, const T &b) { if (a < b) { a = b; return true; } return false; } int nxt() { int first; scanf( %d , &first); return first; } long long gcd(long long a, long long b) { a = abs(a); b = abs(b); while (b) { a %= b; swap(a, b); } return a; } struct pt { long double first, second, z; pt() {} pt(long double first, long double second, long double z) : first(first), second(second), z(z) {} inline pt operator-(const pt &r) const { return pt(first - r.first, second - r.second, z - r.z); } inline pt operator+(const pt &r) const { return pt(first + r.first, second + r.second, z + r.z); } inline pt operator*(const long double &r) const { return pt(first * r, second * r, z * r); } inline long double sqlen() const { return abs(first * first + second * second + z * z); } long double len() const { return sqrtl(sqlen()); } inline bool operator<(const pt &r) const { if (first != r.first) return first < r.first; return second < r.second; } inline bool operator==(const pt &r) const { return first == r.first && second == r.second; } }; ostream &operator<<(ostream &os, const pt &p) { return os << ( << p.first << , << p.second << ) ; } inline pt cross(const pt &l, const pt &r) { return pt(l.second * r.z - l.z * r.second, l.z * r.first - l.first * r.z, l.first * r.second - l.second * r.first); } inline long double dot(const pt &l, const pt &r) { return l.first * r.first + l.second * r.second + l.z * r.z; } long long pwmod(long long a, long long n, long long mod) { long long ret = 1; while (n) { if (n & 1) ret = ret * a % mod; a = a * a % mod; n >>= 1; } return ret; } template <typename T> inline T sqr(T first) { return first * first; } bool remin(long long &first, long long second) { if (first > second) { first = second; return 1; } return 0; } const int N = 300 * 1000; vector<int> g[N]; int size[N]; int parent[N]; int answer[N]; int maxSize[N]; vector<int> childs_[N]; void dfs(int v, int p = -1) { size[v] = 1; parent[v] = p; for (int to : g[v]) { if (to == p) continue; dfs(to, v); size[v] += size[to]; } maxSize[v] = 0; for (int to : g[v]) { if (to == p) continue; remax(maxSize[v], size[to]); } } void dfs2(int v, int p = -1) { vector<int> &ch = childs_[v]; for (int to : g[v]) { if (to == p) continue; dfs2(to, v); ch.push_back(answer[to]); } if (ch.empty()) { answer[v] = v; return; } for (int &u : ch) { int s = size[v] / 2; while (u != v && maxSize[parent[u]] <= s) { u = parent[u]; } } for (int u : ch) { int s = size[v] / 2; int top = size[v] - size[u]; if (maxSize[u] <= s && top <= s) { answer[v] = u; } } } void solve() { int n = nxt(); int q = nxt(); for (int i = 1; i < n; ++i) { int p = nxt() - 1; g[p].push_back(i); g[i].push_back(p); } dfs(0); dfs2(0); for (int i = 0; i < (int)(q); i++) { int v = nxt() - 1; cout << answer[v] + 1 << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); int t = 1; for (int i = 0; i < (int)(t); i++) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; string s[3]; int permutation[6][3] = {{0, 1, 2}, {0, 2, 1}, {1, 0, 2}, {1, 2, 0}, {2, 0, 1}, {2, 1, 0}}; string accepted_strings[6]; string process(string str) { string result = ; for (int i = 0; i < (int)str.length(); i++) { if (str[i] == - || str[i] == ; || str[i] == _ ) { continue; } if (isupper(str[i])) { result += str[i] + 32; continue; } result += str[i]; } return result; } string genString(int i) { string result = ; for (int j = 0; j < 3; j++) { result += s[permutation[i][j]]; } return result; } void solve() { cin >> s[0] >> s[1] >> s[2]; s[0] = process(s[0]); s[1] = process(s[1]); s[2] = process(s[2]); for (int i = 0; i < 6; i++) { accepted_strings[i] = genString(i); } int n; cin >> n; for (int i = 0; i < n; i++) { string t; cin >> t; t = process(t); bool acc = false; for (int j = 0; j < 6; j++) { if (t == accepted_strings[j]) { acc = true; break; } } if (acc) { cout << ACC n ; } else { cout << WA n ; } } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); solve(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxn = 400010, inf = 1 << 30; int N, M, father[maxn], nxt[maxn], toit[maxn], len[maxn], side[maxn], id[maxn], seq[maxn], D[maxn], cnt; int DFN, dfn[maxn], top[maxn], size[maxn], con[maxn], ans[maxn], tree[maxn << 2], cover[maxn << 2]; bool exist[maxn]; inline int find(int a) { if (father[a] != a) father[a] = find(father[a]); return father[a]; } inline void add(int a, int b, int c, int d) { nxt[++cnt] = side[a]; side[a] = cnt; toit[cnt] = b; len[cnt] = c; id[cnt] = d; } inline void ins(int a, int b, int c, int d) { add(a, b, c, d); add(b, a, c, d); } inline int gi() { char ch; int ret = 0, f = 1; do ch = getchar(); while (!(ch >= 0 && ch <= 9 ) && ch != - ); if (ch == - ) f = -1, ch = getchar(); do ret = ret * 10 + ch - 0 , ch = getchar(); while (ch >= 0 && ch <= 9 ); return ret * f; } struct Edge { int u, v, c, id; inline void read(int i) { id = i; u = gi(), v = gi(), c = gi(); } inline void bind() { int a = find(u), b = find(v); if (a != b) { father[a] = b; exist[id] = true; ins(u, v, c, id); } } friend inline bool operator<(const Edge &a, const Edge &b) { return a.c < b.c; } } edge[maxn]; inline void Div(int now, int Top) { dfn[now] = ++DFN; seq[DFN] = now; top[now] = Top; int heavy = 0; for (int i = side[now]; i; i = nxt[i]) if (toit[i] != father[now] && size[toit[i]] > size[heavy]) heavy = toit[i]; if (!heavy) return; Div(heavy, Top); for (int i = side[now]; i; i = nxt[i]) if (toit[i] != father[now] && toit[i] != heavy) Div(toit[i], toit[i]); } inline void dfs(int now) { size[now] = 1; for (int i = side[now]; i; i = nxt[i]) if (toit[i] != father[now]) { father[toit[i]] = now, con[toit[i]] = i; D[toit[i]] = D[now] + 1, dfs(toit[i]); size[now] += size[toit[i]]; } } inline void mst() { sort(edge + 1, edge + M + 1); cnt = 1; for (int i = 1; i <= N; ++i) father[i] = i; for (int i = 1; i <= M; ++i) edge[i].bind(); father[1] = 0; dfs(1); Div(1, 1); } inline int ask(int now, int l, int r, int ql, int qr) { if (l == ql && r == qr) return tree[now]; int mid = (l + r) >> 1; if (qr <= mid) return ask(now << 1, l, mid, ql, qr); else if (ql > mid) return ask(now << 1 | 1, mid + 1, r, ql, qr); else return max(ask(now << 1, l, mid, ql, mid), ask(now << 1 | 1, mid + 1, r, mid + 1, qr)); } inline void modify(int now, int l, int r, int ql, int qr, int c) { if (l == ql && r == qr) { cover[now] = min(cover[now], c); return; } int mid = (l + r) >> 1; if (qr <= mid) modify(now << 1, l, mid, ql, qr, c); else if (ql > mid) modify(now << 1 | 1, mid + 1, r, ql, qr, c); else { modify(now << 1, l, mid, ql, mid, c); modify(now << 1 | 1, mid + 1, r, mid + 1, qr, c); } } inline int Query(int a, int b, int c) { int ret = -inf; while (top[a] != top[b]) { if (D[top[a]] < D[top[b]]) swap(a, b); ret = max(ret, ask(1, 1, N, dfn[top[a]], dfn[a])); modify(1, 1, N, dfn[top[a]], dfn[a], c); a = father[top[a]]; } if (D[a] < D[b]) swap(a, b); if (a != b) { ret = max(ret, ask(1, 1, N, dfn[b] + 1, dfn[a])); modify(1, 1, N, dfn[b] + 1, dfn[a], c); } return ret; } inline void build(int now, int l, int r) { cover[now] = inf; if (l == r) { tree[now] = len[con[seq[l]]]; return; } int mid = (l + r) >> 1; build(now << 1, l, mid); build(now << 1 | 1, mid + 1, r); tree[now] = max(tree[now << 1], tree[now << 1 | 1]); } inline int query(int now, int l, int r, int pos) { if (l == r) return cover[now]; int mid = (l + r) >> 1; if (pos <= mid) return min(cover[now], query(now << 1, l, mid, pos)); else return min(cover[now], query(now << 1 | 1, mid + 1, r, pos)); } inline void work() { build(1, 1, N); for (int i = 1; i <= M; ++i) if (!exist[edge[i].id]) ans[edge[i].id] = Query(edge[i].u, edge[i].v, edge[i].c); for (int i = 2; i <= N; ++i) ans[id[con[i]]] = query(1, 1, N, dfn[i]); for (int i = 1; i <= M; ++i) { if (ans[i] == inf) ans[i] = -1; else --ans[i]; printf( %d , ans[i]); } } int main() { N = gi(); M = gi(); for (int i = 1; i <= M; ++i) edge[i].read(i), ans[i] = inf; mst(); work(); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX4_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__MUX4_PP_BLACKBOX_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND
);
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX4_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int NMAX = 1e6 + 5; const int MOD = 998244353; long long lgput(long long b, long long p) { long long r = 1; while (p) { if (p & 1) { r = 1LL * r * b % MOD; } p >>= 1; b = b * b % MOD; } return r; } long long N; vector<long long> lista[NMAX + 5]; long long good_kids[NMAX + 5]; long long cati[NMAX + 5]; long long total = 0, special = 0; long long answer = 0; void solve() { cin >> N; for (long long i = 1; i <= N; ++i) { cin >> cati[i]; for (long long j = 1; j <= cati[i]; ++j) { long long x; cin >> x; good_kids[x]++; lista[i].push_back(x); } total = (total + 1LL * N * cati[i] % MOD) % MOD; } for (long long i = 1; i <= N; ++i) { for (auto gift : lista[i]) { long long expected = 1LL * lgput(N, MOD - 2) * lgput(cati[i], MOD - 2) % MOD; expected = 1LL * expected * lgput(N, MOD - 2) % MOD * good_kids[gift] % MOD; answer = (answer + expected) % MOD; } } cout << answer << n ; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); long long t; t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; long long int power(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res; } bool sortinrev(const pair<int, int>& a, const pair<int, int>& b) { if (a.first == b.first) return b.second > a.second; return a.first > b.first; } void run(vector<int> v) { for (int i = 0; i < v.size(); i++) cout << v[i] << ; cout << endl; } int modInverse(long long int a, long long int m) { long long int m0 = m; long long int y = 0, x = 1; if (m == 1) return 0; while (a > 1) { long long int q = a / m; long long int t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } void numberOfNodes(int n, vector<long long int> adj[], vector<long long int>& count1, int s, int e) { vector<long long int>::iterator u; count1[s] = 1; for (u = adj[s].begin(); u != adj[s].end(); u++) { if (*u == e) continue; numberOfNodes(n, adj, count1, *u, s); count1[s] += count1[*u]; } } void solve() { int n; cin >> n; long long int a[n], b[n]; int vis[n]; long long int ans = 0; vector<vector<int>> v, total; memset(vis, 0, sizeof(vis)); for (int i = 0; i < n; i++) cin >> a[i]; for (int i = 0; i < n; i++) cin >> b[i]; for (int i = 0; i < n; i++) { int count = 0; if (!vis[i]) { for (int j = 0; j < n; j++) { if (j != i) { if (a[i] == a[j]) { if (count == 0) ans += b[i]; vis[j] = 1; vis[i] = 1; ans += b[j]; count++; } } } } } for (int i = 0; i < n; i++) { vector<int> vi(61); long long int m = a[i]; int count = 0; vector<int> ind; while (m > 0) { if (m % 2 == 1) { ind.push_back(count); } m = m / 2; count++; } for (int j = 0; j < ind.size(); j++) vi[ind[j]] = 1; total.push_back(vi); if (vis[i]) v.push_back(vi); } int count1, k; for (int i = 0; i < n; i++) { if (!vis[i]) { for (int j = 0; j < v.size(); j++) { for (k = 0; k < 60; k++) { if (total[i][k] == 1) { if (v[j][k] == 0) break; } } if (k == 60) { ans += b[i]; vis[i] = 1; v.push_back(total[i]); break; } } } } cout << ans << endl; } int main() { int t; t = 1; while (t--) { solve(); } return 0; } |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_1_cols_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_1_cols_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_1_cols_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_1_cols_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, q; int arr[1000010], lazy[1000010 << 2]; string str; struct data { int n4, n7, n47, n74; data() { n4 = n7 = n47 = n74 = 0; } } tree[1000010 << 2]; void build(int node, int l, int r) { if (l == r) { tree[node].n4 = (arr[l] == 4); tree[node].n7 = (arr[l] == 7); tree[node].n47 = 1; tree[node].n74 = 1; return; } int mid = (l + r) >> 1; build(node << 1, l, mid); build(node << 1 | 1, mid + 1, r); tree[node].n4 = tree[node << 1].n4 + tree[node << 1 | 1].n4; tree[node].n7 = tree[node << 1].n7 + tree[node << 1 | 1].n7; tree[node].n47 = max(max(tree[node << 1].n47 + tree[node << 1 | 1].n7, tree[node << 1].n4 + tree[node << 1 | 1].n47), tree[node << 1].n4 + tree[node << 1 | 1].n7); tree[node].n74 = max(max(tree[node << 1].n7 + tree[node << 1 | 1].n74, tree[node << 1].n74 + tree[node << 1 | 1].n4), tree[node << 1].n7 + tree[node << 1 | 1].n4); } void propagate(int node) { if (lazy[node]) { lazy[node << 1] ^= 1, lazy[node << 1 | 1] ^= 1; swap(tree[node << 1].n4, tree[node << 1].n7); swap(tree[node << 1 | 1].n4, tree[node << 1 | 1].n7); swap(tree[node << 1].n47, tree[node << 1].n74); swap(tree[node << 1 | 1].n47, tree[node << 1 | 1].n74); } lazy[node] = 0; } void update(int node, int l, int r, int i, int j) { if (r < i || l > j) return; if (i <= l && r <= j) { lazy[node] ^= 1; swap(tree[node].n4, tree[node].n7); swap(tree[node].n47, tree[node].n74); return; } int mid = (l + r) >> 1; propagate(node); update(node << 1, l, mid, i, j); update(node << 1 | 1, mid + 1, r, i, j); tree[node].n4 = tree[node << 1].n4 + tree[node << 1 | 1].n4; tree[node].n7 = tree[node << 1].n7 + tree[node << 1 | 1].n7; tree[node].n47 = max(max(tree[node << 1].n47 + tree[node << 1 | 1].n7, tree[node << 1].n4 + tree[node << 1 | 1].n47), tree[node << 1].n4 + tree[node << 1 | 1].n7); tree[node].n74 = max(max(tree[node << 1].n7 + tree[node << 1 | 1].n74, tree[node << 1].n74 + tree[node << 1 | 1].n4), tree[node << 1].n7 + tree[node << 1 | 1].n4); } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cin >> n >> q; for (int i = 0; i < n; ++i) { char c; cin >> c; arr[i + 1] = c - 0 ; } build(1, 1, n); while (q--) { cin >> str; if (str == count ) { cout << tree[1].n47 << n ; } else { int l, r; cin >> l >> r; update(1, 1, n, l, r); } } } |
#include <bits/stdc++.h> using namespace std; int main() { vector<long long> v; int n; cin >> n; v.resize(n); for (int i = 0; i < n; i++) { cin >> v[i]; } sort(v.rbegin(), v.rend()); long long ans = v[0]; for (int i = 1; i < n; i++) { if (v[i] >= v[i - 1]) v[i] = max(v[i - 1] - 1, 0LL); ans += v[i]; } cout << ans; } |
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
////////////////////////////////////////////////////////////
//
// axis to vector
// A generic module to merge all axis 'data' signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axis_infrastructure_v1_1_0_util_axis2vector
//
//--------------------------------------------------------------------------
`ifndef AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V
`define AXIS_INFRASTRUCTURE_V1_0_UTIL_AXIS2VECTOR_V
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axis_infrastructure_v1_1_0_util_axis2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_TDATA_WIDTH = 32,
parameter integer C_TID_WIDTH = 1,
parameter integer C_TDEST_WIDTH = 1,
parameter integer C_TUSER_WIDTH = 1,
parameter integer C_TPAYLOAD_WIDTH = 44,
parameter [31:0] C_SIGNAL_SET = 32'hFF
// C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
// [0] => TREADY present
// [1] => TDATA present
// [2] => TSTRB present, TDATA must be present
// [3] => TKEEP present, TDATA must be present
// [4] => TLAST present
// [5] => TID present
// [6] => TDEST present
// [7] => TUSER present
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// inputs
input wire [C_TDATA_WIDTH-1:0] TDATA,
input wire [C_TDATA_WIDTH/8-1:0] TSTRB,
input wire [C_TDATA_WIDTH/8-1:0] TKEEP,
input wire TLAST,
input wire [C_TID_WIDTH-1:0] TID,
input wire [C_TDEST_WIDTH-1:0] TDEST,
input wire [C_TUSER_WIDTH-1:0] TUSER,
// outputs
output wire [C_TPAYLOAD_WIDTH-1:0] TPAYLOAD
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axis_infrastructure_v1_1_0_axis_infrastructure.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_TDATA_INDX = f_get_tdata_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TSTRB_INDX = f_get_tstrb_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TKEEP_INDX = f_get_tkeep_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TLAST_INDX = f_get_tlast_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TID_INDX = f_get_tid_indx (C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TDEST_INDX = f_get_tdest_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
localparam P_TUSER_INDX = f_get_tuser_indx(C_TDATA_WIDTH, C_TID_WIDTH,
C_TDEST_WIDTH, C_TUSER_WIDTH,
C_SIGNAL_SET);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_SIGNAL_SET[G_INDX_SS_TDATA]) begin : gen_tdata
assign TPAYLOAD[P_TDATA_INDX+:C_TDATA_WIDTH] = TDATA;
end else begin : no_gen_tdata
// Do nothing
end
if (C_SIGNAL_SET[G_INDX_SS_TSTRB]) begin : gen_tstrb
assign TPAYLOAD[P_TSTRB_INDX+:C_TDATA_WIDTH/8] = TSTRB;
end else begin : no_gen_tstrb
// Do nothing
end
if (C_SIGNAL_SET[G_INDX_SS_TKEEP]) begin : gen_tkeep
assign TPAYLOAD[P_TKEEP_INDX+:C_TDATA_WIDTH/8] = TKEEP;
end else begin : no_gen_tkeep
// Do nothing
end
if (C_SIGNAL_SET[G_INDX_SS_TLAST]) begin : gen_tlast
assign TPAYLOAD[P_TLAST_INDX+:1] = TLAST;
end else begin : no_gen_tlast
// Do nothing
end
if (C_SIGNAL_SET[G_INDX_SS_TID]) begin : gen_tid
assign TPAYLOAD[P_TID_INDX+:C_TID_WIDTH] = TID;
end else begin : no_gen_tid
// Do nothing
end
if (C_SIGNAL_SET[G_INDX_SS_TDEST]) begin : gen_tdest
assign TPAYLOAD[P_TDEST_INDX+:C_TDEST_WIDTH] = TDEST;
end else begin : no_gen_tdest
// Do nothing
end
if (C_SIGNAL_SET[G_INDX_SS_TUSER]) begin : gen_tuser
assign TPAYLOAD[P_TUSER_INDX+:C_TUSER_WIDTH] = TUSER;
end else begin : no_gen_tuser
// Do nothing
end
endgenerate
endmodule
`default_nettype wire
`endif
|
#include <bits/stdc++.h> using namespace std; vector<long long> g[(long long)3e5], a((long long)3e5); long long i, n, x, y, r; void b(long long p, long long q, long long m) { a[p]++, r += m; for (auto j : g[p]) if (j != q) b(j, p, m ^ 1), a[p] += a[j]; } int main() { for (cin >> n, i = 1; i < n; i++) cin >> x >> y, g[x].push_back(y), g[y].push_back(x); b(1, 0, 0), r *= (n - r); for (i = 1; i <= n; i++) r += a[i] * (n - a[i]); cout << r / 2; } |
#include <bits/stdc++.h> using namespace std; void actionFun() { long long n; cin >> n; long long c = 2; for (int i = 0; i < n; i++) { cout << c << ; ++c; } cout << endl; return; } int main() { int t; cin >> t; while (t--) { actionFun(); } } |
#include <bits/stdc++.h> #pragma GCC optimize( O3 ) using namespace std; using ll = long long; using ld = long double; using pii = pair<int, int>; using vi = vector<int>; const ld EPS = 1E-9; struct pt { ld x, y; }; struct seg { pt p, q; int id; ld get_y(ld x) const { if (abs(p.x - q.x) < EPS) return p.y; return p.y + (q.y - p.y) * (x - p.x) / (q.x - p.x); } }; inline bool intersect1d(ld l1, ld r1, ld l2, ld r2) { if (l1 > r1) swap(l1, r1); if (l2 > r2) swap(l2, r2); return max(l1, l2) <= min(r1, r2) + EPS; } inline int vec(const pt& a, const pt& b, const pt& c) { ld s = (b.x - a.x) * (c.y - a.y) - (b.y - a.y) * (c.x - a.x); return abs(s) < EPS ? 0 : s > 0 ? +1 : -1; } bool intersect(const seg& a, const seg& b) { return intersect1d(a.p.x, a.q.x, b.p.x, b.q.x) && intersect1d(a.p.y, a.q.y, b.p.y, b.q.y) && vec(a.p, a.q, b.p) * vec(a.p, a.q, b.q) <= 0 && vec(b.p, b.q, a.p) * vec(b.p, b.q, a.q) <= 0; } bool operator<(const seg& a, const seg& b) { ld x = max(min(a.p.x, a.q.x), min(b.p.x, b.q.x)); return a.get_y(x) < b.get_y(x) - EPS; } struct event { ld x; int tp, id; event() {} event(ld x, int tp, int id) : x(x), tp(tp), id(id) {} bool operator<(const event& e) const { if (abs(x - e.x) > EPS) return x < e.x; return tp > e.tp; } }; set<seg> s; vector<set<seg>::iterator> where; inline set<seg>::iterator prev(set<seg>::iterator it) { return it == s.begin() ? s.end() : --it; } inline set<seg>::iterator next(set<seg>::iterator it) { return ++it; } pair<int, int> solve(const vector<seg>& a) { int n = (int)a.size(); vector<event> e; for (int i = 0; i < n; ++i) { e.push_back(event(min(a[i].p.x, a[i].q.x), +1, i)); e.push_back(event(max(a[i].p.x, a[i].q.x), -1, i)); } sort(e.begin(), e.end()); s.clear(); where.resize(a.size()); for (size_t i = 0; i < e.size(); ++i) { int id = e[i].id; if (e[i].tp == +1) { set<seg>::iterator nxt = s.lower_bound(a[id]), prv = prev(nxt); if (nxt != s.end() && intersect(*nxt, a[id])) return make_pair(nxt->id, id); if (prv != s.end() && intersect(*prv, a[id])) return make_pair(prv->id, id); where[id] = s.insert(nxt, a[id]); } else { set<seg>::iterator nxt = next(where[id]), prv = prev(where[id]); if (nxt != s.end() && prv != s.end() && intersect(*nxt, *prv)) return make_pair(prv->id, nxt->id); s.erase(where[id]); } } return make_pair(-1, -1); } int main() { ios::sync_with_stdio(0), cin.tie(0); int n; cin >> n; vector<pt> S(n), V(n); vi U(n); for (int i = 0; i < n; i++) { cin >> S[i].x >> S[i].y >> V[i].x >> V[i].y >> U[i]; ld len = sqrt(V[i].x * V[i].x + V[i].y * V[i].y); V[i].x /= len; V[i].y /= len; V[i].x *= U[i]; V[i].y *= U[i]; } ld lf = 0, rg = 1e12; { ld md = rg; vector<seg> a(n); for (int i = 0; i < n; i++) { a[i].id = i; a[i].p = S[i]; ld X = S[i].x + V[i].x * md; ld Y = S[i].y + V[i].y * md; a[i].q = {X, Y}; } if (solve(a) == make_pair(-1, -1)) { cout << No show :( ; return 0; } } const ld _eps = 1e-8; while ((rg - lf) > _eps) { ld md = (lf + rg) / 2; vector<seg> a(n); for (int i = 0; i < n; i++) { a[i].id = i; a[i].p = S[i]; ld X = S[i].x + V[i].x * md; ld Y = S[i].y + V[i].y * md; a[i].q = {X, Y}; } if (solve(a) != make_pair(-1, -1)) { rg = md; } else { lf = md; } } cout.precision(10); cout << fixed << (lf + rg) / 2; } |
// Gris InterConnect slave
// This module acts as a Wishbone master and receives operations from
// the GIC Master which acts as a Wishbone slave.
module gic_slave #(
parameter idle = 4'b1111
) (
output [31:0] wbm_adr_o,
output wbm_stb_o,
output wbm_cyc_o,
output [3:0] wbm_sel_o,
output wbm_we_o,
output [2:0] wbm_cti_o,
output [1:0] wbm_bte_o,
output [31:0] wbm_dat_o,
input wbm_err_i,
input wbm_ack_i,
input [31:0] wbm_dat_i,
input wbm_rty_i,
input wbm_clk_i,
input wbm_rst_i,
input [3:0] gic_dat_i,
output [3:0] gic_dat_o
);
localparam master_initiate = 4'b1010;
localparam slave_initiate = 4'b0101;
localparam state_m_init = 0;
localparam state_m_cmd = 1;
localparam state_m_sel = 2;
localparam state_m_adr = 3;
localparam state_m_dat = 4;
localparam state_m_cksum = 5;
localparam state_s_init = 6;
localparam state_s_resp = 7;
localparam state_s_dat = 8;
localparam state_s_cksum = 9;
reg [3:0] state_r = state_m_init;
reg [3:0] next_state_r = state_m_init;
reg [2:0] cntr_r = 0;
reg [3:0] gic_dat_r = 0;
reg [3:0] gic_chksum_r = 0;
reg data_correct_r = 1'b0;
reg wb_we_r = 1'b0;
reg [31:0] wb_adr_r = 0;
reg [31:0] wb_dat_r = 0;
reg [31:0] wbm_dat_r = 0;
reg [3:0] wb_sel_r = 0;
reg wb_cycle_r = 1'b0;
// We invert part of last checksum to make the bus cycle
// with all 1/0's invalid.
wire [3:0] chksum_operand = (cntr_r == 0) ? 4'b1100 : 4'b0000;
assign wbm_adr_o = wb_adr_r;
assign wbm_dat_o = wb_dat_r;
assign wbm_we_o = wb_we_r;
assign wbm_stb_o = wb_cycle_r & data_correct_r;
assign wbm_cyc_o = wb_cycle_r & data_correct_r;
assign wbm_sel_o = wb_sel_r;
assign wbm_cti_o = 3'b000; // We only support classic cycles
assign wbm_cti_o = 3'b000;
assign wbm_bte_o = 2'b00;
wire cycle_complete = wbm_ack_i | wbm_err_i | wbm_rty_i;
assign gic_dat_o = gic_dat_r;
// Mealy FSM
always @(posedge wbm_clk_i)
begin
if (wbm_rst_i) begin
state_r <= state_m_init;
end else begin
state_r <= next_state_r;
end
end
// Data/address position counter
always @(posedge wbm_clk_i)
begin
if (wbm_rst_i) begin
cntr_r <= 7;
end else begin
cntr_r <= 7;
if ((state_r == state_m_adr) | (state_r == state_m_dat) |
(state_r == state_s_dat)) begin
// Since we're in each of the above states for 8 cycles we will
// overflow and up at 7 again, so the transition from m_adr -> m_dat.
cntr_r <= cntr_r - 1;
end
end
end
// Checksum calculator
always @(posedge wbm_clk_i)
begin
gic_chksum_r <= gic_chksum_r;
case (state_r)
state_m_sel:
gic_chksum_r <= gic_dat_i;
state_m_adr | state_m_dat:
gic_chksum_r <= gic_chksum_r ^ gic_dat_i ^ chksum_operand;
state_s_resp:
gic_chksum_r <= 0;
state_s_dat:
gic_chksum_r <= gic_chksum_r ^ wbm_dat_r[cntr_r*4+:4] ^ chksum_operand;
endcase
end
// Checksum validator
always @(state_r)
begin
data_correct_r <= 1'b1;
// TODO(bluecmd)
end
// GIC Data driver
always @(state_r or cntr_r or cycle_complete)
begin
gic_dat_r <= idle;
case (state_r)
state_s_init:
if (cycle_complete)
gic_dat_r <= slave_initiate;
state_s_resp:
gic_dat_r <= 4'bxxxx;
state_s_dat:
gic_dat_r <= wbm_dat_r[cntr_r*4+:4];
state_s_cksum:
gic_dat_r <= gic_chksum_r;
endcase
end
// Wishbone driver
always @(posedge wbm_clk_i)
begin
wb_adr_r <= wb_adr_r;
wb_dat_r <= wb_dat_r;
wb_sel_r <= wb_sel_r;
wb_cycle_r <= wb_cycle_r;
wb_we_r <= wb_we_r;
case (state_r)
state_m_cmd:
wb_we_r <= gic_dat_i[3];
state_m_sel:
wb_sel_r <= gic_dat_i;
state_m_adr:
wb_adr_r[cntr_r*4+:4] <= gic_dat_i;
state_m_dat:
wb_dat_r[cntr_r*4+:4] <= gic_dat_i;
state_m_cksum:
wb_cycle_r <= 1'b1;
state_s_init:
wb_cycle_r <= ~cycle_complete;
endcase
end
// Wishbone input capture
always @(posedge wbm_clk_i)
begin
wbm_dat_r <= wbm_dat_r;
case (state_r)
state_s_init:
if (cycle_complete)
wbm_dat_r <= wbm_dat_i;
endcase
end
always @(state_r or cntr_r or cycle_complete)
begin
next_state_r <= state_r;
case (state_r)
state_m_init:
if (gic_dat_i == master_initiate)
next_state_r <= state_m_cmd;
state_m_cmd:
next_state_r <= state_m_sel;
state_m_sel:
next_state_r <= state_m_adr;
state_m_adr:
if (cntr_r == 0)
next_state_r <= wb_we_r ? state_m_dat : state_m_cksum;
state_m_dat:
if (cntr_r == 0)
next_state_r <= state_m_cksum;
state_m_cksum:
next_state_r <= state_s_init;
state_s_init:
if (cycle_complete)
next_state_r <= state_s_resp;
state_s_resp:
next_state_r <= wb_we_r ? state_m_init : state_s_dat;
state_s_dat:
if (cntr_r == 0)
next_state_r <= state_s_cksum;
state_s_cksum:
next_state_r <= state_m_init;
endcase
end
`ifdef DEBUG_GIC_SLAVE
always @(posedge wbm_clk_i)
begin
if (cycle_complete & (state_r == state_s_init)) begin
$display("Finished wishbone cycle: 0x%08x", wb_adr_r);
$display("Data returned: 0x%08x", wbm_dat_i);
$display("Status: ACK %b ERR %b RTY %b", wbm_ack_i, wbm_err_i, wbm_rty_i);
end else if (state_r == state_s_dat) begin
$display("Checksum: %4b", gic_chksum_r);
end else if (state_r == state_s_cksum) begin
$display("Final Checksum: %4b", gic_chksum_r);
end
end
`endif
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { double r, x, y, z, t; cin >> r >> x >> y >> z >> t; double d = (x - z) * (x - z) + (y - t) * (y - t); d = sqrt(d); double i; for (i = 0; i < 10000000; i++) { if ((i * r) >= d / 2) break; } cout << i << endl; } |
#include <bits/stdc++.h> using namespace std; int n, k; int query(int x, int y) { cout << 1 << x << << y << endl; string ans; cin >> ans; if (ans == TAK ) return 1; return 0; } int find(int l, int r) { if (l > r) return -1; int L = l; int R = r; while (L < R) { int mid = (L + R) / 2; if (query(mid, mid + 1)) R = mid; else L = mid + 1; } return L; } int main() { cin >> n >> k; int x = find(1, n); int y = find(1, x - 1); if (x == 1 || !query(y, x)) y = find(x + 1, n); cout << 2 << x << << y << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; pair<int, int> x[1024], y[1024]; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t; cin >> t; while (t--) { int n; cin >> n; for (int i = 0; i < n; i++) { cin >> x[i].first >> x[i].second; y[i].first = x[i].first; y[i].second = x[i].second; } sort(x, x + n, [](const pair<int, int>& a, const pair<int, int>& b) { return a.first < b.first || (a.first == b.first && a.second < b.second); }); sort(y, y + n, [](const pair<int, int>& a, const pair<int, int>& b) { return a.second < b.second || (a.second == b.second && a.first < b.first); }); string ans = ; int r = 0, c = 0; for (int i = 0; i < n; i++) { if (x[i] != y[i]) { cout << NO << endl; ans = ; break; } else { ans += string(x[i].first - r, R ); ans += string(x[i].second - c, U ); r = x[i].first; c = x[i].second; } } if (!ans.empty()) { cout << YES << endl << ans << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; struct Rect { int x1, y1, x2, y2; long long area() { return (long long)(x2 - x1) * (y2 - y1); } }; long long intersect(const Rect&, const Rect&); Rect intersectingRect(const Rect&, const Rect&); int main() { Rect white, black1, black2, b1Inside, b2Inside; long long b1Cover, b2Cover, totalCover; cin >> white.x1 >> white.y1 >> white.x2 >> white.y2; cin >> black1.x1 >> black1.y1 >> black1.x2 >> black1.y2; cin >> black2.x1 >> black2.y1 >> black2.x2 >> black2.y2; b1Cover = intersect(white, black1); b2Cover = intersect(white, black2); b1Inside = intersectingRect(white, black1); b2Inside = intersectingRect(white, black2); totalCover = b1Cover + b2Cover - intersect(b1Inside, b2Inside); if (white.area() - totalCover == 0) cout << NO ; else cout << YES ; } long long intersect(const Rect& rect1, const Rect& rect2) { long long x = max(0, min(rect1.x2, rect2.x2) - max(rect1.x1, rect2.x1)); long long y = max(0, min(rect1.y2, rect2.y2) - max(rect1.y1, rect2.y1)); return x * y; } Rect intersectingRect(const Rect& rect1, const Rect& rect2) { Rect rect; if (intersect(rect1, rect2)) { rect.x1 = max(rect1.x1, rect2.x1); rect.x2 = min(rect1.x2, rect2.x2); rect.y1 = max(rect1.y1, rect2.y1); rect.y2 = min(rect1.y2, rect2.y2); } else { rect.x1 = 0; rect.x2 = 0; rect.y1 = 0; rect.y2 = 0; } return rect; } |
// Verilog netlist generated by Workcraft 3
module VME (d, lds, dtack, dsr, dsw, ldtack);
input dsr, dsw, ldtack;
output d, lds, dtack;
wire U1_ON, IN_BUBBLE3_ON, IN_BUBBLE5_ON, U7_ON, IN_BUBBLE10_ON, OUT_BUBBLE1_ON, U14_ON, IN_BUBBLE16_ON, IN_BUBBLE18_ON, U20_ON, IN_BUBBLE23_ON, IN_BUBBLE25_ON, IN_BUBBLE28_ON, OUT_BUBBLE2_ON, U31_ON, IN_BUBBLE33_ON, OUT_BUBBLE3_ON, U36_ON;
NAND3BX1 U1 (.Y(U1_ON), .AN(OUT_BUBBLE3_ON), .B(ldtack), .C(dsr));
// This inverter should have a short delay
INVX1 IN_BUBBLE3 (.Y(IN_BUBBLE3_ON), .A(OUT_BUBBLE2_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE5 (.Y(IN_BUBBLE5_ON), .A(ldtack));
OAI221X1 U7 (.Y(U7_ON), .A0(IN_BUBBLE3_ON), .A1(d), .B0(IN_BUBBLE5_ON), .B1(OUT_BUBBLE3_ON), .C0(dsw));
NAND2X1 U8 (.Y(d), .A(U7_ON), .B(U1_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE10 (.Y(IN_BUBBLE10_ON), .A(OUT_BUBBLE3_ON));
INVX1 OUT_BUBBLE1 (.Y(OUT_BUBBLE1_ON), .A(U14_ON));
OAI221X1 U14 (.Y(U14_ON), .A0(d), .A1(dsr), .B0(dsr), .B1(OUT_BUBBLE2_ON), .C0(IN_BUBBLE10_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE16 (.Y(IN_BUBBLE16_ON), .A(OUT_BUBBLE2_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE18 (.Y(IN_BUBBLE18_ON), .A(dsw));
OAI31X1 U20 (.Y(U20_ON), .A0(IN_BUBBLE18_ON), .A1(IN_BUBBLE16_ON), .A2(d), .B0(OUT_BUBBLE3_ON));
C2 U21 (.Q(lds), .A(U20_ON), .B(OUT_BUBBLE1_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE23 (.Y(IN_BUBBLE23_ON), .A(OUT_BUBBLE3_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE25 (.Y(IN_BUBBLE25_ON), .A(OUT_BUBBLE2_ON));
AOI221X1 U26 (.Y(dtack), .A0(IN_BUBBLE23_ON), .A1(dsw), .B0(d), .B1(OUT_BUBBLE3_ON), .C0(IN_BUBBLE25_ON));
// This inverter should have a short delay
INVX1 IN_BUBBLE28 (.Y(IN_BUBBLE28_ON), .A(OUT_BUBBLE3_ON));
INVX1 OUT_BUBBLE2 (.Y(OUT_BUBBLE2_ON), .A(U31_ON));
OAI222X1 U31 (.Y(U31_ON), .A0(IN_BUBBLE28_ON), .A1(dsw), .B0(OUT_BUBBLE2_ON), .B1(d), .C0(d), .C1(lds));
// This inverter should have a short delay
INVX1 IN_BUBBLE33 (.Y(IN_BUBBLE33_ON), .A(d));
INVX1 OUT_BUBBLE3 (.Y(OUT_BUBBLE3_ON), .A(U36_ON));
AOI32X1 U36 (.Y(U36_ON), .A0(IN_BUBBLE33_ON), .A1(ldtack), .A2(OUT_BUBBLE2_ON), .B0(ldtack), .B1(OUT_BUBBLE3_ON));
// signal values at the initial state:
// U1_ON IN_BUBBLE3_ON IN_BUBBLE5_ON U7_ON !d IN_BUBBLE10_ON !OUT_BUBBLE1_ON U14_ON IN_BUBBLE16_ON IN_BUBBLE18_ON U20_ON !lds IN_BUBBLE23_ON IN_BUBBLE25_ON !dtack IN_BUBBLE28_ON !OUT_BUBBLE2_ON U31_ON IN_BUBBLE33_ON !OUT_BUBBLE3_ON U36_ON !dsr !dsw !ldtack
endmodule
|
#include <bits/stdc++.h> using namespace std; int f[10000050], pre[10000050], used[10000050], edge[105]; vector<int> vec; int main() { int n, m, i, j, x, y, maxi, size, news; scanf( %d%d , &n, &m); for (i = 1; i <= m; i++) { scanf( %d%d , &x, &y); edge[x] |= 1 << y; edge[y] |= 1 << x; } memset(f, 127, sizeof(f)); for (i = 1; i <= n; i++) f[1 << i] = 0; maxi = 0; for (i = 1; i <= n; i++) maxi |= 1 << i; for (i = 0; i <= maxi; i++) if (f[i] < 999999999) { for (j = 1; j <= n; j++) if ((1 << j) & i) { news = i | edge[j]; if (f[i] + 1 < f[news]) { f[news] = f[i] + 1; used[news] = j; pre[news] = i; } } else if ((i & edge[j]) == i) { news = i | (1 << j); if (f[i] < f[news]) { f[news] = f[i]; used[news] = 0; pre[news] = i; } } } vec.clear(); for (i = maxi; (i & -i) != i; i = pre[i]) if (used[i]) vec.push_back(used[i]); size = vec.size(); printf( %d n , size); for (i = size - 1; i >= 0; i--) printf( %d , vec[i]); printf( n ); return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD3_FUNCTIONAL_PP_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__clkdlyinv5sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD3_FUNCTIONAL_PP_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Matt Myers.
// SPDX-License-Identifier: CC0-1.0
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
package config_pkg;
typedef struct packed {
int UPPER0;
struct packed {
int USE_QUAD0;
int USE_QUAD1;
int USE_QUAD2;
} mac;
int UPPER2;
} config_struct;
function automatic config_struct static_config(int selector);
config_struct return_config;
return_config = '0;
return_config.UPPER0 = 10;
return_config.UPPER2 = 20;
return_config.mac.USE_QUAD0 = 4;
return_config.mac.USE_QUAD2 = 6;
case (selector)
1: return_config.mac.USE_QUAD1 = 5;
endcase
return return_config;
endfunction
endpackage : config_pkg
module t;
import config_pkg::*;
localparam config_struct MY_CONFIG = static_config(1);
struct_submodule #(.MY_CONFIG(MY_CONFIG)) a_submodule_I ();
endmodule : t
module struct_submodule
import config_pkg::*;
#(parameter config_struct MY_CONFIG = '0);
initial begin
`checkd(MY_CONFIG.UPPER0, 10);
`checkd(MY_CONFIG.mac.USE_QUAD0, 4);
`checkd(MY_CONFIG.mac.USE_QUAD1, 5);
`checkd(MY_CONFIG.mac.USE_QUAD2, 6);
`checkd(MY_CONFIG.UPPER2, 20);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : struct_submodule
|
#include <bits/stdc++.h> using namespace std; int main() { int m, n; cin >> m >> n; vector<int> sg(n, +1); for (int i = 1, x; i <= n; ++i) { cout << i << n ; fflush(stdout); cin >> x; if (x < 0) sg[i - 1] = -1; if (x == 0) return 0; } int l = n + 1, r = m, pt = 0, x; while (l < r) { int md = (l + r) >> 1; cout << md << n ; fflush(stdout); cin >> x; x *= sg[pt]; pt = (pt + 1) % n; if (x == 0) return 0; if (x < 0) r = md; else l = md + 1; } cout << l << n ; fflush(stdout); return 0; } |
module xyz (/*AUTOARG*/
// Outputs
signal_f, signal_c,
// Inputs
signal_b
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [2:0] signal_b; // To u_abc of abc.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output signal_c; // From u_abc of abc.v
output signal_f; // From u_def of def.v
// End of automatics
/*AUTOWIRE*/
/* abc AUTO_TEMPLATE
(
// Outputs
.signal_c (signal_c),
// Inputs
.signal_a ({1'b0, signal_f}),
.signal_b (signal_b[2:0]));
*/
abc u_abc
(/*AUTOINST*/
// Outputs
.signal_c (signal_c), // Templated
// Inputs
.signal_a ({1'b0, signal_f}), // Templated
.signal_b (signal_b[2:0])); // Templated
/* def AUTO_TEMPLATE
(// Outputs
.signal_f (signal_f),
// Inputs
.signal_d ({1'b1, signal_c}),
.signal_e ({2'b11, signal_e}));
*/
def u_def
(/*AUTOINST*/
// Outputs
.signal_f (signal_f), // Templated
// Inputs
.signal_d ({1'b1, signal_c}), // Templated
.signal_e ({2'b11, signal_e})); // Templated
endmodule // xyz
module abc (/*AUTOARG*/
// Outputs
signal_c,
// Inputs
signal_a, signal_b
);
input [1:0] signal_a;
input [2:0] signal_b;
output signal_c;
endmodule // abc
module def (/*AUTOARG*/
// Outputs
signal_f,
// Inputs
signal_d, signal_e
);
input [1:0] signal_d;
input [2:0] signal_e;
output signal_f;
endmodule // def
// Local Variables:
// verilog-auto-ignore-concat: t
// End:
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int MAXN = 1e5 + 10; bool bd[MAXN]; int n; int a[MAXN]; vector<pair<int, int>> sol; pair<int, int> coord(pair<int, int> p) { return {(n - 1 - p.second), p.first}; } int main(void) { scanf( %d , &n); for (int i = 0; i < n; ++i) scanf( %d , &a[i]); for (int i = 0; i < n; ++i) bd[i] = false; int lst = -1; queue<int> dva; for (int i = n - 1; i >= 0; --i) { if (a[i] == 0) continue; while (!dva.empty() && bd[dva.front()]) dva.pop(); if ((a[i] == 2 && dva.empty()) || (a[i] == 3 && lst == -1)) { printf( -1 n ); return 0; } if (a[i] == 1) { sol.emplace_back(i, (n - 1) - i); lst = i; dva.push(i); continue; } if (a[i] == 2) { int xx = dva.front(); dva.pop(); bd[i] = bd[xx] = true; sol.emplace_back(i, (n - 1) - xx); lst = i; } if (a[i] == 3) { sol.emplace_back(i, (n - 1) - i); sol.emplace_back(lst, (n - 1) - i); bd[i] = bd[lst] = true; lst = i; } } printf( %d n , (int)sol.size()); for (auto &p : sol) { auto c = coord(p); printf( %d %d n , c.first + 1, c.second + 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2000 * 2000 + 1; int n, m, mark[N], mx, rep; string s; vector<int> adj[N]; bool circle(int v) { mark[v] = 1; for (int i = 0; i < adj[v].size(); i++) { int u = adj[v][i]; if (mark[u] == 1 || (!mark[u] && circle(u))) return true; } mark[v] = 2; return false; } int dfs(int v) { int res = 1; for (int i = 0; i < adj[v].size(); i++) { int u = adj[v][i], t = dfs(u); res = max(res, t + 1); if (t > mx) mx = t, rep = false; else if (t == mx) rep = true; } return res; } int main() { ios_base::sync_with_stdio(false); cin >> n >> m; for (int i = 0; i < n; i++) { string t; cin >> t; s += t; } n *= m; for (int i = 0; i < n; i++) if (s[i] == ^ ) adj[i - m].push_back(i); else if (s[i] == < ) adj[i - 1].push_back(i); else if (s[i] == > ) adj[i + 1].push_back(i); else if (s[i] == v ) adj[i + m].push_back(i); for (int i = 0; i < n; i++) if (circle(i)) { cout << -1 << n ; return 0; } fill(mark, mark + n, 0); for (int i = 0; i < n; i++) if (s[i] == # ) dfs(i); cout << max(0, 2 * mx - !rep) << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; using namespace placeholders; template <class T> void mini(T &l, T r) { l = min(l, r); } template <class T> void maxi(T &l, T r) { l = max(l, r); } template <class TH> void _dbg(const char *sdbg, TH h) { cerr << sdbg << = << h << n ; } template <class TH, class... TA> void _dbg(const char *sdbg, TH h, TA... a) { while (*sdbg != , ) cerr << *sdbg++; cerr << = << h << , ; _dbg(sdbg + 1, a...); } template <class T> ostream &operator<<(ostream &os, vector<T> v) { os << [ ; for (auto vv : v) os << vv << , ; return os << ] ; } template <class L, class R> ostream &operator<<(ostream &os, pair<L, R> p) { return os << ( << p.first << , << p.second << ) ; } using llint = long long; const int B = 1e9 + 7; int a[40][40]; llint mem[40], cnt[40]; void add(llint &a, llint b) { a = (a + b) % B; if (a < 0) a += B; } void init() { mem[0] = 1; cnt[0] = 1; for (int i = 1; i < 40; ++i) { int c = 1 << (i - 1); cnt[i] = cnt[i - 1] * 4 % B; add(mem[i], mem[i - 1] * 4 % B + 1ll * c * c % B * c % B * 2 % B); } } llint calc(llint a, llint b) { a %= B, b %= B; return ((a + b) * (b - a + 1) / 2) % B; } pair<llint, llint> get(int x, int y, int k, int d) { llint ret = 0; int sz = 1 << d; if (x < y) swap(x, y); if (x <= 0 || y <= 0 || k <= 0) return make_pair(0, 0); if (x >= sz) { llint a = min(k, sz); llint b = min(y, sz); ret = calc(1, a) * b % B; ; return make_pair(b * calc(1, a) % B, b * a % B); } if (d == 0) return make_pair(1 <= k, 1 <= k); int t = 1 << (d - 1); auto t1 = get(x, y, k, d - 1); auto t2 = get(x - t, y, k - t, d - 1); auto t3 = get(y, y - t, k - t, d - 1); auto t4 = get(x - t, y - t, k, d - 1); ; add(ret, t1.first); add(ret, t2.first + t2.second * t % B); add(ret, t3.first + t3.second * t % B); add(ret, t4.first); llint c = 0; add(c, t1.second); add(c, t2.second); add(c, t3.second); add(c, t4.second); ; return make_pair(ret, c); } llint go(int x1, int y1, int x2, int y2, int k) { llint ret = 0; add(ret, get(x2, y2, k, 30).first); add(ret, -get(x1 - 1, y2, k, 30).first); add(ret, -get(x2, y1 - 1, k, 30).first); add(ret, get(x1 - 1, y1 - 1, k, 30).first); return ret; } void run() { init(); ; int q; scanf( %d , &q); for (int i = 1; i <= q; ++i) { int x1, y1, x2, y2, k; scanf( %d%d%d%d%d , &x1, &y1, &x2, &y2, &k); printf( %lld n , go(x1, y1, x2, y2, k)); } } int main() { run(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0); int n, m; cin >> n >> m; vector<vector<int>> adj(n); for (int i = 0, u, v; i < m; ++i) { cin >> u >> v; --u, --v; adj[u].push_back(v); adj[v].push_back(u); } set<int> go; queue<int> q; for (int i = 0; i < n; ++i) go.insert(i); int ans = 0; for (int x = 0; x < n; ++x) if (go.find(x) != go.end()) { ++ans; go.erase(x); q.push(x); while (!q.empty()) { int u = q.front(); q.pop(); vector<int> add; for (auto v : adj[u]) if (go.find(v) != go.end()) { go.erase(v); add.push_back(v); } for (auto v : go) q.push(v); go.clear(); for (auto v : add) go.insert(v); } } cout << ans - 1 << n ; return 0; } |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : CRT Registers decoding logic
// File : crt_reg_dec.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module does rd/wr decoding for CR registers.
// The decoding supports 16-bit and 8-bit writes.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module crt_reg_dec
(
input h_reset_n,
input h_iord,
input h_iowr,
input h_hclk,
input h_io_16,
input h_io_8,
input misc_b0, // 0- 3bx, 1- 3dx
input h_dec_3bx,
input h_dec_3cx,
input h_dec_3dx,
input m_dec_sr07,
input m_dec_sr00_sr06,
input [15:0] h_io_addr,
input [15:0] h_io_dbus,
output [7:0] crtc_index, // crtc index register
output reg [7:0] ext_index, // extension index register
output trim_wr, // delayed write strobe to load data reg
output c_gr_ext_en,
output [3:0] c_ext_index_b,
output crt_mod_rd_en_hb,
output crt_mod_rd_en_lb,
output c_ready_n,
output sr_00_06_wr, // any iowrite to 3C5 index = 00 thru 06.
output sr07_wr,
output cr24_rd,
output cr26_rd,
output c_dec_3ba_or_3da,
output c_cr0c_f13_22_hit
);
reg [7:0] int_io_dbus;
reg [5:0] store_index;
reg rd_or_wr_d;
reg h_iowr_d; // h_iowr is delayed by one h_hclk
wire fcr_rd, fcr_wr; // for generating ready_n
wire ins0_rd, ins1_rd;
wire crt_index_hit;
wire ext_index_hit;
wire crt_reg_hit;
wire crt_index_wr;
wire crt_reg_en;
wire crt_index_rd;
wire rd_or_wr;
wire dec_3bx_or_3dx;
wire cr_reg_hit;
wire crt_io_hit_hb;
wire crt_io_hit_lb;
wire index_from_crtc;
wire addr_sel = misc_b0;
// Instantiating crtc index registers
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n) begin
store_index <= 6'h0;
ext_index <= 8'h0;
end else if (h_iowr) begin
if (crt_index_hit) store_index <= h_io_dbus[5:0];
if (ext_index_hit) ext_index <= {4'b0, h_io_dbus[3:0]};
end
assign crtc_index = {2'b0, store_index};
assign c_ext_index_b[3:0] = ext_index[3:0];
assign c_gr_ext_en = 1'b1;
// We need to delay h_iowr signal by one h_hclk to support 16 bit writing.
// To avoid wr glitches, we first write into index register(lower byte) and
// then with one h_hclk delay, data will be written into the data
// register(upper byte). During one h_hclk delay, the decoder output will
// become stable and clean.
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n) h_iowr_d <= 1'b0;
else h_iowr_d <= h_iowr;
// iowrite pulse for data register writes.
assign trim_wr = h_iowr & h_iowr_d;
assign crt_index_hit = addr_sel ? (h_io_addr == 16'h3d4) :
(h_io_addr == 16'h3b4);
assign crt_reg_hit = addr_sel ? (h_io_addr == 16'h3d5) :
(h_io_addr == 16'h3b5);
assign crt_index_wr = crt_index_hit & h_iowr;
assign crt_index_rd = crt_index_hit & h_iord;
assign crt_reg_en = ( (crt_index_hit & h_io_16) | crt_reg_hit );
assign cr24_rd = (crtc_index == 36) & h_iord;
assign cr26_rd = (crtc_index == 38) & h_iord;
// Decode for Extension registers
assign ext_index_hit = (h_io_addr == 16'h3ce) ;
// Write into extension index register when ext_index_hit is true and h_iowr
// is true.
// The password must be set before any writes can take place to the
// extension data registers.
assign sr_00_06_wr = m_dec_sr00_sr06 & h_iowr;
assign sr07_wr = m_dec_sr07 & h_iowr;
assign dec_3bx_or_3dx = h_dec_3bx | h_dec_3dx;
// Generating crt_io_hit by checking that the address range falls into one
// of the IO register of crt module
assign cr_reg_hit = crt_reg_en
& ( ((crtc_index >= 8'h00) & (crtc_index <= 8'h0b))
| ((crtc_index >= 8'h10) & (crtc_index <= 8'h18) &
(crtc_index != 8'h13)) );
assign crt_io_hit_hb = cr_reg_hit;
// Lower byte bus is enabled for all 16-bit operations and even addressed
// 8-bit operations.
// Whenever there is a read for er30 to er39, cr0c to cr0f, cr13, cr24 , cr26
// and if that is 16-bit operation, index has to come from crtc module.
// crt_index_hit & h_io_8 - 8-bit read to CR index register
// ext_index_hit & h_io_8 - 8-bit read to ER index register
// 3CC: misc rd or write
assign c_dec_3ba_or_3da = addr_sel ? (h_io_addr == 16'h03da) :
(h_io_addr == 16'h03ba);
assign fcr_wr = c_dec_3ba_or_3da & h_iowr;
assign fcr_rd = (h_io_addr == 16'h03ca) & h_iord;
assign ins0_rd = (h_io_addr == 16'h03c2) & h_iord;
assign ins1_rd = c_dec_3ba_or_3da & h_iord;
assign crt_io_hit_lb = (h_io_addr == 16'h3cc & h_iord) |
(h_io_addr == 16'h3c2 & h_iowr) |
ins0_rd | ins1_rd |
fcr_rd | fcr_wr |
(ext_index_hit & (h_io_16 | h_io_8)) |
(crt_index_hit & (h_io_16 | h_io_8));
// delay (h_iowr | h_iord) by one h_hclk and then give it out as c_ready_n
assign rd_or_wr = h_iowr | h_iord;
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n) rd_or_wr_d <= 1'b0;
else rd_or_wr_d <= rd_or_wr;
assign c_ready_n = (~(rd_or_wr_d & (crt_io_hit_hb |
crt_io_hit_lb)));
// Decoding for io hit for any of cr00 to cr0b, cr10 to cr18, misc, ins0,
// ins1 and fcr .
assign crt_mod_rd_en_hb = crt_io_hit_hb & h_iord;
assign crt_mod_rd_en_lb = (crt_io_hit_lb |
(index_from_crtc & h_io_16)) & h_iord;
// Decoding for io hit for any of cr0c to cr0f or cr13
assign c_cr0c_f13_22_hit = crt_reg_en & ( ((crtc_index >= 8'h0c) &
(crtc_index <= 8'h0f))
| (crtc_index == 19)
| (crtc_index == 34));
assign index_from_crtc = c_cr0c_f13_22_hit |
cr24_rd | cr26_rd ;
endmodule
|
#include <bits/stdc++.h> const int INF = 1e6; using namespace std; const int maxn = 1e5 + 5; const int N = 1e6; const int big = 1e9; long long int get(long long int a, long long int b, long long int x, long long int y) { x--; y--; long long int temp = (y * (y - 1) - x * (x - 1)) / 2; return a * (y - x) + b * temp; } int main() { ios::sync_with_stdio(0); cin.tie(0); long long int a, b, n, i, l, m, t; cin >> a >> b >> n; for (i = 0; i < n; i++) { cin >> l >> t >> m; long long int st = l; long long int en = 2e6 + 5; while (en - st > 1) { long long int mid = st + (en - st) / 2; if ((a + (mid - 2) * b) <= t && get(a, b, l, mid) <= m * t) st = mid; else en = mid; } if (st == l) st = 0; cout << st - 1 << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; map<string, int> A; string s; int main() { A[ void ] = 100; A[ errtype ] = 0; int n; cin >> n; for (int i = 0; i < n; ++i) { cin >> s; if (s[4] == d ) { string a, b; cin >> a >> b; int l = a.length(); int p = 0, q = 0; for (int j = 0; j < l; ++j) if (a[j] == & ) ++p; else if (a[j] == * ) ++q; a = a.substr(p, l - p - q); q -= p; if (A[a] + q < 100) A[b] = 0; else A[b] = A[a] + q; } else { string a; cin >> a; int p = 0, q = 0; int l = a.length(); for (int j = 0; j < l; ++j) if (a[j] == & ) ++p; else if (a[j] == * ) ++q; a = a.substr(p, l - p - q); q -= p; if (A[a] + q < 100) puts( errtype ); else { printf( void ); int t = A[a] + q; for (int j = 100; j < t; ++j) printf( * ); puts( ); } } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m, min = 1000; scanf( %d %d , &n, &m); vector<int> v(m); for (int i = 0; i < m; i++) scanf( %d , &v[i]); sort(v.begin(), v.end()); for (int i = 0; n + i - 1 < m; i++) { if (min > v[n + i - 1] - v[i]) min = v[n + i - 1] - v[i]; } printf( %d , min); return 0; } |
#include <bits/stdc++.h> using namespace std; int dp, p[201000], tt[201000], pre[201000], l[201000], vis[201000]; int n, m, i, j, a[1010][1010], g[201000], now[201000], s, t, dis[201000], z[201000], ans; void link(int x, int y, int z) { dp++; pre[dp] = p[x]; p[x] = dp; tt[dp] = y; g[dp] = z; } int dfs(int x) { int i; i = p[x]; while (i) { if (vis[tt[i]] == 0) { vis[tt[i]] = 1; if ((l[tt[i]] == 0) || (dfs(l[tt[i]]))) { l[tt[i]] = x; return 1; } } i = pre[i]; } return 0; } int bfs() { int i, head, tail; memcpy(now, p, sizeof(p)); memset(vis, 0, sizeof(vis)); head = 0; tail = 1; vis[s] = 1; dis[s] = 0; z[tail] = s; do { head++; i = p[z[head]]; while (i) { if ((vis[tt[i]] == 0) && (g[i] > 0)) { vis[tt[i]] = 1; dis[tt[i]] = dis[z[head]] + 1; tail++; z[tail] = tt[i]; } i = pre[i]; } } while (head != tail); return vis[t]; } int dfs(int u, int flow) { int ans, tmp, i; if (u == t) return flow; i = now[u]; ans = 0; while (i) { if ((dis[u] + 1 == dis[tt[i]]) && (g[i] > 0)) { tmp = dfs(tt[i], min(flow - ans, g[i])); ans += tmp; g[i] -= tmp; if (i % 2 == 1) g[i + 1] += tmp; else g[i - 1] += tmp; if (flow == ans) return flow; } i = pre[i]; now[u] = i; } if (flow > ans) dis[u] = 1; return ans; } int main() { cin >> n; for (i = 1; i <= n; i++) { cin >> a[i][0]; for (j = 1; j <= a[i][0]; j++) { cin >> a[i][j]; link(n + i, a[i][j], 0); } } for (i = n + 1; i <= 2 * n; i++) { memset(vis, 0, sizeof(vis)); dfs(i); } dp = 0; memset(p, 0, sizeof(p)); s = 0; t = n + 1; for (i = 1; i <= n; i++) { cin >> m; if (m > 0) { link(s, i, m); link(i, s, 0); } else { ans += m; link(i, t, -m); link(t, i, 0); } } for (i = 1; i <= n; i++) { for (j = 1; j <= a[i][0]; j++) if (l[a[i][j]] - n != i) { link(l[a[i][j]] - n, i, 0x37373737); link(i, l[a[i][j]] - n, 0); } } while (bfs()) ans += dfs(s, 0x37373737); cout << ans; } |
#include <bits/stdc++.h> using namespace std; int x[5], y[5]; int matr[5005][5005]; inline void err() { for (int i = 0; i <= 5000; ++i) for (int j = 0; j <= 5000; ++j) matr[i][j] = -1; } inline void fil(int i, int j, int ii, int jj, int val) { for (int a = i; a <= ii; ++a) for (int b = j; b <= jj; ++b) matr[a][b] = val; } int main() { ios ::sync_with_stdio(false); int a, b, c, d, e, f; cin >> a >> b >> c >> d >> e >> f; int S = a * b + c * d + e * f; int rad = (int)sqrt((double)S); if (rad * rad != S) { cout << -1; exit(0); } x[0] = a; y[0] = b; x[1] = c; y[1] = d; x[2] = e; y[2] = f; int lim = 1 << 3; lim--; for (int i = 0; i <= lim; ++i) { for (int j = 0; j <= 3; ++j) if (i & (1 << j)) swap(x[j], y[j]); err(); for (int masca = 0; masca <= lim; ++masca) { if (__builtin_popcount(masca) < 2) continue; int xx1 = 0; int m = 0; m ^= 1; m ^= 2; m ^= 4; int ymax = 0; int ymin = 1 << 30; int tx = 0; int ty = 0; for (int j = 0; j <= 2; ++j) if (masca & (1 << j)) { xx1 += x[j]; m ^= (1 << j); ymax = max(ymax, y[j]); ymin = min(ymin, y[j]); } else { tx = x[j]; ty = y[j]; } if (ty != ymax - ymin and ty != rad - ymax) continue; if (xx1 == rad) { err(); int lastx = 1; int lasty = 1; for (int j = 0; j <= 3; ++j) if (masca & (1 << j)) { fil(lastx, lasty, lastx + x[j] - 1, lasty + y[j] - 1, j); lastx = lastx + x[j]; lasty = 1; } int muie = -1; while (m) { ++muie; m >>= 1; } cout << rad << n ; for (int i = 1; i <= rad; ++i) { for (int j = 1; j <= rad; ++j) { if (matr[i][j] == -1) matr[i][j] = muie; cout << (char)(matr[i][j] + A ); } cout << n ; } exit(0); } } for (int j = 0; j <= 3; ++j) if (i & (1 << j)) swap(x[j], y[j]); } cout << -1; exit(0); return 0; } |
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2007 www.xilinx.com
//
// XAPP xxx
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : chnlbond.v
//
// Description : Channel Bonding Logic
// TMDS channel de-skew
//
// Author : Bob Feng
//
// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
// provided to you "as is". Xilinx and its licensors makeand you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specificallydisclaims any
// implied warranties of merchantability, non-infringement,or
// fitness for a particular purpose. Xilinx does notwarrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designswill be
// uninterrupted or error free, or that defects in theDesigns
// will be corrected. Furthermore, Xilinx does not warrantor
// make any representations regarding use or the results ofthe
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits,cost
// or procurement of substitute goods or services, or forany
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on anytheory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure ofthe
// essential purpose of any limited remedies herein.
//
// Copyright © 2004 Xilinx, Inc.
// All rights reserved
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1ps
module chnlbond (
input wire clk,
input wire [9:0] rawdata,
input wire iamvld,
input wire other_ch0_vld,
input wire other_ch1_vld,
input wire other_ch0_rdy,
input wire other_ch1_rdy,
output reg iamrdy,
output reg [9:0] sdata
);
parameter CTRLTOKEN0 = 10'b1101010100;
parameter CTRLTOKEN1 = 10'b0010101011;
parameter CTRLTOKEN2 = 10'b0101010100;
parameter CTRLTOKEN3 = 10'b1010101011;
wire rawdata_vld;
assign rawdata_vld = other_ch0_vld & other_ch1_vld & iamvld;
reg [3:0] wa, ra;
reg we;
////////////////////////////////////////////////////////
// FIFO Write Control Logic
////////////////////////////////////////////////////////
always @ (posedge clk) begin
we <=#1 rawdata_vld;
end
always @ (posedge clk) begin
if(rawdata_vld)
wa <=#1 wa + 1'b1;
else
wa <=#1 4'h0;
end
wire [9:0] dpfo_dout;
DRAM16XN #(.data_width(10))
cbfifo_i (
.DATA_IN(rawdata),
.ADDRESS(wa),
.ADDRESS_DP(ra),
.WRITE_EN(we),
.CLK(clk),
.O_DATA_OUT(),
.O_DATA_OUT_DP(dpfo_dout));
always @ (posedge clk) begin
sdata <=#1 dpfo_dout;
end
////////////////////////////////////////////////////////
// FIFO read Control Logic
////////////////////////////////////////////////////////
////////////////////////////////
// Use blank period beginning
// as a speical marker to
// align all channel together
////////////////////////////////
reg rcvd_ctkn, rcvd_ctkn_q; //received control token
reg blnkbgn; //blank period begins
always @ (posedge clk) begin
rcvd_ctkn <=#1 ((sdata == CTRLTOKEN0) || (sdata == CTRLTOKEN1) || (sdata == CTRLTOKEN2) || (sdata == CTRLTOKEN3));
rcvd_ctkn_q <=#1 rcvd_ctkn;
blnkbgn <=#1 !rcvd_ctkn_q & rcvd_ctkn;
end
/////////////////////////////
//skip the current line
/////////////////////////////
wire next_blnkbgn;
reg skip_line;
always @ (posedge clk) begin
if(!rawdata_vld)
skip_line <=#1 1'b0;
else if(blnkbgn)
skip_line <=#1 1'b1;
end
assign next_blnkbgn = skip_line & blnkbgn;
//////////////////////////////
//Declare my own readiness
//////////////////////////////
always @ (posedge clk) begin
if(!rawdata_vld)
iamrdy <=#1 1'b0;
else if(next_blnkbgn)
iamrdy <=#1 1'b1;
end
reg rawdata_vld_q;
reg rawdata_vld_rising;
always @ (posedge clk) begin
rawdata_vld_q <=#1 rawdata_vld;
rawdata_vld_rising <=#1 rawdata_vld & !rawdata_vld_q;
end
//////////////////////////////////////////////////////////////////////////////////////////
// 1. FIFO flow through first when all channels are found valid(phase aligned)
// 2. When the speical marker on my channel is found, the fifo read is hold
// 3. Until the same markers are found across all three channels, the fifo read resumes
//////////////////////////////////////////////////////////////////////////////////////////
reg ra_en = 1'b0;
always @ (posedge clk) begin
if(rawdata_vld_rising || (other_ch0_rdy & other_ch1_rdy & iamrdy))
ra_en <=#1 1'b1;
else if(next_blnkbgn && !(other_ch0_rdy & other_ch1_rdy & iamrdy))
ra_en <=#1 1'b0;
end
/////////////////////////////////////////
//FIFO Read Address Counter
/////////////////////////////////////////
always @ (posedge clk) begin
if(!rawdata_vld)
ra <=#1 4'h0;
else if(ra_en)
ra <=#1 ra + 1'b1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int x, i, p = 0, k = 0; cin >> x; char n[x + 1]; cin >> n; for (i = 0; i < x; i++) { if (n[i] == L ) p++; else k++; } cout << p + k + 1 << endl; } |
/**
\file "channel-ledr-expect-fail.v"
Chain a source and sink in prsim to verilog.
$Id: $
*/
`timescale 1ns/1ps
`include "standard.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
reg l0, l1;
wire r0, r1;
DELAY #(0.01) d0(l0, r0);
DELAY #(0.01) d1(l1, r1);
// prsim stuff
initial
begin
// @haco@ channel-ledr-source-sink.haco-c
$prsim("channel-ledr-source-sink.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("echo-commands on");
$prsim_cmd("mode fatal");
$from_prsim("L.d","TOP.l0");
$from_prsim("L.r","TOP.l1");
$to_prsim("TOP.r0", "R.d");
$to_prsim("TOP.r1", "R.r");
$prsim_cmd("breaks");
$prsim_cmd("watchall");
$prsim_cmd("confirm");
// $prsim_cmd("watchall-queue");
$prsim_cmd("channel-ledr L : :0 d:0 r:0");
$prsim_cmd("channel-ledr R : :0 d:0 r:0");
$prsim_cmd("channel-timing L after 100");
$prsim_cmd("channel-source-args-loop L 0 1 1 0 0 1");
// $prsim_cmd("channel-sink R");
$prsim_cmd("channel-expect-args-loop R 0 1 1 0 0 0");
// $prsim_cmd("channel-expect-args R 0 1 1 0 0 0");
// $prsim_cmd("channel-log R R.dat");
$prsim_cmd("channel-watchall");
$prsim_cmd("channel-ignore-all");
$prsim_cmd("channel-reset-all");
// $prsim_cmd("channel-show-all");
#2
$prsim_cmd("channel-release-all");
$prsim_cmd("channel-heed-all");
// $prsim_cmd("channel-show-all");
#1
$prsim_cmd("channel-show-all");
#2
$finish;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2016.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Base Phase-Locked Loop (PLL)
// /___/ /\ Filename : PLLE4_BASE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 10/22/2014 808642 - Added #1 to $finish
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PLLE4_BASE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer CLKFBOUT_MULT = 5,
parameter real CLKFBOUT_PHASE = 0.000,
parameter real CLKIN_PERIOD = 0.000,
parameter integer CLKOUT0_DIVIDE = 1,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter CLKOUTPHY_MODE = "VCO_2X",
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0,
parameter [0:0] IS_CLKIN_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER = 0.010,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKFBOUT,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUTPHY,
output LOCKED,
input CLKFBIN,
input CLKIN,
input CLKOUTPHYEN,
input PWRDWN,
input RST
);
// define constants
localparam MODULE_NAME = "PLLE4_BASE";
initial begin
#1;
if ($realtime == 0) begin
$display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME);
$display ("The simulator resolution must be set to 1ps or smaller. Instance %m");
#1 $finish;
end
end
wire OPEN_DRDY;
wire OPEN_PSDONE;
wire OPEN_FBS;
wire OPEN_INS;
wire [15:0] OPEN_DO;
PLLE4_ADV #(
.CLKFBOUT_MULT(CLKFBOUT_MULT),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN_PERIOD(CLKIN_PERIOD),
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUTPHY_MODE(CLKOUTPHY_MODE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.IS_CLKFBIN_INVERTED(IS_CLKFBIN_INVERTED),
.IS_CLKIN_INVERTED(IS_CLKIN_INVERTED),
.IS_PWRDWN_INVERTED(IS_PWRDWN_INVERTED),
.IS_RST_INVERTED(IS_RST_INVERTED),
.REF_JITTER(REF_JITTER),
.STARTUP_WAIT(STARTUP_WAIT)
) pll_adv_1 (
.CLKFBOUT (CLKFBOUT),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUTPHY (CLKOUTPHY),
.CLKOUTPHYEN (CLKOUTPHYEN),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.LOCKED (LOCKED),
.CLKFBIN (CLKFBIN),
.CLKIN (CLKIN),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.PWRDWN(PWRDWN),
.RST (RST)
);
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
(posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLKFBIN, 0:0:0, notifier);
$period (negedge CLKFBOUT, 0:0:0, notifier);
$period (negedge CLKIN, 0:0:0, notifier);
$period (negedge CLKOUT0, 0:0:0, notifier);
$period (negedge CLKOUT0B, 0:0:0, notifier);
$period (negedge CLKOUT1, 0:0:0, notifier);
$period (negedge CLKOUT1B, 0:0:0, notifier);
$period (negedge CLKOUTPHY, 0:0:0, notifier);
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge CLKFBOUT, 0:0:0, notifier);
$period (posedge CLKIN, 0:0:0, notifier);
$period (posedge CLKOUT0, 0:0:0, notifier);
$period (posedge CLKOUT0B, 0:0:0, notifier);
$period (posedge CLKOUT1, 0:0:0, notifier);
$period (posedge CLKOUT1B, 0:0:0, notifier);
$period (posedge CLKOUTPHY, 0:0:0, notifier);
$width (negedge CLKIN, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge CLKIN, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; int main() { int t, n, ind; cin >> t; while (t--) { cin >> n; ind = -1; int a[n]; for (int i = 0; i < n; ++i) { cin >> a[i]; if (a[i] % 2 == 0) ind = i; } if (ind != -1) cout << 1 n << ind + 1 << n ; else if (n > 1) cout << 2 n1 2 n ; else cout << -1 n ; } } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_2_V
`define SKY130_FD_SC_LP__A21BO_2_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21bo_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_2_V
|
#include <bits/stdc++.h> using namespace std; ifstream Cin( input.txt ); ofstream Cout( output.txt ); pair<bool, long long> Try(long long A, long long B, long long N) { long long err = 0, C; while (A > 0 && B > 0 && N > 0) { if (A == 1 && B != 1) { C = B - 1; A = B = 1; } else if (A >= B) { C = A / B; A %= B; } else { C = B / A; B %= A; } err += C - 1; N -= C; } return make_pair(N == 0 && A == 0 && B == 1, err); } string get(long long A, long long B, long long N) { string TMP; while (N) { N--; if (A >= B) { A -= B; TMP.push_back( T ); } else { B -= A; TMP.push_back( B ); } } reverse(TMP.begin(), TMP.end()); return TMP; } int main() { long long n, r, i, A, B, ER = (long long)1e15; pair<bool, long long> Cur; cin >> n >> r; for (i = 1; i <= r; i++) { Cur = Try(i, r, n); if (Cur.first) { if (Cur.second < ER) { ER = Cur.second; A = i; B = r; } } Cur = Try(r, i, n); if (Cur.first) { if (Cur.second < ER) { ER = Cur.second; A = r; B = i; } } } if (ER == (long long)1e15) cout << IMPOSSIBLE ; else cout << ER << endl << get(A, B, n); } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); cin.tie(0); int N; cin >> N; int arr[N], grr[100006] = {0}, fre[100005] = {0}, x, ma = 0, ans = 0; for (int i = 0; i < N; i++) { bool ok = false; cin >> x; grr[fre[x]]--; fre[x]++; grr[fre[x]]++; ma = max(ma, fre[x]); if (grr[1] == i + 1) ok = true; else if (grr[i + 1] == 1) ok = true; else if (grr[ma - 1] * (ma - 1) == i + 1 - ma && grr[ma] == 1) ok = true; else if (grr[1] == 1 && grr[ma] * (ma) == i) ok = true; if (ok) ans = i + 1; } cout << ans; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A211O_FUNCTIONAL_PP_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a211o (
VPWR,
VGND,
X ,
A1 ,
A2 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
// Local signals
wire C1 and0_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, C1, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211O_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; long long int n, m; long long int arr[200005]; map<long long int, long long int> x; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cin >> n >> m; for (int i = 0; i < n; ++i) cin >> arr[i]; long long int l = 0, sum = 0, rem = 0, ksum = 0; vector<long long int> ans; while (l < n) { int cnt = 0; rem = 0; sum = ksum; if (sum + arr[l] > m) { auto it = x.rbegin(); while (sum + arr[l] > m && it != x.rend()) { pair<long long int, long long int> curr = *(it); if ((long long int)ceil((sum + arr[l] - m) * 1.0 / curr.first) > curr.second) { rem += curr.second; sum -= (curr.first * curr.second); it++; } else { rem += (long long int)ceil((sum + arr[l] - m) * 1.0 / curr.first); sum -= (curr.first) * ((long long int)ceil((sum + arr[l] - m) * 1.0 / curr.first)); } } } ksum += arr[l]; if (x.find(arr[l]) != x.end()) { pair<long long int, long long int> curr = *(x.find(arr[l])); x.erase(arr[l]); x.insert(make_pair(curr.first, curr.second + 1)); } else x.insert(make_pair(arr[l], 1)); ans.push_back(rem); l++; } for (auto it : ans) cout << it << ; cout << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD1_TB_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD1_TB_V
/**
* clkdlyinv5sd1: Clock Delay Inverter 5-stage 0.15um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv5sd1.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__clkdlyinv5sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD1_TB_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// This has 3 functions:
// Correct the VITA packet length
// [optional] Frame DSP packets with an header line to be handled by the protocol machine
// Hold on to the packet until there is a complete one before allowing to leave
module dsp_framer36
#(parameter BUF_SIZE = 9,
parameter PORT_SEL = 0,
parameter PROT_ENG_FLAGS = 1)
(input clk, input reset, input clear,
input [35:0] data_i, input src_rdy_i, output dst_rdy_o,
output [35:0] data_o, output src_rdy_o, input dst_rdy_i);
wire dfifo_in_dst_rdy, dfifo_in_src_rdy, dfifo_out_dst_rdy, dfifo_out_src_rdy;
wire tfifo_in_dst_rdy, tfifo_in_src_rdy, tfifo_out_dst_rdy, tfifo_out_src_rdy;
wire do_xfer_in = dfifo_in_src_rdy & dfifo_in_dst_rdy;
wire do_xfer_out = src_rdy_o & dst_rdy_i;
wire have_space = dfifo_in_dst_rdy & tfifo_in_dst_rdy;
reg [15:0] pkt_len_in, pkt_len_out;
wire [15:0] tfifo_data;
wire [35:0] dfifo_out_data;
assign dst_rdy_o = have_space;
assign dfifo_in_src_rdy = src_rdy_i & have_space;
fifo_cascade #(.WIDTH(36), .SIZE(BUF_SIZE)) dfifo
(.clk(clk), .reset(reset), .clear(clear),
.datain(data_i), .src_rdy_i(dfifo_in_src_rdy), .dst_rdy_o(dfifo_in_dst_rdy),
.dataout(dfifo_out_data), .src_rdy_o(dfifo_out_src_rdy), .dst_rdy_i(dfifo_out_dst_rdy) );
fifo_short #(.WIDTH(16)) tfifo
(.clk(clk), .reset(reset), .clear(clear),
.datain(pkt_len_in), .src_rdy_i(tfifo_in_src_rdy), .dst_rdy_o(tfifo_in_dst_rdy),
.dataout(tfifo_data), .src_rdy_o(tfifo_out_src_rdy), .dst_rdy_i(tfifo_out_dst_rdy),
.space(), .occupied() );
// FIXME won't handle single-line packets, will show wrong length
always @(posedge clk)
if(reset | clear)
pkt_len_in <= 0;
else if(do_xfer_in)
if(data_i[32]) // sof
pkt_len_in <= 2; // fixes off by one since number is stored before increment
else
pkt_len_in <= pkt_len_in + 1;
assign tfifo_in_src_rdy = do_xfer_in & data_i[33]; // store length when at eof in
assign tfifo_out_dst_rdy = do_xfer_out & data_o[33]; // remove length from list at eof out
always @(posedge clk)
if(reset | clear)
pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1);
else if(do_xfer_out)
if(dfifo_out_data[33]) // eof
pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1);
else
pkt_len_out <= pkt_len_out + 1;
assign dfifo_out_dst_rdy = do_xfer_out & (pkt_len_out != 0);
wire [1:0] port_sel_bits = PORT_SEL;
assign data_o = (pkt_len_out == 0) ? {3'b000, 1'b1, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} :
(pkt_len_out == 1) ? {3'b000, (PROT_ENG_FLAGS ? 1'b0: 1'b1), dfifo_out_data[31:16],tfifo_data} :
{dfifo_out_data[35:33], 1'b0, dfifo_out_data[31:0] };
assign src_rdy_o = dfifo_out_src_rdy & tfifo_out_src_rdy;
endmodule // dsp_framer36
|
#include <bits/stdc++.h> using namespace std; const int m = 31623; int nim[] = { 0, 1, 2, 1, 4, 3, 2, 1, 5, 6, 2, 1, 8, 7, 5, 9, 8, 7, 3, 4, 7, 4, 2, 1, 10, 9, 3, 6, 11, 12, }; bool isLarge[m]; int n; int main(void) { cin >> n; memset(isLarge, true, sizeof(isLarge)); for (int i = 2; i < m; i++) if (isLarge[i]) { for (int j = i * i; j < m; j *= i) isLarge[j] = false; } int ans = 0; int left = n; for (int i = 2; i < min(n + 1, m); i++) { if (isLarge[i]) { int cnt = 0; for (long long j = 1; j <= n; j *= i, cnt++) ; cnt--; ans = ans ^ nim[cnt]; left -= cnt; } } if (left % 2 == 1) ans = ans ^ 1; if (ans) cout << Vasya << endl; else cout << Petya << endl; return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.07.2017 23:51:28
// Design Name:
// Module Name: t_id
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: The purpose of this test is to check if the decoding of
// the instruction works. I wrote 4 blocks to test R-Type, I-Type and J-type
// instructions. The order of these tests are not trivial, I first tested lw
// (I-type) to store 2 values into temporary registers in the register file and
// then I used an add instruction (R-type) and stored the result into a $t2. The
// simulation result of the register file showed $t0 and $t1 had the value 32'h1
// and $t2 had the value 32'h2.
// I then tested the 2 PC related instructions, BEQ (I) and J (J-Type) and made
// sure that the Immediate from the instruction was sign extended for both cases
// and that the immediate was word aligned for the Jump instruction.
// I didn't find it necessary to test the full range of the control unit or the
// register file as this was done previously. Those modules are unchanged and were
// instantaited into the ID module as is.
//
//////////////////////////////////////////////////////////////////////////////////
module t_id;
// Inputs
reg [31:0] pcplus41, instruction, resultw;
reg [4:0] writereg;
reg regwritew, clk;
// Outputs
wire [31:0] read1, read2, immse, pcplus42;
wire [27:0] wainstr;
wire [4:0] rt, rd;
wire [2:0] alucontrol;
wire regwrited, memtoreg, memwrite, branch, alusrc, regdst, jump;
instructiondecode uut(
.clk( clk ),
.read1( read1 ),
.read2( read2 ),
.immediateSE( immse ),
.PCPlus4D2( pcplus42 ),
.WAinstrD( wainstr ),
.rt( rt ),
.rd( rd ),
.ALUControlD( alucontrol ),
.RegWriteD( regwrited ),
.MemToRegD( memtoreg ),
.MemWriteD( memwrite ),
.BranchD( branch ),
.ALUSrcD( alusrc ),
.RegDstD( regdst ),
.JumpD( jump ),
.PCPlus4D1( pcplus41),
.instruction( instruction ),
.ResultW( resultw ),
.WriteRegW( writereg ),
.RegWriteW( regwritew )
);
initial begin
clk = 0;
forever begin
#10 clk = 1;
#10 clk = 0;
end
end
initial begin
// Initialise the inputs
pcplus41 = 0; instruction = 0; resultw = 0;
writereg = 0; regwritew = 0;
// Wait 100ns for global resets to finish
#100;
// Write some test machine code instructions to test an R-type, I-type and J-type instruction and see if the decode works as intended
// I-Type test
// lw rt, offset(rs) - op rs rt imm
#10 instruction = 32'b10001100000010000000000000000001; // store (1+0) into register 8($t0)
writereg = 5'h08; resultw = 32'h00000001; regwritew = 1; // generate my own aluresult, as if the module was connected to the whole circuit
// expected outputs: read1 = 0; immse = 32'b1; rt = 8; rd = 0; regwrited = 1; memtoreg = 1; alusrc = 1; alucontrol = 010;
// reset
#20 instruction = 0;
writereg = 5'h00; resultw = 32'h00000000; regwritew = 0;
// lw rt, offset(rs) - op rs rt imm
#20 instruction = 32'b10001100000010010000000000000001; // store (1+0) into register 9($t1)
writereg = 5'h09; resultw = 32'h00000001; regwritew = 1; // generate my own aluresult, as if the module was connected to the whole circuit
// expected outputs: read1 = 0; immse = 32'b1; rt = 8; rd = 0; regwrited = 1; memtoreg = 1; alusrc = 1; alucontrol = 010; all else 0 or don't care;
// reset
#20 instruction = 0;
writereg = 5'b00; resultw = 32'h00000000; regwritew = 0;
#100; // wait
// R-Type test
// and rd, rs, rt - op rs rt rd shamt funct
instruction = 32'b00000001000010010101000000100000; // $t2 = $t0 + $t1
writereg = 5'h0A; resultw = 32'h00000002; regwritew = 1; // generate my own aluresult, as if the module was connected to the whole circuit
// expected outputs: read1 = 32'h1; read2 = 32'h1; rt = 01001; rd = 01010; regwrited = 1; memtoreg = 1; regdst = 1; alucontrol = 010;
//reset
#20 instruction = 0; // $t2 = $t0 and $t1
writereg = 5'h0; resultw = 32'h00000000; regwritew = 0; // generate my own aluresult, as if the module was connected to the whole circuit
#100; // wait
// BEQ (branch) Test
instruction = 32'b00010001001010000000000000000001; // if $t0 == $t1, nPC = immse + pc+4
// expected outputs: read1 = 32'h1; read2 = 32'h1; immse = 32'b4; branch = 1; alucontrol = 110(sub);
// reset
#20 instruction = 0;
#100; // wait
// J-Type (jump) Test
instruction = 32'b00001000000000000000000000000001; // Jump to instruction in address 32'h00000004;
// expected outputs: WAInstr = 32'h00000004; jump = 1;
#20 instruction = 0;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; set<int> s; for (int i = 0; i < n; i++) { int x; cin >> x; s.insert(x); } set<int>::iterator it = s.begin(); int c = 0; while (it != s.end()) { if (*it == 0) c++; it++; } cout << s.size() - c << endl; } |
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 1; const long long int mod2 = 1e9 + 9; const long long int maxn = 1e6 + 1; const int root = 1e7 + 5; const long long inf = 1e18 + 18; double pie4 = 3.1415926535; long long int visit[maxn], a[maxn]; void die() { cout << INFINITE ; exit(0); } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long int n, i, pos; string s; cin >> n; cin >> s; for (i = 0; i < n; i++) cin >> a[i]; pos = 0; visit[0] = 0; while (1) { if (s[pos] == > ) { pos += a[pos]; if (pos >= n || pos < 0) { cout << FINITE ; return 0; } if (visit[pos]) die(); visit[pos] = 1; } else { pos -= a[pos]; if (pos >= n || pos < 0) { cout << FINITE ; return 0; } if (visit[pos]) die(); visit[pos] = 1; } if (pos >= n || pos < 0) { cout << FINITE ; return 0; } } } |
#include <bits/stdc++.h> #pragma comment(linker, /STACK:16777216 ) using namespace std; int a, b, c, d, i, j, n, m, k, ans; int cs[100001], mas[100001], dp[100001]; inline int sum(int a, int b) { if (!a) return cs[b]; else return cs[b] - cs[a - 1]; } int main() { scanf( %d , &n); for (int _n((n)-1), i(0); i <= _n; i++) { scanf( %d , &mas[i]); if (!i) cs[i] = mas[i]; else cs[i] = cs[i - 1] + mas[i]; } ans = -1000000000 - 1; for (int _n((n)-1), i(0); i <= _n; i++) { if (!i) dp[i] = max(cs[i], -cs[i]); else dp[i] = max(dp[i - 1] + mas[i], max(cs[i], -cs[i])); ans = max(ans, dp[i]); } a = 0; for (int i = (n - 2), _b = (0); i >= _b; i--) { a += mas[i + 1]; ans = max(ans, max(a, -a) + dp[i]); } ans = max(ans, cs[n - 1]); ans = max(ans, -cs[n - 1]); ans = max(ans, dp[n - 1]); printf( %d n , ans); } |
`include "../define.v"
`include "memory.v"
module rom_tb;
reg rst;
reg ce;
reg[`MemDataWidth-1:0] data;
reg[`MemAddrWidth-1:0] addr;
reg we;
reg[`ByteSlctWidth-1:0] byte_slct;
wire[`MemDataWidth-1:0] data_o;
memory #(.MemoryDataNum(32)) test_momory(
.rst(rst),
.ce(ce),
.data_i(data),
.addr_i(addr),
.we(we),
.byte_slct(byte_slct),
.data_o(data_o)
);
reg[5:0] i;
initial begin : memory_test
$dumpfile("test_info/yamin/ram_test.vcd");
$dumpvars;
$readmemh("test_info/yamin/ram.data", test_momory.mem_data);
$display("time\taddr\tinst");
rst = ~`RstEnable;
for (i = 0; i < 32; i = i + 1) begin
#1 ce = `ChipEnable;
addr = i << 2;
#1 $display("%2d\t%d\t%32b", $time, addr, data_o);
ce = ~`ChipEnable;
end
rst = `RstEnable;
#1 $display("==============================================================");
rst = ~`RstEnable;
for (i = 0; i < 32; i = i + 1) begin
#1 ce = `ChipEnable;
addr = i << 2;
#1 $display("%2d\t%d\t%32b", $time, addr, data_o);
ce = ~`ChipEnable;
end
#1 $display("==============================================================");
for (i = 0; i < 32; i = i + 1) begin
addr = i << 2;
data = 32'b11111111111111111111111111111111;
byte_slct = 4'b110;
#1 we = `WriteEnable;
#1 we = ~`WriteEnable;
end
for (i = 0; i < 32; i = i + 1) begin
#1 ce = `ChipEnable;
addr = i << 2;
#1 $display("%2d\t%d\t%32b", $time, addr, data_o);
ce = ~`ChipEnable;
end
#1 $display("==============================================================");
for (i = 0; i < 32; i = i + 1) begin
addr = i << 2;
data = 32'b11111111111111111111111111111111;
byte_slct = 4'b0001;
#1 we = `WriteEnable;
#1 we = ~`WriteEnable;
end
for (i = 0; i < 32; i = i + 1) begin
#1 ce = `ChipEnable;
addr = i << 2;
#1 $display("%2d\t%d\t%32b", $time, addr, data_o);
ce = ~`ChipEnable;
end
$finish;
end
endmodule |
#include <bits/stdc++.h> using namespace std; int n; vector<vector<int>> adj; vector<long long> d; vector<bool> visited; bitset<5000> sol; void dfs(int m) { bitset<5000> tmp; d[m] = 1; tmp[0] = 1; for (auto l : adj[m]) { if (!visited[l]) { visited[l] = 1; dfs(l); d[m] += d[l]; tmp |= (tmp << d[l]); } } tmp |= (tmp << (n - d[m])); sol |= tmp; } int main(int argc, const char* argv[]) { ios::sync_with_stdio(0); cin.tie(0); int a, b; cin >> n; adj = vector<vector<int>>(n + 2); d = vector<long long>(n + 1); visited = vector<bool>(n + 1, false); int p = n; while (--n) { cin >> a >> b; adj[a].push_back(b); adj[b].push_back(a); } n = p; visited[a] = 1; dfs(a); int counter = 0; for (int i = 1; i < n - 1; i++) { if (sol[i]) { counter++; } } cout << counter << n ; for (int i = 1; i < n - 1; i++) { if (sol[i]) { cout << i << << n - i - 1 << n ; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int num; cin >> num; if (num <= 9) { cout << num << endl; } else if (10 < num && num <= 189) { num = num - 9; int tmp = num / 2; tmp = 9 + tmp + num % 2; if (num % 2) cout << tmp / 10 << endl; else cout << tmp % 10 << endl; } else if (190 <= num) { num = num - 189; int tmp = num / 3; if (num % 3 != 0) tmp = 100 + tmp; else tmp = 99 + tmp; if (num % 3 == 0) { cout << tmp % 10 << endl; } else if (num % 3 == 1) { cout << tmp / 100 << endl; } else { tmp = tmp / 10; tmp = tmp % 10; cout << tmp << endl; } } return 0; } |
Require Import HJ.Vars.
Set Arguments Implicit.
(**
A count-down rsem with dynamic registration works exactly like
a reverse semaphore, it includes has three operations:
- an operation to register a task that increments the reverse semaphore;
- an operation to signal, or deregister, a task that decrements the reverse semaphore;
- an operation to wait that checks if the reverse semaphore is zero.
The reason the we call it a "reverse" semaphore is because the blocking condition
is reversed, that is a semaphore blocks while it is zero, whereas a reverse semaphore
blocks until it becomes zero.
We represent a rsem as a set of tasks to be able to bookkeep registered tasks.
*)
Record rsem := mk_rsem {
value : set_tid
}.
(**
We create a rsem without any registered task.
*)
Definition zero := mk_rsem Set_TID.empty.
Section API.
Variable l:rsem.
(**
Registers a task in the rsem. Registered task must
be eventually signaled or deregistered so that
synchronization can happen.
*)
Definition register (t:tid) :=
mk_rsem (Set_TID.add t (value l)).
Definition inc := register.
(**
Signaling a task revokes its registration,
so tasks blocked on [wait] will no longer wait for
the signalling task.
*)
Definition signal (t:tid) :=
mk_rsem (Set_TID.remove t (value l)).
Definition deregister := signal.
Definition dec := signal.
(**
The [wait] operation should block until there are
no registered tasks.
*)
Inductive Wait : Prop :=
wait_def:
Set_TID.Empty (value l) ->
Wait.
(**
Asserts that task [t] is registerd in rsem [l].
*)
Inductive Registered (t:tid) : Prop :=
registered_def:
Set_TID.In t (value l) ->
Registered t.
End API.
Inductive Eq (l1:rsem) (l2:rsem) : Prop :=
eq_def:
Set_TID.eq (value l1) (value l2) ->
Eq l1 l2.
Module Sem.
(** How do we represent that synchronization works? *)
Inductive op :=
| REG
| SIG
| WAIT.
Inductive Redex (l:rsem) (t:tid) : op -> rsem -> Prop :=
| redex_reg:
~ Registered l t ->
Redex l t REG (register l t)
| redex_sig:
Registered l t ->
Redex l t SIG (signal l t)
| redex_wait:
Wait l ->
Redex l t WAIT l.
End Sem.
Module Props.
Import Sem.
Inductive Check (l:rsem) (t:tid) : op -> Prop :=
| check_reg:
~ Wait l ->
~ Registered l t ->
Check l t REG
| check_sig:
Registered l t ->
Check l t SIG
| check_wait:
~ Registered l t ->
Check l t WAIT.
(*
Module Commutativity.
Lemma check_respects_reduce:
forall l l' t t' o o',
Check l t o ->
Redex l t' o' l' ->
t <> t' ->
Check l' t o.
Admitted.
Lemma check_reduces_inv:
forall l t o l',
Redex l t o l' ->
Check l t o.
Admitted.
Lemma commutativity:
forall l1 l2 l2' l3 l3' t1 t2 o1 o2,
t1 <> t2 ->
Redex l1 t1 o1 l2 -> Redex l2 t2 o2 l3 ->
Redex l1 t2 o2 l2' -> Redex l2' t1 o1 l3' ->
Eq l1 l2.
Admitted.
*)
Section Progress.
(**
Progress means that either the rsem is a value, or there
is at least an operation that can be issued.
But how can we enumerate the available operations?
At any time a task may be registered, which means that there is always
*)
Variable l: rsem.
(**
The first thing to show is that there is progress for
unblocked tasks. We define a unblocking predicate that yields [true]
when the operation is unblocking.
*)
Definition blocking (o:op) :=
match o with
| REG => false
| SIG => false
| WAIT => true
end.
Lemma blocking_true:
forall o,
blocking o = true <-> o = WAIT.
Proof.
destruct o; (simpl;
(split; (
intros;
inversion H))); auto.
Qed.
(**
Any unblocked
The proof for this lemma is trivial, by inversion of proposition [Check].
*)
Require Import HJ.Progress.
Lemma progress_unblocked:
forall t o,
Check l t o ->
blocking o = false ->
CanReduce (Redex l) t o.
Proof.
intros.
destruct o.
- inversion H.
subst.
eauto using redex_reg, can_reduce_def.
- inversion H.
subst.
eauto using redex_sig, can_reduce_def.
- inversion H0.
Qed.
Variable r:Map_TID.t op.
Variable reg_in_r : forall t, Registered l t <-> Map_TID.In t r.
Variable r_check:
forall t o, Map_TID.MapsTo t o r -> Check l t o.
Lemma registered_in_reqs:
(forall t o, Map_TID.MapsTo t o r -> blocking o = true) ->
forall t,
Registered l t ->
Map_TID.MapsTo t WAIT r.
Proof.
intros.
apply reg_in_r in H0.
apply Map_TID_Extra.in_to_mapsto in H0.
destruct H0 as (o, Hmt).
assert (o = WAIT). {
apply H in Hmt.
apply blocking_true.
assumption.
}
subst.
assumption.
Qed.
Lemma registered_check_wait:
(forall t o, Map_TID.MapsTo t o r -> blocking o = true) ->
forall t,
Registered l t ->
Check l t WAIT.
Proof.
intros.
auto using registered_in_reqs.
Qed.
Lemma progress_blocked:
~ Map_TID.Empty r ->
(forall t o, Map_TID.MapsTo t o r -> blocking o = true) ->
exists t o,
Map_TID.MapsTo t o r /\
CanReduce (Redex l) t o.
Proof.
intros.
(** Wait is enabled. *)
assert (Hw: Wait l). {
apply wait_def.
unfold Set_TID.Empty.
intros.
destruct (Set_TID_Props.In_dec a (value l)).
- assert (Hreg : Registered l a). { auto using registered_def. }
assert (Check l a WAIT). {
eapply registered_check_wait; auto.
}
inversion H1.
contradiction H2.
- assumption.
}
(** We can pick a task. *)
destruct (Vars.Set_TID_Dep.choose (value l)) as [(t,Hin)|Hempty].
- exists t.
exists WAIT.
split.
+ eauto using registered_def, registered_in_reqs.
+ exists l.
auto using redex_wait.
- apply Map_TID_Extra.nonempty_in in H.
destruct H as (t, Hin).
assert (Hsin : Set_TID.In t (value l)). {
apply reg_in_r in Hin.
inversion Hin.
assumption.
}
unfold Set_TID.Empty in Hempty.
assert (~ Set_TID.In t (value l)). {
apply Hempty.
}
contradiction Hsin.
Qed.
Require HJ.Progress.
Variable reqs_spec :
HJ.Progress.RequestSpec.request_spec r
(Check l)
(Registered l).
Let l_prog:
@HJ.Progress.progress_spec op r (Check l) rsem (Redex l) blocking.
Proof.
intros.
refine (
@HJ.Progress.mk_progress_spec op r (Check l) _
(Redex l) blocking _ _); auto.
- apply progress_unblocked.
- apply progress_blocked.
Defined.
Lemma prog:
~ Map_TID.Empty r ->
(** There is a task that can reduce. *)
exists t o,
Map_TID.MapsTo t o r /\ CanReduce (Redex l) t o.
Proof.
intros.
eauto using HJ.Progress.main_progress, l_prog.
Qed.
End Progress.
End Props.
|
#include <bits/stdc++.h> using namespace std; const int MOD = 1e9 + 7; const int SIZE = 1e6 + 10; int a[SIZE], b[SIZE], c[SIZE], cnt[SIZE]; bool used[SIZE]; vector<int> r[SIZE]; set<int> H; void print_array(vector<int>& arr) { for (int i = 0; i < (((int)(arr).size())); ++i) { if (i) printf( ); printf( %d , arr[i]); } puts( ); } bool check(int r_id) { if (b[r_id] == c[r_id]) { if (a[r_id] == b[r_id]) { return cnt[c[r_id]] < 9; } else { return cnt[c[r_id]] < 8; } } else { if (a[r_id] != b[r_id]) { if (cnt[b[r_id]] == 9) return false; } if (a[r_id] != c[r_id]) { if (cnt[c[r_id]] == 9) return false; } return true; } } int main() { int(n); scanf( %d , &n); for (int i = 0; i < (4 * n); ++i) { scanf( %d%d%d , &(a[i]), &(b[i]), &(c[i])); r[a[i]].push_back(i); r[b[i]].push_back(i); r[c[i]].push_back(i); H.insert(i); } for (int i = 0; i < (n); ++i) cnt[i + 1] = 4; puts( YES ); vector<int> an; while (((int)(H).size())) { int me = *H.begin(); used[me] = 1; H.erase(me); int now[3] = {a[me], b[me], c[me]}; cnt[a[me]]--; cnt[b[me]]++; cnt[c[me]]++; an.push_back(me + 1); for (int k = 0; k < (3); ++k) { int id = now[k]; for (int i = 0; i < (((int)(r[id]).size())); ++i) { int r_id = r[id][i]; if (!used[r_id]) { if (check(r_id)) { H.insert(r_id); } else { if (H.count(r_id)) H.erase(r_id); } } } } } print_array(an); assert(((int)(an).size()) == n * 4); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); ; int n; bool allSame = true; cin >> n; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; if (i > 0 and a[i] != a[i - 1]) allSame = false; } sort(a, a + n); if (n == 1) { cout << -1 ; return 0; } if (allSame) { cout << 1 n << a[0]; return 0; } if (n == 2) { if ((a[0] + a[1]) % 2 != 0) cout << 2 n << a[0] - (a[1] - a[0]) << << a[1] + (a[1] - a[0]); else cout << 3 n << a[0] - (a[1] - a[0]) << << (a[0] + a[1]) / 2 << << a[1] + (a[1] - a[0]); return 0; } if (n == 3) { int d1 = a[1] - a[0], d2 = a[2] - a[1]; if (d1 == d2) { cout << 2 n << a[0] - d1 << << a[2] + d1; return 0; } else if (d1 == 2 * d2) { cout << 1 n << a[0] + d1 / 2; return 0; } else if (2 * d1 == d2) { cout << 1 n << a[1] + d2 / 2; return 0; } } set<int> uniq; multiset<int> freq; for (int i = 1; i < n; i++) { uniq.insert(a[i] - a[i - 1]); freq.insert(a[i] - a[i - 1]); } if (uniq.size() == 1) { cout << 2 n << a[0] - *uniq.begin() << << a[n - 1] + *uniq.begin(); return 0; } else if (uniq.size() == 2) { int d1 = *uniq.begin(); int f1 = freq.erase(d1); uniq.erase(d1); int d2 = *uniq.begin(); int f2 = freq.erase(d2); int d = f1 > f2 ? d1 : d2; if (f1 > 1 and f2 > 1) { cout << 0 ; return 0; } if (d1 == 0 or d2 == 0) { cout << 0 ; return 0; } for (int i = 1; i < n; i++) { if (a[i] - a[i - 1] == 2 * d) { cout << 1 n << a[i - 1] + d; return 0; } } } cout << 0 ; } |
#include <bits/stdc++.h> using namespace std; void solve() { int n, k; cin >> n >> k; priority_queue<pair<int, int> > p; set<int> s; for (int i = 1; i <= n; i++) { int in; cin >> in; p.push({in, i}); s.insert(i + k); } long long ans = 0; vector<int> v(n); while (p.size()) { int c = p.top().first, d = p.top().second; p.pop(); auto it = s.lower_bound(d); ans += 1LL * (*it - d) * c; v[d - 1] = *it; s.erase(it); } cout << ans << n ; for (auto i : v) cout << i << ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); ; solve(); return 0; } |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_clk_edgelogic.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_clk_edgelogic(/*AUTOARG*/
// Outputs
clk_pad_clk_so, to_pad,
// Inputs
clk, clk_pad_clk_si, clk_pad_clk_se, clk_value,
dram_io_clk_enable, testmode_l
);
//////////////////////////////////////////////////////////////////////////
// INPUTS
//////////////////////////////////////////////////////////////////////////
input clk;
input testmode_l;
input clk_pad_clk_si;
input clk_pad_clk_se;
input clk_value;
input dram_io_clk_enable;
//////////////////////////////////////////////////////////////////////////
// OUTPUTS
//////////////////////////////////////////////////////////////////////////
output clk_pad_clk_so;
output to_pad;
//////////////////////////////////////////////////////////////////////////
// CODE
//////////////////////////////////////////////////////////////////////////
// CREATING MUX FOR TEST CLOCK
wire tclk = testmode_l ? ~clk : clk;
// INSTANTIATING PAD LOGIC
dff_s #(1) flop_io_pad_flip_clk(
.din(dram_io_clk_enable),
.q(dram_io_clk_enable_d1),
.clk(tclk),
.si(clk_pad_clk_si), .so(clk_pad_clk_so), .se(clk_pad_clk_se));
wire clk_out = clk_value & dram_io_clk_enable_d1;
wire enable_mux_val = dram_io_clk_enable_d1 ? ~clk_out : clk_out;
assign to_pad = clk ? clk_out : enable_mux_val;
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int rj = 1000000000; int n, m, a, b; scanf( %d %d %d %d , &n, &m, &a, &b); for (int i = 0; i <= n; i++) for (int j = 0; j <= n; j++) { if (i + j * m < n) continue; rj = min(rj, a * i + b * j); } printf( %d n , rj); return 0; } |
#include <bits/stdc++.h> using namespace std; long long mod = (1000000007LL); inline long long mult(long long a, long long b) { return (a * b) % mod; } inline long long poww(long long a, long long b) { long long res = 1; while (b > 0) { if (b & 1) res = (res * a) % mod; a = (a * a) % mod; b >>= 1; } return res; } long long gcd(long long a, long long b) { while (b) { a %= b; swap(a, b); } return a; } int n, m, q, k, v[300050], ans; pair<int, int> w[300050]; string second; int leaf[300050], root, dp[300050], qtd[300050][2]; int ini[300050], yes = 1; vector<int> grafo[300050]; void dfs(int x, int p) { int can = 0; if (leaf[x] and dp[x] == 1) yes = 0; for (auto v : grafo[x]) { if (v == p) continue; if (leaf[v]) can = 1; dp[v] = (dp[x] ^ 1); dfs(v, x); for (int j = 0; j < 2; j++) { if (qtd[x][j] > 0 and qtd[v][j ^ dp[v] ^ 1]) yes = 0; } qtd[x][0] += qtd[v][0]; qtd[x][1] += qtd[v][1]; } if ((can or p == root) and !leaf[x]) ans++; } int32_t main() { ios::sync_with_stdio(false); cin.tie(0); cin >> n; for (int i = 1; i < n; i++) { int a, b; cin >> a >> b; grafo[a].push_back(b); grafo[b].push_back(a); } ans = n - 1; root = 1; for (int i = 1; i <= n; i++) { if ((int)(grafo[i]).size() == 1) leaf[i] = 1, root = i, ans--; } dfs(root, root); cout << (yes ? 1 : 3) << << ans << n ; } |
//
// Copyright (C) 2015-2016 Markus Hiienkari <>
//
// This file is part of Open Source Scan Converter project.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`define STATE_IDLE 2'b00
`define STATE_LEADVERIFY 2'b01
`define STATE_DATARCV 2'b10
module ir_rcv (
input clk27,
input reset_n,
input ir_rx,
output reg [15:0] ir_code,
output reg ir_code_ack,
output reg [7:0] ir_code_cnt
);
// ~37ns clock period
parameter LEADCODE_LO_THOLD = 200000; //7.4ms
parameter LEADCODE_HI_THOLD = 100000; //3.7ms
parameter LEADCODE_HI_TIMEOUT = 160000; //5.9ms
parameter LEADCODE_HI_RPT_THOLD = 54000; //2.0ms
parameter RPT_RELEASE_THOLD = ; //120ms
parameter BIT_ONE_THOLD = 27000; //1.0ms
parameter BIT_DETECT_THOLD = 7628; //0.28ms
parameter IDLE_THOLD = 141480; //5.24ms
reg [1:0] state; // 3 states
reg [31:0] databuf; // temp. buffer
reg [5:0] bits_detected; // max. 63, effectively between 0 and 33
reg [17:0] act_cnt; // max. 9.7ms
reg [17:0] leadvrf_cnt; // max. 9.7ms
reg [17:0] datarcv_cnt; // max. 9.7ms
reg [21:0] rpt_cnt; // max. 155ms
// activity when signal is low
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
act_cnt <= 0;
else
begin
if ((state == `STATE_IDLE) & (~ir_rx))
act_cnt <= act_cnt + 1'b1;
else
act_cnt <= 0;
end
end
// lead code verify counter
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
leadvrf_cnt <= 0;
else
begin
if ((state == `STATE_LEADVERIFY) & ir_rx)
leadvrf_cnt <= leadvrf_cnt + 1'b1;
else
leadvrf_cnt <= 0;
end
end
// '0' and '1' are differentiated by high phase duration preceded by constant length low phase
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
begin
datarcv_cnt <= 0;
bits_detected <= 0;
databuf <= 0;
end
else
begin
if (state == `STATE_DATARCV)
begin
if (ir_rx)
datarcv_cnt <= datarcv_cnt + 1'b1;
else
datarcv_cnt <= 0;
if (datarcv_cnt == BIT_DETECT_THOLD)
bits_detected <= bits_detected + 1'b1;
if (datarcv_cnt == BIT_ONE_THOLD)
databuf[32-bits_detected] <= 1'b1;
end
else
begin
datarcv_cnt <= 0;
bits_detected <= 0;
databuf <= 0;
end
end
end
// read and validate data after 32 bits detected (last bit may change to '1' at any time)
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
begin
ir_code_ack <= 1'b0;
ir_code <= 16'h00000000;
end
else
begin
if ((bits_detected == 32) & (databuf[31:24] == ~databuf[23:16]) & (databuf[15:8] == ~databuf[7:0]))
begin
ir_code <= {databuf[31:24], databuf[15:8]};
ir_code_ack <= 1'b1;
end
else if (rpt_cnt >= RPT_RELEASE_THOLD)
begin
ir_code <= 16'h00000000;
ir_code_ack <= 1'b0;
end
else
ir_code_ack <= 1'b0;
end
end
always @(posedge clk27 or negedge reset_n)
begin
if (!reset_n)
begin
state <= `STATE_IDLE;
rpt_cnt <= 0;
ir_code_cnt <= 0;
end
else
begin
rpt_cnt <= rpt_cnt + 1'b1;
case (state)
`STATE_IDLE:
begin
if ((act_cnt >= LEADCODE_LO_THOLD) & ir_rx)
state <= `STATE_LEADVERIFY;
if (rpt_cnt >= RPT_RELEASE_THOLD)
ir_code_cnt <= 0;
end
`STATE_LEADVERIFY:
begin
if (leadvrf_cnt == LEADCODE_HI_RPT_THOLD)
begin
if (ir_code != 0)
ir_code_cnt <= ir_code_cnt + 1'b1;
rpt_cnt <= 0;
end
if (!ir_rx)
state <= (leadvrf_cnt >= LEADCODE_HI_THOLD) ? `STATE_DATARCV : `STATE_IDLE;
else if (leadvrf_cnt >= LEADCODE_HI_TIMEOUT)
state <= `STATE_IDLE;
end
`STATE_DATARCV:
begin
if (ir_code_ack == 1'b1)
ir_code_cnt <= 1;
if ((datarcv_cnt >= IDLE_THOLD)|bits_detected >= 33)
state <= `STATE_IDLE;
end
default:
state <= `STATE_IDLE;
endcase
end
end
endmodule
|
//`timescale 1 ms /1 us
`include "mux81c.v"
module chap4p32c_tb (S);
// module declaration
output [0:3] S;
reg [0:3] S;
//S[0]=A, S[1]=B, S[2]=C, S[3]=D
wire [0:7] I;
wire Y;
integer fp;
// program body
assign I[0]=~S[3];
assign I[1]=~S[3];
assign I[2]=S[3];
assign I[3]=S[3];
assign I[4]=1'b0;
assign I[5]=S[3];
assign I[6]=1'b0;
assign I[7]=~S[3];
mux81c I1 (I,S[0:2],Y);
initial
begin
fp=$fopen("./chap4p32c_tb.out");
$fmonitor(fp,"time=%0d",$time,,"I=%b S=%b Y=%b",I,S,Y);
#2000
$fclose(fp);
$finish;
end
initial
begin
S=4'b0000;
#100
S=4'b0001;
#100
S=4'b0010;
#100
S=4'b0011;
#100
S=4'b0100;
#100
S=4'b0101;
#100
S=4'b0110;
#100
S=4'b0111;
#100
S=4'b1000;
#100
S=4'b1001;
#100
S=4'b1010;
#100
S=4'b1011;
#100
S=4'b1100;
#100
S=4'b1101;
#100
S=4'b1110;
#100
S=4'b1111;
end
initial #4000 $finish;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 50 + 5; int n, a[N][N], tot; int main() { cin >> n; int i = 0, j = n / 2, x, y; for (int k = 1; k <= n * n; k++) { if (a[i][j]) { i = (x + 1) % n; j = y; } a[i][j] = k; x = i; y = j; i = (i - 1 + n) % n; j = (j + 1) % n; } for (int i = 0; i < n; i++) for (int j = 0; j < n; j++) printf( %d%c , a[i][j], n [j + 1 == n]); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long mod = 1e9 + 7; int n, m, q; int a[1110][810]; char s[1100]; int ni[5] = {0, 1, 3, 2, 4}; long long pow_mod(long long a, long long e) { long long res = 1; for (; e; a = a * a % mod, e >>= 1) if (e & 1) res = res * a % mod; return res; } int frnum; const int BASE = 5; int wr[1100]; void gauss() { for (int i = 1; i <= n; i++) { int flag = 0; for (int j = i; j <= m; j++) if (a[j][i]) { for (int k = 1; k <= n + q; k++) swap(a[j][k], a[i][k]); flag = 1; break; } if (flag == 0) { m++; for (int j = 1; j <= n + q; j++) a[m][j] = a[i][j], a[i][j] = 0; continue; } for (int j = i + 1; j <= n + q; j++) a[i][j] = (a[i][j] * ni[a[i][i]]) % BASE; a[i][i] = 1; for (int j = 1; j <= m; j++) if (a[j][i] && j != i) { for (int k = 1; k <= n + q; k++) if (k != i) a[j][k] = (a[j][k] + 5 - (a[j][i] * a[i][k]) % BASE) % BASE; a[j][i] = 0; } } for (int i = 1; i <= n; i++) if (a[i][i] == 0) frnum++; for (int i = 1; i <= m; i++) { int ff = 0; for (int j = 1; j <= n; j++) if (a[i][j]) ff = 1; if (ff) continue; for (int j = n + 1; j <= n + q; j++) if (a[i][j]) wr[j - n] = 1; } } int main() { scanf( %d %d , &n, &m); for (int i = 1; i <= n; i++) { scanf( %s , s + 1); for (int j = 1; j <= m; j++) a[j][i] = s[j] - a ; } scanf( %d , &q); for (int i = 1; i <= q; i++) { scanf( %s , s + 1); for (int j = 1; j <= m; j++) a[j][i + n] = s[j] - a ; } gauss(); for (int i = 1; i <= q; i++) { if (wr[i]) cout << 0 << endl; else cout << pow_mod(5, frnum) << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = 1000000000000000; int main() { int n, m; cin >> n >> m; vector<int> x(n); for (int i = 0; i < n; i++) { cin >> x[i]; } vector<int> p(m), c(m); for (int i = 0; i < m; i++) { cin >> p[i] >> c[i]; } sort(x.begin(), x.end()); vector<pair<int, int>> P(m); for (int i = 0; i < m; i++) { P[i] = make_pair(p[i], c[i]); } sort(P.begin(), P.end()); for (int i = 0; i < m; i++) { p[i] = P[i].first; c[i] = P[i].second; } int sum = 0; for (int i = 0; i < m; i++) { sum += c[i]; } if (sum < n) { cout << -1 << endl; } else { vector<long long> dp(n + 1, INF); dp[0] = 0; for (int i = 0; i < m; i++) { vector<long long> d(n); for (int j = 0; j < n; j++) { d[j] = abs(x[j] - p[i]); } vector<long long> S(n + 1); S[0] = 0; for (int j = 0; j < n; j++) { S[j + 1] = S[j] + d[j]; } vector<long long> a(n + 1); for (int j = 0; j <= n; j++) { a[j] = dp[j] - S[j]; } deque<int> dq; for (int j = 0; j <= n; j++) { while (!dq.empty()) { if (a[dq.back()] >= a[j]) { dq.pop_back(); } else { break; } } dq.push_back(j); dp[j] = a[dq.front()] + S[j]; if (dq.front() == j - c[i]) { dq.pop_front(); } } } cout << dp[n] << endl; } } |
#include <bits/stdc++.h> using namespace std; int tr[400], ar[400]; vector<pair<int, int> > vv; int main() { int n; cin >> n; for (int i = 0; i < n; i++) cin >> ar[i]; for (int i = 0; i < n; i++) cin >> tr[i]; for (int i = 0; i < n; i++) { if (tr[i] == ar[i]) continue; int j; for (j = i + 1; j < n; j++) if (tr[j] == ar[i]) break; for (j = j - 1; j >= i; j--) { int tmp = tr[j]; tr[j] = tr[j + 1]; tr[j + 1] = tmp; vv.push_back(make_pair(j, j + 1)); } } if (vv.size() >= 1000000) return -1; cout << vv.size() << endl; for (int i = 0; i < vv.size(); i++) { cout << vv[i].first + 1 << << vv[i].second + 1 << endl; } return 0; } |
#include <bits/stdc++.h> constexpr int N = 1.5e5, M = 1 << 18; int n, q; int parent[N], dep[N]; char ch[N]; int down[N], h[N], deg[N]; int mx[N][26], edge[N][26], sum[N]; int e[N][2]; int bad; void add(int u, int c, int v) { u = down[u]; edge[u][c] += v; for (u = parent[u]; u != -1; u = parent[u]) { bad -= sum[u] > h[u]; sum[u] -= mx[u][c]; mx[u][c] = 0; for (int i = 0; i < deg[u]; ++i) mx[u][c] = std::max(mx[u][c], mx[e[u][i]][c] + edge[e[u][i]][c]); sum[u] += mx[u][c]; bad += sum[u] > h[u]; } } int main() { std::ios::sync_with_stdio(false); std::cin.tie(nullptr); std::cin >> n >> q; parent[0] = -1; for (int i = 1; i < n; ++i) { std::cin >> parent[i] >> ch[i]; --parent[i]; e[parent[i]][deg[parent[i]]++] = i; } for (int i = n - 1; i > 0; --i) h[parent[i]] = h[i] + 1; for (int i = 1; i < n; ++i) { if (h[parent[i]] != h[i] + 1) { while (q--) std::cout << Fou n ; return 0; } if (parent[i] != 0 && deg[parent[i]] == 1) parent[i] = parent[parent[i]]; } for (int i = n - 1; i > 0; --i) down[i] = deg[i] == 1 ? down[e[i][0]] : i; for (int i = 0; i < n; ++i) deg[i] = 0; for (int i = 1; i < n; ++i) if (down[i] == i) e[parent[i]][deg[parent[i]]++] = i; for (int i = 1; i < n; ++i) if (ch[i] != ? ) add(i, ch[i] - a , 1); while (q--) { int v; char c; std::cin >> v >> c; --v; if (ch[v] != ? ) add(v, ch[v] - a , -1); if (c != ? ) add(v, c - a , 1); ch[v] = c; if (bad == 0) { int ans = 0; for (int i = 0; i < 26; ++i) ans += (i + 1) * (h[0] - sum[0] + mx[0][i]); std::cout << Shi << ans << n ; } else { std::cout << Fou n ; } } return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:01:29 04/03/2016
// Design Name: Register
// Module Name: C:/Users/Ranolazine/Desktop/lab5_better_io/test_for_reg.v
// Project Name: lab5
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Register
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_reg;
// Inputs
reg clock_in;
reg regWrite;
reg [4:0] readReg1;
reg [4:0] readReg2;
reg [4:0] writeReg;
reg [31:0] writeData;
reg reset;
// Outputs
wire [31:0] readData1;
wire [31:0] readData2;
wire [31:0] reg1;
wire [31:0] reg2;
// Instantiate the Unit Under Test (UUT)
Register uut (
.clock_in(clock_in),
.regWrite(regWrite),
.readReg1(readReg1),
.readReg2(readReg2),
.writeReg(writeReg),
.writeData(writeData),
.reset(reset),
.readData1(readData1),
.readData2(readData2),
.reg1(reg1),
.reg2(reg2)
);
always #15 clock_in = ~clock_in;
initial begin
// Initialize Inputs
clock_in = 0;
regWrite = 0;
readReg1 = 0;
readReg2 = 0;
writeReg = 0;
writeData = 0;
reset = 1;
#40;
reset = 0;
readReg1 = 'b01;
readReg2 = 'b10;
writeReg = 'b01;
writeData = 255;
#30;
regWrite = 1;
writeReg = 'b10;
#30;
writeData = 233;
writeReg = 'b11;
#30;
readReg1 = 'b11;
end
endmodule
|
// EE 471 Lab 4, Beck Pang, Spring 2015
// four 4-word block directly mapped cache with write back method
// Instruction cache, only need to read instruction
// but the cache is a general cache
module dCache (
input clk, // Clock
input rst_n, // Asynchronous reset active low
input WrEn,
input [31:0] dataIn, // Data from memory
input [10:0] adxIn, // Address from ALU
output [31:0] dataOutHigh, // Data write up to register files
);
parameter DATA_WIDTH = 32;
wire [15:0] dataOutLow; // Data write down to memory
wire [10:0] adxBlock; // Block address for moving a 4-word block from the memory to cache
reg [1:0] valid, dirty;
reg [6:0] tag [1:0];
reg [127:0]CACH [1:0];
wire [1:0] index;
wire [6:0] tagIn;
wire [1:0] offset;
wire MemWrEn;
SRAM2Kby16 dataMemory(clk, adxBlock, MemWrEn, dataOutLow);
assign offset= adxIn[1:0] ;
assign index = adxIn[3:2] ; // 7 bit tag, 2 bit index, 2 bit offset
assign tagIn = adxIn[10:4];
// In read operation, WrEn == 1'b0
// If cache hit, return value
// else,
// find the index
// If dirty, dataOutLow write
// Read data from DRAM
// clear the dirty bit to 1'b0
// dataOutReg write
always @(*) begin
if (WrEn == 1'b0) begin
if (tag[index] == tagIn) begin // cache hit
MemWrEn = 1'b1;
dataOutLow = 16'bZ;
end else begin
if(dirty[index]) begin
// Write to Memory
end
// read data from DRAM into the cache
dirty[index] = 1'b0;
end
dataOutHigh = CACH[index][(32 * index + 31) -: 31];
end else begin
dataOutHigh = 32'bZ;
if (tag[index] != tagIn) begin
if(dirty[index]) begin
// Write to Memory
end
// read data from DRAM into the cache
end
CACH[index][(32 * index + 31) -: 31] = dataIn;
dirty[index] = 1'b1;
end
end
// In write operation, WrEn == 1'b1
// If cache not hit,
// find the index
// If dirty, dataOutMem write
// Read data from DRAM
// Always do,
// write the new data into the cache block
// Dirty bit to 1'b1
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017.
// SPDX-License-Identifier: CC0-1.0
interface if1;
integer var1;
endinterface
interface if2;
if1 i1 ();
integer var2;
endinterface
module mod1
(
input clk,
input integer modnum, // Don't use parameter, want same module twice for better checking
if2 foo
);
logic l1, l2;
always_ff @(posedge clk) begin
if (modnum==1) begin
if (foo.i1.var1 != 1) $stop;
if (foo.var2 != 2) $stop;
end
if (modnum==2) begin
if (foo.i1.var1 != 1) $stop;
if (foo.var2 != 2) $stop;
end
end
endmodule
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
if2 i2a ();
if2 i2b ();
assign i2a.i1.var1 = 1;
assign i2a.var2 = 2;
assign i2b.i1.var1 = 3;
assign i2b.var2 = 4;
mod1 mod1a
(
.modnum (1),
.clk (clk),
.foo (i2a)
);
mod1 mod1b
(
.modnum (2),
.clk (clk),
.foo (i2a)
);
integer cyc = 0;
always_ff @(posedge clk) begin
cyc <= cyc+1;
if (cyc==2) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main(void) { int n, i, j = -100, k, *a, cnt = 0, cnt1 = 0; cin >> n; a = new int[n]; for (i = 0; i < n; i++) { cin >> a[i]; } for (i = 0; i < n - 2; i++) { if (a[i] == 1 && a[i + 1] == 0 && a[i + 2] == 1) { if (i - j > 2) { cnt++; j = i; cnt1 = 0; } else { cnt1++; } } } cout << cnt; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); long long n, m, k, t; cin >> n >> m >> k >> t; pair<int, int> mp[k + 1]; long long x, y, a, b; for (int i = 0; i < k; i++) { cin >> mp[i].first >> mp[i].second; } sort(mp, mp + k); for (int i = 0; i < t; i++) { cin >> x >> y; long long idx = m * (x - 1) + y; bool f = true; for (int i = 0; i < k; i++) { if (mp[i].first > x || (mp[i].first == x && mp[i].second > y)) { idx -= (i + 1); break; } if (mp[i].first == x && mp[i].second == y) { f = false; cout << Waste << endl; break; } if (i == k - 1) idx = idx - k - 1; } if (idx % 3 == 0 && f) cout << Carrots << endl; else if (idx % 3 == 1 && f) cout << Kiwis << endl; else if (idx % 3 == 2 && f) cout << Grapes << endl; } } |
#include <bits/stdc++.h> using namespace std; const int N = 5000010; vector<long long> v[N]; int a[N]; long long com2(long long n) { return n * (n - 1) / 2; } int main() { long long n, m; cin >> n >> m; for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); if (a[i] >= m) { printf( 0 n ); return 0; } } for (int i = 1; i <= n; i++) if (a[i]) { for (int j = i; j <= n; j++) v[0].push_back(a[j]); break; } if (v[0].size() == 2) { long long lt = 1, rt = m / v[0][0] + 1, mid; long long ans = 0; while (lt <= rt) { mid = (lt + rt) >> 1; if (1LL * mid * v[0][0] + v[0][1] >= m) ans = mid, rt = mid - 1; else lt = mid + 1; } cout << ans << endl; } else if (v[0].size() == 3) { long long lt = 1, rt = 2000000000, mid; long long ans = 0; while (lt <= rt) { mid = (lt + rt) >> 1; long long p = com2(mid + 1); if (m / v[0][0] < p) { ans = mid, rt = mid - 1; continue; } p = p * v[0][0] + mid * v[0][1] + v[0][2]; if (p >= m) { ans = mid, rt = mid - 1; } else lt = mid + 1; } cout << ans << endl; } else { for (int i = 1; i < N; i++) { long long sum = 0; for (int j = 0; j < v[i - 1].size(); j++) { sum += v[i - 1][j]; v[i].push_back(sum); if (sum >= m) { printf( %d n , i); return 0; } } } } return 0; } |
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
parameter REQ_ACK_START = 2'b00;
parameter REQ_ACK_WAIT = 2'b01;
parameter REQ_ACK_ERR = 2'b10;
parameter REQ_ACK_DEASSERT = 2'b11;
reg [1:0] r_state;
reg [1:0] r_r_state;
reg r_req;
reg r_ack;
integer i;
integer j;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_req;
wire valid_ack;
assign valid_req = ~( req ^ req );
assign valid_ack = ~( ack ^ ack );
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=REQ_ACK_START;
r_r_state=REQ_ACK_START;
r_req=0;
r_ack=0;
i = 0;
j = 0;
end
`endif
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
case (r_state)
REQ_ACK_START:
begin
if ((max_ack_length != 0) && ack == 1'b1 && r_ack == 1'b1)
begin
j <= j+1;
if (j >= max_ack_length)
begin
r_state <= REQ_ACK_ERR;
ovl_error_t(`OVL_FIRE_2STATE,"Duration of continuous asserted state of acknowledge violates specified maximum ack_max_length cycles");
end
end
else if ((max_ack_length != 0) && ack == 1'b0 )
begin
j <= 0;
end
else if ((max_ack_length != 0) && ack == 1'b1 && r_ack == 1'b0)
begin
j <= 1;
end
if (req == 1'b1) begin
if (r_ack == 1'b1 && ack == 1'b1 && r_req == 1'b0) begin
r_state <= REQ_ACK_ERR;
ovl_error_t(`OVL_FIRE_2STATE,"New request arrives before previous request is acknowledged");
end
else if (deassert_count != 0 && r_req == 1'b1 && req == 1'b1 &&
r_ack == 1'b1) begin
if (deassert_count == 1'b1) begin
r_state <= REQ_ACK_ERR;
ovl_error_t(`OVL_FIRE_2STATE,"Duration of continuous asserted state of request violates specified deassert_count cycles");
end
else begin
r_state <= REQ_ACK_DEASSERT;
i <= deassert_count-1;
end
end
else if (ack == 1'b1 && r_ack == 1'b0 && r_req == 1'b1)
begin
r_state <= REQ_ACK_ERR;
ovl_error_t(`OVL_FIRE_2STATE,"Acknowledge arrives without a pending request");
end
else if ((min_ack_cycle != 0) && ack && r_ack == 1'b0)
begin
r_state <= REQ_ACK_ERR;
ovl_error_t(`OVL_FIRE_2STATE,"Acknowledge asserted before elapse of specified minimum min_ack_cycle cycles from request");
end
else if (ack == 1'b0 && r_req === 1'b0) begin
r_state <= REQ_ACK_WAIT;
i <= 1;
j <= 0;
end
end
else begin
if (ack == 1'b1 && r_ack == 1'b0) begin
r_state <= REQ_ACK_ERR;
ovl_error_t(`OVL_FIRE_2STATE,"Acknowledge arrives without a pending request");
end
end
end
REQ_ACK_WAIT:
begin
i <= i + 1;
if (ack) begin
r_state <= REQ_ACK_START;
j <= 1;
end
if ((min_ack_cycle != 0) && (i < min_ack_cycle) &&
ack == 1'b1) begin
r_state <= REQ_ACK_ERR;
ovl_error_t(`OVL_FIRE_2STATE,"Acknowledge asserted before elapse of specified minimum min_ack_cycle cycles from request");
end
else if ((!ack) && (max_ack_cycle != 0) && i >= max_ack_cycle) begin
r_state <= REQ_ACK_ERR;
ovl_error_t(`OVL_FIRE_2STATE,"Acknowledge is not asserted within specified maximum max_ack_cycle cycles from request");
end
else if (req_drop == 1'b1 && req == 1'b0) begin
r_state <= REQ_ACK_ERR;
ovl_error_t(`OVL_FIRE_2STATE,"Request is deasserted before acknowledgement arrives");
end
else if (req == 1'b1 && r_req == 1'b0) begin
r_state <= REQ_ACK_ERR;
ovl_error_t(`OVL_FIRE_2STATE,"New request arrives before previous request is acknowledged");
end
end
REQ_ACK_ERR:
begin
if (req == 1'b1 && ack == 1'b0 && r_req == 1'b0) begin
r_state <= REQ_ACK_WAIT;
i <= 1;
j <= 0;
end
else if (req == 1'b1 && r_req == 1'b0 && ack == 1'b1 && r_ack == 1'b0)
begin
if (min_ack_cycle != 0)
begin
ovl_error_t(`OVL_FIRE_2STATE,"Acknowledge asserted before elapse of specified minimum min_ack_cycle cycles from request");
end
else
begin
r_state <= REQ_ACK_START;
i <= 1;
j <= 1;
end
end
else if (ack == 1'b0) begin
r_state <= REQ_ACK_START;
i <= 0;
j <= 0;
end
end
REQ_ACK_DEASSERT:
begin
i <= i-1;
if( req == 1'b0 )
begin
r_state <= REQ_ACK_START;
i <= 0;
end
else if((req == 1'b1) && (i == 1))
begin
r_state <= REQ_ACK_ERR;
ovl_error_t(`OVL_FIRE_2STATE,"Duration of continuous asserted state of request violates specified deassert_count cycles");
end
if ((max_ack_length != 0) && ack == 1'b1 && r_ack == 1'b1)
begin
j <= j+1;
if (j >= max_ack_length)
begin
r_state <= REQ_ACK_ERR;
ovl_error_t(`OVL_FIRE_2STATE,"Duration of continuous asserted state of acknowledge violates specified maximum ack_max_length cycles");
end
end
else if ((max_ack_length != 0) && ack == 1'b0 )
begin
j <= 0;
end
else if ((max_ack_length != 0) && ack == 1'b1 && r_ack == 1'b0)
begin
r_state <= REQ_ACK_ERR;
ovl_error_t(`OVL_FIRE_2STATE,"Acknowledge arrives without a pending request");
end
end
endcase
r_r_state <= r_state;
r_ack <= ack;
r_req <= req;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
if ( valid_req == 1'b1 )
begin
//Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"req contains X or Z");
end
if ( valid_ack == 1'b1 )
begin
//Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"ack contains X or Z");
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
end
else begin
r_state <= REQ_ACK_START;
r_r_state <= REQ_ACK_START;
r_ack <= 0;
r_req <= 0;
i <= 0;
j <= 0;
end
end // always
`endif // OVL_ASSERT_ON
`ifdef OVL_COVER_ON
reg prev_req, prev_ack;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
prev_req <= req;
prev_ack <= ack;
if (prev_req != req && prev_req == 1'b0) begin
ovl_cover_t("req_asserted covered");
end
if (prev_ack != ack && prev_ack == 1'b0) begin
ovl_cover_t("ack_asserted covered");
end
end //basic coverage
end // OVL_COVER_NONE
end
else begin
`ifdef OVL_INIT_REG
prev_req <= 0;
prev_ack <= 0;
`endif
end
end //always
`endif // OVL_COVER_ON
|
#include <bits/stdc++.h> using namespace std; int main() { int n, x = 0; cin >> n; while (n > 0) { if (n >= 100) { x += n / 100; n %= 100; } else if (n >= 20 && n < 100) { x += n / 20; n %= 20; } else if (n >= 10 && n < 50) { x += n / 10; n %= 10; } else if (n >= 5 && n < 10) { x += n / 5; n %= 5; } else { x += n; n = 0; } } cout << x; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_SYMBOL_V
`define SKY130_FD_SC_LP__CLKBUF_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkbuf (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_SYMBOL_V
|
#include <bits/stdc++.h> using namespace std; long long fa[2005], fb[2005]; long long mina[2005], minb[2005]; signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n, m; cin >> n >> m; vector<long long> a(n), b(m); for (int i = 0; i < n; i++) { cin >> a[i]; fa[i + 1] = fa[i] + a[i]; } for (int j = 0; j < m; j++) { cin >> b[j]; fb[j + 1] = fb[j] + b[j]; } long long x; cin >> x; for (int i = 0; i <= n; i++) { mina[i] = 2000000000; for (int k = 0; k + i <= n; k++) { mina[i] = min(mina[i], fa[k + i] - fa[k]); } } for (int j = 0; j <= m; j++) { minb[j] = 2000000000; for (int k = 0; k + j <= m; k++) { minb[j] = min(minb[j], fb[k + j] - fb[k]); } } long long ans = 0; for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { if (mina[i] * minb[j] <= x) ans = max(ans, i * 1ll * j); } } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int a[101][4]; int main() { int n; cin >> n; int min = 0, ind = 0; for (int i = 0; i < n; i++) cin >> a[i][0] >> a[i][1] >> a[i][2] >> a[i][3]; min = 100000; ind = 0; for (int i = 0; i < n; i++) { bool ust = false; for (int j = 0; j < n; j++) if (i != j) if (a[i][0] < a[j][0] && a[i][1] < a[j][1] && a[i][2] < a[j][2]) { ust = true; break; } if (!ust) if (a[i][3] < min) { min = a[i][3]; ind = i; } } cout << ind + 1 << endl; return 0; } |
// $Id: c_err_rpt.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// error reporting module
//==============================================================================
module c_err_rpt
(clk, reset, active, errors_in, errors_out);
`include "c_constants.v"
// number of error inputs
parameter num_errors = 1;
// select mode of operation
parameter capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
input active;
// raw error inputs
input [0:num_errors-1] errors_in;
// registered and potentially held error outputs
output [0:num_errors-1] errors_out;
wire [0:num_errors-1] errors_out;
generate
if(capture_mode != `ERROR_CAPTURE_MODE_NONE)
begin
wire [0:num_errors-1] errors_s, errors_q;
case(capture_mode)
`ERROR_CAPTURE_MODE_NO_HOLD:
begin
assign errors_s = errors_in;
end
`ERROR_CAPTURE_MODE_HOLD_FIRST:
begin
assign errors_s = ~|errors_q ? errors_in : errors_q;
end
`ERROR_CAPTURE_MODE_HOLD_ALL:
begin
assign errors_s = errors_q | errors_in;
end
endcase
c_dff
#(.width(num_errors),
.reset_type(reset_type))
errorsq
(.clk(clk),
.reset(reset),
.active(active),
.d(errors_s),
.q(errors_q));
assign errors_out = errors_q;
end
else
assign errors_out = {num_errors{1'b0}};
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; const int OO = 0x3f3f3f3f, N = 1e2 + 5, mod = 1e9 + 7; int ans, lst = OO, gt[26]; string s1, s2; vector<int> idx[26]; int main() { cin >> s1 >> s2; for (int i = 0; i < s1.size(); ++i) idx[s1[i] - a ].push_back(i); for (int i = 0; i < s2.size(); ++i) { int ch = s2[i] - a ; if (!idx[ch].size()) exit(puts( -1 )); if (idx[ch].back() > lst && idx[ch][gt[ch]] <= lst) gt[ch] = lower_bound(idx[ch].begin(), idx[ch].end(), lst) - idx[ch].begin(); if (idx[ch].size() <= gt[ch] || idx[ch].back() <= lst) { ++ans, memset(gt, 0, sizeof gt); gt[ch] = 1, lst = idx[ch][0]; } else lst = (idx[ch][gt[ch]++]); } cout << ans; return 0; } |
#include <bits/stdc++.h> int main() { int n, p, q, p1[150], q1[150], pq[300], i, j, k, l, m; scanf( %d , &n); scanf( %d , &p); for (i = 0; i < p; i++) { scanf( %d , &p1[i]); } scanf( %d , &q); for (j = 0; j < q; j++) { scanf( %d , &q1[j]); } if ((p == 0) && (q == 0)) { printf( Oh, my keyboard! n ); return 0; } else { for (k = 0; k < (p + q); k++) { if (k < p) { pq[k] = p1[k]; } else { pq[k] = q1[k - p]; } } for (l = 1; l <= n; l++) { for (m = 0; m < p + q; m++) { if (pq[m] == l) { break; } else if (m == (p + q - 1)) { printf( Oh, my keyboard! n ); return 0; } } } printf( I become the guy. n ); } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode; initial _mode = 0;
// verilator lint_off LITENDIAN
reg [7:0] mem_narrow [0:31]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
reg [77:0] mem_wide [1024:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
reg [7:0] mem_dly_narrow [0:1]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
reg [77:0] mem_dly_wide [1:0]; //surefire lint_off_line RD_WRT WRTWRT NBAJAM
reg [34:0] vec_wide;
// verilator lint_on LITENDIAN
reg [31:0] wrd0 [15:0];
wire [3:0] sel = 4'h3;
wire [31:0] selout = wrd0[sel];
// Must take LSBs into account in bit extract widths.
wire [15:14] sixt = 2'b10; // surefire lint_off_line ASWCBB
wire [16:14] sixt2 = 3'b110; // surefire lint_off_line ASWCBB
wire [3:0] sixfrom = 13;
wire [4:0] sixfrom2 = 16;
wire sixtext = sixt[sixfrom];
wire sixtext2 = sixt2[sixfrom2];
// Non-power of 2 memory overwriting checks
reg [2:0] np2_mem [5:0] /*verilator public*/;
reg [2:0] np2_guard [7:6] /*verilator public*/;
integer i;
always @ (posedge clk) begin
if (_mode!=0) begin
wrd0[0] = 32'h1;
//
for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR
mem_narrow[i] = i[7:0];
mem_wide[i] = {i[7:0],70'hfeed};
end
//
for (i=0; i<32; i=i+1) begin //surefire lint_off_line STMFOR
if (mem_narrow[i] !== i[7:0]) $stop;
if (mem_wide[i] !== {i[7:0],70'hfeed}) $stop;
end
//
vec_wide <= 0;
//
np2_guard[6] = 0;
np2_guard[7] = 0;
//
$write("selout %b %b %b\n", selout, sixtext, sixtext2);
end
if (_mode == 1) begin
_mode <= 2;
//
i=0;
mem_dly_narrow[0] <= ~i[7:0];
mem_dly_wide[0] <= {~i[7:0],70'hface};
i=1;
mem_dly_narrow[i] <= ~i[7:0];
mem_dly_wide[i] <= {~i[7:0],70'hface};
//
for (i=0; i<16; i=i+1) begin //surefire lint_off_line STMFOR
// verilator lint_off width
np2_mem[i] = i[2:0]; // surefire lint_off_line ASWSBB
// verilator lint_on width
if (np2_guard[6]!=0 || np2_guard[7]!=0) $stop;
end
// lint_checking BNDMEM OFF
if (np2_mem[6] !== np2_mem[7]) begin
$write("Mem[6]!=Mem[7] during randomize...\n");
//$stop; // Random value, so this can happen
end
//if (np2_mem[8] !== np2_mem[9]) $stop; // Enhancement: Illegal indexes, make sure map to X's
//
vec_wide[32:31] <= 2'b11;
vec_wide[34] <= 1'b1;
$display("%x",vec_wide);
end
if (_mode == 2) begin
_mode <= 3;
//
for (i=0; i<2; i=i+1) begin //surefire lint_off_line STMFOR
if (mem_dly_narrow[i] !== ~i[7:0]) $stop;
if (mem_dly_wide[i] !== {~i[7:0],70'hface}) $stop;
end
//
//$write ("VW %x %x\n", vec_wide[34:32], vec_wide[31:0]);
if (vec_wide != {4'b101_1,31'd0}) $stop;
//
$write("*-* All Finished *-*\n");
$finish;
end
_mode <= _mode + 1;
end
endmodule
|
// ghrd_10as066n2_ocm_0.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_ocm_0 (
input wire clk, // clk1.clk
input wire reset, // reset1.reset
input wire reset_req, // .reset_req
input wire [17:0] address, // s1.address
input wire clken, // .clken
input wire chipselect, // .chipselect
input wire write, // .write
output wire [7:0] readdata, // .readdata
input wire [7:0] writedata // .writedata
);
ghrd_10as066n2_ocm_0_altera_avalon_onchip_memory2_171_ehvj5ii ocm_0 (
.clk (clk), // input, width = 1, clk1.clk
.address (address), // input, width = 18, s1.address
.clken (clken), // input, width = 1, .clken
.chipselect (chipselect), // input, width = 1, .chipselect
.write (write), // input, width = 1, .write
.readdata (readdata), // output, width = 8, .readdata
.writedata (writedata), // input, width = 8, .writedata
.reset (reset), // input, width = 1, reset1.reset
.reset_req (reset_req), // input, width = 1, .reset_req
.freeze (1'b0) // (terminated),
);
endmodule
|
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