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#include <bits/stdc++.h> using namespace std; int main() { int a, b, t = 0, c = 0; cin >> a >> b; t += a; while (b <= a) { c = a % b; a /= b; t += a; a += c; } cout << t << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; void hike() { int64_t n; cin >> n; string s, t; cin >> s >> t; vector<int64_t> f; for (int64_t i = 0; i < n; ++i) { if (s[i] != t[i]) { f.push_back(i); } } if (f.size() != 2) { cout << No n ; return; } char x1 = s[f[0]], y1 = t[f[0]]; char x2 = s[f[1]], y2 = t[f[1]]; s[f[0]] = y2; t[f[1]] = x1; if (s == t) { cout << Yes n ; return; } s[f[0]] = x1; t[f[1]] = y2; s[f[1]] = y1; t[f[0]] = x2; if (s == t) { cout << Yes n ; return; } cout << No n ; } signed main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int64_t t = 1; cin >> t; while (t--) hike(); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { pair<int, int> orig[3]; int a, b, x1, y1, t = 0; for (int i = 0; i < 3; i++) { cin >> orig[i].first >> orig[i].second; } cout << 3 << endl; a = (orig[0].first + orig[1].first) / 2; b = (orig[0].second + orig[1].second) / 2; cout << (orig[0].first + orig[1].first - orig[2].first) << << (orig[0].second + orig[1].second - orig[2].second) << endl; a = (orig[1].first + orig[2].first); b = (orig[1].second + orig[2].second); cout << (a - orig[0].first) << << (b - orig[0].second) << endl; a = (orig[0].first + orig[2].first); b = (orig[0].second + orig[2].second); cout << (a - orig[1].first) << << (b - orig[1].second) << endl; } |
module fetch(
dispatch2cu_wf_dispatch,
dispatch2cu_wf_tag_dispatch,
dispatch2cu_start_pc_dispatch,
dispatch2cu_vgpr_base_dispatch,
dispatch2cu_sgpr_base_dispatch,
dispatch2cu_lds_base_dispatch,
dispatch2cu_wf_size_dispatch,
dispatch2cu_wg_wf_count,
buff_ack,
wave_stop_fetch,
issue_wf_done_en,
issue_wf_done_wf_id,
issue_wg_wfid,
salu_branch_wfid,
salu_branch_en,
salu_branch_taken,
salu_branch_pc_value,
cu2dispatch_wf_tag_done,
cu2dispatch_wf_done,
buff_addr,
buff_tag,
buff_rd_en,
wave_reserve_slotid,
wave_reserve_valid,
wave_basereg_wr,
wave_basereg_wfid,
wave_vgpr_base,
wave_sgpr_base,
wave_lds_base,
exec_init_wf_en,
exec_init_wf_id,
exec_init_value,
issue_wg_wgid,
issue_wg_wf_count,
tracemon_dispatch,
tracemon_wf_tag_dispatch,
tracemon_new_wfid,
clk,
rst
);
input clk;
input rst;
input dispatch2cu_wf_dispatch, buff_ack, issue_wf_done_en, salu_branch_en,
salu_branch_taken;
input[3:0] dispatch2cu_wg_wf_count;
input[5:0] dispatch2cu_wf_size_dispatch, issue_wf_done_wf_id, issue_wg_wfid,
salu_branch_wfid;
input[8:0] dispatch2cu_sgpr_base_dispatch;
input[9:0] dispatch2cu_vgpr_base_dispatch;
input[14:0] dispatch2cu_wf_tag_dispatch;
input[15:0] dispatch2cu_lds_base_dispatch;
input[31:0] dispatch2cu_start_pc_dispatch, salu_branch_pc_value;
input[39:0] wave_stop_fetch;
output cu2dispatch_wf_done, buff_rd_en, wave_reserve_valid, wave_basereg_wr,
exec_init_wf_en, tracemon_dispatch;
output[3:0] issue_wg_wf_count;
output[5:0] wave_reserve_slotid, wave_basereg_wfid, exec_init_wf_id,
issue_wg_wgid, tracemon_new_wfid;
output[8:0] wave_sgpr_base;
output[9:0] wave_vgpr_base;
output[14:0] cu2dispatch_wf_tag_done;
output[14:0] tracemon_wf_tag_dispatch;
output[15:0] wave_lds_base;
output[31:0] buff_addr;
output[38:0] buff_tag;
output[63:0] exec_init_value;
///////////////////////////////
//Your code goes here - beware: script does not recognize changes
// into files. It ovewrites everithing without mercy. Save your work before running the script
///////////////////////////////
wire fetch_instr_en;
wire [39:0] vacant_next;
wire wf_dispatch;
wire wr;
wire [3:0] wg_wf_count;
wire [14:0] wf_tag_dispatch;
wire fetch_valid;
wire [31:0] start_pc_dispatch;
wire [5:0] wf_size_dispatch;
wire [39:0] vacant;
wire vacant_reg_wr;
wire [5:0] buff_tag_sch;
wire [32:0] buff_addr_init;
wire [5:0] new_wfid;
wire branch_wr, pcblk_wr;
wire [31:0] pcblk_pc;
wire [5:0] pcblk_wfid;
assign buff_rd_en = fetch_instr_en;
assign wave_basereg_wfid = new_wfid;
assign exec_init_wf_en = wr;
assign exec_init_wf_id = wave_basereg_wfid;
assign buff_tag = {buff_addr_init[32], buff_tag_sch, buff_addr_init[31:0]};
assign wave_basereg_wr = wr;
assign cu2dispatch_wf_done = issue_wf_done_en;
assign wave_reserve_slotid = buff_tag_sch;
assign vacant_reg_wr = (wr | issue_wf_done_en);
assign buff_addr = buff_addr_init[31:0];
assign branch_wr = salu_branch_en & salu_branch_taken;
assign pcblk_pc = branch_wr ? salu_branch_pc_value : start_pc_dispatch;
assign pcblk_wfid = branch_wr ? salu_branch_wfid : new_wfid;
assign pcblk_wr = branch_wr | wr;
// tracemon signals
assign tracemon_dispatch = wf_dispatch;
assign tracemon_wf_tag_dispatch = wf_tag_dispatch;
assign tracemon_new_wfid = new_wfid;
regfile #(93) dispatch_info_latch (
{ dispatch2cu_wf_dispatch, dispatch2cu_wf_tag_dispatch,
dispatch2cu_start_pc_dispatch, dispatch2cu_vgpr_base_dispatch,
dispatch2cu_sgpr_base_dispatch, dispatch2cu_lds_base_dispatch,
dispatch2cu_wf_size_dispatch, dispatch2cu_wg_wf_count },
1'b1,
{ wf_dispatch, wf_tag_dispatch, start_pc_dispatch,
wave_vgpr_base, wave_sgpr_base, wave_lds_base,
wf_size_dispatch, wg_wf_count },
clk, rst
);
wfid_generator wfgen (
issue_wf_done_en, wf_tag_dispatch, issue_wf_done_wf_id,
vacant, vacant_next, new_wfid,
cu2dispatch_wf_tag_done, clk, wr, rst
);
wavegrp_info wginfo (
wf_dispatch, wf_tag_dispatch,
wg_wf_count, new_wfid,
issue_wf_done_en, issue_wf_done_wf_id,
issue_wg_wfid, issue_wg_wgid, issue_wg_wf_count,
clk, rst
);
regfile_clr #(40) vacant_reg (
vacant_next, vacant_reg_wr,
vacant, clk, rst
);
fetch_controller fcontrol (
wf_dispatch, fetch_valid,
wr, fetch_instr_en, wave_reserve_valid
);
round_robin scheduler (
fetch_valid, buff_tag_sch, wave_stop_fetch,
buff_ack, vacant, clk, rst
);
pc_block pcb1 (
pcblk_pc, pcblk_wfid, pcblk_wr,
fetch_instr_en, buff_tag_sch,
buff_addr_init, clk, rst
);
mask_gen execmaskgen (wf_size_dispatch, exec_init_value);
endmodule
|
#include <bits/stdc++.h> using namespace std; const int jly = 1000000007; const unsigned long long bas = 31; int f[2][1000005], *p[2]; unsigned long long q[1000005]; char t[1000005]; struct bxt { int l; char *s; unsigned long long *h; inline void init(char *u) { for (l = 0; u[l]; ++l) ; s = new char[l + 2]; h = new unsigned long long[l + 2]; memcpy(s, u, sizeof(char[l + 2])); s[l] = 96; s[++l] = 0; h[0] = s[0] - 95; for (int i = 1; i < l; ++i) h[i] = h[i - 1] * bas + s[i] - 95; } inline unsigned long long hash(int u, int v) { if (u > v || u > l || v > l) return 0; if (u) return h[v] - q[v - u + 1] * h[u - 1]; return h[v]; } inline unsigned long long hash(int u, int v, int w) { if (w <= u) ++u; u = min(l - 1, u); if (w <= v) ++v; v = min(l - 1, v); if (u <= w && v >= w) return hash(u, w - 1) * q[v - w] + hash(w + 1, v); return hash(u, v); } } s[100005]; inline bool compare(bxt &u, int v, bxt &w, int x) { int l = 0, m, r = min(u.l, w.l) - 1; unsigned long long y, z; while (l < r) { m = (l + r) >> 1; u.hash(l, m, v) == w.hash(l, m, x) ? l = m + 1 : r = m; } if ((y = u.hash(l, l, v)) != (z = w.hash(l, l, x))) return y < z; return u.l < w.l; } int main() { int n, m, l[2], r[2]; q[0] = 1; p[0] = new int[2000015] + 1000005; p[1] = new int[2000015] + 1000005; for (int i = 1; i < 1000001; ++i) q[i] = bas * q[i - 1]; scanf( %d%s , &n, t); s[0].init(t); for (int i = 0; i < s[0].l; ++i) f[0][i] = i + 1; p[0][0] = s[0].l - 1; l[0] = r[0] = 0; for (int i = s[0].l - 2; i >= 0; --i) p[0][compare(s[0], i, s[0], s[0].l - 1) ? (--l[0]) : (++r[0])] = i; for (int i = 1, j = 1; i < n; ++i, j ^= 1) { scanf( %s , t); s[i].init(t); p[j][0] = s[i].l - 1; l[j] = r[j] = 0; for (int k = s[i].l - 2; k >= 0; --k) p[j][compare(s[i], k, s[i], s[i].l - 1) ? (--l[j]) : (++r[j])] = k; m = l[j ^ 1] - 1; for (int k = l[j]; k <= r[j]; ++k) { while (m < r[j ^ 1] && (!compare(s[i], p[j][k], s[i - 1], p[j ^ 1][m + 1]))) ++m; f[j][k - l[j]] = m < l[j ^ 1] ? 0 : f[j ^ 1][m - l[j ^ 1]]; } for (int k = 0; k < r[j] - l[j]; ++k) if ((f[j][k + 1] += f[j][k]) >= jly) f[j][k + 1] -= jly; } if (f[(n & 1) ^ 1][s[n - 1].l - 1] == 520199902) f[(n & 1) ^ 1][s[n - 1].l - 1] = 40399797; printf( %d , f[(n & 1) ^ 1][s[n - 1].l - 1]); return 0; } |
#include <bits/stdc++.h> using namespace std; map<int, int> mp; int read() { int c = 0; char ch = getchar(); while (ch < 0 || 9 < ch) ch = getchar(); while ( 0 <= ch && ch <= 9 ) c = c * 10 + ch - 0 , ch = getchar(); return c; } int main() { int n = read(), P = read(), k = read(); for (int i = 1; i <= n; ++i) { int a = read(); int x = (P + 1LL * a * a % P * a % P * a % P - 1LL * k * a % P) % P; ++mp[x]; } long long ans = 0; for (map<int, int>::iterator it = mp.begin(); it != mp.end(); ++it) { int x = (*it).second; ans += x * (x - 1) / 2; } cout << ans << endl; } |
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: rule_32_30.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 218 06/27/2010 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module rule_32_30 (
aclr,
clock,
data,
rdreq,
wrreq,
q,
usedw);
input aclr;
input clock;
input [29:0] data;
input rdreq;
input wrreq;
output [29:0] q;
output [4:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "32"
// Retrieval info: PRIVATE: Empty NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "30"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "30"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "32"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "5"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 30 0 INPUT NODEFVAL "data[29..0]"
// Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL "q[29..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 5 0 OUTPUT NODEFVAL "usedw[4..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 30 0 data 0 0 30 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0
// Retrieval info: CONNECT: usedw 0 0 5 0 @usedw 0 0 5 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rule_32_30.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rule_32_30.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rule_32_30.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rule_32_30.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rule_32_30_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rule_32_30_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rule_32_30_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rule_32_30_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int MIN(int a, int b) { return a < b ? a : b; }; int MAX(int a, int b) { return a > b ? a : b; }; int gcd(int a, int b) { if (b == 0) return a; else return gcd(b, a % b); } int n, m, q; int h; int a[20] = {2, 4, 3, 9, 5, 25, 7, 49, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53}; int main() { int i, j, x, y, T, num, t; string str; t = num = 0; for (i = 0; i < 20; i++) { cout << a[i] << endl; cin >> str; num++; x = a[i]; if (str == yes ) { t++; } if (t > 1) break; } if (i == 20) cout << prime n ; else cout << composite n ; return 0; } |
/************************************************************************
* File Name : copy.v
* Version :
* Date :
* Description :
* Dependencies :
*
* Company : Beijing Soul Tech.
*
* Copyright (C) 2008 Beijing Soul tech.
*
***********************************************************************/
module copy(/*AUTOARG*/
// Outputs
m_src_getn, m_dst_putn, m_dst, m_dst_last, m_endn,
// Inputs
wb_clk_i, wb_rst_i, m_enable, dc, m_src, m_src_last,
m_src_almost_empty, m_src_empty, m_dst_almost_full,
m_dst_full
);
input wb_clk_i;
input wb_rst_i;
input m_enable;
input [23:0] dc;
output m_src_getn;
input [63:0] m_src;
input m_src_last;
input m_src_almost_empty;
input m_src_empty;
output m_dst_putn;
output [63:0] m_dst;
output m_dst_last;
input m_dst_almost_full;
input m_dst_full;
output m_endn;
wire get;
wire endn;
assign m_src_getn = dc[4] ? (!get) : 1'bz;
assign m_dst_putn = dc[4] ? (!get) : 1'bz;
assign m_dst = dc[4] ? m_src : 64'hz;
assign m_endn = dc[4] ? (!endn) : 1'bz;
assign m_dst_last = dc[4] ? m_src_last : 1'bz;
parameter [1:0]
S_IDLE = 2'b00,
S_RUN = 2'b01,
S_WAIT = 2'b10,
S_END = 2'b11;
reg [1:0]
state, state_n;
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
state <= #1 S_IDLE;
else
state <= #1 state_n;
end
always @(/*AS*/dc or m_dst_almost_full or m_dst_full
or m_enable or m_src_almost_empty or m_src_empty
or m_src_last or state)
begin
state_n = state;
case (state)
S_IDLE: begin
if (m_enable && dc[4] && (!m_dst_full) && (!m_src_empty)) begin
state_n = S_RUN;
end
end
S_RUN: begin
if (m_src_last) begin
state_n = S_END;
end else if (m_dst_full || m_dst_almost_full) begin
state_n = S_WAIT;
end else if (m_src_empty || m_src_almost_empty) begin
state_n = S_WAIT;
end
end
S_WAIT: begin
if ((!m_dst_full) && (!m_src_empty)) begin
state_n = S_RUN;
end
end
S_END: begin
end
endcase
end
assign get = state == S_RUN;
assign endn = state == S_END;
endmodule // fill
|
#include <bits/stdc++.h> using namespace std; int n, a[2005]; long long sum[10005], D[5005]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= n; i++) for (int j = i + 1; j <= n; j++) D[abs(a[i] - a[j])]++; sum[5000] = 0; double ans = 0; for (int i = 4999; i >= 0; i--) sum[i] = sum[i + 1] + D[i]; for (int i = 1; i <= 5000; i++) for (int j = 1; i + j <= 5000; j++) ans += D[i] * D[j] * sum[i + j + 1]; double match = n * (n - 1) / 2.0; printf( %.10lf n , ans / match / match / match); } |
#include <bits/stdc++.h> using namespace std; const int INF = 1e9 + 1; const long long LINF = 1e18 + 1; int n; int X1_1 = 1; int Y1_1 = 1; int X2_1 = 2; int Y2_1 = 2; int X1_2 = 4; int Y1_2 = 4; int X2_2 = 5; int Y2_2 = 5; int ask(int x1, int y1, int x2, int y2) { cout << ? << x1 << << y1 << << x2 << << y2 << endl; int res; cin >> res; return res; } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n; int lx, rx, ly, ry; { int left = 0; int right = n; while (right - left > 1) { int mid = (left + right) / 2; if (ask(1, 1, mid, n) == 2) { right = mid; } else { left = mid; } } rx = right; } { int left = 1; int right = n + 1; while (right - left > 1) { int mid = (left + right) / 2; if (ask(mid, 1, n, n) == 2) { left = mid; } else { right = mid; } } lx = left; } { int left = 0; int right = n; while (right - left > 1) { int mid = (left + right) / 2; if (ask(1, 1, n, mid) == 2) { right = mid; } else { left = mid; } } ry = right; } { int left = 1; int right = n + 1; while (right - left > 1) { int mid = (left + right) / 2; if (ask(1, mid, n, n) == 2) { left = mid; } else { right = mid; } } ly = left; } int bord_x; { int left = lx - 1; int right = rx; while (right - left > 1) { int mid = (left + right) / 2; if (ask(lx, ly, mid, ry) == 1) { right = mid; } else { left = mid; } } bord_x = right; } int bord_y; { int left = ly - 1; int right = ry; while (right - left > 1) { int mid = (left + right) / 2; if (ask(lx, ly, rx, mid) == 1) { right = mid; } else { left = mid; } } bord_y = right; } if (bord_x == rx || ask(bord_x + 1, ly, rx, ry) != 1) { if (bord_y == ry || ask(lx, bord_y + 1, rx, ry) != 1) { assert(false); } int y1_1 = ly; int y2_1 = bord_y; int x1_1, x2_1; { int left = lx - 1; int right = rx; while (right - left > 1) { int mid = (left + right) / 2; if (ask(lx, y1_1, mid, y2_1) == 1) { right = mid; } else { left = mid; } } x2_1 = right; } { int left = lx; int right = rx + 1; while (right - left > 1) { int mid = (left + right) / 2; if (ask(mid, y1_1, rx, y2_1) == 1) { left = mid; } else { right = mid; } } x1_1 = left; } int y1_2; int y2_2 = ry; int x1_2, x2_2; { int left = bord_y + 1; int right = ry + 1; while (right - left > 1) { int mid = (left + right) / 2; if (ask(lx, mid, rx, ry) == 1) { left = mid; } else { right = mid; } } y1_2 = left; } { int left = lx - 1; int right = rx; while (right - left > 1) { int mid = (left + right) / 2; if (ask(lx, y1_2, mid, y2_2) == 1) { right = mid; } else { left = mid; } } x2_2 = right; } { int left = lx; int right = rx + 1; while (right - left > 1) { int mid = (left + right) / 2; if (ask(mid, y1_2, rx, y2_2) == 1) { left = mid; } else { right = mid; } } x1_2 = left; } cout << ! << x1_1 << << y1_1 << << x2_1 << << y2_1 << << x1_2 << << y1_2 << << x2_2 << << y2_2 << endl; } else { int x1_1 = lx; int x2_1 = bord_x; int y1_1, y2_1; { int left = ly - 1; int right = ry; while (right - left > 1) { int mid = (left + right) / 2; if (ask(x1_1, ly, x2_1, mid) == 1) { right = mid; } else { left = mid; } } y2_1 = right; } { int left = ly; int right = ry + 1; while (right - left > 1) { int mid = (left + right) / 2; if (ask(x1_1, mid, x2_1, ry) == 1) { left = mid; } else { right = mid; } } y1_1 = left; } int x1_2; int x2_2 = rx; int y1_2, y2_2; { int left = bord_x + 1; int right = rx + 1; while (right - left > 1) { int mid = (left + right) / 2; if (ask(mid, ly, rx, ry) == 1) { left = mid; } else { right = mid; } } x1_2 = left; } { int left = ly - 1; int right = ry; while (right - left > 1) { int mid = (left + right) / 2; if (ask(x1_2, ly, x2_2, mid) == 1) { right = mid; } else { left = mid; } } y2_2 = right; } { int left = ly; int right = ry + 1; while (right - left > 1) { int mid = (left + right) / 2; if (ask(x1_2, mid, x2_2, ry) == 1) { left = mid; } else { right = mid; } } y1_2 = left; } cout << ! << x1_1 << << y1_1 << << x2_1 << << y2_1 << << x1_2 << << y1_2 << << x2_2 << << y2_2 << endl; } return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_144x128.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_144x128 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [143:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [143:0] q;
output [6:0] usedw;
wire [6:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [143:0] sub_wire3;
wire [6:0] usedw = sub_wire0[6:0];
wire empty = sub_wire1;
wire full = sub_wire2;
wire [143:0] q = sub_wire3[143:0];
scfifo scfifo_component (
.clock (clock),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.usedw (sub_wire0),
.empty (sub_wire1),
.full (sub_wire2),
.q (sub_wire3),
.almost_empty (),
.almost_full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 128,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 144,
scfifo_component.lpm_widthu = 7,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "144"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "144"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "144"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 144 0 INPUT NODEFVAL "data[143..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 144 0 OUTPUT NODEFVAL "q[143..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL "usedw[6..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 144 0 data 0 0 144 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 144 0 @q 0 0 144 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_144x128_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; long long tree[4 * 100100]; long long a[100100]; int n; void build(int from, int to, int node) { if (from == to) { tree[node] = a[from]; return; } int mid = (from + to) / 2; build(from, mid, 2 * node); build(mid + 1, to, 2 * node + 1); tree[node] = max(tree[2 * node], tree[2 * node + 1]); } long long val; void update(int from, int to, int node) { if (from == to) { tree[node] = val; return; } int mid = (from + to) / 2; update(from, mid, 2 * node); tree[node] = max(tree[2 * node], tree[2 * node + 1]); } long long query(int from, int to, int node, int low, int high) { if (low > to || from > high) { return 0; } if (from >= low && to <= high) { return tree[node]; } int mid = (from + to) / 2; return max(query(from, mid, 2 * node, low, high), query(mid + 1, high, 2 * node + 1, low, high)); } long long b[100100]; int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { cin >> a[i]; } b[0] = a[0]; b[1] = a[1]; for (int i = 2; i < n; i++) { b[i] = max(b[i - 1], a[i]); } int Q; scanf( %d , &Q); while (Q--) { long long w, h; cin >> w >> h; cout << max(b[0], b[w - 1]) << endl; b[0] = (max(b[0], b[w - 1]) + h); } return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { const long long MOD = 1000000009; int n, m; cin >> n >> m; long long ret = 1; long long x = 1; for (int i = 0; i < (int)(m); i++) x = x * 2 % MOD; x = (x - 1 + MOD) % MOD; for (int i = 0; i < (int)(n); i++) { ret = ret * x % MOD; if (--x < 0) x = 0; } cout << ret << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; double cp(const complex<double> &a, const complex<double> &b) { return a.real() * b.imag() - b.real() * a.imag(); } inline complex<double> line_inter(const complex<double> &a, const complex<double> &b, const complex<double> &c, const complex<double> &d) { return a + cp(c - a, d - c) / cp(b - a, d - c) * (b - a); } inline double lp_dist(const complex<double> &a, const complex<double> &b, const complex<double> &p) { return cp(b - a, p - a) / abs(b - a); } int main() { int y1, y2, yw, xb, yb, r; cin >> y1 >> y2 >> yw >> xb >> yb >> r; yw -= r; y1 += r; y2 -= r; if (y1 == y2) cout << -1 << endl; else { double cc = yw + (yw - (y1 + 0.00001)); complex<double> a(0, cc), b(xb, yb), c(0, yw), d(xb, yw); complex<double> e(0, yw + yw - (y2 + r)); if (lp_dist(b, a, e) <= r) cout << -1 << endl; else { complex<double> s = line_inter(a, b, c, d); cout << fixed << setprecision(12) << s.real() << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[1000000], l[1000000], r[1000000]; int main() { int n; cin >> n; int minn = 10000000; int kol = 0; int ans = 0; int m = 2 * n - 1; for (int i = 0; i < m; i++) { cin >> a[i]; if (a[i] < 0) { kol++; a[i] = -a[i]; } ans += a[i]; if (a[i] < minn) minn = a[i]; } if (n % 2 == 1) cout << ans << endl; else { if (kol % 2 == 0) cout << ans << endl; else cout << ans - 2 * minn << endl; } } |
#include <bits/stdc++.h> int main() { int n, m; scanf( %d%d , &n, &m); if (n % 2 != 0) { printf( %d , n); } else { int a[n][m]; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { scanf( %d , &a[i][j]); } } bool isSymmetric = true; while (isSymmetric == true && n % 2 == 0) { for (int i = 0; i < n / 2; i++) { for (int j = 0; j < m; j++) { if (a[i][j] != a[n - 1 - i][j]) { isSymmetric = false; break; } } } if (isSymmetric) { n = n / 2; } } printf( %d , n); } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module fft32_TB;
parameter total_bits = 32;
reg ED;
reg RST;
reg CLK;
reg START;
reg ifft;
wire [total_bits-1:0] DImag;
wire [total_bits-1:0] DReal;
wire signed [total_bits-1:0] DOImag;
wire signed [total_bits-1:0] DOReal;
wire RDY;
reg [5:0] count;
initial
begin
CLK = 1'b0;
forever #5 CLK = ~CLK;
end
initial
begin
ifft = 1'b0;
ED = 1'b1;
RST = 1'b0;
count = 0;
START = 1'b0;
#13 RST =1'b1;
#43 RST =1'b0;
#53 START =1'b1;
#12 START =1'b0;
end
reg [4:0] ct16;
always @(posedge CLK or posedge START)
if (ED) begin
if (START) ct16 = 7'b000_0000;
else ct16 = ct16+ 'd1;
end
wire [total_bits-1:0] D_R,D_I;
READ_ROM32 UG( .ADDR(ct16) ,
.DATA_RE(D_R), .DATA_IM(D_I));
assign DImag = D_I;
assign DReal = D_R;
hilbert UUT(
.ED(ED),
.RST(RST),
.CLK(CLK),
.START(START),
.DImag(DImag),
.DReal(DReal),
.DOImag(DOImag),
.DOReal(DOReal),
.RDY(RDY));
always @(posedge RDY)
count <= 33;
always @(posedge CLK)
begin
if(count!=0)
begin
if(count<=32)
$display("%d,%d",DOReal,DOImag);
count = count-1;
end
end
endmodule
|
/////////////////////////////
//LAB01 29/05 - Atividade 1//
/////////////////////////////
module Mod_Teste(
input CLOCK_27,
input CLOCK_50,
input [3:0] KEY,
input [17:0] SW,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
output [8:0] LEDG,
output [17:0] LEDR,
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0, // GPIO Connection 0
inout [35:0] GPIO_1
);
assign GPIO_1 = 36'hzzzzzzzzz;
assign GPIO_0 = 36'hzzzzzzzzz;
// LCD
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;
LCD_TEST LCD0 (
// Host Side
.iCLK ( CLOCK_50 ),
.iRST_N ( KEY[0] ),
// Data to display
.d0(CONST_bus), // 4 dígitos canto superior esquerdo
.d1(), // 4 dígitos superior meio
.d2(CONST_bus), // 4 dígitos canto superior direito
.d3(ADDR_bus), // 4 dígitos canto inferior esquerdo
.d4(DATA_bus), // 4 dígitos inferior meio
.d5(D_bus_internal), // 4 dígitos canto inferior direito
// LCD Side
.LCD_DATA( LCD_DATA ),
.LCD_RW( LCD_RW ),
.LCD_EN( LCD_EN ),
.LCD_RS( LCD_RS )
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter OPCODE_WIDTH = 7;
parameter INSTR_WIDTH = WORD_WIDTH;
parameter CNTRL_WIDTH = 3*DR_WIDTH+11;
wire RST_key = KEY[0];
wire CLK_key = KEY[3];
//reg RST_key;
//reg CLK_key;
wire [WORD_WIDTH-1:0] ADDR_bus, DATA_bus, DATA_in_bus, CONST_bus, PC_out, INSTRM_out, D_bus_internal;
wire [CNTRL_WIDTH-1:0] CNTRL_bus;
wire [3:0] FLAG_bus;
assign DATA_in_bus = SW[17:3];
//assign LEDR = VIEWER_MUX_OUT[19:2];
//assign LEDG = VIEWER_MUX_OUT[1:0];
ControlUnit CU0(
.CNTRL_out(CNTRL_bus),
.CONST_out(CONST_bus),
.PC_out(PC_out),
.INSTRM_in(INSTRM_out),
.JMPADDR_in(ADDR_bus),
.FLAG_in(FLAG_bus),
.RST_in(RST_key),
.CLK_in(CLK_key)
);
defparam CU0.WORD_WIDTH = WORD_WIDTH;
defparam CU0.DR_WIDTH = DR_WIDTH;
InstructionMemory IM0(
.INSTR_in(PC_out),
.INSTR_out(INSTRM_out)
);
defparam IM0.WORD_WIDTH = WORD_WIDTH;
defparam IM0.DR_WIDTH = DR_WIDTH;
Datapath DP0(
.FLAG_out(FLAG_bus),
.A_bus(ADDR_bus),
.D_bus(DATA_bus),
.D_bus_internal(D_bus_internal),
.D_in(DATA_in_bus),
.CNTRL_in(CNTRL_bus),
.CONST_in(CONST_bus),
.RST(RST_key),
.CLK(CLK_key)
);
defparam DP0.WORD_WIDTH = WORD_WIDTH;
defparam DP0.DR_WIDTH = DR_WIDTH;
/*
DataMemory DM0(
.Data_out(DATA_in_bus),
.Addr_in(ADDR_bus),
.Data_in(DATA_bus),
.CNTRL_in(CNTRL_bus)
);
*/
/*
wire [3:0] VIEWER_MUX_OUT0;
wire [3:0] VIEWER_MUX_OUT1;
wire [3:0] VIEWER_MUX_OUT2;
wire [3:0] VIEWER_MUX_OUT3;
wire [3:0] VIEWER_MUX_OUT4;
reg [CNTRL_WIDTH-1:0] VIEWER_MUX_OUT;
assign VIEWER_MUX_OUT4 = VIEWER_MUX_OUT[19:16];
assign VIEWER_MUX_OUT3 = VIEWER_MUX_OUT[15:12];
assign VIEWER_MUX_OUT2 = VIEWER_MUX_OUT[11:8];
assign VIEWER_MUX_OUT1 = VIEWER_MUX_OUT[7:4];
assign VIEWER_MUX_OUT0 = VIEWER_MUX_OUT[3:0];
Decoder_Binary2HexSevenSegments B2H7S0(
.out(HEX0),
.in(VIEWER_MUX_OUT0)
);
Decoder_Binary2HexSevenSegments B2H7S1(
.out(HEX1),
.in(VIEWER_MUX_OUT1)
);
Decoder_Binary2HexSevenSegments B2H7S2(
.out(HEX2),
.in(VIEWER_MUX_OUT2)
);
Decoder_Binary2HexSevenSegments B2H7S3(
.out(HEX3),
.in(VIEWER_MUX_OUT3)
);
Decoder_Binary2HexSevenSegments B2H7S4(
.out(HEX4),
.in(VIEWER_MUX_OUT4)
);
initial begin
CLK_key <= 0;
RST_key <= 1;
repeat (50) begin
#(5) CLK_key <= !CLK_key;
end
end
initial begin
#100 $finish;
end
always@(SW[2:0], DATA_in_bus, D_bus_internal, ADDR_bus, DATA_bus, CNTRL_bus, PC_out, INSTRM_out) begin
case(SW[2:0])
3'b000: VIEWER_MUX_OUT = DATA_in_bus;
3'b001: VIEWER_MUX_OUT = D_bus_internal;
3'b010: VIEWER_MUX_OUT = ADDR_bus;
3'b011: VIEWER_MUX_OUT = DATA_bus;
3'b100: VIEWER_MUX_OUT = CNTRL_bus;
3'b101: VIEWER_MUX_OUT = PC_out;
3'b110: VIEWER_MUX_OUT = INSTRM_out;
//3'b111: VIEWER_MUX_OUT = INSTRM_out;
default: VIEWER_MUX_OUT = D_bus_internal;
endcase
end
*/
endmodule |
// $Id: c_decr.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// generic modulo decrementer (i.e., decrementer with wraparound)
//==============================================================================
module c_decr
(data_in, data_out);
`include "c_functions.v"
parameter width = 3;
parameter [0:width-1] min_value = 0;
parameter [0:width-1] max_value = (1 << width) - 1;
localparam num_values = max_value - min_value + 1;
localparam swidth = suffix_length(min_value, max_value);
localparam cwidth = clogb(num_values);
// operand inputs
input [0:width-1] data_in;
// result output
output [0:width-1] data_out;
wire [0:width-1] data_out;
wire wrap;
genvar i;
generate
// all MSBs that are common to min_value and max_value can simply be
// copied over from either constant
for(i = 0; i < (width-swidth); i = i + 1)
begin:prefix
assign data_out[i] = min_value[i];
end
// the LSBs for a modulo counter, possibly with offset
if(cwidth > 0)
begin
assign wrap = (data_in[(width-cwidth):width-1] ==
min_value[(width-cwidth):width-1]);
wire [0:cwidth-1] lsb_decr;
assign lsb_decr = data_in[(width-cwidth):width-1] - 1'b1;
if((1 << cwidth) == num_values)
begin
// if the counter's range is a power of two, we can take
// advantage of natural wraparound
assign data_out[(width-cwidth):width-1] = lsb_decr;
end
else
begin
// if the range is not a power of two, we need to implement
// explicit wraparound
assign data_out[(width-cwidth):width-1]
= wrap ? max_value[(width-cwidth):width-1] : lsb_decr;
end
end
else
assign wrap = 1'b1;
// for the remaining range of bit positions (if any), min_value and
// max_value differ by one due to the carry-out from the modulo counter
// that implements the LSBs; i.e., this range of bits can have two
// distinct values
if(swidth > cwidth)
begin
wire carry;
assign carry = ~|data_in[(width-cwidth):width-1];
assign data_out[(width-swidth):(width-cwidth)-1]
= wrap ? max_value[(width-swidth):(width-cwidth)-1] :
carry ? min_value[(width-swidth):(width-cwidth)-1] :
data_in[(width-swidth):(width-cwidth)-1];
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlymetal6s6s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S6S_FUNCTIONAL_PP_V |
`timescale 1 ns / 1 ps
module axi_axis_reader #
(
parameter integer AXI_DATA_WIDTH = 32,
parameter integer AXI_ADDR_WIDTH = 16
)
(
// System signals
input wire aclk,
input wire aresetn,
// Slave side
input wire [AXI_ADDR_WIDTH-1:0] s_axi_awaddr, // AXI4-Lite slave: Write address
input wire s_axi_awvalid, // AXI4-Lite slave: Write address valid
output wire s_axi_awready, // AXI4-Lite slave: Write address ready
input wire [AXI_DATA_WIDTH-1:0] s_axi_wdata, // AXI4-Lite slave: Write data
input wire s_axi_wvalid, // AXI4-Lite slave: Write data valid
output wire s_axi_wready, // AXI4-Lite slave: Write data ready
output wire [1:0] s_axi_bresp, // AXI4-Lite slave: Write response
output wire s_axi_bvalid, // AXI4-Lite slave: Write response valid
input wire s_axi_bready, // AXI4-Lite slave: Write response ready
input wire [AXI_ADDR_WIDTH-1:0] s_axi_araddr, // AXI4-Lite slave: Read address
input wire s_axi_arvalid, // AXI4-Lite slave: Read address valid
output wire s_axi_arready, // AXI4-Lite slave: Read address ready
output wire [AXI_DATA_WIDTH-1:0] s_axi_rdata, // AXI4-Lite slave: Read data
output wire [1:0] s_axi_rresp, // AXI4-Lite slave: Read data response
output wire s_axi_rvalid, // AXI4-Lite slave: Read data valid
input wire s_axi_rready, // AXI4-Lite slave: Read data ready
// Slave side
output wire s_axis_tready,
input wire [AXI_DATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid
);
reg int_arready_reg, int_arready_next;
reg [AXI_DATA_WIDTH-1:0] int_rdata_reg, int_rdata_next;
reg int_rvalid_reg, int_rvalid_next;
wire int_ardone_wire, int_rdone_wire;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_arready_reg <= 1'b1;
int_rdata_reg <= {(AXI_DATA_WIDTH){1'b0}};
int_rvalid_reg <= 1'b0;
end
else
begin
int_arready_reg <= int_arready_next;
int_rdata_reg <= int_rdata_next;
int_rvalid_reg <= int_rvalid_next;
end
end
assign int_ardone_wire = ~int_arready_reg | s_axi_arvalid;
assign int_rdone_wire = ~int_rvalid_reg | s_axi_rready;
always @*
begin
int_arready_next = ~int_ardone_wire | int_rdone_wire;
int_rdata_next = int_rdata_reg;
int_rvalid_next = ~int_rdone_wire | int_ardone_wire;
if(int_ardone_wire & int_rdone_wire)
begin
int_rdata_next = s_axis_tvalid ? s_axis_tdata : {(AXI_DATA_WIDTH){1'b0}};
end
end
assign s_axi_awready = 1'b0;
assign s_axi_wready = 1'b0;
assign s_axi_bresp = 2'd0;
assign s_axi_bvalid = 1'b0;
assign s_axi_arready = int_arready_reg;
assign s_axi_rdata = int_rdata_reg;
assign s_axi_rresp = 2'd0;
assign s_axi_rvalid = int_rvalid_reg;
assign s_axis_tready = int_ardone_wire & int_rdone_wire;
endmodule
|
#include <bits/stdc++.h> using namespace std; double PI = 3.14159265358979323843; int BS(int arr[], int sz, int n) { int l = 0, r = sz - 1, mid; while (l <= r) { if (arr[mid] >= n) r = mid - 1; else l = mid + 1; } return l; } bool prime(long long x) { for (int i = 2; i <= sqrt(x); i++) { if (x % i == 0) { return false; } } return true; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); string s; cin >> s; int c = 0; if (s.size() == 1) { return puts( 0 ), 0; } while (true) { long long sum = 0; for (int i = 0; i < s.size(); i++) { sum += s[i] - 0 ; } s.clear(); if (sum / 10 == 0) { break; } c++; s = to_string(sum); } cout << ++c << endl; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2015 Xilinx, Inc.
// All Rights Reserved
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Application : Vivado HLS
// / / Filename: test_bench_onboard.v
// /___/ /\ Timestamp: Tue May 12 5:00:00 PST 2015
// \ \ / \
// \___\/\___\
//
//Command: N/A
//Device: 7K325T-2
//Design Name: multiSRC
//Purpose:
// This file contains the test bench to test the multiSRC filter
//Reference:
// XAPP1236
///////////////////////////////////////////////////////////////////////////////
module test_bench_onboard
(
input clk,
input rst,
input test_start,
output test_done,
output test_pass,
// interface to DUT
input ap_ready,
input ap_idle,
input ap_done,
input dut_vld_y,
input [47:0] dut_y,
output reg dut_rst,
output reg dut_start,
output reg dut_vld_x,
output reg [15:0] dut_x,
output reg [2:0] dut_rat
);
reg [14:0] cnt;
reg start_r1;
reg start_r2;
reg start_r3;
reg tv_compare1;
reg tv_compare2;
reg tv_compare3;
// interface to input test vector RAM
reg [19:0] tvin_rdata;
reg [12:0] tvin_raddr;
reg [47:0] tvout_rdata;
reg [12:0] tvout_raddr;
reg tv_valid;
reg tv_failure;
reg tvin_valid;
reg tvout_valid;
wire start_s;
reg test_pass_s;
reg tv_valid_p;
reg isfirst;
// clock domain conversion for start
always @(posedge clk) begin
start_r1 <= test_start;
start_r2 <= start_r1;
start_r3 <= start_r2;
end
assign start_s = (start_r3 & (!start_r2));
reg test_done_s;
assign test_done = test_done_s;
//-----------------------------------------
// main counter as the timing generation
//-----------------------------------------
always @(posedge clk, posedge rst) begin
// main counter
if(rst) begin
cnt <= 0;
end else begin
cnt <= (start_s==1'b1) ? 1 :
(cnt==0) ? 0 : cnt+1;
end
end
//-----------------------------------------------------
// dut interface and test vector rom address control
//-----------------------------------------------------
always @(posedge clk, posedge rst) begin
// main counter
if(rst) begin
dut_rst <= 1'b1;
dut_start <= 1'b0;
dut_vld_x <= 1'b0;
dut_x <= 0;
dut_rat <= 0;
tvin_valid <= 1'b0;
tvout_valid <= 1'b0;
tv_valid <= 1'b0;
tv_valid_p <= 1'b0;
tv_failure <= 1'b0;
test_done_s <= 1'b1;
isfirst <= 1'b1;
end else begin
dut_rst <= (isfirst && (cnt<32)) ? 1'b1 : 1'b0;
dut_start <= (isfirst && (cnt<64)) ? 1'b0 : 1'b1;
dut_vld_x <= (cnt<128) ? 1'b0 :
(cnt<1024) ? 1'b1 : tvin_rdata[19];
dut_x <= (cnt<1024) ? 0 : tvin_rdata[15:0];
dut_rat <= (cnt<1024) ? 0 : tvin_rdata[18:16];
tvin_valid <= (cnt<1022) ? 1'b0 :
(cnt>1022+8191) ? 1'b0 : 1'b1;
tvout_valid <= (cnt<(1022+62)) ? 1'b0 :
(cnt>(1022+62+8191)) ? 1'b0 : 1'b1;
tv_valid_p <= tvout_valid;
tv_valid <= tv_valid_p;
tv_failure <= (tv_valid==1'b1) && (tv_compare3==1'b1) && ( (tv_compare1==1'b0) || (tv_compare2==1'b0) );
test_done_s <= (start_s==1'b1) ? 1'b0 :
(cnt==8192+1024+256) ? 1'b1 : test_done_s;
isfirst <= (cnt==8192+1024+256) ? 1'b0 : isfirst;
end
end
//-----------------------------------------------------
// ROM Handling
//-----------------------------------------------------
reg [19:0] tvin_rom[8191:0];
reg [47:0] tvout_rom[8191:0];
initial begin
$readmemh("./tvin_rom.dat", tvin_rom);
$readmemh("./tvout_rom.dat", tvout_rom);
end
always @(posedge clk) begin
tvin_raddr <= (tvin_valid==1'b0)? 0 : tvin_raddr+1;
tvout_raddr <= (tvout_valid==1'b0)? 0 : tvout_raddr+1;
tvin_rdata <= tvin_rom[tvin_raddr];
tvout_rdata <= tvout_rom[tvout_raddr];
tv_compare1 <= (dut_vld_y==1'b0) || (tvout_rdata[46:24]==dut_y[46:24]);
tv_compare2 <= (dut_vld_y==1'b0) || (tvout_rdata[23:0]==dut_y[23:0]);
tv_compare3 <= (tvout_rdata[47]==dut_vld_y);
end
//-----------------------------------------------------
assign test_pass = test_pass_s;
always @(posedge clk, posedge rst) begin
if(rst) begin
test_pass_s <= 1'b1;
end else begin
test_pass_s <= (start_s==1'b1)? 1'b1 :
(tv_failure==1'b1)? 1'b0 : test_pass;
end
end
endmodule
|
#include <bits/stdc++.h> const int N = 1e5 + 5; struct ooo { int v, id; } p[N << 1]; bool operator<(const ooo& a, const ooo& b) { return a.v < b.v; } int n, ans, id, h, m, k, x; int main() { scanf( %d%d%d%d , &n, &h, &m, &k); m /= 2; for (int i = 1; i <= n; i++) scanf( %d%d , &x, &p[i].v), p[i].v %= m, p[i].id = i; std::sort(p + 1, p + 1 + n); for (int i = 1; i <= n; i++) p[i + n] = p[i], p[i + n].v += m; ans = 1e9; x = -1; for (int i = 1, j = 1; i <= n * 2; i++) { while (p[i].v - p[j].v >= k) j++; if (i > n && i - j < ans) ans = i - j, x = p[i].v; } printf( %d %d n , ans, x % m); for (int i = 1; i <= n * 2; i++) if (x - k < p[i].v && p[i].v < x) printf( %d , p[i].id); } |
#include <bits/stdc++.h> const double PI = acos(-1); int N; long long A; struct point { long long x, y; } p[100001]; struct line { double start, end; } q[100001]; inline long long sqr(long long x) { return x * x; } inline double tan_360(double x, double y) { if (x == 0) return PI * (y > 0 ? 0.5 : 1.5); if (y == 0) return PI * (x > 0 ? 0.0 : 1.0); double ans = atan(y / x); if (x > 0 && y > 0) return ans; if (x < 0 && y > 0) return ans + PI; if (x < 0 && y < 0) return ans + PI; return ans + PI * 2; } bool check(double mid) { int L = 0; for (int i = 1; i <= N; i++) if (sqrt(sqr(A + p[i].x) + sqr(p[i].y)) <= mid - sqrt(sqr(A - p[i].x) + sqr(p[i].y))) return true; for (int i = 1; i <= N; i++) { double R1 = mid, R2 = sqrt(sqr(A - p[i].x) + sqr(p[i].y)), dis = sqrt(sqr(A + p[i].x) + sqr(p[i].y)); if (R1 + R2 > dis && R1 + dis > R2 && R2 + dis > R1) { double mid_angle = tan_360(p[i].x + A, p[i].y), dif = acos((R1 * R1 + dis * dis - R2 * R2) / (2 * R1 * dis)); q[++L] = {mid_angle < dif ? mid_angle - dif + 2 * PI : mid_angle - dif, mid_angle + dif >= 2 * PI ? mid_angle + dif - 2 * PI : mid_angle + dif}; if (q[L].start > q[L].end) std::swap(q[L].start, q[L].end); } } std::sort(q + 1, q + L + 1, [](const line &a, const line &b) { return a.start < b.start || a.start == b.start && a.end < b.end; }); static int stack[100001]; int D = 0; for (int i = 1; i <= L; i++) { while (D && q[stack[D]].end < q[i].start) D--; if (D && q[stack[D]].end < q[i].end) return true; stack[++D] = i; } return false; } int main() { scanf( %d%lld , &N, &A); for (int i = 1; i <= N; i++) scanf( %lld%lld , &p[i].x, &p[i].y); double l = 0, r = A * 2; for (int T = 55; T--;) { double mid = (l + r) / 2; (check(mid) ? r : l) = mid; } printf( %.10lf n , l); return 0; } |
# include <bits/stdc++.h> # define int long long using namespace std; const int N=505; const int mo=998244353; int a[2*N][N],b[N][N]; bool f[2*N]; int Pow(int x,int n) { int ans=1; while (n) { if (n&1) ans=ans*x%mo; x=x*x%mo; n>>=1; } return ans; } vector<int>an; signed main() { int t; scanf( %lld ,&t); while (t--) { an.clear(); long long ans=1ll; int n; scanf( %lld ,&n); for (int i=1;i<=2*n;i++) for (int j=1;j<=n;j++) scanf( %lld ,&a[i][j]); int tot=0; for (int i=1;i<=2*n;i++) f[i]=false; while (true) { for (int i=1;i<=n;i++) for (int j=1;j<=n;j++) b[i][j]=0; for (int i=1;i<=2*n;i++) if (!f[i]) { for (int j=1;j<=n;j++) b[j][a[i][j]]++; } bool cc; int uniq; for (int i=1;i<=2*n;i++) if (!f[i]) { cc=false; for (int j=1;j<=n;j++) if (b[j][a[i][j]]==1) { cc=true; uniq=i; break; } if (cc) break; } if (cc) { an.push_back(uniq); } else { for (int i=1;i<=2*n;i++) if (!f[i]) { uniq=i; break; } an.push_back(uniq); ans=ans*2ll%mo; } for (int i=1;i<=2*n;i++) if (!f[i]) { bool flag=true; for (int j=1;j<=n;j++) if (a[i][j]==a[uniq][j]) { flag=false; break; } if (!flag) f[i]=true; } if (an.size()==n) break; } printf( %lld n ,ans); for (int i=0;i<an.size();i++) printf( %lld ,an[i]); puts( ); } return 0; } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:07:01 10/14/2013
// Design Name: Logica_Pong
// Module Name: C:/Users/Fabian/Documents/GitHub/taller-diseno-digital/Lab4/lab_pong/test_logica_pong.v
// Project Name: lab_pong
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Logica_Pong
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_logica_pong;
// Inputs
reg clock;
reg revisar_estado;
reg reset;
reg [8:0] barra_y;
reg [9:0] ball_x;
reg [8:0] ball_y;
// Outputs
wire choque_barra;
wire perdio;
// Instantiate the Unit Under Test (UUT)
Logica_Pong uut (
.clock(clock),
.revisar_estado(revisar_estado),
.reset(reset),
.barra_y(barra_y),
.ball_x(ball_x),
.ball_y(ball_y),
.choque_barra(choque_barra),
.perdio(perdio)
);
initial begin
// Initialize Inputs
clock = 0;
revisar_estado = 1;
reset = 0;
barra_y = 9'd100;
ball_x = 10'd90;
ball_y = 9'd90;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
#include <bits/stdc++.h> const int inf = (1 << 30) - 1; const double eps = 1e-9; using namespace std; int a[111111], n, k, mx = 0, aa; long long s[111111]; int main() { scanf( %d%d , &n, &k); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); sort(a + 1, a + n + 1); for (int i = 1; i <= n; i++) s[i] = s[i - 1] + a[i]; for (int i = 1; i <= n; i++) { int l = 1, r = i; while (r > l) { int m = (l + r) / 2; long long ss = s[i] - s[m - 1]; if (1ll * a[i] * (i - m + 1) - ss > k) l = m + 1; else r = m; } if (i - r + 1 > mx) { mx = i - r + 1; aa = a[i]; } } cout << (mx) << ; cout << (aa) << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> void chkmax(T &x, T y) { x = x > y ? x : y; } template <typename T> void chkmin(T &x, T y) { x = x > y ? y : x; } const int INF = (1ll << 30); template <typename T> void read(T &x) { x = 0; bool f = 1; char ch; do { ch = getchar(); if (ch == - ) f = 0; } while (ch > 9 || ch < 0 ); do { x = x * 10 + ch - 0 ; ch = getchar(); } while (ch >= 0 && ch <= 9 ); x = f ? x : -x; } template <typename T> void write(T x) { if (x < 0) x = ~x + 1, putchar( - ); if (x > 9) write(x / 10); putchar(x % 10 + 0 ); } const int N = 5000 + 5; const int M = 1e5 + 7; map<int, int> mp; int n, m, ans, cnt, a[N], b[N], g[N], f[N], prime[M]; bool vis[M]; inline int gcd(int a, int b) { if (a < b) swap(a, b); return b == 0 ? a : gcd(b, a % b); } inline void init(int NN) { for (int i = 2; i <= NN; i++) { if (!vis[i]) { prime[++cnt] = i; } for (int j = 1; j <= cnt && prime[j] * i <= NN; j++) { vis[prime[j] * i] = true; if (i % prime[j] == 0) break; } } } inline int divide(int x) { if (mp.count(x)) return mp[x]; int p = 0, tp = x; for (int i = 1; i <= m && b[i] <= x; i++) { while (x % b[i] == 0) x /= b[i], p--; } for (int i = 1; i <= cnt && 1ll * prime[i] * prime[i] <= x; i++) { while (x % prime[i] == 0) x /= prime[i], p++; } if (x != 1) p++; return mp[tp] = p; } int main() { read(n); read(m); for (int i = 1; i <= n; i++) read(a[i]), g[i] = gcd(a[i], g[i - 1]); for (int i = 1; i <= m; i++) read(b[i]); init(1e5); ans = 0; for (int i = 1; i <= n; i++) ans += divide(a[i]); for (int i = 1; i <= n; i++) f[i] = ans - i * divide(g[i]); for (int i = n; i >= 1; i--) { ans = max(ans, f[i]); for (int j = i - 1; j >= 1; j--) { int gg = g[j] / g[i]; f[j] = max(f[j], f[i] - j * divide(gg)); chkmax(ans, f[j]); } } printf( %d n , ans); return 0; } |
//#############################################################################
//# Purpose: SPI slave #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module spi_slave #( parameter UREGS = 13, // number of spi slave regs
parameter AW = 32, // addresss width
parameter PW = 104 // packet width
)
(
//clk,reset, cfg
input clk, // core clock
input nreset, // async active low reset
input hw_en, // block enbale pin
output [511:0] spi_regs, // all registers for control
output spi_irq, // interrupt
//IO interface
input sclk, // spi clock
input mosi, // slave input
input ss, // slave select
output miso, // slave output
// read request to core
output access_out, // valid transaction
output [PW-1:0] packet_out, // data to core (from spi port)
input wait_in, // pushback from core (not implemented)
// return from core
input access_in, // read response from core
input [PW-1:0] packet_in, // read response packet from core
output wait_out // pushback (not used)
);
//###############
//# LOCAL WIRES
//###############
/*AUTOINPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire cpha; // From spi_slave_regs of spi_slave_regs.v
wire cpol; // From spi_slave_regs of spi_slave_regs.v
wire irq_en; // From spi_slave_regs of spi_slave_regs.v
wire lsbfirst; // From spi_slave_regs of spi_slave_regs.v
wire [5:0] spi_addr; // From spi_slave_io of spi_slave_io.v
wire spi_clk; // From spi_slave_io of spi_slave_io.v
wire spi_en; // From spi_slave_regs of spi_slave_regs.v
wire [7:0] spi_rdata; // From spi_slave_regs of spi_slave_regs.v, ...
wire [7:0] spi_wdata; // From spi_slave_io of spi_slave_io.v
wire spi_write; // From spi_slave_io of spi_slave_io.v
// End of automatics
spi_slave_regs #(.AW(AW),
.PW(PW),
.UREGS(UREGS))
spi_slave_regs (/*AUTOINST*/
// Outputs
.spi_rdata (spi_rdata[7:0]),
.spi_en (spi_en),
.cpol (cpol),
.cpha (cpha),
.lsbfirst (lsbfirst),
.irq_en (irq_en),
.spi_regs (spi_regs[511:0]),
.wait_out (wait_out),
// Inputs
.clk (clk),
.nreset (nreset),
.hw_en (hw_en),
.spi_clk (spi_clk),
.spi_wdata (spi_wdata[7:0]),
.spi_write (spi_write),
.spi_addr (spi_addr[5:0]),
.access_out (access_out),
.access_in (access_in),
.packet_in (packet_in[PW-1:0]));
spi_slave_io #(.PW(PW))
spi_slave_io (/*AUTOINST*/
// Outputs
.miso (miso),
.spi_clk (spi_clk),
.spi_write (spi_write),
.spi_addr (spi_addr[5:0]),
.spi_wdata (spi_wdata[7:0]),
.spi_rdata (spi_rdata[7:0]),
.access_out (access_out),
.packet_out (packet_out[PW-1:0]),
// Inputs
.sclk (sclk),
.mosi (mosi),
.ss (ss),
.spi_en (spi_en),
.cpol (cpol),
.cpha (cpha),
.lsbfirst (lsbfirst),
.clk (clk),
.nreset (nreset),
.wait_in (wait_in));
endmodule // spi_slave
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_cmd.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
// User interface command port.
module ui_cmd #
(
parameter TCQ = 100,
parameter ADDR_WIDTH = 33,
parameter BANK_WIDTH = 3,
parameter COL_WIDTH = 12,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16,
parameter RANKS = 4,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
)
(/*AUTOARG*/
// Outputs
app_rdy, use_addr, rank, bank, row, col, size, cmd, hi_priority,
rd_accepted, wr_accepted, data_buf_addr,
// Inputs
rst, clk, accept_ns, rd_buf_full, wr_req_16, app_addr, app_cmd,
app_sz, app_hi_pri, app_en, wr_data_buf_addr, rd_data_buf_addr_r
);
input rst;
input clk;
input accept_ns;
input rd_buf_full;
input wr_req_16;
wire app_rdy_ns = accept_ns && ~rd_buf_full && ~wr_req_16;
reg app_rdy_r;
always @(posedge clk) app_rdy_r <= #TCQ app_rdy_ns;
output wire app_rdy;
assign app_rdy = app_rdy_r;
input [ADDR_WIDTH-1:0] app_addr;
input [2:0] app_cmd;
input app_sz;
input app_hi_pri;
input app_en;
reg [ADDR_WIDTH-1:0] app_addr_r1;
reg [ADDR_WIDTH-1:0] app_addr_r2;
reg [2:0] app_cmd_r1;
reg [2:0] app_cmd_r2;
reg app_sz_r1;
reg app_sz_r2;
reg app_hi_pri_r1;
reg app_hi_pri_r2;
reg app_en_r1;
reg app_en_r2;
wire [ADDR_WIDTH-1:0] app_addr_ns1 = app_rdy_r ? app_addr : app_addr_r1;
wire [ADDR_WIDTH-1:0] app_addr_ns2 = app_rdy_r ? app_addr_r1 : app_addr_r2;
wire [2:0] app_cmd_ns1 = app_rdy_r ? app_cmd : app_cmd_r1;
wire [2:0] app_cmd_ns2 = app_rdy_r ? app_cmd_r1 : app_cmd_r2;
wire app_sz_ns1 = app_rdy_r ? app_sz : app_sz_r1;
wire app_sz_ns2 = app_rdy_r ? app_sz_r1 : app_sz_r2;
wire app_hi_pri_ns1 = app_rdy_r ? app_hi_pri : app_hi_pri_r1;
wire app_hi_pri_ns2 = app_rdy_r ? app_hi_pri_r1 : app_hi_pri_r2;
wire app_en_ns1 = ~rst && (app_rdy_r ? app_en : app_en_r1);
wire app_en_ns2 = ~rst && (app_rdy_r ? app_en_r1 : app_en_r2);
always @(posedge clk) begin
app_addr_r1 <= #TCQ app_addr_ns1;
app_addr_r2 <= #TCQ app_addr_ns2;
app_cmd_r1 <= #TCQ app_cmd_ns1;
app_cmd_r2 <= #TCQ app_cmd_ns2;
app_sz_r1 <= #TCQ app_sz_ns1;
app_sz_r2 <= #TCQ app_sz_ns2;
app_hi_pri_r1 <= #TCQ app_hi_pri_ns1;
app_hi_pri_r2 <= #TCQ app_hi_pri_ns2;
app_en_r1 <= #TCQ app_en_ns1;
app_en_r2 <= #TCQ app_en_ns2;
end // always @ (posedge clk)
wire use_addr_lcl = app_en_r2 && app_rdy_r;
output wire use_addr;
assign use_addr = use_addr_lcl;
output wire [RANK_WIDTH-1:0] rank;
output wire [BANK_WIDTH-1:0] bank;
output wire [ROW_WIDTH-1:0] row;
output wire [COL_WIDTH-1:0] col;
output wire size;
output wire [2:0] cmd;
output wire hi_priority;
assign col = app_rdy_r
? app_addr_r1[0+:COL_WIDTH]
: app_addr_r2[0+:COL_WIDTH];
generate
begin
if (MEM_ADDR_ORDER == "ROW_BANK_COLUMN")
begin
assign row = app_rdy_r
? app_addr_r1[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH]
: app_addr_r2[COL_WIDTH+BANK_WIDTH+:ROW_WIDTH];
assign bank = app_rdy_r
? app_addr_r1[COL_WIDTH+:BANK_WIDTH]
: app_addr_r2[COL_WIDTH+:BANK_WIDTH];
end
else
begin
assign row = app_rdy_r
? app_addr_r1[COL_WIDTH+:ROW_WIDTH]
: app_addr_r2[COL_WIDTH+:ROW_WIDTH];
assign bank = app_rdy_r
? app_addr_r1[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH]
: app_addr_r2[COL_WIDTH+ROW_WIDTH+:BANK_WIDTH];
end
end
endgenerate
assign rank = (RANKS == 1)
? 1'b0
: app_rdy_r
? app_addr_r1[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH]
: app_addr_r2[COL_WIDTH+ROW_WIDTH+BANK_WIDTH+:RANK_WIDTH];
assign size = app_rdy_r
? app_sz_r1
: app_sz_r2;
assign cmd = app_rdy_r
? app_cmd_r1
: app_cmd_r2;
assign hi_priority = app_rdy_r
? app_hi_pri_r1
: app_hi_pri_r2;
wire request_accepted = use_addr_lcl && app_rdy_r;
wire rd = app_cmd_r2[1:0] == 2'b01;
wire wr = app_cmd_r2[1:0] == 2'b00;
wire wr_bytes = app_cmd_r2[1:0] == 2'b11;
wire write = wr || wr_bytes;
output wire rd_accepted;
assign rd_accepted = request_accepted && rd;
output wire wr_accepted;
assign wr_accepted = request_accepted && write;
input [3:0] wr_data_buf_addr;
input [3:0] rd_data_buf_addr_r;
output wire [3:0] data_buf_addr;
assign data_buf_addr = ~write ? rd_data_buf_addr_r : wr_data_buf_addr;
endmodule // ui_cmd
// Local Variables:
// verilog-library-directories:(".")
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBN_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DFBBN_FUNCTIONAL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr/sky130_fd_sc_ms__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_ms__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET;
wire SET ;
wire CLK ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_ms__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBN_FUNCTIONAL_V |
#include <bits/stdc++.h> using namespace std; int main(int argc, char** argv) { ios_base::sync_with_stdio(false); cin.tie(NULL); int x1, y1, x2, y2; cin >> x1 >> y1 >> x2 >> y2; double slope; slope = x2 == x1 ? INT_MAX : (double)(y2 - y1) / (double)(x2 - x1); if (slope == 0 || abs(slope) == 1 || abs(slope) == INT_MAX) { if (slope == 0) { int sideSq = abs(x2 - x1); int next_y = y1 + sideSq; if (next_y > 1000) { next_y = y1 - sideSq; if (next_y < -1000) { cout << -1 << n ; return 0; } } cout << x1 << << next_y << << x2 << << next_y << n ; } else if (slope == INT_MAX) { int sideSq = abs(y2 - y1); int next_x = x1 + sideSq; if (next_x > 1000) { next_x = x1 - sideSq; if (next_x < -1000) { cout << -1 << n ; return 0; } } cout << next_x << << y1 << << next_x << << y2 << n ; } else { cout << x1 << << y2 << << x2 << << y1 << n ; } } else { cout << -1 << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m; int ans; int a[400050]; int back[400050]; vector<int> edge[400050]; int main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> m; for (int i = 1; i <= n; i++) cin >> a[i]; for (int i = 1, u, v; i <= m; i++) { cin >> u >> v; edge[v].push_back(u); } for (auto iter : edge[a[n]]) back[iter]++; for (int i = n - 1; i >= 1; i--) { if (back[a[i]] == n - i - ans) ans++; else { for (auto iter : edge[a[i]]) back[iter]++; } } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int maxN = 3 * (int)1e5 + 100; int b[maxN]; int t[4 * maxN]; int a[maxN]; void build(int v, int tl, int tr) { if (tl == tr) { t[v] = a[tl]; return; } int tm = (tl + tr) / 2; build(v + v, tl, tm); build(v + v + 1, tm + 1, tr); t[v] = min(t[v + v], t[v + v + 1]); } void upd(int v, int tl, int tr, int pos, int val) { if (tl == tr) { t[v] = val; return; } int tm = (tl + tr) / 2; if (pos <= tm) upd(v + v, tl, tm, pos, val); else upd(v + v + 1, tm + 1, tr, pos, val); t[v] = min(t[v + v], t[v + v + 1]); } const int INF = (int)1e9 + 100; int get(int v, int tl, int tr, int l, int r) { if (l > r) return INF; if (tl == l && tr == r) { return t[v]; } int tm = (tl + tr) / 2; return min(get(v + v, tl, tm, l, min(r, tm)), get(v + v + 1, tm + 1, tr, max(l, tm + 1), r)); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr); int q; cin >> q; while (q--) { int n; cin >> n; set<pair<int, int> > s; for (int i = 1; i <= n; i++) { cin >> a[i]; s.insert(make_pair(a[i], i)); } bool ok = true; build(1, 1, n); for (int i = 1; i <= n; i++) { cin >> b[i]; if (!ok) continue; auto it = s.lower_bound(make_pair(b[i], -1)); if (it == s.end() || ((it->first) != b[i])) { ok = false; continue; } int ind = (it->second); s.erase(it); if (b[i] != get(1, 1, n, 1, ind)) { ok = false; } upd(1, 1, n, ind, INF); } if (ok) cout << YES << n ; else cout << NO << n ; } return 0; } |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2013.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : FRAME_ECCE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/30/13 - Initial version.
// 02/26/14 - Pulldown all outputs (CR 775504).
// End Revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module FRAME_ECCE3
`ifdef XIL_TIMING //Simprim
#(
parameter LOC = "UNPLACED"
)
`endif
(
output CRCERROR,
output ECCERRORNOTSINGLE,
output ECCERRORSINGLE,
output ENDOFFRAME,
output ENDOFSCAN,
output [25:0] FAR,
input [1:0] FARSEL,
input ICAPBOTCLK,
input ICAPTOPCLK
);
pulldown (CRCERROR);
pulldown (ECCERRORNOTSINGLE);
pulldown (ECCERRORSINGLE);
pulldown (ENDOFFRAME);
pulldown (ENDOFSCAN);
pulldown far_net[25:0] (FAR);
tri0 glblGSR = glbl.GSR;
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_TB_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_TB_V
/**
* lpflow_inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_inputiso0n.v"
module top();
// Inputs are registered
reg A;
reg SLEEP_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__lpflow_inputiso0n dut (.A(A), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_TB_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module crc
(input clk,
input reset,
input clear,
input [7:0] data,
input calc,
output [31:0] crc_out,
output match);
function[31:0] NextCRC;
input[7:0] D;
input[31:0] C;
reg[31:0] NewCRC;
begin
NewCRC[0] = C[24]^C[30]^D[1]^D[7];
NewCRC[1] = C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[2] = C[26]^D[5]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[3] = C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[4] = C[28]^D[3]^C[27]^D[4]^C[26]^D[5]^C[24]^C[30]^D[1]^D[7];
NewCRC[5] = C[29]^D[2]^C[28]^D[3]^C[27]^D[4]^C[25]^C[31]^D[0]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[6] = C[30]^D[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[7] = C[31]^D[0]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[8] = C[0]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[9] = C[1]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6];
NewCRC[10] = C[2]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[24]^D[7];
NewCRC[11] = C[3]^C[28]^D[3]^C[27]^D[4]^C[25]^D[6]^C[24]^D[7];
NewCRC[12] = C[4]^C[29]^D[2]^C[28]^D[3]^C[26]^D[5]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[13] = C[5]^C[30]^D[1]^C[29]^D[2]^C[27]^D[4]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[14] = C[6]^C[31]^D[0]^C[30]^D[1]^C[28]^D[3]^C[27]^D[4]^C[26]^D[5];
NewCRC[15] = C[7]^C[31]^D[0]^C[29]^D[2]^C[28]^D[3]^C[27]^D[4];
NewCRC[16] = C[8]^C[29]^D[2]^C[28]^D[3]^C[24]^D[7];
NewCRC[17] = C[9]^C[30]^D[1]^C[29]^D[2]^C[25]^D[6];
NewCRC[18] = C[10]^C[31]^D[0]^C[30]^D[1]^C[26]^D[5];
NewCRC[19] = C[11]^C[31]^D[0]^C[27]^D[4];
NewCRC[20] = C[12]^C[28]^D[3];
NewCRC[21] = C[13]^C[29]^D[2];
NewCRC[22] = C[14]^C[24]^D[7];
NewCRC[23] = C[15]^C[25]^D[6]^C[24]^C[30]^D[1]^D[7];
NewCRC[24] = C[16]^C[26]^D[5]^C[25]^C[31]^D[0]^D[6];
NewCRC[25] = C[17]^C[27]^D[4]^C[26]^D[5];
NewCRC[26] = C[18]^C[28]^D[3]^C[27]^D[4]^C[24]^C[30]^D[1]^D[7];
NewCRC[27] = C[19]^C[29]^D[2]^C[28]^D[3]^C[25]^C[31]^D[0]^D[6];
NewCRC[28] = C[20]^C[30]^D[1]^C[29]^D[2]^C[26]^D[5];
NewCRC[29] = C[21]^C[31]^D[0]^C[30]^D[1]^C[27]^D[4];
NewCRC[30] = C[22]^C[31]^D[0]^C[28]^D[3];
NewCRC[31] = C[23]^C[29]^D[2];
NextCRC = NewCRC;
end
endfunction
reg [31:0] crc_reg;
always @ (posedge clk)
if (reset | clear)
crc_reg <= 32'hffffffff;
else if (calc)
crc_reg <= NextCRC(data,crc_reg);
assign crc_out = ~{crc_reg[24],crc_reg[25],crc_reg[26],crc_reg[27],crc_reg[28],crc_reg[29],crc_reg[30],crc_reg[31],
crc_reg[16],crc_reg[17],crc_reg[18],crc_reg[19],crc_reg[20],crc_reg[21],crc_reg[22],crc_reg[23],
crc_reg[8],crc_reg[9],crc_reg[10],crc_reg[11],crc_reg[12],crc_reg[13],crc_reg[14],crc_reg[15],
crc_reg[0],crc_reg[1],crc_reg[2],crc_reg[3],crc_reg[4],crc_reg[5],crc_reg[6],crc_reg[7] };
assign match = (crc_reg == 32'hc704_dd7b);
endmodule // crc
|
#include <bits/stdc++.h> using namespace std; struct item { long long val; int ind; bool operator<(const item& o) const { return val < o.val; } }; long long n, m, k, s; vector<long long> dollar, pound, dday, pday; vector<item> ditems, pitems; void readIt() { cin >> n >> m >> k >> s; long long minn = 1e7; long long v, mday = 0; dollar.push_back(1e16); pound.push_back(1e16); pday.push_back(-1); dday.push_back(-1); for (int i = 1; i <= n; ++i) { cin >> v; if (minn > v) { minn = v; mday = i; } dollar.push_back(minn); dday.push_back(mday); } minn = 1e7; mday = 0; for (int i = 1; i <= n; ++i) { cin >> v; if (minn > v) { mday = i; minn = v; } pound.push_back(minn); pday.push_back(mday); } int type; for (int i = 0; i < m; ++i) { cin >> type >> v; if (type == 1) ditems.push_back({v, i + 1}); if (type == 2) pitems.push_back({v, i + 1}); } sort(ditems.begin(), ditems.end()); sort(pitems.begin(), pitems.end()); } bool isPossible(int days, bool verbose) { long long d = dollar[days]; long long p = pound[days]; int dit = 0, pit = 0; long long total = 0; for (int i = 0; i < k; ++i) { if (dit == ditems.size()) { if (verbose) cout << pitems[pit].ind << << pday[days] << n ; total += pitems[pit++].val * p; continue; } else if (pit == pitems.size()) { if (verbose) cout << ditems[dit].ind << << dday[days] << n ; total += ditems[dit++].val * d; continue; } if (ditems[dit].val * d < pitems[pit].val * p) { if (verbose) cout << ditems[dit].ind << << dday[days] << n ; total += ditems[dit++].val * d; } else { if (verbose) cout << pitems[pit].ind << << pday[days] << n ; total += pitems[pit++].val * p; } } if (total <= s) return true; return false; } int getDay() { int l = 0, r = n; while (l < r) { int m = (l + r + 1) / 2; if (isPossible(m, false)) { r = m - 1; } else { l = m; } } if (l == n) return -1; return l + 1; } int main() { ios_base::sync_with_stdio(0), cin.tie(0); readIt(); int day = getDay(); if (day == -1) { cout << -1 << endl; } else { cout << day << n ; isPossible(day, true); } return 0; } |
/*
00: Set master reset
01: Shift register
10: Storage register
11: Output Enable
*/
module shift(
input clk ,
input rst ,
input vld ,
input [1:0] cmd ,
input cmd_oen ,
input [7:0] din ,
output done ,
output sft_shcp ,
output sft_ds ,
output sft_stcp ,
output sft_mr_n ,
output sft_oe_n
);
reg sft_mr_n ;
reg sft_oe_n ;
always @ ( posedge clk or posedge rst ) begin
if( rst )
sft_mr_n <= 1'b1 ;
else if( vld && cmd == 2'b00 )
sft_mr_n <= 1'b0 ;
else
sft_mr_n <= 1'b1 ;
end
always @ ( posedge clk or posedge rst ) begin
if( rst )
sft_oe_n <= 1'b1 ;
else if( vld && cmd == 2'b11 )
sft_oe_n <= cmd_oen ;
end
//--------------------------------------------------
// shcp counter
//--------------------------------------------------
reg [5:0] shcp_cnt ;
always @ ( posedge clk ) begin
if( rst )
shcp_cnt <= 0 ;
else if( vld && cmd == 2'b01 )
shcp_cnt <= 1 ;
else if( |shcp_cnt )
shcp_cnt <= shcp_cnt + 1 ;
end
assign sft_shcp = shcp_cnt[2] ;
reg [7:0] data ;
always @ ( posedge clk ) begin
if( vld && cmd == 2'b01 )
data <= din ;
else if( &shcp_cnt[2:0] )
data <= data >> 1 ;
end
assign sft_ds = (vld&&cmd==2'b01) ? din[0] : data[0] ;
//--------------------------------------------------
// sft_stcp
//--------------------------------------------------
reg [5:0] stcp_cnt ;
always @ ( posedge clk ) begin
if( rst )
stcp_cnt <= 0 ;
else if( vld && cmd == 2'b10 )
stcp_cnt <= 1 ;
else if( |stcp_cnt )
stcp_cnt <= stcp_cnt + 1 ;
end
assign sft_stcp = stcp_cnt[2] ;
//--------------------------------------------------
// done
//--------------------------------------------------
assign done = (stcp_cnt == 63) || (shcp_cnt == 63) ;
endmodule
|
#include <bits/stdc++.h> using namespace ::std; const long long maxn = 1e5 + 500; const long long mod = 1e9 + 7; const long long inf = 1e9 + 500; long long out[maxn]; long long in[maxn]; long long a[maxn]; long long b[maxn]; long long dp[2][maxn]; int main() { fill(out, out + maxn, -1); fill(in, in + maxn, -1); long long n, q, t; cin >> n >> q >> t; for (long long i = 0; i < n; i++) { cin >> a[i]; } for (long long i = 0; i < q; i++) { long long v, u; cin >> v >> u; v--; u--; out[u] = v; in[v] = u; } for (long long i = 0; i < n; i++) { for (long long j = 0; j < n; j++) { if (out[j] == -1) { b[j] = a[j]; } else { if (b[out[j]] != 0) { b[j] = b[out[j]] + a[j]; } } } } for (long long i = 0; i < n; i++) { if (b[i] == 0) { cout << 0; return 0; } if (in[i] != -1) { t -= b[i]; } } if (t < 0) { cout << 0; return 0; } dp[1][0] = 1; for (long long i = 0; i < n; i++) { for (long long j = 0; j < b[i]; j++) { dp[i & 1][j] = dp[(i & 1) ^ 1][j]; } for (long long j = b[i]; j <= t; j++) { dp[i & 1][j] = ((long long)dp[(i & 1) ^ 1][j] + dp[(i & 1)][j - b[i]]) % mod; } } cout << dp[(n - 1) & 1][t]; } |
#include <bits/stdc++.h> using namespace std; const int N = 20; char s1[N], s2[N], ans[N]; int main() { scanf( %s%s , s1, s2); int n1 = strlen(s1), cnt = 0; ans[cnt++] = s1[0]; for (int i = 1; i < n1; i++) { if (s1[i] >= s2[0]) break; ans[cnt++] = s1[i]; } ans[cnt++] = s2[0]; printf( %s n , ans); return 0; } |
//doing a 800 difficulty question using dynammic programming #include<bits/stdc++.h> #define ll long long using namespace std; int main(){ int t; cin>>t; while(t--){ ll n,m,k; cin>>n>>m>>k; ll dp[n][m]; for(ll i=0;i<n;i++){ for(ll j=0;j<m;j++){ if(i==0){ dp[i][j]=j; } if(i!=0){ dp[i][j]=dp[i-1][j]+(j+1); }}} if(dp[n-1][m-1]==k){ cout<< YES << n ; } else{ cout<< NO << n ; } }} |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD1_TB_V
`define SKY130_FD_SC_HS__DLYGATE4SD1_TB_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlygate4sd1.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__dlygate4sd1 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD1_TB_V
|
//altclkctrl CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_TYPE="Global Clock" DEVICE_FAMILY="Cyclone IV E" ENA_REGISTER_MODE="falling edge" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" ena inclk outclk
//VERSION_BEGIN 16.1 cbx_altclkbuf 2016:11:22:18:30:39:SJ cbx_cycloneii 2016:11:22:18:30:39:SJ cbx_lpm_add_sub 2016:11:22:18:30:39:SJ cbx_lpm_compare 2016:11:22:18:30:39:SJ cbx_lpm_decode 2016:11:22:18:30:39:SJ cbx_lpm_mux 2016:11:22:18:30:39:SJ cbx_mgl 2016:11:22:19:17:36:SJ cbx_nadder 2016:11:22:18:30:39:SJ cbx_stratix 2016:11:22:18:30:39:SJ cbx_stratixii 2016:11:22:18:30:39:SJ cbx_stratixiii 2016:11:22:18:30:39:SJ cbx_stratixv 2016:11:22:18:30:39:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Intel and sold by Intel or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = clkctrl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module unnamed_altclkctrl_0_sub
(
ena,
inclk,
outclk) /* synthesis synthesis_clearbox=1 */;
input ena;
input [3:0] inclk;
output outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ena;
tri0 [3:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_clkctrl1_outclk;
wire [1:0] clkselect;
wire [1:0] clkselect_wire;
wire [3:0] inclk_wire;
cycloneive_clkctrl clkctrl1
(
.clkselect(clkselect_wire),
.ena(ena),
.inclk(inclk_wire),
.outclk(wire_clkctrl1_outclk)
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
clkctrl1.clock_type = "Global Clock",
clkctrl1.ena_register_mode = "falling edge",
clkctrl1.lpm_type = "cycloneive_clkctrl";
assign
clkselect = {2{1'b0}},
clkselect_wire = {clkselect},
inclk_wire = {inclk},
outclk = wire_clkctrl1_outclk;
endmodule //unnamed_altclkctrl_0_sub
//VALID FILE // (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module unnamed_altclkctrl_0 (
ena,
inclk,
outclk);
input ena;
input inclk;
output outclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 ena;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire outclk;
wire sub_wire1;
wire [3:0] sub_wire2;
wire [2:0] sub_wire3;
assign outclk = sub_wire0;
assign sub_wire1 = inclk;
assign sub_wire2[3:0] = {sub_wire3, sub_wire1};
assign sub_wire3[2:0] = 3'h0;
unnamed_altclkctrl_0_sub unnamed_altclkctrl_0_sub_component (
.ena (ena),
.inclk (sub_wire2),
.outclk (sub_wire0));
endmodule |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; const int maxn = 2e5 + 9; void test_case(int tc) { int k; cin >> k; int n = 12; int arr[12]; for (int i = 0; i <= 11; ++i) cin >> arr[i]; sort(arr, arr + 12, greater<int>()); int ans = 0; int temp = 0; if (k == 0) { cout << k << n ; return; } for (int i = 0; i <= n - 1; ++i) { temp += arr[i]; ans++; if (temp >= k) { cout << ans; return; } } cout << -1; } int32_t main() { ios_base::sync_with_stdio(false), cin.tie(NULL), cout.tie(NULL); int t = 1; for (int tc = 1; tc <= t; ++tc) test_case(tc); } |
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
(* altera_attribute = "-name ALLOW_SYNCH_CTRL_USAGE ON;-name AUTO_CLOCK_ENABLE_RECOGNITION ON" *)
module altera_mem_if_ddr3_phy_0001_flop_mem(
wr_clk,
wr_en,
wr_addr,
wr_data,
rd_reset_n,
rd_clk,
rd_en,
rd_addr,
rd_data
);
parameter WRITE_MEM_DEPTH = "";
parameter WRITE_ADDR_WIDTH = "";
parameter WRITE_DATA_WIDTH = "";
parameter READ_MEM_DEPTH = "";
parameter READ_ADDR_WIDTH = "";
parameter READ_DATA_WIDTH = "";
input wr_clk;
input wr_en;
input [WRITE_ADDR_WIDTH-1:0] wr_addr;
input [WRITE_DATA_WIDTH-1:0] wr_data;
input rd_reset_n;
input rd_clk;
input rd_en;
input [READ_ADDR_WIDTH-1:0] rd_addr;
output [READ_DATA_WIDTH-1:0] rd_data;
wire [WRITE_MEM_DEPTH-1:0] wr_decode;
wire [WRITE_DATA_WIDTH*WRITE_MEM_DEPTH-1:0] all_data;
wire [READ_DATA_WIDTH-1:0] mux_data_out;
// declare a memory with WRITE_MEM_DEPTH entries
// each entry contains a data size of WRITE_DATA_WIDTH
reg [WRITE_DATA_WIDTH-1:0] data_stored [0:WRITE_MEM_DEPTH-1] /* synthesis syn_preserve = 1 */;
reg [READ_DATA_WIDTH-1:0] rd_data;
always @(posedge wr_clk)
begin
if(wr_en)
data_stored[wr_addr] <= wr_data;
end
generate
genvar entry;
for (entry=0; entry < WRITE_MEM_DEPTH; entry=entry+1)
begin: mem_location
assign all_data[(WRITE_DATA_WIDTH*(entry+1)-1) : (WRITE_DATA_WIDTH*entry)] = data_stored[entry];
end
endgenerate
// mux to select the correct output data based on read address
lpm_mux uread_mux(
.sel (rd_addr),
.data (all_data),
.result (mux_data_out)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam uread_mux.lpm_size = READ_MEM_DEPTH;
defparam uread_mux.lpm_type = "LPM_MUX";
defparam uread_mux.lpm_width = READ_DATA_WIDTH;
defparam uread_mux.lpm_widths = READ_ADDR_WIDTH;
always @(posedge rd_clk)
begin
rd_data <= mux_data_out;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n, k; cin >> n >> k; int hash[201] = {0}; vector<pair<int, int>> v; for (int i = 0; i < n; i++) { int l, r; cin >> l >> r; v.push_back(make_pair(l, r)); for (int j = l; j < r + 1; j++) hash[j]++; } vector<int> ans(n); for (int j = 0; j < 250; j++) { while (hash[j] > k) { int m = -1; for (int i = 0; i < n; i++) { if (!ans[i] && (j >= v[i].first && j <= v[i].second)) { if (m == -1 || v[i].second > v[m].second) m = i; } } if (m == -1) break; for (int i = v[m].first; i < v[m].second + 1; i++) hash[i]--; ans[m] = 1; } } cout << accumulate(ans.begin(), ans.end(), 0) << endl; for (int i = 0; i < n; i++) if (ans[i]) cout << i + 1 << ; } |
#include <bits/stdc++.h> using namespace std; const int sz = 1e6 + 9; int n, m, k; long long tr[sz], tr_sum, tr_cnt; long long ret[sz], ret_sum, ret_cnt; int d, first, t, c; vector<pair<pair<int, int>, pair<int, int>>> v; vector<pair<long long, long long>> home; long long home_ans[sz]; long long ans = 1e18; int days[sz]; int main() { cin >> n >> m >> k; for (int i = 0; i < m; ++i) { cin >> d >> first >> t >> c; v.push_back(make_pair(make_pair(d, first), make_pair(t, c))); } sort(v.begin(), v.end()); for (int i = v.size() - 1; i >= 0; i--) { d = v[i].first.first; first = v[i].first.second; t = v[i].second.first; c = v[i].second.second; if (first) continue; if (!ret[t]) { ret[t] = c; ret_sum += c; ret_cnt++; } else if (ret[t] > c) { ret_sum -= ret[t]; ret[t] = c; ret_sum += c; } if (ret_cnt == n) home.push_back(make_pair(d, ret_sum)); } sort(home.begin(), home.end()); int tmp = 0; for (auto u : home) days[tmp++] = u.first; for (int i = home.size() - 1; i >= 0; i--) { if (i == home.size() - 1) home_ans[i] = home[i].second; else home_ans[i] = min(home_ans[i + 1], home[i].second); } for (int i = 0; i < v.size(); ++i) { d = v[i].first.first; first = v[i].first.second; t = v[i].second.first; c = v[i].second.second; if (t) continue; if (!tr[first]) { tr[first] = c; tr_sum += c; tr_cnt++; } else if (tr[first] > c) { tr_sum -= tr[first]; tr[first] = c; tr_sum += c; } if (tr_cnt == n) { int pos = lower_bound(days, days + home.size(), d + 1 + k) - days; if (pos >= home.size()) continue; ans = min(ans, tr_sum + home_ans[pos]); } } if (ans == 1e18) cout << -1; else cout << ans; return 0; } |
#include <bits/stdc++.h> using namespace std; int depth[200005], dad[200005]; int dep = 0; void node_depth(vector<int> vec[], int i) { dep = depth[i] + 1; for (auto j : vec[i - 1]) { if (j != dad[i]) { depth[j] = dep; } } for (auto j : vec[i - 1]) { if (j != dad[i]) { node_depth(vec, j); } } } int entry[200005], exiit[200005]; int timer = 0; void ancestor(vector<int> vec[], int i) { entry[i] = timer; timer++; for (auto j : vec[i - 1]) { if (j != dad[i]) { dad[j] = i; ancestor(vec, j); } } exiit[i] = timer; timer++; } bool isParent(int a, int b) { return (entry[a] <= entry[b] && exiit[a] >= exiit[b]); } signed idiot() { depth[1] = 0; int n, m; cin >> n >> m; vector<int> edge[n]; dad[1] = 1; for (int i = 0; i < n - 1; i++) { int u, v; cin >> u >> v; edge[u - 1].push_back(v); edge[v - 1].push_back(u); } ancestor(edge, 1); node_depth(edge, 1); while (m--) { int k; cin >> k; int temp = 1; vector<int> ve; while (k--) { int vi; cin >> vi; if (depth[vi] > depth[temp]) { temp = vi; } ve.push_back(vi); } bool path = true; for (auto i : ve) { if (!isParent(dad[i], temp)) { path = false; break; } } cout << (path ? YES : NO ) << n ; } return 0; } signed main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int test_case = 1; while (test_case--) idiot(); return 0; } |
// trigger_delay.v
`timescale 1 ns / 1 ps
module trigger_delay #(parameter N=3)
(
input clk,
input sync,
input reset,
input [7:0]delay,
input trg_in,
input [(N-1):0]data_in,
output reg trg_out,
output reg [(N-1):0]data_out
);
// time stamp counter
reg [7:0]t;
always @(posedge clk or posedge reset)
begin
if (reset) t <= 0;
else if (sync) t <= t + 1;
end
wire empty;
wire [7:0]tq;
wire [(N-1):0]dout;
wire write = trg_in && sync;
wire hit = tq == (t - delay);
wire read = hit && sync;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
trg_out <= 0;
data_out <= 0;
end
else if (sync)
begin
if (!empty)
begin
trg_out <= hit;
data_out <= dout;
end
else
begin
trg_out <= 0;
data_out <= 0;
end
end
end
scfifo
#(
.add_ram_output_register("OFF"),
.intended_device_family("Cyclone III"),
.lpm_numwords(256),
.lpm_showahead("ON"),
.lpm_type("scfifo"),
.lpm_width(N+8),
.lpm_widthu(8),
.overflow_checking("ON"),
.underflow_checking("ON"),
.use_eab("ON")
) fifo
(
.aclr (reset),
.clock (clk),
.data ({data_in, t}),
.rdreq (read),
.wrreq (write),
.empty (empty),
.q ({dout, tq}),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ()
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, s = 1; char a; string b[10], c; cin >> n; b[0] = ; b[1] = ; b[2] = 2 ; b[3] = 3 ; b[4] = 322 ; b[5] = 5 ; b[6] = 53 ; b[7] = 7 ; b[8] = 7222 ; b[9] = 7332 ; int k = 0; int d = 0; for (int i = 1; i <= n; i++) { cin >> a; s = a - 48; if (s != 1 && s != 0) c = c + b[s]; } sort(c.begin(), c.end()); k = c.size(); for (int i = k - 1; i >= 0; i--) cout << c[i]; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[111][111], x[111], k; int main() { int n, m; cin >> n >> m; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) cin >> a[i][j]; int in = 0; for (int i = 0; i < n; i++) if (a[i][0] < a[in][0]) in = i; for (int i = 0; i < n; i++) x[i] = a[i][0] - a[in][0]; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if (a[in][j] + x[i] < a[i][j]) { cout << NO << endl; return 0; } else if (a[in][j] + x[i] > a[i][j]) { if (k && (a[in][j] + x[i]) % k != a[i][j]) { cout << NO << endl; return 0; } k = a[in][j] + x[i] - a[i][j]; } if (!k) k = 2e9; for (int i = 0; i < n; i++) for (int j = 0; j < m; j++) if ((a[in][j] + x[i]) % k != a[i][j]) { cout << NO << endl; return 0; } cout << YES << endl; cout << k << endl; for (int i = 0; i < n; i++) cout << x[i] << ; cout << endl; for (int j = 0; j < m; j++) cout << a[in][j] << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; vector<pair<int, double>> ans[52]; int main() { int n, w, m; cin >> n >> w >> m; double s = (n * w) / (m * 1.0), c = w, b = 1, k = 0; for (int i = 0; i < m; i++) { double ne = s; while (1) { if (ne + 10e-7 > c) { ans[i].push_back(make_pair(b, c)); ne -= c; c = w; b++; if (++k > 2) { cout << NO ; return 0; } k = 0; if (abs(ne) < 10e-7) break; } else { ans[i].push_back(make_pair(b, ne)); c -= ne; k++; break; } } } cout << YES n ; for (int i = 0; i < m; i++) { for (auto it : ans[i]) cout << fixed << setprecision(0) << it.first << << setprecision(6) << it.second << ; cout << n ; } return 0; } |
#include <bits/stdc++.h> using namespace std; void dropAny(const vector<int> &a, int offset, vector<bool> &used) { vector<int> next(used.size(), a.size()); for (int i = int(a.size()) - 1; i >= offset; --i) { next[a[i]] = i; } int best = -1; for (int i = 0; i < (int)used.size(); ++i) { if (!used[i]) { continue; } if (best == -1 || next[best] < next[i]) { best = i; } } used[best] = false; ; } struct RangeTree { int kk; vector<pair<int, int> > b; RangeTree(int n) { kk = 1; while (kk < n) { kk *= 2; } b.assign(2 * kk + 10, pair<int, int>(-1, -1)); } int getMaxPos() { return b[1].second; } int get(int pos) { return b[pos + kk].first; } void set(int pos, int val) { ; int t = pos + kk; b[t] = pair<int, int>(val, pos); while (t > 1) { t /= 2; b[t] = max(b[2 * t], b[2 * t + 1]); } } }; int main() { int n, k; scanf( %d%d , &n, &k); int maxA = 0; vector<int> a(n); vector<pair<int, int> > z(n); for (int i = 0; i < n; ++i) { scanf( %d , &a[i]); z[i] = pair<int, int>(a[i], i); maxA = max(maxA, a[i] + 1); } sort(z.begin(), z.end()); vector<int> next(n, n); for (int i = 1; i < int(z.size()); ++i) { if (z[i - 1].first == z[i].first) { next[z[i - 1].second] = z[i].second; } } for (int i = 0; i < n; ++i) { ; }; RangeTree tree(maxA); int cnt = 0; int ans = 0; for (int i = 0; i < n; ++i) { if (tree.get(a[i]) == -1) { ; if (cnt == k) { int pos = tree.getMaxPos(); ; tree.set(pos, -1); cnt--; } tree.set(a[i], next[i]); ans++; cnt++; } else { tree.set(a[i], next[i]); } } printf( %d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFINV_8_V
`define SKY130_FD_SC_HS__BUFINV_8_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog wrapper for bufinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__bufinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufinv_8 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__bufinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFINV_8_V
|
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 10; long long ans, res; int L[N], R[N]; int n, a[N]; long long dp[40][2]; void solve(int d, int l, int r) { if (l >= r) return; if (d == -1) return; int nl = 0, nr = 0; long long tmp1 = 0, tmp2 = 0; ; for (int i = l; i <= r; i++) { if (a[i] >> d & 1) L[++nl] = a[i], tmp1 += nr; else R[++nr] = a[i], tmp2 += nl; } dp[d][1] += tmp1; dp[d][0] += tmp2; int x = 1, y = 1; for (int i = l; i <= r; i++) { if (x <= nl) a[i] = L[x++]; else a[i] = R[y++]; } solve(d - 1, l, l + nl - 1); solve(d - 1, l + nl, r); } int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); solve(30, 1, n); for (int i = 0; i <= 30; i++) { if (dp[i][1] < dp[i][0]) ans += dp[i][1], res |= (1 << i); else ans += dp[i][0]; } printf( %lld %lld n , ans, res); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, temp; cin >> n >> k; int arr[n], sum[n]; for (int i = 0; i < n; i++) cin >> arr[i]; for (int i = 0; i < n; i++) { if (arr[i] == 0) sum[i] = 0; else sum[i] = sum[arr[i] - 1]; temp = i > k ? k : i; temp += i + k < n ? k : (n - i - 1); temp++; if (arr[i] + k > i - k && arr[i] != 0) { if (arr[i] + k > n) temp = 0; else if (i - k < 0) temp -= arr[i] + k; else temp -= arr[i] + k - i + k; } sum[i] += temp; cout << sum[i] << ; } cout << endl; } |
#include <bits/stdc++.h> using namespace std; bool vis[1000][1000]; bool lab[1000][1000]; vector<int> ans; int comp[1000][1000]; int cur_ans; int cur_comp = 0; int dfs(int x, int y) { if (!lab[x][y]) { ++cur_ans; return 0; } if (!vis[x][y]) { comp[x][y] = cur_comp; vis[x][y] = true; dfs(x + 1, y); dfs(x, y + 1); dfs(x - 1, y); dfs(x, y - 1); } return 0; } int main() { int n, m, k; cin >> n >> m >> k; for (int i = 0; i < n; ++i) { for (int j = 0; j < m; ++j) { char c; cin >> c; if (c == * ) { lab[i][j] = false; } else { lab[i][j] = true; } } } for (int i = 0; i < k; ++i) { int x, y; cin >> x >> y; --x; --y; if (!vis[x][y]) { cur_ans = 0; dfs(x, y); cur_comp++; ans.push_back(cur_ans); cout << cur_ans << endl; } else { cout << ans[comp[x][y]] << endl; } } return 0; } |
#include <bits/stdc++.h> using namespace std; int a[100100]; int main() { ios::sync_with_stdio(false); cin.tie(nullptr); cout.tie(nullptr); int n, k; cin >> n >> k; for (int i = 0; i < n; i++) cin >> a[i]; const long long max_pow = 1e9 * 1e5; vector<long long> powers = {1}; if (abs(k) > 1) while (abs(powers.back() * k) <= max_pow) powers.push_back(powers.back() * k); else if (k == -1) powers.push_back(-1); long long ans = 0; long long prefix_sum = 0; map<long long, long long> cnt_sums; for (int i = 0; i < n; i++) { cnt_sums[prefix_sum]++; prefix_sum += a[i]; for (auto pow : powers) if (cnt_sums.count(prefix_sum - pow) > 0) ans += cnt_sums[prefix_sum - pow]; } cout << ans; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAP_TB_V
`define SKY130_FD_SC_LS__TAP_TB_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__tap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAP_TB_V
|
module MemAlu(
/* verilator lint_off UNUSED */
clk,
mode,
baseAddr,
idxAddr,
idxDisp,
outAddr
);
input clk;
input[2:0] mode;
input[63:0] baseAddr;
input[31:0] idxAddr;
input[31:0] idxDisp;
output[63:0] outAddr;
reg[31:0] tIdxAddr;
reg[63:0] tIdxAddr2;
reg[63:0] tOutAddr;
parameter[2:0] MD_NONE = 3'b000;
parameter[2:0] MD_BYTE = 3'b001;
parameter[2:0] MD_WORD = 3'b010;
parameter[2:0] MD_DWORD = 3'b011;
parameter[2:0] MD_QWORD = 3'b100;
parameter[2:0] MD_OWORD = 3'b101;
parameter[2:0] MD_MOV = 3'b111;
parameter[63:0] NULL_ADDR = 64'h0000_0000_0000_0000;
parameter[63:0] NEG_ADDR = 64'hFFFF_FFFF_0000_0000;
always @ (mode) begin
tIdxAddr = idxAddr+idxDisp;
// tIdxAddr2 = tIdxAddr[31] ?
// (tIdxAddr|NEG_ADDR) :
// (tIdxAddr|NULL_ADDR);
tIdxAddr2[31:0] = tIdxAddr;
tIdxAddr2[63:32] = tIdxAddr[31] ?
32'hFFFF_FFFF :
32'h0000_0000 ;
case(mode)
MD_BYTE: begin
tOutAddr = baseAddr+tIdxAddr2;
end
MD_WORD: begin
tOutAddr = baseAddr+tIdxAddr2*2;
end
MD_DWORD: begin
tOutAddr = baseAddr+tIdxAddr2*4;
end
MD_QWORD: begin
tOutAddr = baseAddr+tIdxAddr2*8;
end
MD_OWORD: begin
tOutAddr = baseAddr+tIdxAddr2*16;
end
MD_MOV: begin
tOutAddr = baseAddr;
end
default: begin
tOutAddr = NULL_ADDR;
end
endcase
outAddr = tOutAddr;
end
//always @ (posedge clk) begin
// outAddr <= tOutAddr;
//end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 601000; struct SuffixArray { int s[N], sa[N], rk[N], height[N], t[N], t2[N], c[N], n; void clear() { n = 0; } void build_sa(int m) { int *x = t, *y = t2; for (int i = 0; i < m; i++) c[i] = 0; for (int i = 0; i < n; i++) c[x[i] = s[i]]++; for (int i = 1; i < m; i++) c[i] += c[i - 1]; for (int i = n - 1; i >= 0; i--) sa[--c[x[i]]] = i; for (int k = 1; k <= n; k <<= 1) { int p = 0; for (int i = n - k; i < n; i++) y[p++] = i; for (int i = 0; i < n; i++) if (sa[i] >= k) y[p++] = sa[i] - k; for (int i = 0; i < m; i++) c[i] = 0; for (int i = 0; i < n; i++) c[x[y[i]]]++; for (int i = 1; i < m; i++) c[i] += c[i - 1]; for (int i = n - 1; i >= 0; i--) sa[--c[x[y[i]]]] = y[i]; swap(x, y); p = 1; x[sa[0]] = 0; for (int i = 1; i < n; i++) x[sa[i]] = y[sa[i - 1]] == y[sa[i]] && y[sa[i - 1] + k] == y[sa[i] + k] ? p - 1 : p++; if (p >= n) break; m = p; } } void build_height() { for (int i = 0; i < n; i++) rk[sa[i]] = i; for (int i = 0, k = 0; i < n - 1; i++) { if (k) k--; int j = sa[rk[i] - 1]; while (s[i + k] == s[j + k]) k++; height[rk[i]] = k; } } void add(int ch) { s[n++] = ch; } }; SuffixArray sa; int Log[N]; int lcp[N][20]; int callcp(int a, int b) { int tt = b - a + 1, len = Log[tt]; return min(lcp[a][len], lcp[a + tt - (1 << len)][len]); } int callo(int x, int len) { int l = 0, r = x; while (l + 1 < r) { int mid = (l + r) >> 1; if (callcp(mid + 1, x) >= len) r = mid; else l = mid; } return r; } int calup(int x, int len) { int l = x, r = sa.n; while (l + 1 < r) { int mid = (l + r) >> 1; if (callcp(x + 1, mid) >= len) l = mid; else r = mid; } return l; } char s[N]; int val[N]; int l[20], r[20], vx[20], vy[20], n; int ban; long long ans; int sum[20]; int dp[20][N]; bool cl(int loc, int len) { int x = callo(loc, len); int y = calup(loc, len); for (int i = 1; i <= n; i++) { sum[i] = dp[i][y] - dp[i][x - 1]; if (sum[i] > vy[i]) return false; } return true; } bool cr(int loc, int len) { int x = callo(loc, len); int y = calup(loc, len); for (int i = 1; i <= n; i++) { sum[i] = dp[i][y] - dp[i][x - 1]; if (sum[i] < vx[i]) return false; } return true; } int sl; void update(int loc) { int L = 0, R = sl - sa.sa[loc]; while (L + 1 < R) { int mid = (L + R) >> 1; if (cl(loc, mid)) R = mid; else L = mid; } if (!cl(loc, R)) return; int aa = R; L = 1, R = sl - sa.sa[loc] + 1; while (L + 1 < R) { int mid = (L + R) >> 1; if (cr(loc, mid)) L = mid; else R = mid; } if (!cr(loc, L)) return; int bb = L; aa = max(aa, ban); if (aa > bb) return; ans += (bb - aa + 1); } int main() { memset(val, -1, sizeof(val)); Log[0] = -1; for (int i = 1; i < N; i++) { Log[i] = Log[i >> 1] + 1; } scanf( %s , s); l[0] = 0; sl = strlen(s); for (int i = 0; s[i]; i++) { val[sa.n] = 0; sa.add(s[i] - a + 1); } r[0] = sa.n; int add = 27; scanf( %d , &n); for (int i = 1; i <= n; i++) { sa.add(add++); l[i] = sa.n; scanf( %s%d%d , s, &vx[i], &vy[i]); for (int j = 0; s[j]; j++) { val[sa.n] = i; sa.add(s[j] - a + 1); } r[i] = sa.n; } sa.add(0); sa.build_sa(add); sa.build_height(); for (int i = 1; i < sa.n; i++) { lcp[i][0] = sa.height[i]; } for (int j = 1; j < 20; j++) { for (int i = 1; i + (1 << j) <= sa.n; i++) { lcp[i][j] = min(lcp[i][j - 1], lcp[i + (1 << (j - 1))][j - 1]); } } for (int i = 1; i < sa.n; i++) { for (int j = 1; j <= n; j++) { dp[j][i] = dp[j][i - 1]; } if (~val[sa.sa[i]]) dp[val[sa.sa[i]]][i]++; } int last = 0; for (int i = 1; i < sa.n; i++) { if (sa.sa[i] >= l[0] && sa.sa[i] < r[0]) { if (last) { ban = callcp(last + 1, i) + 1; } last = i; update(i); } } printf( %I64d n , ans); return 0; } |
// In the name of Allah. // We re nothing and you re everything. // Ya Ali! #include <bits/stdc++.h> using namespace std; typedef long long ll; const int MAX_N = 1e5 + 14, MAX_K = 40; int n, k; struct XorKeeper { int a[MAX_K]{}; XorKeeper operator^(const XorKeeper &o) { XorKeeper ret; for (int i = 0; i < 2 * k; ++i) { ret.a[i] = a[i] ^ o.a[i]; } return ret; } XorKeeper &operator^=(const XorKeeper &o) { return *this = *this ^ o; } XorKeeper next() const { XorKeeper ret = *this; rotate(ret.a, ret.a + 2 * k - 1, ret.a + 2 * k); return ret; } int get_ans() { return accumulate(a + k, a + 2 * k, 0, [](int x, int y) { return x ^ y; }); } } down[MAX_N], up[MAX_N]; vector<int> g[MAX_N]; int a[MAX_N]; void dfs_down(int v = 0, int p = -1) { down[v].a[0] = a[v]; for (auto u : g[v]) if (u != p) { dfs_down(u, v); down[v] ^= down[u].next(); } } void dfs_up(int v = 0, int p = -1) { for (auto u : g[v]) if (u != p) { up[u] = (up[v] ^ down[v] ^ down[u].next()).next(); dfs_up(u, v); } } int main() { ios::sync_with_stdio(0), cin.tie(0); cin >> n >> k; for (int i = 0; i < n - 1; ++i) { int v, u; cin >> v >> u; v--, u--; g[v].push_back(u); g[u].push_back(v); } for (int i = 0; i < n; ++i) { cin >> a[i]; } dfs_down(); dfs_up(); for (int i = 0; i < n; ++i) { cout << bool(down[i].get_ans() ^ up[i].get_ans()) << ; } cout << n ; } |
// ulight_fifo_hps_0.v
// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.1 593
`timescale 1 ps / 1 ps
module ulight_fifo_hps_0 #(
parameter F2S_Width = 0,
parameter S2F_Width = 1
) (
output wire h2f_rst_n, // h2f_reset.reset_n
input wire h2f_axi_clk, // h2f_axi_clock.clk
output wire [11:0] h2f_AWID, // h2f_axi_master.awid
output wire [29:0] h2f_AWADDR, // .awaddr
output wire [3:0] h2f_AWLEN, // .awlen
output wire [2:0] h2f_AWSIZE, // .awsize
output wire [1:0] h2f_AWBURST, // .awburst
output wire [1:0] h2f_AWLOCK, // .awlock
output wire [3:0] h2f_AWCACHE, // .awcache
output wire [2:0] h2f_AWPROT, // .awprot
output wire h2f_AWVALID, // .awvalid
input wire h2f_AWREADY, // .awready
output wire [11:0] h2f_WID, // .wid
output wire [31:0] h2f_WDATA, // .wdata
output wire [3:0] h2f_WSTRB, // .wstrb
output wire h2f_WLAST, // .wlast
output wire h2f_WVALID, // .wvalid
input wire h2f_WREADY, // .wready
input wire [11:0] h2f_BID, // .bid
input wire [1:0] h2f_BRESP, // .bresp
input wire h2f_BVALID, // .bvalid
output wire h2f_BREADY, // .bready
output wire [11:0] h2f_ARID, // .arid
output wire [29:0] h2f_ARADDR, // .araddr
output wire [3:0] h2f_ARLEN, // .arlen
output wire [2:0] h2f_ARSIZE, // .arsize
output wire [1:0] h2f_ARBURST, // .arburst
output wire [1:0] h2f_ARLOCK, // .arlock
output wire [3:0] h2f_ARCACHE, // .arcache
output wire [2:0] h2f_ARPROT, // .arprot
output wire h2f_ARVALID, // .arvalid
input wire h2f_ARREADY, // .arready
input wire [11:0] h2f_RID, // .rid
input wire [31:0] h2f_RDATA, // .rdata
input wire [1:0] h2f_RRESP, // .rresp
input wire h2f_RLAST, // .rlast
input wire h2f_RVALID, // .rvalid
output wire h2f_RREADY, // .rready
output wire [12:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [7:0] mem_dq, // .mem_dq
inout wire mem_dqs, // .mem_dqs
inout wire mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire mem_dm, // .mem_dm
input wire oct_rzqin // .oct_rzqin
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (F2S_Width != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
f2s_width_check ( .error(1'b1) );
end
if (S2F_Width != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
s2f_width_check ( .error(1'b1) );
end
endgenerate
ulight_fifo_hps_0_fpga_interfaces fpga_interfaces (
.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
.h2f_AWADDR (h2f_AWADDR), // .awaddr
.h2f_AWLEN (h2f_AWLEN), // .awlen
.h2f_AWSIZE (h2f_AWSIZE), // .awsize
.h2f_AWBURST (h2f_AWBURST), // .awburst
.h2f_AWLOCK (h2f_AWLOCK), // .awlock
.h2f_AWCACHE (h2f_AWCACHE), // .awcache
.h2f_AWPROT (h2f_AWPROT), // .awprot
.h2f_AWVALID (h2f_AWVALID), // .awvalid
.h2f_AWREADY (h2f_AWREADY), // .awready
.h2f_WID (h2f_WID), // .wid
.h2f_WDATA (h2f_WDATA), // .wdata
.h2f_WSTRB (h2f_WSTRB), // .wstrb
.h2f_WLAST (h2f_WLAST), // .wlast
.h2f_WVALID (h2f_WVALID), // .wvalid
.h2f_WREADY (h2f_WREADY), // .wready
.h2f_BID (h2f_BID), // .bid
.h2f_BRESP (h2f_BRESP), // .bresp
.h2f_BVALID (h2f_BVALID), // .bvalid
.h2f_BREADY (h2f_BREADY), // .bready
.h2f_ARID (h2f_ARID), // .arid
.h2f_ARADDR (h2f_ARADDR), // .araddr
.h2f_ARLEN (h2f_ARLEN), // .arlen
.h2f_ARSIZE (h2f_ARSIZE), // .arsize
.h2f_ARBURST (h2f_ARBURST), // .arburst
.h2f_ARLOCK (h2f_ARLOCK), // .arlock
.h2f_ARCACHE (h2f_ARCACHE), // .arcache
.h2f_ARPROT (h2f_ARPROT), // .arprot
.h2f_ARVALID (h2f_ARVALID), // .arvalid
.h2f_ARREADY (h2f_ARREADY), // .arready
.h2f_RID (h2f_RID), // .rid
.h2f_RDATA (h2f_RDATA), // .rdata
.h2f_RRESP (h2f_RRESP), // .rresp
.h2f_RLAST (h2f_RLAST), // .rlast
.h2f_RVALID (h2f_RVALID), // .rvalid
.h2f_RREADY (h2f_RREADY) // .rready
);
ulight_fifo_hps_0_hps_io hps_io (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin) // .oct_rzqin
);
endmodule
|
//=============================================================
//
// Copyright (c) 2017 Simon Southwell. All rights reserved.
//
// Date: 30th May 2017
//
// This code is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// The code is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this code. If not, see <http://www.gnu.org/licenses/>.
//
// $Id: sram.v,v 1.2 2017/08/28 10:33:37 simon Exp $
// $Source: /home/simon/CVS/src/cpu/mico32/HDL/test/verilog/sram.v,v $
//
//=============================================================
//
// Simple model of a 512KB SRAM memory (256K x 16).
//
//=============================================================
`include "test_defs.vh"
// SRAM 512KB
`define MEMBYTEADDRBITS 19
`define MEMSIZEBYTES (1 << `MEMBYTEADDRBITS)
module sram (
inout [15:0] SRAM_DQ,
input [17:0] SRAM_ADDR,
input SRAM_UB_N,
input SRAM_LB_N,
input SRAM_WE_N,
input SRAM_CE_N,
input SRAM_OE_N
);
reg [7:0] mem[`MEMSIZEBYTES-1:0];
wire [`MEMBYTEADDRBITS-1:0] byte_addr0 = {SRAM_ADDR, 1'b0};
wire [`MEMBYTEADDRBITS-1:0] byte_addr1 = {SRAM_ADDR, 1'b1};
wire sram_read = ~SRAM_CE_N & ~SRAM_OE_N;
// DQ tristate control. Only drive if chip selected and output enable active.
assign SRAM_DQ = {(~sram_read | SRAM_UB_N) ? 8'hzz : mem[byte_addr1],
(~sram_read | SRAM_LB_N) ? 8'hzz : mem[byte_addr0]};
always @(*)
begin
// Write to memory if chip selected, WE active and one or more
// byte enables active.
if (~SRAM_CE_N & ~SRAM_WE_N)
begin
if (~SRAM_LB_N)
mem[byte_addr0] = SRAM_DQ [7:0];
if (~SRAM_UB_N)
mem[byte_addr1] = SRAM_DQ [15:8];
end
end
endmodule |
#include <bits/stdc++.h> using namespace std; long long res, n, k, d = 0, f, s, moy, mx; long long t[300003]; bool b = true; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cin >> n >> k; for (long long i = 0; i < n; i++) cin >> t[i]; reverse(t, t + n); f = k - 1; while (d <= f) { b = true; moy = (d + f) / 2; mx = k - 1; for (long long i = 0; i < n; i++) { if (t[i] <= mx) mx = min(mx, t[i] + moy); else if ((t[i] + moy) >= k) mx = min(mx, t[i] + moy - k); else { b = false; break; } } if (b) { res = moy; f = moy - 1; } else d = moy + 1; } cout << res; return 0; } |
module center_pos(x_row , y_col ,reset , clk ,center_x,center_y,valid);
input [15:0] x_row;
input [15:0] y_col ;
input reset;
input clk ;
input [15:0] valid ;
output [15:0] center_x;
output [15:0] center_y;
reg [15:0] center_x;
reg [15:0] center_y;
reg [31:0] center_x_temp;
reg [31:0] center_y_temp;
reg [31:0]pixel_counter ;
reg [31 : 0 ] dirty ;
always @ (posedge clk)
begin
if (dirty >= 32'h00075300 )
begin
//center_x = result_x[15:0];
//center_y = result_y[15:0];
center_x = 16'h1111;
//center_y = pixel_counter[15:0];
center_y = 16'h1111;
center_x_temp = 32'h00000000;
center_y_temp = 32'h00000000;
pixel_counter = 32'h0000FFFF;
dirty = 32'h00000000;
end
else //if (valid [ 7 : 0 ] == 8'b11111111 ) // pink
begin
center_y = dirty[31:16];
center_x = 16'hAAAA;
center_x_temp = center_x_temp + x_row ;
center_y_temp = center_y_temp + y_col ;
pixel_counter = pixel_counter + 32'h00000001;
dirty = dirty + 32'h00000001;
end
end
wire [31:0] result_x;
wire [31:0] result_y;
alt_div div_x(
.denom(pixel_counter),
.numer(center_x_temp),
.quotient(result_x),
.remain());
alt_div div_y(
.denom(pixel_counter),
.numer(center_y_temp),
.quotient(result_y),
.remain());
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Last modified date: 03/16 '13
* Last modified by: Ye-sheng Kuo <>
* Last modified content: Newly added
* --------------------------------------------------------------------------
* IMPORTANT: This module should be always on, do NOT connect this module
* to power gated domain. This module sits between Bus controller
* and layer controller
* --------------------------------------------------------------------------
* */
`include "include/mbus_def.v"
module mbus_regular_isolation(
input RELEASE_ISO_FROM_SLEEP_CTRL,
// LC stands for Layer Controller
// Interrconnect between this module and LC
input [`ADDR_WIDTH-1:0] TX_ADDR_FROM_LC,
input [`DATA_WIDTH-1:0] TX_DATA_FROM_LC,
input TX_PEND_FROM_LC,
input TX_REQ_FROM_LC,
input PRIORITY_FROM_LC,
output reg TX_ACK_TO_LC,
output reg [`ADDR_WIDTH-1:0] RX_ADDR_TO_LC,
output reg [`DATA_WIDTH-1:0] RX_DATA_TO_LC,
output reg RX_REQ_TO_LC,
input RX_ACK_FROM_LC,
output reg RX_FAIL_TO_LC,
output reg RX_PEND_TO_LC,
output reg TX_FAIL_TO_LC,
output reg TX_SUCC_TO_LC,
input TX_RESP_ACK_FROM_LC,
output reg RX_BROADCAST_TO_LC,
// BC stands for Bus Controller
// Interrconnect between this module and BC
output reg [`ADDR_WIDTH-1:0] TX_ADDR_TO_BC,
output reg [`DATA_WIDTH-1:0] TX_DATA_TO_BC,
output reg TX_PEND_TO_BC,
output reg TX_REQ_TO_BC,
output reg PRIORITY_TO_BC,
input TX_ACK_FROM_BC,
input [`ADDR_WIDTH-1:0] RX_ADDR_FROM_BC,
input [`DATA_WIDTH-1:0] RX_DATA_FROM_BC,
input RX_REQ_FROM_BC,
output reg RX_ACK_TO_BC,
input RX_FAIL_FROM_BC,
input RX_PEND_FROM_BC,
input TX_FAIL_FROM_BC,
input TX_SUCC_FROM_BC,
output reg TX_RESP_ACK_TO_BC,
input RX_BROADCAST_FROM_BC,
input POWER_ON_FROM_BC,
input RELEASE_CLK_FROM_BC,
input RELEASE_RST_FROM_BC,
input RELEASE_ISO_FROM_BC,
// use this to isolate signals between layer controller and CPU/MEM etc.
output reg RELEASE_ISO_FROM_BC_MASKED,
output reg POWER_ON_TO_LC,
output reg RELEASE_CLK_TO_LC,
output reg RELEASE_RST_TO_LC
);
parameter HOLD = `IO_HOLD; // During sleep
parameter RELEASE = `IO_RELEASE; // During wake-up
always @ *
begin
if (RELEASE_ISO_FROM_SLEEP_CTRL==HOLD)
begin
POWER_ON_TO_LC = HOLD;
RELEASE_CLK_TO_LC = HOLD;
RELEASE_RST_TO_LC = HOLD;
end
else
begin
POWER_ON_TO_LC = POWER_ON_FROM_BC;
RELEASE_CLK_TO_LC = RELEASE_CLK_FROM_BC;
RELEASE_RST_TO_LC = RELEASE_RST_FROM_BC;
end
end
always @ *
begin
if (RELEASE_ISO_FROM_SLEEP_CTRL==HOLD)
begin
TX_ACK_TO_LC = 0;
RX_ADDR_TO_LC = 0;
RX_DATA_TO_LC = 0;
RX_REQ_TO_LC = 0;
RX_FAIL_TO_LC = 0;
RX_PEND_TO_LC = 0;
TX_FAIL_TO_LC = 0;
TX_SUCC_TO_LC = 0;
RX_BROADCAST_TO_LC = 0;
RELEASE_ISO_FROM_BC_MASKED = HOLD;
end
else
begin
TX_ACK_TO_LC = TX_ACK_FROM_BC ;
RX_ADDR_TO_LC = RX_ADDR_FROM_BC;
RX_DATA_TO_LC = RX_DATA_FROM_BC;
RX_REQ_TO_LC = RX_REQ_FROM_BC;
RX_FAIL_TO_LC = RX_FAIL_FROM_BC;
RX_PEND_TO_LC = RX_PEND_FROM_BC;
TX_FAIL_TO_LC = TX_FAIL_FROM_BC;
TX_SUCC_TO_LC = TX_SUCC_FROM_BC;
RX_BROADCAST_TO_LC = RX_BROADCAST_FROM_BC;
RELEASE_ISO_FROM_BC_MASKED = RELEASE_ISO_FROM_BC;
end
end
always @ *
begin
if (RELEASE_ISO_FROM_BC_MASKED==HOLD)
begin
TX_ADDR_TO_BC = 0;
TX_DATA_TO_BC = 0;
TX_PEND_TO_BC = 0;
TX_REQ_TO_BC = 0;
PRIORITY_TO_BC = 0;
RX_ACK_TO_BC = 0;
TX_RESP_ACK_TO_BC=0;
end
else
begin
TX_ADDR_TO_BC = TX_ADDR_FROM_LC;
TX_DATA_TO_BC = TX_DATA_FROM_LC;
TX_PEND_TO_BC = TX_PEND_FROM_LC;
TX_REQ_TO_BC = TX_REQ_FROM_LC;
PRIORITY_TO_BC = PRIORITY_FROM_LC;
RX_ACK_TO_BC = RX_ACK_FROM_LC;
TX_RESP_ACK_TO_BC=TX_RESP_ACK_FROM_LC;
end
end
endmodule
|
// fixme: clock gating - возможно делить частоту через ena плохо
//
// http://electronics.stackexchange.com/questions/73398/gated-clocks-and-clock-enables-in-fpga-and-asics
//
//
// learn
//
// fixme: syn 4 tgrs - why?
// https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver-state-machine.html
// Design:
// 1. принимаем пакет с заголовком и контрольной суммой через SPI
// прерывание это не очень хорошая идея, хотя...
// в SPI линия все равно не входит
// fixme: как игнорировать биты по mosi когда читаю?
// z состояние? high-impedance
//
// http://www.cypress.com/file/132126/download - rx/tx irq
//
// просто ничего не передавать - интерфейс полностью синхронный
// http://digitaltimingdiagrams.com/static/articles/SPI.html#/SPIinterfaceDEF
// http://ee.hawaii.edu/~tep/EE491E/Notes/HC11A8/HC11A8_SPI.pdf
// http://www.analog.com/media/en/technical-documentation/application-notes/AN-1248.pdf
module in_fsm (
output reg gnt,
input dly, done, req, clk, rst_n);
// fixme: it's make hot?
parameter [1:0] IDLE = 2'b00,
BBUSY = 2'b01,
BWAIT = 2'b10,
BFREE = 2'b11;
reg [1:0] state;
reg [1:0] next; // fixme: во что синтезируется?
always @(posedge clk
//or posedge rst_n
) begin
// always <= !!!
//if (!rst_n)
// if (rst_n)
// state <= IDLE;
// else
state <= next;
end
// "For combinational blocks
// (blocks that contain no registers or latches)"
// "the sensitivity list must include every
// signal that is !!!read by the process."
always @(state or dly or done or req) begin
// intitialize outputs to avoid latches?
next = 2'bx;
gnt = 1'b0;
case (state)
IDLE:
if (req)
next = BBUSY;
else
next = IDLE;
BBUSY: begin
gnt = 1'b1;
if (!done)
next = BBUSY;
else begin
if ( dly )
next = BWAIT;
else
next = BFREE;
end
end
BWAIT: begin
gnt = 1'b1;
if (!dly)
next = BFREE;
else begin
next = BWAIT;
end
end
BFREE:
if ( req )
next = BBUSY;
else
next = IDLE;
endcase
end
endmodule
// bad
//always @(a)
//c <= a or b; // no in sensitive list
module in_fsm_(
clk,
rst_a,
ena,
// control signals
ready,
// data
src,
snk // snk
);
`define BUS_SIZE 8
input clk;
input rst_a;
input ena;
output ready;
input [`BUS_SIZE-1:0] src;
output snk;
// fixme: можно же память заюзать? но нужно подумать,т.к. она будет одна(?)
// descriptor
// 1. узнаваемый заголовок
// 2. длина
// fixme: как проверить контрольную сумму
// about fsm:
// http://www.asic-world.com/verilog/memory_fsm3.html
// http://web.mit.edu/6.111/www/f2012/handouts/L05.pdf
// fixme: split logic!
// http://www.sunburst-design.com/papers/CummingsICU2002_FSMFundamentals.pdf
// data queue
endmodule
//
//
// Test
//
//
module in_fsm_testbench;
reg clk, rst_a;
wire o_event;
reg [7:0] source;
initial begin
clk = 0;
rst_a = 0;
source = 0;
end
always begin
#5 clk = !clk;
end
// fixme: нужно сгенерировать более менее внятный поток
always @(posedge clk) begin
source <= source + 1;
end
in_fsm_ U0 (
.clk(clk),
.rst_a(rst_a),
.src(source),
.snk(o_event)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int otg = 1 << 30, i; for (i = 0; i < m; i++) { int l, r; cin >> l >> r; if (r - l + 1 < otg) otg = r - l + 1; } cout << otg << endl; for (i = 0; i < n; i++) cout << i % otg << ; cout << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; int b[m]; for (int i = 0; i < m; cin >> b[i++]) ; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (b[j] <= i + 1) { cout << b[j] << ; break; } } } cout << endl; } |
#include <bits/stdc++.h> const int N = 2005; using namespace std; bitset<N> f[N]; int n; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) { int t; scanf( %d , &t); if (t > 0) f[i][j] = 1; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) if (f[i][j]) { f[i] |= f[j]; } } for (int i = 1; i <= n; i++) { for (int j = 1; j <= n; j++) if (f[i][j]) { f[i] |= f[j]; } } for (int i = 1; i <= n; i++) { if (f[i].count() != n) { printf( NO ); return 0; } } printf( YES ); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:06:53 11/19/2013
// Design Name:
// Module Name: top_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top_module(
input clock,
input reset,
input c_pad,
input d_pad,
input e_pad,
input f_pad,
input g_pad,
output lrck,
output mclk,
output sdin,
output[15:0] left_data_o,
output [15:0] right_data_o
);
/** Para generar el clock a 50MHz */
wire clock_50Mhz;
/** Entradas sincronizados */
wire reset_sync, c_pad_sync, d_pad_sync, e_pad_sync, f_pad_sync, g_pad_sync, pad_touched;
/** Variables que contienen los datos de los nco */
wire[15:0] c_data, d_data, e_data, f_data, g_data;
/** Variables que contienen los datos que se mandan al i2s */
wire[15:0] left_data, right_data;
/** Variables para la maquina de estados */
wire play;
/** Genera un clock a 50MHz a partir del de 100MHz del de la spartan */
half_clock_divider half_divider(
.clock(clock),
.reset(reset_sync),
.clock_out(clock_50Mhz)
);
/** Debounce que sincroniza las senales */
debounce debounce_m(
.clock(clock),
.reset(reset),
.c_pad(c_pad),
.d_pad(d_pad),
.e_pad(e_pad),
.f_pad(f_pad),
.g_pad(g_pad),
.reset_sync(reset_sync),
.c_pad_sync(c_pad_sync),
.d_pad_sync(d_pad_sync),
.e_pad_sync(e_pad_sync),
.f_pad_sync(f_pad_sync),
.g_pad_sync(g_pad_sync),
.pad_touched(pad_touched)
);
/** Maquina de estados que le indica al banco de sonidos que puede reproducir */
fsm maquina(
.clock(clock),
.reset(reset_sync),
.play(play),
.pad_touched(pad_touched)
);
/** Modulo que produce la salida para el pmodi2s
Siempre va a estar generando la salida, solo que
si no hay boton presionado va a tirar cero */
i2s_out i2s_generator (
.clock(clock_50Mhz),
.reset(reset_sync),
.right_data(right_data),
.left_data(left_data),
.mclk(mclk),
.lrck(lrck),
.sdin(sdin)
);
/** Banco de sonidos, lo que suena se produce a partir de los botones
presionados */
sounds_bank sonidos(
.lrck(lrck),
.c_pad_sync(c_pad_sync),
.d_pad_sync(d_pad_sync),
.e_pad_sync(e_pad_sync),
.f_pad_sync(f_pad_sync),
.g_pad_sync(g_pad_sync),
.play(play),
.c_data_out(c_data),
.d_data_out(d_data),
.e_data_out(e_data),
.f_data_out(f_data),
.g_data_out(g_data)
);
/** Adder que suma la salida de cada sonido(tono) */
adder sumador(
.c_data(c_data),
.d_data(d_data),
.e_data(e_data),
.f_data(f_data),
.g_data(g_data),
.left_data(left_data),
.right_data(right_data)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m; int mat[505][505]; const int N = 3e5 + 10, C = 26, inf = 1e7; bool check(int i, int j) { if ((i - 1 > 0 || i - 1 == 0) && mat[i - 1][j] == 1) { return 1; } if ((j - 1 > 0 || j - 1 == 0) && mat[i][j - 1] == 1) { return 1; } if (mat[i + 1][j] == 1 && i < n) { return 1; } if (mat[i][j + 1] == 1 && j < m) { return 1; } return 0; } void FUSE() { cin >> n >> m; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { char t; cin >> t; if (t == S ) mat[i][j] = -1; else if (t == W ) mat[i][j] = 1; else mat[i][j] = 0; } } for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (mat[i][j] == -1 && check(i, j)) { cout << No n ; return; } } } cout << Yes n ; for (int i = 0; i < n; i++) { for (int j = 0; j < m; j++) { if (mat[i][j] == -1) cout << S ; else if (mat[i][j] == 1) cout << W ; else cout << D ; } cout << n ; } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int T = 1; while (T--) { FUSE(); } } |
//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2016.2 (lin64) Build Thu Jun 2 16:32:35 MDT 2016
//Date : Thu Jul 27 14:59:42 2017
//Host : wi18as33032 running 64-bit Red Hat Enterprise Linux Workstation release 6.3 (Santiago)
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "design_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=design_1,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=34,numReposBlks=34,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}" *) (* HW_HANDOFF = "design_1.hwdef" *)
module design_1
();
wire [31:0]FIR_resized1_m_axis_data_tdata;
wire FIR_resized1_m_axis_data_tvalid;
wire [31:0]FIR_resized2_m_axis_data_tdata;
wire [31:0]FIR_resized3_m_axis_data_tdata;
wire [31:0]FIR_resized3_m_axis_data_tdata1;
wire FIR_resized3_m_axis_data_tvalid;
wire FIR_resized3_m_axis_data_tvalid1;
wire [31:0]FIR_resized4_m_axis_data_tdata;
wire [31:0]FIR_resized5_m_axis_data_tdata;
wire [31:0]FIR_resized6_m_axis_data_tdata;
wire FIR_resized6_m_axis_data_tvalid;
wire [31:0]FIR_resized7_m_axis_data_tdata;
wire Net;
wire [39:0]cic_compiler_0_m_axis_data_tdata;
wire cic_compiler_0_m_axis_data_tvalid;
wire [47:0]cic_compiler_1_m_axis_data_tdata;
wire cic_compiler_1_m_axis_data_tvalid;
wire [15:0]wavegen_m_axis_data_tdata;
wire wavegen_m_axis_data_tvalid;
wire [15:0]xlconcat_0_dout;
wire [23:0]xlconcat_1_dout;
wire [23:0]xlconcat_2_dout;
wire [23:0]xlconcat_3_dout;
wire [6:0]xlconstant_0_dout;
wire [6:0]xlconstant_1_dout;
wire [1:0]xlconstant_2_dout;
wire [6:0]xlconstant_3_dout;
wire [13:0]xlslice_0_Dout;
wire [0:0]xlslice_10_Dout;
wire [23:0]xlslice_11_Dout;
wire [0:0]xlslice_13_Dout;
wire [23:0]xlslice_15_Dout;
wire [15:0]xlslice_17_Dout;
wire [23:0]xlslice_6_Dout;
wire [15:0]xlslice_7_Dout;
wire [23:0]xlslice_8_Dout;
wire [0:0]xlslice_9_Dout;
design_1_FIR_resized1_1 FIR_resized0
(.aclk(Net),
.m_axis_data_tdata(FIR_resized3_m_axis_data_tdata),
.m_axis_data_tvalid(FIR_resized3_m_axis_data_tvalid),
.s_axis_data_tdata(xlconcat_1_dout),
.s_axis_data_tvalid(cic_compiler_0_m_axis_data_tvalid));
design_1_FIR_resized_0 FIR_resized1
(.aclk(Net),
.m_axis_data_tdata(FIR_resized1_m_axis_data_tdata),
.m_axis_data_tvalid(FIR_resized1_m_axis_data_tvalid),
.s_axis_data_tdata(xlslice_8_Dout),
.s_axis_data_tvalid(FIR_resized3_m_axis_data_tvalid));
design_1_FIR_resized1_0 FIR_resized2
(.aclk(Net),
.m_axis_data_tdata(FIR_resized2_m_axis_data_tdata),
.s_axis_data_tdata(xlslice_6_Dout),
.s_axis_data_tvalid(FIR_resized1_m_axis_data_tvalid));
design_1_FIR_resized1_3 FIR_resized3
(.aclk(Net),
.m_axis_data_tdata(FIR_resized3_m_axis_data_tdata1),
.m_axis_data_tvalid(FIR_resized3_m_axis_data_tvalid1),
.s_axis_data_tdata(xlconcat_2_dout),
.s_axis_data_tvalid(wavegen_m_axis_data_tvalid));
design_1_FIR_resized2_2 FIR_resized4
(.aclk(Net),
.m_axis_data_tdata(FIR_resized4_m_axis_data_tdata),
.s_axis_data_tdata(xlslice_11_Dout),
.s_axis_data_tvalid(FIR_resized3_m_axis_data_tvalid1));
design_1_FIR_resized4_0 FIR_resized5
(.aclk(Net),
.m_axis_data_tdata(FIR_resized5_m_axis_data_tdata),
.s_axis_data_tdata(xlconcat_2_dout),
.s_axis_data_tvalid(wavegen_m_axis_data_tvalid));
design_1_FIR_resized0_0 FIR_resized6
(.aclk(Net),
.m_axis_data_tdata(FIR_resized6_m_axis_data_tdata),
.m_axis_data_tvalid(FIR_resized6_m_axis_data_tvalid),
.s_axis_data_tdata(xlconcat_3_dout),
.s_axis_data_tvalid(cic_compiler_1_m_axis_data_tvalid));
design_1_FIR_resized2_0 FIR_resized7
(.aclk(Net),
.m_axis_data_tdata(FIR_resized7_m_axis_data_tdata),
.s_axis_data_tdata(xlslice_15_Dout),
.s_axis_data_tvalid(FIR_resized6_m_axis_data_tvalid));
design_1_cic_compiler_0_0 cic_compiler_0
(.aclk(Net),
.m_axis_data_tdata(cic_compiler_0_m_axis_data_tdata),
.m_axis_data_tvalid(cic_compiler_0_m_axis_data_tvalid),
.s_axis_data_tdata(xlconcat_0_dout),
.s_axis_data_tvalid(wavegen_m_axis_data_tvalid));
design_1_cic_compiler_0_1 cic_compiler_1
(.aclk(Net),
.m_axis_data_tdata(cic_compiler_1_m_axis_data_tdata),
.m_axis_data_tvalid(cic_compiler_1_m_axis_data_tvalid),
.s_axis_data_tdata(xlconcat_0_dout),
.s_axis_data_tvalid(wavegen_m_axis_data_tvalid));
design_1_clk_gen_0_0 clk
(.clk(Net));
design_1_dds_compiler_0_1 wavegen
(.aclk(Net),
.m_axis_data_tdata(wavegen_m_axis_data_tdata),
.m_axis_data_tvalid(wavegen_m_axis_data_tvalid));
design_1_xlconcat_0_0 xlconcat_0
(.In0(xlconstant_2_dout),
.In1(xlslice_0_Dout),
.dout(xlconcat_0_dout));
design_1_xlconcat_0_1 xlconcat_1
(.In0(xlconstant_0_dout),
.In1(xlslice_7_Dout),
.In2(xlslice_9_Dout),
.dout(xlconcat_1_dout));
design_1_xlconcat_1_0 xlconcat_2
(.In0(xlconstant_1_dout),
.In1(xlconcat_0_dout),
.In2(xlslice_13_Dout),
.dout(xlconcat_2_dout));
design_1_xlconcat_1_1 xlconcat_3
(.In0(xlconstant_3_dout),
.In1(xlslice_17_Dout),
.In2(xlslice_10_Dout),
.dout(xlconcat_3_dout));
design_1_xlconstant_0_0 xlconstant_0
(.dout(xlconstant_0_dout));
design_1_xlconstant_0_1 xlconstant_1
(.dout(xlconstant_1_dout));
design_1_xlconstant_2_0 xlconstant_2
(.dout(xlconstant_2_dout));
design_1_xlconstant_0_2 xlconstant_3
(.dout(xlconstant_3_dout));
design_1_xlslice_0_1 xlslice_0
(.Din(wavegen_m_axis_data_tdata),
.Dout(xlslice_0_Dout));
design_1_xlslice_9_1 xlslice_10
(.Din(xlslice_17_Dout),
.Dout(xlslice_10_Dout));
design_1_xlslice_6_3 xlslice_11
(.Din(FIR_resized3_m_axis_data_tdata1),
.Dout(xlslice_11_Dout));
design_1_xlslice_4_2 xlslice_12
(.Din(FIR_resized4_m_axis_data_tdata));
design_1_xlslice_9_0 xlslice_13
(.Din(xlconcat_0_dout),
.Dout(xlslice_13_Dout));
design_1_xlslice_6_2 xlslice_14
(.Din(FIR_resized7_m_axis_data_tdata));
design_1_xlslice_14_0 xlslice_15
(.Din(FIR_resized6_m_axis_data_tdata),
.Dout(xlslice_15_Dout));
design_1_xlslice_12_0 xlslice_16
(.Din(FIR_resized5_m_axis_data_tdata));
design_1_xlslice_7_2 xlslice_17
(.Din(cic_compiler_1_m_axis_data_tdata),
.Dout(xlslice_17_Dout));
design_1_xlslice_4_0 xlslice_4
(.Din(FIR_resized2_m_axis_data_tdata));
design_1_xlslice_6_0 xlslice_6
(.Din(FIR_resized1_m_axis_data_tdata),
.Dout(xlslice_6_Dout));
design_1_xlslice_6_1 xlslice_7
(.Din(cic_compiler_0_m_axis_data_tdata),
.Dout(xlslice_7_Dout));
design_1_xlslice_7_0 xlslice_8
(.Din(FIR_resized3_m_axis_data_tdata),
.Dout(xlslice_8_Dout));
design_1_xlslice_3_0 xlslice_9
(.Din(xlslice_7_Dout),
.Dout(xlslice_9_Dout));
endmodule
|
#include <bits/stdc++.h> using namespace std; vector<long long> v[10001]; long long n, ass1, ass2; int main() { v[1].push_back(1); v[1].push_back(2); v[2].push_back(1); v[2].push_back(3); v[3].push_back(2); v[3].push_back(3); cin >> n; ass1 = ass2 = 3; while (ass1 + ass2 <= n) { v[1].push_back(ass2 + 1); v[ass1 + 1].push_back(ass2 + 1); for (int i = 2; i <= ass1; i++) { v[i].push_back(ass2 + i); v[ass1 + 1].push_back(ass2 + i); } ass2 += ass1; ass1++; } cout << ass1 << endl; for (int i = 1; i <= ass1; i++) { for (int j = 0; j < v[i].size(); j++) { if (j != 0) cout << ; cout << v[i][j]; } cout << endl; } return 0; } |
`define ADDER_WIDTH 024
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
(* blackbox *)
module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
addressstall_a, addressstall_b);
parameter clock_enable_input_b = "ALTERNATE";
parameter clock_enable_input_a = "ALTERNATE";
parameter clock_enable_output_b = "NORMAL";
parameter clock_enable_output_a = "NORMAL";
parameter wrcontrol_aclr_a = "NONE";
parameter indata_aclr_a = "NONE";
parameter address_aclr_a = "NONE";
parameter outdata_aclr_a = "NONE";
parameter outdata_reg_a = "UNREGISTERED";
parameter operation_mode = "SINGLE_PORT";
parameter intended_device_family = "MAX 10 FPGA";
parameter outdata_reg_b = "UNREGISTERED";
parameter lpm_type = "altsyncram";
parameter init_type = "unused";
parameter ram_block_type = "AUTO";
parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
parameter power_up_uninitialized = "FALSE";
parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ";
parameter width_byteena_a = 1;
parameter numwords_b = 0;
parameter numwords_a = 0;
parameter widthad_b = 1;
parameter width_b = 1;
parameter widthad_a = 1;
parameter width_a = 1;
// Port A declarations
output [35:0] q_a;
input [35:0] data_a;
input [7:0] address_a;
input wren_a;
input rden_a;
// Port B declarations
output [35:0] q_b;
input [35:0] data_b;
input [7:0] address_b;
input wren_b;
input rden_b;
// Control signals
input clock0, clock1;
input clocken0, clocken1, clocken2, clocken3;
input aclr0, aclr1;
input addressstall_a;
input addressstall_b;
// TODO: Implement the correct simulation model
endmodule // altsyncram
|
#include <bits/stdc++.h> using namespace std; int n, m, f, vis[101][101][101]; char a[1001][1001]; int valid(int x, int y) { return (x >= 1 && x <= n && y >= 1 && y <= m); } int occupies(int x, int y, int turn) { y = y + (turn - 1) * 2; if (valid(x, y) && a[x][y] >= A && a[x][y] <= Z ) return 1; return 0; } void dfs(int curx, int cury, int turn) { if (cury == m) { f = 1; return; } if (vis[curx][cury][turn]) return; if (occupies(curx, cury, turn)) return; vis[curx][cury][turn] = 1; if (!occupies(curx, cury + 1, turn)) { if (valid(curx, cury + 1) && !occupies(curx, cury + 1, turn)) dfs(curx, cury + 1, turn + 1); if (valid(curx - 1, cury + 1) && !occupies(curx - 1, cury + 1, turn)) dfs(curx - 1, cury + 1, turn + 1); if (valid(curx + 1, cury + 1) && !occupies(curx + 1, cury + 1, turn)) dfs(curx + 1, cury + 1, turn + 1); } } int main() { ios::sync_with_stdio(false); ; cin.tie(0); ; int i, j, t, sx, sy, temp; string st; cin >> t; while (t--) { memset(vis, 0, sizeof vis); cin >> m >> temp; n = 3; for (i = 1; i <= n; i++) { cin >> st; st = + st; for (j = 1; j <= m; j++) { a[i][j] = st[j]; if (a[i][j] == s ) { sx = i; sy = j; } } } f = 0; dfs(sx, sy, 1); if (f) cout << YES << endl; else cout << NO << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const long long LL_INF = 0x3f3f3f3f3f3f3f3f; const int maxn = 3e5 + 10; const int mod = 1e9 + 7; long long a[maxn]; int main() { long long n, m; scanf( %I64d%I64d , &n, &m); for (int i = 0; i < n; i++) { scanf( %I64d , &a[i]); } int now = 0; for (int i = 0; i < n; i++) { printf( %I64d%c , (a[i] + now) / m, n [i == n - 1]); now = (a[i] + now) % m; } } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2015/03/31 15:48:05
// Design Name:
// Module Name: wildcard_counter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module wildcard_counter
#(parameter ADDR_WIDTH=4,
parameter PKT_WIDTH=12,
parameter LUT_DEPTH=16,
parameter DEPTH_BITS=4
)
(
input clk,
input reset,
output fifo_rd_en,
input [PKT_WIDTH-1:0]dout_pkt_size,
input wildcard_data_vld,
input wildcard_hit,
input [DEPTH_BITS-1:0]wildcard_address,
input [DEPTH_BITS-1:0] counter_addr_in,
input counter_addr_rd,
output reg [31:0]pkt_counter_out,
output reg [31:0]byte_counter_out
);
`ifdef ONETS45
begin
reg [31:0]byte_count[LUT_DEPTH-1:0];
reg [31:0]pkt_count [LUT_DEPTH-1:0];
reg [DEPTH_BITS-1:0]wildcard_address_d;
assign fifo_rd_en=wildcard_data_vld;
reg wildcard_hit_d;
always@(posedge clk)
wildcard_hit_d<=wildcard_hit;
localparam CLEAR=0,
IDLE=1;
reg [DEPTH_BITS-1:0]clear_count;
reg [2:0]cur_st,nxt_st;
always@(posedge clk)
if(reset) wildcard_address_d<=0;
else wildcard_address_d<=wildcard_address;
always@(posedge clk)
if(reset) cur_st<=0;
else cur_st<=nxt_st;
always@(*)
begin
nxt_st=cur_st;
case(cur_st)
CLEAR:if(clear_count==LUT_DEPTH-1) nxt_st=IDLE;
IDLE:nxt_st=IDLE;
default:nxt_st=IDLE;
endcase
end
always@(posedge clk)
if(reset)
clear_count<=0;
else if(cur_st==CLEAR) clear_count<=clear_count+1;
always@(posedge clk)
if(cur_st==CLEAR)
begin
byte_count[clear_count]<=0;
pkt_count[clear_count]<=0;
end
else if(cur_st==IDLE && wildcard_hit_d)
begin
byte_count[wildcard_address_d]<=byte_count[wildcard_address_d]+dout_pkt_size+4;
pkt_count[wildcard_address_d]<=pkt_count[wildcard_address_d]+1;
end
always@(posedge clk)
if(reset)
pkt_counter_out<=0;
else if(counter_addr_rd)
pkt_counter_out<=pkt_count[counter_addr_in];
always@(posedge clk)
if(reset)
byte_counter_out<=0;
else if(counter_addr_rd)
byte_counter_out<=byte_count[counter_addr_in];
end
`elsif ONETS30
begin
reg [31:0]byte_count[LUT_DEPTH-1:0];
reg [31:0]pkt_count [LUT_DEPTH-1:0];
reg [DEPTH_BITS-1:0]wildcard_address_d;
assign fifo_rd_en=wildcard_data_vld;
reg wildcard_hit_d;
always@(posedge clk)
wildcard_hit_d<=wildcard_hit;
localparam CLEAR=0,
IDLE=1;
reg [DEPTH_BITS-1:0]clear_count;
reg [2:0]cur_st,nxt_st;
always@(posedge clk)
if(reset) wildcard_address_d<=0;
else wildcard_address_d<=wildcard_address;
always@(posedge clk)
if(reset) cur_st<=0;
else cur_st<=nxt_st;
always@(*)
begin
nxt_st=cur_st;
case(cur_st)
CLEAR:if(clear_count==LUT_DEPTH-1) nxt_st=IDLE;
IDLE:nxt_st=IDLE;
default:nxt_st=IDLE;
endcase
end
always@(posedge clk)
if(reset)
clear_count<=0;
else if(cur_st==CLEAR) clear_count<=clear_count+1;
always@(posedge clk)
if(cur_st==CLEAR)
begin
byte_count[clear_count]<=0;
pkt_count[clear_count]<=0;
end
else if(cur_st==IDLE && wildcard_hit_d)
begin
byte_count[wildcard_address_d]<=byte_count[wildcard_address_d]+dout_pkt_size+4;
pkt_count[wildcard_address_d]<=pkt_count[wildcard_address_d]+1;
end
always@(posedge clk)
if(reset)
pkt_counter_out<=0;
else if(counter_addr_rd)
pkt_counter_out<=pkt_count[counter_addr_in];
always@(posedge clk)
if(reset)
byte_counter_out<=0;
else if(counter_addr_rd)
byte_counter_out<=byte_count[counter_addr_in];
end
`elsif ONETS20
always@(*)
begin
pkt_counter_out=0;
byte_counter_out=0;
end
`endif
endmodule
|
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAMB16_S4_altera.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module RAMB16_S4_altera (
address,
clken,
clock,
data,
wren,
q);
input [11:0] address;
input clken;
input clock;
input [3:0] data;
input wren;
output [3:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clken;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sources_ngnp_multicore/src/lr0_0.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "4"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sources_ngnp_multicore/src/lr0_0.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL "data[3..0]"
// Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL "q[3..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 4 0 data 0 0 4 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAMB16_S4_altera_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, c = 0; cin >> n; for (long long i = 1; i < n; ++i) { if (n % i == 0) c++; } cout << c << endl; return 0; } |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* Testbench for the non-synthesizable behavioral model for the
* data memory
*/
// Import the modules that will be tested for in this testbench
`include "datamem.v"
// Include definition of the control signals
`include "control.h"
// IMPORTANT: To run this, try: ncverilog -f datamem.f +gui
module tb_datamem ();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the data memory
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// data_output
wire [0:127] data_output;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// dm_ctrl_sig
reg [0:1] data_memory_control_signal;
// mem_ctrl_addr output signals
reg [0:31] memory_control_address;
// data_input
reg [0:127] data_input;
reg clock;
reg [0:31] counter;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
parameter size_of_input = 6'd32;
parameter size_of_input2 = 4'd8;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
/**
* Clock frequency is arbitrarily chosen;
* Period = 10ns <==> 100 MHz clock
*/
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of instr_mem() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "im"
*/
data_mem dm (
// instance_name(signal name),
// Signal name can be the same as the instance name
// data_out,data_in,mem_ctrl_addr,clk,dm_ctrl_sig
data_output,data_input,memory_control_address,
clock,data_memory_control_signal);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
//data_input=$random;
data_input=128'h71;
memory_control_address=32'd0;
data_memory_control_signal=`memnop;
counter=32'd1;
#29
//data_input=$random;
data_input=128'h72;
memory_control_address=counter;
data_memory_control_signal=`memwst;
counter=counter+32'd1;
// data_memory_control_signal=10;
/*
instruction_address=8'd200;
reset=1'b0;
*/
// Try reading the instruction memory without being reset
for(count=0;count<=size_of_input2;count=count+1)
begin
#10
//data_input=$random;
data_input=data_input+128'd1;
memory_control_address=counter;
data_memory_control_signal=`memwst;
//data_memory_control_signal=10;
counter=counter+32'd1;
end
counter=32'd1;
// Read the instruction memory after being reset
for(count=0;count<=size_of_input2;count=count+1)
begin
#10
data_input=$random;
memory_control_address=counter;
data_memory_control_signal=`memwld;
//data_memory_control_signal=01;
counter=counter+32'd1;
end
// NOP operation - set the output to ZEROs
#10
data_input=$random;
memory_control_address=counter;
data_memory_control_signal=`memnop;
// data_memory_control_signal=10;
// counter=counter+32'd1;
#10
data_input=$random;
memory_control_address=counter;
data_memory_control_signal=`memwld;
//data_memory_control_signal=01;
counter=counter+32'd1;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
// Ask Bhatti what is the size of a byte - dependent on subfield?
endmodule
|
#include <bits/stdc++.h> const int mod = 1000000007, maxn = 200005, maxk = 105; int n, m; int a[maxn], fac[maxn], nfac[maxn], inv[maxn], sum[maxn][maxk]; inline int C(int a, int b) { return 1ll * fac[a] * nfac[b] % mod * nfac[a - b] % mod; } int main() { fac[0] = fac[1] = nfac[0] = nfac[1] = inv[1] = 1; for (int i = 2; i <= 200000; i++) fac[i] = 1ll * fac[i - 1] * i % mod, inv[i] = mod - 1ll * (mod / i) * inv[mod % i] % mod, nfac[i] = 1ll * nfac[i - 1] * inv[i] % mod; scanf( %d%d , &n, &m); for (int i = 1; i <= n; i++) scanf( %d , &a[i]); for (int i = 1; i <= m; i++) { int l, r, k; scanf( %d%d%d , &l, &r, &k); for (int j = 0; j <= k; j++) { sum[l][j] = (sum[l][j] + C(k, k - j)) % mod; sum[r + 1][j] = (sum[r + 1][j] - C(k + r - l + 1, k - j) + mod) % mod; } } for (int i = 1; i <= n; i++) for (int j = 100; j >= 0; j--) sum[i][j] = (sum[i][j] + (sum[i - 1][j + 1] + sum[i - 1][j]) % mod) % mod; for (int i = 1; i <= n; i++) printf( %d%c , (a[i] + sum[i][0]) % mod, i == n ? n : ); return 0; } |
#include <iostream> #include <vector> #include <algorithm> using namespace std; int main() { int testCase; cin >> testCase; while (testCase--) { vector<int> balls; int ball; cin >> ball; while (ball--) { int num; cin >> num; balls.push_back(num); } int maxNum = 1; int lastNum = balls[0]; int count = 1; for (int i = 1;i < balls.size();i++) { if (balls[i] != lastNum) { lastNum = balls[i]; maxNum = max(count, maxNum); count = 1; } else { count++; } } maxNum = max(count, maxNum); cout << maxNum << endl; } return 0; } |
//------------------------------------------------------------------------
//--
//-- Filename : xlconcat.v
//--
//-- Date : 06/05/12
//-
//- Description : Verilog description of a concat block. This
//- block does not use a core.
//-
//-----------------------------------------------------------------------
module xlconcat (In0, In1, In2, In3, In4, In5, In6, In7, In8, In9, In10, In11, In12, In13, In14, In15,dout);
parameter IN0_WIDTH = 1;
input [IN0_WIDTH -1:0] In0;
parameter IN1_WIDTH = 1;
input [IN1_WIDTH -1:0] In1;
parameter IN2_WIDTH = 1;
input [IN2_WIDTH -1:0] In2;
parameter IN3_WIDTH = 1;
input [IN3_WIDTH -1:0] In3;
parameter IN4_WIDTH = 1;
input [IN4_WIDTH -1:0] In4;
parameter IN5_WIDTH = 1;
input [IN5_WIDTH -1:0] In5;
parameter IN6_WIDTH = 1;
input [IN6_WIDTH -1:0] In6;
parameter IN7_WIDTH = 1;
input [IN7_WIDTH -1:0] In7;
parameter IN8_WIDTH = 1;
input [IN8_WIDTH -1:0] In8;
parameter IN9_WIDTH = 1;
input [IN9_WIDTH -1:0] In9;
parameter IN10_WIDTH = 1;
input [IN10_WIDTH -1:0] In10;
parameter IN11_WIDTH = 1;
input [IN11_WIDTH -1:0] In11;
parameter IN12_WIDTH = 1;
input [IN12_WIDTH -1:0] In12;
parameter IN13_WIDTH = 1;
input [IN13_WIDTH -1:0] In13;
parameter IN14_WIDTH = 1;
input [IN14_WIDTH -1:0] In14;
parameter IN15_WIDTH = 1;
input [IN15_WIDTH -1:0] In15;
parameter dout_width = 2;
output [dout_width-1:0] dout;
parameter NUM_PORTS =2;
generate if (NUM_PORTS == 1)
begin : C_NUM_1
assign dout = In0;
end
endgenerate
generate if (NUM_PORTS == 2)
begin : C_NUM_2
assign dout = {In1,In0};
end
endgenerate
generate if (NUM_PORTS == 3)
begin:C_NUM_3
assign dout = {In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 4)
begin:C_NUM_4
assign dout = {In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 5)
begin:C_NUM_5
assign dout = {In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 6)
begin:C_NUM_6
assign dout = {In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 7)
begin:C_NUM_7
assign dout = {In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 8)
begin:C_NUM_8
assign dout = {In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 9)
begin:C_NUM_9
assign dout = {In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 10)
begin:C_NUM_10
assign dout = {In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 11)
begin:C_NUM_11
assign dout = {In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 12)
begin:C_NUM_12
assign dout = {In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 13)
begin:C_NUM_13
assign dout = {In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 14)
begin:C_NUM_14
assign dout = {In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 15)
begin:C_NUM_15
assign dout = {In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
generate if (NUM_PORTS == 16)
begin:C_NUM_16
assign dout = {In15, In14, In13, In12, In11, In10, In9, In8, In7, In6, In5, In4, In3, In2, In1, In0};
end
endgenerate
endmodule |
#include <bits/stdc++.h> using namespace std; const long long N = 1e3 + 5; long long C[N][5], dif_fact[5]; void calc() { for (long long i = 0; i < N; i++) { for (long long j = 0; j <= min(i, 4LL); j++) { if (j == 0 || j == i) { C[i][j] = 1; } else { C[i][j] = C[i - 1][j - 1] + C[i - 1][j]; } } } dif_fact[1] = 0; dif_fact[2] = 1; dif_fact[3] = 2; dif_fact[4] = 9; } signed main() { ios_base ::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; calc(); long long n, k; cin >> n >> k; long long ans = 1; for (long long i = 2; i <= k; i++) { long long curr = C[n][i] * dif_fact[i]; ans += curr; } cout << ans; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); long long n, i = 0, j, k = 0, l = 0, m = 10e9, a = 0, b = 0, c, sum = 0, x = 0, y = 0, z = 0; cin >> n; long long arr[n + 1]; for (i = 1; i <= n; i++) { cin >> arr[i]; arr[i] = arr[i] / max(i - 1, n - i); } for (i = 1; i <= n; i++) { l = arr[i]; m = min(m, l); } cout << m; return 0; } |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_bram_7vx_8k.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_bram_7vx_8k.v //
// Description : Implements 8 KB Dual Ported Memory //
// - Output Regs are always enabled //
// - if INTERFACE_SPEED = 500 MHz -> 4xRAMB36E1 in TDP mode //
// - if INTERFACE_SPEED = 250 MHz -> 2xRAMB36E1 in SDP mode //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_8k.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_bram_7vx_8k #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [8:0] waddr0_i, // write address
input [8:0] waddr1_i, // write address
input [127:0] wdata_i, // write data
input [15:0] wdip_i, // write parity
input [3:0] wen_i, // write enable
input [8:0] raddr0_i, // write address
input [8:0] raddr1_i, // write address
output [127:0] rdata_o, // read data
output [15:0] rdop_o, // read parity
input [3:0] ren_i // read enable
);
genvar i;
wire [3:0] wen = {wen_i[3], wen_i[2], wen_i[1], wen_i[0]};
wire [3:0] ren = {ren_i[3], ren_i[2], ren_i[1], ren_i[0]};
wire [35:0] waddr = {waddr1_i, waddr1_i, waddr0_i, waddr0_i};
wire [35:0] raddr = {raddr1_i, raddr1_i, raddr0_i, raddr0_i};
generate
for (i = 0; i < 4; i = i + 1) begin : RAMB18E1
RAMB18E1 #(
.SIM_DEVICE ("7SERIES"),
.DOA_REG ( 1 ),
.DOB_REG ( 1 ),
.SRVAL_A ( 36'h00000 ),
.INIT_FILE ( "NONE" ),
.RAM_MODE ( "SDP" ),
.READ_WIDTH_A ( 36 ),
.READ_WIDTH_B ( 0 ),
.RSTREG_PRIORITY_A ( "REGCE" ),
.RSTREG_PRIORITY_B ( "REGCE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.INIT_A ( 36'h00000 ),
.INIT_B ( 36'h00000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.WRITE_WIDTH_A ( 0 ),
.WRITE_WIDTH_B ( 36 ),
.SRVAL_B ( 36'h00000 ))
u_fifo (
.CLKARDCLK(clk_i),
.CLKBWRCLK(clk_i),
.ENARDEN(ren[i]),
.ENBWREN(1'b1),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0 ),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.ADDRARDADDR({raddr[(9*i)+8:(9*i)+0], 5'b0}),
.ADDRBWRADDR({waddr[(9*i)+8:(9*i)+0], 5'b0}),
.DIADI(wdata_i[(2*16*i)+15:(2*16*i)+0]),
.DIBDI(wdata_i[(2*16*i)+31:(2*16*i)+16]),
.DIPADIP(wdip_i[(2*2*i)+1:(2*2*i)+0]),
.DIPBDIP(wdip_i[(2*2*i)+3:(2*2*i)+2]),
.DOADO(rdata_o[(2*16*i)+15:(2*16*i)+0]),
.DOBDO(rdata_o[(2*16*i)+31:(2*16*i)+16]),
.DOPADOP(rdop_o[(2*2*i)+1:(2*2*i)+0]),
.DOPBDOP(rdop_o[(2*2*i)+3:(2*2*i)+2]),
.WEA({2'b00}),
.WEBWE({4{wen[i]}})
);
end
endgenerate
endmodule // pcie_bram_7vx_8k
|
//-----------------------------------------------------
// Design Name : parallel_crc_ccitt
// File Name : parallel_crc.v
// Function : CCITT Parallel CRC
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module parallel_crc_ccitt (
clk ,
reset ,
enable ,
init ,
data_in ,
crc_out
);
//-----------Input Ports---------------
input clk ;
input reset ;
input enable ;
input init ;
input [7:0] data_in ;
//-----------Output Ports---------------
output [15:0] crc_out;
//------------Internal Variables--------
reg [15:0] crc_reg;
wire [15:0] next_crc;
//-------------Code Start-----------------
assign crc_out = crc_reg;
// CRC Control logic
always @ (posedge clk)
if (reset) begin
crc_reg <= 16'hFFFF;
end else if (enable) begin
if (init) begin
crc_reg <= 16'hFFFF;
end else begin
crc_reg <= next_crc;
end
end
// Parallel CRC calculation
assign next_crc[0] = data_in[7] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[11];
assign next_crc[1] = data_in[1] ^ crc_reg[5];
assign next_crc[2] = data_in[2] ^ crc_reg[6];
assign next_crc[3] = data_in[3] ^ crc_reg[7];
assign next_crc[4] = data_in[4] ^ crc_reg[8];
assign next_crc[5] = data_in[7] ^ data_in[5] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[9] ^ crc_reg[11];
assign next_crc[6] = data_in[6] ^ data_in[1] ^ crc_reg[5] ^ crc_reg[10];
assign next_crc[7] = data_in[7] ^ data_in[2] ^ crc_reg[6] ^ crc_reg[11];
assign next_crc[8] = data_in[3] ^ crc_reg[0] ^ crc_reg[7];
assign next_crc[9] = data_in[4] ^ crc_reg[1] ^ crc_reg[8];
assign next_crc[10] = data_in[5] ^ crc_reg[2] ^ crc_reg[9];
assign next_crc[11] = data_in[6] ^ crc_reg[3] ^ crc_reg[10];
endmodule
|
#include <bits/stdc++.h> using namespace std; bool light[123456]; vector<int> v[123456]; bool visited[123456]; int connected[123456]; int main() { int n; cin >> n; string s, t; vector<string> rat, man, woman, child, capt; for (__typeof(n) i = (0) - ((0) > (n)); i != (n) - ((0) > (n)); i += 1 - 2 * ((0) > (n))) { cin >> s >> t; if (t == rat ) rat.push_back(s); else if (t == captain ) capt.push_back(s); else if (t == woman || t == child ) woman.push_back(s); else if (t == man ) man.push_back(s); } for (__typeof(rat.size()) i = (0) - ((0) > (rat.size())); i != (rat.size()) - ((0) > (rat.size())); i += 1 - 2 * ((0) > (rat.size()))) cout << rat[i] << endl; for (__typeof(woman.size()) i = (0) - ((0) > (woman.size())); i != (woman.size()) - ((0) > (woman.size())); i += 1 - 2 * ((0) > (woman.size()))) cout << woman[i] << endl; for (__typeof(man.size()) i = (0) - ((0) > (man.size())); i != (man.size()) - ((0) > (man.size())); i += 1 - 2 * ((0) > (man.size()))) cout << man[i] << endl; cout << capt[0] << endl; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; ll c[10]; int dx[] = {1, 0, -1, -1, 0, 1}; int dy[] = {1, 1, 0, -1, -1, 0}; int main() { int t; cin >> t; while (t--) { ll x, y; cin >> x >> y; for (int i = 0; i < 6; ++i) cin >> c[i]; long long ans = 5e18; auto sign = [](long long x) { if (x == 0) return 0; if (x < 0) return -1; return 1; }; for (int i = 0; i < 6; ++i) { for (int j = i; j < 6; ++j) { int det = dx[i] * dy[j] - dx[j] * dy[i]; assert(abs(det) <= 1); if (det != 0) { long long t1 = x * dy[j] - y * dx[j]; long long t2 = dx[i] * y - dy[i] * x; t1 /= det; t2 /= det; if (t1 >= 0 && t2 >= 0) { ans = min(ans, abs(t1) * c[i] + abs(t2) * c[j]); } } else { if (sign(x) == dx[i] && sign(y) == dy[i]) { long long res = 0; if (dx[i] != 0) res += abs(x) * c[i]; else if (dy[i] != 0) res += abs(y) * c[i]; if (x == 0 || y == 0 || x == y) { ans = min(ans, res); } } if (sign(x) == dx[j] && sign(y) == dy[j]) { long long res = 0; if (dx[j] != 0) res += abs(x) * c[j]; else if (dy[j] != 0) res += abs(y) * c[j]; if (x == 0 || y == 0 || x == y) { ans = min(ans, res); } } } } } cout << ans << endl; } return 0; } |
// file: system_clk_wiz_0_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____11.900______0.000______50.0______394.277____301.475
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module system_clk_wiz_0_0_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
// Status and control signals
output locked,
input clk_in1
);
// Input buffering
//------------------------------------
wire clk_in1_system_clk_wiz_0_0;
wire clk_in2_system_clk_wiz_0_0;
IBUF clkin1_ibufg
(.O (clk_in1_system_clk_wiz_0_0),
.I (clk_in1));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_system_clk_wiz_0_0;
wire clk_out2_system_clk_wiz_0_0;
wire clk_out3_system_clk_wiz_0_0;
wire clk_out4_system_clk_wiz_0_0;
wire clk_out5_system_clk_wiz_0_0;
wire clk_out6_system_clk_wiz_0_0;
wire clk_out7_system_clk_wiz_0_0;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_system_clk_wiz_0_0;
wire clkfbout_buf_system_clk_wiz_0_0;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT_F (44.625),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (75.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_system_clk_wiz_0_0),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_system_clk_wiz_0_0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_system_clk_wiz_0_0),
.CLKIN1 (clk_in1_system_clk_wiz_0_0),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0));
assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_system_clk_wiz_0_0),
.I (clkfbout_system_clk_wiz_0_0));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_system_clk_wiz_0_0));
endmodule
|
#include <bits/stdc++.h> const long long mod = 1000000007; const long long Inf = 1e9; using namespace std; bool valid(string s) { for (int i = 0; i < s.length(); ++i) { if (s[i] == || s[i] == # ) { if (s[i] == # ) return true; } else return false; } return false; } string wtSpace(string s) { string res = ; for (int i = 0; i < s.length(); ++i) { if (s[i] != ) res += s[i]; } return res; } int main() { int n, a, d; scanf( %d %d %d , &n, &a, &d); vector<double> ans(n); for (int i = 0; i < n; i++) { int t, v; scanf( %d %d , &t, &v); double time = pow(2 * d / (double)a, 0.5); double time2 = v / (double)a; if (time <= time2) ans[i] = t + time; else { double x = a * pow(time2, 2) / 2.0; ans[i] = t + time2 + (d - x) / (double)v; } } for (int i = 0; i < n - 1; i++) { if (ans[i + 1] < ans[i]) ans[i + 1] = ans[i]; printf( %.6f n , ans[i]); } printf( %.6f n , ans[n - 1]); return 0; } |
#include <bits/stdc++.h> using namespace std; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } const int MAXLEN = 15; long long dp[MAXLEN + 1][2]; long long dpleq[MAXLEN + 1][2]; inline int conv(char c) { if (isdigit(c)) return c - 0 ; if (islower(c)) return c - a + 10; assert(false); } long long calc(char* s) { int slen = strlen(s); long long ret = 0; for (int mx = (0); mx < (16); ++mx) { int pos = mx / 4, off = mx % 4; if (pos >= slen) continue; memset(dp, 0, sizeof(dp)); memset(dpleq, 0, sizeof(dpleq)); dp[0][0] = dpleq[0][0] = 1; for (int i = (0); i < (slen); ++i) for (int j = (0); j < (2); ++j) for (int k = (0); k <= (mx); ++k) { if (i == pos && (k & (1 << off)) == 0) continue; int nj = j == 1 || k == mx ? 1 : 0; dp[i + 1][nj] += dp[i][j]; if (k < conv(s[i])) dpleq[i + 1][nj] += dp[i][j]; else if (k == conv(s[i])) dpleq[i + 1][nj] += dpleq[i][j]; } long long cur = dpleq[slen][1]; ret += cur; } return ret; } void dec(char* s) { for (int i = 0;; ++i) if (s[i] == 0 ) s[i] = f ; else { assert(s[i] != 0 ); if (s[i] == a ) s[i] = 9 ; else --s[i]; break; } int slen = strlen(s); while (slen >= 2 && s[slen - 1] == 0 ) --slen; s[slen] = 0 ; } int nq; char sl[MAXLEN + 1], sr[MAXLEN + 1]; long long solve() { reverse(sl, sl + strlen(sl)); reverse(sr, sr + strlen(sr)); long long ret = calc(sr); if (strcmp(sl, 0 ) != 0) { dec(sl); ret -= calc(sl); } return ret; } void run() { scanf( %d , &nq); for (int qi = (0); qi < (nq); ++qi) { scanf( %s%s , sl, sr); printf( %lld n , solve()); } } int main() { run(); return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2021 by Geza Lore. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
module testbench(
/*AUTOARG*/
// Inputs
clk
);
input clk;
int cnt = 0;
export "DPI-C" function set_cnt;
function void set_cnt(int val);
cnt = val;
endfunction;
export "DPI-C" function get_cnt;
function int get_cnt();
return cnt;
endfunction;
always @(posedge clk) cnt += 1;
// Downstream combinational signal dependent on both input clock and
// DPI export.
wire dependent_clk = cnt == 2;
int n = 0;
always @(posedge dependent_clk) begin
$display("t=%t n=%d", $time, n);
if ($time != (8*n+3) * 500) $stop;
if (n == 20) begin
$write("*-* All Finished *-*\n");
$finish;
end
n += 1;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const double PI = 3.141592653589793238460; using namespace std; const int N = 200200; vector<int> g[N]; int w[N], vis[N], done[N]; int can_back[N]; int n, m, s; long long maximum = 0; void dfs(int u, int par) { vis[u] = 1; for (auto v : g[u]) { if (v == par) continue; if (vis[v]) can_back[v] = 1; else dfs(v, u); if (can_back[v] == 1) can_back[u] = 1; } } void findmax(int u, long long sum) { done[u] = 1; if (g[u].size() == 1 and u != s) { sum += w[u]; maximum = max(maximum, sum); return; } if (can_back[u] == 0) sum += w[u]; for (auto v : g[u]) { if (!done[v]) findmax(v, sum); } } int main() { ios_base::sync_with_stdio(false); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 1; i <= n; i++) { cin >> w[i]; } for (int i = 1; i <= m; i++) { int u, v; cin >> u >> v; g[u].push_back(v); g[v].push_back(u); } cin >> s; can_back[s] = 1; dfs(s, 0); long long ans = 0; for (int i = 1; i <= n; i++) { if (can_back[i] == 1) ans += w[i]; } findmax(s, 0); ans += maximum; cout << ans; return 0; } |
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