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`timescale 1 ns / 1 ps
module axis_pulse_height_analyzer #
(
parameter integer AXIS_TDATA_WIDTH = 16,
parameter AXIS_TDATA_SIGNED = "FALSE",
parameter integer CNTR_WIDTH = 16
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire bln_flag,
input wire [AXIS_TDATA_WIDTH-1:0] bln_data,
input wire [CNTR_WIDTH-1:0] cfg_data,
input wire [AXIS_TDATA_WIDTH-1:0] min_data,
input wire [AXIS_TDATA_WIDTH-1:0] max_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [AXIS_TDATA_WIDTH-1:0] int_data_reg[1:0], int_data_next[1:0];
reg [AXIS_TDATA_WIDTH-1:0] int_min_reg, int_min_next;
reg [AXIS_TDATA_WIDTH-1:0] int_tdata_reg, int_tdata_next;
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next;
reg int_enbl_reg, int_enbl_next;
reg int_rising_reg, int_rising_next;
reg int_tvalid_reg, int_tvalid_next;
wire [AXIS_TDATA_WIDTH-1:0] int_tdata_wire, int_min_wire;
wire int_mincut_wire, int_maxcut_wire, int_rising_wire, int_delay_wire;
assign int_delay_wire = int_cntr_reg < cfg_data;
assign int_min_wire = bln_flag ? int_min_reg : bln_data;
generate
if(AXIS_TDATA_SIGNED == "TRUE")
begin : SIGNED
assign int_rising_wire = $signed(int_data_reg[1]) < $signed(s_axis_tdata);
assign int_tdata_wire = $signed(int_data_reg[0]) - $signed(int_min_wire);
assign int_mincut_wire = $signed(int_tdata_wire) > $signed(min_data);
assign int_maxcut_wire = $signed(int_data_reg[0]) < $signed(max_data);
end
else
begin : UNSIGNED
assign int_rising_wire = int_data_reg[1] < s_axis_tdata;
assign int_tdata_wire = int_data_reg[0] - int_min_wire;
assign int_mincut_wire = int_tdata_wire > min_data;
assign int_maxcut_wire = int_data_reg[0] < max_data;
end
endgenerate
always @(posedge aclk)
begin
if(~aresetn)
begin
int_data_reg[0] <= {(AXIS_TDATA_WIDTH){1'b0}};
int_data_reg[1] <= {(AXIS_TDATA_WIDTH){1'b0}};
int_tdata_reg <= {(AXIS_TDATA_WIDTH){1'b0}};
int_min_reg <= {(AXIS_TDATA_WIDTH){1'b0}};
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
int_rising_reg <= 1'b0;
int_tvalid_reg <= 1'b0;
end
else
begin
int_data_reg[0] <= int_data_next[0];
int_data_reg[1] <= int_data_next[1];
int_tdata_reg <= int_tdata_next;
int_min_reg <= int_min_next;
int_cntr_reg <= int_cntr_next;
int_enbl_reg <= int_enbl_next;
int_rising_reg <= int_rising_next;
int_tvalid_reg <= int_tvalid_next;
end
end
always @*
begin
int_data_next[0] = int_data_reg[0];
int_data_next[1] = int_data_reg[1];
int_tdata_next = int_tdata_reg;
int_min_next = int_min_reg;
int_cntr_next = int_cntr_reg;
int_enbl_next = int_enbl_reg;
int_rising_next = int_rising_reg;
int_tvalid_next = int_tvalid_reg;
if(s_axis_tvalid)
begin
int_data_next[0] = s_axis_tdata;
int_data_next[1] = int_data_reg[0];
int_rising_next = int_rising_wire;
end
if(s_axis_tvalid & int_delay_wire)
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
// minimum after delay
if(s_axis_tvalid & ~int_delay_wire & ~int_rising_reg & int_rising_wire)
begin
int_min_next = int_data_reg[1];
int_enbl_next = 1'b1;
end
// maximum after minimum
if(s_axis_tvalid & int_enbl_reg & int_rising_reg & ~int_rising_wire & int_mincut_wire)
begin
int_tdata_next = int_maxcut_wire ? int_tdata_wire : {(AXIS_TDATA_WIDTH){1'b0}};
int_tvalid_next = int_maxcut_wire;
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_enbl_next = 1'b0;
end
if(m_axis_tready & int_tvalid_reg)
begin
int_tdata_next = {(AXIS_TDATA_WIDTH){1'b0}};
int_tvalid_next = 1'b0;
end
end
assign s_axis_tready = 1'b1;
assign m_axis_tdata = int_tdata_reg;
assign m_axis_tvalid = int_tvalid_reg;
endmodule
|
`timescale 1ns / 100ps
module ee201_debouncer(CLK, RESET, PB, DPB, SCEN, MCEN, CCEN);
//inputs
input CLK, RESET;
input PB;
//outputs
output DPB;
output SCEN, MCEN, CCEN;
//parameters
parameter N_dc = 7;
(* fsm_encoding = "user" *)
reg [5:0] state;
// other items not controlledd by the special atribute
reg [N_dc-1:0] debounce_count;
reg [3:0] MCEN_count;
//concurrent signal assignment statements
// The following is possible because of the output coding used by us.
assign {DPB, SCEN, MCEN, CCEN} = state[5:2];
//constants used for state naming // the don't cares are replaced here with zeros
localparam
INI = 6'b000000,
W84 = 6'b000001,
SCEN_st = 6'b111100,
WS = 6'b100000,
MCEN_st = 6'b101100,
CCEN_st = 6'b100100,
MCEN_cont = 6'b101101,
CCR = 6'b100001,
WFCR = 6'b100010;
//logic
always @ (posedge CLK, posedge RESET)
begin : State_Machine
if (RESET)
begin
state <= INI;
debounce_count <= 'bx;
MCEN_count <= 4'bx;
end
else
begin
case (state)
INI: begin
debounce_count <= 0;
MCEN_count <= 0;
if (PB)
begin
state <= W84;
end
end
W84: begin
debounce_count <= debounce_count + 1;
if (!PB)
begin
state <= INI;
end
else if (debounce_count[N_dc-5])// for N_dc of 28, it is debounce_count[23], i.e T = 0.084 sec for f = 100MHz
begin
state <= SCEN_st;
end
end
SCEN_st: begin
debounce_count <= 0;
MCEN_count <= MCEN_count + 1;
state <= WS;
end
WS: begin
debounce_count <= debounce_count + 1;
if (!PB)
begin
state <= CCR;
end
else if (debounce_count[N_dc-1])// for N_dc of 28, it is debounce_count[27], i.e T = 1.342 sec for f = 100MHz
begin
state <= MCEN_st;
end
end
MCEN_st: begin
debounce_count <= 0;
MCEN_count <= MCEN_count + 1;
state <= CCEN_st;
end
CCEN_st: begin
debounce_count <= debounce_count + 1;
if (!PB)
begin
state <= CCR;
end
else if (debounce_count[N_dc-1])// for N_dc of 28, it is debounce_count[27], i.e T = 1.342 sec for f = 100MHz
begin
if (MCEN_count == 4'b1000)
begin
state <= MCEN_cont;
end
else
begin
state <= MCEN_st;
end
end
end
MCEN_cont: begin
if (!PB)
begin
state <= CCR;
end
end
CCR: begin
debounce_count <= 0;
MCEN_count <= 0;
state <= WFCR;
end
WFCR: begin
debounce_count <= debounce_count + 1;
if (PB)
begin
state <= WS;
end
else if (debounce_count[N_dc-5])// for N_dc of 28, it is debounce_count[23], i.e T = 0.084 sec for f = 100MHz
begin
state <= INI;
end
end
endcase
end
end // State_Machine
endmodule // ee201_debouncer |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_impctl_clkgen.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_impctl_clkgen(se ,oe_out ,updclk ,so_l ,si_l ,
synced_upd_imped ,bypass ,global_reset_n ,clk ,hard_reset_n ,sclk ,
reset_l ,avgcntr_rst );
output oe_out ;
output updclk ;
output so_l ;
output bypass ;
output global_reset_n ;
output sclk ;
output avgcntr_rst ;
input se ;
input si_l ;
input synced_upd_imped ;
input clk ;
input hard_reset_n ;
input reset_l ;
wire int_sclk ;
wire net42 ;
bw_io_impctl_sclk I227 (
.l2clk (clk ),
.int_sclk (int_sclk ),
.sclk (sclk ),
.ssclk_n (net42 ),
.se (se ),
.si_l (si_l ),
.global_reset_n (global_reset_n ) );
bw_io_impctl_upclk I208 (
.int_sclk (int_sclk ),
.l2clk (clk ),
.synced_upd_imped (synced_upd_imped ),
.updclk (updclk ),
.reset_l (reset_l ),
.oe_out (oe_out ),
.bypass (bypass ),
.avgcntr_rst (avgcntr_rst ),
.so_l (so_l ),
.hard_reset_n (hard_reset_n ),
.si_l (net42 ),
.se (se ),
.global_reset_n (global_reset_n ) );
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, l[1000005], dp[1000005][2][2]; char s[1000005]; void Calc(int k) { if (s[k] == 0 ) dp[k][0][0] = 1; else if (s[k] == 1 ) dp[k][1][1] = 1; else { dp[k][1][0] = 1; dp[k][0][1] = 1; } } void Change(int x, int L, int R, int O) { int tmp[2][2] = {0}; for (int a = 0; a < 2; a++) for (int b = 0; b < 2; b++) if (dp[L][a][b]) for (int c = 0; c < 2; c++) for (int d = 0; d < 2; d++) if (dp[R][c][d]) if (s[O] == & ) tmp[a & c][b & d] = 1; else if (s[O] == | ) tmp[a | c][b | d] = 1; else tmp[a ^ c][b ^ d] = 1; for (int a = 0; a < 2; a++) for (int b = 0; b < 2; b++) dp[x][a][b] = tmp[a][b]; } int Dfs(int l) { int r = l + 1, L = -1, O = -1; while (s[r] != ) ) { if ((s[r] == ? || s[r] == 0 || s[r] == 1 ) && L == -1) Calc(r), L = r, O = r + 1; if (s[r] == ( ) r = Dfs(r); r++; if (r - l >= 3 && s[r] != ( ) { if (s[r] == ? || s[r] == 1 || s[r] == 0 ) { Calc(r); if (L != -1) Change(r, L, r, O); L = r; O = r + 1; r++; } else { if (L != -1) Change(r - 1, L, r - 1, O); L = r - 1; O = r; } O = r; } } for (int a = 0; a < 2; a++) for (int b = 0; b < 2; b++) dp[r][a][b] = dp[r - 1][a][b]; return r; } int main() { scanf( %d , &n); scanf( %s , &s); int n = strlen(s) - 1, flag = 0; for (int i = 0; i <= n; i++) if (s[i] == ? ) flag = 1; if (n == 0) { if (s[0] == 0 || s[0] == 1 ) puts( NO ); else puts( YES ); return 0; } Dfs(0); if (((dp[n][0][1] || dp[n][1][0]) && flag) || n == 0) puts( YES ); else puts( NO ); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { int a, b, c; cin >> a >> b >> c; long long ans = 0; for (int i = 1; i < min(b, c); i++) { ans += a; a++; } ans *= 2; for (int i = min(b, c); i <= max(b, c); i++) { ans += a; } cout << ans << endl; return 0; } |
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Helper module to handle bursting large sequential blocks of memory to or
// from global memory.
//
/*****************************************************************************/
// Burst read master:
// Keeps a local buffer populated with data from a sequential block of
// global memory. The block of global memory is specified by a base address
// and size.
/*****************************************************************************/
module lsu_burst_read_master (
clk,
reset,
o_active, //Debugging signal
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_go,
control_done,
control_early_done,
// user logic inputs and outputs
user_read_buffer,
user_buffer_data,
user_data_available,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_burstcount,
master_waitrequest
);
/*************
* Parameters *
*************/
parameter DATAWIDTH = 32;
parameter MAXBURSTCOUNT = 4;
parameter BURSTCOUNTWIDTH = 3;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
parameter READTHRESHOLD = FIFODEPTH - MAXBURSTCOUNT - 4;
/********
* Ports *
********/
input clk;
input reset;
output o_active;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
output wire control_done;
output wire control_early_done; // don't use this unless you know what you are doing, it's going to fire when the last read is posted, not when the last data returns!
// user logic inputs and outputs
input user_read_buffer;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
/***************
* Architecture *
***************/
// internal control signals
reg control_fixed_location_d1;
wire fifo_empty;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
reg [FIFODEPTH_LOG2-1:0] reads_pending;
wire increment_address;
wire [BURSTCOUNTWIDTH-1:0] burst_count;
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire first_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire final_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
wire too_many_reads_pending;
wire [FIFODEPTH_LOG2-1:0] fifo_used;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, increment by the burst count presented
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
length <= length - (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, decrement by the burst count presented
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign master_burstcount = burst_count;
assign control_done = (length == 0) & (reads_pending == 0); // need to make sure that the reads have returned before firing the done bit
assign control_early_done = (length == 0); // advanced feature, you should use 'control_done' if you need all the reads to return first
assign master_read = (too_many_reads_pending == 0) & (length != 0);
assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
assign first_short_burst_enable = (burst_boundary_word_address != 0);
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
assign final_short_burst_count = (length / BYTEENABLEWIDTH);
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // this will get the transfer back on a burst boundary,
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address = (too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
assign too_many_reads_pending = (reads_pending + fifo_used) >= READTHRESHOLD; // make sure there are fewer reads posted than room in the FIFO
// tracking FIFO
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
reads_pending <= 0;
end
else
begin
if(increment_address == 1)
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending + burst_count;
end
else
begin
reads_pending <= reads_pending + burst_count - 1; // a burst read was posted, but a word returned
end
end
else
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending; // burst read was not posted and no read returned
end
else
begin
reads_pending <= reads_pending - 1; // burst read was not posted but a word returned
end
end
end
end
assign o_active = |reads_pending;
// read data feeding user logic
assign user_data_available = !fifo_empty;
scfifo the_master_to_user_fifo (
.aclr (reset),
.clock (clk),
.data (master_readdata),
.empty (fifo_empty),
.q (user_buffer_data),
.rdreq (user_read_buffer),
.usedw (fifo_used),
.wrreq (master_readdatavalid),
.almost_empty(),
.almost_full(),
.full(),
.sclr()
);
defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
defparam the_master_to_user_fifo.lpm_widthu = FIFODEPTH_LOG2;
defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
defparam the_master_to_user_fifo.lpm_showahead = "ON";
defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
defparam the_master_to_user_fifo.underflow_checking = "OFF";
defparam the_master_to_user_fifo.overflow_checking = "OFF";
initial
if ( READTHRESHOLD > FIFODEPTH ||
READTHRESHOLD > FIFODEPTH - 4 ||
READTHRESHOLD < 1 )
$error("Invalid FIFODEPTH and MAXBURSTCOUNT comination. Produced READTHRESHOLD = %d\n",READTHRESHOLD);
endmodule
|
#include <bits/stdc++.h> using namespace std; int32_t main() { long long n; cin >> n; vector<long long> v(n); for (long long i = 0; i < n; i++) { cin >> v[i]; } sort(v.begin(), v.end()); long long count = 0; while (v.size() > 0) { count++; long long num = v[0]; for (long long i = 0; i < v.size(); i++) { if (v[i] % num == 0) { v.erase(v.begin() + i, v.begin() + i + 1); i--; } } } cout << count << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1000005; struct Node { int left, right; long long sum; } L[N << 2]; void bulid(int step, int l, int r) { L[step].left = l; L[step].right = r; L[step].sum = 0; if (l == r) return; int m = (l + r) >> 1; bulid(step << 1, l, m); bulid(step << 1 | 1, m + 1, r); } void update(int step, int pos, long long val) { if (L[step].left == L[step].right) { L[step].sum = (val) % 1000000007; return; } int m = (L[step].left + L[step].right) >> 1; if (pos <= m) update(step << 1, pos, val); else update(step << 1 | 1, pos, val); L[step].sum = (L[step << 1].sum + L[step << 1 | 1].sum) % 1000000007; } long long query(int step, int l, int r) { if (L[step].left == l && L[step].right == r) return L[step].sum; int m = (L[step].left + L[step].right) >> 1; if (r <= m) return query(step << 1, l, r); else if (l > m) return query(step << 1 | 1, l, r); else return (query(step << 1, l, m) + query(step << 1 | 1, m + 1, r)) % 1000000007; } long long a[N]; int main() { int n; scanf( %d , &n); bulid(1, 1, 1000000); long long ans = 0; for (int i = 0; i < n; i++) { scanf( %I64d , &a[i]); long long sub = query(1, a[i], a[i]); long long sum = (a[i] + a[i] * query(1, 1, a[i])) % 1000000007; ans = ((ans + sum - sub) % 1000000007 + 1000000007) % 1000000007; update(1, a[i], sum); } printf( %I64d n , ans); return 0; } |
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_clockgen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_clockgen.v,v $
// Revision 1.4 2005/02/21 12:48:05 igorm
// Warning fixes.
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/01 22:28:55 mohor
// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
//
//
`include "timescale.v"
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
parameter Tp=1;
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg Mdc;
reg [7:0] Counter;
wire CountEq0;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Counter[7:0] <= #Tp 8'h1;
else
begin
if(CountEq0)
begin
Counter[7:0] <= #Tp CounterPreset[7:0];
end
else
Counter[7:0] <= #Tp Counter - 8'h1;
end
end
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= #Tp 1'b0;
else
begin
if(CountEq0)
Mdc <= #Tp ~Mdc;
end
end
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iobdg_dbg_porta.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg_dbg_porta (IO Bridge debug/visibility)
// Description:
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module iobdg_dbg_porta (/*AUTOARG*/
// Outputs
iob_io_dbg_data, iob_io_dbg_en, iob_io_dbg_ck_p, iob_io_dbg_ck_n,
l2_vis_armin, iob_clk_tr,
// Inputs
rst_l, clk, src0_data, src1_data, src2_data, src3_data, src4_data,
src0_vld, src1_vld, src2_vld, src3_vld, src4_vld,
creg_dbg_enet_ctrl, creg_dbg_enet_idleval, io_trigin
);
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
// Global interface
input rst_l;
input clk;
// Debug input buses
input [39:0] src0_data;
input [39:0] src1_data;
input [39:0] src2_data;
input [39:0] src3_data;
input [39:0] src4_data;
input src0_vld;
input src1_vld;
input src2_vld;
input src3_vld;
input src4_vld;
// Debug output bus
output [39:0] iob_io_dbg_data;
output iob_io_dbg_en;
output [2:0] iob_io_dbg_ck_p;
output [2:0] iob_io_dbg_ck_n;
// Control interface
input [63:0] creg_dbg_enet_ctrl;
input [63:0] creg_dbg_enet_idleval;
// Misc interface
input io_trigin;
output l2_vis_armin;
output iob_clk_tr;
// Internal signals
wire dbg_en;
wire dbg_armin_en;
wire dbg_trigin_en;
wire [3:0] dbg_sel;
wire [39:0] dbg_idleval;
reg [39:0] mux_data;
reg mux_vld;
wire [39:0] dbg_data;
wire iob_io_dbg_ck_p_next;
wire io_trigin_d1;
wire io_trigin_d2;
wire io_trigin_d3;
wire io_trigin_detected;
wire iob_clk_tr_a1;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
assign dbg_en = creg_dbg_enet_ctrl[8];
assign dbg_armin_en = creg_dbg_enet_ctrl[6];
assign dbg_trigin_en = creg_dbg_enet_ctrl[5];
assign dbg_sel = creg_dbg_enet_ctrl[3:0];
assign dbg_idleval = creg_dbg_enet_idleval[39:0];
always @(/*AUTOSENSE*/dbg_sel or src0_data or src0_vld or src1_data
or src1_vld or src2_data or src2_vld or src3_data
or src3_vld or src4_data or src4_vld)
case (dbg_sel)
4'b0000: {mux_vld,mux_data} = {src0_vld,src0_data};
4'b0001: {mux_vld,mux_data} = {src1_vld,src1_data};
4'b0010: {mux_vld,mux_data} = {src2_vld,src2_data};
4'b0011: {mux_vld,mux_data} = {src3_vld,src3_data};
4'b0100: {mux_vld,mux_data} = {src4_vld,src4_data};
default: {mux_vld,mux_data} = {1'b0,40'b0};
endcase // case(dbg_sel)
assign dbg_data = mux_vld ? mux_data : dbg_idleval;
dff_ns #(40) iob_io_dbg_data_ff (.din(dbg_data),
.clk(clk),
.q(iob_io_dbg_data));
dff_ns #(1) iob_io_dbg_en_ff (.din(dbg_en),
.clk(clk),
.q(iob_io_dbg_en));
// Generate clocks for the debug pad
assign iob_io_dbg_ck_p_next = ~iob_io_dbg_ck_p[0] & dbg_en;
dff_ns #(1) iob_io_dbg_ck_p_ff (.din(iob_io_dbg_ck_p_next),
.clk(clk),
.q(iob_io_dbg_ck_p[0]));
assign iob_io_dbg_ck_p[1] = iob_io_dbg_ck_p[0];
assign iob_io_dbg_ck_p[2] = iob_io_dbg_ck_p[0];
assign iob_io_dbg_ck_n = ~iob_io_dbg_ck_p;
// Flop TRIGIN pin and detect edge
dffrl_ns #(1) io_trigin_d1_ff (.din(io_trigin),
.clk(clk),
.rst_l(rst_l),
.q(io_trigin_d1));
dffrl_ns #(1) io_trigin_d2_ff (.din(io_trigin_d1),
.clk(clk),
.rst_l(rst_l),
.q(io_trigin_d2));
dffrl_ns #(1) io_trigin_d3_ff (.din(io_trigin_d2),
.clk(clk),
.rst_l(rst_l),
.q(io_trigin_d3));
assign io_trigin_detected = io_trigin_d2 & ~io_trigin_d3;
// Route TRIGIN pin to L2 Visibility port as ARM_IN
assign l2_vis_armin = dbg_armin_en & io_trigin_detected;
// Route TRIGIN pin to clock block for stop_and_scan
assign iob_clk_tr_a1 = dbg_trigin_en & io_trigin_detected;
dffrl_ns #(1) iob_clk_tr_ff (.din(iob_clk_tr_a1),
.clk(clk),
.rst_l(rst_l),
.q(iob_clk_tr));
endmodule // iobdg_dbg_porta
// Local Variables:
// verilog-auto-sense-defines-constant:t
// End:
|
#include <bits/stdc++.h> using namespace std; int rbq[505][505]; int score[505]; int main() { int n, m, q; while (~scanf( %d%d%d , &n, &m, &q)) { for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { scanf( %d , &rbq[i][j]); } } for (int i = 1; i <= n; i++) { int max = 0; for (int j = 1; j <= m; j++) { int count = 0; while (j <= m && rbq[i][j] == 1) { j++; count++; } if (count > max) max = count; } score[i] = max; } for (int i = 0; i < q; i++) { int r, l; scanf( %d%d , &r, &l); if (rbq[r][l] == 0) rbq[r][l] = 1; else rbq[r][l] = 0; int max = 0; for (int j = 1; j <= m; j++) { int count = 0; while (j <= m && rbq[r][j] == 1) { j++; count++; } if (count > max) max = count; } score[r] = max; int max_score = 0; for (int j = 1; j <= n; j++) { if (score[j] > max_score) max_score = score[j]; } printf( %d n , max_score); } } return 0; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2010 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] O_out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.O_out (O_out[31:0]));
initial begin
if (O_out != 32'h4) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module Test
(
output [31:0] O_out
);
test
#(
.pFOO(5),
.pBAR(2)
) U_test
(
.O_out(O_out)
);
endmodule
module test
#(parameter pFOO = 7,
parameter pBAR = 3,
parameter pBAZ = ceiling(pFOO, pBAR)
)
(
output [31:0] O_out
);
assign O_out = pBAZ;
function integer ceiling;
input [31:0] x, y;
ceiling = ((x%y == 0) ? x/y : (x/y)+1) + 1;
endfunction
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O31A_M_V
`define SKY130_FD_SC_LP__O31A_M_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog wrapper for o31a with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o31a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_m (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o31a_m (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o31a base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O31A_M_V
|
#include <bits/stdc++.h> using namespace std; int n, co[200010], to[200010]; int cnt = 0; int dfn[200010], low[200010]; int scc_cnt; int sccno[200010]; int nt[200010], va[200010]; stack<int> S; void dfs(int u) { dfn[u] = low[u] = ++cnt; S.push(u); int v = to[u]; if (dfn[v] == 0) { dfs(v); low[u] = min(low[u], low[v]); } else if (!sccno[v]) { low[u] = min(low[u], dfn[v]); } int MMM = 0x3f3f3f3f; if (low[u] == dfn[u]) { ++scc_cnt; while (true) { int x = S.top(); S.pop(); sccno[x] = scc_cnt; MMM = min(MMM, co[x]); if (x == u) { break; } } va[scc_cnt] = MMM; } } int num[200010]; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> co[i]; for (int i = 1; i <= n; i++) cin >> to[i]; memset(dfn, 0, sizeof(dfn)); cnt = scc_cnt = 0; for (int i = 1; i <= n; ++i) { if (!dfn[i]) { dfs(i); } } for (int u = 1; u <= n; ++u) { int v = to[u]; if (sccno[u] != sccno[v]) { nt[sccno[u]] = sccno[v]; num[sccno[u]]++; } } queue<int> q; int ans = 0; for (int i = 1; i <= scc_cnt; i++) { if (num[i] == 0) { ans += va[i]; } } cout << ans << endl; ; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, m, k, x, y; int main() { scanf( %d%d%d , &n, &m, &k); for (int i = 1; i <= k; i++) { scanf( %d%d , &x, &y); if (x <= 5 || (n - x + 1) <= 5 || y <= 5 || (m - y + 1) <= 5) return printf( YES n ), 0; } printf( NO n ); } |
#include <bits/stdc++.h> using namespace std; const long long int mod = 1e9 + 7; bool sortbysec(const pair<int, int>& a, const pair<int, int>& b) { return (a.second < b.second); } long long int modpower(long long int a, long long int b, long long int c) { long long int res = 1; while (b) { if (b & 1LL) res = (res * a) % c; a = (a * a) % c; b >>= 1; } return res; } long long int gcd(long long int a, long long int b) { if (a == 0) return b; return gcd(b % a, a); } template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cout << name << : << arg1 << n ; } using namespace std; const int INF = 987654321; const int MOD = 1000000007; const int N = 1e5 + 5; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int t; cin >> t; while (t--) { int n, m; cin >> n >> m; int a[N], b[N]; for (int i = 1; i <= 1000; i++) { a[i] = 0; } for (int i = 0; i < n; i++) { int x; cin >> x; a[x]++; } int j = -1; for (int i = 0; i < m; i++) { cin >> b[i]; if (a[b[i]]) { j = b[i]; } } if (j > 0) cout << YES << n << 1 << j << n ; else cout << NO << n ; } return 0; } |
// stereo volume control
// channel 1&2 --> left
// channel 0&3 --> right
module paula_audio_mixer (
input clk, //bus clock
input clk7_en,
input [7:0] sample0, //sample 0 input
input [7:0] sample1, //sample 1 input
input [7:0] sample2, //sample 2 input
input [7:0] sample3, //sample 3 input
input [6:0] vol0, //volume 0 input
input [6:0] vol1, //volume 1 input
input [6:0] vol2, //volume 2 input
input [6:0] vol3, //volume 3 input
output reg [14:0]ldatasum, //left DAC data
output reg [14:0]rdatasum //right DAC data
);
// volume control
wire [14-1:0] msample0, msample1, msample2, msample3;
// when volume MSB is set, volume is always maximum
paula_audio_volume sv0
(
.sample(sample0),
.volume({ (vol0[6] | vol0[5]),
(vol0[6] | vol0[4]),
(vol0[6] | vol0[3]),
(vol0[6] | vol0[2]),
(vol0[6] | vol0[1]),
(vol0[6] | vol0[0]) }),
.out(msample0)
);
paula_audio_volume sv1
(
.sample(sample1),
.volume({ (vol1[6] | vol1[5]),
(vol1[6] | vol1[4]),
(vol1[6] | vol1[3]),
(vol1[6] | vol1[2]),
(vol1[6] | vol1[1]),
(vol1[6] | vol1[0]) }),
.out(msample1)
);
paula_audio_volume sv2
(
.sample(sample2),
.volume({ (vol2[6] | vol2[5]),
(vol2[6] | vol2[4]),
(vol2[6] | vol2[3]),
(vol2[6] | vol2[2]),
(vol2[6] | vol2[1]),
(vol2[6] | vol2[0]) }),
.out(msample2)
);
paula_audio_volume sv3
(
.sample(sample3),
.volume({ (vol3[6] | vol3[5]),
(vol3[6] | vol3[4]),
(vol3[6] | vol3[3]),
(vol3[6] | vol3[2]),
(vol3[6] | vol3[1]),
(vol3[6] | vol3[0]) }),
.out(msample3)
);
// channel muxing
// !!! this is 28MHz clock !!!
always @ (posedge clk) begin
ldatasum <= #1 {msample1[13], msample1} + {msample2[13], msample2};
rdatasum <= #1 {msample0[13], msample0} + {msample3[13], msample3};
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { int n = ({ int x; scanf( %d , &x); x; }); string s; cin >> s; string ans = no ; for (int d = (1); d < (30); d += (1)) { for (int i = (0); i < (n); i += (1)) { int g = 1; for (int j = (0); j < (5); j += (1)) { if (i + j * d >= n || s[i + j * d] == . ) { g = 0; } } if (g) { ans = yes ; break; } } } cout << ans << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { int n, k, sum = 0; cin >> n >> k; int a[n]; for (int i = 0; i < n; i++) { cin >> a[i]; } for (int j = 0; j < k; j++) { int c1 = 0, c2 = 0; for (int i = j; i < n; i += k) { if (a[i] == 1) c1++; else c2++; } (c1 > c2) ? (sum += c2) : (sum += c1); } cout << sum << endl; } |
`timescale 1ns / 1ps
/////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
// Josh Sackos
//
// Create Date: 07/26/2012
// Module Name: SPIcomponent
// Project Name: PmodACL_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: The spi_master controls the state of the entire interface. Using
// several signals to interact with the other modules. The spi_master
// selects the data to be transmitted and stores all data received
// from the PmodACL. The data is then made available to the rest of
// the design on the xAxis, yAxis, and zAxis outputs.
//
//
// Inputs:
// CLK 100MHz onboard system clock
// RST Main Reset Controller
// START Signal to initialize a data transfer
// SDI Serial Data In
//
// Outputs:
// SDO Serial Data Out
// SCLK Serial Clock
// SS Slave Select
// xAxis x-axis data received from PmodACL
// yAxis y-axis data received from PmodACL
// zAxis z-axis data received from PmodACL
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added comments and modified code (Josh Sackos)
////////////////////////////////////////////////////////////////////////////////////
// ===================================================================================
// Define Module, Inputs and Outputs
// ===================================================================================
module SPIcomponent(
CLK,
RST,
START,
SDI,
SDO,
SCLK,
SS,
xAxis,
yAxis,
zAxis
);
// ====================================================================================
// Port Declarations
// ====================================================================================
input CLK;
input RST;
input START;
input SDI;
output SDO;
output SCLK;
output SS;
output [9:0] xAxis;
output [9:0] yAxis;
output [9:0] zAxis;
// ====================================================================================
// Parameters, Register, and Wires
// ====================================================================================
wire [9:0] xAxis;
wire [9:0] yAxis;
wire [9:0] zAxis;
wire [15:0] TxBuffer;
wire [7:0] RxBuffer;
wire doneConfigure;
wire done;
wire transmit;
// ===================================================================================
// Implementation
// ===================================================================================
//-------------------------------------------------------------------------
// Controls SPI Interface, Stores Received Data, and Controls Data to Send
//-------------------------------------------------------------------------
SPImaster C0(
.rst(RST),
.start(START),
.clk(CLK),
.transmit(transmit),
.txdata(TxBuffer),
.rxdata(RxBuffer),
.done(done),
.x_axis_data(xAxis),
.y_axis_data(yAxis),
.z_axis_data(zAxis)
);
//-------------------------------------------------------------------------
// Produces Timing Signal, Reads ACL Data, and Writes Data to ACL
//-------------------------------------------------------------------------
SPIinterface C1(
.sdi(SDI),
.sdo(SDO),
.rst(RST),
.clk(CLK),
.sclk(SCLK),
.txbuffer(TxBuffer),
.rxbuffer(RxBuffer),
.done_out(done),
.transmit(transmit)
);
//-------------------------------------------------------------------------
// Enables/Disables PmodACL Communication
//-------------------------------------------------------------------------
slaveSelect C2(
.clk(CLK),
.ss(SS),
.done(done),
.transmit(transmit),
.rst(RST)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); int n; cin >> n; char s; int d = 1, j = 1; for (int i = 1; i <= n; i++) { cin >> s; j -= 1; if (j == 0) { cout << s; d += 1; j = d; } } return 0; } |
#include <bits/stdc++.h> using namespace std; vector<double> E[100010]; int color[100010]; int seen[100010]; set<int> sets[100010]; void dfs(int u) { for (int i = 0; i < E[u].size(); ++i) { int v = E[u][i]; if (color[u] != color[v]) sets[color[u]].insert(color[v]); if (!seen[v]) { seen[v] = true; dfs(v); } } } int main() { int n, m, u, v; cin >> n >> m; set<int> colorids; for (int i = 0; i < n; ++i) { cin >> color[i]; colorids.insert(color[i]); } for (int i = 0; i < m; ++i) { cin >> u >> v; --u; --v; E[u].push_back(v); E[v].push_back(u); } memset(seen, 0, sizeof(seen)); for (int i = 0; i < n; ++i) if (!seen[i]) { seen[i] = true; dfs(i); } int maxcolor = -1; int maxn = -(1 << 30); for (typeof(colorids.begin()) it = colorids.begin(); it != colorids.end(); ++it) { int color = *it; int ncolors = sets[*it].size(); if (maxn < ncolors) { maxn = ncolors; maxcolor = *it; } } cout << maxcolor << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T1, class T2> inline istream& operator>>(istream& fin, pair<T1, T2>& pr) { fin >> pr.first >> pr.second; return fin; } template <class T0, class T1, class T2> inline istream& operator>>(istream& fin, tuple<T0, T1, T2>& t) { fin >> get<0>(t) >> get<1>(t) >> get<2>(t); return fin; } template <class T> inline istream& operator>>(istream& fin, vector<T>& a) { if (!a.size()) { size_t n; fin >> n; a.resize(n); } for (auto& u : a) fin >> u; return fin; } string probB() { vector<string> a(2); cin >> a; const auto n = a[0].length(); size_t diff = 0; for (size_t i = 0; i < n; ++i) diff += a[0][i] != a[1][i]; if (diff & 1) return impossible ; string str; size_t k = 0; for (size_t i = 0; i < n; ++i) if (a[0][i] == a[1][i]) str.push_back(a[0][i]); else if (2 * k < diff) str.push_back(a[0][i]), ++k; else str.push_back(a[1][i]); return str; } int main(const int argc, char* argv[]) { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; cout << probB(); return EXIT_SUCCESS; } |
/*
* Titor - General purpose synchronous memory
* Copyright (C) 2012,2013 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Memory
`else
`define INC_Memory
`timescale 1 ns / 100 ps
// Memory module
// takes arguments from the Control_Logic module and handles some of the logic for each one
// in a partially configurable way that takes out some of the complexity
// and facilitates writing the logic in a way that can fit into a spreadsheet and be copied over
module Memory(
dout,
din,
address,
size,
read_write,
enable,
clk,
reset
);
`include "definition/Definition.v"
parameter MFILE = BLANKFILE;
parameter MWIDTH = WORD; // overridable memory element width
output reg [WORD-1:0] dout;
input [WORD-1:0] din;
input [WORD-1:0] address;
input [LOGWORDBYTE-1:0] size;
input read_write;
input enable;
input clk;
input reset;
reg [MWIDTH-1:0] array [(1<<LOGMEM)-1:0];
initial begin
if(MFILE != BLANKFILE) begin
$readmemh(MFILE, array);
end
end
always @(posedge clk) begin
if((read_write == WRITE) && enable) array[address] <= din;
if((read_write == READ) && enable) dout <= array[address];
else dout <= dout;
end
endmodule
`endif
|
/* Model for xilinx async fifo*/
module fifo_async_104x32
(/*AUTOARG*/
// Outputs
full, prog_full, almost_full, dout, empty, valid,
// Inputs
wr_rst, rd_rst, wr_clk, rd_clk, wr_en, din, rd_en
);
parameter DW = 104;//104 wide
parameter DEPTH = 16; //
//##########
//# RESET/CLOCK
//##########
input wr_rst; //asynchronous reset
input rd_rst; //asynchronous reset
input wr_clk; //write clock
input rd_clk; //read clock
//##########
//# FIFO WRITE
//##########
input wr_en;
input [DW-1:0] din;
output full;
output prog_full;
output almost_full;
//###########
//# FIFO READ
//###########
input rd_en;
output [DW-1:0] dout;
output empty;
output valid;
defparam fifo_model.DW=104;
defparam fifo_model.DEPTH=32;
fifo_async_model fifo_model (/*AUTOINST*/
// Outputs
.full (full),
.prog_full (prog_full),
.almost_full (almost_full),
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.wr_rst (wr_rst),
.rd_rst (rd_rst),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
endmodule // fifo_async
// Local Variables:
// verilog-library-directories:("." "../../memory/hdl")
// End:
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
#include <bits/stdc++.h> using namespace std; map<int, vector<pair<int, int> > > mp; int n, tt; int arr[300000]; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> arr[i]; for (int r = 1; r <= n; r++) { long long sum = 0; for (int l = r; l >= 1; l--) { sum += arr[l]; mp[sum].push_back(make_pair(l, r)); } } map<int, vector<pair<int, int> > >::iterator it; vector<pair<int, int> > ans; for (it = mp.begin(); it != mp.end(); it++) { int sum = 0; vector<pair<int, int> > &now = it->second; vector<pair<int, int> > cnt; int r = -1; for (int i = 0; i < now.size(); i++) { if (now[i].first > r) sum++, r = now[i].second, cnt.push_back(make_pair(now[i].first, now[i].second)); } if (sum > tt) ans = cnt, tt = sum; } cout << tt << endl; for (int i = 0; i < ans.size(); i++) cout << ans[i].first << << ans[i].second << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 5; const int MOD = 1e9 + 7; const long long M = 1e18; long long qpow(long long a, long long b, long long m) { long long ans = 1; while (b) { if (b & 1) ans = (ans * a) % m; b /= 2; a = (a * a) % m; } return ans; } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); ; int t = 1; while (t--) { int n, q; cin >> n >> q; int a[n + 1]; map<int, int> mn, mx, ct; for (int i = 1; i <= n; i++) { cin >> a[i]; if (mn[a[i]] == 0) mn[a[i]] = i; mx[a[i]] = i; ct[a[i]]++; } int l = 1, r = 1; int ans = 0; for (int i = 1; i <= n; i++) { r = max(r, mx[a[i]]); if (i == r) { int ans1 = N; for (int j = l; j <= r; j++) { ans1 = min(ans1, (r - l + 1) - ct[a[j]]); } ans += ans1; l = r + 1; r++; } } cout << ans; } } |
#include <bits/stdc++.h> const double PI = acos(-1.0); int main() { double n, r; scanf( %lf%lf , &n, &r); double p1 = PI / n, p2 = PI / (2 * n), p3 = PI - p1 - p2; double l3 = r, l2 = l3 / sin(p3) * sin(p2); double s = l3 * l2 * sin(p1); printf( %.15f n , n * s); return 0; } |
#include <bits/stdc++.h> using namespace std; const int dx[8] = {0, -1, 0, 1, 1, -1, -1, 1}; const int dy[8] = {-1, 0, 1, 0, -1, -1, 1, 1}; const long long mod = 1000000007; const int base = 311; const int N = 6e5 + 5; map<long long, vector<pair<int, int>>> e; int n, m; long long a[N]; vector<int> dsk[N]; long long pw[N]; int dd[N]; int k; void dfs(int u, int &d) { dd[u] = 1; ++d; for (int v : dsk[u]) if (!dd[v]) dfs(v, d); } void gogo() { cin >> n >> m >> k; for (int i = 1; i <= n; ++i) cin >> a[i]; for (int i = 1; i <= m; ++i) { int u, v; cin >> u >> v; e[a[u] ^ a[v]].push_back(make_pair(u, v)); } pw[0] = 1; for (int i = 1; i <= 6e5; ++i) pw[i] = pw[i - 1] * 2 % mod; long long ans = pw[k] * pw[n] % mod; for (auto it : e) { vector<pair<int, int>> tmp = it.second; for (pair<int, int> i : tmp) { dsk[i.first].push_back(i.second); dsk[i.second].push_back(i.first); } vector<int> cnt; for (pair<int, int> i : tmp) { int d = 0; if (!dd[i.first]) { dfs(i.first, d); cnt.push_back(d); } } int sum = 0; for (int i : cnt) sum += i; long long comp = n - sum + ((int)(cnt).size()); ans = (ans - pw[n] + pw[comp] + mod * mod) % mod; for (pair<int, int> i : tmp) { dd[i.first] = dd[i.second] = 0; dsk[i.first].clear(); dsk[i.second].clear(); } } cout << ans; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); if (fopen( sol .inp , r )) { freopen( sol .inp , r , stdin); freopen( sol .out , w , stdout); } gogo(); } |
`ifndef SDIO_DEFINES
`define SDIO_DEFINES
`define SDIO_STATE_RESET 0
`define SDIO_STATE_ACTIVE 1
`define SDIO_C_BIT_TXRX_DIR 1
`define SDIO_C_BIT_CMD_START 2
`define SDIO_C_BIT_CMD_END 7
`define SDIO_C_BIT_ARG_START 8
`define SDIO_C_BIT_ARG_END 39
`define SDIO_C_BIT_CRC_START 40
`define SDIO_C_BIT_CRC_END 46
`define SDIO_C_BIT_FINISH 47
`define SDIO_R_BIT_START_BIT 0
`define SDIO_R_BIT_TXRX_DIR 1
`define SD_CMD_GO_IDLE_STATE (6'd0 )
//`define SD_CMD_SEND_CID (6'd2 )
`define SD_CMD_SEND_RELATIVE_ADDR (6'd3 )
//`define SD_CMD_SET_DSR (6'd4 )
`define SD_CMD_IO_SEND_OP_CMD (6'd5 )
//`define SD_CMD_SWITCH_FUNC (6'd6 )
`define SD_CMD_SEL_DESEL_CARD (6'd7 )
`define SD_CMD_SEND_IF_COND (6'd8 )
//`define SD_CMD_SEND_CSD (6'd9 )
//`define SD_CMD_SEND_CID (6'd10)
`define SD_CMD_VOLTAGE_SWITCH (6'd11)
//`define SD_CMD_STOP_TRANSMISSION (6'd12)
//`define SD_CMD_SEND_STATUS (6'd13)
`define SD_CMD_GO_INACTIVE_STATE (6'd15)
//`define SD_CMD_SET_BLOCKLEN (6'd16)
//`define SD_CMD_READ_SINGLE_BLOCK (6'd17)
//`define SD_CMD_READ_MULTIPLE_BLOCK (6'd18)
`define SD_CMD_SEND_TUNNING_BLOCK (6'd19)
//`define SD_CMD_SET_BLOCK_COUNT (6'd23)
//`define SD_CMD_WRITE_BLOCK (6'd24)
//`define SD_CMD_WRITE_MULTIPLE_BLOCK (6'd25)
//`define SD_CMD_PROGRAM_CSD (6'd27)
//`define SD_CMD_SET_WRITE_PROT (6'd28)
//`define SD_CMD_CLR_WRITE_PRO (6'd29)
//`define SD_CMD_SEND_WRITE_PROT (6'd30)
//`define SD_CMD_ERASE_WR_BLK_START (6'd32)
//`define SD_CMD_ERASE_WR_BLK_END (6'd33)
//`define SD_CMD_ERASE (6'd38)
//`define SD_CMD_LOCK_UNLOCK (6'd42)
`define SD_CMD_IO_RW_DIRECT (6'd52)
`define SD_CMD_IO_RW_EXTENDED (6'd53)
//`define SD_CMD_APP_CMD (6'd55)
//`define SD_CMD_GEN_CMD (6'd56)
//`define SD_ACMD_SET_BUS_WIDTH (6'd6)
//`define SD_ACMD_SD_STATUS (6'd13)
//`define SD_ACMD_SEND_NUM_WR_BLOCK (6'd22)
//`define SD_ACMD_SET_WR_BLK_ERASE_CNT (6'd23)
//`define SD_ACMD_SD_APP_OP_COND (6'd41)
//`define SD_ACMD_SET_CLR_CARD_DETECT (6'd42)
//`define SD_ACMD_SEND_SCR (6'd51)
//Relative Card Address
`define RELATIVE_CARD_ADDRESS (16'h0001)
//Not SD_CURRENT_STATE shall always return 0x0F
//Card Status
`define CMD_RSP_CMD 45:40
`define CMD_RSP_CRD_STS_START (39)
`define CMD_RSP_CRD_STS_END (8)
//IO_SEND_OP_COND Response (R4 32 bits)
`define CMD5_ARG_S18R (24)
`define CMD5_ARG_VHS 23:0
`define VHS_DEFAULT_VALUE (4'b0001)
`define CMD8_ARG_VHS_START 15
`define CMD8_ARG_VHS_END 8
`define CMD8_ARG_PATTERN 7:0
`define CMD52_ARG_RW_FLAG 31 /* 0 = Read 1 = Write */
`define CMD52_ARG_FNUM 30:27
`define CMD52_ARG_RAW_FLAG 26 /* Read the value of the register after a write RW_FLAG = 1*/
`define CMD52_ARG_REG_ADDR 24:8
`define CMD52_ARG_WR_DATA 7:0
`define CMD52_RST_ADDR 6
`define CMD52_RST_BIT 3
//Extended
`define CMD53_ARG_RW_FLAG 31
`define CMD53_ARG_FNUM 30:27
`define CMD53_ARG_BLOCK_MODE 26
`define CMD53_ARG_INC_ADDR 25
`define CMD53_ARG_REG_ADDR 24:8
`define CMD53_ARG_DATA_COUNT 7:0
//COMMAND SEL DESEL CARD
//Response R1
`define R1_OUT_OF_RANGE (39)
`define R1_COM_CRC_ERROR (38)
`define R1_ILLEGAL_COMMAND (37)
`define R1_ERROR (19)
`define R1_CURRENT_STATE 12:9
//Respone R4
`define R4_RSRVD 45:40
`define R4_READY (39) /* Card is ready to operate */
`define R4_NUM_FUNCS 38:36 /* Number of functions */
`define R4_MEM_PRESENT (35) /* Memory is Also Availalbe */
`define R4_UHSII_AVAILABLE (34) /* Ultra HS Mode II Available */
`define R4_S18A (32) /* Accept switch to 1.8V */
`define R4_IO_OCR 31:16 /* Operating Condition Range */
//Response R5
`define R5_FLAGS_RANGE 31:16
`define R5_DATA 15:8
`define R5_FLAG_CRC_ERROR (15)
`define R5_INVALID_CMD (14)
`define R5_FLAG_CURR_STATE 13:12
`define R5_FLAG_ERROR (11)
`define R5_INVALID_FNUM (9)
`define R5_OUT_OF_RANGE (8)
//Response R6
`define R6_REL_ADDR 39:24
`define R6_STS_CRC_COMM_ERR (23)
`define R6_STS_ILLEGAL_CMD (22)
`define R6_STS_ERROR (21)
//Response 7
`define R7_VHS 19:16
`define R7_PATTERN 15:8
`endif
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_pdl_even.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_pdl_even(/*AUTOARG*/
// Outputs
arbpc0_pcxdp_grant_pa, arbpc0_pcxdp_q0_hold_pa_l,
arbpc0_pcxdp_qsel0_pa, arbpc0_pcxdp_qsel1_pa_l,
arbpc0_pcxdp_shift_px, arbpc2_pcxdp_grant_pa,
arbpc2_pcxdp_q0_hold_pa_l, arbpc2_pcxdp_qsel0_pa,
arbpc2_pcxdp_qsel1_pa_l, arbpc2_pcxdp_shift_px,
// Inputs
arbpc0_pcxdp_grant_bufp1_pa_l, arbpc0_pcxdp_q0_hold_bufp1_pa,
arbpc0_pcxdp_qsel0_bufp1_pa_l, arbpc0_pcxdp_qsel1_bufp1_pa,
arbpc0_pcxdp_shift_bufp1_px_l, arbpc2_pcxdp_grant_bufp1_pa_l,
arbpc2_pcxdp_q0_hold_bufp1_pa, arbpc2_pcxdp_qsel0_bufp1_pa_l,
arbpc2_pcxdp_qsel1_bufp1_pa, arbpc2_pcxdp_shift_bufp1_px_l
);
output arbpc0_pcxdp_grant_pa ;
output arbpc0_pcxdp_q0_hold_pa_l ;
output arbpc0_pcxdp_qsel0_pa ;
output arbpc0_pcxdp_qsel1_pa_l ;
output arbpc0_pcxdp_shift_px ;
output arbpc2_pcxdp_grant_pa ;
output arbpc2_pcxdp_q0_hold_pa_l ;
output arbpc2_pcxdp_qsel0_pa ;
output arbpc2_pcxdp_qsel1_pa_l ;
output arbpc2_pcxdp_shift_px ;
input arbpc0_pcxdp_grant_bufp1_pa_l;
input arbpc0_pcxdp_q0_hold_bufp1_pa;
input arbpc0_pcxdp_qsel0_bufp1_pa_l;
input arbpc0_pcxdp_qsel1_bufp1_pa;
input arbpc0_pcxdp_shift_bufp1_px_l;
input arbpc2_pcxdp_grant_bufp1_pa_l;
input arbpc2_pcxdp_q0_hold_bufp1_pa;
input arbpc2_pcxdp_qsel0_bufp1_pa_l;
input arbpc2_pcxdp_qsel1_bufp1_pa;
input arbpc2_pcxdp_shift_bufp1_px_l;
assign arbpc0_pcxdp_grant_pa = ~arbpc0_pcxdp_grant_bufp1_pa_l;
assign arbpc0_pcxdp_q0_hold_pa_l = ~arbpc0_pcxdp_q0_hold_bufp1_pa;
assign arbpc0_pcxdp_qsel0_pa = ~arbpc0_pcxdp_qsel0_bufp1_pa_l;
assign arbpc0_pcxdp_qsel1_pa_l = ~arbpc0_pcxdp_qsel1_bufp1_pa;
assign arbpc0_pcxdp_shift_px = ~arbpc0_pcxdp_shift_bufp1_px_l;
assign arbpc2_pcxdp_grant_pa = ~arbpc2_pcxdp_grant_bufp1_pa_l;
assign arbpc2_pcxdp_q0_hold_pa_l = ~arbpc2_pcxdp_q0_hold_bufp1_pa;
assign arbpc2_pcxdp_qsel0_pa = ~arbpc2_pcxdp_qsel0_bufp1_pa_l;
assign arbpc2_pcxdp_qsel1_pa_l = ~arbpc2_pcxdp_qsel1_bufp1_pa;
assign arbpc2_pcxdp_shift_px = ~arbpc2_pcxdp_shift_bufp1_px_l;
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sd_spi
(input clk,
input rst,
// SD Card interface
output reg sd_clk,
output sd_mosi,
input sd_miso,
// Controls
input [7:0] clk_div,
input [7:0] send_dat,
output [7:0] rcv_dat,
input go,
output ready);
reg [7:0] clk_ctr;
reg [3:0] bit_ctr;
wire bit_ready = (clk_ctr == 8'd0);
wire bit_busy = (clk_ctr != 8'd0);
wire bit_done = (clk_ctr == clk_div);
wire send_clk_hi = (clk_ctr == (clk_div>>1));
wire latch_dat = (clk_ctr == (clk_div - 8'd2));
wire send_clk_lo = (clk_ctr == (clk_div - 8'd1));
wire send_bit = (bit_ready && (bit_ctr != 0));
assign ready = (bit_ctr == 0);
always @(posedge clk)
if(rst)
clk_ctr <= 0;
else if(bit_done)
clk_ctr <= 0;
else if(bit_busy)
clk_ctr <= clk_ctr + 1;
else if(send_bit)
clk_ctr <= 1;
always @(posedge clk)
if(rst)
sd_clk <= 0;
else if(send_clk_hi)
sd_clk <= 1;
else if(send_clk_lo)
sd_clk <= 0;
always @(posedge clk)
if(rst)
bit_ctr <= 0;
else if(bit_done)
if(bit_ctr == 4'd8)
bit_ctr <= 0;
else
bit_ctr <= bit_ctr + 1;
else if(bit_ready & go)
bit_ctr <= 1;
reg [7:0] shift_reg;
always @(posedge clk)
if(go)
shift_reg <= send_dat;
else if(latch_dat)
shift_reg <= {shift_reg[6:0],sd_miso};
assign sd_mosi = shift_reg[7];
assign rcv_dat = shift_reg;
endmodule // sd_spi
|
#include <bits/stdc++.h> using namespace std; template <class T> inline void read(T& a) { char c = getchar(); int f = 1; a = 0; for (; c > 9 || c < 0 ; c = getchar()) if (c == - ) f = -1; for (; c <= 9 && c >= 0 ; c = getchar()) a = a * 10 + c - 48; a *= f; } const int o = 1e5 + 10; inline long long Max(long long a, long long b) { return a > b ? a : b; } long long T, n, k, a[o]; pair<long long, long long> p[o]; signed main() { for (read(T); T--;) { read(n); for (long long i = 1; i <= n; ++i) { read(k); for (long long j = 0; j < k; ++j) read(a[j]); a[k] = 0; for (long long j = k - 1; j + 1; --j) a[j] = Max(a[j + 1], a[j] - j); p[i] = make_pair(a[0], k); } sort(p + 1, p + 1 + n); for (long long i = 2, j = p[1].second; i <= n; j += p[i++].second) p[i].first = Max(p[i - 1].first, p[i].first - j); printf( %lld n , p[n].first + 1); } return 0; } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 19:26:51 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_util_vector_logic_0_0/system_util_vector_logic_0_0_stub.v
// Design : system_util_vector_logic_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "util_vector_logic,Vivado 2016.4" *)
module system_util_vector_logic_0_0(Op1, Op2, Res)
/* synthesis syn_black_box black_box_pad_pin="Op1[0:0],Op2[0:0],Res[0:0]" */;
input [0:0]Op1;
input [0:0]Op2;
output [0:0]Res;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O2BB2AI_PP_BLACKBOX_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2AI_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; const int N = 501; int n, m, a[N]; bool dp[2][N][N]; vector<int> sol; int main() { scanf( %d%d , &n, &m); for (int i = 0; i < n; ++i) scanf( %d , &a[i]); dp[0][0][0] = dp[0][a[0]][0] = dp[0][a[0]][a[0]] = true; int at = 0; for (int i = 1; i < n; ++i) { at ^= 1; for (int j = 0; j <= m; ++j) for (int k = 0; k <= m; ++k) { dp[at][j][k] = dp[at ^ 1][j][k]; if (a[i] <= j) dp[at][j][k] |= dp[at ^ 1][j - a[i]][k]; if (a[i] <= j && a[i] <= k && k <= j) dp[at][j][k] |= dp[at ^ 1][j - a[i]][k - a[i]]; } } for (int i = 0; i <= m; ++i) if (dp[at][m][i]) sol.push_back(i); printf( %d n , (int)sol.size()); for (int i = 0; i < (int)sol.size(); ++i) printf( %s%d , i ? : , sol[i]); puts( ); return 0; } |
module drv_bus_req(
input clk_sys,
input ready,
input r,
input w,
input in,
input [0:7] a1,
input [0:15] a2,
input [0:15] a3,
input zw,
output reg zg,
input ans_any,
output dw,
output dr,
output din,
output dpn,
output [0:3] dnb,
output [0:15] dad,
output [0:15] ddt
);
// registered data input/output
reg ir, iw, iin;
reg [0:7] ia1;
reg [0:15] ia2;
reg [0:15] ia3;
// request trigger
wire req = ready & (r | w | in);
localparam IDLE = 4'd0;
localparam REQ = 4'd1;
reg [0:0] state = IDLE;
always @ (posedge clk_sys) begin
case (state)
IDLE: begin
if (req) begin
ir <= r;
iw <= w;
iin <= in;
ia1 <= a1;
ia2 <= a2;
ia3 <= a3;
zg <= 1;
state <= REQ;
end
end
REQ: begin
if (zw & ans_any) begin
zg <= 0;
state <= IDLE;
end
end
endcase
end
wire zwzg = zw & zg;
assign dw = zwzg ? iw : 1'd0;
assign dr = zwzg ? ir : 1'd0;
assign din = zwzg ? iin : 1'd0;
assign dpn = zwzg ? ia1[3] : 1'd0;
assign dnb = zwzg ? ia1[4:7] : 4'd0;
assign dad = zwzg ? ia2 : 16'd0;
assign ddt = zwzg ? ia3 : 16'd0;
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
#include <iostream> #include <cmath> #include <vector> #include <algorithm> #include <set> #include <cstdio> #include <map> #include <queue> #include <ctime> #include <iomanip> #include <stack> #include <assert.h> #include <unordered_map> using namespace std; #define F first #define ll long long #define S second #define ld long double #define all(x) x.begin(), x.end() #define rep(i, n) for (int i = 0; i < (int)n; ++i) #define PI acos(-1) ll a, b, c, d, e, fl, maxn, cnt, k, s; vector <ll> ar; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); ll t = 1; cin >> t; while(t--) { cin >> a; ll last_time = -1; ll last_pos = 0; ll nap = 0; ll pos = 0; ll ans = 0; ll lst = 0, lsp = 0; queue <pair <ll, ll> > q; rep(i, a + 1) { ll p, p1; if (i != a) cin >> p >> p1; else p = (ll)1e15; if (!q.empty()) { pair <ll, ll> pp = q.front(); q.pop(); ll st = last_pos + nap * (pp.F - last_time); ll fin = last_pos + nap * (min(p, lst) - last_time); //cout << i << << st << << fin << << pp.S << n ; if (min(st, fin) <= pp.S && max(st, fin) >= pp.S) ++ans; } if (i == a) continue; if (p >= lst) { last_time = p; last_pos = lsp; lsp = p1; lst = abs(last_pos - p1) + p; if (last_pos > p1) nap = -1; else nap = 1; } q.push({p, p1}); } cout << ans << n ; } } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 100005; const int MOD = 1000000007; int N; int a[MAXN]; vector<int> ch[MAXN]; int dp[MAXN][2]; inline int add(int x, int y) { x += y; if (x >= MOD) x -= MOD; return x; } inline int mul(int x, int y) { return (long long)x * y % MOD; } void load() { scanf( %d , &N); for (int i = 1; i < N; i++) { int x; scanf( %d , &x); ch[x].push_back(i); } for (int i = 0; i < N; i++) scanf( %d , a + i); } int dfs(int x) { vector<int> tmp; for (int i = 0; i < ch[x].size(); i++) tmp.push_back(dfs(ch[x][i])); int prod = 1, sz = tmp.size(); for (int i = 0; i < sz; i++) prod = mul(prod, tmp[i]); if (a[x]) dp[x][1] = prod; else { dp[x][0] = prod; vector<int> suff(sz + 1); suff[sz] = 1; for (int i = sz - 1; i >= 0; i--) suff[i] = mul(suff[i + 1], tmp[i]); prod = 1; for (int i = 0; i < sz; i++) { dp[x][1] = add(dp[x][1], mul(mul(prod, suff[i + 1]), dp[ch[x][i]][1])); prod = mul(prod, tmp[i]); } } return add(dp[x][0], dp[x][1]); } int solve() { dfs(0); return dp[0][1]; } int main() { load(); printf( %d n , solve()); return 0; } |
// `define ASYNC_RESET
module fsm_test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b);
input clk, reset, button_a, button_b;
output reg red_a, green_a, red_b, green_b;
(* gentb_constant = 0 *)
wire reset;
integer state;
reg [3:0] cnt;
`ifdef ASYNC_RESET
always @(posedge clk, posedge reset)
`else
always @(posedge clk)
`endif
begin
cnt <= 0;
red_a <= 1;
red_b <= 1;
green_a <= 0;
green_b <= 0;
if (reset)
state <= 100;
else
case (state)
100: begin
if (button_a && !button_b)
state <= 200;
if (!button_a && button_b)
state <= 300;
end
200: begin
red_a <= 0;
green_a <= 1;
cnt <= cnt + 1;
if (cnt == 5)
state <= 210;
end
210: begin
red_a <= 0;
green_a <= cnt[0];
cnt <= cnt + 1;
if (cnt == 10)
state <= 100;
end
300: begin
red_b <= 0;
green_b <= 1;
cnt <= cnt + 1;
if (cnt == 5)
state <= 310;
end
310: begin
red_b <= 0;
green_b <= cnt[0];
cnt <= cnt + 1;
if (cnt == 10)
state <= 100;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> using namespace std; mt19937 rng((uint32_t)chrono::steady_clock::now().time_since_epoch().count()); void setIO(string name) { ios_base::sync_with_stdio(false); cin.tie(nullptr); cin.exceptions(istream::failbit); } const int inf = 0x3f3f3f3f, mod = 1e9 + 7, maxn = 1e5 + 5; vector<vector<pair<int, int>>> adj; vector<long long> pass, sub, weight, cost; void dfs(int c, int p) { if (p != -1 && adj[c].size() == 1) { sub[c] = 1; } for (auto i : adj[c]) { if (i.first != p) { dfs(i.first, c); pass[i.second] = sub[i.first]; sub[c] += sub[i.first]; } } } int main() { setIO( 1 ); int t; cin >> t; while (t--) { int n; cin >> n; long long s; cin >> s; adj = vector<vector<pair<int, int>>>(n); pass = sub = weight = cost = vector<long long>(n); for (int i = 0; i < n - 1; ++i) { int a, b; cin >> a >> b >> weight[i] >> cost[i]; --a, --b; adj[a].push_back({b, i}); adj[b].push_back({a, i}); } dfs(0, -1); pair<long long, long long> total; priority_queue<pair<long long, int>> one, two; for (int i = 0; i < n - 1; ++i) { if (cost[i] == 1) { total.first += pass[i] * weight[i]; one.push({pass[i] * (weight[i] - weight[i] / 2), i}); } else { total.second += pass[i] * weight[i]; two.push({pass[i] * (weight[i] - weight[i] / 2), i}); } } vector<long long> costs; while (total.first) { costs.push_back(total.first); pair<long long, int> cur = one.top(); one.pop(); total.first -= cur.first; weight[cur.second] /= 2; one.push( {pass[cur.second] * (weight[cur.second] - weight[cur.second] / 2), cur.second}); } costs.push_back(0); long long sol = 1e18, cnt = 0; while (total.second) { long long lo = 0, hi = (int)costs.size() - 1, mid, res = -1; while (lo <= hi) { mid = (lo + hi) / 2; if (costs[mid] + total.second <= s) { res = mid; hi = mid - 1; } else { lo = mid + 1; } } if (res != -1) { sol = min(sol, res + 2 * cnt); } pair<long long, int> cur = two.top(); two.pop(); total.second -= cur.first; weight[cur.second] /= 2; two.push( {pass[cur.second] * (weight[cur.second] - weight[cur.second] / 2), cur.second}); ++cnt; } long long lo = 0, hi = costs.size(), mid, res = -1; while (lo <= hi) { mid = (lo + hi) / 2; if (costs[mid] <= s) { res = mid; hi = mid - 1; } else { lo = mid + 1; } } if (res != -1) { sol = min(sol, res + 2 * cnt); } cout << min(sol, res + 2 * cnt) << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
/**
* lpflow_isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog wrapper for lpflow_isobufsrc with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_isobufsrc.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc_2 (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_isobufsrc_2 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRC_2_V
|
// Copyright (c) 2015 Wladimir J. van der Laan
// Distributed under the MIT software license, see the accompanying
// file COPYING or http://www.opensource.org/licenses/mit-license.php.
/* Very simple interface to PMOD SPI. Serial port accepts bytes in the
* form:
* 0001zzzz Followed by z+1 bytes. Transfer data to SPI.
* 001abcde Set parallel control flags: a CS, b DC, c RES, e VBATC, f VDDC
* */
`timescale 1 ns / 1 ps
`default_nettype none
module top(input clk,
output TXD, // UART TX
input RXD, // UART RX
input resetq,
output LED0, // Led
output LED1, // Led
output LED2, // Led
output LED4, // Center led
output PMOD_CS,
output PMOD_SDIN,
output PMOD_SCLK,
output PMOD_DC,
output PMOD_RES,
output PMOD_VBATC,
output PMOD_VDDC,
);
localparam MHZ = 12;
// ###### UART ##########################################
//
reg uart0_valid, uart0_busy;
wire [7:0] uart0_data_in;
wire [7:0] uart0_data_out = 0;
wire uart0_wr = 0;
wire uart0_rd = 1;
wire [31:0] uart_baud = ;
buart #(.CLKFREQ(MHZ * )) _uart0 (
.clk(clk),
.resetq(1),
.baud(uart_baud),
.rx(RXD),
.tx(TXD),
.rd(uart0_rd),
.wr(uart0_wr),
.valid(uart0_valid),
.busy(uart0_busy),
.tx_data(uart0_data_out),
.rx_data(uart0_data_in));
reg led0;
reg led4;
reg [4:0] outcount;
reg halfclk;
reg [3:0] spi_count; /* number of data bits */
reg [7:0] spi_data_out;
reg uart_processed; /* UART input byte processed */
always @(posedge clk) begin
// Acme clock divider 12MHz -> 6MHz (to get under max 10MHz)
halfclk <= ~halfclk;
// Handle SPI output
if (halfclk) begin
// rising edge
PMOD_SCLK <= 1;
end else begin
// falling edge
if (|spi_count) begin
// if active - load new data bit on falling edge
{PMOD_SDIN,spi_data_out} <= {spi_data_out[7:0],1'b1};
PMOD_SCLK <= 0;
spi_count <= spi_count - 1;
end
LED1 <= spi_count; // Just for fun
end
// Handle UART input, if not processed yet
if (uart0_valid && !uart_processed) begin
uart_processed <= 1;
if (|outcount) begin
// SPI transmission in progress
outcount <= outcount - 1;
spi_data_out <= uart0_data_in;
spi_count <= 8;
led0 <= ~led0; // Blinkenlights just for fun
end else begin
// Handle opcodes
casez (uart0_data_in)
8'b0001zzzz: begin
// Send next N+1 bytes to SPI
outcount <= (uart0_data_in & 5'b01111) + 1;
end
8'b001zzzzz: begin
// Set flags
{PMOD_CS,PMOD_DC,PMOD_RES,PMOD_VBATC,PMOD_VDDC} <= uart0_data_in[4:0];
end
default: ;
endcase
led4 <= ~led4; // Blinkenlights
end
end
// New data word coming in, reset processed flag
if (~uart0_valid)
uart_processed <= 0;
end
assign LED0 = led0;
assign LED4 = led4;
endmodule // top
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__MUX2_PP_BLACKBOX_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__mux2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2_PP_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; int n, f, r[4]; char names[4][16] = { Gryffindor , Hufflepuff , Ravenclaw , Slytherin }; int main() { scanf( %d , &n); vector<vector<int> > v; v.push_back(vector<int>(4)); for (int k = 0; k < (int)(n); k++) { char op; scanf( %c , &op); ((void)0); if (op != ? ) { for (int i = 0; i < (int)(4); i++) if (op == names[i][0]) { for (int j = 0; j < (int)(v.size()); j++) v[j][i]++; } } else { vector<vector<int> > nv; for (int j = 0; j < (int)(v.size()); j++) { int mx = 1 << 30; for (int i = 0; i < (int)(4); i++) mx = min(mx, v[j][i]); for (int i = 0; i < (int)(4); i++) if (v[j][i] == mx) { nv.push_back(v[j]); nv.back()[i]++; } } sort(nv.begin(), nv.end()); nv.erase(unique(nv.begin(), nv.end()), nv.end()); v = nv; } } for (int i = 0; i < (int)(v.size()); i++) { int mx = 1 << 30; for (int j = 0; j < (int)(4); j++) mx = min(mx, v[i][j]); for (int j = 0; j < (int)(4); j++) if (v[i][j] == mx) r[j] = 1; } for (int i = 0; i < (int)(4); i++) if (r[i]) puts(names[i]); return 0; } |
#include <bits/stdc++.h> using namespace std; const long long INF = (long long)1e16; const int N = 900300; const int K = 40; int n; long long a[N]; long long sum[N]; long long dp[N][2]; int par[N][2][3]; int intPoint[N]; int m; vector<int> ans; long long getCost(int L, int R, int f1, int f2) { int len = R - L; if (len == 1) { if (a[L] == 0) return 0; if (f1 == 0 || f2 == 0) return -1; return a[L]; } if (len == 2) { if (a[L] == a[L + 1]) return 0; if (a[L] < a[L + 1]) { if (f2 == 0) return -1; return abs(a[L + 1] - a[L]); } else { if (f1 == 0) return -1; return abs(a[L + 1] - a[L]); } } if (f1 == 0 && a[L] > a[L + 1]) return -1; if (f2 == 0 && a[R - 1] > a[R - 2]) return -1; long long cost = abs(sum[R] - sum[L]); if (len == 3) { if (a[L] + a[L + 2] <= a[L + 1]) return cost; if (f1 == 1 && f2 == 1) return cost; if (f1 == 0 && f2 == 0) return -1; return cost; } return cost; } void restoreAns(int L, int R, int f1, int f2) { int len = R - L; if (len == 1) { return; } if (len == 2) { if (a[L] == 0 || a[L + 1] == 0) return; ans.push_back(L); return; } if (f1 == 0 && a[L] != 0 && a[L + 1] != 0) { long long x = min(a[L], a[L + 1]); ans.push_back(L); a[L] -= x; a[L + 1] -= x; } if (f2 == 0 && a[R - 1] != 0 && a[R - 2] != 0) { long long x = min(a[R - 1], a[R - 2]); ans.push_back(R - 2); a[R - 2] -= x; a[R - 1] -= x; } for (int i = L; i < R - 1; i++) { if (a[i] != 0 && a[i + 1] != 0) { long long x = min(a[i], a[i + 1]); ans.push_back(i); a[i] -= x; a[i + 1] -= x; } } } int main() { scanf( %d , &n); for (int i = 0; i < n; i++) { scanf( %lld , &a[i]); sum[i + 1] = sum[i]; if (i % 2 == 0) sum[i + 1] += a[i]; else sum[i + 1] -= a[i]; } for (int i = 0; i <= n; i++) { if (i < 5 || i > n - 5) { intPoint[m++] = i; continue; } if (a[i - 1] <= a[i - 2] || a[i] <= a[i + 1]) intPoint[m++] = i; } for (int i = 0; i <= m; i++) dp[i][0] = dp[i][1] = -INF; dp[0][0] = 0; dp[0][1] = 0; for (int i = 0; i < m; i++) for (int f1 = 0; f1 < 2; f1++) { if (dp[i][f1] < 0) continue; for (int j = i + 1; j < min(m, i + K); j++) { for (int f2 = 0; f2 < 2 - f1; f2++) for (int f3 = 0; f3 < 2; f3++) { long long cost = getCost(intPoint[i], intPoint[j], f2, f3); if (cost == -1) continue; if (dp[i][f1] + cost > dp[j][f3]) { dp[j][f3] = dp[i][f1] + cost; par[j][f3][0] = i; par[j][f3][1] = f1; par[j][f3][2] = f2; } } } } int x = m - 1; int f = 0; if (dp[x][1] > dp[x][0]) f = 1; while (x > 0) { restoreAns(intPoint[par[x][f][0]], intPoint[x], par[x][f][2], f); int nx = par[x][f][0]; f = par[x][f][1]; x = nx; } printf( %d n , (int)ans.size()); for (int y : ans) printf( %d n , 1 + y); return 0; } |
#include <bits/stdc++.h> using namespace std; template <class T> inline void remax(T& A, T B) { if (A < B) A = B; } template <class T> inline void remin(T& A, T B) { if (A > B) A = B; } string ToString(long long num) { string ret; do { ret += ((num % 10) + 0 ); num /= 10; } while (num); reverse(ret.begin(), ret.end()); return ret; } long long ToNumber(string s) { long long r = 0, p = 1; for (int i = s.size() - 1; i >= 0; --i) r += (s[i] - 0 ) * p, p *= 10; return r; } long long Gcd(long long a, long long b) { while (a %= b ^= a ^= b ^= a) ; return b; } long long Power(long long base, long long power) { long long ret = 1; while (power) { if (power & 1) ret *= base; power >>= 1; base *= base; } return ret; } long long PowerMod(long long base, long long power, long long mod) { if (!power) return 1; if (power & 1) return (base * PowerMod(base, power - 1, mod)) % mod; return PowerMod((base * base) % mod, power >> 1, mod); } int Log(long long num, long long base) { int ret = 0; while (num) { ++ret; num /= base; } return ret; } int Count(long long mask) { int ret = 0; while (mask) { if (mask & 1) ++ret; mask >>= 1; } return ret; } inline void run() { int n, k, ans, sum; scanf( %d%d , &n, &k); ans = n, sum = (n << 1); while (true) { if (sum >= k) break; if (!n) break; --ans, ++sum, --n; } printf( %d n , ans); } int main() { ios_base::sync_with_stdio(false); cin.tie(nullptr), cout.tie(nullptr); run(); return 0; } |
/**
* bsg_cache_dma_to_wormhole.v
*
* This module interfaces bsg_cache_dma to a wormhole link.
* dma_pkts come in two flavors:
* - Write packets send a wormhole header flit, then an address flit, then N data flits (the
* evicted data)
* - Read packets send a womrhole header flit, then an address flit, then recieve
* N data flits (the fill data) asynchronously.
*/
`include "bsg_defines.v"
`include "bsg_noc_links.vh"
`include "bsg_cache.vh"
// TODO: Should be part of basejump stl
`include "bp_me_cache_defines.svh"
module bsg_cache_dma_to_wormhole
import bsg_noc_pkg::*;
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(dma_addr_width_p) // cache addr width (byte addr)
, parameter `BSG_INV_PARAM(dma_burst_len_p) // num of data beats in dma transfer
// flit width should match the cache dma width.
, parameter `BSG_INV_PARAM(wh_flit_width_p)
, parameter `BSG_INV_PARAM(wh_cid_width_p)
, parameter `BSG_INV_PARAM(wh_len_width_p)
, parameter `BSG_INV_PARAM(wh_cord_width_p)
, parameter dma_pkt_width_lp=`bsg_cache_dma_pkt_width(dma_addr_width_p)
, parameter wh_link_sif_width_lp=`bsg_ready_and_link_sif_width(wh_flit_width_p)
, parameter dma_data_width_lp=wh_flit_width_p
// Whether to buffer the returning data flits. May be necessary for timing purposes
, parameter buffer_return_p = 1
)
(
input clk_i
, input reset_i
, input [dma_pkt_width_lp-1:0] dma_pkt_i
, input dma_pkt_v_i
, output dma_pkt_yumi_o
, output logic [dma_data_width_lp-1:0] dma_data_o
, output logic dma_data_v_o
, input dma_data_ready_and_i
, input [dma_data_width_lp-1:0] dma_data_i
, input dma_data_v_i
, output logic dma_data_yumi_o
, input [wh_link_sif_width_lp-1:0] wh_link_sif_i
, output logic [wh_link_sif_width_lp-1:0] wh_link_sif_o
, input [wh_cord_width_p-1:0] my_wh_cord_i
, input [wh_cord_width_p-1:0] dest_wh_cord_i
, input [wh_cid_width_p-1:0] my_wh_cid_i
, input [wh_cid_width_p-1:0] dest_wh_cid_i
);
`declare_bsg_cache_dma_pkt_s(dma_addr_width_p);
`declare_bsg_ready_and_link_sif_s(wh_flit_width_p, wh_link_sif_s);
wh_link_sif_s wh_link_sif_in;
wh_link_sif_s wh_link_sif_out;
assign wh_link_sif_in = wh_link_sif_i;
assign wh_link_sif_o = wh_link_sif_out;
// dma pkt fifo
logic dma_pkt_ready_lo;
logic dma_pkt_v_lo;
logic dma_pkt_yumi_li;
bsg_cache_dma_pkt_s dma_pkt_lo;
// two fifo is needed here to avoid bubble between consecutive dma_pkts,
// which can occur with during a writeback->fill operation
bsg_two_fifo #(
.width_p(dma_pkt_width_lp)
) dma_pkt_fifo (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(dma_pkt_v_i)
,.data_i(dma_pkt_i)
,.ready_o(dma_pkt_ready_lo)
,.v_o(dma_pkt_v_lo)
,.data_o(dma_pkt_lo)
,.yumi_i(dma_pkt_yumi_li)
);
assign dma_pkt_yumi_o = dma_pkt_ready_lo & dma_pkt_v_i;
// FIFO for wormhole flits coming back to vcache.
logic return_fifo_v_lo;
logic [wh_flit_width_p-1:0] return_fifo_data_lo;
logic return_fifo_ready_li, return_fifo_yumi_li;
if (buffer_return_p) begin : br
bsg_two_fifo #(
.width_p(wh_flit_width_p)
) return_fifo (
.clk_i (clk_i)
,.reset_i (reset_i)
,.v_i (wh_link_sif_in.v)
,.data_i (wh_link_sif_in.data)
,.ready_o (wh_link_sif_out.ready_and_rev)
,.v_o (return_fifo_v_lo)
,.data_o (return_fifo_data_lo)
,.yumi_i (return_fifo_yumi_li)
);
assign return_fifo_yumi_li = return_fifo_ready_li & return_fifo_v_lo;
end else begin : nbr
assign return_fifo_v_lo = wh_link_sif_in.v;
assign return_fifo_data_lo = wh_link_sif_in.data;
assign wh_link_sif_out.ready_and_rev = return_fifo_ready_li;
assign return_fifo_yumi_li = wh_link_sif_out.ready_and_rev & wh_link_sif_in.v;
end
// counter
localparam count_width_lp = `BSG_SAFE_CLOG2(dma_burst_len_p);
logic send_clear_li;
logic send_up_li;
logic [count_width_lp-1:0] send_count_lo;
bsg_counter_clear_up #(
.max_val_p(dma_burst_len_p-1)
,.init_val_p(0)
) send_count (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(send_clear_li)
,.up_i(send_up_li)
,.count_o(send_count_lo)
);
// send FSM
enum logic [1:0] {
SEND_RESET
, SEND_READY
, SEND_ADDR
, SEND_DATA
} send_state_n, send_state_r;
`declare_bsg_cache_wh_header_flit_s(wh_flit_width_p,wh_cord_width_p,wh_len_width_p,wh_cid_width_p);
bsg_cache_wh_header_flit_s header_flit;
assign header_flit.unused = '0;
assign header_flit.write_not_read = dma_pkt_lo.write_not_read;
assign header_flit.src_cid = my_wh_cid_i;
assign header_flit.src_cord = my_wh_cord_i;
assign header_flit.len = dma_pkt_lo.write_not_read
? wh_len_width_p'(1+dma_burst_len_p) // header + addr + data
: wh_len_width_p'(1); // header + addr
assign header_flit.cord = dest_wh_cord_i;
assign header_flit.cid = dest_wh_cid_i;
always_comb begin
send_state_n = send_state_r;
dma_pkt_yumi_li = 1'b0;
send_clear_li = 1'b0;
send_up_li = 1'b0;
wh_link_sif_out.v = 1'b0;
wh_link_sif_out.data = dma_data_i;
dma_data_yumi_o = 1'b0;
case (send_state_r)
SEND_RESET: begin
send_state_n = SEND_READY;
end
SEND_READY: begin
wh_link_sif_out.data = header_flit;
if (dma_pkt_v_lo) begin
wh_link_sif_out.v = 1'b1;
send_state_n = (wh_link_sif_in.ready_and_rev & wh_link_sif_out.v)
? SEND_ADDR
: SEND_READY;
end
end
SEND_ADDR: begin
wh_link_sif_out.data = wh_flit_width_p'(dma_pkt_lo.addr);
if (dma_pkt_v_lo) begin
wh_link_sif_out.v = 1'b1;
dma_pkt_yumi_li = wh_link_sif_in.ready_and_rev & wh_link_sif_out.v;
send_state_n = dma_pkt_yumi_li
? (dma_pkt_lo.write_not_read ? SEND_DATA : SEND_READY)
: SEND_ADDR;
end
end
SEND_DATA: begin
wh_link_sif_out.data = dma_data_i;
if (dma_data_v_i) begin
wh_link_sif_out.v = 1'b1;
dma_data_yumi_o = wh_link_sif_in.ready_and_rev & wh_link_sif_out.v;
send_up_li = dma_data_yumi_o & (send_count_lo != dma_burst_len_p-1);
send_clear_li = dma_data_yumi_o & (send_count_lo == dma_burst_len_p-1);
send_state_n = send_clear_li
? SEND_READY
: SEND_DATA;
end
end
// should never happen
default: begin
send_state_n = SEND_READY;
end
endcase
end
// receiver FSM
logic recv_clear_li;
logic recv_up_li;
logic [count_width_lp-1:0] recv_count_lo;
bsg_counter_clear_up #(
.max_val_p(dma_burst_len_p-1)
,.init_val_p(0)
) recv_count (
.clk_i(clk_i)
,.reset_i(reset_i)
,.clear_i(recv_clear_li)
,.up_i(recv_up_li)
,.count_o(recv_count_lo)
);
typedef enum logic [1:0] {
RECV_RESET
, RECV_READY
, RECV_DATA
} recv_state_e;
recv_state_e recv_state_r, recv_state_n;
always_comb begin
recv_state_n = recv_state_r;
recv_clear_li = 1'b0;
recv_up_li = 1'b0;
return_fifo_ready_li = 1'b0;
dma_data_v_o = 1'b0;
dma_data_o = return_fifo_data_lo;
case (recv_state_r)
RECV_RESET: begin
recv_state_n = RECV_READY;
end
RECV_READY: begin
return_fifo_ready_li = 1'b1;
recv_state_n = return_fifo_yumi_li
? RECV_DATA
: RECV_READY;
end
RECV_DATA: begin
return_fifo_ready_li = dma_data_ready_and_i;
dma_data_v_o = return_fifo_v_lo;
recv_up_li = return_fifo_yumi_li & (recv_count_lo != dma_burst_len_p-1);
recv_clear_li = return_fifo_yumi_li & (recv_count_lo == dma_burst_len_p-1);
recv_state_n = recv_clear_li
? RECV_READY
: RECV_DATA;
end
default: begin
recv_state_n = RECV_READY;
end
endcase
end
// sequential logic
always_ff @ (posedge clk_i) begin
if (reset_i) begin
send_state_r <= SEND_RESET;
recv_state_r <= RECV_RESET;
end
else begin
send_state_r <= send_state_n;
recv_state_r <= recv_state_n;
end
end
//synopsys translate_off
if (wh_flit_width_p != dma_data_width_lp)
$error("WH flit width must be equal to DMA data width");
if (wh_flit_width_p < dma_addr_width_p)
$error("WH flit width must be larger than address width");
if (wh_len_width_p < `BSG_WIDTH(dma_burst_len_p+1))
$error("WH len width %d must be large enough to hold the dma transfer size %d", wh_len_width_p, `BSG_WIDTH(dma_burst_len_p+1));
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_dma_to_wormhole)
|
#include <bits/stdc++.h> using namespace std; int a[1000002], b[4000000], intialsum[1000003]; int q(int ind) { int sum = 0; while (ind > 0) { sum += b[ind]; ind -= ind & (-ind); } return sum; } void u(int ind, int n, int val) { while (ind <= n) { b[ind] += val; ind += ind & (-ind); } } int main() { { ios_base::sync_with_stdio(false); cin.tie(0); }; int i, j, k, l, n, m, t, h; cin >> n >> k; for (i = 1; i <= n; i++) { cin >> j; a[j]++; } for (i = 1; i <= n; i++) intialsum[i] = intialsum[i - 1] + a[i]; for (i = 1; i <= k; i++) { cin >> j; if (j > 0) { a[j]++; u(j, n, 1); } else { l = 1; h = n; while (h > l) { m = (l + h) >> 1; if (intialsum[m] + q(m) >= -j) h = m; else l = m + 1; } a[l]--; u(l, n, -1); } } for (i = 1; i <= n; i++) if (a[i] > 0) return cout << i << endl, 0; cout << 0 << endl; return 0; } |
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
David Fritz
seven segment display
*/
module mod_sseg(rst, clk, ie, de, iaddr, daddr, drw, din, iout, dout, sseg_an, sseg_display);
input rst;
input clk;
input ie,de;
input [31:0] iaddr, daddr;
input [1:0] drw;
input [31:0] din;
output [31:0] iout, dout;
output reg [3:0] sseg_an;
output [7:0] sseg_display;
/* by spec, the iout and dout signals must go hiZ when we're not using them */
wire [31:0] idata, ddata;
assign iout = idata;
assign dout = ddata;
/* the seven segment register */
reg [31:0] sseg;
assign idata = 32'h00000000;
assign ddata = sseg;
parameter CLOCK_FREQ = 25000000;
parameter TICKS = CLOCK_FREQ/240; /* 60Hz (by 4) tick clock */
reg [31:0] counter;
/* segment logic */
assign sseg_display = sseg_an == 4'b1110 ? sseg[7:0] :
sseg_an == 4'b1101 ? sseg[15:8] :
sseg_an == 4'b1011 ? sseg[23:16] :
sseg_an == 4'b0111 ? sseg[31:24] : sseg[7:0];
/* all data bus activity is negative edge triggered */
always @(negedge clk) begin
if (drw[0] && de && !rst) begin
sseg = din;
end else if (rst) begin
sseg = 32'h00000000;
counter = 0;
end
counter = counter + 1;
if (counter == TICKS) begin
counter = 0;
sseg_an = sseg_an == 4'b1110 ? 4'b1101 :
sseg_an == 4'b1101 ? 4'b1011 :
sseg_an == 4'b1011 ? 4'b0111 :
sseg_an == 4'b0111 ? 4'b1110 : 4'b1110;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const int MAXN = 1e6 + 10; typedef struct Item { long long v; int id; Item(long long a, int b) { v = a; id = b; } bool operator<(const Item &rhs) const { return v < rhs.v; } } Item; typedef struct Node { vector<int> p; vector<Item> pp; long long sum, r; int id; bool operator<(const Node &rhs) const { return pp.back().v < rhs.pp.back().v; } } Node; int n, m; Node nd[MAXN]; int bs(int i, int u, int v, long long x) { if (u > v) return -1; int mid = u + (v - u) / 2; if (nd[i].pp[mid].v == x) return mid; else if (nd[i].pp[mid].v > x) return bs(i, u, mid - 1, x); return bs(i, mid + 1, v, x); } int main(void) { ios::sync_with_stdio(false); cin.tie(0); cout << setprecision(10) << fixed; cin >> n; for (int i = 0; i < n; i++) { int k; cin >> k; nd[i].sum = 0; nd[i].id = i + 1; for (int j = 0; j < k; j++) { long long v; cin >> v; nd[i].sum += v; nd[i].p.push_back(v); } for (int j = 0; j < k; j++) nd[i].pp.push_back(Item(nd[i].sum - nd[i].p[j], j + 1)); sort(nd[i].pp.begin(), nd[i].pp.end()); nd[i].r = nd[i].pp.back().v; } sort(nd, nd + n); bool found = false; for (int i = 1; i < n; i++) { for (int j = i - 1; j >= 0; j--) { if (nd[j].r < nd[i].pp[0].v) break; for (int k = 0; k < nd[j].pp.size(); k++) { int pos = bs(i, 0, nd[i].pp.size() - 1, nd[j].pp[k].v); if (pos > -1) { found = true; cout << YES << endl; cout << nd[i].id << << nd[i].pp[pos].id << endl; cout << nd[j].id << << nd[j].pp[k].id << endl; break; } } if (found) break; } if (found) break; } if (!found) cout << NO << endl; cerr << execute time : << (double)clock() / CLOCKS_PER_SEC << endl; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAP_2_V
`define SKY130_FD_SC_LS__TAP_2_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog wrapper for tap with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tap_2 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__tap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__tap_2 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__tap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAP_2_V
|
#include <bits/stdc++.h> using namespace std; namespace io { inline char nc() { static char buf[100000], *p1 = buf, *p2 = buf; return p1 == p2 && (p2 = (p1 = buf) + fread(buf, 1, 100000, stdin), p1 == p2) ? EOF : *p1++; } template <class I> inline void fr(I &num) { num = 0; register char c = nc(); register int p = 1; while (c < 0 || c > 9 ) c == - ? p = -1, c = nc() : c = nc(); while (c >= 0 && c <= 9 ) num = num * 10 + c - 0 , c = nc(); num *= p; } template <class I> inline I Max(I p, I q) { return p > q ? p : q; } template <class I> inline I Min(I p, I q) { return p < q ? p : q; } template <class I> inline I A(I x) { return x < 0 ? -x : x; } template <class I> inline void sp(I &p, I &q) { I x = p; p = q, q = x; } template <class I> inline void ckMax(I &p, I q) { p = (p > q ? p : q); } template <class I> inline void ckMin(I &p, I q) { p = (p < q ? p : q); } }; // namespace io using io ::A; using io ::ckMax; using io ::ckMin; using io ::fr; using io ::Max; using io ::Min; using io ::nc; using io ::sp; const int N = 1000005; map<pair<int, int>, int> mp; int n, k, cn, d; inline void gcd(const int a, const int b) { return !b ? d = a, void() : gcd(b, a % b); } inline double dis(const int x, const int y) { return sqrt(1.0 * x * x + 1.0 * y * y); } struct ky { int x, y; double ds; bool operator<(const ky &p) const { return ds < p.ds; } }; vector<ky> vec[N]; vector<double> o; int main() { scanf( %d%d , &n, &k); const int kk = k >> 1; register double ans = 0; for (register int i = 1, x, y; i <= n; ++i) { scanf( %d%d , &x, &y); if ((!x) && (!y)) { vec[++cn].push_back((ky){x, y, 0}); continue; } gcd(A(x), A(y)); pair<int, int> p = make_pair(x / d, y / d); if (!mp[p]) mp[p] = ++cn; vec[mp[p]].push_back((ky){x, y, dis(x, y)}); } for (register int j = 1, i; j <= cn; ++j) { const int sz = vec[j].size(); register int mn = Min(kk, sz); std::sort(vec[j].begin(), vec[j].end()); for (i = 1; i <= mn; ++i) o.push_back(vec[j][sz - i].ds * ((k - i) - (i - 1))); double s = 0; mn = Min(k, sz); for (i = kk + 1; i <= mn; ++i) o.push_back(vec[j][i - kk - 1].ds * ((k - kk - 1) - kk) - 2.0 * s), s += vec[j][i - kk - 1].ds; } std::sort(o.begin(), o.end()); for (register int i = o.size() - 1; (~i) && k; --i) ans += o[i], --k; printf( %.9lf , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; long long H[200005]; int a[200005]; long long c[200005 << 2]; long long s[200005 << 2]; long long lz[200005 << 2]; vector<int> v[200005]; int u; int yl, yr; void build(int o, int l, int r) { if (l == r) { lz[o] = l; c[o] = l; s[o] = l; return; } int mid = (l + r) >> 1; build(o * 2, l, mid); build(o * 2 + 1, mid + 1, r); lz[o] = -1; c[o] = c[o * 2] + c[o * 2 + 1]; s[o] = min(s[o * 2], s[o * 2 + 1]); } void pushdown(int o, int l, int r) { if (l == r) return; if (lz[o] == -1) return; lz[o * 2] = lz[o]; lz[o * 2 + 1] = lz[o]; s[o * 2] = lz[o]; s[o * 2 + 1] = lz[o]; int mid = (l + r) >> 1; c[o * 2] = lz[o] * (mid - l + 1); c[o * 2 + 1] = lz[o] * (r - mid); lz[o] = -1; } void update(int o, int l, int r) { if (yl <= l && yr >= r) { c[o] = 1LL * u * (r - l + 1); s[o] = u; lz[o] = u; return; } pushdown(o, l, r); int mid = (l + r) >> 1; if (yl <= mid) update(o * 2, l, mid); if (yr > mid) update(o * 2 + 1, mid + 1, r); c[o] = c[o * 2] + c[o * 2 + 1]; s[o] = min(s[o * 2], s[o * 2 + 1]); if (lz[o * 2] == lz[o * 2 + 1] && lz[o * 2] >= 0) lz[o] = lz[o * 2]; } int query(int o, int l, int r) { if (l == r && c[o] < u) return l; if (l == r && c[o] >= u) return 0; if (lz[o] != -1 && lz[o] < u) return r; if (lz[o] != -1 && lz[o] >= u) return 0; int mid = (l + r) >> 1; if (s[o * 2 + 1] < u) return query(o * 2 + 1, mid + 1, r); else return query(o * 2, l, mid); } int main() { int n; scanf( %d , &n); int mx = -1; memset(a, 0, sizeof(a)); for (int i = 1; i < n + 1; ++i) { int tmp; scanf( %d , &tmp); a[tmp] = i; mx = max(mx, tmp); } for (int i = 1; i <= mx; ++i) { for (int j = 1; j * i <= mx; ++j) { if (a[j * i]) v[i].push_back(a[j * i]); } } for (int i = 0; i <= mx; ++i) sort(v[i].begin(), v[i].end()); long long sum = 1LL * n * (n + 1); build(1, 1, n); for (int i = mx; i >= 0; --i) { H[i] = sum - c[1]; int k = v[i].size(); if (k < 2) { continue; } u = n + 1; yl = v[i][1] + 1; yr = n; if (yl <= yr) update(1, 1, n); u = v[i][k - 1]; int pos = query(1, 1, n); pos = min(pos, v[i][1]); if (pos > v[i][0] && pos <= v[i][1]) { yl = v[i][0] + 1; yr = pos; update(1, 1, n); } u = v[i][k - 2]; pos = query(1, 1, n); pos = min(pos, v[i][0]); if (pos >= 1 && pos <= v[i][0]) { yl = 1; yr = pos; update(1, 1, n); } } long long ans = 0; for (int i = 1; i <= mx; ++i) { ans += 1LL * i * (H[i] - H[i - 1]); } printf( %I64d n , ans); } |
#include <bits/stdc++.h> using namespace std; const int dx[8] = {-2, -2, -1, -1, 1, 1, 2, 2}; const int dy[8] = {-1, 1, -2, 2, -2, 2, -1, 1}; int n, m; int xw, yw, xb, yb; int xtw, ytw, xtb, ytb; deque<pair<int, int>> ww, wb, bw, bb; int dist[1000][1000], parx[1000][1000], pary[1000][1000]; int crap; void shortestWay(int sx, int sy, int tx, int ty, deque<pair<int, int>> &res) { for (int i = 0; i < n; ++i) for (int j = 0; j < m; ++j) dist[i][j] = -1; dist[sx][sy] = 0; queue<pair<int, int>> q; q.push({sx, sy}); while (!q.empty()) { int x = q.front().first, y = q.front().second; q.pop(); if (x == tx && y == ty) break; for (int i = 0; i < 8; ++i) { int xx = x + dx[i], yy = y + dy[i]; if (xx < 0 || yy < 0 || xx >= n || yy >= m) continue; if (dist[xx][yy] == -1) { dist[xx][yy] = dist[x][y] + 1; parx[xx][yy] = x, pary[xx][yy] = y; q.push({xx, yy}); } } } int cx = tx, cy = ty; while (cx != sx || cy != sy) { res.push_front({cx, cy}); int ccx = parx[cx][cy]; cy = pary[cx][cy]; cx = ccx; } } void normal(deque<pair<int, int>> &way, int ox, int oy) { for (int i = 0; i < way.size(); ++i) { cout << way[i].first + 1 << << way[i].second + 1 << n << flush; if (way[i].first == ox && way[i].second == oy) exit(0); if (i < way.size() - 1) { cin >> ox >> oy; ox--; oy--; } } } void normalWhite() { cout << WHITE n << flush; normal(ww, xb, yb); } void normalBlack() { cout << BLACK n << flush; cin >> xw >> yw; xw--; yw--; normal(bb, xw, yw); } void advanced(deque<pair<int, int>> &way, int x, int y, int tx, int ty, int ox, int oy) { if (way.size() > 0) { normal(way, ox, oy); cin >> ox >> oy; ox--; oy--; x = way.back().first, y = way.back().second; } for (int i = 0; i < 8; ++i) { int xx = x + dx[i], yy = y + dy[i]; if (xx == ox && yy == oy) { cout << xx + 1 << << yy + 1 << n << flush; exit(0); } } deque<pair<int, int>> d; if (tx > x) { d.push_back({x + 1, y + 2}); d.push_back({x + 3, y + 1}); d.push_back({x + 1, y}); } else { d.push_back({x - 1, y + 2}); d.push_back({x - 3, y + 1}); d.push_back({x - 1, y}); } normal(d, ox, oy); } void advancedWhite() { cout << WHITE n << flush; advanced(wb, xw, yw, xtw, ytw, xb, yb); } void advancedBlack() { cout << BLACK n << flush; cin >> xw >> yw; xw--; yw--; advanced(bw, xb, yb, xtb, ytb, xw, yw); } int main() { cin >> n >> m >> xw >> yw >> xb >> yb; xw--; yw--; xb--; yb--; xtw = n / 2 - 1; ytw = m / 2 - 1; xtb = n / 2; ytb = m / 2 - 1; shortestWay(xw, yw, xtw, ytw, ww); shortestWay(xw, yw, xtb, ytb, wb); shortestWay(xb, yb, xtw, ytw, bw); shortestWay(xb, yb, xtb, ytb, bb); if ((xw + yw) % 2 != (xb + yb) % 2) { if (ww.size() <= bb.size()) normalWhite(); else if (wb.size() >= bb.size() + 2) normalBlack(); else advancedWhite(); } else { if (bb.size() < ww.size()) normalBlack(); else if (bw.size() > ww.size()) normalWhite(); else advancedBlack(); } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22OI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A22OI_FUNCTIONAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22OI_FUNCTIONAL_V |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int ben[11]; int n, k; int mem[505][505 * 11]; int arr[505 * 505]; int freqFav[100005]; int freqCards[100005]; int solve(int num, int rem) { if (rem == 0 || num == 0) return 0; int &ret = mem[num][rem]; if (~ret) return ret; for (int i = 0; i < min(k, rem); i++) { ret = max(ret, ben[i] + solve(num - 1, rem - i - 1)); } return ret; } int main() { memset(mem, -1, sizeof(mem)); scanf( %d %d , &n, &k); for (int i = 0; i < k * n; i++) { scanf( %d , arr + i); freqCards[arr[i]]++; } for (int i = 0; i < n; i++) { int fav; scanf( %d , &fav); freqFav[fav]++; } for (int i = 0; i < k; i++) { scanf( %d , ben + i); } int res = 0; for (int i = 0; i < 100005; i++) { res += solve(freqFav[i], freqCards[i]); } printf( %d n , res); return 0; } |
#include <bits/stdc++.h> using namespace std; int dist[2 * 100000 + 2 + 5], N, K; vector<int> G[2 * 100000 + 2 + 5]; void addedge(const string &wall, const string &wall2, int i, int offs) { int here = i + offs, there = i + N - offs; if (wall[i] == X ) return; if (i != 0 && wall[i - 1] != X ) G[here].push_back(here - 1); if (i == N - 1 || wall[i + 1] != X ) G[here].push_back(here + 1); if (i + K >= N) { G[here].push_back(2 * N); } else if (wall2[i + K] != X ) { G[here].push_back(there + K); } } int main() { ios_base::sync_with_stdio(0); cin.tie(0); string L, R; cin >> N >> K >> L >> R; for (int i = 0; i < N; i++) { addedge(L, R, i, 0); addedge(R, L, i, N); } memset(dist, -1, sizeof(dist)); queue<int> q; dist[0] = 0; q.push(0); while (!q.empty()) { int fr = q.front(), d = dist[fr]; q.pop(); for (int to : G[fr]) { if (dist[to] == -1 && (to % N > d || to >= 2 * N)) { dist[to] = d + 1; q.push(to); } } } if (dist[2 * N] != -1 || dist[2 * N + 1] != -1) cout << YES n ; else cout << NO n ; } |
#include <bits/stdc++.h> using namespace std; int n, a[1005] = {0, 1, 1, 1, 2, 1, 2, 1, 5, 2, 2, 1, 5, 1, 2, 1, 14, 1, 5, 1, 5, 2, 2, 1, 15, 2, 2, 5, 4, 1, 4, 1, 51, 1, 2, 1, 14, 1, 2, 2, 14, 1, 6, 1, 4, 2, 2, 1, 52, 2, 5, 1, 5, 1, 15, 2, 13, 2, 2, 1, 13, 1, 2, 4, 267, 1, 4, 1, 5, 1, 4, 1, 50, 1, 2, 3, 4, 1, 6, 1, 52, 15, 2, 1, 15, 1, 2, 1, 12, 1, 10, 1, 4, 2}; int main() { scanf( %d , &n); printf( %d , a[n]); return 0; } |
//=========================================================================
//MIDO
`timescale 1 ps / 1 ps
module top_mido(
input reset,
input clk,
//-----------------------------------mdio ½Ó¿Ú---------------------------------
output mdc,//Êä³ö¸øÍⲿоƬµÄʱÖÓ
inout mdio,
output [3:0] port_link
);
/************Ä£¿éÁ¬½ÓÇø**************/
wire req_enb;//ʹÄÜÐźţ¬ÀàËÆÓÚƬѡÐźÅ
wire [1:0] req_op; //±¾´ÎÇëÇóµÄ²Ù×÷ģʽ [1]ÓÐЧΪ¶Á£¬[0]ÓÐЧΪд
wire [4:0] phy_addr;//phyоƬѡÔñ
wire [4:0] reg_addr;//phyоƬÖеļĴæÆ÷Ñ¡Ôñ
wire [15:0] data_phy;
//--------------¸øÓû§µÄµ±Ç°Ã¦ÏÐÐźÅ---------------------
wire work_flag;//1:ÕýÔÚ¹¤×÷״̬ 0£º´¦ÓÚÏÐÖÃ״̬
//-----------------------------------
wire [15:0] data_sta;
wire sta_enb;
mdio_mdc mdio_mdc(
.reset(reset),
.clk(clk),
//-----------------------------------mdio ½Ó¿Ú---------------------------------
.mdc(mdc),//Êä³ö¸øÍⲿоƬµÄʱÖÓ
.mdio(mdio),
//--------------Óû§¸ø³öµÄ²Ù×÷Ö¸Áî×é---------------------
.req_enb(req_enb),//ʹÄÜÐźţ¬ÀàËÆÓÚƬѡÐźÅ
.req_op(req_op), //±¾´ÎÇëÇóµÄ²Ù×÷ģʽ [1]ÓÐЧΪ¶Á£¬[0]ÓÐЧΪд
.phy_addr(phy_addr),//phyоƬѡÔñ
.reg_addr(reg_addr),//phyоƬÖеļĴæÆ÷Ñ¡Ôñ
.data_phy(data_phy),
//--------------¸øÓû§µÄµ±Ç°Ã¦ÏÐÐźÅ---------------------
.work_flag(work_flag),//1:ÕýÔÚ¹¤×÷״̬ 0£º´¦ÓÚÏÐÖÃ״̬
//-----------------------------------
.data_sta(data_sta),
.sta_enb(sta_enb)
);
reg_access reg_access (
.clk(clk),
.data_sta(data_sta),
.phy_addr(phy_addr),
.port_link(port_link),
.reg_addr(reg_addr),
.req_enb(req_enb),
.req_op(req_op),
.reset(reset),
.sta_enb(sta_enb),
.work_bit(work_flag)
);
endmodule
|
/*
* downloaded from http://electrosofts.com/verilog/fifo.html
* only changed names and defines
*/
`include "fifo.v"
`define DATA_WIDTH 8
`define ADDR_WIDTH 8
module fifo_test();
reg clk, rst, wr_en, rd_en ;
reg[`DATA_WIDTH-1:0] buf_in;
reg[`DATA_WIDTH-1:0] tempdata;
wire [`DATA_WIDTH-1:0] buf_out;
wire [`ADDR_WIDTH-1:0] fifo_counter;
fifo #(.data_width(`DATA_WIDTH), .addr_width(`ADDR_WIDTH))
ff( .clk(clk), .rst(rst), .data_in(buf_in), .data_out(buf_out),
.wr_en(wr_en), .rd_en(rd_en), .empty(buf_empty),
.full(buf_full), .cnt(fifo_counter));
initial
begin
clk = 0;
rst = 1;
rd_en = 0;
wr_en = 0;
tempdata = 0;
buf_in = 0;
#15 rst = 0;
push(1);
fork
push(2);
pop(tempdata);
join //push and pop together
push(10);
push(20);
push(30);
push(40);
push(50);
push(60);
push(70);
push(80);
push(90);
push(100);
push(110);
push(120);
push(130);
pop(tempdata);
push(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
push(140);
pop(tempdata);
push(tempdata);//
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
pop(tempdata);
push(5);
pop(tempdata);
$finish;
end
always
#5 clk = ~clk;
task push;
input[`DATA_WIDTH-1:0] data;
if( buf_full )
$display("---Cannot push: Buffer Full---");
else
begin
$display("push ", data);
buf_in = data;
wr_en = 1;
@(posedge clk);
#1 wr_en = 0;
end
endtask
task pop;
output [`DATA_WIDTH-1:0] data;
if( buf_empty )
$display("---Cannot Pop: Buffer Empty---");
else
begin
rd_en = 1;
@(posedge clk);
#1 rd_en = 0;
data = buf_out;
$display("pop ", data);
end
endtask
endmodule
|
#include <bits/stdc++.h> using namespace std; const int N = 100010; const long long INF = 1LL << 55; struct Tree { Tree *nex[26]; vector<int> G[2]; int deep; Tree() { for (int i = 0; i < 26; i++) nex[i] = NULL; deep = 0; } }; Tree *tree; void Insert(char *s, int u, int id) { Tree *p = tree; for (int i = 0; s[i]; i++) { int a = s[i] - a ; if (p->nex[a] == NULL) { Tree *q = new Tree; q->deep = i + 1; p->nex[a] = q; } p = p->nex[a]; p->G[u].push_back(id); } } char vis1[N], vis2[N]; int ans[N]; long long ret; void DFS(Tree *t) { for (int i = 0; i < 26; i++) if (t->nex[i]) DFS(t->nex[i]); int a = 0; int b = t->G[1].size(); for (int i = 0; i < t->G[0].size(); i++) { while (a < b && vis2[t->G[1][a]]) a++; if (a >= b) break; int v = t->G[0][i]; if (!vis1[v]) { vis1[v] = 1; vis2[t->G[1][a]] = 1; ret += (long long)(t->deep); ans[v] = t->G[1][a++]; } } } int main() { int i, j, k, m, n; char s[800010]; while (scanf( %d , &n) == 1) { tree = new Tree; for (i = 1; i <= n; i++) tree->G[0].push_back(i); for (i = 1; i <= n; i++) tree->G[1].push_back(i); for (i = 1; i <= n; i++) scanf( %s , s), Insert(s, 0, i); for (i = 1; i <= n; i++) scanf( %s , s), Insert(s, 1, i); memset(vis1, 0, sizeof(vis1)); memset(vis2, 0, sizeof(vis2)); ret = 0; DFS(tree); printf( %I64d n , ret); for (i = 1; i <= n; i++) printf( %d %d n , i, ans[i]); } return 0; } |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build Thu Jun 15 18:39:09 MDT 2017
// Date : Fri Sep 22 23:01:14 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_4_stub.v
// Design : zqynq_lab_1_design_auto_pc_4
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wid, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awaddr, m_axi_awprot, m_axi_awvalid,
m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid, m_axi_wready, m_axi_bresp,
m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot, m_axi_arvalid, m_axi_arready,
m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready" */;
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [3:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [3:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
output [31:0]m_axi_awaddr;
output [2:0]m_axi_awprot;
output m_axi_awvalid;
input m_axi_awready;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wvalid;
input m_axi_wready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
output m_axi_bready;
output [31:0]m_axi_araddr;
output [2:0]m_axi_arprot;
output m_axi_arvalid;
input m_axi_arready;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rvalid;
output m_axi_rready;
endmodule
|
#include <bits/stdc++.h> using namespace std; long long N = 0, M, K; long long MOD = 998244353; string S, S1; struct st { long long x, i; }; bool operator<(const st& a, const st& b) { if (a.x == b.x) return a.i < b.i; return a.x < b.x; } long long gcd(long long a, long long b) { while (b > 0) { a %= b; swap(a, b); } return a; } long long fact(long long x) { long long x1 = 1; while (x >= 1) { x1 *= x; x--; } return x1; } void prime(long long n, vector<long long>& pr) { vector<long long> lp(n + 90); for (long long i = 2; i <= n; ++i) { if (!lp[i]) { pr.push_back(i); lp[i] = i; } for (long long j = 0; j < pr.size() && pr[j] <= lp[i] && i * pr[j] <= n; ++j) { lp[i * pr[j]] = pr[j]; } } } void dfs(long long x, vector<long long>& b, vector<long long>& w, vector<vector<long long>>& v) { w[x] = 1; b.push_back(x); for (long long i : v[x]) { if (!w[i]) dfs(i, b, w, v); } } signed main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); string s, s1; long long n, k = 0, m; long long x = 0, y = 0, ans = 0; cin >> s >> n; vector<long long> a; for (long long i = 0; i < n; i++) { s1 = ; cin >> x >> y >> k; m = y - x + 1; k = k % m; for (long long j = y - k; j <= y - 1; j++) s1 += s[j]; s.erase(y - k, k); s.insert(x - 1, s1); } cout << s << n ; cin >> N; return 0; } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f, N = 3.1e5; int n, m, dis[N], fm[N]; vector<int> vec[N]; void bfs() { memset(dis, 0x3f, sizeof(dis)); queue<int> q; q.push(1); dis[1] = 0; while (!q.empty()) { int u = q.front(); q.pop(); for (int v : vec[u]) if (dis[v] == INF) dis[v] = dis[u] + 1, fm[v] = u, q.push(v); } } int x[N], y[N], fa[N], sz[N], d[N]; bool vis[N]; int find(int u) { return u == fa[u] ? u : fa[u] = find(fa[u]); } int main() { ios::sync_with_stdio(0); cin.tie(0); cin >> n >> m; for (int i = 1; i <= m; i++) cin >> x[i] >> y[i], vec[x[i]].push_back(y[i]), vec[y[i]].push_back(x[i]); bfs(); stack<int> s; if (dis[n] <= 4) for (int i = n; i; i = fm[i]) s.push(i); else { bool ok = 0; for (int i = 1; i <= n; i++) if (dis[i] == 2) { s.push(n); s.push(1); s.push(i); s.push(fm[i]); s.push(1); ok = 1; break; } if (!ok) { for (int i = 1; i <= n; i++) fa[i] = i, sz[i] = 1; for (int i = 1; i <= m; i++) if (x[i] != 1 && y[i] != 1 && dis[x[i]] == 1 && dis[y[i]] == 1) { int u = x[i], v = y[i]; d[u]++, d[v]++; int fv = find(v), fu = find(u); if (fu == fv) continue; fa[fv] = fu, sz[fu] += sz[fv]; } for (int i = 1; i <= n; i++) if (dis[i] == 1 && d[i] != sz[find(i)] - 1) { for (int v : vec[i]) if (v != 1) vis[v] = 1; for (int v : vec[i]) if (v != 1) { bool Get = 0; for (int vv : vec[v]) if (vv != 1 && vv != i && !vis[vv]) { s.push(n); s.push(i); s.push(vv); s.push(v); s.push(i); s.push(1); Get = 1; break; } if (Get) break; } break; } } } cout << int(s.size() - 1) << endl; while (!s.empty()) cout << s.top() << , s.pop(); return 0; } |
module lc3_pipeline_stage4(
input reset,
input clk,
input stall,
input [5:0] state,
input [19:0] I_DR,
input [1:0] I_WBtype,
input [2:0] I_Memtype,
input [15:0] I_Res,
output [19:0] O_DR,
output reg [1:0] O_WBtype,
output [15:0] O_Res,
input [15:0] memdata,
output [15:0] memaddr,
output memtype,
output [15:0] memdatawr,
output memapply,
output reg [2:0] CC,
output inst_ld
);
reg [15:0] Res;
reg [19:0] DR;
reg [2:0] Memtype;
assign memdatawr=DR[15:0];
assign memaddr=Res;
assign memapply=Memtype[2]&state[4];
assign memtype=Memtype[0];
assign O_Res=( (memapply&~memtype)?memdata:Res );
assign O_DR=DR;
always@(negedge clk or posedge reset) begin
if(reset) begin
//nothing to do
end else begin
if(~stall) begin
DR<=I_DR;
Res<=I_Res;
Memtype<=I_Memtype;
O_WBtype<=I_WBtype;
end
end
end
always@(*) begin
if(memdata==16'b0)
CC=3'b010;
else if(memdata[15]==1)
CC=3'b100;
else
CC=3'b001;
end
assign inst_ld=Memtype[2]&~Memtype[0];
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long int t; t = 1; while (t--) { long long int n, c1 = 0, c2 = 0, x; cin >> n; while (n--) { cin >> x; if (x == 1) c1++; else c2++; } x = min(c1, c2); c1 -= x; c2 -= x; cout << x + (c1 / 3); } return 0; } |
#include <bits/stdc++.h> using namespace std; int mult(int a, int b) { return ((long long)a * b) % 1000000007; } int binaryPow(int n, int p) { int acc = 1; while (p) { if (p & 1) acc = mult(acc, n); n = mult(n, n); p >>= 1; } return acc; } int modularInv(int n) { return binaryPow(n, 1000000007 - 2); } int main() { int k, a, b; cin >> k >> a >> b; int pa = mult(a, modularInv(a + b)); int pb = mult(b, modularInv(a + b)); int modPB = modularInv(pb); int dp[k + 1][k + 1]; for (int i = k; i >= 1; i--) { for (int j = k; j >= 0; j--) { if (i + j < k) { dp[i][j] = (mult(pa, dp[i + 1][j]) + mult(pb, dp[i][i + j])) % 1000000007; } else { dp[i][j] = (i + j + mult(pa, modPB)) % 1000000007; } } } cout << dp[1][0] << n ; return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_TB_V
`define SKY130_FD_SC_HVL__DFSTP_TB_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfstp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 SET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 SET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__dfstp dut (.D(D), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_TB_V
|
#include <bits/stdc++.h> const int N = 2e5 + 5; using namespace std; vector<int> G[N]; long long b[N]; int vis[N]; long long ans[N]; long long flag = 1; void dfs(int x, int fa) { long long minn = 0x3f3f3f3f; if (b[x] == -1) { for (int i = 0; i < G[x].size(); i++) { int g = G[x][i]; if (!vis[g]) { vis[g] = 1; minn = min(minn, b[g]); dfs(g, x); } if (minn != 0x3f3f3f3f) b[x] = minn; else b[x] = b[fa]; } } else { for (int i = 0; i < G[x].size(); i++) { int g = G[x][i]; if (!vis[g]) { vis[g] = 1; dfs(g, x); } } } } void dfs2(int x, int fa) { for (int i = 0; i < G[x].size(); i++) { int g = G[x][i]; if (!vis[g]) { vis[g] = 1; ans[g] = b[g] - b[x]; if (ans[g] < 0) { flag = 0; return; } dfs2(g, x); } } } int main() { int n; cin >> n; for (int i = 2; i <= n; i++) { int u; cin >> u; G[i].push_back(u); G[u].push_back(i); } for (int i = 1; i <= n; i++) cin >> b[i]; vis[1] = 1; dfs(1, -1); memset(vis, 0, sizeof vis); vis[1] = 1; ans[1] = b[1]; dfs2(1, -1); if (flag) { long long res = 0; for (int i = 1; i <= n; i++) if (ans[i] > 0) res += ans[i]; cout << res << endl; } else cout << -1 << endl; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); int n, w; cin >> n >> w; vector<int> a(n), b(n); for (int& v : a) cin >> v; for (int& v : b) cin >> v; double l = 0, r = 2e9; for (int t = 0; t < 500; t++) { double m = (l + r) / 2; double now = m; for (int i = 0; i < n && now >= 0; i++) { now -= (w + now) / a[i]; if (now < 0) break; now -= (w + now) / b[(i + 1) % n]; } if (now >= 0) r = m; else l = m; } if (r == 2e9) cout << -1 << n ; else cout << fixed << setprecision(10) << r << n ; } |
#include <bits/stdc++.h> using namespace std; void setIO(string name = ) { ios_base::sync_with_stdio(0); cin.tie(0); if (!name.empty()) { freopen((name + .in ).c_str(), r , stdin); freopen((name + .out ).c_str(), w , stdout); } } long long calc(long long a, long long b) { return (a + a * b) * b / 2; } int main() { setIO(); long long a, b; cin >> a >> b; if (b == 1) { cout << a; return 0; } long long cur; if (b % 2) cur = (b + 1) / 2 * b; else cur = b / 2 * (b + 1); if (a <= b || a < cur || b >= 400000) { cout << -1; return 0; } vector<long long> divs; for (long long i = 1; i * i <= a; i++) { if (a % i == 0) { if (i == a / i) divs.push_back(i); else { divs.push_back(i); divs.push_back(a / i); } } } sort(divs.begin(), divs.end()); for (int i = (int)divs.size() - 1; i >= 0; i--) { if (calc(divs[i], b) <= a && (calc(divs[i], b) % divs[i] == 0)) { long long cur = divs[i]; for (int j = 1; j <= b; j++) { if (j != b) { cout << cur * j << ; a -= cur * j; } else { cout << a; return 0; } } } } cout << -1; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:40:18 03/10/2016
// Design Name:
// Module Name: Decodificador
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Decodificador(
input [6:0] Cuenta,
output reg [7:0] catodo1,catodo2,catodo3,catodo4
);
always @(*)
begin
case (Cuenta)
6'd0: begin
catodo1 <= 8'b00000011;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd1: begin
catodo1 <= 8'b10011111;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd2: begin
catodo1 <= 8'b00100101;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd3: begin
catodo1 <= 8'b00001101;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd4: begin
catodo1 <= 8'b10011001;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd5: begin
catodo1 <= 8'b01001001;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd6: begin
catodo1 <= 8'b01000001;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd7: begin
catodo1 <= 8'b00011111;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd8: begin
catodo1 <= 8'b00000001;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd9: begin
catodo1 <= 8'b00011001;
catodo2 <= 8'b00000011;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd10: begin
catodo1 <= 8'b00000011;
catodo2 <= 8'b10011111;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd11: begin
catodo1 <= 8'b10011111;
catodo2 <= 8'b10011111;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd12: begin
catodo1 <= 8'b00100101;
catodo2 <= 8'b10011111;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd13: begin
catodo1 <= 8'b00001101;
catodo2 <= 8'b10011111;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd14: begin
catodo1 <= 8'b10011001;
catodo2 <= 8'b10011111;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
6'd15: begin
catodo1 <= 8'b01001001;
catodo2 <= 8'b10011111;
catodo3 <= 8'b00000011;
catodo4 <= 8'b00000011;
end
default: begin
catodo1 <= 8'b10011111;
catodo2 <= 8'b10011111;
catodo3 <= 8'b10011111;
catodo4 <= 8'b10011111;
end
endcase
end
endmodule
|
#include <bits/stdc++.h> #pragma optimize( SEX_ON_THE_BEACH ) #pragma GCC optimize( unroll-loops ) #pragma GCC optimize( O3 ) #pragma GCC optimize( Ofast ) #pragma GCC optimize( fast-math ) #pragma GCC optimize( no-stack-protector ) #pragma GCC target( sse,sse2,sse3,ssse3,popcnt,abm,mmx,tune=native ) using ll = long long int; using ull = unsigned long long int; using dd = double; using ldd = long double; namespace someUsefull { template <typename T1, typename T2> inline void checkMin(T1& a, T2 b) { if (a > b) a = b; } template <typename T1, typename T2> inline void checkMax(T1& a, T2 b) { if (a < b) a = b; } const int _bitfunctions_size_ = 16; const int _bitfunctions_mask_ = (1 << _bitfunctions_size_) - 1; char* _bits_count_; inline void _build_bits_count_() { _bits_count_ = new char[1 << _bitfunctions_size_]; for (int i = 1; i < (1 << _bitfunctions_size_); ++i) { _bits_count_[i] = _bits_count_[i >> 1]; if (i & 1) ++_bits_count_[i]; } } template <typename T1 = char, typename T2 = int> inline T1 popcnt(T2 x) { T1 ans = 0; while (x) { ans += _bits_count_[x & _bitfunctions_mask_]; x >>= _bitfunctions_size_; } return ans; } } // namespace someUsefull namespace operators { template <typename T1, typename T2> std::istream& operator>>(std::istream& in, std::pair<T1, T2>& x) { in >> x.first >> x.second; return in; } template <typename T1, typename T2> std::ostream& operator<<(std::ostream& out, std::pair<T1, T2> x) { out << x.first << << x.second; return out; } template <typename T1> std::istream& operator>>(std::istream& in, std::vector<T1>& x) { for (auto& i : x) in >> i; return in; } template <typename T1> std::ostream& operator<<(std::ostream& out, std::vector<T1>& x) { for (auto& i : x) out << i << ; return out; } } // namespace operators using namespace std; using namespace operators; using namespace someUsefull; vector<vector<int>> gr; vector<pair<int, int>> ed; vector<int> d; void dfs(int v, int _d = 0, int p = -1) { d[v] = _d; for (int to : gr[v]) { if (to != p) dfs(to, _d + 1, v); } } struct Tree { const int _size = 1 << 19; int n, t; vector<pair<int, int>> tree; vector<int> upd; vector<int> d; vector<int> pre; vector<int> tin, tout, tos; void dfs(int v, int _d = 0, int p = -1) { d[v] = _d; pre[v] = p; tin[v] = tos.size(); tos.push_back(v); for (int to : gr[v]) { if (to != p) dfs(to, _d + 1, v); } tout[v] = tos.size(); } pair<int, int> merge(pair<int, int> a, pair<int, int> b) { return {max(a.first, b.first), max(a.second, b.second)}; } Tree(int v) { tree.resize(_size << 1, {0, 0}); upd.resize(_size << 1, 0); n = gr.size(); t = 0; d.resize(n); tin.resize(n); tout.resize(n); pre.resize(n); 0; ; dfs(v); 0; ; for (int i = 0; i < n; ++i) tree[_size + i].first = d[tos[i]]; for (int i = _size - 1; i > 0; --i) tree[i] = merge(tree[i << 1], tree[i << 1 | 1]); } void change(int v) { upd[v] ^= 1; swap(tree[v].first, tree[v].second); } void push(int v) { if (!upd[v]) return; change(v << 1); change(v << 1 | 1); upd[v] = 0; } void update(int v, int l, int r, int fl, int fr) { if (r <= l || r <= fl || fr <= l) return; if (fl <= l && r <= fr) { change(v); return; } push(v); update(v << 1, l, (r + l) >> 1, fl, fr); update(v << 1 | 1, (r + l) >> 1, r, fl, fr); tree[v] = merge(tree[v << 1], tree[v << 1 | 1]); } int add(int a, int b) { if (pre[a] != b) swap(a, b); update(1, 0, _size, tin[a], tout[a]); return tree[1].first; } }; void solve(int test) { int n; cin >> n; gr.resize(n); vector<int> type(n - 1); for (int i = 0; i < n - 1; ++i) { int a, b; cin >> a >> b >> type[i]; --a; --b; ed.push_back({a, b}); gr[a].push_back(b); gr[b].push_back(a); } d.resize(n); d.assign(n, -1); dfs(0); int v = 0; for (int i = 0; i < n; ++i) if (d[v] < d[i]) v = i; dfs(v); int L = v; int R = 0; for (int i = 0; i < n; ++i) if (d[R] < d[i]) R = i; 0; ; 0; ; Tree LT(L), RT(R); 0; ; for (int i = 0; i < n - 1; ++i) { if (type[i]) LT.add(ed[i].first, ed[i].second), RT.add(ed[i].first, ed[i].second); } int m; cin >> m; for (int i = 0; i < m; ++i) { int x; cin >> x; --x; int ans = 0; checkMax(ans, LT.add(ed[x].first, ed[x].second)); checkMax(ans, RT.add(ed[x].first, ed[x].second)); cout << ans << n ; } } signed main() { ios_base::sync_with_stdio(false); cout.tie(0); cin.tie(0); _build_bits_count_(); cout << setprecision(12) << fixed; int t = 1; for (int i = 0; i < t; ++i) { 0; ; solve(i + 1); } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 5e5 + 5; int n = 5e5, f[N], s[N]; vector<int> v[N]; int q, a[N], c[N]; int main() { int i, j, t; long long ans; for (i = 1; i <= n; i = i + 1) { if (i == 1) f[i] = 1; for (j = i; j <= n; j = j + i) { v[j].push_back(i); if (j > i) f[j] -= f[i]; } } scanf( %d%d , &n, &q); for (i = 1; i <= n; i = i + 1) scanf( %d , a + i); ans = 0; while (q--) { scanf( %d , &i); t = v[a[i]].size(); if (c[i]) { c[i] = 0; i = a[i]; for (j = 0; j < t; j = j + 1) ans -= f[v[i][j]] * (--s[v[i][j]]); } else { c[i] = 1; i = a[i]; for (j = 0; j < t; j = j + 1) ans += f[v[i][j]] * (s[v[i][j]]++); } cout << ans << endl; } return 0; } |
module SensorFSM (
input Reset_n_i,
input Clk_i,
input In0_i,
input In1_i,
input In2_i,
input In3_i,
input In4_i,
input In5_i,
input In6_i,
input In7_i,
input In8_i,
input In9_i,
output Out0_o,
output Out1_o,
output Out2_o,
output Out3_o,
output Out4_o,
output Out5_o,
output Out6_o,
output Out7_o,
output Out8_o,
output Out9_o,
input CfgMode_i,
input CfgClk_i,
input CfgShift_i,
input CfgDataIn_i,
output CfgDataOut_o
);
wire [9:0] Input_s;
wire [9:0] Output_s;
wire ScanEnable_s;
wire ScanClk_s;
wire ScanDataIn_s;
wire ScanDataOut_s;
TRFSM #(
.InputWidth(10),
.OutputWidth(10),
.StateWidth(5),
.UseResetRow(0),
.NumRows0(5),
.NumRows1(10),
.NumRows2(10),
.NumRows3(5),
.NumRows4(5),
.NumRows5(0),
.NumRows6(0),
.NumRows7(0),
.NumRows8(0),
.NumRows9(0)
) TRFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Input_i(Input_s),
.Output_o(Output_s),
.CfgMode_i(CfgMode_i),
.CfgClk_i(CfgClk_i),
.CfgShift_i(CfgShift_i),
.CfgDataIn_i(CfgDataIn_i),
.CfgDataOut_o(CfgDataOut_o),
.ScanEnable_i(ScanEnable_s),
.ScanClk_i(ScanClk_s),
.ScanDataIn_i(ScanDataIn_s),
.ScanDataOut_o(ScanDataOut_s)
);
assign Input_s = { In9_i, In8_i, In7_i, In6_i, In5_i, In4_i, In3_i, In2_i, In1_i, In0_i };
assign Out0_o = Output_s[0];
assign Out1_o = Output_s[1];
assign Out2_o = Output_s[2];
assign Out3_o = Output_s[3];
assign Out4_o = Output_s[4];
assign Out5_o = Output_s[5];
assign Out6_o = Output_s[6];
assign Out7_o = Output_s[7];
assign Out8_o = Output_s[8];
assign Out9_o = Output_s[9];
assign ScanEnable_s = 1'b0;
assign ScanClk_s = 1'b0;
assign ScanDataIn_s = 1'b0;
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:64000000 ) using namespace std; inline unsigned long long gcd(unsigned long long a, unsigned long long b) { if (a < b) { a ^= b; b ^= a; a ^= b; }; return (a > b) ? gcd(a - b, b) : a; } inline int abs(int x) { return x > 0 ? x : -x; } void solve() { const string s[33] = { 111111101010101111100101001111111 , 100000100000000001010110001000001 , 101110100110110000011010001011101 , 101110101011001001111101001011101 , 101110101100011000111100101011101 , 100000101010101011010000101000001 , 111111101010101010101010101111111 , 000000001111101111100111100000000 , 100010111100100001011110111111001 , 110111001111111100100001000101100 , 011100111010000101000111010001010 , 011110000110001111110101100000011 , 111111111111111000111001001011000 , 111000010111010011010011010100100 , 101010100010110010110101010000010 , 101100000101010001111101000000000 , 000010100011001101000111101011010 , 101001001111101111000101010001110 , 101101111111000100100001110001000 , 000010011000100110000011010000010 , 001101101001101110010010011011000 , 011101011010001000111101010100110 , 111010100110011101001101000001110 , 110001010010101111000101111111000 , 001000111011100001010110111110000 , 000000001110010110100010100010110 , 111111101000101111000110101011010 , 100000100111010101111100100011011 , 101110101001010000101000111111000 , 101110100011010010010111111011010 , 101110100100011011110110101110000 , 100000100110011001111100111100000 , 111111101101000101001101110010001 }; int a, b; cin >> a >> b; cout << s[a][b]; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); solve(); return 0; } |
/*
* cpu.v
* The Brainfuck Processor
*
* Copyright (C) 2013 James Cowgill
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns / 1ps
module cpu(clk, data_in, data_available, data_out, data_out_en, data_read);
// Width of instruction addresses (affects size of ROM)
parameter IADDR_WIDTH = 8;
// Width of data addresses (affects size of RAM area)
parameter DADDR_WIDTH = 15;
// Width of stack addresses (affects size of loop stack)
parameter SADDR_WIDTH = 5;
// Width of data entries
parameter DATA_WIDTH = 8;
// True to initialize RAM for simulations
parameter INIT_RAM = 0;
// Inputs and outputs
output reg [DATA_WIDTH - 1:0] data_out; // Output data bus
output reg data_out_en; // If high, output was written on last cycle
output reg data_read; // If high, input was read on last cycle
input clk; // Clock
input [DATA_WIDTH - 1:0] data_in; // Input data bus
input data_available; // Data available on the input bus
// Internal Registers
reg [IADDR_WIDTH - 1:0] pc; // Program counter
reg [DADDR_WIDTH - 1:0] dp; // Data pointer
reg [SADDR_WIDTH - 1:0] lsc; // Loop skip counter
/*
* The loop skip counter is used for skipping entire loops
* when *DP == 0 when entering them. During normal operation
* the counter equals 0. When entering a loop which should be
* skipped, the counter is set to 1 and is used to detect nested
* loops and when the program should resume.
* When loop_skip_count != 0, normal instructions are not executed.
*/
// Internal Signals (wires driven by block memories)
wire [3:0] ci; // Current instruction
wire [DATA_WIDTH - 1:0] data_from_ram; // Data at dp from RAM
reg [DATA_WIDTH - 1:0] data_to_ram; // Data to write into RAM at dp
reg ram_write; // Write enable on RAM
wire [IADDR_WIDTH - 1:0] stack_top; // Address on top of the loop stack
reg [IADDR_WIDTH - 1:0] stack_data; // Data to push onto the stack
reg stack_push; // High to push onto the stack
reg stack_pop; // High to pop off the stack
reg [IADDR_WIDTH - 1:0] next_pc; // Next value of the program counter
reg [DADDR_WIDTH - 1:0] next_dp; // Next value of the data pointer
reg [SADDR_WIDTH - 1:0] next_lsc; // Next value of the loop skip counter
// Block memory instances
instruction_rom #(.ADDR_WIDTH(IADDR_WIDTH)) rom (
.address(pc),
.data_out(ci)
);
data_ram #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(DADDR_WIDTH), .INIT_RAM(INIT_RAM)) ram (
.data_out(data_from_ram),
.clk(clk),
.address(next_dp),
.data_in(data_to_ram),
.write(ram_write)
);
stack #(.DATA_WIDTH(IADDR_WIDTH), .ADDR_WIDTH(SADDR_WIDTH)) loop_stack (
.top(stack_top),
.clk(clk),
.pushd(stack_data),
.push_en(stack_push),
.pop_en(stack_pop)
);
// Register initialization
initial
begin
pc = 0;
dp = 0;
lsc = 0;
end
// Combinational part
always @(*)
begin
// Default signal states
data_out = 32'bX;
data_out_en = 0;
data_read = 0;
data_to_ram = 32'bX;
ram_write = 0;
stack_data = 32'bX;
stack_push = 0;
stack_pop = 0;
next_dp = dp;
next_pc = pc + 1'b1;
next_lsc = lsc;
// Different handling depending on lsc
if (lsc == 0)
begin
// Handle each opcode
case (ci)
4'h0:
begin
// Halt - set pc to itself so we just loop on this instruction
next_pc = pc;
end
4'h8:
begin
// Increment DP
next_dp = dp + 1'b1;
end
4'h9:
begin
// Decrement DP
next_dp = dp - 1'b1;
end
4'hA:
begin
// Increment *DP
data_to_ram = data_from_ram + 1'b1;
ram_write = 1;
end
4'hB:
begin
// Decrement *DP
data_to_ram = data_from_ram - 1'b1;
ram_write = 1;
end
4'hC:
begin
// Start loop - either skip entire loop or push into it
if (data_from_ram == 0)
begin
// Skip entire loop
next_lsc = 1;
end
else
begin
// Start loop - push PC + 1 onto the stack
stack_data = next_pc;
stack_push = 1;
end
end
4'hD:
begin
// End of loop - either exit the loop or loop around
if (data_from_ram == 0)
stack_pop = 1;
else
next_pc = stack_top;
end
4'hE:
begin
// Output 1 byte
data_out = data_from_ram;
data_out_en = 1;
end
4'hF:
begin
// Input 1 byte
if (data_available)
begin
// Read this byte into memory and signal that it was read
data_to_ram = data_in;
ram_write = 1;
data_read = 1;
end
else
begin
// Busy wait here until we can read (this is like the halt instruction)
next_pc = pc;
end
end
// Default - no op
endcase
end
else
begin
// Special loop skip counter handling
case (ci)
4'hC:
begin
// Increment lsc
next_lsc = lsc + 1'b1;
end
4'hD:
begin
// Decrement lsc
next_lsc = lsc - 1'b1;
end
endcase
end
end
// Synchronous (register update) part
always @(posedge clk)
begin
// Update registers
pc <= next_pc;
dp <= next_dp;
lsc <= next_lsc;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long INF = 1e18; const int inf = 1e9; int main() { long long n, m, grt = 0, eq = 0, less = 0, i; cin >> n >> m; for (i = 0; i < n; i++) { long long temp; cin >> temp; if (temp == m) eq++; else if (temp < m) less++; else grt++; } long long ans = 0, tot; if (eq == 0) { eq++; ans++; } tot = less + eq + grt; long long temp = (tot + 1) / 2; if (less + eq < temp) { ans += grt - less - eq; less += grt - less - eq; } else if (tot - (grt + eq) > temp) { ans += less - eq - grt; grt += less - eq - grt; } tot = less + eq + grt; temp = (tot + 1) / 2; if (less == temp) ans++; if (grt == tot - temp + 1) ans++; cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int n, a[101]; void scan() { scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); sort(a, a + n); } void out() { int ans = 0, k = 0, c; while (1) { c = 0; for (int i = 0; i < n; i++) { if (a[i] != -1) { if (a[i] >= k) { ++k; a[i] = -1; } } else if (a[i] == -1) ++c; } if (c == n) break; ++ans; k = 0; } cout << ans << n ; } int main() { scan(); out(); return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 2; const int M = 1e9 + 7; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int n; cin >> n; vector<int> v(n); for (int i = 0; i < n; i++) cin >> v[i]; vector<int> pre(n, 1); for (int i = 1; i < n; i++) { if (v[i] <= v[i - 1] * 2) pre[i] = pre[i - 1] + 1; } cout << *max_element(pre.begin(), pre.end()); return 0; } |
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_AsyncResetReg (
input d,
output reg q,
input en,
input clk,
input rst);
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else if (en) begin
q <= d;
end
end
endmodule // AsyncResetReg
|
#include <bits/stdc++.h> #pragma comment(linker, /stack:200000000 ) #pragma GCC optimize( Ofast,no-stack-protector ) #pragma GCC target( sse,sse2,sse3,ssse3,sse4,popcnt,abm,mmx,avx,tune=native ) #pragma GCC optimize( unroll-loops ) const int MAX = 2e3 + 10; const int MOD = 1e9 + 7; using namespace std; int n, m; char s[MAX][MAX]; int vis[30], x[30], y[30]; int sum1[MAX][MAX], sum2[MAX][MAX]; bool f(int a, int b) { if (a < 1 || b < 1 || a > n || b > m) return false; return true; } int main() { ios::sync_with_stdio(false), cout.tie(NULL); cin >> n >> m; for (int i = 1; i <= n; i++) cin >> (s[i] + 1); for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) { sum1[i][j] = sum1[i - 1][j]; sum2[i][j] = sum2[i][j - 1]; if (s[i][j] == # ) { sum1[i][j]++; sum2[i][j]++; } else if (s[i][j] != . ) { vis[s[i][j] - A ] = 1; x[s[i][j] - A ] = i; y[s[i][j] - A ] = j; } } } int k; cin >> k; while (k--) { char dir[2]; int len; cin >> dir >> len; if (dir[0] == N ) { for (int i = 0; i < 27; i++) { if (vis[i]) { int xx = x[i] - len; if (!f(xx, y[i]) || sum1[x[i]][y[i]] != sum1[xx - 1][y[i]]) vis[i] = 0; x[i] = xx; } } } else if (dir[0] == S ) { for (int i = 0; i < 27; i++) { if (vis[i]) { int xx = x[i] + len; if (!f(xx, y[i]) || sum1[x[i]][y[i]] != sum1[xx][y[i]]) vis[i] = 0; x[i] = xx; } } } else if (dir[0] == W ) { for (int i = 0; i < 27; i++) { if (vis[i]) { int yy = y[i] - len; if (!f(x[i], yy) || sum2[x[i]][y[i]] != sum2[x[i]][yy - 1]) vis[i] = 0; y[i] = yy; } } } else { for (int i = 0; i < 27; i++) { if (vis[i]) { int yy = y[i] + len; if (!f(x[i], yy) || sum2[x[i]][y[i]] != sum2[x[i]][yy]) { vis[i] = 0; } y[i] = yy; } } } } int fg = 0; for (int i = 0; i < 27; i++) { if (vis[i]) { fg = 1; cout << char(i + A ); } } if (!fg) cout << no solution ; cout << endl; } |
#include <bits/stdc++.h> using namespace std; const long long INF = (1e9) + 7; const long long C = (1 << (17)); vector<vector<long long> > up, sum; vector<long long> cost, maxw, d; long long LOG = 20; void push(long long v, long long x) { cost.push_back(x); maxw.push_back(x); d.push_back(0); for (int i = 0; i < LOG; ++i) { sum[i].push_back(x); up[i].push_back(v); } } void init() { up.resize(20); sum.resize(20); push(0, 0); } void add(long long pr, long long w) { long long v = up[0].size(); if (maxw[pr] < w) { push(v, w); return; } for (int i = LOG - 1; i >= 0; --i) { if (cost[up[i][pr]] < w) pr = up[i][pr]; } if (cost[pr] < w) { pr = up[0][pr]; assert(cost[pr] >= w); } cost.push_back(w); maxw.push_back(maxw[pr]); d.push_back(d[pr] + 1); up[0].push_back(pr); sum[0].push_back(cost[pr]); for (int i = 1; i < LOG; ++i) { long long pp = up[i - 1][v]; up[i].push_back(up[i - 1][pp]); if (pp != up[i - 1][pp]) { sum[i].push_back(sum[i - 1][v] + sum[i - 1][pp]); } else { sum[i].push_back(sum[i - 1][v]); } } } long long req(long long v, long long first) { if (cost[v] > first) return 0; first -= cost[v]; long long ans = 1; for (int i = LOG - 1; i >= 0; --i) { if (sum[i][v] <= first) { ans += d[v] - d[up[i][v]]; first -= sum[i][v]; v = up[i][v]; } } return ans; } int source() { init(); long long Q; cin >> Q; long long last = 0; for (long long q1 = 0; q1 < Q; ++q1) { long long type, p, q; cin >> type >> p >> q; long long R = p ^ last; --R; long long W = q ^ last; if (type == 1) { add(R, W); } else { last = req(R, W); cout << last << n ; } } return 0; } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); source(); return 0; } |
#include <iostream> #include<bits/stdc++.h> #include<vector> #define fo(i,n) for(long long i=0;i<n;i++) #define ll long long int #define inf 999999999999999999 #define pb push_back #define fi first #define se second #define vi vector<ll> #define vii vector<vector<ll>> #define pi pair<ll,ll> #define mp make_pair #define MOD 1000000007 #define tr(c,it) for(auto it = (c).begin(); it != (c).end(); ++it) #define fio ios_base::sync_with_stdio(false);cin.tie(0); using namespace std; //cerr<< n << Time elapsed : << clock() * 1000.0 / CLOCKS_PER_SEC << ms n ; //freopen( explicit.in , r , stdin); //freopen( explicit.out , w , stdout); void SieveOfEratosthenes() { bool prime[10000001]; memset(prime, true, sizeof(prime)); for (ll p=2; p*p<=10000000; p++) { if (prime[p] == true) { // Update all multiples of p greater than or // equal to the square of it // numbers which are multiple of p and are // less than p^2 are already been marked. for (ll i=p*p; i<=10000000; i += p) { prime[i] = false; } } } } ll binpow(ll a, ll b) { ll res = 1; while (b > 0) { if (b & 1) res = (res * a); a = (a * a); b >>= 1; } return res; } ll gcd(ll a,ll b) { if(b%a==0) return a; return gcd(b%a,a); } ll power(ll x,ll y,ll p) { ll r = 1; x = x % p; while (y > 0) { if (y & 1) r = (r * x) % p; y = y >> 1; x = (x * x) % p; } return r; } ll modInverse(ll n, ll p) { return power(n, p - 2, p); } ll nCrModP(ll n,ll r, ll p) { ll fac[100005]; if (r == 0) return 1; return (fac[n] * modInverse(fac[r], p) % p * modInverse(fac[n - r], p) % p) % p; } int32_t main() { fio ll j,i,n,t,l,s,r,c,h,k,m,maxi,d,a,b,x; cin>>t; string w; for(i=0;i<t;i++) { cin>>a>>b>>c; s=0; for(j=0;j<c;j++) { s=s*10+1; } l=s; while(true) { x=s; d=0; while(x!=0) { x=x/10; d++; } if(d==a) break; s=s*2; } m=s; s=l; while(true) { x=s; d=0; while(x!=0) { x=x/10; d++; } if(d==b) break; s=s*3; } cout<<m<< <<s<<endl; // cout<<__gcd(m,s)<<endl; } } |
#include <bits/stdc++.h> template <typename Arg1> void ZZ(const char* name, Arg1&& arg1) { std::cout << name << = << arg1 << std::endl; } template <typename Arg1, typename... Args> void ZZ(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); std::cout.write(names, comma - names) << = << arg1; ZZ(comma, args...); } using namespace std; long long int to_ll(string& s) { long long int i, ret = 0, p = 1; for (i = (long long int)s.length() - 1; i >= 0; i--) ret += (s[i] - 0 ) * p, p *= 10LL; return ret; } long long int gcd(long long int x, long long int y) { if (y == 0) return x; return gcd(y, x % y); } long long int pwr(long long int base, long long int expo, long long int m) { if (base == 0) return 0LL; if (expo == 0) return (1LL % m); if ((expo & 1) == 0) { long long int temp = pwr(base, expo >> 1, m); return (temp * temp) % m; } return ((base % m) * pwr(base, expo - 1, m)) % 1000000007; } vector<long long int> adj[200009]; long long int dp_down[200009][5], dp_up[200009][5], sz_down[200009][5], sz_up[200009][5], p[200009], dp[200009][5], dp_sz[200009][5]; bool v_dp_down[200009][5], v_dp_up[200009][5], v_sz_down[200009][5], v_sz_up[200009][5]; long long int n, k; void dfs(long long int node, long long int parent) { long long int i; p[node] = parent; for (i = 0; i < adj[node].size(); i++) { long long int nxt = adj[node][i]; if (nxt == parent) continue; dfs(nxt, node); } } void dfs_sz_down(long long int node, long long int parent, long long int m) { long long int i; if (v_sz_down[node][m] == 1) return; v_sz_down[node][m] = 1; for (i = 0; i < adj[node].size(); i++) { long long int nxt = adj[node][i]; long long int nxt_m = ((m - 1) % k + k) % k; if (nxt == parent) continue; dfs_sz_down(nxt, node, nxt_m); sz_down[node][m] += sz_down[nxt][nxt_m]; dp_sz[node][nxt_m] += sz_down[nxt][nxt_m]; } if (m == 0) sz_down[node][m]++; } void dfs_sz_up(long long int node, long long int parent, long long int m) { if (v_sz_up[node][m] == 1) return; v_sz_up[node][m] = 1; if (m == 0) sz_up[node][m]++; if (parent == -1) return; long long int nxt_m = ((m - 1) % k + k) % k, i; dfs_sz_up(parent, p[parent], nxt_m); sz_up[node][m] += sz_up[parent][nxt_m]; sz_up[node][m] += dp_sz[parent][((m - 2) % k + k) % k]; sz_up[node][m] -= sz_down[node][((m - 2) % k + k) % k]; } void dfs_up(long long int node, long long int parent, long long int m) { if (v_dp_up[node][m] == 1) return; v_dp_up[node][m] = 1; if (parent == -1) return; long long int nxt_m = ((m - 1) % k + k) % k, i; dfs_up(parent, p[parent], nxt_m); dp_up[node][m] += sz_up[parent][nxt_m] + dp_up[parent][nxt_m]; dp_up[node][m] += dp[parent][((m - 2) % k + k) % k]; dp_up[node][m] -= (2 * sz_down[node][((m - 2) % k + k) % k] + dp_down[node][((m - 2) % k + k) % k]); } void dfs_down(long long int node, long long int parent, long long int m) { if (v_dp_down[node][m] == 1) return; v_dp_down[node][m] = 1; long long int i; for (i = 0; i < adj[node].size(); i++) { long long int nxt = adj[node][i]; long long int nxt_m = ((m - 1) % k + k) % k; if (nxt == parent) continue; dfs_down(nxt, node, nxt_m); dp_down[node][m] += sz_down[nxt][nxt_m] + dp_down[nxt][nxt_m]; dp[node][nxt_m] += (2 * sz_down[nxt][nxt_m] + dp_down[nxt][nxt_m]); } } int main() { ios::sync_with_stdio(false); cin.tie(0); cout.tie(0); ; long long int i, j, x, y, ans = 0; cin >> n >> k; for (i = 0; i < n - 1; i++) { cin >> x >> y; adj[x].push_back(y); adj[y].push_back(x); } dfs(1, -1); for (i = 1; i <= n; i++) for (j = 0; j < k; j++) dfs_sz_down(i, p[i], j); for (i = 1; i <= n; i++) for (j = 0; j < k; j++) dfs_sz_up(i, p[i], j); for (i = 1; i <= n; i++) for (j = 0; j < k; j++) dfs_down(i, p[i], j); for (i = 1; i <= n; i++) for (j = 0; j < k; j++) dfs_up(i, p[i], j); for (j = 0; j < k; j++) { for (i = 1; i <= n; i++) { long long int total = dp_up[i][j] + dp_down[i][j]; long long int total_sz = sz_down[i][j] + sz_up[i][j]; if (j == 0) total_sz--; long long int val = ((total - total_sz * j) / k); if (j != 0) val += total_sz; ans += val; } } cout << ans / 2 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = int64_t; using u64 = uint64_t; using u32 = uint32_t; struct Node { int idx; Node *left = nullptr, *right = nullptr; }; int depth(Node* v) { if (!v) return 0; return max(depth(v->left), depth(v->right)) + 1; } int main() { ios::sync_with_stdio(false); cin.tie(nullptr); int n; cin >> n; vector<int> a(n); for (auto& ai : a) cin >> ai; auto it = min_element(begin(a), end(a)); int orig_shift = (n - (it - begin(a))) % n; rotate(begin(a), it, end(a)); int left = 0, right = n; vector<int> b(n); vector<Node> nodes(n); for (int i = 0; i < n; ++i) nodes[i].idx = i; vector<Node*> stack; int mind = n; while (right - left > 1) { for (auto& node : nodes) node.left = node.right = nullptr; stack.clear(); int mid = (left + right) / 2; int start = (n - mid) % n; for (int i = start; i < n + start; ++i) { Node* left = nullptr; while (!stack.empty() && a[stack.back()->idx] > a[i % n]) { left = stack.back(); stack.pop_back(); } if (!stack.empty()) stack.back()->right = &nodes[i % n]; if (right) nodes[i % n].left = left; stack.push_back(&nodes[i % n]); } Node* root = stack.front(); auto ldepth = depth(root->left); auto rdepth = depth(root->right); mind = min(mind, max(ldepth, rdepth) + 1); if (ldepth == rdepth) { cout << (ldepth + 1) << << ((n - mid - orig_shift + n) % n) << n ; return 0; } else if (ldepth > rdepth) { right = mid; } else { left = mid; } } cout << mind << << ((n - left - orig_shift + n) % n) << n ; return 0; } |
#include <bits/stdc++.h> const int MAXN = 200000 + 10; const int INF = 0x7fffffff; using namespace std; struct EDGE { int u, v, w; bool operator<(const EDGE &b) const { return w > b.w; } }; int fa[MAXN + MAXN]; int n, m, vis[MAXN]; int Min[MAXN]; vector<EDGE> edge; int Find(int x) { return fa[x] < 0 ? x : fa[x] = Find(fa[x]); } int main() { edge.clear(); scanf( %d%d , &n, &m); memset(fa, -1, sizeof(fa)); memset(vis, 0, sizeof(vis)); for (int i = 1; i <= m; i++) { int a, b, w; scanf( %d%d%d , &a, &b, &w); edge.push_back((EDGE){a, b, w}); } sort(edge.begin(), edge.end()); long long Ans = 0ll; for (int i = 0; i < m; i++) { int u = edge[i].u, v = edge[i].v; u = Find(u); v = Find(v); if (u == v) { if (fa[u] == -2) continue; fa[u] = -2; Ans += (long long)edge[i].w; continue; } if (fa[u] == -2 && fa[v] == -2) continue; fa[v] = min(fa[v], fa[u]); Ans += (long long)edge[i].w; fa[u] = v; } printf( %lld n , Ans); return 0; } |
#include <bits/stdc++.h> using namespace std; const int Nmax = 100000 + 10; int n; int nr[Nmax]; char s[Nmax], ans[Nmax]; bool ok(int L, int R) { int i, sum; if (L > R) return 0; for (i = 1; i <= n; ++i) nr[i] = s[i] - 0 ; if (L == 1 && nr[R] == 0) return 0; if (L == 2 && nr[1] != 1) return 0; for (nr[L] += nr[L - 1] * 10; true; L++, R--) { if (L == R) { ans[L] = nr[L] / 2 + 0 ; return nr[L] % 2 == 0; } if (L + 1 == R) { sum = nr[L]; if (nr[L] == nr[R] + 11) sum--; ans[L] = ans[R] = sum / 2 + 0 ; if (sum & 1) ans[L]++; return (nr[L] == nr[R] || nr[L] == nr[R] + 11); } if (nr[L] - nr[R] != 0 && nr[L] - nr[R] != 1 && nr[L] - nr[R] != 10 && nr[L] - nr[R] != 11) return 0; sum = nr[L]; if (nr[L] == nr[R]) ; if (nr[L] == nr[R] + 1 || nr[L] == nr[R] + 11) sum--, nr[L + 1] += 10; if (nr[L] == nr[R] + 10 || nr[L] == nr[R] + 11) { if (nr[R] == 9) return 0; for (i = R - 1; i >= L && nr[i] == 0; --i) nr[i] = 9; if (i == L) return 0; nr[i]--; } ans[L] = ans[R] = sum / 2 + 0 ; if (sum & 1) ans[L]++; int mata = 5; } return 1; } int main() { gets(s + 1); n = strlen(s + 1); if (ok(1, n)) puts(ans + 1); else if (ok(2, n)) puts(ans + 2); else puts( 0 ); return 0; } |
`timescale 1ns / 1ps
/*
* File : IDEX_Stage.v
* Project : University of Utah, XUM Project MIPS32 core
* Creator(s) : Grant Ayers ()
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 9-Jun-2011 GEA Initial design.
* 2.0 26-Jul-2012 GEA Many updates have been made.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* The Pipeline Register to bridge the Instruction Decode
* and Execute stages.
*/
module IDEX_Stage(
input clock,
input reset,
input ID_Flush,
input ID_Stall,
input EX_Stall,
// Control Signals
input ID_Link,
input ID_RegDst,
input ID_ALUSrcImm,
input [4:0] ID_ALUOp,
input ID_Movn,
input ID_Movz,
input ID_LLSC,
input ID_MemRead,
input ID_MemWrite,
input ID_MemByte,
input ID_MemHalf,
input ID_MemSignExtend,
input ID_Left,
input ID_Right,
input ID_RegWrite,
input ID_MemtoReg,
input ID_ReverseEndian,
// Hazard & Forwarding
input [4:0] ID_Rs,
input [4:0] ID_Rt,
input ID_WantRsByEX,
input ID_NeedRsByEX,
input ID_WantRtByEX,
input ID_NeedRtByEX,
// Exception Control/Info
input ID_KernelMode,
input [31:0] ID_RestartPC,
input ID_IsBDS,
input ID_Trap,
input ID_TrapCond,
input ID_EX_CanErr,
input ID_M_CanErr,
// Data Signals
input [31:0] ID_ReadData1,
input [31:0] ID_ReadData2,
input [16:0] ID_SignExtImm, // ID_Rd, ID_Shamt included here
// ----------------
output [4:0] EX_Rd,
output [4:0] EX_Shamt,
output [1:0] EX_LinkRegDst,
output [31:0] EX_SignExtImm,
// Voter Signals for Registers
input [16:0] EX_SignExtImm_pre,
input EX_RegDst,
input EX_Link,
input EX_ALUSrcImm,
input [4:0] EX_ALUOp,
input EX_Movn,
input EX_Movz,
input EX_LLSC,
input EX_MemRead,
input EX_MemWrite,
input EX_MemByte,
input EX_MemHalf,
input EX_MemSignExtend,
input EX_Left,
input EX_Right,
input EX_RegWrite,
input EX_MemtoReg,
input EX_ReverseEndian,
input [4:0] EX_Rs,
input [4:0] EX_Rt,
input EX_WantRsByEX,
input EX_NeedRsByEX,
input EX_WantRtByEX,
input EX_NeedRtByEX,
input EX_KernelMode,
input [31:0] EX_RestartPC,
input EX_IsBDS,
input EX_Trap,
input EX_TrapCond,
input EX_EX_CanErr,
input EX_M_CanErr,
input [31:0] EX_ReadData1,
input [31:0] EX_ReadData2,
output reg [16:0] vote_EX_SignExtImm_pre,
output reg vote_EX_RegDst,
output reg vote_EX_Link,
output reg vote_EX_ALUSrcImm,
output reg [4:0] vote_EX_ALUOp,
output reg vote_EX_Movn,
output reg vote_EX_Movz,
output reg vote_EX_LLSC,
output reg vote_EX_MemRead,
output reg vote_EX_MemWrite,
output reg vote_EX_MemByte,
output reg vote_EX_MemHalf,
output reg vote_EX_MemSignExtend,
output reg vote_EX_Left,
output reg vote_EX_Right,
output reg vote_EX_RegWrite,
output reg vote_EX_MemtoReg,
output reg vote_EX_ReverseEndian,
output reg [4:0] vote_EX_Rs,
output reg [4:0] vote_EX_Rt,
output reg vote_EX_WantRsByEX,
output reg vote_EX_NeedRsByEX,
output reg vote_EX_WantRtByEX,
output reg vote_EX_NeedRtByEX,
output reg vote_EX_KernelMode,
output reg [31:0] vote_EX_RestartPC,
output reg vote_EX_IsBDS,
output reg vote_EX_Trap,
output reg vote_EX_TrapCond,
output reg vote_EX_EX_CanErr,
output reg vote_EX_M_CanErr,
output reg [31:0] vote_EX_ReadData1,
output reg [31:0] vote_EX_ReadData2
);
/***
The purpose of a pipeline register is to capture data from one pipeline stage
and provide it to the next pipeline stage. This creates at least one clock cycle
of delay, but reduces the combinatorial path length of signals which allows for
higher clock speeds.
All pipeline registers update unless the forward stage is stalled. When this occurs
or when the current stage is being flushed, the forward stage will receive data that
is effectively a NOP and causes nothing to happen throughout the remaining pipeline
traversal. In other words:
A stall masks all control signals to forward stages. A flush permanently clears
control signals to forward stages (but not certain data for exception purposes).
***/
assign EX_LinkRegDst = (EX_Link) ? 2'b10 : ((EX_RegDst) ? 2'b01 : 2'b00);
assign EX_Rd = EX_SignExtImm[15:11];
assign EX_Shamt = EX_SignExtImm[10:6];
assign EX_SignExtImm = (EX_SignExtImm_pre[16]) ? {15'h7fff, EX_SignExtImm_pre[16:0]} : {15'h0000, EX_SignExtImm_pre[16:0]};
always @(posedge clock) begin
vote_EX_Link <= (reset) ? 1'b0 : ((EX_Stall) ? EX_Link : ID_Link);
vote_EX_RegDst <= (reset) ? 1'b0 : ((EX_Stall) ? EX_RegDst : ID_RegDst);
vote_EX_ALUSrcImm <= (reset) ? 1'b0 : ((EX_Stall) ? EX_ALUSrcImm : ID_ALUSrcImm);
vote_EX_ALUOp <= (reset) ? 5'b0 : ((EX_Stall) ? EX_ALUOp : ((ID_Stall | ID_Flush) ? 5'b0 : ID_ALUOp));
vote_EX_Movn <= (reset) ? 1'b0 : ((EX_Stall) ? EX_Movn : ID_Movn);
vote_EX_Movz <= (reset) ? 1'b0 : ((EX_Stall) ? EX_Movz : ID_Movz);
vote_EX_LLSC <= (reset) ? 1'b0 : ((EX_Stall) ? EX_LLSC : ID_LLSC);
vote_EX_MemRead <= (reset) ? 1'b0 : ((EX_Stall) ? EX_MemRead : ((ID_Stall | ID_Flush) ? 1'b0 : ID_MemRead));
vote_EX_MemWrite <= (reset) ? 1'b0 : ((EX_Stall) ? EX_MemWrite : ((ID_Stall | ID_Flush) ? 1'b0 : ID_MemWrite));
vote_EX_MemByte <= (reset) ? 1'b0 : ((EX_Stall) ? EX_MemByte : ID_MemByte);
vote_EX_MemHalf <= (reset) ? 1'b0 : ((EX_Stall) ? EX_MemHalf : ID_MemHalf);
vote_EX_MemSignExtend <= (reset) ? 1'b0 : ((EX_Stall) ? EX_MemSignExtend : ID_MemSignExtend);
vote_EX_Left <= (reset) ? 1'b0 : ((EX_Stall) ? EX_Left : ID_Left);
vote_EX_Right <= (reset) ? 1'b0 : ((EX_Stall) ? EX_Right : ID_Right);
vote_EX_RegWrite <= (reset) ? 1'b0 : ((EX_Stall) ? EX_RegWrite : ((ID_Stall | ID_Flush) ? 1'b0 : ID_RegWrite));
vote_EX_MemtoReg <= (reset) ? 1'b0 : ((EX_Stall) ? EX_MemtoReg : ID_MemtoReg);
vote_EX_ReverseEndian <= (reset) ? 1'b0 : ((EX_Stall) ? EX_ReverseEndian : ID_ReverseEndian);
vote_EX_RestartPC <= (reset) ? 32'b0 : ((EX_Stall) ? EX_RestartPC : ID_RestartPC);
vote_EX_IsBDS <= (reset) ? 1'b0 : ((EX_Stall) ? EX_IsBDS : ID_IsBDS);
vote_EX_Trap <= (reset) ? 1'b0 : ((EX_Stall) ? EX_Trap : ((ID_Stall | ID_Flush) ? 1'b0 : ID_Trap));
vote_EX_TrapCond <= (reset) ? 1'b0 : ((EX_Stall) ? EX_TrapCond : ID_TrapCond);
vote_EX_EX_CanErr <= (reset) ? 1'b0 : ((EX_Stall) ? EX_EX_CanErr : ((ID_Stall | ID_Flush) ? 1'b0 : ID_EX_CanErr));
vote_EX_M_CanErr <= (reset) ? 1'b0 : ((EX_Stall) ? EX_M_CanErr : ((ID_Stall | ID_Flush) ? 1'b0 : ID_M_CanErr));
vote_EX_ReadData1 <= (reset) ? 32'b0 : ((EX_Stall) ? EX_ReadData1 : ID_ReadData1);
vote_EX_ReadData2 <= (reset) ? 32'b0 : ((EX_Stall) ? EX_ReadData2 : ID_ReadData2);
vote_EX_SignExtImm_pre <= (reset) ? 17'b0 : ((EX_Stall) ? EX_SignExtImm_pre : ID_SignExtImm);
vote_EX_Rs <= (reset) ? 5'b0 : ((EX_Stall) ? EX_Rs : ID_Rs);
vote_EX_Rt <= (reset) ? 5'b0 : ((EX_Stall) ? EX_Rt : ID_Rt);
vote_EX_WantRsByEX <= (reset) ? 1'b0 : ((EX_Stall) ? EX_WantRsByEX : ((ID_Stall | ID_Flush) ? 1'b0 : ID_WantRsByEX));
vote_EX_NeedRsByEX <= (reset) ? 1'b0 : ((EX_Stall) ? EX_NeedRsByEX : ((ID_Stall | ID_Flush) ? 1'b0 : ID_NeedRsByEX));
vote_EX_WantRtByEX <= (reset) ? 1'b0 : ((EX_Stall) ? EX_WantRtByEX : ((ID_Stall | ID_Flush) ? 1'b0 : ID_WantRtByEX));
vote_EX_NeedRtByEX <= (reset) ? 1'b0 : ((EX_Stall) ? EX_NeedRtByEX : ((ID_Stall | ID_Flush) ? 1'b0 : ID_NeedRtByEX));
vote_EX_KernelMode <= (reset) ? 1'b0 : ((EX_Stall) ? EX_KernelMode : ID_KernelMode);
end
endmodule
|
/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Transceiver and PHY wrapper
*/
module eth_xcvr_phy_wrapper #
(
parameter HAS_COMMON = 1,
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire xcvr_ctrl_clk,
input wire xcvr_ctrl_rst,
/*
* Common
*/
output wire xcvr_gtpowergood_out,
/*
* PLL out
*/
input wire xcvr_gtrefclk00_in,
output wire xcvr_qpll0lock_out,
output wire xcvr_qpll0outclk_out,
output wire xcvr_qpll0outrefclk_out,
/*
* PLL in
*/
input wire xcvr_qpll0lock_in,
output wire xcvr_qpll0reset_out,
input wire xcvr_qpll0clk_in,
input wire xcvr_qpll0refclk_in,
/*
* Serial data
*/
output wire xcvr_txp,
output wire xcvr_txn,
input wire xcvr_rxp,
input wire xcvr_rxn,
/*
* PHY connections
*/
output wire phy_tx_clk,
output wire phy_tx_rst,
input wire [DATA_WIDTH-1:0] phy_xgmii_txd,
input wire [CTRL_WIDTH-1:0] phy_xgmii_txc,
output wire phy_rx_clk,
output wire phy_rx_rst,
output wire [DATA_WIDTH-1:0] phy_xgmii_rxd,
output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc,
output wire phy_tx_bad_block,
output wire [6:0] phy_rx_error_count,
output wire phy_rx_bad_block,
output wire phy_rx_sequence_error,
output wire phy_rx_block_lock,
output wire phy_rx_high_ber,
input wire phy_tx_prbs31_enable,
input wire phy_rx_prbs31_enable
);
wire phy_rx_reset_req;
wire gt_reset_tx_datapath = 1'b0;
wire gt_reset_rx_datapath = phy_rx_reset_req;
wire gt_reset_tx_done;
wire gt_reset_rx_done;
wire [5:0] gt_txheader;
wire [63:0] gt_txdata;
wire gt_rxgearboxslip;
wire [5:0] gt_rxheader;
wire [1:0] gt_rxheadervalid;
wire [63:0] gt_rxdata;
wire [1:0] gt_rxdatavalid;
generate
if (HAS_COMMON) begin : xcvr
eth_xcvr_gt_full
eth_xcvr_gt_full_inst (
// Common
.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
.gtwiz_reset_all_in(xcvr_ctrl_rst),
.gtpowergood_out(xcvr_gtpowergood_out),
// PLL
.gtrefclk00_in(xcvr_gtrefclk00_in),
.qpll0lock_out(xcvr_qpll0lock_out),
.qpll0outclk_out(xcvr_qpll0outclk_out),
.qpll0outrefclk_out(xcvr_qpll0outrefclk_out),
// Serial data
.gthtxp_out(xcvr_txp),
.gthtxn_out(xcvr_txn),
.gthrxp_in(xcvr_rxp),
.gthrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(1'b0),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(phy_tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.txpmaresetdone_out(),
.txprgdivresetdone_out(),
.txpolarity_in(1'b1),
.gtwiz_userdata_tx_in(gt_txdata),
.txheader_in(gt_txheader),
.txsequence_in(7'b0),
// Receive
.gtwiz_userclk_rx_reset_in(1'b0),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(phy_rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.rxpmaresetdone_out(),
.rxprgdivresetdone_out(),
.rxpolarity_in(1'b0),
.rxgearboxslip_in(gt_rxgearboxslip),
.gtwiz_userdata_rx_out(gt_rxdata),
.rxdatavalid_out(gt_rxdatavalid),
.rxheader_out(gt_rxheader),
.rxheadervalid_out(gt_rxheadervalid),
.rxstartofseq_out()
);
end else begin : xcvr
eth_xcvr_gt_channel
eth_xcvr_gt_channel_inst (
// Common
.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
.gtwiz_reset_all_in(xcvr_ctrl_rst),
.gtpowergood_out(xcvr_gtpowergood_out),
// PLL
.gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in),
.gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out),
.qpll0clk_in(xcvr_qpll0clk_in),
.qpll0refclk_in(xcvr_qpll0refclk_in),
.qpll1clk_in(1'b0),
.qpll1refclk_in(1'b0),
// Serial data
.gthtxp_out(xcvr_txp),
.gthtxn_out(xcvr_txn),
.gthrxp_in(xcvr_rxp),
.gthrxn_in(xcvr_rxn),
// Transmit
.gtwiz_userclk_tx_reset_in(1'b0),
.gtwiz_userclk_tx_srcclk_out(),
.gtwiz_userclk_tx_usrclk_out(),
.gtwiz_userclk_tx_usrclk2_out(phy_tx_clk),
.gtwiz_userclk_tx_active_out(),
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
.txpmaresetdone_out(),
.txprgdivresetdone_out(),
.txpolarity_in(1'b1),
.gtwiz_userdata_tx_in(gt_txdata),
.txheader_in(gt_txheader),
.txsequence_in(7'b0),
// Receive
.gtwiz_userclk_rx_reset_in(1'b0),
.gtwiz_userclk_rx_srcclk_out(),
.gtwiz_userclk_rx_usrclk_out(),
.gtwiz_userclk_rx_usrclk2_out(phy_rx_clk),
.gtwiz_userclk_rx_active_out(),
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
.gtwiz_reset_rx_cdr_stable_out(),
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
.rxpmaresetdone_out(),
.rxprgdivresetdone_out(),
.rxpolarity_in(1'b0),
.rxgearboxslip_in(gt_rxgearboxslip),
.gtwiz_userdata_rx_out(gt_rxdata),
.rxdatavalid_out(gt_rxdatavalid),
.rxheader_out(gt_rxheader),
.rxheadervalid_out(gt_rxheadervalid),
.rxstartofseq_out()
);
end
endgenerate
sync_reset #(
.N(4)
)
tx_reset_sync_inst (
.clk(phy_tx_clk),
.rst(!gt_reset_tx_done),
.out(phy_tx_rst)
);
sync_reset #(
.N(4)
)
rx_reset_sync_inst (
.clk(phy_rx_clk),
.rst(!gt_reset_rx_done),
.out(phy_rx_rst)
);
eth_phy_10g #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(1),
.SCRAMBLER_DISABLE(0),
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
phy_inst (
.tx_clk(phy_tx_clk),
.tx_rst(phy_tx_rst),
.rx_clk(phy_rx_clk),
.rx_rst(phy_rx_rst),
.xgmii_txd(phy_xgmii_txd),
.xgmii_txc(phy_xgmii_txc),
.xgmii_rxd(phy_xgmii_rxd),
.xgmii_rxc(phy_xgmii_rxc),
.serdes_tx_data(gt_txdata),
.serdes_tx_hdr(gt_txheader),
.serdes_rx_data(gt_rxdata),
.serdes_rx_hdr(gt_rxheader),
.serdes_rx_bitslip(gt_rxgearboxslip),
.serdes_rx_reset_req(phy_rx_reset_req),
.tx_bad_block(phy_tx_bad_block),
.rx_error_count(phy_rx_error_count),
.rx_bad_block(phy_rx_bad_block),
.rx_sequence_error(phy_rx_sequence_error),
.rx_block_lock(phy_rx_block_lock),
.rx_high_ber(phy_rx_high_ber),
.tx_prbs31_enable(phy_tx_prbs31_enable),
.rx_prbs31_enable(phy_rx_prbs31_enable)
);
endmodule
`resetall
|
#include <bits/stdc++.h> using namespace std; long long int gcd(long long int a, long long int b) { if (b == 0) return a; else return gcd(b, a % b); } int main() { long long int n, x, ans, ans1, y; cin >> y; n = (long long int)sqrt((double)y); for (long long int i = n; i > 0; i--) { if (y % i == 0) { x = y / i; if (gcd(i, x) == 1) { ans = i; ans1 = x; break; } } } if (y != 1) cout << ans << << ans1 << endl; else cout << 1 << << 1 << endl; } |
// niosii_mm_interconnect_0_avalon_st_adapter_005.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii_mm_interconnect_0_avalon_st_adapter_005 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
niosii_mm_interconnect_0_avalon_st_adapter_005_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); int a, b, c, d; int n; cin >> a >> b >> c >> d >> n; vector<int> v(n); for (int i = 0; i < n; i++) { cin >> v[i]; } cout << YES n ; int row = max(b, d); int col = a + c; char ans[row][col]; for (int i = 0; i < row; i++) { for (int j = 0; j < col; j++) { ans[i][j] = . ; } } int x, y, yc; int dir; if (d % 2 == 1) { y = a + c - 1; yc = a; x = d - 1; dir = -1; } else { y = a; yc = a + c - 1; x = d - 1; dir = 1; } int ind = 0; for (int i = x; i >= 0; i--) { for (int j = y; j < a + c and j > a - 1; j += dir) { if (v[ind]) { ans[i][j] = a + ind; v[ind]--; } else { ind++; j -= dir; } } dir = (dir == 1) ? -1 : 1; swap(y, yc); } dir = -1; y = a - 1; yc = 0; for (int i = 0; i < b; i++) { for (int j = y; j < a and j >= 0; j += dir) { if (v[ind]) { ans[i][j] = a + ind; v[ind]--; } else { ind++; j -= dir; } } dir = (dir == 1) ? -1 : 1; swap(y, yc); } for (int i = 0; i < row; i++) { for (int j = 0; j < col; j++) { cout << ans[i][j]; } cout << endl; } } |
#include <bits/stdc++.h> using namespace std; template <typename Arg1> void __f(const char* name, Arg1&& arg1) { cerr << name << : << arg1 << n ; } template <typename Arg1, typename... Args> void __f(const char* names, Arg1&& arg1, Args&&... args) { const char* comma = strchr(names + 1, , ); cout.write(names, comma - names) << : << arg1 << | ; __f(comma + 1, args...); } long long pows(long long b, long long e) { if (e == 0) return 1; else if (e % 2 == 0) { long long a = pow(b, e / 2); return a * a; } else { long long a = pow(b, e / 2); return b * a * a; } } long long powm(long long x, long long y, long long m) { x = x % m; long long res = 1; while (y) { if (y & 1) res = res * x; res %= m; y = y >> 1; x = x * x; x %= m; } return res; } long long modInverse(long long a, long long m = 1000000007) { if (m == 1) return 0; long long m0 = m, y = 0, x = 1; while (a > 1) { long long q = a / m, t = m; m = a % m, a = t; t = y; y = x - q * y; x = t; } if (x < 0) x += m0; return x; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); long long n, m, i, j, k, x, y, z, e, f, p, q, g, l, r, w, h, count1 = 0, prod = 1, a, b, c, d, index, x1, x2, diff, ans = 0, sum = 0, sum1 = 0, sum2 = 0, flag = 0, flag1 = 0, flag2 = 0; string s, s1, s2; cin >> n; if (n == 1) { cout << 1 ; return 0; } else { ans = 1; k = 3; for (i = 2; i <= n; i++) { ans += k * 4; k += 3; } cout << ans; } } |
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 3, P = 998244353; int fc[N], ifc[N]; int qp(int a, int b) { int r = 1; for (; b; b >>= 1, a = a * 1ll * a % P) if (b & 1) r = r * 1ll * a % P; return r; } int main() { int n, m = 0, i, j, k, l, o, s = 0; scanf( %d%d%d , &n, &k, &o), l = o, fc[0] = 1; if (n == 1) return puts( 0 ), 0; for (i = 1; i < n; ++i) scanf( %d , &j), m += j != l, l = j; for (i = 1, m += j != o; i <= m; ++i) fc[i] = fc[i - 1] * 1ll * i % P; for (i = m, ifc[m] = qp(fc[m], P - 2); i; --i) ifc[i - 1] = ifc[i] * 1ll * i % P; for (i = m / 2, o = (k - 2) * 1ll * (k - 2) % P, l = qp(k - 2, m - i * 2); ~i; --i) s = (s + (fc[m] * 1ll * ifc[i] % P * ifc[(m) - (i)] % P) * (fc[m - i] * 1ll * ifc[i] % P * ifc[(m - i) - (i)] % P) % P * l) % P, l = l * 1ll * o % P; printf( %lld , ((qp(k, m) - s) * 1ll * qp(2, P - 2) % P * qp(k, n - m) % P + P) % P); return 0; } |
module dcache_top
(
// System clock, reset and stall
clk_i,
rst_i,
// to Data Memory interface
mem_data_i,
mem_ack_i,
mem_data_o,
mem_addr_o,
mem_enable_o,
mem_write_o,
// to CPU interface
p1_data_i,
p1_addr_i,
p1_MemRead_i,
p1_MemWrite_i,
p1_data_o,
p1_stall_o
);
//
// System clock, start
//
input clk_i;
input rst_i;
//
// to Data Memory interface
//
input [256-1:0] mem_data_i;
input mem_ack_i;
output [256-1:0] mem_data_o;
output [32-1:0] mem_addr_o;
output mem_enable_o;
output mem_write_o;
//
// to core interface
//
input [32-1:0] p1_data_i;
input [32-1:0] p1_addr_i;
input p1_MemRead_i;
input p1_MemWrite_i;
output [32-1:0] p1_data_o;
output p1_stall_o;
//
// to SRAM interface
//
wire [4:0] cache_sram_index;
wire cache_sram_enable;
wire [23:0] cache_sram_tag;
wire [255:0] cache_sram_data;
wire cache_sram_write;
wire [23:0] sram_cache_tag;
wire [255:0] sram_cache_data;
// cache
wire sram_valid;
wire sram_dirty;
// controller
parameter STATE_IDLE = 3'h0,
STATE_READMISS = 3'h1,
STATE_READMISSOK = 3'h2,
STATE_WRITEBACK = 3'h3,
STATE_MISS = 3'h4;
reg [2:0] state;
reg mem_enable;
reg mem_write;
reg cache_we;
wire cache_dirty;
reg write_back;
// regs & wires
wire [4:0] p1_offset;
wire [4:0] p1_index;
wire [21:0] p1_tag;
wire [255:0] r_hit_data;
wire [21:0] sram_tag;
wire hit;
reg [255:0] w_hit_data;
wire write_hit;
wire p1_req;
reg [31:0] p1_data;
// project1 interface
assign p1_req = p1_MemRead_i | p1_MemWrite_i;
assign p1_offset = p1_addr_i[4:0];
assign p1_index = p1_addr_i[9:5];
assign p1_tag = p1_addr_i[31:10];
assign p1_stall_o = ~hit & p1_req;
assign p1_data_o = p1_data;
// SRAM interface
assign sram_valid = sram_cache_tag[23];
assign sram_dirty = sram_cache_tag[22];
assign sram_tag = sram_cache_tag[21:0];
assign cache_sram_index = p1_index;
assign cache_sram_enable = p1_req;
assign cache_sram_write = cache_we | write_hit;
assign cache_sram_tag = {1'b1, cache_dirty, p1_tag};
assign cache_sram_data = (hit) ? w_hit_data : mem_data_i;
// memory interface
assign mem_enable_o = mem_enable;
assign mem_addr_o = (write_back) ? {sram_tag, p1_index, 5'b0} : {p1_tag, p1_index, 5'b0};
assign mem_data_o = sram_cache_data;
assign mem_write_o = mem_write;
assign write_hit = hit & p1_MemWrite_i;
assign cache_dirty = write_hit;
// tag comparator
//!!! add you code here! (hit=...?, r_hit_data=...?)
// read data : 256-bit to 32-bit
always@(p1_offset or r_hit_data) begin
//!!! add you code here! (p1_data=...?)
end
// write data : 32-bit to 256-bit
always@(p1_offset or r_hit_data or p1_data_i) begin
//!!! add you code here! (w_hit_data=...?)
end
// controller
always@(posedge clk_i or negedge rst_i) begin
if(~rst_i) begin
state <= STATE_IDLE;
mem_enable <= 1'b0;
mem_write <= 1'b0;
cache_we <= 1'b0;
write_back <= 1'b0;
end
else begin
case(state)
STATE_IDLE: begin
if(p1_req && !hit) begin //wait for request
state <= STATE_MISS;
end
else begin
state <= STATE_IDLE;
end
end
STATE_MISS: begin
if(sram_dirty) begin //write back if dirty
//!!! add you code here!
state <= STATE_WRITEBACK;
end
else begin //write allocate: write miss = read miss + write hit; read miss = read miss + read hit
//!!! add you code here!
state <= STATE_READMISS;
end
end
STATE_READMISS: begin
if(mem_ack_i) begin //wait for data memory acknowledge
//!!! add you code here!
state <= STATE_READMISSOK;
end
else begin
state <= STATE_READMISS;
end
end
STATE_READMISSOK: begin //wait for data memory acknowledge
//!!! add you code here!
state <= STATE_IDLE;
end
STATE_WRITEBACK: begin
if(mem_ack_i) begin //wait for data memory acknowledge
//!!! add you code here!
state <= STATE_READMISS;
end
else begin
state <= STATE_WRITEBACK;
end
end
endcase
end
end
//
// Tag SRAM 0
//
dcache_tag_sram dcache_tag_sram
(
.clk_i(clk_i),
.addr_i(cache_sram_index),
.data_i(cache_sram_tag),
.enable_i(cache_sram_enable),
.write_i(cache_sram_write),
.data_o(sram_cache_tag)
);
//
// Data SRAM 0
//
dcache_data_sram dcache_data_sram
(
.clk_i(clk_i),
.addr_i(cache_sram_index),
.data_i(cache_sram_data),
.enable_i(cache_sram_enable),
.write_i(cache_sram_write),
.data_o(sram_cache_data)
);
endmodule |
module prometheus_fx3_stream_out(
input rst_n,
input clk_100,
input stream_out_mode_selected,
input i_gpif_in_ch1_rdy_d,
input i_gpif_out_ch1_rdy_d,
input [31:0]stream_out_data_from_fx3,
output o_gpif_re_n_stream_out_,
output o_gpif_oe_n_stream_out_
);
reg [2:0]current_stream_out_state;
reg [2:0]next_stream_out_state;
//parameters for StreamOUT mode state machine
parameter [2:0] stream_out_idle = 3'd0;
parameter [2:0] stream_out_flagc_rcvd = 3'd1;
parameter [2:0] stream_out_wait_flagd = 3'd2;
parameter [2:0] stream_out_read = 3'd3;
parameter [2:0] stream_out_read_rd_and_oe_delay = 3'd4;
parameter [2:0] stream_out_read_oe_delay = 3'd5;
reg [1:0] oe_delay_cnt;
reg rd_oe_delay_cnt;
assign o_gpif_re_n_stream_out_ = ((current_stream_out_state == stream_out_read) | (current_stream_out_state == stream_out_read_rd_and_oe_delay)) ? 1'b0 : 1'b1;
assign o_gpif_oe_n_stream_out_ = ((current_stream_out_state == stream_out_read) | (current_stream_out_state == stream_out_read_rd_and_oe_delay) | (current_stream_out_state == stream_out_read_oe_delay)) ? 1'b0 : 1'b1;
//counter to delay the read and output enable signal
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
rd_oe_delay_cnt <= 1'b0;
end else if(current_stream_out_state == stream_out_read) begin
rd_oe_delay_cnt <= 1'b1;
end else if((current_stream_out_state == stream_out_read_rd_and_oe_delay) & (rd_oe_delay_cnt > 1'b0))begin
rd_oe_delay_cnt <= rd_oe_delay_cnt - 1'b1;
end else begin
rd_oe_delay_cnt <= rd_oe_delay_cnt;
end
end
//Counter to delay the OUTPUT Enable(oe) signal
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
oe_delay_cnt <= 2'd0;
end else if(current_stream_out_state == stream_out_read_rd_and_oe_delay) begin
oe_delay_cnt <= 2'd2;
end else if((current_stream_out_state == stream_out_read_oe_delay) & (oe_delay_cnt > 1'b0))begin
oe_delay_cnt <= oe_delay_cnt - 1'b1;
end else begin
oe_delay_cnt <= oe_delay_cnt;
end
end
//stream_out mode state machine
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
current_stream_out_state <= stream_out_idle;
end else begin
current_stream_out_state <= next_stream_out_state;
end
end
//steamOUT mode state machine combo
always @(*)begin
next_stream_out_state = current_stream_out_state;
case(current_stream_out_state)
stream_out_idle:begin
if((stream_out_mode_selected) & (i_gpif_in_ch1_rdy_d == 1'b1))begin
next_stream_out_state = stream_out_flagc_rcvd;
end else begin
next_stream_out_state = stream_out_idle;
end
end
stream_out_flagc_rcvd:begin
next_stream_out_state = stream_out_wait_flagd;
end
stream_out_wait_flagd:begin
if(i_gpif_out_ch1_rdy_d == 1'b1)begin
next_stream_out_state = stream_out_read;
end else begin
next_stream_out_state = stream_out_wait_flagd;
end
end
stream_out_read :begin
if(i_gpif_out_ch1_rdy_d == 1'b0)begin
next_stream_out_state = stream_out_read_rd_and_oe_delay;
end else begin
next_stream_out_state = stream_out_read;
end
end
stream_out_read_rd_and_oe_delay : begin
if(rd_oe_delay_cnt == 0)begin
next_stream_out_state = stream_out_read_oe_delay;
end else begin
next_stream_out_state = stream_out_read_rd_and_oe_delay;
end
end
stream_out_read_oe_delay : begin
if(oe_delay_cnt == 0)begin
next_stream_out_state = stream_out_idle;
end else begin
next_stream_out_state = stream_out_read_oe_delay;
end
end
endcase
end
endmodule
|
// Author: Adam Nunez,
// Copyright (C) 2015 Adam Nunez
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
`timescale 1ns/1ns
module KeyPadTestBench();
reg flag;
//Inputs to KeyPadInterpreter
reg Clock;
reg ResetButton;
reg KeyRead;
reg [3:0] RowDataIn;
//Outputs from KeyPadInterpreter
wire KeyReady;
wire [3:0] DataOut;
wire [3:0] ColDataOut;
wire [3:0] PressCount;
//Clock Setup
initial begin
Clock = 0;
end
always begin
#1 Clock = ~Clock;
end
//End Clock Setup
//Keypad Emulator,
// returns that "5" is pressed after flag goes high
always @(ColDataOut) begin
if(flag==1) begin
case(ColDataOut)
4'bzzz0: RowDataIn = 4'b1111;
4'bzz0z: RowDataIn = 4'b1111;
4'bz0zz: RowDataIn = 4'b1101;
4'b0zzz: RowDataIn = 4'b1111;
endcase
end
else begin
case(ColDataOut)
4'bzzz0: RowDataIn = 4'b1111;
4'bzz0z: RowDataIn = 4'b1111;
4'bz0zz: RowDataIn = 4'b1111;
4'b0zzz: RowDataIn = 4'b1111;
endcase
end
end
//End Keypad Emulator
//Actual Testing
initial begin
#0 flag = 0;
#0 ResetButton = 0;
#3 ResetButton = 1;
#10000000; //Wait a long time
flag = 1;
#10000000; //Wait a little more
if(DataOut == 4'b0110)
$display("CorrectKey");
else
$display("Wrong DataOut");
end
//End of Testing
//Module to be tested
KeyPadInterpreter test(Clock,ResetButton,KeyRead,RowDataIn,KeyReady,DataOut,ColDataOut,PressCount);
endmodule |
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