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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__NAND4BB_BEHAVIORAL_PP_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4BB_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long mod = 1000000007; long long fac[300011], inv[300011]; int F, W, H; long long fastpower(long long v, long long p) { long long ret = 1; while (p > 0) { if (p % 2 == 1) { ret = ret * v; ret %= mod; p--; } else { v = v * v; v %= mod; p /= 2; } } return ret; } void init() { fac[0] = inv[0] = 1; for (int i = 1; i < 300011; ++i) { fac[i] = fac[i - 1] * i; inv[i] = inv[i - 1] * fastpower(i, mod - 2); fac[i] %= mod; inv[i] %= mod; } } long long C(int n, int k) { if (n < k) return 0; return ((fac[n] * inv[k]) % mod * inv[n - k]) % mod; } long long add(long long v, long long u) { return (v + u) % mod; } long long cost(long long n, long long k, long long low) { n = n - k * low; if (n < 0) return 0; return C(n + k - 1, n); } long long calc(int num, int limit) { long long v1 = cost(F, num, 1) * cost(W, num, limit) * 2; long long v2 = cost(F, num, 1) * cost(W, num + 1, limit); long long v3 = cost(F, num, 1) * cost(W, num - 1, limit); return add(add(v1, v2), v3); } int main() { init(); scanf( %d%d%d , &F, &W, &H); H++; if (W == 0) { printf( 1 n ); return 0; } if (W < H) { printf( 0 n ); return 0; } if (W == 0) { printf( 1 n ); return 0; } if (F == 0) { printf( 1 n ); return 0; } long long ans = 0; for (int i = 1; i <= F; ++i) { ans += calc(i, H); ans %= mod; } ans = ans + mod; ans %= mod; ans = ans * fastpower(C(W + F, W), mod - 2); ans = ans % mod; printf( %I64d n , ans); return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O22A_1_V
`define SKY130_FD_SC_HS__O22A_1_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o22a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o22a_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o22a_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o22a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O22A_1_V
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_31x128.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1.30 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module sfifo_31x128 (
data,
wrreq,
rdreq,
clock,
aclr,
q,
full,
empty,
usedw,
almost_full);
input [30:0] data;
input wrreq;
input rdreq;
input clock;
input aclr;
output [30:0] q;
output full;
output empty;
output [6:0] usedw;
output almost_full;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "31"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "3"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "31"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "3"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: USED_PORT: data 0 0 31 0 INPUT NODEFVAL data[30..0]
// Retrieval info: USED_PORT: q 0 0 31 0 OUTPUT NODEFVAL q[30..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0]
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: CONNECT: @data 0 0 31 0 data 0 0 31 0
// Retrieval info: CONNECT: q 0 0 31 0 @q 0 0 31 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_31x128_wave*.jpg FALSE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXBP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__EDFXBP_FUNCTIONAL_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ls__edfxbp (
Q ,
Q_N,
CLK,
D ,
DE
);
// Module ports
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_ls__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXBP_FUNCTIONAL_V |
#include <bits/stdc++.h> int main() { int n, m; scanf( %d%d , &n, &m); int a[n], b[m], i, j; for (i = 0; i < n; i++) scanf( %d , &a[i]); for (i = 0; i < m; i++) scanf( %d , &b[i]); for (i = 0; i < n; i++) { for (j = 0; j < m; j++) { if (b[j] == a[i]) printf( %d , a[i]); } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 10; const int M = 1e3 + 10; const long long mod = 1e9 + 7; const long long inf = 1e18 + 10; int a[N], st[N], ft[N], ind[N], lzy[4 * N], t, n, m; vector<int> adj[N]; bitset<M> seg[4 * N], P, res, one; void dfs(int v, int p) { st[v] = t; ind[t++] = v - 1; for (int u : adj[v]) if (u != p) dfs(u, v); ft[v] = t; } void build(int l = 0, int r = n, int id = 1) { if (r - l == 1) { seg[id][a[ind[l]]] = 1; return; } int mid = (l + r) / 2; build(l, mid, 2 * id); build(mid, r, 2 * id + 1); seg[id] = seg[2 * id] | seg[2 * id + 1]; } void shift(int id) { int x = lzy[id]; seg[2 * id] = (seg[2 * id] << x) & one | (seg[2 * id] >> (m - x)); seg[2 * id + 1] = (seg[2 * id + 1] << x) & one | (seg[2 * id + 1] >> (m - x)); lzy[2 * id] = (lzy[2 * id] + x) % m; lzy[2 * id + 1] = (lzy[2 * id + 1] + x) % m; lzy[id] = 0; } void upd(int l, int r, int x, int s = 0, int e = n, int id = 1) { if (e <= l || r <= s) return; if (l <= s && e <= r) { seg[id] = (seg[id] << x) & one | (seg[id] >> (m - x)); lzy[id] = (lzy[id] + x) % m; return; } shift(id); int mid = (s + e) / 2; upd(l, r, x, s, mid, 2 * id); upd(l, r, x, mid, e, 2 * id + 1); seg[id] = seg[2 * id] | seg[2 * id + 1]; } void get(int l, int r, int s = 0, int e = n, int id = 1) { if (e <= l || r <= s) return; if (l <= s && e <= r) { res |= seg[id]; return; } shift(id); int mid = (s + e) / 2; get(l, r, s, mid, 2 * id); get(l, r, mid, e, 2 * id + 1); } int main() { ios::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n >> m; for (int i = 0; i < n; i++) cin >> a[i], a[i] %= m; for (int i = 1; i < n; i++) { int u, v; cin >> u >> v; adj[u].push_back(v); adj[v].push_back(u); } dfs(1, 0); build(); for (int i = 2; i < m; i++) P[i] = 1; for (int i = 2; i < m; i++) if (P[i]) for (int j = i * i; j < m; j += i) P[j] = 0; for (int i = 0; i < m; i++) one[i] = 1; int q; cin >> q; while (q--) { int typ; cin >> typ; if (typ == 1) { int v, x; cin >> v >> x; x %= m; upd(st[v], ft[v], x); } else { int v; cin >> v; res &= 0; get(st[v], ft[v]); cout << (res & P).count() << n ; } } return 0; } |
// part of NeoGS flash programmer project (c) 2014 lvd^NedoPC
//
// rom controller
//
// !!!!!!!!!!!enables addr bus as soon as reset is removed!!!!!!!
module rom
(
input wire clk,
input wire rst_n,
input wire wr_addr,
input wire wr_data,
input wire rd_data,
input wire [ 7:0] wr_buffer,
output reg [ 7:0] rd_buffer,
input wire autoinc_ena,
output wire [18:0] rom_a,
inout wire [ 7:0] rom_d,
output reg rom_cs_n,
output reg rom_oe_n,
output reg rom_we_n
);
reg [7:0] wrdata;
wire [7:0] rddata;
reg enadata;
reg [18:0] addr;
reg [18:0] next_addr;
reg enaaddr;
reg [2:0] addr_phase;
reg rnw;
reg [6:0] rw_phase;
// dbus control
assign rom_d = enadata ? wrdata : 8'bZZZZ_ZZZZ;
assign rddata = rom_d;
// abus control
assign rom_a = enaaddr ? addr : {19{1'bZ}};
// enaaddr control
always @(posedge clk, negedge rst_n)
if( !rst_n )
enaaddr <= 1'b0;
else
enaaddr <= 1'b1;
// address phase (points which one of 3byte address to write into)
always @(posedge clk, negedge rst_n)
if( !rst_n )
begin
addr_phase <= 3'b001;
end
else
case( {wr_addr, wr_data, rd_data} )
3'b100: addr_phase <= {addr_phase[1:0], addr_phase[2] };
3'b010,3'b001: addr_phase <= 3'b001;
default: addr_phase <= addr_phase;
endcase
// address control
always @(posedge clk, negedge rst_n)
if( !rst_n )
begin
next_addr <= 19'd0;
end
else
case( {wr_addr, wr_data, rd_data} )
3'b100: begin
next_addr[ 7:0 ] <= addr_phase[0] ? wr_buffer[7:0] : next_addr[ 7:0 ];
next_addr[15:8 ] <= addr_phase[1] ? wr_buffer[7:0] : next_addr[15:8 ];
next_addr[18:16] <= addr_phase[2] ? wr_buffer[2:0] : next_addr[18:16];
end
3'b010, 3'b001: if( autoinc_ena ) next_addr <= next_addr + 19'd1;
default: next_addr <= next_addr;
endcase
// address output register
always @(posedge clk)
if( wr_data || rd_data )
addr <= next_addr;
// read/write sequence
always @(posedge clk, negedge rst_n)
if( !rst_n )
begin
rw_phase <= 'd0;
rnw <= 1'b1;
end
else if( rd_data || wr_data )
begin
rw_phase <= 'd1;
rnw <= rd_data;
end
else
begin
rw_phase <= rw_phase<<1;
end
// output control
always @(posedge clk, negedge rst_n)
if( !rst_n )
begin
enadata <= 1'b0;
end
else if( rw_phase[0] )
begin
enadata <= !rnw;
end
else if( rw_phase[6] )
begin
enadata <= 1'b0;
end
//
always @(posedge clk, negedge rst_n)
if( !rst_n )
begin
rom_cs_n <= 1'b1;
rom_oe_n <= 1'b1;
rom_we_n <= 1'b1;
end
else if( rw_phase[1] )
begin
rom_cs_n <= 1'b0;
rom_oe_n <= !rnw;
rom_we_n <= rnw;
end
else if( rw_phase[6] )
begin
rom_cs_n <= 1'b1;
rom_oe_n <= 1'b1;
rom_we_n <= 1'b1;
end
//
always @(posedge clk)
if( wr_data )
wrdata <= wr_buffer;
// input control
always @(posedge clk)
if( rw_phase[6] && rnw )
rd_buffer <= rddata;
endmodule
|
#include <bits/stdc++.h> using namespace std; const int maxn = 300100; int read() { int x = 0, w = 1; char ch = 0; while (!isdigit(ch)) { ch = getchar(); if (ch == - ) w = -1; } while (isdigit(ch)) x = x * 10 + ch - 0 , ch = getchar(); return x * w; } vector<int> G[maxn]; int vis[maxn]; int fa[maxn], ans[maxn]; int findfa(int rt) { return rt == fa[rt] ? rt : fa[rt] = findfa(fa[rt]); } void merge(int a, int b) { if (findfa(a) != findfa(b)) fa[fa[a]] = fa[b]; } int tmp = 0, tmp2 = 0; void dfs(int rt, int col, int res) { if (vis[rt] == col) return; if (res > tmp) tmp = res, tmp2 = rt; vis[rt] = col; for (int to : G[rt]) merge(rt, to), dfs(to, col, res + 1); } int main() { int n = read(), m = read(), q = read(); for (int i = 1; i <= n; i++) fa[i] = i; while (m--) { int u = read(), v = read(); G[u].push_back(v); G[v].push_back(u); } for (int i = 1; i <= n; i++) if (!vis[i]) { tmp = 0, tmp2 = i; dfs(i, i, 0); tmp = 0; dfs(tmp2, tmp2, 0); ans[findfa(i)] = tmp; } while (q--) { int opt = read(); if (opt == 1) printf( %d n , ans[findfa(read())]); else { int u = read(), v = read(); u = findfa(u), v = findfa(v); if (u == v) continue; fa[u] = v; ans[v] = max(max(ans[v], ans[u]), (ans[u] + 1) / 2 + (ans[v] + 1) / 2 + 1); } } } |
// ddc_2.v - decimating downconverter V2 - runs at full 40MSPS
// 07-17-16 E. Brombaugh
module ddc_2 #(
parameter isz = 10,
fsz = 26,
osz = 16
)
(
input clk, reset,
input [isz-1:0] in,
input [fsz-1:0] frq,
input ns_ena,
output reg valid,
output reg signed [osz-1:0] i_out, q_out
);
//------------------------------
// clock divider
//------------------------------
reg [7:0] dcnt;
reg ena_cic;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
dcnt <= 8'b0;
ena_cic <= 1'b0;
end
else
begin
dcnt <= dcnt + 1;
ena_cic <= &dcnt;
end
end
//------------------------------
// convert to signed
//------------------------------
reg signed [isz-1:0] ddat;
always @(posedge clk)
begin
if(reset)
begin
ddat <= {isz{1'b0}};
end
else
begin
ddat <= in ^ {1'b1,{isz-1{1'b0}}};
end
end
//------------------------------
// tuner instance
//------------------------------
wire signed [isz-1:0] tuner_i, tuner_q;
tuner_2 #(
.dsz(isz),
.fsz(fsz)
)
u_tuner(
.clk(clk),
.reset(reset),
.in(ddat),
.frq(frq),
.ns_ena(ns_ena),
.i_out(tuner_i),
.q_out(tuner_q)
);
// testing - zero out one of the TDM samples on the tuner output
//wire signed [isz-1:0] tuner_iq_tst = (tuner_v==1'b1) ? tuner_iq : 10'h000;
//`define FULL_CIC
`ifdef FULL_CIC
//------------------------------
// Full precision CICs
//------------------------------
//------------------------------
// I cic decimator instance
//------------------------------
wire cic_v;
wire signed [32+isz-1:0] cic_i;
cic_dec_2 #(
.NUM_STAGES(4), // Stages of int / comb
.STG_GSZ(8), // Bit growth per stage
.ISZ(isz) // input word size
)
u_cic_i(
.clk(clk), // System clock
.reset(reset), // System POR
.ena_out(ena_cic), // Decimated output rate (2 clks wide)
.x(tuner_i), // Input data
.y(cic_i), // Output data
.valid(cic_v) // Output Valid
);
//------------------------------
// Q cic decimator instance
//------------------------------
wire signed [32+isz-1:0] cic_q;
cic_dec_2 #(
.NUM_STAGES(4), // Stages of int / comb
.STG_GSZ(8), // Bit growth per stage
.ISZ(isz) // input word size
)
u_cic_q(
.clk(clk), // System clock
.reset(reset), // System POR
.ena_out(ena_cic), // Decimated output rate (2 clks wide)
.x(tuner_q), // Input data
.y(cic_q), // Output data
.valid() // Output Valid (unused)
);
// trim cic output to 16 bits
wire signed [osz-1:0] cic_i_trim = cic_i[32+isz-1:32+isz-osz];
wire signed [osz-1:0] cic_q_trim = cic_q[32+isz-1:32+isz-osz];
`else
//------------------------------
// Full precision CICs
//------------------------------
parameter cicsz = 21;
//------------------------------
// I cic decimator instance
//------------------------------
wire cic_v;
wire signed [cicsz-1:0] cic_i;
cic_dec_3 #(
.NUM_STAGES(4), // Stages of int / comb
.STG_GSZ(8), // Bit growth per stage
.ISZ(isz), // input word size
.OSZ(cicsz) // output word size
)
u_cic_i(
.clk(clk), // System clock
.reset(reset), // System POR
.ena_out(ena_cic), // Decimated output rate (2 clks wide)
.x(tuner_i), // Input data
.y(cic_i), // Output data
.valid(cic_v) // Output Valid
);
//------------------------------
// Q cic decimator instance
//------------------------------
wire signed [cicsz-1:0] cic_q;
cic_dec_3 #(
.NUM_STAGES(4), // Stages of int / comb
.STG_GSZ(8), // Bit growth per stage
.ISZ(isz), // input word size
.OSZ(cicsz) // output word size
)
u_cic_q(
.clk(clk), // System clock
.reset(reset), // System POR
.ena_out(ena_cic), // Decimated output rate (2 clks wide)
.x(tuner_q), // Input data
.y(cic_q), // Output data
.valid() // Output Valid (unused)
);
// trim cic output to 16 bits
wire signed [osz-1:0] cic_i_trim = cic_i[cicsz-1:cicsz-osz];
wire signed [osz-1:0] cic_q_trim = cic_q[cicsz-1:cicsz-osz];
`endif
//------------------------------
// Mux CIC outputs into single stream
//------------------------------
reg cic_v_d, cic_iq_v;
reg signed [osz-1:0] cic_iq_mux;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
cic_v_d <= 1'b0;
cic_iq_v <= 1'b0;
cic_iq_mux <= {osz{1'b0}};
end
else
begin
cic_v_d <= cic_v;
if((cic_v_d == 1'b0) & (cic_v == 1'b1))
begin
cic_iq_v <= 1'b1;
cic_iq_mux <= cic_i_trim;
end
else if((cic_v_d == 1'b1) & (cic_v == 1'b0))
begin
cic_iq_v <= 1'b1;
cic_iq_mux <= cic_q_trim;
end
else
begin
cic_iq_v <= 1'b0;
end
end
end
//------------------------------
// 8x FIR decimator instance
//------------------------------
wire fir_v;
wire signed [osz-1:0] fir_qi;
fir8dec #(
.isz(osz), // input data size
.osz(osz) // output data size
)
u_fir(
.clk(clk), // System clock
.reset(reset), // System POR
.ena(cic_iq_v), // New sample available on input
.iq_in(cic_iq_mux), // Input data
.valid(fir_v), // New output sample ready
.qi_out(fir_qi) // Decimated Output data
);
//------------------------------
// demux outputs (fir output order is reversed)
//------------------------------
reg p_valid;
always @(posedge clk)
begin
if(reset == 1'b1)
begin
p_valid <= 1'b0;
valid <= 1'b0;
i_out <= {osz{1'b0}};
q_out <= {osz{1'b0}};
end
else
begin
p_valid <= fir_v;
if((p_valid == 1'b1) & (fir_v == 1'b1))
i_out <= fir_qi;
if((p_valid == 1'b0) & (fir_v == 1'b1))
begin
q_out <= fir_qi;
valid <= 1'b1;
end
else
valid <= 1'b0;
end
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// SHA-256 ////
//// Secure Hash Algorithm (SHA-256) testbench ////
//// ////
//// Author: marsgod ////
//// ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/sha_core/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002-2004 marsgod ////
//// ////
//// ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
`timescale 1ns/10ps
`define SHA256_TEST "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"
`define SHA256_TEST_PADDING {1'b1,63'b0,448'b0,64'd448} // 448 bit
`define SHA256_TEST_RESULT 256'h248d6a61_d20638b8_e5c02693_0c3e6039_a33ce459_64ff2167_f6ecedd4_19db06c1
module test_sha;
reg clk,rst,cmd_w_i;
reg [31:0] text_i;
reg [2:0] cmd_i;
wire [31:0] text_o;
wire [3:0] cmd_o;
initial
begin
// $sdf_annotate("syn/data/sha256.sdf",sha_core);
clk = 1'b0;
rst = 1'b0;
cmd_w_i = 1'b0;
cmd_i = 3'b0;
#21;
rst = 1'b1;
#17;
rst = 1'b0;
test_SHA256;
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
$finish;
end
always #5 clk = ~clk;
sha256 sha_core(
.clk_i(clk),
.rst_i(rst),
.text_i(text_i),
.text_o(text_o),
.cmd_i(cmd_i),
.cmd_w_i(cmd_w_i),
.cmd_o(cmd_o)
);
task test_SHA256;
integer i;
reg [1023:0] all_message;
reg [511:0] tmp_i;
reg [255:0] tmp_o;
reg [31:0] tmp;
begin
all_message = {`SHA256_TEST,`SHA256_TEST_PADDING};
tmp_i = all_message[1023:512];
tmp_o = `SHA256_TEST_RESULT;
#100;
@(posedge clk);
cmd_i = 3'b010;
cmd_w_i = 1'b1;
for (i=0;i<16;i=i+1)
begin
@(posedge clk);
cmd_w_i = 1'b0;
text_i = tmp_i[16*32-1:15*32];
tmp_i = tmp_i << 32;
end
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
while (cmd_o[3])
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
#100;
tmp_i = all_message[511:0];
@(posedge clk);
cmd_i = 3'b110;
cmd_w_i = 1'b1;
for (i=0;i<16;i=i+1)
begin
@(posedge clk);
cmd_w_i = 1'b0;
text_i = tmp_i[16*32-1:15*32];
tmp_i = tmp_i << 32;
end
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
while (cmd_o[3])
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
cmd_i = 3'b001;
cmd_w_i = 1'b1;
@(posedge clk);
cmd_w_i = 1'b0;
for (i=0;i<8;i=i+1)
begin
@(posedge clk);
#1;
tmp = tmp_o[8*32-1:7*32];
if (text_o !== tmp | (|text_o)===1'bx)
begin
$display("ERROR(SHA-256-%02d) Expected %x, Got %x", i,tmp, text_o);
end
else
begin
$display("OK(SHA-256-%02d),Expected %x, Got %x", i,tmp, text_o);
end
tmp_o = tmp_o << 32;
end
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
@(posedge clk);
#100;
end
endtask
endmodule |
#include <bits/stdc++.h> using namespace std; vector<int> r; vector<int> l; int n, ans, a[550000]; int main() { cin >> n; for (int i = 1; i <= n; i++) cin >> a[i]; a[0] = a[1]; a[n + 1] = a[n]; for (int i = 1; i <= n; i++) { if (a[i] == a[i + 1] && a[i] != a[i - 1]) r.push_back(i); if (a[i] != a[i + 1] && a[i] == a[i - 1]) l.push_back(i); } for (int i = 0; i < l.size(); i++) ans = max(ans, r[i] - l[i]); cout << ans / 2 << endl; for (int i = 0; i < l.size(); i++) if (a[l[i]] == a[r[i]]) for (int j = l[i]; j <= r[i]; j++) a[j] = a[l[i]]; else { for (int j = l[i]; j <= (r[i] + l[i]) / 2; j++) a[j] = a[l[i]]; for (int j = (r[i] + l[i]) / 2 + 1; j <= r[i]; j++) a[j] = a[r[i]]; } for (int i = 1; i <= n; i++) cout << a[i] << ; } |
module testit;
reg clk;
reg a_i;
reg b_i;
reg a_o;
reg b_o;
reg rst_n;
reg [7:0] shreg;
//== State enumeration
parameter [2:0] // synopsys enum state_info
SM_IDLE = 3'b000,
SM_SEND = 3'b001,
SM_WAIT1 = 3'b010;
//== State variables
reg [2:0] /* synopsys enum state_info */
state_r; /* synopsys state_vector state_r */
reg [2:0] /* synopsys enum state_info */
state_e1;
//== ASCII state decoding
/*AUTOASCIIENUM("state_r", "_stateascii_r", "sm_")*/
// Beginning of automatic ASCII enum decoding
reg [39:0] _stateascii_r; // Decode of state_r
always @(state_r) begin
case ({state_r})
SM_IDLE: _stateascii_r = "idle ";
SM_SEND: _stateascii_r = "send ";
SM_WAIT1: _stateascii_r = "wait1";
default: _stateascii_r = "%Erro";
endcase
end
// End of automatics
initial begin
clk = 0;
a_i = 0;
b_i = 0;
rst_n = 0;
#20 rst_n = 1;
end
always #5 clk = ~clk;
always @(posedge clk or rst_n) begin
if (~rst_n) begin
a_o <= 0;
b_o <= 0;
shreg <= 8'b00110011;
end
else begin
a_o <= a_i;
b_o <= b_i;
shreg <= {shreg[6:0], shreg[7]};
end
end
task set_a_i;
begin
a_i = shreg[0];
end
endtask // set_a_i
always @(shreg & a_o) begin
set_a_i;
end
initial begin
$vcdpluson;
#500 $finish;
end
endmodule // testit
|
#include <bits/stdc++.h> using namespace std; int main() { long long n, d, m, l, i, j, x; cin >> n >> d >> m >> l; for (i = 0; i < n - 1; i++) { if ((i * m + l) / d * d + d < (i + 1) * m) break; } cout << (i * m + l) / d * d + d; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 3e5 + 5; const int INF = 0x3f3f3f3f; const long long llINF = 0x3f3f3f3f3f3f3f3f; const int mod = 998244353; long long read() { long long x = 0, w = 1; char ch = 0; while (!isdigit(ch)) { if (ch == - ) w = -1; ch = getchar(); } while (isdigit(ch)) { x = x * 10 + (ch - 0 ); ch = getchar(); } return x * w; } int main() { int n = read(); long long sum = 0, a; while (n--) { a = read(); sum += a - 1; if (sum & 1) puts( 1 ); else puts( 2 ); } return 0; } |
#include <bits/stdc++.h> using namespace std; void print_ret(const std::vector<long long>& ret) { long long r = 0; for (typeof((ret).end()) it = (ret).begin(); it != (ret).end(); ++it) r ^= *it; cout << r << endl; cout << ret.size() << endl; for (typeof((ret).end()) it = (ret).begin(); it != (ret).end(); ++it) cout << *it << ; cout << endl; } int main(int argc, const char* argv[]) { long long l, r, k; std::vector<long long> ret; cin >> l >> r >> k; if (k == 1) { ret.push_back(l); } else if (k == 2) { k2: if (r - l >= 2) { ret.push_back(l + 1); if (l & 1) ret.push_back(l + 2); else ret.push_back(l); } else { ret.push_back(l); if ((l ^ (l + 1)) < l) ret.push_back(l + 1); } } else if (k == 3) { long long t = l; while (t & (t - 1)) t &= (t - 1); t |= (t << 1); if (t <= r) { ret.push_back(l); ret.push_back(t); ret.push_back(l ^ t); } else { goto k2; } } else { for (long long t = l; t <= r; t++) { if (!(t & 3)) { if (t + 3 <= r) { ret.push_back(t); ret.push_back(t + 1); ret.push_back(t + 2); ret.push_back(t + 3); print_ret(ret); return 0; } break; } } std::vector<long long> vals; for (long long t = l; t <= r; t++) vals.push_back(t); long long bestval = l; long long bestmask = 1; for (int mask = 1; mask < (1 << vals.size()); mask++) { long long cur = 0; for (int i = 0; i < vals.size(); i++) { if (mask & (1 << i)) cur ^= vals[i]; } if (cur < bestval) { bestval = cur; bestmask = mask; } } for (int i = 0; i < vals.size(); i++) { if (bestmask & (1 << i)) ret.push_back(vals[i]); } } print_ret(ret); return 0; } |
// mbt 9/8/2014
//
// bsg_front_side_bus_hop_in
//
// This implements the front side bus
// input side. In normal use, nodes
// must always keep their ready_i lines
// high and admit any data that arrives.
// Otherwise deadlock is likely, especially
// if multiple nodes are in use at once.
//
// This means in practice that every node
// needs an input buffer and must have
// some out-of-band mechanism for making
// sure that the buffer does not overflow.
//
// Although it is tempting
// to omit flow control and reduce
// this to a chain of registers,
// it creates a large overhead for
// doing simple, high bandwidth stream tests,
// which are one of the easiest ways
// to stress test the system.
// So we add the flow control.
// Let the hardware designer beware.
`include "bsg_defines.v"
module bsg_front_side_bus_hop_in
#(parameter `BSG_INV_PARAM( width_p)
, parameter fan_out_p=2
)
(input clk_i
, input reset_i
// from previous hop
, output ready_o
, input v_i
, input [width_p-1:0] data_i
// 0 is to the next hop
// 1 is to the local switch
, output [fan_out_p-1:0] v_o
, output [fan_out_p-1:0] [width_p-1:0] data_o
, input [fan_out_p-1:0] ready_i
);
logic [fan_out_p-1:0] sent_r, sent_n;
genvar i;
logic [fan_out_p-1:0] v_o_tmp;
logic [width_p-1:0] data_o_tmp;
wire fifo_v, fifo_yumi;
bsg_two_fifo #(.width_p(width_p)) fifo
(.clk_i (clk_i)
,.reset_i (reset_i)
,.data_i (data_i)
,.data_o (data_o_tmp)
,.v_o (fifo_v)
,.yumi_i (fifo_yumi)
,.ready_o (ready_o)
,.v_i (v_i)
);
for (i = 0; i < fan_out_p; i = i+1)
begin
assign data_o[i] = data_o_tmp;
assign v_o [i] = v_o_tmp[i];
// we have data and we haven't sent it
assign v_o_tmp[i] = fifo_v & ~sent_r[i];
always_ff @(posedge clk_i)
if (reset_i)
sent_r[i] <= 1'b0;
else
sent_r[i] <= sent_n[i] & ~fifo_yumi;
always_comb
begin
sent_n[i] = sent_r[i];
// if we have data,
if (v_o_tmp[i] & ready_i[i])
sent_n[i] = 1'b1;
end // always_comb
end
assign fifo_yumi = & sent_n;
endmodule
`BSG_ABSTRACT_MODULE(bsg_front_side_bus_hop_in)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21O_BLACKBOX_V
`define SKY130_FD_SC_HD__A21O_BLACKBOX_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a21o (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21O_BLACKBOX_V
|
#include <bits/stdc++.h> using namespace std; long long N, K; long long s1, s2, p1, p2; long long Get(long long now, long long to) { if (now <= to << 1) return 0; long long re = 0; s1 = 1; s2 = 0; p1 = now; p2 = now - 1; while (p2 >= to << 1) { if (p2 == to << 1) return s1 + re; if (p1 & 1) { re += s1 + s2; s1 = (s1 << 1) + s2; } else { re += s1 + s2; s2 = (s2 << 1) + s1; } p2 = (p1 >> 1) - 1; p1 = (p1 >> 1); } return re; } long long solve(long long l, long long r, long long p, long long k) { long long mid = (l + r) >> 1; if (k == 1) return mid; long long tmp = Get(mid - l, p), Tmp = Get(r - mid, p + 1); if (k > tmp + Tmp + 1) return solve(mid + 1, r, p, k - tmp - 1); else return solve(l, mid - 1, p, k - Tmp - 1); } int main() { scanf( %lld%lld , &N, &K); if (K == 1) { printf( 1 ); return 0; } if (K == 2) { printf( %lld , N); return 0; } N -= 2; K -= 2; long long l = 0, r = (N >> 1) + 1; while (r - l > 1) { long long mid = (l + r) >> 1; if (Get(N, mid) < K) r = mid; else l = mid; } printf( %lld , solve(1, N, l, K) + 1); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, c = 0; cin >> n; bool* V = new bool[n]; bool Back = false; for (int i = 0; i < n; ++i) { cin >> V[i]; if (V[i]) { if (Back && c) c++; c++; Back = false; } else { Back = true; } } cout << c << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; template <typename T> T abs(T a) { return a < 0 ? -a : a; } template <typename T> T sqr(T a) { return a * a; } const int INF = (int)1e9; const long double EPS = 1e-9; const long double PI = 3.1415926535897932384626433832795; long double a, b, h; inline pair<long double, long double> rotate( const pair<long double, long double>& a, const long double& ang) { return pair<long double, long double>( a.first * cos(ang) + a.second * sin(ang), -a.first * sin(ang) + a.second * cos(ang)); } inline long double dist(const long double& w, const long double& h, const long double& ang) { pair<long double, long double> pa(w * cos(ang), 0); pair<long double, long double> push_back(0, w * sin(ang)); pair<long double, long double> v = rotate(pair<long double, long double>(h, 0), ang - PI / 2); pa.first += v.first; pa.second += v.second; push_back.first += v.first; push_back.second += v.second; long double A, B, C; A = push_back.second - pa.second; B = pa.first - push_back.first; C = -A * pa.first - B * pa.second; return (A * b + B * a + C) / sqrtl(A * A + B * B); } inline long double findMaxAng(const long double& w, const long double& h) { long double lf = 0; long double rg = PI / 2; for (int i = 0; i < int(100); ++i) { long double mid = lf + (rg - lf) / 2; if (w * cos(mid) + h * sin(mid) > b) lf = mid; else rg = mid; } return lf; } inline bool check(const long double& w, const long double& h) { if (a + EPS < h) return false; if (w <= b + EPS) return true; long double lf = 0; long double rg = findMaxAng(w, h); for (int i = 0; i < int(200); ++i) { long double d = (rg - lf) / 3; long double ml = lf + d; long double mr = rg - d; if (dist(w, h, ml) > dist(w, h, mr)) lf = ml; else rg = mr; } return dist(w, h, lf) > -EPS; } int main() { cin >> a >> b >> h; long double lf = 0; long double rg = h; for (int i = 0; i < int(100); ++i) { long double mid = lf + ((rg - lf) / 2); if (check(h, mid) || check(mid, h)) lf = mid; else rg = mid; } if (lf < EPS) { puts( My poor head =( ); } else { cout.precision(10); cout << fixed << lf << endl; } return 0; } |
#include <bits/stdc++.h> using namespace std; const int MaxN = 123456, Mod = 1000000000; long long a[MaxN], f[MaxN]; int main(void) { int i, j, n, m; f[0] = f[1] = 1; for (i = 2; i < MaxN; i++) f[i] = (f[i - 1] + f[i - 2]) % Mod; while (scanf( %d %d , &n, &m) != EOF) { int i, t, l, r; for (i = 0; i < n; i++) scanf( %I64d , &a[i]); for (j = 0; j < m; j++) { scanf( %d %d %d , &t, &l, &r); if (t == 1) a[l - 1] = r; else { long long s = 0; for (i = 0; i <= r - l; i++) s = (s + a[i + l - 1] * f[i]) % Mod; printf( %d n , (int)s); } } } } |
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; long long gcd(long long a, long long b) { return b == 0 ? a : gcd(b, a % b); } long long lcm(long long a, long long b) { return a * (b / gcd(a, b)); } const int MAXN = 600010; set<int> g[MAXN]; int n, t, m, k; int visited[MAXN]; void dfs(int i) { visited[i] = 1; for (auto x : g[i]) if (!visited[x]) dfs(x); return; } int main() { cin >> n; pair<int, int> a[n]; for (long long i = 0; i < n; i++) cin >> a[i].first >> a[i].second; sort(a, a + n); int res = 0; set<pair<int, pair<int, int> > > s; for (long long i = 0; i < n; i++) { auto x = s.lower_bound({a[i].first, {-((long long)1e15), -((long long)1e15)}}); while (x != s.begin()) { s.erase(s.begin()); } auto it = s.upper_bound({a[i].second, {-((long long)1e15), -((long long)1e15)}}); x = s.begin(); while (x != it) { g[i].insert(x->second.second); g[x->second.second].insert(i); res++; if (res >= n) { cout << NO << n ; return 0; } x++; } s.insert({a[i].second, {a[i].first, i}}); } dfs(0); for (long long i = 0; i < n; i++) { if (!visited[i]) { cout << NO ; return 0; } } if (res == n - 1) cout << YES ; else cout << NO ; return 0; } |
#include <bits/stdc++.h> using namespace std; using ll = long long; using pii = pair<int, int>; int main() { ios_base::sync_with_stdio(false); int t; cin >> t; while (t--) { ll a, b, c; cin >> a >> b >> c; ll x, y; if (a == c and b == 1) { cout << -1 -1 << n ; continue; } if (c <= a) x = -1; else x = 1; if (a * b <= c) y = -1; else y = b; cout << x << << y << n ; } return 0; } |
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module nand_bram_block_dp #(
parameter DATA = 32,
parameter ADDR = 10,
parameter DEPTH = 517
) (
input wire a_clk,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
input wire b_clk,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
reg [DATA-1:0] mem [DEPTH-1:0];
always @(posedge a_clk) begin
a_dout <= mem[a_addr];
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end
end
always @(posedge b_clk) begin
b_dout <= mem[b_addr];
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; bool check(int x1, int y1, int r1, int x2, int y2, int r2, int R2) { int l = (x1 - x2) * (x1 - x2) + (y1 - y2) * (y1 - y2); int rr1 = (r1 - r2) * (r1 - r2); int rr2 = (r1 + r2) * (r1 + r2); int RR1 = (r1 - R2) * (r1 - R2); int RR2 = (r1 + R2) * (r1 + R2); if (l <= rr1 && l <= RR1 && (r1 <= r2 || r1 >= R2)) return 1; if (rr2 <= l && RR2 <= l) return 1; return 0; } int main() { int x1, y1, r1, R1, x2, y2, r2, R2; while (scanf( %d %d %d %d , &x1, &y1, &r1, &R1) != EOF) { scanf( %d %d %d %d , &x2, &y2, &r2, &R2); int ans = 0; if (check(x1, y1, r1, x2, y2, r2, R2)) ans++; if (check(x1, y1, R1, x2, y2, r2, R2)) ans++; if (check(x2, y2, r2, x1, y1, r1, R1)) ans++; if (check(x2, y2, R2, x1, y1, r1, R1)) ans++; printf( %d n , ans); } return 0; } |
`timescale 1ns / 1ns
`define HALT 4'hF
module opc2tb();
reg [7:0] mem [ 2047:0 ];
reg clk, reset_b;
wire [9:0] addr;
wire rnw ;
wire ceb = 1'b0;
wire oeb = !rnw;
wire [7:0] data = ( !ceb & rnw & !oeb ) ? mem[ addr ] : 8'bz ;
// OPC CPU instantiation
opc2cpu dut0_u (.address(addr), .data(data), .rnw(rnw), .clk(clk), .reset_b(reset_b));
initial
begin
$dumpvars;
$readmemh("test.hex", mem); // Problems with readmemb - use readmemh for now
clk = 0;
reset_b = 0;
#1005 reset_b = 1;
#180000000 $finish;
end
// Simple negedge synchronous memory to avoid messing with delays initially
always @ (negedge clk)
if (!rnw && !ceb && oeb && reset_b)
mem[addr] <= data;
always
begin
#500 clk = !clk;
//$display("%4x %2x %x", dut0_u.PC_q, dut0_u.ACC_q, dut0_u.LINK_q);
end
// Always stop simulation on encountering the halt pseudo instruction
always @ (negedge clk)
if (dut0_u.IR_q== `HALT)
begin
$display("Simulation terminated with halt instruction at time", $time);
$writememh("test.vdump",mem);
$finish;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; long long mp[2050][2050]; int main() { for (int i = 0; i <= 1000; i++) { mp[i][0] = 1; mp[i][i] = 1; } for (int i = 0; i <= 1000; i++) { for (int j = 1; j < i; j++) { mp[i][j] = (mp[i - 1][j] + mp[i - 1][j - 1]) % 1000000007; } } long long n, m, k; cin >> n >> m >> k; cout << (mp[n - 1][2 * k] * mp[m - 1][2 * k]) % 1000000007 << n ; return 0; } |
#include <bits/stdc++.h> using namespace std; const int mod = 1e9 + 7; template <class T, class U> inline void add_self(T &a, U b) { a += b; if (a >= mod) a -= mod; if (a < 0) a += mod; } template <class T, class U> inline void min_self(T &x, U y) { if (y < x) x = y; } template <class T, class U> inline void max_self(T &x, U y) { if (y > x) x = y; } template <typename T> void print(T v, bool show_index = false) { int w = 2; if (show_index) { for (int i = 0; i < v.size(); i++) cout << setw(w) << i << ; cout << endl; } for (auto i = v.begin(); i != v.end(); i++) cout << setw(w) << *i << ; cout << endl; } template <typename T> void print_vv(T v) { if (v.size() == 0) { cout << Empty << endl; return; } int w = 3; cout << setw(w) << ; for (int j = 0; j < v[0].size(); j++) cout << setw(w) << j << ; cout << endl; for (auto i = 0; i < v.size(); i++) { cout << i << { ; for (auto j = 0; j != v[i].size(); j++) { cout << setw(w) << v[i][j] << , ; } cout << }, << endl; } cout << endl; } template <class T, class U> void print_m(map<T, U> m, int w = 3) { if (m.empty()) { cout << Empty << endl; return; } for (auto x : m) cout << ( << x.first << : << x.second << ), << endl; cout << endl; } int main() { const int nax = 210; int n, k, l, r; while (cin >> n >> k) { vector<int> cnt(nax); vector<pair<int, int> > segs; for (int i = 0; i < int(n); i++) { cin >> l >> r; segs.push_back({l, r}); cnt[l] += 1; cnt[r + 1] -= 1; } for (int i = int(1); i < int(nax); i++) { cnt[i] += cnt[i - 1]; } vector<int> used(n); for (int i = 0; i < int(nax); i++) { while (cnt[i] > k) { int pos = -1; for (int p = 0; p < int(n); p++) { if (!used[p] && (segs[p].first <= i && i <= segs[p].second) && (pos == -1 || segs[p].second > segs[pos].second)) pos = p; } assert(pos != -1); used[pos] = 1; for (int j = segs[pos].first; j <= segs[pos].second; ++j) --cnt[j]; } } vector<int> out; for (int i = 0; i < int(n); i++) if (used[i]) out.push_back(i + 1); int sz = out.size(); cout << sz << endl; for (int i = 0; i < int(sz); i++) cout << out[i] << ; cout << endl; } return 0; } |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR2_BLACKBOX_V
`define SKY130_FD_SC_HS__XNOR2_BLACKBOX_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__xnor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR2_BLACKBOX_V
|
`include "../include/tune.v"
// PentEvo project (c) NedoPC 2008-2011
//
// vertical blank, sync and window. H is period of horizontal sync;
// from the last non-blanked line:
// 3H is pre-blank,
// 2.xxH is vertical sync (slightly more than 2H, all hsync edges preserved)
// vblank is total of 25H
module video_sync_v(
input wire clk,
input wire hsync_start, // synchronizing signal
input wire line_start, // to end vsync some time after hsync has ended
input wire hint_start,
// atm video mode input
input wire mode_atm_n_pent,
output reg vblank,
output reg vsync,
output reg int_start, // one-shot positive pulse marking beginning of INT for Z80
output reg vpix // vertical picture marker: active when there is line with pixels in it, not just a border. changes with hsync edge
);
localparam VBLNK_BEG = 9'd00;
localparam VSYNC_BEG = 9'd08;
localparam VSYNC_END = 9'd11;
localparam VBLNK_END = 9'd32;
localparam INT_BEG = 9'd0;
// pentagon (x192)
localparam VPIX_BEG_PENT = 9'd080;//9'd064;
localparam VPIX_END_PENT = 9'd272;//9'd256;
// ATM (x200)
localparam VPIX_BEG_ATM = 9'd076;//9'd060;
localparam VPIX_END_ATM = 9'd276;//9'd260;
localparam VPERIOD = 9'd320; // pentagono foreva!
reg [8:0] vcount;
initial
begin
vcount = 9'd0;
vsync = 1'b0;
vblank = 1'b0;
vpix = 1'b0;
int_start = 1'b0;
end
always @(posedge clk) if( hsync_start )
begin
if( vcount==(VPERIOD-9'd1) )
vcount <= 9'd0;
else
vcount <= vcount + 9'd1;
end
always @(posedge clk) if( hsync_start )
begin
if( vcount==VBLNK_BEG )
vblank <= 1'b1;
else if( vcount==VBLNK_END )
vblank <= 1'b0;
end
always @(posedge clk)
begin
if( (vcount==VSYNC_BEG) && hsync_start )
vsync <= 1'b1;
else if( (vcount==VSYNC_END) && line_start )
vsync <= 1'b0;
end
always @(posedge clk)
begin
if( (vcount==INT_BEG) && hint_start )
int_start <= 1'b1;
else
int_start <= 1'b0;
end
always @(posedge clk) if( hsync_start )
begin
if( vcount==(mode_atm_n_pent ? VPIX_BEG_ATM : VPIX_BEG_PENT) )
vpix <= 1'b1;
else if( vcount==(mode_atm_n_pent ? VPIX_END_ATM : VPIX_END_PENT) )
vpix <= 1'b0;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2018 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
reg [15:0] v1;
reg [15:0] v2;
reg [15:0] v3;
integer nosplit;
always @ (posedge clk) begin
// write needed so that V3Dead doesn't kill v0..v3
$write(" values %x %x %x\n", v1, v2, v3);
// Locally-set 'nosplit' will prevent the if from splitting
// in splitAlwaysAll(). This whole always block should still be
// intact when we call splitReorderAll() which is the subject
// of this test.
nosplit = cyc;
if (nosplit > 2) begin
/* S1 */ v1 <= 16'h0;
/* S2 */ v1 <= m_din;
/* S3 */ if (m_din == 16'h0) begin
/* X1 */ v2 <= v1;
/* X2 */ v3 <= v2;
end
end
// We expect to swap S2 and S3, and to swap X1 and X2.
// We can check that this worked by the absense of dly vars
// in the generated output; if the reorder fails (or is disabled)
// we should see dly vars for v1 and v2.
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; void fastIo() { ios_base::sync_with_stdio(false); cin.tie(NULL); } int main() { fastIo(); int q; cin >> q; while (q--) { int n; cin >> n; string s; cin >> s; if (n == 1) { cout << NO << endl; } else if (n == 2) { if (s[0] >= s[1]) cout << NO << endl; else { cout << YES << endl; cout << 2 << endl; cout << s[0] << << s[1] << endl; } } else { cout << YES << endl; cout << 2 << endl; cout << s[0] << ; for (int i = 1; i < n; i++) cout << s[i]; cout << endl; } } return 0; } |
`timescale 1ns/1ns
`define DAC_MSB 7
`define ADC_MSB 15
`define NSEC 1
`define USEC (`NSEC*1000)
`define MSEC (`USEC*1000)
// TOPLEVEL TO STIMULATE
module toy_toplevel(
input wire [`ADC_MSB:0] V_load_adc,
input wire V_load_valid,
output reg pwm,
output reg [`DAC_MSB:0] V_src
) ;
parameter time STARTUP_DELAY = 2 * `MSEC;
parameter real ADC_RANGE = 32.0;
parameter real ADC_OFFSET = -ADC_RANGE/2.0;
parameter real DAC_RANGE = 16.0;
parameter real DAC_OFFSET = -DAC_RANGE/2.0;
parameter real UPDATE_FREQ_MHZ = 1.0;
parameter time CLOCK_INTERVAL = `USEC / UPDATE_FREQ_MHZ;
reg clk = 0;
reg ls_only = 0;
real V_load = 0.0;
function real decode_value( input real base, input real range, input integer msb, input integer value );
begin
decode_value = base + range * value / $itor(1<< (msb+1));
end
endfunction
function integer encode_value( input real base, input real range, input integer msb, input real value );
begin
encode_value = (value -base) * $itor(1<< (msb+1)) / range;
end
endfunction
always @( posedge(V_load_valid) )
begin
V_load = decode_value( ADC_OFFSET, ADC_RANGE, `ADC_MSB, V_load_adc );
end
initial
begin
clk = 0;
ls_only = 0;
#( `USEC * 1 );
# ( CLOCK_INTERVAL/4 );
$finish; // Stop things for VPI unit test...
forever
begin
# ( CLOCK_INTERVAL/2 );
clk <= ! clk;
end
end
always @clk
begin
ls_only= (V_load >2.5);
pwm <= clk | ls_only;
end
initial
begin
V_src = encode_value( DAC_OFFSET, DAC_RANGE, `DAC_MSB, 7.2 );
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_PP_BLACKBOX_V
/**
* lpflow_inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputiso1n (
X ,
A ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1N_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_BLACKBOX_V
/**
* udp_dff$P_pp$PG$N: Positive edge triggered D flip-flop
* (Q output UDP).
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dff$P_pp$PG$N (
Q ,
D ,
CLK ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_P_PP_PG_N_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSTP_TB_V
`define SKY130_FD_SC_HD__SDFSTP_TB_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfstp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 SCD = 1'b1;
#220 SCE = 1'b1;
#240 SET_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 SCD = 1'b0;
#380 SCE = 1'b0;
#400 SET_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SET_B = 1'b1;
#600 SCE = 1'b1;
#620 SCD = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SET_B = 1'bx;
#760 SCE = 1'bx;
#780 SCD = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sdfstp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSTP_TB_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_sync_clk1_clk2.v ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor () ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_sync_clk1_clk2.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.3 2001/11/26 10:47:09 mohor
// Crc generation is different for read or write commands. Small synthesys fixes.
//
// Revision 1.2 2001/10/19 11:40:01 mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
//
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
// FF in clock domain 1 is being set by a signal from the clock domain 2
module dbg_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);
parameter Tp = 1;
input clk1;
input clk2;
input reset1;
input reset2;
input set2;
output sync_out;
reg set2_q;
reg set2_q2;
reg set1_q;
reg set1_q2;
reg clear2_q;
reg clear2_q2;
reg sync_out;
wire z;
assign z = set2 | set2_q & ~clear2_q2;
// Latching and synchronizing "set" to clk2
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
set2_q <=#Tp 1'b0;
else
set2_q <=#Tp z;
end
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
set2_q2 <=#Tp 1'b0;
else
set2_q2 <=#Tp set2_q;
end
// Synchronizing "set" to clk1
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
set1_q <=#Tp 1'b0;
else
set1_q <=#Tp set2_q2;
end
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
set1_q2 <=#Tp 1'b0;
else
set1_q2 <=#Tp set1_q;
end
// Synchronizing "clear" to clk2
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
clear2_q <=#Tp 1'b0;
else
clear2_q <=#Tp set1_q2;
end
always @ (posedge clk2 or posedge reset2)
begin
if(reset2)
clear2_q2 <=#Tp 1'b0;
else
clear2_q2 <=#Tp clear2_q;
end
always @ (posedge clk1 or posedge reset1)
begin
if(reset1)
sync_out <=#Tp 1'b0;
else
sync_out <=#Tp set1_q2;
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int Q, m, n, a[10001], c[100001], ans, f[5001][101], d[1001]; char b[500001][13]; void dfs(int x, int now, int zong, int he) { if (x > n) { if (zong <= 100) f[he][zong] += c[now]; return; } dfs(x + 1, now * 2 + 1, zong + (d[x] == 1 ? a[x] : 0), he); dfs(x + 1, now * 2, zong + (d[x] == 0 ? a[x] : 0), he); } int main() { int i, j, now, t, ha; char s[10001]; scanf( %d%d%d , &n, &m, &Q); for (i = 1; i <= n; i++) scanf( %d , &a[i]); for (i = 1; i <= m; i++) { now = 0; scanf( %s , b[i] + 1); for (j = 1; j <= n; j++) { now = now * 2; if (b[i][j] == 1 ) now++; } c[now]++; } for (i = 0; i < (1 << n); i++) { now = i; ha = 0; for (j = 1; j <= n; j++) { d[j] = now % 2; ha = ha * 2 + d[j]; now /= 2; } dfs(1, 0, 0, ha); } for (i = 0; i < (1 << n); i++) for (j = 1; j <= 100; j++) f[i][j] += f[i][j - 1]; while (Q--) { scanf( %s%d , s + 1, &t); now = 0; for (i = 1; i <= n; i++) now = now * 2 + (s[i] == 1 ); printf( %d n , f[now][t]); } } |
#include <bits/stdc++.h> using namespace std; int main() { int n; cin >> n; int arr; int a = 0, b = 0, i, j, k; for (i = 0; i < n; i++) { cin >> arr; if (arr >= 0) { a += arr; } else { b += arr; } } cout << a - b << endl; return 0; } |
// Copyright (c) 2000-2013 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
//
// Transfer takes 2 dCLK to see data,
// sRDY recovers takes 2 dCLK + 2 sCLK
module SyncHandshake(
sCLK,
sRST,
dCLK,
sEN,
sRDY,
dPulse
);
parameter init = 1'b0;
parameter delayreturn = 1'b0;
// Source clock port signal
input sCLK ;
input sRST ;
input sEN ;
output sRDY ;
// Destination clock port signal
input dCLK ;
output dPulse ;
// Flops to hold data
reg dSyncReg1, dSyncReg2 ;
reg dLastState ;
reg sToggleReg ;
reg sSyncReg1, sSyncReg2 ;
// Output signal
assign dPulse = dSyncReg2 != dLastState ;
assign sRDY = sSyncReg2 == sToggleReg;
wire ackValue = delayreturn ? dLastState : dSyncReg2 ;
always @(posedge sCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY ! init ; // Reset hi so sRDY is low during reset
sSyncReg2 <= `BSV_ASSIGNMENT_DELAY ! init ;
sToggleReg <= `BSV_ASSIGNMENT_DELAY init ;
end
else
begin
// hadshake return synchronizer
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY ackValue ;// clock domain crossing
sSyncReg2 <= `BSV_ASSIGNMENT_DELAY sSyncReg1 ;
// Pulse send
if ( sEN )
begin
sToggleReg <= `BSV_ASSIGNMENT_DELAY ! sToggleReg ;
end // if ( sEN )
end
end // always @ (posedge sCLK or `BSV_RESET_EDGE sRST)
always @(posedge dCLK or `BSV_RESET_EDGE sRST)
begin
if (sRST == `BSV_RESET_VALUE)
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY init;
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY init;
dLastState <= `BSV_ASSIGNMENT_DELAY init ;
end
else
begin
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sToggleReg ;// domain crossing
dSyncReg2 <= `BSV_ASSIGNMENT_DELAY dSyncReg1 ;
dLastState <= `BSV_ASSIGNMENT_DELAY dSyncReg2 ;
end
end // always @ (posedge dCLK or `BSV_RESET_EDGE sRST)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
dSyncReg1 = init ;
dSyncReg2 = init ;
dLastState = init ;
sToggleReg = init ;
sSyncReg1 = ! init ;
sSyncReg2 = ! init ;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule // HandshakeSync
|
#include <bits/stdc++.h> using namespace std; const int N = 2e5 + 2; int tree[N * 32][2], cnt[N * 32]; long long int curr = 1, n, ans; vector<long long int> arr(N); void clean() { for (long long int i = 0; i <= N * 32 - 1; i++) tree[i][0] = tree[i][1] = -1; } void add(long long int x) { long long int v = 0; cnt[v]++; for (long long int i = 32; i >= 0; i--) { long long int b = (x >> i) & 1; if (tree[v][b] == -1) tree[v][b] = curr++; v = tree[v][b]; cnt[v]++; } } long long int calc(int v) { if (v == -1) return 0; int s0 = 0, s1 = 0; if (tree[v][0] != -1) s0 = cnt[tree[v][0]]; if (tree[v][1] != -1) s1 = cnt[tree[v][1]]; if (s0 == 0 && s1 == 0) return cnt[v]; if (s0 == 0) return calc(tree[v][1]); if (s1 == 0) return calc(tree[v][0]); return 1 + max(calc(tree[v][0]), calc(tree[v][1])); } int main() { clean(); cin >> n; for (long long int i = 0; i <= n - 1; i++) cin >> arr[i], add(arr[i]); cout << n - calc(0); } |
#include <bits/stdc++.h> using namespace std; int main() { int n, pos, l, r, diff, rflag = 1, lflag = 1; cin >> n >> pos >> l >> r; diff = r - l; if (l == 1) lflag = 0; if (r == n) rflag = 0; if (lflag == 0 && rflag == 0) cout << 0; else if (lflag == 0) cout << abs(r - pos) + 1; else if (rflag == 0) cout << abs(pos - l) + 1; else cout << diff + min(abs(r - pos), abs(pos - l)) + 2; } |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
parameter ONE = 1;
wire [17:10] bitout;
reg [7:0] allbits;
reg [15:0] onebit;
sub sub [7:0] (allbits, onebit, bitout);
integer x;
always @ (posedge clk) begin
//$write("%x\n", bitout);
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
allbits <= 8'hac;
onebit <= 16'hc01a;
end
if (cyc==2) begin
if (bitout !== 8'h07) $stop;
allbits <= 8'hca;
onebit <= 16'h1f01;
end
if (cyc==3) begin
if (bitout !== 8'h41) $stop;
if (sub[0].bitout !== 1'b1) $stop;
if (sub[1].bitout !== 1'b0) $stop;
`ifndef verilator // Hacky array subscripting
if (sub[ONE].bitout !== 1'b0) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
module sub (input [7:0] allbits, input [1:0] onebit, output bitout);
`INLINE_MODULE
wire bitout = (^ onebit) ^ (^ allbits);
endmodule
|
#include <bits/stdc++.h> using namespace std; const long long MOD = 1e9 + 7; const long long N = 2e5 + 6; const long long inf = 1e15; long long ex, ey, ez, bx, by, bz, a[7]; int main() { ios::sync_with_stdio(false); cin.tie(NULL); if (fopen( inp.txt , r )) { freopen( inp.txt , r , stdin); freopen( outp.txt , w , stdout); } cin >> ex >> ey >> ez; cin >> bx >> by >> bz; long long i, ans = 0; for (i = 1; i <= 7; i++) cin >> a[i]; if (ex > bx) ans += a[6]; else if (ex < 0) ans += a[5]; if (ey > by) ans += a[2]; else if (ey < 0) ans += a[1]; if (ez > bz) ans += a[4]; else if (ez < 0) ans += a[3]; cout << ans; return 0; } |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: audio_fifo.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module audio_fifo (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [31:0] q = sub_wire2[31:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "ON",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL audio_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; const int N = 1e5 + 5; int n, m, k, a[N]; long long rem, cnt, sum; double ans; int main() { cin >> n >> k >> m; for (int i = 1; i <= n; ++i) { scanf( %d , a + i); sum += a[i]; } sort(a + 1, a + n + 1); for (int i = 1; i <= n; ++i) { cnt = n - i + 1; rem = m - i + 1; if (rem < 0) { break; } ans = max(ans, (sum + min(rem, cnt * k)) * 1.0 / cnt); sum -= a[i]; } printf( %0.9lf , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; void s() { puts( Stannis ); } void d() { puts( Daenerys ); } int main() { int n, k; scanf( %d %d , &n, &k); int odd = 0; int even = 0; long long tot = 0; for (int i = 0; i < n; i++) { int x; scanf( %d , &x); if (x % 2 == 0) even++; else odd++; tot += (long long)x; } int move = n - k; if (n == k) { if (tot % 2LL == 0) { d(); } else { s(); } } else { if (move % 2 == 1) { if (move < odd && move < even) { s(); } else { if (move / 2 >= odd) { d(); } else { if (move / 2 >= even && ((move - even) + odd) % 2 == 0) { d(); } else { s(); } } } } else { if (move < odd && move < even) { d(); } else { if (move / 2 >= even && ((move - even) + odd) % 2 == 1) { s(); } else { d(); } } } } return 0; } |
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: three_new2.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module three_new2 (
address,
clock,
q);
input [9:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../newnums2/three_new2.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../newnums2/three_new2.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../newnums2/three_new2.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL three_new2.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL three_new2.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL three_new2.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL three_new2.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL three_new2_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL three_new2_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
#include <bits/stdc++.h> using namespace std; #pragma comment(linker, /STACK:102400000,102400000 ) const int N = 205; int n; long long a[N]; map<long long, int> mp; vector<int> G[N], ans; bool vis[N]; bool dfs(int u, int step) { if (step == n) { ans.push_back(u); return true; } vis[u] = true; for (int to : G[u]) if (!vis[to]) { if (dfs(to, step + 1)) { ans.push_back(u); return true; } } vis[u] = false; return false; } int main() { scanf( %d , &n); for (int i = 1; i <= n; ++i) scanf( %lld , &a[i]), mp[a[i]] = i; for (int i = 1; i <= n; ++i) { if (a[i] % 3 == 0) { if (mp.find(a[i] / 3) != mp.end()) G[mp[a[i] / 3]].push_back(i); } if (mp.find(a[i] * 2) != mp.end()) G[mp[a[i] * 2]].push_back(i); } for (int i = 1; i <= n; ++i) { memset(vis, false, sizeof(vis)); if (dfs(i, 1)) { for (int v : ans) printf( %lld , a[v]); break; } } return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = 1e6 + 5; const long long INF = 1e18; int n; int p[N]; long long dif[N]; long long ans = INF; int id; void add(int l, int r, int val) { dif[l] += val; dif[r + 1] -= val; } int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); cin >> n; long long res = 0; for (int i = 1; i <= n; i++) { cin >> p[i]; res += (1LL) * abs(p[i] - i); if (p[i] >= i) { add(2, i, 1); add(i + 1, i + 1, (n - p[i]) - (p[i] - 1)); add(i + 2, i + 2 + (n - p[i]) - 1, -1); add(i + 2 + (n - p[i]), n, 1); } else { add(2, i - p[i] + 1, -1); add(i - p[i] + 2, i, 1); add(i + 1, i + 1, (n - p[i]) - (p[i] - 1)); add(i + 2, n, -1); } } for (int i = 1; i <= n; i++) { dif[i] += dif[i - 1]; res += dif[i]; if (res < ans) { ans = res, id = n - i + 1; if (id == n) id = 0; } } cout << ans << << id << n ; return 0; } |
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import PrimInt63 FloatClass.
(** * Definition of the interface for primitive floating-point arithmetic
This interface provides processor operators for the Binary64 format of the
IEEE standard. *)
(** ** Type definition for the co-domain of [compare] *)
Variant float_comparison : Set := FEq | FLt | FGt | FNotComparable.
Register float_comparison as kernel.ind_f_cmp.
Register float_class as kernel.ind_f_class.
(** ** The main type *)
(** [float]: primitive type for Binary64 floating-point numbers. *)
Primitive float := #float64_type.
(** ** Syntax support *)
Module Import PrimFloatNotationsInternalA.
Declare Scope float_scope.
Delimit Scope float_scope with float.
Bind Scope float_scope with float.
End PrimFloatNotationsInternalA.
Declare ML Module "float_syntax_plugin".
(** ** Floating-point operators *)
Primitive classify := #float64_classify.
Primitive abs := #float64_abs.
Primitive sqrt := #float64_sqrt.
Primitive opp := #float64_opp.
Primitive eqb := #float64_eq.
Primitive ltb := #float64_lt.
Primitive leb := #float64_le.
Primitive compare := #float64_compare.
Primitive mul := #float64_mul.
Primitive add := #float64_add.
Primitive sub := #float64_sub.
Primitive div := #float64_div.
Module Import PrimFloatNotationsInternalB.
Notation "- x" := (opp x) : float_scope.
Notation "x =? y" := (eqb x y) (at level 70, no associativity) : float_scope.
Notation "x <? y" := (ltb x y) (at level 70, no associativity) : float_scope.
Notation "x <=? y" := (leb x y) (at level 70, no associativity) : float_scope.
Notation "x ?= y" := (compare x y) (at level 70, no associativity) : float_scope.
Notation "x * y" := (mul x y) : float_scope.
Notation "x + y" := (add x y) : float_scope.
Notation "x - y" := (sub x y) : float_scope.
Notation "x / y" := (div x y) : float_scope.
End PrimFloatNotationsInternalB.
(** ** Conversions *)
(** [of_uint63]: convert a primitive unsigned integer into a float value.
The value is rounded if need be. *)
Primitive of_uint63 := #float64_of_uint63.
(** Specification of [normfr_mantissa]:
- If the input is a float value with an absolute value inside $[0.5, 1.)$#[0.5, 1.)#;
- Then return its mantissa as a primitive integer.
The mantissa will be a 53-bit integer with its most significant bit set to 1;
- Else return zero.
The sign bit is always ignored. *)
Primitive normfr_mantissa := #float64_normfr_mantissa.
(** ** Exponent manipulation functions *)
(** [frshiftexp]: convert a float to fractional part in $[0.5, 1.)$#[0.5, 1.)#
and integer part. *)
Primitive frshiftexp := #float64_frshiftexp.
(** [ldshiftexp]: multiply a float by an integral power of 2. *)
Primitive ldshiftexp := #float64_ldshiftexp.
(** ** Predecesor/Successor functions *)
(** [next_up]: return the next float towards positive infinity. *)
Primitive next_up := #float64_next_up.
(** [next_down]: return the next float towards negative infinity. *)
Primitive next_down := #float64_next_down.
(** ** Special values (needed for pretty-printing) *)
Definition infinity := Eval compute in div (of_uint63 1) (of_uint63 0).
Definition neg_infinity := Eval compute in opp infinity.
Definition nan := Eval compute in div (of_uint63 0) (of_uint63 0).
Register infinity as num.float.infinity.
Register neg_infinity as num.float.neg_infinity.
Register nan as num.float.nan.
(** ** Other special values *)
Definition one := Eval compute in (of_uint63 1).
Definition zero := Eval compute in (of_uint63 0).
Definition neg_zero := Eval compute in (-zero)%float.
Definition two := Eval compute in (of_uint63 2).
(** ** Predicates and helper functions *)
Definition is_nan f := negb (f =? f)%float.
Definition is_zero f := (f =? zero)%float. (* note: 0 =? -0 with floats *)
Definition is_infinity f := (abs f =? infinity)%float.
Definition is_finite (x : float) := negb (is_nan x || is_infinity x).
(** [get_sign]: return [true] for [-] sign, [false] for [+] sign. *)
Definition get_sign f :=
let f := if is_zero f then (one / f)%float else f in
(f <? zero)%float.
Module Export PrimFloatNotations.
Local Open Scope float_scope.
#[deprecated(since="8.13",note="use infix <? instead")]
Notation "x < y" := (x <? y) (at level 70, no associativity) : float_scope.
#[deprecated(since="8.13",note="use infix <=? instead")]
Notation "x <= y" := (x <=? y) (at level 70, no associativity) : float_scope.
#[deprecated(since="8.13",note="use infix =? instead")]
Notation "x == y" := (x =? y) (at level 70, no associativity) : float_scope.
Export PrimFloatNotationsInternalA.
Export PrimFloatNotationsInternalB.
End PrimFloatNotations.
#[deprecated(since="8.14",note="Use of_uint63 instead.")]
Notation of_int63 := of_uint63 (only parsing).
|
#include <bits/stdc++.h> using namespace std; const int N = 200000 + 10; int n; long long x[N], y[N]; int main() { scanf( %d , &n); for (int i = 1; i <= n; i++) { scanf( %lld%lld , &x[i], &y[i]); } while (1) { vector<int> r; for (int i = 1; i <= n; i++) { if ((x[i] + y[i]) % 2 == 0) r.push_back(i); } if (r.size() == 0 || r.size() == n) { for (int i = 1; i <= n; i++) { long long tx = x[i]; long long ty = y[i]; x[i] = tx - ty; y[i] = tx + ty; } if (x[1] % 2 != 0) { for (int i = 1; i <= n; i++) { x[i]++, y[i]++; x[i] /= 2, y[i] /= 2; } } while (1) { bool ok = 1; for (int i = 1; i <= n; i++) { if (x[i] % 2 || y[i] % 2) ok = 0; } if (ok) { for (int i = 1; i <= n; i++) { x[i] /= 2, y[i] /= 2; } } else { break; } } continue; } printf( %d n , r.size()); for (auto x : r) { printf( %d , x); } return 0; } } |
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Flow generator - flow descriptor FIFO
*/
module fg_fd_fifo #
(
parameter ADDR_WIDTH = 10,
parameter DEST_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* Flow descriptor input
*/
input wire input_fd_valid,
output wire input_fd_ready,
input wire [DEST_WIDTH-1:0] input_fd_dest,
input wire [15:0] input_fd_rate_num,
input wire [15:0] input_fd_rate_denom,
input wire [31:0] input_fd_len,
input wire [31:0] input_fd_burst_len,
/*
* Flow descriptor output
*/
output wire output_fd_valid,
input wire output_fd_ready,
output wire [DEST_WIDTH-1:0] output_fd_dest,
output wire [15:0] output_fd_rate_num,
output wire [15:0] output_fd_rate_denom,
output wire [31:0] output_fd_len,
output wire [31:0] output_fd_burst_len,
/*
* Status
*/
output wire [ADDR_WIDTH-1:0] count,
output wire [ADDR_WIDTH+32-1:0] byte_count
);
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}};
reg [DEST_WIDTH-1:0] fd_dest_reg = 0;
reg [15:0] fd_rate_num_reg = 0;
reg [15:0] fd_rate_denom_reg = 0;
reg [31:0] fd_len_reg = 0;
reg [31:0] fd_burst_len_reg = 0;
reg [DEST_WIDTH-1:0] fd_dest_mem[(2**ADDR_WIDTH)-1:0];
reg [15:0] fd_rate_num_mem[(2**ADDR_WIDTH)-1:0];
reg [15:0] fd_rate_denom_mem[(2**ADDR_WIDTH)-1:0];
reg [31:0] fd_len_mem[(2**ADDR_WIDTH)-1:0];
reg [31:0] fd_burst_len_mem[(2**ADDR_WIDTH)-1:0];
reg output_read = 1'b0;
reg output_fd_valid_reg = 1'b0;
reg [ADDR_WIDTH-1:0] count_reg = 0;
reg [ADDR_WIDTH+32-1:0] byte_count_reg = 0;
// full when first MSB different but rest same
wire full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) &&
(wr_ptr[ADDR_WIDTH-1:0] == rd_ptr[ADDR_WIDTH-1:0]));
// empty when pointers match exactly
wire empty = wr_ptr == rd_ptr;
wire write = input_fd_valid & ~full;
wire read = (output_fd_ready | ~output_fd_valid_reg) & ~empty;
assign output_fd_dest = fd_dest_reg;
assign output_fd_rate_num = fd_rate_num_reg;
assign output_fd_rate_denom = fd_rate_denom_reg;
assign output_fd_len = fd_len_reg;
assign output_fd_burst_len = fd_burst_len_reg;
assign count = count_reg;
assign byte_count = byte_count_reg;
assign input_fd_ready = ~full;
assign output_fd_valid = output_fd_valid_reg;
// write
always @(posedge clk or posedge rst) begin
if (rst) begin
wr_ptr <= 0;
end else if (write) begin
fd_dest_mem[wr_ptr[ADDR_WIDTH-1:0]] <= input_fd_dest;
fd_rate_num_mem[wr_ptr[ADDR_WIDTH-1:0]] <= input_fd_rate_num;
fd_rate_denom_mem[wr_ptr[ADDR_WIDTH-1:0]] <= input_fd_rate_denom;
fd_len_mem[wr_ptr[ADDR_WIDTH-1:0]] <= input_fd_len;
fd_burst_len_mem[wr_ptr[ADDR_WIDTH-1:0]] <= input_fd_burst_len;
wr_ptr <= wr_ptr + 1;
end
end
// read
always @(posedge clk or posedge rst) begin
if (rst) begin
rd_ptr <= 0;
end else if (read) begin
fd_dest_reg <= fd_dest_mem[rd_ptr[ADDR_WIDTH-1:0]];
fd_rate_num_reg <= fd_rate_num_mem[rd_ptr[ADDR_WIDTH-1:0]];
fd_rate_denom_reg <= fd_rate_denom_mem[rd_ptr[ADDR_WIDTH-1:0]];
fd_len_reg <= fd_len_mem[rd_ptr[ADDR_WIDTH-1:0]];
fd_burst_len_reg <= fd_burst_len_mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr <= rd_ptr + 1;
end
end
// source ready output
always @(posedge clk or posedge rst) begin
if (rst) begin
output_fd_valid_reg <= 1'b0;
end else if (output_fd_ready | ~output_fd_valid_reg) begin
output_fd_valid_reg <= ~empty;
end else begin
output_fd_valid_reg <= output_fd_valid_reg;
end
end
// counters
always @(posedge clk or posedge rst) begin
if (rst) begin
count_reg <= 0;
byte_count_reg <= 0;
end else if (output_fd_ready & output_fd_valid_reg & write) begin
byte_count_reg <= byte_count_reg + input_fd_len - fd_len_reg;
end else if (output_fd_ready & output_fd_valid_reg) begin
count_reg <= count_reg - 1;
byte_count_reg <= byte_count_reg - fd_len_reg;
end else if (write) begin
count_reg <= count_reg + 1;
byte_count_reg <= byte_count_reg + input_fd_len;
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int getint() { int x = 0; char c = getchar(); while (c < 0 || c > 9 ) c = getchar(); while (c >= 0 && c <= 9 ) x *= 10, x += (c - 0 ), c = getchar(); return x; } vector<pair<int, int> > ans; int n, m, tag; int a[40][40], b[40][40], cnt[910]; void init() { n = getint(); m = getint(); for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { a[i][j] = getint(); cnt[a[i][j]]++; if (cnt[a[i][j]] == 1) tag++; } for (int i = 1; i <= n; i++) for (int j = 1; j <= m; j++) { b[i][j] = getint(); cnt[b[i][j]]--; if (cnt[b[i][j]] == 0) tag--; if (cnt[b[i][j]] < 0) tag = 10000; } } void solve2() { if (n == 1) { for (int i = 1; i <= m; i++) if (a[1][i] != b[1][i]) { for (int j = i + 1; j <= m; j++) { if (a[1][j] != b[1][i]) continue; bool tflag = true; for (int k = i; k < j; k++) if (a[1][k] != b[1][k + 1]) { tflag = false; break; } for (int k = j + 1; k <= m; k++) if (a[1][k] != b[1][k]) { tflag = false; break; } if (tflag) { printf( %d n , j - i); for (int k = j; k >= i; k--) printf( 1 %d n , k); return; } } break; } for (int i = m; i >= 1; i--) if (a[1][i] != b[1][i]) { for (int j = i - 1; j >= 1; j--) { if (a[1][j] != b[1][i]) continue; bool tflag = true; for (int k = i; k > j; k--) if (a[1][k] != b[1][k - 1]) { tflag = false; break; } for (int k = j - 1; k >= 1; k--) if (a[1][k] != b[1][k]) { tflag = false; break; } if (tflag) { printf( %d n , i - j); for (int k = j; k <= i; k++) printf( 1 %d n , k); return; } } break; } puts( -1 ); return; } else { for (int i = 1; i <= n; i++) if (a[i][1] != b[i][1]) { for (int j = i + 1; j <= n; j++) { if (a[j][1] != b[i][1]) continue; bool tflag = true; for (int k = i; k < j; k++) if (a[k][1] != b[k + 1][1]) { tflag = false; break; } for (int k = j + 1; k <= n; k++) if (a[k][1] != b[k][1]) { tflag = false; break; } if (tflag) { printf( %d n , j - i); for (int k = j; k >= i; k--) printf( %d 1 n , k); return; } } } for (int i = n; i >= 1; i--) if (a[i][1] != b[i][1]) { for (int j = i - 1; j >= 1; j--) { if (a[j][1] != b[i][1]) continue; bool tflag = true; for (int k = i; k > j; k--) if (a[k][1] != b[k - 1][1]) { tflag = false; break; } for (int k = j - 1; k >= 1; k--) if (a[k][1] != b[k][1]) { tflag = false; break; } if (tflag) { printf( %d n , i - j); for (int k = j; k <= i; k++) printf( %d 1 n , k); return; } } break; } puts( -1 ); return; } } int sn, sm; void move(int ttn, int ttm) { while (sn != ttn && sm != ttm) { if (sn > ttn && sm > ttm) { int tswap = a[sn][sm]; a[sn][sm] = a[sn - 1][sm - 1]; a[sn - 1][sm - 1] = tswap; sn--; sm--; } else if (sn > ttn && sm < ttm) { int tswap = a[sn][sm]; a[sn][sm] = a[sn - 1][sm + 1]; a[sn - 1][sm + 1] = tswap; sn--; sm++; } else if (sn < ttn && sm > ttm) { int tswap = a[sn][sm]; a[sn][sm] = a[sn + 1][sm - 1]; a[sn + 1][sm - 1] = tswap; sn++; sm--; } else { int tswap = a[sn][sm]; a[sn][sm] = a[sn + 1][sm + 1]; a[sn + 1][sm + 1] = tswap; sn++; sm++; } ans.push_back(make_pair(sn, sm)); } while (sn != ttn) { if (sn < ttn) { int tswap = a[sn][sm]; a[sn][sm] = a[sn + 1][sm]; a[sn + 1][sm] = tswap; sn++; } else { int tswap = a[sn][sm]; a[sn][sm] = a[sn - 1][sm]; a[sn - 1][sm] = tswap; sn--; } ans.push_back(make_pair(sn, sm)); } while (sm != ttm) { if (sm < ttm) { int tswap = a[sn][sm]; a[sn][sm] = a[sn][sm + 1]; a[sn][sm + 1] = tswap; sm++; } else { int tswap = a[sn][sm]; a[sn][sm] = a[sn][sm - 1]; a[sn][sm - 1] = tswap; sm--; } ans.push_back(make_pair(sn, sm)); } } void turn(int rn) { for (int i = m; i >= 1; i--) { move(1, 1); if (a[rn][i] == b[rn][i]) continue; int xn = 0, xm; for (int j = rn; j >= 1; j--) { for (int k = (j == rn ? i - 1 : m); k >= 1; k--) if (a[j][k] == b[rn][i]) { xn = j; xm = k; break; } if (xn) break; } if (xm > i && xn < rn) { while (xm > i && xn < rn && xm - i > rn - xn) { if (xn == 1) { move(xn, xm - 1); move(xn + 1, xm - 1); move(xn, xm); xn++; xm--; } else { move(xn - 1, xm); move(xn, xm - 1); move(xn, xm); xm--; } } } while (xn != rn && xm != i) { if (xm < i) { if (xn == 1) { move(xn, xm - 1); move(xn + 1, xm); move(xn + 1, xm + 1); move(xn, xm); xn++; xm++; } else { move(xn - 1, xm + 1); move(xn + 1, xm + 1); move(xn, xm); xn++; xm++; } } else { if (xn == 1) { move(xn, xm - 1); move(xn + 1, xm - 1); move(xn, xm); xn++; xm--; } else { move(xn - 1, xm - 1); move(xn + 1, xm - 1); move(xn, xm); xn++; xm--; } } } while (xn != rn) { if (xn == 1) { move(xn, xm - 1); move(xn + 1, xm); move(xn, xm); xn++; } else { move(xn - 1, xm); if (xm == 1) move(xn, xm + 1); else move(xn, xm - 1); move(xn + 1, xm); move(xn, xm); xn++; } } while (xm != i) { assert(xn - 1 >= 1 && xm + 1 <= m); move(xn - 1, xm); move(xn, xm + 1); move(xn, xm); xm++; } } } void turn2() { for (int j = m; j >= 1; j--) for (int i = 2; i >= 1; i--) { move(1, 1); if (a[i][j] == b[i][j]) continue; int xn = 0, xm; for (int k = j; k >= 1; k--) { for (int l = (k == j ? i - 1 : 2); l >= 1; l--) { if (a[l][k] == b[i][j]) { xn = l; xm = k; break; } } if (xn) break; } while (xn != i && xm != j) { if (xn < i) { move(xn + 1, xm - 1); move(xn + 1, xm + 1); move(xn, xm); xn++; xm++; } else { move(xn - 1, xm + 1); move(xn, xm); xn--; xm++; } } while (xn != i) { if (xn < i) { move(xn, xm - 1); move(xn + 1, xm); move(xn, xm); xn++; } else { move(xn - 1, xm); move(xn, xm); xn--; } } while (xm != j) { if (xn != 1) { move(xn - 1, xm); move(xn, xm + 1); move(xn, xm); xm++; } else { move(xn, xm - 1); move(xn + 1, xm); move(xn, xm + 1); move(xn, xm); xm++; } } } } void solve3() { for (int i = 1; i <= n; i++) { for (int j = 1; j <= m; j++) if (a[i][j] == b[1][1]) { sn = i; sm = j; break; } if (sn) break; } int an = sn, am = sm; move(1, 1); for (int i = n; i > 2; i--) turn(i); turn2(); printf( %d n , (int)ans.size()); printf( %d %d n , an, am); for (int i = 0; i < (int)ans.size(); i++) printf( %d %d n , ans[i].first, ans[i].second); } void solve() { if (tag != 0) { puts( -1 ); return; } if (n == 1 || m == 1) solve2(); else solve3(); } int main() { init(); solve(); } |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 15:17:13 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_sim_netlist.v
// Design : system_inverter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_inverter_0_0,inverter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "inverter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_inverter_0_0
(x,
x_not);
input x;
output x_not;
wire x;
wire x_not;
LUT1 #(
.INIT(2'h1))
x_not_INST_0
(.I0(x),
.O(x_not));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
Copyright (c) 2015 LeafLabs LLC
Author: Charlie Lamantia
Date: December 2015
Testbench for rhd2000_dm. Exercises all available SPI commands including
ADC data conversion via concatenated input array "analogIn".
*/
`timescale 1ns / 1ps
`define STARTDELAY 100
`include "llLib.v"
module rhd2000_dm_tb #(
parameter CHANNELS = 32,
parameter REVISION = 1,
parameter UNIPOLAR = 1,
parameter ID = 1
)();
////// unit under test //////
reg [511:0] analog;
reg nCs = 1;
reg sclk;
wire miso;
reg mosi = 0;
wire aux;
rhd2000_dm #(
.CHANNELS (CHANNELS ),
.REVISION (REVISION ),
.UNIPOLAR (UNIPOLAR ),
.ID (ID )
)
uut (
.analogIn (analog ),
.nCs (nCs ),
.sClk (sclk ),
.mosi (mosi ),
.miso (miso ),
.aux (aux )
);
////// read/write transaction //////
task SPI_TRANSACTION;
input [15:0] command;
output [15:0] return;
reg [3:0] bit;
reg [15:0] temp;
begin
nCs = 0;
bit = 4'd15;
repeat (16) begin
#20.8
mosi = command[bit];
#10.4;
sclk = 1;
temp[bit] = miso;
#20.8
sclk = 0;
bit = bit - 4'd1;
end
#41.6;
nCs = 1;
return = temp;
// minimum time between transactions
#154.0;
end
endtask
////// tests //////
// convert
task testConvert;
reg [15:0] channel;
reg [15:0] return;
reg [15:0] dummy;
begin
channel = 0;
dummy = { 2'b01, 6'b101010, 8'd0 };
SPI_TRANSACTION ( channel << 8, return); // read first channel, return X
channel = channel + 1;
SPI_TRANSACTION ( channel << 8, return); // read second channel, return X
repeat (32) begin
channel = channel + 1;
SPI_TRANSACTION (channel << 8, return); // channel itterator, valid returns
// assert
if (return != channel - 1) begin
$display("!TEST FAILED! Capture channel %d returned %b.", channel - 1, return);
end
end
end
endtask
// calibration
task testCalibration;
reg [15:0] calibrate;
reg [15:0] return;
reg [15:0] dummy;
integer itteration;
begin
calibrate = { 2'b01, 6'b010101, 8'b0 };
dummy = { 2'b01, 6'b101010, 8'b0 };
itteration = 0;
SPI_TRANSACTION (calibrate, return); // send calibration command, return x
repeat (10) begin
itteration = itteration + 1;
SPI_TRANSACTION (dummy, return); // 9 cycles of dummy
// assert
if (return != {1'b1, 15'b0}) begin
$display("!TEST FAILED! Calibration itteration %d returned %b", itteration, return);
end
end
end
endtask
// read/write
task testReadWrite;
reg [5:0] address;
reg [7:0] data;
reg [15:0] return;
reg [15:0] dummy;
begin
dummy = { 2'b01, 6'b101010, 8'b0 };
address = 0;
repeat (28) begin
data = llLib.RANDRANGE (255, 0); // generate random data
SPI_TRANSACTION ({ 2'b10, address, data }, return); // write to address, return X
SPI_TRANSACTION ({ 2'b11, address, 8'b0 }, return); // read from address, return X
SPI_TRANSACTION (dummy, return); // dummy, return written value
// assert (write return)
if (return != { {8{1'b1}}, data }) begin
$display ("!TEST FAILED! Address %d write returned incorrect value %b", address, return);
end
SPI_TRANSACTION (dummy, return); // dummy, return read value;
// assert (read return: ram)
if (address >= 0 && address <= 17) begin
if (return != { 8'b0, data }) begin
$display("!TEST FAILED! RAM %d read returned incorrect value %b", address, return);
end
if (address == 17) address = 40;
else address = address + 1;
end
// else assert (read return: rom intan)
else if (address >= 40 && address <= 44) begin
if (address == 40 && return != { 8'b0, "I" }) begin
$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
end
else if (address == 41 && return != { 8'b0, "N" }) begin
$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
end
else if (address == 42 && return != { 8'b0, "T" }) begin
$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
end
else if (address == 43 && return != { 8'b0, "A" }) begin
$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
end
else if (address == 44 && return != { 8'b0, "N" }) begin
$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
end
if (address == 44) address = 60;
else address = address + 1;
end
// else assert (read return: rom remainder)
else if (address >= 60 && address <= 63) begin
if (address == 60 && return != { 8'b0, REVISION[7:0] }) begin
$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
end
else if (address == 61 && return != { 8'b0, UNIPOLAR[7:0] }) begin
$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
end
else if (address == 62 && return != { 8'b0, CHANNELS[7:0] }) begin
$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
end
else if (address == 63 && return != { 8'b0, ID[7:0] }) begin
$display("!TEST FAILED! ROM %d read returned incorrect value %b", address, return);
end
address = address + 1;
end
end
end
endtask
////// initialization //////
reg [7:0] t = 16'd0;
initial begin
// iverilog boilerplate
$dumpfile("test.vcd");
$dumpvars(0, rhd2000_dm_tb); // tb module name
// controls
nCs <= 1;
mosi <= 0;
sclk <= 0;
// generate tags for each adc channel
// channel 0 will contain data 16'd1, 1 -> 16'd2, etc...
t = 16'd0;
repeat (33) begin
analog[(t - 1) * 16 +: 16] <= t;
#1;
t = t + 16'd1;
#1;
end
end
////// Main //////
always begin
$display("#--- STARTING ---# Testbench for Intan RHD2000 Data Model...");
#`STARTDELAY;
testConvert;
testCalibration;
testReadWrite;
$display("#--- FINISHED ---# RHD2000 Data Model.");
$finish;
end
endmodule |
#include <bits/stdc++.h> using namespace std; int n, q; int m; int lastans; int a[1000][700]; int b[100100]; int sz[1000]; short int cnt[1000][100100]; void remake() { int pos = 0; for (int i = 0; i <= m; i++) { sz[i] = 0; for (int j = 0; j < 700; a[i][j] = 0, j++) { if (a[i][j] == -1 || a[i][j] == 0) continue; cnt[i][a[i][j]]--; b[pos] = a[i][j]; pos++; } } for (int i = 0; i < n; i++) { a[i / 333][i % 333] = b[i]; cnt[i / 333][b[i]]++; sz[i / 333]++; } } int find(int it, int pos) { int i = 0; pos--; while (pos || a[it][i] == -1) { if (a[it][i] == -1) pos++; pos--; i++; } int res = a[it][i]; a[it][i] = -1; return res; } void update(int it, int pos, int k) { pos--; int t = sz[it] - pos; int i = 0; while (pos || a[it][i] == -1) { if (a[it][i] == -1) pos++; pos--; i++; } int buf = a[it][i]; a[it][i] = k; while (t) { i++; if (buf != -1) t--; swap(a[it][i], buf); } } int solve(int r, int k) { int res = 0; int pos = 0; int it = 0; while (it <= m && sz[it] <= r) { r -= sz[it]; res += cnt[it][k]; it++; } int i = 0; while (pos < r) { if (a[it][i] == -1 || a[it][i] == 0) { i++; continue; } res += (a[it][i] == k); i++; pos++; } return res; } int main() { ios_base::sync_with_stdio(0); cin >> n; for (int i = 0; i < n; i++) { cin >> a[i / 333][i % 333]; cnt[i / 333][a[i / 333][i % 333]]++; sz[i / 333]++; } m = (n - 1) / 333 + 1; cin >> q; while (q--) { int type, l, r, k; cin >> type >> l >> r; l = (l + lastans - 1) % n + 1; r = (r + lastans - 1) % n + 1; if (l > r) swap(l, r); if (type == 1) { int it = 0; int pos = 0; while (pos < l) { pos += sz[it]; it++; } if (pos >= l) { it--; pos -= sz[it]; } int p1 = pos; int w = it; it = 0; pos = 0; while (pos < r) { pos += sz[it]; it++; } if (pos >= r) { it--; pos -= sz[it]; } k = find(it, r - pos); cnt[w][k]++; cnt[it][k]--; sz[w]++; sz[it]--; update(w, l - p1, k); if (sz[w] > 2 * 333) remake(); } else { cin >> k; k = (k + lastans - 1) % n + 1; lastans = solve(r, k) - solve(l - 1, k); printf( %d n , lastans); } } } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x6fffffff; const int MINF = 0x80000000; const long long mod = 1000000007; const int cons = 100001; const double pi = 3.141592653589793; vector<int> pos; bool isOk(int x, int t) { double res = 0; for (int i = 1; i < pos.size(); i++) { int diff = pos[i] - pos[i - 1]; int l = -1; int r = x + 1; while (l + 1 < r) { int mid = l + r >> 1; int y = x - mid; double avail = (double)y / 2 + mid; if (avail >= (double)diff) r = mid; else l = mid; } if (r == x + 1) return false; diff -= r; res += (double)r * 2; res += min((double)diff, ((double)x - r) / 2); } return res <= (double)t; } int main() { int n, k, s, t; cin >> n >> k >> s >> t; map<int, int> M; for (int i = 0; i < n; i++) { int c, v; scanf( %d%d , &c, &v); M[c] = max(M[c], v); } int cur = 0; vector<pair<int, int> > dat; for (auto it : M) { if (cur < it.second) { cur = it.second; dat.push_back(it); } } pos.resize(k); for (int i = 0; i < k; i++) { scanf( %d , &pos[i]); } pos.push_back(0); pos.push_back(s); sort(pos.begin(), pos.end()); int L = -1; int R = dat.size(); while (L + 1 < R) { int mid = L + R >> 1; if (isOk(dat[mid].second, t)) R = mid; else L = mid; } if (R == dat.size()) puts( -1 ); else printf( %d n , dat[R].first); return 0; } |
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: gsu_mult.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module gsu_mult (
dataa,
datab,
result);
input [7:0] dataa;
input [7:0] datab;
output [15:0] result;
wire [15:0] sub_wire0;
wire [15:0] result = sub_wire0[15:0];
lpm_mult lpm_mult_component (
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 8,
lpm_mult_component.lpm_widthb = 8,
lpm_mult_component.lpm_widthp = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "8"
// Retrieval info: PRIVATE: WidthB NUMERIC "8"
// Retrieval info: PRIVATE: WidthP NUMERIC "16"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "16"
// Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL "dataa[7..0]"
// Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL "datab[7..0]"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
// Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_mult.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_mult.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_mult.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_mult.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_mult_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gsu_mult_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
#include <bits/stdc++.h> using namespace std; int main() { int n, m; cin >> n >> m; long long ans = 0; for (int i = (0); i < (n); ++i) { long long t, T, x, cost; cin >> t >> T >> x >> cost; if (t >= T) { ans += cost + m * x; continue; } long long aux1 = cost; if (m > (T - t)) aux1 += m * x; long long aux2 = (long long)ceil((double)(m - (T - t)) / (T - t)) + 1; aux2 *= cost; ans += min(aux1, aux2); } cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(false); unsigned long long c = 0; short p; int n; cin >> n; for (int i = 0; i < n; i++) { cin >> p; c += p; } cout << setprecision(14) << ((double)c / n); } |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/17.0std/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_clock_crosser.v $
// $Revision: #1 $
// $Date: 2017/01/22 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_clock_crosser(
in_clk,
in_reset,
in_ready,
in_valid,
in_data,
out_clk,
out_reset,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter FORWARD_SYNC_DEPTH = 2;
parameter BACKWARD_SYNC_DEPTH = 2;
parameter USE_OUTPUT_PIPELINE = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input in_clk;
input in_reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_clk;
input out_reset;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
// Data is guaranteed valid by control signal clock crossing. Cut data
// buffer false path.
(* altera_attribute = {"-name SUPPRESS_DA_RULE_INTERNAL \"D101,D102\""} *) reg [DATA_WIDTH-1:0] in_data_buffer;
reg [DATA_WIDTH-1:0] out_data_buffer;
reg in_data_toggle;
wire in_data_toggle_returned;
wire out_data_toggle;
reg out_data_toggle_flopped;
wire take_in_data;
wire out_data_taken;
wire out_valid_internal;
wire out_ready_internal;
assign in_ready = ~(in_data_toggle_returned ^ in_data_toggle);
assign take_in_data = in_valid & in_ready;
assign out_valid_internal = out_data_toggle ^ out_data_toggle_flopped;
assign out_data_taken = out_ready_internal & out_valid_internal;
always @(posedge in_clk or posedge in_reset) begin
if (in_reset) begin
in_data_buffer <= {DATA_WIDTH{1'b0}};
in_data_toggle <= 1'b0;
end else begin
if (take_in_data) begin
in_data_toggle <= ~in_data_toggle;
in_data_buffer <= in_data;
end
end //in_reset
end //in_clk always block
always @(posedge out_clk or posedge out_reset) begin
if (out_reset) begin
out_data_toggle_flopped <= 1'b0;
out_data_buffer <= {DATA_WIDTH{1'b0}};
end else begin
out_data_buffer <= in_data_buffer;
if (out_data_taken) begin
out_data_toggle_flopped <= out_data_toggle;
end
end //end if
end //out_clk always block
altera_std_synchronizer_nocut #(.depth(FORWARD_SYNC_DEPTH)) in_to_out_synchronizer (
.clk(out_clk),
.reset_n(~out_reset),
.din(in_data_toggle),
.dout(out_data_toggle)
);
altera_std_synchronizer_nocut #(.depth(BACKWARD_SYNC_DEPTH)) out_to_in_synchronizer (
.clk(in_clk),
.reset_n(~in_reset),
.din(out_data_toggle_flopped),
.dout(in_data_toggle_returned)
);
generate if (USE_OUTPUT_PIPELINE == 1) begin
altera_avalon_st_pipeline_base
#(
.BITS_PER_SYMBOL(BITS_PER_SYMBOL),
.SYMBOLS_PER_BEAT(SYMBOLS_PER_BEAT)
) output_stage (
.clk(out_clk),
.reset(out_reset),
.in_ready(out_ready_internal),
.in_valid(out_valid_internal),
.in_data(out_data_buffer),
.out_ready(out_ready),
.out_valid(out_valid),
.out_data(out_data)
);
end else begin
assign out_valid = out_valid_internal;
assign out_ready_internal = out_ready;
assign out_data = out_data_buffer;
end
endgenerate
endmodule
|
#include <bits/stdc++.h> using namespace std; long long modpow(long long a, long long b, long long m = 1000000007) { a %= m; long long res = 1; while (b) { if (b & 1) res = res * a % m; a = a * a % m; b >>= 1; } return res; } long long bpow(long long a, long long b) { long long res = 1; while (b) { if (b & 1) res = res * a; a = a * a; b >>= 1; } return res; } long long modinv(long long a) { return modpow(a, 1000000007 - 2, 1000000007); } void graph(vector<vector<long long> > &adj, long long m) { long long x, y; for (long long i = 0; i < m; i++) { cin >> x >> y; adj[x - 1].push_back(y - 1); adj[y - 1].push_back(x - 1); } } const int mxN = 2e5 + 5; void solve() { int n; cin >> n; string s; cin >> s; set<int> color[26]; std::vector<int> out(n); for (long long i = 0; i < s.size(); i++) { int x = s[i] - a ; for (long long j = 1; j <= 26; j++) { bool ok = true; for (long long k = x + 1; k < 26; k++) { ok &= !(color[k].count(j)); } if (ok) { color[x].insert(j); out[i] = j; break; } } } set<int> distinct; for (auto &k : out) distinct.insert(k); cout << distinct.size() << n ; for (auto &k : out) cout << k << ; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; while (t--) { solve(); } } |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:10:17 05/08/2017
// Design Name: axi_spi_if
// Module Name: D:/Projects/Rendszerarch/axi_spi_master_if/axi_spi/axi_spi_test.v
// Project Name: axi_spi
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: axi_spi_if
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module axi_spi_test;
// Inputs
reg clk_i;
reg reset_n_i;
reg awvalid_i;
reg [27:0] awaddr_i;
reg awprot_i;
reg wvalid_i;
reg [31:0] wdata_i;
reg [3:0] wstrb_i;
reg bready_i;
reg arvalid_i;
reg [27:0] araddr_i;
reg [2:0] arprot_i;
reg rready_i;
reg spi_miso_i;
// Outputs
wire awready_o;
wire wready_o;
wire bvalid_o;
wire [1:0] bresp_o;
wire arready_o;
wire rvalid_o;
wire [31:0] rdata_o;
wire [1:0] rresp_o;
wire [3:0] spi_ssel_o;
wire spi_sck_o;
wire spi_mosi_o;
// Instantiate the Unit Under Test (UUT)
axi_spi_if uut (
.clk_i(clk_i),
.reset_n_i(reset_n_i),
.awvalid_i(awvalid_i),
.awready_o(awready_o),
.awaddr_i(awaddr_i),
.awprot_i(awprot_i),
.wvalid_i(wvalid_i),
.wready_o(wready_o),
.wdata_i(wdata_i),
.wstrb_i(wstrb_i),
.bvalid_o(bvalid_o),
.bready_i(bready_i),
.bresp_o(bresp_o),
.arvalid_i(arvalid_i),
.arready_o(arready_o),
.araddr_i(araddr_i),
.arprot_i(arprot_i),
.rvalid_o(rvalid_o),
.rready_i(rready_i),
.rdata_o(rdata_o),
.rresp_o(rresp_o),
.spi_ssel_o(spi_ssel_o),
.spi_sck_o(spi_sck_o),
.spi_mosi_o(spi_mosi_o),
.spi_miso_i(spi_miso_i)
);
initial begin
// Initialize Inputs
clk_i = 0;
reset_n_i = 0;
awvalid_i = 0;
awaddr_i = 0;
awprot_i = 0;
wvalid_i = 0;
wdata_i = 0;
wstrb_i = 0;
bready_i = 0;
arvalid_i = 0;
araddr_i = 0;
arprot_i = 0;
rready_i = 0;
spi_miso_i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset_n_i = 1;
spi_miso_i = 1;
/*
reg_control_i = 32'h0000_0602;
reg_trans_ctrl_i = 32'h0000_0002;
*/
wdata_i = 32'h0000_0602;
awaddr_i = 0;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#1000;
wdata_i = 32'h0000_0002;
awaddr_i = 1;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
wdata_i = 32'h0000_0073;
awaddr_i = 3;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
wdata_i = 32'h0000_0073;
awaddr_i = 4;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
end
always #5 clk_i = ~clk_i;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_16_V
`define SKY130_FD_SC_HDLL__CLKINV_16_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_16_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2010 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 3-State Differential Signaling Output Buffer
// /___/ /\ Filename : OBUFTDS_DCIEN.v
// \ \ / \ Timestamp : Thu Apr 29 14:59:30 PDT 2010
// \___\/\___\
//
// Revision:
// 04/29/10 - Initial version.
// 12/20/10 - CR 587760 -- For backend support only, no corresponding unisim
// 06/10/11 - CR 584500 - added attribute SLEW
// 09/20/11 - CR 625725 -- Removed attribute CAPACITANCE
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OBUFTDS_DCIEN (O, OB, DCITERMDISABLE, I, T);
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif // `ifdef XIL_TIMING
parameter SLEW = "SLOW";
output O;
output OB;
input DCITERMDISABLE;
input I;
input T;
wire ts;
tri0 GTS = glbl.GTS;
or O1 (ts, GTS, T);
bufif0 B1 (O, I, ts);
notif0 N1 (OB, I, ts);
`ifdef XIL_TIMING
specify
(DCITERMDISABLE => O) = (0:0:0, 0:0:0);
(DCITERMDISABLE => OB) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
(I => OB) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
(T => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule
`endcelldefine
|
#include <bits/stdc++.h> using namespace std; inline void Boost() { ios::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); } const long double eps = 1e-10; int main() { Boost(); int n; cin >> n; vector<long double> A(n), B(n); for (auto &x : A) cin >> x; for (auto &x : B) cin >> x; long double lo = 0; long double hi = 1000000000; long double best = 0; while (hi - lo > eps) { long double mid = (lo + hi) / 2.0; pair<long double, long double> inter = {A[0] - mid * B[0], A[0] + mid * B[0]}; for (int i = 1; i < n; ++i) { pair<long double, long double> temp = {A[i] - mid * B[i], A[i] + mid * B[i]}; inter.first = max(inter.first, temp.first); inter.second = min(inter.second, temp.second); } if (inter.first <= inter.second) { best = mid; hi = mid; } else { lo = mid; } } cout << fixed << setprecision(10) << best; return 0; } |
#include <bits/stdc++.h> using namespace std; int a[5]; bool able[5]; int main() { int T; scanf( %d , &T); while (T--) { for (int i = 1; i <= 4; i++) able[i] = true; bool flag = true; for (int i = 1; i <= 4; i++) scanf( %d , &a[i]); if ((a[1] + a[2]) % 2 == 1) flag = false; if (flag) { able[1] = able[2] = false; if (a[4] == 0 && a[1] == 0) able[4] = false; if (a[2] == 0 && a[3] == 0) able[3] = false; } else { able[3] = able[4] = false; if (a[4] == 0 && a[1] == 0) able[1] = false; if (a[2] == 0 && a[3] == 0) able[2] = false; } for (int i = 1; i <= 4; i++) { if (able[i]) printf( Ya ); else printf( Tidak ); } puts( ); } return 0; } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O41A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__O41A_BEHAVIORAL_PP_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o41a (
VPWR,
VGND,
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1
);
// Module ports
input VPWR;
input VGND;
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
// Local signals
wire A4 or0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O41A_BEHAVIORAL_PP_V |
/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "DeepGATE_include.v"
module DeepGATE_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output wire [7:0]led,
// Raspberry Pi Interface
input RaspberrySPI_SS,
input RaspberrySPI_SCLK,
input RaspberrySPI_MOSI,
output reg RaspberrySPI_MISO,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
//SDRAM interface
output sdram_clk,
output sdram_cle,
output sdram_dqm,
output sdram_cs,
output sdram_we,
output sdram_cas,
output sdram_ras,
output [1:0] sdram_ba,
output [12:0] sdram_a,
inout [7:0] sdram_dq
);
`include "networkParam_include.v"
wire rst = ~rst_n; //becomes active high
wire [7:0] tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire new_rx_data;
reg [7:0] tx_data_buffer = 0;
reg [7:0] rx_data_buffer = 0;
reg new_tx_data = 0;
avr_interface AVR (
.clk (clk),
.rst (rst),
.cclk (cclk),
.spi_miso (spi_miso),
.spi_mosi (spi_mosi),
.spi_sck (spi_sck),
.spi_ss (spi_ss),
.spi_channel (spi_channel),
.tx (avr_rx),
.rx (avr_tx),
.channel (4'd15),
.tx_data (tx_data),
.new_tx_data (new_tx_data),
.tx_busy (tx_busy),
.tx_block (avr_rx_busy),
.rx_data (rx_data),
.new_rx_data (new_rx_data)
);
wire [31:0] sdramDataOut;
wire [22:0] sdramAddr;
wire sdramBusy;
wire sdramOutValid;
reg [31:0] sdramDataIn;
reg sdramInValid;
reg sdramRW = 0;
sdram SDRAM (
.clk (clk),
.rst (rst),
// these signals go directly to the IO pins
.sdram_clk (sdram_clk),
.sdram_cle (sdram_cle),
.sdram_cs (sdram_cs),
.sdram_cas (sdram_cas),
.sdram_ras (sdram_ras),
.sdram_we (sdram_we),
.sdram_dqm (sdram_dqm),
.sdram_ba (sdram_ba),
.sdram_a (sdram_a),
.sdram_dq (sdram_dq),
// User interface
.addr (sdramAddr), // address to read/write
.rw (sdramRW), // 1 = write, 0 = read
.data_in (sdramDataIn), // data from a read
.data_out (sdramDataOut), // data for a write
.busy (sdramBusy), // controller is busy when high
.in_valid (sdramInValid), // pulse high to initiate a read/write
.out_valid (sdramOutValid) // pulses high when data from read is valid
);
wire [7:0] networkOut;
wire networkIdle;
wire networkDataReady;
wire [7:0] networkTestData;
reg [31:0] transferCnt = 0;
reg [7:0] testData = 0;
reg [7:0] networkAddr = 0;
reg procBegin = 0;
reg procBeginFlag = 0;
reg networkWriteEn = 0;
reg [7:0] networkDataIn = 0;
tileNetwork MLPNN( //multi-layer perceptron neural network
.clk (clk),
.procBegin (procBegin),
.dataIn (networkDataIn),
.wr (networkWriteEn),
.wr_addr (networkAddr),
.weightDataIn (48'hBABEFACEBABE),
.networkIdle (networkIdle),
.networkOut (networkOut),
.dataReady (networkDataReady)
);
reg start = 0;
reg transfer = 0;
reg dataSent = 0;
reg first = 0;
reg [22:0] readAddr = 0;
reg [22:0] writeAddr = 0;
reg [22:0] stopAddr = 0;
reg [23:0] command = 0;
reg [79:0] test_reg = 0;
reg [31:0] readCnt = 0;
reg [7:0] dataRAM [783 : 0];
reg [7:0] hold = 0;
//initial begin
//$readmemh("C:/Users/cedric/Documents/UCF/C Programs/DeepGateDataGeneration/DeepGateDataGeneration/randomNetworkData.txt", dataRAM);
//end
assign tx_data = !start ? tx_data_buffer : test_reg[7:0];
assign led = rx_data_buffer;
assign sdramAddr = !transfer ? writeAddr : readAddr;
always@(posedge clk) begin
sdramRW <= 0;
sdramInValid <= 0;
procBegin <= 0;
new_tx_data <= 0;
if(new_rx_data && !transfer) begin
writeAddr <= writeAddr + 1'b1;
rx_data_buffer <= rx_data;
dataRAM[writeAddr] <= rx_data;
command <= {command[15:0], rx_data};
end
else if(!tx_busy && !new_tx_data && (transfer || start)) begin
new_tx_data <= 1'b1;
readAddr <= readAddr + 1'b1;
tx_data_buffer <= dataRAM[readAddr];
end
if(writeAddr == 784) begin
writeAddr <= 0;
transfer <= 1;
end
if(readAddr == 784) begin
transfer <= 0;
readAddr <= 0;
end
if(transfer)
readCnt <= readCnt + 1'b1;
//if(sdramOutValid)
//tx_data_buffer <= sdramDataOut;
if(!sdramBusy && !sdramInValid) begin
if(!transfer) begin
sdramDataIn <= rx_data_buffer;
sdramRW <= 1;
end
sdramInValid <= 1;
end
/*
if(command == 24'h242424) begin //$$$ in ASCII
//transfer <= 1;
writeAddr <= 0;
stopAddr <= writeAddr;
command <= 0;
end
*/
if(command == 24'h262626) //&&& in ASCII
start <= 1;
if(networkDataReady)
test_reg <= {test_reg[71:0], networkOut};
else if(!networkDataReady && !tx_busy && !new_tx_data)
test_reg <= {test_reg[71:0], test_reg[79:72]} ;
if(start && networkIdle && !procBeginFlag) begin
procBegin <= 1;
procBeginFlag <= 1;
end
if(((procBeginFlag && !procBegin && transferCnt == 0) || (transferCnt > 0 && transferCnt < 784)) && !hold) begin
transferCnt <= transferCnt + 1'b1;
networkDataIn <= dataRAM[transferCnt];
end
if(transferCnt == 784) begin
hold <= hold + 1'b1;
if(hold == 10) begin
transferCnt <= 0;
hold <= 0;
end
end
end
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 23512 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w1024,
w1023,
w2048,
w3071,
w32,
w33,
w132,
w2939,
w23512;
assign w1 = i_data0;
assign w1023 = w1024 - w1;
assign w1024 = w1 << 10;
assign w132 = w33 << 2;
assign w2048 = w1 << 11;
assign w23512 = w2939 << 3;
assign w2939 = w3071 - w132;
assign w3071 = w1023 + w2048;
assign w32 = w1 << 5;
assign w33 = w1 + w32;
assign o_data0 = w23512;
//multiplier_block area estimate = 6153.83997047941;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
#include <bits/stdc++.h> using namespace std; int n, m, k; string s; long long ans; bool flag; struct A { int id, p, s; }; bool comp(A a, A b) { if (a.p > b.p) return true; return false; } void solve() { cin >> n >> m >> k; vector<int> p(n); for (auto i = 0; i < n; i++) cin >> p[i]; ; vector<int> s(n); for (auto i = 0; i < n; i++) cin >> s[i]; ; vector<A> v(n); for (auto i = 0; i < n; i++) { v[i].id = i + 1; v[i].s = s[i]; v[i].p = p[i]; } sort(v.begin(), v.end(), comp); unordered_set<int> school; unordered_set<int> kid; for (auto i = 0; i < n; i++) { if (school.find(v[i].s) == school.end()) { school.insert(v[i].s); kid.insert(v[i].id); } int mm = school.size(); if (mm == m) break; } vector<int> K(k); for (auto i = 0; i < k; i++) cin >> K[i]; ; int count = 0; for (auto i = 0; i < k; i++) { if (kid.find(K[i]) == kid.end()) { count++; } } cout << count; } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); int t = 1; while (t--) { solve(); } return 0; } |
#include <bits/stdc++.h> using namespace std; int x[4]; int y[4]; int newx[4]; int newy[4]; int T; int get() { int answ = INT_MAX; for (auto y1 : y) for (auto y2 : y) { int delta = abs(y1 - y2); if (delta == 0) continue; set<int> s; for (auto x1 : x) for (auto x2 : x) for (auto d : {0, -delta, -2 * delta, 1, -delta + 1, -2 * delta + 1}) s.insert((x1 + x2 + d) / 2); for (auto x1 : s) { int p[4] = {3, 2, 1, 0}; for (int ori = 0; ori < 24; ori++) { next_permutation(p, p + 4); int xs[4] = {x1, x1, x1 + delta, x1 + delta}; int ys[4] = {y1, y2, y1, y2}; bool flag = false; for (int i = 0; i < 4; i++) if (xs[i] != x[p[i]] && ys[i] != y[p[i]]) { flag = true; } if (flag) continue; int t = 0; for (int i = 0; i < 4; i++) t = max(t, abs(xs[i] - x[p[i]]) + abs(ys[i] - y[p[i]])); if (answ > t) { answ = t; for (int i = 0; i < 4; i++) { newx[p[i]] = xs[i]; newy[p[i]] = ys[i]; } } } } } return answ; } int boom = 1e9; int main() { scanf( %d , &T); while (T--) { for (int i = 0; i < 4; i++) { scanf( %d%d , &x[i], &y[i]); x[i] = x[i] + boom; y[i] = y[i] + boom; } int t1 = get(); swap(x, y); swap(newx, newy); int t2 = get(); swap(x, y); swap(newx, newy); if (t1 < t2) get(); if (min(t1, t2) == INT_MAX) { puts( -1 ); } else { printf( %d n , min(t1, t2)); for (int i = 0; i < 4; i++) printf( %d %d n , newx[i] - boom, newy[i] - boom); } } return 0; } |
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// read_rs1 O 64
// read_rs1_port2 O 64
// read_rs2 O 64
// CLK I 1 clock
// RST_N I 1 reset
// read_rs1_rs1 I 5
// read_rs1_port2_rs1 I 5
// read_rs2_rs2 I 5
// write_rd_rd I 5
// write_rd_rd_val I 64 reg
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_write_rd I 1
//
// Combinational paths from inputs to outputs:
// read_rs1_rs1 -> read_rs1
// read_rs1_port2_rs1 -> read_rs1_port2
// read_rs2_rs2 -> read_rs2
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkGPR_RegFile(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
read_rs1_rs1,
read_rs1,
read_rs1_port2_rs1,
read_rs1_port2,
read_rs2_rs2,
read_rs2,
write_rd_rd,
write_rd_rd_val,
EN_write_rd);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// value method read_rs1
input [4 : 0] read_rs1_rs1;
output [63 : 0] read_rs1;
// value method read_rs1_port2
input [4 : 0] read_rs1_port2_rs1;
output [63 : 0] read_rs1_port2;
// value method read_rs2
input [4 : 0] read_rs2_rs2;
output [63 : 0] read_rs2;
// action method write_rd
input [4 : 0] write_rd_rd;
input [63 : 0] write_rd_rd_val;
input EN_write_rd;
// signals for module outputs
wire [63 : 0] read_rs1, read_rs1_port2, read_rs2;
wire RDY_server_reset_request_put, RDY_server_reset_response_get;
// register rg_state
reg [1 : 0] rg_state;
reg [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule regfile
wire [63 : 0] regfile$D_IN,
regfile$D_OUT_1,
regfile$D_OUT_2,
regfile$D_OUT_3;
wire [4 : 0] regfile$ADDR_1,
regfile$ADDR_2,
regfile$ADDR_3,
regfile$ADDR_4,
regfile$ADDR_5,
regfile$ADDR_IN;
wire regfile$WE;
// rule scheduling signals
wire CAN_FIRE_RL_rl_reset_loop,
CAN_FIRE_RL_rl_reset_start,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_write_rd,
WILL_FIRE_RL_rl_reset_loop,
WILL_FIRE_RL_rl_reset_start,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_write_rd;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_rsps$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_rsps$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
rg_state == 2'd2 && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// value method read_rs1
assign read_rs1 = (read_rs1_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_3 ;
// value method read_rs1_port2
assign read_rs1_port2 =
(read_rs1_port2_rs1 == 5'd0) ? 64'd0 : regfile$D_OUT_2 ;
// value method read_rs2
assign read_rs2 = (read_rs2_rs2 == 5'd0) ? 64'd0 : regfile$D_OUT_1 ;
// action method write_rd
assign CAN_FIRE_write_rd = 1'd1 ;
assign WILL_FIRE_write_rd = EN_write_rd ;
// submodule f_reset_rsps
FIFO20 #(.guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule regfile
RegFile #(.addr_width(32'd5),
.data_width(32'd64),
.lo(5'h0),
.hi(5'd31)) regfile(.CLK(CLK),
.ADDR_1(regfile$ADDR_1),
.ADDR_2(regfile$ADDR_2),
.ADDR_3(regfile$ADDR_3),
.ADDR_4(regfile$ADDR_4),
.ADDR_5(regfile$ADDR_5),
.ADDR_IN(regfile$ADDR_IN),
.D_IN(regfile$D_IN),
.WE(regfile$WE),
.D_OUT_1(regfile$D_OUT_1),
.D_OUT_2(regfile$D_OUT_2),
.D_OUT_3(regfile$D_OUT_3),
.D_OUT_4(),
.D_OUT_5());
// rule RL_rl_reset_start
assign CAN_FIRE_RL_rl_reset_start = rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_reset_start = rg_state == 2'd0 ;
// rule RL_rl_reset_loop
assign CAN_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ;
assign WILL_FIRE_RL_rl_reset_loop = rg_state == 2'd1 ;
// register rg_state
always@(EN_server_reset_request_put or
WILL_FIRE_RL_rl_reset_loop or WILL_FIRE_RL_rl_reset_start)
case (1'b1)
EN_server_reset_request_put: rg_state$D_IN = 2'd0;
WILL_FIRE_RL_rl_reset_loop: rg_state$D_IN = 2'd2;
WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 2'd1;
default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign rg_state$EN =
EN_server_reset_request_put || WILL_FIRE_RL_rl_reset_start ||
WILL_FIRE_RL_rl_reset_loop ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = EN_server_reset_request_put ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule regfile
assign regfile$ADDR_1 = read_rs2_rs2 ;
assign regfile$ADDR_2 = read_rs1_port2_rs1 ;
assign regfile$ADDR_3 = read_rs1_rs1 ;
assign regfile$ADDR_4 = 5'h0 ;
assign regfile$ADDR_5 = 5'h0 ;
assign regfile$ADDR_IN = write_rd_rd ;
assign regfile$D_IN = write_rd_rd_val ;
assign regfile$WE = EN_write_rd && write_rd_rd != 5'd0 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_state = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkGPR_RegFile
|
#include <bits/stdc++.h> using namespace std; const int maxn = 200000 + 10; long long n, T, a[maxn], x, y, t1, t2, k; long long b[maxn]; long long cmp(long long x, long long y) { return x > y; } long long cmp1(long long x, long long y) { return x > y; } long long check(long long len) { for (long long i = 1; i <= len; i++) { if (i % t1 == 0 && i % t2 == 0) b[i] = x + y; else if (i % t1 == 0) b[i] = x; else if (i % t2 == 0) b[i] = y; } sort(b + 1, b + 1 + len, cmp1); long long ans = 0; for (long long i = 1; i <= len; i++) { ans += b[i] * a[i]; } if (ans >= k) return 1; return 0; } int main() { cin >> T; while (T--) { cin >> n; for (long long i = 1; i <= n; i++) cin >> a[i]; sort(a + 1, a + 1 + n, cmp); cin >> x >> t1 >> y >> t2 >> k; k *= 100; long long l = 0, r = n, ans = 0x7f7f7f7f; while (l <= r) { long long mid = (l + r) / 2; memset(b, 0, sizeof(b)); if (check(mid)) { r = mid - 1; ans = mid; } else { l = mid + 1; } } if (ans == 0x7f7f7f7f) cout << -1 << endl; else cout << ans << endl; } } |
#include <bits/stdc++.h> using namespace std; const int INF = 0x3f3f3f3f; const double eps = 1e-6; const int MAXN = 1e5 + 10; const int MAXM = 1e6 + 10; const long long mod = 1e9 + 7; int a[1010]; int main() { int n; scanf( %d , &n); for (int i = 0; i < n; i++) scanf( %d , &a[i]); int ans = 0; for (int i = 1; i < n - 1; i++) { if (a[i] > a[i - 1] && a[i] > a[i + 1]) ans++; if (a[i] < a[i - 1] && a[i] < a[i + 1]) ans++; } printf( %d n , ans); return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0), cin.tie(0); int t; cin >> t; while (t--) { int n, m, k; cin >> n >> m >> k; vector<int> deg(n); vector<vector<int>> adj(n); for (int i = 0, u, v; i < m; ++i) { cin >> u >> v; --u, --v; adj[u].push_back(v); adj[v].push_back(u); ++deg[u], ++deg[v]; } deque<int> q; for (int i = 0; i < n; ++i) { sort(adj[i].begin(), adj[i].end()); if (deg[i] == k - 1) q.push_back(i); if (deg[i] < k - 1) q.push_front(i); } vector<int> ans; vector<bool> mp(n); while (!q.empty()) { int u = q.front(); q.pop_front(); if (deg[u] == -1) continue; if (deg[u] == k - 1) { vector<int> &c = ans; for (auto v : adj[u]) if (deg[v] != -1) { c.push_back(v); mp[v] = true; } c.insert(upper_bound(c.begin(), c.end(), u), u); mp[u] = true; bool ok = true; for (auto &i : c) { if (adj[i].size() <= 3 * c.size()) { int cnt = 0; for (auto j : adj[i]) cnt += mp[j]; if (cnt != k - 1) { ok = false; break; } } else { for (size_t j = &i - &c[0]; ++j < c.size();) { auto it = lower_bound(adj[i].begin(), adj[i].end(), c[j]); if (it == adj[i].end() || *it != c[j]) { ok = false; break; } } } } if (ok) break; for (auto i : c) mp[i] = false; c.clear(); } deg[u] = -1; for (auto v : adj[u]) if (deg[v] != -1) { if (deg[v] == k - 1) q.push_front(v); if (deg[v] == k) q.push_back(v); --deg[v]; } } if (ans.empty()) { for (int i = 0; i < n; ++i) if (deg[i] != -1) ans.push_back(i); if (!ans.empty()) { cout << 1 << ans.size() << n ; for (auto &i : ans) cout << i + 1 << n [&i == &ans.back()]; } else cout << -1 n ; } else { cout << 2 n ; for (auto &i : ans) cout << i + 1 << n [&i == &ans.back()]; } } return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/24/2016 03:50:03 PM
// Design Name:
// Module Name: Problem4
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Problem4(
input A,
input B,
input GTI,
input LTI,
input EQI,
output reg GTO,
output reg LTO,
output reg EQO
);
always @ (A or B or GTI or LTI or EQI) // sensitivity list
begin
if ( A > B )
begin
GTO = 1;
LTO = 0;
EQO = 0;
end
else if ( A < B ) // Change value to Less than
begin
LTO = 1;
GTO = 0;
EQO = 0;
end
else // Stay the Same
begin
EQO = EQI;
GTO = GTI;
LTO = LTI;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [19:10] bitout;
wire [29:24] short_bitout;
wire [7:0] allbits;
wire [15:0] twobits;
sub
i_sub1 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14])),
i_sub2 [3:0] (.allbits (allbits),
.twobits (twobits[7:0]),
.bitout (bitout[13:10]));
sub
i_sub3 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14]));
sub
i_sub4 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (short_bitout[27:24]));
sub
i_sub5 [7:0] (.allbits (allbits),
.twobits (twobits),
.bitout (bitout[17:10]));
sub
i_sub6 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout ({bitout[18+:2],short_bitout[28+:2]}));
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Signals under test
assign allbits = crc[7:0];
assign twobits = crc[15:0];
wire [63:0] result = {48'h0, short_bitout, bitout};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha1da9ff8082a4ff6
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule // t
module sub
( input wire [7:0] allbits,
input wire [1:0] twobits,
output wire bitout);
assign bitout = (^ twobits) ^ (^ allbits);
endmodule // sub
|
#include <bits/stdc++.h> using namespace std; int main() { int l, p, q; cin >> l >> p >> q; double ans; ans = (double)l * p / ((p + q)); cout << ans << endl; return 0; } |
#include <bits/stdc++.h> using namespace std; int main() { ios_base::sync_with_stdio(0); cin.tie(0); cout.tie(0); int h, m, s, t1, t2; cin >> h >> m >> s >> t1 >> t2; h %= 12; t1 %= 12; t2 %= 12; m /= 5; s /= 5; if (t1 > t2) swap(t1, t2); if (((h >= t1 && h < t2) + (m >= t1 && m < t2) + (s >= t1 && s < t2)) % 3 == 0) { cout << YES ; } else cout << NO ; cout << endl; return 0; } |
///////////////////////////////////////////////////////////////////////////////
// $Id: ethernet_parser_64bit.v 2201 2007-08-21 06:52:51Z jnaous $
//
// Module: ethernet_parser_64bit.v
// Project: NF2.1
// Description: parses the Ethernet header for a 64 bit datapath
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module ethernet_parser_64bit
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter NUM_IQ_BITS = 3,
parameter INPUT_ARBITER_STAGE_NUM = 2
)
(// --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
// --- Interface to output_port_lookup
output reg [47:0] dst_mac,
output reg [47:0] src_mac,
output reg [15:0] ethertype,
output reg eth_done,
output reg [NUM_IQ_BITS-1:0] src_port,
// --- Misc
input reset,
input clk
);
// ------------ Internal Params --------
parameter NUM_STATES = 3;
parameter READ_WORD_1 = 1;
parameter READ_WORD_2 = 2;
parameter WAIT_EOP = 4;
// ------------- Regs/ wires -----------
reg [NUM_STATES-1:0] state;
reg [NUM_STATES-1:0] state_next;
reg [47:0] dst_mac_next;
reg [47:0] src_mac_next;
reg [15:0] ethertype_next;
reg eth_done_next;
reg [NUM_IQ_BITS-1:0] src_port_next;
// ------------ Logic ----------------
always @(*) begin
dst_mac_next = dst_mac;
src_mac_next = src_mac;
ethertype_next = ethertype;
eth_done_next = eth_done;
src_port_next = src_port;
state_next = state;
case(state)
/* read the input source header and get the first word */
READ_WORD_1: begin
if(in_wr && in_ctrl==`IO_QUEUE_STAGE_NUM) begin
src_port_next = in_data[`IOQ_SRC_PORT_POS + NUM_IQ_BITS - 1 : `IOQ_SRC_PORT_POS];
end
else if(in_wr && in_ctrl==0) begin
dst_mac_next = in_data[63:16] ;
src_mac_next[47:32] = in_data[15:0];
state_next = READ_WORD_2;
end
end // case: READ_WORD_1
READ_WORD_2: begin
if(in_wr) begin
src_mac_next [31:0] = in_data[63:32];
ethertype_next = in_data[31:16];
state_next = WAIT_EOP;
eth_done_next = 1;
end
end
WAIT_EOP: begin
if(in_wr && in_ctrl!=0) begin
eth_done_next = 0;
state_next = READ_WORD_1;
end
end
endcase // case(state)
end // always @ (*)
always @(posedge clk) begin
if(reset) begin
src_mac <= 0;
dst_mac <= 0;
ethertype <= 0;
eth_done <= 0;
state <= READ_WORD_1;
src_port <= 0;
end
else begin
src_mac <= src_mac_next;
dst_mac <= dst_mac_next;
ethertype <= ethertype_next;
eth_done <= eth_done_next;
state <= state_next;
src_port <= src_port_next;
end // else: !if(reset)
end // always @ (posedge clk)
endmodule // ethernet_parser_64bit
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// sound_main is the main sound module: it incorporates data storage (512b memory), from which
// it reads data, prepares it through sound_mulacc and sends to sound_dac. It incorporates in itself
// sound_dac, so it has outs to the DAC.
// clock is ordinary 24 MHz clock, mode_8chans is asynchronous input signal controlling mode of operation,
// either 4 or 8 channels.
//
// channels in 4 channel mode (mode_8chans=0,mode_pan4ch=0)
// 1,2 -> left
// 3,4 -> right
// channels in 8 channel mode (mode_8chans=1,mode_pan4ch=0)
// 1,2,5,6 -> left
// 3,4,7,8 -> right
// channels in panning 4 channel mode (mode_8chans=0,mode_pan4ch=1)
// 1,2,3,4 (vols 1,2,5,6) -> left
// 1,2,3,4 (vols 3,4,7,8) -> right
// channels in mem are at addressed 0-7 (corresponding to channels 1-8, respectively).
// mem contains volumes (lower 6 bits, 0-zero volume, 63-max volume) and sound data (signed value with sign inverted:
// -data in mem---+----value--
// $FF | +$7F
// $81 | +$01
// $80 | +$00
// $7F | -$01 (or $FF)
// $01 | -$7F (or $81)
// $00 | -$80 (or $80)
// alternatively, it could be treated as unsigned positive samples with middle point of $7F-$80.
//
// inv7b causes 7th bit inversion: samples become signed
//
// clock ``\__/``\__/``\__/``\__/``\__/``\__/``\__/``\__
// mem_read ______/`````\__________________________________
// mem_wraddr | no | |addr |
// mem_di |write| |data |
// mem_***_we ______|here!|_____/`````\______________________
// ^-- data written here!
module sound_main(
clock, // system clock (24 MHz)
mode_8chans, // =1 - 8 channels, =0 - 4 channels
mode_pan4ch, // =1 - 4 channels with panning
mode_inv7b, // =1 - invert 7th bit of every sample byte
in_wrtoggle, // from ports.v module (async to clock)
in_datnvol, //
in_wraddr, //
in_data, //
dac_clock, // output to DAC
dac_leftright, // output to DAC
dac_data // output to DAC
);
// input-output description
input clock;
input mode_8chans;
input mode_pan4ch;
input mode_inv7b;
input in_wrtoggle;
input in_datnvol;
input [2:0] in_wraddr;
input [7:0] in_data;
output dac_clock;
output dac_leftright;
output dac_data;
// internal regs/wires
reg mem_read; // write to mem is forbidden while mem_read=1
reg datnvol;
reg [5:0] vol; // temporary storage for volume
reg mem_we; // write strobe
reg wrtgl1, wrtgl2, wrtgl3; // sync in and edge detect of in_wrtoggle
reg do_write; // indicates that write should be performed
reg [2:0] bf_wraddr;
reg [7:0] bf_data;
reg bf_datnvol;
wire dac_load; // signal from sound_dac module (when it loads new data)
wire [15:0] dac_pardata; // parallel data from sound_mulacc to sound_dac
reg mulacc_load; // load to sound_mulacc
reg mulacc_clrsum; // clr_sum to sound_mulacc
wire mulacc_ready; // ready from sound_mulacc
wire [7:0] mem_do; // data output of DAT or VOL
reg [8:0] mem_rdaddr; // read address for both memory blocks
reg int_mode_8chans; // internal and sync-in mode_8chans signals
reg sync_mode_8chans; //
reg int_mode_pan4ch,sync_mode_pan4ch; // same for pan4ch signal
reg int_mode_inv7b, sync_mode_inv7b; // ...
reg [1:0] chanptr; // pointer to channels (4 channels total: 0,1,4,5 or 2,3,6,7 depending on lrptr state)
reg lrptr; // left-right pointer (selects either left (0) or right (1) channels)
reg [2:0] cur_st,nxt_st;
// instantiating modules
sound_dac my_dac( .clock(clock),
.dac_clock(dac_clock),
.dac_leftright(dac_leftright),
.dac_data(dac_data),
.load(dac_load),
.datain(dac_pardata) );
sound_mulacc my_mulacc( .clock(clock),
.vol_in(vol),
.dat_in(mem_do),
.mode_inv7b(int_mode_inv7b),
.load(mulacc_load),
.clr_sum(mulacc_clrsum),
.ready(mulacc_ready),
.sum_out(dac_pardata) );
// DAT-VOL memory block
mem512b my_mem( .clk(clock),
.re(1'b1),
.rdaddr(mem_rdaddr),
.dataout(mem_do),
.wraddr({5'b0,bf_datnvol,bf_wraddr}),
.datain(bf_data),
.we(mem_we) );
// syncing in asynchronous control signals
always @(posedge clock)
begin
{ int_mode_8chans,sync_mode_8chans } <= { sync_mode_8chans, mode_8chans };
{ int_mode_pan4ch,sync_mode_pan4ch } <= { sync_mode_pan4ch, mode_pan4ch };
{ int_mode_inv7b ,sync_mode_inv7b } <= { sync_mode_inv7b, mode_inv7b };
end
// load lrptr (left-right pointer) on dac_load pulse
always @(posedge clock)
begin
if( dac_load )
lrptr <= ~dac_leftright;
end
// make memory read address from chanptr and lrptr
always @*
begin
/* mem_rdaddr[8:4] <= 5'd0;
mem_rdaddr[3] <= datnvol;
mem_rdaddr[2] <= int_mode_8chans ? chanptr[1] : 1'b0;
mem_rdaddr[1] <= lrptr;
mem_rdaddr[0] <= chanptr[0];*/
mem_rdaddr[8:4] <= 5'd0;
if( int_mode_8chans )
begin
mem_rdaddr[3] <= datnvol;
mem_rdaddr[2] <= chanptr[1];
mem_rdaddr[1] <= lrptr;
mem_rdaddr[0] <= chanptr[0];
end
else if( int_mode_pan4ch )
begin
mem_rdaddr[3] <= datnvol;
if( datnvol ) // sample data
begin
mem_rdaddr[2] <= 1'b0;
mem_rdaddr[1] <= chanptr[1];
mem_rdaddr[0] <= chanptr[0];
end
else // !datnvol: volumes
begin
mem_rdaddr[2] <= chanptr[1]; // same as in 8 channel
mem_rdaddr[1] <= lrptr;
mem_rdaddr[0] <= chanptr[0];
end
end
else //normal 4 channel mode
begin
mem_rdaddr[3] <= datnvol;
mem_rdaddr[2] <= 1'b0;
mem_rdaddr[1] <= lrptr;
mem_rdaddr[0] <= chanptr[0];
end
end
// handle mulacc_clrsum signal
always @(posedge clock)
begin
if( dac_load )
mulacc_clrsum <= 1'b1; // set on dac_load pulse
else if( mulacc_load )
mulacc_clrsum <= 1'b0; // clear on mulacc_load pulse, so only first mulacc cycle will read clrsum high
end
localparam START = 0;
localparam LOAD_VOL = 1;
localparam LOAD_VOL2 = 2;
localparam LOAD_DAT = 3;
localparam LOAD_DAT2 = 4;
localparam START_MUL = 5;
localparam WAIT_STOP = 6;
localparam LOOP = 7;
// for simulation purposes
initial
begin
bf_wraddr <= 0;
bf_datnvol <= 0;
bf_data <= 0;
do_write <= 0;
cur_st <= START;
end
// FSM!
always @(posedge clock)
begin
if( dac_load )
cur_st <= START;
else
cur_st <= nxt_st;
end
always @*
begin
case( cur_st )
/////////////////////////////////////////////////////////////////////
START:
nxt_st <= LOAD_VOL;
/////////////////////////////////////////////////////////////////////
LOAD_VOL:
nxt_st <= LOAD_VOL2;
/////////////////////////////////////////////////////////////////////
LOAD_VOL2:
nxt_st <= LOAD_DAT;
/////////////////////////////////////////////////////////////////////
LOAD_DAT:
nxt_st <= LOAD_DAT2;
/////////////////////////////////////////////////////////////////////
LOAD_DAT2:
nxt_st <= START_MUL;
/////////////////////////////////////////////////////////////////////
START_MUL:
nxt_st <= WAIT_STOP;
/////////////////////////////////////////////////////////////////////
WAIT_STOP:
if( (!mulacc_ready) || (chanptr == 2'd3) )
nxt_st <= WAIT_STOP;
else
nxt_st <= LOOP;
/////////////////////////////////////////////////////////////////////
LOOP:
nxt_st <= LOAD_VOL;
/////////////////////////////////////////////////////////////////////
endcase
end
always @(posedge clock)
begin
case( cur_st )
/////////////////////////////////////////////////////////////////////
START:
begin
chanptr <= 2'd0;
mulacc_load <= 1'b0;
mem_read <= 1'b0;
end
/////////////////////////////////////////////////////////////////////
LOAD_VOL:
begin
mem_read <= 1'b1;
datnvol <= 1'b0;
end
/////////////////////////////////////////////////////////////////////
LOAD_VOL2:
begin
mem_read <= 1'b0;
end
/////////////////////////////////////////////////////////////////////
LOAD_DAT:
begin
vol <= mem_do[5:0];
mem_read <= 1'b1;
datnvol <= 1'b1;
end
/////////////////////////////////////////////////////////////////////
LOAD_DAT2:
begin
mem_read <= 1'b0;
mulacc_load <= 1'b1;
end
/////////////////////////////////////////////////////////////////////
START_MUL:
begin
mulacc_load <= 1'b0;
end
/////////////////////////////////////////////////////////////////////
// WAIT_STOP:
/////////////////////////////////////////////////////////////////////
LOOP:
begin
chanptr <= chanptr + 2'd1;
end
/////////////////////////////////////////////////////////////////////
endcase
end
// controlling writes to memory
// toggles
always @(negedge clock)
wrtgl1 <= in_wrtoggle;
always @(posedge clock)
{wrtgl3,wrtgl2} <= {wrtgl2,wrtgl1};
// intermediate buffers and writing
always @(posedge clock)
begin
if( wrtgl3!=wrtgl2 )
begin
bf_wraddr <= in_wraddr;
bf_data <= in_data;
bf_datnvol <= in_datnvol;
do_write <= 1'b1;
end
else if( mem_we )
begin
do_write <= 1'b0;
end
end
always @*
begin
mem_we <= do_write & (~mem_read);
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
wire signed [7:0] sgn_wide;
wire [7:0] unsgn_wide;
// The instantiation will Z extend, not sign extend
// verilator lint_off WIDTH
sub sub (.clk,
.sgn(sgn_wide), .unsgn(unsgn_wide),
.iss(3'sh7), .isu(3'h7),
.ius(3'sh7), .iuu(3'h7));
// verilator lint_on WIDTH
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("out: 'b%b 'b%b\n", sgn_wide, unsgn_wide);
`endif
if (sgn_wide[2:0] != 3'sh7) $stop;
if (unsgn_wide[2:0] != 3'h7) $stop;
if (sgn_wide !== 8'sh7) $stop;
// Simulators differ here.
if (sgn_wide !== 8'sbzzzzz111 // z-extension - NC
`ifdef VERILATOR
&& sgn_wide !== 8'sb00000111 // 0-extension - verilator as it doesn't have Z
`endif
&& sgn_wide !== 8'sb11111111) $stop; // sign extension - VCS
if (unsgn_wide !== 8'sbzzzzz111
&& unsgn_wide!== 8'sb00000111) $stop;
cyc <= cyc + 1;
if (cyc==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (
input clk,
output wire signed [2:0] sgn,
output wire [2:0] unsgn,
input signed [7:0] iss,
input signed [7:0] isu,
input [7:0] ius,
input [7:0] iuu);
assign sgn = 3'sh7;
assign unsgn = 3'h7;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("in: %x %x %x %x\n", iss, isu, ius, iuu);
if (iss != 8'hff) $stop;
if (isu != 8'h07) $stop;
if (ius != 8'hff) $stop;
if (iuu != 8'h07) $stop;
`endif
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111AI_0_V
`define SKY130_FD_SC_LP__O2111AI_0_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111ai with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o2111ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111ai_0 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o2111ai_0 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o2111ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111AI_0_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// XTEA IP Core ////
//// ////
//// This file is part of the xtea project ////
//// http://www.opencores.org/projects.cgi/web/xtea/overview ////
//// ////
//// An implementation of the XTEA encryption algorithm. ////
//// ////
//// TODO: ////
//// * Write a spec ////
//// * Wishbone compliance ////
//// ////
//// Author: David Johnson, ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2006 David Johnson ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, write to the ////
//// Free Software Foundation, Inc., 51 Franklin Street, Fifth ////
//// Floor, Boston, MA 02110-1301 USA ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
module xtea(clock, reset, mode, data_in1, data_in2, key_in, data_out1, data_out2, all_done);
parameter s0 = 8'd0, s1 = 8'd1, s2 = 8'd2, s3 = 8'd3, s4 = 8'd4, s5 = 8'd5, s6 = 8'd6, s7 = 8'd7, s8 = 8'd8, s9 = 8'd9, s10 = 8'd10,
s11 = 8'd11, s12 = 8'd12, s13 = 8'd13, s14 = 8'd14, s15 = 8'd15, s16 = 8'd16, s17 = 8'd17;
input clock, reset, mode;
input[31:0] data_in1, data_in2;
input[127:0] key_in;
output[31:0] data_out1, data_out2;
output all_done;
wire clock, reset;
wire[31:0] data_in1, data_in2;
wire[127:0] key_in;
reg all_done, while_flag, modereg;
reg[1:0] selectslice;
reg[7:0] state;
reg[7:0] x;
reg[31:0] data_out1, data_out2, sum, workunit1, workunit2, delta;
always @(posedge clock or posedge reset)
begin
if (reset)
//reset state
state = s0;
else begin
case (state)
s0: state = s1;
s1: state = s2;
s2: state = s3;
s3: state = while_flag ? s4 : s14;
s4: state = modereg ? s10 : s5;
s5: state = s6;
s6: state = s7;
s7: state = s8;
s8: state = s9;
s9: state = s2;
s10: state = s11;
s11: state = s12;
s12: state = s13;
s13: state = s14;
s14: state = s2;
s15: state = s16;
s16: state = s17;
s17: state = s17;
default: state = 4'bxxxx;
endcase
end
end
always @(posedge clock or posedge reset)
begin
if (reset) begin
//reset all our outputs and registers
data_out1 = 32'h00000000;
data_out2 = 32'h00000000;
x = 8'b00000000;
sum = 32'h00000000;
while_flag = 1'b0;
workunit1 = 32'h00000000;
workunit2 = 32'h00000000;
selectslice = 1'b0;
all_done = 1'b0;
delta = 32'h00000000;
modereg = 1'b0;
end
else begin
case (state)
s1: begin
//store input values to registers in case they're not stable
workunit1 = data_in1;
workunit2 = data_in2;
delta = 32'h9E3779B9;
sum = 32'hc6ef3720;
modereg = mode;
end
s2: if (x < 8'd32) while_flag = 1'b1; else while_flag = 1'b0;
s3: begin
//This null state was necessary to fix a timing issue.
//s2 sets while_flag and previously the control path read it in the same state
//(but in the next clock cycle), however the reg wasn't set when we tried to
//read it, so this state was inserted to add a delay. This was when running @25MHz.
//FIXME: there's got to be a better solution to this...
end
s4: begin
//This state does nothing in the data path; it's used for an if statement in the
//control path.
end
/* States 5-9 used for decipher operations */
s5: selectslice = (sum >> 32'd11 & 32'd3);
s6: case (selectslice)
2'b00: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[127:96]));
2'b01: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[95:64]));
2'b10: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[63:32]));
2'b11: workunit2 = workunit2 - (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[31:0]));
default: workunit2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
endcase
s7: sum = sum - delta;
s8: selectslice = (sum & 32'd3);
s9: begin
case (selectslice)
2'b00: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[127:96]));
2'b01: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[95:64]));
2'b10: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[63:32]));
2'b11: workunit1 = workunit1 - (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[31:0]));
default: workunit1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
endcase
x = x + 1'b1;
end
/* States 10-14 used for encipher operations */
s10: selectslice = (sum & 32'd3);
s11: case (selectslice)
2'b00: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[127:96]));
2'b01: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[95:64]));
2'b10: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[63:32]));
2'b11: workunit1 = workunit1 + (((workunit2 << 4 ^ workunit2 >> 5) + workunit2) ^ (sum + key_in[31:0]));
default: workunit1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
endcase
s12: sum = sum + delta;
s13: selectslice = (sum >> 32'd11 & 32'd3);
s14: begin
case (selectslice)
2'b00: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[127:96]));
2'b01: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[95:64]));
2'b10: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[63:32]));
2'b11: workunit2 = workunit2 + (((workunit1 << 4 ^ workunit1 >> 5) + workunit1) ^ (sum + key_in[31:0]));
default: workunit2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
endcase
x = x + 1'b1;
end
s15: begin
//This state was added to fix a timing issue.
//Same issue as above - trying to read workunit1 & workunit2 before they've settled.
end
s16: begin
//set the outputs to the working registers
data_out1 = workunit1;
data_out2 = workunit2;
end
s17: all_done = 1'b1;
default: begin
data_out1 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
data_out2 = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
end
endcase
end
end
endmodule |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: user.org:user:fmrv32im_dbussel:1.0
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fmrv32im_artya7_dbussel_upgraded_ipi_0 (
D_MEM_WAIT,
D_MEM_ENA,
D_MEM_WSTB,
D_MEM_ADDR,
D_MEM_WDATA,
D_MEM_RDATA,
D_MEM_BADMEM_EXCPT,
C_MEM_WAIT,
C_MEM_ENA,
C_MEM_WSTB,
C_MEM_ADDR,
C_MEM_WDATA,
C_MEM_RDATA,
C_MEM_BADMEM_EXCPT,
PERIPHERAL_BUS_WAIT,
PERIPHERAL_BUS_ENA,
PERIPHERAL_BUS_WSTB,
PERIPHERAL_BUS_ADDR,
PERIPHERAL_BUS_WDATA,
PERIPHERAL_BUS_RDATA,
PLIC_BUS_WE,
PLIC_BUS_ADDR,
PLIC_BUS_WDATA,
PLIC_BUS_RDATA,
TIMER_BUS_WE,
TIMER_BUS_ADDR,
TIMER_BUS_WDATA,
TIMER_BUS_RDATA
);
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WAIT" *)
output wire D_MEM_WAIT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_ENA" *)
input wire D_MEM_ENA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WSTB" *)
input wire [3 : 0] D_MEM_WSTB;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_ADDR" *)
input wire [31 : 0] D_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_WDATA" *)
input wire [31 : 0] D_MEM_WDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_RDATA" *)
output wire [31 : 0] D_MEM_RDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 D_MEM_BUS MEM_BADMEM_EXCPT" *)
output wire D_MEM_BADMEM_EXCPT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 C_MEM_BUS MEM_WAIT" *)
input wire C_MEM_WAIT;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 C_MEM_BUS MEM_ENA" *)
output wire C_MEM_ENA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 C_MEM_BUS MEM_WSTB" *)
output wire [3 : 0] C_MEM_WSTB;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 C_MEM_BUS MEM_ADDR" *)
output wire [31 : 0] C_MEM_ADDR;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 C_MEM_BUS MEM_WDATA" *)
output wire [31 : 0] C_MEM_WDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 C_MEM_BUS MEM_RDATA" *)
input wire [31 : 0] C_MEM_RDATA;
(* X_INTERFACE_INFO = "user.org:user:MEM_BUS:1.0 C_MEM_BUS MEM_BADMEM_EXCPT" *)
input wire C_MEM_BADMEM_EXCPT;
(* X_INTERFACE_INFO = "user.org:user:PERIPHERAL_BUS:1.0 PERIPHERAL BUS_WAIT" *)
input wire PERIPHERAL_BUS_WAIT;
(* X_INTERFACE_INFO = "user.org:user:PERIPHERAL_BUS:1.0 PERIPHERAL BUS_ENA" *)
output wire PERIPHERAL_BUS_ENA;
(* X_INTERFACE_INFO = "user.org:user:PERIPHERAL_BUS:1.0 PERIPHERAL BUS_WSTB" *)
output wire [3 : 0] PERIPHERAL_BUS_WSTB;
(* X_INTERFACE_INFO = "user.org:user:PERIPHERAL_BUS:1.0 PERIPHERAL BUS_ADDR" *)
output wire [31 : 0] PERIPHERAL_BUS_ADDR;
(* X_INTERFACE_INFO = "user.org:user:PERIPHERAL_BUS:1.0 PERIPHERAL BUS_WDATA" *)
output wire [31 : 0] PERIPHERAL_BUS_WDATA;
(* X_INTERFACE_INFO = "user.org:user:PERIPHERAL_BUS:1.0 PERIPHERAL BUS_RDATA" *)
input wire [31 : 0] PERIPHERAL_BUS_RDATA;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 PLIC BUS_WE" *)
output wire PLIC_BUS_WE;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 PLIC BUS_ADDR" *)
output wire [3 : 0] PLIC_BUS_ADDR;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 PLIC BUS_WDATA" *)
output wire [31 : 0] PLIC_BUS_WDATA;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 PLIC BUS_RDATA" *)
input wire [31 : 0] PLIC_BUS_RDATA;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 TIMER BUS_WE" *)
output wire TIMER_BUS_WE;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 TIMER BUS_ADDR" *)
output wire [3 : 0] TIMER_BUS_ADDR;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 TIMER BUS_WDATA" *)
output wire [31 : 0] TIMER_BUS_WDATA;
(* X_INTERFACE_INFO = "user.org:user:SYS_BUS:1.0 TIMER BUS_RDATA" *)
input wire [31 : 0] TIMER_BUS_RDATA;
fmrv32im_BADMEM_sel inst (
.D_MEM_WAIT(D_MEM_WAIT),
.D_MEM_ENA(D_MEM_ENA),
.D_MEM_WSTB(D_MEM_WSTB),
.D_MEM_ADDR(D_MEM_ADDR),
.D_MEM_WDATA(D_MEM_WDATA),
.D_MEM_RDATA(D_MEM_RDATA),
.D_MEM_BADMEM_EXCPT(D_MEM_BADMEM_EXCPT),
.C_MEM_WAIT(C_MEM_WAIT),
.C_MEM_ENA(C_MEM_ENA),
.C_MEM_WSTB(C_MEM_WSTB),
.C_MEM_ADDR(C_MEM_ADDR),
.C_MEM_WDATA(C_MEM_WDATA),
.C_MEM_RDATA(C_MEM_RDATA),
.C_MEM_BADMEM_EXCPT(C_MEM_BADMEM_EXCPT),
.PERIPHERAL_BUS_WAIT(PERIPHERAL_BUS_WAIT),
.PERIPHERAL_BUS_ENA(PERIPHERAL_BUS_ENA),
.PERIPHERAL_BUS_WSTB(PERIPHERAL_BUS_WSTB),
.PERIPHERAL_BUS_ADDR(PERIPHERAL_BUS_ADDR),
.PERIPHERAL_BUS_WDATA(PERIPHERAL_BUS_WDATA),
.PERIPHERAL_BUS_RDATA(PERIPHERAL_BUS_RDATA),
.PLIC_BUS_WE(PLIC_BUS_WE),
.PLIC_BUS_ADDR(PLIC_BUS_ADDR),
.PLIC_BUS_WDATA(PLIC_BUS_WDATA),
.PLIC_BUS_RDATA(PLIC_BUS_RDATA),
.TIMER_BUS_WE(TIMER_BUS_WE),
.TIMER_BUS_ADDR(TIMER_BUS_ADDR),
.TIMER_BUS_WDATA(TIMER_BUS_WDATA),
.TIMER_BUS_RDATA(TIMER_BUS_RDATA)
);
endmodule
|
#include <bits/stdc++.h> #pragma comment(linker, /STACK:102400000,102400000 ) using namespace std; const int INF = 0x3f3f3f3f; template <typename X> inline bool minimize(X& p, X q) { if (p <= q) return 0; p = q; return 1; } template <typename X> inline bool maximize(X& p, X q) { if (p >= q) return 0; p = q; return 1; } char str[100]; bool v[10000005]; int a[5005]; int n, kk; void doit() { memset(v, 0, sizeof(v)); for (int i = 1; i <= n; i++) { scanf( %d , &a[i]); v[a[i]] = 1; } int q, x, tmp, left, xx; scanf( %d , &q); for (int ii = 1; ii <= q; ii++) { scanf( %d , &xx); int ans = 50; for (int i = 1; i <= n; i++) for (int j = 0; j <= kk; j++) { x = xx; tmp = a[i] * j; if (x < tmp) continue; if (x == tmp) { ans = min(ans, j); continue; } x -= tmp; left = kk - j; for (int k = 1; k <= left; k++) if (x % k == 0) { if (x / k >= 10000005) continue; if (v[x / k]) { ans = min(ans, j + k); break; } } } if (ans != 50) printf( %d n , ans); else printf( %d n , -1); } } int main() { while (scanf( %d%d , &n, &kk) != EOF) doit(); } |
#include <bits/stdc++.h> using namespace std; const int MAXN = 2e5 + 3; vector<int> adj[MAXN]; int sz[MAXN], rt = -1, ok[MAXN], k; int dfs1(int u, int p) { for (int i = 0; i < adj[u].size(); i++) if (adj[u][i] != p) sz[u] += dfs1(adj[u][i], u); return sz[u]; } pair<int, int> dfs2(int u, int p) { vector<pair<int, int> > ans; pair<int, int> ret; ans.push_back(make_pair(sz[u], u)); for (int i = 0; i < adj[u].size(); i++) if (adj[u][i] != p) { if (sz[adj[u][i]] >= k) { ans.push_back(make_pair(sz[adj[u][i]], adj[u][i])); ans.push_back(dfs2(adj[u][i], u)); } } sort(ans.begin(), ans.end()); for (int i = 0; i < ans.size(); i++) { if (ans[i].first >= k && (rt == -1 || sz[rt] > ans[i].first)) rt = ans[i].second, ret = ans[i]; } return ret; } long long dfs3(int u, int p, int dep) { long long ret = 0; if (ok[u]) ret += dep; for (int i = 0; i < adj[u].size(); i++) if (adj[u][i] != p) ret += dfs3(adj[u][i], u, dep + 1); return ret; } int main() { int n, x; scanf( %d%d , &n, &k); for (int i = 0; i < 2 * k; i++) scanf( %d , &x), ok[x] = sz[x] = 1; for (int i = 0; i < n - 1; i++) { int a, b; scanf( %d%d , &a, &b); adj[a].push_back(b); adj[b].push_back(a); } dfs1(1, -1); dfs2(1, -1); printf( %I64d n , dfs3(rt, -1, 0)); } |
#include <bits/stdc++.h> using namespace std; char str[2000 + 5][2000 + 5]; int v, res, n, m, k, cnt; int main() { scanf( %d%d%d , &n, &m, &k); bool flag = 0; if (k == 1) flag = 1; for (int i = 1; i <= n; i++) scanf( %s , str[i]); for (int i = 1; i <= n; i++) { for (int j = 0; j < m; j++) { if (str[i][j] == * ) { if (v >= k) res += v - k + 1; v = 0; } else v++, cnt++; } if (v >= k) res += v - k + 1; v = 0; } if (flag == 1) { printf( %d , cnt); return 0; } for (int i = 0; i < m; i++) { for (int j = 1; j <= n; j++) { if (str[j][i] == * ) { if (v >= k) res += v - k + 1; v = 0; } else v++; } if (v >= k) res += v - k + 1; v = 0; } printf( %d , res); return 0; } |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:03:51 02/23/2015
// Design Name:
// Module Name: HCORDIC_Pipeline
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module HCORDIC_Pipeline_FSL(
input [107:0] InstructionPacket,
input reset,
input clock,
output [103:0] InstructionPacketOut,
output InstructionAck,
output OutputReady
);
wire stall,load,ALU_done,converge;
wire operation_Fetch,operation_iter,operation_FSM,operation_Execute;
wire [107:0] InstructionPacket_Processed;
wire [7:0] InsTagFetchOut,InsTagMuxOut,InsTagFSMOut,InsTag_iter,InsTagScaleOut,InsTagFinal;
wire [1:0] mode_Fetch,mode_iter,mode_FSM,mode_Execute;
wire [31:0] x_input, x_iter, xout_Mux, x_scale, xout_FSM;
wire [31:0] y_input, y_iter, yout_Mux, y_scale, yout_FSM;
wire [31:0] z_input, z_iter, zout_Mux, z_scale, zout_FSM;
wire [31:0] k_iter, kout_Mux, k_scale, kout_FSM;
wire [31:0] thetaout_FSM;
wire [31:0] deltaout_FSM;
wire [31:0] kappaout_FSM;
wire ScaleValid;
wire ProcessInputReady;
wire [31:0] x_out, y_out, z_out;
wire NatLogFlag, NatLogFlag_iter, NatLogFlagout_Mux, NatLogFlagScaleOut, NatLogFlag_Execute;
assign InstructionAck = stall;
assign InstructionPacketOut[31:0] = x_out;
assign InstructionPacketOut[63:32] = y_out;
assign InstructionPacketOut[95:64] = z_out;
assign InstructionPacketOut[103:96] = InsTagFinal;
Fetch_FSL v0 (
.InstructionPacket(InstructionPacket),
.InstructionPacket_Processed(InstructionPacket_Processed),
.ProcessInputReady(ProcessInputReady),
.reset(reset),
.clock(clock),
.stall(stall),
.x_input(x_input),
.y_input(y_input),
.z_input(z_input),
.mode(mode_Fetch),
.operation(operation_Fetch),
.InsTagFetchOut(InsTagFetchOut),
.load(load),
.NatLogFlag(NatLogFlag)
);
PreProcessxy v6 (
.InstructionPacket(InstructionPacket),
.clock(clock),
.InstructionPacketOut(InstructionPacket_Processed),
.InputReady(ProcessInputReady)
);
InputMux v1 (
.x_in(x_input),
.y_in(y_input),
.z_in(z_input),
.x_iter(x_iter),
.y_iter(y_iter),
.z_iter(z_iter),
.k_iter(k_iter),
.load(load),
.ALU_done(ALU_done),
.reset(reset),
.clock(clock),
.mode_in(mode_Fetch),
.operation_in(operation_Fetch),
.NatLogFlag(NatLogFlag),
.mode_iter(mode_iter),
.operation_iter(operation_iter),
.NatLogFlag_iter(NatLogFlag_iter),
.InsTagFetchOut(InsTagFetchOut),
.InsTag_iter(InsTag_iter),
.x_out(xout_Mux),
.y_out(yout_Mux),
.z_out(zout_Mux),
.k_out(kout_Mux),
.x_scale(x_scale),
.y_scale(y_scale),
.z_scale(z_scale),
.k_scale(k_scale),
.modeout_Mux(mode_FSM),
.operationout_Mux(operation_FSM),
.NatLogFlagout_Mux(NatLogFlagout_Mux),
.converge(converge),
.stall(stall),
.InsTagMuxOut(InsTagMuxOut),
.InsTagScaleOut(InsTagScaleOut),
.NatLogFlagScaleOut(NatLogFlagScaleOut),
.ScaleValid(ScaleValid)
);
FSM v3 (
.x_FSM(xout_Mux),
.y_FSM(yout_Mux),
.z_FSM(zout_Mux),
.k_FSM(kout_Mux),
.reset(reset),
.clock(clock),
.mode_FSM(mode_FSM),
.operation_FSM(operation_FSM),
.NatLogFlagout_Mux(NatLogFlagout_Mux),
.InsTagMuxOut(InsTagMuxOut),
.modeout_FSM(mode_Execute),
.operationout_FSM(operation_Execute),
.NatLogFlagout_FSM(NatLogFlag_Execute),
.xout_FSM(xout_FSM),
.yout_FSM(yout_FSM),
.zout_FSM(zout_FSM),
.kout_FSM(kout_FSM),
.thetaout_FSM(thetaout_FSM),
.deltaout_FSM(deltaout_FSM),
.kappaout_FSM(kappaout_FSM),
.InsTagFSMOut(InsTagFSMOut)
);
ExecutePipeline v4 (
.X_in(xout_FSM),
.Y_in(yout_FSM),
.Z_in(zout_FSM),
.K_in(kout_FSM),
.kappa_in(kappaout_FSM),
.theta_in(thetaout_FSM),
.delta_in(deltaout_FSM),
.reset(reset),
.clock(clock),
.operation(operation_Execute),
.NatLogFlag_Execute(NatLogFlag_Execute),
.mode(mode_Execute),
.InsTagFSMOut(InsTagFSMOut),
.X_next(x_iter),
.Y_next(y_iter),
.Z_next(z_iter),
.K_next(k_iter),
.mode_out(mode_iter),
.operation_out(operation_iter),
.NatLogFlag_iter(NatLogFlag_iter),
.ALU_done(ALU_done),
.InsTag_iter(InsTag_iter)
);
Descale_pipeline v5 (
.x_scale(x_scale),
.y_scale(y_scale),
.z_scale(z_scale),
.k_in(k_scale),
.InsTagScaleOut(InsTagScaleOut),
.ScaleValid(ScaleValid),
.NatLogFlagScaleOut(NatLogFlagScaleOut),
.reset(reset),
.clock(clock),
.x_out(x_out),
.y_out(y_out),
.z_out(z_out),
.done(OutputReady),
.InsTagFinal(InsTagFinal)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O22A_BEHAVIORAL_PP_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o22a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22A_BEHAVIORAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long INF = 1e9, MOD = INF + 7; const int N = 1e5 + 5; int n, a[N], nxt[N], lucky[N]; struct Node { int mn = INF, cnt = 0, idx = -1, lazy = 0; } seg[4 * N]; int doLuck(int i, int x) { if (x > 1e4) return i; if (x) lucky[i] = x, i++; i = doLuck(i, 10 * x + 4); return doLuck(i, 10 * x + 7); } void apply(int id, int x) { seg[id].mn += x; seg[id].lazy += x; } void shift(int id) { if (seg[id].lazy == 0) return; apply(2 * id, seg[id].lazy); apply(2 * id + 1, seg[id].lazy); seg[id].lazy = 0; } Node merge(const Node &x, const Node &y) { Node z; z.mn = min(x.mn, y.mn); if (z.mn == y.mn) z.cnt += y.cnt, z.idx = y.idx; if (z.mn == x.mn) z.cnt += x.cnt, z.idx = x.idx; return z; } void build(int id = 1, int s = 0, int e = n) { if (e - s < 2) { int d = lucky[0] - a[s]; seg[id].mn = d; seg[id].cnt = 1; seg[id].idx = s; return; } int md = (s + e) / 2; build(2 * id, s, md); build(2 * id + 1, md, e); seg[id] = merge(seg[2 * id], seg[2 * id + 1]); } void update(int l, int r, int x, int id = 1, int s = 0, int e = n) { if (l >= e || s >= r) return; if (l <= s && e <= r) { apply(id, x); return; } shift(id); int md = (s + e) / 2; update(l, r, x, 2 * id, s, md); update(l, r, x, 2 * id + 1, md, e); seg[id] = merge(seg[2 * id], seg[2 * id + 1]); } Node get(int l, int r, int id = 1, int s = 0, int e = n) { if (l >= e || s >= r) return Node(); if (l <= s && e <= r) return seg[id]; shift(id); int md = (s + e) / 2; return merge(get(l, r, 2 * id, s, md), get(l, r, 2 * id + 1, md, e)); } void recheck() { if (seg[1].mn >= 0) return; int x = seg[1].idx; update(x, x + 1, lucky[nxt[x] + 1] - lucky[nxt[x]]); nxt[x]++; recheck(); } int main() { ios::sync_with_stdio(0), cin.tie(0), cout.tie(0); int m = doLuck(0, 0); sort(lucky, lucky + m); lucky[m] = INF; int q; cin >> n >> q; for (int i = 0; i < n; i++) cin >> a[i]; build(); while (q--) { recheck(); string s; cin >> s; int l, r; cin >> l >> r; l--; if (s == add ) { int d; cin >> d; update(l, r, -d); } else { Node x = get(l, r); cout << (x.mn == 0) * x.cnt << n ; } } return 0; } |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
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// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
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// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Round-Robin Arbiter for R and B channel responses
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// arbiter_resp
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_10_arbiter_resp #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 4, // Number of requesting Slave ports = [2:16]
parameter integer C_NUM_S_LOG = 2, // Log2(C_NUM_S)
parameter integer C_GRANT_ENC = 0, // Enable encoded grant output
parameter integer C_GRANT_HOT = 1 // Enable 1-hot grant output
)
(
// Global Inputs
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S-1:0] S_VALID, // Request from each slave
output wire [C_NUM_S-1:0] S_READY, // Grant response to each slave
// Master Ports
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, // Granted slave index (encoded)
output wire [C_NUM_S-1:0] M_GRANT_HOT, // Granted slave index (1-hot)
output wire M_VALID, // Grant event
input wire M_READY
);
// Generates a binary coded from onehotone encoded
function [4:0] f_hot2enc
(
input [16:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 17'b01010101010101010);
f_hot2enc[1] = |(one_hot & 17'b01100110011001100);
f_hot2enc[2] = |(one_hot & 17'b01111000011110000);
f_hot2enc[3] = |(one_hot & 17'b01111111100000000);
f_hot2enc[4] = |(one_hot & 17'b10000000000000000);
end
endfunction
(* use_clock_enable = "yes" *)
reg [C_NUM_S-1:0] chosen;
wire [C_NUM_S-1:0] grant_hot;
wire master_selected;
wire active_master;
wire need_arbitration;
wire m_valid_i;
wire [C_NUM_S-1:0] s_ready_i;
wire access_done;
reg [C_NUM_S-1:0] last_rr_hot;
wire [C_NUM_S-1:0] valid_rr;
reg [C_NUM_S-1:0] next_rr_hot;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
integer i;
integer j;
integer n;
/////////////////////////////////////////////////////////////////////////////
//
// Implementation of the arbiter outputs independant of arbitration
//
/////////////////////////////////////////////////////////////////////////////
// Mask the current requests with the chosen master
assign grant_hot = chosen & S_VALID;
// See if we have a selected master
assign master_selected = |grant_hot[0+:C_NUM_S];
// See if we have current requests
assign active_master = |S_VALID;
// Access is completed
assign access_done = m_valid_i & M_READY;
// Need to handle if we drive S_ready combinatorial and without an IDLE state
// Drive S_READY on the master who has been chosen when we get a M_READY
assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];
// Drive M_VALID if we have a selected master
assign m_valid_i = master_selected;
// If we have request and not a selected master, we need to arbitrate a new chosen
assign need_arbitration = (active_master & ~master_selected) | access_done;
// need internal signals of the output signals
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Select a new chosen when we need to arbitrate
// If we don't have a new chosen, keep the old one since it's a good chance
// that it will do another request
always @(posedge ACLK)
begin
if (ARESET) begin
chosen <= {C_NUM_S{1'b0}};
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
end else if (need_arbitration) begin
chosen <= next_rr_hot;
if (|next_rr_hot) last_rr_hot <= next_rr_hot;
end
end
assign valid_rr = S_VALID;
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin
next_rr_hot = 0;
for (i=0;i<C_NUM_S;i=i+1) begin
n = (i>0) ? (i-1) : (C_NUM_S-1);
carry_rr[i*C_NUM_S] = last_rr_hot[n];
mask_rr[i*C_NUM_S] = ~valid_rr[n];
for (j=1;j<C_NUM_S;j=j+1) begin
n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);
carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);
if (j < C_NUM_S-1) begin
mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];
end
end
next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];
end
end
endmodule
|
#include <bits/stdc++.h> using namespace std; int main() { ios::sync_with_stdio(0); long long arr[41] = { 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8092, 16184, 32368, 64736, 129472, 258944, 517888, 1035776, 2071552, 4143104, 8286208, 16572416, 33144832, 66289664, 132579328, 265158656, 530317312, 1060634624, 2121269248, 4242538496, 8485076992, 16970153984, 33940307968}; int a; cin >> a; cout << arr[a]; return 0; } |
#include <bits/stdc++.h> using namespace std; const int N = (int)1e6 + 100; const long long INF = 9 * (long long)(1e18); const long double PI = 3.14159265358979323846; long long int modexp(long long int x, long long int y, long long int p) { long long int res = 1; x = x % p; if (y == 0) return 1; else if (x == 0) return 0; while (y > 0) { if (y & 1) res = (res * x) % p; y = y >> 1; x = (x * x) % p; } return res % p; } vector<long long int> is_prime(N + 1, 1); void sieve(long long int n) { for (long long int i = 1; i <= n; i++) is_prime[i] = i; for (long long int i = 2; i * i <= n; i++) { if (is_prime[i] == i) { for (long long int j = i * i; j <= n; j += i) is_prime[j] = min(i, is_prime[j]); } } } int main() { ios_base::sync_with_stdio(false); cin.tie(NULL); long long int foo; cin >> foo; while (foo--) { long long int n; cin >> n; long long int x = (n + 3) / 4; string s = string(x, 8 ); n -= x; string s2 = string(n, 9 ); cout << s2 + s << n ; } } |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__DLRTN_FUNCTIONAL_PP_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hdll__udp_dlatch_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hdll__dlrtn (
Q ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET;
wire GATE ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (GATE , GATE_N );
sky130_fd_sc_hdll__udp_dlatch$PR_pp$PG$N `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTN_FUNCTIONAL_PP_V |
#include <bits/stdc++.h> using namespace std; const long long N = 5e5 + 20; long long n, m, k; long long col[N]; vector<long long> g[N]; struct edge { long long u, v; } e[N]; long long ans; long long dead[N]; map<pair<long long, long long>, bool> vis; map<pair<long long, long long>, vector<pair<long long, long long>>> edges_between; long long par[N], f[N]; vector<pair<long long, long long>> parhistory, fhistory; long long root(long long v, bool save_history = 0) { if (par[v] < 0) return v; if (save_history) { parhistory.push_back({v, par[v]}); fhistory.push_back({v, f[v]}); } long long res = root(par[v], save_history); f[v] ^= f[par[v]]; par[v] = res; return res; } inline long long merge(long long u, long long v, bool save_history = 0) { long long ru = root(u, save_history), rv = root(v, save_history); if (ru == rv) { if (f[u] == f[v]) return -1; return 0; } if (save_history) { parhistory.push_back({ru, -1}); fhistory.push_back({ru, 0}); } if (f[u] == f[v]) f[ru] = 1; else f[ru] = 0; par[ru] = rv; return 1; } int32_t main() { ios::sync_with_stdio(false), cin.tie(0), cout.tie(0); cin >> n >> m >> k; for (long long i = 0; i < n; i++) cin >> col[i], col[i]--; for (long long i = 0; i < m; i++) { cin >> e[i].u >> e[i].v; e[i].u--, e[i].v--; g[e[i].u].push_back(e[i].v); g[e[i].v].push_back(e[i].u); } memset(par, -1, sizeof par); for (long long i = 0; i < m; i++) { long long u = e[i].u, v = e[i].v; if (col[u] == col[v]) { if (merge(u, v) == -1) dead[col[u]] = 1; } } long long cnt = 0; for (long long i = 0; i < k; i++) cnt += (!dead[i]); for (long long i = 0; i < n; i++) root(i); ans = 1ll * cnt * (cnt - 1) / 2; for (long long i = 0; i < m; i++) { long long u = e[i].u, v = e[i].v; if (col[u] == col[v]) continue; if (dead[col[u]] || dead[col[v]]) continue; long long x = col[u], y = col[v]; if (x > y) swap(x, y); edges_between[{x, y}].push_back({u, v}); vis[{x, y}] = 1; } for (auto p : vis) { long long x = p.first.first, y = p.first.second; ans--; bool ok = 1; for (pair<long long, long long> ed : edges_between[{x, y}]) { if (merge(ed.first, ed.second, 1) == -1) { ok = 0; break; } } while (parhistory.size()) { pair<long long, long long> p = parhistory.back(); par[p.first] = p.second; parhistory.pop_back(); } while (fhistory.size()) { pair<long long, long long> p = fhistory.back(); f[p.first] = p.second; fhistory.pop_back(); } ans += ok; } cout << ans << n ; } |
#include<bits/stdc++.h> using namespace std; #define FOR(i, a, b) for(int i = (a); i < (b); ++i) #define RFOR(i, b, a) for(int i = (b) - 1; i >= (a); --i) #define REP(i, N) FOR(i, 0, N) #define RREP(i, N) RFOR(i, N, 0) #define FILL(A,value) memset(A,value,sizeof(A)) #define endl n #define ALL(V) V.begin(), V.end() #define SZ(V) (int)V.size() #define watch(x) cout << (#x) << is << (x) << endl #define pb push_back #define mp make_pair #define Pi 3.14159265358979 #define A first #define B second typedef long long ll; typedef vector <int> vi; typedef vector<ll> vl; typedef pair <int, int> pi; typedef pair <ll, int> pl; typedef pair <ll, ll> pll; typedef pair <double, double> pd; //change these according to prob constraints const int INF = 0x3f3f3f3f; const int MAX = 100005; const int MAX1 = 1005; const int MAX2 = 105; const int LEN = 105; const int BASE = 1000000000; const double EPS = 1e-7; const int MOD = 1000000007; //g++ -std=c++11 your_file.cpp -o your_program ll mypow(ll a, ll b){ ll ans=1; while(b){ if(b&1) ans=(ans*a)%MOD; b/=2; a=(a*a)%MOD; } return ans; } int main(void){ ios_base::sync_with_stdio(false); cin.tie(NULL); cout.tie(NULL); ifstream in( ); ofstream out( ); clock_t begin = clock(); int q; cin >> q; while (q--){ int n; cin >> n; if (n == 1) cout << 9 << endl; else if (n == 2) cout << 98 << endl; else if (n == 3) cout << 989 << endl; if (n <= 3) continue; string s = 98 ; int ct = 9; REP(i, n - 2){ if (ct == 10) ct = 0; s += to_string(ct); ct++; } cout << s << endl; } clock_t end = clock(); double esecs = double(end - begin) / CLOCKS_PER_SEC; //cout << esecs << seconds << endl; return 0; } |
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